drivers/mtd/nand/omap2.c

   1 /*
   2  * Copyright © 2004 Texas Instruments, Jian Zhang <jzhang@ti.com>
   3  * Copyright © 2004 Micron Technology Inc.
   4  * Copyright © 2004 David Brownell
   5  *
   6  * This program is free software; you can redistribute it and/or modify
   7  * it under the terms of the GNU General Public License version 2 as
   8  * published by the Free Software Foundation.
   9  */
  10
  11 #include <linux/platform_device.h>
  12 #include <linux/dma-mapping.h>
  13 #include <linux/delay.h>
  14 #include <linux/interrupt.h>
  15 #include <linux/jiffies.h>
  16 #include <linux/sched.h>
  17 #include <linux/mtd/mtd.h>
  18 #include <linux/mtd/nand.h>
  19 #include <linux/mtd/partitions.h>
  20 #include <linux/io.h>
  21 #include <linux/slab.h>
  22
  23 #include <plat/dma.h>
  24 #include <plat/gpmc.h>
  25 #include <plat/nand.h>
  26
  27 #define DRIVER_NAME     "omap2-nand"
  28 #define OMAP_NAND_TIMEOUT_MS    5000
  29
  30 #define NAND_Ecc_P1e            (1 << 0)
  31 #define NAND_Ecc_P2e            (1 << 1)
  32 #define NAND_Ecc_P4e            (1 << 2)
  33 #define NAND_Ecc_P8e            (1 << 3)
  34 #define NAND_Ecc_P16e           (1 << 4)
  35 #define NAND_Ecc_P32e           (1 << 5)
  36 #define NAND_Ecc_P64e           (1 << 6)
  37 #define NAND_Ecc_P128e          (1 << 7)
  38 #define NAND_Ecc_P256e          (1 << 8)
  39 #define NAND_Ecc_P512e          (1 << 9)
  40 #define NAND_Ecc_P1024e         (1 << 10)
  41 #define NAND_Ecc_P2048e         (1 << 11)
  42
  43 #define NAND_Ecc_P1o            (1 << 16)
  44 #define NAND_Ecc_P2o            (1 << 17)
  45 #define NAND_Ecc_P4o            (1 << 18)
  46 #define NAND_Ecc_P8o            (1 << 19)
  47 #define NAND_Ecc_P16o           (1 << 20)
  48 #define NAND_Ecc_P32o           (1 << 21)
  49 #define NAND_Ecc_P64o           (1 << 22)
  50 #define NAND_Ecc_P128o          (1 << 23)
  51 #define NAND_Ecc_P256o          (1 << 24)
  52 #define NAND_Ecc_P512o          (1 << 25)
  53 #define NAND_Ecc_P1024o         (1 << 26)
  54 #define NAND_Ecc_P2048o         (1 << 27)
  55
  56 #define TF(value)       (value ? 1 : 0)
  57
  58 #define P2048e(a)       (TF(a & NAND_Ecc_P2048e)        << 0)
  59 #define P2048o(a)       (TF(a & NAND_Ecc_P2048o)        << 1)
  60 #define P1e(a)          (TF(a & NAND_Ecc_P1e)           << 2)
  61 #define P1o(a)          (TF(a & NAND_Ecc_P1o)           << 3)
  62 #define P2e(a)          (TF(a & NAND_Ecc_P2e)           << 4)
  63 #define P2o(a)          (TF(a & NAND_Ecc_P2o)           << 5)
  64 #define P4e(a)          (TF(a & NAND_Ecc_P4e)           << 6)
  65 #define P4o(a)          (TF(a & NAND_Ecc_P4o)           << 7)
  66
  67 #define P8e(a)          (TF(a & NAND_Ecc_P8e)           << 0)
  68 #define P8o(a)          (TF(a & NAND_Ecc_P8o)           << 1)
  69 #define P16e(a)         (TF(a & NAND_Ecc_P16e)          << 2)
  70 #define P16o(a)         (TF(a & NAND_Ecc_P16o)          << 3)
  71 #define P32e(a)         (TF(a & NAND_Ecc_P32e)          << 4)
  72 #define P32o(a)         (TF(a & NAND_Ecc_P32o)          << 5)
  73 #define P64e(a)         (TF(a & NAND_Ecc_P64e)          << 6)
  74 #define P64o(a)         (TF(a & NAND_Ecc_P64o)          << 7)
  75
  76 #define P128e(a)        (TF(a & NAND_Ecc_P128e)         << 0)
  77 #define P128o(a)        (TF(a & NAND_Ecc_P128o)         << 1)
  78 #define P256e(a)        (TF(a & NAND_Ecc_P256e)         << 2)
  79 #define P256o(a)        (TF(a & NAND_Ecc_P256o)         << 3)
  80 #define P512e(a)        (TF(a & NAND_Ecc_P512e)         << 4)
  81 #define P512o(a)        (TF(a & NAND_Ecc_P512o)         << 5)
  82 #define P1024e(a)       (TF(a & NAND_Ecc_P1024e)        << 6)
  83 #define P1024o(a)       (TF(a & NAND_Ecc_P1024o)        << 7)
  84
  85 #define P8e_s(a)        (TF(a & NAND_Ecc_P8e)           << 0)
  86 #define P8o_s(a)        (TF(a & NAND_Ecc_P8o)           << 1)
  87 #define P16e_s(a)       (TF(a & NAND_Ecc_P16e)          << 2)
  88 #define P16o_s(a)       (TF(a & NAND_Ecc_P16o)          << 3)
  89 #define P1e_s(a)        (TF(a & NAND_Ecc_P1e)           << 4)
  90 #define P1o_s(a)        (TF(a & NAND_Ecc_P1o)           << 5)
  91 #define P2e_s(a)        (TF(a & NAND_Ecc_P2e)           << 6)
  92 #define P2o_s(a)        (TF(a & NAND_Ecc_P2o)           << 7)
  93
  94 #define P4e_s(a)        (TF(a & NAND_Ecc_P4e)           << 0)
  95 #define P4o_s(a)        (TF(a & NAND_Ecc_P4o)           << 1)
  96
  97 static const char *part_probes[] = { "cmdlinepart", NULL };
  98
  99 /* oob info generated runtime depending on ecc algorithm and layout selected */
 100 static struct nand_ecclayout omap_oobinfo;
 101 /* Define some generic bad / good block scan pattern which are used
 102  * while scanning a device for factory marked good / bad blocks
 103  */
 104 static uint8_t scan_ff_pattern[] = { 0xff };
 105 static struct nand_bbt_descr bb_descrip_flashbased = {
 106         .options = NAND_BBT_SCANEMPTY | NAND_BBT_SCANALLPAGES,
 107         .offs = 0,
 108         .len = 1,
 109         .pattern = scan_ff_pattern,
 110 };
 111
 112
 113 struct omap_nand_info {
 114         struct nand_hw_control          controller;
 115         struct omap_nand_platform_data  *pdata;
 116         struct mtd_info                 mtd;
 117         struct mtd_partition            *parts;
 118         struct nand_chip                nand;
 119         struct platform_device          *pdev;
 120
 121         int                             gpmc_cs;
 122         unsigned long                   phys_base;
 123         struct completion               comp;
 124         int                             dma_ch;
 125         int                             gpmc_irq;
 126         enum {
 127                 OMAP_NAND_IO_READ = 0,  /* read */
 128                 OMAP_NAND_IO_WRITE,     /* write */
 129         } iomode;
 130         u_char                          *buf;
 131         int                                     buf_len;
 132 };
 133
 134 /**
 135  * omap_hwcontrol - hardware specific access to control-lines
 136  * @mtd: MTD device structure
 137  * @cmd: command to device
 138  * @ctrl:
 139  * NAND_NCE: bit 0 -> don't care
 140  * NAND_CLE: bit 1 -> Command Latch
 141  * NAND_ALE: bit 2 -> Address Latch
 142  *
 143  * NOTE: boards may use different bits for these!!
 144  */
 145 static void omap_hwcontrol(struct mtd_info *mtd, int cmd, unsigned int ctrl)
 146 {
 147         struct omap_nand_info *info = container_of(mtd,
 148                                         struct omap_nand_info, mtd);
 149
 150         if (cmd != NAND_CMD_NONE) {
 151                 if (ctrl & NAND_CLE)
 152                         gpmc_nand_write(info->gpmc_cs, GPMC_NAND_COMMAND, cmd);
 153
 154                 else if (ctrl & NAND_ALE)
 155                         gpmc_nand_write(info->gpmc_cs, GPMC_NAND_ADDRESS, cmd);
 156
 157                 else /* NAND_NCE */
 158                         gpmc_nand_write(info->gpmc_cs, GPMC_NAND_DATA, cmd);
 159         }
 160 }
 161
 162 /**
 163  * omap_read_buf8 - read data from NAND controller into buffer
 164  * @mtd: MTD device structure
 165  * @buf: buffer to store date
 166  * @len: number of bytes to read
 167  */
 168 static void omap_read_buf8(struct mtd_info *mtd, u_char *buf, int len)
 169 {
 170         struct nand_chip *nand = mtd->priv;
 171
 172         ioread8_rep(nand->IO_ADDR_R, buf, len);
 173 }
 174
 175 /**
 176  * omap_write_buf8 - write buffer to NAND controller
 177  * @mtd: MTD device structure
 178  * @buf: data buffer
 179  * @len: number of bytes to write
 180  */
 181 static void omap_write_buf8(struct mtd_info *mtd, const u_char *buf, int len)
 182 {
 183         struct omap_nand_info *info = container_of(mtd,
 184                                                 struct omap_nand_info, mtd);
 185         u_char *p = (u_char *)buf;
 186         u32     status = 0;
 187
 188         while (len--) {
 189                 iowrite8(*p++, info->nand.IO_ADDR_W);
 190                 /* wait until buffer is available for write */
 191                 do {
 192                         status = gpmc_read_status(GPMC_STATUS_BUFFER);
 193                 } while (!status);
 194         }
 195 }
 196
 197 /**
 198  * omap_read_buf16 - read data from NAND controller into buffer
 199  * @mtd: MTD device structure
 200  * @buf: buffer to store date
 201  * @len: number of bytes to read
 202  */
 203 static void omap_read_buf16(struct mtd_info *mtd, u_char *buf, int len)
 204 {
 205         struct nand_chip *nand = mtd->priv;
 206
 207         ioread16_rep(nand->IO_ADDR_R, buf, len / 2);
 208 }
 209
 210 /**
 211  * omap_write_buf16 - write buffer to NAND controller
 212  * @mtd: MTD device structure
 213  * @buf: data buffer
 214  * @len: number of bytes to write
 215  */
 216 static void omap_write_buf16(struct mtd_info *mtd, const u_char * buf, int len)
 217 {
 218         struct omap_nand_info *info = container_of(mtd,
 219                                                 struct omap_nand_info, mtd);
 220         u16 *p = (u16 *) buf;
 221         u32     status = 0;
 222         /* FIXME try bursts of writesw() or DMA ... */
 223         len >>= 1;
 224
 225         while (len--) {
 226                 iowrite16(*p++, info->nand.IO_ADDR_W);
 227                 /* wait until buffer is available for write */
 228                 do {
 229                         status = gpmc_read_status(GPMC_STATUS_BUFFER);
 230                 } while (!status);
 231         }
 232 }
 233
 234 /**
 235  * omap_read_buf_pref - read data from NAND controller into buffer
 236  * @mtd: MTD device structure
 237  * @buf: buffer to store date
 238  * @len: number of bytes to read
 239  */
 240 static void omap_read_buf_pref(struct mtd_info *mtd, u_char *buf, int len)
 241 {
 242         struct omap_nand_info *info = container_of(mtd,
 243                                                 struct omap_nand_info, mtd);
 244         uint32_t r_count = 0;
 245         int ret = 0;
 246         u32 *p = (u32 *)buf;
 247
 248         /* take care of subpage reads */
 249         if (len % 4) {
 250                 if (info->nand.options & NAND_BUSWIDTH_16)
 251                         omap_read_buf16(mtd, buf, len % 4);
 252                 else
 253                         omap_read_buf8(mtd, buf, len % 4);
 254                 p = (u32 *) (buf + len % 4);
 255                 len -= len % 4;
 256         }
 257
 258         /* configure and start prefetch transfer */
 259         ret = gpmc_prefetch_enable(info->gpmc_cs,
 260                         PREFETCH_FIFOTHRESHOLD_MAX, 0x0, len, 0x0);
 261         if (ret) {
 262                 /* PFPW engine is busy, use cpu copy method */
 263                 if (info->nand.options & NAND_BUSWIDTH_16)
 264                         omap_read_buf16(mtd, (u_char *)p, len);
 265                 else
 266                         omap_read_buf8(mtd, (u_char *)p, len);
 267         } else {
 268                 do {
 269                         r_count = gpmc_read_status(GPMC_PREFETCH_FIFO_CNT);
 270                         r_count = r_count >> 2;
 271                         ioread32_rep(info->nand.IO_ADDR_R, p, r_count);
 272                         p += r_count;
 273                         len -= r_count << 2;
 274                 } while (len);
 275                 /* disable and stop the PFPW engine */
 276                 gpmc_prefetch_reset(info->gpmc_cs);
 277         }
 278 }
 279
 280 /**
 281  * omap_write_buf_pref - write buffer to NAND controller
 282  * @mtd: MTD device structure
 283  * @buf: data buffer
 284  * @len: number of bytes to write
 285  */
 286 static void omap_write_buf_pref(struct mtd_info *mtd,
 287                                         const u_char *buf, int len)
 288 {
 289         struct omap_nand_info *info = container_of(mtd,
 290                                                 struct omap_nand_info, mtd);
 291         uint32_t w_count = 0;
 292         int i = 0, ret = 0;
 293         u16 *p = (u16 *)buf;
 294         unsigned long tim, limit;
 295
 296         /* take care of subpage writes */
 297         if (len % 2 != 0) {
 298                 writeb(*buf, info->nand.IO_ADDR_W);
 299                 p = (u16 *)(buf + 1);
 300                 len--;
 301         }
 302
 303         /*  configure and start prefetch transfer */
 304         ret = gpmc_prefetch_enable(info->gpmc_cs,
 305                         PREFETCH_FIFOTHRESHOLD_MAX, 0x0, len, 0x1);
 306         if (ret) {
 307                 /* PFPW engine is busy, use cpu copy method */
 308                 if (info->nand.options & NAND_BUSWIDTH_16)
 309                         omap_write_buf16(mtd, (u_char *)p, len);
 310                 else
 311                         omap_write_buf8(mtd, (u_char *)p, len);
 312         } else {
 313                 while (len) {
 314                         w_count = gpmc_read_status(GPMC_PREFETCH_FIFO_CNT);
 315                         w_count = w_count >> 1;
 316                         for (i = 0; (i < w_count) && len; i++, len -= 2)
 317                                 iowrite16(*p++, info->nand.IO_ADDR_W);
 318                 }
 319                 /* wait for data to flushed-out before reset the prefetch */
 320                 tim = 0;
 321                 limit = (loops_per_jiffy *
 322                                         msecs_to_jiffies(OMAP_NAND_TIMEOUT_MS));
 323                 while (gpmc_read_status(GPMC_PREFETCH_COUNT) && (tim++ < limit))
 324                         cpu_relax();
 325
 326                 /* disable and stop the PFPW engine */
 327                 gpmc_prefetch_reset(info->gpmc_cs);
 328         }
 329 }
 330
 331 /*
 332  * omap_nand_dma_cb: callback on the completion of dma transfer
 333  * @lch: logical channel
 334  * @ch_satuts: channel status
 335  * @data: pointer to completion data structure
 336  */
 337 static void omap_nand_dma_cb(int lch, u16 ch_status, void *data)
 338 {
 339         complete((struct completion *) data);
 340 }
 341
 342 /*
 343  * omap_nand_dma_transfer: configer and start dma transfer
 344  * @mtd: MTD device structure
 345  * @addr: virtual address in RAM of source/destination
 346  * @len: number of data bytes to be transferred
 347  * @is_write: flag for read/write operation
 348  */
 349 static inline int omap_nand_dma_transfer(struct mtd_info *mtd, void *addr,
 350                                         unsigned int len, int is_write)
 351 {
 352         struct omap_nand_info *info = container_of(mtd,
 353                                         struct omap_nand_info, mtd);
 354         enum dma_data_direction dir = is_write ? DMA_TO_DEVICE :
 355                                                         DMA_FROM_DEVICE;
 356         dma_addr_t dma_addr;
 357         int ret;
 358         unsigned long tim, limit;
 359
 360         /* The fifo depth is 64 bytes max.
 361          * But configure the FIFO-threahold to 32 to get a sync at each frame
 362          * and frame length is 32 bytes.
 363          */
 364         int buf_len = len >> 6;
 365
 366         if (addr >= high_memory) {
 367                 struct page *p1;
 368
 369                 if (((size_t)addr & PAGE_MASK) !=
 370                         ((size_t)(addr + len - 1) & PAGE_MASK))
 371                         goto out_copy;
 372                 p1 = vmalloc_to_page(addr);
 373                 if (!p1)
 374                         goto out_copy;
 375                 addr = page_address(p1) + ((size_t)addr & ~PAGE_MASK);
 376         }
 377
 378         dma_addr = dma_map_single(&info->pdev->dev, addr, len, dir);
 379         if (dma_mapping_error(&info->pdev->dev, dma_addr)) {
 380                 dev_err(&info->pdev->dev,
 381                         "Couldn't DMA map a %d byte buffer\n", len);
 382                 goto out_copy;
 383         }
 384
 385         if (is_write) {
 386             omap_set_dma_dest_params(info->dma_ch, 0, OMAP_DMA_AMODE_CONSTANT,
 387                                                 info->phys_base, 0, 0);
 388             omap_set_dma_src_params(info->dma_ch, 0, OMAP_DMA_AMODE_POST_INC,
 389                                                         dma_addr, 0, 0);
 390             omap_set_dma_transfer_params(info->dma_ch, OMAP_DMA_DATA_TYPE_S32,
 391                                         0x10, buf_len, OMAP_DMA_SYNC_FRAME,
 392                                         OMAP24XX_DMA_GPMC, OMAP_DMA_DST_SYNC);
 393         } else {
 394             omap_set_dma_src_params(info->dma_ch, 0, OMAP_DMA_AMODE_CONSTANT,
 395                                                 info->phys_base, 0, 0);
 396             omap_set_dma_dest_params(info->dma_ch, 0, OMAP_DMA_AMODE_POST_INC,
 397                                                         dma_addr, 0, 0);
 398             omap_set_dma_transfer_params(info->dma_ch, OMAP_DMA_DATA_TYPE_S32,
 399                                         0x10, buf_len, OMAP_DMA_SYNC_FRAME,
 400                                         OMAP24XX_DMA_GPMC, OMAP_DMA_SRC_SYNC);
 401         }
 402         /*  configure and start prefetch transfer */
 403         ret = gpmc_prefetch_enable(info->gpmc_cs,
 404                         PREFETCH_FIFOTHRESHOLD_MAX, 0x1, len, is_write);
 405         if (ret)
 406                 /* PFPW engine is busy, use cpu copy method */
 407                 goto out_copy;
 408
 409         init_completion(&info->comp);
 410
 411         omap_start_dma(info->dma_ch);
 412
 413         /* setup and start DMA using dma_addr */
 414         wait_for_completion(&info->comp);
 415         tim = 0;
 416         limit = (loops_per_jiffy * msecs_to_jiffies(OMAP_NAND_TIMEOUT_MS));
 417         while (gpmc_read_status(GPMC_PREFETCH_COUNT) && (tim++ < limit))
 418                 cpu_relax();
 419
 420         /* disable and stop the PFPW engine */
 421         gpmc_prefetch_reset(info->gpmc_cs);
 422
 423         dma_unmap_single(&info->pdev->dev, dma_addr, len, dir);
 424         return 0;
 425
 426 out_copy:
 427         if (info->nand.options & NAND_BUSWIDTH_16)
 428                 is_write == 0 ? omap_read_buf16(mtd, (u_char *) addr, len)
 429                         : omap_write_buf16(mtd, (u_char *) addr, len);
 430         else
 431                 is_write == 0 ? omap_read_buf8(mtd, (u_char *) addr, len)
 432                         : omap_write_buf8(mtd, (u_char *) addr, len);
 433         return 0;
 434 }
 435
 436 /**
 437  * omap_read_buf_dma_pref - read data from NAND controller into buffer
 438  * @mtd: MTD device structure
 439  * @buf: buffer to store date
 440  * @len: number of bytes to read
 441  */
 442 static void omap_read_buf_dma_pref(struct mtd_info *mtd, u_char *buf, int len)
 443 {
 444         if (len <= mtd->oobsize)
 445                 omap_read_buf_pref(mtd, buf, len);
 446         else
 447                 /* start transfer in DMA mode */
 448                 omap_nand_dma_transfer(mtd, buf, len, 0x0);
 449 }
 450
 451 /**
 452  * omap_write_buf_dma_pref - write buffer to NAND controller
 453  * @mtd: MTD device structure
 454  * @buf: data buffer
 455  * @len: number of bytes to write
 456  */
 457 static void omap_write_buf_dma_pref(struct mtd_info *mtd,
 458                                         const u_char *buf, int len)
 459 {
 460         if (len <= mtd->oobsize)
 461                 omap_write_buf_pref(mtd, buf, len);
 462         else
 463                 /* start transfer in DMA mode */
 464                 omap_nand_dma_transfer(mtd, (u_char *) buf, len, 0x1);
 465 }
 466
 467 /*
 468  * omap_nand_irq - GMPC irq handler
 469  * @this_irq: gpmc irq number
 470  * @dev: omap_nand_info structure pointer is passed here
 471  */
 472 static irqreturn_t omap_nand_irq(int this_irq, void *dev)
 473 {
 474         struct omap_nand_info *info = (struct omap_nand_info *) dev;
 475         u32 bytes;
 476         u32 irq_stat;
 477
 478         irq_stat = gpmc_read_status(GPMC_GET_IRQ_STATUS);
 479         bytes = gpmc_read_status(GPMC_PREFETCH_FIFO_CNT);
 480         bytes = bytes  & 0xFFFC; /* io in multiple of 4 bytes */
 481         if (info->iomode == OMAP_NAND_IO_WRITE) { /* checks for write io */
 482                 if (irq_stat & 0x2)
 483                         goto done;
 484
 485                 if (info->buf_len && (info->buf_len < bytes))
 486                         bytes = info->buf_len;
 487                 else if (!info->buf_len)
 488                         bytes = 0;
 489                 iowrite32_rep(info->nand.IO_ADDR_W,
 490                                                 (u32 *)info->buf, bytes >> 2);
 491                 info->buf = info->buf + bytes;
 492                 info->buf_len -= bytes;
 493
 494         } else {
 495                 ioread32_rep(info->nand.IO_ADDR_R,
 496                                                 (u32 *)info->buf, bytes >> 2);
 497                 info->buf = info->buf + bytes;
 498
 499                 if (irq_stat & 0x2)
 500                         goto done;
 501         }
 502         gpmc_cs_configure(info->gpmc_cs, GPMC_SET_IRQ_STATUS, irq_stat);
 503
 504         return IRQ_HANDLED;
 505
 506 done:
 507         complete(&info->comp);
 508         /* disable irq */
 509         gpmc_cs_configure(info->gpmc_cs, GPMC_ENABLE_IRQ, 0);
 510
 511         /* clear status */
 512         gpmc_cs_configure(info->gpmc_cs, GPMC_SET_IRQ_STATUS, irq_stat);
 513
 514         return IRQ_HANDLED;
 515 }
 516
 517 /*
 518  * omap_read_buf_irq_pref - read data from NAND controller into buffer
 519  * @mtd: MTD device structure
 520  * @buf: buffer to store date
 521  * @len: number of bytes to read
 522  */
 523 static void omap_read_buf_irq_pref(struct mtd_info *mtd, u_char *buf, int len)
 524 {
 525         struct omap_nand_info *info = container_of(mtd,
 526                                                 struct omap_nand_info, mtd);
 527         int ret = 0;
 528
 529         if (len <= mtd->oobsize) {
 530                 omap_read_buf_pref(mtd, buf, len);
 531                 return;
 532         }
 533
 534         info->iomode = OMAP_NAND_IO_READ;
 535         info->buf = buf;
 536         init_completion(&info->comp);
 537
 538         /*  configure and start prefetch transfer */
 539         ret = gpmc_prefetch_enable(info->gpmc_cs,
 540                         PREFETCH_FIFOTHRESHOLD_MAX/2, 0x0, len, 0x0);
 541         if (ret)
 542                 /* PFPW engine is busy, use cpu copy method */
 543                 goto out_copy;
 544
 545         info->buf_len = len;
 546         /* enable irq */
 547         gpmc_cs_configure(info->gpmc_cs, GPMC_ENABLE_IRQ,
 548                 (GPMC_IRQ_FIFOEVENTENABLE | GPMC_IRQ_COUNT_EVENT));
 549
 550         /* waiting for read to complete */
 551         wait_for_completion(&info->comp);
 552
 553         /* disable and stop the PFPW engine */
 554         gpmc_prefetch_reset(info->gpmc_cs);
 555         return;
 556
 557 out_copy:
 558         if (info->nand.options & NAND_BUSWIDTH_16)
 559                 omap_read_buf16(mtd, buf, len);
 560         else
 561                 omap_read_buf8(mtd, buf, len);
 562 }
 563
 564 /*
 565  * omap_write_buf_irq_pref - write buffer to NAND controller
 566  * @mtd: MTD device structure
 567  * @buf: data buffer
 568  * @len: number of bytes to write
 569  */
 570 static void omap_write_buf_irq_pref(struct mtd_info *mtd,
 571                                         const u_char *buf, int len)
 572 {
 573         struct omap_nand_info *info = container_of(mtd,
 574                                                 struct omap_nand_info, mtd);
 575         int ret = 0;
 576         unsigned long tim, limit;
 577
 578         if (len <= mtd->oobsize) {
 579                 omap_write_buf_pref(mtd, buf, len);
 580                 return;
 581         }
 582
 583         info->iomode = OMAP_NAND_IO_WRITE;
 584         info->buf = (u_char *) buf;
 585         init_completion(&info->comp);
 586
 587         /* configure and start prefetch transfer : size=24 */
 588         ret = gpmc_prefetch_enable(info->gpmc_cs,
 589                         (PREFETCH_FIFOTHRESHOLD_MAX * 3) / 8, 0x0, len, 0x1);
 590         if (ret)
 591                 /* PFPW engine is busy, use cpu copy method */
 592                 goto out_copy;
 593
 594         info->buf_len = len;
 595         /* enable irq */
 596         gpmc_cs_configure(info->gpmc_cs, GPMC_ENABLE_IRQ,
 597                         (GPMC_IRQ_FIFOEVENTENABLE | GPMC_IRQ_COUNT_EVENT));
 598
 599         /* waiting for write to complete */
 600         wait_for_completion(&info->comp);
 601         /* wait for data to flushed-out before reset the prefetch */
 602         tim = 0;
 603         limit = (loops_per_jiffy *  msecs_to_jiffies(OMAP_NAND_TIMEOUT_MS));
 604         while (gpmc_read_status(GPMC_PREFETCH_COUNT) && (tim++ < limit))
 605                 cpu_relax();
 606
 607         /* disable and stop the PFPW engine */
 608         gpmc_prefetch_reset(info->gpmc_cs);
 609         return;
 610
 611 out_copy:
 612         if (info->nand.options & NAND_BUSWIDTH_16)
 613                 omap_write_buf16(mtd, buf, len);
 614         else
 615                 omap_write_buf8(mtd, buf, len);
 616 }
 617
 618 /**
 619  * omap_verify_buf - Verify chip data against buffer
 620  * @mtd: MTD device structure
 621  * @buf: buffer containing the data to compare
 622  * @len: number of bytes to compare
 623  */
 624 static int omap_verify_buf(struct mtd_info *mtd, const u_char * buf, int len)
 625 {
 626         struct omap_nand_info *info = container_of(mtd, struct omap_nand_info,
 627                                                         mtd);
 628         u16 *p = (u16 *) buf;
 629
 630         len >>= 1;
 631         while (len--) {
 632                 if (*p++ != cpu_to_le16(readw(info->nand.IO_ADDR_R)))
 633                         return -EFAULT;
 634         }
 635
 636         return 0;
 637 }
 638
 639 /**
 640  * gen_true_ecc - This function will generate true ECC value
 641  * @ecc_buf: buffer to store ecc code
 642  *
 643  * This generated true ECC value can be used when correcting
 644  * data read from NAND flash memory core
 645  */
 646 static void gen_true_ecc(u8 *ecc_buf)
 647 {
 648         u32 tmp = ecc_buf[0] | (ecc_buf[1] << 16) |
 649                 ((ecc_buf[2] & 0xF0) << 20) | ((ecc_buf[2] & 0x0F) << 8);
 650
 651         ecc_buf[0] = ~(P64o(tmp) | P64e(tmp) | P32o(tmp) | P32e(tmp) |
 652                         P16o(tmp) | P16e(tmp) | P8o(tmp) | P8e(tmp));
 653         ecc_buf[1] = ~(P1024o(tmp) | P1024e(tmp) | P512o(tmp) | P512e(tmp) |
 654                         P256o(tmp) | P256e(tmp) | P128o(tmp) | P128e(tmp));
 655         ecc_buf[2] = ~(P4o(tmp) | P4e(tmp) | P2o(tmp) | P2e(tmp) | P1o(tmp) |
 656                         P1e(tmp) | P2048o(tmp) | P2048e(tmp));
 657 }
 658
 659 /**
 660  * omap_compare_ecc - Detect (2 bits) and correct (1 bit) error in data
 661  * @ecc_data1:  ecc code from nand spare area
 662  * @ecc_data2:  ecc code from hardware register obtained from hardware ecc
 663  * @page_data:  page data
 664  *
 665  * This function compares two ECC's and indicates if there is an error.
 666  * If the error can be corrected it will be corrected to the buffer.
 667  * If there is no error, %0 is returned. If there is an error but it
 668  * was corrected, %1 is returned. Otherwise, %-1 is returned.
 669  */
 670 static int omap_compare_ecc(u8 *ecc_data1,      /* read from NAND memory */
 671                             u8 *ecc_data2,      /* read from register */
 672                             u8 *page_data)
 673 {
 674         uint    i;
 675         u8      tmp0_bit[8], tmp1_bit[8], tmp2_bit[8];
 676         u8      comp0_bit[8], comp1_bit[8], comp2_bit[8];
 677         u8      ecc_bit[24];
 678         u8      ecc_sum = 0;
 679         u8      find_bit = 0;
 680         uint    find_byte = 0;
 681         int     isEccFF;
 682
 683         isEccFF = ((*(u32 *)ecc_data1 & 0xFFFFFF) == 0xFFFFFF);
 684
 685         gen_true_ecc(ecc_data1);
 686         gen_true_ecc(ecc_data2);
 687
 688         for (i = 0; i <= 2; i++) {
 689                 *(ecc_data1 + i) = ~(*(ecc_data1 + i));
 690                 *(ecc_data2 + i) = ~(*(ecc_data2 + i));
 691         }
 692
 693         for (i = 0; i < 8; i++) {
 694                 tmp0_bit[i]     = *ecc_data1 % 2;
 695                 *ecc_data1      = *ecc_data1 / 2;
 696         }
 697
 698         for (i = 0; i < 8; i++) {
 699                 tmp1_bit[i]      = *(ecc_data1 + 1) % 2;
 700                 *(ecc_data1 + 1) = *(ecc_data1 + 1) / 2;
 701         }
 702
 703         for (i = 0; i < 8; i++) {
 704                 tmp2_bit[i]      = *(ecc_data1 + 2) % 2;
 705                 *(ecc_data1 + 2) = *(ecc_data1 + 2) / 2;
 706         }
 707
 708         for (i = 0; i < 8; i++) {
 709                 comp0_bit[i]     = *ecc_data2 % 2;
 710                 *ecc_data2       = *ecc_data2 / 2;
 711         }
 712
 713         for (i = 0; i < 8; i++) {
 714                 comp1_bit[i]     = *(ecc_data2 + 1) % 2;
 715                 *(ecc_data2 + 1) = *(ecc_data2 + 1) / 2;
 716         }
 717
 718         for (i = 0; i < 8; i++) {
 719                 comp2_bit[i]     = *(ecc_data2 + 2) % 2;
 720                 *(ecc_data2 + 2) = *(ecc_data2 + 2) / 2;
 721         }
 722
 723         for (i = 0; i < 6; i++)
 724                 ecc_bit[i] = tmp2_bit[i + 2] ^ comp2_bit[i + 2];
 725
 726         for (i = 0; i < 8; i++)
 727                 ecc_bit[i + 6] = tmp0_bit[i] ^ comp0_bit[i];
 728
 729         for (i = 0; i < 8; i++)
 730                 ecc_bit[i + 14] = tmp1_bit[i] ^ comp1_bit[i];
 731
 732         ecc_bit[22] = tmp2_bit[0] ^ comp2_bit[0];
 733         ecc_bit[23] = tmp2_bit[1] ^ comp2_bit[1];
 734
 735         for (i = 0; i < 24; i++)
 736                 ecc_sum += ecc_bit[i];
 737
 738         switch (ecc_sum) {
 739         case 0:
 740                 /* Not reached because this function is not called if
 741                  *  ECC values are equal
 742                  */
 743                 return 0;
 744
 745         case 1:
 746                 /* Uncorrectable error */
 747                 DEBUG(MTD_DEBUG_LEVEL0, "ECC UNCORRECTED_ERROR 1\n");
 748                 return -1;
 749
 750         case 11:
 751                 /* UN-Correctable error */
 752                 DEBUG(MTD_DEBUG_LEVEL0, "ECC UNCORRECTED_ERROR B\n");
 753                 return -1;
 754
 755         case 12:
 756                 /* Correctable error */
 757                 find_byte = (ecc_bit[23] << 8) +
 758                             (ecc_bit[21] << 7) +
 759                             (ecc_bit[19] << 6) +
 760                             (ecc_bit[17] << 5) +
 761                             (ecc_bit[15] << 4) +
 762                             (ecc_bit[13] << 3) +
 763                             (ecc_bit[11] << 2) +
 764                             (ecc_bit[9]  << 1) +
 765                             ecc_bit[7];
 766
 767                 find_bit = (ecc_bit[5] << 2) + (ecc_bit[3] << 1) + ecc_bit[1];
 768
 769                 DEBUG(MTD_DEBUG_LEVEL0, "Correcting single bit ECC error at "
 770                                 "offset: %d, bit: %d\n", find_byte, find_bit);
 771
 772                 page_data[find_byte] ^= (1 << find_bit);
 773
 774                 return 1;
 775         default:
 776                 if (isEccFF) {
 777                         if (ecc_data2[0] == 0 &&
 778                             ecc_data2[1] == 0 &&
 779                             ecc_data2[2] == 0)
 780                                 return 0;
 781                 }
 782                 DEBUG(MTD_DEBUG_LEVEL0, "UNCORRECTED_ERROR default\n");
 783                 return -1;
 784         }
 785 }
 786
 787 /**
 788  * omap_correct_data - Compares the ECC read with HW generated ECC
 789  * @mtd: MTD device structure
 790  * @dat: page data
 791  * @read_ecc: ecc read from nand flash
 792  * @calc_ecc: ecc read from HW ECC registers
 793  *
 794  * Compares the ecc read from nand spare area with ECC registers values
 795  * and if ECC's mismatched, it will call 'omap_compare_ecc' for error
 796  * detection and correction. If there are no errors, %0 is returned. If
 797  * there were errors and all of the errors were corrected, the number of
 798  * corrected errors is returned. If uncorrectable errors exist, %-1 is
 799  * returned.
 800  */
 801 static int omap_correct_data(struct mtd_info *mtd, u_char *dat,
 802                                 u_char *read_ecc, u_char *calc_ecc)
 803 {
 804         struct omap_nand_info *info = container_of(mtd, struct omap_nand_info,
 805                                                         mtd);
 806         int blockCnt = 0, i = 0, ret = 0;
 807         int stat = 0;
 808
 809         /* Ex NAND_ECC_HW12_2048 */
 810         if ((info->nand.ecc.mode == NAND_ECC_HW) &&
 811                         (info->nand.ecc.size  == 2048))
 812                 blockCnt = 4;
 813         else
 814                 blockCnt = 1;
 815
 816         for (i = 0; i < blockCnt; i++) {
 817                 if (memcmp(read_ecc, calc_ecc, 3) != 0) {
 818                         ret = omap_compare_ecc(read_ecc, calc_ecc, dat);
 819                         if (ret < 0)
 820                                 return ret;
 821                         /* keep track of the number of corrected errors */
 822                         stat += ret;
 823                 }
 824                 read_ecc += 3;
 825                 calc_ecc += 3;
 826                 dat      += 512;
 827         }
 828         return stat;
 829 }
 830
 831 /**
 832  * omap_calcuate_ecc - Generate non-inverted ECC bytes.
 833  * @mtd: MTD device structure
 834  * @dat: The pointer to data on which ecc is computed
 835  * @ecc_code: The ecc_code buffer
 836  *
 837  * Using noninverted ECC can be considered ugly since writing a blank
 838  * page ie. padding will clear the ECC bytes. This is no problem as long
 839  * nobody is trying to write data on the seemingly unused page. Reading
 840  * an erased page will produce an ECC mismatch between generated and read
 841  * ECC bytes that has to be dealt with separately.
 842  */
 843 static int omap_calculate_ecc(struct mtd_info *mtd, const u_char *dat,
 844                                 u_char *ecc_code)
 845 {
 846         struct omap_nand_info *info = container_of(mtd, struct omap_nand_info,
 847                                                         mtd);
 848         return gpmc_calculate_ecc(info->gpmc_cs, dat, ecc_code);
 849 }
 850
 851 /**
 852  * omap_enable_hwecc - This function enables the hardware ecc functionality
 853  * @mtd: MTD device structure
 854  * @mode: Read/Write mode
 855  */
 856 static void omap_enable_hwecc(struct mtd_info *mtd, int mode)
 857 {
 858         struct omap_nand_info *info = container_of(mtd, struct omap_nand_info,
 859                                                         mtd);
 860         struct nand_chip *chip = mtd->priv;
 861         unsigned int dev_width = (chip->options & NAND_BUSWIDTH_16) ? 1 : 0;
 862
 863         gpmc_enable_hwecc(info->gpmc_cs, mode, dev_width, info->nand.ecc.size);
 864 }
 865
 866 /**
 867  * omap_wait - wait until the command is done
 868  * @mtd: MTD device structure
 869  * @chip: NAND Chip structure
 870  *
 871  * Wait function is called during Program and erase operations and
 872  * the way it is called from MTD layer, we should wait till the NAND
 873  * chip is ready after the programming/erase operation has completed.
 874  *
 875  * Erase can take up to 400ms and program up to 20ms according to
 876  * general NAND and SmartMedia specs
 877  */
 878 static int omap_wait(struct mtd_info *mtd, struct nand_chip *chip)
 879 {
 880         struct nand_chip *this = mtd->priv;
 881         struct omap_nand_info *info = container_of(mtd, struct omap_nand_info,
 882                                                         mtd);
 883         unsigned long timeo = jiffies;
 884         int status = NAND_STATUS_FAIL, state = this->state;
 885
 886         if (state == FL_ERASING)
 887                 timeo += (HZ * 400) / 1000;
 888         else
 889                 timeo += (HZ * 20) / 1000;
 890
 891         gpmc_nand_write(info->gpmc_cs,
 892                         GPMC_NAND_COMMAND, (NAND_CMD_STATUS & 0xFF));
 893         while (time_before(jiffies, timeo)) {
 894                 status = gpmc_nand_read(info->gpmc_cs, GPMC_NAND_DATA);
 895                 if (status & NAND_STATUS_READY)
 896                         break;
 897                 cond_resched();
 898         }
 899         return status;
 900 }
 901
 902 /**
 903  * omap_dev_ready - calls the platform specific dev_ready function
 904  * @mtd: MTD device structure
 905  */
 906 static int omap_dev_ready(struct mtd_info *mtd)
 907 {
 908         unsigned int val = 0;
 909         struct omap_nand_info *info = container_of(mtd, struct omap_nand_info,
 910                                                         mtd);
 911
 912         val = gpmc_read_status(GPMC_GET_IRQ_STATUS);
 913         if ((val & 0x100) == 0x100) {
 914                 /* Clear IRQ Interrupt */
 915                 val |= 0x100;
 916                 val &= ~(0x0);
 917                 gpmc_cs_configure(info->gpmc_cs, GPMC_SET_IRQ_STATUS, val);
 918         } else {
 919                 unsigned int cnt = 0;
 920                 while (cnt++ < 0x1FF) {
 921                         if  ((val & 0x100) == 0x100)
 922                                 return 0;
 923                         val = gpmc_read_status(GPMC_GET_IRQ_STATUS);
 924                 }
 925         }
 926
 927         return 1;
 928 }
 929
 930 static int __devinit omap_nand_probe(struct platform_device *pdev)
 931 {
 932         struct omap_nand_info           *info;
 933         struct omap_nand_platform_data  *pdata;
 934         int                             err;
 935         int                             i, offset;
 936
 937         pdata = pdev->dev.platform_data;
 938         if (pdata == NULL) {
 939                 dev_err(&pdev->dev, "platform data missing\n");
 940                 return -ENODEV;
 941         }
 942
 943         info = kzalloc(sizeof(struct omap_nand_info), GFP_KERNEL);
 944         if (!info)
 945                 return -ENOMEM;
 946
 947         platform_set_drvdata(pdev, info);
 948
 949         spin_lock_init(&info->controller.lock);
 950         init_waitqueue_head(&info->controller.wq);
 951
 952         info->pdev = pdev;
 953
 954         info->gpmc_cs           = pdata->cs;
 955         info->phys_base         = pdata->phys_base;
 956
 957         info->mtd.priv          = &info->nand;
 958         info->mtd.name          = dev_name(&pdev->dev);
 959         info->mtd.owner         = THIS_MODULE;
 960
 961         info->nand.options      = pdata->devsize;
 962         info->nand.options      |= NAND_SKIP_BBTSCAN;
 963
 964         /* NAND write protect off */
 965         gpmc_cs_configure(info->gpmc_cs, GPMC_CONFIG_WP, 0);
 966
 967         if (!request_mem_region(info->phys_base, NAND_IO_SIZE,
 968                                 pdev->dev.driver->name)) {
 969                 err = -EBUSY;
 970                 goto out_free_info;
 971         }
 972
 973         info->nand.IO_ADDR_R = ioremap(info->phys_base, NAND_IO_SIZE);
 974         if (!info->nand.IO_ADDR_R) {
 975                 err = -ENOMEM;
 976                 goto out_release_mem_region;
 977         }
 978
 979         info->nand.controller = &info->controller;
 980
 981         info->nand.IO_ADDR_W = info->nand.IO_ADDR_R;
 982         info->nand.cmd_ctrl  = omap_hwcontrol;
 983
 984         /*
 985          * If RDY/BSY line is connected to OMAP then use the omap ready
 986          * funcrtion and the generic nand_wait function which reads the status
 987          * register after monitoring the RDY/BSY line.Otherwise use a standard
 988          * chip delay which is slightly more than tR (AC Timing) of the NAND
 989          * device and read status register until you get a failure or success
 990          */
 991         if (pdata->dev_ready) {
 992                 info->nand.dev_ready = omap_dev_ready;
 993                 info->nand.chip_delay = 0;
 994         } else {
 995                 info->nand.waitfunc = omap_wait;
 996                 info->nand.chip_delay = 50;
 997         }
 998
 999         switch (pdata->xfer_type) {
1000         case NAND_OMAP_PREFETCH_POLLED:
1001                 info->nand.read_buf   = omap_read_buf_pref;
1002                 info->nand.write_buf  = omap_write_buf_pref;
1003                 break;
1004
1005         case NAND_OMAP_POLLED:
1006                 if (info->nand.options & NAND_BUSWIDTH_16) {
1007                         info->nand.read_buf   = omap_read_buf16;
1008                         info->nand.write_buf  = omap_write_buf16;
1009                 } else {
1010                         info->nand.read_buf   = omap_read_buf8;
1011                         info->nand.write_buf  = omap_write_buf8;
1012                 }
1013                 break;
1014
1015         case NAND_OMAP_PREFETCH_DMA:
1016                 err = omap_request_dma(OMAP24XX_DMA_GPMC, "NAND",
1017                                 omap_nand_dma_cb, &info->comp, &info->dma_ch);
1018                 if (err < 0) {
1019                         info->dma_ch = -1;
1020                         dev_err(&pdev->dev, "DMA request failed!\n");
1021                         goto out_release_mem_region;
1022                 } else {
1023                         omap_set_dma_dest_burst_mode(info->dma_ch,
1024                                         OMAP_DMA_DATA_BURST_16);
1025                         omap_set_dma_src_burst_mode(info->dma_ch,
1026                                         OMAP_DMA_DATA_BURST_16);
1027
1028                         info->nand.read_buf   = omap_read_buf_dma_pref;
1029                         info->nand.write_buf  = omap_write_buf_dma_pref;
1030                 }
1031                 break;
1032
1033         case NAND_OMAP_PREFETCH_IRQ:
1034                 err = request_irq(pdata->gpmc_irq,
1035                                 omap_nand_irq, IRQF_SHARED, "gpmc-nand", info);
1036                 if (err) {
1037                         dev_err(&pdev->dev, "requesting irq(%d) error:%d",
1038                                                         pdata->gpmc_irq, err);
1039                         goto out_release_mem_region;
1040                 } else {
1041                         info->gpmc_irq       = pdata->gpmc_irq;
1042                         info->nand.read_buf  = omap_read_buf_irq_pref;
1043                         info->nand.write_buf = omap_write_buf_irq_pref;
1044                 }
1045                 break;
1046
1047         default:
1048                 dev_err(&pdev->dev,
1049                         "xfer_type(%d) not supported!\n", pdata->xfer_type);
1050                 err = -EINVAL;
1051                 goto out_release_mem_region;
1052         }
1053
1054         info->nand.verify_buf = omap_verify_buf;
1055
1056         /* selsect the ecc type */
1057         if (pdata->ecc_opt == OMAP_ECC_HAMMING_CODE_DEFAULT)
1058                 info->nand.ecc.mode = NAND_ECC_SOFT;
1059         else if ((pdata->ecc_opt == OMAP_ECC_HAMMING_CODE_HW) ||
1060                 (pdata->ecc_opt == OMAP_ECC_HAMMING_CODE_HW_ROMCODE)) {
1061                 info->nand.ecc.bytes            = 3;
1062                 info->nand.ecc.size             = 512;
1063                 info->nand.ecc.calculate        = omap_calculate_ecc;
1064                 info->nand.ecc.hwctl            = omap_enable_hwecc;
1065                 info->nand.ecc.correct          = omap_correct_data;
1066                 info->nand.ecc.mode             = NAND_ECC_HW;
1067         }
1068
1069         /* DIP switches on some boards change between 8 and 16 bit
1070          * bus widths for flash.  Try the other width if the first try fails.
1071          */
1072         if (nand_scan_ident(&info->mtd, 1, NULL)) {
1073                 info->nand.options ^= NAND_BUSWIDTH_16;
1074                 if (nand_scan_ident(&info->mtd, 1, NULL)) {
1075                         err = -ENXIO;
1076                         goto out_release_mem_region;
1077                 }
1078         }
1079
1080         /* rom code layout */
1081         if (pdata->ecc_opt == OMAP_ECC_HAMMING_CODE_HW_ROMCODE) {
1082
1083                 if (info->nand.options & NAND_BUSWIDTH_16)
1084                         offset = 2;
1085                 else {
1086                         offset = 1;
1087                         info->nand.badblock_pattern = &bb_descrip_flashbased;
1088                 }
1089                 omap_oobinfo.eccbytes = 3 * (info->mtd.oobsize/16);
1090                 for (i = 0; i < omap_oobinfo.eccbytes; i++)
1091                         omap_oobinfo.eccpos[i] = i+offset;
1092
1093                 omap_oobinfo.oobfree->offset = offset + omap_oobinfo.eccbytes;
1094                 omap_oobinfo.oobfree->length = info->mtd.oobsize -
1095                                         (offset + omap_oobinfo.eccbytes);
1096
1097                 info->nand.ecc.layout = &omap_oobinfo;
1098         }
1099
1100         /* second phase scan */
1101         if (nand_scan_tail(&info->mtd)) {
1102                 err = -ENXIO;
1103                 goto out_release_mem_region;
1104         }
1105
1106         err = parse_mtd_partitions(&info->mtd, part_probes, &info->parts, 0);
1107         if (err > 0)
1108                 mtd_device_register(&info->mtd, info->parts, err);
1109         else if (pdata->parts)
1110                 mtd_device_register(&info->mtd, pdata->parts, pdata->nr_parts);
1111         else
1112                 mtd_device_register(&info->mtd, NULL, 0);
1113
1114         platform_set_drvdata(pdev, &info->mtd);
1115
1116         return 0;
1117
1118 out_release_mem_region:
1119         release_mem_region(info->phys_base, NAND_IO_SIZE);
1120 out_free_info:
1121         kfree(info);
1122
1123         return err;
1124 }
1125
1126 static int omap_nand_remove(struct platform_device *pdev)
1127 {
1128         struct mtd_info *mtd = platform_get_drvdata(pdev);
1129         struct omap_nand_info *info = container_of(mtd, struct omap_nand_info,
1130                                                         mtd);
1131
1132         platform_set_drvdata(pdev, NULL);
1133         if (info->dma_ch != -1)
1134                 omap_free_dma(info->dma_ch);
1135
1136         if (info->gpmc_irq)
1137                 free_irq(info->gpmc_irq, info);
1138
1139         /* Release NAND device, its internal structures and partitions */
1140         nand_release(&info->mtd);
1141         iounmap(info->nand.IO_ADDR_R);
1142         kfree(&info->mtd);
1143         return 0;
1144 }
1145
1146 static struct platform_driver omap_nand_driver = {
1147         .probe          = omap_nand_probe,
1148         .remove         = omap_nand_remove,
1149         .driver         = {
1150                 .name   = DRIVER_NAME,
1151                 .owner  = THIS_MODULE,
1152         },
1153 };
1154
1155 static int __init omap_nand_init(void)
1156 {
1157         pr_info("%s driver initializing\n", DRIVER_NAME);
1158
1159         return platform_driver_register(&omap_nand_driver);
1160 }
1161
1162 static void __exit omap_nand_exit(void)
1163 {
1164         platform_driver_unregister(&omap_nand_driver);
1165 }
1166
1167 module_init(omap_nand_init);
1168 module_exit(omap_nand_exit);
1169
1170 MODULE_ALIAS("platform:" DRIVER_NAME);
1171 MODULE_LICENSE("GPL");
1172 MODULE_DESCRIPTION("Glue layer for NAND flash on TI OMAP boards");