drivers/mtd/nand/omap_gpmc.c

   1 /*
   2  * (C) Copyright 2004-2008 Texas Instruments, <www.ti.com>
   3  * Rohit Choraria <rohitkc@ti.com>
   4  *
   5  * SPDX-License-Identifier:     GPL-2.0+
   6  */
   7
   8 #include <common.h>
   9 #include <asm/io.h>
  10 #include <asm/errno.h>
  11 #include <asm/arch/mem.h>
  12 #include <linux/mtd/omap_gpmc.h>
  13 #include <linux/mtd/nand_ecc.h>
  14 #include <linux/bch.h>
  15 #include <linux/compiler.h>
  16 #include <nand.h>
  17 #include <linux/mtd/omap_elm.h>
  18
  19 #define BADBLOCK_MARKER_LENGTH  2
  20 #define SECTOR_BYTES            512
  21 #define ECCCLEAR                (0x1 << 8)
  22 #define ECCRESULTREG1           (0x1 << 0)
  23 /* 4 bit padding to make byte aligned, 56 = 52 + 4 */
  24 #define BCH4_BIT_PAD            4
  25
  26 #ifdef CONFIG_BCH
  27 static u8  bch8_polynomial[] = {0xef, 0x51, 0x2e, 0x09, 0xed, 0x93, 0x9a, 0xc2,
  28                                 0x97, 0x79, 0xe5, 0x24, 0xb5};
  29 #endif
  30 static uint8_t cs_next;
  31 static __maybe_unused struct nand_ecclayout omap_ecclayout;
  32
  33 #if defined(CONFIG_NAND_OMAP_GPMC_WSCFG)
  34 static const int8_t wscfg[CONFIG_SYS_MAX_NAND_DEVICE] =
  35         { CONFIG_NAND_OMAP_GPMC_WSCFG };
  36 #else
  37 /* wscfg is preset to zero since its a static variable */
  38 static const int8_t wscfg[CONFIG_SYS_MAX_NAND_DEVICE];
  39 #endif
  40
  41 /*
  42  * Driver configurations
  43  */
  44 struct omap_nand_info {
  45         struct bch_control *control;
  46         enum omap_ecc ecc_scheme;
  47         uint8_t cs;
  48         uint8_t ws;             /* wait status pin (0,1) */
  49 };
  50
  51 /* We are wasting a bit of memory but al least we are safe */
  52 static struct omap_nand_info omap_nand_info[GPMC_MAX_CS];
  53
  54 static struct gpmc __iomem *gpmc_cfg = (void __iomem *)GPMC_BASE;
  55
  56 #ifdef CONFIG_SYS_NAND_USE_FLASH_BBT
  57 static uint8_t bbt_pattern[] = {'B', 'b', 't', '0' };
  58 static uint8_t mirror_pattern[] = {'1', 't', 'b', 'B' };
  59
  60 static struct nand_bbt_descr bbt_main_descr = {
  61         .options = NAND_BBT_LASTBLOCK | NAND_BBT_CREATE | NAND_BBT_WRITE |
  62                 NAND_BBT_2BIT | NAND_BBT_VERSION | NAND_BBT_PERCHIP,
  63         .offs = 0, /* may be overwritten depending on ECC layout */
  64         .len = 4,
  65         .veroffs = 4, /* may be overwritten depending on ECC layout */
  66         .maxblocks = 4,
  67         .pattern = bbt_pattern,
  68 };
  69
  70 static struct nand_bbt_descr bbt_mirror_descr = {
  71         .options = NAND_BBT_LASTBLOCK | NAND_BBT_CREATE | NAND_BBT_WRITE |
  72                 NAND_BBT_2BIT | NAND_BBT_VERSION | NAND_BBT_PERCHIP,
  73         .offs = 0, /* may be overwritten depending on ECC layout */
  74         .len = 4,
  75         .veroffs = 4, /* may be overwritten depending on ECC layout */
  76         .maxblocks = 4,
  77         .pattern = mirror_pattern,
  78 };
  79 #endif
  80
  81 #define PREFETCH_FIFOTHRESHOLD_MAX              0x40
  82 #define PREFETCH_FIFOTHRESHOLD(val)             ((val) << 8)
  83
  84 #define PREFETCH_ENABLEOPTIMIZEDACCESS          (0x1 << 27)
  85
  86 #define GPMC_PREFETCH_STATUS_FIFO_CNT(val)      (((val) >> 24) & 0x7F)
  87 #define GPMC_PREFETCH_STATUS_COUNT(val)         ((val) & 0x00003fff)
  88
  89 #define CS_NUM_SHIFT                            24
  90 #define ENABLE_PREFETCH                         (0x1 << 7)
  91 #define DMA_MPU_MODE                            2
  92
  93 #define OMAP_NAND_TIMEOUT_MS                    5000
  94
  95 #define PRINT_REG(x) debug("+++ %.15s (0x%08x)=0x%08x\n", #x, &gpmc_cfg->x, readl(&gpmc_cfg->x))
  96
  97 #ifdef CONFIG_SYS_GPMC_PREFETCH_ENABLE
  98 /**
  99  * gpmc_prefetch_enable - configures and starts prefetch transfer
 100  * @cs: cs (chip select) number
 101  * @fifo_th: fifo threshold to be used for read/ write
 102  * @count: number of bytes to be transferred
 103  * @is_write: prefetch read(0) or write post(1) mode
 104  */
 105 static inline void gpmc_prefetch_enable(int cs, int fifo_th,
 106                                         unsigned int count, int is_write)
 107 {
 108         writel(count, &gpmc_cfg->pref_config2);
 109
 110         /* Set the prefetch read / post write and enable the engine.
 111          * Set which cs is has requested for.
 112          */
 113         uint32_t val = (cs << CS_NUM_SHIFT) |
 114                 PREFETCH_ENABLEOPTIMIZEDACCESS |
 115                 PREFETCH_FIFOTHRESHOLD(fifo_th) |
 116                 ENABLE_PREFETCH |
 117                 !!is_write;
 118         writel(val, &gpmc_cfg->pref_config1);
 119
 120         /*  Start the prefetch engine */
 121         writel(0x1, &gpmc_cfg->pref_control);
 122 }
 123
 124 /**
 125  * gpmc_prefetch_reset - disables and stops the prefetch engine
 126  */
 127 static inline void gpmc_prefetch_reset(void)
 128 {
 129         /* Stop the PFPW engine */
 130         writel(0x0, &gpmc_cfg->pref_control);
 131
 132         /* Reset/disable the PFPW engine */
 133         writel(0x0, &gpmc_cfg->pref_config1);
 134 }
 135
 136 //#define FIFO_IOADDR           (nand->IO_ADDR_R)
 137 #define FIFO_IOADDR             PISMO1_NAND_BASE
 138
 139 /**
 140  * read_buf_pref - read data from NAND controller into buffer
 141  * @mtd: MTD device structure
 142  * @buf: buffer to store date
 143  * @len: number of bytes to read
 144  */
 145 static void read_buf_pref(struct mtd_info *mtd, u_char *buf, int len)
 146 {
 147         gpmc_prefetch_enable(cs, PREFETCH_FIFOTHRESHOLD_MAX, len, 0);
 148         do {
 149                 // Get number of bytes waiting in the FIFO
 150                 uint32_t read_bytes = GPMC_PREFETCH_STATUS_FIFO_CNT(readl(&gpmc_cfg->pref_status));
 151
 152                 if (read_bytes == 0)
 153                         continue;
 154                 // Alignment of Destination Buffer
 155                 while (read_bytes && ((unsigned int)buf & 3)) {
 156                         *buf++ = readb(FIFO_IOADDR);
 157                         read_bytes--;
 158                         len--;
 159                 }
 160                 // Use maximum word size (32bit) inside this loop, because speed is limited by
 161                 // GPMC bus arbitration with a maximum transfer rate of 3.000.000/sec.
 162                 len -= read_bytes & ~3;
 163                 while (read_bytes >= 4) {
 164                         *((uint32_t*)buf) = readl(FIFO_IOADDR);
 165                         buf += 4;
 166                         read_bytes -= 4;
 167                 }
 168                 // Transfer the last (non-aligned) bytes only at the last iteration,
 169                 // to maintain full speed up to the end of the transfer.
 170                 if (read_bytes == len) {
 171                         while (read_bytes) {
 172                                 *buf++ = readb(FIFO_IOADDR);
 173                                 read_bytes--;
 174                         }
 175                         len = 0;
 176                 }
 177         } while (len > 0);
 178         gpmc_prefetch_reset();
 179 }
 180
 181 /*
 182  * write_buf_pref - write buffer to NAND controller
 183  * @mtd: MTD device structure
 184  * @buf: data buffer
 185  * @len: number of bytes to write
 186  */
 187 static void write_buf_pref(struct mtd_info *mtd, const u_char *buf, int len)
 188 {
 189         /*  configure and start prefetch transfer */
 190         gpmc_prefetch_enable(cs, PREFETCH_FIFOTHRESHOLD_MAX, len, 1);
 191
 192         while (len) {
 193                 // Get number of free bytes in the FIFO
 194                 uint32_t write_bytes = GPMC_PREFETCH_STATUS_FIFO_CNT(readl(&gpmc_cfg->pref_status));
 195
 196                 // don't write more bytes than requested
 197                 if (write_bytes > len)
 198                         write_bytes = len;
 199
 200                 // Alignment of Source Buffer
 201                 while (write_bytes && ((unsigned int)buf & 3)) {
 202                         writeb(*buf++, FIFO_IOADDR);
 203                         write_bytes--;
 204                         len--;
 205                 }
 206
 207                 // Use maximum word size (32bit) inside this loop, because speed is limited by
 208                 // GPMC bus arbitration with a maximum transfer rate of 3.000.000/sec.
 209                 len -= write_bytes & ~3;
 210                 while (write_bytes >= 4) {
 211                         writel(*((uint32_t*)buf), FIFO_IOADDR);
 212                         buf += 4;
 213                         write_bytes -= 4;
 214                 }
 215
 216                 // Transfer the last (non-aligned) bytes only at the last iteration,
 217                 // to maintain full speed up to the end of the transfer.
 218                 if (write_bytes == len) {
 219                         while (write_bytes) {
 220                                 writeb(*buf++, FIFO_IOADDR);
 221                                 write_bytes--;
 222                         }
 223                         len = 0;
 224                 }
 225         }
 226
 227         /* wait for data to be flushed out before resetting the prefetch */
 228         while ((len = GPMC_PREFETCH_STATUS_COUNT(readl(&gpmc_cfg->pref_status)))) {
 229                 debug("%u bytes still in FIFO\n", PREFETCH_FIFOTHRESHOLD_MAX - len);
 230                 ndelay(1);
 231         }
 232
 233         /* disable and stop the PFPW engine */
 234         gpmc_prefetch_reset();
 235 }
 236 #endif /* CONFIG_SYS_GPMC_PREFETCH_ENABLE */
 237
 238 /*
 239  * omap_nand_hwcontrol - Set the address pointers corretly for the
 240  *                      following address/data/command operation
 241  */
 242 static void omap_nand_hwcontrol(struct mtd_info *mtd, int32_t cmd,
 243                                 uint32_t ctrl)
 244 {
 245         register struct nand_chip *this = mtd->priv;
 246         struct omap_nand_info *info = this->priv;
 247         int cs = info->cs;
 248
 249         /*
 250          * Point the IO_ADDR to DATA and ADDRESS registers instead
 251          * of chip address
 252          */
 253         switch (ctrl) {
 254         case NAND_CTRL_CHANGE | NAND_CTRL_CLE:
 255                 this->IO_ADDR_W = (void __iomem *)&gpmc_cfg->cs[cs].nand_cmd;
 256                 break;
 257         case NAND_CTRL_CHANGE | NAND_CTRL_ALE:
 258                 this->IO_ADDR_W = (void __iomem *)&gpmc_cfg->cs[cs].nand_adr;
 259                 break;
 260         case NAND_CTRL_CHANGE | NAND_NCE:
 261                 this->IO_ADDR_W = (void __iomem *)&gpmc_cfg->cs[cs].nand_dat;
 262                 break;
 263         }
 264
 265         if (cmd != NAND_CMD_NONE)
 266                 writeb(cmd, this->IO_ADDR_W);
 267 }
 268
 269 /* Check wait pin as dev ready indicator */
 270 static int omap_dev_ready(struct mtd_info *mtd)
 271 {
 272         return !!(readl(&gpmc_cfg->status) & (1 << (8 + info->ws)));
 273 }
 274
 275 /*
 276  * gen_true_ecc - This function will generate true ECC value, which
 277  * can be used when correcting data read from NAND flash memory core
 278  *
 279  * @ecc_buf:    buffer to store ecc code
 280  *
 281  * @return:     re-formatted ECC value
 282  */
 283 static uint32_t gen_true_ecc(uint8_t *ecc_buf)
 284 {
 285         return ecc_buf[0] | (ecc_buf[1] << 16) | ((ecc_buf[2] & 0xF0) << 20) |
 286                 ((ecc_buf[2] & 0x0F) << 8);
 287 }
 288
 289 /*
 290  * omap_correct_data - Compares the ecc read from nand spare area with ECC
 291  * registers values and corrects one bit error if it has occured
 292  * Further details can be had from OMAP TRM and the following selected links:
 293  * http://en.wikipedia.org/wiki/Hamming_code
 294  * http://www.cs.utexas.edu/users/plaxton/c/337/05f/slides/ErrorCorrection-4.pdf
 295  *
 296  * @mtd:                 MTD device structure
 297  * @dat:                 page data
 298  * @read_ecc:            ecc read from nand flash
 299  * @calc_ecc:            ecc read from ECC registers
 300  *
 301  * @return 0 if data is OK or corrected, else returns -1
 302  */
 303 static int __maybe_unused omap_correct_data(struct mtd_info *mtd, uint8_t *dat,
 304                                 uint8_t *read_ecc, uint8_t *calc_ecc)
 305 {
 306         uint32_t orig_ecc, new_ecc, res, hm;
 307         uint16_t parity_bits, byte;
 308         uint8_t bit;
 309
 310         /* Regenerate the orginal ECC */
 311         orig_ecc = gen_true_ecc(read_ecc);
 312         new_ecc = gen_true_ecc(calc_ecc);
 313         /* Get the XOR of real ecc */
 314         res = orig_ecc ^ new_ecc;
 315         if (res) {
 316                 /* Get the hamming width */
 317                 hm = hweight32(res);
 318                 /* Single bit errors can be corrected! */
 319                 if (hm == 12) {
 320                         /* Correctable data! */
 321                         parity_bits = res >> 16;
 322                         bit = (parity_bits & 0x7);
 323                         byte = (parity_bits >> 3) & 0x1FF;
 324                         /* Flip the bit to correct */
 325                         dat[byte] ^= (0x1 << bit);
 326                 } else if (hm == 1) {
 327                         printf("Error: Ecc is wrong\n");
 328                         /* ECC itself is corrupted */
 329                         return 2;
 330                 } else {
 331                         /*
 332                          * hm distance != parity pairs OR one, could mean 2 bit
 333                          * error OR potentially be on a blank page..
 334                          * orig_ecc: contains spare area data from nand flash.
 335                          * new_ecc: generated ecc while reading data area.
 336                          * Note: if the ecc = 0, all data bits from which it was
 337                          * generated are 0xFF.
 338                          * The 3 byte(24 bits) ecc is generated per 512byte
 339                          * chunk of a page. If orig_ecc(from spare area)
 340                          * is 0xFF && new_ecc(computed now from data area)=0x0,
 341                          * this means that data area is 0xFF and spare area is
 342                          * 0xFF. A sure sign of a erased page!
 343                          */
 344                         if ((orig_ecc == 0x0FFF0FFF) && (new_ecc == 0x00000000))
 345                                 return 0;
 346                         printf("Error: Bad compare! failed\n");
 347                         /* detected 2 bit error */
 348                         return -1;
 349                 }
 350         }
 351         return 0;
 352 }
 353
 354 /*
 355  * omap_enable_hwecc - configures GPMC as per ECC scheme before read/write
 356  * @mtd:        MTD device structure
 357  * @mode:       Read/Write mode
 358  */
 359 __maybe_unused
 360 static void omap_enable_hwecc(struct mtd_info *mtd, int32_t mode)
 361 {
 362         struct nand_chip        *nand   = mtd->priv;
 363         struct omap_nand_info   *info   = nand->priv;
 364         unsigned int dev_width = (nand->options & NAND_BUSWIDTH_16) ? 1 : 0;
 365         unsigned int ecc_algo = 0;
 366         unsigned int bch_type = 0;
 367         unsigned int eccsize1 = 0x00, eccsize0 = 0x00, bch_wrapmode = 0x00;
 368         u32 ecc_size_config_val = 0;
 369         u32 ecc_config_val = 0;
 370         int cs = info->cs;
 371
 372         /* configure GPMC for specific ecc-scheme */
 373         switch (info->ecc_scheme) {
 374         case OMAP_ECC_HAM1_CODE_SW:
 375                 return;
 376         case OMAP_ECC_HAM1_CODE_HW:
 377                 ecc_algo = 0x0;
 378                 bch_type = 0x0;
 379                 bch_wrapmode = 0x00;
 380                 eccsize0 = 0xFF;
 381                 eccsize1 = 0xFF;
 382                 break;
 383         case OMAP_ECC_BCH8_CODE_HW_DETECTION_SW:
 384         case OMAP_ECC_BCH8_CODE_HW:
 385                 ecc_algo = 0x1;
 386                 bch_type = 0x1;
 387                 if (mode == NAND_ECC_WRITE) {
 388                         bch_wrapmode = 0x01;
 389                         eccsize0 = 0;  /* extra bits in nibbles per sector */
 390                         eccsize1 = 28; /* OOB bits in nibbles per sector */
 391                 } else {
 392                         bch_wrapmode = 0x01;
 393                         eccsize0 = 26; /* ECC bits in nibbles per sector */
 394                         eccsize1 = 2;  /* non-ECC bits in nibbles per sector */
 395                 }
 396                 break;
 397         case OMAP_ECC_BCH16_CODE_HW:
 398                 ecc_algo = 0x1;
 399                 bch_type = 0x2;
 400                 if (mode == NAND_ECC_WRITE) {
 401                         bch_wrapmode = 0x01;
 402                         eccsize0 = 0;  /* extra bits in nibbles per sector */
 403                         eccsize1 = 52; /* OOB bits in nibbles per sector */
 404                 } else {
 405                         bch_wrapmode = 0x01;
 406                         eccsize0 = 52; /* ECC bits in nibbles per sector */
 407                         eccsize1 = 0;  /* non-ECC bits in nibbles per sector */
 408                 }
 409                 break;
 410         default:
 411                 return;
 412         }
 413         /* Clear ecc and enable bits */
 414         writel(ECCCLEAR | ECCRESULTREG1, &gpmc_cfg->ecc_control);
 415         /* Configure ecc size for BCH */
 416         ecc_size_config_val = (eccsize1 << 22) | (eccsize0 << 12);
 417         writel(ecc_size_config_val, &gpmc_cfg->ecc_size_config);
 418
 419         /* Configure device details for BCH engine */
 420         ecc_config_val = ((ecc_algo << 16)      | /* HAM1 | BCHx */
 421                         (bch_type << 12)        | /* BCH4/BCH8/BCH16 */
 422                         (bch_wrapmode << 8)     | /* wrap mode */
 423                         (dev_width << 7)        | /* bus width */
 424                         (0x0 << 4)              | /* number of sectors */
 425                         (cs <<  1)              | /* ECC CS */
 426                         (0x1));                   /* enable ECC */
 427         writel(ecc_config_val, &gpmc_cfg->ecc_config);
 428 }
 429
 430 /*
 431  *  omap_calculate_ecc - Read ECC result
 432  *  @mtd:       MTD structure
 433  *  @dat:       unused
 434  *  @ecc_code:  ecc_code buffer
 435  *  Using noninverted ECC can be considered ugly since writing a blank
 436  *  page ie. padding will clear the ECC bytes. This is no problem as
 437  *  long nobody is trying to write data on the seemingly unused page.
 438  *  Reading an erased page will produce an ECC mismatch between
 439  *  generated and read ECC bytes that has to be dealt with separately.
 440  *  E.g. if page is 0xFF (fresh erased), and if HW ECC engine within GPMC
 441  *  is used, the result of read will be 0x0 while the ECC offsets of the
 442  *  spare area will be 0xFF which will result in an ECC mismatch.
 443  */
 444 static int omap_calculate_ecc(struct mtd_info *mtd, const uint8_t *dat,
 445                                 uint8_t *ecc_code)
 446 {
 447         struct nand_chip *chip = mtd->priv;
 448         struct omap_nand_info *info = chip->priv;
 449         uint32_t *ptr, val = 0;
 450         int8_t i = 0, j;
 451
 452         switch (info->ecc_scheme) {
 453         case OMAP_ECC_HAM1_CODE_HW:
 454                 val = readl(&gpmc_cfg->ecc1_result);
 455                 ecc_code[0] = val & 0xFF;
 456                 ecc_code[1] = (val >> 16) & 0xFF;
 457                 ecc_code[2] = ((val >> 8) & 0x0F) | ((val >> 20) & 0xF0);
 458                 break;
 459 #ifdef CONFIG_BCH
 460         case OMAP_ECC_BCH8_CODE_HW_DETECTION_SW:
 461 #endif
 462         case OMAP_ECC_BCH8_CODE_HW:
 463                 ptr = &gpmc_cfg->bch_result_0_3[0].bch_result_x[3];
 464                 val = readl(ptr);
 465                 ecc_code[i++] = (val >>  0) & 0xFF;
 466                 ptr--;
 467                 for (j = 0; j < 3; j++) {
 468                         val = readl(ptr);
 469                         ecc_code[i++] = (val >> 24) & 0xFF;
 470                         ecc_code[i++] = (val >> 16) & 0xFF;
 471                         ecc_code[i++] = (val >>  8) & 0xFF;
 472                         ecc_code[i++] = (val >>  0) & 0xFF;
 473                         ptr--;
 474                 }
 475                 break;
 476         case OMAP_ECC_BCH16_CODE_HW:
 477                 val = readl(&gpmc_cfg->bch_result_4_6[0].bch_result_x[2]);
 478                 ecc_code[i++] = (val >>  8) & 0xFF;
 479                 ecc_code[i++] = (val >>  0) & 0xFF;
 480                 val = readl(&gpmc_cfg->bch_result_4_6[0].bch_result_x[1]);
 481                 ecc_code[i++] = (val >> 24) & 0xFF;
 482                 ecc_code[i++] = (val >> 16) & 0xFF;
 483                 ecc_code[i++] = (val >>  8) & 0xFF;
 484                 ecc_code[i++] = (val >>  0) & 0xFF;
 485                 val = readl(&gpmc_cfg->bch_result_4_6[0].bch_result_x[0]);
 486                 ecc_code[i++] = (val >> 24) & 0xFF;
 487                 ecc_code[i++] = (val >> 16) & 0xFF;
 488                 ecc_code[i++] = (val >>  8) & 0xFF;
 489                 ecc_code[i++] = (val >>  0) & 0xFF;
 490                 for (j = 3; j >= 0; j--) {
 491                         val = readl(&gpmc_cfg->bch_result_0_3[0].bch_result_x[j]
 492                                                                         );
 493                         ecc_code[i++] = (val >> 24) & 0xFF;
 494                         ecc_code[i++] = (val >> 16) & 0xFF;
 495                         ecc_code[i++] = (val >>  8) & 0xFF;
 496                         ecc_code[i++] = (val >>  0) & 0xFF;
 497                 }
 498                 break;
 499         default:
 500                 return -EINVAL;
 501         }
 502         /* ECC scheme specific syndrome customizations */
 503         switch (info->ecc_scheme) {
 504         case OMAP_ECC_HAM1_CODE_HW:
 505                 break;
 506 #ifdef CONFIG_BCH
 507         case OMAP_ECC_BCH8_CODE_HW_DETECTION_SW:
 508
 509                 for (i = 0; i < chip->ecc.bytes; i++)
 510                         *(ecc_code + i) = *(ecc_code + i) ^
 511                                                 bch8_polynomial[i];
 512                 break;
 513 #endif
 514         case OMAP_ECC_BCH8_CODE_HW:
 515                 ecc_code[chip->ecc.bytes - 1] = 0x00;
 516                 break;
 517         case OMAP_ECC_BCH16_CODE_HW:
 518                 break;
 519         default:
 520                 return -EINVAL;
 521         }
 522         return 0;
 523 }
 524
 525 #ifdef CONFIG_NAND_OMAP_ELM
 526 /*
 527  * omap_reverse_list - re-orders list elements in reverse order [internal]
 528  * @list:       pointer to start of list
 529  * @length:     length of list
 530 */
 531 static void omap_reverse_list(u8 *list, unsigned int length)
 532 {
 533         unsigned int i, j;
 534         unsigned int half_length = length / 2;
 535         u8 tmp;
 536         for (i = 0, j = length - 1; i < half_length; i++, j--) {
 537                 tmp = list[i];
 538                 list[i] = list[j];
 539                 list[j] = tmp;
 540         }
 541 }
 542
 543 /*
 544  * omap_correct_data_bch - Compares the ecc read from nand spare area
 545  * with ECC registers values and corrects one bit error if it has occured
 546  *
 547  * @mtd:        MTD device structure
 548  * @dat:        page data
 549  * @read_ecc:   ecc read from nand flash (ignored)
 550  * @calc_ecc:   ecc read from ECC registers
 551  *
 552  * @return 0 if data is OK or corrected, else returns -1
 553  */
 554 static int omap_correct_data_bch(struct mtd_info *mtd, uint8_t *dat,
 555                                 uint8_t *read_ecc, uint8_t *calc_ecc)
 556 {
 557         struct nand_chip *chip = mtd->priv;
 558         struct omap_nand_info *info = chip->priv;
 559         struct nand_ecc_ctrl *ecc = &chip->ecc;
 560         uint32_t error_count = 0, error_max;
 561         uint32_t error_loc[ELM_MAX_ERROR_COUNT];
 562         enum bch_level bch_type;
 563         uint32_t i, ecc_flag = 0;
 564         uint8_t count;
 565         uint32_t byte_pos, bit_pos;
 566         int err = 0;
 567
 568         /* check calculated ecc */
 569         for (i = 0; i < ecc->bytes && !ecc_flag; i++) {
 570                 if (calc_ecc[i] != 0x00)
 571                         ecc_flag = 1;
 572         }
 573         if (!ecc_flag)
 574                 return 0;
 575
 576         /* check for whether its a erased-page */
 577         ecc_flag = 0;
 578         for (i = 0; i < ecc->bytes && !ecc_flag; i++) {
 579                 if (read_ecc[i] != 0xff)
 580                         ecc_flag = 1;
 581         }
 582         if (!ecc_flag)
 583                 return 0;
 584
 585         /*
 586          * while reading ECC result we read it in big endian.
 587          * Hence while loading to ELM we have rotate to get the right endian.
 588          */
 589         switch (info->ecc_scheme) {
 590         case OMAP_ECC_BCH8_CODE_HW:
 591                 bch_type = BCH_8_BIT;
 592                 omap_reverse_list(calc_ecc, ecc->bytes - 1);
 593                 break;
 594         case OMAP_ECC_BCH16_CODE_HW:
 595                 bch_type = BCH_16_BIT;
 596                 omap_reverse_list(calc_ecc, ecc->bytes);
 597                 break;
 598         default:
 599                 return -EINVAL;
 600         }
 601         /* use elm module to check for errors */
 602         elm_config(bch_type);
 603         err = elm_check_error(calc_ecc, bch_type, &error_count, error_loc);
 604         if (err)
 605                 return err;
 606
 607         /* correct bch error */
 608         for (count = 0; count < error_count; count++) {
 609                 switch (info->ecc_scheme) {
 610                 case OMAP_ECC_BCH8_CODE_HW:
 611                         /* 14th byte in ECC is reserved to match ROM layout */
 612                         error_max = SECTOR_BYTES + (ecc->bytes - 1);
 613                         break;
 614                 case OMAP_ECC_BCH16_CODE_HW:
 615                         error_max = SECTOR_BYTES + ecc->bytes;
 616                         break;
 617                 default:
 618                         return -EINVAL;
 619                 }
 620                 byte_pos = error_max - (error_loc[count] / 8) - 1;
 621                 bit_pos  = error_loc[count] % 8;
 622                 if (byte_pos < SECTOR_BYTES) {
 623                         dat[byte_pos] ^= 1 << bit_pos;
 624                         printf("nand: bit-flip corrected @data=%d\n", byte_pos);
 625                 } else if (byte_pos < error_max) {
 626                         read_ecc[byte_pos - SECTOR_BYTES] ^= 1 << bit_pos;
 627                         printf("nand: bit-flip corrected @oob=%d\n", byte_pos -
 628                                                                 SECTOR_BYTES);
 629                 } else {
 630                         err = -EBADMSG;
 631                         printf("nand: error: invalid bit-flip location\n");
 632                 }
 633         }
 634         return (err) ? err : error_count;
 635 }
 636
 637 #ifdef CONFIG_NAND_OMAP_GPMC_PREFETCH
 638
 639 #define PREFETCH_CONFIG1_CS_SHIFT       24
 640 #define PREFETCH_FIFOTHRESHOLD_MAX      0x40
 641 #define PREFETCH_FIFOTHRESHOLD(val)     ((val) << 8)
 642 #define PREFETCH_STATUS_COUNT(val)      (val & 0x00003fff)
 643 #define PREFETCH_STATUS_FIFO_CNT(val)   ((val >> 24) & 0x7F)
 644 #define ENABLE_PREFETCH                 (1 << 7)
 645
 646 /**
 647  * omap_prefetch_enable - configures and starts prefetch transfer
 648  * @fifo_th: fifo threshold to be used for read/ write
 649  * @count: number of bytes to be transferred
 650  * @is_write: prefetch read(0) or write post(1) mode
 651  * @cs: chip select to use
 652  */
 653 static int omap_prefetch_enable(int fifo_th, unsigned int count, int is_write, int cs)
 654 {
 655         uint32_t val;
 656
 657         if (fifo_th > PREFETCH_FIFOTHRESHOLD_MAX)
 658                 return -EINVAL;
 659
 660         if (readl(&gpmc_cfg->prefetch_control))
 661                 return -EBUSY;
 662
 663         /* Set the amount of bytes to be prefetched */
 664         writel(count, &gpmc_cfg->prefetch_config2);
 665
 666         val = (cs << PREFETCH_CONFIG1_CS_SHIFT) | (is_write & 1) |
 667                 PREFETCH_FIFOTHRESHOLD(fifo_th) | ENABLE_PREFETCH;
 668         writel(val, &gpmc_cfg->prefetch_config1);
 669
 670         /*  Start the prefetch engine */
 671         writel(1, &gpmc_cfg->prefetch_control);
 672
 673         return 0;
 674 }
 675
 676 /**
 677  * omap_prefetch_reset - disables and stops the prefetch engine
 678  */
 679 static void omap_prefetch_reset(void)
 680 {
 681         writel(0, &gpmc_cfg->prefetch_control);
 682         writel(0, &gpmc_cfg->prefetch_config1);
 683 }
 684
 685 static int __read_prefetch_aligned(struct nand_chip *chip, uint32_t *buf, int len)
 686 {
 687         int ret;
 688         uint32_t cnt;
 689         struct omap_nand_info *info = chip->priv;
 690
 691         ret = omap_prefetch_enable(PREFETCH_FIFOTHRESHOLD_MAX, len, 0, info->cs);
 692         if (ret < 0)
 693                 return ret;
 694
 695         do {
 696                 int i;
 697
 698                 cnt = readl(&gpmc_cfg->prefetch_status);
 699                 cnt = PREFETCH_STATUS_FIFO_CNT(cnt);
 700
 701                 for (i = 0; i < cnt / 4; i++) {
 702                         *buf++ = readl(CONFIG_SYS_NAND_BASE);
 703                         len -= 4;
 704                 }
 705         } while (len);
 706
 707         omap_prefetch_reset();
 708
 709         return 0;
 710 }
 711
 712 static void omap_nand_read_prefetch8(struct mtd_info *mtd, uint8_t *buf, int len)
 713 {
 714         int ret;
 715         uint32_t head, tail;
 716         struct nand_chip *chip = mtd->priv;
 717
 718         /*
 719          * If the destination buffer is unaligned, start with reading
 720          * the overlap byte-wise.
 721          */
 722         head = ((uint32_t) buf) % 4;
 723         if (head) {
 724                 nand_read_buf(mtd, buf, head);
 725                 buf += head;
 726                 len -= head;
 727         }
 728
 729         /*
 730          * Only transfer multiples of 4 bytes in a pre-fetched fashion.
 731          * If there's a residue, care for it byte-wise afterwards.
 732          */
 733         tail = len % 4;
 734
 735         ret = __read_prefetch_aligned(chip, (uint32_t *) buf, len - tail);
 736         if (ret < 0) {
 737                 /* fallback in case the prefetch engine is busy */
 738                 nand_read_buf(mtd, buf, len);
 739         } else if (tail) {
 740                 buf += len - tail;
 741                 nand_read_buf(mtd, buf, tail);
 742         }
 743 }
 744 #endif /* CONFIG_NAND_OMAP_GPMC_PREFETCH */
 745
 746 /**
 747  * omap_read_page_bch - hardware ecc based page read function
 748  * @mtd:        mtd info structure
 749  * @chip:       nand chip info structure
 750  * @buf:        buffer to store read data
 751  * @oob_required: caller expects OOB data read to chip->oob_poi
 752  * @page:       page number to read
 753  *
 754  */
 755 static int omap_read_page_bch(struct mtd_info *mtd, struct nand_chip *chip,
 756                                 uint8_t *buf, int oob_required, int page)
 757 {
 758         int i, eccsize = chip->ecc.size;
 759         int eccbytes = chip->ecc.bytes;
 760         int eccsteps = chip->ecc.steps;
 761         uint8_t *p = buf;
 762         uint8_t *ecc_calc = chip->buffers->ecccalc;
 763         uint8_t *ecc_code = chip->buffers->ecccode;
 764         uint32_t *eccpos = chip->ecc.layout->eccpos;
 765         uint8_t *oob = &chip->oob_poi[eccpos[0]];
 766         uint32_t data_pos;
 767         uint32_t oob_pos;
 768
 769         data_pos = 0;
 770         /* oob area start */
 771         oob_pos = (eccsize * eccsteps) + eccpos[0];
 772
 773         for (i = 0; eccsteps; eccsteps--, i += eccbytes, p += eccsize,
 774                                 oob += eccbytes) {
 775                 chip->ecc.hwctl(mtd, NAND_ECC_READ);
 776                 /* read data */
 777                 chip->cmdfunc(mtd, NAND_CMD_RNDOUT, data_pos, -1);
 778                 chip->read_buf(mtd, p, eccsize);
 779
 780                 /* read respective ecc from oob area */
 781                 chip->cmdfunc(mtd, NAND_CMD_RNDOUT, oob_pos, -1);
 782                 chip->read_buf(mtd, oob, eccbytes);
 783                 /* read syndrome */
 784                 chip->ecc.calculate(mtd, p, &ecc_calc[i]);
 785
 786                 if (oob_required) {
 787                         /* reread the OOB area to get the metadata */
 788                         chip->cmdfunc(mtd, NAND_CMD_RNDOUT, mtd->writesize, page);
 789                         chip->read_buf(mtd, chip->oob_poi, mtd->oobsize);
 790                 }
 791
 792                 data_pos += eccsize;
 793                 oob_pos += eccbytes;
 794         }
 795
 796         for (i = 0; i < chip->ecc.total; i++)
 797                 ecc_code[i] = chip->oob_poi[eccpos[i]];
 798
 799         eccsteps = chip->ecc.steps;
 800         p = buf;
 801
 802         for (i = 0 ; eccsteps; eccsteps--, i += eccbytes, p += eccsize) {
 803                 int stat;
 804
 805                 stat = chip->ecc.correct(mtd, p, &ecc_code[i], &ecc_calc[i]);
 806                 if (stat < 0)
 807                         mtd->ecc_stats.failed++;
 808                 else
 809                         mtd->ecc_stats.corrected += stat;
 810         }
 811         return 0;
 812 }
 813 #endif /* CONFIG_NAND_OMAP_ELM */
 814
 815 /*
 816  * OMAP3 BCH8 support (with BCH library)
 817  */
 818 #ifdef CONFIG_BCH
 819 /**
 820  * omap_correct_data_bch_sw - Decode received data and correct errors
 821  * @mtd: MTD device structure
 822  * @data: page data
 823  * @read_ecc: ecc read from nand flash
 824  * @calc_ecc: ecc read from HW ECC registers
 825  */
 826 static int omap_correct_data_bch_sw(struct mtd_info *mtd, u_char *data,
 827                                  u_char *read_ecc, u_char *calc_ecc)
 828 {
 829         int i, count;
 830         /* cannot correct more than 8 errors */
 831         unsigned int errloc[8];
 832         struct nand_chip *chip = mtd->priv;
 833         struct omap_nand_info *info = chip->priv;
 834
 835         count = decode_bch(info->control, NULL, 512, read_ecc, calc_ecc,
 836                                                         NULL, errloc);
 837         if (count > 0) {
 838                 /* correct errors */
 839                 for (i = 0; i < count; i++) {
 840                         /* correct data only, not ecc bytes */
 841                         if (errloc[i] < 8*512)
 842                                 data[errloc[i]/8] ^= 1 << (errloc[i] & 7);
 843                         printf("corrected bitflip %u\n", errloc[i]);
 844 #ifdef DEBUG
 845                         printf("read_ecc: ");
 846                         /*
 847                          * BCH8 have 13 bytes of ECC; BCH4 needs adoption
 848                          * here!
 849                          */
 850                         for (i = 0; i < 13; i++)
 851                                 printf("%02x ", read_ecc[i]);
 852                         printf("\n");
 853                         printf("calc_ecc: ");
 854                         for (i = 0; i < 13; i++)
 855                                 printf("%02x ", calc_ecc[i]);
 856                         printf("\n");
 857 #endif
 858                 }
 859         } else if (count < 0) {
 860                 printf("ecc unrecoverable error\n");
 861         }
 862         return count;
 863 }
 864
 865 /**
 866  * omap_free_bch - Release BCH ecc resources
 867  * @mtd: MTD device structure
 868  */
 869 static void __maybe_unused omap_free_bch(struct mtd_info *mtd)
 870 {
 871         struct nand_chip *chip = mtd->priv;
 872         struct omap_nand_info *info = chip->priv;
 873
 874         if (info->control) {
 875                 free_bch(info->control);
 876                 info->control = NULL;
 877         }
 878 }
 879 #endif /* CONFIG_BCH */
 880
 881 /**
 882  * omap_select_ecc_scheme - configures driver for particular ecc-scheme
 883  * @nand: NAND chip device structure
 884  * @ecc_scheme: ecc scheme to configure
 885  * @pagesize: number of main-area bytes per page of NAND device
 886  * @oobsize: number of OOB/spare bytes per page of NAND device
 887  */
 888 static int omap_select_ecc_scheme(struct nand_chip *nand,
 889         enum omap_ecc ecc_scheme, unsigned int pagesize, unsigned int oobsize) {
 890         struct omap_nand_info   *info           = nand->priv;
 891         struct nand_ecclayout   *ecclayout      = &omap_ecclayout;
 892         int eccsteps = pagesize / SECTOR_BYTES;
 893         int i;
 894
 895         switch (ecc_scheme) {
 896         case OMAP_ECC_HAM1_CODE_SW:
 897                 debug("nand: selected OMAP_ECC_HAM1_CODE_SW\n");
 898                 /* For this ecc-scheme, ecc.bytes, ecc.layout, ... are
 899                  * initialized in nand_scan_tail(), so just set ecc.mode */
 900                 info->control           = NULL;
 901                 nand->ecc.mode          = NAND_ECC_SOFT;
 902                 nand->ecc.layout        = NULL;
 903                 nand->ecc.size          = 0;
 904                 break;
 905
 906         case OMAP_ECC_HAM1_CODE_HW:
 907                 debug("nand: selected OMAP_ECC_HAM1_CODE_HW\n");
 908                 /* check ecc-scheme requirements before updating ecc info */
 909                 if ((3 * eccsteps) + BADBLOCK_MARKER_LENGTH > oobsize) {
 910                         printf("nand: error: insufficient OOB: require=%d\n", (
 911                                 (3 * eccsteps) + BADBLOCK_MARKER_LENGTH));
 912                         return -EINVAL;
 913                 }
 914                 info->control           = NULL;
 915                 /* populate ecc specific fields */
 916                 memset(&nand->ecc, 0, sizeof(struct nand_ecc_ctrl));
 917                 nand->ecc.mode          = NAND_ECC_HW;
 918                 nand->ecc.strength      = 1;
 919                 nand->ecc.size          = SECTOR_BYTES;
 920                 nand->ecc.bytes         = 3;
 921                 nand->ecc.hwctl         = omap_enable_hwecc;
 922                 nand->ecc.correct       = omap_correct_data;
 923                 nand->ecc.calculate     = omap_calculate_ecc;
 924                 /* define ecc-layout */
 925                 ecclayout->eccbytes     = nand->ecc.bytes * eccsteps;
 926                 for (i = 0; i < ecclayout->eccbytes; i++) {
 927                         if (nand->options & NAND_BUSWIDTH_16)
 928                                 ecclayout->eccpos[i] = i + 2;
 929                         else
 930                                 ecclayout->eccpos[i] = i + 1;
 931                 }
 932                 ecclayout->oobfree[0].offset = i + BADBLOCK_MARKER_LENGTH;
 933                 ecclayout->oobfree[0].length = oobsize - ecclayout->eccbytes -
 934                                                 BADBLOCK_MARKER_LENGTH;
 935                 break;
 936
 937         case OMAP_ECC_BCH8_CODE_HW_DETECTION_SW:
 938 #ifdef CONFIG_BCH
 939                 debug("nand: selected OMAP_ECC_BCH8_CODE_HW_DETECTION_SW\n");
 940                 /* check ecc-scheme requirements before updating ecc info */
 941                 if ((13 * eccsteps) + BADBLOCK_MARKER_LENGTH > oobsize) {
 942                         printf("nand: error: insufficient OOB: require=%d\n", (
 943                                 (13 * eccsteps) + BADBLOCK_MARKER_LENGTH));
 944                         return -EINVAL;
 945                 }
 946                 /* check if BCH S/W library can be used for error detection */
 947                 info->control = init_bch(13, 8, 0x201b);
 948                 if (!info->control) {
 949                         printf("nand: error: could not init_bch()\n");
 950                         return -ENODEV;
 951                 }
 952                 /* populate ecc specific fields */
 953                 memset(&nand->ecc, 0, sizeof(struct nand_ecc_ctrl));
 954                 nand->ecc.mode          = NAND_ECC_HW;
 955                 nand->ecc.strength      = 8;
 956                 nand->ecc.size          = SECTOR_BYTES;
 957                 nand->ecc.bytes         = 13;
 958                 nand->ecc.hwctl         = omap_enable_hwecc;
 959                 nand->ecc.correct       = omap_correct_data_bch_sw;
 960                 nand->ecc.calculate     = omap_calculate_ecc;
 961                 /* define ecc-layout */
 962                 ecclayout->eccbytes     = nand->ecc.bytes * eccsteps;
 963                 ecclayout->eccpos[0]    = BADBLOCK_MARKER_LENGTH;
 964                 for (i = 1; i < ecclayout->eccbytes; i++) {
 965                         if (i % nand->ecc.bytes)
 966                                 ecclayout->eccpos[i] =
 967                                                 ecclayout->eccpos[i - 1] + 1;
 968                         else
 969                                 ecclayout->eccpos[i] =
 970                                                 ecclayout->eccpos[i - 1] + 2;
 971                 }
 972                 ecclayout->oobfree[0].offset = i + BADBLOCK_MARKER_LENGTH;
 973                 ecclayout->oobfree[0].length = oobsize - ecclayout->eccbytes -
 974                                                 BADBLOCK_MARKER_LENGTH;
 975                 break;
 976 #else
 977                 printf("nand: error: CONFIG_BCH required for ECC\n");
 978                 return -EINVAL;
 979 #endif
 980
 981         case OMAP_ECC_BCH8_CODE_HW:
 982 #ifdef CONFIG_NAND_OMAP_ELM
 983                 debug("nand: selected OMAP_ECC_BCH8_CODE_HW\n");
 984                 /* check ecc-scheme requirements before updating ecc info */
 985                 if ((14 * eccsteps) + BADBLOCK_MARKER_LENGTH > oobsize) {
 986                         printf("nand: error: insufficient OOB: require=%d\n", (
 987                                 (14 * eccsteps) + BADBLOCK_MARKER_LENGTH));
 988                         return -EINVAL;
 989                 }
 990                 /* intialize ELM for ECC error detection */
 991                 elm_init();
 992                 info->control           = NULL;
 993                 /* populate ecc specific fields */
 994                 memset(&nand->ecc, 0, sizeof(struct nand_ecc_ctrl));
 995                 nand->ecc.mode          = NAND_ECC_HW;
 996                 nand->ecc.strength      = 8;
 997                 nand->ecc.size          = SECTOR_BYTES;
 998                 nand->ecc.bytes         = 14;
 999                 nand->ecc.hwctl         = omap_enable_hwecc;
1000                 nand->ecc.correct       = omap_correct_data_bch;
1001                 nand->ecc.calculate     = omap_calculate_ecc;
1002                 nand->ecc.read_page     = omap_read_page_bch;
1003                 /* define ecc-layout */
1004                 ecclayout->eccbytes     = nand->ecc.bytes * eccsteps;
1005                 for (i = 0; i < ecclayout->eccbytes; i++)
1006                         ecclayout->eccpos[i] = i + BADBLOCK_MARKER_LENGTH;
1007                 ecclayout->oobfree[0].offset = i + BADBLOCK_MARKER_LENGTH;
1008                 ecclayout->oobfree[0].length = oobsize - ecclayout->eccbytes -
1009                                                 BADBLOCK_MARKER_LENGTH;
1010                 break;
1011 #else
1012                 printf("nand: error: CONFIG_NAND_OMAP_ELM required for ECC\n");
1013                 return -EINVAL;
1014 #endif
1015
1016         case OMAP_ECC_BCH16_CODE_HW:
1017 #ifdef CONFIG_NAND_OMAP_ELM
1018                 debug("nand: using OMAP_ECC_BCH16_CODE_HW\n");
1019                 /* check ecc-scheme requirements before updating ecc info */
1020                 if ((26 * eccsteps) + BADBLOCK_MARKER_LENGTH > oobsize) {
1021                         printf("nand: error: insufficient OOB: require=%d\n", (
1022                                 (26 * eccsteps) + BADBLOCK_MARKER_LENGTH));
1023                         return -EINVAL;
1024                 }
1025                 /* intialize ELM for ECC error detection */
1026                 elm_init();
1027                 /* populate ecc specific fields */
1028                 nand->ecc.mode          = NAND_ECC_HW;
1029                 nand->ecc.size          = SECTOR_BYTES;
1030                 nand->ecc.bytes         = 26;
1031                 nand->ecc.strength      = 16;
1032                 nand->ecc.hwctl         = omap_enable_hwecc;
1033                 nand->ecc.correct       = omap_correct_data_bch;
1034                 nand->ecc.calculate     = omap_calculate_ecc;
1035                 nand->ecc.read_page     = omap_read_page_bch;
1036                 /* define ecc-layout */
1037                 ecclayout->eccbytes     = nand->ecc.bytes * eccsteps;
1038                 for (i = 0; i < ecclayout->eccbytes; i++)
1039                         ecclayout->eccpos[i] = i + BADBLOCK_MARKER_LENGTH;
1040                 ecclayout->oobfree[0].offset = i + BADBLOCK_MARKER_LENGTH;
1041                 ecclayout->oobfree[0].length = oobsize - nand->ecc.bytes -
1042                                                 BADBLOCK_MARKER_LENGTH;
1043                 break;
1044 #else
1045                 printf("nand: error: CONFIG_NAND_OMAP_ELM required for ECC\n");
1046                 return -EINVAL;
1047 #endif
1048         default:
1049                 debug("nand: error: ecc scheme not enabled or supported\n");
1050                 return -EINVAL;
1051         }
1052
1053         /* nand_scan_tail() sets ham1 sw ecc; hw ecc layout is set by driver */
1054         if (ecc_scheme != OMAP_ECC_HAM1_CODE_SW)
1055                 nand->ecc.layout = ecclayout;
1056
1057         info->ecc_scheme = ecc_scheme;
1058         return 0;
1059 }
1060
1061 #ifndef CONFIG_SPL_BUILD
1062 /*
1063  * omap_nand_switch_ecc - switch the ECC operation between different engines
1064  * (h/w and s/w) and different algorithms (hamming and BCHx)
1065  *
1066  * @hardware            - true if one of the HW engines should be used
1067  * @eccstrength         - the number of bits that could be corrected
1068  *                        (1 - hamming, 4 - BCH4, 8 - BCH8, 16 - BCH16)
1069  */
1070 int __maybe_unused omap_nand_switch_ecc(uint32_t hardware, uint32_t eccstrength)
1071 {
1072         struct nand_chip *nand;
1073         struct mtd_info *mtd;
1074         int err = 0;
1075
1076         if (nand_curr_device < 0 ||
1077             nand_curr_device >= CONFIG_SYS_MAX_NAND_DEVICE ||
1078             !nand_info[nand_curr_device].name) {
1079                 printf("nand: error: no NAND devices found\n");
1080                 return -ENODEV;
1081         }
1082
1083         mtd = &nand_info[nand_curr_device];
1084         nand = mtd->priv;
1085         nand->options |= NAND_OWN_BUFFERS;
1086         nand->options &= ~NAND_SUBPAGE_READ;
1087         /* Setup the ecc configurations again */
1088         if (hardware) {
1089                 if (eccstrength == 1) {
1090                         err = omap_select_ecc_scheme(nand,
1091                                         OMAP_ECC_HAM1_CODE_HW,
1092                                         mtd->writesize, mtd->oobsize);
1093                 } else if (eccstrength == 8) {
1094                         err = omap_select_ecc_scheme(nand,
1095                                         OMAP_ECC_BCH8_CODE_HW,
1096                                         mtd->writesize, mtd->oobsize);
1097                 } else {
1098                         printf("nand: error: unsupported ECC scheme\n");
1099                         return -EINVAL;
1100                 }
1101         } else {
1102                 if (eccstrength == 1) {
1103                         err = omap_select_ecc_scheme(nand,
1104                                         OMAP_ECC_HAM1_CODE_SW,
1105                                         mtd->writesize, mtd->oobsize);
1106                 } else if (eccstrength == 8) {
1107                         err = omap_select_ecc_scheme(nand,
1108                                         OMAP_ECC_BCH8_CODE_HW_DETECTION_SW,
1109                                         mtd->writesize, mtd->oobsize);
1110                 } else {
1111                         printf("nand: error: unsupported ECC scheme\n");
1112                         return -EINVAL;
1113                 }
1114         }
1115
1116         /* Update NAND handling after ECC mode switch */
1117         if (!err)
1118                 err = nand_scan_tail(mtd);
1119         return err;
1120 }
1121 #endif /* CONFIG_SPL_BUILD */
1122
1123 /*
1124  * Board-specific NAND initialization. The following members of the
1125  * argument are board-specific:
1126  * - IO_ADDR_R: address to read the 8 I/O lines of the flash device
1127  * - IO_ADDR_W: address to write the 8 I/O lines of the flash device
1128  * - cmd_ctrl: hardwarespecific function for accesing control-lines
1129  * - waitfunc: hardwarespecific function for accesing device ready/busy line
1130  * - ecc.hwctl: function to enable (reset) hardware ecc generator
1131  * - ecc.mode: mode of ecc, see defines
1132  * - chip_delay: chip dependent delay for transfering data from array to
1133  *   read regs (tR)
1134  * - options: various chip options. They can partly be set to inform
1135  *   nand_scan about special functionality. See the defines for further
1136  *   explanation
1137  */
1138 int board_nand_init(struct nand_chip *nand)
1139 {
1140         int32_t gpmc_config = 0;
1141         int cs = cs_next++;
1142         int err = 0;
1143         /*
1144          * xloader/Uboot's gpmc configuration would have configured GPMC for
1145          * nand type of memory. The following logic scans and latches on to the
1146          * first CS with NAND type memory.
1147          * TBD: need to make this logic generic to handle multiple CS NAND
1148          * devices.
1149          */
1150         while (cs < GPMC_MAX_CS) {
1151                 /* Check if NAND type is set */
1152                 if ((readl(&gpmc_cfg->cs[cs].config1) & 0xC00) == 0x800) {
1153                         /* Found it!! */
1154                         break;
1155                 }
1156                 cs++;
1157         }
1158         if (cs >= GPMC_MAX_CS) {
1159                 printf("nand: error: Unable to find NAND settings in "
1160                         "GPMC Configuration - quitting\n");
1161                 return -ENODEV;
1162         }
1163
1164         gpmc_config = readl(&gpmc_cfg->config);
1165         /* Disable Write protect */
1166         gpmc_config |= 0x10;
1167         writel(gpmc_config, &gpmc_cfg->config);
1168
1169         nand->IO_ADDR_R = (void __iomem *)&gpmc_cfg->cs[cs].nand_dat;
1170         nand->IO_ADDR_W = (void __iomem *)&gpmc_cfg->cs[cs].nand_cmd;
1171         omap_nand_info[cs].control = NULL;
1172         omap_nand_info[cs].cs = cs;
1173         omap_nand_info[cs].ws = wscfg[cs];
1174         nand->priv      = &omap_nand_info[cs];
1175         nand->cmd_ctrl  = omap_nand_hwcontrol;
1176         nand->options   |= NAND_NO_PADDING | NAND_CACHEPRG;
1177         nand->chip_delay = 100;
1178         nand->ecc.layout = &omap_ecclayout;
1179
1180         /* configure driver and controller based on NAND device bus-width */
1181         gpmc_config = readl(&gpmc_cfg->cs[cs].config1);
1182 #if defined(CONFIG_SYS_NAND_BUSWIDTH_16BIT)
1183         nand->options |= NAND_BUSWIDTH_16;
1184         writel(gpmc_config | (0x1 << 12), &gpmc_cfg->cs[cs].config1);
1185 #else
1186         nand->options &= ~NAND_BUSWIDTH_16;
1187         writel(gpmc_config & ~(0x1 << 12), &gpmc_cfg->cs[cs].config1);
1188 #endif
1189         /* select ECC scheme */
1190 #if defined(CONFIG_NAND_OMAP_ECCSCHEME)
1191         err = omap_select_ecc_scheme(nand, CONFIG_NAND_OMAP_ECCSCHEME,
1192                         CONFIG_SYS_NAND_PAGE_SIZE, CONFIG_SYS_NAND_OOBSIZE);
1193 #else
1194         /* pagesize and oobsize are not required to configure sw ecc-scheme */
1195         err = omap_select_ecc_scheme(nand, OMAP_ECC_HAM1_CODE_SW,
1196                         0, 0);
1197 #endif
1198         if (err)
1199                 return err;
1200 #ifdef CONFIG_SYS_NAND_USE_FLASH_BBT
1201         if (nand->ecc.layout) {
1202                 bbt_main_descr.offs = nand->ecc.layout->oobfree[0].offset;
1203                 bbt_main_descr.veroffs = bbt_main_descr.offs +
1204                         sizeof(bbt_pattern);
1205
1206                 bbt_mirror_descr.offs = nand->ecc.layout->oobfree[0].offset;
1207                 bbt_mirror_descr.veroffs = bbt_mirror_descr.offs +
1208                         sizeof(mirror_pattern);
1209         }
1210
1211         nand->bbt_options |= NAND_BBT_USE_FLASH;
1212         nand->bbt_td = &bbt_main_descr;
1213         nand->bbt_md = &bbt_mirror_descr;
1214 #endif
1215
1216         /* TODO: Implement for 16-bit bus width */
1217         if (nand->options & NAND_BUSWIDTH_16)
1218                 nand->read_buf = nand_read_buf16;
1219 #ifdef CONFIG_NAND_OMAP_GPMC_PREFETCH
1220         else
1221                 nand->read_buf = omap_nand_read_prefetch8;
1222 #else
1223         else
1224                 nand->read_buf = nand_read_buf;
1225 #endif
1226
1227         nand->dev_ready = omap_dev_ready;
1228
1229         return 0;
1230 }