drivers/mtd/nand/xway_nand.c

   1 /*
   2  *  This program is free software; you can redistribute it and/or modify it
   3  *  under the terms of the GNU General Public License version 2 as published
   4  *  by the Free Software Foundation.
   5  *
   6  *  Copyright © 2012 John Crispin <blogic@openwrt.org>
   7  *  Copyright © 2016 Hauke Mehrtens <hauke@hauke-m.de>
   8  */
   9
  10 #include <linux/mtd/nand.h>
  11 #include <linux/of_gpio.h>
  12 #include <linux/of_platform.h>
  13
  14 #include <lantiq_soc.h>
  15
  16 /* nand registers */
  17 #define EBU_ADDSEL1             0x24
  18 #define EBU_NAND_CON            0xB0
  19 #define EBU_NAND_WAIT           0xB4
  20 #define  NAND_WAIT_RD           BIT(0) /* NAND flash status output */
  21 #define  NAND_WAIT_WR_C         BIT(3) /* NAND Write/Read complete */
  22 #define EBU_NAND_ECC0           0xB8
  23 #define EBU_NAND_ECC_AC         0xBC
  24
  25 /*
  26  * nand commands
  27  * The pins of the NAND chip are selected based on the address bits of the
  28  * "register" read and write. There are no special registers, but an
  29  * address range and the lower address bits are used to activate the
  30  * correct line. For example when the bit (1 << 2) is set in the address
  31  * the ALE pin will be activated.
  32  */
  33 #define NAND_CMD_ALE            BIT(2) /* address latch enable */
  34 #define NAND_CMD_CLE            BIT(3) /* command latch enable */
  35 #define NAND_CMD_CS             BIT(4) /* chip select */
  36 #define NAND_CMD_SE             BIT(5) /* spare area access latch */
  37 #define NAND_CMD_WP             BIT(6) /* write protect */
  38 #define NAND_WRITE_CMD_RESET    0xff
  39 #define NAND_WRITE_CMD          (NAND_CMD_CS | NAND_CMD_CLE)
  40 #define NAND_WRITE_ADDR         (NAND_CMD_CS | NAND_CMD_ALE)
  41 #define NAND_WRITE_DATA         (NAND_CMD_CS)
  42 #define NAND_READ_DATA          (NAND_CMD_CS)
  43
  44 /* we need to tel the ebu which addr we mapped the nand to */
  45 #define ADDSEL1_MASK(x)         (x << 4)
  46 #define ADDSEL1_REGEN           1
  47
  48 /* we need to tell the EBU that we have nand attached and set it up properly */
  49 #define BUSCON1_SETUP           (1 << 22)
  50 #define BUSCON1_BCGEN_RES       (0x3 << 12)
  51 #define BUSCON1_WAITWRC2        (2 << 8)
  52 #define BUSCON1_WAITRDC2        (2 << 6)
  53 #define BUSCON1_HOLDC1          (1 << 4)
  54 #define BUSCON1_RECOVC1         (1 << 2)
  55 #define BUSCON1_CMULT4          1
  56
  57 #define NAND_CON_CE             (1 << 20)
  58 #define NAND_CON_OUT_CS1        (1 << 10)
  59 #define NAND_CON_IN_CS1         (1 << 8)
  60 #define NAND_CON_PRE_P          (1 << 7)
  61 #define NAND_CON_WP_P           (1 << 6)
  62 #define NAND_CON_SE_P           (1 << 5)
  63 #define NAND_CON_CS_P           (1 << 4)
  64 #define NAND_CON_CSMUX          (1 << 1)
  65 #define NAND_CON_NANDM          1
  66
  67 struct xway_nand_data {
  68         struct nand_chip        chip;
  69 };
  70
  71 static void xway_reset_chip(struct nand_chip *chip)
  72 {
  73         unsigned long nandaddr = (unsigned long) chip->IO_ADDR_W;
  74         unsigned long flags;
  75
  76         nandaddr &= ~NAND_WRITE_ADDR;
  77         nandaddr |= NAND_WRITE_CMD;
  78
  79         /* finish with a reset */
  80         spin_lock_irqsave(&ebu_lock, flags);
  81         writeb(NAND_WRITE_CMD_RESET, (void __iomem *) nandaddr);
  82         while ((ltq_ebu_r32(EBU_NAND_WAIT) & NAND_WAIT_WR_C) == 0)
  83                 ;
  84         spin_unlock_irqrestore(&ebu_lock, flags);
  85 }
  86
  87 static void xway_select_chip(struct mtd_info *mtd, int chip)
  88 {
  89
  90         switch (chip) {
  91         case -1:
  92                 ltq_ebu_w32_mask(NAND_CON_CE, 0, EBU_NAND_CON);
  93                 ltq_ebu_w32_mask(NAND_CON_NANDM, 0, EBU_NAND_CON);
  94                 break;
  95         case 0:
  96                 ltq_ebu_w32_mask(0, NAND_CON_NANDM, EBU_NAND_CON);
  97                 ltq_ebu_w32_mask(0, NAND_CON_CE, EBU_NAND_CON);
  98                 break;
  99         default:
 100                 BUG();
 101         }
 102 }
 103
 104 static void xway_cmd_ctrl(struct mtd_info *mtd, int cmd, unsigned int ctrl)
 105 {
 106         struct nand_chip *this = mtd_to_nand(mtd);
 107         unsigned long nandaddr = (unsigned long) this->IO_ADDR_W;
 108         unsigned long flags;
 109
 110         if (ctrl & NAND_CTRL_CHANGE) {
 111                 nandaddr &= ~(NAND_WRITE_CMD | NAND_WRITE_ADDR);
 112                 if (ctrl & NAND_CLE)
 113                         nandaddr |= NAND_WRITE_CMD;
 114                 else
 115                         nandaddr |= NAND_WRITE_ADDR;
 116                 this->IO_ADDR_W = (void __iomem *) nandaddr;
 117         }
 118
 119         if (cmd != NAND_CMD_NONE) {
 120                 spin_lock_irqsave(&ebu_lock, flags);
 121                 writeb(cmd, this->IO_ADDR_W);
 122                 while ((ltq_ebu_r32(EBU_NAND_WAIT) & NAND_WAIT_WR_C) == 0)
 123                         ;
 124                 spin_unlock_irqrestore(&ebu_lock, flags);
 125         }
 126 }
 127
 128 static int xway_dev_ready(struct mtd_info *mtd)
 129 {
 130         return ltq_ebu_r32(EBU_NAND_WAIT) & NAND_WAIT_RD;
 131 }
 132
 133 static unsigned char xway_read_byte(struct mtd_info *mtd)
 134 {
 135         struct nand_chip *this = mtd_to_nand(mtd);
 136         unsigned long nandaddr = (unsigned long) this->IO_ADDR_R;
 137         unsigned long flags;
 138         int ret;
 139
 140         spin_lock_irqsave(&ebu_lock, flags);
 141         ret = ltq_r8((void __iomem *)(nandaddr + NAND_READ_DATA));
 142         spin_unlock_irqrestore(&ebu_lock, flags);
 143
 144         return ret;
 145 }
 146
 147 /*
 148  * Probe for the NAND device.
 149  */
 150 static int xway_nand_probe(struct platform_device *pdev)
 151 {
 152         struct xway_nand_data *data;
 153         struct mtd_info *mtd;
 154         struct resource *res;
 155         int err;
 156         void __iomem *nandaddr;
 157         u32 cs;
 158         u32 cs_flag = 0;
 159
 160         /* Allocate memory for the device structure (and zero it) */
 161         data = devm_kzalloc(&pdev->dev, sizeof(struct xway_nand_data),
 162                             GFP_KERNEL);
 163         if (!data)
 164                 return -ENOMEM;
 165
 166         res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
 167         nandaddr = devm_ioremap_resource(&pdev->dev, res);
 168         if (IS_ERR(nandaddr))
 169                 return PTR_ERR(nandaddr);
 170
 171         nand_set_flash_node(&data->chip, pdev->dev.of_node);
 172         mtd = nand_to_mtd(&data->chip);
 173         mtd->dev.parent = &pdev->dev;
 174
 175         data->chip.IO_ADDR_R = nandaddr;
 176         data->chip.IO_ADDR_W = nandaddr;
 177         data->chip.cmd_ctrl = xway_cmd_ctrl;
 178         data->chip.dev_ready = xway_dev_ready;
 179         data->chip.select_chip = xway_select_chip;
 180         data->chip.read_byte = xway_read_byte;
 181         data->chip.chip_delay = 30;
 182
 183         data->chip.ecc.mode = NAND_ECC_SOFT;
 184         data->chip.ecc.algo = NAND_ECC_HAMMING;
 185
 186         platform_set_drvdata(pdev, data);
 187         nand_set_controller_data(&data->chip, data);
 188
 189         /* load our CS from the DT. Either we find a valid 1 or default to 0 */
 190         err = of_property_read_u32(pdev->dev.of_node, "lantiq,cs", &cs);
 191         if (!err && cs == 1)
 192                 cs_flag = NAND_CON_IN_CS1 | NAND_CON_OUT_CS1;
 193
 194         /* setup the EBU to run in NAND mode on our base addr */
 195         ltq_ebu_w32(CPHYSADDR(nandaddr)
 196                 | ADDSEL1_MASK(3) | ADDSEL1_REGEN, EBU_ADDSEL1);
 197
 198         ltq_ebu_w32(BUSCON1_SETUP | BUSCON1_BCGEN_RES | BUSCON1_WAITWRC2
 199                 | BUSCON1_WAITRDC2 | BUSCON1_HOLDC1 | BUSCON1_RECOVC1
 200                 | BUSCON1_CMULT4, LTQ_EBU_BUSCON1);
 201
 202         ltq_ebu_w32(NAND_CON_NANDM | NAND_CON_CSMUX | NAND_CON_CS_P
 203                 | NAND_CON_SE_P | NAND_CON_WP_P | NAND_CON_PRE_P
 204                 | cs_flag, EBU_NAND_CON);
 205
 206         /* finish with a reset */
 207         xway_reset_chip(&data->chip);
 208
 209         /* Scan to find existence of the device */
 210         err = nand_scan(mtd, 1);
 211         if (err)
 212                 return err;
 213
 214         err = mtd_device_register(mtd, NULL, 0);
 215         if (err)
 216                 nand_release(mtd);
 217
 218         return err;
 219 }
 220
 221 /*
 222  * Remove a NAND device.
 223  */
 224 static int xway_nand_remove(struct platform_device *pdev)
 225 {
 226         struct xway_nand_data *data = platform_get_drvdata(pdev);
 227
 228         nand_release(nand_to_mtd(&data->chip));
 229
 230         return 0;
 231 }
 232
 233 static const struct of_device_id xway_nand_match[] = {
 234         { .compatible = "lantiq,nand-xway" },
 235         {},
 236 };
 237 MODULE_DEVICE_TABLE(of, xway_nand_match);
 238
 239 static struct platform_driver xway_nand_driver = {
 240         .probe  = xway_nand_probe,
 241         .remove = xway_nand_remove,
 242         .driver = {
 243                 .name           = "lantiq,nand-xway",
 244                 .of_match_table = xway_nand_match,
 245         },
 246 };
 247
 248 module_platform_driver(xway_nand_driver);
 249
 250 MODULE_LICENSE("GPL");