drivers/mtd/spi/sf_ops.c

   1 /*
   2  * SPI flash operations
   3  *
   4  * Copyright (C) 2008 Atmel Corporation
   5  * Copyright (C) 2010 Reinhard Meyer, EMK Elektronik
   6  * Copyright (C) 2013 Jagannadha Sutradharudu Teki, Xilinx Inc.
   7  *
   8  * SPDX-License-Identifier:     GPL-2.0+
   9  */
  10
  11 #include <common.h>
  12 #include <malloc.h>
  13 #include <spi.h>
  14 #include <spi_flash.h>
  15 #include <watchdog.h>
  16
  17 #include "sf_internal.h"
  18
  19 static void spi_flash_addr(u32 addr, u8 *cmd)
  20 {
  21         /* cmd[0] is actual command */
  22         cmd[1] = addr >> 16;
  23         cmd[2] = addr >> 8;
  24         cmd[3] = addr >> 0;
  25 }
  26
  27 int spi_flash_cmd_read_status(struct spi_flash *flash, u8 *rs)
  28 {
  29         int ret;
  30         u8 cmd;
  31
  32         cmd = CMD_READ_STATUS;
  33         ret = spi_flash_read_common(flash, &cmd, 1, rs, 1);
  34         if (ret < 0) {
  35                 debug("SF: fail to read status register\n");
  36                 return ret;
  37         }
  38
  39         return 0;
  40 }
  41
  42 int spi_flash_cmd_write_status(struct spi_flash *flash, u8 sr)
  43 {
  44         u8 cmd;
  45         int ret;
  46
  47         cmd = CMD_WRITE_STATUS;
  48         ret = spi_flash_write_common(flash, &cmd, 1, &sr, 1);
  49         if (ret < 0) {
  50                 debug("SF: fail to write status register\n");
  51                 return ret;
  52         }
  53
  54         return 0;
  55 }
  56
  57 #if defined(CONFIG_SPI_FLASH_SPANSION) || defined(CONFIG_SPI_FLASH_WINBOND)
  58 int spi_flash_cmd_read_config(struct spi_flash *flash, u8 *rc)
  59 {
  60         int ret;
  61         u8 cmd;
  62
  63         cmd = CMD_READ_CONFIG;
  64         ret = spi_flash_read_common(flash, &cmd, 1, rc, 1);
  65         if (ret < 0) {
  66                 debug("SF: fail to read config register\n");
  67                 return ret;
  68         }
  69
  70         return 0;
  71 }
  72
  73 int spi_flash_cmd_write_config(struct spi_flash *flash, u8 wc)
  74 {
  75         u8 data[2];
  76         u8 cmd;
  77         int ret;
  78
  79         ret = spi_flash_cmd_read_status(flash, &data[0]);
  80         if (ret < 0)
  81                 return ret;
  82
  83         cmd = CMD_WRITE_STATUS;
  84         data[1] = wc;
  85         ret = spi_flash_write_common(flash, &cmd, 1, &data, 2);
  86         if (ret) {
  87                 debug("SF: fail to write config register\n");
  88                 return ret;
  89         }
  90
  91         return 0;
  92 }
  93 #endif
  94
  95 #ifdef CONFIG_SPI_FLASH_BAR
  96 static int spi_flash_cmd_bankaddr_write(struct spi_flash *flash, u8 bank_sel)
  97 {
  98         u8 cmd;
  99         int ret;
 100
 101         if (flash->bank_curr == bank_sel) {
 102                 debug("SF: not require to enable bank%d\n", bank_sel);
 103                 return 0;
 104         }
 105
 106         cmd = flash->bank_write_cmd;
 107         ret = spi_flash_write_common(flash, &cmd, 1, &bank_sel, 1);
 108         if (ret < 0) {
 109                 debug("SF: fail to write bank register\n");
 110                 return ret;
 111         }
 112         flash->bank_curr = bank_sel;
 113
 114         return 0;
 115 }
 116
 117 static int spi_flash_bank(struct spi_flash *flash, u32 offset)
 118 {
 119         u8 bank_sel;
 120         int ret;
 121
 122         bank_sel = offset / SPI_FLASH_16MB_BOUN;
 123
 124         ret = spi_flash_cmd_bankaddr_write(flash, bank_sel);
 125         if (ret) {
 126                 debug("SF: fail to set bank%d\n", bank_sel);
 127                 return ret;
 128         }
 129
 130         return 0;
 131 }
 132 #endif
 133
 134 int spi_flash_cmd_wait_ready(struct spi_flash *flash, unsigned long timeout)
 135 {
 136         struct spi_slave *spi = flash->spi;
 137         unsigned long timebase;
 138         int ret;
 139         u8 status;
 140         u8 check_status = 0x0;
 141         u8 poll_bit = STATUS_WIP;
 142         u8 cmd = flash->poll_cmd;
 143
 144         if (cmd == CMD_FLAG_STATUS) {
 145                 poll_bit = STATUS_PEC;
 146                 check_status = poll_bit;
 147         }
 148
 149         ret = spi_xfer(spi, 8, &cmd, NULL, SPI_XFER_BEGIN);
 150         if (ret) {
 151                 debug("SF: fail to read %s status register\n",
 152                       cmd == CMD_READ_STATUS ? "read" : "flag");
 153                 return ret;
 154         }
 155
 156         timebase = get_timer(0);
 157         do {
 158                 WATCHDOG_RESET();
 159
 160                 ret = spi_xfer(spi, 8, NULL, &status, 0);
 161                 if (ret)
 162                         return -1;
 163
 164                 if ((status & poll_bit) == check_status)
 165                         break;
 166
 167         } while (get_timer(timebase) < timeout);
 168
 169         spi_xfer(spi, 0, NULL, NULL, SPI_XFER_END);
 170
 171         if ((status & poll_bit) == check_status)
 172                 return 0;
 173
 174         /* Timed out */
 175         debug("SF: time out!\n");
 176         return -1;
 177 }
 178
 179 int spi_flash_write_common(struct spi_flash *flash, const u8 *cmd,
 180                 size_t cmd_len, const void *buf, size_t buf_len)
 181 {
 182         struct spi_slave *spi = flash->spi;
 183         unsigned long timeout = SPI_FLASH_PROG_TIMEOUT;
 184         int ret;
 185
 186         if (buf == NULL)
 187                 timeout = SPI_FLASH_PAGE_ERASE_TIMEOUT;
 188
 189         ret = spi_claim_bus(flash->spi);
 190         if (ret) {
 191                 debug("SF: unable to claim SPI bus\n");
 192                 return ret;
 193         }
 194
 195         ret = spi_flash_cmd_write_enable(flash);
 196         if (ret < 0) {
 197                 debug("SF: enabling write failed\n");
 198                 return ret;
 199         }
 200
 201         ret = spi_flash_cmd_write(spi, cmd, cmd_len, buf, buf_len);
 202         if (ret < 0) {
 203                 debug("SF: write cmd failed\n");
 204                 return ret;
 205         }
 206
 207         ret = spi_flash_cmd_wait_ready(flash, timeout);
 208         if (ret < 0) {
 209                 debug("SF: write %s timed out\n",
 210                       timeout == SPI_FLASH_PROG_TIMEOUT ?
 211                         "program" : "page erase");
 212                 return ret;
 213         }
 214
 215         spi_release_bus(spi);
 216
 217         return ret;
 218 }
 219
 220 int spi_flash_cmd_erase_ops(struct spi_flash *flash, u32 offset, size_t len)
 221 {
 222         u32 erase_size;
 223         u8 cmd[SPI_FLASH_CMD_LEN];
 224         int ret = -1;
 225
 226         erase_size = flash->erase_size;
 227         if (offset % erase_size || len % erase_size) {
 228                 debug("SF: Erase offset/length not multiple of erase size\n");
 229                 return -1;
 230         }
 231
 232         cmd[0] = flash->erase_cmd;
 233         while (len) {
 234 #ifdef CONFIG_SPI_FLASH_BAR
 235                 ret = spi_flash_bank(flash, offset);
 236                 if (ret < 0)
 237                         return ret;
 238 #endif
 239                 spi_flash_addr(offset, cmd);
 240
 241                 debug("SF: erase %2x %2x %2x %2x (%x)\n", cmd[0], cmd[1],
 242                       cmd[2], cmd[3], offset);
 243
 244                 ret = spi_flash_write_common(flash, cmd, sizeof(cmd), NULL, 0);
 245                 if (ret < 0) {
 246                         debug("SF: erase failed\n");
 247                         break;
 248                 }
 249
 250                 offset += erase_size;
 251                 len -= erase_size;
 252         }
 253
 254         return ret;
 255 }
 256
 257 int spi_flash_cmd_write_ops(struct spi_flash *flash, u32 offset,
 258                 size_t len, const void *buf)
 259 {
 260         unsigned long byte_addr, page_size;
 261         size_t chunk_len, actual;
 262         u8 cmd[SPI_FLASH_CMD_LEN];
 263         int ret = -1;
 264
 265         page_size = flash->page_size;
 266
 267         cmd[0] = flash->write_cmd;
 268         for (actual = 0; actual < len; actual += chunk_len) {
 269 #ifdef CONFIG_SPI_FLASH_BAR
 270                 ret = spi_flash_bank(flash, offset);
 271                 if (ret < 0)
 272                         return ret;
 273 #endif
 274                 byte_addr = offset % page_size;
 275                 chunk_len = min(len - actual, page_size - byte_addr);
 276
 277                 if (flash->spi->max_write_size)
 278                         chunk_len = min(chunk_len, flash->spi->max_write_size);
 279
 280                 spi_flash_addr(offset, cmd);
 281
 282                 debug("PP: 0x%p => cmd = { 0x%02x 0x%02x%02x%02x } chunk_len = %zu\n",
 283                       buf + actual, cmd[0], cmd[1], cmd[2], cmd[3], chunk_len);
 284
 285                 ret = spi_flash_write_common(flash, cmd, sizeof(cmd),
 286                                         buf + actual, chunk_len);
 287                 if (ret < 0) {
 288                         debug("SF: write failed\n");
 289                         break;
 290                 }
 291
 292                 offset += chunk_len;
 293         }
 294
 295         return ret;
 296 }
 297
 298 int spi_flash_read_common(struct spi_flash *flash, const u8 *cmd,
 299                 size_t cmd_len, void *data, size_t data_len)
 300 {
 301         struct spi_slave *spi = flash->spi;
 302         int ret;
 303
 304         ret = spi_claim_bus(flash->spi);
 305         if (ret) {
 306                 debug("SF: unable to claim SPI bus\n");
 307                 return ret;
 308         }
 309
 310         ret = spi_flash_cmd_read(spi, cmd, cmd_len, data, data_len);
 311         if (ret < 0) {
 312                 debug("SF: read cmd failed\n");
 313                 return ret;
 314         }
 315
 316         spi_release_bus(spi);
 317
 318         return ret;
 319 }
 320
 321 int spi_flash_cmd_read_ops(struct spi_flash *flash, u32 offset,
 322                 size_t len, void *data)
 323 {
 324         u8 *cmd, cmdsz, bank_sel = 0;
 325         u32 remain_len, read_len;
 326         int ret = -1;
 327
 328         /* Handle memory-mapped SPI */
 329         if (flash->memory_map) {
 330                 ret = spi_claim_bus(flash->spi);
 331                 if (ret) {
 332                         debug("SF: unable to claim SPI bus\n");
 333                         return ret;
 334                 }
 335                 spi_xfer(flash->spi, 0, NULL, NULL, SPI_XFER_MMAP);
 336                 memcpy(data, flash->memory_map + offset, len);
 337                 spi_xfer(flash->spi, 0, NULL, NULL, SPI_XFER_MMAP_END);
 338                 spi_release_bus(flash->spi);
 339                 return 0;
 340         }
 341
 342         cmdsz = SPI_FLASH_CMD_LEN + flash->dummy_byte;
 343         cmd = malloc(cmdsz);
 344         memset(cmd, 0, cmdsz);
 345
 346         cmd[0] = flash->read_cmd;
 347         while (len) {
 348 #ifdef CONFIG_SPI_FLASH_BAR
 349                 bank_sel = offset / SPI_FLASH_16MB_BOUN;
 350
 351                 ret = spi_flash_cmd_bankaddr_write(flash, bank_sel);
 352                 if (ret) {
 353                         debug("SF: fail to set bank%d\n", bank_sel);
 354                         return ret;
 355                 }
 356 #endif
 357                 remain_len = (SPI_FLASH_16MB_BOUN * (bank_sel + 1)) - offset;
 358                 if (len < remain_len)
 359                         read_len = len;
 360                 else
 361                         read_len = remain_len;
 362
 363                 spi_flash_addr(offset, cmd);
 364
 365                 ret = spi_flash_read_common(flash, cmd, cmdsz, data, read_len);
 366                 if (ret < 0) {
 367                         debug("SF: read failed\n");
 368                         break;
 369                 }
 370
 371                 offset += read_len;
 372                 len -= read_len;
 373                 data += read_len;
 374         }
 375
 376         return ret;
 377 }
 378
 379 #ifdef CONFIG_SPI_FLASH_SST
 380 static int sst_byte_write(struct spi_flash *flash, u32 offset, const void *buf)
 381 {
 382         int ret;
 383         u8 cmd[4] = {
 384                 CMD_SST_BP,
 385                 offset >> 16,
 386                 offset >> 8,
 387                 offset,
 388         };
 389
 390         debug("BP[%02x]: 0x%p => cmd = { 0x%02x 0x%06x }\n",
 391               spi_w8r8(flash->spi, CMD_READ_STATUS), buf, cmd[0], offset);
 392
 393         ret = spi_flash_cmd_write_enable(flash);
 394         if (ret)
 395                 return ret;
 396
 397         ret = spi_flash_cmd_write(flash->spi, cmd, sizeof(cmd), buf, 1);
 398         if (ret)
 399                 return ret;
 400
 401         return spi_flash_cmd_wait_ready(flash, SPI_FLASH_PROG_TIMEOUT);
 402 }
 403
 404 int sst_write_wp(struct spi_flash *flash, u32 offset, size_t len,
 405                 const void *buf)
 406 {
 407         size_t actual, cmd_len;
 408         int ret;
 409         u8 cmd[4];
 410
 411         ret = spi_claim_bus(flash->spi);
 412         if (ret) {
 413                 debug("SF: Unable to claim SPI bus\n");
 414                 return ret;
 415         }
 416
 417         /* If the data is not word aligned, write out leading single byte */
 418         actual = offset % 2;
 419         if (actual) {
 420                 ret = sst_byte_write(flash, offset, buf);
 421                 if (ret)
 422                         goto done;
 423         }
 424         offset += actual;
 425
 426         ret = spi_flash_cmd_write_enable(flash);
 427         if (ret)
 428                 goto done;
 429
 430         cmd_len = 4;
 431         cmd[0] = CMD_SST_AAI_WP;
 432         cmd[1] = offset >> 16;
 433         cmd[2] = offset >> 8;
 434         cmd[3] = offset;
 435
 436         for (; actual < len - 1; actual += 2) {
 437                 debug("WP[%02x]: 0x%p => cmd = { 0x%02x 0x%06x }\n",
 438                       spi_w8r8(flash->spi, CMD_READ_STATUS), buf + actual,
 439                       cmd[0], offset);
 440
 441                 ret = spi_flash_cmd_write(flash->spi, cmd, cmd_len,
 442                                         buf + actual, 2);
 443                 if (ret) {
 444                         debug("SF: sst word program failed\n");
 445                         break;
 446                 }
 447
 448                 ret = spi_flash_cmd_wait_ready(flash, SPI_FLASH_PROG_TIMEOUT);
 449                 if (ret)
 450                         break;
 451
 452                 cmd_len = 1;
 453                 offset += 2;
 454         }
 455
 456         if (!ret)
 457                 ret = spi_flash_cmd_write_disable(flash);
 458
 459         /* If there is a single trailing byte, write it out */
 460         if (!ret && actual != len)
 461                 ret = sst_byte_write(flash, offset, buf + actual);
 462
 463  done:
 464         debug("SF: sst: program %s %zu bytes @ 0x%zx\n",
 465               ret ? "failure" : "success", len, offset - actual);
 466
 467         spi_release_bus(flash->spi);
 468         return ret;
 469 }
 470 #endif