2 * Copyright 2008-2013 Freescale Semiconductor, Inc. All Rights Reserved.
4 * The code contained herein is licensed under the GNU General Public
5 * License. You may obtain a copy of the GNU General Public License
6 * Version 2 or later at the following locations:
8 * http://www.opensource.org/licenses/gpl-license.html
9 * http://www.gnu.org/copyleft/gpl.html
13 * @brief MXC Asynchronous Sample Rate Converter
18 #include <linux/module.h>
19 #include <linux/platform_device.h>
20 #include <linux/miscdevice.h>
21 #include <linux/kernel.h>
22 #include <linux/init.h>
23 #include <linux/clk.h>
24 #include <linux/slab.h>
25 #include <linux/ctype.h>
26 #include <linux/regmap.h>
27 #include <linux/pagemap.h>
28 #include <linux/vmalloc.h>
29 #include <linux/types.h>
30 #include <linux/version.h>
31 #include <linux/interrupt.h>
32 #include <linux/proc_fs.h>
33 #include <linux/dma-mapping.h>
34 #include <linux/fsl_devices.h>
35 #include <linux/sched.h>
37 #include <linux/memory.h>
38 #include <linux/delay.h>
39 #include <linux/of_address.h>
40 #include <linux/of_irq.h>
41 #include <linux/of_platform.h>
42 #include <linux/platform_data/dma-imx.h>
43 #include <linux/mxc_asrc.h>
45 #define ASRC_PROC_PATH "driver/asrc"
47 #define ASRC_RATIO_DECIMAL_DEPTH 26
49 DEFINE_SPINLOCK(data_lock);
50 DEFINE_SPINLOCK(pair_lock);
51 DEFINE_SPINLOCK(input_int_lock);
52 DEFINE_SPINLOCK(output_int_lock);
54 /* Sample rates are aligned with that defined in pcm.h file */
55 static const unsigned char asrc_process_table[][8][2] = {
56 /* 32kHz 44.1kHz 48kHz 64kHz 88.2kHz 96kHz 176kHz 192kHz */
57 {{0, 0}, {0, 0}, {0, 0}, {0, 0}, {0, 0}, {0, 0}, {0, 0}, {0, 0},}, /* 5512Hz */
58 {{0, 0}, {0, 0}, {0, 0}, {0, 0}, {0, 0}, {0, 0}, {0, 0}, {0, 0},}, /* 8kHz */
59 {{0, 0}, {0, 0}, {0, 0}, {0, 0}, {0, 0}, {0, 0}, {0, 0}, {0, 0},}, /* 11025Hz */
60 {{0, 1}, {0, 1}, {0, 1}, {0, 0}, {0, 0}, {0, 0}, {0, 0}, {0, 0},}, /* 16kHz */
61 {{0, 1}, {0, 1}, {0, 1}, {0, 0}, {0, 0}, {0, 0}, {0, 0}, {0, 0},}, /* 22050Hz */
62 {{0, 1}, {0, 1}, {0, 1}, {0, 1}, {0, 1}, {0, 0}, {0, 0}, {0, 0},}, /* 32kHz */
63 {{0, 2}, {0, 1}, {0, 1}, {0, 1}, {0, 1}, {0, 1}, {0, 0}, {0, 0},}, /* 44.1kHz */
64 {{0, 2}, {0, 2}, {0, 1}, {0, 1}, {0, 1}, {0, 1}, {0, 0}, {0, 0},}, /* 48kHz */
65 {{1, 2}, {0, 2}, {0, 2}, {0, 1}, {0, 1}, {0, 1}, {0, 1}, {0, 0},}, /* 64kHz */
66 {{1, 2}, {1, 2}, {1, 2}, {1, 1}, {1, 1}, {1, 1}, {1, 1}, {1, 1},}, /* 88.2kHz */
67 {{1, 2}, {1, 2}, {1, 2}, {1, 1}, {1, 1}, {1, 1}, {1, 1}, {1, 1},}, /* 96kHz */
68 {{2, 2}, {2, 2}, {2, 2}, {2, 1}, {2, 1}, {2, 1}, {2, 1}, {2, 1},}, /* 176kHz */
69 {{2, 2}, {2, 2}, {2, 2}, {2, 1}, {2, 1}, {2, 1}, {2, 1}, {2, 1},}, /* 192kHz */
72 static struct asrc_data *asrc;
75 * The following tables map the relationship between asrc_inclk/asrc_outclk in
76 * mxc_asrc.h and the registers of ASRCSR
78 static unsigned char input_clk_map_v1[] = {
79 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 0xa, 0xb, 0xc, 0xd, 0xe, 0xf,
82 static unsigned char output_clk_map_v1[] = {
83 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 0xa, 0xb, 0xc, 0xd, 0xe, 0xf,
86 /* V2 uses the same map for input and output */
87 static unsigned char input_clk_map_v2[] = {
88 /* 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7 0x8 0x9 0xa 0xb 0xc 0xd 0xe 0xf*/
89 0x0, 0x1, 0x2, 0x7, 0x4, 0x5, 0x6, 0x3, 0x8, 0x9, 0xa, 0xb, 0xc, 0xf, 0xe, 0xd,
92 static unsigned char output_clk_map_v2[] = {
93 /* 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7 0x8 0x9 0xa 0xb 0xc 0xd 0xe 0xf*/
94 0x8, 0x9, 0xa, 0x7, 0xc, 0x5, 0x6, 0xb, 0x0, 0x1, 0x2, 0x3, 0x4, 0xf, 0xe, 0xd,
97 static unsigned char *input_clk_map, *output_clk_map;
99 /* ALL registers of ASRC are 24-bit efficient */
100 static u32 asrc_regmap_read(struct regmap *map, unsigned int reg,
103 #ifndef ASRC_USE_REGMAP
104 *val = readl((void __iomem *)asrc->vaddr + reg) & 0xffffff;
107 return regmap_read(map, reg, val);
111 static void asrc_regmap_write(struct regmap *map, unsigned int reg,
114 #ifndef ASRC_USE_REGMAP
115 writel(val & 0xffffff, (void __iomem *)asrc->vaddr + reg);
117 return regmap_write(map, reg, val);
121 static void asrc_regmap_update_bits(struct regmap *map, unsigned int reg,
122 unsigned int mask, unsigned int val)
124 #ifndef ASRC_USE_REGMAP
127 regval = readl((void __iomem *)asrc->vaddr + reg) & 0xffffff;
128 regval = (regval & ~mask) | (val & mask);
129 writel(regval & 0xffffff, (void __iomem *)asrc->vaddr + reg);
131 regmap_update_bits(map, reg, mask, val);
135 /* Set ASRC_REG_ASRCNCR reg, only supporting one-pair setting at once */
136 static int asrc_set_channel_number(enum asrc_pair_index index, u32 val)
140 asrc_regmap_read(asrc->regmap, REG_ASRCNCR, &num);
144 num &= ~ASRCNCR_ANCA_MASK(asrc->channel_bits);
148 num &= ~ASRCNCR_ANCB_MASK(asrc->channel_bits);
149 num |= val << asrc->channel_bits;
152 num &= ~ASRCNCR_ANCC_MASK(asrc->channel_bits);
153 num |= val << asrc->channel_bits * 2;
156 dev_err(asrc->dev, "ASRC pair number not exists.\n");
160 asrc_regmap_write(asrc->regmap, REG_ASRCNCR, num);
204 static void dump_regs(void)
209 for (i = 0; i < ARRAY_SIZE(asrc_reg); i++) {
211 asrc_regmap_read(asrc->regmap, reg, &val);
212 pr_debug("REG addr=0x%x val=0x%x\n", reg, val);
216 static void dump_regs(void) {}
219 /* Only used for Ideal Ratio mode */
220 static int asrc_set_clock_ratio(enum asrc_pair_index index,
221 int inrate, int outrate)
223 unsigned long val = 0;
228 dev_err(asrc->dev, "Wrong output sample rate: %d\n", outrate);
232 /* Formula: r = (1 << ASRC_RATIO_DECIMAL_DEPTH) / outrate * inrate; */
233 for (integ = 0; inrate >= outrate; integ++)
236 val |= (integ << ASRC_RATIO_DECIMAL_DEPTH);
238 for (i = 1; i <= ASRC_RATIO_DECIMAL_DEPTH; i++) {
239 if ((inrate * 2) >= outrate) {
240 val |= (1 << (ASRC_RATIO_DECIMAL_DEPTH - i));
241 inrate = inrate * 2 - outrate;
243 inrate = inrate << 1;
249 asrc_regmap_write(asrc->regmap, REG_ASRIDRL(index), val);
250 asrc_regmap_write(asrc->regmap, REG_ASRIDRH(index), (val >> 24));
255 /* Corresponding to asrc_process_table */
256 static int supported_input_rate[] = {
257 5512, 8000, 11025, 16000, 22050, 32000, 44100, 48000, 64000, 88200,
258 96000, 176400, 192000,
261 static int supported_output_rate[] = {
262 32000, 44100, 48000, 64000, 88200, 96000, 176400, 192000,
265 static int asrc_set_process_configuration(enum asrc_pair_index index,
266 int inrate, int outrate)
270 for (in = 0; in < ARRAY_SIZE(supported_input_rate); in++) {
271 if (inrate == supported_input_rate[in])
275 if (in == ARRAY_SIZE(supported_input_rate)) {
276 dev_err(asrc->dev, "Unsupported input sample rate: %d\n", in);
280 for (out = 0; out < ARRAY_SIZE(supported_output_rate); out++) {
281 if (outrate == supported_output_rate[out])
285 if (out == ARRAY_SIZE(supported_output_rate)) {
286 dev_err(asrc->dev, "Unsupported output sample rate: %d\n", out);
290 asrc_regmap_update_bits(asrc->regmap, REG_ASRCFG,
291 ASRCFG_PREMODx_MASK(index) | ASRCFG_POSTMODx_MASK(index),
292 ASRCFG_PREMOD(index, asrc_process_table[in][out][0]) |
293 ASRCFG_POSTMOD(index, asrc_process_table[in][out][1]));
298 static int asrc_get_asrck_clock_divider(int samplerate)
300 unsigned int prescaler, divider;
301 unsigned int ratio, ra;
302 unsigned long bitclk;
305 if (samplerate == 0) {
306 dev_err(asrc->dev, "Wrong sample rate: %d\n", samplerate);
310 bitclk = clk_get_rate(asrc->asrc_clk);
312 ra = bitclk/samplerate;
315 /* Calculate the prescaler */
316 for (i = 0; ratio > 8; i++)
321 /* Calculate the divider */
323 divider = ((ra + (1 << (i - 1)) - 1) >> i) - 1;
327 /* The totally divider is (2 ^ prescaler) * divider */
328 return (divider << ASRCDRx_AxCPx_WIDTH) + prescaler;
331 int asrc_req_pair(int chn_num, enum asrc_pair_index *index)
333 struct asrc_pair *pair;
334 unsigned long lock_flags;
335 int imax = 0, busy = 0, i, ret = 0;
337 spin_lock_irqsave(&data_lock, lock_flags);
339 for (i = ASRC_PAIR_A; i < ASRC_PAIR_MAX_NUM; i++) {
340 pair = &asrc->asrc_pair[i];
341 if (chn_num > pair->chn_max) {
344 } else if (pair->active) {
348 /* Save the current qualified pair */
351 /* Check if this pair is a perfect one */
352 if (chn_num == pair->chn_max)
356 if (imax == ASRC_PAIR_MAX_NUM) {
357 dev_err(asrc->dev, "No pair could afford requested channel number.\n");
359 } else if (busy == ASRC_PAIR_MAX_NUM) {
360 dev_err(asrc->dev, "All pairs are busy now.\n");
362 } else if (busy + imax >= ASRC_PAIR_MAX_NUM) {
363 pr_err("All affordable pairs are busy now.\n");
366 pair = &asrc->asrc_pair[*index];
367 pair->chn_num = chn_num;
371 spin_unlock_irqrestore(&data_lock, lock_flags);
374 clk_enable(asrc->asrc_clk);
378 EXPORT_SYMBOL(asrc_req_pair);
380 void asrc_release_pair(enum asrc_pair_index index)
382 struct asrc_pair *pair = &asrc->asrc_pair[index];
383 unsigned long lock_flags;
385 spin_lock_irqsave(&data_lock, lock_flags);
388 pair->overload_error = 0;
391 asrc_regmap_update_bits(asrc->regmap, REG_ASRCTR,
392 ASRCTR_ASRCEx_MASK(index), 0);
394 spin_unlock_irqrestore(&data_lock, lock_flags);
396 EXPORT_SYMBOL(asrc_release_pair);
398 int asrc_config_pair(struct asrc_config *config)
400 u32 inrate = config->input_sample_rate, indiv;
401 u32 outrate = config->output_sample_rate, outdiv;
402 unsigned long lock_flags;
403 int index = config->pair;
407 /* Set the channel number */
408 spin_lock_irqsave(&data_lock, lock_flags);
409 asrc->asrc_pair[index].chn_num = config->channel_num;
410 spin_unlock_irqrestore(&data_lock, lock_flags);
412 if (asrc->channel_bits > 3)
413 channel_num = config->channel_num;
415 channel_num = (config->channel_num + 1) / 2;
417 asrc_set_channel_number(index, channel_num);
419 /* Set the clock source */
420 asrc_regmap_update_bits(asrc->regmap, REG_ASRCSR,
421 ASRCSR_AICSx_MASK(index) | ASRCSR_AOCSx_MASK(index),
422 ASRCSR_AICS(index, input_clk_map[config->inclk]) |
423 ASRCSR_AOCS(index, output_clk_map[config->outclk]));
425 /* Default setting: Automatic selection for processing mode */
426 asrc_regmap_update_bits(asrc->regmap, REG_ASRCTR,
427 ASRCTR_ATSx_MASK(index), ASRCTR_ATS(index));
428 asrc_regmap_update_bits(asrc->regmap, REG_ASRCTR,
429 ASRCTR_USRx_MASK(index), 0);
431 /* Default Input Clock Divider Setting */
432 switch (config->inclk & ASRCSR_AxCSx_MASK) {
434 indiv = ASRC_PRESCALER_SPDIF_RX;
437 indiv = ASRC_PRESCALER_SPDIF_TX;
439 case INCLK_ASRCK1_CLK:
440 indiv = asrc_get_asrck_clock_divider(inrate);
443 switch (config->input_word_width) {
444 case ASRC_WIDTH_16_BIT:
445 indiv = ASRC_PRESCALER_I2S_16BIT;
447 case ASRC_WIDTH_24_BIT:
448 indiv = ASRC_PRESCALER_I2S_24BIT;
451 dev_err(asrc->dev, "Unsupported input word width %d\n",
452 config->input_word_width);
458 /* Default Output Clock Divider Setting */
459 switch (config->outclk & ASRCSR_AxCSx_MASK) {
460 case OUTCLK_SPDIF_RX:
461 outdiv = ASRC_PRESCALER_SPDIF_RX;
463 case OUTCLK_SPDIF_TX:
464 outdiv = ASRC_PRESCALER_SPDIF_TX;
466 case OUTCLK_ASRCK1_CLK:
467 if ((config->inclk & ASRCSR_AxCSx_MASK) == INCLK_NONE)
468 outdiv = ASRC_PRESCALER_IDEAL_RATIO;
470 outdiv = asrc_get_asrck_clock_divider(outrate);
473 switch (config->output_word_width) {
474 case ASRC_WIDTH_16_BIT:
475 outdiv = ASRC_PRESCALER_I2S_16BIT;
477 case ASRC_WIDTH_24_BIT:
478 outdiv = ASRC_PRESCALER_I2S_24BIT;
481 dev_err(asrc->dev, "Unsupported output word width %d\n",
482 config->input_word_width);
488 /* indiv and outdiv'd include prescaler's value, so add its MASK too */
489 asrc_regmap_update_bits(asrc->regmap, REG_ASRCDR(index),
490 ASRCDRx_AOCPx_MASK(index) | ASRCDRx_AICPx_MASK(index) |
491 ASRCDRx_AOCDx_MASK(index) | ASRCDRx_AICDx_MASK(index),
492 ASRCDRx_AOCP(index, outdiv) | ASRCDRx_AICP(index, indiv));
494 /* Check whether ideal ratio is a must */
495 switch (config->inclk & ASRCSR_AxCSx_MASK) {
497 /* Clear ASTSx bit to use ideal ratio */
498 asrc_regmap_update_bits(asrc->regmap, REG_ASRCTR,
499 ASRCTR_ATSx_MASK(index), 0);
501 asrc_regmap_update_bits(asrc->regmap, REG_ASRCTR,
502 ASRCTR_IDRx_MASK(index) | ASRCTR_USRx_MASK(index),
503 ASRCTR_IDR(index) | ASRCTR_USR(index));
505 ret = asrc_set_clock_ratio(index, inrate, outrate);
509 ret = asrc_set_process_configuration(index, inrate, outrate);
514 case INCLK_ASRCK1_CLK:
515 /* This case and default are both remained for v1 */
516 if (inrate == 44100 || inrate == 88200) {
517 dev_err(asrc->dev, "Unsupported sample rate %d by ASRC clock.\n",
523 if ((config->outclk & ASRCSR_AxCSx_MASK) != OUTCLK_ASRCK1_CLK)
526 if (outrate == 44100 || outrate == 88200) {
527 dev_err(asrc->dev, "Unsupported sample rate %d by ASRC clock.\n",
534 /* Config input and output wordwidth */
535 if (config->output_word_width == ASRC_WIDTH_8_BIT) {
536 dev_err(asrc->dev, "Unsupported wordwidth for output: 8bit.\n");
537 dev_err(asrc->dev, "Output only support: 16bit or 24bit.\n");
541 asrc_regmap_update_bits(asrc->regmap, REG_ASRMCR1(index),
542 ASRMCR1x_OW16_MASK | ASRMCR1x_IWD_MASK,
543 ASRMCR1x_OW16(config->output_word_width) |
544 ASRMCR1x_IWD(config->input_word_width));
546 /* Enable BUFFER STALL */
547 asrc_regmap_update_bits(asrc->regmap, REG_ASRMCR(index),
548 ASRMCRx_BUFSTALLx_MASK, ASRMCRx_BUFSTALLx);
550 /* Set Threshold for input and output FIFO */
551 ret = asrc_set_watermark(index, ASRC_INPUTFIFO_THRESHOLD,
552 ASRC_INPUTFIFO_THRESHOLD);
556 EXPORT_SYMBOL(asrc_config_pair);
558 #define ASRC_MAX_FIFO_THRESHOLD 63
560 int asrc_set_watermark(enum asrc_pair_index index, u32 in_wm, u32 out_wm)
562 if (in_wm > ASRC_MAX_FIFO_THRESHOLD ||
563 out_wm > ASRC_MAX_FIFO_THRESHOLD) {
564 dev_err(asrc->dev, "Error watermark!\n");
568 asrc_regmap_update_bits(asrc->regmap, REG_ASRMCR(index),
569 ASRMCRx_EXTTHRSHx_MASK | ASRMCRx_INFIFO_THRESHOLD_MASK |
570 ASRMCRx_OUTFIFO_THRESHOLD_MASK,
571 ASRMCRx_EXTTHRSHx | ASRMCRx_INFIFO_THRESHOLD(in_wm) |
572 ASRMCRx_OUTFIFO_THRESHOLD(out_wm));
576 EXPORT_SYMBOL(asrc_set_watermark);
578 void asrc_start_conv(enum asrc_pair_index index)
580 unsigned long lock_flags;
583 spin_lock_irqsave(&data_lock, lock_flags);
585 asrc_regmap_update_bits(asrc->regmap, REG_ASRCTR,
586 ASRCTR_ASRCEx_MASK(index), ASRCTR_ASRCE(index));
588 /* Wait for status of initialization */
589 for (retry = 10, reg = 0; !reg && retry; --retry) {
591 asrc_regmap_read(asrc->regmap, REG_ASRCFG, ®);
592 reg &= ASRCFG_INIRQx_MASK(index);
595 /* Overload Interrupt Enable */
596 asrc_regmap_write(asrc->regmap, REG_ASRIER, ASRIER_AOLIE);
598 spin_unlock_irqrestore(&data_lock, lock_flags);
602 EXPORT_SYMBOL(asrc_start_conv);
604 void asrc_stop_conv(enum asrc_pair_index index)
606 unsigned long lock_flags;
608 spin_lock_irqsave(&data_lock, lock_flags);
610 asrc_regmap_update_bits(asrc->regmap, REG_ASRCTR,
611 ASRCTR_ASRCEx_MASK(index), 0);
613 spin_unlock_irqrestore(&data_lock, lock_flags);
617 EXPORT_SYMBOL(asrc_stop_conv);
619 void asrc_finish_conv(enum asrc_pair_index index)
621 clk_disable(asrc->asrc_clk);
624 EXPORT_SYMBOL(asrc_finish_conv);
626 #define SET_OVERLOAD_ERR(index, err) \
627 do {asrc->asrc_pair[index].overload_error |= err; } while (0)
629 static irqreturn_t asrc_isr(int irq, void *dev_id)
631 enum asrc_pair_index index;
634 asrc_regmap_read(asrc->regmap, REG_ASRSTR, &status);
636 for (index = ASRC_PAIR_A; index < ASRC_PAIR_MAX_NUM; index++) {
637 if (asrc->asrc_pair[index].active == 0)
639 if (status & ASRSTR_ATQOL)
640 SET_OVERLOAD_ERR(index, ASRC_TASK_Q_OVERLOAD);
641 if (status & ASRSTR_AOOL(index))
642 SET_OVERLOAD_ERR(index, ASRC_OUTPUT_TASK_OVERLOAD);
643 if (status & ASRSTR_AIOL(index))
644 SET_OVERLOAD_ERR(index, ASRC_INPUT_TASK_OVERLOAD);
645 if (status & ASRSTR_AODO(index))
646 SET_OVERLOAD_ERR(index, ASRC_OUTPUT_BUFFER_OVERFLOW);
647 if (status & ASRSTR_AIDU(index))
648 SET_OVERLOAD_ERR(index, ASRC_INPUT_BUFFER_UNDERRUN);
651 /* Clean overload error */
652 asrc_regmap_update_bits(asrc->regmap, REG_ASRSTR,
653 ASRSTR_AOLE_MASK, ASRSTR_AOLE);
658 void asrc_get_status(struct asrc_status_flags *flags)
660 enum asrc_pair_index index = flags->index;
661 unsigned long lock_flags;
663 spin_lock_irqsave(&data_lock, lock_flags);
665 flags->overload_error = asrc->asrc_pair[index].overload_error;
667 spin_unlock_irqrestore(&data_lock, lock_flags);
671 EXPORT_SYMBOL(asrc_get_status);
673 u32 asrc_get_per_addr(enum asrc_pair_index index, bool in)
675 u32 addr = in ? REG_ASRDI(index) : REG_ASRDO(index);
677 return asrc->paddr + addr;
679 EXPORT_SYMBOL(asrc_get_per_addr);
681 static int mxc_init_asrc(void)
683 /* Halt ASRC internal FP when input FIFO needs data for pair A, B, C */
684 asrc_regmap_write(asrc->regmap, REG_ASRCTR, ASRCTR_ASRCEN);
686 /* Disable interrupt by default */
687 asrc_regmap_write(asrc->regmap, REG_ASRIER, 0x0);
689 /* Default 2: 6: 2 channel assignment */
690 asrc_set_channel_number(ASRC_PAIR_A, 2);
691 asrc_set_channel_number(ASRC_PAIR_B, 6);
692 asrc_set_channel_number(ASRC_PAIR_C, 2);
694 /* Parameter Registers recommended settings */
695 asrc_regmap_write(asrc->regmap, REG_ASRPM1, 0x7fffff);
696 asrc_regmap_write(asrc->regmap, REG_ASRPM2, 0x255555);
697 asrc_regmap_write(asrc->regmap, REG_ASRPM3, 0xff7280);
698 asrc_regmap_write(asrc->regmap, REG_ASRPM4, 0xff7280);
699 asrc_regmap_write(asrc->regmap, REG_ASRPM5, 0xff7280);
701 /* Base address for task queue FIFO. Set to 0x7C */
702 asrc_regmap_update_bits(asrc->regmap, REG_ASRTFR1,
703 ASRTFR1_TF_BASE_MASK, ASRTFR1_TF_BASE(0xfc));
705 /* Set the processing clock for 76KHz, 133M */
706 asrc_regmap_write(asrc->regmap, REG_ASR76K, 0x06D6);
708 /* Set the processing clock for 56KHz, 133M */
709 asrc_regmap_write(asrc->regmap, REG_ASR56K, 0x0947);
714 #define ASRC_xPUT_DMA_CALLBACK(in) \
715 ((in) ? asrc_input_dma_callback : asrc_output_dma_callback)
717 static void asrc_input_dma_callback(void *data)
719 struct asrc_pair_params *params = (struct asrc_pair_params *)data;
720 unsigned long lock_flags;
722 dma_unmap_sg(NULL, params->input_sg, params->input_sg_nodes,
725 spin_lock_irqsave(&input_int_lock, lock_flags);
727 params->input_counter++;
728 wake_up_interruptible(¶ms->input_wait_queue);
730 spin_unlock_irqrestore(&input_int_lock, lock_flags);
732 schedule_work(¶ms->task_output_work);
737 static void asrc_output_dma_callback(void *data)
739 struct asrc_pair_params *params = (struct asrc_pair_params *)data;
741 dma_unmap_sg(NULL, params->output_sg, params->output_sg_nodes,
745 static unsigned int asrc_get_output_FIFO_size(enum asrc_pair_index index)
749 asrc_regmap_read(asrc->regmap, REG_ASRFST(index), &val);
751 val &= ASRFSTx_OUTPUT_FIFO_MASK;
753 return val >> ASRFSTx_OUTPUT_FIFO_SHIFT;
756 static unsigned int asrc_get_input_FIFO_size(enum asrc_pair_index index)
760 asrc_regmap_read(asrc->regmap, REG_ASRFST(index), &val);
762 val &= ASRFSTx_INPUT_FIFO_MASK;
764 return val >> ASRFSTx_INPUT_FIFO_SHIFT;
767 static u32 asrc_read_one_from_output_FIFO(enum asrc_pair_index index)
771 asrc_regmap_read(asrc->regmap, REG_ASRDO(index), &val);
776 static void asrc_write_one_to_output_FIFO(enum asrc_pair_index index, u32 val)
778 asrc_regmap_write(asrc->regmap, REG_ASRDI(index), val);
781 static void asrc_read_output_FIFO(struct asrc_pair_params *params)
783 u32 *reg24 = params->output_last_period.dma_vaddr;
784 u16 *reg16 = params->output_last_period.dma_vaddr;
785 enum asrc_pair_index index = params->index;
786 u32 d, i, j, reg, size, t_size;
789 if (params->output_word_width == ASRC_WIDTH_24_BIT)
792 /* Delay for last period data output */
793 d = 1000000 / params->output_sample_rate * params->last_period_sample;
798 size = asrc_get_output_FIFO_size(index);
799 for (i = 0; i < size; i++) {
800 for (j = 0; j < params->channel_nums; j++) {
801 reg = asrc_read_one_from_output_FIFO(index);
814 if (t_size > params->last_period_sample)
815 t_size = params->last_period_sample;
817 params->output_last_period.length = t_size * params->channel_nums * 2;
819 params->output_last_period.length *= 2;
822 static void asrc_output_task_worker(struct work_struct *w)
824 struct asrc_pair_params *params =
825 container_of(w, struct asrc_pair_params, task_output_work);
826 unsigned long lock_flags;
828 if (!params->pair_hold)
831 spin_lock_irqsave(&pair_lock, lock_flags);
832 asrc_read_output_FIFO(params);
833 spin_unlock_irqrestore(&pair_lock, lock_flags);
835 /* Finish receiving all output data */
836 spin_lock_irqsave(&output_int_lock, lock_flags);
838 params->output_counter++;
839 wake_up_interruptible(¶ms->output_wait_queue);
841 spin_unlock_irqrestore(&output_int_lock, lock_flags);
844 static void mxc_free_dma_buf(struct asrc_pair_params *params)
846 if (params->input_dma_total.dma_vaddr != NULL) {
847 kfree(params->input_dma_total.dma_vaddr);
848 params->input_dma_total.dma_vaddr = NULL;
851 if (params->output_dma_total.dma_vaddr != NULL) {
852 kfree(params->output_dma_total.dma_vaddr);
853 params->output_dma_total.dma_vaddr = NULL;
856 if (params->output_last_period.dma_vaddr) {
857 dma_free_coherent(asrc->dev, 1024 * params->last_period_sample,
858 params->output_last_period.dma_vaddr,
859 params->output_last_period.dma_paddr);
860 params->output_last_period.dma_vaddr = NULL;
866 static int mxc_allocate_dma_buf(struct asrc_pair_params *params)
868 struct dma_block *input_a, *output_a, *last_period;
870 input_a = ¶ms->input_dma_total;
871 output_a = ¶ms->output_dma_total;
872 last_period = ¶ms->output_last_period;
874 input_a->dma_vaddr = kzalloc(input_a->length, GFP_KERNEL);
875 if (!input_a->dma_vaddr) {
876 dev_err(asrc->dev, "failed to allocate input dma buffer!\n");
879 input_a->dma_paddr = virt_to_dma(NULL, input_a->dma_vaddr);
881 output_a->dma_vaddr = kzalloc(output_a->length, GFP_KERNEL);
882 if (!output_a->dma_vaddr) {
883 dev_err(asrc->dev, "failed to allocate output dma buffer!\n");
886 output_a->dma_paddr = virt_to_dma(NULL, output_a->dma_vaddr);
888 last_period->dma_vaddr = dma_alloc_coherent(NULL,
889 1024 * params->last_period_sample,
890 &last_period->dma_paddr, GFP_KERNEL);
895 mxc_free_dma_buf(params);
896 dev_err(asrc->dev, "failed to allocate buffer.\n");
901 static struct dma_chan *imx_asrc_dma_request_channel(
902 struct asrc_pair_params *params, bool in)
906 sprintf(name, "%cx%c", in ? 'r' : 't', params->index + 'a');
908 return dma_request_slave_channel(asrc->dev, name);
911 static int imx_asrc_dma_config(struct asrc_pair_params *params,
912 struct dma_chan *chan, u32 dma_addr, void *buf_addr,
913 u32 buf_len, bool in, enum asrc_word_width word_width)
915 struct dma_async_tx_descriptor *desc;
916 struct dma_slave_config slave_config;
917 enum dma_slave_buswidth buswidth;
918 struct scatterlist *sg;
919 unsigned int sg_nent, i;
923 sg = params->input_sg;
924 sg_nent = params->input_sg_nodes;
925 desc = params->desc_in;
927 sg = params->output_sg;
928 sg_nent = params->output_sg_nodes;
929 desc = params->desc_out;
932 switch (word_width) {
933 case ASRC_WIDTH_16_BIT:
934 buswidth = DMA_SLAVE_BUSWIDTH_2_BYTES;
936 case ASRC_WIDTH_24_BIT:
937 buswidth = DMA_SLAVE_BUSWIDTH_4_BYTES;
940 dev_err(asrc->dev, "Error word_width.\n");
945 slave_config.direction = DMA_MEM_TO_DEV;
946 slave_config.dst_addr = dma_addr;
947 slave_config.dst_addr_width = buswidth;
948 slave_config.dst_maxburst =
949 params->input_wm * params->channel_nums / buswidth;
951 slave_config.direction = DMA_DEV_TO_MEM;
952 slave_config.src_addr = dma_addr;
953 slave_config.src_addr_width = buswidth;
954 slave_config.src_maxburst =
955 params->output_wm * params->channel_nums / buswidth;
957 ret = dmaengine_slave_config(chan, &slave_config);
959 dev_err(asrc->dev, "imx_asrc_dma_config(%d) failed: %d\r\n", in, ret);
963 sg_init_table(sg, sg_nent);
966 sg_init_one(sg, buf_addr, buf_len);
971 for (i = 0; i < (sg_nent - 1); i++)
972 sg_set_buf(&sg[i], buf_addr + i * ASRC_MAX_BUFFER_SIZE,
973 ASRC_MAX_BUFFER_SIZE);
975 sg_set_buf(&sg[i], buf_addr + i * ASRC_MAX_BUFFER_SIZE,
976 buf_len - ASRC_MAX_BUFFER_SIZE * i);
979 dev_err(asrc->dev, "Error Input DMA nodes number[%d]!\n", sg_nent);
983 ret = dma_map_sg(NULL, sg, sg_nent, slave_config.direction);
984 if (ret != sg_nent) {
985 dev_err(asrc->dev, "DMA mapping error!\n");
989 desc = chan->device->device_prep_slave_sg(chan, sg, sg_nent,
990 slave_config.direction, 1, NULL);
993 params->desc_in = desc;
994 params->desc_in->callback = asrc_input_dma_callback;
996 params->desc_out = desc;
997 params->desc_out->callback = asrc_output_dma_callback;
1001 desc->callback = ASRC_xPUT_DMA_CALLBACK(in);
1002 desc->callback_param = params;
1010 static int mxc_asrc_prepare_io_buffer(struct asrc_pair_params *params,
1011 struct asrc_convert_buffer *pbuf, bool in)
1013 struct dma_chan *dma_channel;
1014 enum asrc_word_width width;
1015 unsigned int *dma_len, *sg_nodes, buf_len, wm;
1016 void __user *buf_vaddr;
1018 u32 word_size, fifo_addr;
1021 dma_channel = params->input_dma_channel;
1022 dma_vaddr = params->input_dma_total.dma_vaddr;
1023 dma_len = ¶ms->input_dma_total.length;
1024 width = params->input_word_width;
1025 sg_nodes = ¶ms->input_sg_nodes;
1026 wm = params->input_wm;
1027 buf_vaddr = (void __user *)pbuf->input_buffer_vaddr;
1028 buf_len = pbuf->input_buffer_length;
1030 dma_channel = params->output_dma_channel;
1031 dma_vaddr = params->output_dma_total.dma_vaddr;
1032 dma_len = ¶ms->output_dma_total.length;
1033 width = params->output_word_width;
1034 sg_nodes = ¶ms->output_sg_nodes;
1035 wm = params->last_period_sample;
1036 buf_vaddr = (void __user *)pbuf->output_buffer_vaddr;
1037 buf_len = pbuf->output_buffer_length;
1041 case ASRC_WIDTH_24_BIT:
1044 case ASRC_WIDTH_16_BIT:
1045 case ASRC_WIDTH_8_BIT:
1049 dev_err(asrc->dev, "error %s word size!\n", in ? "input" : "output");
1053 if (buf_len < word_size * params->channel_nums * wm) {
1054 dev_err(asrc->dev, "%s buffer size[%d] is too small!\n",
1055 in ? "input" : "output", buf_len);
1059 /* Copy origin data into input buffer */
1060 if (in && copy_from_user(dma_vaddr, buf_vaddr, buf_len))
1065 *dma_len -= wm * word_size * params->channel_nums;
1067 *sg_nodes = *dma_len / ASRC_MAX_BUFFER_SIZE + 1;
1069 fifo_addr = asrc_get_per_addr(params->index, in);
1071 return imx_asrc_dma_config(params, dma_channel, fifo_addr, dma_vaddr,
1072 *dma_len, in, width);
1075 static int mxc_asrc_prepare_buffer(struct asrc_pair_params *params,
1076 struct asrc_convert_buffer *pbuf)
1080 ret = mxc_asrc_prepare_io_buffer(params, pbuf, true);
1082 dev_err(asrc->dev, "failed to prepare input buffer: %d\n", ret);
1086 ret = mxc_asrc_prepare_io_buffer(params, pbuf, false);
1088 dev_err(asrc->dev, "failed to prepare output buffer: %d\n", ret);
1095 int mxc_asrc_process_io_buffer(struct asrc_pair_params *params,
1096 struct asrc_convert_buffer *pbuf, bool in)
1098 void *last_vaddr = params->output_last_period.dma_vaddr;
1099 unsigned int *last_len = ¶ms->output_last_period.length;
1100 unsigned int *counter, dma_len, *buf_len;
1101 unsigned long lock_flags;
1102 void __user *buf_vaddr;
1104 wait_queue_head_t *q;
1108 dma_vaddr = params->input_dma_total.dma_vaddr;
1109 dma_len = params->input_dma_total.length;
1110 q = ¶ms->input_wait_queue;
1111 counter = ¶ms->input_counter;
1112 buf_len = &pbuf->input_buffer_length;
1113 lock = &input_int_lock;
1114 buf_vaddr = (void __user *)pbuf->input_buffer_vaddr;
1116 dma_vaddr = params->output_dma_total.dma_vaddr;
1117 dma_len = params->output_dma_total.length;
1118 q = ¶ms->output_wait_queue;
1119 counter = ¶ms->output_counter;
1120 buf_len = &pbuf->output_buffer_length;
1121 lock = &output_int_lock;
1122 buf_vaddr = (void __user *)pbuf->output_buffer_vaddr;
1125 if (!wait_event_interruptible_timeout(*q, *counter != 0, 10 * HZ)) {
1126 dev_err(asrc->dev, "ASRC_DQ_OUTBUF timeout counter %x\n", *counter);
1128 } else if (signal_pending(current)) {
1129 dev_err(asrc->dev, "ASRC_DQ_INBUF interrupt received.\n");
1130 return -ERESTARTSYS;
1133 spin_lock_irqsave(lock, lock_flags);
1135 spin_unlock_irqrestore(lock, lock_flags);
1139 /* Only output need return data to user space */
1141 if (copy_to_user(buf_vaddr, dma_vaddr, dma_len))
1144 *buf_len += *last_len;
1146 if (copy_to_user(buf_vaddr + dma_len, last_vaddr, *last_len))
1153 int mxc_asrc_process_buffer(struct asrc_pair_params *params,
1154 struct asrc_convert_buffer *pbuf)
1158 ret = mxc_asrc_process_io_buffer(params, pbuf, true);
1160 dev_err(asrc->dev, "failed to process input buffer: %d\n", ret);
1164 ret = mxc_asrc_process_io_buffer(params, pbuf, false);
1166 dev_err(asrc->dev, "failed to process output buffer: %d\n", ret);
1173 static void mxc_asrc_submit_dma(struct asrc_pair_params *params)
1175 enum asrc_pair_index index = params->index;
1176 u32 size = asrc_get_output_FIFO_size(params->index);
1179 /* Read all data in OUTPUT FIFO */
1181 for (j = 0; j < size; j++)
1182 for (i = 0; i < params->channel_nums; i++)
1183 asrc_read_one_from_output_FIFO(index);
1185 * delay before size-getting should be:
1186 * 1s / output_sample_rate * last_period_sample
1187 * but we don't know last time's output_sample_rate and
1188 * last_period_sample, and in order to cover max case
1189 * so use min(sample_rate)=32kHz and max(last_period_sample)=32
1190 * Thus 1s / 32k * 32 = 1ms
1194 size = asrc_get_output_FIFO_size(index);
1197 /* Fill the input FIFO until reach the stall level */
1198 size = asrc_get_input_FIFO_size(index);
1200 for (i = 0; i < params->channel_nums; i++)
1201 asrc_write_one_to_output_FIFO(index, 0);
1202 size = asrc_get_input_FIFO_size(index);
1205 /* Submit dma request */
1206 dmaengine_submit(params->desc_in);
1207 dma_async_issue_pending(params->desc_in->chan);
1209 dmaengine_submit(params->desc_out);
1210 dma_async_issue_pending(params->desc_out->chan);
1212 sdma_set_event_pending(params->input_dma_channel);
1215 static long asrc_ioctl_req_pair(struct asrc_pair_params *params,
1218 struct asrc_req req;
1221 ret = copy_from_user(&req, user, sizeof(req));
1223 dev_err(asrc->dev, "failed to get req from user space: %ld\n", ret);
1227 ret = asrc_req_pair(req.chn_num, &req.index);
1229 dev_err(asrc->dev, "failed to request pair: %ld\n", ret);
1233 params->pair_hold = 1;
1234 params->index = req.index;
1235 params->channel_nums = req.chn_num;
1237 ret = copy_to_user(user, &req, sizeof(req));
1239 dev_err(asrc->dev, "failed to send req to user space: %ld\n", ret);
1246 static long asrc_ioctl_config_pair(struct asrc_pair_params *params,
1249 struct asrc_config config;
1250 enum asrc_pair_index index;
1253 ret = copy_from_user(&config, user, sizeof(config));
1255 dev_err(asrc->dev, "failed to get config from user space: %ld\n", ret);
1259 ret = asrc_config_pair(&config);
1261 dev_err(asrc->dev, "failed to config pair: %ld\n", ret);
1265 index = config.pair;
1267 params->input_wm = 4;
1268 params->output_wm = 2;
1270 ret = asrc_set_watermark(index, params->input_wm, params->output_wm);
1274 params->output_buffer_size = config.dma_buffer_size;
1275 params->input_buffer_size = config.dma_buffer_size;
1276 if (config.buffer_num > ASRC_DMA_BUFFER_NUM)
1277 params->buffer_num = ASRC_DMA_BUFFER_NUM;
1279 params->buffer_num = config.buffer_num;
1281 params->input_dma_total.length = ASRC_DMA_BUFFER_SIZE;
1282 params->output_dma_total.length = ASRC_DMA_BUFFER_SIZE;
1284 params->input_word_width = config.input_word_width;
1285 params->output_word_width = config.output_word_width;
1287 params->input_sample_rate = config.input_sample_rate;
1288 params->output_sample_rate = config.output_sample_rate;
1290 params->last_period_sample = ASRC_OUTPUT_LAST_SAMPLE_DEFAULT;
1292 /* Expand last period buffer if output_sample_rate is much bigger */
1293 if (params->output_sample_rate / params->input_sample_rate > 2)
1294 params->last_period_sample *= 5;
1295 else if (params->output_sample_rate / params->input_sample_rate > 1)
1296 params->last_period_sample *= 3;
1298 ret = mxc_allocate_dma_buf(params);
1300 dev_err(asrc->dev, "failed to allocate dma buffer: %ld\n", ret);
1304 /* Request DMA channel for both input and output */
1305 params->input_dma_channel =
1306 imx_asrc_dma_request_channel(params, true);
1307 if (params->input_dma_channel == NULL) {
1308 dev_err(asrc->dev, "failed to request rx channel for Pair %c\n",
1313 params->output_dma_channel =
1314 imx_asrc_dma_request_channel(params, false);
1315 if (params->output_dma_channel == NULL) {
1316 dev_err(asrc->dev, "failed to request tx channel for Pair %c\n",
1321 init_waitqueue_head(¶ms->input_wait_queue);
1322 init_waitqueue_head(¶ms->output_wait_queue);
1324 /* Add work struct to receive last period of output data */
1325 INIT_WORK(¶ms->task_output_work, asrc_output_task_worker);
1327 ret = copy_to_user(user, &config, sizeof(config));
1329 dev_err(asrc->dev, "failed to send config to user space: %ld\n", ret);
1336 static long asrc_ioctl_release_pair(struct asrc_pair_params *params,
1339 enum asrc_pair_index index;
1340 unsigned long lock_flags;
1343 ret = copy_from_user(&index, user, sizeof(index));
1345 dev_err(asrc->dev, "failed to get index from user space: %ld\n", ret);
1349 /* index might be not valid due to some application failure. */
1353 params->asrc_active = 0;
1355 spin_lock_irqsave(&pair_lock, lock_flags);
1356 params->pair_hold = 0;
1357 spin_unlock_irqrestore(&pair_lock, lock_flags);
1359 if (params->input_dma_channel)
1360 dma_release_channel(params->input_dma_channel);
1361 if (params->output_dma_channel)
1362 dma_release_channel(params->output_dma_channel);
1363 mxc_free_dma_buf(params);
1364 asrc_release_pair(index);
1365 asrc_finish_conv(index);
1370 static long asrc_ioctl_convert(struct asrc_pair_params *params,
1373 struct asrc_convert_buffer buf;
1376 ret = copy_from_user(&buf, user, sizeof(buf));
1378 dev_err(asrc->dev, "failed to get buf from user space: %ld\n", ret);
1382 ret = mxc_asrc_prepare_buffer(params, &buf);
1384 dev_err(asrc->dev, "failed to prepare buffer: %ld\n", ret);
1388 mxc_asrc_submit_dma(params);
1390 ret = mxc_asrc_process_buffer(params, &buf);
1392 dev_err(asrc->dev, "failed to process buffer: %ld\n", ret);
1396 ret = copy_to_user(user, &buf, sizeof(buf));
1398 dev_err(asrc->dev, "failed to send buf to user space: %ld\n", ret);
1405 static long asrc_ioctl_start_conv(struct asrc_pair_params *params,
1408 enum asrc_pair_index index;
1411 ret = copy_from_user(&index, user, sizeof(index));
1413 dev_err(asrc->dev, "failed to get index from user space: %ld\n", ret);
1417 params->asrc_active = 1;
1418 asrc_start_conv(index);
1423 static long asrc_ioctl_stop_conv(struct asrc_pair_params *params,
1426 enum asrc_pair_index index;
1429 ret = copy_from_user(&index, user, sizeof(index));
1431 dev_err(asrc->dev, "failed to get index from user space: %ld\n", ret);
1435 dmaengine_terminate_all(params->input_dma_channel);
1436 dmaengine_terminate_all(params->output_dma_channel);
1438 asrc_stop_conv(index);
1439 params->asrc_active = 0;
1444 static long asrc_ioctl_status(struct asrc_pair_params *params,
1447 struct asrc_status_flags flags;
1450 ret = copy_from_user(&flags, user, sizeof(flags));
1452 dev_err(asrc->dev, "failed to get flags from user space: %ld\n", ret);
1456 asrc_get_status(&flags);
1458 ret = copy_to_user(user, &flags, sizeof(flags));
1460 dev_err(asrc->dev, "failed to send flags to user space: %ld\n", ret);
1467 static long asrc_ioctl_flush(struct asrc_pair_params *params,
1470 enum asrc_pair_index index = params->index;
1471 unsigned long lock_flags;
1473 /* Flush input dma buffer */
1474 spin_lock_irqsave(&input_int_lock, lock_flags);
1475 params->input_counter = 0;
1476 spin_unlock_irqrestore(&input_int_lock, lock_flags);
1478 /* Flush output dma buffer */
1479 spin_lock_irqsave(&output_int_lock, lock_flags);
1480 params->output_counter = 0;
1481 spin_unlock_irqrestore(&output_int_lock, lock_flags);
1483 /* Release DMA and request again */
1484 dma_release_channel(params->input_dma_channel);
1485 dma_release_channel(params->output_dma_channel);
1487 params->input_dma_channel = imx_asrc_dma_request_channel(params, true);
1488 if (params->input_dma_channel == NULL) {
1489 dev_err(asrc->dev, "failed to request rx channel for Pair %c\n",
1494 params->output_dma_channel =
1495 imx_asrc_dma_request_channel(params, false);
1496 if (params->output_dma_channel == NULL) {
1497 dev_err(asrc->dev, "failed to request tx channel for Pair %c\n",
1505 static long asrc_ioctl(struct file *file, unsigned int cmd, unsigned long arg)
1507 struct asrc_pair_params *params = file->private_data;
1508 void __user *user = (void __user *)arg;
1513 ret = asrc_ioctl_req_pair(params, user);
1515 case ASRC_CONFIG_PAIR:
1516 ret = asrc_ioctl_config_pair(params, user);
1518 case ASRC_RELEASE_PAIR:
1519 ret = asrc_ioctl_release_pair(params, user);
1522 ret = asrc_ioctl_convert(params, user);
1524 case ASRC_START_CONV:
1525 ret = asrc_ioctl_start_conv(params, user);
1528 case ASRC_STOP_CONV:
1529 ret = asrc_ioctl_stop_conv(params, user);
1532 ret = asrc_ioctl_status(params, user);
1535 ret = asrc_ioctl_flush(params, user);
1538 dev_err(asrc->dev, "Unsupported ioctl cmd!\n");
1545 static int mxc_asrc_open(struct inode *inode, struct file *file)
1547 struct asrc_pair_params *pair_params;
1550 ret = signal_pending(current);
1552 dev_err(asrc->dev, "Current process has a signal pending.\n");
1556 pair_params = kzalloc(sizeof(struct asrc_pair_params), GFP_KERNEL);
1557 if (pair_params == NULL) {
1558 dev_err(asrc->dev, "failed to allocate pair_params.\n");
1562 file->private_data = pair_params;
1567 static int mxc_asrc_close(struct inode *inode, struct file *file)
1569 struct asrc_pair_params *pair_params;
1570 unsigned long lock_flags;
1572 pair_params = file->private_data;
1577 if (pair_params->asrc_active) {
1578 pair_params->asrc_active = 0;
1580 dmaengine_terminate_all(pair_params->input_dma_channel);
1581 dmaengine_terminate_all(pair_params->output_dma_channel);
1583 asrc_stop_conv(pair_params->index);
1585 wake_up_interruptible(&pair_params->input_wait_queue);
1586 wake_up_interruptible(&pair_params->output_wait_queue);
1588 if (pair_params->pair_hold) {
1589 spin_lock_irqsave(&pair_lock, lock_flags);
1590 pair_params->pair_hold = 0;
1591 spin_unlock_irqrestore(&pair_lock, lock_flags);
1593 if (pair_params->input_dma_channel)
1594 dma_release_channel(pair_params->input_dma_channel);
1595 if (pair_params->output_dma_channel)
1596 dma_release_channel(pair_params->output_dma_channel);
1598 mxc_free_dma_buf(pair_params);
1600 asrc_release_pair(pair_params->index);
1601 asrc_finish_conv(pair_params->index);
1605 file->private_data = NULL;
1610 static int mxc_asrc_mmap(struct file *file, struct vm_area_struct *vma)
1612 unsigned long size = vma->vm_end - vma->vm_start;
1615 vma->vm_page_prot = pgprot_writecombine(vma->vm_page_prot);
1617 ret = remap_pfn_range(vma, vma->vm_start, vma->vm_pgoff,
1618 size, vma->vm_page_prot);
1620 dev_err(asrc->dev, "failed to memory map!\n");
1624 vma->vm_flags &= ~VM_IO;
1629 static const struct file_operations asrc_fops = {
1630 .owner = THIS_MODULE,
1631 .unlocked_ioctl = asrc_ioctl,
1632 .mmap = mxc_asrc_mmap,
1633 .open = mxc_asrc_open,
1634 .release = mxc_asrc_close,
1637 static struct miscdevice asrc_miscdev = {
1640 .minor = MISC_DYNAMIC_MINOR,
1643 static int asrc_read_proc_attr(struct file *file, char __user *buf,
1644 size_t count, loff_t *off)
1653 asrc_regmap_read(asrc->regmap, REG_ASRCNCR, ®);
1655 len += sprintf(tmpbuf, "ANCA: %d\nANCB: %d\nANCC: %d\n",
1656 (int)ASRCNCR_ANCA_get(reg, asrc->channel_bits),
1657 (int)ASRCNCR_ANCB_get(reg, asrc->channel_bits),
1658 (int)ASRCNCR_ANCC_get(reg, asrc->channel_bits));
1663 if (copy_to_user(buf, &tmpbuf, len))
1671 #define ASRC_MAX_PROC_BUFFER_SIZE 63
1673 static int asrc_write_proc_attr(struct file *file, const char __user *buffer,
1674 size_t count, loff_t *data)
1676 char buf[ASRC_MAX_PROC_BUFFER_SIZE];
1680 if (count > ASRC_MAX_PROC_BUFFER_SIZE) {
1681 dev_err(asrc->dev, "Attr proc write: The input string was too long.\n");
1685 if (copy_from_user(buf, buffer, count)) {
1686 dev_err(asrc->dev, "Attr proc write: Failed to copy buffer from user.\n");
1690 sscanf(buf, "ANCA: %d\nANCB: %d\nANCC: %d", &na, &nb, &nc);
1692 total = asrc->channel_bits > 3 ? 10 : 5;
1694 if (na + nb + nc > total) {
1695 dev_err(asrc->dev, "Don't surpass %d for total.\n", total);
1697 } else if (na % 2 != 0 || nb % 2 != 0 || nc % 2 != 0) {
1698 dev_err(asrc->dev, "Please set an even number for each pair.\n");
1700 } else if (na < 0 || nb < 0 || nc < 0) {
1701 dev_err(asrc->dev, "Please set an positive number for each pair.\n");
1706 asrc->asrc_pair[ASRC_PAIR_A].chn_max = na;
1707 asrc->asrc_pair[ASRC_PAIR_B].chn_max = nb;
1708 asrc->asrc_pair[ASRC_PAIR_C].chn_max = nc;
1710 asrc_set_channel_number(ASRC_PAIR_A, na);
1711 asrc_set_channel_number(ASRC_PAIR_B, nb);
1712 asrc_set_channel_number(ASRC_PAIR_C, nc);
1717 static const struct file_operations asrc_proc_fops = {
1718 .read = asrc_read_proc_attr,
1719 .write = asrc_write_proc_attr,
1722 static void asrc_proc_create(void)
1724 struct proc_dir_entry *proc_attr;
1726 asrc->proc_asrc = proc_mkdir(ASRC_PROC_PATH, NULL);
1727 if (!asrc->proc_asrc) {
1728 dev_err(asrc->dev, "failed to create proc entry %s\n", ASRC_PROC_PATH);
1732 proc_attr = proc_create("ChSettings", S_IFREG | S_IRUGO | S_IWUSR,
1733 asrc->proc_asrc, &asrc_proc_fops);
1735 remove_proc_entry(ASRC_PROC_PATH, NULL);
1736 dev_err(asrc->dev, "failed to create proc attribute entry.\n");
1740 static void asrc_proc_remove(void)
1742 remove_proc_entry("ChSettings", asrc->proc_asrc);
1743 remove_proc_entry(ASRC_PROC_PATH, NULL);
1747 #ifdef ASRC_USE_REGMAP
1748 /* ============= ASRC REGMAP ============= */
1750 static bool asrc_readable_reg(struct device *dev, unsigned int reg)
1794 static bool asrc_writeable_reg(struct device *dev, unsigned int reg)
1834 static bool asrc_volatile_reg(struct device *dev, unsigned int reg)
1836 /* Sync all registers after reset */
1840 static const struct regmap_config asrc_regmap_config = {
1845 .max_register = REG_ASRMCR1C,
1846 .readable_reg = asrc_readable_reg,
1847 .writeable_reg = asrc_writeable_reg,
1848 .volatile_reg = asrc_volatile_reg,
1849 .cache_type = REGCACHE_RBTREE,
1853 static int mxc_asrc_probe(struct platform_device *pdev)
1855 struct device_node *np = pdev->dev.of_node;
1856 struct resource res;
1860 /* Check if the device is existed */
1861 if (!of_device_is_available(np)) {
1862 dev_err(&pdev->dev, "improper devicetree status.\n");
1866 asrc = devm_kzalloc(&pdev->dev, sizeof(struct asrc_data), GFP_KERNEL);
1868 dev_err(&pdev->dev, "failed to allocate asrc.\n");
1872 asrc->dev = &pdev->dev;
1873 asrc->dev->coherent_dma_mask = DMA_BIT_MASK(32);
1875 asrc->asrc_pair[ASRC_PAIR_A].chn_max = 2;
1876 asrc->asrc_pair[ASRC_PAIR_B].chn_max = 6;
1877 asrc->asrc_pair[ASRC_PAIR_C].chn_max = 2;
1878 asrc->asrc_pair[ASRC_PAIR_A].overload_error = 0;
1879 asrc->asrc_pair[ASRC_PAIR_B].overload_error = 0;
1880 asrc->asrc_pair[ASRC_PAIR_C].overload_error = 0;
1882 /* Map the address */
1883 ret = of_address_to_resource(np, 0, &res);
1885 dev_err(&pdev->dev, "failed to map address: %d\n", ret);
1888 asrc->paddr = res.start;
1890 regs = of_iomap(np, 0);
1892 dev_err(&pdev->dev, "failed to map io resources.\n");
1893 return IS_ERR(regs);
1895 asrc->vaddr = (unsigned long)regs;
1897 #ifdef ASRC_USE_REGMAP
1898 asrc->regmap = devm_regmap_init_mmio_clk(&pdev->dev,
1899 "core", regs, &asrc_regmap_config);
1900 if (IS_ERR(asrc->regmap)) {
1901 dev_err(&pdev->dev, "regmap init failed\n");
1902 ret = PTR_ERR(asrc->regmap);
1905 regcache_cache_only(asrc->regmap, false);
1908 asrc->irq = irq_of_parse_and_map(np, 0);
1909 if (asrc->irq == NO_IRQ) {
1910 dev_err(&pdev->dev, "no irq for node %s\n", np->full_name);
1914 ret = devm_request_irq(&pdev->dev, asrc->irq,
1915 asrc_isr, 0, "asrc", NULL);
1917 dev_err(&pdev->dev, "failed to request IRQ: %d\n", ret);
1921 asrc->asrc_clk = devm_clk_get(&pdev->dev, NULL);
1922 if (IS_ERR(asrc->asrc_clk)) {
1923 ret = PTR_ERR(asrc->asrc_clk);
1926 #ifndef ASRC_USE_REGMAP
1927 clk_prepare_enable(asrc->asrc_clk);
1930 ret = of_property_read_u32_array(pdev->dev.of_node,
1931 "fsl,clk-channel-bits", &asrc->channel_bits, 1);
1933 dev_err(&pdev->dev, "failed to get clk-channel-bits.\n");
1937 ret = of_property_read_u32_array(pdev->dev.of_node,
1938 "fsl,clk-map-version", &asrc->clk_map_ver, 1);
1940 dev_err(&pdev->dev, "failed to get clk-map-version.\n");
1944 switch (asrc->clk_map_ver) {
1946 input_clk_map = input_clk_map_v1;
1947 output_clk_map = output_clk_map_v1;
1951 input_clk_map = input_clk_map_v2;
1952 output_clk_map = output_clk_map_v2;
1956 ret = misc_register(&asrc_miscdev);
1958 dev_err(&pdev->dev, "failed to register char device %d\n", ret);
1964 ret = mxc_init_asrc();
1968 dev_info(&pdev->dev, "mxc_asrc registered.\n");
1973 misc_deregister(&asrc_miscdev);
1977 dev_err(&pdev->dev, "mxc_asrc register failed: err %d\n", ret);
1982 static int mxc_asrc_remove(struct platform_device *pdev)
1985 misc_deregister(&asrc_miscdev);
1990 static const struct of_device_id fsl_asrc_ids[] = {
1991 { .compatible = "fsl,imx6q-asrc", },
1995 static struct platform_driver mxc_asrc_driver = {
1998 .of_match_table = fsl_asrc_ids,
2000 .probe = mxc_asrc_probe,
2001 .remove = mxc_asrc_remove,
2004 module_platform_driver(mxc_asrc_driver);
2006 MODULE_AUTHOR("Freescale Semiconductor, Inc.");
2007 MODULE_DESCRIPTION("Asynchronous Sample Rate Converter");
2008 MODULE_LICENSE("GPL");