drivers/net/bnx2.c

   1 /* bnx2.c: Broadcom NX2 network driver.
   2  *
   3  * Copyright (c) 2004, 2005 Broadcom Corporation
   4  *
   5  * This program is free software; you can redistribute it and/or modify
   6  * it under the terms of the GNU General Public License as published by
   7  * the Free Software Foundation.
   8  *
   9  * Written by: Michael Chan  (mchan@broadcom.com)
  10  */
  11
  12 #include "bnx2.h"
  13 #include "bnx2_fw.h"
  14
  15 #define DRV_MODULE_NAME         "bnx2"
  16 #define PFX DRV_MODULE_NAME     ": "
  17 #define DRV_MODULE_VERSION      "1.2.19"
  18 #define DRV_MODULE_RELDATE      "May 23, 2005"
  19
  20 #define RUN_AT(x) (jiffies + (x))
  21
  22 /* Time in jiffies before concluding the transmitter is hung. */
  23 #define TX_TIMEOUT  (5*HZ)
  24
  25 static char version[] __devinitdata =
  26         "Broadcom NetXtreme II Gigabit Ethernet Driver " DRV_MODULE_NAME " v" DRV_MODULE_VERSION " (" DRV_MODULE_RELDATE ")\n";
  27
  28 MODULE_AUTHOR("Michael Chan <mchan@broadcom.com>");
  29 MODULE_DESCRIPTION("Broadcom NetXtreme II BCM5706 Driver");
  30 MODULE_LICENSE("GPL");
  31 MODULE_VERSION(DRV_MODULE_VERSION);
  32
  33 static int disable_msi = 0;
  34
  35 module_param(disable_msi, int, 0);
  36 MODULE_PARM_DESC(disable_msi, "Disable Message Signaled Interrupt (MSI)");
  37
  38 typedef enum {
  39         BCM5706 = 0,
  40         NC370T,
  41         NC370I,
  42         BCM5706S,
  43         NC370F,
  44 } board_t;
  45
  46 /* indexed by board_t, above */
  47 static struct {
  48         char *name;
  49 } board_info[] __devinitdata = {
  50         { "Broadcom NetXtreme II BCM5706 1000Base-T" },
  51         { "HP NC370T Multifunction Gigabit Server Adapter" },
  52         { "HP NC370i Multifunction Gigabit Server Adapter" },
  53         { "Broadcom NetXtreme II BCM5706 1000Base-SX" },
  54         { "HP NC370F Multifunction Gigabit Server Adapter" },
  55         };
  56
  57 static struct pci_device_id bnx2_pci_tbl[] = {
  58         { PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_NX2_5706,
  59           PCI_VENDOR_ID_HP, 0x3101, 0, 0, NC370T },
  60         { PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_NX2_5706,
  61           PCI_VENDOR_ID_HP, 0x3106, 0, 0, NC370I },
  62         { PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_NX2_5706,
  63           PCI_ANY_ID, PCI_ANY_ID, 0, 0, BCM5706 },
  64         { PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_NX2_5706S,
  65           PCI_VENDOR_ID_HP, 0x3102, 0, 0, NC370F },
  66         { PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_NX2_5706S,
  67           PCI_ANY_ID, PCI_ANY_ID, 0, 0, BCM5706S },
  68         { 0, }
  69 };
  70
  71 static struct flash_spec flash_table[] =
  72 {
  73         /* Slow EEPROM */
  74         {0x00000000, 0x40030380, 0x009f0081, 0xa184a053, 0xaf000400,
  75          1, SEEPROM_PAGE_BITS, SEEPROM_PAGE_SIZE,
  76          SEEPROM_BYTE_ADDR_MASK, SEEPROM_TOTAL_SIZE,
  77          "EEPROM - slow"},
  78         /* Fast EEPROM */
  79         {0x02000000, 0x62008380, 0x009f0081, 0xa184a053, 0xaf000400,
  80          1, SEEPROM_PAGE_BITS, SEEPROM_PAGE_SIZE,
  81          SEEPROM_BYTE_ADDR_MASK, SEEPROM_TOTAL_SIZE,
  82          "EEPROM - fast"},
  83         /* ATMEL AT45DB011B (buffered flash) */
  84         {0x02000003, 0x6e008173, 0x00570081, 0x68848353, 0xaf000400,
  85          1, BUFFERED_FLASH_PAGE_BITS, BUFFERED_FLASH_PAGE_SIZE,
  86          BUFFERED_FLASH_BYTE_ADDR_MASK, BUFFERED_FLASH_TOTAL_SIZE,
  87          "Buffered flash"},
  88         /* Saifun SA25F005 (non-buffered flash) */
  89         /* strap, cfg1, & write1 need updates */
  90         {0x01000003, 0x5f008081, 0x00050081, 0x03840253, 0xaf020406,
  91          0, SAIFUN_FLASH_PAGE_BITS, SAIFUN_FLASH_PAGE_SIZE,
  92          SAIFUN_FLASH_BYTE_ADDR_MASK, SAIFUN_FLASH_BASE_TOTAL_SIZE,
  93          "Non-buffered flash (64kB)"},
  94         /* Saifun SA25F010 (non-buffered flash) */
  95         /* strap, cfg1, & write1 need updates */
  96         {0x00000001, 0x47008081, 0x00050081, 0x03840253, 0xaf020406,
  97          0, SAIFUN_FLASH_PAGE_BITS, SAIFUN_FLASH_PAGE_SIZE,
  98          SAIFUN_FLASH_BYTE_ADDR_MASK, SAIFUN_FLASH_BASE_TOTAL_SIZE*2,
  99          "Non-buffered flash (128kB)"},
 100         /* Saifun SA25F020 (non-buffered flash) */
 101         /* strap, cfg1, & write1 need updates */
 102         {0x00000003, 0x4f008081, 0x00050081, 0x03840253, 0xaf020406,
 103          0, SAIFUN_FLASH_PAGE_BITS, SAIFUN_FLASH_PAGE_SIZE,
 104          SAIFUN_FLASH_BYTE_ADDR_MASK, SAIFUN_FLASH_BASE_TOTAL_SIZE*4,
 105          "Non-buffered flash (256kB)"},
 106 };
 107
 108 MODULE_DEVICE_TABLE(pci, bnx2_pci_tbl);
 109
 110 static inline u32 bnx2_tx_avail(struct bnx2 *bp)
 111 {
 112         u32 diff = TX_RING_IDX(bp->tx_prod) - TX_RING_IDX(bp->tx_cons);
 113
 114         if (diff > MAX_TX_DESC_CNT)
 115                 diff = (diff & MAX_TX_DESC_CNT) - 1;
 116         return (bp->tx_ring_size - diff);
 117 }
 118
 119 static u32
 120 bnx2_reg_rd_ind(struct bnx2 *bp, u32 offset)
 121 {
 122         REG_WR(bp, BNX2_PCICFG_REG_WINDOW_ADDRESS, offset);
 123         return (REG_RD(bp, BNX2_PCICFG_REG_WINDOW));
 124 }
 125
 126 static void
 127 bnx2_reg_wr_ind(struct bnx2 *bp, u32 offset, u32 val)
 128 {
 129         REG_WR(bp, BNX2_PCICFG_REG_WINDOW_ADDRESS, offset);
 130         REG_WR(bp, BNX2_PCICFG_REG_WINDOW, val);
 131 }
 132
 133 static void
 134 bnx2_ctx_wr(struct bnx2 *bp, u32 cid_addr, u32 offset, u32 val)
 135 {
 136         offset += cid_addr;
 137         REG_WR(bp, BNX2_CTX_DATA_ADR, offset);
 138         REG_WR(bp, BNX2_CTX_DATA, val);
 139 }
 140
 141 static int
 142 bnx2_read_phy(struct bnx2 *bp, u32 reg, u32 *val)
 143 {
 144         u32 val1;
 145         int i, ret;
 146
 147         if (bp->phy_flags & PHY_INT_MODE_AUTO_POLLING_FLAG) {
 148                 val1 = REG_RD(bp, BNX2_EMAC_MDIO_MODE);
 149                 val1 &= ~BNX2_EMAC_MDIO_MODE_AUTO_POLL;
 150
 151                 REG_WR(bp, BNX2_EMAC_MDIO_MODE, val1);
 152                 REG_RD(bp, BNX2_EMAC_MDIO_MODE);
 153
 154                 udelay(40);
 155         }
 156
 157         val1 = (bp->phy_addr << 21) | (reg << 16) |
 158                 BNX2_EMAC_MDIO_COMM_COMMAND_READ | BNX2_EMAC_MDIO_COMM_DISEXT |
 159                 BNX2_EMAC_MDIO_COMM_START_BUSY;
 160         REG_WR(bp, BNX2_EMAC_MDIO_COMM, val1);
 161
 162         for (i = 0; i < 50; i++) {
 163                 udelay(10);
 164
 165                 val1 = REG_RD(bp, BNX2_EMAC_MDIO_COMM);
 166                 if (!(val1 & BNX2_EMAC_MDIO_COMM_START_BUSY)) {
 167                         udelay(5);
 168
 169                         val1 = REG_RD(bp, BNX2_EMAC_MDIO_COMM);
 170                         val1 &= BNX2_EMAC_MDIO_COMM_DATA;
 171
 172                         break;
 173                 }
 174         }
 175
 176         if (val1 & BNX2_EMAC_MDIO_COMM_START_BUSY) {
 177                 *val = 0x0;
 178                 ret = -EBUSY;
 179         }
 180         else {
 181                 *val = val1;
 182                 ret = 0;
 183         }
 184
 185         if (bp->phy_flags & PHY_INT_MODE_AUTO_POLLING_FLAG) {
 186                 val1 = REG_RD(bp, BNX2_EMAC_MDIO_MODE);
 187                 val1 |= BNX2_EMAC_MDIO_MODE_AUTO_POLL;
 188
 189                 REG_WR(bp, BNX2_EMAC_MDIO_MODE, val1);
 190                 REG_RD(bp, BNX2_EMAC_MDIO_MODE);
 191
 192                 udelay(40);
 193         }
 194
 195         return ret;
 196 }
 197
 198 static int
 199 bnx2_write_phy(struct bnx2 *bp, u32 reg, u32 val)
 200 {
 201         u32 val1;
 202         int i, ret;
 203
 204         if (bp->phy_flags & PHY_INT_MODE_AUTO_POLLING_FLAG) {
 205                 val1 = REG_RD(bp, BNX2_EMAC_MDIO_MODE);
 206                 val1 &= ~BNX2_EMAC_MDIO_MODE_AUTO_POLL;
 207
 208                 REG_WR(bp, BNX2_EMAC_MDIO_MODE, val1);
 209                 REG_RD(bp, BNX2_EMAC_MDIO_MODE);
 210
 211                 udelay(40);
 212         }
 213
 214         val1 = (bp->phy_addr << 21) | (reg << 16) | val |
 215                 BNX2_EMAC_MDIO_COMM_COMMAND_WRITE |
 216                 BNX2_EMAC_MDIO_COMM_START_BUSY | BNX2_EMAC_MDIO_COMM_DISEXT;
 217         REG_WR(bp, BNX2_EMAC_MDIO_COMM, val1);
 218
 219         for (i = 0; i < 50; i++) {
 220                 udelay(10);
 221
 222                 val1 = REG_RD(bp, BNX2_EMAC_MDIO_COMM);
 223                 if (!(val1 & BNX2_EMAC_MDIO_COMM_START_BUSY)) {
 224                         udelay(5);
 225                         break;
 226                 }
 227         }
 228
 229         if (val1 & BNX2_EMAC_MDIO_COMM_START_BUSY)
 230                 ret = -EBUSY;
 231         else
 232                 ret = 0;
 233
 234         if (bp->phy_flags & PHY_INT_MODE_AUTO_POLLING_FLAG) {
 235                 val1 = REG_RD(bp, BNX2_EMAC_MDIO_MODE);
 236                 val1 |= BNX2_EMAC_MDIO_MODE_AUTO_POLL;
 237
 238                 REG_WR(bp, BNX2_EMAC_MDIO_MODE, val1);
 239                 REG_RD(bp, BNX2_EMAC_MDIO_MODE);
 240
 241                 udelay(40);
 242         }
 243
 244         return ret;
 245 }
 246
 247 static void
 248 bnx2_disable_int(struct bnx2 *bp)
 249 {
 250         REG_WR(bp, BNX2_PCICFG_INT_ACK_CMD,
 251                BNX2_PCICFG_INT_ACK_CMD_MASK_INT);
 252         REG_RD(bp, BNX2_PCICFG_INT_ACK_CMD);
 253 }
 254
 255 static void
 256 bnx2_enable_int(struct bnx2 *bp)
 257 {
 258         u32 val;
 259
 260         REG_WR(bp, BNX2_PCICFG_INT_ACK_CMD,
 261                BNX2_PCICFG_INT_ACK_CMD_INDEX_VALID | bp->last_status_idx);
 262
 263         val = REG_RD(bp, BNX2_HC_COMMAND);
 264         REG_WR(bp, BNX2_HC_COMMAND, val | BNX2_HC_COMMAND_COAL_NOW);
 265 }
 266
 267 static void
 268 bnx2_disable_int_sync(struct bnx2 *bp)
 269 {
 270         atomic_inc(&bp->intr_sem);
 271         bnx2_disable_int(bp);
 272         synchronize_irq(bp->pdev->irq);
 273 }
 274
 275 static void
 276 bnx2_netif_stop(struct bnx2 *bp)
 277 {
 278         bnx2_disable_int_sync(bp);
 279         if (netif_running(bp->dev)) {
 280                 netif_poll_disable(bp->dev);
 281                 netif_tx_disable(bp->dev);
 282                 bp->dev->trans_start = jiffies; /* prevent tx timeout */
 283         }
 284 }
 285
 286 static void
 287 bnx2_netif_start(struct bnx2 *bp)
 288 {
 289         if (atomic_dec_and_test(&bp->intr_sem)) {
 290                 if (netif_running(bp->dev)) {
 291                         netif_wake_queue(bp->dev);
 292                         netif_poll_enable(bp->dev);
 293                         bnx2_enable_int(bp);
 294                 }
 295         }
 296 }
 297
 298 static void
 299 bnx2_free_mem(struct bnx2 *bp)
 300 {
 301         if (bp->stats_blk) {
 302                 pci_free_consistent(bp->pdev, sizeof(struct statistics_block),
 303                                     bp->stats_blk, bp->stats_blk_mapping);
 304                 bp->stats_blk = NULL;
 305         }
 306         if (bp->status_blk) {
 307                 pci_free_consistent(bp->pdev, sizeof(struct status_block),
 308                                     bp->status_blk, bp->status_blk_mapping);
 309                 bp->status_blk = NULL;
 310         }
 311         if (bp->tx_desc_ring) {
 312                 pci_free_consistent(bp->pdev,
 313                                     sizeof(struct tx_bd) * TX_DESC_CNT,
 314                                     bp->tx_desc_ring, bp->tx_desc_mapping);
 315                 bp->tx_desc_ring = NULL;
 316         }
 317         if (bp->tx_buf_ring) {
 318                 kfree(bp->tx_buf_ring);
 319                 bp->tx_buf_ring = NULL;
 320         }
 321         if (bp->rx_desc_ring) {
 322                 pci_free_consistent(bp->pdev,
 323                                     sizeof(struct rx_bd) * RX_DESC_CNT,
 324                                     bp->rx_desc_ring, bp->rx_desc_mapping);
 325                 bp->rx_desc_ring = NULL;
 326         }
 327         if (bp->rx_buf_ring) {
 328                 kfree(bp->rx_buf_ring);
 329                 bp->rx_buf_ring = NULL;
 330         }
 331 }
 332
 333 static int
 334 bnx2_alloc_mem(struct bnx2 *bp)
 335 {
 336         bp->tx_buf_ring = kmalloc(sizeof(struct sw_bd) * TX_DESC_CNT,
 337                                      GFP_KERNEL);
 338         if (bp->tx_buf_ring == NULL)
 339                 return -ENOMEM;
 340
 341         memset(bp->tx_buf_ring, 0, sizeof(struct sw_bd) * TX_DESC_CNT);
 342         bp->tx_desc_ring = pci_alloc_consistent(bp->pdev,
 343                                                 sizeof(struct tx_bd) *
 344                                                 TX_DESC_CNT,
 345                                                 &bp->tx_desc_mapping);
 346         if (bp->tx_desc_ring == NULL)
 347                 goto alloc_mem_err;
 348
 349         bp->rx_buf_ring = kmalloc(sizeof(struct sw_bd) * RX_DESC_CNT,
 350                                      GFP_KERNEL);
 351         if (bp->rx_buf_ring == NULL)
 352                 goto alloc_mem_err;
 353
 354         memset(bp->rx_buf_ring, 0, sizeof(struct sw_bd) * RX_DESC_CNT);
 355         bp->rx_desc_ring = pci_alloc_consistent(bp->pdev,
 356                                                 sizeof(struct rx_bd) *
 357                                                 RX_DESC_CNT,
 358                                                 &bp->rx_desc_mapping);
 359         if (bp->rx_desc_ring == NULL)
 360                 goto alloc_mem_err;
 361
 362         bp->status_blk = pci_alloc_consistent(bp->pdev,
 363                                               sizeof(struct status_block),
 364                                               &bp->status_blk_mapping);
 365         if (bp->status_blk == NULL)
 366                 goto alloc_mem_err;
 367
 368         memset(bp->status_blk, 0, sizeof(struct status_block));
 369
 370         bp->stats_blk = pci_alloc_consistent(bp->pdev,
 371                                              sizeof(struct statistics_block),
 372                                              &bp->stats_blk_mapping);
 373         if (bp->stats_blk == NULL)
 374                 goto alloc_mem_err;
 375
 376         memset(bp->stats_blk, 0, sizeof(struct statistics_block));
 377
 378         return 0;
 379
 380 alloc_mem_err:
 381         bnx2_free_mem(bp);
 382         return -ENOMEM;
 383 }
 384
 385 static void
 386 bnx2_report_link(struct bnx2 *bp)
 387 {
 388         if (bp->link_up) {
 389                 netif_carrier_on(bp->dev);
 390                 printk(KERN_INFO PFX "%s NIC Link is Up, ", bp->dev->name);
 391
 392                 printk("%d Mbps ", bp->line_speed);
 393
 394                 if (bp->duplex == DUPLEX_FULL)
 395                         printk("full duplex");
 396                 else
 397                         printk("half duplex");
 398
 399                 if (bp->flow_ctrl) {
 400                         if (bp->flow_ctrl & FLOW_CTRL_RX) {
 401                                 printk(", receive ");
 402                                 if (bp->flow_ctrl & FLOW_CTRL_TX)
 403                                         printk("& transmit ");
 404                         }
 405                         else {
 406                                 printk(", transmit ");
 407                         }
 408                         printk("flow control ON");
 409                 }
 410                 printk("\n");
 411         }
 412         else {
 413                 netif_carrier_off(bp->dev);
 414                 printk(KERN_ERR PFX "%s NIC Link is Down\n", bp->dev->name);
 415         }
 416 }
 417
 418 static void
 419 bnx2_resolve_flow_ctrl(struct bnx2 *bp)
 420 {
 421         u32 local_adv, remote_adv;
 422
 423         bp->flow_ctrl = 0;
 424         if ((bp->autoneg & (AUTONEG_SPEED | AUTONEG_FLOW_CTRL)) !=
 425                 (AUTONEG_SPEED | AUTONEG_FLOW_CTRL)) {
 426
 427                 if (bp->duplex == DUPLEX_FULL) {
 428                         bp->flow_ctrl = bp->req_flow_ctrl;
 429                 }
 430                 return;
 431         }
 432
 433         if (bp->duplex != DUPLEX_FULL) {
 434                 return;
 435         }
 436
 437         bnx2_read_phy(bp, MII_ADVERTISE, &local_adv);
 438         bnx2_read_phy(bp, MII_LPA, &remote_adv);
 439
 440         if (bp->phy_flags & PHY_SERDES_FLAG) {
 441                 u32 new_local_adv = 0;
 442                 u32 new_remote_adv = 0;
 443
 444                 if (local_adv & ADVERTISE_1000XPAUSE)
 445                         new_local_adv |= ADVERTISE_PAUSE_CAP;
 446                 if (local_adv & ADVERTISE_1000XPSE_ASYM)
 447                         new_local_adv |= ADVERTISE_PAUSE_ASYM;
 448                 if (remote_adv & ADVERTISE_1000XPAUSE)
 449                         new_remote_adv |= ADVERTISE_PAUSE_CAP;
 450                 if (remote_adv & ADVERTISE_1000XPSE_ASYM)
 451                         new_remote_adv |= ADVERTISE_PAUSE_ASYM;
 452
 453                 local_adv = new_local_adv;
 454                 remote_adv = new_remote_adv;
 455         }
 456
 457         /* See Table 28B-3 of 802.3ab-1999 spec. */
 458         if (local_adv & ADVERTISE_PAUSE_CAP) {
 459                 if(local_adv & ADVERTISE_PAUSE_ASYM) {
 460                         if (remote_adv & ADVERTISE_PAUSE_CAP) {
 461                                 bp->flow_ctrl = FLOW_CTRL_TX | FLOW_CTRL_RX;
 462                         }
 463                         else if (remote_adv & ADVERTISE_PAUSE_ASYM) {
 464                                 bp->flow_ctrl = FLOW_CTRL_RX;
 465                         }
 466                 }
 467                 else {
 468                         if (remote_adv & ADVERTISE_PAUSE_CAP) {
 469                                 bp->flow_ctrl = FLOW_CTRL_TX | FLOW_CTRL_RX;
 470                         }
 471                 }
 472         }
 473         else if (local_adv & ADVERTISE_PAUSE_ASYM) {
 474                 if ((remote_adv & ADVERTISE_PAUSE_CAP) &&
 475                         (remote_adv & ADVERTISE_PAUSE_ASYM)) {
 476
 477                         bp->flow_ctrl = FLOW_CTRL_TX;
 478                 }
 479         }
 480 }
 481
 482 static int
 483 bnx2_serdes_linkup(struct bnx2 *bp)
 484 {
 485         u32 bmcr, local_adv, remote_adv, common;
 486
 487         bp->link_up = 1;
 488         bp->line_speed = SPEED_1000;
 489
 490         bnx2_read_phy(bp, MII_BMCR, &bmcr);
 491         if (bmcr & BMCR_FULLDPLX) {
 492                 bp->duplex = DUPLEX_FULL;
 493         }
 494         else {
 495                 bp->duplex = DUPLEX_HALF;
 496         }
 497
 498         if (!(bmcr & BMCR_ANENABLE)) {
 499                 return 0;
 500         }
 501
 502         bnx2_read_phy(bp, MII_ADVERTISE, &local_adv);
 503         bnx2_read_phy(bp, MII_LPA, &remote_adv);
 504
 505         common = local_adv & remote_adv;
 506         if (common & (ADVERTISE_1000XHALF | ADVERTISE_1000XFULL)) {
 507
 508                 if (common & ADVERTISE_1000XFULL) {
 509                         bp->duplex = DUPLEX_FULL;
 510                 }
 511                 else {
 512                         bp->duplex = DUPLEX_HALF;
 513                 }
 514         }
 515
 516         return 0;
 517 }
 518
 519 static int
 520 bnx2_copper_linkup(struct bnx2 *bp)
 521 {
 522         u32 bmcr;
 523
 524         bnx2_read_phy(bp, MII_BMCR, &bmcr);
 525         if (bmcr & BMCR_ANENABLE) {
 526                 u32 local_adv, remote_adv, common;
 527
 528                 bnx2_read_phy(bp, MII_CTRL1000, &local_adv);
 529                 bnx2_read_phy(bp, MII_STAT1000, &remote_adv);
 530
 531                 common = local_adv & (remote_adv >> 2);
 532                 if (common & ADVERTISE_1000FULL) {
 533                         bp->line_speed = SPEED_1000;
 534                         bp->duplex = DUPLEX_FULL;
 535                 }
 536                 else if (common & ADVERTISE_1000HALF) {
 537                         bp->line_speed = SPEED_1000;
 538                         bp->duplex = DUPLEX_HALF;
 539                 }
 540                 else {
 541                         bnx2_read_phy(bp, MII_ADVERTISE, &local_adv);
 542                         bnx2_read_phy(bp, MII_LPA, &remote_adv);
 543
 544                         common = local_adv & remote_adv;
 545                         if (common & ADVERTISE_100FULL) {
 546                                 bp->line_speed = SPEED_100;
 547                                 bp->duplex = DUPLEX_FULL;
 548                         }
 549                         else if (common & ADVERTISE_100HALF) {
 550                                 bp->line_speed = SPEED_100;
 551                                 bp->duplex = DUPLEX_HALF;
 552                         }
 553                         else if (common & ADVERTISE_10FULL) {
 554                                 bp->line_speed = SPEED_10;
 555                                 bp->duplex = DUPLEX_FULL;
 556                         }
 557                         else if (common & ADVERTISE_10HALF) {
 558                                 bp->line_speed = SPEED_10;
 559                                 bp->duplex = DUPLEX_HALF;
 560                         }
 561                         else {
 562                                 bp->line_speed = 0;
 563                                 bp->link_up = 0;
 564                         }
 565                 }
 566         }
 567         else {
 568                 if (bmcr & BMCR_SPEED100) {
 569                         bp->line_speed = SPEED_100;
 570                 }
 571                 else {
 572                         bp->line_speed = SPEED_10;
 573                 }
 574                 if (bmcr & BMCR_FULLDPLX) {
 575                         bp->duplex = DUPLEX_FULL;
 576                 }
 577                 else {
 578                         bp->duplex = DUPLEX_HALF;
 579                 }
 580         }
 581
 582         return 0;
 583 }
 584
 585 static int
 586 bnx2_set_mac_link(struct bnx2 *bp)
 587 {
 588         u32 val;
 589
 590         REG_WR(bp, BNX2_EMAC_TX_LENGTHS, 0x2620);
 591         if (bp->link_up && (bp->line_speed == SPEED_1000) &&
 592                 (bp->duplex == DUPLEX_HALF)) {
 593                 REG_WR(bp, BNX2_EMAC_TX_LENGTHS, 0x26ff);
 594         }
 595
 596         /* Configure the EMAC mode register. */
 597         val = REG_RD(bp, BNX2_EMAC_MODE);
 598
 599         val &= ~(BNX2_EMAC_MODE_PORT | BNX2_EMAC_MODE_HALF_DUPLEX |
 600                 BNX2_EMAC_MODE_MAC_LOOP | BNX2_EMAC_MODE_FORCE_LINK);
 601
 602         if (bp->link_up) {
 603                 if (bp->line_speed != SPEED_1000)
 604                         val |= BNX2_EMAC_MODE_PORT_MII;
 605                 else
 606                         val |= BNX2_EMAC_MODE_PORT_GMII;
 607         }
 608         else {
 609                 val |= BNX2_EMAC_MODE_PORT_GMII;
 610         }
 611
 612         /* Set the MAC to operate in the appropriate duplex mode. */
 613         if (bp->duplex == DUPLEX_HALF)
 614                 val |= BNX2_EMAC_MODE_HALF_DUPLEX;
 615         REG_WR(bp, BNX2_EMAC_MODE, val);
 616
 617         /* Enable/disable rx PAUSE. */
 618         bp->rx_mode &= ~BNX2_EMAC_RX_MODE_FLOW_EN;
 619
 620         if (bp->flow_ctrl & FLOW_CTRL_RX)
 621                 bp->rx_mode |= BNX2_EMAC_RX_MODE_FLOW_EN;
 622         REG_WR(bp, BNX2_EMAC_RX_MODE, bp->rx_mode);
 623
 624         /* Enable/disable tx PAUSE. */
 625         val = REG_RD(bp, BNX2_EMAC_TX_MODE);
 626         val &= ~BNX2_EMAC_TX_MODE_FLOW_EN;
 627
 628         if (bp->flow_ctrl & FLOW_CTRL_TX)
 629                 val |= BNX2_EMAC_TX_MODE_FLOW_EN;
 630         REG_WR(bp, BNX2_EMAC_TX_MODE, val);
 631
 632         /* Acknowledge the interrupt. */
 633         REG_WR(bp, BNX2_EMAC_STATUS, BNX2_EMAC_STATUS_LINK_CHANGE);
 634
 635         return 0;
 636 }
 637
 638 static int
 639 bnx2_set_link(struct bnx2 *bp)
 640 {
 641         u32 bmsr;
 642         u8 link_up;
 643
 644         if (bp->loopback == MAC_LOOPBACK) {
 645                 bp->link_up = 1;
 646                 return 0;
 647         }
 648
 649         link_up = bp->link_up;
 650
 651         bnx2_read_phy(bp, MII_BMSR, &bmsr);
 652         bnx2_read_phy(bp, MII_BMSR, &bmsr);
 653
 654         if ((bp->phy_flags & PHY_SERDES_FLAG) &&
 655             (CHIP_NUM(bp) == CHIP_NUM_5706)) {
 656                 u32 val;
 657
 658                 val = REG_RD(bp, BNX2_EMAC_STATUS);
 659                 if (val & BNX2_EMAC_STATUS_LINK)
 660                         bmsr |= BMSR_LSTATUS;
 661                 else
 662                         bmsr &= ~BMSR_LSTATUS;
 663         }
 664
 665         if (bmsr & BMSR_LSTATUS) {
 666                 bp->link_up = 1;
 667
 668                 if (bp->phy_flags & PHY_SERDES_FLAG) {
 669                         bnx2_serdes_linkup(bp);
 670                 }
 671                 else {
 672                         bnx2_copper_linkup(bp);
 673                 }
 674                 bnx2_resolve_flow_ctrl(bp);
 675         }
 676         else {
 677                 if ((bp->phy_flags & PHY_SERDES_FLAG) &&
 678                         (bp->autoneg & AUTONEG_SPEED)) {
 679
 680                         u32 bmcr;
 681
 682                         bnx2_read_phy(bp, MII_BMCR, &bmcr);
 683                         if (!(bmcr & BMCR_ANENABLE)) {
 684                                 bnx2_write_phy(bp, MII_BMCR, bmcr |
 685                                         BMCR_ANENABLE);
 686                         }
 687                 }
 688                 bp->phy_flags &= ~PHY_PARALLEL_DETECT_FLAG;
 689                 bp->link_up = 0;
 690         }
 691
 692         if (bp->link_up != link_up) {
 693                 bnx2_report_link(bp);
 694         }
 695
 696         bnx2_set_mac_link(bp);
 697
 698         return 0;
 699 }
 700
 701 static int
 702 bnx2_reset_phy(struct bnx2 *bp)
 703 {
 704         int i;
 705         u32 reg;
 706
 707         bnx2_write_phy(bp, MII_BMCR, BMCR_RESET);
 708
 709 #define PHY_RESET_MAX_WAIT 100
 710         for (i = 0; i < PHY_RESET_MAX_WAIT; i++) {
 711                 udelay(10);
 712
 713                 bnx2_read_phy(bp, MII_BMCR, &reg);
 714                 if (!(reg & BMCR_RESET)) {
 715                         udelay(20);
 716                         break;
 717                 }
 718         }
 719         if (i == PHY_RESET_MAX_WAIT) {
 720                 return -EBUSY;
 721         }
 722         return 0;
 723 }
 724
 725 static u32
 726 bnx2_phy_get_pause_adv(struct bnx2 *bp)
 727 {
 728         u32 adv = 0;
 729
 730         if ((bp->req_flow_ctrl & (FLOW_CTRL_RX | FLOW_CTRL_TX)) ==
 731                 (FLOW_CTRL_RX | FLOW_CTRL_TX)) {
 732
 733                 if (bp->phy_flags & PHY_SERDES_FLAG) {
 734                         adv = ADVERTISE_1000XPAUSE;
 735                 }
 736                 else {
 737                         adv = ADVERTISE_PAUSE_CAP;
 738                 }
 739         }
 740         else if (bp->req_flow_ctrl & FLOW_CTRL_TX) {
 741                 if (bp->phy_flags & PHY_SERDES_FLAG) {
 742                         adv = ADVERTISE_1000XPSE_ASYM;
 743                 }
 744                 else {
 745                         adv = ADVERTISE_PAUSE_ASYM;
 746                 }
 747         }
 748         else if (bp->req_flow_ctrl & FLOW_CTRL_RX) {
 749                 if (bp->phy_flags & PHY_SERDES_FLAG) {
 750                         adv = ADVERTISE_1000XPAUSE | ADVERTISE_1000XPSE_ASYM;
 751                 }
 752                 else {
 753                         adv = ADVERTISE_PAUSE_CAP | ADVERTISE_PAUSE_ASYM;
 754                 }
 755         }
 756         return adv;
 757 }
 758
 759 static int
 760 bnx2_setup_serdes_phy(struct bnx2 *bp)
 761 {
 762         u32 adv, bmcr;
 763         u32 new_adv = 0;
 764
 765         if (!(bp->autoneg & AUTONEG_SPEED)) {
 766                 u32 new_bmcr;
 767
 768                 bnx2_read_phy(bp, MII_BMCR, &bmcr);
 769                 new_bmcr = bmcr & ~BMCR_ANENABLE;
 770                 new_bmcr |= BMCR_SPEED1000;
 771                 if (bp->req_duplex == DUPLEX_FULL) {
 772                         new_bmcr |= BMCR_FULLDPLX;
 773                 }
 774                 else {
 775                         new_bmcr &= ~BMCR_FULLDPLX;
 776                 }
 777                 if (new_bmcr != bmcr) {
 778                         /* Force a link down visible on the other side */
 779                         if (bp->link_up) {
 780                                 bnx2_read_phy(bp, MII_ADVERTISE, &adv);
 781                                 adv &= ~(ADVERTISE_1000XFULL |
 782                                         ADVERTISE_1000XHALF);
 783                                 bnx2_write_phy(bp, MII_ADVERTISE, adv);
 784                                 bnx2_write_phy(bp, MII_BMCR, bmcr |
 785                                         BMCR_ANRESTART | BMCR_ANENABLE);
 786
 787                                 bp->link_up = 0;
 788                                 netif_carrier_off(bp->dev);
 789                         }
 790                         bnx2_write_phy(bp, MII_BMCR, new_bmcr);
 791                 }
 792                 return 0;
 793         }
 794
 795         if (bp->advertising & ADVERTISED_1000baseT_Full)
 796                 new_adv |= ADVERTISE_1000XFULL;
 797
 798         new_adv |= bnx2_phy_get_pause_adv(bp);
 799
 800         bnx2_read_phy(bp, MII_ADVERTISE, &adv);
 801         bnx2_read_phy(bp, MII_BMCR, &bmcr);
 802
 803         bp->serdes_an_pending = 0;
 804         if ((adv != new_adv) || ((bmcr & BMCR_ANENABLE) == 0)) {
 805                 /* Force a link down visible on the other side */
 806                 if (bp->link_up) {
 807                         int i;
 808
 809                         bnx2_write_phy(bp, MII_BMCR, BMCR_LOOPBACK);
 810                         for (i = 0; i < 110; i++) {
 811                                 udelay(100);
 812                         }
 813                 }
 814
 815                 bnx2_write_phy(bp, MII_ADVERTISE, new_adv);
 816                 bnx2_write_phy(bp, MII_BMCR, bmcr | BMCR_ANRESTART |
 817                         BMCR_ANENABLE);
 818                 if (CHIP_NUM(bp) == CHIP_NUM_5706) {
 819                         /* Speed up link-up time when the link partner
 820                          * does not autonegotiate which is very common
 821                          * in blade servers. Some blade servers use
 822                          * IPMI for kerboard input and it's important
 823                          * to minimize link disruptions. Autoneg. involves
 824                          * exchanging base pages plus 3 next pages and
 825                          * normally completes in about 120 msec.
 826                          */
 827                         bp->current_interval = SERDES_AN_TIMEOUT;
 828                         bp->serdes_an_pending = 1;
 829                         mod_timer(&bp->timer, jiffies + bp->current_interval);
 830                 }
 831         }
 832
 833         return 0;
 834 }
 835
 836 #define ETHTOOL_ALL_FIBRE_SPEED                                         \
 837         (ADVERTISED_1000baseT_Full)
 838
 839 #define ETHTOOL_ALL_COPPER_SPEED                                        \
 840         (ADVERTISED_10baseT_Half | ADVERTISED_10baseT_Full |            \
 841         ADVERTISED_100baseT_Half | ADVERTISED_100baseT_Full |           \
 842         ADVERTISED_1000baseT_Full)
 843
 844 #define PHY_ALL_10_100_SPEED (ADVERTISE_10HALF | ADVERTISE_10FULL | \
 845         ADVERTISE_100HALF | ADVERTISE_100FULL | ADVERTISE_CSMA)
 846
 847 #define PHY_ALL_1000_SPEED (ADVERTISE_1000HALF | ADVERTISE_1000FULL)
 848
 849 static int
 850 bnx2_setup_copper_phy(struct bnx2 *bp)
 851 {
 852         u32 bmcr;
 853         u32 new_bmcr;
 854
 855         bnx2_read_phy(bp, MII_BMCR, &bmcr);
 856
 857         if (bp->autoneg & AUTONEG_SPEED) {
 858                 u32 adv_reg, adv1000_reg;
 859                 u32 new_adv_reg = 0;
 860                 u32 new_adv1000_reg = 0;
 861
 862                 bnx2_read_phy(bp, MII_ADVERTISE, &adv_reg);
 863                 adv_reg &= (PHY_ALL_10_100_SPEED | ADVERTISE_PAUSE_CAP |
 864                         ADVERTISE_PAUSE_ASYM);
 865
 866                 bnx2_read_phy(bp, MII_CTRL1000, &adv1000_reg);
 867                 adv1000_reg &= PHY_ALL_1000_SPEED;
 868
 869                 if (bp->advertising & ADVERTISED_10baseT_Half)
 870                         new_adv_reg |= ADVERTISE_10HALF;
 871                 if (bp->advertising & ADVERTISED_10baseT_Full)
 872                         new_adv_reg |= ADVERTISE_10FULL;
 873                 if (bp->advertising & ADVERTISED_100baseT_Half)
 874                         new_adv_reg |= ADVERTISE_100HALF;
 875                 if (bp->advertising & ADVERTISED_100baseT_Full)
 876                         new_adv_reg |= ADVERTISE_100FULL;
 877                 if (bp->advertising & ADVERTISED_1000baseT_Full)
 878                         new_adv1000_reg |= ADVERTISE_1000FULL;
 879
 880                 new_adv_reg |= ADVERTISE_CSMA;
 881
 882                 new_adv_reg |= bnx2_phy_get_pause_adv(bp);
 883
 884                 if ((adv1000_reg != new_adv1000_reg) ||
 885                         (adv_reg != new_adv_reg) ||
 886                         ((bmcr & BMCR_ANENABLE) == 0)) {
 887
 888                         bnx2_write_phy(bp, MII_ADVERTISE, new_adv_reg);
 889                         bnx2_write_phy(bp, MII_CTRL1000, new_adv1000_reg);
 890                         bnx2_write_phy(bp, MII_BMCR, BMCR_ANRESTART |
 891                                 BMCR_ANENABLE);
 892                 }
 893                 else if (bp->link_up) {
 894                         /* Flow ctrl may have changed from auto to forced */
 895                         /* or vice-versa. */
 896
 897                         bnx2_resolve_flow_ctrl(bp);
 898                         bnx2_set_mac_link(bp);
 899                 }
 900                 return 0;
 901         }
 902
 903         new_bmcr = 0;
 904         if (bp->req_line_speed == SPEED_100) {
 905                 new_bmcr |= BMCR_SPEED100;
 906         }
 907         if (bp->req_duplex == DUPLEX_FULL) {
 908                 new_bmcr |= BMCR_FULLDPLX;
 909         }
 910         if (new_bmcr != bmcr) {
 911                 u32 bmsr;
 912                 int i = 0;
 913
 914                 bnx2_read_phy(bp, MII_BMSR, &bmsr);
 915                 bnx2_read_phy(bp, MII_BMSR, &bmsr);
 916
 917                 if (bmsr & BMSR_LSTATUS) {
 918                         /* Force link down */
 919                         bnx2_write_phy(bp, MII_BMCR, BMCR_LOOPBACK);
 920                         do {
 921                                 udelay(100);
 922                                 bnx2_read_phy(bp, MII_BMSR, &bmsr);
 923                                 bnx2_read_phy(bp, MII_BMSR, &bmsr);
 924                                 i++;
 925                         } while ((bmsr & BMSR_LSTATUS) && (i < 620));
 926                 }
 927
 928                 bnx2_write_phy(bp, MII_BMCR, new_bmcr);
 929
 930                 /* Normally, the new speed is setup after the link has
 931                  * gone down and up again. In some cases, link will not go
 932                  * down so we need to set up the new speed here.
 933                  */
 934                 if (bmsr & BMSR_LSTATUS) {
 935                         bp->line_speed = bp->req_line_speed;
 936                         bp->duplex = bp->req_duplex;
 937                         bnx2_resolve_flow_ctrl(bp);
 938                         bnx2_set_mac_link(bp);
 939                 }
 940         }
 941         return 0;
 942 }
 943
 944 static int
 945 bnx2_setup_phy(struct bnx2 *bp)
 946 {
 947         if (bp->loopback == MAC_LOOPBACK)
 948                 return 0;
 949
 950         if (bp->phy_flags & PHY_SERDES_FLAG) {
 951                 return (bnx2_setup_serdes_phy(bp));
 952         }
 953         else {
 954                 return (bnx2_setup_copper_phy(bp));
 955         }
 956 }
 957
 958 static int
 959 bnx2_init_serdes_phy(struct bnx2 *bp)
 960 {
 961         bp->phy_flags &= ~PHY_PARALLEL_DETECT_FLAG;
 962
 963         if (CHIP_NUM(bp) == CHIP_NUM_5706) {
 964                 REG_WR(bp, BNX2_MISC_UNUSED0, 0x300);
 965         }
 966
 967         if (bp->dev->mtu > 1500) {
 968                 u32 val;
 969
 970                 /* Set extended packet length bit */
 971                 bnx2_write_phy(bp, 0x18, 0x7);
 972                 bnx2_read_phy(bp, 0x18, &val);
 973                 bnx2_write_phy(bp, 0x18, (val & 0xfff8) | 0x4000);
 974
 975                 bnx2_write_phy(bp, 0x1c, 0x6c00);
 976                 bnx2_read_phy(bp, 0x1c, &val);
 977                 bnx2_write_phy(bp, 0x1c, (val & 0x3ff) | 0xec02);
 978         }
 979         else {
 980                 u32 val;
 981
 982                 bnx2_write_phy(bp, 0x18, 0x7);
 983                 bnx2_read_phy(bp, 0x18, &val);
 984                 bnx2_write_phy(bp, 0x18, val & ~0x4007);
 985
 986                 bnx2_write_phy(bp, 0x1c, 0x6c00);
 987                 bnx2_read_phy(bp, 0x1c, &val);
 988                 bnx2_write_phy(bp, 0x1c, (val & 0x3fd) | 0xec00);
 989         }
 990
 991         return 0;
 992 }
 993
 994 static int
 995 bnx2_init_copper_phy(struct bnx2 *bp)
 996 {
 997         bp->phy_flags |= PHY_CRC_FIX_FLAG;
 998
 999         if (bp->phy_flags & PHY_CRC_FIX_FLAG) {
1000                 bnx2_write_phy(bp, 0x18, 0x0c00);
1001                 bnx2_write_phy(bp, 0x17, 0x000a);
1002                 bnx2_write_phy(bp, 0x15, 0x310b);
1003                 bnx2_write_phy(bp, 0x17, 0x201f);
1004                 bnx2_write_phy(bp, 0x15, 0x9506);
1005                 bnx2_write_phy(bp, 0x17, 0x401f);
1006                 bnx2_write_phy(bp, 0x15, 0x14e2);
1007                 bnx2_write_phy(bp, 0x18, 0x0400);
1008         }
1009
1010         if (bp->dev->mtu > 1500) {
1011                 u32 val;
1012
1013                 /* Set extended packet length bit */
1014                 bnx2_write_phy(bp, 0x18, 0x7);
1015                 bnx2_read_phy(bp, 0x18, &val);
1016                 bnx2_write_phy(bp, 0x18, val | 0x4000);
1017
1018                 bnx2_read_phy(bp, 0x10, &val);
1019                 bnx2_write_phy(bp, 0x10, val | 0x1);
1020         }
1021         else {
1022                 u32 val;
1023
1024                 bnx2_write_phy(bp, 0x18, 0x7);
1025                 bnx2_read_phy(bp, 0x18, &val);
1026                 bnx2_write_phy(bp, 0x18, val & ~0x4007);
1027
1028                 bnx2_read_phy(bp, 0x10, &val);
1029                 bnx2_write_phy(bp, 0x10, val & ~0x1);
1030         }
1031
1032         return 0;
1033 }
1034
1035
1036 static int
1037 bnx2_init_phy(struct bnx2 *bp)
1038 {
1039         u32 val;
1040         int rc = 0;
1041
1042         bp->phy_flags &= ~PHY_INT_MODE_MASK_FLAG;
1043         bp->phy_flags |= PHY_INT_MODE_LINK_READY_FLAG;
1044
1045         REG_WR(bp, BNX2_EMAC_ATTENTION_ENA, BNX2_EMAC_ATTENTION_ENA_LINK);
1046
1047         bnx2_reset_phy(bp);
1048
1049         bnx2_read_phy(bp, MII_PHYSID1, &val);
1050         bp->phy_id = val << 16;
1051         bnx2_read_phy(bp, MII_PHYSID2, &val);
1052         bp->phy_id |= val & 0xffff;
1053
1054         if (bp->phy_flags & PHY_SERDES_FLAG) {
1055                 rc = bnx2_init_serdes_phy(bp);
1056         }
1057         else {
1058                 rc = bnx2_init_copper_phy(bp);
1059         }
1060
1061         bnx2_setup_phy(bp);
1062
1063         return rc;
1064 }
1065
1066 static int
1067 bnx2_set_mac_loopback(struct bnx2 *bp)
1068 {
1069         u32 mac_mode;
1070
1071         mac_mode = REG_RD(bp, BNX2_EMAC_MODE);
1072         mac_mode &= ~BNX2_EMAC_MODE_PORT;
1073         mac_mode |= BNX2_EMAC_MODE_MAC_LOOP | BNX2_EMAC_MODE_FORCE_LINK;
1074         REG_WR(bp, BNX2_EMAC_MODE, mac_mode);
1075         bp->link_up = 1;
1076         return 0;
1077 }
1078
1079 static int
1080 bnx2_fw_sync(struct bnx2 *bp, u32 msg_data)
1081 {
1082         int i;
1083         u32 val;
1084
1085         if (bp->fw_timed_out)
1086                 return -EBUSY;
1087
1088         bp->fw_wr_seq++;
1089         msg_data |= bp->fw_wr_seq;
1090
1091         REG_WR_IND(bp, HOST_VIEW_SHMEM_BASE + BNX2_DRV_MB, msg_data);
1092
1093         /* wait for an acknowledgement. */
1094         for (i = 0; i < (FW_ACK_TIME_OUT_MS * 1000)/5; i++) {
1095                 udelay(5);
1096
1097                 val = REG_RD_IND(bp, HOST_VIEW_SHMEM_BASE + BNX2_FW_MB);
1098
1099                 if ((val & BNX2_FW_MSG_ACK) == (msg_data & BNX2_DRV_MSG_SEQ))
1100                         break;
1101         }
1102
1103         /* If we timed out, inform the firmware that this is the case. */
1104         if (((val & BNX2_FW_MSG_ACK) != (msg_data & BNX2_DRV_MSG_SEQ)) &&
1105                 ((msg_data & BNX2_DRV_MSG_DATA) != BNX2_DRV_MSG_DATA_WAIT0)) {
1106
1107                 msg_data &= ~BNX2_DRV_MSG_CODE;
1108                 msg_data |= BNX2_DRV_MSG_CODE_FW_TIMEOUT;
1109
1110                 REG_WR_IND(bp, HOST_VIEW_SHMEM_BASE + BNX2_DRV_MB, msg_data);
1111
1112                 bp->fw_timed_out = 1;
1113
1114                 return -EBUSY;
1115         }
1116
1117         return 0;
1118 }
1119
1120 static void
1121 bnx2_init_context(struct bnx2 *bp)
1122 {
1123         u32 vcid;
1124
1125         vcid = 96;
1126         while (vcid) {
1127                 u32 vcid_addr, pcid_addr, offset;
1128
1129                 vcid--;
1130
1131                 if (CHIP_ID(bp) == CHIP_ID_5706_A0) {
1132                         u32 new_vcid;
1133
1134                         vcid_addr = GET_PCID_ADDR(vcid);
1135                         if (vcid & 0x8) {
1136                                 new_vcid = 0x60 + (vcid & 0xf0) + (vcid & 0x7);
1137                         }
1138                         else {
1139                                 new_vcid = vcid;
1140                         }
1141                         pcid_addr = GET_PCID_ADDR(new_vcid);
1142                 }
1143                 else {
1144                         vcid_addr = GET_CID_ADDR(vcid);
1145                         pcid_addr = vcid_addr;
1146                 }
1147
1148                 REG_WR(bp, BNX2_CTX_VIRT_ADDR, 0x00);
1149                 REG_WR(bp, BNX2_CTX_PAGE_TBL, pcid_addr);
1150
1151                 /* Zero out the context. */
1152                 for (offset = 0; offset < PHY_CTX_SIZE; offset += 4) {
1153                         CTX_WR(bp, 0x00, offset, 0);
1154                 }
1155
1156                 REG_WR(bp, BNX2_CTX_VIRT_ADDR, vcid_addr);
1157                 REG_WR(bp, BNX2_CTX_PAGE_TBL, pcid_addr);
1158         }
1159 }
1160
1161 static int
1162 bnx2_alloc_bad_rbuf(struct bnx2 *bp)
1163 {
1164         u16 *good_mbuf;
1165         u32 good_mbuf_cnt;
1166         u32 val;
1167
1168         good_mbuf = kmalloc(512 * sizeof(u16), GFP_KERNEL);
1169         if (good_mbuf == NULL) {
1170                 printk(KERN_ERR PFX "Failed to allocate memory in "
1171                                     "bnx2_alloc_bad_rbuf\n");
1172                 return -ENOMEM;
1173         }
1174
1175         REG_WR(bp, BNX2_MISC_ENABLE_SET_BITS,
1176                 BNX2_MISC_ENABLE_SET_BITS_RX_MBUF_ENABLE);
1177
1178         good_mbuf_cnt = 0;
1179
1180         /* Allocate a bunch of mbufs and save the good ones in an array. */
1181         val = REG_RD_IND(bp, BNX2_RBUF_STATUS1);
1182         while (val & BNX2_RBUF_STATUS1_FREE_COUNT) {
1183                 REG_WR_IND(bp, BNX2_RBUF_COMMAND, BNX2_RBUF_COMMAND_ALLOC_REQ);
1184
1185                 val = REG_RD_IND(bp, BNX2_RBUF_FW_BUF_ALLOC);
1186
1187                 val &= BNX2_RBUF_FW_BUF_ALLOC_VALUE;
1188
1189                 /* The addresses with Bit 9 set are bad memory blocks. */
1190                 if (!(val & (1 << 9))) {
1191                         good_mbuf[good_mbuf_cnt] = (u16) val;
1192                         good_mbuf_cnt++;
1193                 }
1194
1195                 val = REG_RD_IND(bp, BNX2_RBUF_STATUS1);
1196         }
1197
1198         /* Free the good ones back to the mbuf pool thus discarding
1199          * all the bad ones. */
1200         while (good_mbuf_cnt) {
1201                 good_mbuf_cnt--;
1202
1203                 val = good_mbuf[good_mbuf_cnt];
1204                 val = (val << 9) | val | 1;
1205
1206                 REG_WR_IND(bp, BNX2_RBUF_FW_BUF_FREE, val);
1207         }
1208         kfree(good_mbuf);
1209         return 0;
1210 }
1211
1212 static void
1213 bnx2_set_mac_addr(struct bnx2 *bp)
1214 {
1215         u32 val;
1216         u8 *mac_addr = bp->dev->dev_addr;
1217
1218         val = (mac_addr[0] << 8) | mac_addr[1];
1219
1220         REG_WR(bp, BNX2_EMAC_MAC_MATCH0, val);
1221
1222         val = (mac_addr[2] << 24) | (mac_addr[3] << 16) |
1223                 (mac_addr[4] << 8) | mac_addr[5];
1224
1225         REG_WR(bp, BNX2_EMAC_MAC_MATCH1, val);
1226 }
1227
1228 static inline int
1229 bnx2_alloc_rx_skb(struct bnx2 *bp, u16 index)
1230 {
1231         struct sk_buff *skb;
1232         struct sw_bd *rx_buf = &bp->rx_buf_ring[index];
1233         dma_addr_t mapping;
1234         struct rx_bd *rxbd = &bp->rx_desc_ring[index];
1235         unsigned long align;
1236
1237         skb = dev_alloc_skb(bp->rx_buf_size);
1238         if (skb == NULL) {
1239                 return -ENOMEM;
1240         }
1241
1242         if (unlikely((align = (unsigned long) skb->data & 0x7))) {
1243                 skb_reserve(skb, 8 - align);
1244         }
1245
1246         skb->dev = bp->dev;
1247         mapping = pci_map_single(bp->pdev, skb->data, bp->rx_buf_use_size,
1248                 PCI_DMA_FROMDEVICE);
1249
1250         rx_buf->skb = skb;
1251         pci_unmap_addr_set(rx_buf, mapping, mapping);
1252
1253         rxbd->rx_bd_haddr_hi = (u64) mapping >> 32;
1254         rxbd->rx_bd_haddr_lo = (u64) mapping & 0xffffffff;
1255
1256         bp->rx_prod_bseq += bp->rx_buf_use_size;
1257
1258         return 0;
1259 }
1260
1261 static void
1262 bnx2_phy_int(struct bnx2 *bp)
1263 {
1264         u32 new_link_state, old_link_state;
1265
1266         new_link_state = bp->status_blk->status_attn_bits &
1267                 STATUS_ATTN_BITS_LINK_STATE;
1268         old_link_state = bp->status_blk->status_attn_bits_ack &
1269                 STATUS_ATTN_BITS_LINK_STATE;
1270         if (new_link_state != old_link_state) {
1271                 if (new_link_state) {
1272                         REG_WR(bp, BNX2_PCICFG_STATUS_BIT_SET_CMD,
1273                                 STATUS_ATTN_BITS_LINK_STATE);
1274                 }
1275                 else {
1276                         REG_WR(bp, BNX2_PCICFG_STATUS_BIT_CLEAR_CMD,
1277                                 STATUS_ATTN_BITS_LINK_STATE);
1278                 }
1279                 bnx2_set_link(bp);
1280         }
1281 }
1282
1283 static void
1284 bnx2_tx_int(struct bnx2 *bp)
1285 {
1286         u16 hw_cons, sw_cons, sw_ring_cons;
1287         int tx_free_bd = 0;
1288
1289         hw_cons = bp->status_blk->status_tx_quick_consumer_index0;
1290         if ((hw_cons & MAX_TX_DESC_CNT) == MAX_TX_DESC_CNT) {
1291                 hw_cons++;
1292         }
1293         sw_cons = bp->tx_cons;
1294
1295         while (sw_cons != hw_cons) {
1296                 struct sw_bd *tx_buf;
1297                 struct sk_buff *skb;
1298                 int i, last;
1299
1300                 sw_ring_cons = TX_RING_IDX(sw_cons);
1301
1302                 tx_buf = &bp->tx_buf_ring[sw_ring_cons];
1303                 skb = tx_buf->skb;
1304 #ifdef BCM_TSO
1305                 /* partial BD completions possible with TSO packets */
1306                 if (skb_shinfo(skb)->tso_size) {
1307                         u16 last_idx, last_ring_idx;
1308
1309                         last_idx = sw_cons +
1310                                 skb_shinfo(skb)->nr_frags + 1;
1311                         last_ring_idx = sw_ring_cons +
1312                                 skb_shinfo(skb)->nr_frags + 1;
1313                         if (unlikely(last_ring_idx >= MAX_TX_DESC_CNT)) {
1314                                 last_idx++;
1315                         }
1316                         if (((s16) ((s16) last_idx - (s16) hw_cons)) > 0) {
1317                                 break;
1318                         }
1319                 }
1320 #endif
1321                 pci_unmap_single(bp->pdev, pci_unmap_addr(tx_buf, mapping),
1322                         skb_headlen(skb), PCI_DMA_TODEVICE);
1323
1324                 tx_buf->skb = NULL;
1325                 last = skb_shinfo(skb)->nr_frags;
1326
1327                 for (i = 0; i < last; i++) {
1328                         sw_cons = NEXT_TX_BD(sw_cons);
1329
1330                         pci_unmap_page(bp->pdev,
1331                                 pci_unmap_addr(
1332                                         &bp->tx_buf_ring[TX_RING_IDX(sw_cons)],
1333                                         mapping),
1334                                 skb_shinfo(skb)->frags[i].size,
1335                                 PCI_DMA_TODEVICE);
1336                 }
1337
1338                 sw_cons = NEXT_TX_BD(sw_cons);
1339
1340                 tx_free_bd += last + 1;
1341
1342                 dev_kfree_skb_irq(skb);
1343
1344                 hw_cons = bp->status_blk->status_tx_quick_consumer_index0;
1345                 if ((hw_cons & MAX_TX_DESC_CNT) == MAX_TX_DESC_CNT) {
1346                         hw_cons++;
1347                 }
1348         }
1349
1350         bp->tx_cons = sw_cons;
1351
1352         if (unlikely(netif_queue_stopped(bp->dev))) {
1353                 spin_lock(&bp->tx_lock);
1354                 if ((netif_queue_stopped(bp->dev)) &&
1355                     (bnx2_tx_avail(bp) > MAX_SKB_FRAGS)) {
1356
1357                         netif_wake_queue(bp->dev);
1358                 }
1359                 spin_unlock(&bp->tx_lock);
1360         }
1361 }
1362
1363 static inline void
1364 bnx2_reuse_rx_skb(struct bnx2 *bp, struct sk_buff *skb,
1365         u16 cons, u16 prod)
1366 {
1367         struct sw_bd *cons_rx_buf = &bp->rx_buf_ring[cons];
1368         struct sw_bd *prod_rx_buf = &bp->rx_buf_ring[prod];
1369         struct rx_bd *cons_bd = &bp->rx_desc_ring[cons];
1370         struct rx_bd *prod_bd = &bp->rx_desc_ring[prod];
1371
1372         pci_dma_sync_single_for_device(bp->pdev,
1373                 pci_unmap_addr(cons_rx_buf, mapping),
1374                 bp->rx_offset + RX_COPY_THRESH, PCI_DMA_FROMDEVICE);
1375
1376         prod_rx_buf->skb = cons_rx_buf->skb;
1377         pci_unmap_addr_set(prod_rx_buf, mapping,
1378                         pci_unmap_addr(cons_rx_buf, mapping));
1379
1380         memcpy(prod_bd, cons_bd, 8);
1381
1382         bp->rx_prod_bseq += bp->rx_buf_use_size;
1383
1384 }
1385
1386 static int
1387 bnx2_rx_int(struct bnx2 *bp, int budget)
1388 {
1389         u16 hw_cons, sw_cons, sw_ring_cons, sw_prod, sw_ring_prod;
1390         struct l2_fhdr *rx_hdr;
1391         int rx_pkt = 0;
1392
1393         hw_cons = bp->status_blk->status_rx_quick_consumer_index0;
1394         if ((hw_cons & MAX_RX_DESC_CNT) == MAX_RX_DESC_CNT) {
1395                 hw_cons++;
1396         }
1397         sw_cons = bp->rx_cons;
1398         sw_prod = bp->rx_prod;
1399
1400         /* Memory barrier necessary as speculative reads of the rx
1401          * buffer can be ahead of the index in the status block
1402          */
1403         rmb();
1404         while (sw_cons != hw_cons) {
1405                 unsigned int len;
1406                 u16 status;
1407                 struct sw_bd *rx_buf;
1408                 struct sk_buff *skb;
1409
1410                 sw_ring_cons = RX_RING_IDX(sw_cons);
1411                 sw_ring_prod = RX_RING_IDX(sw_prod);
1412
1413                 rx_buf = &bp->rx_buf_ring[sw_ring_cons];
1414                 skb = rx_buf->skb;
1415                 pci_dma_sync_single_for_cpu(bp->pdev,
1416                         pci_unmap_addr(rx_buf, mapping),
1417                         bp->rx_offset + RX_COPY_THRESH, PCI_DMA_FROMDEVICE);
1418
1419                 rx_hdr = (struct l2_fhdr *) skb->data;
1420                 len = rx_hdr->l2_fhdr_pkt_len - 4;
1421
1422                 if (rx_hdr->l2_fhdr_errors &
1423                         (L2_FHDR_ERRORS_BAD_CRC |
1424                         L2_FHDR_ERRORS_PHY_DECODE |
1425                         L2_FHDR_ERRORS_ALIGNMENT |
1426                         L2_FHDR_ERRORS_TOO_SHORT |
1427                         L2_FHDR_ERRORS_GIANT_FRAME)) {
1428
1429                         goto reuse_rx;
1430                 }
1431
1432                 /* Since we don't have a jumbo ring, copy small packets
1433                  * if mtu > 1500
1434                  */
1435                 if ((bp->dev->mtu > 1500) && (len <= RX_COPY_THRESH)) {
1436                         struct sk_buff *new_skb;
1437
1438                         new_skb = dev_alloc_skb(len + 2);
1439                         if (new_skb == NULL)
1440                                 goto reuse_rx;
1441
1442                         /* aligned copy */
1443                         memcpy(new_skb->data,
1444                                 skb->data + bp->rx_offset - 2,
1445                                 len + 2);
1446
1447                         skb_reserve(new_skb, 2);
1448                         skb_put(new_skb, len);
1449                         new_skb->dev = bp->dev;
1450
1451                         bnx2_reuse_rx_skb(bp, skb,
1452                                 sw_ring_cons, sw_ring_prod);
1453
1454                         skb = new_skb;
1455                 }
1456                 else if (bnx2_alloc_rx_skb(bp, sw_ring_prod) == 0) {
1457                         pci_unmap_single(bp->pdev,
1458                                 pci_unmap_addr(rx_buf, mapping),
1459                                 bp->rx_buf_use_size, PCI_DMA_FROMDEVICE);
1460
1461                         skb_reserve(skb, bp->rx_offset);
1462                         skb_put(skb, len);
1463                 }
1464                 else {
1465 reuse_rx:
1466                         bnx2_reuse_rx_skb(bp, skb,
1467                                 sw_ring_cons, sw_ring_prod);
1468                         goto next_rx;
1469                 }
1470
1471                 skb->protocol = eth_type_trans(skb, bp->dev);
1472
1473                 if ((len > (bp->dev->mtu + ETH_HLEN)) &&
1474                         (htons(skb->protocol) != 0x8100)) {
1475
1476                         dev_kfree_skb_irq(skb);
1477                         goto next_rx;
1478
1479                 }
1480
1481                 status = rx_hdr->l2_fhdr_status;
1482                 skb->ip_summed = CHECKSUM_NONE;
1483                 if (bp->rx_csum &&
1484                         (status & (L2_FHDR_STATUS_TCP_SEGMENT |
1485                         L2_FHDR_STATUS_UDP_DATAGRAM))) {
1486
1487                         u16 cksum = rx_hdr->l2_fhdr_tcp_udp_xsum;
1488
1489                         if (cksum == 0xffff)
1490                                 skb->ip_summed = CHECKSUM_UNNECESSARY;
1491                 }
1492
1493 #ifdef BCM_VLAN
1494                 if ((status & L2_FHDR_STATUS_L2_VLAN_TAG) && (bp->vlgrp != 0)) {
1495                         vlan_hwaccel_receive_skb(skb, bp->vlgrp,
1496                                 rx_hdr->l2_fhdr_vlan_tag);
1497                 }
1498                 else
1499 #endif
1500                         netif_receive_skb(skb);
1501
1502                 bp->dev->last_rx = jiffies;
1503                 rx_pkt++;
1504
1505 next_rx:
1506                 rx_buf->skb = NULL;
1507
1508                 sw_cons = NEXT_RX_BD(sw_cons);
1509                 sw_prod = NEXT_RX_BD(sw_prod);
1510
1511                 if ((rx_pkt == budget))
1512                         break;
1513         }
1514         bp->rx_cons = sw_cons;
1515         bp->rx_prod = sw_prod;
1516
1517         REG_WR16(bp, MB_RX_CID_ADDR + BNX2_L2CTX_HOST_BDIDX, sw_prod);
1518
1519         REG_WR(bp, MB_RX_CID_ADDR + BNX2_L2CTX_HOST_BSEQ, bp->rx_prod_bseq);
1520
1521         mmiowb();
1522
1523         return rx_pkt;
1524
1525 }
1526
1527 /* MSI ISR - The only difference between this and the INTx ISR
1528  * is that the MSI interrupt is always serviced.
1529  */
1530 static irqreturn_t
1531 bnx2_msi(int irq, void *dev_instance, struct pt_regs *regs)
1532 {
1533         struct net_device *dev = dev_instance;
1534         struct bnx2 *bp = dev->priv;
1535
1536         REG_WR(bp, BNX2_PCICFG_INT_ACK_CMD,
1537                 BNX2_PCICFG_INT_ACK_CMD_USE_INT_HC_PARAM |
1538                 BNX2_PCICFG_INT_ACK_CMD_MASK_INT);
1539
1540         /* Return here if interrupt is disabled. */
1541         if (unlikely(atomic_read(&bp->intr_sem) != 0)) {
1542                 return IRQ_RETVAL(1);
1543         }
1544
1545         if (netif_rx_schedule_prep(dev)) {
1546                 __netif_rx_schedule(dev);
1547         }
1548
1549         return IRQ_RETVAL(1);
1550 }
1551
1552 static irqreturn_t
1553 bnx2_interrupt(int irq, void *dev_instance, struct pt_regs *regs)
1554 {
1555         struct net_device *dev = dev_instance;
1556         struct bnx2 *bp = dev->priv;
1557
1558         /* When using INTx, it is possible for the interrupt to arrive
1559          * at the CPU before the status block posted prior to the
1560          * interrupt. Reading a register will flush the status block.
1561          * When using MSI, the MSI message will always complete after
1562          * the status block write.
1563          */
1564         if ((bp->status_blk->status_idx == bp->last_status_idx) ||
1565             (REG_RD(bp, BNX2_PCICFG_MISC_STATUS) &
1566              BNX2_PCICFG_MISC_STATUS_INTA_VALUE))
1567                 return IRQ_RETVAL(0);
1568
1569         REG_WR(bp, BNX2_PCICFG_INT_ACK_CMD,
1570                 BNX2_PCICFG_INT_ACK_CMD_USE_INT_HC_PARAM |
1571                 BNX2_PCICFG_INT_ACK_CMD_MASK_INT);
1572
1573         /* Return here if interrupt is shared and is disabled. */
1574         if (unlikely(atomic_read(&bp->intr_sem) != 0)) {
1575                 return IRQ_RETVAL(1);
1576         }
1577
1578         if (netif_rx_schedule_prep(dev)) {
1579                 __netif_rx_schedule(dev);
1580         }
1581
1582         return IRQ_RETVAL(1);
1583 }
1584
1585 static int
1586 bnx2_poll(struct net_device *dev, int *budget)
1587 {
1588         struct bnx2 *bp = dev->priv;
1589         int rx_done = 1;
1590
1591         bp->last_status_idx = bp->status_blk->status_idx;
1592
1593         rmb();
1594         if ((bp->status_blk->status_attn_bits &
1595                 STATUS_ATTN_BITS_LINK_STATE) !=
1596                 (bp->status_blk->status_attn_bits_ack &
1597                 STATUS_ATTN_BITS_LINK_STATE)) {
1598
1599                 spin_lock(&bp->phy_lock);
1600                 bnx2_phy_int(bp);
1601                 spin_unlock(&bp->phy_lock);
1602         }
1603
1604         if (bp->status_blk->status_tx_quick_consumer_index0 != bp->tx_cons) {
1605                 bnx2_tx_int(bp);
1606         }
1607
1608         if (bp->status_blk->status_rx_quick_consumer_index0 != bp->rx_cons) {
1609                 int orig_budget = *budget;
1610                 int work_done;
1611
1612                 if (orig_budget > dev->quota)
1613                         orig_budget = dev->quota;
1614
1615                 work_done = bnx2_rx_int(bp, orig_budget);
1616                 *budget -= work_done;
1617                 dev->quota -= work_done;
1618
1619                 if (work_done >= orig_budget) {
1620                         rx_done = 0;
1621                 }
1622         }
1623
1624         if (rx_done) {
1625                 netif_rx_complete(dev);
1626                 REG_WR(bp, BNX2_PCICFG_INT_ACK_CMD,
1627                         BNX2_PCICFG_INT_ACK_CMD_INDEX_VALID |
1628                         bp->last_status_idx);
1629                 return 0;
1630         }
1631
1632         return 1;
1633 }
1634
1635 /* Called with rtnl_lock from vlan functions and also dev->xmit_lock
1636  * from set_multicast.
1637  */
1638 static void
1639 bnx2_set_rx_mode(struct net_device *dev)
1640 {
1641         struct bnx2 *bp = dev->priv;
1642         u32 rx_mode, sort_mode;
1643         int i;
1644
1645         spin_lock_bh(&bp->phy_lock);
1646
1647         rx_mode = bp->rx_mode & ~(BNX2_EMAC_RX_MODE_PROMISCUOUS |
1648                                   BNX2_EMAC_RX_MODE_KEEP_VLAN_TAG);
1649         sort_mode = 1 | BNX2_RPM_SORT_USER0_BC_EN;
1650 #ifdef BCM_VLAN
1651         if (!bp->vlgrp) {
1652                 rx_mode |= BNX2_EMAC_RX_MODE_KEEP_VLAN_TAG;
1653         }
1654 #else
1655         rx_mode |= BNX2_EMAC_RX_MODE_KEEP_VLAN_TAG;
1656 #endif
1657         if (dev->flags & IFF_PROMISC) {
1658                 /* Promiscuous mode. */
1659                 rx_mode |= BNX2_EMAC_RX_MODE_PROMISCUOUS;
1660                 sort_mode |= BNX2_RPM_SORT_USER0_PROM_EN;
1661         }
1662         else if (dev->flags & IFF_ALLMULTI) {
1663                 for (i = 0; i < NUM_MC_HASH_REGISTERS; i++) {
1664                         REG_WR(bp, BNX2_EMAC_MULTICAST_HASH0 + (i * 4),
1665                                0xffffffff);
1666                 }
1667                 sort_mode |= BNX2_RPM_SORT_USER0_MC_EN;
1668         }
1669         else {
1670                 /* Accept one or more multicast(s). */
1671                 struct dev_mc_list *mclist;
1672                 u32 mc_filter[NUM_MC_HASH_REGISTERS];
1673                 u32 regidx;
1674                 u32 bit;
1675                 u32 crc;
1676
1677                 memset(mc_filter, 0, 4 * NUM_MC_HASH_REGISTERS);
1678
1679                 for (i = 0, mclist = dev->mc_list; mclist && i < dev->mc_count;
1680                      i++, mclist = mclist->next) {
1681
1682                         crc = ether_crc_le(ETH_ALEN, mclist->dmi_addr);
1683                         bit = crc & 0xff;
1684                         regidx = (bit & 0xe0) >> 5;
1685                         bit &= 0x1f;
1686                         mc_filter[regidx] |= (1 << bit);
1687                 }
1688
1689                 for (i = 0; i < NUM_MC_HASH_REGISTERS; i++) {
1690                         REG_WR(bp, BNX2_EMAC_MULTICAST_HASH0 + (i * 4),
1691                                mc_filter[i]);
1692                 }
1693
1694                 sort_mode |= BNX2_RPM_SORT_USER0_MC_HSH_EN;
1695         }
1696
1697         if (rx_mode != bp->rx_mode) {
1698                 bp->rx_mode = rx_mode;
1699                 REG_WR(bp, BNX2_EMAC_RX_MODE, rx_mode);
1700         }
1701
1702         REG_WR(bp, BNX2_RPM_SORT_USER0, 0x0);
1703         REG_WR(bp, BNX2_RPM_SORT_USER0, sort_mode);
1704         REG_WR(bp, BNX2_RPM_SORT_USER0, sort_mode | BNX2_RPM_SORT_USER0_ENA);
1705
1706         spin_unlock_bh(&bp->phy_lock);
1707 }
1708
1709 static void
1710 load_rv2p_fw(struct bnx2 *bp, u32 *rv2p_code, u32 rv2p_code_len,
1711         u32 rv2p_proc)
1712 {
1713         int i;
1714         u32 val;
1715
1716
1717         for (i = 0; i < rv2p_code_len; i += 8) {
1718                 REG_WR(bp, BNX2_RV2P_INSTR_HIGH, *rv2p_code);
1719                 rv2p_code++;
1720                 REG_WR(bp, BNX2_RV2P_INSTR_LOW, *rv2p_code);
1721                 rv2p_code++;
1722
1723                 if (rv2p_proc == RV2P_PROC1) {
1724                         val = (i / 8) | BNX2_RV2P_PROC1_ADDR_CMD_RDWR;
1725                         REG_WR(bp, BNX2_RV2P_PROC1_ADDR_CMD, val);
1726                 }
1727                 else {
1728                         val = (i / 8) | BNX2_RV2P_PROC2_ADDR_CMD_RDWR;
1729                         REG_WR(bp, BNX2_RV2P_PROC2_ADDR_CMD, val);
1730                 }
1731         }
1732
1733         /* Reset the processor, un-stall is done later. */
1734         if (rv2p_proc == RV2P_PROC1) {
1735                 REG_WR(bp, BNX2_RV2P_COMMAND, BNX2_RV2P_COMMAND_PROC1_RESET);
1736         }
1737         else {
1738                 REG_WR(bp, BNX2_RV2P_COMMAND, BNX2_RV2P_COMMAND_PROC2_RESET);
1739         }
1740 }
1741
1742 static void
1743 load_cpu_fw(struct bnx2 *bp, struct cpu_reg *cpu_reg, struct fw_info *fw)
1744 {
1745         u32 offset;
1746         u32 val;
1747
1748         /* Halt the CPU. */
1749         val = REG_RD_IND(bp, cpu_reg->mode);
1750         val |= cpu_reg->mode_value_halt;
1751         REG_WR_IND(bp, cpu_reg->mode, val);
1752         REG_WR_IND(bp, cpu_reg->state, cpu_reg->state_value_clear);
1753
1754         /* Load the Text area. */
1755         offset = cpu_reg->spad_base + (fw->text_addr - cpu_reg->mips_view_base);
1756         if (fw->text) {
1757                 int j;
1758
1759                 for (j = 0; j < (fw->text_len / 4); j++, offset += 4) {
1760                         REG_WR_IND(bp, offset, fw->text[j]);
1761                 }
1762         }
1763
1764         /* Load the Data area. */
1765         offset = cpu_reg->spad_base + (fw->data_addr - cpu_reg->mips_view_base);
1766         if (fw->data) {
1767                 int j;
1768
1769                 for (j = 0; j < (fw->data_len / 4); j++, offset += 4) {
1770                         REG_WR_IND(bp, offset, fw->data[j]);
1771                 }
1772         }
1773
1774         /* Load the SBSS area. */
1775         offset = cpu_reg->spad_base + (fw->sbss_addr - cpu_reg->mips_view_base);
1776         if (fw->sbss) {
1777                 int j;
1778
1779                 for (j = 0; j < (fw->sbss_len / 4); j++, offset += 4) {
1780                         REG_WR_IND(bp, offset, fw->sbss[j]);
1781                 }
1782         }
1783
1784         /* Load the BSS area. */
1785         offset = cpu_reg->spad_base + (fw->bss_addr - cpu_reg->mips_view_base);
1786         if (fw->bss) {
1787                 int j;
1788
1789                 for (j = 0; j < (fw->bss_len/4); j++, offset += 4) {
1790                         REG_WR_IND(bp, offset, fw->bss[j]);
1791                 }
1792         }
1793
1794         /* Load the Read-Only area. */
1795         offset = cpu_reg->spad_base +
1796                 (fw->rodata_addr - cpu_reg->mips_view_base);
1797         if (fw->rodata) {
1798                 int j;
1799
1800                 for (j = 0; j < (fw->rodata_len / 4); j++, offset += 4) {
1801                         REG_WR_IND(bp, offset, fw->rodata[j]);
1802                 }
1803         }
1804
1805         /* Clear the pre-fetch instruction. */
1806         REG_WR_IND(bp, cpu_reg->inst, 0);
1807         REG_WR_IND(bp, cpu_reg->pc, fw->start_addr);
1808
1809         /* Start the CPU. */
1810         val = REG_RD_IND(bp, cpu_reg->mode);
1811         val &= ~cpu_reg->mode_value_halt;
1812         REG_WR_IND(bp, cpu_reg->state, cpu_reg->state_value_clear);
1813         REG_WR_IND(bp, cpu_reg->mode, val);
1814 }
1815
1816 static void
1817 bnx2_init_cpus(struct bnx2 *bp)
1818 {
1819         struct cpu_reg cpu_reg;
1820         struct fw_info fw;
1821
1822         /* Initialize the RV2P processor. */
1823         load_rv2p_fw(bp, bnx2_rv2p_proc1, sizeof(bnx2_rv2p_proc1), RV2P_PROC1);
1824         load_rv2p_fw(bp, bnx2_rv2p_proc2, sizeof(bnx2_rv2p_proc2), RV2P_PROC2);
1825
1826         /* Initialize the RX Processor. */
1827         cpu_reg.mode = BNX2_RXP_CPU_MODE;
1828         cpu_reg.mode_value_halt = BNX2_RXP_CPU_MODE_SOFT_HALT;
1829         cpu_reg.mode_value_sstep = BNX2_RXP_CPU_MODE_STEP_ENA;
1830         cpu_reg.state = BNX2_RXP_CPU_STATE;
1831         cpu_reg.state_value_clear = 0xffffff;
1832         cpu_reg.gpr0 = BNX2_RXP_CPU_REG_FILE;
1833         cpu_reg.evmask = BNX2_RXP_CPU_EVENT_MASK;
1834         cpu_reg.pc = BNX2_RXP_CPU_PROGRAM_COUNTER;
1835         cpu_reg.inst = BNX2_RXP_CPU_INSTRUCTION;
1836         cpu_reg.bp = BNX2_RXP_CPU_HW_BREAKPOINT;
1837         cpu_reg.spad_base = BNX2_RXP_SCRATCH;
1838         cpu_reg.mips_view_base = 0x8000000;
1839
1840         fw.ver_major = bnx2_RXP_b06FwReleaseMajor;
1841         fw.ver_minor = bnx2_RXP_b06FwReleaseMinor;
1842         fw.ver_fix = bnx2_RXP_b06FwReleaseFix;
1843         fw.start_addr = bnx2_RXP_b06FwStartAddr;
1844
1845         fw.text_addr = bnx2_RXP_b06FwTextAddr;
1846         fw.text_len = bnx2_RXP_b06FwTextLen;
1847         fw.text_index = 0;
1848         fw.text = bnx2_RXP_b06FwText;
1849
1850         fw.data_addr = bnx2_RXP_b06FwDataAddr;
1851         fw.data_len = bnx2_RXP_b06FwDataLen;
1852         fw.data_index = 0;
1853         fw.data = bnx2_RXP_b06FwData;
1854
1855         fw.sbss_addr = bnx2_RXP_b06FwSbssAddr;
1856         fw.sbss_len = bnx2_RXP_b06FwSbssLen;
1857         fw.sbss_index = 0;
1858         fw.sbss = bnx2_RXP_b06FwSbss;
1859
1860         fw.bss_addr = bnx2_RXP_b06FwBssAddr;
1861         fw.bss_len = bnx2_RXP_b06FwBssLen;
1862         fw.bss_index = 0;
1863         fw.bss = bnx2_RXP_b06FwBss;
1864
1865         fw.rodata_addr = bnx2_RXP_b06FwRodataAddr;
1866         fw.rodata_len = bnx2_RXP_b06FwRodataLen;
1867         fw.rodata_index = 0;
1868         fw.rodata = bnx2_RXP_b06FwRodata;
1869
1870         load_cpu_fw(bp, &cpu_reg, &fw);
1871
1872         /* Initialize the TX Processor. */
1873         cpu_reg.mode = BNX2_TXP_CPU_MODE;
1874         cpu_reg.mode_value_halt = BNX2_TXP_CPU_MODE_SOFT_HALT;
1875         cpu_reg.mode_value_sstep = BNX2_TXP_CPU_MODE_STEP_ENA;
1876         cpu_reg.state = BNX2_TXP_CPU_STATE;
1877         cpu_reg.state_value_clear = 0xffffff;
1878         cpu_reg.gpr0 = BNX2_TXP_CPU_REG_FILE;
1879         cpu_reg.evmask = BNX2_TXP_CPU_EVENT_MASK;
1880         cpu_reg.pc = BNX2_TXP_CPU_PROGRAM_COUNTER;
1881         cpu_reg.inst = BNX2_TXP_CPU_INSTRUCTION;
1882         cpu_reg.bp = BNX2_TXP_CPU_HW_BREAKPOINT;
1883         cpu_reg.spad_base = BNX2_TXP_SCRATCH;
1884         cpu_reg.mips_view_base = 0x8000000;
1885
1886         fw.ver_major = bnx2_TXP_b06FwReleaseMajor;
1887         fw.ver_minor = bnx2_TXP_b06FwReleaseMinor;
1888         fw.ver_fix = bnx2_TXP_b06FwReleaseFix;
1889         fw.start_addr = bnx2_TXP_b06FwStartAddr;
1890
1891         fw.text_addr = bnx2_TXP_b06FwTextAddr;
1892         fw.text_len = bnx2_TXP_b06FwTextLen;
1893         fw.text_index = 0;
1894         fw.text = bnx2_TXP_b06FwText;
1895
1896         fw.data_addr = bnx2_TXP_b06FwDataAddr;
1897         fw.data_len = bnx2_TXP_b06FwDataLen;
1898         fw.data_index = 0;
1899         fw.data = bnx2_TXP_b06FwData;
1900
1901         fw.sbss_addr = bnx2_TXP_b06FwSbssAddr;
1902         fw.sbss_len = bnx2_TXP_b06FwSbssLen;
1903         fw.sbss_index = 0;
1904         fw.sbss = bnx2_TXP_b06FwSbss;
1905
1906         fw.bss_addr = bnx2_TXP_b06FwBssAddr;
1907         fw.bss_len = bnx2_TXP_b06FwBssLen;
1908         fw.bss_index = 0;
1909         fw.bss = bnx2_TXP_b06FwBss;
1910
1911         fw.rodata_addr = bnx2_TXP_b06FwRodataAddr;
1912         fw.rodata_len = bnx2_TXP_b06FwRodataLen;
1913         fw.rodata_index = 0;
1914         fw.rodata = bnx2_TXP_b06FwRodata;
1915
1916         load_cpu_fw(bp, &cpu_reg, &fw);
1917
1918         /* Initialize the TX Patch-up Processor. */
1919         cpu_reg.mode = BNX2_TPAT_CPU_MODE;
1920         cpu_reg.mode_value_halt = BNX2_TPAT_CPU_MODE_SOFT_HALT;
1921         cpu_reg.mode_value_sstep = BNX2_TPAT_CPU_MODE_STEP_ENA;
1922         cpu_reg.state = BNX2_TPAT_CPU_STATE;
1923         cpu_reg.state_value_clear = 0xffffff;
1924         cpu_reg.gpr0 = BNX2_TPAT_CPU_REG_FILE;
1925         cpu_reg.evmask = BNX2_TPAT_CPU_EVENT_MASK;
1926         cpu_reg.pc = BNX2_TPAT_CPU_PROGRAM_COUNTER;
1927         cpu_reg.inst = BNX2_TPAT_CPU_INSTRUCTION;
1928         cpu_reg.bp = BNX2_TPAT_CPU_HW_BREAKPOINT;
1929         cpu_reg.spad_base = BNX2_TPAT_SCRATCH;
1930         cpu_reg.mips_view_base = 0x8000000;
1931
1932         fw.ver_major = bnx2_TPAT_b06FwReleaseMajor;
1933         fw.ver_minor = bnx2_TPAT_b06FwReleaseMinor;
1934         fw.ver_fix = bnx2_TPAT_b06FwReleaseFix;
1935         fw.start_addr = bnx2_TPAT_b06FwStartAddr;
1936
1937         fw.text_addr = bnx2_TPAT_b06FwTextAddr;
1938         fw.text_len = bnx2_TPAT_b06FwTextLen;
1939         fw.text_index = 0;
1940         fw.text = bnx2_TPAT_b06FwText;
1941
1942         fw.data_addr = bnx2_TPAT_b06FwDataAddr;
1943         fw.data_len = bnx2_TPAT_b06FwDataLen;
1944         fw.data_index = 0;
1945         fw.data = bnx2_TPAT_b06FwData;
1946
1947         fw.sbss_addr = bnx2_TPAT_b06FwSbssAddr;
1948         fw.sbss_len = bnx2_TPAT_b06FwSbssLen;
1949         fw.sbss_index = 0;
1950         fw.sbss = bnx2_TPAT_b06FwSbss;
1951
1952         fw.bss_addr = bnx2_TPAT_b06FwBssAddr;
1953         fw.bss_len = bnx2_TPAT_b06FwBssLen;
1954         fw.bss_index = 0;
1955         fw.bss = bnx2_TPAT_b06FwBss;
1956
1957         fw.rodata_addr = bnx2_TPAT_b06FwRodataAddr;
1958         fw.rodata_len = bnx2_TPAT_b06FwRodataLen;
1959         fw.rodata_index = 0;
1960         fw.rodata = bnx2_TPAT_b06FwRodata;
1961
1962         load_cpu_fw(bp, &cpu_reg, &fw);
1963
1964         /* Initialize the Completion Processor. */
1965         cpu_reg.mode = BNX2_COM_CPU_MODE;
1966         cpu_reg.mode_value_halt = BNX2_COM_CPU_MODE_SOFT_HALT;
1967         cpu_reg.mode_value_sstep = BNX2_COM_CPU_MODE_STEP_ENA;
1968         cpu_reg.state = BNX2_COM_CPU_STATE;
1969         cpu_reg.state_value_clear = 0xffffff;
1970         cpu_reg.gpr0 = BNX2_COM_CPU_REG_FILE;
1971         cpu_reg.evmask = BNX2_COM_CPU_EVENT_MASK;
1972         cpu_reg.pc = BNX2_COM_CPU_PROGRAM_COUNTER;
1973         cpu_reg.inst = BNX2_COM_CPU_INSTRUCTION;
1974         cpu_reg.bp = BNX2_COM_CPU_HW_BREAKPOINT;
1975         cpu_reg.spad_base = BNX2_COM_SCRATCH;
1976         cpu_reg.mips_view_base = 0x8000000;
1977
1978         fw.ver_major = bnx2_COM_b06FwReleaseMajor;
1979         fw.ver_minor = bnx2_COM_b06FwReleaseMinor;
1980         fw.ver_fix = bnx2_COM_b06FwReleaseFix;
1981         fw.start_addr = bnx2_COM_b06FwStartAddr;
1982
1983         fw.text_addr = bnx2_COM_b06FwTextAddr;
1984         fw.text_len = bnx2_COM_b06FwTextLen;
1985         fw.text_index = 0;
1986         fw.text = bnx2_COM_b06FwText;
1987
1988         fw.data_addr = bnx2_COM_b06FwDataAddr;
1989         fw.data_len = bnx2_COM_b06FwDataLen;
1990         fw.data_index = 0;
1991         fw.data = bnx2_COM_b06FwData;
1992
1993         fw.sbss_addr = bnx2_COM_b06FwSbssAddr;
1994         fw.sbss_len = bnx2_COM_b06FwSbssLen;
1995         fw.sbss_index = 0;
1996         fw.sbss = bnx2_COM_b06FwSbss;
1997
1998         fw.bss_addr = bnx2_COM_b06FwBssAddr;
1999         fw.bss_len = bnx2_COM_b06FwBssLen;
2000         fw.bss_index = 0;
2001         fw.bss = bnx2_COM_b06FwBss;
2002
2003         fw.rodata_addr = bnx2_COM_b06FwRodataAddr;
2004         fw.rodata_len = bnx2_COM_b06FwRodataLen;
2005         fw.rodata_index = 0;
2006         fw.rodata = bnx2_COM_b06FwRodata;
2007
2008         load_cpu_fw(bp, &cpu_reg, &fw);
2009
2010 }
2011
2012 static int
2013 bnx2_set_power_state(struct bnx2 *bp, int state)
2014 {
2015         u16 pmcsr;
2016
2017         pci_read_config_word(bp->pdev, bp->pm_cap + PCI_PM_CTRL, &pmcsr);
2018
2019         switch (state) {
2020         case 0: {
2021                 u32 val;
2022
2023                 pci_write_config_word(bp->pdev, bp->pm_cap + PCI_PM_CTRL,
2024                         (pmcsr & ~PCI_PM_CTRL_STATE_MASK) |
2025                         PCI_PM_CTRL_PME_STATUS);
2026
2027                 if (pmcsr & PCI_PM_CTRL_STATE_MASK)
2028                         /* delay required during transition out of D3hot */
2029                         msleep(20);
2030
2031                 val = REG_RD(bp, BNX2_EMAC_MODE);
2032                 val |= BNX2_EMAC_MODE_MPKT_RCVD | BNX2_EMAC_MODE_ACPI_RCVD;
2033                 val &= ~BNX2_EMAC_MODE_MPKT;
2034                 REG_WR(bp, BNX2_EMAC_MODE, val);
2035
2036                 val = REG_RD(bp, BNX2_RPM_CONFIG);
2037                 val &= ~BNX2_RPM_CONFIG_ACPI_ENA;
2038                 REG_WR(bp, BNX2_RPM_CONFIG, val);
2039                 break;
2040         }
2041         case 3: {
2042                 int i;
2043                 u32 val, wol_msg;
2044
2045                 if (bp->wol) {
2046                         u32 advertising;
2047                         u8 autoneg;
2048
2049                         autoneg = bp->autoneg;
2050                         advertising = bp->advertising;
2051
2052                         bp->autoneg = AUTONEG_SPEED;
2053                         bp->advertising = ADVERTISED_10baseT_Half |
2054                                 ADVERTISED_10baseT_Full |
2055                                 ADVERTISED_100baseT_Half |
2056                                 ADVERTISED_100baseT_Full |
2057                                 ADVERTISED_Autoneg;
2058
2059                         bnx2_setup_copper_phy(bp);
2060
2061                         bp->autoneg = autoneg;
2062                         bp->advertising = advertising;
2063
2064                         bnx2_set_mac_addr(bp);
2065
2066                         val = REG_RD(bp, BNX2_EMAC_MODE);
2067
2068                         /* Enable port mode. */
2069                         val &= ~BNX2_EMAC_MODE_PORT;
2070                         val |= BNX2_EMAC_MODE_PORT_MII |
2071                                BNX2_EMAC_MODE_MPKT_RCVD |
2072                                BNX2_EMAC_MODE_ACPI_RCVD |
2073                                BNX2_EMAC_MODE_FORCE_LINK |
2074                                BNX2_EMAC_MODE_MPKT;
2075
2076                         REG_WR(bp, BNX2_EMAC_MODE, val);
2077
2078                         /* receive all multicast */
2079                         for (i = 0; i < NUM_MC_HASH_REGISTERS; i++) {
2080                                 REG_WR(bp, BNX2_EMAC_MULTICAST_HASH0 + (i * 4),
2081                                        0xffffffff);
2082                         }
2083                         REG_WR(bp, BNX2_EMAC_RX_MODE,
2084                                BNX2_EMAC_RX_MODE_SORT_MODE);
2085
2086                         val = 1 | BNX2_RPM_SORT_USER0_BC_EN |
2087                               BNX2_RPM_SORT_USER0_MC_EN;
2088                         REG_WR(bp, BNX2_RPM_SORT_USER0, 0x0);
2089                         REG_WR(bp, BNX2_RPM_SORT_USER0, val);
2090                         REG_WR(bp, BNX2_RPM_SORT_USER0, val |
2091                                BNX2_RPM_SORT_USER0_ENA);
2092
2093                         /* Need to enable EMAC and RPM for WOL. */
2094                         REG_WR(bp, BNX2_MISC_ENABLE_SET_BITS,
2095                                BNX2_MISC_ENABLE_SET_BITS_RX_PARSER_MAC_ENABLE |
2096                                BNX2_MISC_ENABLE_SET_BITS_TX_HEADER_Q_ENABLE |
2097                                BNX2_MISC_ENABLE_SET_BITS_EMAC_ENABLE);
2098
2099                         val = REG_RD(bp, BNX2_RPM_CONFIG);
2100                         val &= ~BNX2_RPM_CONFIG_ACPI_ENA;
2101                         REG_WR(bp, BNX2_RPM_CONFIG, val);
2102
2103                         wol_msg = BNX2_DRV_MSG_CODE_SUSPEND_WOL;
2104                 }
2105                 else {
2106                         wol_msg = BNX2_DRV_MSG_CODE_SUSPEND_NO_WOL;
2107                 }
2108
2109                 bnx2_fw_sync(bp, BNX2_DRV_MSG_DATA_WAIT3 | wol_msg);
2110
2111                 pmcsr &= ~PCI_PM_CTRL_STATE_MASK;
2112                 if ((CHIP_ID(bp) == CHIP_ID_5706_A0) ||
2113                     (CHIP_ID(bp) == CHIP_ID_5706_A1)) {
2114
2115                         if (bp->wol)
2116                                 pmcsr |= 3;
2117                 }
2118                 else {
2119                         pmcsr |= 3;
2120                 }
2121                 if (bp->wol) {
2122                         pmcsr |= PCI_PM_CTRL_PME_ENABLE;
2123                 }
2124                 pci_write_config_word(bp->pdev, bp->pm_cap + PCI_PM_CTRL,
2125                                       pmcsr);
2126
2127                 /* No more memory access after this point until
2128                  * device is brought back to D0.
2129                  */
2130                 udelay(50);
2131                 break;
2132         }
2133         default:
2134                 return -EINVAL;
2135         }
2136         return 0;
2137 }
2138
2139 static int
2140 bnx2_acquire_nvram_lock(struct bnx2 *bp)
2141 {
2142         u32 val;
2143         int j;
2144
2145         /* Request access to the flash interface. */
2146         REG_WR(bp, BNX2_NVM_SW_ARB, BNX2_NVM_SW_ARB_ARB_REQ_SET2);
2147         for (j = 0; j < NVRAM_TIMEOUT_COUNT; j++) {
2148                 val = REG_RD(bp, BNX2_NVM_SW_ARB);
2149                 if (val & BNX2_NVM_SW_ARB_ARB_ARB2)
2150                         break;
2151
2152                 udelay(5);
2153         }
2154
2155         if (j >= NVRAM_TIMEOUT_COUNT)
2156                 return -EBUSY;
2157
2158         return 0;
2159 }
2160
2161 static int
2162 bnx2_release_nvram_lock(struct bnx2 *bp)
2163 {
2164         int j;
2165         u32 val;
2166
2167         /* Relinquish nvram interface. */
2168         REG_WR(bp, BNX2_NVM_SW_ARB, BNX2_NVM_SW_ARB_ARB_REQ_CLR2);
2169
2170         for (j = 0; j < NVRAM_TIMEOUT_COUNT; j++) {
2171                 val = REG_RD(bp, BNX2_NVM_SW_ARB);
2172                 if (!(val & BNX2_NVM_SW_ARB_ARB_ARB2))
2173                         break;
2174
2175                 udelay(5);
2176         }
2177
2178         if (j >= NVRAM_TIMEOUT_COUNT)
2179                 return -EBUSY;
2180
2181         return 0;
2182 }
2183
2184
2185 static int
2186 bnx2_enable_nvram_write(struct bnx2 *bp)
2187 {
2188         u32 val;
2189
2190         val = REG_RD(bp, BNX2_MISC_CFG);
2191         REG_WR(bp, BNX2_MISC_CFG, val | BNX2_MISC_CFG_NVM_WR_EN_PCI);
2192
2193         if (!bp->flash_info->buffered) {
2194                 int j;
2195
2196                 REG_WR(bp, BNX2_NVM_COMMAND, BNX2_NVM_COMMAND_DONE);
2197                 REG_WR(bp, BNX2_NVM_COMMAND,
2198                        BNX2_NVM_COMMAND_WREN | BNX2_NVM_COMMAND_DOIT);
2199
2200                 for (j = 0; j < NVRAM_TIMEOUT_COUNT; j++) {
2201                         udelay(5);
2202
2203                         val = REG_RD(bp, BNX2_NVM_COMMAND);
2204                         if (val & BNX2_NVM_COMMAND_DONE)
2205                                 break;
2206                 }
2207
2208                 if (j >= NVRAM_TIMEOUT_COUNT)
2209                         return -EBUSY;
2210         }
2211         return 0;
2212 }
2213
2214 static void
2215 bnx2_disable_nvram_write(struct bnx2 *bp)
2216 {
2217         u32 val;
2218
2219         val = REG_RD(bp, BNX2_MISC_CFG);
2220         REG_WR(bp, BNX2_MISC_CFG, val & ~BNX2_MISC_CFG_NVM_WR_EN);
2221 }
2222
2223
2224 static void
2225 bnx2_enable_nvram_access(struct bnx2 *bp)
2226 {
2227         u32 val;
2228
2229         val = REG_RD(bp, BNX2_NVM_ACCESS_ENABLE);
2230         /* Enable both bits, even on read. */
2231         REG_WR(bp, BNX2_NVM_ACCESS_ENABLE,
2232                val | BNX2_NVM_ACCESS_ENABLE_EN | BNX2_NVM_ACCESS_ENABLE_WR_EN);
2233 }
2234
2235 static void
2236 bnx2_disable_nvram_access(struct bnx2 *bp)
2237 {
2238         u32 val;
2239
2240         val = REG_RD(bp, BNX2_NVM_ACCESS_ENABLE);
2241         /* Disable both bits, even after read. */
2242         REG_WR(bp, BNX2_NVM_ACCESS_ENABLE,
2243                 val & ~(BNX2_NVM_ACCESS_ENABLE_EN |
2244                         BNX2_NVM_ACCESS_ENABLE_WR_EN));
2245 }
2246
2247 static int
2248 bnx2_nvram_erase_page(struct bnx2 *bp, u32 offset)
2249 {
2250         u32 cmd;
2251         int j;
2252
2253         if (bp->flash_info->buffered)
2254                 /* Buffered flash, no erase needed */
2255                 return 0;
2256
2257         /* Build an erase command */
2258         cmd = BNX2_NVM_COMMAND_ERASE | BNX2_NVM_COMMAND_WR |
2259               BNX2_NVM_COMMAND_DOIT;
2260
2261         /* Need to clear DONE bit separately. */
2262         REG_WR(bp, BNX2_NVM_COMMAND, BNX2_NVM_COMMAND_DONE);
2263
2264         /* Address of the NVRAM to read from. */
2265         REG_WR(bp, BNX2_NVM_ADDR, offset & BNX2_NVM_ADDR_NVM_ADDR_VALUE);
2266
2267         /* Issue an erase command. */
2268         REG_WR(bp, BNX2_NVM_COMMAND, cmd);
2269
2270         /* Wait for completion. */
2271         for (j = 0; j < NVRAM_TIMEOUT_COUNT; j++) {
2272                 u32 val;
2273
2274                 udelay(5);
2275
2276                 val = REG_RD(bp, BNX2_NVM_COMMAND);
2277                 if (val & BNX2_NVM_COMMAND_DONE)
2278                         break;
2279         }
2280
2281         if (j >= NVRAM_TIMEOUT_COUNT)
2282                 return -EBUSY;
2283
2284         return 0;
2285 }
2286
2287 static int
2288 bnx2_nvram_read_dword(struct bnx2 *bp, u32 offset, u8 *ret_val, u32 cmd_flags)
2289 {
2290         u32 cmd;
2291         int j;
2292
2293         /* Build the command word. */
2294         cmd = BNX2_NVM_COMMAND_DOIT | cmd_flags;
2295
2296         /* Calculate an offset of a buffered flash. */
2297         if (bp->flash_info->buffered) {
2298                 offset = ((offset / bp->flash_info->page_size) <<
2299                            bp->flash_info->page_bits) +
2300                           (offset % bp->flash_info->page_size);
2301         }
2302
2303         /* Need to clear DONE bit separately. */
2304         REG_WR(bp, BNX2_NVM_COMMAND, BNX2_NVM_COMMAND_DONE);
2305
2306         /* Address of the NVRAM to read from. */
2307         REG_WR(bp, BNX2_NVM_ADDR, offset & BNX2_NVM_ADDR_NVM_ADDR_VALUE);
2308
2309         /* Issue a read command. */
2310         REG_WR(bp, BNX2_NVM_COMMAND, cmd);
2311
2312         /* Wait for completion. */
2313         for (j = 0; j < NVRAM_TIMEOUT_COUNT; j++) {
2314                 u32 val;
2315
2316                 udelay(5);
2317
2318                 val = REG_RD(bp, BNX2_NVM_COMMAND);
2319                 if (val & BNX2_NVM_COMMAND_DONE) {
2320                         val = REG_RD(bp, BNX2_NVM_READ);
2321
2322                         val = be32_to_cpu(val);
2323                         memcpy(ret_val, &val, 4);
2324                         break;
2325                 }
2326         }
2327         if (j >= NVRAM_TIMEOUT_COUNT)
2328                 return -EBUSY;
2329
2330         return 0;
2331 }
2332
2333
2334 static int
2335 bnx2_nvram_write_dword(struct bnx2 *bp, u32 offset, u8 *val, u32 cmd_flags)
2336 {
2337         u32 cmd, val32;
2338         int j;
2339
2340         /* Build the command word. */
2341         cmd = BNX2_NVM_COMMAND_DOIT | BNX2_NVM_COMMAND_WR | cmd_flags;
2342
2343         /* Calculate an offset of a buffered flash. */
2344         if (bp->flash_info->buffered) {
2345                 offset = ((offset / bp->flash_info->page_size) <<
2346                           bp->flash_info->page_bits) +
2347                          (offset % bp->flash_info->page_size);
2348         }
2349
2350         /* Need to clear DONE bit separately. */
2351         REG_WR(bp, BNX2_NVM_COMMAND, BNX2_NVM_COMMAND_DONE);
2352
2353         memcpy(&val32, val, 4);
2354         val32 = cpu_to_be32(val32);
2355
2356         /* Write the data. */
2357         REG_WR(bp, BNX2_NVM_WRITE, val32);
2358
2359         /* Address of the NVRAM to write to. */
2360         REG_WR(bp, BNX2_NVM_ADDR, offset & BNX2_NVM_ADDR_NVM_ADDR_VALUE);
2361
2362         /* Issue the write command. */
2363         REG_WR(bp, BNX2_NVM_COMMAND, cmd);
2364
2365         /* Wait for completion. */
2366         for (j = 0; j < NVRAM_TIMEOUT_COUNT; j++) {
2367                 udelay(5);
2368
2369                 if (REG_RD(bp, BNX2_NVM_COMMAND) & BNX2_NVM_COMMAND_DONE)
2370                         break;
2371         }
2372         if (j >= NVRAM_TIMEOUT_COUNT)
2373                 return -EBUSY;
2374
2375         return 0;
2376 }
2377
2378 static int
2379 bnx2_init_nvram(struct bnx2 *bp)
2380 {
2381         u32 val;
2382         int j, entry_count, rc;
2383         struct flash_spec *flash;
2384
2385         /* Determine the selected interface. */
2386         val = REG_RD(bp, BNX2_NVM_CFG1);
2387
2388         entry_count = sizeof(flash_table) / sizeof(struct flash_spec);
2389
2390         rc = 0;
2391         if (val & 0x40000000) {
2392
2393                 /* Flash interface has been reconfigured */
2394                 for (j = 0, flash = &flash_table[0]; j < entry_count;
2395                         j++, flash++) {
2396
2397                         if (val == flash->config1) {
2398                                 bp->flash_info = flash;
2399                                 break;
2400                         }
2401                 }
2402         }
2403         else {
2404                 /* Not yet been reconfigured */
2405
2406                 for (j = 0, flash = &flash_table[0]; j < entry_count;
2407                         j++, flash++) {
2408
2409                         if ((val & FLASH_STRAP_MASK) == flash->strapping) {
2410                                 bp->flash_info = flash;
2411
2412                                 /* Request access to the flash interface. */
2413                                 if ((rc = bnx2_acquire_nvram_lock(bp)) != 0)
2414                                         return rc;
2415
2416                                 /* Enable access to flash interface */
2417                                 bnx2_enable_nvram_access(bp);
2418
2419                                 /* Reconfigure the flash interface */
2420                                 REG_WR(bp, BNX2_NVM_CFG1, flash->config1);
2421                                 REG_WR(bp, BNX2_NVM_CFG2, flash->config2);
2422                                 REG_WR(bp, BNX2_NVM_CFG3, flash->config3);
2423                                 REG_WR(bp, BNX2_NVM_WRITE1, flash->write1);
2424
2425                                 /* Disable access to flash interface */
2426                                 bnx2_disable_nvram_access(bp);
2427                                 bnx2_release_nvram_lock(bp);
2428
2429                                 break;
2430                         }
2431                 }
2432         } /* if (val & 0x40000000) */
2433
2434         if (j == entry_count) {
2435                 bp->flash_info = NULL;
2436                 printk(KERN_ALERT "Unknown flash/EEPROM type.\n");
2437                 rc = -ENODEV;
2438         }
2439
2440         return rc;
2441 }
2442
2443 static int
2444 bnx2_nvram_read(struct bnx2 *bp, u32 offset, u8 *ret_buf,
2445                 int buf_size)
2446 {
2447         int rc = 0;
2448         u32 cmd_flags, offset32, len32, extra;
2449
2450         if (buf_size == 0)
2451                 return 0;
2452
2453         /* Request access to the flash interface. */
2454         if ((rc = bnx2_acquire_nvram_lock(bp)) != 0)
2455                 return rc;
2456
2457         /* Enable access to flash interface */
2458         bnx2_enable_nvram_access(bp);
2459
2460         len32 = buf_size;
2461         offset32 = offset;
2462         extra = 0;
2463
2464         cmd_flags = 0;
2465
2466         if (offset32 & 3) {
2467                 u8 buf[4];
2468                 u32 pre_len;
2469
2470                 offset32 &= ~3;
2471                 pre_len = 4 - (offset & 3);
2472
2473                 if (pre_len >= len32) {
2474                         pre_len = len32;
2475                         cmd_flags = BNX2_NVM_COMMAND_FIRST |
2476                                     BNX2_NVM_COMMAND_LAST;
2477                 }
2478                 else {
2479                         cmd_flags = BNX2_NVM_COMMAND_FIRST;
2480                 }
2481
2482                 rc = bnx2_nvram_read_dword(bp, offset32, buf, cmd_flags);
2483
2484                 if (rc)
2485                         return rc;
2486
2487                 memcpy(ret_buf, buf + (offset & 3), pre_len);
2488
2489                 offset32 += 4;
2490                 ret_buf += pre_len;
2491                 len32 -= pre_len;
2492         }
2493         if (len32 & 3) {
2494                 extra = 4 - (len32 & 3);
2495                 len32 = (len32 + 4) & ~3;
2496         }
2497
2498         if (len32 == 4) {
2499                 u8 buf[4];
2500
2501                 if (cmd_flags)
2502                         cmd_flags = BNX2_NVM_COMMAND_LAST;
2503                 else
2504                         cmd_flags = BNX2_NVM_COMMAND_FIRST |
2505                                     BNX2_NVM_COMMAND_LAST;
2506
2507                 rc = bnx2_nvram_read_dword(bp, offset32, buf, cmd_flags);
2508
2509                 memcpy(ret_buf, buf, 4 - extra);
2510         }
2511         else if (len32 > 0) {
2512                 u8 buf[4];
2513
2514                 /* Read the first word. */
2515                 if (cmd_flags)
2516                         cmd_flags = 0;
2517                 else
2518                         cmd_flags = BNX2_NVM_COMMAND_FIRST;
2519
2520                 rc = bnx2_nvram_read_dword(bp, offset32, ret_buf, cmd_flags);
2521
2522                 /* Advance to the next dword. */
2523                 offset32 += 4;
2524                 ret_buf += 4;
2525                 len32 -= 4;
2526
2527                 while (len32 > 4 && rc == 0) {
2528                         rc = bnx2_nvram_read_dword(bp, offset32, ret_buf, 0);
2529
2530                         /* Advance to the next dword. */
2531                         offset32 += 4;
2532                         ret_buf += 4;
2533                         len32 -= 4;
2534                 }
2535
2536                 if (rc)
2537                         return rc;
2538
2539                 cmd_flags = BNX2_NVM_COMMAND_LAST;
2540                 rc = bnx2_nvram_read_dword(bp, offset32, buf, cmd_flags);
2541
2542                 memcpy(ret_buf, buf, 4 - extra);
2543         }
2544
2545         /* Disable access to flash interface */
2546         bnx2_disable_nvram_access(bp);
2547
2548         bnx2_release_nvram_lock(bp);
2549
2550         return rc;
2551 }
2552
2553 static int
2554 bnx2_nvram_write(struct bnx2 *bp, u32 offset, u8 *data_buf,
2555                 int buf_size)
2556 {
2557         u32 written, offset32, len32;
2558         u8 *buf, start[4], end[4];
2559         int rc = 0;
2560         int align_start, align_end;
2561
2562         buf = data_buf;
2563         offset32 = offset;
2564         len32 = buf_size;
2565         align_start = align_end = 0;
2566
2567         if ((align_start = (offset32 & 3))) {
2568                 offset32 &= ~3;
2569                 len32 += align_start;
2570                 if ((rc = bnx2_nvram_read(bp, offset32, start, 4)))
2571                         return rc;
2572         }
2573
2574         if (len32 & 3) {
2575                 if ((len32 > 4) || !align_start) {
2576                         align_end = 4 - (len32 & 3);
2577                         len32 += align_end;
2578                         if ((rc = bnx2_nvram_read(bp, offset32 + len32 - 4,
2579                                 end, 4))) {
2580                                 return rc;
2581                         }
2582                 }
2583         }
2584
2585         if (align_start || align_end) {
2586                 buf = kmalloc(len32, GFP_KERNEL);
2587                 if (buf == 0)
2588                         return -ENOMEM;
2589                 if (align_start) {
2590                         memcpy(buf, start, 4);
2591                 }
2592                 if (align_end) {
2593                         memcpy(buf + len32 - 4, end, 4);
2594                 }
2595                 memcpy(buf + align_start, data_buf, buf_size);
2596         }
2597
2598         written = 0;
2599         while ((written < len32) && (rc == 0)) {
2600                 u32 page_start, page_end, data_start, data_end;
2601                 u32 addr, cmd_flags;
2602                 int i;
2603                 u8 flash_buffer[264];
2604
2605                 /* Find the page_start addr */
2606                 page_start = offset32 + written;
2607                 page_start -= (page_start % bp->flash_info->page_size);
2608                 /* Find the page_end addr */
2609                 page_end = page_start + bp->flash_info->page_size;
2610                 /* Find the data_start addr */
2611                 data_start = (written == 0) ? offset32 : page_start;
2612                 /* Find the data_end addr */
2613                 data_end = (page_end > offset32 + len32) ?
2614                         (offset32 + len32) : page_end;
2615
2616                 /* Request access to the flash interface. */
2617                 if ((rc = bnx2_acquire_nvram_lock(bp)) != 0)
2618                         goto nvram_write_end;
2619
2620                 /* Enable access to flash interface */
2621                 bnx2_enable_nvram_access(bp);
2622
2623                 cmd_flags = BNX2_NVM_COMMAND_FIRST;
2624                 if (bp->flash_info->buffered == 0) {
2625                         int j;
2626
2627                         /* Read the whole page into the buffer
2628                          * (non-buffer flash only) */
2629                         for (j = 0; j < bp->flash_info->page_size; j += 4) {
2630                                 if (j == (bp->flash_info->page_size - 4)) {
2631                                         cmd_flags |= BNX2_NVM_COMMAND_LAST;
2632                                 }
2633                                 rc = bnx2_nvram_read_dword(bp,
2634                                         page_start + j,
2635                                         &flash_buffer[j],
2636                                         cmd_flags);
2637
2638                                 if (rc)
2639                                         goto nvram_write_end;
2640
2641                                 cmd_flags = 0;
2642                         }
2643                 }
2644
2645                 /* Enable writes to flash interface (unlock write-protect) */
2646                 if ((rc = bnx2_enable_nvram_write(bp)) != 0)
2647                         goto nvram_write_end;
2648
2649                 /* Erase the page */
2650                 if ((rc = bnx2_nvram_erase_page(bp, page_start)) != 0)
2651                         goto nvram_write_end;
2652
2653                 /* Re-enable the write again for the actual write */
2654                 bnx2_enable_nvram_write(bp);
2655
2656                 /* Loop to write back the buffer data from page_start to
2657                  * data_start */
2658                 i = 0;
2659                 if (bp->flash_info->buffered == 0) {
2660                         for (addr = page_start; addr < data_start;
2661                                 addr += 4, i += 4) {
2662
2663                                 rc = bnx2_nvram_write_dword(bp, addr,
2664                                         &flash_buffer[i], cmd_flags);
2665
2666                                 if (rc != 0)
2667                                         goto nvram_write_end;
2668
2669                                 cmd_flags = 0;
2670                         }
2671                 }
2672
2673                 /* Loop to write the new data from data_start to data_end */
2674                 for (addr = data_start; addr < data_end; addr += 4, i++) {
2675                         if ((addr == page_end - 4) ||
2676                                 ((bp->flash_info->buffered) &&
2677                                  (addr == data_end - 4))) {
2678
2679                                 cmd_flags |= BNX2_NVM_COMMAND_LAST;
2680                         }
2681                         rc = bnx2_nvram_write_dword(bp, addr, buf,
2682                                 cmd_flags);
2683
2684                         if (rc != 0)
2685                                 goto nvram_write_end;
2686
2687                         cmd_flags = 0;
2688                         buf += 4;
2689                 }
2690
2691                 /* Loop to write back the buffer data from data_end
2692                  * to page_end */
2693                 if (bp->flash_info->buffered == 0) {
2694                         for (addr = data_end; addr < page_end;
2695                                 addr += 4, i += 4) {
2696
2697                                 if (addr == page_end-4) {
2698                                         cmd_flags = BNX2_NVM_COMMAND_LAST;
2699                                 }
2700                                 rc = bnx2_nvram_write_dword(bp, addr,
2701                                         &flash_buffer[i], cmd_flags);
2702
2703                                 if (rc != 0)
2704                                         goto nvram_write_end;
2705
2706                                 cmd_flags = 0;
2707                         }
2708                 }
2709
2710                 /* Disable writes to flash interface (lock write-protect) */
2711                 bnx2_disable_nvram_write(bp);
2712
2713                 /* Disable access to flash interface */
2714                 bnx2_disable_nvram_access(bp);
2715                 bnx2_release_nvram_lock(bp);
2716
2717                 /* Increment written */
2718                 written += data_end - data_start;
2719         }
2720
2721 nvram_write_end:
2722         if (align_start || align_end)
2723                 kfree(buf);
2724         return rc;
2725 }
2726
2727 static int
2728 bnx2_reset_chip(struct bnx2 *bp, u32 reset_code)
2729 {
2730         u32 val;
2731         int i, rc = 0;
2732
2733         /* Wait for the current PCI transaction to complete before
2734          * issuing a reset. */
2735         REG_WR(bp, BNX2_MISC_ENABLE_CLR_BITS,
2736                BNX2_MISC_ENABLE_CLR_BITS_TX_DMA_ENABLE |
2737                BNX2_MISC_ENABLE_CLR_BITS_DMA_ENGINE_ENABLE |
2738                BNX2_MISC_ENABLE_CLR_BITS_RX_DMA_ENABLE |
2739                BNX2_MISC_ENABLE_CLR_BITS_HOST_COALESCE_ENABLE);
2740         val = REG_RD(bp, BNX2_MISC_ENABLE_CLR_BITS);
2741         udelay(5);
2742
2743         /* Deposit a driver reset signature so the firmware knows that
2744          * this is a soft reset. */
2745         REG_WR_IND(bp, HOST_VIEW_SHMEM_BASE + BNX2_DRV_RESET_SIGNATURE,
2746                    BNX2_DRV_RESET_SIGNATURE_MAGIC);
2747
2748         bp->fw_timed_out = 0;
2749
2750         /* Wait for the firmware to tell us it is ok to issue a reset. */
2751         bnx2_fw_sync(bp, BNX2_DRV_MSG_DATA_WAIT0 | reset_code);
2752
2753         /* Do a dummy read to force the chip to complete all current transaction
2754          * before we issue a reset. */
2755         val = REG_RD(bp, BNX2_MISC_ID);
2756
2757         val = BNX2_PCICFG_MISC_CONFIG_CORE_RST_REQ |
2758               BNX2_PCICFG_MISC_CONFIG_REG_WINDOW_ENA |
2759               BNX2_PCICFG_MISC_CONFIG_TARGET_MB_WORD_SWAP;
2760
2761         /* Chip reset. */
2762         REG_WR(bp, BNX2_PCICFG_MISC_CONFIG, val);
2763
2764         if ((CHIP_ID(bp) == CHIP_ID_5706_A0) ||
2765             (CHIP_ID(bp) == CHIP_ID_5706_A1))
2766                 msleep(15);
2767
2768         /* Reset takes approximate 30 usec */
2769         for (i = 0; i < 10; i++) {
2770                 val = REG_RD(bp, BNX2_PCICFG_MISC_CONFIG);
2771                 if ((val & (BNX2_PCICFG_MISC_CONFIG_CORE_RST_REQ |
2772                             BNX2_PCICFG_MISC_CONFIG_CORE_RST_BSY)) == 0) {
2773                         break;
2774                 }
2775                 udelay(10);
2776         }
2777
2778         if (val & (BNX2_PCICFG_MISC_CONFIG_CORE_RST_REQ |
2779                    BNX2_PCICFG_MISC_CONFIG_CORE_RST_BSY)) {
2780                 printk(KERN_ERR PFX "Chip reset did not complete\n");
2781                 return -EBUSY;
2782         }
2783
2784         /* Make sure byte swapping is properly configured. */
2785         val = REG_RD(bp, BNX2_PCI_SWAP_DIAG0);
2786         if (val != 0x01020304) {
2787                 printk(KERN_ERR PFX "Chip not in correct endian mode\n");
2788                 return -ENODEV;
2789         }
2790
2791         bp->fw_timed_out = 0;
2792
2793         /* Wait for the firmware to finish its initialization. */
2794         bnx2_fw_sync(bp, BNX2_DRV_MSG_DATA_WAIT1 | reset_code);
2795
2796         if (CHIP_ID(bp) == CHIP_ID_5706_A0) {
2797                 /* Adjust the voltage regular to two steps lower.  The default
2798                  * of this register is 0x0000000e. */
2799                 REG_WR(bp, BNX2_MISC_VREG_CONTROL, 0x000000fa);
2800
2801                 /* Remove bad rbuf memory from the free pool. */
2802                 rc = bnx2_alloc_bad_rbuf(bp);
2803         }
2804
2805         return rc;
2806 }
2807
2808 static int
2809 bnx2_init_chip(struct bnx2 *bp)
2810 {
2811         u32 val;
2812
2813         /* Make sure the interrupt is not active. */
2814         REG_WR(bp, BNX2_PCICFG_INT_ACK_CMD, BNX2_PCICFG_INT_ACK_CMD_MASK_INT);
2815
2816         val = BNX2_DMA_CONFIG_DATA_BYTE_SWAP |
2817               BNX2_DMA_CONFIG_DATA_WORD_SWAP |
2818 #ifdef __BIG_ENDIAN
2819               BNX2_DMA_CONFIG_CNTL_BYTE_SWAP |
2820 #endif
2821               BNX2_DMA_CONFIG_CNTL_WORD_SWAP |
2822               DMA_READ_CHANS << 12 |
2823               DMA_WRITE_CHANS << 16;
2824
2825         val |= (0x2 << 20) | (1 << 11);
2826
2827         if ((bp->flags & PCIX_FLAG) && (bp->bus_speed_mhz = 133))
2828                 val |= (1 << 23);
2829
2830         if ((CHIP_NUM(bp) == CHIP_NUM_5706) &&
2831             (CHIP_ID(bp) != CHIP_ID_5706_A0) && !(bp->flags & PCIX_FLAG))
2832                 val |= BNX2_DMA_CONFIG_CNTL_PING_PONG_DMA;
2833
2834         REG_WR(bp, BNX2_DMA_CONFIG, val);
2835
2836         if (CHIP_ID(bp) == CHIP_ID_5706_A0) {
2837                 val = REG_RD(bp, BNX2_TDMA_CONFIG);
2838                 val |= BNX2_TDMA_CONFIG_ONE_DMA;
2839                 REG_WR(bp, BNX2_TDMA_CONFIG, val);
2840         }
2841
2842         if (bp->flags & PCIX_FLAG) {
2843                 u16 val16;
2844
2845                 pci_read_config_word(bp->pdev, bp->pcix_cap + PCI_X_CMD,
2846                                      &val16);
2847                 pci_write_config_word(bp->pdev, bp->pcix_cap + PCI_X_CMD,
2848                                       val16 & ~PCI_X_CMD_ERO);
2849         }
2850
2851         REG_WR(bp, BNX2_MISC_ENABLE_SET_BITS,
2852                BNX2_MISC_ENABLE_SET_BITS_HOST_COALESCE_ENABLE |
2853                BNX2_MISC_ENABLE_STATUS_BITS_RX_V2P_ENABLE |
2854                BNX2_MISC_ENABLE_STATUS_BITS_CONTEXT_ENABLE);
2855
2856         /* Initialize context mapping and zero out the quick contexts.  The
2857          * context block must have already been enabled. */
2858         bnx2_init_context(bp);
2859
2860         bnx2_init_cpus(bp);
2861         bnx2_init_nvram(bp);
2862
2863         bnx2_set_mac_addr(bp);
2864
2865         val = REG_RD(bp, BNX2_MQ_CONFIG);
2866         val &= ~BNX2_MQ_CONFIG_KNL_BYP_BLK_SIZE;
2867         val |= BNX2_MQ_CONFIG_KNL_BYP_BLK_SIZE_256;
2868         REG_WR(bp, BNX2_MQ_CONFIG, val);
2869
2870         val = 0x10000 + (MAX_CID_CNT * MB_KERNEL_CTX_SIZE);
2871         REG_WR(bp, BNX2_MQ_KNL_BYP_WIND_START, val);
2872         REG_WR(bp, BNX2_MQ_KNL_WIND_END, val);
2873
2874         val = (BCM_PAGE_BITS - 8) << 24;
2875         REG_WR(bp, BNX2_RV2P_CONFIG, val);
2876
2877         /* Configure page size. */
2878         val = REG_RD(bp, BNX2_TBDR_CONFIG);
2879         val &= ~BNX2_TBDR_CONFIG_PAGE_SIZE;
2880         val |= (BCM_PAGE_BITS - 8) << 24 | 0x40;
2881         REG_WR(bp, BNX2_TBDR_CONFIG, val);
2882
2883         val = bp->mac_addr[0] +
2884               (bp->mac_addr[1] << 8) +
2885               (bp->mac_addr[2] << 16) +
2886               bp->mac_addr[3] +
2887               (bp->mac_addr[4] << 8) +
2888               (bp->mac_addr[5] << 16);
2889         REG_WR(bp, BNX2_EMAC_BACKOFF_SEED, val);
2890
2891         /* Program the MTU.  Also include 4 bytes for CRC32. */
2892         val = bp->dev->mtu + ETH_HLEN + 4;
2893         if (val > (MAX_ETHERNET_PACKET_SIZE + 4))
2894                 val |= BNX2_EMAC_RX_MTU_SIZE_JUMBO_ENA;
2895         REG_WR(bp, BNX2_EMAC_RX_MTU_SIZE, val);
2896
2897         bp->last_status_idx = 0;
2898         bp->rx_mode = BNX2_EMAC_RX_MODE_SORT_MODE;
2899
2900         /* Set up how to generate a link change interrupt. */
2901         REG_WR(bp, BNX2_EMAC_ATTENTION_ENA, BNX2_EMAC_ATTENTION_ENA_LINK);
2902
2903         REG_WR(bp, BNX2_HC_STATUS_ADDR_L,
2904                (u64) bp->status_blk_mapping & 0xffffffff);
2905         REG_WR(bp, BNX2_HC_STATUS_ADDR_H, (u64) bp->status_blk_mapping >> 32);
2906
2907         REG_WR(bp, BNX2_HC_STATISTICS_ADDR_L,
2908                (u64) bp->stats_blk_mapping & 0xffffffff);
2909         REG_WR(bp, BNX2_HC_STATISTICS_ADDR_H,
2910                (u64) bp->stats_blk_mapping >> 32);
2911
2912         REG_WR(bp, BNX2_HC_TX_QUICK_CONS_TRIP,
2913                (bp->tx_quick_cons_trip_int << 16) | bp->tx_quick_cons_trip);
2914
2915         REG_WR(bp, BNX2_HC_RX_QUICK_CONS_TRIP,
2916                (bp->rx_quick_cons_trip_int << 16) | bp->rx_quick_cons_trip);
2917
2918         REG_WR(bp, BNX2_HC_COMP_PROD_TRIP,
2919                (bp->comp_prod_trip_int << 16) | bp->comp_prod_trip);
2920
2921         REG_WR(bp, BNX2_HC_TX_TICKS, (bp->tx_ticks_int << 16) | bp->tx_ticks);
2922
2923         REG_WR(bp, BNX2_HC_RX_TICKS, (bp->rx_ticks_int << 16) | bp->rx_ticks);
2924
2925         REG_WR(bp, BNX2_HC_COM_TICKS,
2926                (bp->com_ticks_int << 16) | bp->com_ticks);
2927
2928         REG_WR(bp, BNX2_HC_CMD_TICKS,
2929                (bp->cmd_ticks_int << 16) | bp->cmd_ticks);
2930
2931         REG_WR(bp, BNX2_HC_STATS_TICKS, bp->stats_ticks & 0xffff00);
2932         REG_WR(bp, BNX2_HC_STAT_COLLECT_TICKS, 0xbb8);  /* 3ms */
2933
2934         if (CHIP_ID(bp) == CHIP_ID_5706_A1)
2935                 REG_WR(bp, BNX2_HC_CONFIG, BNX2_HC_CONFIG_COLLECT_STATS);
2936         else {
2937                 REG_WR(bp, BNX2_HC_CONFIG, BNX2_HC_CONFIG_RX_TMR_MODE |
2938                        BNX2_HC_CONFIG_TX_TMR_MODE |
2939                        BNX2_HC_CONFIG_COLLECT_STATS);
2940         }
2941
2942         /* Clear internal stats counters. */
2943         REG_WR(bp, BNX2_HC_COMMAND, BNX2_HC_COMMAND_CLR_STAT_NOW);
2944
2945         REG_WR(bp, BNX2_HC_ATTN_BITS_ENABLE, STATUS_ATTN_BITS_LINK_STATE);
2946
2947         /* Initialize the receive filter. */
2948         bnx2_set_rx_mode(bp->dev);
2949
2950         bnx2_fw_sync(bp, BNX2_DRV_MSG_DATA_WAIT2 | BNX2_DRV_MSG_CODE_RESET);
2951
2952         REG_WR(bp, BNX2_MISC_ENABLE_SET_BITS, 0x5ffffff);
2953         REG_RD(bp, BNX2_MISC_ENABLE_SET_BITS);
2954
2955         udelay(20);
2956
2957         return 0;
2958 }
2959
2960
2961 static void
2962 bnx2_init_tx_ring(struct bnx2 *bp)
2963 {
2964         struct tx_bd *txbd;
2965         u32 val;
2966
2967         txbd = &bp->tx_desc_ring[MAX_TX_DESC_CNT];
2968
2969         txbd->tx_bd_haddr_hi = (u64) bp->tx_desc_mapping >> 32;
2970         txbd->tx_bd_haddr_lo = (u64) bp->tx_desc_mapping & 0xffffffff;
2971
2972         bp->tx_prod = 0;
2973         bp->tx_cons = 0;
2974         bp->tx_prod_bseq = 0;
2975
2976         val = BNX2_L2CTX_TYPE_TYPE_L2;
2977         val |= BNX2_L2CTX_TYPE_SIZE_L2;
2978         CTX_WR(bp, GET_CID_ADDR(TX_CID), BNX2_L2CTX_TYPE, val);
2979
2980         val = BNX2_L2CTX_CMD_TYPE_TYPE_L2;
2981         val |= 8 << 16;
2982         CTX_WR(bp, GET_CID_ADDR(TX_CID), BNX2_L2CTX_CMD_TYPE, val);
2983
2984         val = (u64) bp->tx_desc_mapping >> 32;
2985         CTX_WR(bp, GET_CID_ADDR(TX_CID), BNX2_L2CTX_TBDR_BHADDR_HI, val);
2986
2987         val = (u64) bp->tx_desc_mapping & 0xffffffff;
2988         CTX_WR(bp, GET_CID_ADDR(TX_CID), BNX2_L2CTX_TBDR_BHADDR_LO, val);
2989 }
2990
2991 static void
2992 bnx2_init_rx_ring(struct bnx2 *bp)
2993 {
2994         struct rx_bd *rxbd;
2995         int i;
2996         u16 prod, ring_prod;
2997         u32 val;
2998
2999         /* 8 for CRC and VLAN */
3000         bp->rx_buf_use_size = bp->dev->mtu + ETH_HLEN + bp->rx_offset + 8;
3001         /* 8 for alignment */
3002         bp->rx_buf_size = bp->rx_buf_use_size + 8;
3003
3004         ring_prod = prod = bp->rx_prod = 0;
3005         bp->rx_cons = 0;
3006         bp->rx_prod_bseq = 0;
3007
3008         rxbd = &bp->rx_desc_ring[0];
3009         for (i = 0; i < MAX_RX_DESC_CNT; i++, rxbd++) {
3010                 rxbd->rx_bd_len = bp->rx_buf_use_size;
3011                 rxbd->rx_bd_flags = RX_BD_FLAGS_START | RX_BD_FLAGS_END;
3012         }
3013
3014         rxbd->rx_bd_haddr_hi = (u64) bp->rx_desc_mapping >> 32;
3015         rxbd->rx_bd_haddr_lo = (u64) bp->rx_desc_mapping & 0xffffffff;
3016
3017         val = BNX2_L2CTX_CTX_TYPE_CTX_BD_CHN_TYPE_VALUE;
3018         val |= BNX2_L2CTX_CTX_TYPE_SIZE_L2;
3019         val |= 0x02 << 8;
3020         CTX_WR(bp, GET_CID_ADDR(RX_CID), BNX2_L2CTX_CTX_TYPE, val);
3021
3022         val = (u64) bp->rx_desc_mapping >> 32;
3023         CTX_WR(bp, GET_CID_ADDR(RX_CID), BNX2_L2CTX_NX_BDHADDR_HI, val);
3024
3025         val = (u64) bp->rx_desc_mapping & 0xffffffff;
3026         CTX_WR(bp, GET_CID_ADDR(RX_CID), BNX2_L2CTX_NX_BDHADDR_LO, val);
3027
3028         for ( ;ring_prod < bp->rx_ring_size; ) {
3029                 if (bnx2_alloc_rx_skb(bp, ring_prod) < 0) {
3030                         break;
3031                 }
3032                 prod = NEXT_RX_BD(prod);
3033                 ring_prod = RX_RING_IDX(prod);
3034         }
3035         bp->rx_prod = prod;
3036
3037         REG_WR16(bp, MB_RX_CID_ADDR + BNX2_L2CTX_HOST_BDIDX, prod);
3038
3039         REG_WR(bp, MB_RX_CID_ADDR + BNX2_L2CTX_HOST_BSEQ, bp->rx_prod_bseq);
3040 }
3041
3042 static void
3043 bnx2_free_tx_skbs(struct bnx2 *bp)
3044 {
3045         int i;
3046
3047         if (bp->tx_buf_ring == NULL)
3048                 return;
3049
3050         for (i = 0; i < TX_DESC_CNT; ) {
3051                 struct sw_bd *tx_buf = &bp->tx_buf_ring[i];
3052                 struct sk_buff *skb = tx_buf->skb;
3053                 int j, last;
3054
3055                 if (skb == NULL) {
3056                         i++;
3057                         continue;
3058                 }
3059
3060                 pci_unmap_single(bp->pdev, pci_unmap_addr(tx_buf, mapping),
3061                         skb_headlen(skb), PCI_DMA_TODEVICE);
3062
3063                 tx_buf->skb = NULL;
3064
3065                 last = skb_shinfo(skb)->nr_frags;
3066                 for (j = 0; j < last; j++) {
3067                         tx_buf = &bp->tx_buf_ring[i + j + 1];
3068                         pci_unmap_page(bp->pdev,
3069                                 pci_unmap_addr(tx_buf, mapping),
3070                                 skb_shinfo(skb)->frags[j].size,
3071                                 PCI_DMA_TODEVICE);
3072                 }
3073                 dev_kfree_skb_any(skb);
3074                 i += j + 1;
3075         }
3076
3077 }
3078
3079 static void
3080 bnx2_free_rx_skbs(struct bnx2 *bp)
3081 {
3082         int i;
3083
3084         if (bp->rx_buf_ring == NULL)
3085                 return;
3086
3087         for (i = 0; i < RX_DESC_CNT; i++) {
3088                 struct sw_bd *rx_buf = &bp->rx_buf_ring[i];
3089                 struct sk_buff *skb = rx_buf->skb;
3090
3091                 if (skb == 0)
3092                         continue;
3093
3094                 pci_unmap_single(bp->pdev, pci_unmap_addr(rx_buf, mapping),
3095                         bp->rx_buf_use_size, PCI_DMA_FROMDEVICE);
3096
3097                 rx_buf->skb = NULL;
3098
3099                 dev_kfree_skb_any(skb);
3100         }
3101 }
3102
3103 static void
3104 bnx2_free_skbs(struct bnx2 *bp)
3105 {
3106         bnx2_free_tx_skbs(bp);
3107         bnx2_free_rx_skbs(bp);
3108 }
3109
3110 static int
3111 bnx2_reset_nic(struct bnx2 *bp, u32 reset_code)
3112 {
3113         int rc;
3114
3115         rc = bnx2_reset_chip(bp, reset_code);
3116         bnx2_free_skbs(bp);
3117         if (rc)
3118                 return rc;
3119
3120         bnx2_init_chip(bp);
3121         bnx2_init_tx_ring(bp);
3122         bnx2_init_rx_ring(bp);
3123         return 0;
3124 }
3125
3126 static int
3127 bnx2_init_nic(struct bnx2 *bp)
3128 {
3129         int rc;
3130
3131         if ((rc = bnx2_reset_nic(bp, BNX2_DRV_MSG_CODE_RESET)) != 0)
3132                 return rc;
3133
3134         bnx2_init_phy(bp);
3135         bnx2_set_link(bp);
3136         return 0;
3137 }
3138
3139 static int
3140 bnx2_test_registers(struct bnx2 *bp)
3141 {
3142         int ret;
3143         int i;
3144         static struct {
3145                 u16   offset;
3146                 u16   flags;
3147                 u32   rw_mask;
3148                 u32   ro_mask;
3149         } reg_tbl[] = {
3150                 { 0x006c, 0, 0x00000000, 0x0000003f },
3151                 { 0x0090, 0, 0xffffffff, 0x00000000 },
3152                 { 0x0094, 0, 0x00000000, 0x00000000 },
3153
3154                 { 0x0404, 0, 0x00003f00, 0x00000000 },
3155                 { 0x0418, 0, 0x00000000, 0xffffffff },
3156                 { 0x041c, 0, 0x00000000, 0xffffffff },
3157                 { 0x0420, 0, 0x00000000, 0x80ffffff },
3158                 { 0x0424, 0, 0x00000000, 0x00000000 },
3159                 { 0x0428, 0, 0x00000000, 0x00000001 },
3160                 { 0x0450, 0, 0x00000000, 0x0000ffff },
3161                 { 0x0454, 0, 0x00000000, 0xffffffff },
3162                 { 0x0458, 0, 0x00000000, 0xffffffff },
3163
3164                 { 0x0808, 0, 0x00000000, 0xffffffff },
3165                 { 0x0854, 0, 0x00000000, 0xffffffff },
3166                 { 0x0868, 0, 0x00000000, 0x77777777 },
3167                 { 0x086c, 0, 0x00000000, 0x77777777 },
3168                 { 0x0870, 0, 0x00000000, 0x77777777 },
3169                 { 0x0874, 0, 0x00000000, 0x77777777 },
3170
3171                 { 0x0c00, 0, 0x00000000, 0x00000001 },
3172                 { 0x0c04, 0, 0x00000000, 0x03ff0001 },
3173                 { 0x0c08, 0, 0x0f0ff073, 0x00000000 },
3174                 { 0x0c0c, 0, 0x00ffffff, 0x00000000 },
3175                 { 0x0c30, 0, 0x00000000, 0xffffffff },
3176                 { 0x0c34, 0, 0x00000000, 0xffffffff },
3177                 { 0x0c38, 0, 0x00000000, 0xffffffff },
3178                 { 0x0c3c, 0, 0x00000000, 0xffffffff },
3179                 { 0x0c40, 0, 0x00000000, 0xffffffff },
3180                 { 0x0c44, 0, 0x00000000, 0xffffffff },
3181                 { 0x0c48, 0, 0x00000000, 0x0007ffff },
3182                 { 0x0c4c, 0, 0x00000000, 0xffffffff },
3183                 { 0x0c50, 0, 0x00000000, 0xffffffff },
3184                 { 0x0c54, 0, 0x00000000, 0xffffffff },
3185                 { 0x0c58, 0, 0x00000000, 0xffffffff },
3186                 { 0x0c5c, 0, 0x00000000, 0xffffffff },
3187                 { 0x0c60, 0, 0x00000000, 0xffffffff },
3188                 { 0x0c64, 0, 0x00000000, 0xffffffff },
3189                 { 0x0c68, 0, 0x00000000, 0xffffffff },
3190                 { 0x0c6c, 0, 0x00000000, 0xffffffff },
3191                 { 0x0c70, 0, 0x00000000, 0xffffffff },
3192                 { 0x0c74, 0, 0x00000000, 0xffffffff },
3193                 { 0x0c78, 0, 0x00000000, 0xffffffff },
3194                 { 0x0c7c, 0, 0x00000000, 0xffffffff },
3195                 { 0x0c80, 0, 0x00000000, 0xffffffff },
3196                 { 0x0c84, 0, 0x00000000, 0xffffffff },
3197                 { 0x0c88, 0, 0x00000000, 0xffffffff },
3198                 { 0x0c8c, 0, 0x00000000, 0xffffffff },
3199                 { 0x0c90, 0, 0x00000000, 0xffffffff },
3200                 { 0x0c94, 0, 0x00000000, 0xffffffff },
3201                 { 0x0c98, 0, 0x00000000, 0xffffffff },
3202                 { 0x0c9c, 0, 0x00000000, 0xffffffff },
3203                 { 0x0ca0, 0, 0x00000000, 0xffffffff },
3204                 { 0x0ca4, 0, 0x00000000, 0xffffffff },
3205                 { 0x0ca8, 0, 0x00000000, 0x0007ffff },
3206                 { 0x0cac, 0, 0x00000000, 0xffffffff },
3207                 { 0x0cb0, 0, 0x00000000, 0xffffffff },
3208                 { 0x0cb4, 0, 0x00000000, 0xffffffff },
3209                 { 0x0cb8, 0, 0x00000000, 0xffffffff },
3210                 { 0x0cbc, 0, 0x00000000, 0xffffffff },
3211                 { 0x0cc0, 0, 0x00000000, 0xffffffff },
3212                 { 0x0cc4, 0, 0x00000000, 0xffffffff },
3213                 { 0x0cc8, 0, 0x00000000, 0xffffffff },
3214                 { 0x0ccc, 0, 0x00000000, 0xffffffff },
3215                 { 0x0cd0, 0, 0x00000000, 0xffffffff },
3216                 { 0x0cd4, 0, 0x00000000, 0xffffffff },
3217                 { 0x0cd8, 0, 0x00000000, 0xffffffff },
3218                 { 0x0cdc, 0, 0x00000000, 0xffffffff },
3219                 { 0x0ce0, 0, 0x00000000, 0xffffffff },
3220                 { 0x0ce4, 0, 0x00000000, 0xffffffff },
3221                 { 0x0ce8, 0, 0x00000000, 0xffffffff },
3222                 { 0x0cec, 0, 0x00000000, 0xffffffff },
3223                 { 0x0cf0, 0, 0x00000000, 0xffffffff },
3224                 { 0x0cf4, 0, 0x00000000, 0xffffffff },
3225                 { 0x0cf8, 0, 0x00000000, 0xffffffff },
3226                 { 0x0cfc, 0, 0x00000000, 0xffffffff },
3227                 { 0x0d00, 0, 0x00000000, 0xffffffff },
3228                 { 0x0d04, 0, 0x00000000, 0xffffffff },
3229
3230                 { 0x1000, 0, 0x00000000, 0x00000001 },
3231                 { 0x1004, 0, 0x00000000, 0x000f0001 },
3232                 { 0x1044, 0, 0x00000000, 0xffc003ff },
3233                 { 0x1080, 0, 0x00000000, 0x0001ffff },
3234                 { 0x1084, 0, 0x00000000, 0xffffffff },
3235                 { 0x1088, 0, 0x00000000, 0xffffffff },
3236                 { 0x108c, 0, 0x00000000, 0xffffffff },
3237                 { 0x1090, 0, 0x00000000, 0xffffffff },
3238                 { 0x1094, 0, 0x00000000, 0xffffffff },
3239                 { 0x1098, 0, 0x00000000, 0xffffffff },
3240                 { 0x109c, 0, 0x00000000, 0xffffffff },
3241                 { 0x10a0, 0, 0x00000000, 0xffffffff },
3242
3243                 { 0x1408, 0, 0x01c00800, 0x00000000 },
3244                 { 0x149c, 0, 0x8000ffff, 0x00000000 },
3245                 { 0x14a8, 0, 0x00000000, 0x000001ff },
3246                 { 0x14ac, 0, 0x4fffffff, 0x10000000 },
3247                 { 0x14b0, 0, 0x00000002, 0x00000001 },
3248                 { 0x14b8, 0, 0x00000000, 0x00000000 },
3249                 { 0x14c0, 0, 0x00000000, 0x00000009 },
3250                 { 0x14c4, 0, 0x00003fff, 0x00000000 },
3251                 { 0x14cc, 0, 0x00000000, 0x00000001 },
3252                 { 0x14d0, 0, 0xffffffff, 0x00000000 },
3253                 { 0x1500, 0, 0x00000000, 0xffffffff },
3254                 { 0x1504, 0, 0x00000000, 0xffffffff },
3255                 { 0x1508, 0, 0x00000000, 0xffffffff },
3256                 { 0x150c, 0, 0x00000000, 0xffffffff },
3257                 { 0x1510, 0, 0x00000000, 0xffffffff },
3258                 { 0x1514, 0, 0x00000000, 0xffffffff },
3259                 { 0x1518, 0, 0x00000000, 0xffffffff },
3260                 { 0x151c, 0, 0x00000000, 0xffffffff },
3261                 { 0x1520, 0, 0x00000000, 0xffffffff },
3262                 { 0x1524, 0, 0x00000000, 0xffffffff },
3263                 { 0x1528, 0, 0x00000000, 0xffffffff },
3264                 { 0x152c, 0, 0x00000000, 0xffffffff },
3265                 { 0x1530, 0, 0x00000000, 0xffffffff },
3266                 { 0x1534, 0, 0x00000000, 0xffffffff },
3267                 { 0x1538, 0, 0x00000000, 0xffffffff },
3268                 { 0x153c, 0, 0x00000000, 0xffffffff },
3269                 { 0x1540, 0, 0x00000000, 0xffffffff },
3270                 { 0x1544, 0, 0x00000000, 0xffffffff },
3271                 { 0x1548, 0, 0x00000000, 0xffffffff },
3272                 { 0x154c, 0, 0x00000000, 0xffffffff },
3273                 { 0x1550, 0, 0x00000000, 0xffffffff },
3274                 { 0x1554, 0, 0x00000000, 0xffffffff },
3275                 { 0x1558, 0, 0x00000000, 0xffffffff },
3276                 { 0x1600, 0, 0x00000000, 0xffffffff },
3277                 { 0x1604, 0, 0x00000000, 0xffffffff },
3278                 { 0x1608, 0, 0x00000000, 0xffffffff },
3279                 { 0x160c, 0, 0x00000000, 0xffffffff },
3280                 { 0x1610, 0, 0x00000000, 0xffffffff },
3281                 { 0x1614, 0, 0x00000000, 0xffffffff },
3282                 { 0x1618, 0, 0x00000000, 0xffffffff },
3283                 { 0x161c, 0, 0x00000000, 0xffffffff },
3284                 { 0x1620, 0, 0x00000000, 0xffffffff },
3285                 { 0x1624, 0, 0x00000000, 0xffffffff },
3286                 { 0x1628, 0, 0x00000000, 0xffffffff },
3287                 { 0x162c, 0, 0x00000000, 0xffffffff },
3288                 { 0x1630, 0, 0x00000000, 0xffffffff },
3289                 { 0x1634, 0, 0x00000000, 0xffffffff },
3290                 { 0x1638, 0, 0x00000000, 0xffffffff },
3291                 { 0x163c, 0, 0x00000000, 0xffffffff },
3292                 { 0x1640, 0, 0x00000000, 0xffffffff },
3293                 { 0x1644, 0, 0x00000000, 0xffffffff },
3294                 { 0x1648, 0, 0x00000000, 0xffffffff },
3295                 { 0x164c, 0, 0x00000000, 0xffffffff },
3296                 { 0x1650, 0, 0x00000000, 0xffffffff },
3297                 { 0x1654, 0, 0x00000000, 0xffffffff },
3298
3299                 { 0x1800, 0, 0x00000000, 0x00000001 },
3300                 { 0x1804, 0, 0x00000000, 0x00000003 },
3301                 { 0x1840, 0, 0x00000000, 0xffffffff },
3302                 { 0x1844, 0, 0x00000000, 0xffffffff },
3303                 { 0x1848, 0, 0x00000000, 0xffffffff },
3304                 { 0x184c, 0, 0x00000000, 0xffffffff },
3305                 { 0x1850, 0, 0x00000000, 0xffffffff },
3306                 { 0x1900, 0, 0x7ffbffff, 0x00000000 },
3307                 { 0x1904, 0, 0xffffffff, 0x00000000 },
3308                 { 0x190c, 0, 0xffffffff, 0x00000000 },
3309                 { 0x1914, 0, 0xffffffff, 0x00000000 },
3310                 { 0x191c, 0, 0xffffffff, 0x00000000 },
3311                 { 0x1924, 0, 0xffffffff, 0x00000000 },
3312                 { 0x192c, 0, 0xffffffff, 0x00000000 },
3313                 { 0x1934, 0, 0xffffffff, 0x00000000 },
3314                 { 0x193c, 0, 0xffffffff, 0x00000000 },
3315                 { 0x1944, 0, 0xffffffff, 0x00000000 },
3316                 { 0x194c, 0, 0xffffffff, 0x00000000 },
3317                 { 0x1954, 0, 0xffffffff, 0x00000000 },
3318                 { 0x195c, 0, 0xffffffff, 0x00000000 },
3319                 { 0x1964, 0, 0xffffffff, 0x00000000 },
3320                 { 0x196c, 0, 0xffffffff, 0x00000000 },
3321                 { 0x1974, 0, 0xffffffff, 0x00000000 },
3322                 { 0x197c, 0, 0xffffffff, 0x00000000 },
3323                 { 0x1980, 0, 0x0700ffff, 0x00000000 },
3324
3325                 { 0x1c00, 0, 0x00000000, 0x00000001 },
3326                 { 0x1c04, 0, 0x00000000, 0x00000003 },
3327                 { 0x1c08, 0, 0x0000000f, 0x00000000 },
3328                 { 0x1c40, 0, 0x00000000, 0xffffffff },
3329                 { 0x1c44, 0, 0x00000000, 0xffffffff },
3330                 { 0x1c48, 0, 0x00000000, 0xffffffff },
3331                 { 0x1c4c, 0, 0x00000000, 0xffffffff },
3332                 { 0x1c50, 0, 0x00000000, 0xffffffff },
3333                 { 0x1d00, 0, 0x7ffbffff, 0x00000000 },
3334                 { 0x1d04, 0, 0xffffffff, 0x00000000 },
3335                 { 0x1d0c, 0, 0xffffffff, 0x00000000 },
3336                 { 0x1d14, 0, 0xffffffff, 0x00000000 },
3337                 { 0x1d1c, 0, 0xffffffff, 0x00000000 },
3338                 { 0x1d24, 0, 0xffffffff, 0x00000000 },
3339                 { 0x1d2c, 0, 0xffffffff, 0x00000000 },
3340                 { 0x1d34, 0, 0xffffffff, 0x00000000 },
3341                 { 0x1d3c, 0, 0xffffffff, 0x00000000 },
3342                 { 0x1d44, 0, 0xffffffff, 0x00000000 },
3343                 { 0x1d4c, 0, 0xffffffff, 0x00000000 },
3344                 { 0x1d54, 0, 0xffffffff, 0x00000000 },
3345                 { 0x1d5c, 0, 0xffffffff, 0x00000000 },
3346                 { 0x1d64, 0, 0xffffffff, 0x00000000 },
3347                 { 0x1d6c, 0, 0xffffffff, 0x00000000 },
3348                 { 0x1d74, 0, 0xffffffff, 0x00000000 },
3349                 { 0x1d7c, 0, 0xffffffff, 0x00000000 },
3350                 { 0x1d80, 0, 0x0700ffff, 0x00000000 },
3351
3352                 { 0x2004, 0, 0x00000000, 0x0337000f },
3353                 { 0x2008, 0, 0xffffffff, 0x00000000 },
3354                 { 0x200c, 0, 0xffffffff, 0x00000000 },
3355                 { 0x2010, 0, 0xffffffff, 0x00000000 },
3356                 { 0x2014, 0, 0x801fff80, 0x00000000 },
3357                 { 0x2018, 0, 0x000003ff, 0x00000000 },
3358
3359                 { 0x2800, 0, 0x00000000, 0x00000001 },
3360                 { 0x2804, 0, 0x00000000, 0x00003f01 },
3361                 { 0x2808, 0, 0x0f3f3f03, 0x00000000 },
3362                 { 0x2810, 0, 0xffff0000, 0x00000000 },
3363                 { 0x2814, 0, 0xffff0000, 0x00000000 },
3364                 { 0x2818, 0, 0xffff0000, 0x00000000 },
3365                 { 0x281c, 0, 0xffff0000, 0x00000000 },
3366                 { 0x2834, 0, 0xffffffff, 0x00000000 },
3367                 { 0x2840, 0, 0x00000000, 0xffffffff },
3368                 { 0x2844, 0, 0x00000000, 0xffffffff },
3369                 { 0x2848, 0, 0xffffffff, 0x00000000 },
3370                 { 0x284c, 0, 0xf800f800, 0x07ff07ff },
3371
3372                 { 0x2c00, 0, 0x00000000, 0x00000011 },
3373                 { 0x2c04, 0, 0x00000000, 0x00030007 },
3374
3375                 { 0x3000, 0, 0x00000000, 0x00000001 },
3376                 { 0x3004, 0, 0x00000000, 0x007007ff },
3377                 { 0x3008, 0, 0x00000003, 0x00000000 },
3378                 { 0x300c, 0, 0xffffffff, 0x00000000 },
3379                 { 0x3010, 0, 0xffffffff, 0x00000000 },
3380                 { 0x3014, 0, 0xffffffff, 0x00000000 },
3381                 { 0x3034, 0, 0xffffffff, 0x00000000 },
3382                 { 0x3038, 0, 0xffffffff, 0x00000000 },
3383                 { 0x3050, 0, 0x00000001, 0x00000000 },
3384
3385                 { 0x3c00, 0, 0x00000000, 0x00000001 },
3386                 { 0x3c04, 0, 0x00000000, 0x00070000 },
3387                 { 0x3c08, 0, 0x00007f71, 0x07f00000 },
3388                 { 0x3c0c, 0, 0x1f3ffffc, 0x00000000 },
3389                 { 0x3c10, 0, 0xffffffff, 0x00000000 },
3390                 { 0x3c14, 0, 0x00000000, 0xffffffff },
3391                 { 0x3c18, 0, 0x00000000, 0xffffffff },
3392                 { 0x3c1c, 0, 0xfffff000, 0x00000000 },
3393                 { 0x3c20, 0, 0xffffff00, 0x00000000 },
3394                 { 0x3c24, 0, 0xffffffff, 0x00000000 },
3395                 { 0x3c28, 0, 0xffffffff, 0x00000000 },
3396                 { 0x3c2c, 0, 0xffffffff, 0x00000000 },
3397                 { 0x3c30, 0, 0xffffffff, 0x00000000 },
3398                 { 0x3c34, 0, 0xffffffff, 0x00000000 },
3399                 { 0x3c38, 0, 0xffffffff, 0x00000000 },
3400                 { 0x3c3c, 0, 0xffffffff, 0x00000000 },
3401                 { 0x3c40, 0, 0xffffffff, 0x00000000 },
3402                 { 0x3c44, 0, 0xffffffff, 0x00000000 },
3403                 { 0x3c48, 0, 0xffffffff, 0x00000000 },
3404                 { 0x3c4c, 0, 0xffffffff, 0x00000000 },
3405                 { 0x3c50, 0, 0xffffffff, 0x00000000 },
3406                 { 0x3c54, 0, 0xffffffff, 0x00000000 },
3407                 { 0x3c58, 0, 0xffffffff, 0x00000000 },
3408                 { 0x3c5c, 0, 0xffffffff, 0x00000000 },
3409                 { 0x3c60, 0, 0xffffffff, 0x00000000 },
3410                 { 0x3c64, 0, 0xffffffff, 0x00000000 },
3411                 { 0x3c68, 0, 0xffffffff, 0x00000000 },
3412                 { 0x3c6c, 0, 0xffffffff, 0x00000000 },
3413                 { 0x3c70, 0, 0xffffffff, 0x00000000 },
3414                 { 0x3c74, 0, 0x0000003f, 0x00000000 },
3415                 { 0x3c78, 0, 0x00000000, 0x00000000 },
3416                 { 0x3c7c, 0, 0x00000000, 0x00000000 },
3417                 { 0x3c80, 0, 0x3fffffff, 0x00000000 },
3418                 { 0x3c84, 0, 0x0000003f, 0x00000000 },
3419                 { 0x3c88, 0, 0x00000000, 0xffffffff },
3420                 { 0x3c8c, 0, 0x00000000, 0xffffffff },
3421
3422                 { 0x4000, 0, 0x00000000, 0x00000001 },
3423                 { 0x4004, 0, 0x00000000, 0x00030000 },
3424                 { 0x4008, 0, 0x00000ff0, 0x00000000 },
3425                 { 0x400c, 0, 0xffffffff, 0x00000000 },
3426                 { 0x4088, 0, 0x00000000, 0x00070303 },
3427
3428                 { 0x4400, 0, 0x00000000, 0x00000001 },
3429                 { 0x4404, 0, 0x00000000, 0x00003f01 },
3430                 { 0x4408, 0, 0x7fff00ff, 0x00000000 },
3431                 { 0x440c, 0, 0xffffffff, 0x00000000 },
3432                 { 0x4410, 0, 0xffff,     0x0000 },
3433                 { 0x4414, 0, 0xffff,     0x0000 },
3434                 { 0x4418, 0, 0xffff,     0x0000 },
3435                 { 0x441c, 0, 0xffff,     0x0000 },
3436                 { 0x4428, 0, 0xffffffff, 0x00000000 },
3437                 { 0x442c, 0, 0xffffffff, 0x00000000 },
3438                 { 0x4430, 0, 0xffffffff, 0x00000000 },
3439                 { 0x4434, 0, 0xffffffff, 0x00000000 },
3440                 { 0x4438, 0, 0xffffffff, 0x00000000 },
3441                 { 0x443c, 0, 0xffffffff, 0x00000000 },
3442                 { 0x4440, 0, 0xffffffff, 0x00000000 },
3443                 { 0x4444, 0, 0xffffffff, 0x00000000 },
3444
3445                 { 0x4c00, 0, 0x00000000, 0x00000001 },
3446                 { 0x4c04, 0, 0x00000000, 0x0000003f },
3447                 { 0x4c08, 0, 0xffffffff, 0x00000000 },
3448                 { 0x4c0c, 0, 0x0007fc00, 0x00000000 },
3449                 { 0x4c10, 0, 0x80003fe0, 0x00000000 },
3450                 { 0x4c14, 0, 0xffffffff, 0x00000000 },
3451                 { 0x4c44, 0, 0x00000000, 0x9fff9fff },
3452                 { 0x4c48, 0, 0x00000000, 0xb3009fff },
3453                 { 0x4c4c, 0, 0x00000000, 0x77f33b30 },
3454                 { 0x4c50, 0, 0x00000000, 0xffffffff },
3455
3456                 { 0x5004, 0, 0x00000000, 0x0000007f },
3457                 { 0x5008, 0, 0x0f0007ff, 0x00000000 },
3458                 { 0x500c, 0, 0xf800f800, 0x07ff07ff },
3459
3460                 { 0x5400, 0, 0x00000008, 0x00000001 },
3461                 { 0x5404, 0, 0x00000000, 0x0000003f },
3462                 { 0x5408, 0, 0x0000001f, 0x00000000 },
3463                 { 0x540c, 0, 0xffffffff, 0x00000000 },
3464                 { 0x5410, 0, 0xffffffff, 0x00000000 },
3465                 { 0x5414, 0, 0x0000ffff, 0x00000000 },
3466                 { 0x5418, 0, 0x0000ffff, 0x00000000 },
3467                 { 0x541c, 0, 0x0000ffff, 0x00000000 },
3468                 { 0x5420, 0, 0x0000ffff, 0x00000000 },
3469                 { 0x5428, 0, 0x000000ff, 0x00000000 },
3470                 { 0x542c, 0, 0xff00ffff, 0x00000000 },
3471                 { 0x5430, 0, 0x001fff80, 0x00000000 },
3472                 { 0x5438, 0, 0xffffffff, 0x00000000 },
3473                 { 0x543c, 0, 0xffffffff, 0x00000000 },
3474                 { 0x5440, 0, 0xf800f800, 0x07ff07ff },
3475
3476                 { 0x5c00, 0, 0x00000000, 0x00000001 },
3477                 { 0x5c04, 0, 0x00000000, 0x0003000f },
3478                 { 0x5c08, 0, 0x00000003, 0x00000000 },
3479                 { 0x5c0c, 0, 0x0000fff8, 0x00000000 },
3480                 { 0x5c10, 0, 0x00000000, 0xffffffff },
3481                 { 0x5c80, 0, 0x00000000, 0x0f7113f1 },
3482                 { 0x5c84, 0, 0x00000000, 0x0000f333 },
3483                 { 0x5c88, 0, 0x00000000, 0x00077373 },
3484                 { 0x5c8c, 0, 0x00000000, 0x0007f737 },
3485
3486                 { 0x6808, 0, 0x0000ff7f, 0x00000000 },
3487                 { 0x680c, 0, 0xffffffff, 0x00000000 },
3488                 { 0x6810, 0, 0xffffffff, 0x00000000 },
3489                 { 0x6814, 0, 0xffffffff, 0x00000000 },
3490                 { 0x6818, 0, 0xffffffff, 0x00000000 },
3491                 { 0x681c, 0, 0xffffffff, 0x00000000 },
3492                 { 0x6820, 0, 0x00ff00ff, 0x00000000 },
3493                 { 0x6824, 0, 0x00ff00ff, 0x00000000 },
3494                 { 0x6828, 0, 0x00ff00ff, 0x00000000 },
3495                 { 0x682c, 0, 0x03ff03ff, 0x00000000 },
3496                 { 0x6830, 0, 0x03ff03ff, 0x00000000 },
3497                 { 0x6834, 0, 0x03ff03ff, 0x00000000 },
3498                 { 0x6838, 0, 0x03ff03ff, 0x00000000 },
3499                 { 0x683c, 0, 0x0000ffff, 0x00000000 },
3500                 { 0x6840, 0, 0x00000ff0, 0x00000000 },
3501                 { 0x6844, 0, 0x00ffff00, 0x00000000 },
3502                 { 0x684c, 0, 0xffffffff, 0x00000000 },
3503                 { 0x6850, 0, 0x7f7f7f7f, 0x00000000 },
3504                 { 0x6854, 0, 0x7f7f7f7f, 0x00000000 },
3505                 { 0x6858, 0, 0x7f7f7f7f, 0x00000000 },
3506                 { 0x685c, 0, 0x7f7f7f7f, 0x00000000 },
3507                 { 0x6908, 0, 0x00000000, 0x0001ff0f },
3508                 { 0x690c, 0, 0x00000000, 0x0ffe00f0 },
3509
3510                 { 0xffff, 0, 0x00000000, 0x00000000 },
3511         };
3512
3513         ret = 0;
3514         for (i = 0; reg_tbl[i].offset != 0xffff; i++) {
3515                 u32 offset, rw_mask, ro_mask, save_val, val;
3516
3517                 offset = (u32) reg_tbl[i].offset;
3518                 rw_mask = reg_tbl[i].rw_mask;
3519                 ro_mask = reg_tbl[i].ro_mask;
3520
3521                 save_val = readl(bp->regview + offset);
3522
3523                 writel(0, bp->regview + offset);
3524
3525                 val = readl(bp->regview + offset);
3526                 if ((val & rw_mask) != 0) {
3527                         goto reg_test_err;
3528                 }
3529
3530                 if ((val & ro_mask) != (save_val & ro_mask)) {
3531                         goto reg_test_err;
3532                 }
3533
3534                 writel(0xffffffff, bp->regview + offset);
3535
3536                 val = readl(bp->regview + offset);
3537                 if ((val & rw_mask) != rw_mask) {
3538                         goto reg_test_err;
3539                 }
3540
3541                 if ((val & ro_mask) != (save_val & ro_mask)) {
3542                         goto reg_test_err;
3543                 }
3544
3545                 writel(save_val, bp->regview + offset);
3546                 continue;
3547
3548 reg_test_err:
3549                 writel(save_val, bp->regview + offset);
3550                 ret = -ENODEV;
3551                 break;
3552         }
3553         return ret;
3554 }
3555
3556 static int
3557 bnx2_do_mem_test(struct bnx2 *bp, u32 start, u32 size)
3558 {
3559         static u32 test_pattern[] = { 0x00000000, 0xffffffff, 0x55555555,
3560                 0xaaaaaaaa , 0xaa55aa55, 0x55aa55aa };
3561         int i;
3562
3563         for (i = 0; i < sizeof(test_pattern) / 4; i++) {
3564                 u32 offset;
3565
3566                 for (offset = 0; offset < size; offset += 4) {
3567
3568                         REG_WR_IND(bp, start + offset, test_pattern[i]);
3569
3570                         if (REG_RD_IND(bp, start + offset) !=
3571                                 test_pattern[i]) {
3572                                 return -ENODEV;
3573                         }
3574                 }
3575         }
3576         return 0;
3577 }
3578
3579 static int
3580 bnx2_test_memory(struct bnx2 *bp)
3581 {
3582         int ret = 0;
3583         int i;
3584         static struct {
3585                 u32   offset;
3586                 u32   len;
3587         } mem_tbl[] = {
3588                 { 0x60000,  0x4000 },
3589                 { 0xa0000,  0x4000 },
3590                 { 0xe0000,  0x4000 },
3591                 { 0x120000, 0x4000 },
3592                 { 0x1a0000, 0x4000 },
3593                 { 0x160000, 0x4000 },
3594                 { 0xffffffff, 0    },
3595         };
3596
3597         for (i = 0; mem_tbl[i].offset != 0xffffffff; i++) {
3598                 if ((ret = bnx2_do_mem_test(bp, mem_tbl[i].offset,
3599                         mem_tbl[i].len)) != 0) {
3600                         return ret;
3601                 }
3602         }
3603
3604         return ret;
3605 }
3606
3607 static int
3608 bnx2_test_loopback(struct bnx2 *bp)
3609 {
3610         unsigned int pkt_size, num_pkts, i;
3611         struct sk_buff *skb, *rx_skb;
3612         unsigned char *packet;
3613         u16 rx_start_idx, rx_idx, send_idx;
3614         u32 send_bseq, val;
3615         dma_addr_t map;
3616         struct tx_bd *txbd;
3617         struct sw_bd *rx_buf;
3618         struct l2_fhdr *rx_hdr;
3619         int ret = -ENODEV;
3620
3621         if (!netif_running(bp->dev))
3622                 return -ENODEV;
3623
3624         bp->loopback = MAC_LOOPBACK;
3625         bnx2_reset_nic(bp, BNX2_DRV_MSG_CODE_DIAG);
3626         bnx2_set_mac_loopback(bp);
3627
3628         pkt_size = 1514;
3629         skb = dev_alloc_skb(pkt_size);
3630         packet = skb_put(skb, pkt_size);
3631         memcpy(packet, bp->mac_addr, 6);
3632         memset(packet + 6, 0x0, 8);
3633         for (i = 14; i < pkt_size; i++)
3634                 packet[i] = (unsigned char) (i & 0xff);
3635
3636         map = pci_map_single(bp->pdev, skb->data, pkt_size,
3637                 PCI_DMA_TODEVICE);
3638
3639         val = REG_RD(bp, BNX2_HC_COMMAND);
3640         REG_WR(bp, BNX2_HC_COMMAND, val | BNX2_HC_COMMAND_COAL_NOW_WO_INT);
3641         REG_RD(bp, BNX2_HC_COMMAND);
3642
3643         udelay(5);
3644         rx_start_idx = bp->status_blk->status_rx_quick_consumer_index0;
3645
3646         send_idx = 0;
3647         send_bseq = 0;
3648         num_pkts = 0;
3649
3650         txbd = &bp->tx_desc_ring[send_idx];
3651
3652         txbd->tx_bd_haddr_hi = (u64) map >> 32;
3653         txbd->tx_bd_haddr_lo = (u64) map & 0xffffffff;
3654         txbd->tx_bd_mss_nbytes = pkt_size;
3655         txbd->tx_bd_vlan_tag_flags = TX_BD_FLAGS_START | TX_BD_FLAGS_END;
3656
3657         num_pkts++;
3658         send_idx = NEXT_TX_BD(send_idx);
3659
3660         send_bseq += pkt_size;
3661
3662         REG_WR16(bp, MB_TX_CID_ADDR + BNX2_L2CTX_TX_HOST_BIDX, send_idx);
3663         REG_WR(bp, MB_TX_CID_ADDR + BNX2_L2CTX_TX_HOST_BSEQ, send_bseq);
3664
3665
3666         udelay(100);
3667
3668         val = REG_RD(bp, BNX2_HC_COMMAND);
3669         REG_WR(bp, BNX2_HC_COMMAND, val | BNX2_HC_COMMAND_COAL_NOW_WO_INT);
3670         REG_RD(bp, BNX2_HC_COMMAND);
3671
3672         udelay(5);
3673
3674         pci_unmap_single(bp->pdev, map, pkt_size, PCI_DMA_TODEVICE);
3675         dev_kfree_skb_irq(skb);
3676
3677         if (bp->status_blk->status_tx_quick_consumer_index0 != send_idx) {
3678                 goto loopback_test_done;
3679         }
3680
3681         rx_idx = bp->status_blk->status_rx_quick_consumer_index0;
3682         if (rx_idx != rx_start_idx + num_pkts) {
3683                 goto loopback_test_done;
3684         }
3685
3686         rx_buf = &bp->rx_buf_ring[rx_start_idx];
3687         rx_skb = rx_buf->skb;
3688
3689         rx_hdr = (struct l2_fhdr *) rx_skb->data;
3690         skb_reserve(rx_skb, bp->rx_offset);
3691
3692         pci_dma_sync_single_for_cpu(bp->pdev,
3693                 pci_unmap_addr(rx_buf, mapping),
3694                 bp->rx_buf_size, PCI_DMA_FROMDEVICE);
3695
3696         if (rx_hdr->l2_fhdr_errors &
3697                 (L2_FHDR_ERRORS_BAD_CRC |
3698                 L2_FHDR_ERRORS_PHY_DECODE |
3699                 L2_FHDR_ERRORS_ALIGNMENT |
3700                 L2_FHDR_ERRORS_TOO_SHORT |
3701                 L2_FHDR_ERRORS_GIANT_FRAME)) {
3702
3703                 goto loopback_test_done;
3704         }
3705
3706         if ((rx_hdr->l2_fhdr_pkt_len - 4) != pkt_size) {
3707                 goto loopback_test_done;
3708         }
3709
3710         for (i = 14; i < pkt_size; i++) {
3711                 if (*(rx_skb->data + i) != (unsigned char) (i & 0xff)) {
3712                         goto loopback_test_done;
3713                 }
3714         }
3715
3716         ret = 0;
3717
3718 loopback_test_done:
3719         bp->loopback = 0;
3720         return ret;
3721 }
3722
3723 #define NVRAM_SIZE 0x200
3724 #define CRC32_RESIDUAL 0xdebb20e3
3725
3726 static int
3727 bnx2_test_nvram(struct bnx2 *bp)
3728 {
3729         u32 buf[NVRAM_SIZE / 4];
3730         u8 *data = (u8 *) buf;
3731         int rc = 0;
3732         u32 magic, csum;
3733
3734         if ((rc = bnx2_nvram_read(bp, 0, data, 4)) != 0)
3735                 goto test_nvram_done;
3736
3737         magic = be32_to_cpu(buf[0]);
3738         if (magic != 0x669955aa) {
3739                 rc = -ENODEV;
3740                 goto test_nvram_done;
3741         }
3742
3743         if ((rc = bnx2_nvram_read(bp, 0x100, data, NVRAM_SIZE)) != 0)
3744                 goto test_nvram_done;
3745
3746         csum = ether_crc_le(0x100, data);
3747         if (csum != CRC32_RESIDUAL) {
3748                 rc = -ENODEV;
3749                 goto test_nvram_done;
3750         }
3751
3752         csum = ether_crc_le(0x100, data + 0x100);
3753         if (csum != CRC32_RESIDUAL) {
3754                 rc = -ENODEV;
3755         }
3756
3757 test_nvram_done:
3758         return rc;
3759 }
3760
3761 static int
3762 bnx2_test_link(struct bnx2 *bp)
3763 {
3764         u32 bmsr;
3765
3766         spin_lock_bh(&bp->phy_lock);
3767         bnx2_read_phy(bp, MII_BMSR, &bmsr);
3768         bnx2_read_phy(bp, MII_BMSR, &bmsr);
3769         spin_unlock_bh(&bp->phy_lock);
3770
3771         if (bmsr & BMSR_LSTATUS) {
3772                 return 0;
3773         }
3774         return -ENODEV;
3775 }
3776
3777 static int
3778 bnx2_test_intr(struct bnx2 *bp)
3779 {
3780         int i;
3781         u32 val;
3782         u16 status_idx;
3783
3784         if (!netif_running(bp->dev))
3785                 return -ENODEV;
3786
3787         status_idx = REG_RD(bp, BNX2_PCICFG_INT_ACK_CMD) & 0xffff;
3788
3789         /* This register is not touched during run-time. */
3790         val = REG_RD(bp, BNX2_HC_COMMAND);
3791         REG_WR(bp, BNX2_HC_COMMAND, val | BNX2_HC_COMMAND_COAL_NOW);
3792         REG_RD(bp, BNX2_HC_COMMAND);
3793
3794         for (i = 0; i < 10; i++) {
3795                 if ((REG_RD(bp, BNX2_PCICFG_INT_ACK_CMD) & 0xffff) !=
3796                         status_idx) {
3797
3798                         break;
3799                 }
3800
3801                 msleep_interruptible(10);
3802         }
3803         if (i < 10)
3804                 return 0;
3805
3806         return -ENODEV;
3807 }
3808
3809 static void
3810 bnx2_timer(unsigned long data)
3811 {
3812         struct bnx2 *bp = (struct bnx2 *) data;
3813         u32 msg;
3814
3815         if (!netif_running(bp->dev))
3816                 return;
3817
3818         if (atomic_read(&bp->intr_sem) != 0)
3819                 goto bnx2_restart_timer;
3820
3821         msg = (u32) ++bp->fw_drv_pulse_wr_seq;
3822         REG_WR_IND(bp, HOST_VIEW_SHMEM_BASE + BNX2_DRV_PULSE_MB, msg);
3823
3824         if ((bp->phy_flags & PHY_SERDES_FLAG) &&
3825             (CHIP_NUM(bp) == CHIP_NUM_5706)) {
3826
3827                 spin_lock(&bp->phy_lock);
3828                 if (bp->serdes_an_pending) {
3829                         bp->serdes_an_pending--;
3830                 }
3831                 else if ((bp->link_up == 0) && (bp->autoneg & AUTONEG_SPEED)) {
3832                         u32 bmcr;
3833
3834                         bp->current_interval = bp->timer_interval;
3835
3836                         bnx2_read_phy(bp, MII_BMCR, &bmcr);
3837
3838                         if (bmcr & BMCR_ANENABLE) {
3839                                 u32 phy1, phy2;
3840
3841                                 bnx2_write_phy(bp, 0x1c, 0x7c00);
3842                                 bnx2_read_phy(bp, 0x1c, &phy1);
3843
3844                                 bnx2_write_phy(bp, 0x17, 0x0f01);
3845                                 bnx2_read_phy(bp, 0x15, &phy2);
3846                                 bnx2_write_phy(bp, 0x17, 0x0f01);
3847                                 bnx2_read_phy(bp, 0x15, &phy2);
3848
3849                                 if ((phy1 & 0x10) &&    /* SIGNAL DETECT */
3850                                         !(phy2 & 0x20)) {       /* no CONFIG */
3851
3852                                         bmcr &= ~BMCR_ANENABLE;
3853                                         bmcr |= BMCR_SPEED1000 |
3854                                                 BMCR_FULLDPLX;
3855                                         bnx2_write_phy(bp, MII_BMCR, bmcr);
3856                                         bp->phy_flags |=
3857                                                 PHY_PARALLEL_DETECT_FLAG;
3858                                 }
3859                         }
3860                 }
3861                 else if ((bp->link_up) && (bp->autoneg & AUTONEG_SPEED) &&
3862                         (bp->phy_flags & PHY_PARALLEL_DETECT_FLAG)) {
3863                         u32 phy2;
3864
3865                         bnx2_write_phy(bp, 0x17, 0x0f01);
3866                         bnx2_read_phy(bp, 0x15, &phy2);
3867                         if (phy2 & 0x20) {
3868                                 u32 bmcr;
3869
3870                                 bnx2_read_phy(bp, MII_BMCR, &bmcr);
3871                                 bmcr |= BMCR_ANENABLE;
3872                                 bnx2_write_phy(bp, MII_BMCR, bmcr);
3873
3874                                 bp->phy_flags &= ~PHY_PARALLEL_DETECT_FLAG;
3875
3876                         }
3877                 }
3878                 else
3879                         bp->current_interval = bp->timer_interval;
3880
3881                 spin_unlock(&bp->phy_lock);
3882         }
3883
3884 bnx2_restart_timer:
3885         mod_timer(&bp->timer, jiffies + bp->current_interval);
3886 }
3887
3888 /* Called with rtnl_lock */
3889 static int
3890 bnx2_open(struct net_device *dev)
3891 {
3892         struct bnx2 *bp = dev->priv;
3893         int rc;
3894
3895         bnx2_set_power_state(bp, 0);
3896         bnx2_disable_int(bp);
3897
3898         rc = bnx2_alloc_mem(bp);
3899         if (rc)
3900                 return rc;
3901
3902         if ((CHIP_ID(bp) != CHIP_ID_5706_A0) &&
3903                 (CHIP_ID(bp) != CHIP_ID_5706_A1) &&
3904                 !disable_msi) {
3905
3906                 if (pci_enable_msi(bp->pdev) == 0) {
3907                         bp->flags |= USING_MSI_FLAG;
3908                         rc = request_irq(bp->pdev->irq, bnx2_msi, 0, dev->name,
3909                                         dev);
3910                 }
3911                 else {
3912                         rc = request_irq(bp->pdev->irq, bnx2_interrupt,
3913                                         SA_SHIRQ, dev->name, dev);
3914                 }
3915         }
3916         else {
3917                 rc = request_irq(bp->pdev->irq, bnx2_interrupt, SA_SHIRQ,
3918                                 dev->name, dev);
3919         }
3920         if (rc) {
3921                 bnx2_free_mem(bp);
3922                 return rc;
3923         }
3924
3925         rc = bnx2_init_nic(bp);
3926
3927         if (rc) {
3928                 free_irq(bp->pdev->irq, dev);
3929                 if (bp->flags & USING_MSI_FLAG) {
3930                         pci_disable_msi(bp->pdev);
3931                         bp->flags &= ~USING_MSI_FLAG;
3932                 }
3933                 bnx2_free_skbs(bp);
3934                 bnx2_free_mem(bp);
3935                 return rc;
3936         }
3937
3938         mod_timer(&bp->timer, jiffies + bp->current_interval);
3939
3940         atomic_set(&bp->intr_sem, 0);
3941
3942         bnx2_enable_int(bp);
3943
3944         if (bp->flags & USING_MSI_FLAG) {
3945                 /* Test MSI to make sure it is working
3946                  * If MSI test fails, go back to INTx mode
3947                  */
3948                 if (bnx2_test_intr(bp) != 0) {
3949                         printk(KERN_WARNING PFX "%s: No interrupt was generated"
3950                                " using MSI, switching to INTx mode. Please"
3951                                " report this failure to the PCI maintainer"
3952                                " and include system chipset information.\n",
3953                                bp->dev->name);
3954
3955                         bnx2_disable_int(bp);
3956                         free_irq(bp->pdev->irq, dev);
3957                         pci_disable_msi(bp->pdev);
3958                         bp->flags &= ~USING_MSI_FLAG;
3959
3960                         rc = bnx2_init_nic(bp);
3961
3962                         if (!rc) {
3963                                 rc = request_irq(bp->pdev->irq, bnx2_interrupt,
3964                                         SA_SHIRQ, dev->name, dev);
3965                         }
3966                         if (rc) {
3967                                 bnx2_free_skbs(bp);
3968                                 bnx2_free_mem(bp);
3969                                 del_timer_sync(&bp->timer);
3970                                 return rc;
3971                         }
3972                         bnx2_enable_int(bp);
3973                 }
3974         }
3975         if (bp->flags & USING_MSI_FLAG) {
3976                 printk(KERN_INFO PFX "%s: using MSI\n", dev->name);
3977         }
3978
3979         netif_start_queue(dev);
3980
3981         return 0;
3982 }
3983
3984 static void
3985 bnx2_reset_task(void *data)
3986 {
3987         struct bnx2 *bp = data;
3988
3989         if (!netif_running(bp->dev))
3990                 return;
3991
3992         bp->in_reset_task = 1;
3993         bnx2_netif_stop(bp);
3994
3995         bnx2_init_nic(bp);
3996
3997         atomic_set(&bp->intr_sem, 1);
3998         bnx2_netif_start(bp);
3999         bp->in_reset_task = 0;
4000 }
4001
4002 static void
4003 bnx2_tx_timeout(struct net_device *dev)
4004 {
4005         struct bnx2 *bp = dev->priv;
4006
4007         /* This allows the netif to be shutdown gracefully before resetting */
4008         schedule_work(&bp->reset_task);
4009 }
4010
4011 #ifdef BCM_VLAN
4012 /* Called with rtnl_lock */
4013 static void
4014 bnx2_vlan_rx_register(struct net_device *dev, struct vlan_group *vlgrp)
4015 {
4016         struct bnx2 *bp = dev->priv;
4017
4018         bnx2_netif_stop(bp);
4019
4020         bp->vlgrp = vlgrp;
4021         bnx2_set_rx_mode(dev);
4022
4023         bnx2_netif_start(bp);
4024 }
4025
4026 /* Called with rtnl_lock */
4027 static void
4028 bnx2_vlan_rx_kill_vid(struct net_device *dev, uint16_t vid)
4029 {
4030         struct bnx2 *bp = dev->priv;
4031
4032         bnx2_netif_stop(bp);
4033
4034         if (bp->vlgrp)
4035                 bp->vlgrp->vlan_devices[vid] = NULL;
4036         bnx2_set_rx_mode(dev);
4037
4038         bnx2_netif_start(bp);
4039 }
4040 #endif
4041
4042 /* Called with dev->xmit_lock.
4043  * hard_start_xmit is pseudo-lockless - a lock is only required when
4044  * the tx queue is full. This way, we get the benefit of lockless
4045  * operations most of the time without the complexities to handle
4046  * netif_stop_queue/wake_queue race conditions.
4047  */
4048 static int
4049 bnx2_start_xmit(struct sk_buff *skb, struct net_device *dev)
4050 {
4051         struct bnx2 *bp = dev->priv;
4052         dma_addr_t mapping;
4053         struct tx_bd *txbd;
4054         struct sw_bd *tx_buf;
4055         u32 len, vlan_tag_flags, last_frag, mss;
4056         u16 prod, ring_prod;
4057         int i;
4058
4059         if (unlikely(bnx2_tx_avail(bp) < (skb_shinfo(skb)->nr_frags + 1))) {
4060                 netif_stop_queue(dev);
4061                 printk(KERN_ERR PFX "%s: BUG! Tx ring full when queue awake!\n",
4062                         dev->name);
4063
4064                 return NETDEV_TX_BUSY;
4065         }
4066         len = skb_headlen(skb);
4067         prod = bp->tx_prod;
4068         ring_prod = TX_RING_IDX(prod);
4069
4070         vlan_tag_flags = 0;
4071         if (skb->ip_summed == CHECKSUM_HW) {
4072                 vlan_tag_flags |= TX_BD_FLAGS_TCP_UDP_CKSUM;
4073         }
4074
4075         if (bp->vlgrp != 0 && vlan_tx_tag_present(skb)) {
4076                 vlan_tag_flags |=
4077                         (TX_BD_FLAGS_VLAN_TAG | (vlan_tx_tag_get(skb) << 16));
4078         }
4079 #ifdef BCM_TSO
4080         if ((mss = skb_shinfo(skb)->tso_size) &&
4081                 (skb->len > (bp->dev->mtu + ETH_HLEN))) {
4082                 u32 tcp_opt_len, ip_tcp_len;
4083
4084                 if (skb_header_cloned(skb) &&
4085                     pskb_expand_head(skb, 0, 0, GFP_ATOMIC)) {
4086                         dev_kfree_skb(skb);
4087                         return NETDEV_TX_OK;
4088                 }
4089
4090                 tcp_opt_len = ((skb->h.th->doff - 5) * 4);
4091                 vlan_tag_flags |= TX_BD_FLAGS_SW_LSO;
4092
4093                 tcp_opt_len = 0;
4094                 if (skb->h.th->doff > 5) {
4095                         tcp_opt_len = (skb->h.th->doff - 5) << 2;
4096                 }
4097                 ip_tcp_len = (skb->nh.iph->ihl << 2) + sizeof(struct tcphdr);
4098
4099                 skb->nh.iph->check = 0;
4100                 skb->nh.iph->tot_len = ntohs(mss + ip_tcp_len + tcp_opt_len);
4101                 skb->h.th->check =
4102                         ~csum_tcpudp_magic(skb->nh.iph->saddr,
4103                                             skb->nh.iph->daddr,
4104                                             0, IPPROTO_TCP, 0);
4105
4106                 if (tcp_opt_len || (skb->nh.iph->ihl > 5)) {
4107                         vlan_tag_flags |= ((skb->nh.iph->ihl - 5) +
4108                                 (tcp_opt_len >> 2)) << 8;
4109                 }
4110         }
4111         else
4112 #endif
4113         {
4114                 mss = 0;
4115         }
4116
4117         mapping = pci_map_single(bp->pdev, skb->data, len, PCI_DMA_TODEVICE);
4118
4119         tx_buf = &bp->tx_buf_ring[ring_prod];
4120         tx_buf->skb = skb;
4121         pci_unmap_addr_set(tx_buf, mapping, mapping);
4122
4123         txbd = &bp->tx_desc_ring[ring_prod];
4124
4125         txbd->tx_bd_haddr_hi = (u64) mapping >> 32;
4126         txbd->tx_bd_haddr_lo = (u64) mapping & 0xffffffff;
4127         txbd->tx_bd_mss_nbytes = len | (mss << 16);
4128         txbd->tx_bd_vlan_tag_flags = vlan_tag_flags | TX_BD_FLAGS_START;
4129
4130         last_frag = skb_shinfo(skb)->nr_frags;
4131
4132         for (i = 0; i < last_frag; i++) {
4133                 skb_frag_t *frag = &skb_shinfo(skb)->frags[i];
4134
4135                 prod = NEXT_TX_BD(prod);
4136                 ring_prod = TX_RING_IDX(prod);
4137                 txbd = &bp->tx_desc_ring[ring_prod];
4138
4139                 len = frag->size;
4140                 mapping = pci_map_page(bp->pdev, frag->page, frag->page_offset,
4141                         len, PCI_DMA_TODEVICE);
4142                 pci_unmap_addr_set(&bp->tx_buf_ring[ring_prod],
4143                                 mapping, mapping);
4144
4145                 txbd->tx_bd_haddr_hi = (u64) mapping >> 32;
4146                 txbd->tx_bd_haddr_lo = (u64) mapping & 0xffffffff;
4147                 txbd->tx_bd_mss_nbytes = len | (mss << 16);
4148                 txbd->tx_bd_vlan_tag_flags = vlan_tag_flags;
4149
4150         }
4151         txbd->tx_bd_vlan_tag_flags |= TX_BD_FLAGS_END;
4152
4153         prod = NEXT_TX_BD(prod);
4154         bp->tx_prod_bseq += skb->len;
4155
4156         REG_WR16(bp, MB_TX_CID_ADDR + BNX2_L2CTX_TX_HOST_BIDX, prod);
4157         REG_WR(bp, MB_TX_CID_ADDR + BNX2_L2CTX_TX_HOST_BSEQ, bp->tx_prod_bseq);
4158
4159         mmiowb();
4160
4161         bp->tx_prod = prod;
4162         dev->trans_start = jiffies;
4163
4164         if (unlikely(bnx2_tx_avail(bp) <= MAX_SKB_FRAGS)) {
4165                 spin_lock(&bp->tx_lock);
4166                 netif_stop_queue(dev);
4167
4168                 if (bnx2_tx_avail(bp) > MAX_SKB_FRAGS)
4169                         netif_wake_queue(dev);
4170                 spin_unlock(&bp->tx_lock);
4171         }
4172
4173         return NETDEV_TX_OK;
4174 }
4175
4176 /* Called with rtnl_lock */
4177 static int
4178 bnx2_close(struct net_device *dev)
4179 {
4180         struct bnx2 *bp = dev->priv;
4181         u32 reset_code;
4182
4183         /* Calling flush_scheduled_work() may deadlock because
4184          * linkwatch_event() may be on the workqueue and it will try to get
4185          * the rtnl_lock which we are holding.
4186          */
4187         while (bp->in_reset_task)
4188                 msleep(1);
4189
4190         bnx2_netif_stop(bp);
4191         del_timer_sync(&bp->timer);
4192         if (bp->wol)
4193                 reset_code = BNX2_DRV_MSG_CODE_SUSPEND_WOL;
4194         else
4195                 reset_code = BNX2_DRV_MSG_CODE_SUSPEND_NO_WOL;
4196         bnx2_reset_chip(bp, reset_code);
4197         free_irq(bp->pdev->irq, dev);
4198         if (bp->flags & USING_MSI_FLAG) {
4199                 pci_disable_msi(bp->pdev);
4200                 bp->flags &= ~USING_MSI_FLAG;
4201         }
4202         bnx2_free_skbs(bp);
4203         bnx2_free_mem(bp);
4204         bp->link_up = 0;
4205         netif_carrier_off(bp->dev);
4206         bnx2_set_power_state(bp, 3);
4207         return 0;
4208 }
4209
4210 #define GET_NET_STATS64(ctr)                                    \
4211         (unsigned long) ((unsigned long) (ctr##_hi) << 32) +    \
4212         (unsigned long) (ctr##_lo)
4213
4214 #define GET_NET_STATS32(ctr)            \
4215         (ctr##_lo)
4216
4217 #if (BITS_PER_LONG == 64)
4218 #define GET_NET_STATS   GET_NET_STATS64
4219 #else
4220 #define GET_NET_STATS   GET_NET_STATS32
4221 #endif
4222
4223 static struct net_device_stats *
4224 bnx2_get_stats(struct net_device *dev)
4225 {
4226         struct bnx2 *bp = dev->priv;
4227         struct statistics_block *stats_blk = bp->stats_blk;
4228         struct net_device_stats *net_stats = &bp->net_stats;
4229
4230         if (bp->stats_blk == NULL) {
4231                 return net_stats;
4232         }
4233         net_stats->rx_packets =
4234                 GET_NET_STATS(stats_blk->stat_IfHCInUcastPkts) +
4235                 GET_NET_STATS(stats_blk->stat_IfHCInMulticastPkts) +
4236                 GET_NET_STATS(stats_blk->stat_IfHCInBroadcastPkts);
4237
4238         net_stats->tx_packets =
4239                 GET_NET_STATS(stats_blk->stat_IfHCOutUcastPkts) +
4240                 GET_NET_STATS(stats_blk->stat_IfHCOutMulticastPkts) +
4241                 GET_NET_STATS(stats_blk->stat_IfHCOutBroadcastPkts);
4242
4243         net_stats->rx_bytes =
4244                 GET_NET_STATS(stats_blk->stat_IfHCInOctets);
4245
4246         net_stats->tx_bytes =
4247                 GET_NET_STATS(stats_blk->stat_IfHCOutOctets);
4248
4249         net_stats->multicast =
4250                 GET_NET_STATS(stats_blk->stat_IfHCOutMulticastPkts);
4251
4252         net_stats->collisions =
4253                 (unsigned long) stats_blk->stat_EtherStatsCollisions;
4254
4255         net_stats->rx_length_errors =
4256                 (unsigned long) (stats_blk->stat_EtherStatsUndersizePkts +
4257                 stats_blk->stat_EtherStatsOverrsizePkts);
4258
4259         net_stats->rx_over_errors =
4260                 (unsigned long) stats_blk->stat_IfInMBUFDiscards;
4261
4262         net_stats->rx_frame_errors =
4263                 (unsigned long) stats_blk->stat_Dot3StatsAlignmentErrors;
4264
4265         net_stats->rx_crc_errors =
4266                 (unsigned long) stats_blk->stat_Dot3StatsFCSErrors;
4267
4268         net_stats->rx_errors = net_stats->rx_length_errors +
4269                 net_stats->rx_over_errors + net_stats->rx_frame_errors +
4270                 net_stats->rx_crc_errors;
4271
4272         net_stats->tx_aborted_errors =
4273                 (unsigned long) (stats_blk->stat_Dot3StatsExcessiveCollisions +
4274                 stats_blk->stat_Dot3StatsLateCollisions);
4275
4276         if (CHIP_NUM(bp) == CHIP_NUM_5706)
4277                 net_stats->tx_carrier_errors = 0;
4278         else {
4279                 net_stats->tx_carrier_errors =
4280                         (unsigned long)
4281                         stats_blk->stat_Dot3StatsCarrierSenseErrors;
4282         }
4283
4284         net_stats->tx_errors =
4285                 (unsigned long)
4286                 stats_blk->stat_emac_tx_stat_dot3statsinternalmactransmiterrors
4287                 +
4288                 net_stats->tx_aborted_errors +
4289                 net_stats->tx_carrier_errors;
4290
4291         return net_stats;
4292 }
4293
4294 /* All ethtool functions called with rtnl_lock */
4295
4296 static int
4297 bnx2_get_settings(struct net_device *dev, struct ethtool_cmd *cmd)
4298 {
4299         struct bnx2 *bp = dev->priv;
4300
4301         cmd->supported = SUPPORTED_Autoneg;
4302         if (bp->phy_flags & PHY_SERDES_FLAG) {
4303                 cmd->supported |= SUPPORTED_1000baseT_Full |
4304                         SUPPORTED_FIBRE;
4305
4306                 cmd->port = PORT_FIBRE;
4307         }
4308         else {
4309                 cmd->supported |= SUPPORTED_10baseT_Half |
4310                         SUPPORTED_10baseT_Full |
4311                         SUPPORTED_100baseT_Half |
4312                         SUPPORTED_100baseT_Full |
4313                         SUPPORTED_1000baseT_Full |
4314                         SUPPORTED_TP;
4315
4316                 cmd->port = PORT_TP;
4317         }
4318
4319         cmd->advertising = bp->advertising;
4320
4321         if (bp->autoneg & AUTONEG_SPEED) {
4322                 cmd->autoneg = AUTONEG_ENABLE;
4323         }
4324         else {
4325                 cmd->autoneg = AUTONEG_DISABLE;
4326         }
4327
4328         if (netif_carrier_ok(dev)) {
4329                 cmd->speed = bp->line_speed;
4330                 cmd->duplex = bp->duplex;
4331         }
4332         else {
4333                 cmd->speed = -1;
4334                 cmd->duplex = -1;
4335         }
4336
4337         cmd->transceiver = XCVR_INTERNAL;
4338         cmd->phy_address = bp->phy_addr;
4339
4340         return 0;
4341 }
4342
4343 static int
4344 bnx2_set_settings(struct net_device *dev, struct ethtool_cmd *cmd)
4345 {
4346         struct bnx2 *bp = dev->priv;
4347         u8 autoneg = bp->autoneg;
4348         u8 req_duplex = bp->req_duplex;
4349         u16 req_line_speed = bp->req_line_speed;
4350         u32 advertising = bp->advertising;
4351
4352         if (cmd->autoneg == AUTONEG_ENABLE) {
4353                 autoneg |= AUTONEG_SPEED;
4354
4355                 cmd->advertising &= ETHTOOL_ALL_COPPER_SPEED;
4356
4357                 /* allow advertising 1 speed */
4358                 if ((cmd->advertising == ADVERTISED_10baseT_Half) ||
4359                         (cmd->advertising == ADVERTISED_10baseT_Full) ||
4360                         (cmd->advertising == ADVERTISED_100baseT_Half) ||
4361                         (cmd->advertising == ADVERTISED_100baseT_Full)) {
4362
4363                         if (bp->phy_flags & PHY_SERDES_FLAG)
4364                                 return -EINVAL;
4365
4366                         advertising = cmd->advertising;
4367
4368                 }
4369                 else if (cmd->advertising == ADVERTISED_1000baseT_Full) {
4370                         advertising = cmd->advertising;
4371                 }
4372                 else if (cmd->advertising == ADVERTISED_1000baseT_Half) {
4373                         return -EINVAL;
4374                 }
4375                 else {
4376                         if (bp->phy_flags & PHY_SERDES_FLAG) {
4377                                 advertising = ETHTOOL_ALL_FIBRE_SPEED;
4378                         }
4379                         else {
4380                                 advertising = ETHTOOL_ALL_COPPER_SPEED;
4381                         }
4382                 }
4383                 advertising |= ADVERTISED_Autoneg;
4384         }
4385         else {
4386                 if (bp->phy_flags & PHY_SERDES_FLAG) {
4387                         if ((cmd->speed != SPEED_1000) ||
4388                                 (cmd->duplex != DUPLEX_FULL)) {
4389                                 return -EINVAL;
4390                         }
4391                 }
4392                 else if (cmd->speed == SPEED_1000) {
4393                         return -EINVAL;
4394                 }
4395                 autoneg &= ~AUTONEG_SPEED;
4396                 req_line_speed = cmd->speed;
4397                 req_duplex = cmd->duplex;
4398                 advertising = 0;
4399         }
4400
4401         bp->autoneg = autoneg;
4402         bp->advertising = advertising;
4403         bp->req_line_speed = req_line_speed;
4404         bp->req_duplex = req_duplex;
4405
4406         spin_lock_bh(&bp->phy_lock);
4407
4408         bnx2_setup_phy(bp);
4409
4410         spin_unlock_bh(&bp->phy_lock);
4411
4412         return 0;
4413 }
4414
4415 static void
4416 bnx2_get_drvinfo(struct net_device *dev, struct ethtool_drvinfo *info)
4417 {
4418         struct bnx2 *bp = dev->priv;
4419
4420         strcpy(info->driver, DRV_MODULE_NAME);
4421         strcpy(info->version, DRV_MODULE_VERSION);
4422         strcpy(info->bus_info, pci_name(bp->pdev));
4423         info->fw_version[0] = ((bp->fw_ver & 0xff000000) >> 24) + '0';
4424         info->fw_version[2] = ((bp->fw_ver & 0xff0000) >> 16) + '0';
4425         info->fw_version[4] = ((bp->fw_ver & 0xff00) >> 8) + '0';
4426         info->fw_version[6] = (bp->fw_ver & 0xff) + '0';
4427         info->fw_version[1] = info->fw_version[3] = info->fw_version[5] = '.';
4428         info->fw_version[7] = 0;
4429 }
4430
4431 static void
4432 bnx2_get_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
4433 {
4434         struct bnx2 *bp = dev->priv;
4435
4436         if (bp->flags & NO_WOL_FLAG) {
4437                 wol->supported = 0;
4438                 wol->wolopts = 0;
4439         }
4440         else {
4441                 wol->supported = WAKE_MAGIC;
4442                 if (bp->wol)
4443                         wol->wolopts = WAKE_MAGIC;
4444                 else
4445                         wol->wolopts = 0;
4446         }
4447         memset(&wol->sopass, 0, sizeof(wol->sopass));
4448 }
4449
4450 static int
4451 bnx2_set_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
4452 {
4453         struct bnx2 *bp = dev->priv;
4454
4455         if (wol->wolopts & ~WAKE_MAGIC)
4456                 return -EINVAL;
4457
4458         if (wol->wolopts & WAKE_MAGIC) {
4459                 if (bp->flags & NO_WOL_FLAG)
4460                         return -EINVAL;
4461
4462                 bp->wol = 1;
4463         }
4464         else {
4465                 bp->wol = 0;
4466         }
4467         return 0;
4468 }
4469
4470 static int
4471 bnx2_nway_reset(struct net_device *dev)
4472 {
4473         struct bnx2 *bp = dev->priv;
4474         u32 bmcr;
4475
4476         if (!(bp->autoneg & AUTONEG_SPEED)) {
4477                 return -EINVAL;
4478         }
4479
4480         spin_lock_bh(&bp->phy_lock);
4481
4482         /* Force a link down visible on the other side */
4483         if (bp->phy_flags & PHY_SERDES_FLAG) {
4484                 bnx2_write_phy(bp, MII_BMCR, BMCR_LOOPBACK);
4485                 spin_unlock_bh(&bp->phy_lock);
4486
4487                 msleep(20);
4488
4489                 spin_lock_bh(&bp->phy_lock);
4490                 if (CHIP_NUM(bp) == CHIP_NUM_5706) {
4491                         bp->current_interval = SERDES_AN_TIMEOUT;
4492                         bp->serdes_an_pending = 1;
4493                         mod_timer(&bp->timer, jiffies + bp->current_interval);
4494                 }
4495         }
4496
4497         bnx2_read_phy(bp, MII_BMCR, &bmcr);
4498         bmcr &= ~BMCR_LOOPBACK;
4499         bnx2_write_phy(bp, MII_BMCR, bmcr | BMCR_ANRESTART | BMCR_ANENABLE);
4500
4501         spin_unlock_bh(&bp->phy_lock);
4502
4503         return 0;
4504 }
4505
4506 static int
4507 bnx2_get_eeprom_len(struct net_device *dev)
4508 {
4509         struct bnx2 *bp = dev->priv;
4510
4511         if (bp->flash_info == 0)
4512                 return 0;
4513
4514         return (int) bp->flash_info->total_size;
4515 }
4516
4517 static int
4518 bnx2_get_eeprom(struct net_device *dev, struct ethtool_eeprom *eeprom,
4519                 u8 *eebuf)
4520 {
4521         struct bnx2 *bp = dev->priv;
4522         int rc;
4523
4524         if (eeprom->offset > bp->flash_info->total_size)
4525                 return -EINVAL;
4526
4527         if ((eeprom->offset + eeprom->len) > bp->flash_info->total_size)
4528                 eeprom->len = bp->flash_info->total_size - eeprom->offset;
4529
4530         rc = bnx2_nvram_read(bp, eeprom->offset, eebuf, eeprom->len);
4531
4532         return rc;
4533 }
4534
4535 static int
4536 bnx2_set_eeprom(struct net_device *dev, struct ethtool_eeprom *eeprom,
4537                 u8 *eebuf)
4538 {
4539         struct bnx2 *bp = dev->priv;
4540         int rc;
4541
4542         if (eeprom->offset > bp->flash_info->total_size)
4543                 return -EINVAL;
4544
4545         if ((eeprom->offset + eeprom->len) > bp->flash_info->total_size)
4546                 eeprom->len = bp->flash_info->total_size - eeprom->offset;
4547
4548         rc = bnx2_nvram_write(bp, eeprom->offset, eebuf, eeprom->len);
4549
4550         return rc;
4551 }
4552
4553 static int
4554 bnx2_get_coalesce(struct net_device *dev, struct ethtool_coalesce *coal)
4555 {
4556         struct bnx2 *bp = dev->priv;
4557
4558         memset(coal, 0, sizeof(struct ethtool_coalesce));
4559
4560         coal->rx_coalesce_usecs = bp->rx_ticks;
4561         coal->rx_max_coalesced_frames = bp->rx_quick_cons_trip;
4562         coal->rx_coalesce_usecs_irq = bp->rx_ticks_int;
4563         coal->rx_max_coalesced_frames_irq = bp->rx_quick_cons_trip_int;
4564
4565         coal->tx_coalesce_usecs = bp->tx_ticks;
4566         coal->tx_max_coalesced_frames = bp->tx_quick_cons_trip;
4567         coal->tx_coalesce_usecs_irq = bp->tx_ticks_int;
4568         coal->tx_max_coalesced_frames_irq = bp->tx_quick_cons_trip_int;
4569
4570         coal->stats_block_coalesce_usecs = bp->stats_ticks;
4571
4572         return 0;
4573 }
4574
4575 static int
4576 bnx2_set_coalesce(struct net_device *dev, struct ethtool_coalesce *coal)
4577 {
4578         struct bnx2 *bp = dev->priv;
4579
4580         bp->rx_ticks = (u16) coal->rx_coalesce_usecs;
4581         if (bp->rx_ticks > 0x3ff) bp->rx_ticks = 0x3ff;
4582
4583         bp->rx_quick_cons_trip = (u16) coal->rx_max_coalesced_frames;
4584         if (bp->rx_quick_cons_trip > 0xff) bp->rx_quick_cons_trip = 0xff;
4585
4586         bp->rx_ticks_int = (u16) coal->rx_coalesce_usecs_irq;
4587         if (bp->rx_ticks_int > 0x3ff) bp->rx_ticks_int = 0x3ff;
4588
4589         bp->rx_quick_cons_trip_int = (u16) coal->rx_max_coalesced_frames_irq;
4590         if (bp->rx_quick_cons_trip_int > 0xff)
4591                 bp->rx_quick_cons_trip_int = 0xff;
4592
4593         bp->tx_ticks = (u16) coal->tx_coalesce_usecs;
4594         if (bp->tx_ticks > 0x3ff) bp->tx_ticks = 0x3ff;
4595
4596         bp->tx_quick_cons_trip = (u16) coal->tx_max_coalesced_frames;
4597         if (bp->tx_quick_cons_trip > 0xff) bp->tx_quick_cons_trip = 0xff;
4598
4599         bp->tx_ticks_int = (u16) coal->tx_coalesce_usecs_irq;
4600         if (bp->tx_ticks_int > 0x3ff) bp->tx_ticks_int = 0x3ff;
4601
4602         bp->tx_quick_cons_trip_int = (u16) coal->tx_max_coalesced_frames_irq;
4603         if (bp->tx_quick_cons_trip_int > 0xff) bp->tx_quick_cons_trip_int =
4604                 0xff;
4605
4606         bp->stats_ticks = coal->stats_block_coalesce_usecs;
4607         if (bp->stats_ticks > 0xffff00) bp->stats_ticks = 0xffff00;
4608         bp->stats_ticks &= 0xffff00;
4609
4610         if (netif_running(bp->dev)) {
4611                 bnx2_netif_stop(bp);
4612                 bnx2_init_nic(bp);
4613                 bnx2_netif_start(bp);
4614         }
4615
4616         return 0;
4617 }
4618
4619 static void
4620 bnx2_get_ringparam(struct net_device *dev, struct ethtool_ringparam *ering)
4621 {
4622         struct bnx2 *bp = dev->priv;
4623
4624         ering->rx_max_pending = MAX_RX_DESC_CNT;
4625         ering->rx_mini_max_pending = 0;
4626         ering->rx_jumbo_max_pending = 0;
4627
4628         ering->rx_pending = bp->rx_ring_size;
4629         ering->rx_mini_pending = 0;
4630         ering->rx_jumbo_pending = 0;
4631
4632         ering->tx_max_pending = MAX_TX_DESC_CNT;
4633         ering->tx_pending = bp->tx_ring_size;
4634 }
4635
4636 static int
4637 bnx2_set_ringparam(struct net_device *dev, struct ethtool_ringparam *ering)
4638 {
4639         struct bnx2 *bp = dev->priv;
4640
4641         if ((ering->rx_pending > MAX_RX_DESC_CNT) ||
4642                 (ering->tx_pending > MAX_TX_DESC_CNT) ||
4643                 (ering->tx_pending <= MAX_SKB_FRAGS)) {
4644
4645                 return -EINVAL;
4646         }
4647         bp->rx_ring_size = ering->rx_pending;
4648         bp->tx_ring_size = ering->tx_pending;
4649
4650         if (netif_running(bp->dev)) {
4651                 bnx2_netif_stop(bp);
4652                 bnx2_init_nic(bp);
4653                 bnx2_netif_start(bp);
4654         }
4655
4656         return 0;
4657 }
4658
4659 static void
4660 bnx2_get_pauseparam(struct net_device *dev, struct ethtool_pauseparam *epause)
4661 {
4662         struct bnx2 *bp = dev->priv;
4663
4664         epause->autoneg = ((bp->autoneg & AUTONEG_FLOW_CTRL) != 0);
4665         epause->rx_pause = ((bp->flow_ctrl & FLOW_CTRL_RX) != 0);
4666         epause->tx_pause = ((bp->flow_ctrl & FLOW_CTRL_TX) != 0);
4667 }
4668
4669 static int
4670 bnx2_set_pauseparam(struct net_device *dev, struct ethtool_pauseparam *epause)
4671 {
4672         struct bnx2 *bp = dev->priv;
4673
4674         bp->req_flow_ctrl = 0;
4675         if (epause->rx_pause)
4676                 bp->req_flow_ctrl |= FLOW_CTRL_RX;
4677         if (epause->tx_pause)
4678                 bp->req_flow_ctrl |= FLOW_CTRL_TX;
4679
4680         if (epause->autoneg) {
4681                 bp->autoneg |= AUTONEG_FLOW_CTRL;
4682         }
4683         else {
4684                 bp->autoneg &= ~AUTONEG_FLOW_CTRL;
4685         }
4686
4687         spin_lock_bh(&bp->phy_lock);
4688
4689         bnx2_setup_phy(bp);
4690
4691         spin_unlock_bh(&bp->phy_lock);
4692
4693         return 0;
4694 }
4695
4696 static u32
4697 bnx2_get_rx_csum(struct net_device *dev)
4698 {
4699         struct bnx2 *bp = dev->priv;
4700
4701         return bp->rx_csum;
4702 }
4703
4704 static int
4705 bnx2_set_rx_csum(struct net_device *dev, u32 data)
4706 {
4707         struct bnx2 *bp = dev->priv;
4708
4709         bp->rx_csum = data;
4710         return 0;
4711 }
4712
4713 #define BNX2_NUM_STATS 45
4714
4715 static struct {
4716         char string[ETH_GSTRING_LEN];
4717 } bnx2_stats_str_arr[BNX2_NUM_STATS] = {
4718         { "rx_bytes" },
4719         { "rx_error_bytes" },
4720         { "tx_bytes" },
4721         { "tx_error_bytes" },
4722         { "rx_ucast_packets" },
4723         { "rx_mcast_packets" },
4724         { "rx_bcast_packets" },
4725         { "tx_ucast_packets" },
4726         { "tx_mcast_packets" },
4727         { "tx_bcast_packets" },
4728         { "tx_mac_errors" },
4729         { "tx_carrier_errors" },
4730         { "rx_crc_errors" },
4731         { "rx_align_errors" },
4732         { "tx_single_collisions" },
4733         { "tx_multi_collisions" },
4734         { "tx_deferred" },
4735         { "tx_excess_collisions" },
4736         { "tx_late_collisions" },
4737         { "tx_total_collisions" },
4738         { "rx_fragments" },
4739         { "rx_jabbers" },
4740         { "rx_undersize_packets" },
4741         { "rx_oversize_packets" },
4742         { "rx_64_byte_packets" },
4743         { "rx_65_to_127_byte_packets" },
4744         { "rx_128_to_255_byte_packets" },
4745         { "rx_256_to_511_byte_packets" },
4746         { "rx_512_to_1023_byte_packets" },
4747         { "rx_1024_to_1522_byte_packets" },
4748         { "rx_1523_to_9022_byte_packets" },
4749         { "tx_64_byte_packets" },
4750         { "tx_65_to_127_byte_packets" },
4751         { "tx_128_to_255_byte_packets" },
4752         { "tx_256_to_511_byte_packets" },
4753         { "tx_512_to_1023_byte_packets" },
4754         { "tx_1024_to_1522_byte_packets" },
4755         { "tx_1523_to_9022_byte_packets" },
4756         { "rx_xon_frames" },
4757         { "rx_xoff_frames" },
4758         { "tx_xon_frames" },
4759         { "tx_xoff_frames" },
4760         { "rx_mac_ctrl_frames" },
4761         { "rx_filtered_packets" },
4762         { "rx_discards" },
4763 };
4764
4765 #define STATS_OFFSET32(offset_name) (offsetof(struct statistics_block, offset_name) / 4)
4766
4767 static unsigned long bnx2_stats_offset_arr[BNX2_NUM_STATS] = {
4768     STATS_OFFSET32(stat_IfHCInOctets_hi),
4769     STATS_OFFSET32(stat_IfHCInBadOctets_hi),
4770     STATS_OFFSET32(stat_IfHCOutOctets_hi),
4771     STATS_OFFSET32(stat_IfHCOutBadOctets_hi),
4772     STATS_OFFSET32(stat_IfHCInUcastPkts_hi),
4773     STATS_OFFSET32(stat_IfHCInMulticastPkts_hi),
4774     STATS_OFFSET32(stat_IfHCInBroadcastPkts_hi),
4775     STATS_OFFSET32(stat_IfHCOutUcastPkts_hi),
4776     STATS_OFFSET32(stat_IfHCOutMulticastPkts_hi),
4777     STATS_OFFSET32(stat_IfHCOutBroadcastPkts_hi),
4778     STATS_OFFSET32(stat_emac_tx_stat_dot3statsinternalmactransmiterrors),
4779     STATS_OFFSET32(stat_Dot3StatsCarrierSenseErrors),
4780     STATS_OFFSET32(stat_Dot3StatsFCSErrors),
4781     STATS_OFFSET32(stat_Dot3StatsAlignmentErrors),
4782     STATS_OFFSET32(stat_Dot3StatsSingleCollisionFrames),
4783     STATS_OFFSET32(stat_Dot3StatsMultipleCollisionFrames),
4784     STATS_OFFSET32(stat_Dot3StatsDeferredTransmissions),
4785     STATS_OFFSET32(stat_Dot3StatsExcessiveCollisions),
4786     STATS_OFFSET32(stat_Dot3StatsLateCollisions),
4787     STATS_OFFSET32(stat_EtherStatsCollisions),
4788     STATS_OFFSET32(stat_EtherStatsFragments),
4789     STATS_OFFSET32(stat_EtherStatsJabbers),
4790     STATS_OFFSET32(stat_EtherStatsUndersizePkts),
4791     STATS_OFFSET32(stat_EtherStatsOverrsizePkts),
4792     STATS_OFFSET32(stat_EtherStatsPktsRx64Octets),
4793     STATS_OFFSET32(stat_EtherStatsPktsRx65Octetsto127Octets),
4794     STATS_OFFSET32(stat_EtherStatsPktsRx128Octetsto255Octets),
4795     STATS_OFFSET32(stat_EtherStatsPktsRx256Octetsto511Octets),
4796     STATS_OFFSET32(stat_EtherStatsPktsRx512Octetsto1023Octets),
4797     STATS_OFFSET32(stat_EtherStatsPktsRx1024Octetsto1522Octets),
4798     STATS_OFFSET32(stat_EtherStatsPktsRx1523Octetsto9022Octets),
4799     STATS_OFFSET32(stat_EtherStatsPktsTx64Octets),
4800     STATS_OFFSET32(stat_EtherStatsPktsTx65Octetsto127Octets),
4801     STATS_OFFSET32(stat_EtherStatsPktsTx128Octetsto255Octets),
4802     STATS_OFFSET32(stat_EtherStatsPktsTx256Octetsto511Octets),
4803     STATS_OFFSET32(stat_EtherStatsPktsTx512Octetsto1023Octets),
4804     STATS_OFFSET32(stat_EtherStatsPktsTx1024Octetsto1522Octets),
4805     STATS_OFFSET32(stat_EtherStatsPktsTx1523Octetsto9022Octets),
4806     STATS_OFFSET32(stat_XonPauseFramesReceived),
4807     STATS_OFFSET32(stat_XoffPauseFramesReceived),
4808     STATS_OFFSET32(stat_OutXonSent),
4809     STATS_OFFSET32(stat_OutXoffSent),
4810     STATS_OFFSET32(stat_MacControlFramesReceived),
4811     STATS_OFFSET32(stat_IfInFramesL2FilterDiscards),
4812     STATS_OFFSET32(stat_IfInMBUFDiscards),
4813 };
4814
4815 /* stat_IfHCInBadOctets and stat_Dot3StatsCarrierSenseErrors are
4816  * skipped because of errata.
4817  */
4818 static u8 bnx2_5706_stats_len_arr[BNX2_NUM_STATS] = {
4819         8,0,8,8,8,8,8,8,8,8,
4820         4,0,4,4,4,4,4,4,4,4,
4821         4,4,4,4,4,4,4,4,4,4,
4822         4,4,4,4,4,4,4,4,4,4,
4823         4,4,4,4,4,
4824 };
4825
4826 #define BNX2_NUM_TESTS 6
4827
4828 static struct {
4829         char string[ETH_GSTRING_LEN];
4830 } bnx2_tests_str_arr[BNX2_NUM_TESTS] = {
4831         { "register_test (offline)" },
4832         { "memory_test (offline)" },
4833         { "loopback_test (offline)" },
4834         { "nvram_test (online)" },
4835         { "interrupt_test (online)" },
4836         { "link_test (online)" },
4837 };
4838
4839 static int
4840 bnx2_self_test_count(struct net_device *dev)
4841 {
4842         return BNX2_NUM_TESTS;
4843 }
4844
4845 static void
4846 bnx2_self_test(struct net_device *dev, struct ethtool_test *etest, u64 *buf)
4847 {
4848         struct bnx2 *bp = dev->priv;
4849
4850         memset(buf, 0, sizeof(u64) * BNX2_NUM_TESTS);
4851         if (etest->flags & ETH_TEST_FL_OFFLINE) {
4852                 bnx2_netif_stop(bp);
4853                 bnx2_reset_chip(bp, BNX2_DRV_MSG_CODE_DIAG);
4854                 bnx2_free_skbs(bp);
4855
4856                 if (bnx2_test_registers(bp) != 0) {
4857                         buf[0] = 1;
4858                         etest->flags |= ETH_TEST_FL_FAILED;
4859                 }
4860                 if (bnx2_test_memory(bp) != 0) {
4861                         buf[1] = 1;
4862                         etest->flags |= ETH_TEST_FL_FAILED;
4863                 }
4864                 if (bnx2_test_loopback(bp) != 0) {
4865                         buf[2] = 1;
4866                         etest->flags |= ETH_TEST_FL_FAILED;
4867                 }
4868
4869                 if (!netif_running(bp->dev)) {
4870                         bnx2_reset_chip(bp, BNX2_DRV_MSG_CODE_RESET);
4871                 }
4872                 else {
4873                         bnx2_init_nic(bp);
4874                         bnx2_netif_start(bp);
4875                 }
4876
4877                 /* wait for link up */
4878                 msleep_interruptible(3000);
4879                 if ((!bp->link_up) && !(bp->phy_flags & PHY_SERDES_FLAG))
4880                         msleep_interruptible(4000);
4881         }
4882
4883         if (bnx2_test_nvram(bp) != 0) {
4884                 buf[3] = 1;
4885                 etest->flags |= ETH_TEST_FL_FAILED;
4886         }
4887         if (bnx2_test_intr(bp) != 0) {
4888                 buf[4] = 1;
4889                 etest->flags |= ETH_TEST_FL_FAILED;
4890         }
4891
4892         if (bnx2_test_link(bp) != 0) {
4893                 buf[5] = 1;
4894                 etest->flags |= ETH_TEST_FL_FAILED;
4895
4896         }
4897 }
4898
4899 static void
4900 bnx2_get_strings(struct net_device *dev, u32 stringset, u8 *buf)
4901 {
4902         switch (stringset) {
4903         case ETH_SS_STATS:
4904                 memcpy(buf, bnx2_stats_str_arr,
4905                         sizeof(bnx2_stats_str_arr));
4906                 break;
4907         case ETH_SS_TEST:
4908                 memcpy(buf, bnx2_tests_str_arr,
4909                         sizeof(bnx2_tests_str_arr));
4910                 break;
4911         }
4912 }
4913
4914 static int
4915 bnx2_get_stats_count(struct net_device *dev)
4916 {
4917         return BNX2_NUM_STATS;
4918 }
4919
4920 static void
4921 bnx2_get_ethtool_stats(struct net_device *dev,
4922                 struct ethtool_stats *stats, u64 *buf)
4923 {
4924         struct bnx2 *bp = dev->priv;
4925         int i;
4926         u32 *hw_stats = (u32 *) bp->stats_blk;
4927         u8 *stats_len_arr = NULL;
4928
4929         if (hw_stats == NULL) {
4930                 memset(buf, 0, sizeof(u64) * BNX2_NUM_STATS);
4931                 return;
4932         }
4933
4934         if (CHIP_NUM(bp) == CHIP_NUM_5706)
4935                 stats_len_arr = bnx2_5706_stats_len_arr;
4936
4937         for (i = 0; i < BNX2_NUM_STATS; i++) {
4938                 if (stats_len_arr[i] == 0) {
4939                         /* skip this counter */
4940                         buf[i] = 0;
4941                         continue;
4942                 }
4943                 if (stats_len_arr[i] == 4) {
4944                         /* 4-byte counter */
4945                         buf[i] = (u64)
4946                                 *(hw_stats + bnx2_stats_offset_arr[i]);
4947                         continue;
4948                 }
4949                 /* 8-byte counter */
4950                 buf[i] = (((u64) *(hw_stats +
4951                                         bnx2_stats_offset_arr[i])) << 32) +
4952                                 *(hw_stats + bnx2_stats_offset_arr[i] + 1);
4953         }
4954 }
4955
4956 static int
4957 bnx2_phys_id(struct net_device *dev, u32 data)
4958 {
4959         struct bnx2 *bp = dev->priv;
4960         int i;
4961         u32 save;
4962
4963         if (data == 0)
4964                 data = 2;
4965
4966         save = REG_RD(bp, BNX2_MISC_CFG);
4967         REG_WR(bp, BNX2_MISC_CFG, BNX2_MISC_CFG_LEDMODE_MAC);
4968
4969         for (i = 0; i < (data * 2); i++) {
4970                 if ((i % 2) == 0) {
4971                         REG_WR(bp, BNX2_EMAC_LED, BNX2_EMAC_LED_OVERRIDE);
4972                 }
4973                 else {
4974                         REG_WR(bp, BNX2_EMAC_LED, BNX2_EMAC_LED_OVERRIDE |
4975                                 BNX2_EMAC_LED_1000MB_OVERRIDE |
4976                                 BNX2_EMAC_LED_100MB_OVERRIDE |
4977                                 BNX2_EMAC_LED_10MB_OVERRIDE |
4978                                 BNX2_EMAC_LED_TRAFFIC_OVERRIDE |
4979                                 BNX2_EMAC_LED_TRAFFIC);
4980                 }
4981                 msleep_interruptible(500);
4982                 if (signal_pending(current))
4983                         break;
4984         }
4985         REG_WR(bp, BNX2_EMAC_LED, 0);
4986         REG_WR(bp, BNX2_MISC_CFG, save);
4987         return 0;
4988 }
4989
4990 static struct ethtool_ops bnx2_ethtool_ops = {
4991         .get_settings           = bnx2_get_settings,
4992         .set_settings           = bnx2_set_settings,
4993         .get_drvinfo            = bnx2_get_drvinfo,
4994         .get_wol                = bnx2_get_wol,
4995         .set_wol                = bnx2_set_wol,
4996         .nway_reset             = bnx2_nway_reset,
4997         .get_link               = ethtool_op_get_link,
4998         .get_eeprom_len         = bnx2_get_eeprom_len,
4999         .get_eeprom             = bnx2_get_eeprom,
5000         .set_eeprom             = bnx2_set_eeprom,
5001         .get_coalesce           = bnx2_get_coalesce,
5002         .set_coalesce           = bnx2_set_coalesce,
5003         .get_ringparam          = bnx2_get_ringparam,
5004         .set_ringparam          = bnx2_set_ringparam,
5005         .get_pauseparam         = bnx2_get_pauseparam,
5006         .set_pauseparam         = bnx2_set_pauseparam,
5007         .get_rx_csum            = bnx2_get_rx_csum,
5008         .set_rx_csum            = bnx2_set_rx_csum,
5009         .get_tx_csum            = ethtool_op_get_tx_csum,
5010         .set_tx_csum            = ethtool_op_set_tx_csum,
5011         .get_sg                 = ethtool_op_get_sg,
5012         .set_sg                 = ethtool_op_set_sg,
5013 #ifdef BCM_TSO
5014         .get_tso                = ethtool_op_get_tso,
5015         .set_tso                = ethtool_op_set_tso,
5016 #endif
5017         .self_test_count        = bnx2_self_test_count,
5018         .self_test              = bnx2_self_test,
5019         .get_strings            = bnx2_get_strings,
5020         .phys_id                = bnx2_phys_id,
5021         .get_stats_count        = bnx2_get_stats_count,
5022         .get_ethtool_stats      = bnx2_get_ethtool_stats,
5023 };
5024
5025 /* Called with rtnl_lock */
5026 static int
5027 bnx2_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd)
5028 {
5029         struct mii_ioctl_data *data = if_mii(ifr);
5030         struct bnx2 *bp = dev->priv;
5031         int err;
5032
5033         switch(cmd) {
5034         case SIOCGMIIPHY:
5035                 data->phy_id = bp->phy_addr;
5036
5037                 /* fallthru */
5038         case SIOCGMIIREG: {
5039                 u32 mii_regval;
5040
5041                 spin_lock_bh(&bp->phy_lock);
5042                 err = bnx2_read_phy(bp, data->reg_num & 0x1f, &mii_regval);
5043                 spin_unlock_bh(&bp->phy_lock);
5044
5045                 data->val_out = mii_regval;
5046
5047                 return err;
5048         }
5049
5050         case SIOCSMIIREG:
5051                 if (!capable(CAP_NET_ADMIN))
5052                         return -EPERM;
5053
5054                 spin_lock_bh(&bp->phy_lock);
5055                 err = bnx2_write_phy(bp, data->reg_num & 0x1f, data->val_in);
5056                 spin_unlock_bh(&bp->phy_lock);
5057
5058                 return err;
5059
5060         default:
5061                 /* do nothing */
5062                 break;
5063         }
5064         return -EOPNOTSUPP;
5065 }
5066
5067 /* Called with rtnl_lock */
5068 static int
5069 bnx2_change_mac_addr(struct net_device *dev, void *p)
5070 {
5071         struct sockaddr *addr = p;
5072         struct bnx2 *bp = dev->priv;
5073
5074         memcpy(dev->dev_addr, addr->sa_data, dev->addr_len);
5075         if (netif_running(dev))
5076                 bnx2_set_mac_addr(bp);
5077
5078         return 0;
5079 }
5080
5081 /* Called with rtnl_lock */
5082 static int
5083 bnx2_change_mtu(struct net_device *dev, int new_mtu)
5084 {
5085         struct bnx2 *bp = dev->priv;
5086
5087         if (((new_mtu + ETH_HLEN) > MAX_ETHERNET_JUMBO_PACKET_SIZE) ||
5088                 ((new_mtu + ETH_HLEN) < MIN_ETHERNET_PACKET_SIZE))
5089                 return -EINVAL;
5090
5091         dev->mtu = new_mtu;
5092         if (netif_running(dev)) {
5093                 bnx2_netif_stop(bp);
5094
5095                 bnx2_init_nic(bp);
5096
5097                 bnx2_netif_start(bp);
5098         }
5099         return 0;
5100 }
5101
5102 #if defined(HAVE_POLL_CONTROLLER) || defined(CONFIG_NET_POLL_CONTROLLER)
5103 static void
5104 poll_bnx2(struct net_device *dev)
5105 {
5106         struct bnx2 *bp = dev->priv;
5107
5108         disable_irq(bp->pdev->irq);
5109         bnx2_interrupt(bp->pdev->irq, dev, NULL);
5110         enable_irq(bp->pdev->irq);
5111 }
5112 #endif
5113
5114 static int __devinit
5115 bnx2_init_board(struct pci_dev *pdev, struct net_device *dev)
5116 {
5117         struct bnx2 *bp;
5118         unsigned long mem_len;
5119         int rc;
5120         u32 reg;
5121
5122         SET_MODULE_OWNER(dev);
5123         SET_NETDEV_DEV(dev, &pdev->dev);
5124         bp = dev->priv;
5125
5126         bp->flags = 0;
5127         bp->phy_flags = 0;
5128
5129         /* enable device (incl. PCI PM wakeup), and bus-mastering */
5130         rc = pci_enable_device(pdev);
5131         if (rc) {
5132                 printk(KERN_ERR PFX "Cannot enable PCI device, aborting.");
5133                 goto err_out;
5134         }
5135
5136         if (!(pci_resource_flags(pdev, 0) & IORESOURCE_MEM)) {
5137                 printk(KERN_ERR PFX "Cannot find PCI device base address, "
5138                        "aborting.\n");
5139                 rc = -ENODEV;
5140                 goto err_out_disable;
5141         }
5142
5143         rc = pci_request_regions(pdev, DRV_MODULE_NAME);
5144         if (rc) {
5145                 printk(KERN_ERR PFX "Cannot obtain PCI resources, aborting.\n");
5146                 goto err_out_disable;
5147         }
5148
5149         pci_set_master(pdev);
5150
5151         bp->pm_cap = pci_find_capability(pdev, PCI_CAP_ID_PM);
5152         if (bp->pm_cap == 0) {
5153                 printk(KERN_ERR PFX "Cannot find power management capability, "
5154                                "aborting.\n");
5155                 rc = -EIO;
5156                 goto err_out_release;
5157         }
5158
5159         bp->pcix_cap = pci_find_capability(pdev, PCI_CAP_ID_PCIX);
5160         if (bp->pcix_cap == 0) {
5161                 printk(KERN_ERR PFX "Cannot find PCIX capability, aborting.\n");
5162                 rc = -EIO;
5163                 goto err_out_release;
5164         }
5165
5166         if (pci_set_dma_mask(pdev, DMA_64BIT_MASK) == 0) {
5167                 bp->flags |= USING_DAC_FLAG;
5168                 if (pci_set_consistent_dma_mask(pdev, DMA_64BIT_MASK) != 0) {
5169                         printk(KERN_ERR PFX "pci_set_consistent_dma_mask "
5170                                "failed, aborting.\n");
5171                         rc = -EIO;
5172                         goto err_out_release;
5173                 }
5174         }
5175         else if (pci_set_dma_mask(pdev, DMA_32BIT_MASK) != 0) {
5176                 printk(KERN_ERR PFX "System does not support DMA, aborting.\n");
5177                 rc = -EIO;
5178                 goto err_out_release;
5179         }
5180
5181         bp->dev = dev;
5182         bp->pdev = pdev;
5183
5184         spin_lock_init(&bp->phy_lock);
5185         spin_lock_init(&bp->tx_lock);
5186         INIT_WORK(&bp->reset_task, bnx2_reset_task, bp);
5187
5188         dev->base_addr = dev->mem_start = pci_resource_start(pdev, 0);
5189         mem_len = MB_GET_CID_ADDR(17);
5190         dev->mem_end = dev->mem_start + mem_len;
5191         dev->irq = pdev->irq;
5192
5193         bp->regview = ioremap_nocache(dev->base_addr, mem_len);
5194
5195         if (!bp->regview) {
5196                 printk(KERN_ERR PFX "Cannot map register space, aborting.\n");
5197                 rc = -ENOMEM;
5198                 goto err_out_release;
5199         }
5200
5201         /* Configure byte swap and enable write to the reg_window registers.
5202          * Rely on CPU to do target byte swapping on big endian systems
5203          * The chip's target access swapping will not swap all accesses
5204          */
5205         pci_write_config_dword(bp->pdev, BNX2_PCICFG_MISC_CONFIG,
5206                                BNX2_PCICFG_MISC_CONFIG_REG_WINDOW_ENA |
5207                                BNX2_PCICFG_MISC_CONFIG_TARGET_MB_WORD_SWAP);
5208
5209         bnx2_set_power_state(bp, 0);
5210
5211         bp->chip_id = REG_RD(bp, BNX2_MISC_ID);
5212
5213         bp->phy_addr = 1;
5214
5215         /* Get bus information. */
5216         reg = REG_RD(bp, BNX2_PCICFG_MISC_STATUS);
5217         if (reg & BNX2_PCICFG_MISC_STATUS_PCIX_DET) {
5218                 u32 clkreg;
5219
5220                 bp->flags |= PCIX_FLAG;
5221
5222                 clkreg = REG_RD(bp, BNX2_PCICFG_PCI_CLOCK_CONTROL_BITS);
5223
5224                 clkreg &= BNX2_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET;
5225                 switch (clkreg) {
5226                 case BNX2_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_133MHZ:
5227                         bp->bus_speed_mhz = 133;
5228                         break;
5229
5230                 case BNX2_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_95MHZ:
5231                         bp->bus_speed_mhz = 100;
5232                         break;
5233
5234                 case BNX2_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_66MHZ:
5235                 case BNX2_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_80MHZ:
5236                         bp->bus_speed_mhz = 66;
5237                         break;
5238
5239                 case BNX2_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_48MHZ:
5240                 case BNX2_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_55MHZ:
5241                         bp->bus_speed_mhz = 50;
5242                         break;
5243
5244                 case BNX2_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_LOW:
5245                 case BNX2_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_32MHZ:
5246                 case BNX2_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_38MHZ:
5247                         bp->bus_speed_mhz = 33;
5248                         break;
5249                 }
5250         }
5251         else {
5252                 if (reg & BNX2_PCICFG_MISC_STATUS_M66EN)
5253                         bp->bus_speed_mhz = 66;
5254                 else
5255                         bp->bus_speed_mhz = 33;
5256         }
5257
5258         if (reg & BNX2_PCICFG_MISC_STATUS_32BIT_DET)
5259                 bp->flags |= PCI_32BIT_FLAG;
5260
5261         /* 5706A0 may falsely detect SERR and PERR. */
5262         if (CHIP_ID(bp) == CHIP_ID_5706_A0) {
5263                 reg = REG_RD(bp, PCI_COMMAND);
5264                 reg &= ~(PCI_COMMAND_SERR | PCI_COMMAND_PARITY);
5265                 REG_WR(bp, PCI_COMMAND, reg);
5266         }
5267         else if ((CHIP_ID(bp) == CHIP_ID_5706_A1) &&
5268                 !(bp->flags & PCIX_FLAG)) {
5269
5270                 printk(KERN_ERR PFX "5706 A1 can only be used in a PCIX bus, "
5271                        "aborting.\n");
5272                 goto err_out_unmap;
5273         }
5274
5275         bnx2_init_nvram(bp);
5276
5277         /* Get the permanent MAC address.  First we need to make sure the
5278          * firmware is actually running.
5279          */
5280         reg = REG_RD_IND(bp, HOST_VIEW_SHMEM_BASE + BNX2_DEV_INFO_SIGNATURE);
5281
5282         if ((reg & BNX2_DEV_INFO_SIGNATURE_MAGIC_MASK) !=
5283             BNX2_DEV_INFO_SIGNATURE_MAGIC) {
5284                 printk(KERN_ERR PFX "Firmware not running, aborting.\n");
5285                 rc = -ENODEV;
5286                 goto err_out_unmap;
5287         }
5288
5289         bp->fw_ver = REG_RD_IND(bp, HOST_VIEW_SHMEM_BASE +
5290                                 BNX2_DEV_INFO_BC_REV);
5291
5292         reg = REG_RD_IND(bp, HOST_VIEW_SHMEM_BASE + BNX2_PORT_HW_CFG_MAC_UPPER);
5293         bp->mac_addr[0] = (u8) (reg >> 8);
5294         bp->mac_addr[1] = (u8) reg;
5295
5296         reg = REG_RD_IND(bp, HOST_VIEW_SHMEM_BASE + BNX2_PORT_HW_CFG_MAC_LOWER);
5297         bp->mac_addr[2] = (u8) (reg >> 24);
5298         bp->mac_addr[3] = (u8) (reg >> 16);
5299         bp->mac_addr[4] = (u8) (reg >> 8);
5300         bp->mac_addr[5] = (u8) reg;
5301
5302         bp->tx_ring_size = MAX_TX_DESC_CNT;
5303         bp->rx_ring_size = 100;
5304
5305         bp->rx_csum = 1;
5306
5307         bp->rx_offset = sizeof(struct l2_fhdr) + 2;
5308
5309         bp->tx_quick_cons_trip_int = 20;
5310         bp->tx_quick_cons_trip = 20;
5311         bp->tx_ticks_int = 80;
5312         bp->tx_ticks = 80;
5313
5314         bp->rx_quick_cons_trip_int = 6;
5315         bp->rx_quick_cons_trip = 6;
5316         bp->rx_ticks_int = 18;
5317         bp->rx_ticks = 18;
5318
5319         bp->stats_ticks = 1000000 & 0xffff00;
5320
5321         bp->timer_interval =  HZ;
5322         bp->current_interval =  HZ;
5323
5324         /* Disable WOL support if we are running on a SERDES chip. */
5325         if (CHIP_BOND_ID(bp) & CHIP_BOND_ID_SERDES_BIT) {
5326                 bp->phy_flags |= PHY_SERDES_FLAG;
5327                 bp->flags |= NO_WOL_FLAG;
5328         }
5329
5330         if (CHIP_ID(bp) == CHIP_ID_5706_A0) {
5331                 bp->tx_quick_cons_trip_int =
5332                         bp->tx_quick_cons_trip;
5333                 bp->tx_ticks_int = bp->tx_ticks;
5334                 bp->rx_quick_cons_trip_int =
5335                         bp->rx_quick_cons_trip;
5336                 bp->rx_ticks_int = bp->rx_ticks;
5337                 bp->comp_prod_trip_int = bp->comp_prod_trip;
5338                 bp->com_ticks_int = bp->com_ticks;
5339                 bp->cmd_ticks_int = bp->cmd_ticks;
5340         }
5341
5342         bp->autoneg = AUTONEG_SPEED | AUTONEG_FLOW_CTRL;
5343         bp->req_line_speed = 0;
5344         if (bp->phy_flags & PHY_SERDES_FLAG) {
5345                 bp->advertising = ETHTOOL_ALL_FIBRE_SPEED | ADVERTISED_Autoneg;
5346
5347                 reg = REG_RD_IND(bp, HOST_VIEW_SHMEM_BASE +
5348                                  BNX2_PORT_HW_CFG_CONFIG);
5349                 reg &= BNX2_PORT_HW_CFG_CFG_DFLT_LINK_MASK;
5350                 if (reg == BNX2_PORT_HW_CFG_CFG_DFLT_LINK_1G) {
5351                         bp->autoneg = 0;
5352                         bp->req_line_speed = bp->line_speed = SPEED_1000;
5353                         bp->req_duplex = DUPLEX_FULL;
5354                 }
5355         }
5356         else {
5357                 bp->advertising = ETHTOOL_ALL_COPPER_SPEED | ADVERTISED_Autoneg;
5358         }
5359
5360         bp->req_flow_ctrl = FLOW_CTRL_RX | FLOW_CTRL_TX;
5361
5362         init_timer(&bp->timer);
5363         bp->timer.expires = RUN_AT(bp->timer_interval);
5364         bp->timer.data = (unsigned long) bp;
5365         bp->timer.function = bnx2_timer;
5366
5367         return 0;
5368
5369 err_out_unmap:
5370         if (bp->regview) {
5371                 iounmap(bp->regview);
5372         }
5373
5374 err_out_release:
5375         pci_release_regions(pdev);
5376
5377 err_out_disable:
5378         pci_disable_device(pdev);
5379         pci_set_drvdata(pdev, NULL);
5380
5381 err_out:
5382         return rc;
5383 }
5384
5385 static int __devinit
5386 bnx2_init_one(struct pci_dev *pdev, const struct pci_device_id *ent)
5387 {
5388         static int version_printed = 0;
5389         struct net_device *dev = NULL;
5390         struct bnx2 *bp;
5391         int rc, i;
5392
5393         if (version_printed++ == 0)
5394                 printk(KERN_INFO "%s", version);
5395
5396         /* dev zeroed in init_etherdev */
5397         dev = alloc_etherdev(sizeof(*bp));
5398
5399         if (!dev)
5400                 return -ENOMEM;
5401
5402         rc = bnx2_init_board(pdev, dev);
5403         if (rc < 0) {
5404                 free_netdev(dev);
5405                 return rc;
5406         }
5407
5408         dev->open = bnx2_open;
5409         dev->hard_start_xmit = bnx2_start_xmit;
5410         dev->stop = bnx2_close;
5411         dev->get_stats = bnx2_get_stats;
5412         dev->set_multicast_list = bnx2_set_rx_mode;
5413         dev->do_ioctl = bnx2_ioctl;
5414         dev->set_mac_address = bnx2_change_mac_addr;
5415         dev->change_mtu = bnx2_change_mtu;
5416         dev->tx_timeout = bnx2_tx_timeout;
5417         dev->watchdog_timeo = TX_TIMEOUT;
5418 #ifdef BCM_VLAN
5419         dev->vlan_rx_register = bnx2_vlan_rx_register;
5420         dev->vlan_rx_kill_vid = bnx2_vlan_rx_kill_vid;
5421 #endif
5422         dev->poll = bnx2_poll;
5423         dev->ethtool_ops = &bnx2_ethtool_ops;
5424         dev->weight = 64;
5425
5426         bp = dev->priv;
5427
5428 #if defined(HAVE_POLL_CONTROLLER) || defined(CONFIG_NET_POLL_CONTROLLER)
5429         dev->poll_controller = poll_bnx2;
5430 #endif
5431
5432         if ((rc = register_netdev(dev))) {
5433                 printk(KERN_ERR PFX "Cannot register net device\n");
5434                 if (bp->regview)
5435                         iounmap(bp->regview);
5436                 pci_release_regions(pdev);
5437                 pci_disable_device(pdev);
5438                 pci_set_drvdata(pdev, NULL);
5439                 free_netdev(dev);
5440                 return rc;
5441         }
5442
5443         pci_set_drvdata(pdev, dev);
5444
5445         memcpy(dev->dev_addr, bp->mac_addr, 6);
5446         bp->name = board_info[ent->driver_data].name,
5447         printk(KERN_INFO "%s: %s (%c%d) PCI%s %s %dMHz found at mem %lx, "
5448                 "IRQ %d, ",
5449                 dev->name,
5450                 bp->name,
5451                 ((CHIP_ID(bp) & 0xf000) >> 12) + 'A',
5452                 ((CHIP_ID(bp) & 0x0ff0) >> 4),
5453                 ((bp->flags & PCIX_FLAG) ? "-X" : ""),
5454                 ((bp->flags & PCI_32BIT_FLAG) ? "32-bit" : "64-bit"),
5455                 bp->bus_speed_mhz,
5456                 dev->base_addr,
5457                 bp->pdev->irq);
5458
5459         printk("node addr ");
5460         for (i = 0; i < 6; i++)
5461                 printk("%2.2x", dev->dev_addr[i]);
5462         printk("\n");
5463
5464         dev->features |= NETIF_F_SG;
5465         if (bp->flags & USING_DAC_FLAG)
5466                 dev->features |= NETIF_F_HIGHDMA;
5467         dev->features |= NETIF_F_IP_CSUM;
5468 #ifdef BCM_VLAN
5469         dev->features |= NETIF_F_HW_VLAN_TX | NETIF_F_HW_VLAN_RX;
5470 #endif
5471 #ifdef BCM_TSO
5472         dev->features |= NETIF_F_TSO;
5473 #endif
5474
5475         netif_carrier_off(bp->dev);
5476
5477         return 0;
5478 }
5479
5480 static void __devexit
5481 bnx2_remove_one(struct pci_dev *pdev)
5482 {
5483         struct net_device *dev = pci_get_drvdata(pdev);
5484         struct bnx2 *bp = dev->priv;
5485
5486         flush_scheduled_work();
5487
5488         unregister_netdev(dev);
5489
5490         if (bp->regview)
5491                 iounmap(bp->regview);
5492
5493         free_netdev(dev);
5494         pci_release_regions(pdev);
5495         pci_disable_device(pdev);
5496         pci_set_drvdata(pdev, NULL);
5497 }
5498
5499 static int
5500 bnx2_suspend(struct pci_dev *pdev, u32 state)
5501 {
5502         struct net_device *dev = pci_get_drvdata(pdev);
5503         struct bnx2 *bp = dev->priv;
5504         u32 reset_code;
5505
5506         if (!netif_running(dev))
5507                 return 0;
5508
5509         bnx2_netif_stop(bp);
5510         netif_device_detach(dev);
5511         del_timer_sync(&bp->timer);
5512         if (bp->wol)
5513                 reset_code = BNX2_DRV_MSG_CODE_SUSPEND_WOL;
5514         else
5515                 reset_code = BNX2_DRV_MSG_CODE_SUSPEND_NO_WOL;
5516         bnx2_reset_chip(bp, reset_code);
5517         bnx2_free_skbs(bp);
5518         bnx2_set_power_state(bp, state);
5519         return 0;
5520 }
5521
5522 static int
5523 bnx2_resume(struct pci_dev *pdev)
5524 {
5525         struct net_device *dev = pci_get_drvdata(pdev);
5526         struct bnx2 *bp = dev->priv;
5527
5528         if (!netif_running(dev))
5529                 return 0;
5530
5531         bnx2_set_power_state(bp, 0);
5532         netif_device_attach(dev);
5533         bnx2_init_nic(bp);
5534         bnx2_netif_start(bp);
5535         return 0;
5536 }
5537
5538 static struct pci_driver bnx2_pci_driver = {
5539         .name           = DRV_MODULE_NAME,
5540         .id_table       = bnx2_pci_tbl,
5541         .probe          = bnx2_init_one,
5542         .remove         = __devexit_p(bnx2_remove_one),
5543         .suspend        = bnx2_suspend,
5544         .resume         = bnx2_resume,
5545 };
5546
5547 static int __init bnx2_init(void)
5548 {
5549         return pci_module_init(&bnx2_pci_driver);
5550 }
5551
5552 static void __exit bnx2_cleanup(void)
5553 {
5554         pci_unregister_driver(&bnx2_pci_driver);
5555 }
5556
5557 module_init(bnx2_init);
5558 module_exit(bnx2_cleanup);
5559
5560
5561