1 /* bnx2.c: Broadcom NX2 network driver.
3 * Copyright (c) 2004-2008 Broadcom Corporation
5 * This program is free software; you can redistribute it and/or modify
6 * it under the terms of the GNU General Public License as published by
7 * the Free Software Foundation.
9 * Written by: Michael Chan (mchan@broadcom.com)
13 #include <linux/module.h>
14 #include <linux/moduleparam.h>
16 #include <linux/kernel.h>
17 #include <linux/timer.h>
18 #include <linux/errno.h>
19 #include <linux/ioport.h>
20 #include <linux/slab.h>
21 #include <linux/vmalloc.h>
22 #include <linux/interrupt.h>
23 #include <linux/pci.h>
24 #include <linux/init.h>
25 #include <linux/netdevice.h>
26 #include <linux/etherdevice.h>
27 #include <linux/skbuff.h>
28 #include <linux/dma-mapping.h>
29 #include <linux/bitops.h>
32 #include <linux/delay.h>
33 #include <asm/byteorder.h>
35 #include <linux/time.h>
36 #include <linux/ethtool.h>
37 #include <linux/mii.h>
38 #ifdef NETIF_F_HW_VLAN_TX
39 #include <linux/if_vlan.h>
44 #include <net/checksum.h>
45 #include <linux/workqueue.h>
46 #include <linux/crc32.h>
47 #include <linux/prefetch.h>
48 #include <linux/cache.h>
49 #include <linux/zlib.h>
55 #define FW_BUF_SIZE 0x10000
57 #define DRV_MODULE_NAME "bnx2"
58 #define PFX DRV_MODULE_NAME ": "
59 #define DRV_MODULE_VERSION "1.7.5"
60 #define DRV_MODULE_RELDATE "April 29, 2008"
62 #define RUN_AT(x) (jiffies + (x))
64 /* Time in jiffies before concluding the transmitter is hung. */
65 #define TX_TIMEOUT (5*HZ)
67 static char version[] __devinitdata =
68 "Broadcom NetXtreme II Gigabit Ethernet Driver " DRV_MODULE_NAME " v" DRV_MODULE_VERSION " (" DRV_MODULE_RELDATE ")\n";
70 MODULE_AUTHOR("Michael Chan <mchan@broadcom.com>");
71 MODULE_DESCRIPTION("Broadcom NetXtreme II BCM5706/5708 Driver");
72 MODULE_LICENSE("GPL");
73 MODULE_VERSION(DRV_MODULE_VERSION);
75 static int disable_msi = 0;
77 module_param(disable_msi, int, 0);
78 MODULE_PARM_DESC(disable_msi, "Disable Message Signaled Interrupt (MSI)");
92 /* indexed by board_t, above */
95 } board_info[] __devinitdata = {
96 { "Broadcom NetXtreme II BCM5706 1000Base-T" },
97 { "HP NC370T Multifunction Gigabit Server Adapter" },
98 { "HP NC370i Multifunction Gigabit Server Adapter" },
99 { "Broadcom NetXtreme II BCM5706 1000Base-SX" },
100 { "HP NC370F Multifunction Gigabit Server Adapter" },
101 { "Broadcom NetXtreme II BCM5708 1000Base-T" },
102 { "Broadcom NetXtreme II BCM5708 1000Base-SX" },
103 { "Broadcom NetXtreme II BCM5709 1000Base-T" },
104 { "Broadcom NetXtreme II BCM5709 1000Base-SX" },
107 static struct pci_device_id bnx2_pci_tbl[] = {
108 { PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_NX2_5706,
109 PCI_VENDOR_ID_HP, 0x3101, 0, 0, NC370T },
110 { PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_NX2_5706,
111 PCI_VENDOR_ID_HP, 0x3106, 0, 0, NC370I },
112 { PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_NX2_5706,
113 PCI_ANY_ID, PCI_ANY_ID, 0, 0, BCM5706 },
114 { PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_NX2_5708,
115 PCI_ANY_ID, PCI_ANY_ID, 0, 0, BCM5708 },
116 { PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_NX2_5706S,
117 PCI_VENDOR_ID_HP, 0x3102, 0, 0, NC370F },
118 { PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_NX2_5706S,
119 PCI_ANY_ID, PCI_ANY_ID, 0, 0, BCM5706S },
120 { PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_NX2_5708S,
121 PCI_ANY_ID, PCI_ANY_ID, 0, 0, BCM5708S },
122 { PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_NX2_5709,
123 PCI_ANY_ID, PCI_ANY_ID, 0, 0, BCM5709 },
124 { PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_NX2_5709S,
125 PCI_ANY_ID, PCI_ANY_ID, 0, 0, BCM5709S },
129 static struct flash_spec flash_table[] =
131 #define BUFFERED_FLAGS (BNX2_NV_BUFFERED | BNX2_NV_TRANSLATE)
132 #define NONBUFFERED_FLAGS (BNX2_NV_WREN)
134 {0x00000000, 0x40830380, 0x009f0081, 0xa184a053, 0xaf000400,
135 BUFFERED_FLAGS, SEEPROM_PAGE_BITS, SEEPROM_PAGE_SIZE,
136 SEEPROM_BYTE_ADDR_MASK, SEEPROM_TOTAL_SIZE,
138 /* Expansion entry 0001 */
139 {0x08000002, 0x4b808201, 0x00050081, 0x03840253, 0xaf020406,
140 NONBUFFERED_FLAGS, SAIFUN_FLASH_PAGE_BITS, SAIFUN_FLASH_PAGE_SIZE,
141 SAIFUN_FLASH_BYTE_ADDR_MASK, 0,
143 /* Saifun SA25F010 (non-buffered flash) */
144 /* strap, cfg1, & write1 need updates */
145 {0x04000001, 0x47808201, 0x00050081, 0x03840253, 0xaf020406,
146 NONBUFFERED_FLAGS, SAIFUN_FLASH_PAGE_BITS, SAIFUN_FLASH_PAGE_SIZE,
147 SAIFUN_FLASH_BYTE_ADDR_MASK, SAIFUN_FLASH_BASE_TOTAL_SIZE*2,
148 "Non-buffered flash (128kB)"},
149 /* Saifun SA25F020 (non-buffered flash) */
150 /* strap, cfg1, & write1 need updates */
151 {0x0c000003, 0x4f808201, 0x00050081, 0x03840253, 0xaf020406,
152 NONBUFFERED_FLAGS, SAIFUN_FLASH_PAGE_BITS, SAIFUN_FLASH_PAGE_SIZE,
153 SAIFUN_FLASH_BYTE_ADDR_MASK, SAIFUN_FLASH_BASE_TOTAL_SIZE*4,
154 "Non-buffered flash (256kB)"},
155 /* Expansion entry 0100 */
156 {0x11000000, 0x53808201, 0x00050081, 0x03840253, 0xaf020406,
157 NONBUFFERED_FLAGS, SAIFUN_FLASH_PAGE_BITS, SAIFUN_FLASH_PAGE_SIZE,
158 SAIFUN_FLASH_BYTE_ADDR_MASK, 0,
160 /* Entry 0101: ST M45PE10 (non-buffered flash, TetonII B0) */
161 {0x19000002, 0x5b808201, 0x000500db, 0x03840253, 0xaf020406,
162 NONBUFFERED_FLAGS, ST_MICRO_FLASH_PAGE_BITS, ST_MICRO_FLASH_PAGE_SIZE,
163 ST_MICRO_FLASH_BYTE_ADDR_MASK, ST_MICRO_FLASH_BASE_TOTAL_SIZE*2,
164 "Entry 0101: ST M45PE10 (128kB non-bufferred)"},
165 /* Entry 0110: ST M45PE20 (non-buffered flash)*/
166 {0x15000001, 0x57808201, 0x000500db, 0x03840253, 0xaf020406,
167 NONBUFFERED_FLAGS, ST_MICRO_FLASH_PAGE_BITS, ST_MICRO_FLASH_PAGE_SIZE,
168 ST_MICRO_FLASH_BYTE_ADDR_MASK, ST_MICRO_FLASH_BASE_TOTAL_SIZE*4,
169 "Entry 0110: ST M45PE20 (256kB non-bufferred)"},
170 /* Saifun SA25F005 (non-buffered flash) */
171 /* strap, cfg1, & write1 need updates */
172 {0x1d000003, 0x5f808201, 0x00050081, 0x03840253, 0xaf020406,
173 NONBUFFERED_FLAGS, SAIFUN_FLASH_PAGE_BITS, SAIFUN_FLASH_PAGE_SIZE,
174 SAIFUN_FLASH_BYTE_ADDR_MASK, SAIFUN_FLASH_BASE_TOTAL_SIZE,
175 "Non-buffered flash (64kB)"},
177 {0x22000000, 0x62808380, 0x009f0081, 0xa184a053, 0xaf000400,
178 BUFFERED_FLAGS, SEEPROM_PAGE_BITS, SEEPROM_PAGE_SIZE,
179 SEEPROM_BYTE_ADDR_MASK, SEEPROM_TOTAL_SIZE,
181 /* Expansion entry 1001 */
182 {0x2a000002, 0x6b808201, 0x00050081, 0x03840253, 0xaf020406,
183 NONBUFFERED_FLAGS, SAIFUN_FLASH_PAGE_BITS, SAIFUN_FLASH_PAGE_SIZE,
184 SAIFUN_FLASH_BYTE_ADDR_MASK, 0,
186 /* Expansion entry 1010 */
187 {0x26000001, 0x67808201, 0x00050081, 0x03840253, 0xaf020406,
188 NONBUFFERED_FLAGS, SAIFUN_FLASH_PAGE_BITS, SAIFUN_FLASH_PAGE_SIZE,
189 SAIFUN_FLASH_BYTE_ADDR_MASK, 0,
191 /* ATMEL AT45DB011B (buffered flash) */
192 {0x2e000003, 0x6e808273, 0x00570081, 0x68848353, 0xaf000400,
193 BUFFERED_FLAGS, BUFFERED_FLASH_PAGE_BITS, BUFFERED_FLASH_PAGE_SIZE,
194 BUFFERED_FLASH_BYTE_ADDR_MASK, BUFFERED_FLASH_TOTAL_SIZE,
195 "Buffered flash (128kB)"},
196 /* Expansion entry 1100 */
197 {0x33000000, 0x73808201, 0x00050081, 0x03840253, 0xaf020406,
198 NONBUFFERED_FLAGS, SAIFUN_FLASH_PAGE_BITS, SAIFUN_FLASH_PAGE_SIZE,
199 SAIFUN_FLASH_BYTE_ADDR_MASK, 0,
201 /* Expansion entry 1101 */
202 {0x3b000002, 0x7b808201, 0x00050081, 0x03840253, 0xaf020406,
203 NONBUFFERED_FLAGS, SAIFUN_FLASH_PAGE_BITS, SAIFUN_FLASH_PAGE_SIZE,
204 SAIFUN_FLASH_BYTE_ADDR_MASK, 0,
206 /* Ateml Expansion entry 1110 */
207 {0x37000001, 0x76808273, 0x00570081, 0x68848353, 0xaf000400,
208 BUFFERED_FLAGS, BUFFERED_FLASH_PAGE_BITS, BUFFERED_FLASH_PAGE_SIZE,
209 BUFFERED_FLASH_BYTE_ADDR_MASK, 0,
210 "Entry 1110 (Atmel)"},
211 /* ATMEL AT45DB021B (buffered flash) */
212 {0x3f000003, 0x7e808273, 0x00570081, 0x68848353, 0xaf000400,
213 BUFFERED_FLAGS, BUFFERED_FLASH_PAGE_BITS, BUFFERED_FLASH_PAGE_SIZE,
214 BUFFERED_FLASH_BYTE_ADDR_MASK, BUFFERED_FLASH_TOTAL_SIZE*2,
215 "Buffered flash (256kB)"},
218 static struct flash_spec flash_5709 = {
219 .flags = BNX2_NV_BUFFERED,
220 .page_bits = BCM5709_FLASH_PAGE_BITS,
221 .page_size = BCM5709_FLASH_PAGE_SIZE,
222 .addr_mask = BCM5709_FLASH_BYTE_ADDR_MASK,
223 .total_size = BUFFERED_FLASH_TOTAL_SIZE*2,
224 .name = "5709 Buffered flash (256kB)",
227 MODULE_DEVICE_TABLE(pci, bnx2_pci_tbl);
229 static inline u32 bnx2_tx_avail(struct bnx2 *bp, struct bnx2_napi *bnapi)
235 /* The ring uses 256 indices for 255 entries, one of them
236 * needs to be skipped.
238 diff = bp->tx_prod - bnapi->tx_cons;
239 if (unlikely(diff >= TX_DESC_CNT)) {
241 if (diff == TX_DESC_CNT)
242 diff = MAX_TX_DESC_CNT;
244 return (bp->tx_ring_size - diff);
248 bnx2_reg_rd_ind(struct bnx2 *bp, u32 offset)
252 spin_lock_bh(&bp->indirect_lock);
253 REG_WR(bp, BNX2_PCICFG_REG_WINDOW_ADDRESS, offset);
254 val = REG_RD(bp, BNX2_PCICFG_REG_WINDOW);
255 spin_unlock_bh(&bp->indirect_lock);
260 bnx2_reg_wr_ind(struct bnx2 *bp, u32 offset, u32 val)
262 spin_lock_bh(&bp->indirect_lock);
263 REG_WR(bp, BNX2_PCICFG_REG_WINDOW_ADDRESS, offset);
264 REG_WR(bp, BNX2_PCICFG_REG_WINDOW, val);
265 spin_unlock_bh(&bp->indirect_lock);
269 bnx2_shmem_wr(struct bnx2 *bp, u32 offset, u32 val)
271 bnx2_reg_wr_ind(bp, bp->shmem_base + offset, val);
275 bnx2_shmem_rd(struct bnx2 *bp, u32 offset)
277 return (bnx2_reg_rd_ind(bp, bp->shmem_base + offset));
281 bnx2_ctx_wr(struct bnx2 *bp, u32 cid_addr, u32 offset, u32 val)
284 spin_lock_bh(&bp->indirect_lock);
285 if (CHIP_NUM(bp) == CHIP_NUM_5709) {
288 REG_WR(bp, BNX2_CTX_CTX_DATA, val);
289 REG_WR(bp, BNX2_CTX_CTX_CTRL,
290 offset | BNX2_CTX_CTX_CTRL_WRITE_REQ);
291 for (i = 0; i < 5; i++) {
293 val = REG_RD(bp, BNX2_CTX_CTX_CTRL);
294 if ((val & BNX2_CTX_CTX_CTRL_WRITE_REQ) == 0)
299 REG_WR(bp, BNX2_CTX_DATA_ADR, offset);
300 REG_WR(bp, BNX2_CTX_DATA, val);
302 spin_unlock_bh(&bp->indirect_lock);
306 bnx2_read_phy(struct bnx2 *bp, u32 reg, u32 *val)
311 if (bp->phy_flags & BNX2_PHY_FLAG_INT_MODE_AUTO_POLLING) {
312 val1 = REG_RD(bp, BNX2_EMAC_MDIO_MODE);
313 val1 &= ~BNX2_EMAC_MDIO_MODE_AUTO_POLL;
315 REG_WR(bp, BNX2_EMAC_MDIO_MODE, val1);
316 REG_RD(bp, BNX2_EMAC_MDIO_MODE);
321 val1 = (bp->phy_addr << 21) | (reg << 16) |
322 BNX2_EMAC_MDIO_COMM_COMMAND_READ | BNX2_EMAC_MDIO_COMM_DISEXT |
323 BNX2_EMAC_MDIO_COMM_START_BUSY;
324 REG_WR(bp, BNX2_EMAC_MDIO_COMM, val1);
326 for (i = 0; i < 50; i++) {
329 val1 = REG_RD(bp, BNX2_EMAC_MDIO_COMM);
330 if (!(val1 & BNX2_EMAC_MDIO_COMM_START_BUSY)) {
333 val1 = REG_RD(bp, BNX2_EMAC_MDIO_COMM);
334 val1 &= BNX2_EMAC_MDIO_COMM_DATA;
340 if (val1 & BNX2_EMAC_MDIO_COMM_START_BUSY) {
349 if (bp->phy_flags & BNX2_PHY_FLAG_INT_MODE_AUTO_POLLING) {
350 val1 = REG_RD(bp, BNX2_EMAC_MDIO_MODE);
351 val1 |= BNX2_EMAC_MDIO_MODE_AUTO_POLL;
353 REG_WR(bp, BNX2_EMAC_MDIO_MODE, val1);
354 REG_RD(bp, BNX2_EMAC_MDIO_MODE);
363 bnx2_write_phy(struct bnx2 *bp, u32 reg, u32 val)
368 if (bp->phy_flags & BNX2_PHY_FLAG_INT_MODE_AUTO_POLLING) {
369 val1 = REG_RD(bp, BNX2_EMAC_MDIO_MODE);
370 val1 &= ~BNX2_EMAC_MDIO_MODE_AUTO_POLL;
372 REG_WR(bp, BNX2_EMAC_MDIO_MODE, val1);
373 REG_RD(bp, BNX2_EMAC_MDIO_MODE);
378 val1 = (bp->phy_addr << 21) | (reg << 16) | val |
379 BNX2_EMAC_MDIO_COMM_COMMAND_WRITE |
380 BNX2_EMAC_MDIO_COMM_START_BUSY | BNX2_EMAC_MDIO_COMM_DISEXT;
381 REG_WR(bp, BNX2_EMAC_MDIO_COMM, val1);
383 for (i = 0; i < 50; i++) {
386 val1 = REG_RD(bp, BNX2_EMAC_MDIO_COMM);
387 if (!(val1 & BNX2_EMAC_MDIO_COMM_START_BUSY)) {
393 if (val1 & BNX2_EMAC_MDIO_COMM_START_BUSY)
398 if (bp->phy_flags & BNX2_PHY_FLAG_INT_MODE_AUTO_POLLING) {
399 val1 = REG_RD(bp, BNX2_EMAC_MDIO_MODE);
400 val1 |= BNX2_EMAC_MDIO_MODE_AUTO_POLL;
402 REG_WR(bp, BNX2_EMAC_MDIO_MODE, val1);
403 REG_RD(bp, BNX2_EMAC_MDIO_MODE);
412 bnx2_disable_int(struct bnx2 *bp)
415 struct bnx2_napi *bnapi;
417 for (i = 0; i < bp->irq_nvecs; i++) {
418 bnapi = &bp->bnx2_napi[i];
419 REG_WR(bp, BNX2_PCICFG_INT_ACK_CMD, bnapi->int_num |
420 BNX2_PCICFG_INT_ACK_CMD_MASK_INT);
422 REG_RD(bp, BNX2_PCICFG_INT_ACK_CMD);
426 bnx2_enable_int(struct bnx2 *bp)
429 struct bnx2_napi *bnapi;
431 for (i = 0; i < bp->irq_nvecs; i++) {
432 bnapi = &bp->bnx2_napi[i];
434 REG_WR(bp, BNX2_PCICFG_INT_ACK_CMD, bnapi->int_num |
435 BNX2_PCICFG_INT_ACK_CMD_INDEX_VALID |
436 BNX2_PCICFG_INT_ACK_CMD_MASK_INT |
437 bnapi->last_status_idx);
439 REG_WR(bp, BNX2_PCICFG_INT_ACK_CMD, bnapi->int_num |
440 BNX2_PCICFG_INT_ACK_CMD_INDEX_VALID |
441 bnapi->last_status_idx);
443 REG_WR(bp, BNX2_HC_COMMAND, bp->hc_cmd | BNX2_HC_COMMAND_COAL_NOW);
447 bnx2_disable_int_sync(struct bnx2 *bp)
451 atomic_inc(&bp->intr_sem);
452 bnx2_disable_int(bp);
453 for (i = 0; i < bp->irq_nvecs; i++)
454 synchronize_irq(bp->irq_tbl[i].vector);
458 bnx2_napi_disable(struct bnx2 *bp)
462 for (i = 0; i < bp->irq_nvecs; i++)
463 napi_disable(&bp->bnx2_napi[i].napi);
467 bnx2_napi_enable(struct bnx2 *bp)
471 for (i = 0; i < bp->irq_nvecs; i++)
472 napi_enable(&bp->bnx2_napi[i].napi);
476 bnx2_netif_stop(struct bnx2 *bp)
478 bnx2_disable_int_sync(bp);
479 if (netif_running(bp->dev)) {
480 bnx2_napi_disable(bp);
481 netif_tx_disable(bp->dev);
482 bp->dev->trans_start = jiffies; /* prevent tx timeout */
487 bnx2_netif_start(struct bnx2 *bp)
489 if (atomic_dec_and_test(&bp->intr_sem)) {
490 if (netif_running(bp->dev)) {
491 netif_wake_queue(bp->dev);
492 bnx2_napi_enable(bp);
499 bnx2_free_mem(struct bnx2 *bp)
503 for (i = 0; i < bp->ctx_pages; i++) {
504 if (bp->ctx_blk[i]) {
505 pci_free_consistent(bp->pdev, BCM_PAGE_SIZE,
507 bp->ctx_blk_mapping[i]);
508 bp->ctx_blk[i] = NULL;
511 if (bp->status_blk) {
512 pci_free_consistent(bp->pdev, bp->status_stats_size,
513 bp->status_blk, bp->status_blk_mapping);
514 bp->status_blk = NULL;
515 bp->stats_blk = NULL;
517 if (bp->tx_desc_ring) {
518 pci_free_consistent(bp->pdev, TXBD_RING_SIZE,
519 bp->tx_desc_ring, bp->tx_desc_mapping);
520 bp->tx_desc_ring = NULL;
522 kfree(bp->tx_buf_ring);
523 bp->tx_buf_ring = NULL;
524 for (i = 0; i < bp->rx_max_ring; i++) {
525 if (bp->rx_desc_ring[i])
526 pci_free_consistent(bp->pdev, RXBD_RING_SIZE,
528 bp->rx_desc_mapping[i]);
529 bp->rx_desc_ring[i] = NULL;
531 vfree(bp->rx_buf_ring);
532 bp->rx_buf_ring = NULL;
533 for (i = 0; i < bp->rx_max_pg_ring; i++) {
534 if (bp->rx_pg_desc_ring[i])
535 pci_free_consistent(bp->pdev, RXBD_RING_SIZE,
536 bp->rx_pg_desc_ring[i],
537 bp->rx_pg_desc_mapping[i]);
538 bp->rx_pg_desc_ring[i] = NULL;
541 vfree(bp->rx_pg_ring);
542 bp->rx_pg_ring = NULL;
546 bnx2_alloc_mem(struct bnx2 *bp)
548 int i, status_blk_size;
550 bp->tx_buf_ring = kzalloc(SW_TXBD_RING_SIZE, GFP_KERNEL);
551 if (bp->tx_buf_ring == NULL)
554 bp->tx_desc_ring = pci_alloc_consistent(bp->pdev, TXBD_RING_SIZE,
555 &bp->tx_desc_mapping);
556 if (bp->tx_desc_ring == NULL)
559 bp->rx_buf_ring = vmalloc(SW_RXBD_RING_SIZE * bp->rx_max_ring);
560 if (bp->rx_buf_ring == NULL)
563 memset(bp->rx_buf_ring, 0, SW_RXBD_RING_SIZE * bp->rx_max_ring);
565 for (i = 0; i < bp->rx_max_ring; i++) {
566 bp->rx_desc_ring[i] =
567 pci_alloc_consistent(bp->pdev, RXBD_RING_SIZE,
568 &bp->rx_desc_mapping[i]);
569 if (bp->rx_desc_ring[i] == NULL)
574 if (bp->rx_pg_ring_size) {
575 bp->rx_pg_ring = vmalloc(SW_RXPG_RING_SIZE *
577 if (bp->rx_pg_ring == NULL)
580 memset(bp->rx_pg_ring, 0, SW_RXPG_RING_SIZE *
584 for (i = 0; i < bp->rx_max_pg_ring; i++) {
585 bp->rx_pg_desc_ring[i] =
586 pci_alloc_consistent(bp->pdev, RXBD_RING_SIZE,
587 &bp->rx_pg_desc_mapping[i]);
588 if (bp->rx_pg_desc_ring[i] == NULL)
593 /* Combine status and statistics blocks into one allocation. */
594 status_blk_size = L1_CACHE_ALIGN(sizeof(struct status_block));
595 if (bp->flags & BNX2_FLAG_MSIX_CAP)
596 status_blk_size = L1_CACHE_ALIGN(BNX2_MAX_MSIX_HW_VEC *
597 BNX2_SBLK_MSIX_ALIGN_SIZE);
598 bp->status_stats_size = status_blk_size +
599 sizeof(struct statistics_block);
601 bp->status_blk = pci_alloc_consistent(bp->pdev, bp->status_stats_size,
602 &bp->status_blk_mapping);
603 if (bp->status_blk == NULL)
606 memset(bp->status_blk, 0, bp->status_stats_size);
608 bp->bnx2_napi[0].status_blk = bp->status_blk;
609 if (bp->flags & BNX2_FLAG_MSIX_CAP) {
610 for (i = 1; i < BNX2_MAX_MSIX_VEC; i++) {
611 struct bnx2_napi *bnapi = &bp->bnx2_napi[i];
613 bnapi->status_blk_msix = (void *)
614 ((unsigned long) bp->status_blk +
615 BNX2_SBLK_MSIX_ALIGN_SIZE * i);
616 bnapi->int_num = i << 24;
620 bp->stats_blk = (void *) ((unsigned long) bp->status_blk +
623 bp->stats_blk_mapping = bp->status_blk_mapping + status_blk_size;
625 if (CHIP_NUM(bp) == CHIP_NUM_5709) {
626 bp->ctx_pages = 0x2000 / BCM_PAGE_SIZE;
627 if (bp->ctx_pages == 0)
629 for (i = 0; i < bp->ctx_pages; i++) {
630 bp->ctx_blk[i] = pci_alloc_consistent(bp->pdev,
632 &bp->ctx_blk_mapping[i]);
633 if (bp->ctx_blk[i] == NULL)
645 bnx2_report_fw_link(struct bnx2 *bp)
647 u32 fw_link_status = 0;
649 if (bp->phy_flags & BNX2_PHY_FLAG_REMOTE_PHY_CAP)
655 switch (bp->line_speed) {
657 if (bp->duplex == DUPLEX_HALF)
658 fw_link_status = BNX2_LINK_STATUS_10HALF;
660 fw_link_status = BNX2_LINK_STATUS_10FULL;
663 if (bp->duplex == DUPLEX_HALF)
664 fw_link_status = BNX2_LINK_STATUS_100HALF;
666 fw_link_status = BNX2_LINK_STATUS_100FULL;
669 if (bp->duplex == DUPLEX_HALF)
670 fw_link_status = BNX2_LINK_STATUS_1000HALF;
672 fw_link_status = BNX2_LINK_STATUS_1000FULL;
675 if (bp->duplex == DUPLEX_HALF)
676 fw_link_status = BNX2_LINK_STATUS_2500HALF;
678 fw_link_status = BNX2_LINK_STATUS_2500FULL;
682 fw_link_status |= BNX2_LINK_STATUS_LINK_UP;
685 fw_link_status |= BNX2_LINK_STATUS_AN_ENABLED;
687 bnx2_read_phy(bp, bp->mii_bmsr, &bmsr);
688 bnx2_read_phy(bp, bp->mii_bmsr, &bmsr);
690 if (!(bmsr & BMSR_ANEGCOMPLETE) ||
691 bp->phy_flags & BNX2_PHY_FLAG_PARALLEL_DETECT)
692 fw_link_status |= BNX2_LINK_STATUS_PARALLEL_DET;
694 fw_link_status |= BNX2_LINK_STATUS_AN_COMPLETE;
698 fw_link_status = BNX2_LINK_STATUS_LINK_DOWN;
700 bnx2_shmem_wr(bp, BNX2_LINK_STATUS, fw_link_status);
704 bnx2_xceiver_str(struct bnx2 *bp)
706 return ((bp->phy_port == PORT_FIBRE) ? "SerDes" :
707 ((bp->phy_flags & BNX2_PHY_FLAG_SERDES) ? "Remote Copper" :
712 bnx2_report_link(struct bnx2 *bp)
715 netif_carrier_on(bp->dev);
716 printk(KERN_INFO PFX "%s NIC %s Link is Up, ", bp->dev->name,
717 bnx2_xceiver_str(bp));
719 printk("%d Mbps ", bp->line_speed);
721 if (bp->duplex == DUPLEX_FULL)
722 printk("full duplex");
724 printk("half duplex");
727 if (bp->flow_ctrl & FLOW_CTRL_RX) {
728 printk(", receive ");
729 if (bp->flow_ctrl & FLOW_CTRL_TX)
730 printk("& transmit ");
733 printk(", transmit ");
735 printk("flow control ON");
740 netif_carrier_off(bp->dev);
741 printk(KERN_ERR PFX "%s NIC %s Link is Down\n", bp->dev->name,
742 bnx2_xceiver_str(bp));
745 bnx2_report_fw_link(bp);
749 bnx2_resolve_flow_ctrl(struct bnx2 *bp)
751 u32 local_adv, remote_adv;
754 if ((bp->autoneg & (AUTONEG_SPEED | AUTONEG_FLOW_CTRL)) !=
755 (AUTONEG_SPEED | AUTONEG_FLOW_CTRL)) {
757 if (bp->duplex == DUPLEX_FULL) {
758 bp->flow_ctrl = bp->req_flow_ctrl;
763 if (bp->duplex != DUPLEX_FULL) {
767 if ((bp->phy_flags & BNX2_PHY_FLAG_SERDES) &&
768 (CHIP_NUM(bp) == CHIP_NUM_5708)) {
771 bnx2_read_phy(bp, BCM5708S_1000X_STAT1, &val);
772 if (val & BCM5708S_1000X_STAT1_TX_PAUSE)
773 bp->flow_ctrl |= FLOW_CTRL_TX;
774 if (val & BCM5708S_1000X_STAT1_RX_PAUSE)
775 bp->flow_ctrl |= FLOW_CTRL_RX;
779 bnx2_read_phy(bp, bp->mii_adv, &local_adv);
780 bnx2_read_phy(bp, bp->mii_lpa, &remote_adv);
782 if (bp->phy_flags & BNX2_PHY_FLAG_SERDES) {
783 u32 new_local_adv = 0;
784 u32 new_remote_adv = 0;
786 if (local_adv & ADVERTISE_1000XPAUSE)
787 new_local_adv |= ADVERTISE_PAUSE_CAP;
788 if (local_adv & ADVERTISE_1000XPSE_ASYM)
789 new_local_adv |= ADVERTISE_PAUSE_ASYM;
790 if (remote_adv & ADVERTISE_1000XPAUSE)
791 new_remote_adv |= ADVERTISE_PAUSE_CAP;
792 if (remote_adv & ADVERTISE_1000XPSE_ASYM)
793 new_remote_adv |= ADVERTISE_PAUSE_ASYM;
795 local_adv = new_local_adv;
796 remote_adv = new_remote_adv;
799 /* See Table 28B-3 of 802.3ab-1999 spec. */
800 if (local_adv & ADVERTISE_PAUSE_CAP) {
801 if(local_adv & ADVERTISE_PAUSE_ASYM) {
802 if (remote_adv & ADVERTISE_PAUSE_CAP) {
803 bp->flow_ctrl = FLOW_CTRL_TX | FLOW_CTRL_RX;
805 else if (remote_adv & ADVERTISE_PAUSE_ASYM) {
806 bp->flow_ctrl = FLOW_CTRL_RX;
810 if (remote_adv & ADVERTISE_PAUSE_CAP) {
811 bp->flow_ctrl = FLOW_CTRL_TX | FLOW_CTRL_RX;
815 else if (local_adv & ADVERTISE_PAUSE_ASYM) {
816 if ((remote_adv & ADVERTISE_PAUSE_CAP) &&
817 (remote_adv & ADVERTISE_PAUSE_ASYM)) {
819 bp->flow_ctrl = FLOW_CTRL_TX;
825 bnx2_5709s_linkup(struct bnx2 *bp)
831 bnx2_write_phy(bp, MII_BNX2_BLK_ADDR, MII_BNX2_BLK_ADDR_GP_STATUS);
832 bnx2_read_phy(bp, MII_BNX2_GP_TOP_AN_STATUS1, &val);
833 bnx2_write_phy(bp, MII_BNX2_BLK_ADDR, MII_BNX2_BLK_ADDR_COMBO_IEEEB0);
835 if ((bp->autoneg & AUTONEG_SPEED) == 0) {
836 bp->line_speed = bp->req_line_speed;
837 bp->duplex = bp->req_duplex;
840 speed = val & MII_BNX2_GP_TOP_AN_SPEED_MSK;
842 case MII_BNX2_GP_TOP_AN_SPEED_10:
843 bp->line_speed = SPEED_10;
845 case MII_BNX2_GP_TOP_AN_SPEED_100:
846 bp->line_speed = SPEED_100;
848 case MII_BNX2_GP_TOP_AN_SPEED_1G:
849 case MII_BNX2_GP_TOP_AN_SPEED_1GKV:
850 bp->line_speed = SPEED_1000;
852 case MII_BNX2_GP_TOP_AN_SPEED_2_5G:
853 bp->line_speed = SPEED_2500;
856 if (val & MII_BNX2_GP_TOP_AN_FD)
857 bp->duplex = DUPLEX_FULL;
859 bp->duplex = DUPLEX_HALF;
864 bnx2_5708s_linkup(struct bnx2 *bp)
869 bnx2_read_phy(bp, BCM5708S_1000X_STAT1, &val);
870 switch (val & BCM5708S_1000X_STAT1_SPEED_MASK) {
871 case BCM5708S_1000X_STAT1_SPEED_10:
872 bp->line_speed = SPEED_10;
874 case BCM5708S_1000X_STAT1_SPEED_100:
875 bp->line_speed = SPEED_100;
877 case BCM5708S_1000X_STAT1_SPEED_1G:
878 bp->line_speed = SPEED_1000;
880 case BCM5708S_1000X_STAT1_SPEED_2G5:
881 bp->line_speed = SPEED_2500;
884 if (val & BCM5708S_1000X_STAT1_FD)
885 bp->duplex = DUPLEX_FULL;
887 bp->duplex = DUPLEX_HALF;
893 bnx2_5706s_linkup(struct bnx2 *bp)
895 u32 bmcr, local_adv, remote_adv, common;
898 bp->line_speed = SPEED_1000;
900 bnx2_read_phy(bp, bp->mii_bmcr, &bmcr);
901 if (bmcr & BMCR_FULLDPLX) {
902 bp->duplex = DUPLEX_FULL;
905 bp->duplex = DUPLEX_HALF;
908 if (!(bmcr & BMCR_ANENABLE)) {
912 bnx2_read_phy(bp, bp->mii_adv, &local_adv);
913 bnx2_read_phy(bp, bp->mii_lpa, &remote_adv);
915 common = local_adv & remote_adv;
916 if (common & (ADVERTISE_1000XHALF | ADVERTISE_1000XFULL)) {
918 if (common & ADVERTISE_1000XFULL) {
919 bp->duplex = DUPLEX_FULL;
922 bp->duplex = DUPLEX_HALF;
930 bnx2_copper_linkup(struct bnx2 *bp)
934 bnx2_read_phy(bp, bp->mii_bmcr, &bmcr);
935 if (bmcr & BMCR_ANENABLE) {
936 u32 local_adv, remote_adv, common;
938 bnx2_read_phy(bp, MII_CTRL1000, &local_adv);
939 bnx2_read_phy(bp, MII_STAT1000, &remote_adv);
941 common = local_adv & (remote_adv >> 2);
942 if (common & ADVERTISE_1000FULL) {
943 bp->line_speed = SPEED_1000;
944 bp->duplex = DUPLEX_FULL;
946 else if (common & ADVERTISE_1000HALF) {
947 bp->line_speed = SPEED_1000;
948 bp->duplex = DUPLEX_HALF;
951 bnx2_read_phy(bp, bp->mii_adv, &local_adv);
952 bnx2_read_phy(bp, bp->mii_lpa, &remote_adv);
954 common = local_adv & remote_adv;
955 if (common & ADVERTISE_100FULL) {
956 bp->line_speed = SPEED_100;
957 bp->duplex = DUPLEX_FULL;
959 else if (common & ADVERTISE_100HALF) {
960 bp->line_speed = SPEED_100;
961 bp->duplex = DUPLEX_HALF;
963 else if (common & ADVERTISE_10FULL) {
964 bp->line_speed = SPEED_10;
965 bp->duplex = DUPLEX_FULL;
967 else if (common & ADVERTISE_10HALF) {
968 bp->line_speed = SPEED_10;
969 bp->duplex = DUPLEX_HALF;
978 if (bmcr & BMCR_SPEED100) {
979 bp->line_speed = SPEED_100;
982 bp->line_speed = SPEED_10;
984 if (bmcr & BMCR_FULLDPLX) {
985 bp->duplex = DUPLEX_FULL;
988 bp->duplex = DUPLEX_HALF;
996 bnx2_init_rx_context0(struct bnx2 *bp)
998 u32 val, rx_cid_addr = GET_CID_ADDR(RX_CID);
1000 val = BNX2_L2CTX_CTX_TYPE_CTX_BD_CHN_TYPE_VALUE;
1001 val |= BNX2_L2CTX_CTX_TYPE_SIZE_L2;
1004 if (CHIP_NUM(bp) == CHIP_NUM_5709) {
1005 u32 lo_water, hi_water;
1007 if (bp->flow_ctrl & FLOW_CTRL_TX)
1008 lo_water = BNX2_L2CTX_LO_WATER_MARK_DEFAULT;
1010 lo_water = BNX2_L2CTX_LO_WATER_MARK_DIS;
1011 if (lo_water >= bp->rx_ring_size)
1014 hi_water = bp->rx_ring_size / 4;
1016 if (hi_water <= lo_water)
1019 hi_water /= BNX2_L2CTX_HI_WATER_MARK_SCALE;
1020 lo_water /= BNX2_L2CTX_LO_WATER_MARK_SCALE;
1024 else if (hi_water == 0)
1026 val |= lo_water | (hi_water << BNX2_L2CTX_HI_WATER_MARK_SHIFT);
1028 bnx2_ctx_wr(bp, rx_cid_addr, BNX2_L2CTX_CTX_TYPE, val);
1032 bnx2_set_mac_link(struct bnx2 *bp)
1036 REG_WR(bp, BNX2_EMAC_TX_LENGTHS, 0x2620);
1037 if (bp->link_up && (bp->line_speed == SPEED_1000) &&
1038 (bp->duplex == DUPLEX_HALF)) {
1039 REG_WR(bp, BNX2_EMAC_TX_LENGTHS, 0x26ff);
1042 /* Configure the EMAC mode register. */
1043 val = REG_RD(bp, BNX2_EMAC_MODE);
1045 val &= ~(BNX2_EMAC_MODE_PORT | BNX2_EMAC_MODE_HALF_DUPLEX |
1046 BNX2_EMAC_MODE_MAC_LOOP | BNX2_EMAC_MODE_FORCE_LINK |
1047 BNX2_EMAC_MODE_25G_MODE);
1050 switch (bp->line_speed) {
1052 if (CHIP_NUM(bp) != CHIP_NUM_5706) {
1053 val |= BNX2_EMAC_MODE_PORT_MII_10M;
1058 val |= BNX2_EMAC_MODE_PORT_MII;
1061 val |= BNX2_EMAC_MODE_25G_MODE;
1064 val |= BNX2_EMAC_MODE_PORT_GMII;
1069 val |= BNX2_EMAC_MODE_PORT_GMII;
1072 /* Set the MAC to operate in the appropriate duplex mode. */
1073 if (bp->duplex == DUPLEX_HALF)
1074 val |= BNX2_EMAC_MODE_HALF_DUPLEX;
1075 REG_WR(bp, BNX2_EMAC_MODE, val);
1077 /* Enable/disable rx PAUSE. */
1078 bp->rx_mode &= ~BNX2_EMAC_RX_MODE_FLOW_EN;
1080 if (bp->flow_ctrl & FLOW_CTRL_RX)
1081 bp->rx_mode |= BNX2_EMAC_RX_MODE_FLOW_EN;
1082 REG_WR(bp, BNX2_EMAC_RX_MODE, bp->rx_mode);
1084 /* Enable/disable tx PAUSE. */
1085 val = REG_RD(bp, BNX2_EMAC_TX_MODE);
1086 val &= ~BNX2_EMAC_TX_MODE_FLOW_EN;
1088 if (bp->flow_ctrl & FLOW_CTRL_TX)
1089 val |= BNX2_EMAC_TX_MODE_FLOW_EN;
1090 REG_WR(bp, BNX2_EMAC_TX_MODE, val);
1092 /* Acknowledge the interrupt. */
1093 REG_WR(bp, BNX2_EMAC_STATUS, BNX2_EMAC_STATUS_LINK_CHANGE);
1095 if (CHIP_NUM(bp) == CHIP_NUM_5709)
1096 bnx2_init_rx_context0(bp);
1102 bnx2_enable_bmsr1(struct bnx2 *bp)
1104 if ((bp->phy_flags & BNX2_PHY_FLAG_SERDES) &&
1105 (CHIP_NUM(bp) == CHIP_NUM_5709))
1106 bnx2_write_phy(bp, MII_BNX2_BLK_ADDR,
1107 MII_BNX2_BLK_ADDR_GP_STATUS);
1111 bnx2_disable_bmsr1(struct bnx2 *bp)
1113 if ((bp->phy_flags & BNX2_PHY_FLAG_SERDES) &&
1114 (CHIP_NUM(bp) == CHIP_NUM_5709))
1115 bnx2_write_phy(bp, MII_BNX2_BLK_ADDR,
1116 MII_BNX2_BLK_ADDR_COMBO_IEEEB0);
1120 bnx2_test_and_enable_2g5(struct bnx2 *bp)
1125 if (!(bp->phy_flags & BNX2_PHY_FLAG_2_5G_CAPABLE))
1128 if (bp->autoneg & AUTONEG_SPEED)
1129 bp->advertising |= ADVERTISED_2500baseX_Full;
1131 if (CHIP_NUM(bp) == CHIP_NUM_5709)
1132 bnx2_write_phy(bp, MII_BNX2_BLK_ADDR, MII_BNX2_BLK_ADDR_OVER1G);
1134 bnx2_read_phy(bp, bp->mii_up1, &up1);
1135 if (!(up1 & BCM5708S_UP1_2G5)) {
1136 up1 |= BCM5708S_UP1_2G5;
1137 bnx2_write_phy(bp, bp->mii_up1, up1);
1141 if (CHIP_NUM(bp) == CHIP_NUM_5709)
1142 bnx2_write_phy(bp, MII_BNX2_BLK_ADDR,
1143 MII_BNX2_BLK_ADDR_COMBO_IEEEB0);
1149 bnx2_test_and_disable_2g5(struct bnx2 *bp)
1154 if (!(bp->phy_flags & BNX2_PHY_FLAG_2_5G_CAPABLE))
1157 if (CHIP_NUM(bp) == CHIP_NUM_5709)
1158 bnx2_write_phy(bp, MII_BNX2_BLK_ADDR, MII_BNX2_BLK_ADDR_OVER1G);
1160 bnx2_read_phy(bp, bp->mii_up1, &up1);
1161 if (up1 & BCM5708S_UP1_2G5) {
1162 up1 &= ~BCM5708S_UP1_2G5;
1163 bnx2_write_phy(bp, bp->mii_up1, up1);
1167 if (CHIP_NUM(bp) == CHIP_NUM_5709)
1168 bnx2_write_phy(bp, MII_BNX2_BLK_ADDR,
1169 MII_BNX2_BLK_ADDR_COMBO_IEEEB0);
1175 bnx2_enable_forced_2g5(struct bnx2 *bp)
1179 if (!(bp->phy_flags & BNX2_PHY_FLAG_2_5G_CAPABLE))
1182 if (CHIP_NUM(bp) == CHIP_NUM_5709) {
1185 bnx2_write_phy(bp, MII_BNX2_BLK_ADDR,
1186 MII_BNX2_BLK_ADDR_SERDES_DIG);
1187 bnx2_read_phy(bp, MII_BNX2_SERDES_DIG_MISC1, &val);
1188 val &= ~MII_BNX2_SD_MISC1_FORCE_MSK;
1189 val |= MII_BNX2_SD_MISC1_FORCE | MII_BNX2_SD_MISC1_FORCE_2_5G;
1190 bnx2_write_phy(bp, MII_BNX2_SERDES_DIG_MISC1, val);
1192 bnx2_write_phy(bp, MII_BNX2_BLK_ADDR,
1193 MII_BNX2_BLK_ADDR_COMBO_IEEEB0);
1194 bnx2_read_phy(bp, bp->mii_bmcr, &bmcr);
1196 } else if (CHIP_NUM(bp) == CHIP_NUM_5708) {
1197 bnx2_read_phy(bp, bp->mii_bmcr, &bmcr);
1198 bmcr |= BCM5708S_BMCR_FORCE_2500;
1201 if (bp->autoneg & AUTONEG_SPEED) {
1202 bmcr &= ~BMCR_ANENABLE;
1203 if (bp->req_duplex == DUPLEX_FULL)
1204 bmcr |= BMCR_FULLDPLX;
1206 bnx2_write_phy(bp, bp->mii_bmcr, bmcr);
1210 bnx2_disable_forced_2g5(struct bnx2 *bp)
1214 if (!(bp->phy_flags & BNX2_PHY_FLAG_2_5G_CAPABLE))
1217 if (CHIP_NUM(bp) == CHIP_NUM_5709) {
1220 bnx2_write_phy(bp, MII_BNX2_BLK_ADDR,
1221 MII_BNX2_BLK_ADDR_SERDES_DIG);
1222 bnx2_read_phy(bp, MII_BNX2_SERDES_DIG_MISC1, &val);
1223 val &= ~MII_BNX2_SD_MISC1_FORCE;
1224 bnx2_write_phy(bp, MII_BNX2_SERDES_DIG_MISC1, val);
1226 bnx2_write_phy(bp, MII_BNX2_BLK_ADDR,
1227 MII_BNX2_BLK_ADDR_COMBO_IEEEB0);
1228 bnx2_read_phy(bp, bp->mii_bmcr, &bmcr);
1230 } else if (CHIP_NUM(bp) == CHIP_NUM_5708) {
1231 bnx2_read_phy(bp, bp->mii_bmcr, &bmcr);
1232 bmcr &= ~BCM5708S_BMCR_FORCE_2500;
1235 if (bp->autoneg & AUTONEG_SPEED)
1236 bmcr |= BMCR_SPEED1000 | BMCR_ANENABLE | BMCR_ANRESTART;
1237 bnx2_write_phy(bp, bp->mii_bmcr, bmcr);
1241 bnx2_5706s_force_link_dn(struct bnx2 *bp, int start)
1245 bnx2_write_phy(bp, MII_BNX2_DSP_ADDRESS, MII_EXPAND_SERDES_CTL);
1246 bnx2_read_phy(bp, MII_BNX2_DSP_RW_PORT, &val);
1248 bnx2_write_phy(bp, MII_BNX2_DSP_RW_PORT, val & 0xff0f);
1250 bnx2_write_phy(bp, MII_BNX2_DSP_RW_PORT, val | 0xc0);
1254 bnx2_set_link(struct bnx2 *bp)
1259 if (bp->loopback == MAC_LOOPBACK || bp->loopback == PHY_LOOPBACK) {
1264 if (bp->phy_flags & BNX2_PHY_FLAG_REMOTE_PHY_CAP)
1267 link_up = bp->link_up;
1269 bnx2_enable_bmsr1(bp);
1270 bnx2_read_phy(bp, bp->mii_bmsr1, &bmsr);
1271 bnx2_read_phy(bp, bp->mii_bmsr1, &bmsr);
1272 bnx2_disable_bmsr1(bp);
1274 if ((bp->phy_flags & BNX2_PHY_FLAG_SERDES) &&
1275 (CHIP_NUM(bp) == CHIP_NUM_5706)) {
1278 if (bp->phy_flags & BNX2_PHY_FLAG_FORCED_DOWN) {
1279 bnx2_5706s_force_link_dn(bp, 0);
1280 bp->phy_flags &= ~BNX2_PHY_FLAG_FORCED_DOWN;
1282 val = REG_RD(bp, BNX2_EMAC_STATUS);
1284 bnx2_write_phy(bp, MII_BNX2_MISC_SHADOW, MISC_SHDW_AN_DBG);
1285 bnx2_read_phy(bp, MII_BNX2_MISC_SHADOW, &an_dbg);
1286 bnx2_read_phy(bp, MII_BNX2_MISC_SHADOW, &an_dbg);
1288 if ((val & BNX2_EMAC_STATUS_LINK) &&
1289 !(an_dbg & MISC_SHDW_AN_DBG_NOSYNC))
1290 bmsr |= BMSR_LSTATUS;
1292 bmsr &= ~BMSR_LSTATUS;
1295 if (bmsr & BMSR_LSTATUS) {
1298 if (bp->phy_flags & BNX2_PHY_FLAG_SERDES) {
1299 if (CHIP_NUM(bp) == CHIP_NUM_5706)
1300 bnx2_5706s_linkup(bp);
1301 else if (CHIP_NUM(bp) == CHIP_NUM_5708)
1302 bnx2_5708s_linkup(bp);
1303 else if (CHIP_NUM(bp) == CHIP_NUM_5709)
1304 bnx2_5709s_linkup(bp);
1307 bnx2_copper_linkup(bp);
1309 bnx2_resolve_flow_ctrl(bp);
1312 if ((bp->phy_flags & BNX2_PHY_FLAG_SERDES) &&
1313 (bp->autoneg & AUTONEG_SPEED))
1314 bnx2_disable_forced_2g5(bp);
1316 if (bp->phy_flags & BNX2_PHY_FLAG_PARALLEL_DETECT) {
1319 bnx2_read_phy(bp, bp->mii_bmcr, &bmcr);
1320 bmcr |= BMCR_ANENABLE;
1321 bnx2_write_phy(bp, bp->mii_bmcr, bmcr);
1323 bp->phy_flags &= ~BNX2_PHY_FLAG_PARALLEL_DETECT;
1328 if (bp->link_up != link_up) {
1329 bnx2_report_link(bp);
1332 bnx2_set_mac_link(bp);
1338 bnx2_reset_phy(struct bnx2 *bp)
1343 bnx2_write_phy(bp, bp->mii_bmcr, BMCR_RESET);
1345 #define PHY_RESET_MAX_WAIT 100
1346 for (i = 0; i < PHY_RESET_MAX_WAIT; i++) {
1349 bnx2_read_phy(bp, bp->mii_bmcr, ®);
1350 if (!(reg & BMCR_RESET)) {
1355 if (i == PHY_RESET_MAX_WAIT) {
1362 bnx2_phy_get_pause_adv(struct bnx2 *bp)
1366 if ((bp->req_flow_ctrl & (FLOW_CTRL_RX | FLOW_CTRL_TX)) ==
1367 (FLOW_CTRL_RX | FLOW_CTRL_TX)) {
1369 if (bp->phy_flags & BNX2_PHY_FLAG_SERDES) {
1370 adv = ADVERTISE_1000XPAUSE;
1373 adv = ADVERTISE_PAUSE_CAP;
1376 else if (bp->req_flow_ctrl & FLOW_CTRL_TX) {
1377 if (bp->phy_flags & BNX2_PHY_FLAG_SERDES) {
1378 adv = ADVERTISE_1000XPSE_ASYM;
1381 adv = ADVERTISE_PAUSE_ASYM;
1384 else if (bp->req_flow_ctrl & FLOW_CTRL_RX) {
1385 if (bp->phy_flags & BNX2_PHY_FLAG_SERDES) {
1386 adv = ADVERTISE_1000XPAUSE | ADVERTISE_1000XPSE_ASYM;
1389 adv = ADVERTISE_PAUSE_CAP | ADVERTISE_PAUSE_ASYM;
1395 static int bnx2_fw_sync(struct bnx2 *, u32, int);
1398 bnx2_setup_remote_phy(struct bnx2 *bp, u8 port)
1400 u32 speed_arg = 0, pause_adv;
1402 pause_adv = bnx2_phy_get_pause_adv(bp);
1404 if (bp->autoneg & AUTONEG_SPEED) {
1405 speed_arg |= BNX2_NETLINK_SET_LINK_ENABLE_AUTONEG;
1406 if (bp->advertising & ADVERTISED_10baseT_Half)
1407 speed_arg |= BNX2_NETLINK_SET_LINK_SPEED_10HALF;
1408 if (bp->advertising & ADVERTISED_10baseT_Full)
1409 speed_arg |= BNX2_NETLINK_SET_LINK_SPEED_10FULL;
1410 if (bp->advertising & ADVERTISED_100baseT_Half)
1411 speed_arg |= BNX2_NETLINK_SET_LINK_SPEED_100HALF;
1412 if (bp->advertising & ADVERTISED_100baseT_Full)
1413 speed_arg |= BNX2_NETLINK_SET_LINK_SPEED_100FULL;
1414 if (bp->advertising & ADVERTISED_1000baseT_Full)
1415 speed_arg |= BNX2_NETLINK_SET_LINK_SPEED_1GFULL;
1416 if (bp->advertising & ADVERTISED_2500baseX_Full)
1417 speed_arg |= BNX2_NETLINK_SET_LINK_SPEED_2G5FULL;
1419 if (bp->req_line_speed == SPEED_2500)
1420 speed_arg = BNX2_NETLINK_SET_LINK_SPEED_2G5FULL;
1421 else if (bp->req_line_speed == SPEED_1000)
1422 speed_arg = BNX2_NETLINK_SET_LINK_SPEED_1GFULL;
1423 else if (bp->req_line_speed == SPEED_100) {
1424 if (bp->req_duplex == DUPLEX_FULL)
1425 speed_arg = BNX2_NETLINK_SET_LINK_SPEED_100FULL;
1427 speed_arg = BNX2_NETLINK_SET_LINK_SPEED_100HALF;
1428 } else if (bp->req_line_speed == SPEED_10) {
1429 if (bp->req_duplex == DUPLEX_FULL)
1430 speed_arg = BNX2_NETLINK_SET_LINK_SPEED_10FULL;
1432 speed_arg = BNX2_NETLINK_SET_LINK_SPEED_10HALF;
1436 if (pause_adv & (ADVERTISE_1000XPAUSE | ADVERTISE_PAUSE_CAP))
1437 speed_arg |= BNX2_NETLINK_SET_LINK_FC_SYM_PAUSE;
1438 if (pause_adv & (ADVERTISE_1000XPSE_ASYM | ADVERTISE_PAUSE_ASYM))
1439 speed_arg |= BNX2_NETLINK_SET_LINK_FC_ASYM_PAUSE;
1441 if (port == PORT_TP)
1442 speed_arg |= BNX2_NETLINK_SET_LINK_PHY_APP_REMOTE |
1443 BNX2_NETLINK_SET_LINK_ETH_AT_WIRESPEED;
1445 bnx2_shmem_wr(bp, BNX2_DRV_MB_ARG0, speed_arg);
1447 spin_unlock_bh(&bp->phy_lock);
1448 bnx2_fw_sync(bp, BNX2_DRV_MSG_CODE_CMD_SET_LINK, 0);
1449 spin_lock_bh(&bp->phy_lock);
1455 bnx2_setup_serdes_phy(struct bnx2 *bp, u8 port)
1460 if (bp->phy_flags & BNX2_PHY_FLAG_REMOTE_PHY_CAP)
1461 return (bnx2_setup_remote_phy(bp, port));
1463 if (!(bp->autoneg & AUTONEG_SPEED)) {
1465 int force_link_down = 0;
1467 if (bp->req_line_speed == SPEED_2500) {
1468 if (!bnx2_test_and_enable_2g5(bp))
1469 force_link_down = 1;
1470 } else if (bp->req_line_speed == SPEED_1000) {
1471 if (bnx2_test_and_disable_2g5(bp))
1472 force_link_down = 1;
1474 bnx2_read_phy(bp, bp->mii_adv, &adv);
1475 adv &= ~(ADVERTISE_1000XFULL | ADVERTISE_1000XHALF);
1477 bnx2_read_phy(bp, bp->mii_bmcr, &bmcr);
1478 new_bmcr = bmcr & ~BMCR_ANENABLE;
1479 new_bmcr |= BMCR_SPEED1000;
1481 if (CHIP_NUM(bp) == CHIP_NUM_5709) {
1482 if (bp->req_line_speed == SPEED_2500)
1483 bnx2_enable_forced_2g5(bp);
1484 else if (bp->req_line_speed == SPEED_1000) {
1485 bnx2_disable_forced_2g5(bp);
1486 new_bmcr &= ~0x2000;
1489 } else if (CHIP_NUM(bp) == CHIP_NUM_5708) {
1490 if (bp->req_line_speed == SPEED_2500)
1491 new_bmcr |= BCM5708S_BMCR_FORCE_2500;
1493 new_bmcr = bmcr & ~BCM5708S_BMCR_FORCE_2500;
1496 if (bp->req_duplex == DUPLEX_FULL) {
1497 adv |= ADVERTISE_1000XFULL;
1498 new_bmcr |= BMCR_FULLDPLX;
1501 adv |= ADVERTISE_1000XHALF;
1502 new_bmcr &= ~BMCR_FULLDPLX;
1504 if ((new_bmcr != bmcr) || (force_link_down)) {
1505 /* Force a link down visible on the other side */
1507 bnx2_write_phy(bp, bp->mii_adv, adv &
1508 ~(ADVERTISE_1000XFULL |
1509 ADVERTISE_1000XHALF));
1510 bnx2_write_phy(bp, bp->mii_bmcr, bmcr |
1511 BMCR_ANRESTART | BMCR_ANENABLE);
1514 netif_carrier_off(bp->dev);
1515 bnx2_write_phy(bp, bp->mii_bmcr, new_bmcr);
1516 bnx2_report_link(bp);
1518 bnx2_write_phy(bp, bp->mii_adv, adv);
1519 bnx2_write_phy(bp, bp->mii_bmcr, new_bmcr);
1521 bnx2_resolve_flow_ctrl(bp);
1522 bnx2_set_mac_link(bp);
1527 bnx2_test_and_enable_2g5(bp);
1529 if (bp->advertising & ADVERTISED_1000baseT_Full)
1530 new_adv |= ADVERTISE_1000XFULL;
1532 new_adv |= bnx2_phy_get_pause_adv(bp);
1534 bnx2_read_phy(bp, bp->mii_adv, &adv);
1535 bnx2_read_phy(bp, bp->mii_bmcr, &bmcr);
1537 bp->serdes_an_pending = 0;
1538 if ((adv != new_adv) || ((bmcr & BMCR_ANENABLE) == 0)) {
1539 /* Force a link down visible on the other side */
1541 bnx2_write_phy(bp, bp->mii_bmcr, BMCR_LOOPBACK);
1542 spin_unlock_bh(&bp->phy_lock);
1544 spin_lock_bh(&bp->phy_lock);
1547 bnx2_write_phy(bp, bp->mii_adv, new_adv);
1548 bnx2_write_phy(bp, bp->mii_bmcr, bmcr | BMCR_ANRESTART |
1550 /* Speed up link-up time when the link partner
1551 * does not autonegotiate which is very common
1552 * in blade servers. Some blade servers use
1553 * IPMI for kerboard input and it's important
1554 * to minimize link disruptions. Autoneg. involves
1555 * exchanging base pages plus 3 next pages and
1556 * normally completes in about 120 msec.
1558 bp->current_interval = SERDES_AN_TIMEOUT;
1559 bp->serdes_an_pending = 1;
1560 mod_timer(&bp->timer, jiffies + bp->current_interval);
1562 bnx2_resolve_flow_ctrl(bp);
1563 bnx2_set_mac_link(bp);
1569 #define ETHTOOL_ALL_FIBRE_SPEED \
1570 (bp->phy_flags & BNX2_PHY_FLAG_2_5G_CAPABLE) ? \
1571 (ADVERTISED_2500baseX_Full | ADVERTISED_1000baseT_Full) :\
1572 (ADVERTISED_1000baseT_Full)
1574 #define ETHTOOL_ALL_COPPER_SPEED \
1575 (ADVERTISED_10baseT_Half | ADVERTISED_10baseT_Full | \
1576 ADVERTISED_100baseT_Half | ADVERTISED_100baseT_Full | \
1577 ADVERTISED_1000baseT_Full)
1579 #define PHY_ALL_10_100_SPEED (ADVERTISE_10HALF | ADVERTISE_10FULL | \
1580 ADVERTISE_100HALF | ADVERTISE_100FULL | ADVERTISE_CSMA)
1582 #define PHY_ALL_1000_SPEED (ADVERTISE_1000HALF | ADVERTISE_1000FULL)
1585 bnx2_set_default_remote_link(struct bnx2 *bp)
1589 if (bp->phy_port == PORT_TP)
1590 link = bnx2_shmem_rd(bp, BNX2_RPHY_COPPER_LINK);
1592 link = bnx2_shmem_rd(bp, BNX2_RPHY_SERDES_LINK);
1594 if (link & BNX2_NETLINK_SET_LINK_ENABLE_AUTONEG) {
1595 bp->req_line_speed = 0;
1596 bp->autoneg |= AUTONEG_SPEED;
1597 bp->advertising = ADVERTISED_Autoneg;
1598 if (link & BNX2_NETLINK_SET_LINK_SPEED_10HALF)
1599 bp->advertising |= ADVERTISED_10baseT_Half;
1600 if (link & BNX2_NETLINK_SET_LINK_SPEED_10FULL)
1601 bp->advertising |= ADVERTISED_10baseT_Full;
1602 if (link & BNX2_NETLINK_SET_LINK_SPEED_100HALF)
1603 bp->advertising |= ADVERTISED_100baseT_Half;
1604 if (link & BNX2_NETLINK_SET_LINK_SPEED_100FULL)
1605 bp->advertising |= ADVERTISED_100baseT_Full;
1606 if (link & BNX2_NETLINK_SET_LINK_SPEED_1GFULL)
1607 bp->advertising |= ADVERTISED_1000baseT_Full;
1608 if (link & BNX2_NETLINK_SET_LINK_SPEED_2G5FULL)
1609 bp->advertising |= ADVERTISED_2500baseX_Full;
1612 bp->advertising = 0;
1613 bp->req_duplex = DUPLEX_FULL;
1614 if (link & BNX2_NETLINK_SET_LINK_SPEED_10) {
1615 bp->req_line_speed = SPEED_10;
1616 if (link & BNX2_NETLINK_SET_LINK_SPEED_10HALF)
1617 bp->req_duplex = DUPLEX_HALF;
1619 if (link & BNX2_NETLINK_SET_LINK_SPEED_100) {
1620 bp->req_line_speed = SPEED_100;
1621 if (link & BNX2_NETLINK_SET_LINK_SPEED_100HALF)
1622 bp->req_duplex = DUPLEX_HALF;
1624 if (link & BNX2_NETLINK_SET_LINK_SPEED_1GFULL)
1625 bp->req_line_speed = SPEED_1000;
1626 if (link & BNX2_NETLINK_SET_LINK_SPEED_2G5FULL)
1627 bp->req_line_speed = SPEED_2500;
1632 bnx2_set_default_link(struct bnx2 *bp)
1634 if (bp->phy_flags & BNX2_PHY_FLAG_REMOTE_PHY_CAP) {
1635 bnx2_set_default_remote_link(bp);
1639 bp->autoneg = AUTONEG_SPEED | AUTONEG_FLOW_CTRL;
1640 bp->req_line_speed = 0;
1641 if (bp->phy_flags & BNX2_PHY_FLAG_SERDES) {
1644 bp->advertising = ETHTOOL_ALL_FIBRE_SPEED | ADVERTISED_Autoneg;
1646 reg = bnx2_shmem_rd(bp, BNX2_PORT_HW_CFG_CONFIG);
1647 reg &= BNX2_PORT_HW_CFG_CFG_DFLT_LINK_MASK;
1648 if (reg == BNX2_PORT_HW_CFG_CFG_DFLT_LINK_1G) {
1650 bp->req_line_speed = bp->line_speed = SPEED_1000;
1651 bp->req_duplex = DUPLEX_FULL;
1654 bp->advertising = ETHTOOL_ALL_COPPER_SPEED | ADVERTISED_Autoneg;
1658 bnx2_send_heart_beat(struct bnx2 *bp)
1663 spin_lock(&bp->indirect_lock);
1664 msg = (u32) (++bp->fw_drv_pulse_wr_seq & BNX2_DRV_PULSE_SEQ_MASK);
1665 addr = bp->shmem_base + BNX2_DRV_PULSE_MB;
1666 REG_WR(bp, BNX2_PCICFG_REG_WINDOW_ADDRESS, addr);
1667 REG_WR(bp, BNX2_PCICFG_REG_WINDOW, msg);
1668 spin_unlock(&bp->indirect_lock);
1672 bnx2_remote_phy_event(struct bnx2 *bp)
1675 u8 link_up = bp->link_up;
1678 msg = bnx2_shmem_rd(bp, BNX2_LINK_STATUS);
1680 if (msg & BNX2_LINK_STATUS_HEART_BEAT_EXPIRED)
1681 bnx2_send_heart_beat(bp);
1683 msg &= ~BNX2_LINK_STATUS_HEART_BEAT_EXPIRED;
1685 if ((msg & BNX2_LINK_STATUS_LINK_UP) == BNX2_LINK_STATUS_LINK_DOWN)
1691 speed = msg & BNX2_LINK_STATUS_SPEED_MASK;
1692 bp->duplex = DUPLEX_FULL;
1694 case BNX2_LINK_STATUS_10HALF:
1695 bp->duplex = DUPLEX_HALF;
1696 case BNX2_LINK_STATUS_10FULL:
1697 bp->line_speed = SPEED_10;
1699 case BNX2_LINK_STATUS_100HALF:
1700 bp->duplex = DUPLEX_HALF;
1701 case BNX2_LINK_STATUS_100BASE_T4:
1702 case BNX2_LINK_STATUS_100FULL:
1703 bp->line_speed = SPEED_100;
1705 case BNX2_LINK_STATUS_1000HALF:
1706 bp->duplex = DUPLEX_HALF;
1707 case BNX2_LINK_STATUS_1000FULL:
1708 bp->line_speed = SPEED_1000;
1710 case BNX2_LINK_STATUS_2500HALF:
1711 bp->duplex = DUPLEX_HALF;
1712 case BNX2_LINK_STATUS_2500FULL:
1713 bp->line_speed = SPEED_2500;
1721 if ((bp->autoneg & (AUTONEG_SPEED | AUTONEG_FLOW_CTRL)) !=
1722 (AUTONEG_SPEED | AUTONEG_FLOW_CTRL)) {
1723 if (bp->duplex == DUPLEX_FULL)
1724 bp->flow_ctrl = bp->req_flow_ctrl;
1726 if (msg & BNX2_LINK_STATUS_TX_FC_ENABLED)
1727 bp->flow_ctrl |= FLOW_CTRL_TX;
1728 if (msg & BNX2_LINK_STATUS_RX_FC_ENABLED)
1729 bp->flow_ctrl |= FLOW_CTRL_RX;
1732 old_port = bp->phy_port;
1733 if (msg & BNX2_LINK_STATUS_SERDES_LINK)
1734 bp->phy_port = PORT_FIBRE;
1736 bp->phy_port = PORT_TP;
1738 if (old_port != bp->phy_port)
1739 bnx2_set_default_link(bp);
1742 if (bp->link_up != link_up)
1743 bnx2_report_link(bp);
1745 bnx2_set_mac_link(bp);
1749 bnx2_set_remote_link(struct bnx2 *bp)
1753 evt_code = bnx2_shmem_rd(bp, BNX2_FW_EVT_CODE_MB);
1755 case BNX2_FW_EVT_CODE_LINK_EVENT:
1756 bnx2_remote_phy_event(bp);
1758 case BNX2_FW_EVT_CODE_SW_TIMER_EXPIRATION_EVENT:
1760 bnx2_send_heart_beat(bp);
1767 bnx2_setup_copper_phy(struct bnx2 *bp)
1772 bnx2_read_phy(bp, bp->mii_bmcr, &bmcr);
1774 if (bp->autoneg & AUTONEG_SPEED) {
1775 u32 adv_reg, adv1000_reg;
1776 u32 new_adv_reg = 0;
1777 u32 new_adv1000_reg = 0;
1779 bnx2_read_phy(bp, bp->mii_adv, &adv_reg);
1780 adv_reg &= (PHY_ALL_10_100_SPEED | ADVERTISE_PAUSE_CAP |
1781 ADVERTISE_PAUSE_ASYM);
1783 bnx2_read_phy(bp, MII_CTRL1000, &adv1000_reg);
1784 adv1000_reg &= PHY_ALL_1000_SPEED;
1786 if (bp->advertising & ADVERTISED_10baseT_Half)
1787 new_adv_reg |= ADVERTISE_10HALF;
1788 if (bp->advertising & ADVERTISED_10baseT_Full)
1789 new_adv_reg |= ADVERTISE_10FULL;
1790 if (bp->advertising & ADVERTISED_100baseT_Half)
1791 new_adv_reg |= ADVERTISE_100HALF;
1792 if (bp->advertising & ADVERTISED_100baseT_Full)
1793 new_adv_reg |= ADVERTISE_100FULL;
1794 if (bp->advertising & ADVERTISED_1000baseT_Full)
1795 new_adv1000_reg |= ADVERTISE_1000FULL;
1797 new_adv_reg |= ADVERTISE_CSMA;
1799 new_adv_reg |= bnx2_phy_get_pause_adv(bp);
1801 if ((adv1000_reg != new_adv1000_reg) ||
1802 (adv_reg != new_adv_reg) ||
1803 ((bmcr & BMCR_ANENABLE) == 0)) {
1805 bnx2_write_phy(bp, bp->mii_adv, new_adv_reg);
1806 bnx2_write_phy(bp, MII_CTRL1000, new_adv1000_reg);
1807 bnx2_write_phy(bp, bp->mii_bmcr, BMCR_ANRESTART |
1810 else if (bp->link_up) {
1811 /* Flow ctrl may have changed from auto to forced */
1812 /* or vice-versa. */
1814 bnx2_resolve_flow_ctrl(bp);
1815 bnx2_set_mac_link(bp);
1821 if (bp->req_line_speed == SPEED_100) {
1822 new_bmcr |= BMCR_SPEED100;
1824 if (bp->req_duplex == DUPLEX_FULL) {
1825 new_bmcr |= BMCR_FULLDPLX;
1827 if (new_bmcr != bmcr) {
1830 bnx2_read_phy(bp, bp->mii_bmsr, &bmsr);
1831 bnx2_read_phy(bp, bp->mii_bmsr, &bmsr);
1833 if (bmsr & BMSR_LSTATUS) {
1834 /* Force link down */
1835 bnx2_write_phy(bp, bp->mii_bmcr, BMCR_LOOPBACK);
1836 spin_unlock_bh(&bp->phy_lock);
1838 spin_lock_bh(&bp->phy_lock);
1840 bnx2_read_phy(bp, bp->mii_bmsr, &bmsr);
1841 bnx2_read_phy(bp, bp->mii_bmsr, &bmsr);
1844 bnx2_write_phy(bp, bp->mii_bmcr, new_bmcr);
1846 /* Normally, the new speed is setup after the link has
1847 * gone down and up again. In some cases, link will not go
1848 * down so we need to set up the new speed here.
1850 if (bmsr & BMSR_LSTATUS) {
1851 bp->line_speed = bp->req_line_speed;
1852 bp->duplex = bp->req_duplex;
1853 bnx2_resolve_flow_ctrl(bp);
1854 bnx2_set_mac_link(bp);
1857 bnx2_resolve_flow_ctrl(bp);
1858 bnx2_set_mac_link(bp);
1864 bnx2_setup_phy(struct bnx2 *bp, u8 port)
1866 if (bp->loopback == MAC_LOOPBACK)
1869 if (bp->phy_flags & BNX2_PHY_FLAG_SERDES) {
1870 return (bnx2_setup_serdes_phy(bp, port));
1873 return (bnx2_setup_copper_phy(bp));
1878 bnx2_init_5709s_phy(struct bnx2 *bp, int reset_phy)
1882 bp->mii_bmcr = MII_BMCR + 0x10;
1883 bp->mii_bmsr = MII_BMSR + 0x10;
1884 bp->mii_bmsr1 = MII_BNX2_GP_TOP_AN_STATUS1;
1885 bp->mii_adv = MII_ADVERTISE + 0x10;
1886 bp->mii_lpa = MII_LPA + 0x10;
1887 bp->mii_up1 = MII_BNX2_OVER1G_UP1;
1889 bnx2_write_phy(bp, MII_BNX2_BLK_ADDR, MII_BNX2_BLK_ADDR_AER);
1890 bnx2_write_phy(bp, MII_BNX2_AER_AER, MII_BNX2_AER_AER_AN_MMD);
1892 bnx2_write_phy(bp, MII_BNX2_BLK_ADDR, MII_BNX2_BLK_ADDR_COMBO_IEEEB0);
1896 bnx2_write_phy(bp, MII_BNX2_BLK_ADDR, MII_BNX2_BLK_ADDR_SERDES_DIG);
1898 bnx2_read_phy(bp, MII_BNX2_SERDES_DIG_1000XCTL1, &val);
1899 val &= ~MII_BNX2_SD_1000XCTL1_AUTODET;
1900 val |= MII_BNX2_SD_1000XCTL1_FIBER;
1901 bnx2_write_phy(bp, MII_BNX2_SERDES_DIG_1000XCTL1, val);
1903 bnx2_write_phy(bp, MII_BNX2_BLK_ADDR, MII_BNX2_BLK_ADDR_OVER1G);
1904 bnx2_read_phy(bp, MII_BNX2_OVER1G_UP1, &val);
1905 if (bp->phy_flags & BNX2_PHY_FLAG_2_5G_CAPABLE)
1906 val |= BCM5708S_UP1_2G5;
1908 val &= ~BCM5708S_UP1_2G5;
1909 bnx2_write_phy(bp, MII_BNX2_OVER1G_UP1, val);
1911 bnx2_write_phy(bp, MII_BNX2_BLK_ADDR, MII_BNX2_BLK_ADDR_BAM_NXTPG);
1912 bnx2_read_phy(bp, MII_BNX2_BAM_NXTPG_CTL, &val);
1913 val |= MII_BNX2_NXTPG_CTL_T2 | MII_BNX2_NXTPG_CTL_BAM;
1914 bnx2_write_phy(bp, MII_BNX2_BAM_NXTPG_CTL, val);
1916 bnx2_write_phy(bp, MII_BNX2_BLK_ADDR, MII_BNX2_BLK_ADDR_CL73_USERB0);
1918 val = MII_BNX2_CL73_BAM_EN | MII_BNX2_CL73_BAM_STA_MGR_EN |
1919 MII_BNX2_CL73_BAM_NP_AFT_BP_EN;
1920 bnx2_write_phy(bp, MII_BNX2_CL73_BAM_CTL1, val);
1922 bnx2_write_phy(bp, MII_BNX2_BLK_ADDR, MII_BNX2_BLK_ADDR_COMBO_IEEEB0);
1928 bnx2_init_5708s_phy(struct bnx2 *bp, int reset_phy)
1935 bp->mii_up1 = BCM5708S_UP1;
1937 bnx2_write_phy(bp, BCM5708S_BLK_ADDR, BCM5708S_BLK_ADDR_DIG3);
1938 bnx2_write_phy(bp, BCM5708S_DIG_3_0, BCM5708S_DIG_3_0_USE_IEEE);
1939 bnx2_write_phy(bp, BCM5708S_BLK_ADDR, BCM5708S_BLK_ADDR_DIG);
1941 bnx2_read_phy(bp, BCM5708S_1000X_CTL1, &val);
1942 val |= BCM5708S_1000X_CTL1_FIBER_MODE | BCM5708S_1000X_CTL1_AUTODET_EN;
1943 bnx2_write_phy(bp, BCM5708S_1000X_CTL1, val);
1945 bnx2_read_phy(bp, BCM5708S_1000X_CTL2, &val);
1946 val |= BCM5708S_1000X_CTL2_PLLEL_DET_EN;
1947 bnx2_write_phy(bp, BCM5708S_1000X_CTL2, val);
1949 if (bp->phy_flags & BNX2_PHY_FLAG_2_5G_CAPABLE) {
1950 bnx2_read_phy(bp, BCM5708S_UP1, &val);
1951 val |= BCM5708S_UP1_2G5;
1952 bnx2_write_phy(bp, BCM5708S_UP1, val);
1955 if ((CHIP_ID(bp) == CHIP_ID_5708_A0) ||
1956 (CHIP_ID(bp) == CHIP_ID_5708_B0) ||
1957 (CHIP_ID(bp) == CHIP_ID_5708_B1)) {
1958 /* increase tx signal amplitude */
1959 bnx2_write_phy(bp, BCM5708S_BLK_ADDR,
1960 BCM5708S_BLK_ADDR_TX_MISC);
1961 bnx2_read_phy(bp, BCM5708S_TX_ACTL1, &val);
1962 val &= ~BCM5708S_TX_ACTL1_DRIVER_VCM;
1963 bnx2_write_phy(bp, BCM5708S_TX_ACTL1, val);
1964 bnx2_write_phy(bp, BCM5708S_BLK_ADDR, BCM5708S_BLK_ADDR_DIG);
1967 val = bnx2_shmem_rd(bp, BNX2_PORT_HW_CFG_CONFIG) &
1968 BNX2_PORT_HW_CFG_CFG_TXCTL3_MASK;
1973 is_backplane = bnx2_shmem_rd(bp, BNX2_SHARED_HW_CFG_CONFIG);
1974 if (is_backplane & BNX2_SHARED_HW_CFG_PHY_BACKPLANE) {
1975 bnx2_write_phy(bp, BCM5708S_BLK_ADDR,
1976 BCM5708S_BLK_ADDR_TX_MISC);
1977 bnx2_write_phy(bp, BCM5708S_TX_ACTL3, val);
1978 bnx2_write_phy(bp, BCM5708S_BLK_ADDR,
1979 BCM5708S_BLK_ADDR_DIG);
1986 bnx2_init_5706s_phy(struct bnx2 *bp, int reset_phy)
1991 bp->phy_flags &= ~BNX2_PHY_FLAG_PARALLEL_DETECT;
1993 if (CHIP_NUM(bp) == CHIP_NUM_5706)
1994 REG_WR(bp, BNX2_MISC_GP_HW_CTL0, 0x300);
1996 if (bp->dev->mtu > 1500) {
1999 /* Set extended packet length bit */
2000 bnx2_write_phy(bp, 0x18, 0x7);
2001 bnx2_read_phy(bp, 0x18, &val);
2002 bnx2_write_phy(bp, 0x18, (val & 0xfff8) | 0x4000);
2004 bnx2_write_phy(bp, 0x1c, 0x6c00);
2005 bnx2_read_phy(bp, 0x1c, &val);
2006 bnx2_write_phy(bp, 0x1c, (val & 0x3ff) | 0xec02);
2011 bnx2_write_phy(bp, 0x18, 0x7);
2012 bnx2_read_phy(bp, 0x18, &val);
2013 bnx2_write_phy(bp, 0x18, val & ~0x4007);
2015 bnx2_write_phy(bp, 0x1c, 0x6c00);
2016 bnx2_read_phy(bp, 0x1c, &val);
2017 bnx2_write_phy(bp, 0x1c, (val & 0x3fd) | 0xec00);
2024 bnx2_init_copper_phy(struct bnx2 *bp, int reset_phy)
2031 if (bp->phy_flags & BNX2_PHY_FLAG_CRC_FIX) {
2032 bnx2_write_phy(bp, 0x18, 0x0c00);
2033 bnx2_write_phy(bp, 0x17, 0x000a);
2034 bnx2_write_phy(bp, 0x15, 0x310b);
2035 bnx2_write_phy(bp, 0x17, 0x201f);
2036 bnx2_write_phy(bp, 0x15, 0x9506);
2037 bnx2_write_phy(bp, 0x17, 0x401f);
2038 bnx2_write_phy(bp, 0x15, 0x14e2);
2039 bnx2_write_phy(bp, 0x18, 0x0400);
2042 if (bp->phy_flags & BNX2_PHY_FLAG_DIS_EARLY_DAC) {
2043 bnx2_write_phy(bp, MII_BNX2_DSP_ADDRESS,
2044 MII_BNX2_DSP_EXPAND_REG | 0x8);
2045 bnx2_read_phy(bp, MII_BNX2_DSP_RW_PORT, &val);
2047 bnx2_write_phy(bp, MII_BNX2_DSP_RW_PORT, val);
2050 if (bp->dev->mtu > 1500) {
2051 /* Set extended packet length bit */
2052 bnx2_write_phy(bp, 0x18, 0x7);
2053 bnx2_read_phy(bp, 0x18, &val);
2054 bnx2_write_phy(bp, 0x18, val | 0x4000);
2056 bnx2_read_phy(bp, 0x10, &val);
2057 bnx2_write_phy(bp, 0x10, val | 0x1);
2060 bnx2_write_phy(bp, 0x18, 0x7);
2061 bnx2_read_phy(bp, 0x18, &val);
2062 bnx2_write_phy(bp, 0x18, val & ~0x4007);
2064 bnx2_read_phy(bp, 0x10, &val);
2065 bnx2_write_phy(bp, 0x10, val & ~0x1);
2068 /* ethernet@wirespeed */
2069 bnx2_write_phy(bp, 0x18, 0x7007);
2070 bnx2_read_phy(bp, 0x18, &val);
2071 bnx2_write_phy(bp, 0x18, val | (1 << 15) | (1 << 4));
2077 bnx2_init_phy(struct bnx2 *bp, int reset_phy)
2082 bp->phy_flags &= ~BNX2_PHY_FLAG_INT_MODE_MASK;
2083 bp->phy_flags |= BNX2_PHY_FLAG_INT_MODE_LINK_READY;
2085 bp->mii_bmcr = MII_BMCR;
2086 bp->mii_bmsr = MII_BMSR;
2087 bp->mii_bmsr1 = MII_BMSR;
2088 bp->mii_adv = MII_ADVERTISE;
2089 bp->mii_lpa = MII_LPA;
2091 REG_WR(bp, BNX2_EMAC_ATTENTION_ENA, BNX2_EMAC_ATTENTION_ENA_LINK);
2093 if (bp->phy_flags & BNX2_PHY_FLAG_REMOTE_PHY_CAP)
2096 bnx2_read_phy(bp, MII_PHYSID1, &val);
2097 bp->phy_id = val << 16;
2098 bnx2_read_phy(bp, MII_PHYSID2, &val);
2099 bp->phy_id |= val & 0xffff;
2101 if (bp->phy_flags & BNX2_PHY_FLAG_SERDES) {
2102 if (CHIP_NUM(bp) == CHIP_NUM_5706)
2103 rc = bnx2_init_5706s_phy(bp, reset_phy);
2104 else if (CHIP_NUM(bp) == CHIP_NUM_5708)
2105 rc = bnx2_init_5708s_phy(bp, reset_phy);
2106 else if (CHIP_NUM(bp) == CHIP_NUM_5709)
2107 rc = bnx2_init_5709s_phy(bp, reset_phy);
2110 rc = bnx2_init_copper_phy(bp, reset_phy);
2115 rc = bnx2_setup_phy(bp, bp->phy_port);
2121 bnx2_set_mac_loopback(struct bnx2 *bp)
2125 mac_mode = REG_RD(bp, BNX2_EMAC_MODE);
2126 mac_mode &= ~BNX2_EMAC_MODE_PORT;
2127 mac_mode |= BNX2_EMAC_MODE_MAC_LOOP | BNX2_EMAC_MODE_FORCE_LINK;
2128 REG_WR(bp, BNX2_EMAC_MODE, mac_mode);
2133 static int bnx2_test_link(struct bnx2 *);
2136 bnx2_set_phy_loopback(struct bnx2 *bp)
2141 spin_lock_bh(&bp->phy_lock);
2142 rc = bnx2_write_phy(bp, bp->mii_bmcr, BMCR_LOOPBACK | BMCR_FULLDPLX |
2144 spin_unlock_bh(&bp->phy_lock);
2148 for (i = 0; i < 10; i++) {
2149 if (bnx2_test_link(bp) == 0)
2154 mac_mode = REG_RD(bp, BNX2_EMAC_MODE);
2155 mac_mode &= ~(BNX2_EMAC_MODE_PORT | BNX2_EMAC_MODE_HALF_DUPLEX |
2156 BNX2_EMAC_MODE_MAC_LOOP | BNX2_EMAC_MODE_FORCE_LINK |
2157 BNX2_EMAC_MODE_25G_MODE);
2159 mac_mode |= BNX2_EMAC_MODE_PORT_GMII;
2160 REG_WR(bp, BNX2_EMAC_MODE, mac_mode);
2166 bnx2_fw_sync(struct bnx2 *bp, u32 msg_data, int silent)
2172 msg_data |= bp->fw_wr_seq;
2174 bnx2_shmem_wr(bp, BNX2_DRV_MB, msg_data);
2176 /* wait for an acknowledgement. */
2177 for (i = 0; i < (FW_ACK_TIME_OUT_MS / 10); i++) {
2180 val = bnx2_shmem_rd(bp, BNX2_FW_MB);
2182 if ((val & BNX2_FW_MSG_ACK) == (msg_data & BNX2_DRV_MSG_SEQ))
2185 if ((msg_data & BNX2_DRV_MSG_DATA) == BNX2_DRV_MSG_DATA_WAIT0)
2188 /* If we timed out, inform the firmware that this is the case. */
2189 if ((val & BNX2_FW_MSG_ACK) != (msg_data & BNX2_DRV_MSG_SEQ)) {
2191 printk(KERN_ERR PFX "fw sync timeout, reset code = "
2194 msg_data &= ~BNX2_DRV_MSG_CODE;
2195 msg_data |= BNX2_DRV_MSG_CODE_FW_TIMEOUT;
2197 bnx2_shmem_wr(bp, BNX2_DRV_MB, msg_data);
2202 if ((val & BNX2_FW_MSG_STATUS_MASK) != BNX2_FW_MSG_STATUS_OK)
2209 bnx2_init_5709_context(struct bnx2 *bp)
2214 val = BNX2_CTX_COMMAND_ENABLED | BNX2_CTX_COMMAND_MEM_INIT | (1 << 12);
2215 val |= (BCM_PAGE_BITS - 8) << 16;
2216 REG_WR(bp, BNX2_CTX_COMMAND, val);
2217 for (i = 0; i < 10; i++) {
2218 val = REG_RD(bp, BNX2_CTX_COMMAND);
2219 if (!(val & BNX2_CTX_COMMAND_MEM_INIT))
2223 if (val & BNX2_CTX_COMMAND_MEM_INIT)
2226 for (i = 0; i < bp->ctx_pages; i++) {
2230 memset(bp->ctx_blk[i], 0, BCM_PAGE_SIZE);
2234 REG_WR(bp, BNX2_CTX_HOST_PAGE_TBL_DATA0,
2235 (bp->ctx_blk_mapping[i] & 0xffffffff) |
2236 BNX2_CTX_HOST_PAGE_TBL_DATA0_VALID);
2237 REG_WR(bp, BNX2_CTX_HOST_PAGE_TBL_DATA1,
2238 (u64) bp->ctx_blk_mapping[i] >> 32);
2239 REG_WR(bp, BNX2_CTX_HOST_PAGE_TBL_CTRL, i |
2240 BNX2_CTX_HOST_PAGE_TBL_CTRL_WRITE_REQ);
2241 for (j = 0; j < 10; j++) {
2243 val = REG_RD(bp, BNX2_CTX_HOST_PAGE_TBL_CTRL);
2244 if (!(val & BNX2_CTX_HOST_PAGE_TBL_CTRL_WRITE_REQ))
2248 if (val & BNX2_CTX_HOST_PAGE_TBL_CTRL_WRITE_REQ) {
2257 bnx2_init_context(struct bnx2 *bp)
2263 u32 vcid_addr, pcid_addr, offset;
2268 if (CHIP_ID(bp) == CHIP_ID_5706_A0) {
2271 vcid_addr = GET_PCID_ADDR(vcid);
2273 new_vcid = 0x60 + (vcid & 0xf0) + (vcid & 0x7);
2278 pcid_addr = GET_PCID_ADDR(new_vcid);
2281 vcid_addr = GET_CID_ADDR(vcid);
2282 pcid_addr = vcid_addr;
2285 for (i = 0; i < (CTX_SIZE / PHY_CTX_SIZE); i++) {
2286 vcid_addr += (i << PHY_CTX_SHIFT);
2287 pcid_addr += (i << PHY_CTX_SHIFT);
2289 REG_WR(bp, BNX2_CTX_VIRT_ADDR, vcid_addr);
2290 REG_WR(bp, BNX2_CTX_PAGE_TBL, pcid_addr);
2292 /* Zero out the context. */
2293 for (offset = 0; offset < PHY_CTX_SIZE; offset += 4)
2294 bnx2_ctx_wr(bp, vcid_addr, offset, 0);
2300 bnx2_alloc_bad_rbuf(struct bnx2 *bp)
2306 good_mbuf = kmalloc(512 * sizeof(u16), GFP_KERNEL);
2307 if (good_mbuf == NULL) {
2308 printk(KERN_ERR PFX "Failed to allocate memory in "
2309 "bnx2_alloc_bad_rbuf\n");
2313 REG_WR(bp, BNX2_MISC_ENABLE_SET_BITS,
2314 BNX2_MISC_ENABLE_SET_BITS_RX_MBUF_ENABLE);
2318 /* Allocate a bunch of mbufs and save the good ones in an array. */
2319 val = bnx2_reg_rd_ind(bp, BNX2_RBUF_STATUS1);
2320 while (val & BNX2_RBUF_STATUS1_FREE_COUNT) {
2321 bnx2_reg_wr_ind(bp, BNX2_RBUF_COMMAND,
2322 BNX2_RBUF_COMMAND_ALLOC_REQ);
2324 val = bnx2_reg_rd_ind(bp, BNX2_RBUF_FW_BUF_ALLOC);
2326 val &= BNX2_RBUF_FW_BUF_ALLOC_VALUE;
2328 /* The addresses with Bit 9 set are bad memory blocks. */
2329 if (!(val & (1 << 9))) {
2330 good_mbuf[good_mbuf_cnt] = (u16) val;
2334 val = bnx2_reg_rd_ind(bp, BNX2_RBUF_STATUS1);
2337 /* Free the good ones back to the mbuf pool thus discarding
2338 * all the bad ones. */
2339 while (good_mbuf_cnt) {
2342 val = good_mbuf[good_mbuf_cnt];
2343 val = (val << 9) | val | 1;
2345 bnx2_reg_wr_ind(bp, BNX2_RBUF_FW_BUF_FREE, val);
2352 bnx2_set_mac_addr(struct bnx2 *bp)
2355 u8 *mac_addr = bp->dev->dev_addr;
2357 val = (mac_addr[0] << 8) | mac_addr[1];
2359 REG_WR(bp, BNX2_EMAC_MAC_MATCH0, val);
2361 val = (mac_addr[2] << 24) | (mac_addr[3] << 16) |
2362 (mac_addr[4] << 8) | mac_addr[5];
2364 REG_WR(bp, BNX2_EMAC_MAC_MATCH1, val);
2368 bnx2_alloc_rx_page(struct bnx2 *bp, u16 index)
2371 struct sw_pg *rx_pg = &bp->rx_pg_ring[index];
2372 struct rx_bd *rxbd =
2373 &bp->rx_pg_desc_ring[RX_RING(index)][RX_IDX(index)];
2374 struct page *page = alloc_page(GFP_ATOMIC);
2378 mapping = pci_map_page(bp->pdev, page, 0, PAGE_SIZE,
2379 PCI_DMA_FROMDEVICE);
2381 pci_unmap_addr_set(rx_pg, mapping, mapping);
2382 rxbd->rx_bd_haddr_hi = (u64) mapping >> 32;
2383 rxbd->rx_bd_haddr_lo = (u64) mapping & 0xffffffff;
2388 bnx2_free_rx_page(struct bnx2 *bp, u16 index)
2390 struct sw_pg *rx_pg = &bp->rx_pg_ring[index];
2391 struct page *page = rx_pg->page;
2396 pci_unmap_page(bp->pdev, pci_unmap_addr(rx_pg, mapping), PAGE_SIZE,
2397 PCI_DMA_FROMDEVICE);
2404 bnx2_alloc_rx_skb(struct bnx2 *bp, struct bnx2_napi *bnapi, u16 index)
2406 struct sk_buff *skb;
2407 struct sw_bd *rx_buf = &bp->rx_buf_ring[index];
2409 struct rx_bd *rxbd = &bp->rx_desc_ring[RX_RING(index)][RX_IDX(index)];
2410 unsigned long align;
2412 skb = netdev_alloc_skb(bp->dev, bp->rx_buf_size);
2417 if (unlikely((align = (unsigned long) skb->data & (BNX2_RX_ALIGN - 1))))
2418 skb_reserve(skb, BNX2_RX_ALIGN - align);
2420 mapping = pci_map_single(bp->pdev, skb->data, bp->rx_buf_use_size,
2421 PCI_DMA_FROMDEVICE);
2424 pci_unmap_addr_set(rx_buf, mapping, mapping);
2426 rxbd->rx_bd_haddr_hi = (u64) mapping >> 32;
2427 rxbd->rx_bd_haddr_lo = (u64) mapping & 0xffffffff;
2429 bnapi->rx_prod_bseq += bp->rx_buf_use_size;
2435 bnx2_phy_event_is_set(struct bnx2 *bp, struct bnx2_napi *bnapi, u32 event)
2437 struct status_block *sblk = bnapi->status_blk;
2438 u32 new_link_state, old_link_state;
2441 new_link_state = sblk->status_attn_bits & event;
2442 old_link_state = sblk->status_attn_bits_ack & event;
2443 if (new_link_state != old_link_state) {
2445 REG_WR(bp, BNX2_PCICFG_STATUS_BIT_SET_CMD, event);
2447 REG_WR(bp, BNX2_PCICFG_STATUS_BIT_CLEAR_CMD, event);
2455 bnx2_phy_int(struct bnx2 *bp, struct bnx2_napi *bnapi)
2457 spin_lock(&bp->phy_lock);
2459 if (bnx2_phy_event_is_set(bp, bnapi, STATUS_ATTN_BITS_LINK_STATE))
2461 if (bnx2_phy_event_is_set(bp, bnapi, STATUS_ATTN_BITS_TIMER_ABORT))
2462 bnx2_set_remote_link(bp);
2464 spin_unlock(&bp->phy_lock);
2469 bnx2_get_hw_tx_cons(struct bnx2_napi *bnapi)
2473 if (bnapi->int_num == 0)
2474 cons = bnapi->status_blk->status_tx_quick_consumer_index0;
2476 cons = bnapi->status_blk_msix->status_tx_quick_consumer_index;
2478 if (unlikely((cons & MAX_TX_DESC_CNT) == MAX_TX_DESC_CNT))
2484 bnx2_tx_int(struct bnx2 *bp, struct bnx2_napi *bnapi, int budget)
2486 u16 hw_cons, sw_cons, sw_ring_cons;
2489 hw_cons = bnx2_get_hw_tx_cons(bnapi);
2490 sw_cons = bnapi->tx_cons;
2492 while (sw_cons != hw_cons) {
2493 struct sw_bd *tx_buf;
2494 struct sk_buff *skb;
2497 sw_ring_cons = TX_RING_IDX(sw_cons);
2499 tx_buf = &bp->tx_buf_ring[sw_ring_cons];
2502 /* partial BD completions possible with TSO packets */
2503 if (skb_is_gso(skb)) {
2504 u16 last_idx, last_ring_idx;
2506 last_idx = sw_cons +
2507 skb_shinfo(skb)->nr_frags + 1;
2508 last_ring_idx = sw_ring_cons +
2509 skb_shinfo(skb)->nr_frags + 1;
2510 if (unlikely(last_ring_idx >= MAX_TX_DESC_CNT)) {
2513 if (((s16) ((s16) last_idx - (s16) hw_cons)) > 0) {
2518 pci_unmap_single(bp->pdev, pci_unmap_addr(tx_buf, mapping),
2519 skb_headlen(skb), PCI_DMA_TODEVICE);
2522 last = skb_shinfo(skb)->nr_frags;
2524 for (i = 0; i < last; i++) {
2525 sw_cons = NEXT_TX_BD(sw_cons);
2527 pci_unmap_page(bp->pdev,
2529 &bp->tx_buf_ring[TX_RING_IDX(sw_cons)],
2531 skb_shinfo(skb)->frags[i].size,
2535 sw_cons = NEXT_TX_BD(sw_cons);
2539 if (tx_pkt == budget)
2542 hw_cons = bnx2_get_hw_tx_cons(bnapi);
2545 bnapi->hw_tx_cons = hw_cons;
2546 bnapi->tx_cons = sw_cons;
2547 /* Need to make the tx_cons update visible to bnx2_start_xmit()
2548 * before checking for netif_queue_stopped(). Without the
2549 * memory barrier, there is a small possibility that bnx2_start_xmit()
2550 * will miss it and cause the queue to be stopped forever.
2554 if (unlikely(netif_queue_stopped(bp->dev)) &&
2555 (bnx2_tx_avail(bp, bnapi) > bp->tx_wake_thresh)) {
2556 netif_tx_lock(bp->dev);
2557 if ((netif_queue_stopped(bp->dev)) &&
2558 (bnx2_tx_avail(bp, bnapi) > bp->tx_wake_thresh))
2559 netif_wake_queue(bp->dev);
2560 netif_tx_unlock(bp->dev);
2566 bnx2_reuse_rx_skb_pages(struct bnx2 *bp, struct bnx2_napi *bnapi,
2567 struct sk_buff *skb, int count)
2569 struct sw_pg *cons_rx_pg, *prod_rx_pg;
2570 struct rx_bd *cons_bd, *prod_bd;
2573 u16 hw_prod = bnapi->rx_pg_prod, prod;
2574 u16 cons = bnapi->rx_pg_cons;
2576 for (i = 0; i < count; i++) {
2577 prod = RX_PG_RING_IDX(hw_prod);
2579 prod_rx_pg = &bp->rx_pg_ring[prod];
2580 cons_rx_pg = &bp->rx_pg_ring[cons];
2581 cons_bd = &bp->rx_pg_desc_ring[RX_RING(cons)][RX_IDX(cons)];
2582 prod_bd = &bp->rx_pg_desc_ring[RX_RING(prod)][RX_IDX(prod)];
2584 if (i == 0 && skb) {
2586 struct skb_shared_info *shinfo;
2588 shinfo = skb_shinfo(skb);
2590 page = shinfo->frags[shinfo->nr_frags].page;
2591 shinfo->frags[shinfo->nr_frags].page = NULL;
2592 mapping = pci_map_page(bp->pdev, page, 0, PAGE_SIZE,
2593 PCI_DMA_FROMDEVICE);
2594 cons_rx_pg->page = page;
2595 pci_unmap_addr_set(cons_rx_pg, mapping, mapping);
2599 prod_rx_pg->page = cons_rx_pg->page;
2600 cons_rx_pg->page = NULL;
2601 pci_unmap_addr_set(prod_rx_pg, mapping,
2602 pci_unmap_addr(cons_rx_pg, mapping));
2604 prod_bd->rx_bd_haddr_hi = cons_bd->rx_bd_haddr_hi;
2605 prod_bd->rx_bd_haddr_lo = cons_bd->rx_bd_haddr_lo;
2608 cons = RX_PG_RING_IDX(NEXT_RX_BD(cons));
2609 hw_prod = NEXT_RX_BD(hw_prod);
2611 bnapi->rx_pg_prod = hw_prod;
2612 bnapi->rx_pg_cons = cons;
2616 bnx2_reuse_rx_skb(struct bnx2 *bp, struct bnx2_napi *bnapi, struct sk_buff *skb,
2619 struct sw_bd *cons_rx_buf, *prod_rx_buf;
2620 struct rx_bd *cons_bd, *prod_bd;
2622 cons_rx_buf = &bp->rx_buf_ring[cons];
2623 prod_rx_buf = &bp->rx_buf_ring[prod];
2625 pci_dma_sync_single_for_device(bp->pdev,
2626 pci_unmap_addr(cons_rx_buf, mapping),
2627 BNX2_RX_OFFSET + RX_COPY_THRESH, PCI_DMA_FROMDEVICE);
2629 bnapi->rx_prod_bseq += bp->rx_buf_use_size;
2631 prod_rx_buf->skb = skb;
2636 pci_unmap_addr_set(prod_rx_buf, mapping,
2637 pci_unmap_addr(cons_rx_buf, mapping));
2639 cons_bd = &bp->rx_desc_ring[RX_RING(cons)][RX_IDX(cons)];
2640 prod_bd = &bp->rx_desc_ring[RX_RING(prod)][RX_IDX(prod)];
2641 prod_bd->rx_bd_haddr_hi = cons_bd->rx_bd_haddr_hi;
2642 prod_bd->rx_bd_haddr_lo = cons_bd->rx_bd_haddr_lo;
2646 bnx2_rx_skb(struct bnx2 *bp, struct bnx2_napi *bnapi, struct sk_buff *skb,
2647 unsigned int len, unsigned int hdr_len, dma_addr_t dma_addr,
2651 u16 prod = ring_idx & 0xffff;
2653 err = bnx2_alloc_rx_skb(bp, bnapi, prod);
2654 if (unlikely(err)) {
2655 bnx2_reuse_rx_skb(bp, bnapi, skb, (u16) (ring_idx >> 16), prod);
2657 unsigned int raw_len = len + 4;
2658 int pages = PAGE_ALIGN(raw_len - hdr_len) >> PAGE_SHIFT;
2660 bnx2_reuse_rx_skb_pages(bp, bnapi, NULL, pages);
2665 skb_reserve(skb, BNX2_RX_OFFSET);
2666 pci_unmap_single(bp->pdev, dma_addr, bp->rx_buf_use_size,
2667 PCI_DMA_FROMDEVICE);
2673 unsigned int i, frag_len, frag_size, pages;
2674 struct sw_pg *rx_pg;
2675 u16 pg_cons = bnapi->rx_pg_cons;
2676 u16 pg_prod = bnapi->rx_pg_prod;
2678 frag_size = len + 4 - hdr_len;
2679 pages = PAGE_ALIGN(frag_size) >> PAGE_SHIFT;
2680 skb_put(skb, hdr_len);
2682 for (i = 0; i < pages; i++) {
2683 frag_len = min(frag_size, (unsigned int) PAGE_SIZE);
2684 if (unlikely(frag_len <= 4)) {
2685 unsigned int tail = 4 - frag_len;
2687 bnapi->rx_pg_cons = pg_cons;
2688 bnapi->rx_pg_prod = pg_prod;
2689 bnx2_reuse_rx_skb_pages(bp, bnapi, NULL,
2696 &skb_shinfo(skb)->frags[i - 1];
2698 skb->data_len -= tail;
2699 skb->truesize -= tail;
2703 rx_pg = &bp->rx_pg_ring[pg_cons];
2705 pci_unmap_page(bp->pdev, pci_unmap_addr(rx_pg, mapping),
2706 PAGE_SIZE, PCI_DMA_FROMDEVICE);
2711 skb_fill_page_desc(skb, i, rx_pg->page, 0, frag_len);
2714 err = bnx2_alloc_rx_page(bp, RX_PG_RING_IDX(pg_prod));
2715 if (unlikely(err)) {
2716 bnapi->rx_pg_cons = pg_cons;
2717 bnapi->rx_pg_prod = pg_prod;
2718 bnx2_reuse_rx_skb_pages(bp, bnapi, skb,
2723 frag_size -= frag_len;
2724 skb->data_len += frag_len;
2725 skb->truesize += frag_len;
2726 skb->len += frag_len;
2728 pg_prod = NEXT_RX_BD(pg_prod);
2729 pg_cons = RX_PG_RING_IDX(NEXT_RX_BD(pg_cons));
2731 bnapi->rx_pg_prod = pg_prod;
2732 bnapi->rx_pg_cons = pg_cons;
2738 bnx2_get_hw_rx_cons(struct bnx2_napi *bnapi)
2740 u16 cons = bnapi->status_blk->status_rx_quick_consumer_index0;
2742 if (unlikely((cons & MAX_RX_DESC_CNT) == MAX_RX_DESC_CNT))
2748 bnx2_rx_int(struct bnx2 *bp, struct bnx2_napi *bnapi, int budget)
2750 u16 hw_cons, sw_cons, sw_ring_cons, sw_prod, sw_ring_prod;
2751 struct l2_fhdr *rx_hdr;
2752 int rx_pkt = 0, pg_ring_used = 0;
2754 hw_cons = bnx2_get_hw_rx_cons(bnapi);
2755 sw_cons = bnapi->rx_cons;
2756 sw_prod = bnapi->rx_prod;
2758 /* Memory barrier necessary as speculative reads of the rx
2759 * buffer can be ahead of the index in the status block
2762 while (sw_cons != hw_cons) {
2763 unsigned int len, hdr_len;
2765 struct sw_bd *rx_buf;
2766 struct sk_buff *skb;
2767 dma_addr_t dma_addr;
2769 sw_ring_cons = RX_RING_IDX(sw_cons);
2770 sw_ring_prod = RX_RING_IDX(sw_prod);
2772 rx_buf = &bp->rx_buf_ring[sw_ring_cons];
2777 dma_addr = pci_unmap_addr(rx_buf, mapping);
2779 pci_dma_sync_single_for_cpu(bp->pdev, dma_addr,
2780 BNX2_RX_OFFSET + RX_COPY_THRESH, PCI_DMA_FROMDEVICE);
2782 rx_hdr = (struct l2_fhdr *) skb->data;
2783 len = rx_hdr->l2_fhdr_pkt_len;
2785 if ((status = rx_hdr->l2_fhdr_status) &
2786 (L2_FHDR_ERRORS_BAD_CRC |
2787 L2_FHDR_ERRORS_PHY_DECODE |
2788 L2_FHDR_ERRORS_ALIGNMENT |
2789 L2_FHDR_ERRORS_TOO_SHORT |
2790 L2_FHDR_ERRORS_GIANT_FRAME)) {
2792 bnx2_reuse_rx_skb(bp, bnapi, skb, sw_ring_cons,
2797 if (status & L2_FHDR_STATUS_SPLIT) {
2798 hdr_len = rx_hdr->l2_fhdr_ip_xsum;
2800 } else if (len > bp->rx_jumbo_thresh) {
2801 hdr_len = bp->rx_jumbo_thresh;
2807 if (len <= bp->rx_copy_thresh) {
2808 struct sk_buff *new_skb;
2810 new_skb = netdev_alloc_skb(bp->dev, len + 2);
2811 if (new_skb == NULL) {
2812 bnx2_reuse_rx_skb(bp, bnapi, skb, sw_ring_cons,
2818 skb_copy_from_linear_data_offset(skb,
2820 new_skb->data, len + 2);
2821 skb_reserve(new_skb, 2);
2822 skb_put(new_skb, len);
2824 bnx2_reuse_rx_skb(bp, bnapi, skb,
2825 sw_ring_cons, sw_ring_prod);
2828 } else if (unlikely(bnx2_rx_skb(bp, bnapi, skb, len, hdr_len,
2829 dma_addr, (sw_ring_cons << 16) | sw_ring_prod)))
2832 skb->protocol = eth_type_trans(skb, bp->dev);
2834 if ((len > (bp->dev->mtu + ETH_HLEN)) &&
2835 (ntohs(skb->protocol) != 0x8100)) {
2842 skb->ip_summed = CHECKSUM_NONE;
2844 (status & (L2_FHDR_STATUS_TCP_SEGMENT |
2845 L2_FHDR_STATUS_UDP_DATAGRAM))) {
2847 if (likely((status & (L2_FHDR_ERRORS_TCP_XSUM |
2848 L2_FHDR_ERRORS_UDP_XSUM)) == 0))
2849 skb->ip_summed = CHECKSUM_UNNECESSARY;
2853 if ((status & L2_FHDR_STATUS_L2_VLAN_TAG) && bp->vlgrp) {
2854 vlan_hwaccel_receive_skb(skb, bp->vlgrp,
2855 rx_hdr->l2_fhdr_vlan_tag);
2859 netif_receive_skb(skb);
2861 bp->dev->last_rx = jiffies;
2865 sw_cons = NEXT_RX_BD(sw_cons);
2866 sw_prod = NEXT_RX_BD(sw_prod);
2868 if ((rx_pkt == budget))
2871 /* Refresh hw_cons to see if there is new work */
2872 if (sw_cons == hw_cons) {
2873 hw_cons = bnx2_get_hw_rx_cons(bnapi);
2877 bnapi->rx_cons = sw_cons;
2878 bnapi->rx_prod = sw_prod;
2881 REG_WR16(bp, MB_RX_CID_ADDR + BNX2_L2CTX_HOST_PG_BDIDX,
2884 REG_WR16(bp, MB_RX_CID_ADDR + BNX2_L2CTX_HOST_BDIDX, sw_prod);
2886 REG_WR(bp, MB_RX_CID_ADDR + BNX2_L2CTX_HOST_BSEQ, bnapi->rx_prod_bseq);
2894 /* MSI ISR - The only difference between this and the INTx ISR
2895 * is that the MSI interrupt is always serviced.
2898 bnx2_msi(int irq, void *dev_instance)
2900 struct net_device *dev = dev_instance;
2901 struct bnx2 *bp = netdev_priv(dev);
2902 struct bnx2_napi *bnapi = &bp->bnx2_napi[0];
2904 prefetch(bnapi->status_blk);
2905 REG_WR(bp, BNX2_PCICFG_INT_ACK_CMD,
2906 BNX2_PCICFG_INT_ACK_CMD_USE_INT_HC_PARAM |
2907 BNX2_PCICFG_INT_ACK_CMD_MASK_INT);
2909 /* Return here if interrupt is disabled. */
2910 if (unlikely(atomic_read(&bp->intr_sem) != 0))
2913 netif_rx_schedule(dev, &bnapi->napi);
2919 bnx2_msi_1shot(int irq, void *dev_instance)
2921 struct net_device *dev = dev_instance;
2922 struct bnx2 *bp = netdev_priv(dev);
2923 struct bnx2_napi *bnapi = &bp->bnx2_napi[0];
2925 prefetch(bnapi->status_blk);
2927 /* Return here if interrupt is disabled. */
2928 if (unlikely(atomic_read(&bp->intr_sem) != 0))
2931 netif_rx_schedule(dev, &bnapi->napi);
2937 bnx2_interrupt(int irq, void *dev_instance)
2939 struct net_device *dev = dev_instance;
2940 struct bnx2 *bp = netdev_priv(dev);
2941 struct bnx2_napi *bnapi = &bp->bnx2_napi[0];
2942 struct status_block *sblk = bnapi->status_blk;
2944 /* When using INTx, it is possible for the interrupt to arrive
2945 * at the CPU before the status block posted prior to the
2946 * interrupt. Reading a register will flush the status block.
2947 * When using MSI, the MSI message will always complete after
2948 * the status block write.
2950 if ((sblk->status_idx == bnapi->last_status_idx) &&
2951 (REG_RD(bp, BNX2_PCICFG_MISC_STATUS) &
2952 BNX2_PCICFG_MISC_STATUS_INTA_VALUE))
2955 REG_WR(bp, BNX2_PCICFG_INT_ACK_CMD,
2956 BNX2_PCICFG_INT_ACK_CMD_USE_INT_HC_PARAM |
2957 BNX2_PCICFG_INT_ACK_CMD_MASK_INT);
2959 /* Read back to deassert IRQ immediately to avoid too many
2960 * spurious interrupts.
2962 REG_RD(bp, BNX2_PCICFG_INT_ACK_CMD);
2964 /* Return here if interrupt is shared and is disabled. */
2965 if (unlikely(atomic_read(&bp->intr_sem) != 0))
2968 if (netif_rx_schedule_prep(dev, &bnapi->napi)) {
2969 bnapi->last_status_idx = sblk->status_idx;
2970 __netif_rx_schedule(dev, &bnapi->napi);
2977 bnx2_tx_msix(int irq, void *dev_instance)
2979 struct net_device *dev = dev_instance;
2980 struct bnx2 *bp = netdev_priv(dev);
2981 struct bnx2_napi *bnapi = &bp->bnx2_napi[BNX2_TX_VEC];
2983 prefetch(bnapi->status_blk_msix);
2985 /* Return here if interrupt is disabled. */
2986 if (unlikely(atomic_read(&bp->intr_sem) != 0))
2989 netif_rx_schedule(dev, &bnapi->napi);
2993 #define STATUS_ATTN_EVENTS (STATUS_ATTN_BITS_LINK_STATE | \
2994 STATUS_ATTN_BITS_TIMER_ABORT)
2997 bnx2_has_work(struct bnx2_napi *bnapi)
2999 struct status_block *sblk = bnapi->status_blk;
3001 if ((bnx2_get_hw_rx_cons(bnapi) != bnapi->rx_cons) ||
3002 (bnx2_get_hw_tx_cons(bnapi) != bnapi->hw_tx_cons))
3005 if ((sblk->status_attn_bits & STATUS_ATTN_EVENTS) !=
3006 (sblk->status_attn_bits_ack & STATUS_ATTN_EVENTS))
3012 static int bnx2_tx_poll(struct napi_struct *napi, int budget)
3014 struct bnx2_napi *bnapi = container_of(napi, struct bnx2_napi, napi);
3015 struct bnx2 *bp = bnapi->bp;
3017 struct status_block_msix *sblk = bnapi->status_blk_msix;
3020 work_done += bnx2_tx_int(bp, bnapi, budget - work_done);
3021 if (unlikely(work_done >= budget))
3024 bnapi->last_status_idx = sblk->status_idx;
3026 } while (bnx2_get_hw_tx_cons(bnapi) != bnapi->hw_tx_cons);
3028 netif_rx_complete(bp->dev, napi);
3029 REG_WR(bp, BNX2_PCICFG_INT_ACK_CMD, bnapi->int_num |
3030 BNX2_PCICFG_INT_ACK_CMD_INDEX_VALID |
3031 bnapi->last_status_idx);
3035 static int bnx2_poll_work(struct bnx2 *bp, struct bnx2_napi *bnapi,
3036 int work_done, int budget)
3038 struct status_block *sblk = bnapi->status_blk;
3039 u32 status_attn_bits = sblk->status_attn_bits;
3040 u32 status_attn_bits_ack = sblk->status_attn_bits_ack;
3042 if ((status_attn_bits & STATUS_ATTN_EVENTS) !=
3043 (status_attn_bits_ack & STATUS_ATTN_EVENTS)) {
3045 bnx2_phy_int(bp, bnapi);
3047 /* This is needed to take care of transient status
3048 * during link changes.
3050 REG_WR(bp, BNX2_HC_COMMAND,
3051 bp->hc_cmd | BNX2_HC_COMMAND_COAL_NOW_WO_INT);
3052 REG_RD(bp, BNX2_HC_COMMAND);
3055 if (bnx2_get_hw_tx_cons(bnapi) != bnapi->hw_tx_cons)
3056 bnx2_tx_int(bp, bnapi, 0);
3058 if (bnx2_get_hw_rx_cons(bnapi) != bnapi->rx_cons)
3059 work_done += bnx2_rx_int(bp, bnapi, budget - work_done);
3064 static int bnx2_poll(struct napi_struct *napi, int budget)
3066 struct bnx2_napi *bnapi = container_of(napi, struct bnx2_napi, napi);
3067 struct bnx2 *bp = bnapi->bp;
3069 struct status_block *sblk = bnapi->status_blk;
3072 work_done = bnx2_poll_work(bp, bnapi, work_done, budget);
3074 if (unlikely(work_done >= budget))
3077 /* bnapi->last_status_idx is used below to tell the hw how
3078 * much work has been processed, so we must read it before
3079 * checking for more work.
3081 bnapi->last_status_idx = sblk->status_idx;
3083 if (likely(!bnx2_has_work(bnapi))) {
3084 netif_rx_complete(bp->dev, napi);
3085 if (likely(bp->flags & BNX2_FLAG_USING_MSI_OR_MSIX)) {
3086 REG_WR(bp, BNX2_PCICFG_INT_ACK_CMD,
3087 BNX2_PCICFG_INT_ACK_CMD_INDEX_VALID |
3088 bnapi->last_status_idx);
3091 REG_WR(bp, BNX2_PCICFG_INT_ACK_CMD,
3092 BNX2_PCICFG_INT_ACK_CMD_INDEX_VALID |
3093 BNX2_PCICFG_INT_ACK_CMD_MASK_INT |
3094 bnapi->last_status_idx);
3096 REG_WR(bp, BNX2_PCICFG_INT_ACK_CMD,
3097 BNX2_PCICFG_INT_ACK_CMD_INDEX_VALID |
3098 bnapi->last_status_idx);
3106 /* Called with rtnl_lock from vlan functions and also netif_tx_lock
3107 * from set_multicast.
3110 bnx2_set_rx_mode(struct net_device *dev)
3112 struct bnx2 *bp = netdev_priv(dev);
3113 u32 rx_mode, sort_mode;
3116 spin_lock_bh(&bp->phy_lock);
3118 rx_mode = bp->rx_mode & ~(BNX2_EMAC_RX_MODE_PROMISCUOUS |
3119 BNX2_EMAC_RX_MODE_KEEP_VLAN_TAG);
3120 sort_mode = 1 | BNX2_RPM_SORT_USER0_BC_EN;
3122 if (!bp->vlgrp && !(bp->flags & BNX2_FLAG_ASF_ENABLE))
3123 rx_mode |= BNX2_EMAC_RX_MODE_KEEP_VLAN_TAG;
3125 if (!(bp->flags & BNX2_FLAG_ASF_ENABLE))
3126 rx_mode |= BNX2_EMAC_RX_MODE_KEEP_VLAN_TAG;
3128 if (dev->flags & IFF_PROMISC) {
3129 /* Promiscuous mode. */
3130 rx_mode |= BNX2_EMAC_RX_MODE_PROMISCUOUS;
3131 sort_mode |= BNX2_RPM_SORT_USER0_PROM_EN |
3132 BNX2_RPM_SORT_USER0_PROM_VLAN;
3134 else if (dev->flags & IFF_ALLMULTI) {
3135 for (i = 0; i < NUM_MC_HASH_REGISTERS; i++) {
3136 REG_WR(bp, BNX2_EMAC_MULTICAST_HASH0 + (i * 4),
3139 sort_mode |= BNX2_RPM_SORT_USER0_MC_EN;
3142 /* Accept one or more multicast(s). */
3143 struct dev_mc_list *mclist;
3144 u32 mc_filter[NUM_MC_HASH_REGISTERS];
3149 memset(mc_filter, 0, 4 * NUM_MC_HASH_REGISTERS);
3151 for (i = 0, mclist = dev->mc_list; mclist && i < dev->mc_count;
3152 i++, mclist = mclist->next) {
3154 crc = ether_crc_le(ETH_ALEN, mclist->dmi_addr);
3156 regidx = (bit & 0xe0) >> 5;
3158 mc_filter[regidx] |= (1 << bit);
3161 for (i = 0; i < NUM_MC_HASH_REGISTERS; i++) {
3162 REG_WR(bp, BNX2_EMAC_MULTICAST_HASH0 + (i * 4),
3166 sort_mode |= BNX2_RPM_SORT_USER0_MC_HSH_EN;
3169 if (rx_mode != bp->rx_mode) {
3170 bp->rx_mode = rx_mode;
3171 REG_WR(bp, BNX2_EMAC_RX_MODE, rx_mode);
3174 REG_WR(bp, BNX2_RPM_SORT_USER0, 0x0);
3175 REG_WR(bp, BNX2_RPM_SORT_USER0, sort_mode);
3176 REG_WR(bp, BNX2_RPM_SORT_USER0, sort_mode | BNX2_RPM_SORT_USER0_ENA);
3178 spin_unlock_bh(&bp->phy_lock);
3182 load_rv2p_fw(struct bnx2 *bp, __le32 *rv2p_code, u32 rv2p_code_len,
3188 if (rv2p_proc == RV2P_PROC2 && CHIP_NUM(bp) == CHIP_NUM_5709) {
3189 val = le32_to_cpu(rv2p_code[XI_RV2P_PROC2_MAX_BD_PAGE_LOC]);
3190 val &= ~XI_RV2P_PROC2_BD_PAGE_SIZE_MSK;
3191 val |= XI_RV2P_PROC2_BD_PAGE_SIZE;
3192 rv2p_code[XI_RV2P_PROC2_MAX_BD_PAGE_LOC] = cpu_to_le32(val);
3195 for (i = 0; i < rv2p_code_len; i += 8) {
3196 REG_WR(bp, BNX2_RV2P_INSTR_HIGH, le32_to_cpu(*rv2p_code));
3198 REG_WR(bp, BNX2_RV2P_INSTR_LOW, le32_to_cpu(*rv2p_code));
3201 if (rv2p_proc == RV2P_PROC1) {
3202 val = (i / 8) | BNX2_RV2P_PROC1_ADDR_CMD_RDWR;
3203 REG_WR(bp, BNX2_RV2P_PROC1_ADDR_CMD, val);
3206 val = (i / 8) | BNX2_RV2P_PROC2_ADDR_CMD_RDWR;
3207 REG_WR(bp, BNX2_RV2P_PROC2_ADDR_CMD, val);
3211 /* Reset the processor, un-stall is done later. */
3212 if (rv2p_proc == RV2P_PROC1) {
3213 REG_WR(bp, BNX2_RV2P_COMMAND, BNX2_RV2P_COMMAND_PROC1_RESET);
3216 REG_WR(bp, BNX2_RV2P_COMMAND, BNX2_RV2P_COMMAND_PROC2_RESET);
3221 load_cpu_fw(struct bnx2 *bp, struct cpu_reg *cpu_reg, struct fw_info *fw)
3228 val = bnx2_reg_rd_ind(bp, cpu_reg->mode);
3229 val |= cpu_reg->mode_value_halt;
3230 bnx2_reg_wr_ind(bp, cpu_reg->mode, val);
3231 bnx2_reg_wr_ind(bp, cpu_reg->state, cpu_reg->state_value_clear);
3233 /* Load the Text area. */
3234 offset = cpu_reg->spad_base + (fw->text_addr - cpu_reg->mips_view_base);
3238 rc = zlib_inflate_blob(fw->text, FW_BUF_SIZE, fw->gz_text,
3243 for (j = 0; j < (fw->text_len / 4); j++, offset += 4) {
3244 bnx2_reg_wr_ind(bp, offset, le32_to_cpu(fw->text[j]));
3248 /* Load the Data area. */
3249 offset = cpu_reg->spad_base + (fw->data_addr - cpu_reg->mips_view_base);
3253 for (j = 0; j < (fw->data_len / 4); j++, offset += 4) {
3254 bnx2_reg_wr_ind(bp, offset, fw->data[j]);
3258 /* Load the SBSS area. */
3259 offset = cpu_reg->spad_base + (fw->sbss_addr - cpu_reg->mips_view_base);
3263 for (j = 0; j < (fw->sbss_len / 4); j++, offset += 4) {
3264 bnx2_reg_wr_ind(bp, offset, 0);
3268 /* Load the BSS area. */
3269 offset = cpu_reg->spad_base + (fw->bss_addr - cpu_reg->mips_view_base);
3273 for (j = 0; j < (fw->bss_len/4); j++, offset += 4) {
3274 bnx2_reg_wr_ind(bp, offset, 0);
3278 /* Load the Read-Only area. */
3279 offset = cpu_reg->spad_base +
3280 (fw->rodata_addr - cpu_reg->mips_view_base);
3284 for (j = 0; j < (fw->rodata_len / 4); j++, offset += 4) {
3285 bnx2_reg_wr_ind(bp, offset, fw->rodata[j]);
3289 /* Clear the pre-fetch instruction. */
3290 bnx2_reg_wr_ind(bp, cpu_reg->inst, 0);
3291 bnx2_reg_wr_ind(bp, cpu_reg->pc, fw->start_addr);
3293 /* Start the CPU. */
3294 val = bnx2_reg_rd_ind(bp, cpu_reg->mode);
3295 val &= ~cpu_reg->mode_value_halt;
3296 bnx2_reg_wr_ind(bp, cpu_reg->state, cpu_reg->state_value_clear);
3297 bnx2_reg_wr_ind(bp, cpu_reg->mode, val);
3303 bnx2_init_cpus(struct bnx2 *bp)
3305 struct cpu_reg cpu_reg;
3310 /* Initialize the RV2P processor. */
3311 text = vmalloc(FW_BUF_SIZE);
3314 if (CHIP_NUM(bp) == CHIP_NUM_5709) {
3315 rv2p = bnx2_xi_rv2p_proc1;
3316 rv2p_len = sizeof(bnx2_xi_rv2p_proc1);
3318 rv2p = bnx2_rv2p_proc1;
3319 rv2p_len = sizeof(bnx2_rv2p_proc1);
3321 rc = zlib_inflate_blob(text, FW_BUF_SIZE, rv2p, rv2p_len);
3325 load_rv2p_fw(bp, text, rc /* == len */, RV2P_PROC1);
3327 if (CHIP_NUM(bp) == CHIP_NUM_5709) {
3328 rv2p = bnx2_xi_rv2p_proc2;
3329 rv2p_len = sizeof(bnx2_xi_rv2p_proc2);
3331 rv2p = bnx2_rv2p_proc2;
3332 rv2p_len = sizeof(bnx2_rv2p_proc2);
3334 rc = zlib_inflate_blob(text, FW_BUF_SIZE, rv2p, rv2p_len);
3338 load_rv2p_fw(bp, text, rc /* == len */, RV2P_PROC2);
3340 /* Initialize the RX Processor. */
3341 cpu_reg.mode = BNX2_RXP_CPU_MODE;
3342 cpu_reg.mode_value_halt = BNX2_RXP_CPU_MODE_SOFT_HALT;
3343 cpu_reg.mode_value_sstep = BNX2_RXP_CPU_MODE_STEP_ENA;
3344 cpu_reg.state = BNX2_RXP_CPU_STATE;
3345 cpu_reg.state_value_clear = 0xffffff;
3346 cpu_reg.gpr0 = BNX2_RXP_CPU_REG_FILE;
3347 cpu_reg.evmask = BNX2_RXP_CPU_EVENT_MASK;
3348 cpu_reg.pc = BNX2_RXP_CPU_PROGRAM_COUNTER;
3349 cpu_reg.inst = BNX2_RXP_CPU_INSTRUCTION;
3350 cpu_reg.bp = BNX2_RXP_CPU_HW_BREAKPOINT;
3351 cpu_reg.spad_base = BNX2_RXP_SCRATCH;
3352 cpu_reg.mips_view_base = 0x8000000;
3354 if (CHIP_NUM(bp) == CHIP_NUM_5709)
3355 fw = &bnx2_rxp_fw_09;
3357 fw = &bnx2_rxp_fw_06;
3360 rc = load_cpu_fw(bp, &cpu_reg, fw);
3364 /* Initialize the TX Processor. */
3365 cpu_reg.mode = BNX2_TXP_CPU_MODE;
3366 cpu_reg.mode_value_halt = BNX2_TXP_CPU_MODE_SOFT_HALT;
3367 cpu_reg.mode_value_sstep = BNX2_TXP_CPU_MODE_STEP_ENA;
3368 cpu_reg.state = BNX2_TXP_CPU_STATE;
3369 cpu_reg.state_value_clear = 0xffffff;
3370 cpu_reg.gpr0 = BNX2_TXP_CPU_REG_FILE;
3371 cpu_reg.evmask = BNX2_TXP_CPU_EVENT_MASK;
3372 cpu_reg.pc = BNX2_TXP_CPU_PROGRAM_COUNTER;
3373 cpu_reg.inst = BNX2_TXP_CPU_INSTRUCTION;
3374 cpu_reg.bp = BNX2_TXP_CPU_HW_BREAKPOINT;
3375 cpu_reg.spad_base = BNX2_TXP_SCRATCH;
3376 cpu_reg.mips_view_base = 0x8000000;
3378 if (CHIP_NUM(bp) == CHIP_NUM_5709)
3379 fw = &bnx2_txp_fw_09;
3381 fw = &bnx2_txp_fw_06;
3384 rc = load_cpu_fw(bp, &cpu_reg, fw);
3388 /* Initialize the TX Patch-up Processor. */
3389 cpu_reg.mode = BNX2_TPAT_CPU_MODE;
3390 cpu_reg.mode_value_halt = BNX2_TPAT_CPU_MODE_SOFT_HALT;
3391 cpu_reg.mode_value_sstep = BNX2_TPAT_CPU_MODE_STEP_ENA;
3392 cpu_reg.state = BNX2_TPAT_CPU_STATE;
3393 cpu_reg.state_value_clear = 0xffffff;
3394 cpu_reg.gpr0 = BNX2_TPAT_CPU_REG_FILE;
3395 cpu_reg.evmask = BNX2_TPAT_CPU_EVENT_MASK;
3396 cpu_reg.pc = BNX2_TPAT_CPU_PROGRAM_COUNTER;
3397 cpu_reg.inst = BNX2_TPAT_CPU_INSTRUCTION;
3398 cpu_reg.bp = BNX2_TPAT_CPU_HW_BREAKPOINT;
3399 cpu_reg.spad_base = BNX2_TPAT_SCRATCH;
3400 cpu_reg.mips_view_base = 0x8000000;
3402 if (CHIP_NUM(bp) == CHIP_NUM_5709)
3403 fw = &bnx2_tpat_fw_09;
3405 fw = &bnx2_tpat_fw_06;
3408 rc = load_cpu_fw(bp, &cpu_reg, fw);
3412 /* Initialize the Completion Processor. */
3413 cpu_reg.mode = BNX2_COM_CPU_MODE;
3414 cpu_reg.mode_value_halt = BNX2_COM_CPU_MODE_SOFT_HALT;
3415 cpu_reg.mode_value_sstep = BNX2_COM_CPU_MODE_STEP_ENA;
3416 cpu_reg.state = BNX2_COM_CPU_STATE;
3417 cpu_reg.state_value_clear = 0xffffff;
3418 cpu_reg.gpr0 = BNX2_COM_CPU_REG_FILE;
3419 cpu_reg.evmask = BNX2_COM_CPU_EVENT_MASK;
3420 cpu_reg.pc = BNX2_COM_CPU_PROGRAM_COUNTER;
3421 cpu_reg.inst = BNX2_COM_CPU_INSTRUCTION;
3422 cpu_reg.bp = BNX2_COM_CPU_HW_BREAKPOINT;
3423 cpu_reg.spad_base = BNX2_COM_SCRATCH;
3424 cpu_reg.mips_view_base = 0x8000000;
3426 if (CHIP_NUM(bp) == CHIP_NUM_5709)
3427 fw = &bnx2_com_fw_09;
3429 fw = &bnx2_com_fw_06;
3432 rc = load_cpu_fw(bp, &cpu_reg, fw);
3436 /* Initialize the Command Processor. */
3437 cpu_reg.mode = BNX2_CP_CPU_MODE;
3438 cpu_reg.mode_value_halt = BNX2_CP_CPU_MODE_SOFT_HALT;
3439 cpu_reg.mode_value_sstep = BNX2_CP_CPU_MODE_STEP_ENA;
3440 cpu_reg.state = BNX2_CP_CPU_STATE;
3441 cpu_reg.state_value_clear = 0xffffff;
3442 cpu_reg.gpr0 = BNX2_CP_CPU_REG_FILE;
3443 cpu_reg.evmask = BNX2_CP_CPU_EVENT_MASK;
3444 cpu_reg.pc = BNX2_CP_CPU_PROGRAM_COUNTER;
3445 cpu_reg.inst = BNX2_CP_CPU_INSTRUCTION;
3446 cpu_reg.bp = BNX2_CP_CPU_HW_BREAKPOINT;
3447 cpu_reg.spad_base = BNX2_CP_SCRATCH;
3448 cpu_reg.mips_view_base = 0x8000000;
3450 if (CHIP_NUM(bp) == CHIP_NUM_5709)
3451 fw = &bnx2_cp_fw_09;
3453 fw = &bnx2_cp_fw_06;
3456 rc = load_cpu_fw(bp, &cpu_reg, fw);
3464 bnx2_set_power_state(struct bnx2 *bp, pci_power_t state)
3468 pci_read_config_word(bp->pdev, bp->pm_cap + PCI_PM_CTRL, &pmcsr);
3474 pci_write_config_word(bp->pdev, bp->pm_cap + PCI_PM_CTRL,
3475 (pmcsr & ~PCI_PM_CTRL_STATE_MASK) |
3476 PCI_PM_CTRL_PME_STATUS);
3478 if (pmcsr & PCI_PM_CTRL_STATE_MASK)
3479 /* delay required during transition out of D3hot */
3482 val = REG_RD(bp, BNX2_EMAC_MODE);
3483 val |= BNX2_EMAC_MODE_MPKT_RCVD | BNX2_EMAC_MODE_ACPI_RCVD;
3484 val &= ~BNX2_EMAC_MODE_MPKT;
3485 REG_WR(bp, BNX2_EMAC_MODE, val);
3487 val = REG_RD(bp, BNX2_RPM_CONFIG);
3488 val &= ~BNX2_RPM_CONFIG_ACPI_ENA;
3489 REG_WR(bp, BNX2_RPM_CONFIG, val);
3500 autoneg = bp->autoneg;
3501 advertising = bp->advertising;
3503 if (bp->phy_port == PORT_TP) {
3504 bp->autoneg = AUTONEG_SPEED;
3505 bp->advertising = ADVERTISED_10baseT_Half |
3506 ADVERTISED_10baseT_Full |
3507 ADVERTISED_100baseT_Half |
3508 ADVERTISED_100baseT_Full |
3512 spin_lock_bh(&bp->phy_lock);
3513 bnx2_setup_phy(bp, bp->phy_port);
3514 spin_unlock_bh(&bp->phy_lock);
3516 bp->autoneg = autoneg;
3517 bp->advertising = advertising;
3519 bnx2_set_mac_addr(bp);
3521 val = REG_RD(bp, BNX2_EMAC_MODE);
3523 /* Enable port mode. */
3524 val &= ~BNX2_EMAC_MODE_PORT;
3525 val |= BNX2_EMAC_MODE_MPKT_RCVD |
3526 BNX2_EMAC_MODE_ACPI_RCVD |
3527 BNX2_EMAC_MODE_MPKT;
3528 if (bp->phy_port == PORT_TP)
3529 val |= BNX2_EMAC_MODE_PORT_MII;
3531 val |= BNX2_EMAC_MODE_PORT_GMII;
3532 if (bp->line_speed == SPEED_2500)
3533 val |= BNX2_EMAC_MODE_25G_MODE;
3536 REG_WR(bp, BNX2_EMAC_MODE, val);
3538 /* receive all multicast */
3539 for (i = 0; i < NUM_MC_HASH_REGISTERS; i++) {
3540 REG_WR(bp, BNX2_EMAC_MULTICAST_HASH0 + (i * 4),
3543 REG_WR(bp, BNX2_EMAC_RX_MODE,
3544 BNX2_EMAC_RX_MODE_SORT_MODE);
3546 val = 1 | BNX2_RPM_SORT_USER0_BC_EN |
3547 BNX2_RPM_SORT_USER0_MC_EN;
3548 REG_WR(bp, BNX2_RPM_SORT_USER0, 0x0);
3549 REG_WR(bp, BNX2_RPM_SORT_USER0, val);
3550 REG_WR(bp, BNX2_RPM_SORT_USER0, val |
3551 BNX2_RPM_SORT_USER0_ENA);
3553 /* Need to enable EMAC and RPM for WOL. */
3554 REG_WR(bp, BNX2_MISC_ENABLE_SET_BITS,
3555 BNX2_MISC_ENABLE_SET_BITS_RX_PARSER_MAC_ENABLE |
3556 BNX2_MISC_ENABLE_SET_BITS_TX_HEADER_Q_ENABLE |
3557 BNX2_MISC_ENABLE_SET_BITS_EMAC_ENABLE);
3559 val = REG_RD(bp, BNX2_RPM_CONFIG);
3560 val &= ~BNX2_RPM_CONFIG_ACPI_ENA;
3561 REG_WR(bp, BNX2_RPM_CONFIG, val);
3563 wol_msg = BNX2_DRV_MSG_CODE_SUSPEND_WOL;
3566 wol_msg = BNX2_DRV_MSG_CODE_SUSPEND_NO_WOL;
3569 if (!(bp->flags & BNX2_FLAG_NO_WOL))
3570 bnx2_fw_sync(bp, BNX2_DRV_MSG_DATA_WAIT3 | wol_msg, 0);
3572 pmcsr &= ~PCI_PM_CTRL_STATE_MASK;
3573 if ((CHIP_ID(bp) == CHIP_ID_5706_A0) ||
3574 (CHIP_ID(bp) == CHIP_ID_5706_A1)) {
3583 pmcsr |= PCI_PM_CTRL_PME_ENABLE;
3585 pci_write_config_word(bp->pdev, bp->pm_cap + PCI_PM_CTRL,
3588 /* No more memory access after this point until
3589 * device is brought back to D0.
3601 bnx2_acquire_nvram_lock(struct bnx2 *bp)
3606 /* Request access to the flash interface. */
3607 REG_WR(bp, BNX2_NVM_SW_ARB, BNX2_NVM_SW_ARB_ARB_REQ_SET2);
3608 for (j = 0; j < NVRAM_TIMEOUT_COUNT; j++) {
3609 val = REG_RD(bp, BNX2_NVM_SW_ARB);
3610 if (val & BNX2_NVM_SW_ARB_ARB_ARB2)
3616 if (j >= NVRAM_TIMEOUT_COUNT)
3623 bnx2_release_nvram_lock(struct bnx2 *bp)
3628 /* Relinquish nvram interface. */
3629 REG_WR(bp, BNX2_NVM_SW_ARB, BNX2_NVM_SW_ARB_ARB_REQ_CLR2);
3631 for (j = 0; j < NVRAM_TIMEOUT_COUNT; j++) {
3632 val = REG_RD(bp, BNX2_NVM_SW_ARB);
3633 if (!(val & BNX2_NVM_SW_ARB_ARB_ARB2))
3639 if (j >= NVRAM_TIMEOUT_COUNT)
3647 bnx2_enable_nvram_write(struct bnx2 *bp)
3651 val = REG_RD(bp, BNX2_MISC_CFG);
3652 REG_WR(bp, BNX2_MISC_CFG, val | BNX2_MISC_CFG_NVM_WR_EN_PCI);
3654 if (bp->flash_info->flags & BNX2_NV_WREN) {
3657 REG_WR(bp, BNX2_NVM_COMMAND, BNX2_NVM_COMMAND_DONE);
3658 REG_WR(bp, BNX2_NVM_COMMAND,
3659 BNX2_NVM_COMMAND_WREN | BNX2_NVM_COMMAND_DOIT);
3661 for (j = 0; j < NVRAM_TIMEOUT_COUNT; j++) {
3664 val = REG_RD(bp, BNX2_NVM_COMMAND);
3665 if (val & BNX2_NVM_COMMAND_DONE)
3669 if (j >= NVRAM_TIMEOUT_COUNT)
3676 bnx2_disable_nvram_write(struct bnx2 *bp)
3680 val = REG_RD(bp, BNX2_MISC_CFG);
3681 REG_WR(bp, BNX2_MISC_CFG, val & ~BNX2_MISC_CFG_NVM_WR_EN);
3686 bnx2_enable_nvram_access(struct bnx2 *bp)
3690 val = REG_RD(bp, BNX2_NVM_ACCESS_ENABLE);
3691 /* Enable both bits, even on read. */
3692 REG_WR(bp, BNX2_NVM_ACCESS_ENABLE,
3693 val | BNX2_NVM_ACCESS_ENABLE_EN | BNX2_NVM_ACCESS_ENABLE_WR_EN);
3697 bnx2_disable_nvram_access(struct bnx2 *bp)
3701 val = REG_RD(bp, BNX2_NVM_ACCESS_ENABLE);
3702 /* Disable both bits, even after read. */
3703 REG_WR(bp, BNX2_NVM_ACCESS_ENABLE,
3704 val & ~(BNX2_NVM_ACCESS_ENABLE_EN |
3705 BNX2_NVM_ACCESS_ENABLE_WR_EN));
3709 bnx2_nvram_erase_page(struct bnx2 *bp, u32 offset)
3714 if (bp->flash_info->flags & BNX2_NV_BUFFERED)
3715 /* Buffered flash, no erase needed */
3718 /* Build an erase command */
3719 cmd = BNX2_NVM_COMMAND_ERASE | BNX2_NVM_COMMAND_WR |
3720 BNX2_NVM_COMMAND_DOIT;
3722 /* Need to clear DONE bit separately. */
3723 REG_WR(bp, BNX2_NVM_COMMAND, BNX2_NVM_COMMAND_DONE);
3725 /* Address of the NVRAM to read from. */
3726 REG_WR(bp, BNX2_NVM_ADDR, offset & BNX2_NVM_ADDR_NVM_ADDR_VALUE);
3728 /* Issue an erase command. */
3729 REG_WR(bp, BNX2_NVM_COMMAND, cmd);
3731 /* Wait for completion. */
3732 for (j = 0; j < NVRAM_TIMEOUT_COUNT; j++) {
3737 val = REG_RD(bp, BNX2_NVM_COMMAND);
3738 if (val & BNX2_NVM_COMMAND_DONE)
3742 if (j >= NVRAM_TIMEOUT_COUNT)
3749 bnx2_nvram_read_dword(struct bnx2 *bp, u32 offset, u8 *ret_val, u32 cmd_flags)
3754 /* Build the command word. */
3755 cmd = BNX2_NVM_COMMAND_DOIT | cmd_flags;
3757 /* Calculate an offset of a buffered flash, not needed for 5709. */
3758 if (bp->flash_info->flags & BNX2_NV_TRANSLATE) {
3759 offset = ((offset / bp->flash_info->page_size) <<
3760 bp->flash_info->page_bits) +
3761 (offset % bp->flash_info->page_size);
3764 /* Need to clear DONE bit separately. */
3765 REG_WR(bp, BNX2_NVM_COMMAND, BNX2_NVM_COMMAND_DONE);
3767 /* Address of the NVRAM to read from. */
3768 REG_WR(bp, BNX2_NVM_ADDR, offset & BNX2_NVM_ADDR_NVM_ADDR_VALUE);
3770 /* Issue a read command. */
3771 REG_WR(bp, BNX2_NVM_COMMAND, cmd);
3773 /* Wait for completion. */
3774 for (j = 0; j < NVRAM_TIMEOUT_COUNT; j++) {
3779 val = REG_RD(bp, BNX2_NVM_COMMAND);
3780 if (val & BNX2_NVM_COMMAND_DONE) {
3781 __be32 v = cpu_to_be32(REG_RD(bp, BNX2_NVM_READ));
3782 memcpy(ret_val, &v, 4);
3786 if (j >= NVRAM_TIMEOUT_COUNT)
3794 bnx2_nvram_write_dword(struct bnx2 *bp, u32 offset, u8 *val, u32 cmd_flags)
3800 /* Build the command word. */
3801 cmd = BNX2_NVM_COMMAND_DOIT | BNX2_NVM_COMMAND_WR | cmd_flags;
3803 /* Calculate an offset of a buffered flash, not needed for 5709. */
3804 if (bp->flash_info->flags & BNX2_NV_TRANSLATE) {
3805 offset = ((offset / bp->flash_info->page_size) <<
3806 bp->flash_info->page_bits) +
3807 (offset % bp->flash_info->page_size);
3810 /* Need to clear DONE bit separately. */
3811 REG_WR(bp, BNX2_NVM_COMMAND, BNX2_NVM_COMMAND_DONE);
3813 memcpy(&val32, val, 4);
3815 /* Write the data. */
3816 REG_WR(bp, BNX2_NVM_WRITE, be32_to_cpu(val32));
3818 /* Address of the NVRAM to write to. */
3819 REG_WR(bp, BNX2_NVM_ADDR, offset & BNX2_NVM_ADDR_NVM_ADDR_VALUE);
3821 /* Issue the write command. */
3822 REG_WR(bp, BNX2_NVM_COMMAND, cmd);
3824 /* Wait for completion. */
3825 for (j = 0; j < NVRAM_TIMEOUT_COUNT; j++) {
3828 if (REG_RD(bp, BNX2_NVM_COMMAND) & BNX2_NVM_COMMAND_DONE)
3831 if (j >= NVRAM_TIMEOUT_COUNT)
3838 bnx2_init_nvram(struct bnx2 *bp)
3841 int j, entry_count, rc = 0;
3842 struct flash_spec *flash;
3844 if (CHIP_NUM(bp) == CHIP_NUM_5709) {
3845 bp->flash_info = &flash_5709;
3846 goto get_flash_size;
3849 /* Determine the selected interface. */
3850 val = REG_RD(bp, BNX2_NVM_CFG1);
3852 entry_count = ARRAY_SIZE(flash_table);
3854 if (val & 0x40000000) {
3856 /* Flash interface has been reconfigured */
3857 for (j = 0, flash = &flash_table[0]; j < entry_count;
3859 if ((val & FLASH_BACKUP_STRAP_MASK) ==
3860 (flash->config1 & FLASH_BACKUP_STRAP_MASK)) {
3861 bp->flash_info = flash;
3868 /* Not yet been reconfigured */
3870 if (val & (1 << 23))
3871 mask = FLASH_BACKUP_STRAP_MASK;
3873 mask = FLASH_STRAP_MASK;
3875 for (j = 0, flash = &flash_table[0]; j < entry_count;
3878 if ((val & mask) == (flash->strapping & mask)) {
3879 bp->flash_info = flash;
3881 /* Request access to the flash interface. */
3882 if ((rc = bnx2_acquire_nvram_lock(bp)) != 0)
3885 /* Enable access to flash interface */
3886 bnx2_enable_nvram_access(bp);
3888 /* Reconfigure the flash interface */
3889 REG_WR(bp, BNX2_NVM_CFG1, flash->config1);
3890 REG_WR(bp, BNX2_NVM_CFG2, flash->config2);
3891 REG_WR(bp, BNX2_NVM_CFG3, flash->config3);
3892 REG_WR(bp, BNX2_NVM_WRITE1, flash->write1);
3894 /* Disable access to flash interface */
3895 bnx2_disable_nvram_access(bp);
3896 bnx2_release_nvram_lock(bp);
3901 } /* if (val & 0x40000000) */
3903 if (j == entry_count) {
3904 bp->flash_info = NULL;
3905 printk(KERN_ALERT PFX "Unknown flash/EEPROM type.\n");
3910 val = bnx2_shmem_rd(bp, BNX2_SHARED_HW_CFG_CONFIG2);
3911 val &= BNX2_SHARED_HW_CFG2_NVM_SIZE_MASK;
3913 bp->flash_size = val;
3915 bp->flash_size = bp->flash_info->total_size;
3921 bnx2_nvram_read(struct bnx2 *bp, u32 offset, u8 *ret_buf,
3925 u32 cmd_flags, offset32, len32, extra;
3930 /* Request access to the flash interface. */
3931 if ((rc = bnx2_acquire_nvram_lock(bp)) != 0)
3934 /* Enable access to flash interface */
3935 bnx2_enable_nvram_access(bp);
3948 pre_len = 4 - (offset & 3);
3950 if (pre_len >= len32) {
3952 cmd_flags = BNX2_NVM_COMMAND_FIRST |
3953 BNX2_NVM_COMMAND_LAST;
3956 cmd_flags = BNX2_NVM_COMMAND_FIRST;
3959 rc = bnx2_nvram_read_dword(bp, offset32, buf, cmd_flags);
3964 memcpy(ret_buf, buf + (offset & 3), pre_len);
3971 extra = 4 - (len32 & 3);
3972 len32 = (len32 + 4) & ~3;
3979 cmd_flags = BNX2_NVM_COMMAND_LAST;
3981 cmd_flags = BNX2_NVM_COMMAND_FIRST |
3982 BNX2_NVM_COMMAND_LAST;
3984 rc = bnx2_nvram_read_dword(bp, offset32, buf, cmd_flags);
3986 memcpy(ret_buf, buf, 4 - extra);
3988 else if (len32 > 0) {
3991 /* Read the first word. */
3995 cmd_flags = BNX2_NVM_COMMAND_FIRST;
3997 rc = bnx2_nvram_read_dword(bp, offset32, ret_buf, cmd_flags);
3999 /* Advance to the next dword. */
4004 while (len32 > 4 && rc == 0) {
4005 rc = bnx2_nvram_read_dword(bp, offset32, ret_buf, 0);
4007 /* Advance to the next dword. */
4016 cmd_flags = BNX2_NVM_COMMAND_LAST;
4017 rc = bnx2_nvram_read_dword(bp, offset32, buf, cmd_flags);
4019 memcpy(ret_buf, buf, 4 - extra);
4022 /* Disable access to flash interface */
4023 bnx2_disable_nvram_access(bp);
4025 bnx2_release_nvram_lock(bp);
4031 bnx2_nvram_write(struct bnx2 *bp, u32 offset, u8 *data_buf,
4034 u32 written, offset32, len32;
4035 u8 *buf, start[4], end[4], *align_buf = NULL, *flash_buffer = NULL;
4037 int align_start, align_end;
4042 align_start = align_end = 0;
4044 if ((align_start = (offset32 & 3))) {
4046 len32 += align_start;
4049 if ((rc = bnx2_nvram_read(bp, offset32, start, 4)))
4054 align_end = 4 - (len32 & 3);
4056 if ((rc = bnx2_nvram_read(bp, offset32 + len32 - 4, end, 4)))
4060 if (align_start || align_end) {
4061 align_buf = kmalloc(len32, GFP_KERNEL);
4062 if (align_buf == NULL)
4065 memcpy(align_buf, start, 4);
4068 memcpy(align_buf + len32 - 4, end, 4);
4070 memcpy(align_buf + align_start, data_buf, buf_size);
4074 if (!(bp->flash_info->flags & BNX2_NV_BUFFERED)) {
4075 flash_buffer = kmalloc(264, GFP_KERNEL);
4076 if (flash_buffer == NULL) {
4078 goto nvram_write_end;
4083 while ((written < len32) && (rc == 0)) {
4084 u32 page_start, page_end, data_start, data_end;
4085 u32 addr, cmd_flags;
4088 /* Find the page_start addr */
4089 page_start = offset32 + written;
4090 page_start -= (page_start % bp->flash_info->page_size);
4091 /* Find the page_end addr */
4092 page_end = page_start + bp->flash_info->page_size;
4093 /* Find the data_start addr */
4094 data_start = (written == 0) ? offset32 : page_start;
4095 /* Find the data_end addr */
4096 data_end = (page_end > offset32 + len32) ?
4097 (offset32 + len32) : page_end;
4099 /* Request access to the flash interface. */
4100 if ((rc = bnx2_acquire_nvram_lock(bp)) != 0)
4101 goto nvram_write_end;
4103 /* Enable access to flash interface */
4104 bnx2_enable_nvram_access(bp);
4106 cmd_flags = BNX2_NVM_COMMAND_FIRST;
4107 if (!(bp->flash_info->flags & BNX2_NV_BUFFERED)) {
4110 /* Read the whole page into the buffer
4111 * (non-buffer flash only) */
4112 for (j = 0; j < bp->flash_info->page_size; j += 4) {
4113 if (j == (bp->flash_info->page_size - 4)) {
4114 cmd_flags |= BNX2_NVM_COMMAND_LAST;
4116 rc = bnx2_nvram_read_dword(bp,
4122 goto nvram_write_end;
4128 /* Enable writes to flash interface (unlock write-protect) */
4129 if ((rc = bnx2_enable_nvram_write(bp)) != 0)
4130 goto nvram_write_end;
4132 /* Loop to write back the buffer data from page_start to
4135 if (!(bp->flash_info->flags & BNX2_NV_BUFFERED)) {
4136 /* Erase the page */
4137 if ((rc = bnx2_nvram_erase_page(bp, page_start)) != 0)
4138 goto nvram_write_end;
4140 /* Re-enable the write again for the actual write */
4141 bnx2_enable_nvram_write(bp);
4143 for (addr = page_start; addr < data_start;
4144 addr += 4, i += 4) {
4146 rc = bnx2_nvram_write_dword(bp, addr,
4147 &flash_buffer[i], cmd_flags);
4150 goto nvram_write_end;
4156 /* Loop to write the new data from data_start to data_end */
4157 for (addr = data_start; addr < data_end; addr += 4, i += 4) {
4158 if ((addr == page_end - 4) ||
4159 ((bp->flash_info->flags & BNX2_NV_BUFFERED) &&
4160 (addr == data_end - 4))) {
4162 cmd_flags |= BNX2_NVM_COMMAND_LAST;
4164 rc = bnx2_nvram_write_dword(bp, addr, buf,
4168 goto nvram_write_end;
4174 /* Loop to write back the buffer data from data_end
4176 if (!(bp->flash_info->flags & BNX2_NV_BUFFERED)) {
4177 for (addr = data_end; addr < page_end;
4178 addr += 4, i += 4) {
4180 if (addr == page_end-4) {
4181 cmd_flags = BNX2_NVM_COMMAND_LAST;
4183 rc = bnx2_nvram_write_dword(bp, addr,
4184 &flash_buffer[i], cmd_flags);
4187 goto nvram_write_end;
4193 /* Disable writes to flash interface (lock write-protect) */
4194 bnx2_disable_nvram_write(bp);
4196 /* Disable access to flash interface */
4197 bnx2_disable_nvram_access(bp);
4198 bnx2_release_nvram_lock(bp);
4200 /* Increment written */
4201 written += data_end - data_start;
4205 kfree(flash_buffer);
4211 bnx2_init_remote_phy(struct bnx2 *bp)
4215 bp->phy_flags &= ~BNX2_PHY_FLAG_REMOTE_PHY_CAP;
4216 if (!(bp->phy_flags & BNX2_PHY_FLAG_SERDES))
4219 val = bnx2_shmem_rd(bp, BNX2_FW_CAP_MB);
4220 if ((val & BNX2_FW_CAP_SIGNATURE_MASK) != BNX2_FW_CAP_SIGNATURE)
4223 if (val & BNX2_FW_CAP_REMOTE_PHY_CAPABLE) {
4224 bp->phy_flags |= BNX2_PHY_FLAG_REMOTE_PHY_CAP;
4226 val = bnx2_shmem_rd(bp, BNX2_LINK_STATUS);
4227 if (val & BNX2_LINK_STATUS_SERDES_LINK)
4228 bp->phy_port = PORT_FIBRE;
4230 bp->phy_port = PORT_TP;
4232 if (netif_running(bp->dev)) {
4235 sig = BNX2_DRV_ACK_CAP_SIGNATURE |
4236 BNX2_FW_CAP_REMOTE_PHY_CAPABLE;
4237 bnx2_shmem_wr(bp, BNX2_DRV_ACK_CAP_MB, sig);
4243 bnx2_setup_msix_tbl(struct bnx2 *bp)
4245 REG_WR(bp, BNX2_PCI_GRC_WINDOW_ADDR, BNX2_PCI_GRC_WINDOW_ADDR_SEP_WIN);
4247 REG_WR(bp, BNX2_PCI_GRC_WINDOW2_ADDR, BNX2_MSIX_TABLE_ADDR);
4248 REG_WR(bp, BNX2_PCI_GRC_WINDOW3_ADDR, BNX2_MSIX_PBA_ADDR);
4252 bnx2_reset_chip(struct bnx2 *bp, u32 reset_code)
4258 /* Wait for the current PCI transaction to complete before
4259 * issuing a reset. */
4260 REG_WR(bp, BNX2_MISC_ENABLE_CLR_BITS,
4261 BNX2_MISC_ENABLE_CLR_BITS_TX_DMA_ENABLE |
4262 BNX2_MISC_ENABLE_CLR_BITS_DMA_ENGINE_ENABLE |
4263 BNX2_MISC_ENABLE_CLR_BITS_RX_DMA_ENABLE |
4264 BNX2_MISC_ENABLE_CLR_BITS_HOST_COALESCE_ENABLE);
4265 val = REG_RD(bp, BNX2_MISC_ENABLE_CLR_BITS);
4268 /* Wait for the firmware to tell us it is ok to issue a reset. */
4269 bnx2_fw_sync(bp, BNX2_DRV_MSG_DATA_WAIT0 | reset_code, 1);
4271 /* Deposit a driver reset signature so the firmware knows that
4272 * this is a soft reset. */
4273 bnx2_shmem_wr(bp, BNX2_DRV_RESET_SIGNATURE,
4274 BNX2_DRV_RESET_SIGNATURE_MAGIC);
4276 /* Do a dummy read to force the chip to complete all current transaction
4277 * before we issue a reset. */
4278 val = REG_RD(bp, BNX2_MISC_ID);
4280 if (CHIP_NUM(bp) == CHIP_NUM_5709) {
4281 REG_WR(bp, BNX2_MISC_COMMAND, BNX2_MISC_COMMAND_SW_RESET);
4282 REG_RD(bp, BNX2_MISC_COMMAND);
4285 val = BNX2_PCICFG_MISC_CONFIG_REG_WINDOW_ENA |
4286 BNX2_PCICFG_MISC_CONFIG_TARGET_MB_WORD_SWAP;
4288 pci_write_config_dword(bp->pdev, BNX2_PCICFG_MISC_CONFIG, val);
4291 val = BNX2_PCICFG_MISC_CONFIG_CORE_RST_REQ |
4292 BNX2_PCICFG_MISC_CONFIG_REG_WINDOW_ENA |
4293 BNX2_PCICFG_MISC_CONFIG_TARGET_MB_WORD_SWAP;
4296 REG_WR(bp, BNX2_PCICFG_MISC_CONFIG, val);
4298 /* Reading back any register after chip reset will hang the
4299 * bus on 5706 A0 and A1. The msleep below provides plenty
4300 * of margin for write posting.
4302 if ((CHIP_ID(bp) == CHIP_ID_5706_A0) ||
4303 (CHIP_ID(bp) == CHIP_ID_5706_A1))
4306 /* Reset takes approximate 30 usec */
4307 for (i = 0; i < 10; i++) {
4308 val = REG_RD(bp, BNX2_PCICFG_MISC_CONFIG);
4309 if ((val & (BNX2_PCICFG_MISC_CONFIG_CORE_RST_REQ |
4310 BNX2_PCICFG_MISC_CONFIG_CORE_RST_BSY)) == 0)
4315 if (val & (BNX2_PCICFG_MISC_CONFIG_CORE_RST_REQ |
4316 BNX2_PCICFG_MISC_CONFIG_CORE_RST_BSY)) {
4317 printk(KERN_ERR PFX "Chip reset did not complete\n");
4322 /* Make sure byte swapping is properly configured. */
4323 val = REG_RD(bp, BNX2_PCI_SWAP_DIAG0);
4324 if (val != 0x01020304) {
4325 printk(KERN_ERR PFX "Chip not in correct endian mode\n");
4329 /* Wait for the firmware to finish its initialization. */
4330 rc = bnx2_fw_sync(bp, BNX2_DRV_MSG_DATA_WAIT1 | reset_code, 0);
4334 spin_lock_bh(&bp->phy_lock);
4335 old_port = bp->phy_port;
4336 bnx2_init_remote_phy(bp);
4337 if ((bp->phy_flags & BNX2_PHY_FLAG_REMOTE_PHY_CAP) &&
4338 old_port != bp->phy_port)
4339 bnx2_set_default_remote_link(bp);
4340 spin_unlock_bh(&bp->phy_lock);
4342 if (CHIP_ID(bp) == CHIP_ID_5706_A0) {
4343 /* Adjust the voltage regular to two steps lower. The default
4344 * of this register is 0x0000000e. */
4345 REG_WR(bp, BNX2_MISC_VREG_CONTROL, 0x000000fa);
4347 /* Remove bad rbuf memory from the free pool. */
4348 rc = bnx2_alloc_bad_rbuf(bp);
4351 if (bp->flags & BNX2_FLAG_USING_MSIX)
4352 bnx2_setup_msix_tbl(bp);
4358 bnx2_init_chip(struct bnx2 *bp)
4363 /* Make sure the interrupt is not active. */
4364 REG_WR(bp, BNX2_PCICFG_INT_ACK_CMD, BNX2_PCICFG_INT_ACK_CMD_MASK_INT);
4366 val = BNX2_DMA_CONFIG_DATA_BYTE_SWAP |
4367 BNX2_DMA_CONFIG_DATA_WORD_SWAP |
4369 BNX2_DMA_CONFIG_CNTL_BYTE_SWAP |
4371 BNX2_DMA_CONFIG_CNTL_WORD_SWAP |
4372 DMA_READ_CHANS << 12 |
4373 DMA_WRITE_CHANS << 16;
4375 val |= (0x2 << 20) | (1 << 11);
4377 if ((bp->flags & BNX2_FLAG_PCIX) && (bp->bus_speed_mhz == 133))
4380 if ((CHIP_NUM(bp) == CHIP_NUM_5706) &&
4381 (CHIP_ID(bp) != CHIP_ID_5706_A0) && !(bp->flags & BNX2_FLAG_PCIX))
4382 val |= BNX2_DMA_CONFIG_CNTL_PING_PONG_DMA;
4384 REG_WR(bp, BNX2_DMA_CONFIG, val);
4386 if (CHIP_ID(bp) == CHIP_ID_5706_A0) {
4387 val = REG_RD(bp, BNX2_TDMA_CONFIG);
4388 val |= BNX2_TDMA_CONFIG_ONE_DMA;
4389 REG_WR(bp, BNX2_TDMA_CONFIG, val);
4392 if (bp->flags & BNX2_FLAG_PCIX) {
4395 pci_read_config_word(bp->pdev, bp->pcix_cap + PCI_X_CMD,
4397 pci_write_config_word(bp->pdev, bp->pcix_cap + PCI_X_CMD,
4398 val16 & ~PCI_X_CMD_ERO);
4401 REG_WR(bp, BNX2_MISC_ENABLE_SET_BITS,
4402 BNX2_MISC_ENABLE_SET_BITS_HOST_COALESCE_ENABLE |
4403 BNX2_MISC_ENABLE_STATUS_BITS_RX_V2P_ENABLE |
4404 BNX2_MISC_ENABLE_STATUS_BITS_CONTEXT_ENABLE);
4406 /* Initialize context mapping and zero out the quick contexts. The
4407 * context block must have already been enabled. */
4408 if (CHIP_NUM(bp) == CHIP_NUM_5709) {
4409 rc = bnx2_init_5709_context(bp);
4413 bnx2_init_context(bp);
4415 if ((rc = bnx2_init_cpus(bp)) != 0)
4418 bnx2_init_nvram(bp);
4420 bnx2_set_mac_addr(bp);
4422 val = REG_RD(bp, BNX2_MQ_CONFIG);
4423 val &= ~BNX2_MQ_CONFIG_KNL_BYP_BLK_SIZE;
4424 val |= BNX2_MQ_CONFIG_KNL_BYP_BLK_SIZE_256;
4425 if (CHIP_ID(bp) == CHIP_ID_5709_A0 || CHIP_ID(bp) == CHIP_ID_5709_A1)
4426 val |= BNX2_MQ_CONFIG_HALT_DIS;
4428 REG_WR(bp, BNX2_MQ_CONFIG, val);
4430 val = 0x10000 + (MAX_CID_CNT * MB_KERNEL_CTX_SIZE);
4431 REG_WR(bp, BNX2_MQ_KNL_BYP_WIND_START, val);
4432 REG_WR(bp, BNX2_MQ_KNL_WIND_END, val);
4434 val = (BCM_PAGE_BITS - 8) << 24;
4435 REG_WR(bp, BNX2_RV2P_CONFIG, val);
4437 /* Configure page size. */
4438 val = REG_RD(bp, BNX2_TBDR_CONFIG);
4439 val &= ~BNX2_TBDR_CONFIG_PAGE_SIZE;
4440 val |= (BCM_PAGE_BITS - 8) << 24 | 0x40;
4441 REG_WR(bp, BNX2_TBDR_CONFIG, val);
4443 val = bp->mac_addr[0] +
4444 (bp->mac_addr[1] << 8) +
4445 (bp->mac_addr[2] << 16) +
4447 (bp->mac_addr[4] << 8) +
4448 (bp->mac_addr[5] << 16);
4449 REG_WR(bp, BNX2_EMAC_BACKOFF_SEED, val);
4451 /* Program the MTU. Also include 4 bytes for CRC32. */
4452 val = bp->dev->mtu + ETH_HLEN + 4;
4453 if (val > (MAX_ETHERNET_PACKET_SIZE + 4))
4454 val |= BNX2_EMAC_RX_MTU_SIZE_JUMBO_ENA;
4455 REG_WR(bp, BNX2_EMAC_RX_MTU_SIZE, val);
4457 for (i = 0; i < BNX2_MAX_MSIX_VEC; i++)
4458 bp->bnx2_napi[i].last_status_idx = 0;
4460 bp->rx_mode = BNX2_EMAC_RX_MODE_SORT_MODE;
4462 /* Set up how to generate a link change interrupt. */
4463 REG_WR(bp, BNX2_EMAC_ATTENTION_ENA, BNX2_EMAC_ATTENTION_ENA_LINK);
4465 REG_WR(bp, BNX2_HC_STATUS_ADDR_L,
4466 (u64) bp->status_blk_mapping & 0xffffffff);
4467 REG_WR(bp, BNX2_HC_STATUS_ADDR_H, (u64) bp->status_blk_mapping >> 32);
4469 REG_WR(bp, BNX2_HC_STATISTICS_ADDR_L,
4470 (u64) bp->stats_blk_mapping & 0xffffffff);
4471 REG_WR(bp, BNX2_HC_STATISTICS_ADDR_H,
4472 (u64) bp->stats_blk_mapping >> 32);
4474 REG_WR(bp, BNX2_HC_TX_QUICK_CONS_TRIP,
4475 (bp->tx_quick_cons_trip_int << 16) | bp->tx_quick_cons_trip);
4477 REG_WR(bp, BNX2_HC_RX_QUICK_CONS_TRIP,
4478 (bp->rx_quick_cons_trip_int << 16) | bp->rx_quick_cons_trip);
4480 REG_WR(bp, BNX2_HC_COMP_PROD_TRIP,
4481 (bp->comp_prod_trip_int << 16) | bp->comp_prod_trip);
4483 REG_WR(bp, BNX2_HC_TX_TICKS, (bp->tx_ticks_int << 16) | bp->tx_ticks);
4485 REG_WR(bp, BNX2_HC_RX_TICKS, (bp->rx_ticks_int << 16) | bp->rx_ticks);
4487 REG_WR(bp, BNX2_HC_COM_TICKS,
4488 (bp->com_ticks_int << 16) | bp->com_ticks);
4490 REG_WR(bp, BNX2_HC_CMD_TICKS,
4491 (bp->cmd_ticks_int << 16) | bp->cmd_ticks);
4493 if (CHIP_NUM(bp) == CHIP_NUM_5708)
4494 REG_WR(bp, BNX2_HC_STATS_TICKS, 0);
4496 REG_WR(bp, BNX2_HC_STATS_TICKS, bp->stats_ticks);
4497 REG_WR(bp, BNX2_HC_STAT_COLLECT_TICKS, 0xbb8); /* 3ms */
4499 if (CHIP_ID(bp) == CHIP_ID_5706_A1)
4500 val = BNX2_HC_CONFIG_COLLECT_STATS;
4502 val = BNX2_HC_CONFIG_RX_TMR_MODE | BNX2_HC_CONFIG_TX_TMR_MODE |
4503 BNX2_HC_CONFIG_COLLECT_STATS;
4506 if (bp->flags & BNX2_FLAG_USING_MSIX) {
4507 u32 base = ((BNX2_TX_VEC - 1) * BNX2_HC_SB_CONFIG_SIZE) +
4508 BNX2_HC_SB_CONFIG_1;
4510 REG_WR(bp, BNX2_HC_MSIX_BIT_VECTOR,
4511 BNX2_HC_MSIX_BIT_VECTOR_VAL);
4514 BNX2_HC_SB_CONFIG_1_TX_TMR_MODE |
4515 BNX2_HC_SB_CONFIG_1_ONE_SHOT);
4517 REG_WR(bp, base + BNX2_HC_TX_QUICK_CONS_TRIP_OFF,
4518 (bp->tx_quick_cons_trip_int << 16) |
4519 bp->tx_quick_cons_trip);
4521 REG_WR(bp, base + BNX2_HC_TX_TICKS_OFF,
4522 (bp->tx_ticks_int << 16) | bp->tx_ticks);
4524 val |= BNX2_HC_CONFIG_SB_ADDR_INC_128B;
4527 if (bp->flags & BNX2_FLAG_ONE_SHOT_MSI)
4528 val |= BNX2_HC_CONFIG_ONE_SHOT;
4530 REG_WR(bp, BNX2_HC_CONFIG, val);
4532 /* Clear internal stats counters. */
4533 REG_WR(bp, BNX2_HC_COMMAND, BNX2_HC_COMMAND_CLR_STAT_NOW);
4535 REG_WR(bp, BNX2_HC_ATTN_BITS_ENABLE, STATUS_ATTN_EVENTS);
4537 /* Initialize the receive filter. */
4538 bnx2_set_rx_mode(bp->dev);
4540 if (CHIP_NUM(bp) == CHIP_NUM_5709) {
4541 val = REG_RD(bp, BNX2_MISC_NEW_CORE_CTL);
4542 val |= BNX2_MISC_NEW_CORE_CTL_DMA_ENABLE;
4543 REG_WR(bp, BNX2_MISC_NEW_CORE_CTL, val);
4545 rc = bnx2_fw_sync(bp, BNX2_DRV_MSG_DATA_WAIT2 | BNX2_DRV_MSG_CODE_RESET,
4548 REG_WR(bp, BNX2_MISC_ENABLE_SET_BITS, BNX2_MISC_ENABLE_DEFAULT);
4549 REG_RD(bp, BNX2_MISC_ENABLE_SET_BITS);
4553 bp->hc_cmd = REG_RD(bp, BNX2_HC_COMMAND);
4559 bnx2_clear_ring_states(struct bnx2 *bp)
4561 struct bnx2_napi *bnapi;
4564 for (i = 0; i < BNX2_MAX_MSIX_VEC; i++) {
4565 bnapi = &bp->bnx2_napi[i];
4568 bnapi->hw_tx_cons = 0;
4569 bnapi->rx_prod_bseq = 0;
4572 bnapi->rx_pg_prod = 0;
4573 bnapi->rx_pg_cons = 0;
4578 bnx2_init_tx_context(struct bnx2 *bp, u32 cid)
4580 u32 val, offset0, offset1, offset2, offset3;
4581 u32 cid_addr = GET_CID_ADDR(cid);
4583 if (CHIP_NUM(bp) == CHIP_NUM_5709) {
4584 offset0 = BNX2_L2CTX_TYPE_XI;
4585 offset1 = BNX2_L2CTX_CMD_TYPE_XI;
4586 offset2 = BNX2_L2CTX_TBDR_BHADDR_HI_XI;
4587 offset3 = BNX2_L2CTX_TBDR_BHADDR_LO_XI;
4589 offset0 = BNX2_L2CTX_TYPE;
4590 offset1 = BNX2_L2CTX_CMD_TYPE;
4591 offset2 = BNX2_L2CTX_TBDR_BHADDR_HI;
4592 offset3 = BNX2_L2CTX_TBDR_BHADDR_LO;
4594 val = BNX2_L2CTX_TYPE_TYPE_L2 | BNX2_L2CTX_TYPE_SIZE_L2;
4595 bnx2_ctx_wr(bp, cid_addr, offset0, val);
4597 val = BNX2_L2CTX_CMD_TYPE_TYPE_L2 | (8 << 16);
4598 bnx2_ctx_wr(bp, cid_addr, offset1, val);
4600 val = (u64) bp->tx_desc_mapping >> 32;
4601 bnx2_ctx_wr(bp, cid_addr, offset2, val);
4603 val = (u64) bp->tx_desc_mapping & 0xffffffff;
4604 bnx2_ctx_wr(bp, cid_addr, offset3, val);
4608 bnx2_init_tx_ring(struct bnx2 *bp)
4612 struct bnx2_napi *bnapi;
4615 if (bp->flags & BNX2_FLAG_USING_MSIX) {
4617 bp->tx_vec = BNX2_TX_VEC;
4618 REG_WR(bp, BNX2_TSCH_TSS_CFG, BNX2_TX_INT_NUM |
4621 bnapi = &bp->bnx2_napi[bp->tx_vec];
4623 bp->tx_wake_thresh = bp->tx_ring_size / 2;
4625 txbd = &bp->tx_desc_ring[MAX_TX_DESC_CNT];
4627 txbd->tx_bd_haddr_hi = (u64) bp->tx_desc_mapping >> 32;
4628 txbd->tx_bd_haddr_lo = (u64) bp->tx_desc_mapping & 0xffffffff;
4631 bp->tx_prod_bseq = 0;
4633 bp->tx_bidx_addr = MB_GET_CID_ADDR(cid) + BNX2_L2CTX_TX_HOST_BIDX;
4634 bp->tx_bseq_addr = MB_GET_CID_ADDR(cid) + BNX2_L2CTX_TX_HOST_BSEQ;
4636 bnx2_init_tx_context(bp, cid);
4640 bnx2_init_rxbd_rings(struct rx_bd *rx_ring[], dma_addr_t dma[], u32 buf_size,
4646 for (i = 0; i < num_rings; i++) {
4649 rxbd = &rx_ring[i][0];
4650 for (j = 0; j < MAX_RX_DESC_CNT; j++, rxbd++) {
4651 rxbd->rx_bd_len = buf_size;
4652 rxbd->rx_bd_flags = RX_BD_FLAGS_START | RX_BD_FLAGS_END;
4654 if (i == (num_rings - 1))
4658 rxbd->rx_bd_haddr_hi = (u64) dma[j] >> 32;
4659 rxbd->rx_bd_haddr_lo = (u64) dma[j] & 0xffffffff;
4664 bnx2_init_rx_ring(struct bnx2 *bp)
4667 u16 prod, ring_prod;
4668 u32 val, rx_cid_addr = GET_CID_ADDR(RX_CID);
4669 struct bnx2_napi *bnapi = &bp->bnx2_napi[0];
4671 bnx2_init_rxbd_rings(bp->rx_desc_ring, bp->rx_desc_mapping,
4672 bp->rx_buf_use_size, bp->rx_max_ring);
4674 bnx2_init_rx_context0(bp);
4676 if (CHIP_NUM(bp) == CHIP_NUM_5709) {
4677 val = REG_RD(bp, BNX2_MQ_MAP_L2_5);
4678 REG_WR(bp, BNX2_MQ_MAP_L2_5, val | BNX2_MQ_MAP_L2_5_ARM);
4681 bnx2_ctx_wr(bp, rx_cid_addr, BNX2_L2CTX_PG_BUF_SIZE, 0);
4682 if (bp->rx_pg_ring_size) {
4683 bnx2_init_rxbd_rings(bp->rx_pg_desc_ring,
4684 bp->rx_pg_desc_mapping,
4685 PAGE_SIZE, bp->rx_max_pg_ring);
4686 val = (bp->rx_buf_use_size << 16) | PAGE_SIZE;
4687 bnx2_ctx_wr(bp, rx_cid_addr, BNX2_L2CTX_PG_BUF_SIZE, val);
4688 bnx2_ctx_wr(bp, rx_cid_addr, BNX2_L2CTX_RBDC_KEY,
4689 BNX2_L2CTX_RBDC_JUMBO_KEY);
4691 val = (u64) bp->rx_pg_desc_mapping[0] >> 32;
4692 bnx2_ctx_wr(bp, rx_cid_addr, BNX2_L2CTX_NX_PG_BDHADDR_HI, val);
4694 val = (u64) bp->rx_pg_desc_mapping[0] & 0xffffffff;
4695 bnx2_ctx_wr(bp, rx_cid_addr, BNX2_L2CTX_NX_PG_BDHADDR_LO, val);
4697 if (CHIP_NUM(bp) == CHIP_NUM_5709)
4698 REG_WR(bp, BNX2_MQ_MAP_L2_3, BNX2_MQ_MAP_L2_3_DEFAULT);
4701 val = (u64) bp->rx_desc_mapping[0] >> 32;
4702 bnx2_ctx_wr(bp, rx_cid_addr, BNX2_L2CTX_NX_BDHADDR_HI, val);
4704 val = (u64) bp->rx_desc_mapping[0] & 0xffffffff;
4705 bnx2_ctx_wr(bp, rx_cid_addr, BNX2_L2CTX_NX_BDHADDR_LO, val);
4707 ring_prod = prod = bnapi->rx_pg_prod;
4708 for (i = 0; i < bp->rx_pg_ring_size; i++) {
4709 if (bnx2_alloc_rx_page(bp, ring_prod) < 0)
4711 prod = NEXT_RX_BD(prod);
4712 ring_prod = RX_PG_RING_IDX(prod);
4714 bnapi->rx_pg_prod = prod;
4716 ring_prod = prod = bnapi->rx_prod;
4717 for (i = 0; i < bp->rx_ring_size; i++) {
4718 if (bnx2_alloc_rx_skb(bp, bnapi, ring_prod) < 0) {
4721 prod = NEXT_RX_BD(prod);
4722 ring_prod = RX_RING_IDX(prod);
4724 bnapi->rx_prod = prod;
4726 REG_WR16(bp, MB_RX_CID_ADDR + BNX2_L2CTX_HOST_PG_BDIDX,
4728 REG_WR16(bp, MB_RX_CID_ADDR + BNX2_L2CTX_HOST_BDIDX, prod);
4730 REG_WR(bp, MB_RX_CID_ADDR + BNX2_L2CTX_HOST_BSEQ, bnapi->rx_prod_bseq);
4733 static u32 bnx2_find_max_ring(u32 ring_size, u32 max_size)
4735 u32 max, num_rings = 1;
4737 while (ring_size > MAX_RX_DESC_CNT) {
4738 ring_size -= MAX_RX_DESC_CNT;
4741 /* round to next power of 2 */
4743 while ((max & num_rings) == 0)
4746 if (num_rings != max)
4753 bnx2_set_rx_ring_size(struct bnx2 *bp, u32 size)
4755 u32 rx_size, rx_space, jumbo_size;
4757 /* 8 for CRC and VLAN */
4758 rx_size = bp->dev->mtu + ETH_HLEN + BNX2_RX_OFFSET + 8;
4760 rx_space = SKB_DATA_ALIGN(rx_size + BNX2_RX_ALIGN) + NET_SKB_PAD +
4761 sizeof(struct skb_shared_info);
4763 bp->rx_copy_thresh = RX_COPY_THRESH;
4764 bp->rx_pg_ring_size = 0;
4765 bp->rx_max_pg_ring = 0;
4766 bp->rx_max_pg_ring_idx = 0;
4767 if ((rx_space > PAGE_SIZE) && !(bp->flags & BNX2_FLAG_JUMBO_BROKEN)) {
4768 int pages = PAGE_ALIGN(bp->dev->mtu - 40) >> PAGE_SHIFT;
4770 jumbo_size = size * pages;
4771 if (jumbo_size > MAX_TOTAL_RX_PG_DESC_CNT)
4772 jumbo_size = MAX_TOTAL_RX_PG_DESC_CNT;
4774 bp->rx_pg_ring_size = jumbo_size;
4775 bp->rx_max_pg_ring = bnx2_find_max_ring(jumbo_size,
4777 bp->rx_max_pg_ring_idx = (bp->rx_max_pg_ring * RX_DESC_CNT) - 1;
4778 rx_size = RX_COPY_THRESH + BNX2_RX_OFFSET;
4779 bp->rx_copy_thresh = 0;
4782 bp->rx_buf_use_size = rx_size;
4784 bp->rx_buf_size = bp->rx_buf_use_size + BNX2_RX_ALIGN;
4785 bp->rx_jumbo_thresh = rx_size - BNX2_RX_OFFSET;
4786 bp->rx_ring_size = size;
4787 bp->rx_max_ring = bnx2_find_max_ring(size, MAX_RX_RINGS);
4788 bp->rx_max_ring_idx = (bp->rx_max_ring * RX_DESC_CNT) - 1;
4792 bnx2_free_tx_skbs(struct bnx2 *bp)
4796 if (bp->tx_buf_ring == NULL)
4799 for (i = 0; i < TX_DESC_CNT; ) {
4800 struct sw_bd *tx_buf = &bp->tx_buf_ring[i];
4801 struct sk_buff *skb = tx_buf->skb;
4809 pci_unmap_single(bp->pdev, pci_unmap_addr(tx_buf, mapping),
4810 skb_headlen(skb), PCI_DMA_TODEVICE);
4814 last = skb_shinfo(skb)->nr_frags;
4815 for (j = 0; j < last; j++) {
4816 tx_buf = &bp->tx_buf_ring[i + j + 1];
4817 pci_unmap_page(bp->pdev,
4818 pci_unmap_addr(tx_buf, mapping),
4819 skb_shinfo(skb)->frags[j].size,
4829 bnx2_free_rx_skbs(struct bnx2 *bp)
4833 if (bp->rx_buf_ring == NULL)
4836 for (i = 0; i < bp->rx_max_ring_idx; i++) {
4837 struct sw_bd *rx_buf = &bp->rx_buf_ring[i];
4838 struct sk_buff *skb = rx_buf->skb;
4843 pci_unmap_single(bp->pdev, pci_unmap_addr(rx_buf, mapping),
4844 bp->rx_buf_use_size, PCI_DMA_FROMDEVICE);
4850 for (i = 0; i < bp->rx_max_pg_ring_idx; i++)
4851 bnx2_free_rx_page(bp, i);
4855 bnx2_free_skbs(struct bnx2 *bp)
4857 bnx2_free_tx_skbs(bp);
4858 bnx2_free_rx_skbs(bp);
4862 bnx2_reset_nic(struct bnx2 *bp, u32 reset_code)
4866 rc = bnx2_reset_chip(bp, reset_code);
4871 if ((rc = bnx2_init_chip(bp)) != 0)
4874 bnx2_clear_ring_states(bp);
4875 bnx2_init_tx_ring(bp);
4876 bnx2_init_rx_ring(bp);
4881 bnx2_init_nic(struct bnx2 *bp, int reset_phy)
4885 if ((rc = bnx2_reset_nic(bp, BNX2_DRV_MSG_CODE_RESET)) != 0)
4888 spin_lock_bh(&bp->phy_lock);
4889 bnx2_init_phy(bp, reset_phy);
4891 if (bp->phy_flags & BNX2_PHY_FLAG_REMOTE_PHY_CAP)
4892 bnx2_remote_phy_event(bp);
4893 spin_unlock_bh(&bp->phy_lock);
4898 bnx2_test_registers(struct bnx2 *bp)
4902 static const struct {
4905 #define BNX2_FL_NOT_5709 1
4909 { 0x006c, 0, 0x00000000, 0x0000003f },
4910 { 0x0090, 0, 0xffffffff, 0x00000000 },
4911 { 0x0094, 0, 0x00000000, 0x00000000 },
4913 { 0x0404, BNX2_FL_NOT_5709, 0x00003f00, 0x00000000 },
4914 { 0x0418, BNX2_FL_NOT_5709, 0x00000000, 0xffffffff },
4915 { 0x041c, BNX2_FL_NOT_5709, 0x00000000, 0xffffffff },
4916 { 0x0420, BNX2_FL_NOT_5709, 0x00000000, 0x80ffffff },
4917 { 0x0424, BNX2_FL_NOT_5709, 0x00000000, 0x00000000 },
4918 { 0x0428, BNX2_FL_NOT_5709, 0x00000000, 0x00000001 },
4919 { 0x0450, BNX2_FL_NOT_5709, 0x00000000, 0x0000ffff },
4920 { 0x0454, BNX2_FL_NOT_5709, 0x00000000, 0xffffffff },
4921 { 0x0458, BNX2_FL_NOT_5709, 0x00000000, 0xffffffff },
4923 { 0x0808, BNX2_FL_NOT_5709, 0x00000000, 0xffffffff },
4924 { 0x0854, BNX2_FL_NOT_5709, 0x00000000, 0xffffffff },
4925 { 0x0868, BNX2_FL_NOT_5709, 0x00000000, 0x77777777 },
4926 { 0x086c, BNX2_FL_NOT_5709, 0x00000000, 0x77777777 },
4927 { 0x0870, BNX2_FL_NOT_5709, 0x00000000, 0x77777777 },
4928 { 0x0874, BNX2_FL_NOT_5709, 0x00000000, 0x77777777 },
4930 { 0x0c00, BNX2_FL_NOT_5709, 0x00000000, 0x00000001 },
4931 { 0x0c04, BNX2_FL_NOT_5709, 0x00000000, 0x03ff0001 },
4932 { 0x0c08, BNX2_FL_NOT_5709, 0x0f0ff073, 0x00000000 },
4934 { 0x1000, 0, 0x00000000, 0x00000001 },
4935 { 0x1004, BNX2_FL_NOT_5709, 0x00000000, 0x000f0001 },
4937 { 0x1408, 0, 0x01c00800, 0x00000000 },
4938 { 0x149c, 0, 0x8000ffff, 0x00000000 },
4939 { 0x14a8, 0, 0x00000000, 0x000001ff },
4940 { 0x14ac, 0, 0x0fffffff, 0x10000000 },
4941 { 0x14b0, 0, 0x00000002, 0x00000001 },
4942 { 0x14b8, 0, 0x00000000, 0x00000000 },
4943 { 0x14c0, 0, 0x00000000, 0x00000009 },
4944 { 0x14c4, 0, 0x00003fff, 0x00000000 },
4945 { 0x14cc, 0, 0x00000000, 0x00000001 },
4946 { 0x14d0, 0, 0xffffffff, 0x00000000 },
4948 { 0x1800, 0, 0x00000000, 0x00000001 },
4949 { 0x1804, 0, 0x00000000, 0x00000003 },
4951 { 0x2800, 0, 0x00000000, 0x00000001 },
4952 { 0x2804, 0, 0x00000000, 0x00003f01 },
4953 { 0x2808, 0, 0x0f3f3f03, 0x00000000 },
4954 { 0x2810, 0, 0xffff0000, 0x00000000 },
4955 { 0x2814, 0, 0xffff0000, 0x00000000 },
4956 { 0x2818, 0, 0xffff0000, 0x00000000 },
4957 { 0x281c, 0, 0xffff0000, 0x00000000 },
4958 { 0x2834, 0, 0xffffffff, 0x00000000 },
4959 { 0x2840, 0, 0x00000000, 0xffffffff },
4960 { 0x2844, 0, 0x00000000, 0xffffffff },
4961 { 0x2848, 0, 0xffffffff, 0x00000000 },
4962 { 0x284c, 0, 0xf800f800, 0x07ff07ff },
4964 { 0x2c00, 0, 0x00000000, 0x00000011 },
4965 { 0x2c04, 0, 0x00000000, 0x00030007 },
4967 { 0x3c00, 0, 0x00000000, 0x00000001 },
4968 { 0x3c04, 0, 0x00000000, 0x00070000 },
4969 { 0x3c08, 0, 0x00007f71, 0x07f00000 },
4970 { 0x3c0c, 0, 0x1f3ffffc, 0x00000000 },
4971 { 0x3c10, 0, 0xffffffff, 0x00000000 },
4972 { 0x3c14, 0, 0x00000000, 0xffffffff },
4973 { 0x3c18, 0, 0x00000000, 0xffffffff },
4974 { 0x3c1c, 0, 0xfffff000, 0x00000000 },
4975 { 0x3c20, 0, 0xffffff00, 0x00000000 },
4977 { 0x5004, 0, 0x00000000, 0x0000007f },
4978 { 0x5008, 0, 0x0f0007ff, 0x00000000 },
4980 { 0x5c00, 0, 0x00000000, 0x00000001 },
4981 { 0x5c04, 0, 0x00000000, 0x0003000f },
4982 { 0x5c08, 0, 0x00000003, 0x00000000 },
4983 { 0x5c0c, 0, 0x0000fff8, 0x00000000 },
4984 { 0x5c10, 0, 0x00000000, 0xffffffff },
4985 { 0x5c80, 0, 0x00000000, 0x0f7113f1 },
4986 { 0x5c84, 0, 0x00000000, 0x0000f333 },
4987 { 0x5c88, 0, 0x00000000, 0x00077373 },
4988 { 0x5c8c, 0, 0x00000000, 0x0007f737 },
4990 { 0x6808, 0, 0x0000ff7f, 0x00000000 },
4991 { 0x680c, 0, 0xffffffff, 0x00000000 },
4992 { 0x6810, 0, 0xffffffff, 0x00000000 },
4993 { 0x6814, 0, 0xffffffff, 0x00000000 },
4994 { 0x6818, 0, 0xffffffff, 0x00000000 },
4995 { 0x681c, 0, 0xffffffff, 0x00000000 },
4996 { 0x6820, 0, 0x00ff00ff, 0x00000000 },
4997 { 0x6824, 0, 0x00ff00ff, 0x00000000 },
4998 { 0x6828, 0, 0x00ff00ff, 0x00000000 },
4999 { 0x682c, 0, 0x03ff03ff, 0x00000000 },
5000 { 0x6830, 0, 0x03ff03ff, 0x00000000 },
5001 { 0x6834, 0, 0x03ff03ff, 0x00000000 },
5002 { 0x6838, 0, 0x03ff03ff, 0x00000000 },
5003 { 0x683c, 0, 0x0000ffff, 0x00000000 },
5004 { 0x6840, 0, 0x00000ff0, 0x00000000 },
5005 { 0x6844, 0, 0x00ffff00, 0x00000000 },
5006 { 0x684c, 0, 0xffffffff, 0x00000000 },
5007 { 0x6850, 0, 0x7f7f7f7f, 0x00000000 },
5008 { 0x6854, 0, 0x7f7f7f7f, 0x00000000 },
5009 { 0x6858, 0, 0x7f7f7f7f, 0x00000000 },
5010 { 0x685c, 0, 0x7f7f7f7f, 0x00000000 },
5011 { 0x6908, 0, 0x00000000, 0x0001ff0f },
5012 { 0x690c, 0, 0x00000000, 0x0ffe00f0 },
5014 { 0xffff, 0, 0x00000000, 0x00000000 },
5019 if (CHIP_NUM(bp) == CHIP_NUM_5709)
5022 for (i = 0; reg_tbl[i].offset != 0xffff; i++) {
5023 u32 offset, rw_mask, ro_mask, save_val, val;
5024 u16 flags = reg_tbl[i].flags;
5026 if (is_5709 && (flags & BNX2_FL_NOT_5709))
5029 offset = (u32) reg_tbl[i].offset;
5030 rw_mask = reg_tbl[i].rw_mask;
5031 ro_mask = reg_tbl[i].ro_mask;
5033 save_val = readl(bp->regview + offset);
5035 writel(0, bp->regview + offset);
5037 val = readl(bp->regview + offset);
5038 if ((val & rw_mask) != 0) {
5042 if ((val & ro_mask) != (save_val & ro_mask)) {
5046 writel(0xffffffff, bp->regview + offset);
5048 val = readl(bp->regview + offset);
5049 if ((val & rw_mask) != rw_mask) {
5053 if ((val & ro_mask) != (save_val & ro_mask)) {
5057 writel(save_val, bp->regview + offset);
5061 writel(save_val, bp->regview + offset);
5069 bnx2_do_mem_test(struct bnx2 *bp, u32 start, u32 size)
5071 static const u32 test_pattern[] = { 0x00000000, 0xffffffff, 0x55555555,
5072 0xaaaaaaaa , 0xaa55aa55, 0x55aa55aa };
5075 for (i = 0; i < sizeof(test_pattern) / 4; i++) {
5078 for (offset = 0; offset < size; offset += 4) {
5080 bnx2_reg_wr_ind(bp, start + offset, test_pattern[i]);
5082 if (bnx2_reg_rd_ind(bp, start + offset) !=
5092 bnx2_test_memory(struct bnx2 *bp)
5096 static struct mem_entry {
5099 } mem_tbl_5706[] = {
5100 { 0x60000, 0x4000 },
5101 { 0xa0000, 0x3000 },
5102 { 0xe0000, 0x4000 },
5103 { 0x120000, 0x4000 },
5104 { 0x1a0000, 0x4000 },
5105 { 0x160000, 0x4000 },
5109 { 0x60000, 0x4000 },
5110 { 0xa0000, 0x3000 },
5111 { 0xe0000, 0x4000 },
5112 { 0x120000, 0x4000 },
5113 { 0x1a0000, 0x4000 },
5116 struct mem_entry *mem_tbl;
5118 if (CHIP_NUM(bp) == CHIP_NUM_5709)
5119 mem_tbl = mem_tbl_5709;
5121 mem_tbl = mem_tbl_5706;
5123 for (i = 0; mem_tbl[i].offset != 0xffffffff; i++) {
5124 if ((ret = bnx2_do_mem_test(bp, mem_tbl[i].offset,
5125 mem_tbl[i].len)) != 0) {
5133 #define BNX2_MAC_LOOPBACK 0
5134 #define BNX2_PHY_LOOPBACK 1
5137 bnx2_run_loopback(struct bnx2 *bp, int loopback_mode)
5139 unsigned int pkt_size, num_pkts, i;
5140 struct sk_buff *skb, *rx_skb;
5141 unsigned char *packet;
5142 u16 rx_start_idx, rx_idx;
5145 struct sw_bd *rx_buf;
5146 struct l2_fhdr *rx_hdr;
5148 struct bnx2_napi *bnapi = &bp->bnx2_napi[0], *tx_napi;
5151 if (bp->flags & BNX2_FLAG_USING_MSIX)
5152 tx_napi = &bp->bnx2_napi[BNX2_TX_VEC];
5154 if (loopback_mode == BNX2_MAC_LOOPBACK) {
5155 bp->loopback = MAC_LOOPBACK;
5156 bnx2_set_mac_loopback(bp);
5158 else if (loopback_mode == BNX2_PHY_LOOPBACK) {
5159 if (bp->phy_flags & BNX2_PHY_FLAG_REMOTE_PHY_CAP)
5162 bp->loopback = PHY_LOOPBACK;
5163 bnx2_set_phy_loopback(bp);
5168 pkt_size = min(bp->dev->mtu + ETH_HLEN, bp->rx_jumbo_thresh - 4);
5169 skb = netdev_alloc_skb(bp->dev, pkt_size);
5172 packet = skb_put(skb, pkt_size);
5173 memcpy(packet, bp->dev->dev_addr, 6);
5174 memset(packet + 6, 0x0, 8);
5175 for (i = 14; i < pkt_size; i++)
5176 packet[i] = (unsigned char) (i & 0xff);
5178 map = pci_map_single(bp->pdev, skb->data, pkt_size,
5181 REG_WR(bp, BNX2_HC_COMMAND,
5182 bp->hc_cmd | BNX2_HC_COMMAND_COAL_NOW_WO_INT);
5184 REG_RD(bp, BNX2_HC_COMMAND);
5187 rx_start_idx = bnx2_get_hw_rx_cons(bnapi);
5191 txbd = &bp->tx_desc_ring[TX_RING_IDX(bp->tx_prod)];
5193 txbd->tx_bd_haddr_hi = (u64) map >> 32;
5194 txbd->tx_bd_haddr_lo = (u64) map & 0xffffffff;
5195 txbd->tx_bd_mss_nbytes = pkt_size;
5196 txbd->tx_bd_vlan_tag_flags = TX_BD_FLAGS_START | TX_BD_FLAGS_END;
5199 bp->tx_prod = NEXT_TX_BD(bp->tx_prod);
5200 bp->tx_prod_bseq += pkt_size;
5202 REG_WR16(bp, bp->tx_bidx_addr, bp->tx_prod);
5203 REG_WR(bp, bp->tx_bseq_addr, bp->tx_prod_bseq);
5207 REG_WR(bp, BNX2_HC_COMMAND,
5208 bp->hc_cmd | BNX2_HC_COMMAND_COAL_NOW_WO_INT);
5210 REG_RD(bp, BNX2_HC_COMMAND);
5214 pci_unmap_single(bp->pdev, map, pkt_size, PCI_DMA_TODEVICE);
5217 if (bnx2_get_hw_tx_cons(tx_napi) != bp->tx_prod)
5218 goto loopback_test_done;
5220 rx_idx = bnx2_get_hw_rx_cons(bnapi);
5221 if (rx_idx != rx_start_idx + num_pkts) {
5222 goto loopback_test_done;
5225 rx_buf = &bp->rx_buf_ring[rx_start_idx];
5226 rx_skb = rx_buf->skb;
5228 rx_hdr = (struct l2_fhdr *) rx_skb->data;
5229 skb_reserve(rx_skb, BNX2_RX_OFFSET);
5231 pci_dma_sync_single_for_cpu(bp->pdev,
5232 pci_unmap_addr(rx_buf, mapping),
5233 bp->rx_buf_size, PCI_DMA_FROMDEVICE);
5235 if (rx_hdr->l2_fhdr_status &
5236 (L2_FHDR_ERRORS_BAD_CRC |
5237 L2_FHDR_ERRORS_PHY_DECODE |
5238 L2_FHDR_ERRORS_ALIGNMENT |
5239 L2_FHDR_ERRORS_TOO_SHORT |
5240 L2_FHDR_ERRORS_GIANT_FRAME)) {
5242 goto loopback_test_done;
5245 if ((rx_hdr->l2_fhdr_pkt_len - 4) != pkt_size) {
5246 goto loopback_test_done;
5249 for (i = 14; i < pkt_size; i++) {
5250 if (*(rx_skb->data + i) != (unsigned char) (i & 0xff)) {
5251 goto loopback_test_done;
5262 #define BNX2_MAC_LOOPBACK_FAILED 1
5263 #define BNX2_PHY_LOOPBACK_FAILED 2
5264 #define BNX2_LOOPBACK_FAILED (BNX2_MAC_LOOPBACK_FAILED | \
5265 BNX2_PHY_LOOPBACK_FAILED)
5268 bnx2_test_loopback(struct bnx2 *bp)
5272 if (!netif_running(bp->dev))
5273 return BNX2_LOOPBACK_FAILED;
5275 bnx2_reset_nic(bp, BNX2_DRV_MSG_CODE_RESET);
5276 spin_lock_bh(&bp->phy_lock);
5277 bnx2_init_phy(bp, 1);
5278 spin_unlock_bh(&bp->phy_lock);
5279 if (bnx2_run_loopback(bp, BNX2_MAC_LOOPBACK))
5280 rc |= BNX2_MAC_LOOPBACK_FAILED;
5281 if (bnx2_run_loopback(bp, BNX2_PHY_LOOPBACK))
5282 rc |= BNX2_PHY_LOOPBACK_FAILED;
5286 #define NVRAM_SIZE 0x200
5287 #define CRC32_RESIDUAL 0xdebb20e3
5290 bnx2_test_nvram(struct bnx2 *bp)
5292 __be32 buf[NVRAM_SIZE / 4];
5293 u8 *data = (u8 *) buf;
5297 if ((rc = bnx2_nvram_read(bp, 0, data, 4)) != 0)
5298 goto test_nvram_done;
5300 magic = be32_to_cpu(buf[0]);
5301 if (magic != 0x669955aa) {
5303 goto test_nvram_done;
5306 if ((rc = bnx2_nvram_read(bp, 0x100, data, NVRAM_SIZE)) != 0)
5307 goto test_nvram_done;
5309 csum = ether_crc_le(0x100, data);
5310 if (csum != CRC32_RESIDUAL) {
5312 goto test_nvram_done;
5315 csum = ether_crc_le(0x100, data + 0x100);
5316 if (csum != CRC32_RESIDUAL) {
5325 bnx2_test_link(struct bnx2 *bp)
5329 if (bp->phy_flags & BNX2_PHY_FLAG_REMOTE_PHY_CAP) {
5334 spin_lock_bh(&bp->phy_lock);
5335 bnx2_enable_bmsr1(bp);
5336 bnx2_read_phy(bp, bp->mii_bmsr1, &bmsr);
5337 bnx2_read_phy(bp, bp->mii_bmsr1, &bmsr);
5338 bnx2_disable_bmsr1(bp);
5339 spin_unlock_bh(&bp->phy_lock);
5341 if (bmsr & BMSR_LSTATUS) {
5348 bnx2_test_intr(struct bnx2 *bp)
5353 if (!netif_running(bp->dev))
5356 status_idx = REG_RD(bp, BNX2_PCICFG_INT_ACK_CMD) & 0xffff;
5358 /* This register is not touched during run-time. */
5359 REG_WR(bp, BNX2_HC_COMMAND, bp->hc_cmd | BNX2_HC_COMMAND_COAL_NOW);
5360 REG_RD(bp, BNX2_HC_COMMAND);
5362 for (i = 0; i < 10; i++) {
5363 if ((REG_RD(bp, BNX2_PCICFG_INT_ACK_CMD) & 0xffff) !=
5369 msleep_interruptible(10);
5377 /* Determining link for parallel detection. */
5379 bnx2_5706_serdes_has_link(struct bnx2 *bp)
5381 u32 mode_ctl, an_dbg, exp;
5383 if (bp->phy_flags & BNX2_PHY_FLAG_NO_PARALLEL)
5386 bnx2_write_phy(bp, MII_BNX2_MISC_SHADOW, MISC_SHDW_MODE_CTL);
5387 bnx2_read_phy(bp, MII_BNX2_MISC_SHADOW, &mode_ctl);
5389 if (!(mode_ctl & MISC_SHDW_MODE_CTL_SIG_DET))
5392 bnx2_write_phy(bp, MII_BNX2_MISC_SHADOW, MISC_SHDW_AN_DBG);
5393 bnx2_read_phy(bp, MII_BNX2_MISC_SHADOW, &an_dbg);
5394 bnx2_read_phy(bp, MII_BNX2_MISC_SHADOW, &an_dbg);
5396 if (an_dbg & (MISC_SHDW_AN_DBG_NOSYNC | MISC_SHDW_AN_DBG_RUDI_INVALID))
5399 bnx2_write_phy(bp, MII_BNX2_DSP_ADDRESS, MII_EXPAND_REG1);
5400 bnx2_read_phy(bp, MII_BNX2_DSP_RW_PORT, &exp);
5401 bnx2_read_phy(bp, MII_BNX2_DSP_RW_PORT, &exp);
5403 if (exp & MII_EXPAND_REG1_RUDI_C) /* receiving CONFIG */
5410 bnx2_5706_serdes_timer(struct bnx2 *bp)
5414 spin_lock(&bp->phy_lock);
5415 if (bp->serdes_an_pending) {
5416 bp->serdes_an_pending--;
5418 } else if ((bp->link_up == 0) && (bp->autoneg & AUTONEG_SPEED)) {
5421 bp->current_interval = bp->timer_interval;
5423 bnx2_read_phy(bp, bp->mii_bmcr, &bmcr);
5425 if (bmcr & BMCR_ANENABLE) {
5426 if (bnx2_5706_serdes_has_link(bp)) {
5427 bmcr &= ~BMCR_ANENABLE;
5428 bmcr |= BMCR_SPEED1000 | BMCR_FULLDPLX;
5429 bnx2_write_phy(bp, bp->mii_bmcr, bmcr);
5430 bp->phy_flags |= BNX2_PHY_FLAG_PARALLEL_DETECT;
5434 else if ((bp->link_up) && (bp->autoneg & AUTONEG_SPEED) &&
5435 (bp->phy_flags & BNX2_PHY_FLAG_PARALLEL_DETECT)) {
5438 bnx2_write_phy(bp, 0x17, 0x0f01);
5439 bnx2_read_phy(bp, 0x15, &phy2);
5443 bnx2_read_phy(bp, bp->mii_bmcr, &bmcr);
5444 bmcr |= BMCR_ANENABLE;
5445 bnx2_write_phy(bp, bp->mii_bmcr, bmcr);
5447 bp->phy_flags &= ~BNX2_PHY_FLAG_PARALLEL_DETECT;
5450 bp->current_interval = bp->timer_interval;
5455 bnx2_write_phy(bp, MII_BNX2_MISC_SHADOW, MISC_SHDW_AN_DBG);
5456 bnx2_read_phy(bp, MII_BNX2_MISC_SHADOW, &val);
5457 bnx2_read_phy(bp, MII_BNX2_MISC_SHADOW, &val);
5459 if (bp->link_up && (val & MISC_SHDW_AN_DBG_NOSYNC)) {
5460 if (!(bp->phy_flags & BNX2_PHY_FLAG_FORCED_DOWN)) {
5461 bnx2_5706s_force_link_dn(bp, 1);
5462 bp->phy_flags |= BNX2_PHY_FLAG_FORCED_DOWN;
5465 } else if (!bp->link_up && !(val & MISC_SHDW_AN_DBG_NOSYNC))
5468 spin_unlock(&bp->phy_lock);
5472 bnx2_5708_serdes_timer(struct bnx2 *bp)
5474 if (bp->phy_flags & BNX2_PHY_FLAG_REMOTE_PHY_CAP)
5477 if ((bp->phy_flags & BNX2_PHY_FLAG_2_5G_CAPABLE) == 0) {
5478 bp->serdes_an_pending = 0;
5482 spin_lock(&bp->phy_lock);
5483 if (bp->serdes_an_pending)
5484 bp->serdes_an_pending--;
5485 else if ((bp->link_up == 0) && (bp->autoneg & AUTONEG_SPEED)) {
5488 bnx2_read_phy(bp, bp->mii_bmcr, &bmcr);
5489 if (bmcr & BMCR_ANENABLE) {
5490 bnx2_enable_forced_2g5(bp);
5491 bp->current_interval = SERDES_FORCED_TIMEOUT;
5493 bnx2_disable_forced_2g5(bp);
5494 bp->serdes_an_pending = 2;
5495 bp->current_interval = bp->timer_interval;
5499 bp->current_interval = bp->timer_interval;
5501 spin_unlock(&bp->phy_lock);
5505 bnx2_timer(unsigned long data)
5507 struct bnx2 *bp = (struct bnx2 *) data;
5509 if (!netif_running(bp->dev))
5512 if (atomic_read(&bp->intr_sem) != 0)
5513 goto bnx2_restart_timer;
5515 bnx2_send_heart_beat(bp);
5517 bp->stats_blk->stat_FwRxDrop =
5518 bnx2_reg_rd_ind(bp, BNX2_FW_RX_DROP_COUNT);
5520 /* workaround occasional corrupted counters */
5521 if (CHIP_NUM(bp) == CHIP_NUM_5708 && bp->stats_ticks)
5522 REG_WR(bp, BNX2_HC_COMMAND, bp->hc_cmd |
5523 BNX2_HC_COMMAND_STATS_NOW);
5525 if (bp->phy_flags & BNX2_PHY_FLAG_SERDES) {
5526 if (CHIP_NUM(bp) == CHIP_NUM_5706)
5527 bnx2_5706_serdes_timer(bp);
5529 bnx2_5708_serdes_timer(bp);
5533 mod_timer(&bp->timer, jiffies + bp->current_interval);
5537 bnx2_request_irq(struct bnx2 *bp)
5539 struct net_device *dev = bp->dev;
5540 unsigned long flags;
5541 struct bnx2_irq *irq;
5544 if (bp->flags & BNX2_FLAG_USING_MSI_OR_MSIX)
5547 flags = IRQF_SHARED;
5549 for (i = 0; i < bp->irq_nvecs; i++) {
5550 irq = &bp->irq_tbl[i];
5551 rc = request_irq(irq->vector, irq->handler, flags, irq->name,
5561 bnx2_free_irq(struct bnx2 *bp)
5563 struct net_device *dev = bp->dev;
5564 struct bnx2_irq *irq;
5567 for (i = 0; i < bp->irq_nvecs; i++) {
5568 irq = &bp->irq_tbl[i];
5570 free_irq(irq->vector, dev);
5573 if (bp->flags & BNX2_FLAG_USING_MSI)
5574 pci_disable_msi(bp->pdev);
5575 else if (bp->flags & BNX2_FLAG_USING_MSIX)
5576 pci_disable_msix(bp->pdev);
5578 bp->flags &= ~(BNX2_FLAG_USING_MSI_OR_MSIX | BNX2_FLAG_ONE_SHOT_MSI);
5582 bnx2_enable_msix(struct bnx2 *bp)
5585 struct msix_entry msix_ent[BNX2_MAX_MSIX_VEC];
5587 bnx2_setup_msix_tbl(bp);
5588 REG_WR(bp, BNX2_PCI_MSIX_CONTROL, BNX2_MAX_MSIX_HW_VEC - 1);
5589 REG_WR(bp, BNX2_PCI_MSIX_TBL_OFF_BIR, BNX2_PCI_GRC_WINDOW2_BASE);
5590 REG_WR(bp, BNX2_PCI_MSIX_PBA_OFF_BIT, BNX2_PCI_GRC_WINDOW3_BASE);
5592 for (i = 0; i < BNX2_MAX_MSIX_VEC; i++) {
5593 msix_ent[i].entry = i;
5594 msix_ent[i].vector = 0;
5597 rc = pci_enable_msix(bp->pdev, msix_ent, BNX2_MAX_MSIX_VEC);
5601 bp->irq_tbl[BNX2_BASE_VEC].handler = bnx2_msi_1shot;
5602 bp->irq_tbl[BNX2_TX_VEC].handler = bnx2_tx_msix;
5604 strcpy(bp->irq_tbl[BNX2_BASE_VEC].name, bp->dev->name);
5605 strcat(bp->irq_tbl[BNX2_BASE_VEC].name, "-base");
5606 strcpy(bp->irq_tbl[BNX2_TX_VEC].name, bp->dev->name);
5607 strcat(bp->irq_tbl[BNX2_TX_VEC].name, "-tx");
5609 bp->irq_nvecs = BNX2_MAX_MSIX_VEC;
5610 bp->flags |= BNX2_FLAG_USING_MSIX | BNX2_FLAG_ONE_SHOT_MSI;
5611 for (i = 0; i < BNX2_MAX_MSIX_VEC; i++)
5612 bp->irq_tbl[i].vector = msix_ent[i].vector;
5616 bnx2_setup_int_mode(struct bnx2 *bp, int dis_msi)
5618 bp->irq_tbl[0].handler = bnx2_interrupt;
5619 strcpy(bp->irq_tbl[0].name, bp->dev->name);
5621 bp->irq_tbl[0].vector = bp->pdev->irq;
5623 if ((bp->flags & BNX2_FLAG_MSIX_CAP) && !dis_msi)
5624 bnx2_enable_msix(bp);
5626 if ((bp->flags & BNX2_FLAG_MSI_CAP) && !dis_msi &&
5627 !(bp->flags & BNX2_FLAG_USING_MSIX)) {
5628 if (pci_enable_msi(bp->pdev) == 0) {
5629 bp->flags |= BNX2_FLAG_USING_MSI;
5630 if (CHIP_NUM(bp) == CHIP_NUM_5709) {
5631 bp->flags |= BNX2_FLAG_ONE_SHOT_MSI;
5632 bp->irq_tbl[0].handler = bnx2_msi_1shot;
5634 bp->irq_tbl[0].handler = bnx2_msi;
5636 bp->irq_tbl[0].vector = bp->pdev->irq;
5641 /* Called with rtnl_lock */
5643 bnx2_open(struct net_device *dev)
5645 struct bnx2 *bp = netdev_priv(dev);
5648 netif_carrier_off(dev);
5650 bnx2_set_power_state(bp, PCI_D0);
5651 bnx2_disable_int(bp);
5653 rc = bnx2_alloc_mem(bp);
5657 bnx2_setup_int_mode(bp, disable_msi);
5658 bnx2_napi_enable(bp);
5659 rc = bnx2_request_irq(bp);
5662 bnx2_napi_disable(bp);
5667 rc = bnx2_init_nic(bp, 1);
5670 bnx2_napi_disable(bp);
5677 mod_timer(&bp->timer, jiffies + bp->current_interval);
5679 atomic_set(&bp->intr_sem, 0);
5681 bnx2_enable_int(bp);
5683 if (bp->flags & BNX2_FLAG_USING_MSI) {
5684 /* Test MSI to make sure it is working
5685 * If MSI test fails, go back to INTx mode
5687 if (bnx2_test_intr(bp) != 0) {
5688 printk(KERN_WARNING PFX "%s: No interrupt was generated"
5689 " using MSI, switching to INTx mode. Please"
5690 " report this failure to the PCI maintainer"
5691 " and include system chipset information.\n",
5694 bnx2_disable_int(bp);
5697 bnx2_setup_int_mode(bp, 1);
5699 rc = bnx2_init_nic(bp, 0);
5702 rc = bnx2_request_irq(bp);
5705 bnx2_napi_disable(bp);
5708 del_timer_sync(&bp->timer);
5711 bnx2_enable_int(bp);
5714 if (bp->flags & BNX2_FLAG_USING_MSI)
5715 printk(KERN_INFO PFX "%s: using MSI\n", dev->name);
5716 else if (bp->flags & BNX2_FLAG_USING_MSIX)
5717 printk(KERN_INFO PFX "%s: using MSIX\n", dev->name);
5719 netif_start_queue(dev);
5725 bnx2_reset_task(struct work_struct *work)
5727 struct bnx2 *bp = container_of(work, struct bnx2, reset_task);
5729 if (!netif_running(bp->dev))
5732 bp->in_reset_task = 1;
5733 bnx2_netif_stop(bp);
5735 bnx2_init_nic(bp, 1);
5737 atomic_set(&bp->intr_sem, 1);
5738 bnx2_netif_start(bp);
5739 bp->in_reset_task = 0;
5743 bnx2_tx_timeout(struct net_device *dev)
5745 struct bnx2 *bp = netdev_priv(dev);
5747 /* This allows the netif to be shutdown gracefully before resetting */
5748 schedule_work(&bp->reset_task);
5752 /* Called with rtnl_lock */
5754 bnx2_vlan_rx_register(struct net_device *dev, struct vlan_group *vlgrp)
5756 struct bnx2 *bp = netdev_priv(dev);
5758 bnx2_netif_stop(bp);
5761 bnx2_set_rx_mode(dev);
5763 bnx2_netif_start(bp);
5767 /* Called with netif_tx_lock.
5768 * bnx2_tx_int() runs without netif_tx_lock unless it needs to call
5769 * netif_wake_queue().
5772 bnx2_start_xmit(struct sk_buff *skb, struct net_device *dev)
5774 struct bnx2 *bp = netdev_priv(dev);
5777 struct sw_bd *tx_buf;
5778 u32 len, vlan_tag_flags, last_frag, mss;
5779 u16 prod, ring_prod;
5781 struct bnx2_napi *bnapi = &bp->bnx2_napi[bp->tx_vec];
5783 if (unlikely(bnx2_tx_avail(bp, bnapi) <
5784 (skb_shinfo(skb)->nr_frags + 1))) {
5785 netif_stop_queue(dev);
5786 printk(KERN_ERR PFX "%s: BUG! Tx ring full when queue awake!\n",
5789 return NETDEV_TX_BUSY;
5791 len = skb_headlen(skb);
5793 ring_prod = TX_RING_IDX(prod);
5796 if (skb->ip_summed == CHECKSUM_PARTIAL) {
5797 vlan_tag_flags |= TX_BD_FLAGS_TCP_UDP_CKSUM;
5800 if (bp->vlgrp && vlan_tx_tag_present(skb)) {
5802 (TX_BD_FLAGS_VLAN_TAG | (vlan_tx_tag_get(skb) << 16));
5804 if ((mss = skb_shinfo(skb)->gso_size)) {
5805 u32 tcp_opt_len, ip_tcp_len;
5808 vlan_tag_flags |= TX_BD_FLAGS_SW_LSO;
5810 tcp_opt_len = tcp_optlen(skb);
5812 if (skb_shinfo(skb)->gso_type & SKB_GSO_TCPV6) {
5813 u32 tcp_off = skb_transport_offset(skb) -
5814 sizeof(struct ipv6hdr) - ETH_HLEN;
5816 vlan_tag_flags |= ((tcp_opt_len >> 2) << 8) |
5817 TX_BD_FLAGS_SW_FLAGS;
5818 if (likely(tcp_off == 0))
5819 vlan_tag_flags &= ~TX_BD_FLAGS_TCP6_OFF0_MSK;
5822 vlan_tag_flags |= ((tcp_off & 0x3) <<
5823 TX_BD_FLAGS_TCP6_OFF0_SHL) |
5824 ((tcp_off & 0x10) <<
5825 TX_BD_FLAGS_TCP6_OFF4_SHL);
5826 mss |= (tcp_off & 0xc) << TX_BD_TCP6_OFF2_SHL;
5829 if (skb_header_cloned(skb) &&
5830 pskb_expand_head(skb, 0, 0, GFP_ATOMIC)) {
5832 return NETDEV_TX_OK;
5835 ip_tcp_len = ip_hdrlen(skb) + sizeof(struct tcphdr);
5839 iph->tot_len = htons(mss + ip_tcp_len + tcp_opt_len);
5840 tcp_hdr(skb)->check = ~csum_tcpudp_magic(iph->saddr,
5844 if (tcp_opt_len || (iph->ihl > 5)) {
5845 vlan_tag_flags |= ((iph->ihl - 5) +
5846 (tcp_opt_len >> 2)) << 8;
5852 mapping = pci_map_single(bp->pdev, skb->data, len, PCI_DMA_TODEVICE);
5854 tx_buf = &bp->tx_buf_ring[ring_prod];
5856 pci_unmap_addr_set(tx_buf, mapping, mapping);
5858 txbd = &bp->tx_desc_ring[ring_prod];
5860 txbd->tx_bd_haddr_hi = (u64) mapping >> 32;
5861 txbd->tx_bd_haddr_lo = (u64) mapping & 0xffffffff;
5862 txbd->tx_bd_mss_nbytes = len | (mss << 16);
5863 txbd->tx_bd_vlan_tag_flags = vlan_tag_flags | TX_BD_FLAGS_START;
5865 last_frag = skb_shinfo(skb)->nr_frags;
5867 for (i = 0; i < last_frag; i++) {
5868 skb_frag_t *frag = &skb_shinfo(skb)->frags[i];
5870 prod = NEXT_TX_BD(prod);
5871 ring_prod = TX_RING_IDX(prod);
5872 txbd = &bp->tx_desc_ring[ring_prod];
5875 mapping = pci_map_page(bp->pdev, frag->page, frag->page_offset,
5876 len, PCI_DMA_TODEVICE);
5877 pci_unmap_addr_set(&bp->tx_buf_ring[ring_prod],
5880 txbd->tx_bd_haddr_hi = (u64) mapping >> 32;
5881 txbd->tx_bd_haddr_lo = (u64) mapping & 0xffffffff;
5882 txbd->tx_bd_mss_nbytes = len | (mss << 16);
5883 txbd->tx_bd_vlan_tag_flags = vlan_tag_flags;
5886 txbd->tx_bd_vlan_tag_flags |= TX_BD_FLAGS_END;
5888 prod = NEXT_TX_BD(prod);
5889 bp->tx_prod_bseq += skb->len;
5891 REG_WR16(bp, bp->tx_bidx_addr, prod);
5892 REG_WR(bp, bp->tx_bseq_addr, bp->tx_prod_bseq);
5897 dev->trans_start = jiffies;
5899 if (unlikely(bnx2_tx_avail(bp, bnapi) <= MAX_SKB_FRAGS)) {
5900 netif_stop_queue(dev);
5901 if (bnx2_tx_avail(bp, bnapi) > bp->tx_wake_thresh)
5902 netif_wake_queue(dev);
5905 return NETDEV_TX_OK;
5908 /* Called with rtnl_lock */
5910 bnx2_close(struct net_device *dev)
5912 struct bnx2 *bp = netdev_priv(dev);
5915 /* Calling flush_scheduled_work() may deadlock because
5916 * linkwatch_event() may be on the workqueue and it will try to get
5917 * the rtnl_lock which we are holding.
5919 while (bp->in_reset_task)
5922 bnx2_disable_int_sync(bp);
5923 bnx2_napi_disable(bp);
5924 del_timer_sync(&bp->timer);
5925 if (bp->flags & BNX2_FLAG_NO_WOL)
5926 reset_code = BNX2_DRV_MSG_CODE_UNLOAD_LNK_DN;
5928 reset_code = BNX2_DRV_MSG_CODE_SUSPEND_WOL;
5930 reset_code = BNX2_DRV_MSG_CODE_SUSPEND_NO_WOL;
5931 bnx2_reset_chip(bp, reset_code);
5936 netif_carrier_off(bp->dev);
5937 bnx2_set_power_state(bp, PCI_D3hot);
5941 #define GET_NET_STATS64(ctr) \
5942 (unsigned long) ((unsigned long) (ctr##_hi) << 32) + \
5943 (unsigned long) (ctr##_lo)
5945 #define GET_NET_STATS32(ctr) \
5948 #if (BITS_PER_LONG == 64)
5949 #define GET_NET_STATS GET_NET_STATS64
5951 #define GET_NET_STATS GET_NET_STATS32
5954 static struct net_device_stats *
5955 bnx2_get_stats(struct net_device *dev)
5957 struct bnx2 *bp = netdev_priv(dev);
5958 struct statistics_block *stats_blk = bp->stats_blk;
5959 struct net_device_stats *net_stats = &bp->net_stats;
5961 if (bp->stats_blk == NULL) {
5964 net_stats->rx_packets =
5965 GET_NET_STATS(stats_blk->stat_IfHCInUcastPkts) +
5966 GET_NET_STATS(stats_blk->stat_IfHCInMulticastPkts) +
5967 GET_NET_STATS(stats_blk->stat_IfHCInBroadcastPkts);
5969 net_stats->tx_packets =
5970 GET_NET_STATS(stats_blk->stat_IfHCOutUcastPkts) +
5971 GET_NET_STATS(stats_blk->stat_IfHCOutMulticastPkts) +
5972 GET_NET_STATS(stats_blk->stat_IfHCOutBroadcastPkts);
5974 net_stats->rx_bytes =
5975 GET_NET_STATS(stats_blk->stat_IfHCInOctets);
5977 net_stats->tx_bytes =
5978 GET_NET_STATS(stats_blk->stat_IfHCOutOctets);
5980 net_stats->multicast =
5981 GET_NET_STATS(stats_blk->stat_IfHCOutMulticastPkts);
5983 net_stats->collisions =
5984 (unsigned long) stats_blk->stat_EtherStatsCollisions;
5986 net_stats->rx_length_errors =
5987 (unsigned long) (stats_blk->stat_EtherStatsUndersizePkts +
5988 stats_blk->stat_EtherStatsOverrsizePkts);
5990 net_stats->rx_over_errors =
5991 (unsigned long) stats_blk->stat_IfInMBUFDiscards;
5993 net_stats->rx_frame_errors =
5994 (unsigned long) stats_blk->stat_Dot3StatsAlignmentErrors;
5996 net_stats->rx_crc_errors =
5997 (unsigned long) stats_blk->stat_Dot3StatsFCSErrors;
5999 net_stats->rx_errors = net_stats->rx_length_errors +
6000 net_stats->rx_over_errors + net_stats->rx_frame_errors +
6001 net_stats->rx_crc_errors;
6003 net_stats->tx_aborted_errors =
6004 (unsigned long) (stats_blk->stat_Dot3StatsExcessiveCollisions +
6005 stats_blk->stat_Dot3StatsLateCollisions);
6007 if ((CHIP_NUM(bp) == CHIP_NUM_5706) ||
6008 (CHIP_ID(bp) == CHIP_ID_5708_A0))
6009 net_stats->tx_carrier_errors = 0;
6011 net_stats->tx_carrier_errors =
6013 stats_blk->stat_Dot3StatsCarrierSenseErrors;
6016 net_stats->tx_errors =
6018 stats_blk->stat_emac_tx_stat_dot3statsinternalmactransmiterrors
6020 net_stats->tx_aborted_errors +
6021 net_stats->tx_carrier_errors;
6023 net_stats->rx_missed_errors =
6024 (unsigned long) (stats_blk->stat_IfInMBUFDiscards +
6025 stats_blk->stat_FwRxDrop);
6030 /* All ethtool functions called with rtnl_lock */
6033 bnx2_get_settings(struct net_device *dev, struct ethtool_cmd *cmd)
6035 struct bnx2 *bp = netdev_priv(dev);
6036 int support_serdes = 0, support_copper = 0;
6038 cmd->supported = SUPPORTED_Autoneg;
6039 if (bp->phy_flags & BNX2_PHY_FLAG_REMOTE_PHY_CAP) {
6042 } else if (bp->phy_port == PORT_FIBRE)
6047 if (support_serdes) {
6048 cmd->supported |= SUPPORTED_1000baseT_Full |
6050 if (bp->phy_flags & BNX2_PHY_FLAG_2_5G_CAPABLE)
6051 cmd->supported |= SUPPORTED_2500baseX_Full;
6054 if (support_copper) {
6055 cmd->supported |= SUPPORTED_10baseT_Half |
6056 SUPPORTED_10baseT_Full |
6057 SUPPORTED_100baseT_Half |
6058 SUPPORTED_100baseT_Full |
6059 SUPPORTED_1000baseT_Full |
6064 spin_lock_bh(&bp->phy_lock);
6065 cmd->port = bp->phy_port;
6066 cmd->advertising = bp->advertising;
6068 if (bp->autoneg & AUTONEG_SPEED) {
6069 cmd->autoneg = AUTONEG_ENABLE;
6072 cmd->autoneg = AUTONEG_DISABLE;
6075 if (netif_carrier_ok(dev)) {
6076 cmd->speed = bp->line_speed;
6077 cmd->duplex = bp->duplex;
6083 spin_unlock_bh(&bp->phy_lock);
6085 cmd->transceiver = XCVR_INTERNAL;
6086 cmd->phy_address = bp->phy_addr;
6092 bnx2_set_settings(struct net_device *dev, struct ethtool_cmd *cmd)
6094 struct bnx2 *bp = netdev_priv(dev);
6095 u8 autoneg = bp->autoneg;
6096 u8 req_duplex = bp->req_duplex;
6097 u16 req_line_speed = bp->req_line_speed;
6098 u32 advertising = bp->advertising;
6101 spin_lock_bh(&bp->phy_lock);
6103 if (cmd->port != PORT_TP && cmd->port != PORT_FIBRE)
6104 goto err_out_unlock;
6106 if (cmd->port != bp->phy_port &&
6107 !(bp->phy_flags & BNX2_PHY_FLAG_REMOTE_PHY_CAP))
6108 goto err_out_unlock;
6110 if (cmd->autoneg == AUTONEG_ENABLE) {
6111 autoneg |= AUTONEG_SPEED;
6113 cmd->advertising &= ETHTOOL_ALL_COPPER_SPEED;
6115 /* allow advertising 1 speed */
6116 if ((cmd->advertising == ADVERTISED_10baseT_Half) ||
6117 (cmd->advertising == ADVERTISED_10baseT_Full) ||
6118 (cmd->advertising == ADVERTISED_100baseT_Half) ||
6119 (cmd->advertising == ADVERTISED_100baseT_Full)) {
6121 if (cmd->port == PORT_FIBRE)
6122 goto err_out_unlock;
6124 advertising = cmd->advertising;
6126 } else if (cmd->advertising == ADVERTISED_2500baseX_Full) {
6127 if (!(bp->phy_flags & BNX2_PHY_FLAG_2_5G_CAPABLE) ||
6128 (cmd->port == PORT_TP))
6129 goto err_out_unlock;
6130 } else if (cmd->advertising == ADVERTISED_1000baseT_Full)
6131 advertising = cmd->advertising;
6132 else if (cmd->advertising == ADVERTISED_1000baseT_Half)
6133 goto err_out_unlock;
6135 if (cmd->port == PORT_FIBRE)
6136 advertising = ETHTOOL_ALL_FIBRE_SPEED;
6138 advertising = ETHTOOL_ALL_COPPER_SPEED;
6140 advertising |= ADVERTISED_Autoneg;
6143 if (cmd->port == PORT_FIBRE) {
6144 if ((cmd->speed != SPEED_1000 &&
6145 cmd->speed != SPEED_2500) ||
6146 (cmd->duplex != DUPLEX_FULL))
6147 goto err_out_unlock;
6149 if (cmd->speed == SPEED_2500 &&
6150 !(bp->phy_flags & BNX2_PHY_FLAG_2_5G_CAPABLE))
6151 goto err_out_unlock;
6153 else if (cmd->speed == SPEED_1000 || cmd->speed == SPEED_2500)
6154 goto err_out_unlock;
6156 autoneg &= ~AUTONEG_SPEED;
6157 req_line_speed = cmd->speed;
6158 req_duplex = cmd->duplex;
6162 bp->autoneg = autoneg;
6163 bp->advertising = advertising;
6164 bp->req_line_speed = req_line_speed;
6165 bp->req_duplex = req_duplex;
6167 err = bnx2_setup_phy(bp, cmd->port);
6170 spin_unlock_bh(&bp->phy_lock);
6176 bnx2_get_drvinfo(struct net_device *dev, struct ethtool_drvinfo *info)
6178 struct bnx2 *bp = netdev_priv(dev);
6180 strcpy(info->driver, DRV_MODULE_NAME);
6181 strcpy(info->version, DRV_MODULE_VERSION);
6182 strcpy(info->bus_info, pci_name(bp->pdev));
6183 strcpy(info->fw_version, bp->fw_version);
6186 #define BNX2_REGDUMP_LEN (32 * 1024)
6189 bnx2_get_regs_len(struct net_device *dev)
6191 return BNX2_REGDUMP_LEN;
6195 bnx2_get_regs(struct net_device *dev, struct ethtool_regs *regs, void *_p)
6197 u32 *p = _p, i, offset;
6199 struct bnx2 *bp = netdev_priv(dev);
6200 u32 reg_boundaries[] = { 0x0000, 0x0098, 0x0400, 0x045c,
6201 0x0800, 0x0880, 0x0c00, 0x0c10,
6202 0x0c30, 0x0d08, 0x1000, 0x101c,
6203 0x1040, 0x1048, 0x1080, 0x10a4,
6204 0x1400, 0x1490, 0x1498, 0x14f0,
6205 0x1500, 0x155c, 0x1580, 0x15dc,
6206 0x1600, 0x1658, 0x1680, 0x16d8,
6207 0x1800, 0x1820, 0x1840, 0x1854,
6208 0x1880, 0x1894, 0x1900, 0x1984,
6209 0x1c00, 0x1c0c, 0x1c40, 0x1c54,
6210 0x1c80, 0x1c94, 0x1d00, 0x1d84,
6211 0x2000, 0x2030, 0x23c0, 0x2400,
6212 0x2800, 0x2820, 0x2830, 0x2850,
6213 0x2b40, 0x2c10, 0x2fc0, 0x3058,
6214 0x3c00, 0x3c94, 0x4000, 0x4010,
6215 0x4080, 0x4090, 0x43c0, 0x4458,
6216 0x4c00, 0x4c18, 0x4c40, 0x4c54,
6217 0x4fc0, 0x5010, 0x53c0, 0x5444,
6218 0x5c00, 0x5c18, 0x5c80, 0x5c90,
6219 0x5fc0, 0x6000, 0x6400, 0x6428,
6220 0x6800, 0x6848, 0x684c, 0x6860,
6221 0x6888, 0x6910, 0x8000 };
6225 memset(p, 0, BNX2_REGDUMP_LEN);
6227 if (!netif_running(bp->dev))
6231 offset = reg_boundaries[0];
6233 while (offset < BNX2_REGDUMP_LEN) {
6234 *p++ = REG_RD(bp, offset);
6236 if (offset == reg_boundaries[i + 1]) {
6237 offset = reg_boundaries[i + 2];
6238 p = (u32 *) (orig_p + offset);
6245 bnx2_get_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
6247 struct bnx2 *bp = netdev_priv(dev);
6249 if (bp->flags & BNX2_FLAG_NO_WOL) {
6254 wol->supported = WAKE_MAGIC;
6256 wol->wolopts = WAKE_MAGIC;
6260 memset(&wol->sopass, 0, sizeof(wol->sopass));
6264 bnx2_set_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
6266 struct bnx2 *bp = netdev_priv(dev);
6268 if (wol->wolopts & ~WAKE_MAGIC)
6271 if (wol->wolopts & WAKE_MAGIC) {
6272 if (bp->flags & BNX2_FLAG_NO_WOL)
6284 bnx2_nway_reset(struct net_device *dev)
6286 struct bnx2 *bp = netdev_priv(dev);
6289 if (!(bp->autoneg & AUTONEG_SPEED)) {
6293 spin_lock_bh(&bp->phy_lock);
6295 if (bp->phy_flags & BNX2_PHY_FLAG_REMOTE_PHY_CAP) {
6298 rc = bnx2_setup_remote_phy(bp, bp->phy_port);
6299 spin_unlock_bh(&bp->phy_lock);
6303 /* Force a link down visible on the other side */
6304 if (bp->phy_flags & BNX2_PHY_FLAG_SERDES) {
6305 bnx2_write_phy(bp, bp->mii_bmcr, BMCR_LOOPBACK);
6306 spin_unlock_bh(&bp->phy_lock);
6310 spin_lock_bh(&bp->phy_lock);
6312 bp->current_interval = SERDES_AN_TIMEOUT;
6313 bp->serdes_an_pending = 1;
6314 mod_timer(&bp->timer, jiffies + bp->current_interval);
6317 bnx2_read_phy(bp, bp->mii_bmcr, &bmcr);
6318 bmcr &= ~BMCR_LOOPBACK;
6319 bnx2_write_phy(bp, bp->mii_bmcr, bmcr | BMCR_ANRESTART | BMCR_ANENABLE);
6321 spin_unlock_bh(&bp->phy_lock);
6327 bnx2_get_eeprom_len(struct net_device *dev)
6329 struct bnx2 *bp = netdev_priv(dev);
6331 if (bp->flash_info == NULL)
6334 return (int) bp->flash_size;
6338 bnx2_get_eeprom(struct net_device *dev, struct ethtool_eeprom *eeprom,
6341 struct bnx2 *bp = netdev_priv(dev);
6344 /* parameters already validated in ethtool_get_eeprom */
6346 rc = bnx2_nvram_read(bp, eeprom->offset, eebuf, eeprom->len);
6352 bnx2_set_eeprom(struct net_device *dev, struct ethtool_eeprom *eeprom,
6355 struct bnx2 *bp = netdev_priv(dev);
6358 /* parameters already validated in ethtool_set_eeprom */
6360 rc = bnx2_nvram_write(bp, eeprom->offset, eebuf, eeprom->len);
6366 bnx2_get_coalesce(struct net_device *dev, struct ethtool_coalesce *coal)
6368 struct bnx2 *bp = netdev_priv(dev);
6370 memset(coal, 0, sizeof(struct ethtool_coalesce));
6372 coal->rx_coalesce_usecs = bp->rx_ticks;
6373 coal->rx_max_coalesced_frames = bp->rx_quick_cons_trip;
6374 coal->rx_coalesce_usecs_irq = bp->rx_ticks_int;
6375 coal->rx_max_coalesced_frames_irq = bp->rx_quick_cons_trip_int;
6377 coal->tx_coalesce_usecs = bp->tx_ticks;
6378 coal->tx_max_coalesced_frames = bp->tx_quick_cons_trip;
6379 coal->tx_coalesce_usecs_irq = bp->tx_ticks_int;
6380 coal->tx_max_coalesced_frames_irq = bp->tx_quick_cons_trip_int;
6382 coal->stats_block_coalesce_usecs = bp->stats_ticks;
6388 bnx2_set_coalesce(struct net_device *dev, struct ethtool_coalesce *coal)
6390 struct bnx2 *bp = netdev_priv(dev);
6392 bp->rx_ticks = (u16) coal->rx_coalesce_usecs;
6393 if (bp->rx_ticks > 0x3ff) bp->rx_ticks = 0x3ff;
6395 bp->rx_quick_cons_trip = (u16) coal->rx_max_coalesced_frames;
6396 if (bp->rx_quick_cons_trip > 0xff) bp->rx_quick_cons_trip = 0xff;
6398 bp->rx_ticks_int = (u16) coal->rx_coalesce_usecs_irq;
6399 if (bp->rx_ticks_int > 0x3ff) bp->rx_ticks_int = 0x3ff;
6401 bp->rx_quick_cons_trip_int = (u16) coal->rx_max_coalesced_frames_irq;
6402 if (bp->rx_quick_cons_trip_int > 0xff)
6403 bp->rx_quick_cons_trip_int = 0xff;
6405 bp->tx_ticks = (u16) coal->tx_coalesce_usecs;
6406 if (bp->tx_ticks > 0x3ff) bp->tx_ticks = 0x3ff;
6408 bp->tx_quick_cons_trip = (u16) coal->tx_max_coalesced_frames;
6409 if (bp->tx_quick_cons_trip > 0xff) bp->tx_quick_cons_trip = 0xff;
6411 bp->tx_ticks_int = (u16) coal->tx_coalesce_usecs_irq;
6412 if (bp->tx_ticks_int > 0x3ff) bp->tx_ticks_int = 0x3ff;
6414 bp->tx_quick_cons_trip_int = (u16) coal->tx_max_coalesced_frames_irq;
6415 if (bp->tx_quick_cons_trip_int > 0xff) bp->tx_quick_cons_trip_int =
6418 bp->stats_ticks = coal->stats_block_coalesce_usecs;
6419 if (CHIP_NUM(bp) == CHIP_NUM_5708) {
6420 if (bp->stats_ticks != 0 && bp->stats_ticks != USEC_PER_SEC)
6421 bp->stats_ticks = USEC_PER_SEC;
6423 if (bp->stats_ticks > BNX2_HC_STATS_TICKS_HC_STAT_TICKS)
6424 bp->stats_ticks = BNX2_HC_STATS_TICKS_HC_STAT_TICKS;
6425 bp->stats_ticks &= BNX2_HC_STATS_TICKS_HC_STAT_TICKS;
6427 if (netif_running(bp->dev)) {
6428 bnx2_netif_stop(bp);
6429 bnx2_init_nic(bp, 0);
6430 bnx2_netif_start(bp);
6437 bnx2_get_ringparam(struct net_device *dev, struct ethtool_ringparam *ering)
6439 struct bnx2 *bp = netdev_priv(dev);
6441 ering->rx_max_pending = MAX_TOTAL_RX_DESC_CNT;
6442 ering->rx_mini_max_pending = 0;
6443 ering->rx_jumbo_max_pending = MAX_TOTAL_RX_PG_DESC_CNT;
6445 ering->rx_pending = bp->rx_ring_size;
6446 ering->rx_mini_pending = 0;
6447 ering->rx_jumbo_pending = bp->rx_pg_ring_size;
6449 ering->tx_max_pending = MAX_TX_DESC_CNT;
6450 ering->tx_pending = bp->tx_ring_size;
6454 bnx2_change_ring_size(struct bnx2 *bp, u32 rx, u32 tx)
6456 if (netif_running(bp->dev)) {
6457 bnx2_netif_stop(bp);
6458 bnx2_reset_chip(bp, BNX2_DRV_MSG_CODE_RESET);
6463 bnx2_set_rx_ring_size(bp, rx);
6464 bp->tx_ring_size = tx;
6466 if (netif_running(bp->dev)) {
6469 rc = bnx2_alloc_mem(bp);
6472 bnx2_init_nic(bp, 0);
6473 bnx2_netif_start(bp);
6479 bnx2_set_ringparam(struct net_device *dev, struct ethtool_ringparam *ering)
6481 struct bnx2 *bp = netdev_priv(dev);
6484 if ((ering->rx_pending > MAX_TOTAL_RX_DESC_CNT) ||
6485 (ering->tx_pending > MAX_TX_DESC_CNT) ||
6486 (ering->tx_pending <= MAX_SKB_FRAGS)) {
6490 rc = bnx2_change_ring_size(bp, ering->rx_pending, ering->tx_pending);
6495 bnx2_get_pauseparam(struct net_device *dev, struct ethtool_pauseparam *epause)
6497 struct bnx2 *bp = netdev_priv(dev);
6499 epause->autoneg = ((bp->autoneg & AUTONEG_FLOW_CTRL) != 0);
6500 epause->rx_pause = ((bp->flow_ctrl & FLOW_CTRL_RX) != 0);
6501 epause->tx_pause = ((bp->flow_ctrl & FLOW_CTRL_TX) != 0);
6505 bnx2_set_pauseparam(struct net_device *dev, struct ethtool_pauseparam *epause)
6507 struct bnx2 *bp = netdev_priv(dev);
6509 bp->req_flow_ctrl = 0;
6510 if (epause->rx_pause)
6511 bp->req_flow_ctrl |= FLOW_CTRL_RX;
6512 if (epause->tx_pause)
6513 bp->req_flow_ctrl |= FLOW_CTRL_TX;
6515 if (epause->autoneg) {
6516 bp->autoneg |= AUTONEG_FLOW_CTRL;
6519 bp->autoneg &= ~AUTONEG_FLOW_CTRL;
6522 spin_lock_bh(&bp->phy_lock);
6524 bnx2_setup_phy(bp, bp->phy_port);
6526 spin_unlock_bh(&bp->phy_lock);
6532 bnx2_get_rx_csum(struct net_device *dev)
6534 struct bnx2 *bp = netdev_priv(dev);
6540 bnx2_set_rx_csum(struct net_device *dev, u32 data)
6542 struct bnx2 *bp = netdev_priv(dev);
6549 bnx2_set_tso(struct net_device *dev, u32 data)
6551 struct bnx2 *bp = netdev_priv(dev);
6554 dev->features |= NETIF_F_TSO | NETIF_F_TSO_ECN;
6555 if (CHIP_NUM(bp) == CHIP_NUM_5709)
6556 dev->features |= NETIF_F_TSO6;
6558 dev->features &= ~(NETIF_F_TSO | NETIF_F_TSO6 |
6563 #define BNX2_NUM_STATS 46
6566 char string[ETH_GSTRING_LEN];
6567 } bnx2_stats_str_arr[BNX2_NUM_STATS] = {
6569 { "rx_error_bytes" },
6571 { "tx_error_bytes" },
6572 { "rx_ucast_packets" },
6573 { "rx_mcast_packets" },
6574 { "rx_bcast_packets" },
6575 { "tx_ucast_packets" },
6576 { "tx_mcast_packets" },
6577 { "tx_bcast_packets" },
6578 { "tx_mac_errors" },
6579 { "tx_carrier_errors" },
6580 { "rx_crc_errors" },
6581 { "rx_align_errors" },
6582 { "tx_single_collisions" },
6583 { "tx_multi_collisions" },
6585 { "tx_excess_collisions" },
6586 { "tx_late_collisions" },
6587 { "tx_total_collisions" },
6590 { "rx_undersize_packets" },
6591 { "rx_oversize_packets" },
6592 { "rx_64_byte_packets" },
6593 { "rx_65_to_127_byte_packets" },
6594 { "rx_128_to_255_byte_packets" },
6595 { "rx_256_to_511_byte_packets" },
6596 { "rx_512_to_1023_byte_packets" },
6597 { "rx_1024_to_1522_byte_packets" },
6598 { "rx_1523_to_9022_byte_packets" },
6599 { "tx_64_byte_packets" },
6600 { "tx_65_to_127_byte_packets" },
6601 { "tx_128_to_255_byte_packets" },
6602 { "tx_256_to_511_byte_packets" },
6603 { "tx_512_to_1023_byte_packets" },
6604 { "tx_1024_to_1522_byte_packets" },
6605 { "tx_1523_to_9022_byte_packets" },
6606 { "rx_xon_frames" },
6607 { "rx_xoff_frames" },
6608 { "tx_xon_frames" },
6609 { "tx_xoff_frames" },
6610 { "rx_mac_ctrl_frames" },
6611 { "rx_filtered_packets" },
6613 { "rx_fw_discards" },
6616 #define STATS_OFFSET32(offset_name) (offsetof(struct statistics_block, offset_name) / 4)
6618 static const unsigned long bnx2_stats_offset_arr[BNX2_NUM_STATS] = {
6619 STATS_OFFSET32(stat_IfHCInOctets_hi),
6620 STATS_OFFSET32(stat_IfHCInBadOctets_hi),
6621 STATS_OFFSET32(stat_IfHCOutOctets_hi),
6622 STATS_OFFSET32(stat_IfHCOutBadOctets_hi),
6623 STATS_OFFSET32(stat_IfHCInUcastPkts_hi),
6624 STATS_OFFSET32(stat_IfHCInMulticastPkts_hi),
6625 STATS_OFFSET32(stat_IfHCInBroadcastPkts_hi),
6626 STATS_OFFSET32(stat_IfHCOutUcastPkts_hi),
6627 STATS_OFFSET32(stat_IfHCOutMulticastPkts_hi),
6628 STATS_OFFSET32(stat_IfHCOutBroadcastPkts_hi),
6629 STATS_OFFSET32(stat_emac_tx_stat_dot3statsinternalmactransmiterrors),
6630 STATS_OFFSET32(stat_Dot3StatsCarrierSenseErrors),
6631 STATS_OFFSET32(stat_Dot3StatsFCSErrors),
6632 STATS_OFFSET32(stat_Dot3StatsAlignmentErrors),
6633 STATS_OFFSET32(stat_Dot3StatsSingleCollisionFrames),
6634 STATS_OFFSET32(stat_Dot3StatsMultipleCollisionFrames),
6635 STATS_OFFSET32(stat_Dot3StatsDeferredTransmissions),
6636 STATS_OFFSET32(stat_Dot3StatsExcessiveCollisions),
6637 STATS_OFFSET32(stat_Dot3StatsLateCollisions),
6638 STATS_OFFSET32(stat_EtherStatsCollisions),
6639 STATS_OFFSET32(stat_EtherStatsFragments),
6640 STATS_OFFSET32(stat_EtherStatsJabbers),
6641 STATS_OFFSET32(stat_EtherStatsUndersizePkts),
6642 STATS_OFFSET32(stat_EtherStatsOverrsizePkts),
6643 STATS_OFFSET32(stat_EtherStatsPktsRx64Octets),
6644 STATS_OFFSET32(stat_EtherStatsPktsRx65Octetsto127Octets),
6645 STATS_OFFSET32(stat_EtherStatsPktsRx128Octetsto255Octets),
6646 STATS_OFFSET32(stat_EtherStatsPktsRx256Octetsto511Octets),
6647 STATS_OFFSET32(stat_EtherStatsPktsRx512Octetsto1023Octets),
6648 STATS_OFFSET32(stat_EtherStatsPktsRx1024Octetsto1522Octets),
6649 STATS_OFFSET32(stat_EtherStatsPktsRx1523Octetsto9022Octets),
6650 STATS_OFFSET32(stat_EtherStatsPktsTx64Octets),
6651 STATS_OFFSET32(stat_EtherStatsPktsTx65Octetsto127Octets),
6652 STATS_OFFSET32(stat_EtherStatsPktsTx128Octetsto255Octets),
6653 STATS_OFFSET32(stat_EtherStatsPktsTx256Octetsto511Octets),
6654 STATS_OFFSET32(stat_EtherStatsPktsTx512Octetsto1023Octets),
6655 STATS_OFFSET32(stat_EtherStatsPktsTx1024Octetsto1522Octets),
6656 STATS_OFFSET32(stat_EtherStatsPktsTx1523Octetsto9022Octets),
6657 STATS_OFFSET32(stat_XonPauseFramesReceived),
6658 STATS_OFFSET32(stat_XoffPauseFramesReceived),
6659 STATS_OFFSET32(stat_OutXonSent),
6660 STATS_OFFSET32(stat_OutXoffSent),
6661 STATS_OFFSET32(stat_MacControlFramesReceived),
6662 STATS_OFFSET32(stat_IfInFramesL2FilterDiscards),
6663 STATS_OFFSET32(stat_IfInMBUFDiscards),
6664 STATS_OFFSET32(stat_FwRxDrop),
6667 /* stat_IfHCInBadOctets and stat_Dot3StatsCarrierSenseErrors are
6668 * skipped because of errata.
6670 static u8 bnx2_5706_stats_len_arr[BNX2_NUM_STATS] = {
6671 8,0,8,8,8,8,8,8,8,8,
6672 4,0,4,4,4,4,4,4,4,4,
6673 4,4,4,4,4,4,4,4,4,4,
6674 4,4,4,4,4,4,4,4,4,4,
6678 static u8 bnx2_5708_stats_len_arr[BNX2_NUM_STATS] = {
6679 8,0,8,8,8,8,8,8,8,8,
6680 4,4,4,4,4,4,4,4,4,4,
6681 4,4,4,4,4,4,4,4,4,4,
6682 4,4,4,4,4,4,4,4,4,4,
6686 #define BNX2_NUM_TESTS 6
6689 char string[ETH_GSTRING_LEN];
6690 } bnx2_tests_str_arr[BNX2_NUM_TESTS] = {
6691 { "register_test (offline)" },
6692 { "memory_test (offline)" },
6693 { "loopback_test (offline)" },
6694 { "nvram_test (online)" },
6695 { "interrupt_test (online)" },
6696 { "link_test (online)" },
6700 bnx2_get_sset_count(struct net_device *dev, int sset)
6704 return BNX2_NUM_TESTS;
6706 return BNX2_NUM_STATS;
6713 bnx2_self_test(struct net_device *dev, struct ethtool_test *etest, u64 *buf)
6715 struct bnx2 *bp = netdev_priv(dev);
6717 memset(buf, 0, sizeof(u64) * BNX2_NUM_TESTS);
6718 if (etest->flags & ETH_TEST_FL_OFFLINE) {
6721 bnx2_netif_stop(bp);
6722 bnx2_reset_chip(bp, BNX2_DRV_MSG_CODE_DIAG);
6725 if (bnx2_test_registers(bp) != 0) {
6727 etest->flags |= ETH_TEST_FL_FAILED;
6729 if (bnx2_test_memory(bp) != 0) {
6731 etest->flags |= ETH_TEST_FL_FAILED;
6733 if ((buf[2] = bnx2_test_loopback(bp)) != 0)
6734 etest->flags |= ETH_TEST_FL_FAILED;
6736 if (!netif_running(bp->dev)) {
6737 bnx2_reset_chip(bp, BNX2_DRV_MSG_CODE_RESET);
6740 bnx2_init_nic(bp, 1);
6741 bnx2_netif_start(bp);
6744 /* wait for link up */
6745 for (i = 0; i < 7; i++) {
6748 msleep_interruptible(1000);
6752 if (bnx2_test_nvram(bp) != 0) {
6754 etest->flags |= ETH_TEST_FL_FAILED;
6756 if (bnx2_test_intr(bp) != 0) {
6758 etest->flags |= ETH_TEST_FL_FAILED;
6761 if (bnx2_test_link(bp) != 0) {
6763 etest->flags |= ETH_TEST_FL_FAILED;
6769 bnx2_get_strings(struct net_device *dev, u32 stringset, u8 *buf)
6771 switch (stringset) {
6773 memcpy(buf, bnx2_stats_str_arr,
6774 sizeof(bnx2_stats_str_arr));
6777 memcpy(buf, bnx2_tests_str_arr,
6778 sizeof(bnx2_tests_str_arr));
6784 bnx2_get_ethtool_stats(struct net_device *dev,
6785 struct ethtool_stats *stats, u64 *buf)
6787 struct bnx2 *bp = netdev_priv(dev);
6789 u32 *hw_stats = (u32 *) bp->stats_blk;
6790 u8 *stats_len_arr = NULL;
6792 if (hw_stats == NULL) {
6793 memset(buf, 0, sizeof(u64) * BNX2_NUM_STATS);
6797 if ((CHIP_ID(bp) == CHIP_ID_5706_A0) ||
6798 (CHIP_ID(bp) == CHIP_ID_5706_A1) ||
6799 (CHIP_ID(bp) == CHIP_ID_5706_A2) ||
6800 (CHIP_ID(bp) == CHIP_ID_5708_A0))
6801 stats_len_arr = bnx2_5706_stats_len_arr;
6803 stats_len_arr = bnx2_5708_stats_len_arr;
6805 for (i = 0; i < BNX2_NUM_STATS; i++) {
6806 if (stats_len_arr[i] == 0) {
6807 /* skip this counter */
6811 if (stats_len_arr[i] == 4) {
6812 /* 4-byte counter */
6814 *(hw_stats + bnx2_stats_offset_arr[i]);
6817 /* 8-byte counter */
6818 buf[i] = (((u64) *(hw_stats +
6819 bnx2_stats_offset_arr[i])) << 32) +
6820 *(hw_stats + bnx2_stats_offset_arr[i] + 1);
6825 bnx2_phys_id(struct net_device *dev, u32 data)
6827 struct bnx2 *bp = netdev_priv(dev);
6834 save = REG_RD(bp, BNX2_MISC_CFG);
6835 REG_WR(bp, BNX2_MISC_CFG, BNX2_MISC_CFG_LEDMODE_MAC);
6837 for (i = 0; i < (data * 2); i++) {
6839 REG_WR(bp, BNX2_EMAC_LED, BNX2_EMAC_LED_OVERRIDE);
6842 REG_WR(bp, BNX2_EMAC_LED, BNX2_EMAC_LED_OVERRIDE |
6843 BNX2_EMAC_LED_1000MB_OVERRIDE |
6844 BNX2_EMAC_LED_100MB_OVERRIDE |
6845 BNX2_EMAC_LED_10MB_OVERRIDE |
6846 BNX2_EMAC_LED_TRAFFIC_OVERRIDE |
6847 BNX2_EMAC_LED_TRAFFIC);
6849 msleep_interruptible(500);
6850 if (signal_pending(current))
6853 REG_WR(bp, BNX2_EMAC_LED, 0);
6854 REG_WR(bp, BNX2_MISC_CFG, save);
6859 bnx2_set_tx_csum(struct net_device *dev, u32 data)
6861 struct bnx2 *bp = netdev_priv(dev);
6863 if (CHIP_NUM(bp) == CHIP_NUM_5709)
6864 return (ethtool_op_set_tx_ipv6_csum(dev, data));
6866 return (ethtool_op_set_tx_csum(dev, data));
6869 static const struct ethtool_ops bnx2_ethtool_ops = {
6870 .get_settings = bnx2_get_settings,
6871 .set_settings = bnx2_set_settings,
6872 .get_drvinfo = bnx2_get_drvinfo,
6873 .get_regs_len = bnx2_get_regs_len,
6874 .get_regs = bnx2_get_regs,
6875 .get_wol = bnx2_get_wol,
6876 .set_wol = bnx2_set_wol,
6877 .nway_reset = bnx2_nway_reset,
6878 .get_link = ethtool_op_get_link,
6879 .get_eeprom_len = bnx2_get_eeprom_len,
6880 .get_eeprom = bnx2_get_eeprom,
6881 .set_eeprom = bnx2_set_eeprom,
6882 .get_coalesce = bnx2_get_coalesce,
6883 .set_coalesce = bnx2_set_coalesce,
6884 .get_ringparam = bnx2_get_ringparam,
6885 .set_ringparam = bnx2_set_ringparam,
6886 .get_pauseparam = bnx2_get_pauseparam,
6887 .set_pauseparam = bnx2_set_pauseparam,
6888 .get_rx_csum = bnx2_get_rx_csum,
6889 .set_rx_csum = bnx2_set_rx_csum,
6890 .set_tx_csum = bnx2_set_tx_csum,
6891 .set_sg = ethtool_op_set_sg,
6892 .set_tso = bnx2_set_tso,
6893 .self_test = bnx2_self_test,
6894 .get_strings = bnx2_get_strings,
6895 .phys_id = bnx2_phys_id,
6896 .get_ethtool_stats = bnx2_get_ethtool_stats,
6897 .get_sset_count = bnx2_get_sset_count,
6900 /* Called with rtnl_lock */
6902 bnx2_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd)
6904 struct mii_ioctl_data *data = if_mii(ifr);
6905 struct bnx2 *bp = netdev_priv(dev);
6910 data->phy_id = bp->phy_addr;
6916 if (bp->phy_flags & BNX2_PHY_FLAG_REMOTE_PHY_CAP)
6919 if (!netif_running(dev))
6922 spin_lock_bh(&bp->phy_lock);
6923 err = bnx2_read_phy(bp, data->reg_num & 0x1f, &mii_regval);
6924 spin_unlock_bh(&bp->phy_lock);
6926 data->val_out = mii_regval;
6932 if (!capable(CAP_NET_ADMIN))
6935 if (bp->phy_flags & BNX2_PHY_FLAG_REMOTE_PHY_CAP)
6938 if (!netif_running(dev))
6941 spin_lock_bh(&bp->phy_lock);
6942 err = bnx2_write_phy(bp, data->reg_num & 0x1f, data->val_in);
6943 spin_unlock_bh(&bp->phy_lock);
6954 /* Called with rtnl_lock */
6956 bnx2_change_mac_addr(struct net_device *dev, void *p)
6958 struct sockaddr *addr = p;
6959 struct bnx2 *bp = netdev_priv(dev);
6961 if (!is_valid_ether_addr(addr->sa_data))
6964 memcpy(dev->dev_addr, addr->sa_data, dev->addr_len);
6965 if (netif_running(dev))
6966 bnx2_set_mac_addr(bp);
6971 /* Called with rtnl_lock */
6973 bnx2_change_mtu(struct net_device *dev, int new_mtu)
6975 struct bnx2 *bp = netdev_priv(dev);
6977 if (((new_mtu + ETH_HLEN) > MAX_ETHERNET_JUMBO_PACKET_SIZE) ||
6978 ((new_mtu + ETH_HLEN) < MIN_ETHERNET_PACKET_SIZE))
6982 return (bnx2_change_ring_size(bp, bp->rx_ring_size, bp->tx_ring_size));
6985 #if defined(HAVE_POLL_CONTROLLER) || defined(CONFIG_NET_POLL_CONTROLLER)
6987 poll_bnx2(struct net_device *dev)
6989 struct bnx2 *bp = netdev_priv(dev);
6991 disable_irq(bp->pdev->irq);
6992 bnx2_interrupt(bp->pdev->irq, dev);
6993 enable_irq(bp->pdev->irq);
6997 static void __devinit
6998 bnx2_get_5709_media(struct bnx2 *bp)
7000 u32 val = REG_RD(bp, BNX2_MISC_DUAL_MEDIA_CTRL);
7001 u32 bond_id = val & BNX2_MISC_DUAL_MEDIA_CTRL_BOND_ID;
7004 if (bond_id == BNX2_MISC_DUAL_MEDIA_CTRL_BOND_ID_C)
7006 else if (bond_id == BNX2_MISC_DUAL_MEDIA_CTRL_BOND_ID_S) {
7007 bp->phy_flags |= BNX2_PHY_FLAG_SERDES;
7011 if (val & BNX2_MISC_DUAL_MEDIA_CTRL_STRAP_OVERRIDE)
7012 strap = (val & BNX2_MISC_DUAL_MEDIA_CTRL_PHY_CTRL) >> 21;
7014 strap = (val & BNX2_MISC_DUAL_MEDIA_CTRL_PHY_CTRL_STRAP) >> 8;
7016 if (PCI_FUNC(bp->pdev->devfn) == 0) {
7021 bp->phy_flags |= BNX2_PHY_FLAG_SERDES;
7029 bp->phy_flags |= BNX2_PHY_FLAG_SERDES;
7035 static void __devinit
7036 bnx2_get_pci_speed(struct bnx2 *bp)
7040 reg = REG_RD(bp, BNX2_PCICFG_MISC_STATUS);
7041 if (reg & BNX2_PCICFG_MISC_STATUS_PCIX_DET) {
7044 bp->flags |= BNX2_FLAG_PCIX;
7046 clkreg = REG_RD(bp, BNX2_PCICFG_PCI_CLOCK_CONTROL_BITS);
7048 clkreg &= BNX2_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET;
7050 case BNX2_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_133MHZ:
7051 bp->bus_speed_mhz = 133;
7054 case BNX2_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_95MHZ:
7055 bp->bus_speed_mhz = 100;
7058 case BNX2_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_66MHZ:
7059 case BNX2_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_80MHZ:
7060 bp->bus_speed_mhz = 66;
7063 case BNX2_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_48MHZ:
7064 case BNX2_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_55MHZ:
7065 bp->bus_speed_mhz = 50;
7068 case BNX2_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_LOW:
7069 case BNX2_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_32MHZ:
7070 case BNX2_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_38MHZ:
7071 bp->bus_speed_mhz = 33;
7076 if (reg & BNX2_PCICFG_MISC_STATUS_M66EN)
7077 bp->bus_speed_mhz = 66;
7079 bp->bus_speed_mhz = 33;
7082 if (reg & BNX2_PCICFG_MISC_STATUS_32BIT_DET)
7083 bp->flags |= BNX2_FLAG_PCI_32BIT;
7087 static int __devinit
7088 bnx2_init_board(struct pci_dev *pdev, struct net_device *dev)
7091 unsigned long mem_len;
7094 u64 dma_mask, persist_dma_mask;
7096 SET_NETDEV_DEV(dev, &pdev->dev);
7097 bp = netdev_priv(dev);
7102 /* enable device (incl. PCI PM wakeup), and bus-mastering */
7103 rc = pci_enable_device(pdev);
7105 dev_err(&pdev->dev, "Cannot enable PCI device, aborting.\n");
7109 if (!(pci_resource_flags(pdev, 0) & IORESOURCE_MEM)) {
7111 "Cannot find PCI device base address, aborting.\n");
7113 goto err_out_disable;
7116 rc = pci_request_regions(pdev, DRV_MODULE_NAME);
7118 dev_err(&pdev->dev, "Cannot obtain PCI resources, aborting.\n");
7119 goto err_out_disable;
7122 pci_set_master(pdev);
7123 pci_save_state(pdev);
7125 bp->pm_cap = pci_find_capability(pdev, PCI_CAP_ID_PM);
7126 if (bp->pm_cap == 0) {
7128 "Cannot find power management capability, aborting.\n");
7130 goto err_out_release;
7136 spin_lock_init(&bp->phy_lock);
7137 spin_lock_init(&bp->indirect_lock);
7138 INIT_WORK(&bp->reset_task, bnx2_reset_task);
7140 dev->base_addr = dev->mem_start = pci_resource_start(pdev, 0);
7141 mem_len = MB_GET_CID_ADDR(TX_TSS_CID + 1);
7142 dev->mem_end = dev->mem_start + mem_len;
7143 dev->irq = pdev->irq;
7145 bp->regview = ioremap_nocache(dev->base_addr, mem_len);
7148 dev_err(&pdev->dev, "Cannot map register space, aborting.\n");
7150 goto err_out_release;
7153 /* Configure byte swap and enable write to the reg_window registers.
7154 * Rely on CPU to do target byte swapping on big endian systems
7155 * The chip's target access swapping will not swap all accesses
7157 pci_write_config_dword(bp->pdev, BNX2_PCICFG_MISC_CONFIG,
7158 BNX2_PCICFG_MISC_CONFIG_REG_WINDOW_ENA |
7159 BNX2_PCICFG_MISC_CONFIG_TARGET_MB_WORD_SWAP);
7161 bnx2_set_power_state(bp, PCI_D0);
7163 bp->chip_id = REG_RD(bp, BNX2_MISC_ID);
7165 if (CHIP_NUM(bp) == CHIP_NUM_5709) {
7166 if (pci_find_capability(pdev, PCI_CAP_ID_EXP) == 0) {
7168 "Cannot find PCIE capability, aborting.\n");
7172 bp->flags |= BNX2_FLAG_PCIE;
7173 if (CHIP_REV(bp) == CHIP_REV_Ax)
7174 bp->flags |= BNX2_FLAG_JUMBO_BROKEN;
7176 bp->pcix_cap = pci_find_capability(pdev, PCI_CAP_ID_PCIX);
7177 if (bp->pcix_cap == 0) {
7179 "Cannot find PCIX capability, aborting.\n");
7185 if (CHIP_NUM(bp) == CHIP_NUM_5709 && CHIP_REV(bp) != CHIP_REV_Ax) {
7186 if (pci_find_capability(pdev, PCI_CAP_ID_MSIX))
7187 bp->flags |= BNX2_FLAG_MSIX_CAP;
7190 if (CHIP_ID(bp) != CHIP_ID_5706_A0 && CHIP_ID(bp) != CHIP_ID_5706_A1) {
7191 if (pci_find_capability(pdev, PCI_CAP_ID_MSI))
7192 bp->flags |= BNX2_FLAG_MSI_CAP;
7195 /* 5708 cannot support DMA addresses > 40-bit. */
7196 if (CHIP_NUM(bp) == CHIP_NUM_5708)
7197 persist_dma_mask = dma_mask = DMA_40BIT_MASK;
7199 persist_dma_mask = dma_mask = DMA_64BIT_MASK;
7201 /* Configure DMA attributes. */
7202 if (pci_set_dma_mask(pdev, dma_mask) == 0) {
7203 dev->features |= NETIF_F_HIGHDMA;
7204 rc = pci_set_consistent_dma_mask(pdev, persist_dma_mask);
7207 "pci_set_consistent_dma_mask failed, aborting.\n");
7210 } else if ((rc = pci_set_dma_mask(pdev, DMA_32BIT_MASK)) != 0) {
7211 dev_err(&pdev->dev, "System does not support DMA, aborting.\n");
7215 if (!(bp->flags & BNX2_FLAG_PCIE))
7216 bnx2_get_pci_speed(bp);
7218 /* 5706A0 may falsely detect SERR and PERR. */
7219 if (CHIP_ID(bp) == CHIP_ID_5706_A0) {
7220 reg = REG_RD(bp, PCI_COMMAND);
7221 reg &= ~(PCI_COMMAND_SERR | PCI_COMMAND_PARITY);
7222 REG_WR(bp, PCI_COMMAND, reg);
7224 else if ((CHIP_ID(bp) == CHIP_ID_5706_A1) &&
7225 !(bp->flags & BNX2_FLAG_PCIX)) {
7228 "5706 A1 can only be used in a PCIX bus, aborting.\n");
7232 bnx2_init_nvram(bp);
7234 reg = bnx2_reg_rd_ind(bp, BNX2_SHM_HDR_SIGNATURE);
7236 if ((reg & BNX2_SHM_HDR_SIGNATURE_SIG_MASK) ==
7237 BNX2_SHM_HDR_SIGNATURE_SIG) {
7238 u32 off = PCI_FUNC(pdev->devfn) << 2;
7240 bp->shmem_base = bnx2_reg_rd_ind(bp, BNX2_SHM_HDR_ADDR_0 + off);
7242 bp->shmem_base = HOST_VIEW_SHMEM_BASE;
7244 /* Get the permanent MAC address. First we need to make sure the
7245 * firmware is actually running.
7247 reg = bnx2_shmem_rd(bp, BNX2_DEV_INFO_SIGNATURE);
7249 if ((reg & BNX2_DEV_INFO_SIGNATURE_MAGIC_MASK) !=
7250 BNX2_DEV_INFO_SIGNATURE_MAGIC) {
7251 dev_err(&pdev->dev, "Firmware not running, aborting.\n");
7256 reg = bnx2_shmem_rd(bp, BNX2_DEV_INFO_BC_REV);
7257 for (i = 0, j = 0; i < 3; i++) {
7260 num = (u8) (reg >> (24 - (i * 8)));
7261 for (k = 100, skip0 = 1; k >= 1; num %= k, k /= 10) {
7262 if (num >= k || !skip0 || k == 1) {
7263 bp->fw_version[j++] = (num / k) + '0';
7268 bp->fw_version[j++] = '.';
7270 reg = bnx2_shmem_rd(bp, BNX2_PORT_FEATURE);
7271 if (reg & BNX2_PORT_FEATURE_WOL_ENABLED)
7274 if (reg & BNX2_PORT_FEATURE_ASF_ENABLED) {
7275 bp->flags |= BNX2_FLAG_ASF_ENABLE;
7277 for (i = 0; i < 30; i++) {
7278 reg = bnx2_shmem_rd(bp, BNX2_BC_STATE_CONDITION);
7279 if (reg & BNX2_CONDITION_MFW_RUN_MASK)
7284 reg = bnx2_shmem_rd(bp, BNX2_BC_STATE_CONDITION);
7285 reg &= BNX2_CONDITION_MFW_RUN_MASK;
7286 if (reg != BNX2_CONDITION_MFW_RUN_UNKNOWN &&
7287 reg != BNX2_CONDITION_MFW_RUN_NONE) {
7289 u32 addr = bnx2_shmem_rd(bp, BNX2_MFW_VER_PTR);
7291 bp->fw_version[j++] = ' ';
7292 for (i = 0; i < 3; i++) {
7293 reg = bnx2_reg_rd_ind(bp, addr + i * 4);
7295 memcpy(&bp->fw_version[j], ®, 4);
7300 reg = bnx2_shmem_rd(bp, BNX2_PORT_HW_CFG_MAC_UPPER);
7301 bp->mac_addr[0] = (u8) (reg >> 8);
7302 bp->mac_addr[1] = (u8) reg;
7304 reg = bnx2_shmem_rd(bp, BNX2_PORT_HW_CFG_MAC_LOWER);
7305 bp->mac_addr[2] = (u8) (reg >> 24);
7306 bp->mac_addr[3] = (u8) (reg >> 16);
7307 bp->mac_addr[4] = (u8) (reg >> 8);
7308 bp->mac_addr[5] = (u8) reg;
7310 bp->tx_ring_size = MAX_TX_DESC_CNT;
7311 bnx2_set_rx_ring_size(bp, 255);
7315 bp->tx_quick_cons_trip_int = 20;
7316 bp->tx_quick_cons_trip = 20;
7317 bp->tx_ticks_int = 80;
7320 bp->rx_quick_cons_trip_int = 6;
7321 bp->rx_quick_cons_trip = 6;
7322 bp->rx_ticks_int = 18;
7325 bp->stats_ticks = USEC_PER_SEC & BNX2_HC_STATS_TICKS_HC_STAT_TICKS;
7327 bp->timer_interval = HZ;
7328 bp->current_interval = HZ;
7332 /* Disable WOL support if we are running on a SERDES chip. */
7333 if (CHIP_NUM(bp) == CHIP_NUM_5709)
7334 bnx2_get_5709_media(bp);
7335 else if (CHIP_BOND_ID(bp) & CHIP_BOND_ID_SERDES_BIT)
7336 bp->phy_flags |= BNX2_PHY_FLAG_SERDES;
7338 bp->phy_port = PORT_TP;
7339 if (bp->phy_flags & BNX2_PHY_FLAG_SERDES) {
7340 bp->phy_port = PORT_FIBRE;
7341 reg = bnx2_shmem_rd(bp, BNX2_SHARED_HW_CFG_CONFIG);
7342 if (!(reg & BNX2_SHARED_HW_CFG_GIG_LINK_ON_VAUX)) {
7343 bp->flags |= BNX2_FLAG_NO_WOL;
7346 if (CHIP_NUM(bp) == CHIP_NUM_5706) {
7347 /* Don't do parallel detect on this board because of
7348 * some board problems. The link will not go down
7349 * if we do parallel detect.
7351 if (pdev->subsystem_vendor == PCI_VENDOR_ID_HP &&
7352 pdev->subsystem_device == 0x310c)
7353 bp->phy_flags |= BNX2_PHY_FLAG_NO_PARALLEL;
7356 if (reg & BNX2_SHARED_HW_CFG_PHY_2_5G)
7357 bp->phy_flags |= BNX2_PHY_FLAG_2_5G_CAPABLE;
7359 bnx2_init_remote_phy(bp);
7361 } else if (CHIP_NUM(bp) == CHIP_NUM_5706 ||
7362 CHIP_NUM(bp) == CHIP_NUM_5708)
7363 bp->phy_flags |= BNX2_PHY_FLAG_CRC_FIX;
7364 else if (CHIP_NUM(bp) == CHIP_NUM_5709 &&
7365 (CHIP_REV(bp) == CHIP_REV_Ax ||
7366 CHIP_REV(bp) == CHIP_REV_Bx))
7367 bp->phy_flags |= BNX2_PHY_FLAG_DIS_EARLY_DAC;
7369 if ((CHIP_ID(bp) == CHIP_ID_5708_A0) ||
7370 (CHIP_ID(bp) == CHIP_ID_5708_B0) ||
7371 (CHIP_ID(bp) == CHIP_ID_5708_B1)) {
7372 bp->flags |= BNX2_FLAG_NO_WOL;
7376 if (CHIP_ID(bp) == CHIP_ID_5706_A0) {
7377 bp->tx_quick_cons_trip_int =
7378 bp->tx_quick_cons_trip;
7379 bp->tx_ticks_int = bp->tx_ticks;
7380 bp->rx_quick_cons_trip_int =
7381 bp->rx_quick_cons_trip;
7382 bp->rx_ticks_int = bp->rx_ticks;
7383 bp->comp_prod_trip_int = bp->comp_prod_trip;
7384 bp->com_ticks_int = bp->com_ticks;
7385 bp->cmd_ticks_int = bp->cmd_ticks;
7388 /* Disable MSI on 5706 if AMD 8132 bridge is found.
7390 * MSI is defined to be 32-bit write. The 5706 does 64-bit MSI writes
7391 * with byte enables disabled on the unused 32-bit word. This is legal
7392 * but causes problems on the AMD 8132 which will eventually stop
7393 * responding after a while.
7395 * AMD believes this incompatibility is unique to the 5706, and
7396 * prefers to locally disable MSI rather than globally disabling it.
7398 if (CHIP_NUM(bp) == CHIP_NUM_5706 && disable_msi == 0) {
7399 struct pci_dev *amd_8132 = NULL;
7401 while ((amd_8132 = pci_get_device(PCI_VENDOR_ID_AMD,
7402 PCI_DEVICE_ID_AMD_8132_BRIDGE,
7405 if (amd_8132->revision >= 0x10 &&
7406 amd_8132->revision <= 0x13) {
7408 pci_dev_put(amd_8132);
7414 bnx2_set_default_link(bp);
7415 bp->req_flow_ctrl = FLOW_CTRL_RX | FLOW_CTRL_TX;
7417 init_timer(&bp->timer);
7418 bp->timer.expires = RUN_AT(bp->timer_interval);
7419 bp->timer.data = (unsigned long) bp;
7420 bp->timer.function = bnx2_timer;
7426 iounmap(bp->regview);
7431 pci_release_regions(pdev);
7434 pci_disable_device(pdev);
7435 pci_set_drvdata(pdev, NULL);
7441 static char * __devinit
7442 bnx2_bus_string(struct bnx2 *bp, char *str)
7446 if (bp->flags & BNX2_FLAG_PCIE) {
7447 s += sprintf(s, "PCI Express");
7449 s += sprintf(s, "PCI");
7450 if (bp->flags & BNX2_FLAG_PCIX)
7451 s += sprintf(s, "-X");
7452 if (bp->flags & BNX2_FLAG_PCI_32BIT)
7453 s += sprintf(s, " 32-bit");
7455 s += sprintf(s, " 64-bit");
7456 s += sprintf(s, " %dMHz", bp->bus_speed_mhz);
7461 static void __devinit
7462 bnx2_init_napi(struct bnx2 *bp)
7465 struct bnx2_napi *bnapi;
7467 for (i = 0; i < BNX2_MAX_MSIX_VEC; i++) {
7468 bnapi = &bp->bnx2_napi[i];
7471 netif_napi_add(bp->dev, &bp->bnx2_napi[0].napi, bnx2_poll, 64);
7472 netif_napi_add(bp->dev, &bp->bnx2_napi[BNX2_TX_VEC].napi, bnx2_tx_poll,
7476 static int __devinit
7477 bnx2_init_one(struct pci_dev *pdev, const struct pci_device_id *ent)
7479 static int version_printed = 0;
7480 struct net_device *dev = NULL;
7484 DECLARE_MAC_BUF(mac);
7486 if (version_printed++ == 0)
7487 printk(KERN_INFO "%s", version);
7489 /* dev zeroed in init_etherdev */
7490 dev = alloc_etherdev(sizeof(*bp));
7495 rc = bnx2_init_board(pdev, dev);
7501 dev->open = bnx2_open;
7502 dev->hard_start_xmit = bnx2_start_xmit;
7503 dev->stop = bnx2_close;
7504 dev->get_stats = bnx2_get_stats;
7505 dev->set_multicast_list = bnx2_set_rx_mode;
7506 dev->do_ioctl = bnx2_ioctl;
7507 dev->set_mac_address = bnx2_change_mac_addr;
7508 dev->change_mtu = bnx2_change_mtu;
7509 dev->tx_timeout = bnx2_tx_timeout;
7510 dev->watchdog_timeo = TX_TIMEOUT;
7512 dev->vlan_rx_register = bnx2_vlan_rx_register;
7514 dev->ethtool_ops = &bnx2_ethtool_ops;
7516 bp = netdev_priv(dev);
7519 #if defined(HAVE_POLL_CONTROLLER) || defined(CONFIG_NET_POLL_CONTROLLER)
7520 dev->poll_controller = poll_bnx2;
7523 pci_set_drvdata(pdev, dev);
7525 memcpy(dev->dev_addr, bp->mac_addr, 6);
7526 memcpy(dev->perm_addr, bp->mac_addr, 6);
7527 bp->name = board_info[ent->driver_data].name;
7529 dev->features |= NETIF_F_IP_CSUM | NETIF_F_SG;
7530 if (CHIP_NUM(bp) == CHIP_NUM_5709)
7531 dev->features |= NETIF_F_IPV6_CSUM;
7534 dev->features |= NETIF_F_HW_VLAN_TX | NETIF_F_HW_VLAN_RX;
7536 dev->features |= NETIF_F_TSO | NETIF_F_TSO_ECN;
7537 if (CHIP_NUM(bp) == CHIP_NUM_5709)
7538 dev->features |= NETIF_F_TSO6;
7540 if ((rc = register_netdev(dev))) {
7541 dev_err(&pdev->dev, "Cannot register net device\n");
7543 iounmap(bp->regview);
7544 pci_release_regions(pdev);
7545 pci_disable_device(pdev);
7546 pci_set_drvdata(pdev, NULL);
7551 printk(KERN_INFO "%s: %s (%c%d) %s found at mem %lx, "
7552 "IRQ %d, node addr %s\n",
7555 ((CHIP_ID(bp) & 0xf000) >> 12) + 'A',
7556 ((CHIP_ID(bp) & 0x0ff0) >> 4),
7557 bnx2_bus_string(bp, str),
7559 bp->pdev->irq, print_mac(mac, dev->dev_addr));
7564 static void __devexit
7565 bnx2_remove_one(struct pci_dev *pdev)
7567 struct net_device *dev = pci_get_drvdata(pdev);
7568 struct bnx2 *bp = netdev_priv(dev);
7570 flush_scheduled_work();
7572 unregister_netdev(dev);
7575 iounmap(bp->regview);
7578 pci_release_regions(pdev);
7579 pci_disable_device(pdev);
7580 pci_set_drvdata(pdev, NULL);
7584 bnx2_suspend(struct pci_dev *pdev, pm_message_t state)
7586 struct net_device *dev = pci_get_drvdata(pdev);
7587 struct bnx2 *bp = netdev_priv(dev);
7590 /* PCI register 4 needs to be saved whether netif_running() or not.
7591 * MSI address and data need to be saved if using MSI and
7594 pci_save_state(pdev);
7595 if (!netif_running(dev))
7598 flush_scheduled_work();
7599 bnx2_netif_stop(bp);
7600 netif_device_detach(dev);
7601 del_timer_sync(&bp->timer);
7602 if (bp->flags & BNX2_FLAG_NO_WOL)
7603 reset_code = BNX2_DRV_MSG_CODE_UNLOAD_LNK_DN;
7605 reset_code = BNX2_DRV_MSG_CODE_SUSPEND_WOL;
7607 reset_code = BNX2_DRV_MSG_CODE_SUSPEND_NO_WOL;
7608 bnx2_reset_chip(bp, reset_code);
7610 bnx2_set_power_state(bp, pci_choose_state(pdev, state));
7615 bnx2_resume(struct pci_dev *pdev)
7617 struct net_device *dev = pci_get_drvdata(pdev);
7618 struct bnx2 *bp = netdev_priv(dev);
7620 pci_restore_state(pdev);
7621 if (!netif_running(dev))
7624 bnx2_set_power_state(bp, PCI_D0);
7625 netif_device_attach(dev);
7626 bnx2_init_nic(bp, 1);
7627 bnx2_netif_start(bp);
7632 * bnx2_io_error_detected - called when PCI error is detected
7633 * @pdev: Pointer to PCI device
7634 * @state: The current pci connection state
7636 * This function is called after a PCI bus error affecting
7637 * this device has been detected.
7639 static pci_ers_result_t bnx2_io_error_detected(struct pci_dev *pdev,
7640 pci_channel_state_t state)
7642 struct net_device *dev = pci_get_drvdata(pdev);
7643 struct bnx2 *bp = netdev_priv(dev);
7646 netif_device_detach(dev);
7648 if (netif_running(dev)) {
7649 bnx2_netif_stop(bp);
7650 del_timer_sync(&bp->timer);
7651 bnx2_reset_nic(bp, BNX2_DRV_MSG_CODE_RESET);
7654 pci_disable_device(pdev);
7657 /* Request a slot slot reset. */
7658 return PCI_ERS_RESULT_NEED_RESET;
7662 * bnx2_io_slot_reset - called after the pci bus has been reset.
7663 * @pdev: Pointer to PCI device
7665 * Restart the card from scratch, as if from a cold-boot.
7667 static pci_ers_result_t bnx2_io_slot_reset(struct pci_dev *pdev)
7669 struct net_device *dev = pci_get_drvdata(pdev);
7670 struct bnx2 *bp = netdev_priv(dev);
7673 if (pci_enable_device(pdev)) {
7675 "Cannot re-enable PCI device after reset.\n");
7677 return PCI_ERS_RESULT_DISCONNECT;
7679 pci_set_master(pdev);
7680 pci_restore_state(pdev);
7682 if (netif_running(dev)) {
7683 bnx2_set_power_state(bp, PCI_D0);
7684 bnx2_init_nic(bp, 1);
7688 return PCI_ERS_RESULT_RECOVERED;
7692 * bnx2_io_resume - called when traffic can start flowing again.
7693 * @pdev: Pointer to PCI device
7695 * This callback is called when the error recovery driver tells us that
7696 * its OK to resume normal operation.
7698 static void bnx2_io_resume(struct pci_dev *pdev)
7700 struct net_device *dev = pci_get_drvdata(pdev);
7701 struct bnx2 *bp = netdev_priv(dev);
7704 if (netif_running(dev))
7705 bnx2_netif_start(bp);
7707 netif_device_attach(dev);
7711 static struct pci_error_handlers bnx2_err_handler = {
7712 .error_detected = bnx2_io_error_detected,
7713 .slot_reset = bnx2_io_slot_reset,
7714 .resume = bnx2_io_resume,
7717 static struct pci_driver bnx2_pci_driver = {
7718 .name = DRV_MODULE_NAME,
7719 .id_table = bnx2_pci_tbl,
7720 .probe = bnx2_init_one,
7721 .remove = __devexit_p(bnx2_remove_one),
7722 .suspend = bnx2_suspend,
7723 .resume = bnx2_resume,
7724 .err_handler = &bnx2_err_handler,
7727 static int __init bnx2_init(void)
7729 return pci_register_driver(&bnx2_pci_driver);
7732 static void __exit bnx2_cleanup(void)
7734 pci_unregister_driver(&bnx2_pci_driver);
7737 module_init(bnx2_init);
7738 module_exit(bnx2_cleanup);