drivers/net/bnx2x/bnx2x_link.c

   1 /* Copyright 2008-2009 Broadcom Corporation
   2  *
   3  * Unless you and Broadcom execute a separate written software license
   4  * agreement governing use of this software, this software is licensed to you
   5  * under the terms of the GNU General Public License version 2, available
   6  * at http://www.gnu.org/licenses/old-licenses/gpl-2.0.html (the "GPL").
   7  *
   8  * Notwithstanding the above, under no circumstances may you combine this
   9  * software in any way with any other Broadcom software provided under a
  10  * license other than the GPL, without Broadcom's express prior written
  11  * consent.
  12  *
  13  * Written by Yaniv Rosner
  14  *
  15  */
  16
  17 #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
  18
  19 #include <linux/kernel.h>
  20 #include <linux/errno.h>
  21 #include <linux/pci.h>
  22 #include <linux/netdevice.h>
  23 #include <linux/delay.h>
  24 #include <linux/ethtool.h>
  25 #include <linux/mutex.h>
  26
  27 #include "bnx2x.h"
  28
  29 /********************************************************/
  30 #define ETH_HLEN                        14
  31 #define ETH_OVREHEAD            (ETH_HLEN + 8 + 8)/* 16 for CRC + VLAN + LLC */
  32 #define ETH_MIN_PACKET_SIZE             60
  33 #define ETH_MAX_PACKET_SIZE             1500
  34 #define ETH_MAX_JUMBO_PACKET_SIZE       9600
  35 #define MDIO_ACCESS_TIMEOUT             1000
  36 #define BMAC_CONTROL_RX_ENABLE  2
  37
  38 /***********************************************************/
  39 /*                      Shortcut definitions               */
  40 /***********************************************************/
  41
  42 #define NIG_LATCH_BC_ENABLE_MI_INT 0
  43
  44 #define NIG_STATUS_EMAC0_MI_INT \
  45                 NIG_STATUS_INTERRUPT_PORT0_REG_STATUS_EMAC0_MISC_MI_INT
  46 #define NIG_STATUS_XGXS0_LINK10G \
  47                 NIG_STATUS_INTERRUPT_PORT0_REG_STATUS_XGXS0_LINK10G
  48 #define NIG_STATUS_XGXS0_LINK_STATUS \
  49                 NIG_STATUS_INTERRUPT_PORT0_REG_STATUS_XGXS0_LINK_STATUS
  50 #define NIG_STATUS_XGXS0_LINK_STATUS_SIZE \
  51                 NIG_STATUS_INTERRUPT_PORT0_REG_STATUS_XGXS0_LINK_STATUS_SIZE
  52 #define NIG_STATUS_SERDES0_LINK_STATUS \
  53                 NIG_STATUS_INTERRUPT_PORT0_REG_STATUS_SERDES0_LINK_STATUS
  54 #define NIG_MASK_MI_INT \
  55                 NIG_MASK_INTERRUPT_PORT0_REG_MASK_EMAC0_MISC_MI_INT
  56 #define NIG_MASK_XGXS0_LINK10G \
  57                 NIG_MASK_INTERRUPT_PORT0_REG_MASK_XGXS0_LINK10G
  58 #define NIG_MASK_XGXS0_LINK_STATUS \
  59                 NIG_MASK_INTERRUPT_PORT0_REG_MASK_XGXS0_LINK_STATUS
  60 #define NIG_MASK_SERDES0_LINK_STATUS \
  61                 NIG_MASK_INTERRUPT_PORT0_REG_MASK_SERDES0_LINK_STATUS
  62
  63 #define MDIO_AN_CL73_OR_37_COMPLETE \
  64                 (MDIO_GP_STATUS_TOP_AN_STATUS1_CL73_AUTONEG_COMPLETE | \
  65                  MDIO_GP_STATUS_TOP_AN_STATUS1_CL37_AUTONEG_COMPLETE)
  66
  67 #define XGXS_RESET_BITS \
  68         (MISC_REGISTERS_RESET_REG_3_MISC_NIG_MUX_XGXS0_RSTB_HW |   \
  69          MISC_REGISTERS_RESET_REG_3_MISC_NIG_MUX_XGXS0_IDDQ |      \
  70          MISC_REGISTERS_RESET_REG_3_MISC_NIG_MUX_XGXS0_PWRDWN |    \
  71          MISC_REGISTERS_RESET_REG_3_MISC_NIG_MUX_XGXS0_PWRDWN_SD | \
  72          MISC_REGISTERS_RESET_REG_3_MISC_NIG_MUX_XGXS0_TXD_FIFO_RSTB)
  73
  74 #define SERDES_RESET_BITS \
  75         (MISC_REGISTERS_RESET_REG_3_MISC_NIG_MUX_SERDES0_RSTB_HW | \
  76          MISC_REGISTERS_RESET_REG_3_MISC_NIG_MUX_SERDES0_IDDQ |    \
  77          MISC_REGISTERS_RESET_REG_3_MISC_NIG_MUX_SERDES0_PWRDWN |  \
  78          MISC_REGISTERS_RESET_REG_3_MISC_NIG_MUX_SERDES0_PWRDWN_SD)
  79
  80 #define AUTONEG_CL37            SHARED_HW_CFG_AN_ENABLE_CL37
  81 #define AUTONEG_CL73            SHARED_HW_CFG_AN_ENABLE_CL73
  82 #define AUTONEG_BAM             SHARED_HW_CFG_AN_ENABLE_BAM
  83 #define AUTONEG_PARALLEL \
  84                                 SHARED_HW_CFG_AN_ENABLE_PARALLEL_DETECTION
  85 #define AUTONEG_SGMII_FIBER_AUTODET \
  86                                 SHARED_HW_CFG_AN_EN_SGMII_FIBER_AUTO_DETECT
  87 #define AUTONEG_REMOTE_PHY      SHARED_HW_CFG_AN_ENABLE_REMOTE_PHY
  88
  89 #define GP_STATUS_PAUSE_RSOLUTION_TXSIDE \
  90                         MDIO_GP_STATUS_TOP_AN_STATUS1_PAUSE_RSOLUTION_TXSIDE
  91 #define GP_STATUS_PAUSE_RSOLUTION_RXSIDE \
  92                         MDIO_GP_STATUS_TOP_AN_STATUS1_PAUSE_RSOLUTION_RXSIDE
  93 #define GP_STATUS_SPEED_MASK \
  94                         MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_MASK
  95 #define GP_STATUS_10M   MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_10M
  96 #define GP_STATUS_100M  MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_100M
  97 #define GP_STATUS_1G    MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_1G
  98 #define GP_STATUS_2_5G  MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_2_5G
  99 #define GP_STATUS_5G    MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_5G
 100 #define GP_STATUS_6G    MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_6G
 101 #define GP_STATUS_10G_HIG \
 102                         MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_10G_HIG
 103 #define GP_STATUS_10G_CX4 \
 104                         MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_10G_CX4
 105 #define GP_STATUS_12G_HIG \
 106                         MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_12G_HIG
 107 #define GP_STATUS_12_5G MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_12_5G
 108 #define GP_STATUS_13G   MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_13G
 109 #define GP_STATUS_15G   MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_15G
 110 #define GP_STATUS_16G   MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_16G
 111 #define GP_STATUS_1G_KX MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_1G_KX
 112 #define GP_STATUS_10G_KX4 \
 113                         MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_10G_KX4
 114
 115 #define LINK_10THD                      LINK_STATUS_SPEED_AND_DUPLEX_10THD
 116 #define LINK_10TFD                      LINK_STATUS_SPEED_AND_DUPLEX_10TFD
 117 #define LINK_100TXHD            LINK_STATUS_SPEED_AND_DUPLEX_100TXHD
 118 #define LINK_100T4                      LINK_STATUS_SPEED_AND_DUPLEX_100T4
 119 #define LINK_100TXFD            LINK_STATUS_SPEED_AND_DUPLEX_100TXFD
 120 #define LINK_1000THD            LINK_STATUS_SPEED_AND_DUPLEX_1000THD
 121 #define LINK_1000TFD            LINK_STATUS_SPEED_AND_DUPLEX_1000TFD
 122 #define LINK_1000XFD            LINK_STATUS_SPEED_AND_DUPLEX_1000XFD
 123 #define LINK_2500THD            LINK_STATUS_SPEED_AND_DUPLEX_2500THD
 124 #define LINK_2500TFD            LINK_STATUS_SPEED_AND_DUPLEX_2500TFD
 125 #define LINK_2500XFD            LINK_STATUS_SPEED_AND_DUPLEX_2500XFD
 126 #define LINK_10GTFD                     LINK_STATUS_SPEED_AND_DUPLEX_10GTFD
 127 #define LINK_10GXFD                     LINK_STATUS_SPEED_AND_DUPLEX_10GXFD
 128 #define LINK_12GTFD                     LINK_STATUS_SPEED_AND_DUPLEX_12GTFD
 129 #define LINK_12GXFD                     LINK_STATUS_SPEED_AND_DUPLEX_12GXFD
 130 #define LINK_12_5GTFD           LINK_STATUS_SPEED_AND_DUPLEX_12_5GTFD
 131 #define LINK_12_5GXFD           LINK_STATUS_SPEED_AND_DUPLEX_12_5GXFD
 132 #define LINK_13GTFD                     LINK_STATUS_SPEED_AND_DUPLEX_13GTFD
 133 #define LINK_13GXFD                     LINK_STATUS_SPEED_AND_DUPLEX_13GXFD
 134 #define LINK_15GTFD                     LINK_STATUS_SPEED_AND_DUPLEX_15GTFD
 135 #define LINK_15GXFD                     LINK_STATUS_SPEED_AND_DUPLEX_15GXFD
 136 #define LINK_16GTFD                     LINK_STATUS_SPEED_AND_DUPLEX_16GTFD
 137 #define LINK_16GXFD                     LINK_STATUS_SPEED_AND_DUPLEX_16GXFD
 138
 139 #define PHY_XGXS_FLAG                   0x1
 140 #define PHY_SGMII_FLAG                  0x2
 141 #define PHY_SERDES_FLAG                 0x4
 142
 143 /* */
 144 #define SFP_EEPROM_CON_TYPE_ADDR                0x2
 145         #define SFP_EEPROM_CON_TYPE_VAL_LC              0x7
 146         #define SFP_EEPROM_CON_TYPE_VAL_COPPER  0x21
 147
 148
 149 #define SFP_EEPROM_COMP_CODE_ADDR               0x3
 150         #define SFP_EEPROM_COMP_CODE_SR_MASK    (1<<4)
 151         #define SFP_EEPROM_COMP_CODE_LR_MASK    (1<<5)
 152         #define SFP_EEPROM_COMP_CODE_LRM_MASK   (1<<6)
 153
 154 #define SFP_EEPROM_FC_TX_TECH_ADDR              0x8
 155         #define SFP_EEPROM_FC_TX_TECH_BITMASK_COPPER_PASSIVE 0x4
 156         #define SFP_EEPROM_FC_TX_TECH_BITMASK_COPPER_ACTIVE      0x8
 157
 158 #define SFP_EEPROM_OPTIONS_ADDR                 0x40
 159         #define SFP_EEPROM_OPTIONS_LINEAR_RX_OUT_MASK 0x1
 160 #define SFP_EEPROM_OPTIONS_SIZE                 2
 161
 162 #define EDC_MODE_LINEAR                         0x0022
 163 #define EDC_MODE_LIMITING                               0x0044
 164 #define EDC_MODE_PASSIVE_DAC                    0x0055
 165
 166
 167 #define ETS_BW_LIMIT_CREDIT_UPPER_BOUND         (0x5000)
 168 #define ETS_BW_LIMIT_CREDIT_WEIGHT              (0x5000)
 169 /**********************************************************/
 170 /*                     INTERFACE                          */
 171 /**********************************************************/
 172
 173 #define CL45_WR_OVER_CL22(_bp, _phy, _bank, _addr, _val) \
 174         bnx2x_cl45_write(_bp, _phy, \
 175                 (_phy)->def_md_devad, \
 176                 (_bank + (_addr & 0xf)), \
 177                 _val)
 178
 179 #define CL45_RD_OVER_CL22(_bp, _phy, _bank, _addr, _val) \
 180         bnx2x_cl45_read(_bp, _phy, \
 181                 (_phy)->def_md_devad, \
 182                 (_bank + (_addr & 0xf)), \
 183                 _val)
 184
 185 static u8 bnx2x_cl45_read(struct bnx2x *bp, struct bnx2x_phy *phy,
 186                           u8 devad, u16 reg, u16 *ret_val);
 187
 188 static u8 bnx2x_cl45_write(struct bnx2x *bp, struct bnx2x_phy *phy,
 189                            u8 devad, u16 reg, u16 val);
 190
 191 static u32 bnx2x_bits_en(struct bnx2x *bp, u32 reg, u32 bits)
 192 {
 193         u32 val = REG_RD(bp, reg);
 194
 195         val |= bits;
 196         REG_WR(bp, reg, val);
 197         return val;
 198 }
 199
 200 static u32 bnx2x_bits_dis(struct bnx2x *bp, u32 reg, u32 bits)
 201 {
 202         u32 val = REG_RD(bp, reg);
 203
 204         val &= ~bits;
 205         REG_WR(bp, reg, val);
 206         return val;
 207 }
 208
 209 /******************************************************************/
 210 /*                              ETS section                       */
 211 /******************************************************************/
 212 void bnx2x_ets_disabled(struct link_params *params)
 213 {
 214         /* ETS disabled configuration*/
 215         struct bnx2x *bp = params->bp;
 216
 217         DP(NETIF_MSG_LINK, "ETS disabled configuration\n");
 218
 219         /**
 220          * mapping between entry  priority to client number (0,1,2 -debug and
 221          * management clients, 3 - COS0 client, 4 - COS client)(HIGHEST)
 222          * 3bits client num.
 223          *   PRI4    |    PRI3    |    PRI2    |    PRI1    |    PRI0
 224          * cos1-100     cos0-011     dbg1-010     dbg0-001     MCP-000
 225          */
 226
 227         REG_WR(bp, NIG_REG_P0_TX_ARB_PRIORITY_CLIENT, 0x4688);
 228         /**
 229          * Bitmap of 5bits length. Each bit specifies whether the entry behaves
 230          * as strict.  Bits 0,1,2 - debug and management entries, 3 -
 231          * COS0 entry, 4 - COS1 entry.
 232          * COS1 | COS0 | DEBUG1 | DEBUG0 | MGMT
 233          * bit4   bit3    bit2   bit1     bit0
 234          * MCP and debug are strict
 235          */
 236
 237         REG_WR(bp, NIG_REG_P0_TX_ARB_CLIENT_IS_STRICT, 0x7);
 238         /* defines which entries (clients) are subjected to WFQ arbitration */
 239         REG_WR(bp, NIG_REG_P0_TX_ARB_CLIENT_IS_SUBJECT2WFQ, 0);
 240         /**
 241         * For strict priority entries defines the number of consecutive
 242         * slots for the highest priority.
 243         */
 244         REG_WR(bp, NIG_REG_P0_TX_ARB_NUM_STRICT_ARB_SLOTS, 0x100);
 245         /**
 246          * mapping between the CREDIT_WEIGHT registers and actual client
 247          * numbers
 248          */
 249         REG_WR(bp, NIG_REG_P0_TX_ARB_CLIENT_CREDIT_MAP, 0);
 250         REG_WR(bp, NIG_REG_P0_TX_ARB_CREDIT_WEIGHT_0, 0);
 251         REG_WR(bp, NIG_REG_P0_TX_ARB_CREDIT_WEIGHT_1, 0);
 252
 253         REG_WR(bp, NIG_REG_P0_TX_ARB_CREDIT_UPPER_BOUND_0, 0);
 254         REG_WR(bp, NIG_REG_P0_TX_ARB_CREDIT_UPPER_BOUND_1, 0);
 255         REG_WR(bp, PBF_REG_HIGH_PRIORITY_COS_NUM, 0);
 256         /* ETS mode disable */
 257         REG_WR(bp, PBF_REG_ETS_ENABLED, 0);
 258         /**
 259          * If ETS mode is enabled (there is no strict priority) defines a WFQ
 260          * weight for COS0/COS1.
 261          */
 262         REG_WR(bp, PBF_REG_COS0_WEIGHT, 0x2710);
 263         REG_WR(bp, PBF_REG_COS1_WEIGHT, 0x2710);
 264         /* Upper bound that COS0_WEIGHT can reach in the WFQ arbiter */
 265         REG_WR(bp, PBF_REG_COS0_UPPER_BOUND, 0x989680);
 266         REG_WR(bp, PBF_REG_COS1_UPPER_BOUND, 0x989680);
 267         /* Defines the number of consecutive slots for the strict priority */
 268         REG_WR(bp, PBF_REG_NUM_STRICT_ARB_SLOTS, 0);
 269 }
 270
 271 void bnx2x_ets_bw_limit_common(const struct link_params *params)
 272 {
 273         /* ETS disabled configuration */
 274         struct bnx2x *bp = params->bp;
 275         DP(NETIF_MSG_LINK, "ETS enabled BW limit configuration\n");
 276         /**
 277         * defines which entries (clients) are subjected to WFQ arbitration
 278         * COS0 0x8
 279         * COS1 0x10
 280         */
 281         REG_WR(bp, NIG_REG_P0_TX_ARB_CLIENT_IS_SUBJECT2WFQ, 0x18);
 282         /**
 283         * mapping between the ARB_CREDIT_WEIGHT registers and actual
 284         * client numbers (WEIGHT_0 does not actually have to represent
 285         * client 0)
 286         *    PRI4    |    PRI3    |    PRI2    |    PRI1    |    PRI0
 287         *  cos1-001     cos0-000     dbg1-100     dbg0-011     MCP-010
 288         */
 289         REG_WR(bp, NIG_REG_P0_TX_ARB_CLIENT_CREDIT_MAP, 0x111A);
 290
 291         REG_WR(bp, NIG_REG_P0_TX_ARB_CREDIT_UPPER_BOUND_0,
 292                ETS_BW_LIMIT_CREDIT_UPPER_BOUND);
 293         REG_WR(bp, NIG_REG_P0_TX_ARB_CREDIT_UPPER_BOUND_1,
 294                ETS_BW_LIMIT_CREDIT_UPPER_BOUND);
 295
 296         /* ETS mode enabled*/
 297         REG_WR(bp, PBF_REG_ETS_ENABLED, 1);
 298
 299         /* Defines the number of consecutive slots for the strict priority */
 300         REG_WR(bp, PBF_REG_NUM_STRICT_ARB_SLOTS, 0);
 301         /**
 302         * Bitmap of 5bits length. Each bit specifies whether the entry behaves
 303         * as strict.  Bits 0,1,2 - debug and management entries, 3 - COS0
 304         * entry, 4 - COS1 entry.
 305         * COS1 | COS0 | DEBUG21 | DEBUG0 | MGMT
 306         * bit4   bit3     bit2     bit1    bit0
 307         * MCP and debug are strict
 308         */
 309         REG_WR(bp, NIG_REG_P0_TX_ARB_CLIENT_IS_STRICT, 0x7);
 310
 311         /* Upper bound that COS0_WEIGHT can reach in the WFQ arbiter.*/
 312         REG_WR(bp, PBF_REG_COS0_UPPER_BOUND,
 313                ETS_BW_LIMIT_CREDIT_UPPER_BOUND);
 314         REG_WR(bp, PBF_REG_COS1_UPPER_BOUND,
 315                ETS_BW_LIMIT_CREDIT_UPPER_BOUND);
 316 }
 317
 318 void bnx2x_ets_bw_limit(const struct link_params *params, const u32 cos0_bw,
 319                         const u32 cos1_bw)
 320 {
 321         /* ETS disabled configuration*/
 322         struct bnx2x *bp = params->bp;
 323         const u32 total_bw = cos0_bw + cos1_bw;
 324         u32 cos0_credit_weight = 0;
 325         u32 cos1_credit_weight = 0;
 326
 327         DP(NETIF_MSG_LINK, "ETS enabled BW limit configuration\n");
 328
 329         if ((0 == total_bw) ||
 330             (0 == cos0_bw) ||
 331             (0 == cos1_bw)) {
 332                 DP(NETIF_MSG_LINK,
 333                    "bnx2x_ets_bw_limit: Total BW can't be zero\n");
 334                 return;
 335         }
 336
 337         cos0_credit_weight = (cos0_bw * ETS_BW_LIMIT_CREDIT_WEIGHT)/
 338                 total_bw;
 339         cos1_credit_weight = (cos1_bw * ETS_BW_LIMIT_CREDIT_WEIGHT)/
 340                 total_bw;
 341
 342         bnx2x_ets_bw_limit_common(params);
 343
 344         REG_WR(bp, NIG_REG_P0_TX_ARB_CREDIT_WEIGHT_0, cos0_credit_weight);
 345         REG_WR(bp, NIG_REG_P0_TX_ARB_CREDIT_WEIGHT_1, cos1_credit_weight);
 346
 347         REG_WR(bp, PBF_REG_COS0_WEIGHT, cos0_credit_weight);
 348         REG_WR(bp, PBF_REG_COS1_WEIGHT, cos1_credit_weight);
 349 }
 350
 351 u8 bnx2x_ets_strict(const struct link_params *params, const u8 strict_cos)
 352 {
 353         /* ETS disabled configuration*/
 354         struct bnx2x *bp = params->bp;
 355         u32 val = 0;
 356
 357         DP(NETIF_MSG_LINK, "ETS enabled strict configuration\n");
 358         /**
 359          * Bitmap of 5bits length. Each bit specifies whether the entry behaves
 360          * as strict.  Bits 0,1,2 - debug and management entries,
 361          * 3 - COS0 entry, 4 - COS1 entry.
 362          *  COS1 | COS0 | DEBUG21 | DEBUG0 | MGMT
 363          *  bit4   bit3   bit2      bit1     bit0
 364          * MCP and debug are strict
 365          */
 366         REG_WR(bp, NIG_REG_P0_TX_ARB_CLIENT_IS_STRICT, 0x1F);
 367         /**
 368          * For strict priority entries defines the number of consecutive slots
 369          * for the highest priority.
 370          */
 371         REG_WR(bp, NIG_REG_P0_TX_ARB_NUM_STRICT_ARB_SLOTS, 0x100);
 372         /* ETS mode disable */
 373         REG_WR(bp, PBF_REG_ETS_ENABLED, 0);
 374         /* Defines the number of consecutive slots for the strict priority */
 375         REG_WR(bp, PBF_REG_NUM_STRICT_ARB_SLOTS, 0x100);
 376
 377         /* Defines the number of consecutive slots for the strict priority */
 378         REG_WR(bp, PBF_REG_HIGH_PRIORITY_COS_NUM, strict_cos);
 379
 380         /**
 381         * mapping between entry  priority to client number (0,1,2 -debug and
 382         * management clients, 3 - COS0 client, 4 - COS client)(HIGHEST)
 383         * 3bits client num.
 384         *   PRI4    |    PRI3    |    PRI2    |    PRI1    |    PRI0
 385         * dbg0-010     dbg1-001     cos1-100     cos0-011     MCP-000
 386         * dbg0-010     dbg1-001     cos0-011     cos1-100     MCP-000
 387         */
 388         val = (0 == strict_cos) ? 0x2318 : 0x22E0;
 389         REG_WR(bp, NIG_REG_P0_TX_ARB_PRIORITY_CLIENT, val);
 390
 391         return 0;
 392 }
 393 /******************************************************************/
 394 /*                      ETS section                               */
 395 /******************************************************************/
 396
 397 static void bnx2x_bmac2_get_pfc_stat(struct link_params *params,
 398                                      u32 pfc_frames_sent[2],
 399                                      u32 pfc_frames_received[2])
 400 {
 401         /* Read pfc statistic */
 402         struct bnx2x *bp = params->bp;
 403         u32 bmac_addr = params->port ? NIG_REG_INGRESS_BMAC1_MEM :
 404                 NIG_REG_INGRESS_BMAC0_MEM;
 405
 406         DP(NETIF_MSG_LINK, "pfc statistic read from BMAC\n");
 407
 408         REG_RD_DMAE(bp, bmac_addr + BIGMAC2_REGISTER_TX_STAT_GTPP,
 409                                         pfc_frames_sent, 2);
 410
 411         REG_RD_DMAE(bp, bmac_addr + BIGMAC2_REGISTER_RX_STAT_GRPP,
 412                                         pfc_frames_received, 2);
 413
 414 }
 415 static void bnx2x_emac_get_pfc_stat(struct link_params *params,
 416                                     u32 pfc_frames_sent[2],
 417                                     u32 pfc_frames_received[2])
 418 {
 419         /* Read pfc statistic */
 420         struct bnx2x *bp = params->bp;
 421         u32 emac_base = params->port ? GRCBASE_EMAC1 : GRCBASE_EMAC0;
 422         u32 val_xon = 0;
 423         u32 val_xoff = 0;
 424
 425         DP(NETIF_MSG_LINK, "pfc statistic read from EMAC\n");
 426
 427         /* PFC received frames */
 428         val_xoff = REG_RD(bp, emac_base +
 429                                 EMAC_REG_RX_PFC_STATS_XOFF_RCVD);
 430         val_xoff &= EMAC_REG_RX_PFC_STATS_XOFF_RCVD_COUNT;
 431         val_xon = REG_RD(bp, emac_base + EMAC_REG_RX_PFC_STATS_XON_RCVD);
 432         val_xon &= EMAC_REG_RX_PFC_STATS_XON_RCVD_COUNT;
 433
 434         pfc_frames_received[0] = val_xon + val_xoff;
 435
 436         /* PFC received sent */
 437         val_xoff = REG_RD(bp, emac_base +
 438                                 EMAC_REG_RX_PFC_STATS_XOFF_SENT);
 439         val_xoff &= EMAC_REG_RX_PFC_STATS_XOFF_SENT_COUNT;
 440         val_xon = REG_RD(bp, emac_base + EMAC_REG_RX_PFC_STATS_XON_SENT);
 441         val_xon &= EMAC_REG_RX_PFC_STATS_XON_SENT_COUNT;
 442
 443         pfc_frames_sent[0] = val_xon + val_xoff;
 444 }
 445
 446 void bnx2x_pfc_statistic(struct link_params *params, struct link_vars *vars,
 447                          u32 pfc_frames_sent[2],
 448                          u32 pfc_frames_received[2])
 449 {
 450         /* Read pfc statistic */
 451         struct bnx2x *bp = params->bp;
 452         u32 val = 0;
 453         DP(NETIF_MSG_LINK, "pfc statistic\n");
 454
 455         if (!vars->link_up)
 456                 return;
 457
 458         val = REG_RD(bp, MISC_REG_RESET_REG_2);
 459         if ((val & (MISC_REGISTERS_RESET_REG_2_RST_BMAC0 << params->port))
 460             == 0) {
 461                 DP(NETIF_MSG_LINK, "About to read stats from EMAC\n");
 462                 bnx2x_emac_get_pfc_stat(params, pfc_frames_sent,
 463                                         pfc_frames_received);
 464         } else {
 465                 DP(NETIF_MSG_LINK, "About to read stats from BMAC\n");
 466                 bnx2x_bmac2_get_pfc_stat(params, pfc_frames_sent,
 467                                          pfc_frames_received);
 468         }
 469 }
 470 /******************************************************************/
 471 /*                      MAC/PBF section                           */
 472 /******************************************************************/
 473 static void bnx2x_emac_init(struct link_params *params,
 474                            struct link_vars *vars)
 475 {
 476         /* reset and unreset the emac core */
 477         struct bnx2x *bp = params->bp;
 478         u8 port = params->port;
 479         u32 emac_base = port ? GRCBASE_EMAC1 : GRCBASE_EMAC0;
 480         u32 val;
 481         u16 timeout;
 482
 483         REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_2_CLEAR,
 484                    (MISC_REGISTERS_RESET_REG_2_RST_EMAC0_HARD_CORE << port));
 485         udelay(5);
 486         REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_2_SET,
 487                    (MISC_REGISTERS_RESET_REG_2_RST_EMAC0_HARD_CORE << port));
 488
 489         /* init emac - use read-modify-write */
 490         /* self clear reset */
 491         val = REG_RD(bp, emac_base + EMAC_REG_EMAC_MODE);
 492         EMAC_WR(bp, EMAC_REG_EMAC_MODE, (val | EMAC_MODE_RESET));
 493
 494         timeout = 200;
 495         do {
 496                 val = REG_RD(bp, emac_base + EMAC_REG_EMAC_MODE);
 497                 DP(NETIF_MSG_LINK, "EMAC reset reg is %u\n", val);
 498                 if (!timeout) {
 499                         DP(NETIF_MSG_LINK, "EMAC timeout!\n");
 500                         return;
 501                 }
 502                 timeout--;
 503         } while (val & EMAC_MODE_RESET);
 504
 505         /* Set mac address */
 506         val = ((params->mac_addr[0] << 8) |
 507                 params->mac_addr[1]);
 508         EMAC_WR(bp, EMAC_REG_EMAC_MAC_MATCH, val);
 509
 510         val = ((params->mac_addr[2] << 24) |
 511                (params->mac_addr[3] << 16) |
 512                (params->mac_addr[4] << 8) |
 513                 params->mac_addr[5]);
 514         EMAC_WR(bp, EMAC_REG_EMAC_MAC_MATCH + 4, val);
 515 }
 516
 517 static u8 bnx2x_emac_enable(struct link_params *params,
 518                           struct link_vars *vars, u8 lb)
 519 {
 520         struct bnx2x *bp = params->bp;
 521         u8 port = params->port;
 522         u32 emac_base = port ? GRCBASE_EMAC1 : GRCBASE_EMAC0;
 523         u32 val;
 524
 525         DP(NETIF_MSG_LINK, "enabling EMAC\n");
 526
 527         /* enable emac and not bmac */
 528         REG_WR(bp, NIG_REG_EGRESS_EMAC0_PORT + port*4, 1);
 529
 530         /* for paladium */
 531         if (CHIP_REV_IS_EMUL(bp)) {
 532                 /* Use lane 1 (of lanes 0-3) */
 533                 REG_WR(bp, NIG_REG_XGXS_LANE_SEL_P0 + port*4, 1);
 534                 REG_WR(bp, NIG_REG_XGXS_SERDES0_MODE_SEL +
 535                             port*4, 1);
 536         }
 537         /* for fpga */
 538         else
 539
 540         if (CHIP_REV_IS_FPGA(bp)) {
 541                 /* Use lane 1 (of lanes 0-3) */
 542                 DP(NETIF_MSG_LINK, "bnx2x_emac_enable: Setting FPGA\n");
 543
 544                 REG_WR(bp, NIG_REG_XGXS_LANE_SEL_P0 + port*4, 1);
 545                 REG_WR(bp, NIG_REG_XGXS_SERDES0_MODE_SEL + port*4,
 546                             0);
 547         } else
 548         /* ASIC */
 549         if (vars->phy_flags & PHY_XGXS_FLAG) {
 550                 u32 ser_lane = ((params->lane_config &
 551                             PORT_HW_CFG_LANE_SWAP_CFG_MASTER_MASK) >>
 552                             PORT_HW_CFG_LANE_SWAP_CFG_MASTER_SHIFT);
 553
 554                 DP(NETIF_MSG_LINK, "XGXS\n");
 555                 /* select the master lanes (out of 0-3) */
 556                 REG_WR(bp, NIG_REG_XGXS_LANE_SEL_P0 +
 557                            port*4, ser_lane);
 558                 /* select XGXS */
 559                 REG_WR(bp, NIG_REG_XGXS_SERDES0_MODE_SEL +
 560                            port*4, 1);
 561
 562         } else { /* SerDes */
 563                 DP(NETIF_MSG_LINK, "SerDes\n");
 564                 /* select SerDes */
 565                 REG_WR(bp, NIG_REG_XGXS_SERDES0_MODE_SEL +
 566                            port*4, 0);
 567         }
 568
 569         bnx2x_bits_en(bp, emac_base + EMAC_REG_EMAC_RX_MODE,
 570                     EMAC_RX_MODE_RESET);
 571         bnx2x_bits_en(bp, emac_base + EMAC_REG_EMAC_TX_MODE,
 572                     EMAC_TX_MODE_RESET);
 573
 574         if (CHIP_REV_IS_SLOW(bp)) {
 575                 /* config GMII mode */
 576                 val = REG_RD(bp, emac_base + EMAC_REG_EMAC_MODE);
 577                 EMAC_WR(bp, EMAC_REG_EMAC_MODE,
 578                             (val | EMAC_MODE_PORT_GMII));
 579         } else { /* ASIC */
 580                 /* pause enable/disable */
 581                 bnx2x_bits_dis(bp, emac_base + EMAC_REG_EMAC_RX_MODE,
 582                                EMAC_RX_MODE_FLOW_EN);
 583
 584                 bnx2x_bits_dis(bp,  emac_base + EMAC_REG_EMAC_TX_MODE,
 585                                (EMAC_TX_MODE_EXT_PAUSE_EN |
 586                                 EMAC_TX_MODE_FLOW_EN));
 587                 if (!(params->feature_config_flags &
 588                       FEATURE_CONFIG_PFC_ENABLED)) {
 589                         if (vars->flow_ctrl & BNX2X_FLOW_CTRL_RX)
 590                                 bnx2x_bits_en(bp, emac_base +
 591                                               EMAC_REG_EMAC_RX_MODE,
 592                                               EMAC_RX_MODE_FLOW_EN);
 593
 594                         if (vars->flow_ctrl & BNX2X_FLOW_CTRL_TX)
 595                                 bnx2x_bits_en(bp, emac_base +
 596                                               EMAC_REG_EMAC_TX_MODE,
 597                                               (EMAC_TX_MODE_EXT_PAUSE_EN |
 598                                                EMAC_TX_MODE_FLOW_EN));
 599                 } else
 600                         bnx2x_bits_en(bp, emac_base + EMAC_REG_EMAC_TX_MODE,
 601                                       EMAC_TX_MODE_FLOW_EN);
 602         }
 603
 604         /* KEEP_VLAN_TAG, promiscuous */
 605         val = REG_RD(bp, emac_base + EMAC_REG_EMAC_RX_MODE);
 606         val |= EMAC_RX_MODE_KEEP_VLAN_TAG | EMAC_RX_MODE_PROMISCUOUS;
 607
 608         /**
 609         * Setting this bit causes MAC control frames (except for pause
 610         * frames) to be passed on for processing. This setting has no
 611         * affect on the operation of the pause frames. This bit effects
 612         * all packets regardless of RX Parser packet sorting logic.
 613         * Turn the PFC off to make sure we are in Xon state before
 614         * enabling it.
 615         */
 616         EMAC_WR(bp, EMAC_REG_RX_PFC_MODE, 0);
 617         if (params->feature_config_flags & FEATURE_CONFIG_PFC_ENABLED) {
 618                 DP(NETIF_MSG_LINK, "PFC is enabled\n");
 619                 /* Enable PFC again */
 620                 EMAC_WR(bp, EMAC_REG_RX_PFC_MODE,
 621                         EMAC_REG_RX_PFC_MODE_RX_EN |
 622                         EMAC_REG_RX_PFC_MODE_TX_EN |
 623                         EMAC_REG_RX_PFC_MODE_PRIORITIES);
 624
 625                 EMAC_WR(bp, EMAC_REG_RX_PFC_PARAM,
 626                         ((0x0101 <<
 627                           EMAC_REG_RX_PFC_PARAM_OPCODE_BITSHIFT) |
 628                          (0x00ff <<
 629                           EMAC_REG_RX_PFC_PARAM_PRIORITY_EN_BITSHIFT)));
 630                 val |= EMAC_RX_MODE_KEEP_MAC_CONTROL;
 631         }
 632         EMAC_WR(bp, EMAC_REG_EMAC_RX_MODE, val);
 633
 634         /* Set Loopback */
 635         val = REG_RD(bp, emac_base + EMAC_REG_EMAC_MODE);
 636         if (lb)
 637                 val |= 0x810;
 638         else
 639                 val &= ~0x810;
 640         EMAC_WR(bp, EMAC_REG_EMAC_MODE, val);
 641
 642         /* enable emac */
 643         REG_WR(bp, NIG_REG_NIG_EMAC0_EN + port*4, 1);
 644
 645         /* enable emac for jumbo packets */
 646         EMAC_WR(bp, EMAC_REG_EMAC_RX_MTU_SIZE,
 647                 (EMAC_RX_MTU_SIZE_JUMBO_ENA |
 648                  (ETH_MAX_JUMBO_PACKET_SIZE + ETH_OVREHEAD)));
 649
 650         /* strip CRC */
 651         REG_WR(bp, NIG_REG_NIG_INGRESS_EMAC0_NO_CRC + port*4, 0x1);
 652
 653         /* disable the NIG in/out to the bmac */
 654         REG_WR(bp, NIG_REG_BMAC0_IN_EN + port*4, 0x0);
 655         REG_WR(bp, NIG_REG_BMAC0_PAUSE_OUT_EN + port*4, 0x0);
 656         REG_WR(bp, NIG_REG_BMAC0_OUT_EN + port*4, 0x0);
 657
 658         /* enable the NIG in/out to the emac */
 659         REG_WR(bp, NIG_REG_EMAC0_IN_EN + port*4, 0x1);
 660         val = 0;
 661         if ((params->feature_config_flags &
 662               FEATURE_CONFIG_PFC_ENABLED) ||
 663             (vars->flow_ctrl & BNX2X_FLOW_CTRL_TX))
 664                 val = 1;
 665
 666         REG_WR(bp, NIG_REG_EMAC0_PAUSE_OUT_EN + port*4, val);
 667         REG_WR(bp, NIG_REG_EGRESS_EMAC0_OUT_EN + port*4, 0x1);
 668
 669         if (CHIP_REV_IS_EMUL(bp)) {
 670                 /* take the BigMac out of reset */
 671                 REG_WR(bp,
 672                            GRCBASE_MISC + MISC_REGISTERS_RESET_REG_2_SET,
 673                            (MISC_REGISTERS_RESET_REG_2_RST_BMAC0 << port));
 674
 675                 /* enable access for bmac registers */
 676                 REG_WR(bp, NIG_REG_BMAC0_REGS_OUT_EN + port*4, 0x1);
 677         } else
 678                 REG_WR(bp, NIG_REG_BMAC0_REGS_OUT_EN + port*4, 0x0);
 679
 680         vars->mac_type = MAC_TYPE_EMAC;
 681         return 0;
 682 }
 683
 684 static void bnx2x_update_pfc_bmac1(struct link_params *params,
 685                                    struct link_vars *vars)
 686 {
 687         u32 wb_data[2];
 688         struct bnx2x *bp = params->bp;
 689         u32 bmac_addr =  params->port ? NIG_REG_INGRESS_BMAC1_MEM :
 690                 NIG_REG_INGRESS_BMAC0_MEM;
 691
 692         u32 val = 0x14;
 693         if ((!(params->feature_config_flags &
 694               FEATURE_CONFIG_PFC_ENABLED)) &&
 695                 (vars->flow_ctrl & BNX2X_FLOW_CTRL_RX))
 696                 /* Enable BigMAC to react on received Pause packets */
 697                 val |= (1<<5);
 698         wb_data[0] = val;
 699         wb_data[1] = 0;
 700         REG_WR_DMAE(bp, bmac_addr + BIGMAC_REGISTER_RX_CONTROL, wb_data, 2);
 701
 702         /* tx control */
 703         val = 0xc0;
 704         if (!(params->feature_config_flags &
 705               FEATURE_CONFIG_PFC_ENABLED) &&
 706                 (vars->flow_ctrl & BNX2X_FLOW_CTRL_TX))
 707                 val |= 0x800000;
 708         wb_data[0] = val;
 709         wb_data[1] = 0;
 710         REG_WR_DMAE(bp, bmac_addr + BIGMAC_REGISTER_TX_CONTROL, wb_data, 2);
 711 }
 712
 713 static void bnx2x_update_pfc_bmac2(struct link_params *params,
 714                                    struct link_vars *vars,
 715                                    u8 is_lb)
 716 {
 717         /*
 718          * Set rx control: Strip CRC and enable BigMAC to relay
 719          * control packets to the system as well
 720          */
 721         u32 wb_data[2];
 722         struct bnx2x *bp = params->bp;
 723         u32 bmac_addr = params->port ? NIG_REG_INGRESS_BMAC1_MEM :
 724                 NIG_REG_INGRESS_BMAC0_MEM;
 725         u32 val = 0x14;
 726
 727         if ((!(params->feature_config_flags &
 728               FEATURE_CONFIG_PFC_ENABLED)) &&
 729                 (vars->flow_ctrl & BNX2X_FLOW_CTRL_RX))
 730                 /* Enable BigMAC to react on received Pause packets */
 731                 val |= (1<<5);
 732         wb_data[0] = val;
 733         wb_data[1] = 0;
 734         REG_WR_DMAE(bp, bmac_addr + BIGMAC2_REGISTER_RX_CONTROL,
 735                         wb_data, 2);
 736         udelay(30);
 737
 738         /* Tx control */
 739         val = 0xc0;
 740         if (!(params->feature_config_flags &
 741                                 FEATURE_CONFIG_PFC_ENABLED) &&
 742             (vars->flow_ctrl & BNX2X_FLOW_CTRL_TX))
 743                 val |= 0x800000;
 744         wb_data[0] = val;
 745         wb_data[1] = 0;
 746         REG_WR_DMAE(bp, bmac_addr + BIGMAC2_REGISTER_TX_CONTROL, wb_data, 2);
 747
 748         if (params->feature_config_flags & FEATURE_CONFIG_PFC_ENABLED) {
 749                 DP(NETIF_MSG_LINK, "PFC is enabled\n");
 750                 /* Enable PFC RX & TX & STATS and set 8 COS  */
 751                 wb_data[0] = 0x0;
 752                 wb_data[0] |= (1<<0);  /* RX */
 753                 wb_data[0] |= (1<<1);  /* TX */
 754                 wb_data[0] |= (1<<2);  /* Force initial Xon */
 755                 wb_data[0] |= (1<<3);  /* 8 cos */
 756                 wb_data[0] |= (1<<5);  /* STATS */
 757                 wb_data[1] = 0;
 758                 REG_WR_DMAE(bp, bmac_addr + BIGMAC2_REGISTER_PFC_CONTROL,
 759                             wb_data, 2);
 760                 /* Clear the force Xon */
 761                 wb_data[0] &= ~(1<<2);
 762         } else {
 763                 DP(NETIF_MSG_LINK, "PFC is disabled\n");
 764                 /* disable PFC RX & TX & STATS and set 8 COS */
 765                 wb_data[0] = 0x8;
 766                 wb_data[1] = 0;
 767         }
 768
 769         REG_WR_DMAE(bp, bmac_addr + BIGMAC2_REGISTER_PFC_CONTROL, wb_data, 2);
 770
 771         /**
 772         * Set Time (based unit is 512 bit time) between automatic
 773         * re-sending of PP packets amd enable automatic re-send of
 774         * Per-Priroity Packet as long as pp_gen is asserted and
 775         * pp_disable is low.
 776         */
 777         val = 0x8000;
 778         if (params->feature_config_flags & FEATURE_CONFIG_PFC_ENABLED)
 779                 val |= (1<<16); /* enable automatic re-send */
 780
 781         wb_data[0] = val;
 782         wb_data[1] = 0;
 783         REG_WR_DMAE(bp, bmac_addr + BIGMAC2_REGISTER_TX_PAUSE_CONTROL,
 784                         wb_data, 2);
 785
 786         /* mac control */
 787         val = 0x3; /* Enable RX and TX */
 788         if (is_lb) {
 789                 val |= 0x4; /* Local loopback */
 790                 DP(NETIF_MSG_LINK, "enable bmac loopback\n");
 791         }
 792         /* When PFC enabled, Pass pause frames towards the NIG. */
 793         if (params->feature_config_flags & FEATURE_CONFIG_PFC_ENABLED)
 794                 val |= ((1<<6)|(1<<5));
 795
 796         wb_data[0] = val;
 797         wb_data[1] = 0;
 798         REG_WR_DMAE(bp, bmac_addr + BIGMAC2_REGISTER_BMAC_CONTROL,
 799                         wb_data, 2);
 800 }
 801
 802 static void bnx2x_update_pfc_brb(struct link_params *params,
 803                 struct link_vars *vars,
 804                 struct bnx2x_nig_brb_pfc_port_params *pfc_params)
 805 {
 806         struct bnx2x *bp = params->bp;
 807         int set_pfc = params->feature_config_flags &
 808                 FEATURE_CONFIG_PFC_ENABLED;
 809
 810         /* default - pause configuration */
 811         u32 pause_xoff_th = PFC_BRB_MAC_PAUSE_XOFF_THRESHOLD_PAUSEABLE;
 812         u32 pause_xon_th = PFC_BRB_MAC_PAUSE_XON_THRESHOLD_PAUSEABLE;
 813         u32 full_xoff_th = PFC_BRB_MAC_FULL_XOFF_THRESHOLD_PAUSEABLE;
 814         u32 full_xon_th = PFC_BRB_MAC_FULL_XON_THRESHOLD_PAUSEABLE;
 815
 816         if (set_pfc && pfc_params)
 817                 /* First COS */
 818                 if (!pfc_params->cos0_pauseable) {
 819                         pause_xoff_th =
 820                           PFC_BRB_MAC_PAUSE_XOFF_THRESHOLD_NON_PAUSEABLE;
 821                         pause_xon_th =
 822                           PFC_BRB_MAC_PAUSE_XON_THRESHOLD_NON_PAUSEABLE;
 823                         full_xoff_th =
 824                           PFC_BRB_MAC_FULL_XOFF_THRESHOLD_NON_PAUSEABLE;
 825                         full_xon_th =
 826                           PFC_BRB_MAC_FULL_XON_THRESHOLD_NON_PAUSEABLE;
 827                 }
 828         /* The number of free blocks below which the pause signal to class 0
 829            of MAC #n is asserted. n=0,1 */
 830         REG_WR(bp, BRB1_REG_PAUSE_0_XOFF_THRESHOLD_0 , pause_xoff_th);
 831         /* The number of free blocks above which the pause signal to class 0
 832            of MAC #n is de-asserted. n=0,1 */
 833         REG_WR(bp, BRB1_REG_PAUSE_0_XON_THRESHOLD_0 , pause_xon_th);
 834         /* The number of free blocks below which the full signal to class 0
 835            of MAC #n is asserted. n=0,1 */
 836         REG_WR(bp, BRB1_REG_FULL_0_XOFF_THRESHOLD_0 , full_xoff_th);
 837         /* The number of free blocks above which the full signal to class 0
 838            of MAC #n is de-asserted. n=0,1 */
 839         REG_WR(bp, BRB1_REG_FULL_0_XON_THRESHOLD_0 , full_xon_th);
 840
 841         if (set_pfc && pfc_params) {
 842                 /* Second COS */
 843                 if (pfc_params->cos1_pauseable) {
 844                         pause_xoff_th =
 845                           PFC_BRB_MAC_PAUSE_XOFF_THRESHOLD_PAUSEABLE;
 846                         pause_xon_th =
 847                           PFC_BRB_MAC_PAUSE_XON_THRESHOLD_PAUSEABLE;
 848                         full_xoff_th =
 849                           PFC_BRB_MAC_FULL_XOFF_THRESHOLD_PAUSEABLE;
 850                         full_xon_th =
 851                           PFC_BRB_MAC_FULL_XON_THRESHOLD_PAUSEABLE;
 852                 } else {
 853                         pause_xoff_th =
 854                           PFC_BRB_MAC_PAUSE_XOFF_THRESHOLD_NON_PAUSEABLE;
 855                         pause_xon_th =
 856                           PFC_BRB_MAC_PAUSE_XON_THRESHOLD_NON_PAUSEABLE;
 857                         full_xoff_th =
 858                           PFC_BRB_MAC_FULL_XOFF_THRESHOLD_NON_PAUSEABLE;
 859                         full_xon_th =
 860                           PFC_BRB_MAC_FULL_XON_THRESHOLD_NON_PAUSEABLE;
 861                 }
 862                 /**
 863                  * The number of free blocks below which the pause signal to
 864                  * class 1 of MAC #n is asserted. n=0,1
 865                  **/
 866                 REG_WR(bp, BRB1_REG_PAUSE_1_XOFF_THRESHOLD_0, pause_xoff_th);
 867                 /**
 868                  * The number of free blocks above which the pause signal to
 869                  * class 1 of MAC #n is de-asserted. n=0,1
 870                  **/
 871                 REG_WR(bp, BRB1_REG_PAUSE_1_XON_THRESHOLD_0, pause_xon_th);
 872                 /**
 873                  * The number of free blocks below which the full signal to
 874                  * class 1 of MAC #n is asserted. n=0,1
 875                  **/
 876                 REG_WR(bp, BRB1_REG_FULL_1_XOFF_THRESHOLD_0, full_xoff_th);
 877                 /**
 878                  * The number of free blocks above which the full signal to
 879                  * class 1 of MAC #n is de-asserted. n=0,1
 880                  **/
 881                 REG_WR(bp, BRB1_REG_FULL_1_XON_THRESHOLD_0, full_xon_th);
 882         }
 883 }
 884
 885 static void bnx2x_update_pfc_nig(struct link_params *params,
 886                 struct link_vars *vars,
 887                 struct bnx2x_nig_brb_pfc_port_params *nig_params)
 888 {
 889         u32 xcm_mask = 0, ppp_enable = 0, pause_enable = 0, llfc_out_en = 0;
 890         u32 llfc_enable = 0, xcm0_out_en = 0, p0_hwpfc_enable = 0;
 891         u32 pkt_priority_to_cos = 0;
 892         u32 val;
 893         struct bnx2x *bp = params->bp;
 894         int port = params->port;
 895         int set_pfc = params->feature_config_flags &
 896                 FEATURE_CONFIG_PFC_ENABLED;
 897         DP(NETIF_MSG_LINK, "updating pfc nig parameters\n");
 898
 899         /**
 900          * When NIG_LLH0_XCM_MASK_REG_LLHX_XCM_MASK_BCN bit is set
 901          * MAC control frames (that are not pause packets)
 902          * will be forwarded to the XCM.
 903          */
 904         xcm_mask = REG_RD(bp,
 905                                 port ? NIG_REG_LLH1_XCM_MASK :
 906                                 NIG_REG_LLH0_XCM_MASK);
 907         /**
 908          * nig params will override non PFC params, since it's possible to
 909          * do transition from PFC to SAFC
 910          */
 911         if (set_pfc) {
 912                 pause_enable = 0;
 913                 llfc_out_en = 0;
 914                 llfc_enable = 0;
 915                 ppp_enable = 1;
 916                 xcm_mask &= ~(port ? NIG_LLH1_XCM_MASK_REG_LLH1_XCM_MASK_BCN :
 917                                      NIG_LLH0_XCM_MASK_REG_LLH0_XCM_MASK_BCN);
 918                 xcm0_out_en = 0;
 919                 p0_hwpfc_enable = 1;
 920         } else  {
 921                 if (nig_params) {
 922                         llfc_out_en = nig_params->llfc_out_en;
 923                         llfc_enable = nig_params->llfc_enable;
 924                         pause_enable = nig_params->pause_enable;
 925                 } else  /*defaul non PFC mode - PAUSE */
 926                         pause_enable = 1;
 927
 928                 xcm_mask |= (port ? NIG_LLH1_XCM_MASK_REG_LLH1_XCM_MASK_BCN :
 929                         NIG_LLH0_XCM_MASK_REG_LLH0_XCM_MASK_BCN);
 930                 xcm0_out_en = 1;
 931         }
 932
 933         REG_WR(bp, port ? NIG_REG_LLFC_OUT_EN_1 :
 934                NIG_REG_LLFC_OUT_EN_0, llfc_out_en);
 935         REG_WR(bp, port ? NIG_REG_LLFC_ENABLE_1 :
 936                NIG_REG_LLFC_ENABLE_0, llfc_enable);
 937         REG_WR(bp, port ? NIG_REG_PAUSE_ENABLE_1 :
 938                NIG_REG_PAUSE_ENABLE_0, pause_enable);
 939
 940         REG_WR(bp, port ? NIG_REG_PPP_ENABLE_1 :
 941                NIG_REG_PPP_ENABLE_0, ppp_enable);
 942
 943         REG_WR(bp, port ? NIG_REG_LLH1_XCM_MASK :
 944                NIG_REG_LLH0_XCM_MASK, xcm_mask);
 945
 946         REG_WR(bp,  NIG_REG_LLFC_EGRESS_SRC_ENABLE_0, 0x7);
 947
 948         /* output enable for RX_XCM # IF */
 949         REG_WR(bp, NIG_REG_XCM0_OUT_EN, xcm0_out_en);
 950
 951         /* HW PFC TX enable */
 952         REG_WR(bp, NIG_REG_P0_HWPFC_ENABLE, p0_hwpfc_enable);
 953
 954         /* 0x2 = BMAC, 0x1= EMAC */
 955         switch (vars->mac_type) {
 956         case MAC_TYPE_EMAC:
 957                 val = 1;
 958                 break;
 959         case MAC_TYPE_BMAC:
 960                 val = 0;
 961                 break;
 962         default:
 963                 val = 0;
 964                 break;
 965         }
 966         REG_WR(bp, NIG_REG_EGRESS_EMAC0_PORT, val);
 967
 968         if (nig_params) {
 969                 pkt_priority_to_cos = nig_params->pkt_priority_to_cos;
 970
 971                 REG_WR(bp, port ? NIG_REG_P1_RX_COS0_PRIORITY_MASK :
 972                        NIG_REG_P0_RX_COS0_PRIORITY_MASK,
 973                        nig_params->rx_cos0_priority_mask);
 974
 975                 REG_WR(bp, port ? NIG_REG_P1_RX_COS1_PRIORITY_MASK :
 976                        NIG_REG_P0_RX_COS1_PRIORITY_MASK,
 977                        nig_params->rx_cos1_priority_mask);
 978
 979                 REG_WR(bp, port ? NIG_REG_LLFC_HIGH_PRIORITY_CLASSES_1 :
 980                        NIG_REG_LLFC_HIGH_PRIORITY_CLASSES_0,
 981                        nig_params->llfc_high_priority_classes);
 982
 983                 REG_WR(bp, port ? NIG_REG_LLFC_LOW_PRIORITY_CLASSES_1 :
 984                        NIG_REG_LLFC_LOW_PRIORITY_CLASSES_0,
 985                        nig_params->llfc_low_priority_classes);
 986         }
 987         REG_WR(bp, port ? NIG_REG_P1_PKT_PRIORITY_TO_COS :
 988                NIG_REG_P0_PKT_PRIORITY_TO_COS,
 989                pkt_priority_to_cos);
 990 }
 991
 992
 993 void bnx2x_update_pfc(struct link_params *params,
 994                       struct link_vars *vars,
 995                       struct bnx2x_nig_brb_pfc_port_params *pfc_params)
 996 {
 997         /**
 998          * The PFC and pause are orthogonal to one another, meaning when
 999          * PFC is enabled, the pause are disabled, and when PFC is
1000          * disabled, pause are set according to the pause result.
1001          */
1002         u32 val;
1003         struct bnx2x *bp = params->bp;
1004
1005         /* update NIG params */
1006         bnx2x_update_pfc_nig(params, vars, pfc_params);
1007
1008         /* update BRB params */
1009         bnx2x_update_pfc_brb(params, vars, pfc_params);
1010
1011         if (!vars->link_up)
1012                 return;
1013
1014         val = REG_RD(bp, MISC_REG_RESET_REG_2);
1015         if ((val & (MISC_REGISTERS_RESET_REG_2_RST_BMAC0 << params->port))
1016             == 0) {
1017                 DP(NETIF_MSG_LINK, "About to update PFC in EMAC\n");
1018                 bnx2x_emac_enable(params, vars, 0);
1019                 return;
1020         }
1021
1022         DP(NETIF_MSG_LINK, "About to update PFC in BMAC\n");
1023         if (CHIP_IS_E2(bp))
1024                 bnx2x_update_pfc_bmac2(params, vars, 0);
1025         else
1026                 bnx2x_update_pfc_bmac1(params, vars);
1027
1028         val = 0;
1029         if ((params->feature_config_flags &
1030               FEATURE_CONFIG_PFC_ENABLED) ||
1031             (vars->flow_ctrl & BNX2X_FLOW_CTRL_TX))
1032                 val = 1;
1033         REG_WR(bp, NIG_REG_BMAC0_PAUSE_OUT_EN + params->port*4, val);
1034 }
1035
1036 static u8 bnx2x_bmac1_enable(struct link_params *params,
1037                              struct link_vars *vars,
1038                           u8 is_lb)
1039 {
1040         struct bnx2x *bp = params->bp;
1041         u8 port = params->port;
1042         u32 bmac_addr = port ? NIG_REG_INGRESS_BMAC1_MEM :
1043                                NIG_REG_INGRESS_BMAC0_MEM;
1044         u32 wb_data[2];
1045         u32 val;
1046
1047         DP(NETIF_MSG_LINK, "Enabling BigMAC1\n");
1048
1049         /* XGXS control */
1050         wb_data[0] = 0x3c;
1051         wb_data[1] = 0;
1052         REG_WR_DMAE(bp, bmac_addr +
1053                       BIGMAC_REGISTER_BMAC_XGXS_CONTROL,
1054                       wb_data, 2);
1055
1056         /* tx MAC SA */
1057         wb_data[0] = ((params->mac_addr[2] << 24) |
1058                        (params->mac_addr[3] << 16) |
1059                        (params->mac_addr[4] << 8) |
1060                         params->mac_addr[5]);
1061         wb_data[1] = ((params->mac_addr[0] << 8) |
1062                         params->mac_addr[1]);
1063         REG_WR_DMAE(bp, bmac_addr + BIGMAC_REGISTER_TX_SOURCE_ADDR,
1064                     wb_data, 2);
1065
1066         /* mac control */
1067         val = 0x3;
1068         if (is_lb) {
1069                 val |= 0x4;
1070                 DP(NETIF_MSG_LINK, "enable bmac loopback\n");
1071         }
1072         wb_data[0] = val;
1073         wb_data[1] = 0;
1074         REG_WR_DMAE(bp, bmac_addr + BIGMAC_REGISTER_BMAC_CONTROL,
1075                     wb_data, 2);
1076
1077         /* set rx mtu */
1078         wb_data[0] = ETH_MAX_JUMBO_PACKET_SIZE + ETH_OVREHEAD;
1079         wb_data[1] = 0;
1080         REG_WR_DMAE(bp, bmac_addr + BIGMAC_REGISTER_RX_MAX_SIZE,
1081                         wb_data, 2);
1082
1083         bnx2x_update_pfc_bmac1(params, vars);
1084
1085         /* set tx mtu */
1086         wb_data[0] = ETH_MAX_JUMBO_PACKET_SIZE + ETH_OVREHEAD;
1087         wb_data[1] = 0;
1088         REG_WR_DMAE(bp, bmac_addr + BIGMAC_REGISTER_TX_MAX_SIZE,
1089                         wb_data, 2);
1090
1091         /* set cnt max size */
1092         wb_data[0] = ETH_MAX_JUMBO_PACKET_SIZE + ETH_OVREHEAD;
1093         wb_data[1] = 0;
1094         REG_WR_DMAE(bp, bmac_addr + BIGMAC_REGISTER_CNT_MAX_SIZE,
1095                     wb_data, 2);
1096
1097         /* configure safc */
1098         wb_data[0] = 0x1000200;
1099         wb_data[1] = 0;
1100         REG_WR_DMAE(bp, bmac_addr + BIGMAC_REGISTER_RX_LLFC_MSG_FLDS,
1101                     wb_data, 2);
1102         /* fix for emulation */
1103         if (CHIP_REV_IS_EMUL(bp)) {
1104                 wb_data[0] = 0xf000;
1105                 wb_data[1] = 0;
1106                 REG_WR_DMAE(bp,
1107                             bmac_addr + BIGMAC_REGISTER_TX_PAUSE_THRESHOLD,
1108                             wb_data, 2);
1109         }
1110
1111
1112         return 0;
1113 }
1114
1115 static u8 bnx2x_bmac2_enable(struct link_params *params,
1116                              struct link_vars *vars,
1117                              u8 is_lb)
1118 {
1119         struct bnx2x *bp = params->bp;
1120         u8 port = params->port;
1121         u32 bmac_addr = port ? NIG_REG_INGRESS_BMAC1_MEM :
1122                                NIG_REG_INGRESS_BMAC0_MEM;
1123         u32 wb_data[2];
1124
1125         DP(NETIF_MSG_LINK, "Enabling BigMAC2\n");
1126
1127         wb_data[0] = 0;
1128         wb_data[1] = 0;
1129         REG_WR_DMAE(bp, bmac_addr + BIGMAC2_REGISTER_BMAC_CONTROL,
1130                         wb_data, 2);
1131         udelay(30);
1132
1133         /* XGXS control: Reset phy HW, MDIO registers, PHY PLL and BMAC */
1134         wb_data[0] = 0x3c;
1135         wb_data[1] = 0;
1136         REG_WR_DMAE(bp, bmac_addr +
1137                         BIGMAC2_REGISTER_BMAC_XGXS_CONTROL,
1138                         wb_data, 2);
1139
1140         udelay(30);
1141
1142         /* tx MAC SA */
1143         wb_data[0] = ((params->mac_addr[2] << 24) |
1144                        (params->mac_addr[3] << 16) |
1145                        (params->mac_addr[4] << 8) |
1146                         params->mac_addr[5]);
1147         wb_data[1] = ((params->mac_addr[0] << 8) |
1148                         params->mac_addr[1]);
1149         REG_WR_DMAE(bp, bmac_addr + BIGMAC2_REGISTER_TX_SOURCE_ADDR,
1150                         wb_data, 2);
1151
1152         udelay(30);
1153
1154         /* Configure SAFC */
1155         wb_data[0] = 0x1000200;
1156         wb_data[1] = 0;
1157         REG_WR_DMAE(bp, bmac_addr + BIGMAC2_REGISTER_RX_LLFC_MSG_FLDS,
1158                         wb_data, 2);
1159         udelay(30);
1160
1161         /* set rx mtu */
1162         wb_data[0] = ETH_MAX_JUMBO_PACKET_SIZE + ETH_OVREHEAD;
1163         wb_data[1] = 0;
1164         REG_WR_DMAE(bp, bmac_addr + BIGMAC2_REGISTER_RX_MAX_SIZE,
1165                         wb_data, 2);
1166         udelay(30);
1167
1168         /* set tx mtu */
1169         wb_data[0] = ETH_MAX_JUMBO_PACKET_SIZE + ETH_OVREHEAD;
1170         wb_data[1] = 0;
1171         REG_WR_DMAE(bp, bmac_addr + BIGMAC2_REGISTER_TX_MAX_SIZE,
1172                         wb_data, 2);
1173         udelay(30);
1174         /* set cnt max size */
1175         wb_data[0] = ETH_MAX_JUMBO_PACKET_SIZE + ETH_OVREHEAD - 2;
1176         wb_data[1] = 0;
1177         REG_WR_DMAE(bp, bmac_addr + BIGMAC2_REGISTER_CNT_MAX_SIZE,
1178                         wb_data, 2);
1179         udelay(30);
1180         bnx2x_update_pfc_bmac2(params, vars, is_lb);
1181
1182         return 0;
1183 }
1184
1185 static u8 bnx2x_bmac_enable(struct link_params *params,
1186                             struct link_vars *vars,
1187                             u8 is_lb)
1188 {
1189         u8 rc, port = params->port;
1190         struct bnx2x *bp = params->bp;
1191         u32 val;
1192         /* reset and unreset the BigMac */
1193         REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_2_CLEAR,
1194                      (MISC_REGISTERS_RESET_REG_2_RST_BMAC0 << port));
1195         msleep(1);
1196
1197         REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_2_SET,
1198                      (MISC_REGISTERS_RESET_REG_2_RST_BMAC0 << port));
1199
1200         /* enable access for bmac registers */
1201         REG_WR(bp, NIG_REG_BMAC0_REGS_OUT_EN + port*4, 0x1);
1202
1203         /* Enable BMAC according to BMAC type*/
1204         if (CHIP_IS_E2(bp))
1205                 rc = bnx2x_bmac2_enable(params, vars, is_lb);
1206         else
1207                 rc = bnx2x_bmac1_enable(params, vars, is_lb);
1208         REG_WR(bp, NIG_REG_XGXS_SERDES0_MODE_SEL + port*4, 0x1);
1209         REG_WR(bp, NIG_REG_XGXS_LANE_SEL_P0 + port*4, 0x0);
1210         REG_WR(bp, NIG_REG_EGRESS_EMAC0_PORT + port*4, 0x0);
1211         val = 0;
1212         if ((params->feature_config_flags &
1213               FEATURE_CONFIG_PFC_ENABLED) ||
1214             (vars->flow_ctrl & BNX2X_FLOW_CTRL_TX))
1215                 val = 1;
1216         REG_WR(bp, NIG_REG_BMAC0_PAUSE_OUT_EN + port*4, val);
1217         REG_WR(bp, NIG_REG_EGRESS_EMAC0_OUT_EN + port*4, 0x0);
1218         REG_WR(bp, NIG_REG_EMAC0_IN_EN + port*4, 0x0);
1219         REG_WR(bp, NIG_REG_EMAC0_PAUSE_OUT_EN + port*4, 0x0);
1220         REG_WR(bp, NIG_REG_BMAC0_IN_EN + port*4, 0x1);
1221         REG_WR(bp, NIG_REG_BMAC0_OUT_EN + port*4, 0x1);
1222
1223         vars->mac_type = MAC_TYPE_BMAC;
1224         return rc;
1225 }
1226
1227
1228 static void bnx2x_update_mng(struct link_params *params, u32 link_status)
1229 {
1230         struct bnx2x *bp = params->bp;
1231
1232         REG_WR(bp, params->shmem_base +
1233                    offsetof(struct shmem_region,
1234                             port_mb[params->port].link_status),
1235                         link_status);
1236 }
1237
1238 static void bnx2x_bmac_rx_disable(struct bnx2x *bp, u8 port)
1239 {
1240         u32 bmac_addr = port ? NIG_REG_INGRESS_BMAC1_MEM :
1241                 NIG_REG_INGRESS_BMAC0_MEM;
1242         u32 wb_data[2];
1243         u32 nig_bmac_enable = REG_RD(bp, NIG_REG_BMAC0_REGS_OUT_EN + port*4);
1244
1245         /* Only if the bmac is out of reset */
1246         if (REG_RD(bp, MISC_REG_RESET_REG_2) &
1247                         (MISC_REGISTERS_RESET_REG_2_RST_BMAC0 << port) &&
1248             nig_bmac_enable) {
1249
1250                 if (CHIP_IS_E2(bp)) {
1251                         /* Clear Rx Enable bit in BMAC_CONTROL register */
1252                         REG_RD_DMAE(bp, bmac_addr +
1253                                         BIGMAC2_REGISTER_BMAC_CONTROL,
1254                                         wb_data, 2);
1255                         wb_data[0] &= ~BMAC_CONTROL_RX_ENABLE;
1256                         REG_WR_DMAE(bp, bmac_addr +
1257                                         BIGMAC2_REGISTER_BMAC_CONTROL,
1258                                         wb_data, 2);
1259                 } else {
1260                         /* Clear Rx Enable bit in BMAC_CONTROL register */
1261                         REG_RD_DMAE(bp, bmac_addr +
1262                                         BIGMAC_REGISTER_BMAC_CONTROL,
1263                                         wb_data, 2);
1264                         wb_data[0] &= ~BMAC_CONTROL_RX_ENABLE;
1265                         REG_WR_DMAE(bp, bmac_addr +
1266                                         BIGMAC_REGISTER_BMAC_CONTROL,
1267                                         wb_data, 2);
1268                 }
1269                 msleep(1);
1270         }
1271 }
1272
1273 static u8 bnx2x_pbf_update(struct link_params *params, u32 flow_ctrl,
1274                          u32 line_speed)
1275 {
1276         struct bnx2x *bp = params->bp;
1277         u8 port = params->port;
1278         u32 init_crd, crd;
1279         u32 count = 1000;
1280
1281         /* disable port */
1282         REG_WR(bp, PBF_REG_DISABLE_NEW_TASK_PROC_P0 + port*4, 0x1);
1283
1284         /* wait for init credit */
1285         init_crd = REG_RD(bp, PBF_REG_P0_INIT_CRD + port*4);
1286         crd = REG_RD(bp, PBF_REG_P0_CREDIT + port*8);
1287         DP(NETIF_MSG_LINK, "init_crd 0x%x  crd 0x%x\n", init_crd, crd);
1288
1289         while ((init_crd != crd) && count) {
1290                 msleep(5);
1291
1292                 crd = REG_RD(bp, PBF_REG_P0_CREDIT + port*8);
1293                 count--;
1294         }
1295         crd = REG_RD(bp, PBF_REG_P0_CREDIT + port*8);
1296         if (init_crd != crd) {
1297                 DP(NETIF_MSG_LINK, "BUG! init_crd 0x%x != crd 0x%x\n",
1298                           init_crd, crd);
1299                 return -EINVAL;
1300         }
1301
1302         if (flow_ctrl & BNX2X_FLOW_CTRL_RX ||
1303             line_speed == SPEED_10 ||
1304             line_speed == SPEED_100 ||
1305             line_speed == SPEED_1000 ||
1306             line_speed == SPEED_2500) {
1307                 REG_WR(bp, PBF_REG_P0_PAUSE_ENABLE + port*4, 1);
1308                 /* update threshold */
1309                 REG_WR(bp, PBF_REG_P0_ARB_THRSH + port*4, 0);
1310                 /* update init credit */
1311                 init_crd = 778;         /* (800-18-4) */
1312
1313         } else {
1314                 u32 thresh = (ETH_MAX_JUMBO_PACKET_SIZE +
1315                               ETH_OVREHEAD)/16;
1316                 REG_WR(bp, PBF_REG_P0_PAUSE_ENABLE + port*4, 0);
1317                 /* update threshold */
1318                 REG_WR(bp, PBF_REG_P0_ARB_THRSH + port*4, thresh);
1319                 /* update init credit */
1320                 switch (line_speed) {
1321                 case SPEED_10000:
1322                         init_crd = thresh + 553 - 22;
1323                         break;
1324
1325                 case SPEED_12000:
1326                         init_crd = thresh + 664 - 22;
1327                         break;
1328
1329                 case SPEED_13000:
1330                         init_crd = thresh + 742 - 22;
1331                         break;
1332
1333                 case SPEED_16000:
1334                         init_crd = thresh + 778 - 22;
1335                         break;
1336                 default:
1337                         DP(NETIF_MSG_LINK, "Invalid line_speed 0x%x\n",
1338                                   line_speed);
1339                         return -EINVAL;
1340                 }
1341         }
1342         REG_WR(bp, PBF_REG_P0_INIT_CRD + port*4, init_crd);
1343         DP(NETIF_MSG_LINK, "PBF updated to speed %d credit %d\n",
1344                  line_speed, init_crd);
1345
1346         /* probe the credit changes */
1347         REG_WR(bp, PBF_REG_INIT_P0 + port*4, 0x1);
1348         msleep(5);
1349         REG_WR(bp, PBF_REG_INIT_P0 + port*4, 0x0);
1350
1351         /* enable port */
1352         REG_WR(bp, PBF_REG_DISABLE_NEW_TASK_PROC_P0 + port*4, 0x0);
1353         return 0;
1354 }
1355
1356 static u32 bnx2x_get_emac_base(struct bnx2x *bp,
1357                                u32 mdc_mdio_access, u8 port)
1358 {
1359         u32 emac_base = 0;
1360         switch (mdc_mdio_access) {
1361         case SHARED_HW_CFG_MDC_MDIO_ACCESS1_PHY_TYPE:
1362                 break;
1363         case SHARED_HW_CFG_MDC_MDIO_ACCESS1_EMAC0:
1364                 if (REG_RD(bp, NIG_REG_PORT_SWAP))
1365                         emac_base = GRCBASE_EMAC1;
1366                 else
1367                         emac_base = GRCBASE_EMAC0;
1368                 break;
1369         case SHARED_HW_CFG_MDC_MDIO_ACCESS1_EMAC1:
1370                 if (REG_RD(bp, NIG_REG_PORT_SWAP))
1371                         emac_base = GRCBASE_EMAC0;
1372                 else
1373                         emac_base = GRCBASE_EMAC1;
1374                 break;
1375         case SHARED_HW_CFG_MDC_MDIO_ACCESS1_BOTH:
1376                 emac_base = (port) ? GRCBASE_EMAC1 : GRCBASE_EMAC0;
1377                 break;
1378         case SHARED_HW_CFG_MDC_MDIO_ACCESS1_SWAPPED:
1379                 emac_base = (port) ? GRCBASE_EMAC0 : GRCBASE_EMAC1;
1380                 break;
1381         default:
1382                 break;
1383         }
1384         return emac_base;
1385
1386 }
1387
1388 u8 bnx2x_cl45_write(struct bnx2x *bp, struct bnx2x_phy *phy,
1389                     u8 devad, u16 reg, u16 val)
1390 {
1391         u32 tmp, saved_mode;
1392         u8 i, rc = 0;
1393
1394         /* set clause 45 mode, slow down the MDIO clock to 2.5MHz
1395          * (a value of 49==0x31) and make sure that the AUTO poll is off
1396          */
1397
1398         saved_mode = REG_RD(bp, phy->mdio_ctrl + EMAC_REG_EMAC_MDIO_MODE);
1399         tmp = saved_mode & ~(EMAC_MDIO_MODE_AUTO_POLL |
1400                              EMAC_MDIO_MODE_CLOCK_CNT);
1401         tmp |= (EMAC_MDIO_MODE_CLAUSE_45 |
1402                 (49 << EMAC_MDIO_MODE_CLOCK_CNT_BITSHIFT));
1403         REG_WR(bp, phy->mdio_ctrl + EMAC_REG_EMAC_MDIO_MODE, tmp);
1404         REG_RD(bp, phy->mdio_ctrl + EMAC_REG_EMAC_MDIO_MODE);
1405         udelay(40);
1406
1407         /* address */
1408
1409         tmp = ((phy->addr << 21) | (devad << 16) | reg |
1410                EMAC_MDIO_COMM_COMMAND_ADDRESS |
1411                EMAC_MDIO_COMM_START_BUSY);
1412         REG_WR(bp, phy->mdio_ctrl + EMAC_REG_EMAC_MDIO_COMM, tmp);
1413
1414         for (i = 0; i < 50; i++) {
1415                 udelay(10);
1416
1417                 tmp = REG_RD(bp, phy->mdio_ctrl +
1418                                    EMAC_REG_EMAC_MDIO_COMM);
1419                 if (!(tmp & EMAC_MDIO_COMM_START_BUSY)) {
1420                         udelay(5);
1421                         break;
1422                 }
1423         }
1424         if (tmp & EMAC_MDIO_COMM_START_BUSY) {
1425                 DP(NETIF_MSG_LINK, "write phy register failed\n");
1426                 rc = -EFAULT;
1427         } else {
1428                 /* data */
1429                 tmp = ((phy->addr << 21) | (devad << 16) | val |
1430                        EMAC_MDIO_COMM_COMMAND_WRITE_45 |
1431                        EMAC_MDIO_COMM_START_BUSY);
1432                 REG_WR(bp, phy->mdio_ctrl + EMAC_REG_EMAC_MDIO_COMM, tmp);
1433
1434                 for (i = 0; i < 50; i++) {
1435                         udelay(10);
1436
1437                         tmp = REG_RD(bp, phy->mdio_ctrl +
1438                                          EMAC_REG_EMAC_MDIO_COMM);
1439                         if (!(tmp & EMAC_MDIO_COMM_START_BUSY)) {
1440                                 udelay(5);
1441                                 break;
1442                         }
1443                 }
1444                 if (tmp & EMAC_MDIO_COMM_START_BUSY) {
1445                         DP(NETIF_MSG_LINK, "write phy register failed\n");
1446                         rc = -EFAULT;
1447                 }
1448         }
1449
1450         /* Restore the saved mode */
1451         REG_WR(bp, phy->mdio_ctrl + EMAC_REG_EMAC_MDIO_MODE, saved_mode);
1452
1453         return rc;
1454 }
1455
1456 u8 bnx2x_cl45_read(struct bnx2x *bp, struct bnx2x_phy *phy,
1457                    u8 devad, u16 reg, u16 *ret_val)
1458 {
1459         u32 val, saved_mode;
1460         u16 i;
1461         u8 rc = 0;
1462
1463         /* set clause 45 mode, slow down the MDIO clock to 2.5MHz
1464          * (a value of 49==0x31) and make sure that the AUTO poll is off
1465          */
1466
1467         saved_mode = REG_RD(bp, phy->mdio_ctrl + EMAC_REG_EMAC_MDIO_MODE);
1468         val = saved_mode & ~((EMAC_MDIO_MODE_AUTO_POLL |
1469                              EMAC_MDIO_MODE_CLOCK_CNT));
1470         val |= (EMAC_MDIO_MODE_CLAUSE_45 |
1471                 (49L << EMAC_MDIO_MODE_CLOCK_CNT_BITSHIFT));
1472         REG_WR(bp, phy->mdio_ctrl + EMAC_REG_EMAC_MDIO_MODE, val);
1473         REG_RD(bp, phy->mdio_ctrl + EMAC_REG_EMAC_MDIO_MODE);
1474         udelay(40);
1475
1476         /* address */
1477         val = ((phy->addr << 21) | (devad << 16) | reg |
1478                EMAC_MDIO_COMM_COMMAND_ADDRESS |
1479                EMAC_MDIO_COMM_START_BUSY);
1480         REG_WR(bp, phy->mdio_ctrl + EMAC_REG_EMAC_MDIO_COMM, val);
1481
1482         for (i = 0; i < 50; i++) {
1483                 udelay(10);
1484
1485                 val = REG_RD(bp, phy->mdio_ctrl + EMAC_REG_EMAC_MDIO_COMM);
1486                 if (!(val & EMAC_MDIO_COMM_START_BUSY)) {
1487                         udelay(5);
1488                         break;
1489                 }
1490         }
1491         if (val & EMAC_MDIO_COMM_START_BUSY) {
1492                 DP(NETIF_MSG_LINK, "read phy register failed\n");
1493
1494                 *ret_val = 0;
1495                 rc = -EFAULT;
1496
1497         } else {
1498                 /* data */
1499                 val = ((phy->addr << 21) | (devad << 16) |
1500                        EMAC_MDIO_COMM_COMMAND_READ_45 |
1501                        EMAC_MDIO_COMM_START_BUSY);
1502                 REG_WR(bp, phy->mdio_ctrl + EMAC_REG_EMAC_MDIO_COMM, val);
1503
1504                 for (i = 0; i < 50; i++) {
1505                         udelay(10);
1506
1507                         val = REG_RD(bp, phy->mdio_ctrl +
1508                                           EMAC_REG_EMAC_MDIO_COMM);
1509                         if (!(val & EMAC_MDIO_COMM_START_BUSY)) {
1510                                 *ret_val = (u16)(val & EMAC_MDIO_COMM_DATA);
1511                                 break;
1512                         }
1513                 }
1514                 if (val & EMAC_MDIO_COMM_START_BUSY) {
1515                         DP(NETIF_MSG_LINK, "read phy register failed\n");
1516
1517                         *ret_val = 0;
1518                         rc = -EFAULT;
1519                 }
1520         }
1521
1522         /* Restore the saved mode */
1523         REG_WR(bp, phy->mdio_ctrl + EMAC_REG_EMAC_MDIO_MODE, saved_mode);
1524
1525         return rc;
1526 }
1527
1528 u8 bnx2x_phy_read(struct link_params *params, u8 phy_addr,
1529                   u8 devad, u16 reg, u16 *ret_val)
1530 {
1531         u8 phy_index;
1532         /**
1533          * Probe for the phy according to the given phy_addr, and execute
1534          * the read request on it
1535          */
1536         for (phy_index = 0; phy_index < params->num_phys; phy_index++) {
1537                 if (params->phy[phy_index].addr == phy_addr) {
1538                         return bnx2x_cl45_read(params->bp,
1539                                                &params->phy[phy_index], devad,
1540                                                reg, ret_val);
1541                 }
1542         }
1543         return -EINVAL;
1544 }
1545
1546 u8 bnx2x_phy_write(struct link_params *params, u8 phy_addr,
1547                    u8 devad, u16 reg, u16 val)
1548 {
1549         u8 phy_index;
1550         /**
1551          * Probe for the phy according to the given phy_addr, and execute
1552          * the write request on it
1553          */
1554         for (phy_index = 0; phy_index < params->num_phys; phy_index++) {
1555                 if (params->phy[phy_index].addr == phy_addr) {
1556                         return bnx2x_cl45_write(params->bp,
1557                                                 &params->phy[phy_index], devad,
1558                                                 reg, val);
1559                 }
1560         }
1561         return -EINVAL;
1562 }
1563
1564 static void bnx2x_set_aer_mmd_xgxs(struct link_params *params,
1565                                    struct bnx2x_phy *phy)
1566 {
1567         u32 ser_lane;
1568         u16 offset, aer_val;
1569         struct bnx2x *bp = params->bp;
1570         ser_lane = ((params->lane_config &
1571                      PORT_HW_CFG_LANE_SWAP_CFG_MASTER_MASK) >>
1572                      PORT_HW_CFG_LANE_SWAP_CFG_MASTER_SHIFT);
1573
1574         offset = phy->addr + ser_lane;
1575         if (CHIP_IS_E2(bp))
1576                 aer_val = 0x2800 + offset - 1;
1577         else
1578                 aer_val = 0x3800 + offset;
1579         CL45_WR_OVER_CL22(bp, phy,
1580                                 MDIO_REG_BANK_AER_BLOCK,
1581                                 MDIO_AER_BLOCK_AER_REG, aer_val);
1582 }
1583 static void bnx2x_set_aer_mmd_serdes(struct bnx2x *bp,
1584                                      struct bnx2x_phy *phy)
1585 {
1586         CL45_WR_OVER_CL22(bp, phy,
1587                                 MDIO_REG_BANK_AER_BLOCK,
1588                                 MDIO_AER_BLOCK_AER_REG, 0x3800);
1589 }
1590
1591 /******************************************************************/
1592 /*                      Internal phy section                      */
1593 /******************************************************************/
1594
1595 static void bnx2x_set_serdes_access(struct bnx2x *bp, u8 port)
1596 {
1597         u32 emac_base = (port) ? GRCBASE_EMAC1 : GRCBASE_EMAC0;
1598
1599         /* Set Clause 22 */
1600         REG_WR(bp, NIG_REG_SERDES0_CTRL_MD_ST + port*0x10, 1);
1601         REG_WR(bp, emac_base + EMAC_REG_EMAC_MDIO_COMM, 0x245f8000);
1602         udelay(500);
1603         REG_WR(bp, emac_base + EMAC_REG_EMAC_MDIO_COMM, 0x245d000f);
1604         udelay(500);
1605          /* Set Clause 45 */
1606         REG_WR(bp, NIG_REG_SERDES0_CTRL_MD_ST + port*0x10, 0);
1607 }
1608
1609 static void bnx2x_serdes_deassert(struct bnx2x *bp, u8 port)
1610 {
1611         u32 val;
1612
1613         DP(NETIF_MSG_LINK, "bnx2x_serdes_deassert\n");
1614
1615         val = SERDES_RESET_BITS << (port*16);
1616
1617         /* reset and unreset the SerDes/XGXS */
1618         REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_3_CLEAR, val);
1619         udelay(500);
1620         REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_3_SET, val);
1621
1622         bnx2x_set_serdes_access(bp, port);
1623
1624         REG_WR(bp, NIG_REG_SERDES0_CTRL_MD_DEVAD +
1625                      port*0x10,
1626                      DEFAULT_PHY_DEV_ADDR);
1627 }
1628
1629 static void bnx2x_xgxs_deassert(struct link_params *params)
1630 {
1631         struct bnx2x *bp = params->bp;
1632         u8 port;
1633         u32 val;
1634         DP(NETIF_MSG_LINK, "bnx2x_xgxs_deassert\n");
1635         port = params->port;
1636
1637         val = XGXS_RESET_BITS << (port*16);
1638
1639         /* reset and unreset the SerDes/XGXS */
1640         REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_3_CLEAR, val);
1641         udelay(500);
1642         REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_3_SET, val);
1643
1644         REG_WR(bp, NIG_REG_XGXS0_CTRL_MD_ST +
1645                      port*0x18, 0);
1646         REG_WR(bp, NIG_REG_XGXS0_CTRL_MD_DEVAD + port*0x18,
1647                      params->phy[INT_PHY].def_md_devad);
1648 }
1649
1650
1651 void bnx2x_link_status_update(struct link_params *params,
1652                             struct link_vars   *vars)
1653 {
1654         struct bnx2x *bp = params->bp;
1655         u8 link_10g;
1656         u8 port = params->port;
1657
1658         vars->link_status = REG_RD(bp, params->shmem_base +
1659                                           offsetof(struct shmem_region,
1660                                            port_mb[port].link_status));
1661
1662         vars->link_up = (vars->link_status & LINK_STATUS_LINK_UP);
1663
1664         if (vars->link_up) {
1665                 DP(NETIF_MSG_LINK, "phy link up\n");
1666
1667                 vars->phy_link_up = 1;
1668                 vars->duplex = DUPLEX_FULL;
1669                 switch (vars->link_status &
1670                                         LINK_STATUS_SPEED_AND_DUPLEX_MASK) {
1671                         case LINK_10THD:
1672                                 vars->duplex = DUPLEX_HALF;
1673                                 /* fall thru */
1674                         case LINK_10TFD:
1675                                 vars->line_speed = SPEED_10;
1676                                 break;
1677
1678                         case LINK_100TXHD:
1679                                 vars->duplex = DUPLEX_HALF;
1680                                 /* fall thru */
1681                         case LINK_100T4:
1682                         case LINK_100TXFD:
1683                                 vars->line_speed = SPEED_100;
1684                                 break;
1685
1686                         case LINK_1000THD:
1687                                 vars->duplex = DUPLEX_HALF;
1688                                 /* fall thru */
1689                         case LINK_1000TFD:
1690                                 vars->line_speed = SPEED_1000;
1691                                 break;
1692
1693                         case LINK_2500THD:
1694                                 vars->duplex = DUPLEX_HALF;
1695                                 /* fall thru */
1696                         case LINK_2500TFD:
1697                                 vars->line_speed = SPEED_2500;
1698                                 break;
1699
1700                         case LINK_10GTFD:
1701                                 vars->line_speed = SPEED_10000;
1702                                 break;
1703
1704                         case LINK_12GTFD:
1705                                 vars->line_speed = SPEED_12000;
1706                                 break;
1707
1708                         case LINK_12_5GTFD:
1709                                 vars->line_speed = SPEED_12500;
1710                                 break;
1711
1712                         case LINK_13GTFD:
1713                                 vars->line_speed = SPEED_13000;
1714                                 break;
1715
1716                         case LINK_15GTFD:
1717                                 vars->line_speed = SPEED_15000;
1718                                 break;
1719
1720                         case LINK_16GTFD:
1721                                 vars->line_speed = SPEED_16000;
1722                                 break;
1723
1724                         default:
1725                                 break;
1726                 }
1727                 vars->flow_ctrl = 0;
1728                 if (vars->link_status & LINK_STATUS_TX_FLOW_CONTROL_ENABLED)
1729                         vars->flow_ctrl |= BNX2X_FLOW_CTRL_TX;
1730
1731                 if (vars->link_status & LINK_STATUS_RX_FLOW_CONTROL_ENABLED)
1732                         vars->flow_ctrl |= BNX2X_FLOW_CTRL_RX;
1733
1734                 if (!vars->flow_ctrl)
1735                         vars->flow_ctrl = BNX2X_FLOW_CTRL_NONE;
1736
1737                 if (vars->line_speed &&
1738                     ((vars->line_speed == SPEED_10) ||
1739                      (vars->line_speed == SPEED_100))) {
1740                         vars->phy_flags |= PHY_SGMII_FLAG;
1741                 } else {
1742                         vars->phy_flags &= ~PHY_SGMII_FLAG;
1743                 }
1744
1745                 /* anything 10 and over uses the bmac */
1746                 link_10g = ((vars->line_speed == SPEED_10000) ||
1747                             (vars->line_speed == SPEED_12000) ||
1748                             (vars->line_speed == SPEED_12500) ||
1749                             (vars->line_speed == SPEED_13000) ||
1750                             (vars->line_speed == SPEED_15000) ||
1751                             (vars->line_speed == SPEED_16000));
1752                 if (link_10g)
1753                         vars->mac_type = MAC_TYPE_BMAC;
1754                 else
1755                         vars->mac_type = MAC_TYPE_EMAC;
1756
1757         } else { /* link down */
1758                 DP(NETIF_MSG_LINK, "phy link down\n");
1759
1760                 vars->phy_link_up = 0;
1761
1762                 vars->line_speed = 0;
1763                 vars->duplex = DUPLEX_FULL;
1764                 vars->flow_ctrl = BNX2X_FLOW_CTRL_NONE;
1765
1766                 /* indicate no mac active */
1767                 vars->mac_type = MAC_TYPE_NONE;
1768         }
1769
1770         DP(NETIF_MSG_LINK, "link_status 0x%x  phy_link_up %x\n",
1771                  vars->link_status, vars->phy_link_up);
1772         DP(NETIF_MSG_LINK, "line_speed %x  duplex %x  flow_ctrl 0x%x\n",
1773                  vars->line_speed, vars->duplex, vars->flow_ctrl);
1774 }
1775
1776
1777 static void bnx2x_set_master_ln(struct link_params *params,
1778                                 struct bnx2x_phy *phy)
1779 {
1780         struct bnx2x *bp = params->bp;
1781         u16 new_master_ln, ser_lane;
1782         ser_lane =  ((params->lane_config &
1783                      PORT_HW_CFG_LANE_SWAP_CFG_MASTER_MASK) >>
1784                      PORT_HW_CFG_LANE_SWAP_CFG_MASTER_SHIFT);
1785
1786         /* set the master_ln for AN */
1787         CL45_RD_OVER_CL22(bp, phy,
1788                               MDIO_REG_BANK_XGXS_BLOCK2,
1789                               MDIO_XGXS_BLOCK2_TEST_MODE_LANE,
1790                               &new_master_ln);
1791
1792         CL45_WR_OVER_CL22(bp, phy,
1793                               MDIO_REG_BANK_XGXS_BLOCK2 ,
1794                               MDIO_XGXS_BLOCK2_TEST_MODE_LANE,
1795                               (new_master_ln | ser_lane));
1796 }
1797
1798 static u8 bnx2x_reset_unicore(struct link_params *params,
1799                               struct bnx2x_phy *phy,
1800                               u8 set_serdes)
1801 {
1802         struct bnx2x *bp = params->bp;
1803         u16 mii_control;
1804         u16 i;
1805
1806         CL45_RD_OVER_CL22(bp, phy,
1807                               MDIO_REG_BANK_COMBO_IEEE0,
1808                               MDIO_COMBO_IEEE0_MII_CONTROL, &mii_control);
1809
1810         /* reset the unicore */
1811         CL45_WR_OVER_CL22(bp, phy,
1812                               MDIO_REG_BANK_COMBO_IEEE0,
1813                               MDIO_COMBO_IEEE0_MII_CONTROL,
1814                               (mii_control |
1815                                MDIO_COMBO_IEEO_MII_CONTROL_RESET));
1816         if (set_serdes)
1817                 bnx2x_set_serdes_access(bp, params->port);
1818
1819         /* wait for the reset to self clear */
1820         for (i = 0; i < MDIO_ACCESS_TIMEOUT; i++) {
1821                 udelay(5);
1822
1823                 /* the reset erased the previous bank value */
1824                 CL45_RD_OVER_CL22(bp, phy,
1825                               MDIO_REG_BANK_COMBO_IEEE0,
1826                               MDIO_COMBO_IEEE0_MII_CONTROL,
1827                               &mii_control);
1828
1829                 if (!(mii_control & MDIO_COMBO_IEEO_MII_CONTROL_RESET)) {
1830                         udelay(5);
1831                         return 0;
1832                 }
1833         }
1834
1835         DP(NETIF_MSG_LINK, "BUG! XGXS is still in reset!\n");
1836         return -EINVAL;
1837
1838 }
1839
1840 static void bnx2x_set_swap_lanes(struct link_params *params,
1841                                  struct bnx2x_phy *phy)
1842 {
1843         struct bnx2x *bp = params->bp;
1844         /* Each two bits represents a lane number:
1845            No swap is 0123 => 0x1b no need to enable the swap */
1846         u16 ser_lane, rx_lane_swap, tx_lane_swap;
1847
1848         ser_lane = ((params->lane_config &
1849                          PORT_HW_CFG_LANE_SWAP_CFG_MASTER_MASK) >>
1850                         PORT_HW_CFG_LANE_SWAP_CFG_MASTER_SHIFT);
1851         rx_lane_swap = ((params->lane_config &
1852                              PORT_HW_CFG_LANE_SWAP_CFG_RX_MASK) >>
1853                             PORT_HW_CFG_LANE_SWAP_CFG_RX_SHIFT);
1854         tx_lane_swap = ((params->lane_config &
1855                              PORT_HW_CFG_LANE_SWAP_CFG_TX_MASK) >>
1856                             PORT_HW_CFG_LANE_SWAP_CFG_TX_SHIFT);
1857
1858         if (rx_lane_swap != 0x1b) {
1859                 CL45_WR_OVER_CL22(bp, phy,
1860                                     MDIO_REG_BANK_XGXS_BLOCK2,
1861                                     MDIO_XGXS_BLOCK2_RX_LN_SWAP,
1862                                     (rx_lane_swap |
1863                                     MDIO_XGXS_BLOCK2_RX_LN_SWAP_ENABLE |
1864                                     MDIO_XGXS_BLOCK2_RX_LN_SWAP_FORCE_ENABLE));
1865         } else {
1866                 CL45_WR_OVER_CL22(bp, phy,
1867                                       MDIO_REG_BANK_XGXS_BLOCK2,
1868                                       MDIO_XGXS_BLOCK2_RX_LN_SWAP, 0);
1869         }
1870
1871         if (tx_lane_swap != 0x1b) {
1872                 CL45_WR_OVER_CL22(bp, phy,
1873                                       MDIO_REG_BANK_XGXS_BLOCK2,
1874                                       MDIO_XGXS_BLOCK2_TX_LN_SWAP,
1875                                       (tx_lane_swap |
1876                                        MDIO_XGXS_BLOCK2_TX_LN_SWAP_ENABLE));
1877         } else {
1878                 CL45_WR_OVER_CL22(bp, phy,
1879                                       MDIO_REG_BANK_XGXS_BLOCK2,
1880                                       MDIO_XGXS_BLOCK2_TX_LN_SWAP, 0);
1881         }
1882 }
1883
1884 static void bnx2x_set_parallel_detection(struct bnx2x_phy *phy,
1885                                          struct link_params *params)
1886 {
1887         struct bnx2x *bp = params->bp;
1888         u16 control2;
1889         CL45_RD_OVER_CL22(bp, phy,
1890                               MDIO_REG_BANK_SERDES_DIGITAL,
1891                               MDIO_SERDES_DIGITAL_A_1000X_CONTROL2,
1892                               &control2);
1893         if (phy->speed_cap_mask & PORT_HW_CFG_SPEED_CAPABILITY_D0_1G)
1894                 control2 |= MDIO_SERDES_DIGITAL_A_1000X_CONTROL2_PRL_DT_EN;
1895         else
1896                 control2 &= ~MDIO_SERDES_DIGITAL_A_1000X_CONTROL2_PRL_DT_EN;
1897         DP(NETIF_MSG_LINK, "phy->speed_cap_mask = 0x%x, control2 = 0x%x\n",
1898                 phy->speed_cap_mask, control2);
1899         CL45_WR_OVER_CL22(bp, phy,
1900                               MDIO_REG_BANK_SERDES_DIGITAL,
1901                               MDIO_SERDES_DIGITAL_A_1000X_CONTROL2,
1902                               control2);
1903
1904         if ((phy->type == PORT_HW_CFG_XGXS_EXT_PHY_TYPE_DIRECT) &&
1905              (phy->speed_cap_mask &
1906                     PORT_HW_CFG_SPEED_CAPABILITY_D0_10G)) {
1907                 DP(NETIF_MSG_LINK, "XGXS\n");
1908
1909                 CL45_WR_OVER_CL22(bp, phy,
1910                                 MDIO_REG_BANK_10G_PARALLEL_DETECT,
1911                                 MDIO_10G_PARALLEL_DETECT_PAR_DET_10G_LINK,
1912                                 MDIO_10G_PARALLEL_DETECT_PAR_DET_10G_LINK_CNT);
1913
1914                 CL45_RD_OVER_CL22(bp, phy,
1915                                 MDIO_REG_BANK_10G_PARALLEL_DETECT,
1916                                 MDIO_10G_PARALLEL_DETECT_PAR_DET_10G_CONTROL,
1917                                 &control2);
1918
1919
1920                 control2 |=
1921                     MDIO_10G_PARALLEL_DETECT_PAR_DET_10G_CONTROL_PARDET10G_EN;
1922
1923                 CL45_WR_OVER_CL22(bp, phy,
1924                                 MDIO_REG_BANK_10G_PARALLEL_DETECT,
1925                                 MDIO_10G_PARALLEL_DETECT_PAR_DET_10G_CONTROL,
1926                                 control2);
1927
1928                 /* Disable parallel detection of HiG */
1929                 CL45_WR_OVER_CL22(bp, phy,
1930                                 MDIO_REG_BANK_XGXS_BLOCK2,
1931                                 MDIO_XGXS_BLOCK2_UNICORE_MODE_10G,
1932                                 MDIO_XGXS_BLOCK2_UNICORE_MODE_10G_CX4_XGXS |
1933                                 MDIO_XGXS_BLOCK2_UNICORE_MODE_10G_HIGIG_XGXS);
1934         }
1935 }
1936
1937 static void bnx2x_set_autoneg(struct bnx2x_phy *phy,
1938                               struct link_params *params,
1939                             struct link_vars *vars,
1940                             u8 enable_cl73)
1941 {
1942         struct bnx2x *bp = params->bp;
1943         u16 reg_val;
1944
1945         /* CL37 Autoneg */
1946         CL45_RD_OVER_CL22(bp, phy,
1947                               MDIO_REG_BANK_COMBO_IEEE0,
1948                               MDIO_COMBO_IEEE0_MII_CONTROL, &reg_val);
1949
1950         /* CL37 Autoneg Enabled */
1951         if (vars->line_speed == SPEED_AUTO_NEG)
1952                 reg_val |= MDIO_COMBO_IEEO_MII_CONTROL_AN_EN;
1953         else /* CL37 Autoneg Disabled */
1954                 reg_val &= ~(MDIO_COMBO_IEEO_MII_CONTROL_AN_EN |
1955                              MDIO_COMBO_IEEO_MII_CONTROL_RESTART_AN);
1956
1957         CL45_WR_OVER_CL22(bp, phy,
1958                               MDIO_REG_BANK_COMBO_IEEE0,
1959                               MDIO_COMBO_IEEE0_MII_CONTROL, reg_val);
1960
1961         /* Enable/Disable Autodetection */
1962
1963         CL45_RD_OVER_CL22(bp, phy,
1964                               MDIO_REG_BANK_SERDES_DIGITAL,
1965                               MDIO_SERDES_DIGITAL_A_1000X_CONTROL1, &reg_val);
1966         reg_val &= ~(MDIO_SERDES_DIGITAL_A_1000X_CONTROL1_SIGNAL_DETECT_EN |
1967                     MDIO_SERDES_DIGITAL_A_1000X_CONTROL1_INVERT_SIGNAL_DETECT);
1968         reg_val |= MDIO_SERDES_DIGITAL_A_1000X_CONTROL1_FIBER_MODE;
1969         if (vars->line_speed == SPEED_AUTO_NEG)
1970                 reg_val |= MDIO_SERDES_DIGITAL_A_1000X_CONTROL1_AUTODET;
1971         else
1972                 reg_val &= ~MDIO_SERDES_DIGITAL_A_1000X_CONTROL1_AUTODET;
1973
1974         CL45_WR_OVER_CL22(bp, phy,
1975                               MDIO_REG_BANK_SERDES_DIGITAL,
1976                               MDIO_SERDES_DIGITAL_A_1000X_CONTROL1, reg_val);
1977
1978         /* Enable TetonII and BAM autoneg */
1979         CL45_RD_OVER_CL22(bp, phy,
1980                               MDIO_REG_BANK_BAM_NEXT_PAGE,
1981                               MDIO_BAM_NEXT_PAGE_MP5_NEXT_PAGE_CTRL,
1982                           &reg_val);
1983         if (vars->line_speed == SPEED_AUTO_NEG) {
1984                 /* Enable BAM aneg Mode and TetonII aneg Mode */
1985                 reg_val |= (MDIO_BAM_NEXT_PAGE_MP5_NEXT_PAGE_CTRL_BAM_MODE |
1986                             MDIO_BAM_NEXT_PAGE_MP5_NEXT_PAGE_CTRL_TETON_AN);
1987         } else {
1988                 /* TetonII and BAM Autoneg Disabled */
1989                 reg_val &= ~(MDIO_BAM_NEXT_PAGE_MP5_NEXT_PAGE_CTRL_BAM_MODE |
1990                              MDIO_BAM_NEXT_PAGE_MP5_NEXT_PAGE_CTRL_TETON_AN);
1991         }
1992         CL45_WR_OVER_CL22(bp, phy,
1993                               MDIO_REG_BANK_BAM_NEXT_PAGE,
1994                               MDIO_BAM_NEXT_PAGE_MP5_NEXT_PAGE_CTRL,
1995                               reg_val);
1996
1997         if (enable_cl73) {
1998                 /* Enable Cl73 FSM status bits */
1999                 CL45_WR_OVER_CL22(bp, phy,
2000                                       MDIO_REG_BANK_CL73_USERB0,
2001                                     MDIO_CL73_USERB0_CL73_UCTRL,
2002                                       0xe);
2003
2004                 /* Enable BAM Station Manager*/
2005                 CL45_WR_OVER_CL22(bp, phy,
2006                         MDIO_REG_BANK_CL73_USERB0,
2007                         MDIO_CL73_USERB0_CL73_BAM_CTRL1,
2008                         MDIO_CL73_USERB0_CL73_BAM_CTRL1_BAM_EN |
2009                         MDIO_CL73_USERB0_CL73_BAM_CTRL1_BAM_STATION_MNGR_EN |
2010                         MDIO_CL73_USERB0_CL73_BAM_CTRL1_BAM_NP_AFTER_BP_EN);
2011
2012                 /* Advertise CL73 link speeds */
2013                 CL45_RD_OVER_CL22(bp, phy,
2014                                               MDIO_REG_BANK_CL73_IEEEB1,
2015                                               MDIO_CL73_IEEEB1_AN_ADV2,
2016                                               &reg_val);
2017                 if (phy->speed_cap_mask &
2018                     PORT_HW_CFG_SPEED_CAPABILITY_D0_10G)
2019                         reg_val |= MDIO_CL73_IEEEB1_AN_ADV2_ADVR_10G_KX4;
2020                 if (phy->speed_cap_mask &
2021                     PORT_HW_CFG_SPEED_CAPABILITY_D0_1G)
2022                         reg_val |= MDIO_CL73_IEEEB1_AN_ADV2_ADVR_1000M_KX;
2023
2024                 CL45_WR_OVER_CL22(bp, phy,
2025                                               MDIO_REG_BANK_CL73_IEEEB1,
2026                                               MDIO_CL73_IEEEB1_AN_ADV2,
2027                                       reg_val);
2028
2029                 /* CL73 Autoneg Enabled */
2030                 reg_val = MDIO_CL73_IEEEB0_CL73_AN_CONTROL_AN_EN;
2031
2032         } else /* CL73 Autoneg Disabled */
2033                 reg_val = 0;
2034
2035         CL45_WR_OVER_CL22(bp, phy,
2036                               MDIO_REG_BANK_CL73_IEEEB0,
2037                               MDIO_CL73_IEEEB0_CL73_AN_CONTROL, reg_val);
2038 }
2039
2040 /* program SerDes, forced speed */
2041 static void bnx2x_program_serdes(struct bnx2x_phy *phy,
2042                                  struct link_params *params,
2043                                struct link_vars *vars)
2044 {
2045         struct bnx2x *bp = params->bp;
2046         u16 reg_val;
2047
2048         /* program duplex, disable autoneg and sgmii*/
2049         CL45_RD_OVER_CL22(bp, phy,
2050                               MDIO_REG_BANK_COMBO_IEEE0,
2051                               MDIO_COMBO_IEEE0_MII_CONTROL, &reg_val);
2052         reg_val &= ~(MDIO_COMBO_IEEO_MII_CONTROL_FULL_DUPLEX |
2053                      MDIO_COMBO_IEEO_MII_CONTROL_AN_EN |
2054                      MDIO_COMBO_IEEO_MII_CONTROL_MAN_SGMII_SP_MASK);
2055         if (phy->req_duplex == DUPLEX_FULL)
2056                 reg_val |= MDIO_COMBO_IEEO_MII_CONTROL_FULL_DUPLEX;
2057         CL45_WR_OVER_CL22(bp, phy,
2058                               MDIO_REG_BANK_COMBO_IEEE0,
2059                               MDIO_COMBO_IEEE0_MII_CONTROL, reg_val);
2060
2061         /* program speed
2062            - needed only if the speed is greater than 1G (2.5G or 10G) */
2063         CL45_RD_OVER_CL22(bp, phy,
2064                                       MDIO_REG_BANK_SERDES_DIGITAL,
2065                                       MDIO_SERDES_DIGITAL_MISC1, &reg_val);
2066         /* clearing the speed value before setting the right speed */
2067         DP(NETIF_MSG_LINK, "MDIO_REG_BANK_SERDES_DIGITAL = 0x%x\n", reg_val);
2068
2069         reg_val &= ~(MDIO_SERDES_DIGITAL_MISC1_FORCE_SPEED_MASK |
2070                      MDIO_SERDES_DIGITAL_MISC1_FORCE_SPEED_SEL);
2071
2072         if (!((vars->line_speed == SPEED_1000) ||
2073               (vars->line_speed == SPEED_100) ||
2074               (vars->line_speed == SPEED_10))) {
2075
2076                 reg_val |= (MDIO_SERDES_DIGITAL_MISC1_REFCLK_SEL_156_25M |
2077                             MDIO_SERDES_DIGITAL_MISC1_FORCE_SPEED_SEL);
2078                 if (vars->line_speed == SPEED_10000)
2079                         reg_val |=
2080                                 MDIO_SERDES_DIGITAL_MISC1_FORCE_SPEED_10G_CX4;
2081                 if (vars->line_speed == SPEED_13000)
2082                         reg_val |=
2083                                 MDIO_SERDES_DIGITAL_MISC1_FORCE_SPEED_13G;
2084         }
2085
2086         CL45_WR_OVER_CL22(bp, phy,
2087                                       MDIO_REG_BANK_SERDES_DIGITAL,
2088                                       MDIO_SERDES_DIGITAL_MISC1, reg_val);
2089
2090 }
2091
2092 static void bnx2x_set_brcm_cl37_advertisment(struct bnx2x_phy *phy,
2093                                              struct link_params *params)
2094 {
2095         struct bnx2x *bp = params->bp;
2096         u16 val = 0;
2097
2098         /* configure the 48 bits for BAM AN */
2099
2100         /* set extended capabilities */
2101         if (phy->speed_cap_mask & PORT_HW_CFG_SPEED_CAPABILITY_D0_2_5G)
2102                 val |= MDIO_OVER_1G_UP1_2_5G;
2103         if (phy->speed_cap_mask & PORT_HW_CFG_SPEED_CAPABILITY_D0_10G)
2104                 val |= MDIO_OVER_1G_UP1_10G;
2105         CL45_WR_OVER_CL22(bp, phy,
2106                               MDIO_REG_BANK_OVER_1G,
2107                               MDIO_OVER_1G_UP1, val);
2108
2109         CL45_WR_OVER_CL22(bp, phy,
2110                               MDIO_REG_BANK_OVER_1G,
2111                               MDIO_OVER_1G_UP3, 0x400);
2112 }
2113
2114 static void bnx2x_calc_ieee_aneg_adv(struct bnx2x_phy *phy,
2115                                      struct link_params *params, u16 *ieee_fc)
2116 {
2117         struct bnx2x *bp = params->bp;
2118         *ieee_fc = MDIO_COMBO_IEEE0_AUTO_NEG_ADV_FULL_DUPLEX;
2119         /* resolve pause mode and advertisement
2120          * Please refer to Table 28B-3 of the 802.3ab-1999 spec */
2121
2122         switch (phy->req_flow_ctrl) {
2123         case BNX2X_FLOW_CTRL_AUTO:
2124                 if (params->req_fc_auto_adv == BNX2X_FLOW_CTRL_BOTH) {
2125                         *ieee_fc |=
2126                              MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_BOTH;
2127                 } else {
2128                         *ieee_fc |=
2129                        MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_ASYMMETRIC;
2130                 }
2131                 break;
2132         case BNX2X_FLOW_CTRL_TX:
2133                 *ieee_fc |=
2134                        MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_ASYMMETRIC;
2135                 break;
2136
2137         case BNX2X_FLOW_CTRL_RX:
2138         case BNX2X_FLOW_CTRL_BOTH:
2139                 *ieee_fc |= MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_BOTH;
2140                 break;
2141
2142         case BNX2X_FLOW_CTRL_NONE:
2143         default:
2144                 *ieee_fc |= MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_NONE;
2145                 break;
2146         }
2147         DP(NETIF_MSG_LINK, "ieee_fc = 0x%x\n", *ieee_fc);
2148 }
2149
2150 static void bnx2x_set_ieee_aneg_advertisment(struct bnx2x_phy *phy,
2151                                              struct link_params *params,
2152                                            u16 ieee_fc)
2153 {
2154         struct bnx2x *bp = params->bp;
2155         u16 val;
2156         /* for AN, we are always publishing full duplex */
2157
2158         CL45_WR_OVER_CL22(bp, phy,
2159                               MDIO_REG_BANK_COMBO_IEEE0,
2160                               MDIO_COMBO_IEEE0_AUTO_NEG_ADV, ieee_fc);
2161         CL45_RD_OVER_CL22(bp, phy,
2162                               MDIO_REG_BANK_CL73_IEEEB1,
2163                               MDIO_CL73_IEEEB1_AN_ADV1, &val);
2164         val &= ~MDIO_CL73_IEEEB1_AN_ADV1_PAUSE_BOTH;
2165         val |= ((ieee_fc<<3) & MDIO_CL73_IEEEB1_AN_ADV1_PAUSE_MASK);
2166         CL45_WR_OVER_CL22(bp, phy,
2167                               MDIO_REG_BANK_CL73_IEEEB1,
2168                               MDIO_CL73_IEEEB1_AN_ADV1, val);
2169 }
2170
2171 static void bnx2x_restart_autoneg(struct bnx2x_phy *phy,
2172                                   struct link_params *params,
2173                                   u8 enable_cl73)
2174 {
2175         struct bnx2x *bp = params->bp;
2176         u16 mii_control;
2177
2178         DP(NETIF_MSG_LINK, "bnx2x_restart_autoneg\n");
2179         /* Enable and restart BAM/CL37 aneg */
2180
2181         if (enable_cl73) {
2182                 CL45_RD_OVER_CL22(bp, phy,
2183                                       MDIO_REG_BANK_CL73_IEEEB0,
2184                                       MDIO_CL73_IEEEB0_CL73_AN_CONTROL,
2185                                       &mii_control);
2186
2187                 CL45_WR_OVER_CL22(bp, phy,
2188                                 MDIO_REG_BANK_CL73_IEEEB0,
2189                                 MDIO_CL73_IEEEB0_CL73_AN_CONTROL,
2190                                 (mii_control |
2191                                 MDIO_CL73_IEEEB0_CL73_AN_CONTROL_AN_EN |
2192                                 MDIO_CL73_IEEEB0_CL73_AN_CONTROL_RESTART_AN));
2193         } else {
2194
2195                 CL45_RD_OVER_CL22(bp, phy,
2196                                       MDIO_REG_BANK_COMBO_IEEE0,
2197                                       MDIO_COMBO_IEEE0_MII_CONTROL,
2198                                       &mii_control);
2199                 DP(NETIF_MSG_LINK,
2200                          "bnx2x_restart_autoneg mii_control before = 0x%x\n",
2201                          mii_control);
2202                 CL45_WR_OVER_CL22(bp, phy,
2203                                       MDIO_REG_BANK_COMBO_IEEE0,
2204                                       MDIO_COMBO_IEEE0_MII_CONTROL,
2205                                       (mii_control |
2206                                        MDIO_COMBO_IEEO_MII_CONTROL_AN_EN |
2207                                        MDIO_COMBO_IEEO_MII_CONTROL_RESTART_AN));
2208         }
2209 }
2210
2211 static void bnx2x_initialize_sgmii_process(struct bnx2x_phy *phy,
2212                                            struct link_params *params,
2213                                          struct link_vars *vars)
2214 {
2215         struct bnx2x *bp = params->bp;
2216         u16 control1;
2217
2218         /* in SGMII mode, the unicore is always slave */
2219
2220         CL45_RD_OVER_CL22(bp, phy,
2221                               MDIO_REG_BANK_SERDES_DIGITAL,
2222                               MDIO_SERDES_DIGITAL_A_1000X_CONTROL1,
2223                       &control1);
2224         control1 |= MDIO_SERDES_DIGITAL_A_1000X_CONTROL1_INVERT_SIGNAL_DETECT;
2225         /* set sgmii mode (and not fiber) */
2226         control1 &= ~(MDIO_SERDES_DIGITAL_A_1000X_CONTROL1_FIBER_MODE |
2227                       MDIO_SERDES_DIGITAL_A_1000X_CONTROL1_AUTODET |
2228                       MDIO_SERDES_DIGITAL_A_1000X_CONTROL1_MSTR_MODE);
2229         CL45_WR_OVER_CL22(bp, phy,
2230                               MDIO_REG_BANK_SERDES_DIGITAL,
2231                               MDIO_SERDES_DIGITAL_A_1000X_CONTROL1,
2232                               control1);
2233
2234         /* if forced speed */
2235         if (!(vars->line_speed == SPEED_AUTO_NEG)) {
2236                 /* set speed, disable autoneg */
2237                 u16 mii_control;
2238
2239                 CL45_RD_OVER_CL22(bp, phy,
2240                                       MDIO_REG_BANK_COMBO_IEEE0,
2241                                       MDIO_COMBO_IEEE0_MII_CONTROL,
2242                                       &mii_control);
2243                 mii_control &= ~(MDIO_COMBO_IEEO_MII_CONTROL_AN_EN |
2244                                  MDIO_COMBO_IEEO_MII_CONTROL_MAN_SGMII_SP_MASK|
2245                                  MDIO_COMBO_IEEO_MII_CONTROL_FULL_DUPLEX);
2246
2247                 switch (vars->line_speed) {
2248                 case SPEED_100:
2249                         mii_control |=
2250                                 MDIO_COMBO_IEEO_MII_CONTROL_MAN_SGMII_SP_100;
2251                         break;
2252                 case SPEED_1000:
2253                         mii_control |=
2254                                 MDIO_COMBO_IEEO_MII_CONTROL_MAN_SGMII_SP_1000;
2255                         break;
2256                 case SPEED_10:
2257                         /* there is nothing to set for 10M */
2258                         break;
2259                 default:
2260                         /* invalid speed for SGMII */
2261                         DP(NETIF_MSG_LINK, "Invalid line_speed 0x%x\n",
2262                                   vars->line_speed);
2263                         break;
2264                 }
2265
2266                 /* setting the full duplex */
2267                 if (phy->req_duplex == DUPLEX_FULL)
2268                         mii_control |=
2269                                 MDIO_COMBO_IEEO_MII_CONTROL_FULL_DUPLEX;
2270                 CL45_WR_OVER_CL22(bp, phy,
2271                                       MDIO_REG_BANK_COMBO_IEEE0,
2272                                       MDIO_COMBO_IEEE0_MII_CONTROL,
2273                                       mii_control);
2274
2275         } else { /* AN mode */
2276                 /* enable and restart AN */
2277                 bnx2x_restart_autoneg(phy, params, 0);
2278         }
2279 }
2280
2281
2282 /*
2283  * link management
2284  */
2285
2286 static void bnx2x_pause_resolve(struct link_vars *vars, u32 pause_result)
2287 {                                               /*  LD      LP   */
2288         switch (pause_result) {                 /* ASYM P ASYM P */
2289         case 0xb:                               /*   1  0   1  1 */
2290                 vars->flow_ctrl = BNX2X_FLOW_CTRL_TX;
2291                 break;
2292
2293         case 0xe:                               /*   1  1   1  0 */
2294                 vars->flow_ctrl = BNX2X_FLOW_CTRL_RX;
2295                 break;
2296
2297         case 0x5:                               /*   0  1   0  1 */
2298         case 0x7:                               /*   0  1   1  1 */
2299         case 0xd:                               /*   1  1   0  1 */
2300         case 0xf:                               /*   1  1   1  1 */
2301                 vars->flow_ctrl = BNX2X_FLOW_CTRL_BOTH;
2302                 break;
2303
2304         default:
2305                 break;
2306         }
2307         if (pause_result & (1<<0))
2308                 vars->link_status |= LINK_STATUS_LINK_PARTNER_SYMMETRIC_PAUSE;
2309         if (pause_result & (1<<1))
2310                 vars->link_status |= LINK_STATUS_LINK_PARTNER_ASYMMETRIC_PAUSE;
2311 }
2312
2313 static u8 bnx2x_direct_parallel_detect_used(struct bnx2x_phy *phy,
2314                                             struct link_params *params)
2315 {
2316         struct bnx2x *bp = params->bp;
2317         u16 pd_10g, status2_1000x;
2318         if (phy->req_line_speed != SPEED_AUTO_NEG)
2319                 return 0;
2320         CL45_RD_OVER_CL22(bp, phy,
2321                               MDIO_REG_BANK_SERDES_DIGITAL,
2322                               MDIO_SERDES_DIGITAL_A_1000X_STATUS2,
2323                               &status2_1000x);
2324         CL45_RD_OVER_CL22(bp, phy,
2325                               MDIO_REG_BANK_SERDES_DIGITAL,
2326                               MDIO_SERDES_DIGITAL_A_1000X_STATUS2,
2327                               &status2_1000x);
2328         if (status2_1000x & MDIO_SERDES_DIGITAL_A_1000X_STATUS2_AN_DISABLED) {
2329                 DP(NETIF_MSG_LINK, "1G parallel detect link on port %d\n",
2330                          params->port);
2331                 return 1;
2332         }
2333
2334         CL45_RD_OVER_CL22(bp, phy,
2335                               MDIO_REG_BANK_10G_PARALLEL_DETECT,
2336                               MDIO_10G_PARALLEL_DETECT_PAR_DET_10G_STATUS,
2337                               &pd_10g);
2338
2339         if (pd_10g & MDIO_10G_PARALLEL_DETECT_PAR_DET_10G_STATUS_PD_LINK) {
2340                 DP(NETIF_MSG_LINK, "10G parallel detect link on port %d\n",
2341                          params->port);
2342                 return 1;
2343         }
2344         return 0;
2345 }
2346
2347 static void bnx2x_flow_ctrl_resolve(struct bnx2x_phy *phy,
2348                                     struct link_params *params,
2349                                     struct link_vars *vars,
2350                                     u32 gp_status)
2351 {
2352         struct bnx2x *bp = params->bp;
2353         u16 ld_pause;   /* local driver */
2354         u16 lp_pause;   /* link partner */
2355         u16 pause_result;
2356
2357         vars->flow_ctrl = BNX2X_FLOW_CTRL_NONE;
2358
2359         /* resolve from gp_status in case of AN complete and not sgmii */
2360         if (phy->req_flow_ctrl != BNX2X_FLOW_CTRL_AUTO)
2361                 vars->flow_ctrl = phy->req_flow_ctrl;
2362         else if (phy->req_line_speed != SPEED_AUTO_NEG)
2363                 vars->flow_ctrl = params->req_fc_auto_adv;
2364         else if ((gp_status & MDIO_AN_CL73_OR_37_COMPLETE) &&
2365                  (!(vars->phy_flags & PHY_SGMII_FLAG))) {
2366                 if (bnx2x_direct_parallel_detect_used(phy, params)) {
2367                         vars->flow_ctrl = params->req_fc_auto_adv;
2368                         return;
2369                 }
2370                 if ((gp_status &
2371                     (MDIO_GP_STATUS_TOP_AN_STATUS1_CL73_AUTONEG_COMPLETE |
2372                      MDIO_GP_STATUS_TOP_AN_STATUS1_CL73_MR_LP_NP_AN_ABLE)) ==
2373                     (MDIO_GP_STATUS_TOP_AN_STATUS1_CL73_AUTONEG_COMPLETE |
2374                      MDIO_GP_STATUS_TOP_AN_STATUS1_CL73_MR_LP_NP_AN_ABLE)) {
2375
2376                         CL45_RD_OVER_CL22(bp, phy,
2377                                               MDIO_REG_BANK_CL73_IEEEB1,
2378                                               MDIO_CL73_IEEEB1_AN_ADV1,
2379                                               &ld_pause);
2380                         CL45_RD_OVER_CL22(bp, phy,
2381                                              MDIO_REG_BANK_CL73_IEEEB1,
2382                                              MDIO_CL73_IEEEB1_AN_LP_ADV1,
2383                                              &lp_pause);
2384                         pause_result = (ld_pause &
2385                                         MDIO_CL73_IEEEB1_AN_ADV1_PAUSE_MASK)
2386                                         >> 8;
2387                         pause_result |= (lp_pause &
2388                                         MDIO_CL73_IEEEB1_AN_LP_ADV1_PAUSE_MASK)
2389                                         >> 10;
2390                         DP(NETIF_MSG_LINK, "pause_result CL73 0x%x\n",
2391                                  pause_result);
2392                 } else {
2393                         CL45_RD_OVER_CL22(bp, phy,
2394                                               MDIO_REG_BANK_COMBO_IEEE0,
2395                                               MDIO_COMBO_IEEE0_AUTO_NEG_ADV,
2396                                               &ld_pause);
2397                         CL45_RD_OVER_CL22(bp, phy,
2398                                MDIO_REG_BANK_COMBO_IEEE0,
2399                                MDIO_COMBO_IEEE0_AUTO_NEG_LINK_PARTNER_ABILITY1,
2400                                &lp_pause);
2401                         pause_result = (ld_pause &
2402                                 MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_MASK)>>5;
2403                         pause_result |= (lp_pause &
2404                                  MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_MASK)>>7;
2405                         DP(NETIF_MSG_LINK, "pause_result CL37 0x%x\n",
2406                                  pause_result);
2407                 }
2408                 bnx2x_pause_resolve(vars, pause_result);
2409         }
2410         DP(NETIF_MSG_LINK, "flow_ctrl 0x%x\n", vars->flow_ctrl);
2411 }
2412
2413 static void bnx2x_check_fallback_to_cl37(struct bnx2x_phy *phy,
2414                                          struct link_params *params)
2415 {
2416         struct bnx2x *bp = params->bp;
2417         u16 rx_status, ustat_val, cl37_fsm_recieved;
2418         DP(NETIF_MSG_LINK, "bnx2x_check_fallback_to_cl37\n");
2419         /* Step 1: Make sure signal is detected */
2420         CL45_RD_OVER_CL22(bp, phy,
2421                               MDIO_REG_BANK_RX0,
2422                               MDIO_RX0_RX_STATUS,
2423                               &rx_status);
2424         if ((rx_status & MDIO_RX0_RX_STATUS_SIGDET) !=
2425             (MDIO_RX0_RX_STATUS_SIGDET)) {
2426                 DP(NETIF_MSG_LINK, "Signal is not detected. Restoring CL73."
2427                              "rx_status(0x80b0) = 0x%x\n", rx_status);
2428                 CL45_WR_OVER_CL22(bp, phy,
2429                                       MDIO_REG_BANK_CL73_IEEEB0,
2430                                       MDIO_CL73_IEEEB0_CL73_AN_CONTROL,
2431                                       MDIO_CL73_IEEEB0_CL73_AN_CONTROL_AN_EN);
2432                 return;
2433         }
2434         /* Step 2: Check CL73 state machine */
2435         CL45_RD_OVER_CL22(bp, phy,
2436                               MDIO_REG_BANK_CL73_USERB0,
2437                               MDIO_CL73_USERB0_CL73_USTAT1,
2438                               &ustat_val);
2439         if ((ustat_val &
2440              (MDIO_CL73_USERB0_CL73_USTAT1_LINK_STATUS_CHECK |
2441               MDIO_CL73_USERB0_CL73_USTAT1_AN_GOOD_CHECK_BAM37)) !=
2442             (MDIO_CL73_USERB0_CL73_USTAT1_LINK_STATUS_CHECK |
2443               MDIO_CL73_USERB0_CL73_USTAT1_AN_GOOD_CHECK_BAM37)) {
2444                 DP(NETIF_MSG_LINK, "CL73 state-machine is not stable. "
2445                              "ustat_val(0x8371) = 0x%x\n", ustat_val);
2446                 return;
2447         }
2448         /* Step 3: Check CL37 Message Pages received to indicate LP
2449         supports only CL37 */
2450         CL45_RD_OVER_CL22(bp, phy,
2451                               MDIO_REG_BANK_REMOTE_PHY,
2452                               MDIO_REMOTE_PHY_MISC_RX_STATUS,
2453                               &cl37_fsm_recieved);
2454         if ((cl37_fsm_recieved &
2455              (MDIO_REMOTE_PHY_MISC_RX_STATUS_CL37_FSM_RECEIVED_OVER1G_MSG |
2456              MDIO_REMOTE_PHY_MISC_RX_STATUS_CL37_FSM_RECEIVED_BRCM_OUI_MSG)) !=
2457             (MDIO_REMOTE_PHY_MISC_RX_STATUS_CL37_FSM_RECEIVED_OVER1G_MSG |
2458               MDIO_REMOTE_PHY_MISC_RX_STATUS_CL37_FSM_RECEIVED_BRCM_OUI_MSG)) {
2459                 DP(NETIF_MSG_LINK, "No CL37 FSM were received. "
2460                              "misc_rx_status(0x8330) = 0x%x\n",
2461                          cl37_fsm_recieved);
2462                 return;
2463         }
2464         /* The combined cl37/cl73 fsm state information indicating that we are
2465         connected to a device which does not support cl73, but does support
2466         cl37 BAM. In this case we disable cl73 and restart cl37 auto-neg */
2467         /* Disable CL73 */
2468         CL45_WR_OVER_CL22(bp, phy,
2469                               MDIO_REG_BANK_CL73_IEEEB0,
2470                               MDIO_CL73_IEEEB0_CL73_AN_CONTROL,
2471                               0);
2472         /* Restart CL37 autoneg */
2473         bnx2x_restart_autoneg(phy, params, 0);
2474         DP(NETIF_MSG_LINK, "Disabling CL73, and restarting CL37 autoneg\n");
2475 }
2476
2477 static void bnx2x_xgxs_an_resolve(struct bnx2x_phy *phy,
2478                                   struct link_params *params,
2479                                   struct link_vars *vars,
2480                                   u32 gp_status)
2481 {
2482         if (gp_status & MDIO_AN_CL73_OR_37_COMPLETE)
2483                 vars->link_status |=
2484                         LINK_STATUS_AUTO_NEGOTIATE_COMPLETE;
2485
2486         if (bnx2x_direct_parallel_detect_used(phy, params))
2487                 vars->link_status |=
2488                         LINK_STATUS_PARALLEL_DETECTION_USED;
2489 }
2490
2491 static u8 bnx2x_link_settings_status(struct bnx2x_phy *phy,
2492                                      struct link_params *params,
2493                                      struct link_vars *vars)
2494 {
2495         struct bnx2x *bp = params->bp;
2496         u16 new_line_speed , gp_status;
2497         u8 rc = 0;
2498
2499         /* Read gp_status */
2500         CL45_RD_OVER_CL22(bp, phy,
2501                                 MDIO_REG_BANK_GP_STATUS,
2502                                 MDIO_GP_STATUS_TOP_AN_STATUS1,
2503                                 &gp_status);
2504
2505         if (phy->req_line_speed == SPEED_AUTO_NEG)
2506                 vars->link_status |= LINK_STATUS_AUTO_NEGOTIATE_ENABLED;
2507         if (gp_status & MDIO_GP_STATUS_TOP_AN_STATUS1_LINK_STATUS) {
2508                 DP(NETIF_MSG_LINK, "phy link up gp_status=0x%x\n",
2509                          gp_status);
2510
2511                 vars->phy_link_up = 1;
2512                 vars->link_status |= LINK_STATUS_LINK_UP;
2513
2514                 if (gp_status & MDIO_GP_STATUS_TOP_AN_STATUS1_DUPLEX_STATUS)
2515                         vars->duplex = DUPLEX_FULL;
2516                 else
2517                         vars->duplex = DUPLEX_HALF;
2518
2519                 if (SINGLE_MEDIA_DIRECT(params)) {
2520                         bnx2x_flow_ctrl_resolve(phy, params, vars, gp_status);
2521                         if (phy->req_line_speed == SPEED_AUTO_NEG)
2522                                 bnx2x_xgxs_an_resolve(phy, params, vars,
2523                                                       gp_status);
2524                 }
2525
2526                 switch (gp_status & GP_STATUS_SPEED_MASK) {
2527                 case GP_STATUS_10M:
2528                         new_line_speed = SPEED_10;
2529                         if (vars->duplex == DUPLEX_FULL)
2530                                 vars->link_status |= LINK_10TFD;
2531                         else
2532                                 vars->link_status |= LINK_10THD;
2533                         break;
2534
2535                 case GP_STATUS_100M:
2536                         new_line_speed = SPEED_100;
2537                         if (vars->duplex == DUPLEX_FULL)
2538                                 vars->link_status |= LINK_100TXFD;
2539                         else
2540                                 vars->link_status |= LINK_100TXHD;
2541                         break;
2542
2543                 case GP_STATUS_1G:
2544                 case GP_STATUS_1G_KX:
2545                         new_line_speed = SPEED_1000;
2546                         if (vars->duplex == DUPLEX_FULL)
2547                                 vars->link_status |= LINK_1000TFD;
2548                         else
2549                                 vars->link_status |= LINK_1000THD;
2550                         break;
2551
2552                 case GP_STATUS_2_5G:
2553                         new_line_speed = SPEED_2500;
2554                         if (vars->duplex == DUPLEX_FULL)
2555                                 vars->link_status |= LINK_2500TFD;
2556                         else
2557                                 vars->link_status |= LINK_2500THD;
2558                         break;
2559
2560                 case GP_STATUS_5G:
2561                 case GP_STATUS_6G:
2562                         DP(NETIF_MSG_LINK,
2563                                  "link speed unsupported  gp_status 0x%x\n",
2564                                   gp_status);
2565                         return -EINVAL;
2566
2567                 case GP_STATUS_10G_KX4:
2568                 case GP_STATUS_10G_HIG:
2569                 case GP_STATUS_10G_CX4:
2570                         new_line_speed = SPEED_10000;
2571                         vars->link_status |= LINK_10GTFD;
2572                         break;
2573
2574                 case GP_STATUS_12G_HIG:
2575                         new_line_speed = SPEED_12000;
2576                         vars->link_status |= LINK_12GTFD;
2577                         break;
2578
2579                 case GP_STATUS_12_5G:
2580                         new_line_speed = SPEED_12500;
2581                         vars->link_status |= LINK_12_5GTFD;
2582                         break;
2583
2584                 case GP_STATUS_13G:
2585                         new_line_speed = SPEED_13000;
2586                         vars->link_status |= LINK_13GTFD;
2587                         break;
2588
2589                 case GP_STATUS_15G:
2590                         new_line_speed = SPEED_15000;
2591                         vars->link_status |= LINK_15GTFD;
2592                         break;
2593
2594                 case GP_STATUS_16G:
2595                         new_line_speed = SPEED_16000;
2596                         vars->link_status |= LINK_16GTFD;
2597                         break;
2598
2599                 default:
2600                         DP(NETIF_MSG_LINK,
2601                                   "link speed unsupported gp_status 0x%x\n",
2602                                   gp_status);
2603                         return -EINVAL;
2604                 }
2605
2606                 vars->line_speed = new_line_speed;
2607
2608         } else { /* link_down */
2609                 DP(NETIF_MSG_LINK, "phy link down\n");
2610
2611                 vars->phy_link_up = 0;
2612
2613                 vars->duplex = DUPLEX_FULL;
2614                 vars->flow_ctrl = BNX2X_FLOW_CTRL_NONE;
2615                 vars->mac_type = MAC_TYPE_NONE;
2616
2617                 if ((phy->req_line_speed == SPEED_AUTO_NEG) &&
2618                     SINGLE_MEDIA_DIRECT(params)) {
2619                         /* Check signal is detected */
2620                         bnx2x_check_fallback_to_cl37(phy, params);
2621                 }
2622         }
2623
2624         DP(NETIF_MSG_LINK, "gp_status 0x%x  phy_link_up %x line_speed %x\n",
2625                  gp_status, vars->phy_link_up, vars->line_speed);
2626         DP(NETIF_MSG_LINK, "duplex %x  flow_ctrl 0x%x link_status 0x%x\n",
2627                    vars->duplex, vars->flow_ctrl, vars->link_status);
2628         return rc;
2629 }
2630
2631 static void bnx2x_set_gmii_tx_driver(struct link_params *params)
2632 {
2633         struct bnx2x *bp = params->bp;
2634         struct bnx2x_phy *phy = &params->phy[INT_PHY];
2635         u16 lp_up2;
2636         u16 tx_driver;
2637         u16 bank;
2638
2639         /* read precomp */
2640         CL45_RD_OVER_CL22(bp, phy,
2641                               MDIO_REG_BANK_OVER_1G,
2642                               MDIO_OVER_1G_LP_UP2, &lp_up2);
2643
2644         /* bits [10:7] at lp_up2, positioned at [15:12] */
2645         lp_up2 = (((lp_up2 & MDIO_OVER_1G_LP_UP2_PREEMPHASIS_MASK) >>
2646                    MDIO_OVER_1G_LP_UP2_PREEMPHASIS_SHIFT) <<
2647                   MDIO_TX0_TX_DRIVER_PREEMPHASIS_SHIFT);
2648
2649         if (lp_up2 == 0)
2650                 return;
2651
2652         for (bank = MDIO_REG_BANK_TX0; bank <= MDIO_REG_BANK_TX3;
2653               bank += (MDIO_REG_BANK_TX1 - MDIO_REG_BANK_TX0)) {
2654                 CL45_RD_OVER_CL22(bp, phy,
2655                                       bank,
2656                                       MDIO_TX0_TX_DRIVER, &tx_driver);
2657
2658                 /* replace tx_driver bits [15:12] */
2659                 if (lp_up2 !=
2660                     (tx_driver & MDIO_TX0_TX_DRIVER_PREEMPHASIS_MASK)) {
2661                         tx_driver &= ~MDIO_TX0_TX_DRIVER_PREEMPHASIS_MASK;
2662                         tx_driver |= lp_up2;
2663                         CL45_WR_OVER_CL22(bp, phy,
2664                                               bank,
2665                                               MDIO_TX0_TX_DRIVER, tx_driver);
2666                 }
2667         }
2668 }
2669
2670 static u8 bnx2x_emac_program(struct link_params *params,
2671                              struct link_vars *vars)
2672 {
2673         struct bnx2x *bp = params->bp;
2674         u8 port = params->port;
2675         u16 mode = 0;
2676
2677         DP(NETIF_MSG_LINK, "setting link speed & duplex\n");
2678         bnx2x_bits_dis(bp, GRCBASE_EMAC0 + port*0x400 +
2679                      EMAC_REG_EMAC_MODE,
2680                      (EMAC_MODE_25G_MODE |
2681                      EMAC_MODE_PORT_MII_10M |
2682                      EMAC_MODE_HALF_DUPLEX));
2683         switch (vars->line_speed) {
2684         case SPEED_10:
2685                 mode |= EMAC_MODE_PORT_MII_10M;
2686                 break;
2687
2688         case SPEED_100:
2689                 mode |= EMAC_MODE_PORT_MII;
2690                 break;
2691
2692         case SPEED_1000:
2693                 mode |= EMAC_MODE_PORT_GMII;
2694                 break;
2695
2696         case SPEED_2500:
2697                 mode |= (EMAC_MODE_25G_MODE | EMAC_MODE_PORT_GMII);
2698                 break;
2699
2700         default:
2701                 /* 10G not valid for EMAC */
2702                 DP(NETIF_MSG_LINK, "Invalid line_speed 0x%x\n",
2703                            vars->line_speed);
2704                 return -EINVAL;
2705         }
2706
2707         if (vars->duplex == DUPLEX_HALF)
2708                 mode |= EMAC_MODE_HALF_DUPLEX;
2709         bnx2x_bits_en(bp,
2710                     GRCBASE_EMAC0 + port*0x400 + EMAC_REG_EMAC_MODE,
2711                     mode);
2712
2713         bnx2x_set_led(params, vars, LED_MODE_OPER, vars->line_speed);
2714         return 0;
2715 }
2716
2717 static void bnx2x_set_preemphasis(struct bnx2x_phy *phy,
2718                                   struct link_params *params)
2719 {
2720
2721         u16 bank, i = 0;
2722         struct bnx2x *bp = params->bp;
2723
2724         for (bank = MDIO_REG_BANK_RX0, i = 0; bank <= MDIO_REG_BANK_RX3;
2725               bank += (MDIO_REG_BANK_RX1-MDIO_REG_BANK_RX0), i++) {
2726                         CL45_WR_OVER_CL22(bp, phy,
2727                                           bank,
2728                                           MDIO_RX0_RX_EQ_BOOST,
2729                                           phy->rx_preemphasis[i]);
2730         }
2731
2732         for (bank = MDIO_REG_BANK_TX0, i = 0; bank <= MDIO_REG_BANK_TX3;
2733                       bank += (MDIO_REG_BANK_TX1 - MDIO_REG_BANK_TX0), i++) {
2734                         CL45_WR_OVER_CL22(bp, phy,
2735                                           bank,
2736                                           MDIO_TX0_TX_DRIVER,
2737                                           phy->tx_preemphasis[i]);
2738         }
2739 }
2740
2741 static void bnx2x_init_internal_phy(struct bnx2x_phy *phy,
2742                                     struct link_params *params,
2743                                     struct link_vars *vars)
2744 {
2745         struct bnx2x *bp = params->bp;
2746         u8 enable_cl73 = (SINGLE_MEDIA_DIRECT(params) ||
2747                           (params->loopback_mode == LOOPBACK_XGXS));
2748         if (!(vars->phy_flags & PHY_SGMII_FLAG)) {
2749                 if (SINGLE_MEDIA_DIRECT(params) &&
2750                     (params->feature_config_flags &
2751                      FEATURE_CONFIG_OVERRIDE_PREEMPHASIS_ENABLED))
2752                         bnx2x_set_preemphasis(phy, params);
2753
2754                 /* forced speed requested? */
2755                 if (vars->line_speed != SPEED_AUTO_NEG ||
2756                     (SINGLE_MEDIA_DIRECT(params) &&
2757                           params->loopback_mode == LOOPBACK_EXT)) {
2758                         DP(NETIF_MSG_LINK, "not SGMII, no AN\n");
2759
2760                         /* disable autoneg */
2761                         bnx2x_set_autoneg(phy, params, vars, 0);
2762
2763                         /* program speed and duplex */
2764                         bnx2x_program_serdes(phy, params, vars);
2765
2766                 } else { /* AN_mode */
2767                         DP(NETIF_MSG_LINK, "not SGMII, AN\n");
2768
2769                         /* AN enabled */
2770                         bnx2x_set_brcm_cl37_advertisment(phy, params);
2771
2772                         /* program duplex & pause advertisement (for aneg) */
2773                         bnx2x_set_ieee_aneg_advertisment(phy, params,
2774                                                        vars->ieee_fc);
2775
2776                         /* enable autoneg */
2777                         bnx2x_set_autoneg(phy, params, vars, enable_cl73);
2778
2779                         /* enable and restart AN */
2780                         bnx2x_restart_autoneg(phy, params, enable_cl73);
2781                 }
2782
2783         } else { /* SGMII mode */
2784                 DP(NETIF_MSG_LINK, "SGMII\n");
2785
2786                 bnx2x_initialize_sgmii_process(phy, params, vars);
2787         }
2788 }
2789
2790 static u8 bnx2x_init_serdes(struct bnx2x_phy *phy,
2791                             struct link_params *params,
2792                             struct link_vars *vars)
2793 {
2794         u8 rc;
2795         vars->phy_flags |= PHY_SGMII_FLAG;
2796         bnx2x_calc_ieee_aneg_adv(phy, params, &vars->ieee_fc);
2797         bnx2x_set_aer_mmd_serdes(params->bp, phy);
2798         rc = bnx2x_reset_unicore(params, phy, 1);
2799         /* reset the SerDes and wait for reset bit return low */
2800         if (rc != 0)
2801                 return rc;
2802         bnx2x_set_aer_mmd_serdes(params->bp, phy);
2803
2804         return rc;
2805 }
2806
2807 static u8 bnx2x_init_xgxs(struct bnx2x_phy *phy,
2808                           struct link_params *params,
2809                           struct link_vars *vars)
2810 {
2811         u8 rc;
2812         vars->phy_flags = PHY_XGXS_FLAG;
2813         if ((phy->req_line_speed &&
2814              ((phy->req_line_speed == SPEED_100) ||
2815               (phy->req_line_speed == SPEED_10))) ||
2816             (!phy->req_line_speed &&
2817              (phy->speed_cap_mask >=
2818               PORT_HW_CFG_SPEED_CAPABILITY_D0_10M_FULL) &&
2819              (phy->speed_cap_mask <
2820               PORT_HW_CFG_SPEED_CAPABILITY_D0_1G)
2821              ))
2822                 vars->phy_flags |= PHY_SGMII_FLAG;
2823         else
2824                 vars->phy_flags &= ~PHY_SGMII_FLAG;
2825
2826         bnx2x_calc_ieee_aneg_adv(phy, params, &vars->ieee_fc);
2827         bnx2x_set_aer_mmd_xgxs(params, phy);
2828         bnx2x_set_master_ln(params, phy);
2829
2830         rc = bnx2x_reset_unicore(params, phy, 0);
2831         /* reset the SerDes and wait for reset bit return low */
2832         if (rc != 0)
2833                 return rc;
2834
2835         bnx2x_set_aer_mmd_xgxs(params, phy);
2836
2837         /* setting the masterLn_def again after the reset */
2838         bnx2x_set_master_ln(params, phy);
2839         bnx2x_set_swap_lanes(params, phy);
2840
2841         return rc;
2842 }
2843
2844 static u16 bnx2x_wait_reset_complete(struct bnx2x *bp,
2845                                      struct bnx2x_phy *phy)
2846 {
2847         u16 cnt, ctrl;
2848         /* Wait for soft reset to get cleared upto 1 sec */
2849         for (cnt = 0; cnt < 1000; cnt++) {
2850                 bnx2x_cl45_read(bp, phy,
2851                                 MDIO_PMA_DEVAD, MDIO_PMA_REG_CTRL, &ctrl);
2852                 if (!(ctrl & (1<<15)))
2853                         break;
2854                 msleep(1);
2855         }
2856         DP(NETIF_MSG_LINK, "control reg 0x%x (after %d ms)\n", ctrl, cnt);
2857         return cnt;
2858 }
2859
2860 static void bnx2x_link_int_enable(struct link_params *params)
2861 {
2862         u8 port = params->port;
2863         u32 mask;
2864         struct bnx2x *bp = params->bp;
2865
2866         /* setting the status to report on link up
2867            for either XGXS or SerDes */
2868
2869         if (params->switch_cfg == SWITCH_CFG_10G) {
2870                 mask = (NIG_MASK_XGXS0_LINK10G |
2871                         NIG_MASK_XGXS0_LINK_STATUS);
2872                 DP(NETIF_MSG_LINK, "enabled XGXS interrupt\n");
2873                 if (!(SINGLE_MEDIA_DIRECT(params)) &&
2874                         params->phy[INT_PHY].type !=
2875                                 PORT_HW_CFG_XGXS_EXT_PHY_TYPE_FAILURE) {
2876                         mask |= NIG_MASK_MI_INT;
2877                         DP(NETIF_MSG_LINK, "enabled external phy int\n");
2878                 }
2879
2880         } else { /* SerDes */
2881                 mask = NIG_MASK_SERDES0_LINK_STATUS;
2882                 DP(NETIF_MSG_LINK, "enabled SerDes interrupt\n");
2883                 if (!(SINGLE_MEDIA_DIRECT(params)) &&
2884                         params->phy[INT_PHY].type !=
2885                                 PORT_HW_CFG_SERDES_EXT_PHY_TYPE_NOT_CONN) {
2886                         mask |= NIG_MASK_MI_INT;
2887                         DP(NETIF_MSG_LINK, "enabled external phy int\n");
2888                 }
2889         }
2890         bnx2x_bits_en(bp,
2891                       NIG_REG_MASK_INTERRUPT_PORT0 + port*4,
2892                       mask);
2893
2894         DP(NETIF_MSG_LINK, "port %x, is_xgxs %x, int_status 0x%x\n", port,
2895                  (params->switch_cfg == SWITCH_CFG_10G),
2896                  REG_RD(bp, NIG_REG_STATUS_INTERRUPT_PORT0 + port*4));
2897         DP(NETIF_MSG_LINK, " int_mask 0x%x, MI_INT %x, SERDES_LINK %x\n",
2898                  REG_RD(bp, NIG_REG_MASK_INTERRUPT_PORT0 + port*4),
2899                  REG_RD(bp, NIG_REG_EMAC0_STATUS_MISC_MI_INT + port*0x18),
2900                  REG_RD(bp, NIG_REG_SERDES0_STATUS_LINK_STATUS+port*0x3c));
2901         DP(NETIF_MSG_LINK, " 10G %x, XGXS_LINK %x\n",
2902            REG_RD(bp, NIG_REG_XGXS0_STATUS_LINK10G + port*0x68),
2903            REG_RD(bp, NIG_REG_XGXS0_STATUS_LINK_STATUS + port*0x68));
2904 }
2905
2906 static void bnx2x_rearm_latch_signal(struct bnx2x *bp, u8 port,
2907                                      u8 exp_mi_int)
2908 {
2909         u32 latch_status = 0;
2910
2911         /**
2912          * Disable the MI INT ( external phy int ) by writing 1 to the
2913          * status register. Link down indication is high-active-signal,
2914          * so in this case we need to write the status to clear the XOR
2915          */
2916         /* Read Latched signals */
2917         latch_status = REG_RD(bp,
2918                                     NIG_REG_LATCH_STATUS_0 + port*8);
2919         DP(NETIF_MSG_LINK, "latch_status = 0x%x\n", latch_status);
2920         /* Handle only those with latched-signal=up.*/
2921         if (exp_mi_int)
2922                 bnx2x_bits_en(bp,
2923                               NIG_REG_STATUS_INTERRUPT_PORT0
2924                               + port*4,
2925                               NIG_STATUS_EMAC0_MI_INT);
2926         else
2927                 bnx2x_bits_dis(bp,
2928                                NIG_REG_STATUS_INTERRUPT_PORT0
2929                                + port*4,
2930                                NIG_STATUS_EMAC0_MI_INT);
2931
2932         if (latch_status & 1) {
2933
2934                 /* For all latched-signal=up : Re-Arm Latch signals */
2935                 REG_WR(bp, NIG_REG_LATCH_STATUS_0 + port*8,
2936                              (latch_status & 0xfffe) | (latch_status & 1));
2937         }
2938         /* For all latched-signal=up,Write original_signal to status */
2939 }
2940
2941 static void bnx2x_link_int_ack(struct link_params *params,
2942                              struct link_vars *vars, u8 is_10g)
2943 {
2944         struct bnx2x *bp = params->bp;
2945         u8 port = params->port;
2946
2947         /* first reset all status
2948          * we assume only one line will be change at a time */
2949         bnx2x_bits_dis(bp, NIG_REG_STATUS_INTERRUPT_PORT0 + port*4,
2950                      (NIG_STATUS_XGXS0_LINK10G |
2951                       NIG_STATUS_XGXS0_LINK_STATUS |
2952                       NIG_STATUS_SERDES0_LINK_STATUS));
2953         if (vars->phy_link_up) {
2954                 if (is_10g) {
2955                         /* Disable the 10G link interrupt
2956                          * by writing 1 to the status register
2957                          */
2958                         DP(NETIF_MSG_LINK, "10G XGXS phy link up\n");
2959                         bnx2x_bits_en(bp,
2960                                       NIG_REG_STATUS_INTERRUPT_PORT0 + port*4,
2961                                       NIG_STATUS_XGXS0_LINK10G);
2962
2963                 } else if (params->switch_cfg == SWITCH_CFG_10G) {
2964                         /* Disable the link interrupt
2965                          * by writing 1 to the relevant lane
2966                          * in the status register
2967                          */
2968                         u32 ser_lane = ((params->lane_config &
2969                                     PORT_HW_CFG_LANE_SWAP_CFG_MASTER_MASK) >>
2970                                     PORT_HW_CFG_LANE_SWAP_CFG_MASTER_SHIFT);
2971
2972                         DP(NETIF_MSG_LINK, "%d speed XGXS phy link up\n",
2973                                  vars->line_speed);
2974                         bnx2x_bits_en(bp,
2975                                       NIG_REG_STATUS_INTERRUPT_PORT0 + port*4,
2976                                       ((1 << ser_lane) <<
2977                                        NIG_STATUS_XGXS0_LINK_STATUS_SIZE));
2978
2979                 } else { /* SerDes */
2980                         DP(NETIF_MSG_LINK, "SerDes phy link up\n");
2981                         /* Disable the link interrupt
2982                          * by writing 1 to the status register
2983                          */
2984                         bnx2x_bits_en(bp,
2985                                       NIG_REG_STATUS_INTERRUPT_PORT0 + port*4,
2986                                       NIG_STATUS_SERDES0_LINK_STATUS);
2987                 }
2988
2989         }
2990 }
2991
2992 static u8 bnx2x_format_ver(u32 num, u8 *str, u16 *len)
2993 {
2994         u8 *str_ptr = str;
2995         u32 mask = 0xf0000000;
2996         u8 shift = 8*4;
2997         u8 digit;
2998         u8 remove_leading_zeros = 1;
2999         if (*len < 10) {
3000                 /* Need more than 10chars for this format */
3001                 *str_ptr = '\0';
3002                 (*len)--;
3003                 return -EINVAL;
3004         }
3005         while (shift > 0) {
3006
3007                 shift -= 4;
3008                 digit = ((num & mask) >> shift);
3009                 if (digit == 0 && remove_leading_zeros) {
3010                         mask = mask >> 4;
3011                         continue;
3012                 } else if (digit < 0xa)
3013                         *str_ptr = digit + '0';
3014                 else
3015                         *str_ptr = digit - 0xa + 'a';
3016                 remove_leading_zeros = 0;
3017                 str_ptr++;
3018                 (*len)--;
3019                 mask = mask >> 4;
3020                 if (shift == 4*4) {
3021                         *str_ptr = '.';
3022                         str_ptr++;
3023                         (*len)--;
3024                         remove_leading_zeros = 1;
3025                 }
3026         }
3027         return 0;
3028 }
3029
3030
3031 static u8 bnx2x_null_format_ver(u32 spirom_ver, u8 *str, u16 *len)
3032 {
3033         str[0] = '\0';
3034         (*len)--;
3035         return 0;
3036 }
3037
3038 u8 bnx2x_get_ext_phy_fw_version(struct link_params *params, u8 driver_loaded,
3039                               u8 *version, u16 len)
3040 {
3041         struct bnx2x *bp;
3042         u32 spirom_ver = 0;
3043         u8 status = 0;
3044         u8 *ver_p = version;
3045         u16 remain_len = len;
3046         if (version == NULL || params == NULL)
3047                 return -EINVAL;
3048         bp = params->bp;
3049
3050         /* Extract first external phy*/
3051         version[0] = '\0';
3052         spirom_ver = REG_RD(bp, params->phy[EXT_PHY1].ver_addr);
3053
3054         if (params->phy[EXT_PHY1].format_fw_ver) {
3055                 status |= params->phy[EXT_PHY1].format_fw_ver(spirom_ver,
3056                                                               ver_p,
3057                                                               &remain_len);
3058                 ver_p += (len - remain_len);
3059         }
3060         if ((params->num_phys == MAX_PHYS) &&
3061             (params->phy[EXT_PHY2].ver_addr != 0)) {
3062                 spirom_ver = REG_RD(bp,
3063                                           params->phy[EXT_PHY2].ver_addr);
3064                 if (params->phy[EXT_PHY2].format_fw_ver) {
3065                         *ver_p = '/';
3066                         ver_p++;
3067                         remain_len--;
3068                         status |= params->phy[EXT_PHY2].format_fw_ver(
3069                                 spirom_ver,
3070                                 ver_p,
3071                                 &remain_len);
3072                         ver_p = version + (len - remain_len);
3073                 }
3074         }
3075         *ver_p = '\0';
3076         return status;
3077 }
3078
3079 static void bnx2x_set_xgxs_loopback(struct bnx2x_phy *phy,
3080                                     struct link_params *params)
3081 {
3082         u8 port = params->port;
3083         struct bnx2x *bp = params->bp;
3084
3085         if (phy->req_line_speed != SPEED_1000) {
3086                 u32 md_devad;
3087
3088                 DP(NETIF_MSG_LINK, "XGXS 10G loopback enable\n");
3089
3090                 /* change the uni_phy_addr in the nig */
3091                 md_devad = REG_RD(bp, (NIG_REG_XGXS0_CTRL_MD_DEVAD +
3092                                           port*0x18));
3093
3094                 REG_WR(bp, NIG_REG_XGXS0_CTRL_MD_DEVAD + port*0x18, 0x5);
3095
3096                 bnx2x_cl45_write(bp, phy,
3097                                5,
3098                                (MDIO_REG_BANK_AER_BLOCK +
3099                                 (MDIO_AER_BLOCK_AER_REG & 0xf)),
3100                                0x2800);
3101
3102                 bnx2x_cl45_write(bp, phy,
3103                                5,
3104                                (MDIO_REG_BANK_CL73_IEEEB0 +
3105                                 (MDIO_CL73_IEEEB0_CL73_AN_CONTROL & 0xf)),
3106                                0x6041);
3107                 msleep(200);
3108                 /* set aer mmd back */
3109                 bnx2x_set_aer_mmd_xgxs(params, phy);
3110
3111                 /* and md_devad */
3112                 REG_WR(bp, NIG_REG_XGXS0_CTRL_MD_DEVAD + port*0x18,
3113                             md_devad);
3114
3115         } else {
3116                 u16 mii_ctrl;
3117                 DP(NETIF_MSG_LINK, "XGXS 1G loopback enable\n");
3118                 bnx2x_cl45_read(bp, phy, 5,
3119                                 (MDIO_REG_BANK_COMBO_IEEE0 +
3120                                 (MDIO_COMBO_IEEE0_MII_CONTROL & 0xf)),
3121                                 &mii_ctrl);
3122                 bnx2x_cl45_write(bp, phy, 5,
3123                                  (MDIO_REG_BANK_COMBO_IEEE0 +
3124                                  (MDIO_COMBO_IEEE0_MII_CONTROL & 0xf)),
3125                                  mii_ctrl |
3126                                  MDIO_COMBO_IEEO_MII_CONTROL_LOOPBACK);
3127         }
3128 }
3129
3130 u8 bnx2x_set_led(struct link_params *params,
3131                  struct link_vars *vars, u8 mode, u32 speed)
3132 {
3133         u8 port = params->port;
3134         u16 hw_led_mode = params->hw_led_mode;
3135         u8 rc = 0, phy_idx;
3136         u32 tmp;
3137         u32 emac_base = port ? GRCBASE_EMAC1 : GRCBASE_EMAC0;
3138         struct bnx2x *bp = params->bp;
3139         DP(NETIF_MSG_LINK, "bnx2x_set_led: port %x, mode %d\n", port, mode);
3140         DP(NETIF_MSG_LINK, "speed 0x%x, hw_led_mode 0x%x\n",
3141                  speed, hw_led_mode);
3142         /* In case */
3143         for (phy_idx = EXT_PHY1; phy_idx < MAX_PHYS; phy_idx++) {
3144                 if (params->phy[phy_idx].set_link_led) {
3145                         params->phy[phy_idx].set_link_led(
3146                                 &params->phy[phy_idx], params, mode);
3147                 }
3148         }
3149
3150         switch (mode) {
3151         case LED_MODE_FRONT_PANEL_OFF:
3152         case LED_MODE_OFF:
3153                 REG_WR(bp, NIG_REG_LED_10G_P0 + port*4, 0);
3154                 REG_WR(bp, NIG_REG_LED_MODE_P0 + port*4,
3155                            SHARED_HW_CFG_LED_MAC1);
3156
3157                 tmp = EMAC_RD(bp, EMAC_REG_EMAC_LED);
3158                 EMAC_WR(bp, EMAC_REG_EMAC_LED, (tmp | EMAC_LED_OVERRIDE));
3159                 break;
3160
3161         case LED_MODE_OPER:
3162                 /**
3163                  * For all other phys, OPER mode is same as ON, so in case
3164                  * link is down, do nothing
3165                  **/
3166                 if (!vars->link_up)
3167                         break;
3168         case LED_MODE_ON:
3169                 if (SINGLE_MEDIA_DIRECT(params)) {
3170                         /**
3171                         * This is a work-around for HW issue found when link
3172                         * is up in CL73
3173                         */
3174                         REG_WR(bp, NIG_REG_LED_MODE_P0 + port*4, 0);
3175                         REG_WR(bp, NIG_REG_LED_10G_P0 + port*4, 1);
3176                 } else {
3177                         REG_WR(bp, NIG_REG_LED_MODE_P0 + port*4,
3178                                    hw_led_mode);
3179                 }
3180
3181                 REG_WR(bp, NIG_REG_LED_CONTROL_OVERRIDE_TRAFFIC_P0 +
3182                            port*4, 0);
3183                 /* Set blinking rate to ~15.9Hz */
3184                 REG_WR(bp, NIG_REG_LED_CONTROL_BLINK_RATE_P0 + port*4,
3185                            LED_BLINK_RATE_VAL);
3186                 REG_WR(bp, NIG_REG_LED_CONTROL_BLINK_RATE_ENA_P0 +
3187                            port*4, 1);
3188                 tmp = EMAC_RD(bp, EMAC_REG_EMAC_LED);
3189                 EMAC_WR(bp, EMAC_REG_EMAC_LED,
3190                             (tmp & (~EMAC_LED_OVERRIDE)));
3191
3192                 if (CHIP_IS_E1(bp) &&
3193                     ((speed == SPEED_2500) ||
3194                      (speed == SPEED_1000) ||
3195                      (speed == SPEED_100) ||
3196                      (speed == SPEED_10))) {
3197                         /* On Everest 1 Ax chip versions for speeds less than
3198                         10G LED scheme is different */
3199                         REG_WR(bp, NIG_REG_LED_CONTROL_OVERRIDE_TRAFFIC_P0
3200                                    + port*4, 1);
3201                         REG_WR(bp, NIG_REG_LED_CONTROL_TRAFFIC_P0 +
3202                                    port*4, 0);
3203                         REG_WR(bp, NIG_REG_LED_CONTROL_BLINK_TRAFFIC_P0 +
3204                                    port*4, 1);
3205                 }
3206                 break;
3207
3208         default:
3209                 rc = -EINVAL;
3210                 DP(NETIF_MSG_LINK, "bnx2x_set_led: Invalid led mode %d\n",
3211                          mode);
3212                 break;
3213         }
3214         return rc;
3215
3216 }
3217
3218 /**
3219  * This function comes to reflect the actual link state read DIRECTLY from the
3220  * HW
3221  */
3222 u8 bnx2x_test_link(struct link_params *params, struct link_vars *vars,
3223                    u8 is_serdes)
3224 {
3225         struct bnx2x *bp = params->bp;
3226         u16 gp_status = 0, phy_index = 0;
3227         u8 ext_phy_link_up = 0, serdes_phy_type;
3228         struct link_vars temp_vars;
3229
3230         CL45_RD_OVER_CL22(bp, &params->phy[INT_PHY],
3231                               MDIO_REG_BANK_GP_STATUS,
3232                               MDIO_GP_STATUS_TOP_AN_STATUS1,
3233                               &gp_status);
3234         /* link is up only if both local phy and external phy are up */
3235         if (!(gp_status & MDIO_GP_STATUS_TOP_AN_STATUS1_LINK_STATUS))
3236                 return -ESRCH;
3237
3238         switch (params->num_phys) {
3239         case 1:
3240                 /* No external PHY */
3241                 return 0;
3242         case 2:
3243                 ext_phy_link_up = params->phy[EXT_PHY1].read_status(
3244                         &params->phy[EXT_PHY1],
3245                         params, &temp_vars);
3246                 break;
3247         case 3: /* Dual Media */
3248                 for (phy_index = EXT_PHY1; phy_index < params->num_phys;
3249                       phy_index++) {
3250                         serdes_phy_type = ((params->phy[phy_index].media_type ==
3251                                             ETH_PHY_SFP_FIBER) ||
3252                                            (params->phy[phy_index].media_type ==
3253                                             ETH_PHY_XFP_FIBER));
3254
3255                         if (is_serdes != serdes_phy_type)
3256                                 continue;
3257                         if (params->phy[phy_index].read_status) {
3258                                 ext_phy_link_up |=
3259                                         params->phy[phy_index].read_status(
3260                                                 &params->phy[phy_index],
3261                                                 params, &temp_vars);
3262                         }
3263                 }
3264                 break;
3265         }
3266         if (ext_phy_link_up)
3267                 return 0;
3268         return -ESRCH;
3269 }
3270
3271 static u8 bnx2x_link_initialize(struct link_params *params,
3272                                 struct link_vars *vars)
3273 {
3274         u8 rc = 0;
3275         u8 phy_index, non_ext_phy;
3276         struct bnx2x *bp = params->bp;
3277         /**
3278         * In case of external phy existence, the line speed would be the
3279         * line speed linked up by the external phy. In case it is direct
3280         * only, then the line_speed during initialization will be
3281         * equal to the req_line_speed
3282         */
3283         vars->line_speed = params->phy[INT_PHY].req_line_speed;
3284
3285         /**
3286          * Initialize the internal phy in case this is a direct board
3287          * (no external phys), or this board has external phy which requires
3288          * to first.
3289          */
3290
3291         if (params->phy[INT_PHY].config_init)
3292                 params->phy[INT_PHY].config_init(
3293                         &params->phy[INT_PHY],
3294                         params, vars);
3295
3296         /* init ext phy and enable link state int */
3297         non_ext_phy = (SINGLE_MEDIA_DIRECT(params) ||
3298                        (params->loopback_mode == LOOPBACK_XGXS));
3299
3300         if (non_ext_phy ||
3301             (params->phy[EXT_PHY1].flags & FLAGS_INIT_XGXS_FIRST) ||
3302             (params->loopback_mode == LOOPBACK_EXT_PHY)) {
3303                 struct bnx2x_phy *phy = &params->phy[INT_PHY];
3304                 if (vars->line_speed == SPEED_AUTO_NEG)
3305                         bnx2x_set_parallel_detection(phy, params);
3306                 bnx2x_init_internal_phy(phy, params, vars);
3307         }
3308
3309         /* Init external phy*/
3310         if (!non_ext_phy)
3311                 for (phy_index = EXT_PHY1; phy_index < params->num_phys;
3312                       phy_index++) {
3313                         /**
3314                          * No need to initialize second phy in case of first
3315                          * phy only selection. In case of second phy, we do
3316                          * need to initialize the first phy, since they are
3317                          * connected.
3318                          **/
3319                         if (phy_index == EXT_PHY2 &&
3320                             (bnx2x_phy_selection(params) ==
3321                              PORT_HW_CFG_PHY_SELECTION_FIRST_PHY)) {
3322                                 DP(NETIF_MSG_LINK, "Not initializing"
3323                                                    "second phy\n");
3324                                 continue;
3325                         }
3326                         params->phy[phy_index].config_init(
3327                                 &params->phy[phy_index],
3328                                 params, vars);
3329                 }
3330
3331         /* Reset the interrupt indication after phy was initialized */
3332         bnx2x_bits_dis(bp, NIG_REG_STATUS_INTERRUPT_PORT0 +
3333                        params->port*4,
3334                        (NIG_STATUS_XGXS0_LINK10G |
3335                         NIG_STATUS_XGXS0_LINK_STATUS |
3336                         NIG_STATUS_SERDES0_LINK_STATUS |
3337                         NIG_MASK_MI_INT));
3338         return rc;
3339 }
3340
3341 static void bnx2x_int_link_reset(struct bnx2x_phy *phy,
3342                                  struct link_params *params)
3343 {
3344         /* reset the SerDes/XGXS */
3345         REG_WR(params->bp, GRCBASE_MISC +
3346                      MISC_REGISTERS_RESET_REG_3_CLEAR,
3347                      (0x1ff << (params->port*16)));
3348 }
3349
3350 static void bnx2x_common_ext_link_reset(struct bnx2x_phy *phy,
3351                                         struct link_params *params)
3352 {
3353         struct bnx2x *bp = params->bp;
3354         u8 gpio_port;
3355         /* HW reset */
3356         if (CHIP_IS_E2(bp))
3357                 gpio_port = BP_PATH(bp);
3358         else
3359                 gpio_port = params->port;
3360         bnx2x_set_gpio(bp, MISC_REGISTERS_GPIO_1,
3361                             MISC_REGISTERS_GPIO_OUTPUT_LOW,
3362                             gpio_port);
3363         bnx2x_set_gpio(bp, MISC_REGISTERS_GPIO_2,
3364                             MISC_REGISTERS_GPIO_OUTPUT_LOW,
3365                             gpio_port);
3366         DP(NETIF_MSG_LINK, "reset external PHY\n");
3367 }
3368
3369 static u8 bnx2x_update_link_down(struct link_params *params,
3370                                struct link_vars *vars)
3371 {
3372         struct bnx2x *bp = params->bp;
3373         u8 port = params->port;
3374
3375         DP(NETIF_MSG_LINK, "Port %x: Link is down\n", port);
3376         bnx2x_set_led(params, vars, LED_MODE_OFF, 0);
3377
3378         /* indicate no mac active */
3379         vars->mac_type = MAC_TYPE_NONE;
3380
3381         /* update shared memory */
3382         vars->link_status = 0;
3383         vars->line_speed = 0;
3384         bnx2x_update_mng(params, vars->link_status);
3385
3386         /* activate nig drain */
3387         REG_WR(bp, NIG_REG_EGRESS_DRAIN0_MODE + port*4, 1);
3388
3389         /* disable emac */
3390         REG_WR(bp, NIG_REG_NIG_EMAC0_EN + port*4, 0);
3391
3392         msleep(10);
3393
3394         /* reset BigMac */
3395         bnx2x_bmac_rx_disable(bp, params->port);
3396         REG_WR(bp, GRCBASE_MISC +
3397                    MISC_REGISTERS_RESET_REG_2_CLEAR,
3398                    (MISC_REGISTERS_RESET_REG_2_RST_BMAC0 << port));
3399         return 0;
3400 }
3401
3402 static u8 bnx2x_update_link_up(struct link_params *params,
3403                              struct link_vars *vars,
3404                              u8 link_10g)
3405 {
3406         struct bnx2x *bp = params->bp;
3407         u8 port = params->port;
3408         u8 rc = 0;
3409
3410         vars->link_status |= LINK_STATUS_LINK_UP;
3411
3412         if (vars->flow_ctrl & BNX2X_FLOW_CTRL_TX)
3413                 vars->link_status |=
3414                         LINK_STATUS_TX_FLOW_CONTROL_ENABLED;
3415
3416         if (vars->flow_ctrl & BNX2X_FLOW_CTRL_RX)
3417                 vars->link_status |=
3418                         LINK_STATUS_RX_FLOW_CONTROL_ENABLED;
3419
3420         if (link_10g) {
3421                 bnx2x_bmac_enable(params, vars, 0);
3422                 bnx2x_set_led(params, vars,
3423                               LED_MODE_OPER, SPEED_10000);
3424         } else {
3425                 rc = bnx2x_emac_program(params, vars);
3426
3427                 bnx2x_emac_enable(params, vars, 0);
3428
3429                 /* AN complete? */
3430                 if ((vars->link_status & LINK_STATUS_AUTO_NEGOTIATE_COMPLETE)
3431                     && (!(vars->phy_flags & PHY_SGMII_FLAG)) &&
3432                     SINGLE_MEDIA_DIRECT(params))
3433                         bnx2x_set_gmii_tx_driver(params);
3434         }
3435
3436         /* PBF - link up */
3437         if (!(CHIP_IS_E2(bp)))
3438                 rc |= bnx2x_pbf_update(params, vars->flow_ctrl,
3439                                        vars->line_speed);
3440
3441         /* disable drain */
3442         REG_WR(bp, NIG_REG_EGRESS_DRAIN0_MODE + port*4, 0);
3443
3444         /* update shared memory */
3445         bnx2x_update_mng(params, vars->link_status);
3446         msleep(20);
3447         return rc;
3448 }
3449 /**
3450  * The bnx2x_link_update function should be called upon link
3451  * interrupt.
3452  * Link is considered up as follows:
3453  * - DIRECT_SINGLE_MEDIA - Only XGXS link (internal link) needs
3454  *   to be up
3455  * - SINGLE_MEDIA - The link between the 577xx and the external
3456  *   phy (XGXS) need to up as well as the external link of the
3457  *   phy (PHY_EXT1)
3458  * - DUAL_MEDIA - The link between the 577xx and the first
3459  *   external phy needs to be up, and at least one of the 2
3460  *   external phy link must be up.
3461  */
3462 u8 bnx2x_link_update(struct link_params *params, struct link_vars *vars)
3463 {
3464         struct bnx2x *bp = params->bp;
3465         struct link_vars phy_vars[MAX_PHYS];
3466         u8 port = params->port;
3467         u8 link_10g, phy_index;
3468         u8 ext_phy_link_up = 0, cur_link_up, rc = 0;
3469         u8 is_mi_int = 0;
3470         u16 ext_phy_line_speed = 0, prev_line_speed = vars->line_speed;
3471         u8 active_external_phy = INT_PHY;
3472         vars->link_status = 0;
3473         for (phy_index = INT_PHY; phy_index < params->num_phys;
3474               phy_index++) {
3475                 phy_vars[phy_index].flow_ctrl = 0;
3476                 phy_vars[phy_index].link_status = 0;
3477                 phy_vars[phy_index].line_speed = 0;
3478                 phy_vars[phy_index].duplex = DUPLEX_FULL;
3479                 phy_vars[phy_index].phy_link_up = 0;
3480                 phy_vars[phy_index].link_up = 0;
3481         }
3482
3483         DP(NETIF_MSG_LINK, "port %x, XGXS?%x, int_status 0x%x\n",
3484                  port, (vars->phy_flags & PHY_XGXS_FLAG),
3485                  REG_RD(bp, NIG_REG_STATUS_INTERRUPT_PORT0 + port*4));
3486
3487         is_mi_int = (u8)(REG_RD(bp, NIG_REG_EMAC0_STATUS_MISC_MI_INT +
3488                                     port*0x18) > 0);
3489         DP(NETIF_MSG_LINK, "int_mask 0x%x MI_INT %x, SERDES_LINK %x\n",
3490                  REG_RD(bp, NIG_REG_MASK_INTERRUPT_PORT0 + port*4),
3491                  is_mi_int,
3492                  REG_RD(bp,
3493                             NIG_REG_SERDES0_STATUS_LINK_STATUS + port*0x3c));
3494
3495         DP(NETIF_MSG_LINK, " 10G %x, XGXS_LINK %x\n",
3496           REG_RD(bp, NIG_REG_XGXS0_STATUS_LINK10G + port*0x68),
3497           REG_RD(bp, NIG_REG_XGXS0_STATUS_LINK_STATUS + port*0x68));
3498
3499         /* disable emac */
3500         REG_WR(bp, NIG_REG_NIG_EMAC0_EN + port*4, 0);
3501
3502         /**
3503         * Step 1:
3504         * Check external link change only for external phys, and apply
3505         * priority selection between them in case the link on both phys
3506         * is up. Note that the instead of the common vars, a temporary
3507         * vars argument is used since each phy may have different link/
3508         * speed/duplex result
3509         */
3510         for (phy_index = EXT_PHY1; phy_index < params->num_phys;
3511               phy_index++) {
3512                 struct bnx2x_phy *phy = &params->phy[phy_index];
3513                 if (!phy->read_status)
3514                         continue;
3515                 /* Read link status and params of this ext phy */
3516                 cur_link_up = phy->read_status(phy, params,
3517                                                &phy_vars[phy_index]);
3518                 if (cur_link_up) {
3519                         DP(NETIF_MSG_LINK, "phy in index %d link is up\n",
3520                                    phy_index);
3521                 } else {
3522                         DP(NETIF_MSG_LINK, "phy in index %d link is down\n",
3523                                    phy_index);
3524                         continue;
3525                 }
3526
3527                 if (!ext_phy_link_up) {
3528                         ext_phy_link_up = 1;
3529                         active_external_phy = phy_index;
3530                 } else {
3531                         switch (bnx2x_phy_selection(params)) {
3532                         case PORT_HW_CFG_PHY_SELECTION_HARDWARE_DEFAULT:
3533                         case PORT_HW_CFG_PHY_SELECTION_FIRST_PHY_PRIORITY:
3534                         /**
3535                          * In this option, the first PHY makes sure to pass the
3536                          * traffic through itself only.
3537                          * Its not clear how to reset the link on the second phy
3538                          **/
3539                                 active_external_phy = EXT_PHY1;
3540                                 break;
3541                         case PORT_HW_CFG_PHY_SELECTION_SECOND_PHY_PRIORITY:
3542                         /**
3543                          * In this option, the first PHY makes sure to pass the
3544                          * traffic through the second PHY.
3545                          **/
3546                                 active_external_phy = EXT_PHY2;
3547                                 break;
3548                         default:
3549                         /**
3550                          * Link indication on both PHYs with the following cases
3551                          * is invalid:
3552                          * - FIRST_PHY means that second phy wasn't initialized,
3553                          * hence its link is expected to be down
3554                          * - SECOND_PHY means that first phy should not be able
3555                          * to link up by itself (using configuration)
3556                          * - DEFAULT should be overriden during initialiazation
3557                          **/
3558                                 DP(NETIF_MSG_LINK, "Invalid link indication"
3559                                            "mpc=0x%x. DISABLING LINK !!!\n",
3560                                            params->multi_phy_config);
3561                                 ext_phy_link_up = 0;
3562                                 break;
3563                         }
3564                 }
3565         }
3566         prev_line_speed = vars->line_speed;
3567         /**
3568         * Step 2:
3569         * Read the status of the internal phy. In case of
3570         * DIRECT_SINGLE_MEDIA board, this link is the external link,
3571         * otherwise this is the link between the 577xx and the first
3572         * external phy
3573         */
3574         if (params->phy[INT_PHY].read_status)
3575                 params->phy[INT_PHY].read_status(
3576                         &params->phy[INT_PHY],
3577                         params, vars);
3578         /**
3579          * The INT_PHY flow control reside in the vars. This include the
3580          * case where the speed or flow control are not set to AUTO.
3581          * Otherwise, the active external phy flow control result is set
3582          * to the vars. The ext_phy_line_speed is needed to check if the
3583          * speed is different between the internal phy and external phy.
3584          * This case may be result of intermediate link speed change.
3585          */
3586         if (active_external_phy > INT_PHY) {
3587                 vars->flow_ctrl = phy_vars[active_external_phy].flow_ctrl;
3588                 /**
3589                  * Link speed is taken from the XGXS. AN and FC result from
3590                  * the external phy.
3591                  */
3592                 vars->link_status |= phy_vars[active_external_phy].link_status;
3593
3594                 /**
3595                  * if active_external_phy is first PHY and link is up - disable
3596                  * disable TX on second external PHY
3597                  */
3598                 if (active_external_phy == EXT_PHY1) {
3599                         if (params->phy[EXT_PHY2].phy_specific_func) {
3600                                 DP(NETIF_MSG_LINK, "Disabling TX on"
3601                                                    " EXT_PHY2\n");
3602                                 params->phy[EXT_PHY2].phy_specific_func(
3603                                         &params->phy[EXT_PHY2],
3604                                         params, DISABLE_TX);
3605                         }
3606                 }
3607
3608                 ext_phy_line_speed = phy_vars[active_external_phy].line_speed;
3609                 vars->duplex = phy_vars[active_external_phy].duplex;
3610                 if (params->phy[active_external_phy].supported &
3611                     SUPPORTED_FIBRE)
3612                         vars->link_status |= LINK_STATUS_SERDES_LINK;
3613                 DP(NETIF_MSG_LINK, "Active external phy selected: %x\n",
3614                            active_external_phy);
3615         }
3616
3617         for (phy_index = EXT_PHY1; phy_index < params->num_phys;
3618               phy_index++) {
3619                 if (params->phy[phy_index].flags &
3620                     FLAGS_REARM_LATCH_SIGNAL) {
3621                         bnx2x_rearm_latch_signal(bp, port,
3622                                                  phy_index ==
3623                                                  active_external_phy);
3624                         break;
3625                 }
3626         }
3627         DP(NETIF_MSG_LINK, "vars->flow_ctrl = 0x%x, vars->link_status = 0x%x,"
3628                    " ext_phy_line_speed = %d\n", vars->flow_ctrl,
3629                    vars->link_status, ext_phy_line_speed);
3630         /**
3631          * Upon link speed change set the NIG into drain mode. Comes to
3632          * deals with possible FIFO glitch due to clk change when speed
3633          * is decreased without link down indicator
3634          */
3635
3636         if (vars->phy_link_up) {
3637                 if (!(SINGLE_MEDIA_DIRECT(params)) && ext_phy_link_up &&
3638                     (ext_phy_line_speed != vars->line_speed)) {
3639                         DP(NETIF_MSG_LINK, "Internal link speed %d is"
3640                                    " different than the external"
3641                                    " link speed %d\n", vars->line_speed,
3642                                    ext_phy_line_speed);
3643                         vars->phy_link_up = 0;
3644                 } else if (prev_line_speed != vars->line_speed) {
3645                         REG_WR(bp, NIG_REG_EGRESS_DRAIN0_MODE
3646                                      + params->port*4, 0);
3647                         msleep(1);
3648                 }
3649         }
3650
3651         /* anything 10 and over uses the bmac */
3652         link_10g = ((vars->line_speed == SPEED_10000) ||
3653                     (vars->line_speed == SPEED_12000) ||
3654                     (vars->line_speed == SPEED_12500) ||
3655                     (vars->line_speed == SPEED_13000) ||
3656                     (vars->line_speed == SPEED_15000) ||
3657                     (vars->line_speed == SPEED_16000));
3658
3659         bnx2x_link_int_ack(params, vars, link_10g);
3660
3661         /**
3662         * In case external phy link is up, and internal link is down
3663         * (not initialized yet probably after link initialization, it
3664         * needs to be initialized.
3665         * Note that after link down-up as result of cable plug, the xgxs
3666         * link would probably become up again without the need
3667         * initialize it
3668         */
3669         if (!(SINGLE_MEDIA_DIRECT(params))) {
3670                 DP(NETIF_MSG_LINK, "ext_phy_link_up = %d, int_link_up = %d,"
3671                            " init_preceding = %d\n", ext_phy_link_up,
3672                            vars->phy_link_up,
3673                            params->phy[EXT_PHY1].flags &
3674                            FLAGS_INIT_XGXS_FIRST);
3675                 if (!(params->phy[EXT_PHY1].flags &
3676                       FLAGS_INIT_XGXS_FIRST)
3677                     && ext_phy_link_up && !vars->phy_link_up) {
3678                         vars->line_speed = ext_phy_line_speed;
3679                         if (vars->line_speed < SPEED_1000)
3680                                 vars->phy_flags |= PHY_SGMII_FLAG;
3681                         else
3682                                 vars->phy_flags &= ~PHY_SGMII_FLAG;
3683                         bnx2x_init_internal_phy(&params->phy[INT_PHY],
3684                                                 params,
3685                                                 vars);
3686                 }
3687         }
3688         /**
3689          *  Link is up only if both local phy and external phy (in case of
3690          *  non-direct board) are up
3691          */
3692         vars->link_up = (vars->phy_link_up &&
3693                          (ext_phy_link_up ||
3694                           SINGLE_MEDIA_DIRECT(params)));
3695
3696         if (vars->link_up)
3697                 rc = bnx2x_update_link_up(params, vars, link_10g);
3698         else
3699                 rc = bnx2x_update_link_down(params, vars);
3700
3701         return rc;
3702 }
3703
3704
3705 /*****************************************************************************/
3706 /*                          External Phy section                             */
3707 /*****************************************************************************/
3708 void bnx2x_ext_phy_hw_reset(struct bnx2x *bp, u8 port)
3709 {
3710         bnx2x_set_gpio(bp, MISC_REGISTERS_GPIO_1,
3711                             MISC_REGISTERS_GPIO_OUTPUT_LOW, port);
3712         msleep(1);
3713         bnx2x_set_gpio(bp, MISC_REGISTERS_GPIO_1,
3714                             MISC_REGISTERS_GPIO_OUTPUT_HIGH, port);
3715 }
3716
3717 static void bnx2x_save_spirom_version(struct bnx2x *bp, u8 port,
3718                                       u32 spirom_ver, u32 ver_addr)
3719 {
3720         DP(NETIF_MSG_LINK, "FW version 0x%x:0x%x for port %d\n",
3721                  (u16)(spirom_ver>>16), (u16)spirom_ver, port);
3722
3723         if (ver_addr)
3724                 REG_WR(bp, ver_addr, spirom_ver);
3725 }
3726
3727 static void bnx2x_save_bcm_spirom_ver(struct bnx2x *bp,
3728                                       struct bnx2x_phy *phy,
3729                                       u8 port)
3730 {
3731         u16 fw_ver1, fw_ver2;
3732
3733         bnx2x_cl45_read(bp, phy, MDIO_PMA_DEVAD,
3734                       MDIO_PMA_REG_ROM_VER1, &fw_ver1);
3735         bnx2x_cl45_read(bp, phy, MDIO_PMA_DEVAD,
3736                       MDIO_PMA_REG_ROM_VER2, &fw_ver2);
3737         bnx2x_save_spirom_version(bp, port, (u32)(fw_ver1<<16 | fw_ver2),
3738                                   phy->ver_addr);
3739 }
3740
3741 static void bnx2x_ext_phy_set_pause(struct link_params *params,
3742                                     struct bnx2x_phy *phy,
3743                                     struct link_vars *vars)
3744 {
3745         u16 val;
3746         struct bnx2x *bp = params->bp;
3747         /* read modify write pause advertizing */
3748         bnx2x_cl45_read(bp, phy, MDIO_AN_DEVAD, MDIO_AN_REG_ADV_PAUSE, &val);
3749
3750         val &= ~MDIO_AN_REG_ADV_PAUSE_BOTH;
3751
3752         /* Please refer to Table 28B-3 of 802.3ab-1999 spec. */
3753         bnx2x_calc_ieee_aneg_adv(phy, params, &vars->ieee_fc);
3754         if ((vars->ieee_fc &
3755             MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_ASYMMETRIC) ==
3756             MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_ASYMMETRIC) {
3757                 val |=  MDIO_AN_REG_ADV_PAUSE_ASYMMETRIC;
3758         }
3759         if ((vars->ieee_fc &
3760             MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_BOTH) ==
3761             MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_BOTH) {
3762                 val |= MDIO_AN_REG_ADV_PAUSE_PAUSE;
3763         }
3764         DP(NETIF_MSG_LINK, "Ext phy AN advertize 0x%x\n", val);
3765         bnx2x_cl45_write(bp, phy, MDIO_AN_DEVAD, MDIO_AN_REG_ADV_PAUSE, val);
3766 }
3767
3768 static u8 bnx2x_ext_phy_resolve_fc(struct bnx2x_phy *phy,
3769                                    struct link_params *params,
3770                                    struct link_vars *vars)
3771 {
3772         struct bnx2x *bp = params->bp;
3773         u16 ld_pause;           /* local */
3774         u16 lp_pause;           /* link partner */
3775         u16 pause_result;
3776         u8 ret = 0;
3777         /* read twice */
3778
3779         vars->flow_ctrl = BNX2X_FLOW_CTRL_NONE;
3780
3781         if (phy->req_flow_ctrl != BNX2X_FLOW_CTRL_AUTO)
3782                 vars->flow_ctrl = phy->req_flow_ctrl;
3783         else if (phy->req_line_speed != SPEED_AUTO_NEG)
3784                 vars->flow_ctrl = params->req_fc_auto_adv;
3785         else if (vars->link_status & LINK_STATUS_AUTO_NEGOTIATE_COMPLETE) {
3786                 ret = 1;
3787                 bnx2x_cl45_read(bp, phy,
3788                               MDIO_AN_DEVAD,
3789                               MDIO_AN_REG_ADV_PAUSE, &ld_pause);
3790                 bnx2x_cl45_read(bp, phy,
3791                               MDIO_AN_DEVAD,
3792                               MDIO_AN_REG_LP_AUTO_NEG, &lp_pause);
3793                 pause_result = (ld_pause &
3794                                 MDIO_AN_REG_ADV_PAUSE_MASK) >> 8;
3795                 pause_result |= (lp_pause &
3796                                  MDIO_AN_REG_ADV_PAUSE_MASK) >> 10;
3797                 DP(NETIF_MSG_LINK, "Ext PHY pause result 0x%x\n",
3798                    pause_result);
3799                 bnx2x_pause_resolve(vars, pause_result);
3800         }
3801         return ret;
3802 }
3803
3804 static void bnx2x_ext_phy_10G_an_resolve(struct bnx2x *bp,
3805                                        struct bnx2x_phy *phy,
3806                                        struct link_vars *vars)
3807 {
3808         u16 val;
3809         bnx2x_cl45_read(bp, phy,
3810                         MDIO_AN_DEVAD,
3811                         MDIO_AN_REG_STATUS, &val);
3812         bnx2x_cl45_read(bp, phy,
3813                         MDIO_AN_DEVAD,
3814                         MDIO_AN_REG_STATUS, &val);
3815         if (val & (1<<5))
3816                 vars->link_status |= LINK_STATUS_AUTO_NEGOTIATE_COMPLETE;
3817         if ((val & (1<<0)) == 0)
3818                 vars->link_status |= LINK_STATUS_PARALLEL_DETECTION_USED;
3819 }
3820
3821 /******************************************************************/
3822 /*              common BCM8073/BCM8727 PHY SECTION                */
3823 /******************************************************************/
3824 static void bnx2x_8073_resolve_fc(struct bnx2x_phy *phy,
3825                                   struct link_params *params,
3826                                   struct link_vars *vars)
3827 {
3828         struct bnx2x *bp = params->bp;
3829         if (phy->req_line_speed == SPEED_10 ||
3830             phy->req_line_speed == SPEED_100) {
3831                 vars->flow_ctrl = phy->req_flow_ctrl;
3832                 return;
3833         }
3834
3835         if (bnx2x_ext_phy_resolve_fc(phy, params, vars) &&
3836             (vars->flow_ctrl == BNX2X_FLOW_CTRL_NONE)) {
3837                 u16 pause_result;
3838                 u16 ld_pause;           /* local */
3839                 u16 lp_pause;           /* link partner */
3840                 bnx2x_cl45_read(bp, phy,
3841                                 MDIO_AN_DEVAD,
3842                                 MDIO_AN_REG_CL37_FC_LD, &ld_pause);
3843
3844                 bnx2x_cl45_read(bp, phy,
3845                                 MDIO_AN_DEVAD,
3846                                 MDIO_AN_REG_CL37_FC_LP, &lp_pause);
3847                 pause_result = (ld_pause &
3848                                 MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_BOTH) >> 5;
3849                 pause_result |= (lp_pause &
3850                                  MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_BOTH) >> 7;
3851
3852                 bnx2x_pause_resolve(vars, pause_result);
3853                 DP(NETIF_MSG_LINK, "Ext PHY CL37 pause result 0x%x\n",
3854                            pause_result);
3855         }
3856 }
3857
3858 static void bnx2x_8073_8727_external_rom_boot(struct bnx2x *bp,
3859                                               struct bnx2x_phy *phy,
3860                                               u8 port)
3861 {
3862         /* Boot port from external ROM  */
3863         /* EDC grst */
3864         bnx2x_cl45_write(bp, phy,
3865                        MDIO_PMA_DEVAD,
3866                        MDIO_PMA_REG_GEN_CTRL,
3867                        0x0001);
3868
3869         /* ucode reboot and rst */
3870         bnx2x_cl45_write(bp, phy,
3871                        MDIO_PMA_DEVAD,
3872                        MDIO_PMA_REG_GEN_CTRL,
3873                        0x008c);
3874
3875         bnx2x_cl45_write(bp, phy,
3876                        MDIO_PMA_DEVAD,
3877                        MDIO_PMA_REG_MISC_CTRL1, 0x0001);
3878
3879         /* Reset internal microprocessor */
3880         bnx2x_cl45_write(bp, phy,
3881                        MDIO_PMA_DEVAD,
3882                        MDIO_PMA_REG_GEN_CTRL,
3883                        MDIO_PMA_REG_GEN_CTRL_ROM_MICRO_RESET);
3884
3885         /* Release srst bit */
3886         bnx2x_cl45_write(bp, phy,
3887                        MDIO_PMA_DEVAD,
3888                        MDIO_PMA_REG_GEN_CTRL,
3889                        MDIO_PMA_REG_GEN_CTRL_ROM_RESET_INTERNAL_MP);
3890
3891         /* wait for 120ms for code download via SPI port */
3892         msleep(120);
3893
3894         /* Clear ser_boot_ctl bit */
3895         bnx2x_cl45_write(bp, phy,
3896                        MDIO_PMA_DEVAD,
3897                        MDIO_PMA_REG_MISC_CTRL1, 0x0000);
3898         bnx2x_save_bcm_spirom_ver(bp, phy, port);
3899 }
3900
3901 static void bnx2x_8073_set_xaui_low_power_mode(struct bnx2x *bp,
3902                                                struct bnx2x_phy *phy)
3903 {
3904         u16 val;
3905         bnx2x_cl45_read(bp, phy,
3906                         MDIO_PMA_DEVAD, MDIO_PMA_REG_8073_CHIP_REV, &val);
3907
3908         if (val == 0) {
3909                 /* Mustn't set low power mode in 8073 A0 */
3910                 return;
3911         }
3912
3913         /* Disable PLL sequencer (use read-modify-write to clear bit 13) */
3914         bnx2x_cl45_read(bp, phy,
3915                         MDIO_XS_DEVAD, MDIO_XS_PLL_SEQUENCER, &val);
3916         val &= ~(1<<13);
3917         bnx2x_cl45_write(bp, phy,
3918                        MDIO_XS_DEVAD, MDIO_XS_PLL_SEQUENCER, val);
3919
3920         /* PLL controls */
3921         bnx2x_cl45_write(bp, phy, MDIO_XS_DEVAD, 0x805E, 0x1077);
3922         bnx2x_cl45_write(bp, phy, MDIO_XS_DEVAD, 0x805D, 0x0000);
3923         bnx2x_cl45_write(bp, phy, MDIO_XS_DEVAD, 0x805C, 0x030B);
3924         bnx2x_cl45_write(bp, phy, MDIO_XS_DEVAD, 0x805B, 0x1240);
3925         bnx2x_cl45_write(bp, phy, MDIO_XS_DEVAD, 0x805A, 0x2490);
3926
3927         /* Tx Controls */
3928         bnx2x_cl45_write(bp, phy, MDIO_XS_DEVAD, 0x80A7, 0x0C74);
3929         bnx2x_cl45_write(bp, phy, MDIO_XS_DEVAD, 0x80A6, 0x9041);
3930         bnx2x_cl45_write(bp, phy, MDIO_XS_DEVAD, 0x80A5, 0x4640);
3931
3932         /* Rx Controls */
3933         bnx2x_cl45_write(bp, phy, MDIO_XS_DEVAD, 0x80FE, 0x01C4);
3934         bnx2x_cl45_write(bp, phy, MDIO_XS_DEVAD, 0x80FD, 0x9249);
3935         bnx2x_cl45_write(bp, phy, MDIO_XS_DEVAD, 0x80FC, 0x2015);
3936
3937         /* Enable PLL sequencer  (use read-modify-write to set bit 13) */
3938         bnx2x_cl45_read(bp, phy, MDIO_XS_DEVAD, MDIO_XS_PLL_SEQUENCER, &val);
3939         val |= (1<<13);
3940         bnx2x_cl45_write(bp, phy, MDIO_XS_DEVAD, MDIO_XS_PLL_SEQUENCER, val);
3941 }
3942
3943 /******************************************************************/
3944 /*                      BCM8073 PHY SECTION                       */
3945 /******************************************************************/
3946 static u8 bnx2x_8073_is_snr_needed(struct bnx2x *bp, struct bnx2x_phy *phy)
3947 {
3948         /* This is only required for 8073A1, version 102 only */
3949         u16 val;
3950
3951         /* Read 8073 HW revision*/
3952         bnx2x_cl45_read(bp, phy,
3953                       MDIO_PMA_DEVAD,
3954                       MDIO_PMA_REG_8073_CHIP_REV, &val);
3955
3956         if (val != 1) {
3957                 /* No need to workaround in 8073 A1 */
3958                 return 0;
3959         }
3960
3961         bnx2x_cl45_read(bp, phy,
3962                       MDIO_PMA_DEVAD,
3963                       MDIO_PMA_REG_ROM_VER2, &val);
3964
3965         /* SNR should be applied only for version 0x102 */
3966         if (val != 0x102)
3967                 return 0;
3968
3969         return 1;
3970 }
3971
3972 static u8 bnx2x_8073_xaui_wa(struct bnx2x *bp, struct bnx2x_phy *phy)
3973 {
3974         u16 val, cnt, cnt1 ;
3975
3976         bnx2x_cl45_read(bp, phy,
3977                       MDIO_PMA_DEVAD,
3978                       MDIO_PMA_REG_8073_CHIP_REV, &val);
3979
3980         if (val > 0) {
3981                 /* No need to workaround in 8073 A1 */
3982                 return 0;
3983         }
3984         /* XAUI workaround in 8073 A0: */
3985
3986         /* After loading the boot ROM and restarting Autoneg,
3987         poll Dev1, Reg $C820: */
3988
3989         for (cnt = 0; cnt < 1000; cnt++) {
3990                 bnx2x_cl45_read(bp, phy,
3991                               MDIO_PMA_DEVAD,
3992                               MDIO_PMA_REG_8073_SPEED_LINK_STATUS,
3993                               &val);
3994                   /* If bit [14] = 0 or bit [13] = 0, continue on with
3995                    system initialization (XAUI work-around not required,
3996                     as these bits indicate 2.5G or 1G link up). */
3997                 if (!(val & (1<<14)) || !(val & (1<<13))) {
3998                         DP(NETIF_MSG_LINK, "XAUI work-around not required\n");
3999                         return 0;
4000                 } else if (!(val & (1<<15))) {
4001                         DP(NETIF_MSG_LINK, "clc bit 15 went off\n");
4002                          /* If bit 15 is 0, then poll Dev1, Reg $C841 until
4003                           it's MSB (bit 15) goes to 1 (indicating that the
4004                           XAUI workaround has completed),
4005                           then continue on with system initialization.*/
4006                         for (cnt1 = 0; cnt1 < 1000; cnt1++) {
4007                                 bnx2x_cl45_read(bp, phy,
4008                                         MDIO_PMA_DEVAD,
4009                                         MDIO_PMA_REG_8073_XAUI_WA, &val);
4010                                 if (val & (1<<15)) {
4011                                         DP(NETIF_MSG_LINK,
4012                                           "XAUI workaround has completed\n");
4013                                         return 0;
4014                                  }
4015                                  msleep(3);
4016                         }
4017                         break;
4018                 }
4019                 msleep(3);
4020         }
4021         DP(NETIF_MSG_LINK, "Warning: XAUI work-around timeout !!!\n");
4022         return -EINVAL;
4023 }
4024
4025 static void bnx2x_807x_force_10G(struct bnx2x *bp, struct bnx2x_phy *phy)
4026 {
4027         /* Force KR or KX */
4028         bnx2x_cl45_write(bp, phy,
4029                          MDIO_PMA_DEVAD, MDIO_PMA_REG_CTRL, 0x2040);
4030         bnx2x_cl45_write(bp, phy,
4031                          MDIO_PMA_DEVAD, MDIO_PMA_REG_10G_CTRL2, 0x000b);
4032         bnx2x_cl45_write(bp, phy,
4033                          MDIO_PMA_DEVAD, MDIO_PMA_REG_BCM_CTRL, 0x0000);
4034         bnx2x_cl45_write(bp, phy,
4035                          MDIO_AN_DEVAD, MDIO_AN_REG_CTRL, 0x0000);
4036 }
4037
4038 static void bnx2x_8073_set_pause_cl37(struct link_params *params,
4039                                       struct bnx2x_phy *phy,
4040                                       struct link_vars *vars)
4041 {
4042         u16 cl37_val;
4043         struct bnx2x *bp = params->bp;
4044         bnx2x_cl45_read(bp, phy,
4045                         MDIO_AN_DEVAD, MDIO_AN_REG_CL37_FC_LD, &cl37_val);
4046
4047         cl37_val &= ~MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_BOTH;
4048         /* Please refer to Table 28B-3 of 802.3ab-1999 spec. */
4049         bnx2x_calc_ieee_aneg_adv(phy, params, &vars->ieee_fc);
4050         if ((vars->ieee_fc &
4051             MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_SYMMETRIC) ==
4052             MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_SYMMETRIC) {
4053                 cl37_val |=  MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_SYMMETRIC;
4054         }
4055         if ((vars->ieee_fc &
4056             MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_ASYMMETRIC) ==
4057             MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_ASYMMETRIC) {
4058                 cl37_val |=  MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_ASYMMETRIC;
4059         }
4060         if ((vars->ieee_fc &
4061             MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_BOTH) ==
4062             MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_BOTH) {
4063                 cl37_val |= MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_BOTH;
4064         }
4065         DP(NETIF_MSG_LINK,
4066                  "Ext phy AN advertize cl37 0x%x\n", cl37_val);
4067
4068         bnx2x_cl45_write(bp, phy,
4069                          MDIO_AN_DEVAD, MDIO_AN_REG_CL37_FC_LD, cl37_val);
4070         msleep(500);
4071 }
4072
4073 static u8 bnx2x_8073_config_init(struct bnx2x_phy *phy,
4074                                  struct link_params *params,
4075                                  struct link_vars *vars)
4076 {
4077         struct bnx2x *bp = params->bp;
4078         u16 val = 0, tmp1;
4079         u8 gpio_port;
4080         DP(NETIF_MSG_LINK, "Init 8073\n");
4081
4082         if (CHIP_IS_E2(bp))
4083                 gpio_port = BP_PATH(bp);
4084         else
4085                 gpio_port = params->port;
4086         /* Restore normal power mode*/
4087         bnx2x_set_gpio(bp, MISC_REGISTERS_GPIO_2,
4088                             MISC_REGISTERS_GPIO_OUTPUT_HIGH, gpio_port);
4089
4090         bnx2x_set_gpio(bp, MISC_REGISTERS_GPIO_1,
4091                             MISC_REGISTERS_GPIO_OUTPUT_HIGH, gpio_port);
4092
4093         /* enable LASI */
4094         bnx2x_cl45_write(bp, phy,
4095                          MDIO_PMA_DEVAD, MDIO_PMA_REG_RX_ALARM_CTRL, (1<<2));
4096         bnx2x_cl45_write(bp, phy,
4097                          MDIO_PMA_DEVAD, MDIO_PMA_REG_LASI_CTRL,  0x0004);
4098
4099         bnx2x_8073_set_pause_cl37(params, phy, vars);
4100
4101         bnx2x_8073_set_xaui_low_power_mode(bp, phy);
4102
4103         bnx2x_cl45_read(bp, phy,
4104                         MDIO_PMA_DEVAD, MDIO_PMA_REG_M8051_MSGOUT_REG, &tmp1);
4105
4106         bnx2x_cl45_read(bp, phy,
4107                         MDIO_PMA_DEVAD, MDIO_PMA_REG_RX_ALARM, &tmp1);
4108
4109         DP(NETIF_MSG_LINK, "Before rom RX_ALARM(port1): 0x%x\n", tmp1);
4110
4111         /**
4112          * If this is forced speed, set to KR or KX (all other are not
4113          * supported)
4114          */
4115         /* Swap polarity if required - Must be done only in non-1G mode */
4116         if (params->lane_config & PORT_HW_CFG_SWAP_PHY_POLARITY_ENABLED) {
4117                 /* Configure the 8073 to swap _P and _N of the KR lines */
4118                 DP(NETIF_MSG_LINK, "Swapping polarity for the 8073\n");
4119                 /* 10G Rx/Tx and 1G Tx signal polarity swap */
4120                 bnx2x_cl45_read(bp, phy,
4121                                 MDIO_PMA_DEVAD,
4122                                 MDIO_PMA_REG_8073_OPT_DIGITAL_CTRL, &val);
4123                 bnx2x_cl45_write(bp, phy,
4124                                  MDIO_PMA_DEVAD,
4125                                  MDIO_PMA_REG_8073_OPT_DIGITAL_CTRL,
4126                                  (val | (3<<9)));
4127         }
4128
4129
4130         /* Enable CL37 BAM */
4131         if (REG_RD(bp, params->shmem_base +
4132                          offsetof(struct shmem_region, dev_info.
4133                                   port_hw_config[params->port].default_cfg)) &
4134             PORT_HW_CFG_ENABLE_BAM_ON_KR_ENABLED) {
4135
4136                 bnx2x_cl45_read(bp, phy,
4137                                 MDIO_AN_DEVAD,
4138                                 MDIO_AN_REG_8073_BAM, &val);
4139                 bnx2x_cl45_write(bp, phy,
4140                                  MDIO_AN_DEVAD,
4141                                  MDIO_AN_REG_8073_BAM, val | 1);
4142                 DP(NETIF_MSG_LINK, "Enable CL37 BAM on KR\n");
4143         }
4144         if (params->loopback_mode == LOOPBACK_EXT) {
4145                 bnx2x_807x_force_10G(bp, phy);
4146                 DP(NETIF_MSG_LINK, "Forced speed 10G on 807X\n");
4147                 return 0;
4148         } else {
4149                 bnx2x_cl45_write(bp, phy,
4150                                  MDIO_PMA_DEVAD, MDIO_PMA_REG_BCM_CTRL, 0x0002);
4151         }
4152         if (phy->req_line_speed != SPEED_AUTO_NEG) {
4153                 if (phy->req_line_speed == SPEED_10000) {
4154                         val = (1<<7);
4155                 } else if (phy->req_line_speed ==  SPEED_2500) {
4156                         val = (1<<5);
4157                         /* Note that 2.5G works only
4158                         when used with 1G advertisment */
4159                 } else
4160                         val = (1<<5);
4161         } else {
4162                 val = 0;
4163                 if (phy->speed_cap_mask &
4164                         PORT_HW_CFG_SPEED_CAPABILITY_D0_10G)
4165                         val |= (1<<7);
4166
4167                 /* Note that 2.5G works only when
4168                 used with 1G advertisment */
4169                 if (phy->speed_cap_mask &
4170                         (PORT_HW_CFG_SPEED_CAPABILITY_D0_1G |
4171                          PORT_HW_CFG_SPEED_CAPABILITY_D0_2_5G))
4172                         val |= (1<<5);
4173                 DP(NETIF_MSG_LINK, "807x autoneg val = 0x%x\n", val);
4174         }
4175
4176         bnx2x_cl45_write(bp, phy, MDIO_AN_DEVAD, MDIO_AN_REG_ADV, val);
4177         bnx2x_cl45_read(bp, phy, MDIO_AN_DEVAD, MDIO_AN_REG_8073_2_5G, &tmp1);
4178
4179         if (((phy->speed_cap_mask & PORT_HW_CFG_SPEED_CAPABILITY_D0_2_5G) &&
4180              (phy->req_line_speed == SPEED_AUTO_NEG)) ||
4181             (phy->req_line_speed == SPEED_2500)) {
4182                 u16 phy_ver;
4183                 /* Allow 2.5G for A1 and above */
4184                 bnx2x_cl45_read(bp, phy,
4185                                 MDIO_PMA_DEVAD, MDIO_PMA_REG_8073_CHIP_REV,
4186                                 &phy_ver);
4187                 DP(NETIF_MSG_LINK, "Add 2.5G\n");
4188                 if (phy_ver > 0)
4189                         tmp1 |= 1;
4190                 else
4191                         tmp1 &= 0xfffe;
4192         } else {
4193                 DP(NETIF_MSG_LINK, "Disable 2.5G\n");
4194                 tmp1 &= 0xfffe;
4195         }
4196
4197         bnx2x_cl45_write(bp, phy, MDIO_AN_DEVAD, MDIO_AN_REG_8073_2_5G, tmp1);
4198         /* Add support for CL37 (passive mode) II */
4199
4200         bnx2x_cl45_read(bp, phy, MDIO_AN_DEVAD, MDIO_AN_REG_CL37_FC_LD, &tmp1);
4201         bnx2x_cl45_write(bp, phy, MDIO_AN_DEVAD, MDIO_AN_REG_CL37_FC_LD,
4202                          (tmp1 | ((phy->req_duplex == DUPLEX_FULL) ?
4203                                   0x20 : 0x40)));
4204
4205         /* Add support for CL37 (passive mode) III */
4206         bnx2x_cl45_write(bp, phy, MDIO_AN_DEVAD, MDIO_AN_REG_CL37_AN, 0x1000);
4207
4208         /* The SNR will improve about 2db by changing
4209         BW and FEE main tap. Rest commands are executed
4210         after link is up*/
4211         if (bnx2x_8073_is_snr_needed(bp, phy))
4212                 bnx2x_cl45_write(bp, phy,
4213                                  MDIO_PMA_DEVAD, MDIO_PMA_REG_EDC_FFE_MAIN,
4214                                  0xFB0C);
4215
4216         /* Enable FEC (Forware Error Correction) Request in the AN */
4217         bnx2x_cl45_read(bp, phy, MDIO_AN_DEVAD, MDIO_AN_REG_ADV2, &tmp1);
4218         tmp1 |= (1<<15);
4219         bnx2x_cl45_write(bp, phy, MDIO_AN_DEVAD, MDIO_AN_REG_ADV2, tmp1);
4220
4221         bnx2x_ext_phy_set_pause(params, phy, vars);
4222
4223         /* Restart autoneg */
4224         msleep(500);
4225         bnx2x_cl45_write(bp, phy, MDIO_AN_DEVAD, MDIO_AN_REG_CTRL, 0x1200);
4226         DP(NETIF_MSG_LINK, "807x Autoneg Restart: Advertise 1G=%x, 10G=%x\n",
4227                    ((val & (1<<5)) > 0), ((val & (1<<7)) > 0));
4228         return 0;
4229 }
4230
4231 static u8 bnx2x_8073_read_status(struct bnx2x_phy *phy,
4232                                  struct link_params *params,
4233                                  struct link_vars *vars)
4234 {
4235         struct bnx2x *bp = params->bp;
4236         u8 link_up = 0;
4237         u16 val1, val2;
4238         u16 link_status = 0;
4239         u16 an1000_status = 0;
4240
4241         bnx2x_cl45_read(bp, phy,
4242                         MDIO_PMA_DEVAD, MDIO_PMA_REG_LASI_STATUS, &val1);
4243
4244         DP(NETIF_MSG_LINK, "8703 LASI status 0x%x\n", val1);
4245
4246         /* clear the interrupt LASI status register */
4247         bnx2x_cl45_read(bp, phy,
4248                         MDIO_PCS_DEVAD, MDIO_PCS_REG_STATUS, &val2);
4249         bnx2x_cl45_read(bp, phy,
4250                         MDIO_PCS_DEVAD, MDIO_PCS_REG_STATUS, &val1);
4251         DP(NETIF_MSG_LINK, "807x PCS status 0x%x->0x%x\n", val2, val1);
4252         /* Clear MSG-OUT */
4253         bnx2x_cl45_read(bp, phy,
4254                         MDIO_PMA_DEVAD, MDIO_PMA_REG_M8051_MSGOUT_REG, &val1);
4255
4256         /* Check the LASI */
4257         bnx2x_cl45_read(bp, phy,
4258                         MDIO_PMA_DEVAD, MDIO_PMA_REG_RX_ALARM, &val2);
4259
4260         DP(NETIF_MSG_LINK, "KR 0x9003 0x%x\n", val2);
4261
4262         /* Check the link status */
4263         bnx2x_cl45_read(bp, phy,
4264                         MDIO_PCS_DEVAD, MDIO_PCS_REG_STATUS, &val2);
4265         DP(NETIF_MSG_LINK, "KR PCS status 0x%x\n", val2);
4266
4267         bnx2x_cl45_read(bp, phy,
4268                         MDIO_PMA_DEVAD, MDIO_PMA_REG_STATUS, &val2);
4269         bnx2x_cl45_read(bp, phy,
4270                         MDIO_PMA_DEVAD, MDIO_PMA_REG_STATUS, &val1);
4271         link_up = ((val1 & 4) == 4);
4272         DP(NETIF_MSG_LINK, "PMA_REG_STATUS=0x%x\n", val1);
4273
4274         if (link_up &&
4275              ((phy->req_line_speed != SPEED_10000))) {
4276                 if (bnx2x_8073_xaui_wa(bp, phy) != 0)
4277                         return 0;
4278         }
4279         bnx2x_cl45_read(bp, phy,
4280                         MDIO_AN_DEVAD, MDIO_AN_REG_LINK_STATUS, &an1000_status);
4281         bnx2x_cl45_read(bp, phy,
4282                         MDIO_AN_DEVAD, MDIO_AN_REG_LINK_STATUS, &an1000_status);
4283
4284         /* Check the link status on 1.1.2 */
4285         bnx2x_cl45_read(bp, phy,
4286                         MDIO_PMA_DEVAD, MDIO_PMA_REG_STATUS, &val2);
4287         bnx2x_cl45_read(bp, phy,
4288                         MDIO_PMA_DEVAD, MDIO_PMA_REG_STATUS, &val1);
4289         DP(NETIF_MSG_LINK, "KR PMA status 0x%x->0x%x,"
4290                    "an_link_status=0x%x\n", val2, val1, an1000_status);
4291
4292         link_up = (((val1 & 4) == 4) || (an1000_status & (1<<1)));
4293         if (link_up && bnx2x_8073_is_snr_needed(bp, phy)) {
4294                 /* The SNR will improve about 2dbby
4295                 changing the BW and FEE main tap.*/
4296                 /* The 1st write to change FFE main
4297                 tap is set before restart AN */
4298                 /* Change PLL Bandwidth in EDC
4299                 register */
4300                 bnx2x_cl45_write(bp, phy,
4301                                  MDIO_PMA_DEVAD, MDIO_PMA_REG_PLL_BANDWIDTH,
4302                                  0x26BC);
4303
4304                 /* Change CDR Bandwidth in EDC register */
4305                 bnx2x_cl45_write(bp, phy,
4306                                  MDIO_PMA_DEVAD, MDIO_PMA_REG_CDR_BANDWIDTH,
4307                                  0x0333);
4308         }
4309         bnx2x_cl45_read(bp, phy,
4310                         MDIO_PMA_DEVAD, MDIO_PMA_REG_8073_SPEED_LINK_STATUS,
4311                         &link_status);
4312
4313         /* Bits 0..2 --> speed detected, bits 13..15--> link is down */
4314         if ((link_status & (1<<2)) && (!(link_status & (1<<15)))) {
4315                 link_up = 1;
4316                 vars->line_speed = SPEED_10000;
4317                 DP(NETIF_MSG_LINK, "port %x: External link up in 10G\n",
4318                            params->port);
4319         } else if ((link_status & (1<<1)) && (!(link_status & (1<<14)))) {
4320                 link_up = 1;
4321                 vars->line_speed = SPEED_2500;
4322                 DP(NETIF_MSG_LINK, "port %x: External link up in 2.5G\n",
4323                            params->port);
4324         } else if ((link_status & (1<<0)) && (!(link_status & (1<<13)))) {
4325                 link_up = 1;
4326                 vars->line_speed = SPEED_1000;
4327                 DP(NETIF_MSG_LINK, "port %x: External link up in 1G\n",
4328                            params->port);
4329         } else {
4330                 link_up = 0;
4331                 DP(NETIF_MSG_LINK, "port %x: External link is down\n",
4332                            params->port);
4333         }
4334
4335         if (link_up) {
4336                 /* Swap polarity if required */
4337                 if (params->lane_config &
4338                     PORT_HW_CFG_SWAP_PHY_POLARITY_ENABLED) {
4339                         /* Configure the 8073 to swap P and N of the KR lines */
4340                         bnx2x_cl45_read(bp, phy,
4341                                         MDIO_XS_DEVAD,
4342                                         MDIO_XS_REG_8073_RX_CTRL_PCIE, &val1);
4343                         /**
4344                         * Set bit 3 to invert Rx in 1G mode and clear this bit
4345                         * when it`s in 10G mode.
4346                         */
4347                         if (vars->line_speed == SPEED_1000) {
4348                                 DP(NETIF_MSG_LINK, "Swapping 1G polarity for"
4349                                               "the 8073\n");
4350                                 val1 |= (1<<3);
4351                         } else
4352                                 val1 &= ~(1<<3);
4353
4354                         bnx2x_cl45_write(bp, phy,
4355                                          MDIO_XS_DEVAD,
4356                                          MDIO_XS_REG_8073_RX_CTRL_PCIE,
4357                                          val1);
4358                 }
4359                 bnx2x_ext_phy_10G_an_resolve(bp, phy, vars);
4360                 bnx2x_8073_resolve_fc(phy, params, vars);
4361         }
4362         return link_up;
4363 }
4364
4365 static void bnx2x_8073_link_reset(struct bnx2x_phy *phy,
4366                                   struct link_params *params)
4367 {
4368         struct bnx2x *bp = params->bp;
4369         u8 gpio_port;
4370         if (CHIP_IS_E2(bp))
4371                 gpio_port = BP_PATH(bp);
4372         else
4373                 gpio_port = params->port;
4374         DP(NETIF_MSG_LINK, "Setting 8073 port %d into low power mode\n",
4375            gpio_port);
4376         bnx2x_set_gpio(bp, MISC_REGISTERS_GPIO_2,
4377                             MISC_REGISTERS_GPIO_OUTPUT_LOW,
4378                             gpio_port);
4379 }
4380
4381 /******************************************************************/
4382 /*                      BCM8705 PHY SECTION                       */
4383 /******************************************************************/
4384 static u8 bnx2x_8705_config_init(struct bnx2x_phy *phy,
4385                                  struct link_params *params,
4386                                  struct link_vars *vars)
4387 {
4388         struct bnx2x *bp = params->bp;
4389         DP(NETIF_MSG_LINK, "init 8705\n");
4390         /* Restore normal power mode*/
4391         bnx2x_set_gpio(bp, MISC_REGISTERS_GPIO_2,
4392                             MISC_REGISTERS_GPIO_OUTPUT_HIGH, params->port);
4393         /* HW reset */
4394         bnx2x_ext_phy_hw_reset(bp, params->port);
4395         bnx2x_cl45_write(bp, phy, MDIO_PMA_DEVAD, MDIO_PMA_REG_CTRL, 0xa040);
4396         bnx2x_wait_reset_complete(bp, phy);
4397
4398         bnx2x_cl45_write(bp, phy,
4399                          MDIO_PMA_DEVAD, MDIO_PMA_REG_MISC_CTRL, 0x8288);
4400         bnx2x_cl45_write(bp, phy,
4401                          MDIO_PMA_DEVAD, MDIO_PMA_REG_PHY_IDENTIFIER, 0x7fbf);
4402         bnx2x_cl45_write(bp, phy,
4403                          MDIO_PMA_DEVAD, MDIO_PMA_REG_CMU_PLL_BYPASS, 0x0100);
4404         bnx2x_cl45_write(bp, phy,
4405                          MDIO_WIS_DEVAD, MDIO_WIS_REG_LASI_CNTL, 0x1);
4406         /* BCM8705 doesn't have microcode, hence the 0 */
4407         bnx2x_save_spirom_version(bp, params->port, params->shmem_base, 0);
4408         return 0;
4409 }
4410
4411 static u8 bnx2x_8705_read_status(struct bnx2x_phy *phy,
4412                                  struct link_params *params,
4413                                  struct link_vars *vars)
4414 {
4415         u8 link_up = 0;
4416         u16 val1, rx_sd;
4417         struct bnx2x *bp = params->bp;
4418         DP(NETIF_MSG_LINK, "read status 8705\n");
4419         bnx2x_cl45_read(bp, phy,
4420                       MDIO_WIS_DEVAD, MDIO_WIS_REG_LASI_STATUS, &val1);
4421         DP(NETIF_MSG_LINK, "8705 LASI status 0x%x\n", val1);
4422
4423         bnx2x_cl45_read(bp, phy,
4424                       MDIO_WIS_DEVAD, MDIO_WIS_REG_LASI_STATUS, &val1);
4425         DP(NETIF_MSG_LINK, "8705 LASI status 0x%x\n", val1);
4426
4427         bnx2x_cl45_read(bp, phy,
4428                       MDIO_PMA_DEVAD, MDIO_PMA_REG_RX_SD, &rx_sd);
4429
4430         bnx2x_cl45_read(bp, phy,
4431                       MDIO_PMA_DEVAD, 0xc809, &val1);
4432         bnx2x_cl45_read(bp, phy,
4433                       MDIO_PMA_DEVAD, 0xc809, &val1);
4434
4435         DP(NETIF_MSG_LINK, "8705 1.c809 val=0x%x\n", val1);
4436         link_up = ((rx_sd & 0x1) && (val1 & (1<<9)) && ((val1 & (1<<8)) == 0));
4437         if (link_up) {
4438                 vars->line_speed = SPEED_10000;
4439                 bnx2x_ext_phy_resolve_fc(phy, params, vars);
4440         }
4441         return link_up;
4442 }
4443
4444 /******************************************************************/
4445 /*                      SFP+ module Section                       */
4446 /******************************************************************/
4447 static void bnx2x_sfp_set_transmitter(struct bnx2x *bp,
4448                                       struct bnx2x_phy *phy,
4449                                       u8 port,
4450                                       u8 tx_en)
4451 {
4452         u16 val;
4453
4454         DP(NETIF_MSG_LINK, "Setting transmitter tx_en=%x for port %x\n",
4455                  tx_en, port);
4456         /* Disable/Enable transmitter ( TX laser of the SFP+ module.)*/
4457         bnx2x_cl45_read(bp, phy,
4458                       MDIO_PMA_DEVAD,
4459                       MDIO_PMA_REG_PHY_IDENTIFIER,
4460                       &val);
4461
4462         if (tx_en)
4463                 val &= ~(1<<15);
4464         else
4465                 val |= (1<<15);
4466
4467         bnx2x_cl45_write(bp, phy,
4468                        MDIO_PMA_DEVAD,
4469                        MDIO_PMA_REG_PHY_IDENTIFIER,
4470                        val);
4471 }
4472
4473 static u8 bnx2x_8726_read_sfp_module_eeprom(struct bnx2x_phy *phy,
4474                                             struct link_params *params,
4475                                           u16 addr, u8 byte_cnt, u8 *o_buf)
4476 {
4477         struct bnx2x *bp = params->bp;
4478         u16 val = 0;
4479         u16 i;
4480         if (byte_cnt > 16) {
4481                 DP(NETIF_MSG_LINK, "Reading from eeprom is"
4482                             " is limited to 0xf\n");
4483                 return -EINVAL;
4484         }
4485         /* Set the read command byte count */
4486         bnx2x_cl45_write(bp, phy,
4487                          MDIO_PMA_DEVAD, MDIO_PMA_REG_SFP_TWO_WIRE_BYTE_CNT,
4488                        (byte_cnt | 0xa000));
4489
4490         /* Set the read command address */
4491         bnx2x_cl45_write(bp, phy,
4492                          MDIO_PMA_DEVAD, MDIO_PMA_REG_SFP_TWO_WIRE_MEM_ADDR,
4493                        addr);
4494
4495         /* Activate read command */
4496         bnx2x_cl45_write(bp, phy,
4497                          MDIO_PMA_DEVAD, MDIO_PMA_REG_SFP_TWO_WIRE_CTRL,
4498                        0x2c0f);
4499
4500         /* Wait up to 500us for command complete status */
4501         for (i = 0; i < 100; i++) {
4502                 bnx2x_cl45_read(bp, phy,
4503                               MDIO_PMA_DEVAD,
4504                               MDIO_PMA_REG_SFP_TWO_WIRE_CTRL, &val);
4505                 if ((val & MDIO_PMA_REG_SFP_TWO_WIRE_CTRL_STATUS_MASK) ==
4506                     MDIO_PMA_REG_SFP_TWO_WIRE_STATUS_COMPLETE)
4507                         break;
4508                 udelay(5);
4509         }
4510
4511         if ((val & MDIO_PMA_REG_SFP_TWO_WIRE_CTRL_STATUS_MASK) !=
4512                     MDIO_PMA_REG_SFP_TWO_WIRE_STATUS_COMPLETE) {
4513                 DP(NETIF_MSG_LINK,
4514                          "Got bad status 0x%x when reading from SFP+ EEPROM\n",
4515                          (val & MDIO_PMA_REG_SFP_TWO_WIRE_CTRL_STATUS_MASK));
4516                 return -EINVAL;
4517         }
4518
4519         /* Read the buffer */
4520         for (i = 0; i < byte_cnt; i++) {
4521                 bnx2x_cl45_read(bp, phy,
4522                               MDIO_PMA_DEVAD,
4523                               MDIO_PMA_REG_8726_TWO_WIRE_DATA_BUF + i, &val);
4524                 o_buf[i] = (u8)(val & MDIO_PMA_REG_8726_TWO_WIRE_DATA_MASK);
4525         }
4526
4527         for (i = 0; i < 100; i++) {
4528                 bnx2x_cl45_read(bp, phy,
4529                               MDIO_PMA_DEVAD,
4530                               MDIO_PMA_REG_SFP_TWO_WIRE_CTRL, &val);
4531                 if ((val & MDIO_PMA_REG_SFP_TWO_WIRE_CTRL_STATUS_MASK) ==
4532                     MDIO_PMA_REG_SFP_TWO_WIRE_STATUS_IDLE)
4533                         return 0;
4534                 msleep(1);
4535         }
4536         return -EINVAL;
4537 }
4538
4539 static u8 bnx2x_8727_read_sfp_module_eeprom(struct bnx2x_phy *phy,
4540                                             struct link_params *params,
4541                                           u16 addr, u8 byte_cnt, u8 *o_buf)
4542 {
4543         struct bnx2x *bp = params->bp;
4544         u16 val, i;
4545
4546         if (byte_cnt > 16) {
4547                 DP(NETIF_MSG_LINK, "Reading from eeprom is"
4548                             " is limited to 0xf\n");
4549                 return -EINVAL;
4550         }
4551
4552         /* Need to read from 1.8000 to clear it */
4553         bnx2x_cl45_read(bp, phy,
4554                       MDIO_PMA_DEVAD,
4555                       MDIO_PMA_REG_SFP_TWO_WIRE_CTRL,
4556                       &val);
4557
4558         /* Set the read command byte count */
4559         bnx2x_cl45_write(bp, phy,
4560                        MDIO_PMA_DEVAD,
4561                        MDIO_PMA_REG_SFP_TWO_WIRE_BYTE_CNT,
4562                        ((byte_cnt < 2) ? 2 : byte_cnt));
4563
4564         /* Set the read command address */
4565         bnx2x_cl45_write(bp, phy,
4566                        MDIO_PMA_DEVAD,
4567                        MDIO_PMA_REG_SFP_TWO_WIRE_MEM_ADDR,
4568                        addr);
4569         /* Set the destination address */
4570         bnx2x_cl45_write(bp, phy,
4571                        MDIO_PMA_DEVAD,
4572                        0x8004,
4573                        MDIO_PMA_REG_8727_TWO_WIRE_DATA_BUF);
4574
4575         /* Activate read command */
4576         bnx2x_cl45_write(bp, phy,
4577                        MDIO_PMA_DEVAD,
4578                        MDIO_PMA_REG_SFP_TWO_WIRE_CTRL,
4579                        0x8002);
4580         /* Wait appropriate time for two-wire command to finish before
4581         polling the status register */
4582         msleep(1);
4583
4584         /* Wait up to 500us for command complete status */
4585         for (i = 0; i < 100; i++) {
4586                 bnx2x_cl45_read(bp, phy,
4587                               MDIO_PMA_DEVAD,
4588                               MDIO_PMA_REG_SFP_TWO_WIRE_CTRL, &val);
4589                 if ((val & MDIO_PMA_REG_SFP_TWO_WIRE_CTRL_STATUS_MASK) ==
4590                     MDIO_PMA_REG_SFP_TWO_WIRE_STATUS_COMPLETE)
4591                         break;
4592                 udelay(5);
4593         }
4594
4595         if ((val & MDIO_PMA_REG_SFP_TWO_WIRE_CTRL_STATUS_MASK) !=
4596                     MDIO_PMA_REG_SFP_TWO_WIRE_STATUS_COMPLETE) {
4597                 DP(NETIF_MSG_LINK,
4598                          "Got bad status 0x%x when reading from SFP+ EEPROM\n",
4599                          (val & MDIO_PMA_REG_SFP_TWO_WIRE_CTRL_STATUS_MASK));
4600                 return -EINVAL;
4601         }
4602
4603         /* Read the buffer */
4604         for (i = 0; i < byte_cnt; i++) {
4605                 bnx2x_cl45_read(bp, phy,
4606                               MDIO_PMA_DEVAD,
4607                               MDIO_PMA_REG_8727_TWO_WIRE_DATA_BUF + i, &val);
4608                 o_buf[i] = (u8)(val & MDIO_PMA_REG_8727_TWO_WIRE_DATA_MASK);
4609         }
4610
4611         for (i = 0; i < 100; i++) {
4612                 bnx2x_cl45_read(bp, phy,
4613                               MDIO_PMA_DEVAD,
4614                               MDIO_PMA_REG_SFP_TWO_WIRE_CTRL, &val);
4615                 if ((val & MDIO_PMA_REG_SFP_TWO_WIRE_CTRL_STATUS_MASK) ==
4616                     MDIO_PMA_REG_SFP_TWO_WIRE_STATUS_IDLE)
4617                         return 0;
4618                 msleep(1);
4619         }
4620
4621         return -EINVAL;
4622 }
4623
4624 static u8 bnx2x_read_sfp_module_eeprom(struct bnx2x_phy *phy,
4625                                        struct link_params *params, u16 addr,
4626                                        u8 byte_cnt, u8 *o_buf)
4627 {
4628         if (phy->type == PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8726)
4629                 return bnx2x_8726_read_sfp_module_eeprom(phy, params, addr,
4630                                                        byte_cnt, o_buf);
4631         else if (phy->type == PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8727)
4632                 return bnx2x_8727_read_sfp_module_eeprom(phy, params, addr,
4633                                                        byte_cnt, o_buf);
4634         return -EINVAL;
4635 }
4636
4637 static u8 bnx2x_get_edc_mode(struct bnx2x_phy *phy,
4638                              struct link_params *params,
4639                                   u16 *edc_mode)
4640 {
4641         struct bnx2x *bp = params->bp;
4642         u8 val, check_limiting_mode = 0;
4643         *edc_mode = EDC_MODE_LIMITING;
4644
4645         /* First check for copper cable */
4646         if (bnx2x_read_sfp_module_eeprom(phy,
4647                                          params,
4648                                          SFP_EEPROM_CON_TYPE_ADDR,
4649                                          1,
4650                                          &val) != 0) {
4651                 DP(NETIF_MSG_LINK, "Failed to read from SFP+ module EEPROM\n");
4652                 return -EINVAL;
4653         }
4654
4655         switch (val) {
4656         case SFP_EEPROM_CON_TYPE_VAL_COPPER:
4657         {
4658                 u8 copper_module_type;
4659
4660                 /* Check if its active cable( includes SFP+ module)
4661                 of passive cable*/
4662                 if (bnx2x_read_sfp_module_eeprom(phy,
4663                                                params,
4664                                                SFP_EEPROM_FC_TX_TECH_ADDR,
4665                                                1,
4666                                                &copper_module_type) !=
4667                     0) {
4668                         DP(NETIF_MSG_LINK,
4669                                 "Failed to read copper-cable-type"
4670                                 " from SFP+ EEPROM\n");
4671                         return -EINVAL;
4672                 }
4673
4674                 if (copper_module_type &
4675                     SFP_EEPROM_FC_TX_TECH_BITMASK_COPPER_ACTIVE) {
4676                         DP(NETIF_MSG_LINK, "Active Copper cable detected\n");
4677                         check_limiting_mode = 1;
4678                 } else if (copper_module_type &
4679                         SFP_EEPROM_FC_TX_TECH_BITMASK_COPPER_PASSIVE) {
4680                                 DP(NETIF_MSG_LINK, "Passive Copper"
4681                                             " cable detected\n");
4682                                 *edc_mode =
4683                                       EDC_MODE_PASSIVE_DAC;
4684                 } else {
4685                         DP(NETIF_MSG_LINK, "Unknown copper-cable-"
4686                                      "type 0x%x !!!\n", copper_module_type);
4687                         return -EINVAL;
4688                 }
4689                 break;
4690         }
4691         case SFP_EEPROM_CON_TYPE_VAL_LC:
4692                 DP(NETIF_MSG_LINK, "Optic module detected\n");
4693                 check_limiting_mode = 1;
4694                 break;
4695         default:
4696                 DP(NETIF_MSG_LINK, "Unable to determine module type 0x%x !!!\n",
4697                          val);
4698                 return -EINVAL;
4699         }
4700
4701         if (check_limiting_mode) {
4702                 u8 options[SFP_EEPROM_OPTIONS_SIZE];
4703                 if (bnx2x_read_sfp_module_eeprom(phy,
4704                                                  params,
4705                                                  SFP_EEPROM_OPTIONS_ADDR,
4706                                                  SFP_EEPROM_OPTIONS_SIZE,
4707                                                  options) != 0) {
4708                         DP(NETIF_MSG_LINK, "Failed to read Option"
4709                                 " field from module EEPROM\n");
4710                         return -EINVAL;
4711                 }
4712                 if ((options[0] & SFP_EEPROM_OPTIONS_LINEAR_RX_OUT_MASK))
4713                         *edc_mode = EDC_MODE_LINEAR;
4714                 else
4715                         *edc_mode = EDC_MODE_LIMITING;
4716         }
4717         DP(NETIF_MSG_LINK, "EDC mode is set to 0x%x\n", *edc_mode);
4718         return 0;
4719 }
4720 /* This function read the relevant field from the module ( SFP+ ),
4721         and verify it is compliant with this board */
4722 static u8 bnx2x_verify_sfp_module(struct bnx2x_phy *phy,
4723                                   struct link_params *params)
4724 {
4725         struct bnx2x *bp = params->bp;
4726         u32 val, cmd;
4727         u32 fw_resp, fw_cmd_param;
4728         char vendor_name[SFP_EEPROM_VENDOR_NAME_SIZE+1];
4729         char vendor_pn[SFP_EEPROM_PART_NO_SIZE+1];
4730         phy->flags &= ~FLAGS_SFP_NOT_APPROVED;
4731         val = REG_RD(bp, params->shmem_base +
4732                          offsetof(struct shmem_region, dev_info.
4733                                   port_feature_config[params->port].config));
4734         if ((val & PORT_FEAT_CFG_OPT_MDL_ENFRCMNT_MASK) ==
4735             PORT_FEAT_CFG_OPT_MDL_ENFRCMNT_NO_ENFORCEMENT) {
4736                 DP(NETIF_MSG_LINK, "NOT enforcing module verification\n");
4737                 return 0;
4738         }
4739
4740         if (params->feature_config_flags &
4741             FEATURE_CONFIG_BC_SUPPORTS_DUAL_PHY_OPT_MDL_VRFY) {
4742                 /* Use specific phy request */
4743                 cmd = DRV_MSG_CODE_VRFY_SPECIFIC_PHY_OPT_MDL;
4744         } else if (params->feature_config_flags &
4745                    FEATURE_CONFIG_BC_SUPPORTS_OPT_MDL_VRFY) {
4746                 /* Use first phy request only in case of non-dual media*/
4747                 if (DUAL_MEDIA(params)) {
4748                         DP(NETIF_MSG_LINK, "FW does not support OPT MDL "
4749                            "verification\n");
4750                         return -EINVAL;
4751                 }
4752                 cmd = DRV_MSG_CODE_VRFY_FIRST_PHY_OPT_MDL;
4753         } else {
4754                 /* No support in OPT MDL detection */
4755                 DP(NETIF_MSG_LINK, "FW does not support OPT MDL "
4756                           "verification\n");
4757                 return -EINVAL;
4758         }
4759
4760         fw_cmd_param = FW_PARAM_SET(phy->addr, phy->type, phy->mdio_ctrl);
4761         fw_resp = bnx2x_fw_command(bp, cmd, fw_cmd_param);
4762         if (fw_resp == FW_MSG_CODE_VRFY_OPT_MDL_SUCCESS) {
4763                 DP(NETIF_MSG_LINK, "Approved module\n");
4764                 return 0;
4765         }
4766
4767         /* format the warning message */
4768         if (bnx2x_read_sfp_module_eeprom(phy,
4769                                          params,
4770                                        SFP_EEPROM_VENDOR_NAME_ADDR,
4771                                        SFP_EEPROM_VENDOR_NAME_SIZE,
4772                                        (u8 *)vendor_name))
4773                 vendor_name[0] = '\0';
4774         else
4775                 vendor_name[SFP_EEPROM_VENDOR_NAME_SIZE] = '\0';
4776         if (bnx2x_read_sfp_module_eeprom(phy,
4777                                          params,
4778                                        SFP_EEPROM_PART_NO_ADDR,
4779                                        SFP_EEPROM_PART_NO_SIZE,
4780                                        (u8 *)vendor_pn))
4781                 vendor_pn[0] = '\0';
4782         else
4783                 vendor_pn[SFP_EEPROM_PART_NO_SIZE] = '\0';
4784
4785         netdev_info(bp->dev, "Warning: Unqualified SFP+ module detected,"
4786                              " Port %d from %s part number %s\n",
4787                     params->port, vendor_name, vendor_pn);
4788         phy->flags |= FLAGS_SFP_NOT_APPROVED;
4789         return -EINVAL;
4790 }
4791
4792 static u8 bnx2x_wait_for_sfp_module_initialized(struct bnx2x_phy *phy,
4793                                                 struct link_params *params)
4794
4795 {
4796         u8 val;
4797         struct bnx2x *bp = params->bp;
4798         u16 timeout;
4799         /* Initialization time after hot-plug may take up to 300ms for some
4800         phys type ( e.g. JDSU ) */
4801         for (timeout = 0; timeout < 60; timeout++) {
4802                 if (bnx2x_read_sfp_module_eeprom(phy, params, 1, 1, &val)
4803                     == 0) {
4804                         DP(NETIF_MSG_LINK, "SFP+ module initialization "
4805                                      "took %d ms\n", timeout * 5);
4806                         return 0;
4807                 }
4808                 msleep(5);
4809         }
4810         return -EINVAL;
4811 }
4812
4813 static void bnx2x_8727_power_module(struct bnx2x *bp,
4814                                     struct bnx2x_phy *phy,
4815                                     u8 is_power_up) {
4816         /* Make sure GPIOs are not using for LED mode */
4817         u16 val;
4818         /*
4819          * In the GPIO register, bit 4 is use to detemine if the GPIOs are
4820          * operating as INPUT or as OUTPUT. Bit 1 is for input, and 0 for
4821          * output
4822          * Bits 0-1 determine the gpios value for OUTPUT in case bit 4 val is 0
4823          * Bits 8-9 determine the gpios value for INPUT in case bit 4 val is 1
4824          * where the 1st bit is the over-current(only input), and 2nd bit is
4825          * for power( only output )
4826         */
4827
4828         /*
4829          * In case of NOC feature is disabled and power is up, set GPIO control
4830          *  as input to enable listening of over-current indication
4831          */
4832         if (phy->flags & FLAGS_NOC)
4833                 return;
4834         if (!(phy->flags &
4835               FLAGS_NOC) && is_power_up)
4836                 val = (1<<4);
4837         else
4838                 /*
4839                  * Set GPIO control to OUTPUT, and set the power bit
4840                  * to according to the is_power_up
4841                  */
4842                 val = ((!(is_power_up)) << 1);
4843
4844         bnx2x_cl45_write(bp, phy,
4845                          MDIO_PMA_DEVAD,
4846                          MDIO_PMA_REG_8727_GPIO_CTRL,
4847                          val);
4848 }
4849
4850 static u8 bnx2x_8726_set_limiting_mode(struct bnx2x *bp,
4851                                        struct bnx2x_phy *phy,
4852                                        u16 edc_mode)
4853 {
4854         u16 cur_limiting_mode;
4855
4856         bnx2x_cl45_read(bp, phy,
4857                       MDIO_PMA_DEVAD,
4858                       MDIO_PMA_REG_ROM_VER2,
4859                       &cur_limiting_mode);
4860         DP(NETIF_MSG_LINK, "Current Limiting mode is 0x%x\n",
4861                  cur_limiting_mode);
4862
4863         if (edc_mode == EDC_MODE_LIMITING) {
4864                 DP(NETIF_MSG_LINK,
4865                          "Setting LIMITING MODE\n");
4866                 bnx2x_cl45_write(bp, phy,
4867                                  MDIO_PMA_DEVAD,
4868                                  MDIO_PMA_REG_ROM_VER2,
4869                                  EDC_MODE_LIMITING);
4870         } else { /* LRM mode ( default )*/
4871
4872                 DP(NETIF_MSG_LINK, "Setting LRM MODE\n");
4873
4874                 /* Changing to LRM mode takes quite few seconds.
4875                 So do it only if current mode is limiting
4876                 ( default is LRM )*/
4877                 if (cur_limiting_mode != EDC_MODE_LIMITING)
4878                         return 0;
4879
4880                 bnx2x_cl45_write(bp, phy,
4881                                MDIO_PMA_DEVAD,
4882                                MDIO_PMA_REG_LRM_MODE,
4883                                0);
4884                 bnx2x_cl45_write(bp, phy,
4885                                MDIO_PMA_DEVAD,
4886                                MDIO_PMA_REG_ROM_VER2,
4887                                0x128);
4888                 bnx2x_cl45_write(bp, phy,
4889                                MDIO_PMA_DEVAD,
4890                                MDIO_PMA_REG_MISC_CTRL0,
4891                                0x4008);
4892                 bnx2x_cl45_write(bp, phy,
4893                                MDIO_PMA_DEVAD,
4894                                MDIO_PMA_REG_LRM_MODE,
4895                                0xaaaa);
4896         }
4897         return 0;
4898 }
4899
4900 static u8 bnx2x_8727_set_limiting_mode(struct bnx2x *bp,
4901                                        struct bnx2x_phy *phy,
4902                                         u16 edc_mode)
4903 {
4904         u16 phy_identifier;
4905         u16 rom_ver2_val;
4906         bnx2x_cl45_read(bp, phy,
4907                        MDIO_PMA_DEVAD,
4908                        MDIO_PMA_REG_PHY_IDENTIFIER,
4909                        &phy_identifier);
4910
4911         bnx2x_cl45_write(bp, phy,
4912                        MDIO_PMA_DEVAD,
4913                        MDIO_PMA_REG_PHY_IDENTIFIER,
4914                        (phy_identifier & ~(1<<9)));
4915
4916         bnx2x_cl45_read(bp, phy,
4917                       MDIO_PMA_DEVAD,
4918                       MDIO_PMA_REG_ROM_VER2,
4919                       &rom_ver2_val);
4920         /* Keep the MSB 8-bits, and set the LSB 8-bits with the edc_mode */
4921         bnx2x_cl45_write(bp, phy,
4922                        MDIO_PMA_DEVAD,
4923                        MDIO_PMA_REG_ROM_VER2,
4924                        (rom_ver2_val & 0xff00) | (edc_mode & 0x00ff));
4925
4926         bnx2x_cl45_write(bp, phy,
4927                        MDIO_PMA_DEVAD,
4928                        MDIO_PMA_REG_PHY_IDENTIFIER,
4929                        (phy_identifier | (1<<9)));
4930
4931         return 0;
4932 }
4933
4934 static void bnx2x_8727_specific_func(struct bnx2x_phy *phy,
4935                                      struct link_params *params,
4936                                      u32 action)
4937 {
4938         struct bnx2x *bp = params->bp;
4939
4940         switch (action) {
4941         case DISABLE_TX:
4942                 bnx2x_sfp_set_transmitter(bp, phy, params->port, 0);
4943                 break;
4944         case ENABLE_TX:
4945                 if (!(phy->flags & FLAGS_SFP_NOT_APPROVED))
4946                         bnx2x_sfp_set_transmitter(bp, phy, params->port, 1);
4947                 break;
4948         default:
4949                 DP(NETIF_MSG_LINK, "Function 0x%x not supported by 8727\n",
4950                    action);
4951                 return;
4952         }
4953 }
4954
4955 static u8 bnx2x_sfp_module_detection(struct bnx2x_phy *phy,
4956                                      struct link_params *params)
4957 {
4958         struct bnx2x *bp = params->bp;
4959         u16 edc_mode;
4960         u8 rc = 0;
4961
4962         u32 val = REG_RD(bp, params->shmem_base +
4963                              offsetof(struct shmem_region, dev_info.
4964                                      port_feature_config[params->port].config));
4965
4966         DP(NETIF_MSG_LINK, "SFP+ module plugged in/out detected on port %d\n",
4967                  params->port);
4968
4969         if (bnx2x_get_edc_mode(phy, params, &edc_mode) != 0) {
4970                 DP(NETIF_MSG_LINK, "Failed to get valid module type\n");
4971                 return -EINVAL;
4972         } else if (bnx2x_verify_sfp_module(phy, params) !=
4973                    0) {
4974                 /* check SFP+ module compatibility */
4975                 DP(NETIF_MSG_LINK, "Module verification failed!!\n");
4976                 rc = -EINVAL;
4977                 /* Turn on fault module-detected led */
4978                 bnx2x_set_gpio(bp, MISC_REGISTERS_GPIO_0,
4979                                   MISC_REGISTERS_GPIO_HIGH,
4980                                   params->port);
4981                 if ((phy->type == PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8727) &&
4982                     ((val & PORT_FEAT_CFG_OPT_MDL_ENFRCMNT_MASK) ==
4983                      PORT_FEAT_CFG_OPT_MDL_ENFRCMNT_POWER_DOWN)) {
4984                         /* Shutdown SFP+ module */
4985                         DP(NETIF_MSG_LINK, "Shutdown SFP+ module!!\n");
4986                         bnx2x_8727_power_module(bp, phy, 0);
4987                         return rc;
4988                 }
4989         } else {
4990                 /* Turn off fault module-detected led */
4991                 DP(NETIF_MSG_LINK, "Turn off fault module-detected led\n");
4992                 bnx2x_set_gpio(bp, MISC_REGISTERS_GPIO_0,
4993                                           MISC_REGISTERS_GPIO_LOW,
4994                                           params->port);
4995         }
4996
4997         /* power up the SFP module */
4998         if (phy->type == PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8727)
4999                 bnx2x_8727_power_module(bp, phy, 1);
5000
5001         /* Check and set limiting mode / LRM mode on 8726.
5002         On 8727 it is done automatically */
5003         if (phy->type == PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8726)
5004                 bnx2x_8726_set_limiting_mode(bp, phy, edc_mode);
5005         else
5006                 bnx2x_8727_set_limiting_mode(bp, phy, edc_mode);
5007         /*
5008          * Enable transmit for this module if the module is approved, or
5009          * if unapproved modules should also enable the Tx laser
5010          */
5011         if (rc == 0 ||
5012             (val & PORT_FEAT_CFG_OPT_MDL_ENFRCMNT_MASK) !=
5013             PORT_FEAT_CFG_OPT_MDL_ENFRCMNT_DISABLE_TX_LASER)
5014                 bnx2x_sfp_set_transmitter(bp, phy, params->port, 1);
5015         else
5016                 bnx2x_sfp_set_transmitter(bp, phy, params->port, 0);
5017
5018         return rc;
5019 }
5020
5021 void bnx2x_handle_module_detect_int(struct link_params *params)
5022 {
5023         struct bnx2x *bp = params->bp;
5024         struct bnx2x_phy *phy = &params->phy[EXT_PHY1];
5025         u32 gpio_val;
5026         u8 port = params->port;
5027
5028         /* Set valid module led off */
5029         bnx2x_set_gpio(bp, MISC_REGISTERS_GPIO_0,
5030                           MISC_REGISTERS_GPIO_HIGH,
5031                           params->port);
5032
5033         /* Get current gpio val refelecting module plugged in / out*/
5034         gpio_val = bnx2x_get_gpio(bp, MISC_REGISTERS_GPIO_3, port);
5035
5036         /* Call the handling function in case module is detected */
5037         if (gpio_val == 0) {
5038
5039                 bnx2x_set_gpio_int(bp, MISC_REGISTERS_GPIO_3,
5040                                    MISC_REGISTERS_GPIO_INT_OUTPUT_CLR,
5041                                    port);
5042
5043                 if (bnx2x_wait_for_sfp_module_initialized(phy, params) == 0)
5044                         bnx2x_sfp_module_detection(phy, params);
5045                 else
5046                         DP(NETIF_MSG_LINK, "SFP+ module is not initialized\n");
5047         } else {
5048                 u32 val = REG_RD(bp, params->shmem_base +
5049                                      offsetof(struct shmem_region, dev_info.
5050                                               port_feature_config[params->port].
5051                                               config));
5052
5053                 bnx2x_set_gpio_int(bp, MISC_REGISTERS_GPIO_3,
5054                                    MISC_REGISTERS_GPIO_INT_OUTPUT_SET,
5055                                    port);
5056                 /* Module was plugged out. */
5057                 /* Disable transmit for this module */
5058                 if ((val & PORT_FEAT_CFG_OPT_MDL_ENFRCMNT_MASK) ==
5059                     PORT_FEAT_CFG_OPT_MDL_ENFRCMNT_DISABLE_TX_LASER)
5060                         bnx2x_sfp_set_transmitter(bp, phy, params->port, 0);
5061         }
5062 }
5063
5064 /******************************************************************/
5065 /*              common BCM8706/BCM8726 PHY SECTION                */
5066 /******************************************************************/
5067 static u8 bnx2x_8706_8726_read_status(struct bnx2x_phy *phy,
5068                                       struct link_params *params,
5069                                       struct link_vars *vars)
5070 {
5071         u8 link_up = 0;
5072         u16 val1, val2, rx_sd, pcs_status;
5073         struct bnx2x *bp = params->bp;
5074         DP(NETIF_MSG_LINK, "XGXS 8706/8726\n");
5075         /* Clear RX Alarm*/
5076         bnx2x_cl45_read(bp, phy,
5077                         MDIO_PMA_DEVAD, MDIO_PMA_REG_RX_ALARM, &val2);
5078         /* clear LASI indication*/
5079         bnx2x_cl45_read(bp, phy,
5080                         MDIO_PMA_DEVAD, MDIO_PMA_REG_LASI_STATUS, &val1);
5081         bnx2x_cl45_read(bp, phy,
5082                         MDIO_PMA_DEVAD, MDIO_PMA_REG_LASI_STATUS, &val2);
5083         DP(NETIF_MSG_LINK, "8706/8726 LASI status 0x%x--> 0x%x\n", val1, val2);
5084
5085         bnx2x_cl45_read(bp, phy,
5086                         MDIO_PMA_DEVAD, MDIO_PMA_REG_RX_SD, &rx_sd);
5087         bnx2x_cl45_read(bp, phy,
5088                         MDIO_PCS_DEVAD, MDIO_PCS_REG_STATUS, &pcs_status);
5089         bnx2x_cl45_read(bp, phy,
5090                         MDIO_AN_DEVAD, MDIO_AN_REG_LINK_STATUS, &val2);
5091         bnx2x_cl45_read(bp, phy,
5092                         MDIO_AN_DEVAD, MDIO_AN_REG_LINK_STATUS, &val2);
5093
5094         DP(NETIF_MSG_LINK, "8706/8726 rx_sd 0x%x pcs_status 0x%x 1Gbps"
5095                         " link_status 0x%x\n", rx_sd, pcs_status, val2);
5096         /* link is up if both bit 0 of pmd_rx_sd and
5097          * bit 0 of pcs_status are set, or if the autoneg bit
5098          * 1 is set
5099          */
5100         link_up = ((rx_sd & pcs_status & 0x1) || (val2 & (1<<1)));
5101         if (link_up) {
5102                 if (val2 & (1<<1))
5103                         vars->line_speed = SPEED_1000;
5104                 else
5105                         vars->line_speed = SPEED_10000;
5106                 bnx2x_ext_phy_resolve_fc(phy, params, vars);
5107         }
5108         return link_up;
5109 }
5110
5111 /******************************************************************/
5112 /*                      BCM8706 PHY SECTION                       */
5113 /******************************************************************/
5114 static u8 bnx2x_8706_config_init(struct bnx2x_phy *phy,
5115                                  struct link_params *params,
5116                                  struct link_vars *vars)
5117 {
5118         u16 cnt, val;
5119         struct bnx2x *bp = params->bp;
5120         bnx2x_set_gpio(bp, MISC_REGISTERS_GPIO_2,
5121                             MISC_REGISTERS_GPIO_OUTPUT_HIGH, params->port);
5122         /* HW reset */
5123         bnx2x_ext_phy_hw_reset(bp, params->port);
5124         bnx2x_cl45_write(bp, phy, MDIO_PMA_DEVAD, MDIO_PMA_REG_CTRL, 0xa040);
5125         bnx2x_wait_reset_complete(bp, phy);
5126
5127         /* Wait until fw is loaded */
5128         for (cnt = 0; cnt < 100; cnt++) {
5129                 bnx2x_cl45_read(bp, phy,
5130                                 MDIO_PMA_DEVAD, MDIO_PMA_REG_ROM_VER1, &val);
5131                 if (val)
5132                         break;
5133                 msleep(10);
5134         }
5135         DP(NETIF_MSG_LINK, "XGXS 8706 is initialized after %d ms\n", cnt);
5136         if ((params->feature_config_flags &
5137              FEATURE_CONFIG_OVERRIDE_PREEMPHASIS_ENABLED)) {
5138                 u8 i;
5139                 u16 reg;
5140                 for (i = 0; i < 4; i++) {
5141                         reg = MDIO_XS_8706_REG_BANK_RX0 +
5142                                 i*(MDIO_XS_8706_REG_BANK_RX1 -
5143                                    MDIO_XS_8706_REG_BANK_RX0);
5144                         bnx2x_cl45_read(bp, phy, MDIO_XS_DEVAD, reg, &val);
5145                         /* Clear first 3 bits of the control */
5146                         val &= ~0x7;
5147                         /* Set control bits according to configuration */
5148                         val |= (phy->rx_preemphasis[i] & 0x7);
5149                         DP(NETIF_MSG_LINK, "Setting RX Equalizer to BCM8706"
5150                                    " reg 0x%x <-- val 0x%x\n", reg, val);
5151                         bnx2x_cl45_write(bp, phy, MDIO_XS_DEVAD, reg, val);
5152                 }
5153         }
5154         /* Force speed */
5155         if (phy->req_line_speed == SPEED_10000) {
5156                 DP(NETIF_MSG_LINK, "XGXS 8706 force 10Gbps\n");
5157
5158                 bnx2x_cl45_write(bp, phy,
5159                                  MDIO_PMA_DEVAD,
5160                                  MDIO_PMA_REG_DIGITAL_CTRL, 0x400);
5161                 bnx2x_cl45_write(bp, phy,
5162                                  MDIO_PMA_DEVAD, MDIO_PMA_REG_LASI_CTRL, 1);
5163         } else {
5164                 /* Force 1Gbps using autoneg with 1G advertisment */
5165
5166                 /* Allow CL37 through CL73 */
5167                 DP(NETIF_MSG_LINK, "XGXS 8706 AutoNeg\n");
5168                 bnx2x_cl45_write(bp, phy,
5169                                  MDIO_AN_DEVAD, MDIO_AN_REG_CL37_CL73, 0x040c);
5170
5171                 /* Enable Full-Duplex advertisment on CL37 */
5172                 bnx2x_cl45_write(bp, phy,
5173                                  MDIO_AN_DEVAD, MDIO_AN_REG_CL37_FC_LP, 0x0020);
5174                 /* Enable CL37 AN */
5175                 bnx2x_cl45_write(bp, phy,
5176                                  MDIO_AN_DEVAD, MDIO_AN_REG_CL37_AN, 0x1000);
5177                 /* 1G support */
5178                 bnx2x_cl45_write(bp, phy,
5179                                  MDIO_AN_DEVAD, MDIO_AN_REG_ADV, (1<<5));
5180
5181                 /* Enable clause 73 AN */
5182                 bnx2x_cl45_write(bp, phy,
5183                                  MDIO_AN_DEVAD, MDIO_AN_REG_CTRL, 0x1200);
5184                 bnx2x_cl45_write(bp, phy,
5185                                  MDIO_PMA_DEVAD, MDIO_PMA_REG_RX_ALARM_CTRL,
5186                                  0x0400);
5187                 bnx2x_cl45_write(bp, phy,
5188                                  MDIO_PMA_DEVAD, MDIO_PMA_REG_LASI_CTRL,
5189                                  0x0004);
5190         }
5191         bnx2x_save_bcm_spirom_ver(bp, phy, params->port);
5192         return 0;
5193 }
5194
5195 static u8 bnx2x_8706_read_status(struct bnx2x_phy *phy,
5196                                  struct link_params *params,
5197                                  struct link_vars *vars)
5198 {
5199         return bnx2x_8706_8726_read_status(phy, params, vars);
5200 }
5201
5202 /******************************************************************/
5203 /*                      BCM8726 PHY SECTION                       */
5204 /******************************************************************/
5205 static void bnx2x_8726_config_loopback(struct bnx2x_phy *phy,
5206                                        struct link_params *params)
5207 {
5208         struct bnx2x *bp = params->bp;
5209         DP(NETIF_MSG_LINK, "PMA/PMD ext_phy_loopback: 8726\n");
5210         bnx2x_cl45_write(bp, phy, MDIO_PMA_DEVAD, MDIO_PMA_REG_CTRL, 0x0001);
5211 }
5212
5213 static void bnx2x_8726_external_rom_boot(struct bnx2x_phy *phy,
5214                                          struct link_params *params)
5215 {
5216         struct bnx2x *bp = params->bp;
5217         /* Need to wait 100ms after reset */
5218         msleep(100);
5219
5220         /* Micro controller re-boot */
5221         bnx2x_cl45_write(bp, phy,
5222                          MDIO_PMA_DEVAD, MDIO_PMA_REG_GEN_CTRL, 0x018B);
5223
5224         /* Set soft reset */
5225         bnx2x_cl45_write(bp, phy,
5226                        MDIO_PMA_DEVAD,
5227                        MDIO_PMA_REG_GEN_CTRL,
5228                        MDIO_PMA_REG_GEN_CTRL_ROM_MICRO_RESET);
5229
5230         bnx2x_cl45_write(bp, phy,
5231                        MDIO_PMA_DEVAD,
5232                        MDIO_PMA_REG_MISC_CTRL1, 0x0001);
5233
5234         bnx2x_cl45_write(bp, phy,
5235                        MDIO_PMA_DEVAD,
5236                        MDIO_PMA_REG_GEN_CTRL,
5237                        MDIO_PMA_REG_GEN_CTRL_ROM_RESET_INTERNAL_MP);
5238
5239         /* wait for 150ms for microcode load */
5240         msleep(150);
5241
5242         /* Disable serial boot control, tristates pins SS_N, SCK, MOSI, MISO */
5243         bnx2x_cl45_write(bp, phy,
5244                        MDIO_PMA_DEVAD,
5245                        MDIO_PMA_REG_MISC_CTRL1, 0x0000);
5246
5247         msleep(200);
5248         bnx2x_save_bcm_spirom_ver(bp, phy, params->port);
5249 }
5250
5251 static u8 bnx2x_8726_read_status(struct bnx2x_phy *phy,
5252                                  struct link_params *params,
5253                                  struct link_vars *vars)
5254 {
5255         struct bnx2x *bp = params->bp;
5256         u16 val1;
5257         u8 link_up = bnx2x_8706_8726_read_status(phy, params, vars);
5258         if (link_up) {
5259                 bnx2x_cl45_read(bp, phy,
5260                                 MDIO_PMA_DEVAD, MDIO_PMA_REG_PHY_IDENTIFIER,
5261                                 &val1);
5262                 if (val1 & (1<<15)) {
5263                         DP(NETIF_MSG_LINK, "Tx is disabled\n");
5264                         link_up = 0;
5265                         vars->line_speed = 0;
5266                 }
5267         }
5268         return link_up;
5269 }
5270
5271
5272 static u8 bnx2x_8726_config_init(struct bnx2x_phy *phy,
5273                                  struct link_params *params,
5274                                  struct link_vars *vars)
5275 {
5276         struct bnx2x *bp = params->bp;
5277         u32 val;
5278         u32 swap_val, swap_override, aeu_gpio_mask, offset;
5279         DP(NETIF_MSG_LINK, "Initializing BCM8726\n");
5280         /* Restore normal power mode*/
5281         bnx2x_set_gpio(bp, MISC_REGISTERS_GPIO_2,
5282                             MISC_REGISTERS_GPIO_OUTPUT_HIGH, params->port);
5283
5284         bnx2x_set_gpio(bp, MISC_REGISTERS_GPIO_1,
5285                             MISC_REGISTERS_GPIO_OUTPUT_HIGH, params->port);
5286
5287         bnx2x_cl45_write(bp, phy, MDIO_PMA_DEVAD, MDIO_PMA_REG_CTRL, 1<<15);
5288         bnx2x_wait_reset_complete(bp, phy);
5289
5290         bnx2x_8726_external_rom_boot(phy, params);
5291
5292         /* Need to call module detected on initialization since
5293         the module detection triggered by actual module
5294         insertion might occur before driver is loaded, and when
5295         driver is loaded, it reset all registers, including the
5296         transmitter */
5297         bnx2x_sfp_module_detection(phy, params);
5298
5299         if (phy->req_line_speed == SPEED_1000) {
5300                 DP(NETIF_MSG_LINK, "Setting 1G force\n");
5301                 bnx2x_cl45_write(bp, phy,
5302                                  MDIO_PMA_DEVAD, MDIO_PMA_REG_CTRL, 0x40);
5303                 bnx2x_cl45_write(bp, phy,
5304                                  MDIO_PMA_DEVAD, MDIO_PMA_REG_10G_CTRL2, 0xD);
5305                 bnx2x_cl45_write(bp, phy,
5306                                  MDIO_PMA_DEVAD, MDIO_PMA_REG_LASI_CTRL, 0x5);
5307                 bnx2x_cl45_write(bp, phy,
5308                                  MDIO_PMA_DEVAD, MDIO_PMA_REG_RX_ALARM_CTRL,
5309                                  0x400);
5310         } else if ((phy->req_line_speed == SPEED_AUTO_NEG) &&
5311                    (phy->speed_cap_mask &
5312                       PORT_HW_CFG_SPEED_CAPABILITY_D0_1G) &&
5313                    ((phy->speed_cap_mask &
5314                       PORT_HW_CFG_SPEED_CAPABILITY_D0_10G) !=
5315                     PORT_HW_CFG_SPEED_CAPABILITY_D0_10G)) {
5316                 DP(NETIF_MSG_LINK, "Setting 1G clause37\n");
5317                 /* Set Flow control */
5318                 bnx2x_ext_phy_set_pause(params, phy, vars);
5319                 bnx2x_cl45_write(bp, phy,
5320                                  MDIO_AN_DEVAD, MDIO_AN_REG_ADV, 0x20);
5321                 bnx2x_cl45_write(bp, phy,
5322                                  MDIO_AN_DEVAD, MDIO_AN_REG_CL37_CL73, 0x040c);
5323                 bnx2x_cl45_write(bp, phy,
5324                                  MDIO_AN_DEVAD, MDIO_AN_REG_CL37_FC_LD, 0x0020);
5325                 bnx2x_cl45_write(bp, phy,
5326                                  MDIO_AN_DEVAD, MDIO_AN_REG_CL37_AN, 0x1000);
5327                 bnx2x_cl45_write(bp, phy,
5328                                 MDIO_AN_DEVAD, MDIO_AN_REG_CTRL, 0x1200);
5329                 /* Enable RX-ALARM control to receive
5330                 interrupt for 1G speed change */
5331                 bnx2x_cl45_write(bp, phy,
5332                                  MDIO_PMA_DEVAD, MDIO_PMA_REG_LASI_CTRL, 0x4);
5333                 bnx2x_cl45_write(bp, phy,
5334                                  MDIO_PMA_DEVAD, MDIO_PMA_REG_RX_ALARM_CTRL,
5335                                  0x400);
5336
5337         } else { /* Default 10G. Set only LASI control */
5338                 bnx2x_cl45_write(bp, phy,
5339                                  MDIO_PMA_DEVAD, MDIO_PMA_REG_LASI_CTRL, 1);
5340         }
5341
5342         /* Set TX PreEmphasis if needed */
5343         if ((params->feature_config_flags &
5344              FEATURE_CONFIG_OVERRIDE_PREEMPHASIS_ENABLED)) {
5345                 DP(NETIF_MSG_LINK, "Setting TX_CTRL1 0x%x,"
5346                          "TX_CTRL2 0x%x\n",
5347                          phy->tx_preemphasis[0],
5348                          phy->tx_preemphasis[1]);
5349                 bnx2x_cl45_write(bp, phy,
5350                                  MDIO_PMA_DEVAD,
5351                                  MDIO_PMA_REG_8726_TX_CTRL1,
5352                                  phy->tx_preemphasis[0]);
5353
5354                 bnx2x_cl45_write(bp, phy,
5355                                  MDIO_PMA_DEVAD,
5356                                  MDIO_PMA_REG_8726_TX_CTRL2,
5357                                  phy->tx_preemphasis[1]);
5358         }
5359
5360         /* Set GPIO3 to trigger SFP+ module insertion/removal */
5361         bnx2x_set_gpio(bp, MISC_REGISTERS_GPIO_3,
5362                             MISC_REGISTERS_GPIO_INPUT_HI_Z, params->port);
5363
5364         /* The GPIO should be swapped if the swap register is set and active */
5365         swap_val = REG_RD(bp, NIG_REG_PORT_SWAP);
5366         swap_override = REG_RD(bp, NIG_REG_STRAP_OVERRIDE);
5367
5368         /* Select function upon port-swap configuration */
5369         if (params->port == 0) {
5370                 offset = MISC_REG_AEU_ENABLE1_FUNC_0_OUT_0;
5371                 aeu_gpio_mask = (swap_val && swap_override) ?
5372                         AEU_INPUTS_ATTN_BITS_GPIO3_FUNCTION_1 :
5373                         AEU_INPUTS_ATTN_BITS_GPIO3_FUNCTION_0;
5374         } else {
5375                 offset = MISC_REG_AEU_ENABLE1_FUNC_1_OUT_0;
5376                 aeu_gpio_mask = (swap_val && swap_override) ?
5377                         AEU_INPUTS_ATTN_BITS_GPIO3_FUNCTION_0 :
5378                         AEU_INPUTS_ATTN_BITS_GPIO3_FUNCTION_1;
5379         }
5380         val = REG_RD(bp, offset);
5381         /* add GPIO3 to group */
5382         val |= aeu_gpio_mask;
5383         REG_WR(bp, offset, val);
5384         return 0;
5385
5386 }
5387
5388 static void bnx2x_8726_link_reset(struct bnx2x_phy *phy,
5389                                   struct link_params *params)
5390 {
5391         struct bnx2x *bp = params->bp;
5392         DP(NETIF_MSG_LINK, "bnx2x_8726_link_reset port %d\n", params->port);
5393         /* Set serial boot control for external load */
5394         bnx2x_cl45_write(bp, phy,
5395                          MDIO_PMA_DEVAD,
5396                          MDIO_PMA_REG_GEN_CTRL, 0x0001);
5397 }
5398
5399 /******************************************************************/
5400 /*                      BCM8727 PHY SECTION                       */
5401 /******************************************************************/
5402
5403 static void bnx2x_8727_set_link_led(struct bnx2x_phy *phy,
5404                                     struct link_params *params, u8 mode)
5405 {
5406         struct bnx2x *bp = params->bp;
5407         u16 led_mode_bitmask = 0;
5408         u16 gpio_pins_bitmask = 0;
5409         u16 val;
5410         /* Only NOC flavor requires to set the LED specifically */
5411         if (!(phy->flags & FLAGS_NOC))
5412                 return;
5413         switch (mode) {
5414         case LED_MODE_FRONT_PANEL_OFF:
5415         case LED_MODE_OFF:
5416                 led_mode_bitmask = 0;
5417                 gpio_pins_bitmask = 0x03;
5418                 break;
5419         case LED_MODE_ON:
5420                 led_mode_bitmask = 0;
5421                 gpio_pins_bitmask = 0x02;
5422                 break;
5423         case LED_MODE_OPER:
5424                 led_mode_bitmask = 0x60;
5425                 gpio_pins_bitmask = 0x11;
5426                 break;
5427         }
5428         bnx2x_cl45_read(bp, phy,
5429                         MDIO_PMA_DEVAD,
5430                         MDIO_PMA_REG_8727_PCS_OPT_CTRL,
5431                         &val);
5432         val &= 0xff8f;
5433         val |= led_mode_bitmask;
5434         bnx2x_cl45_write(bp, phy,
5435                          MDIO_PMA_DEVAD,
5436                          MDIO_PMA_REG_8727_PCS_OPT_CTRL,
5437                          val);
5438         bnx2x_cl45_read(bp, phy,
5439                         MDIO_PMA_DEVAD,
5440                         MDIO_PMA_REG_8727_GPIO_CTRL,
5441                         &val);
5442         val &= 0xffe0;
5443         val |= gpio_pins_bitmask;
5444         bnx2x_cl45_write(bp, phy,
5445                          MDIO_PMA_DEVAD,
5446                          MDIO_PMA_REG_8727_GPIO_CTRL,
5447                          val);
5448 }
5449 static void bnx2x_8727_hw_reset(struct bnx2x_phy *phy,
5450                                 struct link_params *params) {
5451         u32 swap_val, swap_override;
5452         u8 port;
5453         /**
5454          * The PHY reset is controlled by GPIO 1. Fake the port number
5455          * to cancel the swap done in set_gpio()
5456          */
5457         struct bnx2x *bp = params->bp;
5458         swap_val = REG_RD(bp, NIG_REG_PORT_SWAP);
5459         swap_override = REG_RD(bp, NIG_REG_STRAP_OVERRIDE);
5460         port = (swap_val && swap_override) ^ 1;
5461         bnx2x_set_gpio(bp, MISC_REGISTERS_GPIO_1,
5462                             MISC_REGISTERS_GPIO_OUTPUT_LOW, port);
5463 }
5464
5465 static u8 bnx2x_8727_config_init(struct bnx2x_phy *phy,
5466                                  struct link_params *params,
5467                                  struct link_vars *vars)
5468 {
5469         u16 tmp1, val, mod_abs;
5470         u16 rx_alarm_ctrl_val;
5471         u16 lasi_ctrl_val;
5472         struct bnx2x *bp = params->bp;
5473         /* Enable PMD link, MOD_ABS_FLT, and 1G link alarm */
5474
5475         bnx2x_wait_reset_complete(bp, phy);
5476         rx_alarm_ctrl_val = (1<<2) | (1<<5) ;
5477         lasi_ctrl_val = 0x0004;
5478
5479         DP(NETIF_MSG_LINK, "Initializing BCM8727\n");
5480         /* enable LASI */
5481         bnx2x_cl45_write(bp, phy,
5482                          MDIO_PMA_DEVAD, MDIO_PMA_REG_RX_ALARM_CTRL,
5483                          rx_alarm_ctrl_val);
5484
5485         bnx2x_cl45_write(bp, phy,
5486                          MDIO_PMA_DEVAD, MDIO_PMA_REG_LASI_CTRL, lasi_ctrl_val);
5487
5488         /* Initially configure  MOD_ABS to interrupt when
5489         module is presence( bit 8) */
5490         bnx2x_cl45_read(bp, phy,
5491                         MDIO_PMA_DEVAD, MDIO_PMA_REG_PHY_IDENTIFIER, &mod_abs);
5492         /* Set EDC off by setting OPTXLOS signal input to low
5493         (bit 9).
5494         When the EDC is off it locks onto a reference clock and
5495         avoids becoming 'lost'.*/
5496         mod_abs &= ~(1<<8);
5497         if (!(phy->flags & FLAGS_NOC))
5498                 mod_abs &= ~(1<<9);
5499         bnx2x_cl45_write(bp, phy,
5500                          MDIO_PMA_DEVAD, MDIO_PMA_REG_PHY_IDENTIFIER, mod_abs);
5501
5502
5503         /* Make MOD_ABS give interrupt on change */
5504         bnx2x_cl45_read(bp, phy, MDIO_PMA_DEVAD, MDIO_PMA_REG_8727_PCS_OPT_CTRL,
5505                         &val);
5506         val |= (1<<12);
5507         if (phy->flags & FLAGS_NOC)
5508                 val |= (3<<5);
5509
5510         /**
5511          * Set 8727 GPIOs to input to allow reading from the 8727 GPIO0
5512          * status which reflect SFP+ module over-current
5513          */
5514         if (!(phy->flags & FLAGS_NOC))
5515                 val &= 0xff8f; /* Reset bits 4-6 */
5516         bnx2x_cl45_write(bp, phy,
5517                          MDIO_PMA_DEVAD, MDIO_PMA_REG_8727_PCS_OPT_CTRL, val);
5518
5519         bnx2x_8727_power_module(bp, phy, 1);
5520
5521         bnx2x_cl45_read(bp, phy,
5522                         MDIO_PMA_DEVAD, MDIO_PMA_REG_M8051_MSGOUT_REG, &tmp1);
5523
5524         bnx2x_cl45_read(bp, phy,
5525                         MDIO_PMA_DEVAD, MDIO_PMA_REG_RX_ALARM, &tmp1);
5526
5527         /* Set option 1G speed */
5528         if (phy->req_line_speed == SPEED_1000) {
5529                 DP(NETIF_MSG_LINK, "Setting 1G force\n");
5530                 bnx2x_cl45_write(bp, phy,
5531                                  MDIO_PMA_DEVAD, MDIO_PMA_REG_CTRL, 0x40);
5532                 bnx2x_cl45_write(bp, phy,
5533                                  MDIO_PMA_DEVAD, MDIO_PMA_REG_10G_CTRL2, 0xD);
5534                 bnx2x_cl45_read(bp, phy,
5535                                 MDIO_PMA_DEVAD, MDIO_PMA_REG_10G_CTRL2, &tmp1);
5536                 DP(NETIF_MSG_LINK, "1.7 = 0x%x\n", tmp1);
5537                 /**
5538                  * Power down the XAUI until link is up in case of dual-media
5539                  * and 1G
5540                  */
5541                 if (DUAL_MEDIA(params)) {
5542                         bnx2x_cl45_read(bp, phy,
5543                                         MDIO_PMA_DEVAD,
5544                                         MDIO_PMA_REG_8727_PCS_GP, &val);
5545                         val |= (3<<10);
5546                         bnx2x_cl45_write(bp, phy,
5547                                          MDIO_PMA_DEVAD,
5548                                          MDIO_PMA_REG_8727_PCS_GP, val);
5549                 }
5550         } else if ((phy->req_line_speed == SPEED_AUTO_NEG) &&
5551                    ((phy->speed_cap_mask &
5552                      PORT_HW_CFG_SPEED_CAPABILITY_D0_1G)) &&
5553                    ((phy->speed_cap_mask &
5554                       PORT_HW_CFG_SPEED_CAPABILITY_D0_10G) !=
5555                    PORT_HW_CFG_SPEED_CAPABILITY_D0_10G)) {
5556
5557                 DP(NETIF_MSG_LINK, "Setting 1G clause37\n");
5558                 bnx2x_cl45_write(bp, phy,
5559                                  MDIO_AN_DEVAD, MDIO_AN_REG_8727_MISC_CTRL, 0);
5560                 bnx2x_cl45_write(bp, phy,
5561                                  MDIO_AN_DEVAD, MDIO_AN_REG_CL37_AN, 0x1300);
5562         } else {
5563                 /**
5564                  * Since the 8727 has only single reset pin, need to set the 10G
5565                  * registers although it is default
5566                  */
5567                 bnx2x_cl45_write(bp, phy,
5568                                  MDIO_AN_DEVAD, MDIO_AN_REG_8727_MISC_CTRL,
5569                                  0x0020);
5570                 bnx2x_cl45_write(bp, phy,
5571                                  MDIO_AN_DEVAD, MDIO_AN_REG_CL37_AN, 0x0100);
5572                 bnx2x_cl45_write(bp, phy,
5573                                  MDIO_PMA_DEVAD, MDIO_PMA_REG_CTRL, 0x2040);
5574                 bnx2x_cl45_write(bp, phy,
5575                                  MDIO_PMA_DEVAD, MDIO_PMA_REG_10G_CTRL2,
5576                                  0x0008);
5577         }
5578
5579         /* Set 2-wire transfer rate of SFP+ module EEPROM
5580          * to 100Khz since some DACs(direct attached cables) do
5581          * not work at 400Khz.
5582          */
5583         bnx2x_cl45_write(bp, phy,
5584                          MDIO_PMA_DEVAD, MDIO_PMA_REG_8727_TWO_WIRE_SLAVE_ADDR,
5585                          0xa001);
5586
5587         /* Set TX PreEmphasis if needed */
5588         if ((params->feature_config_flags &
5589              FEATURE_CONFIG_OVERRIDE_PREEMPHASIS_ENABLED)) {
5590                 DP(NETIF_MSG_LINK, "Setting TX_CTRL1 0x%x, TX_CTRL2 0x%x\n",
5591                            phy->tx_preemphasis[0],
5592                            phy->tx_preemphasis[1]);
5593                 bnx2x_cl45_write(bp, phy,
5594                                  MDIO_PMA_DEVAD, MDIO_PMA_REG_8727_TX_CTRL1,
5595                                  phy->tx_preemphasis[0]);
5596
5597                 bnx2x_cl45_write(bp, phy,
5598                                  MDIO_PMA_DEVAD, MDIO_PMA_REG_8727_TX_CTRL2,
5599                                  phy->tx_preemphasis[1]);
5600         }
5601
5602         return 0;
5603 }
5604
5605 static void bnx2x_8727_handle_mod_abs(struct bnx2x_phy *phy,
5606                                       struct link_params *params)
5607 {
5608         struct bnx2x *bp = params->bp;
5609         u16 mod_abs, rx_alarm_status;
5610         u32 val = REG_RD(bp, params->shmem_base +
5611                              offsetof(struct shmem_region, dev_info.
5612                                       port_feature_config[params->port].
5613                                       config));
5614         bnx2x_cl45_read(bp, phy,
5615                       MDIO_PMA_DEVAD,
5616                       MDIO_PMA_REG_PHY_IDENTIFIER, &mod_abs);
5617         if (mod_abs & (1<<8)) {
5618
5619                 /* Module is absent */
5620                 DP(NETIF_MSG_LINK, "MOD_ABS indication "
5621                             "show module is absent\n");
5622
5623                 /* 1. Set mod_abs to detect next module
5624                 presence event
5625                    2. Set EDC off by setting OPTXLOS signal input to low
5626                         (bit 9).
5627                         When the EDC is off it locks onto a reference clock and
5628                         avoids becoming 'lost'.*/
5629                 mod_abs &= ~(1<<8);
5630                 if (!(phy->flags & FLAGS_NOC))
5631                         mod_abs &= ~(1<<9);
5632                 bnx2x_cl45_write(bp, phy,
5633                                MDIO_PMA_DEVAD,
5634                                MDIO_PMA_REG_PHY_IDENTIFIER, mod_abs);
5635
5636                 /* Clear RX alarm since it stays up as long as
5637                 the mod_abs wasn't changed */
5638                 bnx2x_cl45_read(bp, phy,
5639                               MDIO_PMA_DEVAD,
5640                               MDIO_PMA_REG_RX_ALARM, &rx_alarm_status);
5641
5642         } else {
5643                 /* Module is present */
5644                 DP(NETIF_MSG_LINK, "MOD_ABS indication "
5645                             "show module is present\n");
5646                 /* First thing, disable transmitter,
5647                 and if the module is ok, the
5648                 module_detection will enable it*/
5649
5650                 /* 1. Set mod_abs to detect next module
5651                 absent event ( bit 8)
5652                    2. Restore the default polarity of the OPRXLOS signal and
5653                 this signal will then correctly indicate the presence or
5654                 absence of the Rx signal. (bit 9) */
5655                 mod_abs |= (1<<8);
5656                 if (!(phy->flags & FLAGS_NOC))
5657                         mod_abs |= (1<<9);
5658                 bnx2x_cl45_write(bp, phy,
5659                                  MDIO_PMA_DEVAD,
5660                                  MDIO_PMA_REG_PHY_IDENTIFIER, mod_abs);
5661
5662                 /* Clear RX alarm since it stays up as long as
5663                 the mod_abs wasn't changed. This is need to be done
5664                 before calling the module detection, otherwise it will clear
5665                 the link update alarm */
5666                 bnx2x_cl45_read(bp, phy,
5667                                 MDIO_PMA_DEVAD,
5668                                 MDIO_PMA_REG_RX_ALARM, &rx_alarm_status);
5669
5670
5671                 if ((val & PORT_FEAT_CFG_OPT_MDL_ENFRCMNT_MASK) ==
5672                     PORT_FEAT_CFG_OPT_MDL_ENFRCMNT_DISABLE_TX_LASER)
5673                         bnx2x_sfp_set_transmitter(bp, phy, params->port, 0);
5674
5675                 if (bnx2x_wait_for_sfp_module_initialized(phy, params) == 0)
5676                         bnx2x_sfp_module_detection(phy, params);
5677                 else
5678                         DP(NETIF_MSG_LINK, "SFP+ module is not initialized\n");
5679         }
5680
5681         DP(NETIF_MSG_LINK, "8727 RX_ALARM_STATUS 0x%x\n",
5682                  rx_alarm_status);
5683         /* No need to check link status in case of
5684         module plugged in/out */
5685 }
5686
5687 static u8 bnx2x_8727_read_status(struct bnx2x_phy *phy,
5688                                  struct link_params *params,
5689                                  struct link_vars *vars)
5690
5691 {
5692         struct bnx2x *bp = params->bp;
5693         u8 link_up = 0;
5694         u16 link_status = 0;
5695         u16 rx_alarm_status, lasi_ctrl, val1;
5696
5697         /* If PHY is not initialized, do not check link status */
5698         bnx2x_cl45_read(bp, phy,
5699                         MDIO_PMA_DEVAD, MDIO_PMA_REG_LASI_CTRL,
5700                         &lasi_ctrl);
5701         if (!lasi_ctrl)
5702                 return 0;
5703
5704         /* Check the LASI */
5705         bnx2x_cl45_read(bp, phy,
5706                         MDIO_PMA_DEVAD, MDIO_PMA_REG_RX_ALARM,
5707                         &rx_alarm_status);
5708         vars->line_speed = 0;
5709         DP(NETIF_MSG_LINK, "8727 RX_ALARM_STATUS  0x%x\n", rx_alarm_status);
5710
5711         bnx2x_cl45_read(bp, phy,
5712                         MDIO_PMA_DEVAD, MDIO_PMA_REG_LASI_STATUS, &val1);
5713
5714         DP(NETIF_MSG_LINK, "8727 LASI status 0x%x\n", val1);
5715
5716         /* Clear MSG-OUT */
5717         bnx2x_cl45_read(bp, phy,
5718                         MDIO_PMA_DEVAD, MDIO_PMA_REG_M8051_MSGOUT_REG, &val1);
5719
5720         /**
5721          * If a module is present and there is need to check
5722          * for over current
5723          */
5724         if (!(phy->flags & FLAGS_NOC) && !(rx_alarm_status & (1<<5))) {
5725                 /* Check over-current using 8727 GPIO0 input*/
5726                 bnx2x_cl45_read(bp, phy,
5727                                 MDIO_PMA_DEVAD, MDIO_PMA_REG_8727_GPIO_CTRL,
5728                                 &val1);
5729
5730                 if ((val1 & (1<<8)) == 0) {
5731                         DP(NETIF_MSG_LINK, "8727 Power fault has been detected"
5732                                        " on port %d\n", params->port);
5733                         netdev_err(bp->dev, "Error:  Power fault on Port %d has"
5734                                             " been detected and the power to "
5735                                             "that SFP+ module has been removed"
5736                                             " to prevent failure of the card."
5737                                             " Please remove the SFP+ module and"
5738                                             " restart the system to clear this"
5739                                             " error.\n",
5740                                    params->port);
5741
5742                         /*
5743                          * Disable all RX_ALARMs except for
5744                          * mod_abs
5745                          */
5746                         bnx2x_cl45_write(bp, phy,
5747                                          MDIO_PMA_DEVAD,
5748                                          MDIO_PMA_REG_RX_ALARM_CTRL, (1<<5));
5749
5750                         bnx2x_cl45_read(bp, phy,
5751                                         MDIO_PMA_DEVAD,
5752                                         MDIO_PMA_REG_PHY_IDENTIFIER, &val1);
5753                         /* Wait for module_absent_event */
5754                         val1 |= (1<<8);
5755                         bnx2x_cl45_write(bp, phy,
5756                                          MDIO_PMA_DEVAD,
5757                                          MDIO_PMA_REG_PHY_IDENTIFIER, val1);
5758                         /* Clear RX alarm */
5759                         bnx2x_cl45_read(bp, phy,
5760                                 MDIO_PMA_DEVAD,
5761                                 MDIO_PMA_REG_RX_ALARM, &rx_alarm_status);
5762                         return 0;
5763                 }
5764         } /* Over current check */
5765
5766         /* When module absent bit is set, check module */
5767         if (rx_alarm_status & (1<<5)) {
5768                 bnx2x_8727_handle_mod_abs(phy, params);
5769                 /* Enable all mod_abs and link detection bits */
5770                 bnx2x_cl45_write(bp, phy,
5771                                  MDIO_PMA_DEVAD, MDIO_PMA_REG_RX_ALARM_CTRL,
5772                                  ((1<<5) | (1<<2)));
5773         }
5774         DP(NETIF_MSG_LINK, "Enabling 8727 TX laser if SFP is approved\n");
5775         bnx2x_8727_specific_func(phy, params, ENABLE_TX);
5776         /* If transmitter is disabled, ignore false link up indication */
5777         bnx2x_cl45_read(bp, phy,
5778                         MDIO_PMA_DEVAD, MDIO_PMA_REG_PHY_IDENTIFIER, &val1);
5779         if (val1 & (1<<15)) {
5780                 DP(NETIF_MSG_LINK, "Tx is disabled\n");
5781                 return 0;
5782         }
5783
5784         bnx2x_cl45_read(bp, phy,
5785                         MDIO_PMA_DEVAD,
5786                         MDIO_PMA_REG_8073_SPEED_LINK_STATUS, &link_status);
5787
5788         /* Bits 0..2 --> speed detected,
5789            bits 13..15--> link is down */
5790         if ((link_status & (1<<2)) && (!(link_status & (1<<15)))) {
5791                 link_up = 1;
5792                 vars->line_speed = SPEED_10000;
5793         } else if ((link_status & (1<<0)) && (!(link_status & (1<<13)))) {
5794                 link_up = 1;
5795                 vars->line_speed = SPEED_1000;
5796                 DP(NETIF_MSG_LINK, "port %x: External link up in 1G\n",
5797                            params->port);
5798         } else {
5799                 link_up = 0;
5800                 DP(NETIF_MSG_LINK, "port %x: External link is down\n",
5801                            params->port);
5802         }
5803         if (link_up)
5804                 bnx2x_ext_phy_resolve_fc(phy, params, vars);
5805
5806         if ((DUAL_MEDIA(params)) &&
5807             (phy->req_line_speed == SPEED_1000)) {
5808                 bnx2x_cl45_read(bp, phy,
5809                                 MDIO_PMA_DEVAD,
5810                                 MDIO_PMA_REG_8727_PCS_GP, &val1);
5811                 /**
5812                  * In case of dual-media board and 1G, power up the XAUI side,
5813                  * otherwise power it down. For 10G it is done automatically
5814                  */
5815                 if (link_up)
5816                         val1 &= ~(3<<10);
5817                 else
5818                         val1 |= (3<<10);
5819                 bnx2x_cl45_write(bp, phy,
5820                                  MDIO_PMA_DEVAD,
5821                                  MDIO_PMA_REG_8727_PCS_GP, val1);
5822         }
5823         return link_up;
5824 }
5825
5826 static void bnx2x_8727_link_reset(struct bnx2x_phy *phy,
5827                                   struct link_params *params)
5828 {
5829         struct bnx2x *bp = params->bp;
5830         /* Disable Transmitter */
5831         bnx2x_sfp_set_transmitter(bp, phy, params->port, 0);
5832         /* Clear LASI */
5833         bnx2x_cl45_write(bp, phy, MDIO_PMA_DEVAD, MDIO_PMA_REG_LASI_CTRL, 0);
5834
5835 }
5836
5837 /******************************************************************/
5838 /*              BCM8481/BCM84823/BCM84833 PHY SECTION             */
5839 /******************************************************************/
5840 static void bnx2x_save_848xx_spirom_version(struct bnx2x_phy *phy,
5841                                            struct link_params *params)
5842 {
5843         u16 val, fw_ver1, fw_ver2, cnt;
5844         struct bnx2x *bp = params->bp;
5845
5846         /* For the 32 bits registers in 848xx, access via MDIO2ARM interface.*/
5847         /* (1) set register 0xc200_0014(SPI_BRIDGE_CTRL_2) to 0x03000000 */
5848         bnx2x_cl45_write(bp, phy, MDIO_PMA_DEVAD, 0xA819, 0x0014);
5849         bnx2x_cl45_write(bp, phy, MDIO_PMA_DEVAD, 0xA81A, 0xc200);
5850         bnx2x_cl45_write(bp, phy, MDIO_PMA_DEVAD, 0xA81B, 0x0000);
5851         bnx2x_cl45_write(bp, phy, MDIO_PMA_DEVAD, 0xA81C, 0x0300);
5852         bnx2x_cl45_write(bp, phy, MDIO_PMA_DEVAD, 0xA817, 0x0009);
5853
5854         for (cnt = 0; cnt < 100; cnt++) {
5855                 bnx2x_cl45_read(bp, phy, MDIO_PMA_DEVAD, 0xA818, &val);
5856                 if (val & 1)
5857                         break;
5858                 udelay(5);
5859         }
5860         if (cnt == 100) {
5861                 DP(NETIF_MSG_LINK, "Unable to read 848xx phy fw version(1)\n");
5862                 bnx2x_save_spirom_version(bp, params->port, 0,
5863                                           phy->ver_addr);
5864                 return;
5865         }
5866
5867
5868         /* 2) read register 0xc200_0000 (SPI_FW_STATUS) */
5869         bnx2x_cl45_write(bp, phy, MDIO_PMA_DEVAD, 0xA819, 0x0000);
5870         bnx2x_cl45_write(bp, phy, MDIO_PMA_DEVAD, 0xA81A, 0xc200);
5871         bnx2x_cl45_write(bp, phy, MDIO_PMA_DEVAD, 0xA817, 0x000A);
5872         for (cnt = 0; cnt < 100; cnt++) {
5873                 bnx2x_cl45_read(bp, phy, MDIO_PMA_DEVAD, 0xA818, &val);
5874                 if (val & 1)
5875                         break;
5876                 udelay(5);
5877         }
5878         if (cnt == 100) {
5879                 DP(NETIF_MSG_LINK, "Unable to read 848xx phy fw version(2)\n");
5880                 bnx2x_save_spirom_version(bp, params->port, 0,
5881                                           phy->ver_addr);
5882                 return;
5883         }
5884
5885         /* lower 16 bits of the register SPI_FW_STATUS */
5886         bnx2x_cl45_read(bp, phy, MDIO_PMA_DEVAD, 0xA81B, &fw_ver1);
5887         /* upper 16 bits of register SPI_FW_STATUS */
5888         bnx2x_cl45_read(bp, phy, MDIO_PMA_DEVAD, 0xA81C, &fw_ver2);
5889
5890         bnx2x_save_spirom_version(bp, params->port, (fw_ver2<<16) | fw_ver1,
5891                                   phy->ver_addr);
5892 }
5893
5894 static void bnx2x_848xx_set_led(struct bnx2x *bp,
5895                                 struct bnx2x_phy *phy)
5896 {
5897         u16 val;
5898
5899         /* PHYC_CTL_LED_CTL */
5900         bnx2x_cl45_read(bp, phy,
5901                         MDIO_PMA_DEVAD,
5902                         MDIO_PMA_REG_8481_LINK_SIGNAL, &val);
5903         val &= 0xFE00;
5904         val |= 0x0092;
5905
5906         bnx2x_cl45_write(bp, phy,
5907                          MDIO_PMA_DEVAD,
5908                          MDIO_PMA_REG_8481_LINK_SIGNAL, val);
5909
5910         bnx2x_cl45_write(bp, phy,
5911                          MDIO_PMA_DEVAD,
5912                          MDIO_PMA_REG_8481_LED1_MASK,
5913                          0x80);
5914
5915         bnx2x_cl45_write(bp, phy,
5916                          MDIO_PMA_DEVAD,
5917                          MDIO_PMA_REG_8481_LED2_MASK,
5918                          0x18);
5919
5920         bnx2x_cl45_write(bp, phy,
5921                          MDIO_PMA_DEVAD,
5922                          MDIO_PMA_REG_8481_LED3_MASK,
5923                          0x0040);
5924
5925         /* 'Interrupt Mask' */
5926         bnx2x_cl45_write(bp, phy,
5927                          MDIO_AN_DEVAD,
5928                          0xFFFB, 0xFFFD);
5929 }
5930
5931 static u8 bnx2x_848xx_cmn_config_init(struct bnx2x_phy *phy,
5932                                       struct link_params *params,
5933                                       struct link_vars *vars)
5934 {
5935         struct bnx2x *bp = params->bp;
5936         u16 autoneg_val, an_1000_val, an_10_100_val;
5937
5938         bnx2x_bits_en(bp, NIG_REG_LATCH_BC_0 + params->port*4,
5939                       1 << NIG_LATCH_BC_ENABLE_MI_INT);
5940
5941         bnx2x_cl45_write(bp, phy,
5942                          MDIO_PMA_DEVAD, MDIO_PMA_REG_CTRL, 0x0000);
5943
5944         bnx2x_848xx_set_led(bp, phy);
5945
5946         /* set 1000 speed advertisement */
5947         bnx2x_cl45_read(bp, phy,
5948                         MDIO_AN_DEVAD, MDIO_AN_REG_8481_1000T_CTRL,
5949                         &an_1000_val);
5950
5951         bnx2x_ext_phy_set_pause(params, phy, vars);
5952         bnx2x_cl45_read(bp, phy,
5953                         MDIO_AN_DEVAD,
5954                         MDIO_AN_REG_8481_LEGACY_AN_ADV,
5955                         &an_10_100_val);
5956         bnx2x_cl45_read(bp, phy,
5957                         MDIO_AN_DEVAD, MDIO_AN_REG_8481_LEGACY_MII_CTRL,
5958                         &autoneg_val);
5959         /* Disable forced speed */
5960         autoneg_val &= ~((1<<6) | (1<<8) | (1<<9) | (1<<12) | (1<<13));
5961         an_10_100_val &= ~((1<<5) | (1<<6) | (1<<7) | (1<<8));
5962
5963         if (((phy->req_line_speed == SPEED_AUTO_NEG) &&
5964              (phy->speed_cap_mask &
5965              PORT_HW_CFG_SPEED_CAPABILITY_D0_1G)) ||
5966             (phy->req_line_speed == SPEED_1000)) {
5967                 an_1000_val |= (1<<8);
5968                 autoneg_val |= (1<<9 | 1<<12);
5969                 if (phy->req_duplex == DUPLEX_FULL)
5970                         an_1000_val |= (1<<9);
5971                 DP(NETIF_MSG_LINK, "Advertising 1G\n");
5972         } else
5973                 an_1000_val &= ~((1<<8) | (1<<9));
5974
5975         bnx2x_cl45_write(bp, phy,
5976                          MDIO_AN_DEVAD, MDIO_AN_REG_8481_1000T_CTRL,
5977                          an_1000_val);
5978
5979         /* set 10 speed advertisement */
5980         if (((phy->req_line_speed == SPEED_AUTO_NEG) &&
5981              (phy->speed_cap_mask &
5982              (PORT_HW_CFG_SPEED_CAPABILITY_D0_100M_FULL |
5983               PORT_HW_CFG_SPEED_CAPABILITY_D0_100M_HALF)))) {
5984                 an_10_100_val |= (1<<7);
5985                 /* Enable autoneg and restart autoneg for legacy speeds */
5986                 autoneg_val |= (1<<9 | 1<<12);
5987
5988                 if (phy->req_duplex == DUPLEX_FULL)
5989                         an_10_100_val |= (1<<8);
5990                 DP(NETIF_MSG_LINK, "Advertising 100M\n");
5991         }
5992         /* set 10 speed advertisement */
5993         if (((phy->req_line_speed == SPEED_AUTO_NEG) &&
5994             (phy->speed_cap_mask &
5995           (PORT_HW_CFG_SPEED_CAPABILITY_D0_10M_FULL |
5996            PORT_HW_CFG_SPEED_CAPABILITY_D0_10M_HALF)))) {
5997                 an_10_100_val |= (1<<5);
5998                 autoneg_val |= (1<<9 | 1<<12);
5999                 if (phy->req_duplex == DUPLEX_FULL)
6000                         an_10_100_val |= (1<<6);
6001                 DP(NETIF_MSG_LINK, "Advertising 10M\n");
6002         }
6003
6004         /* Only 10/100 are allowed to work in FORCE mode */
6005         if (phy->req_line_speed == SPEED_100) {
6006                 autoneg_val |= (1<<13);
6007                 /* Enabled AUTO-MDIX when autoneg is disabled */
6008                 bnx2x_cl45_write(bp, phy,
6009                                  MDIO_AN_DEVAD, MDIO_AN_REG_8481_AUX_CTRL,
6010                                  (1<<15 | 1<<9 | 7<<0));
6011                 DP(NETIF_MSG_LINK, "Setting 100M force\n");
6012         }
6013         if (phy->req_line_speed == SPEED_10) {
6014                 /* Enabled AUTO-MDIX when autoneg is disabled */
6015                 bnx2x_cl45_write(bp, phy,
6016                                  MDIO_AN_DEVAD, MDIO_AN_REG_8481_AUX_CTRL,
6017                                  (1<<15 | 1<<9 | 7<<0));
6018                 DP(NETIF_MSG_LINK, "Setting 10M force\n");
6019         }
6020
6021         bnx2x_cl45_write(bp, phy,
6022                          MDIO_AN_DEVAD, MDIO_AN_REG_8481_LEGACY_AN_ADV,
6023                          an_10_100_val);
6024
6025         if (phy->req_duplex == DUPLEX_FULL)
6026                 autoneg_val |= (1<<8);
6027
6028         bnx2x_cl45_write(bp, phy,
6029                          MDIO_AN_DEVAD,
6030                          MDIO_AN_REG_8481_LEGACY_MII_CTRL, autoneg_val);
6031
6032         if (((phy->req_line_speed == SPEED_AUTO_NEG) &&
6033             (phy->speed_cap_mask &
6034              PORT_HW_CFG_SPEED_CAPABILITY_D0_10G)) ||
6035                 (phy->req_line_speed == SPEED_10000)) {
6036                 DP(NETIF_MSG_LINK, "Advertising 10G\n");
6037                 /* Restart autoneg for 10G*/
6038
6039                 bnx2x_cl45_write(bp, phy,
6040                                  MDIO_AN_DEVAD, MDIO_AN_REG_CTRL,
6041                                  0x3200);
6042         } else if (phy->req_line_speed != SPEED_10 &&
6043                    phy->req_line_speed != SPEED_100) {
6044                 bnx2x_cl45_write(bp, phy,
6045                                  MDIO_AN_DEVAD,
6046                                  MDIO_AN_REG_8481_10GBASE_T_AN_CTRL,
6047                                  1);
6048         }
6049         /* Save spirom version */
6050         bnx2x_save_848xx_spirom_version(phy, params);
6051
6052         return 0;
6053 }
6054
6055 static u8 bnx2x_8481_config_init(struct bnx2x_phy *phy,
6056                                  struct link_params *params,
6057                                  struct link_vars *vars)
6058 {
6059         struct bnx2x *bp = params->bp;
6060         /* Restore normal power mode*/
6061         bnx2x_set_gpio(bp, MISC_REGISTERS_GPIO_2,
6062                             MISC_REGISTERS_GPIO_OUTPUT_HIGH, params->port);
6063
6064         /* HW reset */
6065         bnx2x_ext_phy_hw_reset(bp, params->port);
6066         bnx2x_wait_reset_complete(bp, phy);
6067
6068         bnx2x_cl45_write(bp, phy, MDIO_PMA_DEVAD, MDIO_PMA_REG_CTRL, 1<<15);
6069         return bnx2x_848xx_cmn_config_init(phy, params, vars);
6070 }
6071
6072 static u8 bnx2x_848x3_config_init(struct bnx2x_phy *phy,
6073                                   struct link_params *params,
6074                                   struct link_vars *vars)
6075 {
6076         struct bnx2x *bp = params->bp;
6077         u8 port, initialize = 1;
6078         u16 val;
6079         u16 temp;
6080         u32 actual_phy_selection;
6081         u8 rc = 0;
6082
6083         /* This is just for MDIO_CTL_REG_84823_MEDIA register. */
6084
6085         msleep(1);
6086         if (CHIP_IS_E2(bp))
6087                 port = BP_PATH(bp);
6088         else
6089                 port = params->port;
6090         bnx2x_set_gpio(bp, MISC_REGISTERS_GPIO_3,
6091                        MISC_REGISTERS_GPIO_OUTPUT_HIGH,
6092                        port);
6093         bnx2x_wait_reset_complete(bp, phy);
6094         /* Wait for GPHY to come out of reset */
6095         msleep(50);
6096         /* BCM84823 requires that XGXS links up first @ 10G for normal
6097         behavior */
6098         temp = vars->line_speed;
6099         vars->line_speed = SPEED_10000;
6100         bnx2x_set_autoneg(&params->phy[INT_PHY], params, vars, 0);
6101         bnx2x_program_serdes(&params->phy[INT_PHY], params, vars);
6102         vars->line_speed = temp;
6103
6104         /* Set dual-media configuration according to configuration */
6105
6106         bnx2x_cl45_read(bp, phy, MDIO_CTL_DEVAD,
6107                         MDIO_CTL_REG_84823_MEDIA, &val);
6108         val &= ~(MDIO_CTL_REG_84823_MEDIA_MAC_MASK |
6109                  MDIO_CTL_REG_84823_MEDIA_LINE_MASK |
6110                  MDIO_CTL_REG_84823_MEDIA_COPPER_CORE_DOWN |
6111                  MDIO_CTL_REG_84823_MEDIA_PRIORITY_MASK |
6112                  MDIO_CTL_REG_84823_MEDIA_FIBER_1G);
6113         val |= MDIO_CTL_REG_84823_CTRL_MAC_XFI |
6114                 MDIO_CTL_REG_84823_MEDIA_LINE_XAUI_L;
6115
6116         actual_phy_selection = bnx2x_phy_selection(params);
6117
6118         switch (actual_phy_selection) {
6119         case PORT_HW_CFG_PHY_SELECTION_HARDWARE_DEFAULT:
6120                 /* Do nothing. Essentialy this is like the priority copper */
6121                 break;
6122         case PORT_HW_CFG_PHY_SELECTION_FIRST_PHY_PRIORITY:
6123                 val |= MDIO_CTL_REG_84823_MEDIA_PRIORITY_COPPER;
6124                 break;
6125         case PORT_HW_CFG_PHY_SELECTION_SECOND_PHY_PRIORITY:
6126                 val |= MDIO_CTL_REG_84823_MEDIA_PRIORITY_FIBER;
6127                 break;
6128         case PORT_HW_CFG_PHY_SELECTION_FIRST_PHY:
6129                 /* Do nothing here. The first PHY won't be initialized at all */
6130                 break;
6131         case PORT_HW_CFG_PHY_SELECTION_SECOND_PHY:
6132                 val |= MDIO_CTL_REG_84823_MEDIA_COPPER_CORE_DOWN;
6133                 initialize = 0;
6134                 break;
6135         }
6136         if (params->phy[EXT_PHY2].req_line_speed == SPEED_1000)
6137                 val |= MDIO_CTL_REG_84823_MEDIA_FIBER_1G;
6138
6139         bnx2x_cl45_write(bp, phy, MDIO_CTL_DEVAD,
6140                          MDIO_CTL_REG_84823_MEDIA, val);
6141         DP(NETIF_MSG_LINK, "Multi_phy config = 0x%x, Media control = 0x%x\n",
6142                    params->multi_phy_config, val);
6143
6144         if (initialize)
6145                 rc = bnx2x_848xx_cmn_config_init(phy, params, vars);
6146         else
6147                 bnx2x_save_848xx_spirom_version(phy, params);
6148         return rc;
6149 }
6150
6151 static u8 bnx2x_848xx_read_status(struct bnx2x_phy *phy,
6152                                        struct link_params *params,
6153                                        struct link_vars *vars)
6154 {
6155         struct bnx2x *bp = params->bp;
6156         u16 val, val1, val2;
6157         u8 link_up = 0;
6158
6159         /* Check 10G-BaseT link status */
6160         /* Check PMD signal ok */
6161         bnx2x_cl45_read(bp, phy,
6162                         MDIO_AN_DEVAD, 0xFFFA, &val1);
6163         bnx2x_cl45_read(bp, phy,
6164                         MDIO_PMA_DEVAD, MDIO_PMA_REG_8481_PMD_SIGNAL,
6165                         &val2);
6166         DP(NETIF_MSG_LINK, "BCM848xx: PMD_SIGNAL 1.a811 = 0x%x\n", val2);
6167
6168         /* Check link 10G */
6169         if (val2 & (1<<11)) {
6170                 vars->line_speed = SPEED_10000;
6171                 link_up = 1;
6172                 bnx2x_ext_phy_10G_an_resolve(bp, phy, vars);
6173         } else { /* Check Legacy speed link */
6174                 u16 legacy_status, legacy_speed;
6175
6176                 /* Enable expansion register 0x42 (Operation mode status) */
6177                 bnx2x_cl45_write(bp, phy,
6178                                  MDIO_AN_DEVAD,
6179                                  MDIO_AN_REG_8481_EXPANSION_REG_ACCESS, 0xf42);
6180
6181                 /* Get legacy speed operation status */
6182                 bnx2x_cl45_read(bp, phy,
6183                                 MDIO_AN_DEVAD,
6184                                 MDIO_AN_REG_8481_EXPANSION_REG_RD_RW,
6185                                 &legacy_status);
6186
6187                 DP(NETIF_MSG_LINK, "Legacy speed status"
6188                              " = 0x%x\n", legacy_status);
6189                 link_up = ((legacy_status & (1<<11)) == (1<<11));
6190                 if (link_up) {
6191                         legacy_speed = (legacy_status & (3<<9));
6192                         if (legacy_speed == (0<<9))
6193                                 vars->line_speed = SPEED_10;
6194                         else if (legacy_speed == (1<<9))
6195                                 vars->line_speed = SPEED_100;
6196                         else if (legacy_speed == (2<<9))
6197                                 vars->line_speed = SPEED_1000;
6198                         else /* Should not happen */
6199                                 vars->line_speed = 0;
6200
6201                         if (legacy_status & (1<<8))
6202                                 vars->duplex = DUPLEX_FULL;
6203                         else
6204                                 vars->duplex = DUPLEX_HALF;
6205
6206                         DP(NETIF_MSG_LINK, "Link is up in %dMbps,"
6207                                    " is_duplex_full= %d\n", vars->line_speed,
6208                                    (vars->duplex == DUPLEX_FULL));
6209                         /* Check legacy speed AN resolution */
6210                         bnx2x_cl45_read(bp, phy,
6211                                         MDIO_AN_DEVAD,
6212                                         MDIO_AN_REG_8481_LEGACY_MII_STATUS,
6213                                         &val);
6214                         if (val & (1<<5))
6215                                 vars->link_status |=
6216                                         LINK_STATUS_AUTO_NEGOTIATE_COMPLETE;
6217                         bnx2x_cl45_read(bp, phy,
6218                                         MDIO_AN_DEVAD,
6219                                         MDIO_AN_REG_8481_LEGACY_AN_EXPANSION,
6220                                         &val);
6221                         if ((val & (1<<0)) == 0)
6222                                 vars->link_status |=
6223                                         LINK_STATUS_PARALLEL_DETECTION_USED;
6224                 }
6225         }
6226         if (link_up) {
6227                 DP(NETIF_MSG_LINK, "BCM84823: link speed is %d\n",
6228                            vars->line_speed);
6229                 bnx2x_ext_phy_resolve_fc(phy, params, vars);
6230         }
6231
6232         return link_up;
6233 }
6234
6235 static u8 bnx2x_848xx_format_ver(u32 raw_ver, u8 *str, u16 *len)
6236 {
6237         u8 status = 0;
6238         u32 spirom_ver;
6239         spirom_ver = ((raw_ver & 0xF80) >> 7) << 16 | (raw_ver & 0x7F);
6240         status = bnx2x_format_ver(spirom_ver, str, len);
6241         return status;
6242 }
6243
6244 static void bnx2x_8481_hw_reset(struct bnx2x_phy *phy,
6245                                 struct link_params *params)
6246 {
6247         bnx2x_set_gpio(params->bp, MISC_REGISTERS_GPIO_1,
6248                             MISC_REGISTERS_GPIO_OUTPUT_LOW, 0);
6249         bnx2x_set_gpio(params->bp, MISC_REGISTERS_GPIO_1,
6250                             MISC_REGISTERS_GPIO_OUTPUT_LOW, 1);
6251 }
6252
6253 static void bnx2x_8481_link_reset(struct bnx2x_phy *phy,
6254                                         struct link_params *params)
6255 {
6256         bnx2x_cl45_write(params->bp, phy,
6257                          MDIO_AN_DEVAD, MDIO_AN_REG_CTRL, 0x0000);
6258         bnx2x_cl45_write(params->bp, phy,
6259                          MDIO_PMA_DEVAD, MDIO_PMA_REG_CTRL, 1);
6260 }
6261
6262 static void bnx2x_848x3_link_reset(struct bnx2x_phy *phy,
6263                                    struct link_params *params)
6264 {
6265         struct bnx2x *bp = params->bp;
6266         u8 port;
6267         if (CHIP_IS_E2(bp))
6268                 port = BP_PATH(bp);
6269         else
6270                 port = params->port;
6271         bnx2x_set_gpio(bp, MISC_REGISTERS_GPIO_3,
6272                             MISC_REGISTERS_GPIO_OUTPUT_LOW,
6273                             port);
6274 }
6275
6276 static void bnx2x_848xx_set_link_led(struct bnx2x_phy *phy,
6277                                      struct link_params *params, u8 mode)
6278 {
6279         struct bnx2x *bp = params->bp;
6280         u16 val;
6281
6282         switch (mode) {
6283         case LED_MODE_OFF:
6284
6285                 DP(NETIF_MSG_LINK, "Port 0x%x: LED MODE OFF\n", params->port);
6286
6287                 if ((params->hw_led_mode << SHARED_HW_CFG_LED_MODE_SHIFT) ==
6288                     SHARED_HW_CFG_LED_EXTPHY1) {
6289
6290                         /* Set LED masks */
6291                         bnx2x_cl45_write(bp, phy,
6292                                         MDIO_PMA_DEVAD,
6293                                         MDIO_PMA_REG_8481_LED1_MASK,
6294                                         0x0);
6295
6296                         bnx2x_cl45_write(bp, phy,
6297                                         MDIO_PMA_DEVAD,
6298                                         MDIO_PMA_REG_8481_LED2_MASK,
6299                                         0x0);
6300
6301                         bnx2x_cl45_write(bp, phy,
6302                                         MDIO_PMA_DEVAD,
6303                                         MDIO_PMA_REG_8481_LED3_MASK,
6304                                         0x0);
6305
6306                         bnx2x_cl45_write(bp, phy,
6307                                         MDIO_PMA_DEVAD,
6308                                         MDIO_PMA_REG_8481_LED5_MASK,
6309                                         0x0);
6310
6311                 } else {
6312                         bnx2x_cl45_write(bp, phy,
6313                                          MDIO_PMA_DEVAD,
6314                                          MDIO_PMA_REG_8481_LED1_MASK,
6315                                          0x0);
6316                 }
6317                 break;
6318         case LED_MODE_FRONT_PANEL_OFF:
6319
6320                 DP(NETIF_MSG_LINK, "Port 0x%x: LED MODE FRONT PANEL OFF\n",
6321                    params->port);
6322
6323                 if ((params->hw_led_mode << SHARED_HW_CFG_LED_MODE_SHIFT) ==
6324                     SHARED_HW_CFG_LED_EXTPHY1) {
6325
6326                         /* Set LED masks */
6327                         bnx2x_cl45_write(bp, phy,
6328                                         MDIO_PMA_DEVAD,
6329                                         MDIO_PMA_REG_8481_LED1_MASK,
6330                                         0x0);
6331
6332                         bnx2x_cl45_write(bp, phy,
6333                                         MDIO_PMA_DEVAD,
6334                                         MDIO_PMA_REG_8481_LED2_MASK,
6335                                         0x0);
6336
6337                         bnx2x_cl45_write(bp, phy,
6338                                         MDIO_PMA_DEVAD,
6339                                         MDIO_PMA_REG_8481_LED3_MASK,
6340                                         0x0);
6341
6342                         bnx2x_cl45_write(bp, phy,
6343                                         MDIO_PMA_DEVAD,
6344                                         MDIO_PMA_REG_8481_LED5_MASK,
6345                                         0x20);
6346
6347                 } else {
6348                         bnx2x_cl45_write(bp, phy,
6349                                          MDIO_PMA_DEVAD,
6350                                          MDIO_PMA_REG_8481_LED1_MASK,
6351                                          0x0);
6352                 }
6353                 break;
6354         case LED_MODE_ON:
6355
6356                 DP(NETIF_MSG_LINK, "Port 0x%x: LED MODE ON\n", params->port);
6357
6358                 if ((params->hw_led_mode << SHARED_HW_CFG_LED_MODE_SHIFT) ==
6359                     SHARED_HW_CFG_LED_EXTPHY1) {
6360                         /* Set control reg */
6361                         bnx2x_cl45_read(bp, phy,
6362                                         MDIO_PMA_DEVAD,
6363                                         MDIO_PMA_REG_8481_LINK_SIGNAL,
6364                                         &val);
6365                         val &= 0x8000;
6366                         val |= 0x2492;
6367
6368                         bnx2x_cl45_write(bp, phy,
6369                                         MDIO_PMA_DEVAD,
6370                                         MDIO_PMA_REG_8481_LINK_SIGNAL,
6371                                         val);
6372
6373                         /* Set LED masks */
6374                         bnx2x_cl45_write(bp, phy,
6375                                         MDIO_PMA_DEVAD,
6376                                         MDIO_PMA_REG_8481_LED1_MASK,
6377                                         0x0);
6378
6379                         bnx2x_cl45_write(bp, phy,
6380                                         MDIO_PMA_DEVAD,
6381                                         MDIO_PMA_REG_8481_LED2_MASK,
6382                                         0x20);
6383
6384                         bnx2x_cl45_write(bp, phy,
6385                                         MDIO_PMA_DEVAD,
6386                                         MDIO_PMA_REG_8481_LED3_MASK,
6387                                         0x20);
6388
6389                         bnx2x_cl45_write(bp, phy,
6390                                         MDIO_PMA_DEVAD,
6391                                         MDIO_PMA_REG_8481_LED5_MASK,
6392                                         0x0);
6393                 } else {
6394                         bnx2x_cl45_write(bp, phy,
6395                                         MDIO_PMA_DEVAD,
6396                                         MDIO_PMA_REG_8481_LED1_MASK,
6397                                         0x20);
6398                 }
6399                 break;
6400
6401         case LED_MODE_OPER:
6402
6403                 DP(NETIF_MSG_LINK, "Port 0x%x: LED MODE OPER\n", params->port);
6404
6405                 if ((params->hw_led_mode << SHARED_HW_CFG_LED_MODE_SHIFT) ==
6406                     SHARED_HW_CFG_LED_EXTPHY1) {
6407
6408                         /* Set control reg */
6409                         bnx2x_cl45_read(bp, phy,
6410                                         MDIO_PMA_DEVAD,
6411                                         MDIO_PMA_REG_8481_LINK_SIGNAL,
6412                                         &val);
6413
6414                         if (!((val &
6415                               MDIO_PMA_REG_8481_LINK_SIGNAL_LED4_ENABLE_MASK)
6416                            >> MDIO_PMA_REG_8481_LINK_SIGNAL_LED4_ENABLE_SHIFT)){
6417                                 DP(NETIF_MSG_LINK, "Seting LINK_SIGNAL\n");
6418                                 bnx2x_cl45_write(bp, phy,
6419                                                  MDIO_PMA_DEVAD,
6420                                                  MDIO_PMA_REG_8481_LINK_SIGNAL,
6421                                                  0xa492);
6422                         }
6423
6424                         /* Set LED masks */
6425                         bnx2x_cl45_write(bp, phy,
6426                                         MDIO_PMA_DEVAD,
6427                                         MDIO_PMA_REG_8481_LED1_MASK,
6428                                         0x10);
6429
6430                         bnx2x_cl45_write(bp, phy,
6431                                         MDIO_PMA_DEVAD,
6432                                         MDIO_PMA_REG_8481_LED2_MASK,
6433                                         0x80);
6434
6435                         bnx2x_cl45_write(bp, phy,
6436                                         MDIO_PMA_DEVAD,
6437                                         MDIO_PMA_REG_8481_LED3_MASK,
6438                                         0x98);
6439
6440                         bnx2x_cl45_write(bp, phy,
6441                                         MDIO_PMA_DEVAD,
6442                                         MDIO_PMA_REG_8481_LED5_MASK,
6443                                         0x40);
6444
6445                 } else {
6446                         bnx2x_cl45_write(bp, phy,
6447                                          MDIO_PMA_DEVAD,
6448                                          MDIO_PMA_REG_8481_LED1_MASK,
6449                                          0x80);
6450                 }
6451                 break;
6452         }
6453 }
6454 /******************************************************************/
6455 /*                      SFX7101 PHY SECTION                       */
6456 /******************************************************************/
6457 static void bnx2x_7101_config_loopback(struct bnx2x_phy *phy,
6458                                        struct link_params *params)
6459 {
6460         struct bnx2x *bp = params->bp;
6461         /* SFX7101_XGXS_TEST1 */
6462         bnx2x_cl45_write(bp, phy,
6463                          MDIO_XS_DEVAD, MDIO_XS_SFX7101_XGXS_TEST1, 0x100);
6464 }
6465
6466 static u8 bnx2x_7101_config_init(struct bnx2x_phy *phy,
6467                                  struct link_params *params,
6468                                  struct link_vars *vars)
6469 {
6470         u16 fw_ver1, fw_ver2, val;
6471         struct bnx2x *bp = params->bp;
6472         DP(NETIF_MSG_LINK, "Setting the SFX7101 LASI indication\n");
6473
6474         /* Restore normal power mode*/
6475         bnx2x_set_gpio(bp, MISC_REGISTERS_GPIO_2,
6476                             MISC_REGISTERS_GPIO_OUTPUT_HIGH, params->port);
6477         /* HW reset */
6478         bnx2x_ext_phy_hw_reset(bp, params->port);
6479         bnx2x_wait_reset_complete(bp, phy);
6480
6481         bnx2x_cl45_write(bp, phy,
6482                          MDIO_PMA_DEVAD, MDIO_PMA_REG_LASI_CTRL, 0x1);
6483         DP(NETIF_MSG_LINK, "Setting the SFX7101 LED to blink on traffic\n");
6484         bnx2x_cl45_write(bp, phy,
6485                          MDIO_PMA_DEVAD, MDIO_PMA_REG_7107_LED_CNTL, (1<<3));
6486
6487         bnx2x_ext_phy_set_pause(params, phy, vars);
6488         /* Restart autoneg */
6489         bnx2x_cl45_read(bp, phy,
6490                         MDIO_AN_DEVAD, MDIO_AN_REG_CTRL, &val);
6491         val |= 0x200;
6492         bnx2x_cl45_write(bp, phy,
6493                          MDIO_AN_DEVAD, MDIO_AN_REG_CTRL, val);
6494
6495         /* Save spirom version */
6496         bnx2x_cl45_read(bp, phy,
6497                         MDIO_PMA_DEVAD, MDIO_PMA_REG_7101_VER1, &fw_ver1);
6498
6499         bnx2x_cl45_read(bp, phy,
6500                         MDIO_PMA_DEVAD, MDIO_PMA_REG_7101_VER2, &fw_ver2);
6501         bnx2x_save_spirom_version(bp, params->port,
6502                                   (u32)(fw_ver1<<16 | fw_ver2), phy->ver_addr);
6503         return 0;
6504 }
6505
6506 static u8 bnx2x_7101_read_status(struct bnx2x_phy *phy,
6507                                  struct link_params *params,
6508                                  struct link_vars *vars)
6509 {
6510         struct bnx2x *bp = params->bp;
6511         u8 link_up;
6512         u16 val1, val2;
6513         bnx2x_cl45_read(bp, phy,
6514                         MDIO_PMA_DEVAD, MDIO_PMA_REG_LASI_STATUS, &val2);
6515         bnx2x_cl45_read(bp, phy,
6516                         MDIO_PMA_DEVAD, MDIO_PMA_REG_LASI_STATUS, &val1);
6517         DP(NETIF_MSG_LINK, "10G-base-T LASI status 0x%x->0x%x\n",
6518                    val2, val1);
6519         bnx2x_cl45_read(bp, phy,
6520                         MDIO_PMA_DEVAD, MDIO_PMA_REG_STATUS, &val2);
6521         bnx2x_cl45_read(bp, phy,
6522                         MDIO_PMA_DEVAD, MDIO_PMA_REG_STATUS, &val1);
6523         DP(NETIF_MSG_LINK, "10G-base-T PMA status 0x%x->0x%x\n",
6524                    val2, val1);
6525         link_up = ((val1 & 4) == 4);
6526         /* if link is up
6527          * print the AN outcome of the SFX7101 PHY
6528          */
6529         if (link_up) {
6530                 bnx2x_cl45_read(bp, phy,
6531                                 MDIO_AN_DEVAD, MDIO_AN_REG_MASTER_STATUS,
6532                                 &val2);
6533                 vars->line_speed = SPEED_10000;
6534                 DP(NETIF_MSG_LINK, "SFX7101 AN status 0x%x->Master=%x\n",
6535                            val2, (val2 & (1<<14)));
6536                 bnx2x_ext_phy_10G_an_resolve(bp, phy, vars);
6537                 bnx2x_ext_phy_resolve_fc(phy, params, vars);
6538         }
6539         return link_up;
6540 }
6541
6542
6543 static u8 bnx2x_7101_format_ver(u32 spirom_ver, u8 *str, u16 *len)
6544 {
6545         if (*len < 5)
6546                 return -EINVAL;
6547         str[0] = (spirom_ver & 0xFF);
6548         str[1] = (spirom_ver & 0xFF00) >> 8;
6549         str[2] = (spirom_ver & 0xFF0000) >> 16;
6550         str[3] = (spirom_ver & 0xFF000000) >> 24;
6551         str[4] = '\0';
6552         *len -= 5;
6553         return 0;
6554 }
6555
6556 void bnx2x_sfx7101_sp_sw_reset(struct bnx2x *bp, struct bnx2x_phy *phy)
6557 {
6558         u16 val, cnt;
6559
6560         bnx2x_cl45_read(bp, phy,
6561                       MDIO_PMA_DEVAD,
6562                       MDIO_PMA_REG_7101_RESET, &val);
6563
6564         for (cnt = 0; cnt < 10; cnt++) {
6565                 msleep(50);
6566                 /* Writes a self-clearing reset */
6567                 bnx2x_cl45_write(bp, phy,
6568                                MDIO_PMA_DEVAD,
6569                                MDIO_PMA_REG_7101_RESET,
6570                                (val | (1<<15)));
6571                 /* Wait for clear */
6572                 bnx2x_cl45_read(bp, phy,
6573                               MDIO_PMA_DEVAD,
6574                               MDIO_PMA_REG_7101_RESET, &val);
6575
6576                 if ((val & (1<<15)) == 0)
6577                         break;
6578         }
6579 }
6580
6581 static void bnx2x_7101_hw_reset(struct bnx2x_phy *phy,
6582                                 struct link_params *params) {
6583         /* Low power mode is controlled by GPIO 2 */
6584         bnx2x_set_gpio(params->bp, MISC_REGISTERS_GPIO_2,
6585                             MISC_REGISTERS_GPIO_OUTPUT_LOW, params->port);
6586         /* The PHY reset is controlled by GPIO 1 */
6587         bnx2x_set_gpio(params->bp, MISC_REGISTERS_GPIO_1,
6588                             MISC_REGISTERS_GPIO_OUTPUT_LOW, params->port);
6589 }
6590
6591 static void bnx2x_7101_set_link_led(struct bnx2x_phy *phy,
6592                                     struct link_params *params, u8 mode)
6593 {
6594         u16 val = 0;
6595         struct bnx2x *bp = params->bp;
6596         switch (mode) {
6597         case LED_MODE_FRONT_PANEL_OFF:
6598         case LED_MODE_OFF:
6599                 val = 2;
6600                 break;
6601         case LED_MODE_ON:
6602                 val = 1;
6603                 break;
6604         case LED_MODE_OPER:
6605                 val = 0;
6606                 break;
6607         }
6608         bnx2x_cl45_write(bp, phy,
6609                          MDIO_PMA_DEVAD,
6610                          MDIO_PMA_REG_7107_LINK_LED_CNTL,
6611                          val);
6612 }
6613
6614 /******************************************************************/
6615 /*                      STATIC PHY DECLARATION                    */
6616 /******************************************************************/
6617
6618 static struct bnx2x_phy phy_null = {
6619         .type           = PORT_HW_CFG_XGXS_EXT_PHY_TYPE_NOT_CONN,
6620         .addr           = 0,
6621         .flags          = FLAGS_INIT_XGXS_FIRST,
6622         .def_md_devad   = 0,
6623         .reserved       = 0,
6624         .rx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff},
6625         .tx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff},
6626         .mdio_ctrl      = 0,
6627         .supported      = 0,
6628         .media_type     = ETH_PHY_NOT_PRESENT,
6629         .ver_addr       = 0,
6630         .req_flow_ctrl  = 0,
6631         .req_line_speed = 0,
6632         .speed_cap_mask = 0,
6633         .req_duplex     = 0,
6634         .rsrv           = 0,
6635         .config_init    = (config_init_t)NULL,
6636         .read_status    = (read_status_t)NULL,
6637         .link_reset     = (link_reset_t)NULL,
6638         .config_loopback = (config_loopback_t)NULL,
6639         .format_fw_ver  = (format_fw_ver_t)NULL,
6640         .hw_reset       = (hw_reset_t)NULL,
6641         .set_link_led   = (set_link_led_t)NULL,
6642         .phy_specific_func = (phy_specific_func_t)NULL
6643 };
6644
6645 static struct bnx2x_phy phy_serdes = {
6646         .type           = PORT_HW_CFG_SERDES_EXT_PHY_TYPE_DIRECT,
6647         .addr           = 0xff,
6648         .flags          = 0,
6649         .def_md_devad   = 0,
6650         .reserved       = 0,
6651         .rx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff},
6652         .tx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff},
6653         .mdio_ctrl      = 0,
6654         .supported      = (SUPPORTED_10baseT_Half |
6655                            SUPPORTED_10baseT_Full |
6656                            SUPPORTED_100baseT_Half |
6657                            SUPPORTED_100baseT_Full |
6658                            SUPPORTED_1000baseT_Full |
6659                            SUPPORTED_2500baseX_Full |
6660                            SUPPORTED_TP |
6661                            SUPPORTED_Autoneg |
6662                            SUPPORTED_Pause |
6663                            SUPPORTED_Asym_Pause),
6664         .media_type     = ETH_PHY_UNSPECIFIED,
6665         .ver_addr       = 0,
6666         .req_flow_ctrl  = 0,
6667         .req_line_speed = 0,
6668         .speed_cap_mask = 0,
6669         .req_duplex     = 0,
6670         .rsrv           = 0,
6671         .config_init    = (config_init_t)bnx2x_init_serdes,
6672         .read_status    = (read_status_t)bnx2x_link_settings_status,
6673         .link_reset     = (link_reset_t)bnx2x_int_link_reset,
6674         .config_loopback = (config_loopback_t)NULL,
6675         .format_fw_ver  = (format_fw_ver_t)NULL,
6676         .hw_reset       = (hw_reset_t)NULL,
6677         .set_link_led   = (set_link_led_t)NULL,
6678         .phy_specific_func = (phy_specific_func_t)NULL
6679 };
6680
6681 static struct bnx2x_phy phy_xgxs = {
6682         .type           = PORT_HW_CFG_XGXS_EXT_PHY_TYPE_DIRECT,
6683         .addr           = 0xff,
6684         .flags          = 0,
6685         .def_md_devad   = 0,
6686         .reserved       = 0,
6687         .rx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff},
6688         .tx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff},
6689         .mdio_ctrl      = 0,
6690         .supported      = (SUPPORTED_10baseT_Half |
6691                            SUPPORTED_10baseT_Full |
6692                            SUPPORTED_100baseT_Half |
6693                            SUPPORTED_100baseT_Full |
6694                            SUPPORTED_1000baseT_Full |
6695                            SUPPORTED_2500baseX_Full |
6696                            SUPPORTED_10000baseT_Full |
6697                            SUPPORTED_FIBRE |
6698                            SUPPORTED_Autoneg |
6699                            SUPPORTED_Pause |
6700                            SUPPORTED_Asym_Pause),
6701         .media_type     = ETH_PHY_UNSPECIFIED,
6702         .ver_addr       = 0,
6703         .req_flow_ctrl  = 0,
6704         .req_line_speed = 0,
6705         .speed_cap_mask = 0,
6706         .req_duplex     = 0,
6707         .rsrv           = 0,
6708         .config_init    = (config_init_t)bnx2x_init_xgxs,
6709         .read_status    = (read_status_t)bnx2x_link_settings_status,
6710         .link_reset     = (link_reset_t)bnx2x_int_link_reset,
6711         .config_loopback = (config_loopback_t)bnx2x_set_xgxs_loopback,
6712         .format_fw_ver  = (format_fw_ver_t)NULL,
6713         .hw_reset       = (hw_reset_t)NULL,
6714         .set_link_led   = (set_link_led_t)NULL,
6715         .phy_specific_func = (phy_specific_func_t)NULL
6716 };
6717
6718 static struct bnx2x_phy phy_7101 = {
6719         .type           = PORT_HW_CFG_XGXS_EXT_PHY_TYPE_SFX7101,
6720         .addr           = 0xff,
6721         .flags          = FLAGS_FAN_FAILURE_DET_REQ,
6722         .def_md_devad   = 0,
6723         .reserved       = 0,
6724         .rx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff},
6725         .tx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff},
6726         .mdio_ctrl      = 0,
6727         .supported      = (SUPPORTED_10000baseT_Full |
6728                            SUPPORTED_TP |
6729                            SUPPORTED_Autoneg |
6730                            SUPPORTED_Pause |
6731                            SUPPORTED_Asym_Pause),
6732         .media_type     = ETH_PHY_BASE_T,
6733         .ver_addr       = 0,
6734         .req_flow_ctrl  = 0,
6735         .req_line_speed = 0,
6736         .speed_cap_mask = 0,
6737         .req_duplex     = 0,
6738         .rsrv           = 0,
6739         .config_init    = (config_init_t)bnx2x_7101_config_init,
6740         .read_status    = (read_status_t)bnx2x_7101_read_status,
6741         .link_reset     = (link_reset_t)bnx2x_common_ext_link_reset,
6742         .config_loopback = (config_loopback_t)bnx2x_7101_config_loopback,
6743         .format_fw_ver  = (format_fw_ver_t)bnx2x_7101_format_ver,
6744         .hw_reset       = (hw_reset_t)bnx2x_7101_hw_reset,
6745         .set_link_led   = (set_link_led_t)bnx2x_7101_set_link_led,
6746         .phy_specific_func = (phy_specific_func_t)NULL
6747 };
6748 static struct bnx2x_phy phy_8073 = {
6749         .type           = PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8073,
6750         .addr           = 0xff,
6751         .flags          = FLAGS_HW_LOCK_REQUIRED,
6752         .def_md_devad   = 0,
6753         .reserved       = 0,
6754         .rx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff},
6755         .tx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff},
6756         .mdio_ctrl      = 0,
6757         .supported      = (SUPPORTED_10000baseT_Full |
6758                            SUPPORTED_2500baseX_Full |
6759                            SUPPORTED_1000baseT_Full |
6760                            SUPPORTED_FIBRE |
6761                            SUPPORTED_Autoneg |
6762                            SUPPORTED_Pause |
6763                            SUPPORTED_Asym_Pause),
6764         .media_type     = ETH_PHY_UNSPECIFIED,
6765         .ver_addr       = 0,
6766         .req_flow_ctrl  = 0,
6767         .req_line_speed = 0,
6768         .speed_cap_mask = 0,
6769         .req_duplex     = 0,
6770         .rsrv           = 0,
6771         .config_init    = (config_init_t)bnx2x_8073_config_init,
6772         .read_status    = (read_status_t)bnx2x_8073_read_status,
6773         .link_reset     = (link_reset_t)bnx2x_8073_link_reset,
6774         .config_loopback = (config_loopback_t)NULL,
6775         .format_fw_ver  = (format_fw_ver_t)bnx2x_format_ver,
6776         .hw_reset       = (hw_reset_t)NULL,
6777         .set_link_led   = (set_link_led_t)NULL,
6778         .phy_specific_func = (phy_specific_func_t)NULL
6779 };
6780 static struct bnx2x_phy phy_8705 = {
6781         .type           = PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8705,
6782         .addr           = 0xff,
6783         .flags          = FLAGS_INIT_XGXS_FIRST,
6784         .def_md_devad   = 0,
6785         .reserved       = 0,
6786         .rx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff},
6787         .tx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff},
6788         .mdio_ctrl      = 0,
6789         .supported      = (SUPPORTED_10000baseT_Full |
6790                            SUPPORTED_FIBRE |
6791                            SUPPORTED_Pause |
6792                            SUPPORTED_Asym_Pause),
6793         .media_type     = ETH_PHY_XFP_FIBER,
6794         .ver_addr       = 0,
6795         .req_flow_ctrl  = 0,
6796         .req_line_speed = 0,
6797         .speed_cap_mask = 0,
6798         .req_duplex     = 0,
6799         .rsrv           = 0,
6800         .config_init    = (config_init_t)bnx2x_8705_config_init,
6801         .read_status    = (read_status_t)bnx2x_8705_read_status,
6802         .link_reset     = (link_reset_t)bnx2x_common_ext_link_reset,
6803         .config_loopback = (config_loopback_t)NULL,
6804         .format_fw_ver  = (format_fw_ver_t)bnx2x_null_format_ver,
6805         .hw_reset       = (hw_reset_t)NULL,
6806         .set_link_led   = (set_link_led_t)NULL,
6807         .phy_specific_func = (phy_specific_func_t)NULL
6808 };
6809 static struct bnx2x_phy phy_8706 = {
6810         .type           = PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8706,
6811         .addr           = 0xff,
6812         .flags          = FLAGS_INIT_XGXS_FIRST,
6813         .def_md_devad   = 0,
6814         .reserved       = 0,
6815         .rx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff},
6816         .tx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff},
6817         .mdio_ctrl      = 0,
6818         .supported      = (SUPPORTED_10000baseT_Full |
6819                            SUPPORTED_1000baseT_Full |
6820                            SUPPORTED_FIBRE |
6821                            SUPPORTED_Pause |
6822                            SUPPORTED_Asym_Pause),
6823         .media_type     = ETH_PHY_SFP_FIBER,
6824         .ver_addr       = 0,
6825         .req_flow_ctrl  = 0,
6826         .req_line_speed = 0,
6827         .speed_cap_mask = 0,
6828         .req_duplex     = 0,
6829         .rsrv           = 0,
6830         .config_init    = (config_init_t)bnx2x_8706_config_init,
6831         .read_status    = (read_status_t)bnx2x_8706_read_status,
6832         .link_reset     = (link_reset_t)bnx2x_common_ext_link_reset,
6833         .config_loopback = (config_loopback_t)NULL,
6834         .format_fw_ver  = (format_fw_ver_t)bnx2x_format_ver,
6835         .hw_reset       = (hw_reset_t)NULL,
6836         .set_link_led   = (set_link_led_t)NULL,
6837         .phy_specific_func = (phy_specific_func_t)NULL
6838 };
6839
6840 static struct bnx2x_phy phy_8726 = {
6841         .type           = PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8726,
6842         .addr           = 0xff,
6843         .flags          = (FLAGS_HW_LOCK_REQUIRED |
6844                            FLAGS_INIT_XGXS_FIRST),
6845         .def_md_devad   = 0,
6846         .reserved       = 0,
6847         .rx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff},
6848         .tx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff},
6849         .mdio_ctrl      = 0,
6850         .supported      = (SUPPORTED_10000baseT_Full |
6851                            SUPPORTED_1000baseT_Full |
6852                            SUPPORTED_Autoneg |
6853                            SUPPORTED_FIBRE |
6854                            SUPPORTED_Pause |
6855                            SUPPORTED_Asym_Pause),
6856         .media_type     = ETH_PHY_SFP_FIBER,
6857         .ver_addr       = 0,
6858         .req_flow_ctrl  = 0,
6859         .req_line_speed = 0,
6860         .speed_cap_mask = 0,
6861         .req_duplex     = 0,
6862         .rsrv           = 0,
6863         .config_init    = (config_init_t)bnx2x_8726_config_init,
6864         .read_status    = (read_status_t)bnx2x_8726_read_status,
6865         .link_reset     = (link_reset_t)bnx2x_8726_link_reset,
6866         .config_loopback = (config_loopback_t)bnx2x_8726_config_loopback,
6867         .format_fw_ver  = (format_fw_ver_t)bnx2x_format_ver,
6868         .hw_reset       = (hw_reset_t)NULL,
6869         .set_link_led   = (set_link_led_t)NULL,
6870         .phy_specific_func = (phy_specific_func_t)NULL
6871 };
6872
6873 static struct bnx2x_phy phy_8727 = {
6874         .type           = PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8727,
6875         .addr           = 0xff,
6876         .flags          = FLAGS_FAN_FAILURE_DET_REQ,
6877         .def_md_devad   = 0,
6878         .reserved       = 0,
6879         .rx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff},
6880         .tx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff},
6881         .mdio_ctrl      = 0,
6882         .supported      = (SUPPORTED_10000baseT_Full |
6883                            SUPPORTED_1000baseT_Full |
6884                            SUPPORTED_FIBRE |
6885                            SUPPORTED_Pause |
6886                            SUPPORTED_Asym_Pause),
6887         .media_type     = ETH_PHY_SFP_FIBER,
6888         .ver_addr       = 0,
6889         .req_flow_ctrl  = 0,
6890         .req_line_speed = 0,
6891         .speed_cap_mask = 0,
6892         .req_duplex     = 0,
6893         .rsrv           = 0,
6894         .config_init    = (config_init_t)bnx2x_8727_config_init,
6895         .read_status    = (read_status_t)bnx2x_8727_read_status,
6896         .link_reset     = (link_reset_t)bnx2x_8727_link_reset,
6897         .config_loopback = (config_loopback_t)NULL,
6898         .format_fw_ver  = (format_fw_ver_t)bnx2x_format_ver,
6899         .hw_reset       = (hw_reset_t)bnx2x_8727_hw_reset,
6900         .set_link_led   = (set_link_led_t)bnx2x_8727_set_link_led,
6901         .phy_specific_func = (phy_specific_func_t)bnx2x_8727_specific_func
6902 };
6903 static struct bnx2x_phy phy_8481 = {
6904         .type           = PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8481,
6905         .addr           = 0xff,
6906         .flags          = FLAGS_FAN_FAILURE_DET_REQ |
6907                           FLAGS_REARM_LATCH_SIGNAL,
6908         .def_md_devad   = 0,
6909         .reserved       = 0,
6910         .rx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff},
6911         .tx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff},
6912         .mdio_ctrl      = 0,
6913         .supported      = (SUPPORTED_10baseT_Half |
6914                            SUPPORTED_10baseT_Full |
6915                            SUPPORTED_100baseT_Half |
6916                            SUPPORTED_100baseT_Full |
6917                            SUPPORTED_1000baseT_Full |
6918                            SUPPORTED_10000baseT_Full |
6919                            SUPPORTED_TP |
6920                            SUPPORTED_Autoneg |
6921                            SUPPORTED_Pause |
6922                            SUPPORTED_Asym_Pause),
6923         .media_type     = ETH_PHY_BASE_T,
6924         .ver_addr       = 0,
6925         .req_flow_ctrl  = 0,
6926         .req_line_speed = 0,
6927         .speed_cap_mask = 0,
6928         .req_duplex     = 0,
6929         .rsrv           = 0,
6930         .config_init    = (config_init_t)bnx2x_8481_config_init,
6931         .read_status    = (read_status_t)bnx2x_848xx_read_status,
6932         .link_reset     = (link_reset_t)bnx2x_8481_link_reset,
6933         .config_loopback = (config_loopback_t)NULL,
6934         .format_fw_ver  = (format_fw_ver_t)bnx2x_848xx_format_ver,
6935         .hw_reset       = (hw_reset_t)bnx2x_8481_hw_reset,
6936         .set_link_led   = (set_link_led_t)bnx2x_848xx_set_link_led,
6937         .phy_specific_func = (phy_specific_func_t)NULL
6938 };
6939
6940 static struct bnx2x_phy phy_84823 = {
6941         .type           = PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM84823,
6942         .addr           = 0xff,
6943         .flags          = FLAGS_FAN_FAILURE_DET_REQ |
6944                           FLAGS_REARM_LATCH_SIGNAL,
6945         .def_md_devad   = 0,
6946         .reserved       = 0,
6947         .rx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff},
6948         .tx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff},
6949         .mdio_ctrl      = 0,
6950         .supported      = (SUPPORTED_10baseT_Half |
6951                            SUPPORTED_10baseT_Full |
6952                            SUPPORTED_100baseT_Half |
6953                            SUPPORTED_100baseT_Full |
6954                            SUPPORTED_1000baseT_Full |
6955                            SUPPORTED_10000baseT_Full |
6956                            SUPPORTED_TP |
6957                            SUPPORTED_Autoneg |
6958                            SUPPORTED_Pause |
6959                            SUPPORTED_Asym_Pause),
6960         .media_type     = ETH_PHY_BASE_T,
6961         .ver_addr       = 0,
6962         .req_flow_ctrl  = 0,
6963         .req_line_speed = 0,
6964         .speed_cap_mask = 0,
6965         .req_duplex     = 0,
6966         .rsrv           = 0,
6967         .config_init    = (config_init_t)bnx2x_848x3_config_init,
6968         .read_status    = (read_status_t)bnx2x_848xx_read_status,
6969         .link_reset     = (link_reset_t)bnx2x_848x3_link_reset,
6970         .config_loopback = (config_loopback_t)NULL,
6971         .format_fw_ver  = (format_fw_ver_t)bnx2x_848xx_format_ver,
6972         .hw_reset       = (hw_reset_t)NULL,
6973         .set_link_led   = (set_link_led_t)bnx2x_848xx_set_link_led,
6974         .phy_specific_func = (phy_specific_func_t)NULL
6975 };
6976
6977 /*****************************************************************/
6978 /*                                                               */
6979 /* Populate the phy according. Main function: bnx2x_populate_phy   */
6980 /*                                                               */
6981 /*****************************************************************/
6982
6983 static void bnx2x_populate_preemphasis(struct bnx2x *bp, u32 shmem_base,
6984                                      struct bnx2x_phy *phy, u8 port,
6985                                      u8 phy_index)
6986 {
6987         /* Get the 4 lanes xgxs config rx and tx */
6988         u32 rx = 0, tx = 0, i;
6989         for (i = 0; i < 2; i++) {
6990                 /**
6991                  * INT_PHY and EXT_PHY1 share the same value location in the
6992                  * shmem. When num_phys is greater than 1, than this value
6993                  * applies only to EXT_PHY1
6994                  */
6995                 if (phy_index == INT_PHY || phy_index == EXT_PHY1) {
6996                         rx = REG_RD(bp, shmem_base +
6997                                     offsetof(struct shmem_region,
6998                            dev_info.port_hw_config[port].xgxs_config_rx[i<<1]));
6999
7000                         tx = REG_RD(bp, shmem_base +
7001                                     offsetof(struct shmem_region,
7002                            dev_info.port_hw_config[port].xgxs_config_tx[i<<1]));
7003                 } else {
7004                         rx = REG_RD(bp, shmem_base +
7005                                     offsetof(struct shmem_region,
7006                           dev_info.port_hw_config[port].xgxs_config2_rx[i<<1]));
7007
7008                         tx = REG_RD(bp, shmem_base +
7009                                     offsetof(struct shmem_region,
7010                           dev_info.port_hw_config[port].xgxs_config2_rx[i<<1]));
7011                 }
7012
7013                 phy->rx_preemphasis[i << 1] = ((rx>>16) & 0xffff);
7014                 phy->rx_preemphasis[(i << 1) + 1] = (rx & 0xffff);
7015
7016                 phy->tx_preemphasis[i << 1] = ((tx>>16) & 0xffff);
7017                 phy->tx_preemphasis[(i << 1) + 1] = (tx & 0xffff);
7018         }
7019 }
7020
7021 static u32 bnx2x_get_ext_phy_config(struct bnx2x *bp, u32 shmem_base,
7022                                     u8 phy_index, u8 port)
7023 {
7024         u32 ext_phy_config = 0;
7025         switch (phy_index) {
7026         case EXT_PHY1:
7027                 ext_phy_config = REG_RD(bp, shmem_base +
7028                                               offsetof(struct shmem_region,
7029                         dev_info.port_hw_config[port].external_phy_config));
7030                 break;
7031         case EXT_PHY2:
7032                 ext_phy_config = REG_RD(bp, shmem_base +
7033                                               offsetof(struct shmem_region,
7034                         dev_info.port_hw_config[port].external_phy_config2));
7035                 break;
7036         default:
7037                 DP(NETIF_MSG_LINK, "Invalid phy_index %d\n", phy_index);
7038                 return -EINVAL;
7039         }
7040
7041         return ext_phy_config;
7042 }
7043 static u8 bnx2x_populate_int_phy(struct bnx2x *bp, u32 shmem_base, u8 port,
7044                                  struct bnx2x_phy *phy)
7045 {
7046         u32 phy_addr;
7047         u32 chip_id;
7048         u32 switch_cfg = (REG_RD(bp, shmem_base +
7049                                        offsetof(struct shmem_region,
7050                         dev_info.port_feature_config[port].link_config)) &
7051                           PORT_FEATURE_CONNECTED_SWITCH_MASK);
7052         chip_id = REG_RD(bp, MISC_REG_CHIP_NUM) << 16;
7053         switch (switch_cfg) {
7054         case SWITCH_CFG_1G:
7055                 phy_addr = REG_RD(bp,
7056                                         NIG_REG_SERDES0_CTRL_PHY_ADDR +
7057                                         port * 0x10);
7058                 *phy = phy_serdes;
7059                 break;
7060         case SWITCH_CFG_10G:
7061                 phy_addr = REG_RD(bp,
7062                                         NIG_REG_XGXS0_CTRL_PHY_ADDR +
7063                                         port * 0x18);
7064                 *phy = phy_xgxs;
7065                 break;
7066         default:
7067                 DP(NETIF_MSG_LINK, "Invalid switch_cfg\n");
7068                 return -EINVAL;
7069         }
7070         phy->addr = (u8)phy_addr;
7071         phy->mdio_ctrl = bnx2x_get_emac_base(bp,
7072                                             SHARED_HW_CFG_MDC_MDIO_ACCESS1_BOTH,
7073                                             port);
7074         if (CHIP_IS_E2(bp))
7075                 phy->def_md_devad = E2_DEFAULT_PHY_DEV_ADDR;
7076         else
7077                 phy->def_md_devad = DEFAULT_PHY_DEV_ADDR;
7078
7079         DP(NETIF_MSG_LINK, "Internal phy port=%d, addr=0x%x, mdio_ctl=0x%x\n",
7080                    port, phy->addr, phy->mdio_ctrl);
7081
7082         bnx2x_populate_preemphasis(bp, shmem_base, phy, port, INT_PHY);
7083         return 0;
7084 }
7085
7086 static u8 bnx2x_populate_ext_phy(struct bnx2x *bp,
7087                                  u8 phy_index,
7088                                  u32 shmem_base,
7089                                  u32 shmem2_base,
7090                                  u8 port,
7091                                  struct bnx2x_phy *phy)
7092 {
7093         u32 ext_phy_config, phy_type, config2;
7094         u32 mdc_mdio_access = SHARED_HW_CFG_MDC_MDIO_ACCESS1_BOTH;
7095         ext_phy_config = bnx2x_get_ext_phy_config(bp, shmem_base,
7096                                                   phy_index, port);
7097         phy_type = XGXS_EXT_PHY_TYPE(ext_phy_config);
7098         /* Select the phy type */
7099         switch (phy_type) {
7100         case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8073:
7101                 mdc_mdio_access = SHARED_HW_CFG_MDC_MDIO_ACCESS1_SWAPPED;
7102                 *phy = phy_8073;
7103                 break;
7104         case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8705:
7105                 *phy = phy_8705;
7106                 break;
7107         case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8706:
7108                 *phy = phy_8706;
7109                 break;
7110         case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8726:
7111                 mdc_mdio_access = SHARED_HW_CFG_MDC_MDIO_ACCESS1_EMAC1;
7112                 *phy = phy_8726;
7113                 break;
7114         case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8727_NOC:
7115                 /* BCM8727_NOC => BCM8727 no over current */
7116                 mdc_mdio_access = SHARED_HW_CFG_MDC_MDIO_ACCESS1_EMAC1;
7117                 *phy = phy_8727;
7118                 phy->flags |= FLAGS_NOC;
7119                 break;
7120         case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8727:
7121                 mdc_mdio_access = SHARED_HW_CFG_MDC_MDIO_ACCESS1_EMAC1;
7122                 *phy = phy_8727;
7123                 break;
7124         case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8481:
7125                 *phy = phy_8481;
7126                 break;
7127         case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM84823:
7128                 *phy = phy_84823;
7129                 break;
7130         case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_SFX7101:
7131                 *phy = phy_7101;
7132                 break;
7133         case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_FAILURE:
7134                 *phy = phy_null;
7135                 return -EINVAL;
7136         default:
7137                 *phy = phy_null;
7138                 return 0;
7139         }
7140
7141         phy->addr = XGXS_EXT_PHY_ADDR(ext_phy_config);
7142         bnx2x_populate_preemphasis(bp, shmem_base, phy, port, phy_index);
7143
7144         /**
7145         * The shmem address of the phy version is located on different
7146         * structures. In case this structure is too old, do not set
7147         * the address
7148         */
7149         config2 = REG_RD(bp, shmem_base + offsetof(struct shmem_region,
7150                                         dev_info.shared_hw_config.config2));
7151         if (phy_index == EXT_PHY1) {
7152                 phy->ver_addr = shmem_base + offsetof(struct shmem_region,
7153                                 port_mb[port].ext_phy_fw_version);
7154
7155         /* Check specific mdc mdio settings */
7156         if (config2 & SHARED_HW_CFG_MDC_MDIO_ACCESS1_MASK)
7157                 mdc_mdio_access = config2 &
7158                 SHARED_HW_CFG_MDC_MDIO_ACCESS1_MASK;
7159         } else {
7160                 u32 size = REG_RD(bp, shmem2_base);
7161
7162                 if (size >
7163                     offsetof(struct shmem2_region, ext_phy_fw_version2)) {
7164                         phy->ver_addr = shmem2_base +
7165                             offsetof(struct shmem2_region,
7166                                      ext_phy_fw_version2[port]);
7167                 }
7168                 /* Check specific mdc mdio settings */
7169                 if (config2 & SHARED_HW_CFG_MDC_MDIO_ACCESS2_MASK)
7170                         mdc_mdio_access = (config2 &
7171                         SHARED_HW_CFG_MDC_MDIO_ACCESS2_MASK) >>
7172                         (SHARED_HW_CFG_MDC_MDIO_ACCESS2_SHIFT -
7173                          SHARED_HW_CFG_MDC_MDIO_ACCESS1_SHIFT);
7174         }
7175         phy->mdio_ctrl = bnx2x_get_emac_base(bp, mdc_mdio_access, port);
7176
7177         /**
7178          * In case mdc/mdio_access of the external phy is different than the
7179          * mdc/mdio access of the XGXS, a HW lock must be taken in each access
7180          * to prevent one port interfere with another port's CL45 operations.
7181          */
7182         if (mdc_mdio_access != SHARED_HW_CFG_MDC_MDIO_ACCESS1_BOTH)
7183                 phy->flags |= FLAGS_HW_LOCK_REQUIRED;
7184         DP(NETIF_MSG_LINK, "phy_type 0x%x port %d found in index %d\n",
7185                    phy_type, port, phy_index);
7186         DP(NETIF_MSG_LINK, "             addr=0x%x, mdio_ctl=0x%x\n",
7187                    phy->addr, phy->mdio_ctrl);
7188         return 0;
7189 }
7190
7191 static u8 bnx2x_populate_phy(struct bnx2x *bp, u8 phy_index, u32 shmem_base,
7192                              u32 shmem2_base, u8 port, struct bnx2x_phy *phy)
7193 {
7194         u8 status = 0;
7195         phy->type = PORT_HW_CFG_XGXS_EXT_PHY_TYPE_NOT_CONN;
7196         if (phy_index == INT_PHY)
7197                 return bnx2x_populate_int_phy(bp, shmem_base, port, phy);
7198         status = bnx2x_populate_ext_phy(bp, phy_index, shmem_base, shmem2_base,
7199                                         port, phy);
7200         return status;
7201 }
7202
7203 static void bnx2x_phy_def_cfg(struct link_params *params,
7204                               struct bnx2x_phy *phy,
7205                               u8 phy_index)
7206 {
7207         struct bnx2x *bp = params->bp;
7208         u32 link_config;
7209         /* Populate the default phy configuration for MF mode */
7210         if (phy_index == EXT_PHY2) {
7211                 link_config = REG_RD(bp, params->shmem_base +
7212                                          offsetof(struct shmem_region, dev_info.
7213                         port_feature_config[params->port].link_config2));
7214                 phy->speed_cap_mask = REG_RD(bp, params->shmem_base +
7215                                         offsetof(struct shmem_region, dev_info.
7216                         port_hw_config[params->port].speed_capability_mask2));
7217         } else {
7218                 link_config = REG_RD(bp, params->shmem_base +
7219                                 offsetof(struct shmem_region, dev_info.
7220                                 port_feature_config[params->port].link_config));
7221                 phy->speed_cap_mask = REG_RD(bp, params->shmem_base +
7222                                 offsetof(struct shmem_region, dev_info.
7223                            port_hw_config[params->port].speed_capability_mask));
7224         }
7225         DP(NETIF_MSG_LINK, "Default config phy idx %x cfg 0x%x speed_cap_mask"
7226                        " 0x%x\n", phy_index, link_config, phy->speed_cap_mask);
7227
7228         phy->req_duplex = DUPLEX_FULL;
7229         switch (link_config  & PORT_FEATURE_LINK_SPEED_MASK) {
7230         case PORT_FEATURE_LINK_SPEED_10M_HALF:
7231                 phy->req_duplex = DUPLEX_HALF;
7232         case PORT_FEATURE_LINK_SPEED_10M_FULL:
7233                 phy->req_line_speed = SPEED_10;
7234                 break;
7235         case PORT_FEATURE_LINK_SPEED_100M_HALF:
7236                 phy->req_duplex = DUPLEX_HALF;
7237         case PORT_FEATURE_LINK_SPEED_100M_FULL:
7238                 phy->req_line_speed = SPEED_100;
7239                 break;
7240         case PORT_FEATURE_LINK_SPEED_1G:
7241                 phy->req_line_speed = SPEED_1000;
7242                 break;
7243         case PORT_FEATURE_LINK_SPEED_2_5G:
7244                 phy->req_line_speed = SPEED_2500;
7245                 break;
7246         case PORT_FEATURE_LINK_SPEED_10G_CX4:
7247                 phy->req_line_speed = SPEED_10000;
7248                 break;
7249         default:
7250                 phy->req_line_speed = SPEED_AUTO_NEG;
7251                 break;
7252         }
7253
7254         switch (link_config  & PORT_FEATURE_FLOW_CONTROL_MASK) {
7255         case PORT_FEATURE_FLOW_CONTROL_AUTO:
7256                 phy->req_flow_ctrl = BNX2X_FLOW_CTRL_AUTO;
7257                 break;
7258         case PORT_FEATURE_FLOW_CONTROL_TX:
7259                 phy->req_flow_ctrl = BNX2X_FLOW_CTRL_TX;
7260                 break;
7261         case PORT_FEATURE_FLOW_CONTROL_RX:
7262                 phy->req_flow_ctrl = BNX2X_FLOW_CTRL_RX;
7263                 break;
7264         case PORT_FEATURE_FLOW_CONTROL_BOTH:
7265                 phy->req_flow_ctrl = BNX2X_FLOW_CTRL_BOTH;
7266                 break;
7267         default:
7268                 phy->req_flow_ctrl = BNX2X_FLOW_CTRL_NONE;
7269                 break;
7270         }
7271 }
7272
7273 u32 bnx2x_phy_selection(struct link_params *params)
7274 {
7275         u32 phy_config_swapped, prio_cfg;
7276         u32 return_cfg = PORT_HW_CFG_PHY_SELECTION_HARDWARE_DEFAULT;
7277
7278         phy_config_swapped = params->multi_phy_config &
7279                 PORT_HW_CFG_PHY_SWAPPED_ENABLED;
7280
7281         prio_cfg = params->multi_phy_config &
7282                         PORT_HW_CFG_PHY_SELECTION_MASK;
7283
7284         if (phy_config_swapped) {
7285                 switch (prio_cfg) {
7286                 case PORT_HW_CFG_PHY_SELECTION_FIRST_PHY_PRIORITY:
7287                      return_cfg = PORT_HW_CFG_PHY_SELECTION_SECOND_PHY_PRIORITY;
7288                      break;
7289                 case PORT_HW_CFG_PHY_SELECTION_SECOND_PHY_PRIORITY:
7290                      return_cfg = PORT_HW_CFG_PHY_SELECTION_FIRST_PHY_PRIORITY;
7291                      break;
7292                 case PORT_HW_CFG_PHY_SELECTION_SECOND_PHY:
7293                      return_cfg = PORT_HW_CFG_PHY_SELECTION_FIRST_PHY;
7294                      break;
7295                 case PORT_HW_CFG_PHY_SELECTION_FIRST_PHY:
7296                      return_cfg = PORT_HW_CFG_PHY_SELECTION_SECOND_PHY;
7297                      break;
7298                 }
7299         } else
7300                 return_cfg = prio_cfg;
7301
7302         return return_cfg;
7303 }
7304
7305
7306 u8 bnx2x_phy_probe(struct link_params *params)
7307 {
7308         u8 phy_index, actual_phy_idx, link_cfg_idx;
7309         u32 phy_config_swapped;
7310         struct bnx2x *bp = params->bp;
7311         struct bnx2x_phy *phy;
7312         params->num_phys = 0;
7313         DP(NETIF_MSG_LINK, "Begin phy probe\n");
7314         phy_config_swapped = params->multi_phy_config &
7315                 PORT_HW_CFG_PHY_SWAPPED_ENABLED;
7316
7317         for (phy_index = INT_PHY; phy_index < MAX_PHYS;
7318               phy_index++) {
7319                 link_cfg_idx = LINK_CONFIG_IDX(phy_index);
7320                 actual_phy_idx = phy_index;
7321                 if (phy_config_swapped) {
7322                         if (phy_index == EXT_PHY1)
7323                                 actual_phy_idx = EXT_PHY2;
7324                         else if (phy_index == EXT_PHY2)
7325                                 actual_phy_idx = EXT_PHY1;
7326                 }
7327                 DP(NETIF_MSG_LINK, "phy_config_swapped %x, phy_index %x,"
7328                                " actual_phy_idx %x\n", phy_config_swapped,
7329                            phy_index, actual_phy_idx);
7330                 phy = &params->phy[actual_phy_idx];
7331                 if (bnx2x_populate_phy(bp, phy_index, params->shmem_base,
7332                                        params->shmem2_base, params->port,
7333                                        phy) != 0) {
7334                         params->num_phys = 0;
7335                         DP(NETIF_MSG_LINK, "phy probe failed in phy index %d\n",
7336                                    phy_index);
7337                         for (phy_index = INT_PHY;
7338                               phy_index < MAX_PHYS;
7339                               phy_index++)
7340                                 *phy = phy_null;
7341                         return -EINVAL;
7342                 }
7343                 if (phy->type == PORT_HW_CFG_XGXS_EXT_PHY_TYPE_NOT_CONN)
7344                         break;
7345
7346                 bnx2x_phy_def_cfg(params, phy, phy_index);
7347                 params->num_phys++;
7348         }
7349
7350         DP(NETIF_MSG_LINK, "End phy probe. #phys found %x\n", params->num_phys);
7351         return 0;
7352 }
7353
7354 static void set_phy_vars(struct link_params *params)
7355 {
7356         struct bnx2x *bp = params->bp;
7357         u8 actual_phy_idx, phy_index, link_cfg_idx;
7358         u8 phy_config_swapped = params->multi_phy_config &
7359                         PORT_HW_CFG_PHY_SWAPPED_ENABLED;
7360         for (phy_index = INT_PHY; phy_index < params->num_phys;
7361               phy_index++) {
7362                 link_cfg_idx = LINK_CONFIG_IDX(phy_index);
7363                 actual_phy_idx = phy_index;
7364                 if (phy_config_swapped) {
7365                         if (phy_index == EXT_PHY1)
7366                                 actual_phy_idx = EXT_PHY2;
7367                         else if (phy_index == EXT_PHY2)
7368                                 actual_phy_idx = EXT_PHY1;
7369                 }
7370                 params->phy[actual_phy_idx].req_flow_ctrl  =
7371                         params->req_flow_ctrl[link_cfg_idx];
7372
7373                 params->phy[actual_phy_idx].req_line_speed =
7374                         params->req_line_speed[link_cfg_idx];
7375
7376                 params->phy[actual_phy_idx].speed_cap_mask =
7377                         params->speed_cap_mask[link_cfg_idx];
7378
7379                 params->phy[actual_phy_idx].req_duplex =
7380                         params->req_duplex[link_cfg_idx];
7381
7382                 DP(NETIF_MSG_LINK, "req_flow_ctrl %x, req_line_speed %x,"
7383                            " speed_cap_mask %x\n",
7384                            params->phy[actual_phy_idx].req_flow_ctrl,
7385                            params->phy[actual_phy_idx].req_line_speed,
7386                            params->phy[actual_phy_idx].speed_cap_mask);
7387         }
7388 }
7389
7390 u8 bnx2x_phy_init(struct link_params *params, struct link_vars *vars)
7391 {
7392         struct bnx2x *bp = params->bp;
7393         DP(NETIF_MSG_LINK, "Phy Initialization started\n");
7394         DP(NETIF_MSG_LINK, "(1) req_speed %d, req_flowctrl %d\n",
7395                    params->req_line_speed[0], params->req_flow_ctrl[0]);
7396         DP(NETIF_MSG_LINK, "(2) req_speed %d, req_flowctrl %d\n",
7397                    params->req_line_speed[1], params->req_flow_ctrl[1]);
7398         vars->link_status = 0;
7399         vars->phy_link_up = 0;
7400         vars->link_up = 0;
7401         vars->line_speed = 0;
7402         vars->duplex = DUPLEX_FULL;
7403         vars->flow_ctrl = BNX2X_FLOW_CTRL_NONE;
7404         vars->mac_type = MAC_TYPE_NONE;
7405         vars->phy_flags = 0;
7406
7407         /* disable attentions */
7408         bnx2x_bits_dis(bp, NIG_REG_MASK_INTERRUPT_PORT0 + params->port*4,
7409                        (NIG_MASK_XGXS0_LINK_STATUS |
7410                         NIG_MASK_XGXS0_LINK10G |
7411                         NIG_MASK_SERDES0_LINK_STATUS |
7412                         NIG_MASK_MI_INT));
7413
7414         bnx2x_emac_init(params, vars);
7415
7416         if (params->num_phys == 0) {
7417                 DP(NETIF_MSG_LINK, "No phy found for initialization !!\n");
7418                 return -EINVAL;
7419         }
7420         set_phy_vars(params);
7421
7422         DP(NETIF_MSG_LINK, "Num of phys on board: %d\n", params->num_phys);
7423         if (CHIP_REV_IS_FPGA(bp)) {
7424
7425                 vars->link_up = 1;
7426                 vars->line_speed = SPEED_10000;
7427                 vars->duplex = DUPLEX_FULL;
7428                 vars->flow_ctrl = BNX2X_FLOW_CTRL_NONE;
7429                 vars->link_status = (LINK_STATUS_LINK_UP | LINK_10GTFD);
7430                 /* enable on E1.5 FPGA */
7431                 if (CHIP_IS_E1H(bp)) {
7432                         vars->flow_ctrl |=
7433                                         (BNX2X_FLOW_CTRL_TX |
7434                                          BNX2X_FLOW_CTRL_RX);
7435                         vars->link_status |=
7436                                         (LINK_STATUS_TX_FLOW_CONTROL_ENABLED |
7437                                          LINK_STATUS_RX_FLOW_CONTROL_ENABLED);
7438                 }
7439
7440                 bnx2x_emac_enable(params, vars, 0);
7441                 if (!(CHIP_IS_E2(bp)))
7442                         bnx2x_pbf_update(params, vars->flow_ctrl,
7443                                          vars->line_speed);
7444                 /* disable drain */
7445                 REG_WR(bp, NIG_REG_EGRESS_DRAIN0_MODE + params->port*4, 0);
7446
7447                 /* update shared memory */
7448                 bnx2x_update_mng(params, vars->link_status);
7449
7450                 return 0;
7451
7452         } else
7453         if (CHIP_REV_IS_EMUL(bp)) {
7454
7455                 vars->link_up = 1;
7456                 vars->line_speed = SPEED_10000;
7457                 vars->duplex = DUPLEX_FULL;
7458                 vars->flow_ctrl = BNX2X_FLOW_CTRL_NONE;
7459                 vars->link_status = (LINK_STATUS_LINK_UP | LINK_10GTFD);
7460
7461                 bnx2x_bmac_enable(params, vars, 0);
7462
7463                 bnx2x_pbf_update(params, vars->flow_ctrl, vars->line_speed);
7464                 /* Disable drain */
7465                 REG_WR(bp, NIG_REG_EGRESS_DRAIN0_MODE
7466                                     + params->port*4, 0);
7467
7468                 /* update shared memory */
7469                 bnx2x_update_mng(params, vars->link_status);
7470
7471                 return 0;
7472
7473         } else
7474         if (params->loopback_mode == LOOPBACK_BMAC) {
7475
7476                 vars->link_up = 1;
7477                 vars->line_speed = SPEED_10000;
7478                 vars->duplex = DUPLEX_FULL;
7479                 vars->flow_ctrl = BNX2X_FLOW_CTRL_NONE;
7480                 vars->mac_type = MAC_TYPE_BMAC;
7481
7482                 vars->phy_flags = PHY_XGXS_FLAG;
7483
7484                 bnx2x_xgxs_deassert(params);
7485
7486                 /* set bmac loopback */
7487                 bnx2x_bmac_enable(params, vars, 1);
7488
7489                 REG_WR(bp, NIG_REG_EGRESS_DRAIN0_MODE +
7490                     params->port*4, 0);
7491
7492         } else if (params->loopback_mode == LOOPBACK_EMAC) {
7493
7494                 vars->link_up = 1;
7495                 vars->line_speed = SPEED_1000;
7496                 vars->duplex = DUPLEX_FULL;
7497                 vars->flow_ctrl = BNX2X_FLOW_CTRL_NONE;
7498                 vars->mac_type = MAC_TYPE_EMAC;
7499
7500                 vars->phy_flags = PHY_XGXS_FLAG;
7501
7502                 bnx2x_xgxs_deassert(params);
7503                 /* set bmac loopback */
7504                 bnx2x_emac_enable(params, vars, 1);
7505                 bnx2x_emac_program(params, vars);
7506                 REG_WR(bp, NIG_REG_EGRESS_DRAIN0_MODE +
7507                     params->port*4, 0);
7508
7509         } else if ((params->loopback_mode == LOOPBACK_XGXS) ||
7510                    (params->loopback_mode == LOOPBACK_EXT_PHY)) {
7511
7512                 vars->link_up = 1;
7513                 vars->flow_ctrl = BNX2X_FLOW_CTRL_NONE;
7514                 vars->duplex = DUPLEX_FULL;
7515                 if (params->req_line_speed[0] == SPEED_1000) {
7516                         vars->line_speed = SPEED_1000;
7517                         vars->mac_type = MAC_TYPE_EMAC;
7518                 } else {
7519                         vars->line_speed = SPEED_10000;
7520                         vars->mac_type = MAC_TYPE_BMAC;
7521                 }
7522
7523                 bnx2x_xgxs_deassert(params);
7524                 bnx2x_link_initialize(params, vars);
7525
7526                 if (params->req_line_speed[0] == SPEED_1000) {
7527                         bnx2x_emac_program(params, vars);
7528                         bnx2x_emac_enable(params, vars, 0);
7529                 } else
7530                 bnx2x_bmac_enable(params, vars, 0);
7531
7532                 if (params->loopback_mode == LOOPBACK_XGXS) {
7533                         /* set 10G XGXS loopback */
7534                         params->phy[INT_PHY].config_loopback(
7535                                 &params->phy[INT_PHY],
7536                                 params);
7537
7538                 } else {
7539                         /* set external phy loopback */
7540                         u8 phy_index;
7541                         for (phy_index = EXT_PHY1;
7542                               phy_index < params->num_phys; phy_index++) {
7543                                 if (params->phy[phy_index].config_loopback)
7544                                         params->phy[phy_index].config_loopback(
7545                                                 &params->phy[phy_index],
7546                                                 params);
7547                         }
7548                 }
7549
7550                 REG_WR(bp, NIG_REG_EGRESS_DRAIN0_MODE +
7551                             params->port*4, 0);
7552
7553                 bnx2x_set_led(params, vars,
7554                               LED_MODE_OPER, vars->line_speed);
7555         } else
7556         /* No loopback */
7557         {
7558                 if (params->switch_cfg == SWITCH_CFG_10G)
7559                         bnx2x_xgxs_deassert(params);
7560                 else
7561                         bnx2x_serdes_deassert(bp, params->port);
7562
7563                 bnx2x_link_initialize(params, vars);
7564                 msleep(30);
7565                 bnx2x_link_int_enable(params);
7566         }
7567         return 0;
7568 }
7569 u8 bnx2x_link_reset(struct link_params *params, struct link_vars *vars,
7570                   u8 reset_ext_phy)
7571 {
7572         struct bnx2x *bp = params->bp;
7573         u8 phy_index, port = params->port, clear_latch_ind = 0;
7574         DP(NETIF_MSG_LINK, "Resetting the link of port %d\n", port);
7575         /* disable attentions */
7576         vars->link_status = 0;
7577         bnx2x_update_mng(params, vars->link_status);
7578         bnx2x_bits_dis(bp, NIG_REG_MASK_INTERRUPT_PORT0 + port*4,
7579                      (NIG_MASK_XGXS0_LINK_STATUS |
7580                       NIG_MASK_XGXS0_LINK10G |
7581                       NIG_MASK_SERDES0_LINK_STATUS |
7582                       NIG_MASK_MI_INT));
7583
7584         /* activate nig drain */
7585         REG_WR(bp, NIG_REG_EGRESS_DRAIN0_MODE + port*4, 1);
7586
7587         /* disable nig egress interface */
7588         REG_WR(bp, NIG_REG_BMAC0_OUT_EN + port*4, 0);
7589         REG_WR(bp, NIG_REG_EGRESS_EMAC0_OUT_EN + port*4, 0);
7590
7591         /* Stop BigMac rx */
7592         bnx2x_bmac_rx_disable(bp, port);
7593
7594         /* disable emac */
7595         REG_WR(bp, NIG_REG_NIG_EMAC0_EN + port*4, 0);
7596
7597         msleep(10);
7598         /* The PHY reset is controled by GPIO 1
7599          * Hold it as vars low
7600          */
7601          /* clear link led */
7602         bnx2x_set_led(params, vars, LED_MODE_OFF, 0);
7603
7604         if (reset_ext_phy) {
7605                 for (phy_index = EXT_PHY1; phy_index < params->num_phys;
7606                       phy_index++) {
7607                         if (params->phy[phy_index].link_reset)
7608                                 params->phy[phy_index].link_reset(
7609                                         &params->phy[phy_index],
7610                                         params);
7611                         if (params->phy[phy_index].flags &
7612                             FLAGS_REARM_LATCH_SIGNAL)
7613                                 clear_latch_ind = 1;
7614                 }
7615         }
7616
7617         if (clear_latch_ind) {
7618                 /* Clear latching indication */
7619                 bnx2x_rearm_latch_signal(bp, port, 0);
7620                 bnx2x_bits_dis(bp, NIG_REG_LATCH_BC_0 + port*4,
7621                                1 << NIG_LATCH_BC_ENABLE_MI_INT);
7622         }
7623         if (params->phy[INT_PHY].link_reset)
7624                 params->phy[INT_PHY].link_reset(
7625                         &params->phy[INT_PHY], params);
7626         /* reset BigMac */
7627         REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_2_CLEAR,
7628                (MISC_REGISTERS_RESET_REG_2_RST_BMAC0 << port));
7629
7630         /* disable nig ingress interface */
7631         REG_WR(bp, NIG_REG_BMAC0_IN_EN + port*4, 0);
7632         REG_WR(bp, NIG_REG_EMAC0_IN_EN + port*4, 0);
7633         REG_WR(bp, NIG_REG_BMAC0_OUT_EN + port*4, 0);
7634         REG_WR(bp, NIG_REG_EGRESS_EMAC0_OUT_EN + port*4, 0);
7635         vars->link_up = 0;
7636         return 0;
7637 }
7638
7639 /****************************************************************************/
7640 /*                              Common function                             */
7641 /****************************************************************************/
7642 static u8 bnx2x_8073_common_init_phy(struct bnx2x *bp,
7643                                      u32 shmem_base_path[],
7644                                      u32 shmem2_base_path[], u8 phy_index,
7645                                      u32 chip_id)
7646 {
7647         struct bnx2x_phy phy[PORT_MAX];
7648         struct bnx2x_phy *phy_blk[PORT_MAX];
7649         u16 val;
7650         s8 port;
7651         s8 port_of_path = 0;
7652
7653         bnx2x_ext_phy_hw_reset(bp, 0);
7654         /* PART1 - Reset both phys */
7655         for (port = PORT_MAX - 1; port >= PORT_0; port--) {
7656                 u32 shmem_base, shmem2_base;
7657                 /* In E2, same phy is using for port0 of the two paths */
7658                 if (CHIP_IS_E2(bp)) {
7659                         shmem_base = shmem_base_path[port];
7660                         shmem2_base = shmem2_base_path[port];
7661                         port_of_path = 0;
7662                 } else {
7663                         shmem_base = shmem_base_path[0];
7664                         shmem2_base = shmem2_base_path[0];
7665                         port_of_path = port;
7666                 }
7667
7668                 /* Extract the ext phy address for the port */
7669                 if (bnx2x_populate_phy(bp, phy_index, shmem_base, shmem2_base,
7670                                        port_of_path, &phy[port]) !=
7671                     0) {
7672                         DP(NETIF_MSG_LINK, "populate_phy failed\n");
7673                         return -EINVAL;
7674                 }
7675                 /* disable attentions */
7676                 bnx2x_bits_dis(bp, NIG_REG_MASK_INTERRUPT_PORT0 +
7677                                port_of_path*4,
7678                              (NIG_MASK_XGXS0_LINK_STATUS |
7679                               NIG_MASK_XGXS0_LINK10G |
7680                               NIG_MASK_SERDES0_LINK_STATUS |
7681                               NIG_MASK_MI_INT));
7682
7683                 /* Need to take the phy out of low power mode in order
7684                         to write to access its registers */
7685                 bnx2x_set_gpio(bp, MISC_REGISTERS_GPIO_2,
7686                                   MISC_REGISTERS_GPIO_OUTPUT_HIGH, port);
7687
7688                 /* Reset the phy */
7689                 bnx2x_cl45_write(bp, &phy[port],
7690                                MDIO_PMA_DEVAD,
7691                                MDIO_PMA_REG_CTRL,
7692                                1<<15);
7693         }
7694
7695         /* Add delay of 150ms after reset */
7696         msleep(150);
7697
7698         if (phy[PORT_0].addr & 0x1) {
7699                 phy_blk[PORT_0] = &(phy[PORT_1]);
7700                 phy_blk[PORT_1] = &(phy[PORT_0]);
7701         } else {
7702                 phy_blk[PORT_0] = &(phy[PORT_0]);
7703                 phy_blk[PORT_1] = &(phy[PORT_1]);
7704         }
7705
7706         /* PART2 - Download firmware to both phys */
7707         for (port = PORT_MAX - 1; port >= PORT_0; port--) {
7708                 u16 fw_ver1;
7709                 if (CHIP_IS_E2(bp))
7710                         port_of_path = 0;
7711                 else
7712                         port_of_path = port;
7713
7714                 DP(NETIF_MSG_LINK, "Loading spirom for phy address 0x%x\n",
7715                            phy_blk[port]->addr);
7716                 bnx2x_8073_8727_external_rom_boot(bp, phy_blk[port],
7717                                                   port_of_path);
7718
7719                 bnx2x_cl45_read(bp, phy_blk[port],
7720                               MDIO_PMA_DEVAD,
7721                               MDIO_PMA_REG_ROM_VER1, &fw_ver1);
7722                 if (fw_ver1 == 0 || fw_ver1 == 0x4321) {
7723                         DP(NETIF_MSG_LINK,
7724                                  "bnx2x_8073_common_init_phy port %x:"
7725                                  "Download failed. fw version = 0x%x\n",
7726                                  port, fw_ver1);
7727                         return -EINVAL;
7728                 }
7729
7730                 /* Only set bit 10 = 1 (Tx power down) */
7731                 bnx2x_cl45_read(bp, phy_blk[port],
7732                               MDIO_PMA_DEVAD,
7733                               MDIO_PMA_REG_TX_POWER_DOWN, &val);
7734
7735                 /* Phase1 of TX_POWER_DOWN reset */
7736                 bnx2x_cl45_write(bp, phy_blk[port],
7737                                MDIO_PMA_DEVAD,
7738                                MDIO_PMA_REG_TX_POWER_DOWN,
7739                                (val | 1<<10));
7740         }
7741
7742         /* Toggle Transmitter: Power down and then up with 600ms
7743            delay between */
7744         msleep(600);
7745
7746         /* PART3 - complete TX_POWER_DOWN process, and set GPIO2 back to low */
7747         for (port = PORT_MAX - 1; port >= PORT_0; port--) {
7748                 /* Phase2 of POWER_DOWN_RESET */
7749                 /* Release bit 10 (Release Tx power down) */
7750                 bnx2x_cl45_read(bp, phy_blk[port],
7751                               MDIO_PMA_DEVAD,
7752                               MDIO_PMA_REG_TX_POWER_DOWN, &val);
7753
7754                 bnx2x_cl45_write(bp, phy_blk[port],
7755                                MDIO_PMA_DEVAD,
7756                                MDIO_PMA_REG_TX_POWER_DOWN, (val & (~(1<<10))));
7757                 msleep(15);
7758
7759                 /* Read modify write the SPI-ROM version select register */
7760                 bnx2x_cl45_read(bp, phy_blk[port],
7761                               MDIO_PMA_DEVAD,
7762                               MDIO_PMA_REG_EDC_FFE_MAIN, &val);
7763                 bnx2x_cl45_write(bp, phy_blk[port],
7764                               MDIO_PMA_DEVAD,
7765                               MDIO_PMA_REG_EDC_FFE_MAIN, (val | (1<<12)));
7766
7767                 /* set GPIO2 back to LOW */
7768                 bnx2x_set_gpio(bp, MISC_REGISTERS_GPIO_2,
7769                                   MISC_REGISTERS_GPIO_OUTPUT_LOW, port);
7770         }
7771         return 0;
7772 }
7773 static u8 bnx2x_8726_common_init_phy(struct bnx2x *bp,
7774                                      u32 shmem_base_path[],
7775                                      u32 shmem2_base_path[], u8 phy_index,
7776                                      u32 chip_id)
7777 {
7778         u32 val;
7779         s8 port;
7780         struct bnx2x_phy phy;
7781         /* Use port1 because of the static port-swap */
7782         /* Enable the module detection interrupt */
7783         val = REG_RD(bp, MISC_REG_GPIO_EVENT_EN);
7784         val |= ((1<<MISC_REGISTERS_GPIO_3)|
7785                 (1<<(MISC_REGISTERS_GPIO_3 + MISC_REGISTERS_GPIO_PORT_SHIFT)));
7786         REG_WR(bp, MISC_REG_GPIO_EVENT_EN, val);
7787
7788         bnx2x_ext_phy_hw_reset(bp, 0);
7789         msleep(5);
7790         for (port = 0; port < PORT_MAX; port++) {
7791                 u32 shmem_base, shmem2_base;
7792
7793                 /* In E2, same phy is using for port0 of the two paths */
7794                 if (CHIP_IS_E2(bp)) {
7795                         shmem_base = shmem_base_path[port];
7796                         shmem2_base = shmem2_base_path[port];
7797                 } else {
7798                         shmem_base = shmem_base_path[0];
7799                         shmem2_base = shmem2_base_path[0];
7800                 }
7801                 /* Extract the ext phy address for the port */
7802                 if (bnx2x_populate_phy(bp, phy_index, shmem_base, shmem2_base,
7803                                        port, &phy) !=
7804                     0) {
7805                         DP(NETIF_MSG_LINK, "populate phy failed\n");
7806                         return -EINVAL;
7807                 }
7808
7809                 /* Reset phy*/
7810                 bnx2x_cl45_write(bp, &phy,
7811                                  MDIO_PMA_DEVAD, MDIO_PMA_REG_GEN_CTRL, 0x0001);
7812
7813
7814                 /* Set fault module detected LED on */
7815                 bnx2x_set_gpio(bp, MISC_REGISTERS_GPIO_0,
7816                                   MISC_REGISTERS_GPIO_HIGH,
7817                                   port);
7818         }
7819
7820         return 0;
7821 }
7822 static u8 bnx2x_8727_common_init_phy(struct bnx2x *bp,
7823                                      u32 shmem_base_path[],
7824                                      u32 shmem2_base_path[], u8 phy_index,
7825                                      u32 chip_id)
7826 {
7827         s8 port;
7828         u32 swap_val, swap_override;
7829         struct bnx2x_phy phy[PORT_MAX];
7830         struct bnx2x_phy *phy_blk[PORT_MAX];
7831         s8 port_of_path;
7832         swap_val = REG_RD(bp,  NIG_REG_PORT_SWAP);
7833         swap_override = REG_RD(bp,  NIG_REG_STRAP_OVERRIDE);
7834
7835         port = 1;
7836
7837         bnx2x_ext_phy_hw_reset(bp, port ^ (swap_val && swap_override));
7838
7839         /* Calculate the port based on port swap */
7840         port ^= (swap_val && swap_override);
7841
7842         msleep(5);
7843
7844         /* PART1 - Reset both phys */
7845         for (port = PORT_MAX - 1; port >= PORT_0; port--) {
7846                 u32 shmem_base, shmem2_base;
7847
7848                 /* In E2, same phy is using for port0 of the two paths */
7849                 if (CHIP_IS_E2(bp)) {
7850                         shmem_base = shmem_base_path[port];
7851                         shmem2_base = shmem2_base_path[port];
7852                         port_of_path = 0;
7853                 } else {
7854                         shmem_base = shmem_base_path[0];
7855                         shmem2_base = shmem2_base_path[0];
7856                         port_of_path = port;
7857                 }
7858
7859                 /* Extract the ext phy address for the port */
7860                 if (bnx2x_populate_phy(bp, phy_index, shmem_base, shmem2_base,
7861                                        port_of_path, &phy[port]) !=
7862                                        0) {
7863                         DP(NETIF_MSG_LINK, "populate phy failed\n");
7864                         return -EINVAL;
7865                 }
7866                 /* disable attentions */
7867                 bnx2x_bits_dis(bp, NIG_REG_MASK_INTERRUPT_PORT0 +
7868                                port_of_path*4,
7869                                (NIG_MASK_XGXS0_LINK_STATUS |
7870                                 NIG_MASK_XGXS0_LINK10G |
7871                                 NIG_MASK_SERDES0_LINK_STATUS |
7872                                 NIG_MASK_MI_INT));
7873
7874
7875                 /* Reset the phy */
7876                 bnx2x_cl45_write(bp, &phy[port],
7877                                MDIO_PMA_DEVAD,
7878                                MDIO_PMA_REG_CTRL,
7879                                1<<15);
7880         }
7881
7882         /* Add delay of 150ms after reset */
7883         msleep(150);
7884         if (phy[PORT_0].addr & 0x1) {
7885                 phy_blk[PORT_0] = &(phy[PORT_1]);
7886                 phy_blk[PORT_1] = &(phy[PORT_0]);
7887         } else {
7888                 phy_blk[PORT_0] = &(phy[PORT_0]);
7889                 phy_blk[PORT_1] = &(phy[PORT_1]);
7890         }
7891         /* PART2 - Download firmware to both phys */
7892         for (port = PORT_MAX - 1; port >= PORT_0; port--) {
7893                 u16 fw_ver1;
7894                  if (CHIP_IS_E2(bp))
7895                         port_of_path = 0;
7896                 else
7897                         port_of_path = port;
7898                 DP(NETIF_MSG_LINK, "Loading spirom for phy address 0x%x\n",
7899                            phy_blk[port]->addr);
7900                 bnx2x_8073_8727_external_rom_boot(bp, phy_blk[port],
7901                                                   port_of_path);
7902                 bnx2x_cl45_read(bp, phy_blk[port],
7903                               MDIO_PMA_DEVAD,
7904                               MDIO_PMA_REG_ROM_VER1, &fw_ver1);
7905                 if (fw_ver1 == 0 || fw_ver1 == 0x4321) {
7906                         DP(NETIF_MSG_LINK,
7907                                  "bnx2x_8727_common_init_phy port %x:"
7908                                  "Download failed. fw version = 0x%x\n",
7909                                  port, fw_ver1);
7910                         return -EINVAL;
7911                 }
7912         }
7913
7914         return 0;
7915 }
7916
7917 static u8 bnx2x_ext_phy_common_init(struct bnx2x *bp, u32 shmem_base_path[],
7918                                     u32 shmem2_base_path[], u8 phy_index,
7919                                     u32 ext_phy_type, u32 chip_id)
7920 {
7921         u8 rc = 0;
7922
7923         switch (ext_phy_type) {
7924         case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8073:
7925                 rc = bnx2x_8073_common_init_phy(bp, shmem_base_path,
7926                                                 shmem2_base_path,
7927                                                 phy_index, chip_id);
7928                 break;
7929
7930         case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8727:
7931         case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8727_NOC:
7932                 rc = bnx2x_8727_common_init_phy(bp, shmem_base_path,
7933                                                 shmem2_base_path,
7934                                                 phy_index, chip_id);
7935                 break;
7936
7937         case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8726:
7938                 /* GPIO1 affects both ports, so there's need to pull
7939                 it for single port alone */
7940                 rc = bnx2x_8726_common_init_phy(bp, shmem_base_path,
7941                                                 shmem2_base_path,
7942                                                 phy_index, chip_id);
7943                 break;
7944         case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_FAILURE:
7945                 rc = -EINVAL;
7946                 break;
7947         default:
7948                 DP(NETIF_MSG_LINK,
7949                          "bnx2x_common_init_phy: ext_phy 0x%x not required\n",
7950                          ext_phy_type);
7951                 break;
7952         }
7953
7954         return rc;
7955 }
7956
7957 u8 bnx2x_common_init_phy(struct bnx2x *bp, u32 shmem_base_path[],
7958                          u32 shmem2_base_path[], u32 chip_id)
7959 {
7960         u8 rc = 0;
7961         u32 phy_ver;
7962         u8 phy_index;
7963         u32 ext_phy_type, ext_phy_config;
7964         DP(NETIF_MSG_LINK, "Begin common phy init\n");
7965
7966         if (CHIP_REV_IS_EMUL(bp))
7967                 return 0;
7968
7969         /* Check if common init was already done */
7970         phy_ver = REG_RD(bp, shmem_base_path[0] +
7971                          offsetof(struct shmem_region,
7972                                   port_mb[PORT_0].ext_phy_fw_version));
7973         if (phy_ver) {
7974                 DP(NETIF_MSG_LINK, "Not doing common init; phy ver is 0x%x\n",
7975                                phy_ver);
7976                 return 0;
7977         }
7978
7979         /* Read the ext_phy_type for arbitrary port(0) */
7980         for (phy_index = EXT_PHY1; phy_index < MAX_PHYS;
7981               phy_index++) {
7982                 ext_phy_config = bnx2x_get_ext_phy_config(bp,
7983                                                           shmem_base_path[0],
7984                                                           phy_index, 0);
7985                 ext_phy_type = XGXS_EXT_PHY_TYPE(ext_phy_config);
7986                 rc |= bnx2x_ext_phy_common_init(bp, shmem_base_path,
7987                                                 shmem2_base_path,
7988                                                 phy_index, ext_phy_type,
7989                                                 chip_id);
7990         }
7991         return rc;
7992 }
7993
7994 u8 bnx2x_hw_lock_required(struct bnx2x *bp, u32 shmem_base, u32 shmem2_base)
7995 {
7996         u8 phy_index;
7997         struct bnx2x_phy phy;
7998         for (phy_index = INT_PHY; phy_index < MAX_PHYS;
7999               phy_index++) {
8000                 if (bnx2x_populate_phy(bp, phy_index, shmem_base, shmem2_base,
8001                                        0, &phy) != 0) {
8002                         DP(NETIF_MSG_LINK, "populate phy failed\n");
8003                         return 0;
8004                 }
8005
8006                 if (phy.flags & FLAGS_HW_LOCK_REQUIRED)
8007                         return 1;
8008         }
8009         return 0;
8010 }
8011
8012 u8 bnx2x_fan_failure_det_req(struct bnx2x *bp,
8013                              u32 shmem_base,
8014                              u32 shmem2_base,
8015                              u8 port)
8016 {
8017         u8 phy_index, fan_failure_det_req = 0;
8018         struct bnx2x_phy phy;
8019         for (phy_index = EXT_PHY1; phy_index < MAX_PHYS;
8020               phy_index++) {
8021                 if (bnx2x_populate_phy(bp, phy_index, shmem_base, shmem2_base,
8022                                        port, &phy)
8023                     != 0) {
8024                         DP(NETIF_MSG_LINK, "populate phy failed\n");
8025                         return 0;
8026                 }
8027                 fan_failure_det_req |= (phy.flags &
8028                                         FLAGS_FAN_FAILURE_DET_REQ);
8029         }
8030         return fan_failure_det_req;
8031 }
8032
8033 void bnx2x_hw_reset_phy(struct link_params *params)
8034 {
8035         u8 phy_index;
8036         for (phy_index = EXT_PHY1; phy_index < MAX_PHYS;
8037               phy_index++) {
8038                 if (params->phy[phy_index].hw_reset) {
8039                         params->phy[phy_index].hw_reset(
8040                                 &params->phy[phy_index],
8041                                 params);
8042                         params->phy[phy_index] = phy_null;
8043                 }
8044         }
8045 }