2 * flexcan.c - FLEXCAN CAN controller driver
4 * Copyright (c) 2005-2006 Varma Electronics Oy
5 * Copyright (c) 2009 Sascha Hauer, Pengutronix
6 * Copyright (c) 2010 Marc Kleine-Budde, Pengutronix
8 * Based on code originally by Andrey Volkov <avolkov@varma-el.com>
11 * This program is free software; you can redistribute it and/or
12 * modify it under the terms of the GNU General Public License as
13 * published by the Free Software Foundation version 2.
15 * This program is distributed in the hope that it will be useful,
16 * but WITHOUT ANY WARRANTY; without even the implied warranty of
17 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
18 * GNU General Public License for more details.
22 #include <linux/netdevice.h>
23 #include <linux/can.h>
24 #include <linux/can/dev.h>
25 #include <linux/can/error.h>
26 #include <linux/can/led.h>
27 #include <linux/clk.h>
28 #include <linux/delay.h>
29 #include <linux/if_arp.h>
30 #include <linux/if_ether.h>
31 #include <linux/interrupt.h>
33 #include <linux/kernel.h>
34 #include <linux/list.h>
35 #include <linux/module.h>
37 #include <linux/of_device.h>
38 #include <linux/platform_device.h>
39 #include <linux/regulator/consumer.h>
41 #define DRV_NAME "flexcan"
43 /* 8 for RX fifo and 2 error handling */
44 #define FLEXCAN_NAPI_WEIGHT (8 + 2)
46 /* FLEXCAN module configuration register (CANMCR) bits */
47 #define FLEXCAN_MCR_MDIS BIT(31)
48 #define FLEXCAN_MCR_FRZ BIT(30)
49 #define FLEXCAN_MCR_FEN BIT(29)
50 #define FLEXCAN_MCR_HALT BIT(28)
51 #define FLEXCAN_MCR_NOT_RDY BIT(27)
52 #define FLEXCAN_MCR_WAK_MSK BIT(26)
53 #define FLEXCAN_MCR_SOFTRST BIT(25)
54 #define FLEXCAN_MCR_FRZ_ACK BIT(24)
55 #define FLEXCAN_MCR_SUPV BIT(23)
56 #define FLEXCAN_MCR_SLF_WAK BIT(22)
57 #define FLEXCAN_MCR_WRN_EN BIT(21)
58 #define FLEXCAN_MCR_LPM_ACK BIT(20)
59 #define FLEXCAN_MCR_WAK_SRC BIT(19)
60 #define FLEXCAN_MCR_DOZE BIT(18)
61 #define FLEXCAN_MCR_SRX_DIS BIT(17)
62 #define FLEXCAN_MCR_BCC BIT(16)
63 #define FLEXCAN_MCR_LPRIO_EN BIT(13)
64 #define FLEXCAN_MCR_AEN BIT(12)
65 #define FLEXCAN_MCR_MAXMB(x) ((x) & 0x1f)
66 #define FLEXCAN_MCR_IDAM_A (0 << 8)
67 #define FLEXCAN_MCR_IDAM_B (1 << 8)
68 #define FLEXCAN_MCR_IDAM_C (2 << 8)
69 #define FLEXCAN_MCR_IDAM_D (3 << 8)
71 /* FLEXCAN control register (CANCTRL) bits */
72 #define FLEXCAN_CTRL_PRESDIV(x) (((x) & 0xff) << 24)
73 #define FLEXCAN_CTRL_RJW(x) (((x) & 0x03) << 22)
74 #define FLEXCAN_CTRL_PSEG1(x) (((x) & 0x07) << 19)
75 #define FLEXCAN_CTRL_PSEG2(x) (((x) & 0x07) << 16)
76 #define FLEXCAN_CTRL_BOFF_MSK BIT(15)
77 #define FLEXCAN_CTRL_ERR_MSK BIT(14)
78 #define FLEXCAN_CTRL_CLK_SRC BIT(13)
79 #define FLEXCAN_CTRL_LPB BIT(12)
80 #define FLEXCAN_CTRL_TWRN_MSK BIT(11)
81 #define FLEXCAN_CTRL_RWRN_MSK BIT(10)
82 #define FLEXCAN_CTRL_SMP BIT(7)
83 #define FLEXCAN_CTRL_BOFF_REC BIT(6)
84 #define FLEXCAN_CTRL_TSYN BIT(5)
85 #define FLEXCAN_CTRL_LBUF BIT(4)
86 #define FLEXCAN_CTRL_LOM BIT(3)
87 #define FLEXCAN_CTRL_PROPSEG(x) ((x) & 0x07)
88 #define FLEXCAN_CTRL_ERR_BUS (FLEXCAN_CTRL_ERR_MSK)
89 #define FLEXCAN_CTRL_ERR_STATE \
90 (FLEXCAN_CTRL_TWRN_MSK | FLEXCAN_CTRL_RWRN_MSK | \
91 FLEXCAN_CTRL_BOFF_MSK)
92 #define FLEXCAN_CTRL_ERR_ALL \
93 (FLEXCAN_CTRL_ERR_BUS | FLEXCAN_CTRL_ERR_STATE)
95 /* FLEXCAN error and status register (ESR) bits */
96 #define FLEXCAN_ESR_TWRN_INT BIT(17)
97 #define FLEXCAN_ESR_RWRN_INT BIT(16)
98 #define FLEXCAN_ESR_BIT1_ERR BIT(15)
99 #define FLEXCAN_ESR_BIT0_ERR BIT(14)
100 #define FLEXCAN_ESR_ACK_ERR BIT(13)
101 #define FLEXCAN_ESR_CRC_ERR BIT(12)
102 #define FLEXCAN_ESR_FRM_ERR BIT(11)
103 #define FLEXCAN_ESR_STF_ERR BIT(10)
104 #define FLEXCAN_ESR_TX_WRN BIT(9)
105 #define FLEXCAN_ESR_RX_WRN BIT(8)
106 #define FLEXCAN_ESR_IDLE BIT(7)
107 #define FLEXCAN_ESR_TXRX BIT(6)
108 #define FLEXCAN_EST_FLT_CONF_SHIFT (4)
109 #define FLEXCAN_ESR_FLT_CONF_MASK (0x3 << FLEXCAN_EST_FLT_CONF_SHIFT)
110 #define FLEXCAN_ESR_FLT_CONF_ACTIVE (0x0 << FLEXCAN_EST_FLT_CONF_SHIFT)
111 #define FLEXCAN_ESR_FLT_CONF_PASSIVE (0x1 << FLEXCAN_EST_FLT_CONF_SHIFT)
112 #define FLEXCAN_ESR_BOFF_INT BIT(2)
113 #define FLEXCAN_ESR_ERR_INT BIT(1)
114 #define FLEXCAN_ESR_WAK_INT BIT(0)
115 #define FLEXCAN_ESR_ERR_BUS \
116 (FLEXCAN_ESR_BIT1_ERR | FLEXCAN_ESR_BIT0_ERR | \
117 FLEXCAN_ESR_ACK_ERR | FLEXCAN_ESR_CRC_ERR | \
118 FLEXCAN_ESR_FRM_ERR | FLEXCAN_ESR_STF_ERR)
119 #define FLEXCAN_ESR_ERR_STATE \
120 (FLEXCAN_ESR_TWRN_INT | FLEXCAN_ESR_RWRN_INT | FLEXCAN_ESR_BOFF_INT)
121 #define FLEXCAN_ESR_ERR_ALL \
122 (FLEXCAN_ESR_ERR_BUS | FLEXCAN_ESR_ERR_STATE)
123 #define FLEXCAN_ESR_ALL_INT \
124 (FLEXCAN_ESR_TWRN_INT | FLEXCAN_ESR_RWRN_INT | \
125 FLEXCAN_ESR_BOFF_INT | FLEXCAN_ESR_ERR_INT)
127 /* FLEXCAN interrupt flag register (IFLAG) bits */
128 #define FLEXCAN_RESERVED_BUF_ID 8
129 #define FLEXCAN_TX_BUF_ID 13
130 #define FLEXCAN_IFLAG_BUF(x) BIT(x)
131 #define FLEXCAN_IFLAG_RX_FIFO_OVERFLOW BIT(7)
132 #define FLEXCAN_IFLAG_RX_FIFO_WARN BIT(6)
133 #define FLEXCAN_IFLAG_RX_FIFO_AVAILABLE BIT(5)
134 #define FLEXCAN_IFLAG_DEFAULT \
135 (FLEXCAN_IFLAG_RX_FIFO_OVERFLOW | FLEXCAN_IFLAG_RX_FIFO_AVAILABLE | \
136 FLEXCAN_IFLAG_BUF(FLEXCAN_TX_BUF_ID))
138 /* FLEXCAN message buffers */
139 #define FLEXCAN_MB_CNT_CODE(x) (((x) & 0xf) << 24)
140 #define FLEXCAN_MB_CNT_SRR BIT(22)
141 #define FLEXCAN_MB_CNT_IDE BIT(21)
142 #define FLEXCAN_MB_CNT_RTR BIT(20)
143 #define FLEXCAN_MB_CNT_LENGTH(x) (((x) & 0xf) << 16)
144 #define FLEXCAN_MB_CNT_TIMESTAMP(x) ((x) & 0xffff)
146 #define FLEXCAN_MB_CODE_MASK (0xf0ffffff)
148 #define FLEXCAN_TIMEOUT_US (50)
151 * FLEXCAN hardware feature flags
153 * Below is some version info we got:
154 * SOC Version IP-Version Glitch- [TR]WRN_INT
156 * MX25 FlexCAN2 03.00.00.00 no no
157 * MX28 FlexCAN2 03.00.04.00 yes yes
158 * MX35 FlexCAN2 03.00.00.00 no no
159 * MX53 FlexCAN2 03.00.00.00 yes no
160 * MX6s FlexCAN3 10.00.12.00 yes yes
162 * Some SOCs do not have the RX_WARN & TX_WARN interrupt line connected.
164 #define FLEXCAN_HAS_V10_FEATURES BIT(1) /* For core version >= 10 */
165 #define FLEXCAN_HAS_BROKEN_ERR_STATE BIT(2) /* [TR]WRN_INT not connected */
166 #define FLEXCAN_HAS_ERR005829 BIT(3) /* have errata ERR005829 */
168 /* Structure of the message buffer */
175 /* Structure of the hardware registers */
176 struct flexcan_regs {
179 u32 timer; /* 0x08 */
180 u32 _reserved1; /* 0x0c */
181 u32 rxgmask; /* 0x10 */
182 u32 rx14mask; /* 0x14 */
183 u32 rx15mask; /* 0x18 */
186 u32 imask2; /* 0x24 */
187 u32 imask1; /* 0x28 */
188 u32 iflag2; /* 0x2c */
189 u32 iflag1; /* 0x30 */
192 u32 imeur; /* 0x3c */
195 u32 rxfgmask; /* 0x48 */
196 u32 rxfir; /* 0x4c */
198 struct flexcan_mb cantxfg[64];
201 struct flexcan_devtype_data {
202 u32 features; /* hardware controller features */
205 struct flexcan_priv {
207 struct net_device *dev;
208 struct napi_struct napi;
212 u32 reg_ctrl_default;
216 struct flexcan_platform_data *pdata;
217 const struct flexcan_devtype_data *devtype_data;
218 struct regulator *reg_xceiver;
221 static struct flexcan_devtype_data fsl_p1010_devtype_data = {
222 .features = FLEXCAN_HAS_BROKEN_ERR_STATE,
224 static struct flexcan_devtype_data fsl_imx28_devtype_data;
225 static struct flexcan_devtype_data fsl_imx6q_devtype_data = {
226 .features = FLEXCAN_HAS_V10_FEATURES | FLEXCAN_HAS_ERR005829,
229 static const struct can_bittiming_const flexcan_bittiming_const = {
242 * Abstract off the read/write for arm versus ppc. This
243 * assumes that PPC uses big-endian registers and everything
244 * else uses little-endian registers, independent of CPU
247 #if defined(CONFIG_PPC)
248 static inline u32 flexcan_read(void __iomem *addr)
250 return in_be32(addr);
253 static inline void flexcan_write(u32 val, void __iomem *addr)
258 static inline u32 flexcan_read(void __iomem *addr)
263 static inline void flexcan_write(u32 val, void __iomem *addr)
269 static inline int flexcan_transceiver_enable(const struct flexcan_priv *priv)
271 if (!priv->reg_xceiver)
274 return regulator_enable(priv->reg_xceiver);
277 static inline int flexcan_transceiver_disable(const struct flexcan_priv *priv)
279 if (!priv->reg_xceiver)
282 return regulator_disable(priv->reg_xceiver);
285 static inline int flexcan_has_and_handle_berr(const struct flexcan_priv *priv,
288 return (priv->can.ctrlmode & CAN_CTRLMODE_BERR_REPORTING) &&
289 (reg_esr & FLEXCAN_ESR_ERR_BUS);
292 static int flexcan_chip_enable(struct flexcan_priv *priv)
294 struct flexcan_regs __iomem *regs = priv->base;
295 unsigned int timeout = FLEXCAN_TIMEOUT_US / 10;
298 reg = flexcan_read(®s->mcr);
299 reg &= ~FLEXCAN_MCR_MDIS;
300 flexcan_write(reg, ®s->mcr);
302 while (timeout-- && (flexcan_read(®s->mcr) & FLEXCAN_MCR_LPM_ACK))
303 usleep_range(10, 20);
305 if (flexcan_read(®s->mcr) & FLEXCAN_MCR_LPM_ACK)
311 static int flexcan_chip_disable(struct flexcan_priv *priv)
313 struct flexcan_regs __iomem *regs = priv->base;
314 unsigned int timeout = FLEXCAN_TIMEOUT_US / 10;
317 reg = flexcan_read(®s->mcr);
318 reg |= FLEXCAN_MCR_MDIS;
319 flexcan_write(reg, ®s->mcr);
321 while (timeout-- && !(flexcan_read(®s->mcr) & FLEXCAN_MCR_LPM_ACK))
322 usleep_range(10, 20);
324 if (!(flexcan_read(®s->mcr) & FLEXCAN_MCR_LPM_ACK))
330 static int flexcan_chip_freeze(struct flexcan_priv *priv)
332 struct flexcan_regs __iomem *regs = priv->base;
333 unsigned int timeout = 1000 * 1000 * 10 / priv->can.bittiming.bitrate;
336 reg = flexcan_read(®s->mcr);
337 reg |= FLEXCAN_MCR_HALT;
338 flexcan_write(reg, ®s->mcr);
340 while (timeout-- && !(flexcan_read(®s->mcr) & FLEXCAN_MCR_FRZ_ACK))
341 usleep_range(100, 200);
343 if (!(flexcan_read(®s->mcr) & FLEXCAN_MCR_FRZ_ACK))
349 static int flexcan_chip_unfreeze(struct flexcan_priv *priv)
351 struct flexcan_regs __iomem *regs = priv->base;
352 unsigned int timeout = FLEXCAN_TIMEOUT_US / 10;
355 reg = flexcan_read(®s->mcr);
356 reg &= ~FLEXCAN_MCR_HALT;
357 flexcan_write(reg, ®s->mcr);
359 while (timeout-- && (flexcan_read(®s->mcr) & FLEXCAN_MCR_FRZ_ACK))
360 usleep_range(10, 20);
362 if (flexcan_read(®s->mcr) & FLEXCAN_MCR_FRZ_ACK)
368 static int flexcan_chip_softreset(struct flexcan_priv *priv)
370 struct flexcan_regs __iomem *regs = priv->base;
371 unsigned int timeout = FLEXCAN_TIMEOUT_US / 10;
373 flexcan_write(FLEXCAN_MCR_SOFTRST, ®s->mcr);
374 while (timeout-- && (flexcan_read(®s->mcr) & FLEXCAN_MCR_SOFTRST))
375 usleep_range(10, 20);
377 if (flexcan_read(®s->mcr) & FLEXCAN_MCR_SOFTRST)
383 static int flexcan_get_berr_counter(const struct net_device *dev,
384 struct can_berr_counter *bec)
386 const struct flexcan_priv *priv = netdev_priv(dev);
387 struct flexcan_regs __iomem *regs = priv->base;
388 u32 reg = flexcan_read(®s->ecr);
390 bec->txerr = (reg >> 0) & 0xff;
391 bec->rxerr = (reg >> 8) & 0xff;
396 static int flexcan_start_xmit(struct sk_buff *skb, struct net_device *dev)
398 const struct flexcan_priv *priv = netdev_priv(dev);
399 struct flexcan_regs __iomem *regs = priv->base;
400 struct can_frame *cf = (struct can_frame *)skb->data;
402 u32 ctrl = FLEXCAN_MB_CNT_CODE(0xc) | (cf->can_dlc << 16);
404 if (can_dropped_invalid_skb(dev, skb))
407 netif_stop_queue(dev);
409 if (cf->can_id & CAN_EFF_FLAG) {
410 can_id = cf->can_id & CAN_EFF_MASK;
411 ctrl |= FLEXCAN_MB_CNT_IDE | FLEXCAN_MB_CNT_SRR;
413 can_id = (cf->can_id & CAN_SFF_MASK) << 18;
416 if (cf->can_id & CAN_RTR_FLAG)
417 ctrl |= FLEXCAN_MB_CNT_RTR;
419 if (cf->can_dlc > 0) {
420 u32 data = be32_to_cpup((__be32 *)&cf->data[0]);
421 flexcan_write(data, ®s->cantxfg[FLEXCAN_TX_BUF_ID].data[0]);
423 if (cf->can_dlc > 3) {
424 u32 data = be32_to_cpup((__be32 *)&cf->data[4]);
425 flexcan_write(data, ®s->cantxfg[FLEXCAN_TX_BUF_ID].data[1]);
428 can_put_echo_skb(skb, dev, 0);
430 flexcan_write(can_id, ®s->cantxfg[FLEXCAN_TX_BUF_ID].can_id);
431 flexcan_write(ctrl, ®s->cantxfg[FLEXCAN_TX_BUF_ID].can_ctrl);
433 if (priv->devtype_data->features & FLEXCAN_HAS_ERR005829) {
434 writel(0x0, ®s->cantxfg[FLEXCAN_RESERVED_BUF_ID].can_ctrl);
435 writel(0x0, ®s->cantxfg[FLEXCAN_RESERVED_BUF_ID].can_ctrl);
441 static void do_bus_err(struct net_device *dev,
442 struct can_frame *cf, u32 reg_esr)
444 struct flexcan_priv *priv = netdev_priv(dev);
445 int rx_errors = 0, tx_errors = 0;
447 cf->can_id |= CAN_ERR_PROT | CAN_ERR_BUSERROR;
449 if (reg_esr & FLEXCAN_ESR_BIT1_ERR) {
450 netdev_dbg(dev, "BIT1_ERR irq\n");
451 cf->data[2] |= CAN_ERR_PROT_BIT1;
454 if (reg_esr & FLEXCAN_ESR_BIT0_ERR) {
455 netdev_dbg(dev, "BIT0_ERR irq\n");
456 cf->data[2] |= CAN_ERR_PROT_BIT0;
459 if (reg_esr & FLEXCAN_ESR_ACK_ERR) {
460 netdev_dbg(dev, "ACK_ERR irq\n");
461 cf->can_id |= CAN_ERR_ACK;
462 cf->data[3] |= CAN_ERR_PROT_LOC_ACK;
465 if (reg_esr & FLEXCAN_ESR_CRC_ERR) {
466 netdev_dbg(dev, "CRC_ERR irq\n");
467 cf->data[2] |= CAN_ERR_PROT_BIT;
468 cf->data[3] |= CAN_ERR_PROT_LOC_CRC_SEQ;
471 if (reg_esr & FLEXCAN_ESR_FRM_ERR) {
472 netdev_dbg(dev, "FRM_ERR irq\n");
473 cf->data[2] |= CAN_ERR_PROT_FORM;
476 if (reg_esr & FLEXCAN_ESR_STF_ERR) {
477 netdev_dbg(dev, "STF_ERR irq\n");
478 cf->data[2] |= CAN_ERR_PROT_STUFF;
482 priv->can.can_stats.bus_error++;
484 dev->stats.rx_errors++;
486 dev->stats.tx_errors++;
489 static int flexcan_poll_bus_err(struct net_device *dev, u32 reg_esr)
492 struct can_frame *cf;
494 skb = alloc_can_err_skb(dev, &cf);
498 do_bus_err(dev, cf, reg_esr);
499 netif_receive_skb(skb);
501 dev->stats.rx_packets++;
502 dev->stats.rx_bytes += cf->can_dlc;
507 static void do_state(struct net_device *dev,
508 struct can_frame *cf, enum can_state new_state)
510 struct flexcan_priv *priv = netdev_priv(dev);
511 struct can_berr_counter bec;
513 flexcan_get_berr_counter(dev, &bec);
515 switch (priv->can.state) {
516 case CAN_STATE_ERROR_ACTIVE:
519 * to : ERROR_WARNING, ERROR_PASSIVE, BUS_OFF
520 * => : there was a warning int
522 if (new_state >= CAN_STATE_ERROR_WARNING &&
523 new_state <= CAN_STATE_BUS_OFF) {
524 netdev_dbg(dev, "Error Warning IRQ\n");
525 priv->can.can_stats.error_warning++;
527 cf->can_id |= CAN_ERR_CRTL;
528 cf->data[1] = (bec.txerr > bec.rxerr) ?
529 CAN_ERR_CRTL_TX_WARNING :
530 CAN_ERR_CRTL_RX_WARNING;
532 case CAN_STATE_ERROR_WARNING: /* fallthrough */
534 * from: ERROR_ACTIVE, ERROR_WARNING
535 * to : ERROR_PASSIVE, BUS_OFF
536 * => : error passive int
538 if (new_state >= CAN_STATE_ERROR_PASSIVE &&
539 new_state <= CAN_STATE_BUS_OFF) {
540 netdev_dbg(dev, "Error Passive IRQ\n");
541 priv->can.can_stats.error_passive++;
543 cf->can_id |= CAN_ERR_CRTL;
544 cf->data[1] = (bec.txerr > bec.rxerr) ?
545 CAN_ERR_CRTL_TX_PASSIVE :
546 CAN_ERR_CRTL_RX_PASSIVE;
549 case CAN_STATE_BUS_OFF:
550 netdev_err(dev, "BUG! "
551 "hardware recovered automatically from BUS_OFF\n");
557 /* process state changes depending on the new state */
559 case CAN_STATE_ERROR_ACTIVE:
560 netdev_dbg(dev, "Error Active\n");
561 cf->can_id |= CAN_ERR_PROT;
562 cf->data[2] = CAN_ERR_PROT_ACTIVE;
564 case CAN_STATE_BUS_OFF:
565 cf->can_id |= CAN_ERR_BUSOFF;
573 static int flexcan_poll_state(struct net_device *dev, u32 reg_esr)
575 struct flexcan_priv *priv = netdev_priv(dev);
577 struct can_frame *cf;
578 enum can_state new_state;
581 flt = reg_esr & FLEXCAN_ESR_FLT_CONF_MASK;
582 if (likely(flt == FLEXCAN_ESR_FLT_CONF_ACTIVE)) {
583 if (likely(!(reg_esr & (FLEXCAN_ESR_TX_WRN |
584 FLEXCAN_ESR_RX_WRN))))
585 new_state = CAN_STATE_ERROR_ACTIVE;
587 new_state = CAN_STATE_ERROR_WARNING;
588 } else if (unlikely(flt == FLEXCAN_ESR_FLT_CONF_PASSIVE))
589 new_state = CAN_STATE_ERROR_PASSIVE;
591 new_state = CAN_STATE_BUS_OFF;
593 /* state hasn't changed */
594 if (likely(new_state == priv->can.state))
597 skb = alloc_can_err_skb(dev, &cf);
601 do_state(dev, cf, new_state);
602 priv->can.state = new_state;
603 netif_receive_skb(skb);
605 dev->stats.rx_packets++;
606 dev->stats.rx_bytes += cf->can_dlc;
611 static void flexcan_read_fifo(const struct net_device *dev,
612 struct can_frame *cf)
614 const struct flexcan_priv *priv = netdev_priv(dev);
615 struct flexcan_regs __iomem *regs = priv->base;
616 struct flexcan_mb __iomem *mb = ®s->cantxfg[0];
617 u32 reg_ctrl, reg_id;
619 reg_ctrl = flexcan_read(&mb->can_ctrl);
620 reg_id = flexcan_read(&mb->can_id);
621 if (reg_ctrl & FLEXCAN_MB_CNT_IDE)
622 cf->can_id = ((reg_id >> 0) & CAN_EFF_MASK) | CAN_EFF_FLAG;
624 cf->can_id = (reg_id >> 18) & CAN_SFF_MASK;
626 if (reg_ctrl & FLEXCAN_MB_CNT_RTR)
627 cf->can_id |= CAN_RTR_FLAG;
628 cf->can_dlc = get_can_dlc((reg_ctrl >> 16) & 0xf);
630 *(__be32 *)(cf->data + 0) = cpu_to_be32(flexcan_read(&mb->data[0]));
631 *(__be32 *)(cf->data + 4) = cpu_to_be32(flexcan_read(&mb->data[1]));
634 flexcan_write(FLEXCAN_IFLAG_RX_FIFO_AVAILABLE, ®s->iflag1);
635 flexcan_read(®s->timer);
638 static int flexcan_read_frame(struct net_device *dev)
640 struct net_device_stats *stats = &dev->stats;
641 struct can_frame *cf;
644 skb = alloc_can_skb(dev, &cf);
645 if (unlikely(!skb)) {
650 flexcan_read_fifo(dev, cf);
651 netif_receive_skb(skb);
654 stats->rx_bytes += cf->can_dlc;
656 can_led_event(dev, CAN_LED_EVENT_RX);
661 static int flexcan_poll(struct napi_struct *napi, int quota)
663 struct net_device *dev = napi->dev;
664 const struct flexcan_priv *priv = netdev_priv(dev);
665 struct flexcan_regs __iomem *regs = priv->base;
666 u32 reg_iflag1, reg_esr;
670 * The error bits are cleared on read,
671 * use saved value from irq handler.
673 reg_esr = flexcan_read(®s->esr) | priv->reg_esr;
675 /* handle state changes */
676 work_done += flexcan_poll_state(dev, reg_esr);
679 reg_iflag1 = flexcan_read(®s->iflag1);
680 while (reg_iflag1 & FLEXCAN_IFLAG_RX_FIFO_AVAILABLE &&
682 work_done += flexcan_read_frame(dev);
683 reg_iflag1 = flexcan_read(®s->iflag1);
686 /* report bus errors */
687 if (flexcan_has_and_handle_berr(priv, reg_esr) && work_done < quota)
688 work_done += flexcan_poll_bus_err(dev, reg_esr);
690 if (work_done < quota) {
693 flexcan_write(FLEXCAN_IFLAG_DEFAULT, ®s->imask1);
694 flexcan_write(priv->reg_ctrl_default, ®s->ctrl);
700 static irqreturn_t flexcan_irq(int irq, void *dev_id)
702 struct net_device *dev = dev_id;
703 struct net_device_stats *stats = &dev->stats;
704 struct flexcan_priv *priv = netdev_priv(dev);
705 struct flexcan_regs __iomem *regs = priv->base;
706 u32 reg_iflag1, reg_esr;
708 reg_iflag1 = flexcan_read(®s->iflag1);
709 reg_esr = flexcan_read(®s->esr);
710 /* ACK all bus error and state change IRQ sources */
711 if (reg_esr & FLEXCAN_ESR_ALL_INT)
712 flexcan_write(reg_esr & FLEXCAN_ESR_ALL_INT, ®s->esr);
715 * schedule NAPI in case of:
718 * - bus error IRQ and bus error reporting is activated
720 if ((reg_iflag1 & FLEXCAN_IFLAG_RX_FIFO_AVAILABLE) ||
721 (reg_esr & FLEXCAN_ESR_ERR_STATE) ||
722 flexcan_has_and_handle_berr(priv, reg_esr)) {
724 * The error bits are cleared on read,
725 * save them for later use.
727 priv->reg_esr = reg_esr & FLEXCAN_ESR_ERR_BUS;
728 flexcan_write(FLEXCAN_IFLAG_DEFAULT &
729 ~FLEXCAN_IFLAG_RX_FIFO_AVAILABLE, ®s->imask1);
730 flexcan_write(priv->reg_ctrl_default & ~FLEXCAN_CTRL_ERR_ALL,
732 napi_schedule(&priv->napi);
736 if (reg_iflag1 & FLEXCAN_IFLAG_RX_FIFO_OVERFLOW) {
737 flexcan_write(FLEXCAN_IFLAG_RX_FIFO_OVERFLOW, ®s->iflag1);
738 dev->stats.rx_over_errors++;
739 dev->stats.rx_errors++;
742 /* transmission complete interrupt */
743 if (reg_iflag1 & (1 << FLEXCAN_TX_BUF_ID)) {
744 stats->tx_bytes += can_get_echo_skb(dev, 0);
746 can_led_event(dev, CAN_LED_EVENT_TX);
747 flexcan_write((1 << FLEXCAN_TX_BUF_ID), ®s->iflag1);
748 netif_wake_queue(dev);
754 static void flexcan_set_bittiming(struct net_device *dev)
756 const struct flexcan_priv *priv = netdev_priv(dev);
757 const struct can_bittiming *bt = &priv->can.bittiming;
758 struct flexcan_regs __iomem *regs = priv->base;
761 reg = flexcan_read(®s->ctrl);
762 reg &= ~(FLEXCAN_CTRL_PRESDIV(0xff) |
763 FLEXCAN_CTRL_RJW(0x3) |
764 FLEXCAN_CTRL_PSEG1(0x7) |
765 FLEXCAN_CTRL_PSEG2(0x7) |
766 FLEXCAN_CTRL_PROPSEG(0x7) |
771 reg |= FLEXCAN_CTRL_PRESDIV(bt->brp - 1) |
772 FLEXCAN_CTRL_PSEG1(bt->phase_seg1 - 1) |
773 FLEXCAN_CTRL_PSEG2(bt->phase_seg2 - 1) |
774 FLEXCAN_CTRL_RJW(bt->sjw - 1) |
775 FLEXCAN_CTRL_PROPSEG(bt->prop_seg - 1);
777 if (priv->can.ctrlmode & CAN_CTRLMODE_LOOPBACK)
778 reg |= FLEXCAN_CTRL_LPB;
779 if (priv->can.ctrlmode & CAN_CTRLMODE_LISTENONLY)
780 reg |= FLEXCAN_CTRL_LOM;
781 if (priv->can.ctrlmode & CAN_CTRLMODE_3_SAMPLES)
782 reg |= FLEXCAN_CTRL_SMP;
784 netdev_info(dev, "writing ctrl=0x%08x\n", reg);
785 flexcan_write(reg, ®s->ctrl);
787 /* print chip status */
788 netdev_dbg(dev, "%s: mcr=0x%08x ctrl=0x%08x\n", __func__,
789 flexcan_read(®s->mcr), flexcan_read(®s->ctrl));
795 * this functions is entered with clocks enabled
798 static int flexcan_chip_start(struct net_device *dev)
800 struct flexcan_priv *priv = netdev_priv(dev);
801 struct flexcan_regs __iomem *regs = priv->base;
803 u32 reg_mcr, reg_ctrl;
806 err = flexcan_chip_enable(priv);
811 err = flexcan_chip_softreset(priv);
813 goto out_chip_disable;
815 flexcan_set_bittiming(dev);
823 * only supervisor access
829 reg_mcr = flexcan_read(®s->mcr);
830 reg_mcr &= ~FLEXCAN_MCR_MAXMB(0xff);
831 reg_mcr |= FLEXCAN_MCR_FRZ | FLEXCAN_MCR_FEN | FLEXCAN_MCR_HALT |
832 FLEXCAN_MCR_SUPV | FLEXCAN_MCR_WRN_EN |
833 FLEXCAN_MCR_IDAM_C | FLEXCAN_MCR_SRX_DIS |
834 FLEXCAN_MCR_MAXMB(FLEXCAN_TX_BUF_ID);
835 netdev_dbg(dev, "%s: writing mcr=0x%08x", __func__, reg_mcr);
836 flexcan_write(reg_mcr, ®s->mcr);
841 * disable timer sync feature
843 * disable auto busoff recovery
844 * transmit lowest buffer first
846 * enable tx and rx warning interrupt
847 * enable bus off interrupt
848 * (== FLEXCAN_CTRL_ERR_STATE)
850 reg_ctrl = flexcan_read(®s->ctrl);
851 reg_ctrl &= ~FLEXCAN_CTRL_TSYN;
852 reg_ctrl |= FLEXCAN_CTRL_BOFF_REC | FLEXCAN_CTRL_LBUF |
853 FLEXCAN_CTRL_ERR_STATE;
855 * enable the "error interrupt" (FLEXCAN_CTRL_ERR_MSK),
856 * on most Flexcan cores, too. Otherwise we don't get
857 * any error warning or passive interrupts.
859 if (priv->devtype_data->features & FLEXCAN_HAS_BROKEN_ERR_STATE ||
860 priv->can.ctrlmode & CAN_CTRLMODE_BERR_REPORTING)
861 reg_ctrl |= FLEXCAN_CTRL_ERR_MSK;
863 /* save for later use */
864 priv->reg_ctrl_default = reg_ctrl;
865 netdev_dbg(dev, "%s: writing ctrl=0x%08x", __func__, reg_ctrl);
866 flexcan_write(reg_ctrl, ®s->ctrl);
868 /* Abort any pending TX, mark Mailbox as INACTIVE */
869 flexcan_write(FLEXCAN_MB_CNT_CODE(0x4),
870 ®s->cantxfg[FLEXCAN_TX_BUF_ID].can_ctrl);
872 /* acceptance mask/acceptance code (accept everything) */
873 flexcan_write(0x0, ®s->rxgmask);
874 flexcan_write(0x0, ®s->rx14mask);
875 flexcan_write(0x0, ®s->rx15mask);
877 if (priv->devtype_data->features & FLEXCAN_HAS_V10_FEATURES)
878 flexcan_write(0x0, ®s->rxfgmask);
880 err = flexcan_transceiver_enable(priv);
882 goto out_chip_disable;
884 /* synchronize with the can bus */
885 err = flexcan_chip_unfreeze(priv);
887 goto out_transceiver_disable;
889 priv->can.state = CAN_STATE_ERROR_ACTIVE;
891 /* enable FIFO interrupts */
892 flexcan_write(FLEXCAN_IFLAG_DEFAULT, ®s->imask1);
894 /* print chip status */
895 netdev_dbg(dev, "%s: reading mcr=0x%08x ctrl=0x%08x\n", __func__,
896 flexcan_read(®s->mcr), flexcan_read(®s->ctrl));
900 out_transceiver_disable:
901 flexcan_transceiver_disable(priv);
903 flexcan_chip_disable(priv);
910 * this functions is entered with clocks enabled
913 static void flexcan_chip_stop(struct net_device *dev)
915 struct flexcan_priv *priv = netdev_priv(dev);
916 struct flexcan_regs __iomem *regs = priv->base;
918 /* freeze + disable module */
919 flexcan_chip_freeze(priv);
920 flexcan_chip_disable(priv);
922 /* Disable all interrupts */
923 flexcan_write(0, ®s->imask1);
924 flexcan_write(priv->reg_ctrl_default & ~FLEXCAN_CTRL_ERR_ALL,
927 flexcan_transceiver_disable(priv);
928 priv->can.state = CAN_STATE_STOPPED;
933 static int flexcan_open(struct net_device *dev)
935 struct flexcan_priv *priv = netdev_priv(dev);
938 err = clk_prepare_enable(priv->clk_ipg);
942 err = clk_prepare_enable(priv->clk_per);
944 goto out_disable_ipg;
946 err = open_candev(dev);
948 goto out_disable_per;
950 err = request_irq(dev->irq, flexcan_irq, IRQF_SHARED, dev->name, dev);
954 /* start chip and queuing */
955 err = flexcan_chip_start(dev);
959 can_led_event(dev, CAN_LED_EVENT_OPEN);
961 napi_enable(&priv->napi);
962 netif_start_queue(dev);
967 free_irq(dev->irq, dev);
971 clk_disable_unprepare(priv->clk_per);
973 clk_disable_unprepare(priv->clk_ipg);
978 static int flexcan_close(struct net_device *dev)
980 struct flexcan_priv *priv = netdev_priv(dev);
982 netif_stop_queue(dev);
983 napi_disable(&priv->napi);
984 flexcan_chip_stop(dev);
986 free_irq(dev->irq, dev);
987 clk_disable_unprepare(priv->clk_per);
988 clk_disable_unprepare(priv->clk_ipg);
992 can_led_event(dev, CAN_LED_EVENT_STOP);
997 static int flexcan_set_mode(struct net_device *dev, enum can_mode mode)
1002 case CAN_MODE_START:
1003 err = flexcan_chip_start(dev);
1007 netif_wake_queue(dev);
1017 static const struct net_device_ops flexcan_netdev_ops = {
1018 .ndo_open = flexcan_open,
1019 .ndo_stop = flexcan_close,
1020 .ndo_start_xmit = flexcan_start_xmit,
1021 .ndo_change_mtu = can_change_mtu,
1024 static int register_flexcandev(struct net_device *dev)
1026 struct flexcan_priv *priv = netdev_priv(dev);
1027 struct flexcan_regs __iomem *regs = priv->base;
1030 err = clk_prepare_enable(priv->clk_ipg);
1034 err = clk_prepare_enable(priv->clk_per);
1036 goto out_disable_ipg;
1038 /* select "bus clock", chip must be disabled */
1039 err = flexcan_chip_disable(priv);
1041 goto out_disable_per;
1042 reg = flexcan_read(®s->ctrl);
1043 reg |= FLEXCAN_CTRL_CLK_SRC;
1044 flexcan_write(reg, ®s->ctrl);
1046 err = flexcan_chip_enable(priv);
1048 goto out_chip_disable;
1050 /* set freeze, halt and activate FIFO, restrict register access */
1051 reg = flexcan_read(®s->mcr);
1052 reg |= FLEXCAN_MCR_FRZ | FLEXCAN_MCR_HALT |
1053 FLEXCAN_MCR_FEN | FLEXCAN_MCR_SUPV;
1054 flexcan_write(reg, ®s->mcr);
1057 * Currently we only support newer versions of this core
1058 * featuring a RX FIFO. Older cores found on some Coldfire
1059 * derivates are not yet supported.
1061 reg = flexcan_read(®s->mcr);
1062 if (!(reg & FLEXCAN_MCR_FEN)) {
1063 netdev_err(dev, "Could not enable RX FIFO, unsupported core\n");
1065 goto out_chip_disable;
1068 err = register_candev(dev);
1070 /* disable core and turn off clocks */
1072 flexcan_chip_disable(priv);
1074 clk_disable_unprepare(priv->clk_per);
1076 clk_disable_unprepare(priv->clk_ipg);
1081 static void unregister_flexcandev(struct net_device *dev)
1083 unregister_candev(dev);
1086 static const struct of_device_id flexcan_of_match[] = {
1087 { .compatible = "fsl,imx6q-flexcan", .data = &fsl_imx6q_devtype_data, },
1088 { .compatible = "fsl,imx28-flexcan", .data = &fsl_imx28_devtype_data, },
1089 { .compatible = "fsl,p1010-flexcan", .data = &fsl_p1010_devtype_data, },
1092 MODULE_DEVICE_TABLE(of, flexcan_of_match);
1094 static const struct platform_device_id flexcan_id_table[] = {
1095 { .name = "flexcan", .driver_data = (kernel_ulong_t)&fsl_p1010_devtype_data, },
1098 MODULE_DEVICE_TABLE(platform, flexcan_id_table);
1100 static int flexcan_probe(struct platform_device *pdev)
1102 const struct of_device_id *of_id;
1103 const struct flexcan_devtype_data *devtype_data;
1104 struct net_device *dev;
1105 struct flexcan_priv *priv;
1106 struct resource *mem;
1107 struct clk *clk_ipg = NULL, *clk_per = NULL;
1112 if (pdev->dev.of_node)
1113 of_property_read_u32(pdev->dev.of_node,
1114 "clock-frequency", &clock_freq);
1117 clk_ipg = devm_clk_get(&pdev->dev, "ipg");
1118 if (IS_ERR(clk_ipg)) {
1119 dev_err(&pdev->dev, "no ipg clock defined\n");
1120 return PTR_ERR(clk_ipg);
1123 clk_per = devm_clk_get(&pdev->dev, "per");
1124 if (IS_ERR(clk_per)) {
1125 dev_err(&pdev->dev, "no per clock defined\n");
1126 return PTR_ERR(clk_per);
1128 clock_freq = clk_get_rate(clk_per);
1131 mem = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1132 irq = platform_get_irq(pdev, 0);
1136 base = devm_ioremap_resource(&pdev->dev, mem);
1138 return PTR_ERR(base);
1140 of_id = of_match_device(flexcan_of_match, &pdev->dev);
1142 devtype_data = of_id->data;
1143 } else if (platform_get_device_id(pdev)->driver_data) {
1144 devtype_data = (struct flexcan_devtype_data *)
1145 platform_get_device_id(pdev)->driver_data;
1150 dev = alloc_candev(sizeof(struct flexcan_priv), 1);
1154 dev->netdev_ops = &flexcan_netdev_ops;
1156 dev->flags |= IFF_ECHO;
1158 priv = netdev_priv(dev);
1159 priv->can.clock.freq = clock_freq;
1160 priv->can.bittiming_const = &flexcan_bittiming_const;
1161 priv->can.do_set_mode = flexcan_set_mode;
1162 priv->can.do_get_berr_counter = flexcan_get_berr_counter;
1163 priv->can.ctrlmode_supported = CAN_CTRLMODE_LOOPBACK |
1164 CAN_CTRLMODE_LISTENONLY | CAN_CTRLMODE_3_SAMPLES |
1165 CAN_CTRLMODE_BERR_REPORTING;
1168 priv->clk_ipg = clk_ipg;
1169 priv->clk_per = clk_per;
1170 priv->pdata = dev_get_platdata(&pdev->dev);
1171 priv->devtype_data = devtype_data;
1173 priv->reg_xceiver = devm_regulator_get(&pdev->dev, "xceiver");
1174 if (IS_ERR(priv->reg_xceiver))
1175 priv->reg_xceiver = NULL;
1177 netif_napi_add(dev, &priv->napi, flexcan_poll, FLEXCAN_NAPI_WEIGHT);
1179 platform_set_drvdata(pdev, dev);
1180 SET_NETDEV_DEV(dev, &pdev->dev);
1182 err = register_flexcandev(dev);
1184 dev_err(&pdev->dev, "registering netdev failed\n");
1185 goto failed_register;
1188 devm_can_led_init(dev);
1190 dev_info(&pdev->dev, "device registered (reg_base=%p, irq=%d)\n",
1191 priv->base, dev->irq);
1200 static int flexcan_remove(struct platform_device *pdev)
1202 struct net_device *dev = platform_get_drvdata(pdev);
1203 struct flexcan_priv *priv = netdev_priv(dev);
1205 unregister_flexcandev(dev);
1206 netif_napi_del(&priv->napi);
1212 static int __maybe_unused flexcan_suspend(struct device *device)
1214 struct net_device *dev = dev_get_drvdata(device);
1215 struct flexcan_priv *priv = netdev_priv(dev);
1218 err = flexcan_chip_disable(priv);
1222 if (netif_running(dev)) {
1223 netif_stop_queue(dev);
1224 netif_device_detach(dev);
1226 priv->can.state = CAN_STATE_SLEEPING;
1231 static int __maybe_unused flexcan_resume(struct device *device)
1233 struct net_device *dev = dev_get_drvdata(device);
1234 struct flexcan_priv *priv = netdev_priv(dev);
1236 priv->can.state = CAN_STATE_ERROR_ACTIVE;
1237 if (netif_running(dev)) {
1238 netif_device_attach(dev);
1239 netif_start_queue(dev);
1241 return flexcan_chip_enable(priv);
1244 static SIMPLE_DEV_PM_OPS(flexcan_pm_ops, flexcan_suspend, flexcan_resume);
1246 static struct platform_driver flexcan_driver = {
1249 .owner = THIS_MODULE,
1250 .pm = &flexcan_pm_ops,
1251 .of_match_table = flexcan_of_match,
1253 .probe = flexcan_probe,
1254 .remove = flexcan_remove,
1255 .id_table = flexcan_id_table,
1258 module_platform_driver(flexcan_driver);
1260 MODULE_AUTHOR("Sascha Hauer <kernel@pengutronix.de>, "
1261 "Marc Kleine-Budde <kernel@pengutronix.de>");
1262 MODULE_LICENSE("GPL v2");
1263 MODULE_DESCRIPTION("CAN port driver for flexcan based chip");