2 * flexcan.c - FLEXCAN CAN controller driver
4 * Copyright (c) 2005-2006 Varma Electronics Oy
5 * Copyright (c) 2009 Sascha Hauer, Pengutronix
6 * Copyright (c) 2010 Marc Kleine-Budde, Pengutronix
8 * Based on code originally by Andrey Volkov <avolkov@varma-el.com>
11 * This program is free software; you can redistribute it and/or
12 * modify it under the terms of the GNU General Public License as
13 * published by the Free Software Foundation version 2.
15 * This program is distributed in the hope that it will be useful,
16 * but WITHOUT ANY WARRANTY; without even the implied warranty of
17 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
18 * GNU General Public License for more details.
22 #include <linux/netdevice.h>
23 #include <linux/can.h>
24 #include <linux/can/dev.h>
25 #include <linux/can/error.h>
26 #include <linux/can/led.h>
27 #include <linux/clk.h>
28 #include <linux/delay.h>
29 #include <linux/if_arp.h>
30 #include <linux/if_ether.h>
31 #include <linux/interrupt.h>
33 #include <linux/kernel.h>
34 #include <linux/list.h>
35 #include <linux/module.h>
37 #include <linux/of_device.h>
38 #include <linux/platform_device.h>
39 #include <linux/regulator/consumer.h>
41 #define DRV_NAME "flexcan"
43 /* 8 for RX fifo and 2 error handling */
44 #define FLEXCAN_NAPI_WEIGHT (8 + 2)
46 /* FLEXCAN module configuration register (CANMCR) bits */
47 #define FLEXCAN_MCR_MDIS BIT(31)
48 #define FLEXCAN_MCR_FRZ BIT(30)
49 #define FLEXCAN_MCR_FEN BIT(29)
50 #define FLEXCAN_MCR_HALT BIT(28)
51 #define FLEXCAN_MCR_NOT_RDY BIT(27)
52 #define FLEXCAN_MCR_WAK_MSK BIT(26)
53 #define FLEXCAN_MCR_SOFTRST BIT(25)
54 #define FLEXCAN_MCR_FRZ_ACK BIT(24)
55 #define FLEXCAN_MCR_SUPV BIT(23)
56 #define FLEXCAN_MCR_SLF_WAK BIT(22)
57 #define FLEXCAN_MCR_WRN_EN BIT(21)
58 #define FLEXCAN_MCR_LPM_ACK BIT(20)
59 #define FLEXCAN_MCR_WAK_SRC BIT(19)
60 #define FLEXCAN_MCR_DOZE BIT(18)
61 #define FLEXCAN_MCR_SRX_DIS BIT(17)
62 #define FLEXCAN_MCR_BCC BIT(16)
63 #define FLEXCAN_MCR_LPRIO_EN BIT(13)
64 #define FLEXCAN_MCR_AEN BIT(12)
65 #define FLEXCAN_MCR_MAXMB(x) ((x) & 0x7f)
66 #define FLEXCAN_MCR_IDAM_A (0x0 << 8)
67 #define FLEXCAN_MCR_IDAM_B (0x1 << 8)
68 #define FLEXCAN_MCR_IDAM_C (0x2 << 8)
69 #define FLEXCAN_MCR_IDAM_D (0x3 << 8)
71 /* FLEXCAN control register (CANCTRL) bits */
72 #define FLEXCAN_CTRL_PRESDIV(x) (((x) & 0xff) << 24)
73 #define FLEXCAN_CTRL_RJW(x) (((x) & 0x03) << 22)
74 #define FLEXCAN_CTRL_PSEG1(x) (((x) & 0x07) << 19)
75 #define FLEXCAN_CTRL_PSEG2(x) (((x) & 0x07) << 16)
76 #define FLEXCAN_CTRL_BOFF_MSK BIT(15)
77 #define FLEXCAN_CTRL_ERR_MSK BIT(14)
78 #define FLEXCAN_CTRL_CLK_SRC BIT(13)
79 #define FLEXCAN_CTRL_LPB BIT(12)
80 #define FLEXCAN_CTRL_TWRN_MSK BIT(11)
81 #define FLEXCAN_CTRL_RWRN_MSK BIT(10)
82 #define FLEXCAN_CTRL_SMP BIT(7)
83 #define FLEXCAN_CTRL_BOFF_REC BIT(6)
84 #define FLEXCAN_CTRL_TSYN BIT(5)
85 #define FLEXCAN_CTRL_LBUF BIT(4)
86 #define FLEXCAN_CTRL_LOM BIT(3)
87 #define FLEXCAN_CTRL_PROPSEG(x) ((x) & 0x07)
88 #define FLEXCAN_CTRL_ERR_BUS (FLEXCAN_CTRL_ERR_MSK)
89 #define FLEXCAN_CTRL_ERR_STATE \
90 (FLEXCAN_CTRL_TWRN_MSK | FLEXCAN_CTRL_RWRN_MSK | \
91 FLEXCAN_CTRL_BOFF_MSK)
92 #define FLEXCAN_CTRL_ERR_ALL \
93 (FLEXCAN_CTRL_ERR_BUS | FLEXCAN_CTRL_ERR_STATE)
95 /* FLEXCAN control register 2 (CTRL2) bits */
96 #define FLEXCAN_CTRL2_ECRWRE BIT(29)
97 #define FLEXCAN_CTRL2_WRMFRZ BIT(28)
98 #define FLEXCAN_CTRL2_RFFN(x) (((x) & 0x0f) << 24)
99 #define FLEXCAN_CTRL2_TASD(x) (((x) & 0x1f) << 19)
100 #define FLEXCAN_CTRL2_MRP BIT(18)
101 #define FLEXCAN_CTRL2_RRS BIT(17)
102 #define FLEXCAN_CTRL2_EACEN BIT(16)
104 /* FLEXCAN memory error control register (MECR) bits */
105 #define FLEXCAN_MECR_ECRWRDIS BIT(31)
106 #define FLEXCAN_MECR_HANCEI_MSK BIT(19)
107 #define FLEXCAN_MECR_FANCEI_MSK BIT(18)
108 #define FLEXCAN_MECR_CEI_MSK BIT(16)
109 #define FLEXCAN_MECR_HAERRIE BIT(15)
110 #define FLEXCAN_MECR_FAERRIE BIT(14)
111 #define FLEXCAN_MECR_EXTERRIE BIT(13)
112 #define FLEXCAN_MECR_RERRDIS BIT(9)
113 #define FLEXCAN_MECR_ECCDIS BIT(8)
114 #define FLEXCAN_MECR_NCEFAFRZ BIT(7)
116 /* FLEXCAN error and status register (ESR) bits */
117 #define FLEXCAN_ESR_TWRN_INT BIT(17)
118 #define FLEXCAN_ESR_RWRN_INT BIT(16)
119 #define FLEXCAN_ESR_BIT1_ERR BIT(15)
120 #define FLEXCAN_ESR_BIT0_ERR BIT(14)
121 #define FLEXCAN_ESR_ACK_ERR BIT(13)
122 #define FLEXCAN_ESR_CRC_ERR BIT(12)
123 #define FLEXCAN_ESR_FRM_ERR BIT(11)
124 #define FLEXCAN_ESR_STF_ERR BIT(10)
125 #define FLEXCAN_ESR_TX_WRN BIT(9)
126 #define FLEXCAN_ESR_RX_WRN BIT(8)
127 #define FLEXCAN_ESR_IDLE BIT(7)
128 #define FLEXCAN_ESR_TXRX BIT(6)
129 #define FLEXCAN_EST_FLT_CONF_SHIFT (4)
130 #define FLEXCAN_ESR_FLT_CONF_MASK (0x3 << FLEXCAN_EST_FLT_CONF_SHIFT)
131 #define FLEXCAN_ESR_FLT_CONF_ACTIVE (0x0 << FLEXCAN_EST_FLT_CONF_SHIFT)
132 #define FLEXCAN_ESR_FLT_CONF_PASSIVE (0x1 << FLEXCAN_EST_FLT_CONF_SHIFT)
133 #define FLEXCAN_ESR_BOFF_INT BIT(2)
134 #define FLEXCAN_ESR_ERR_INT BIT(1)
135 #define FLEXCAN_ESR_WAK_INT BIT(0)
136 #define FLEXCAN_ESR_ERR_BUS \
137 (FLEXCAN_ESR_BIT1_ERR | FLEXCAN_ESR_BIT0_ERR | \
138 FLEXCAN_ESR_ACK_ERR | FLEXCAN_ESR_CRC_ERR | \
139 FLEXCAN_ESR_FRM_ERR | FLEXCAN_ESR_STF_ERR)
140 #define FLEXCAN_ESR_ERR_STATE \
141 (FLEXCAN_ESR_TWRN_INT | FLEXCAN_ESR_RWRN_INT | FLEXCAN_ESR_BOFF_INT)
142 #define FLEXCAN_ESR_ERR_ALL \
143 (FLEXCAN_ESR_ERR_BUS | FLEXCAN_ESR_ERR_STATE)
144 #define FLEXCAN_ESR_ALL_INT \
145 (FLEXCAN_ESR_TWRN_INT | FLEXCAN_ESR_RWRN_INT | \
146 FLEXCAN_ESR_BOFF_INT | FLEXCAN_ESR_ERR_INT)
148 /* FLEXCAN interrupt flag register (IFLAG) bits */
149 /* Errata ERR005829 step7: Reserve first valid MB */
150 #define FLEXCAN_TX_BUF_RESERVED 8
151 #define FLEXCAN_TX_BUF_ID 9
152 #define FLEXCAN_IFLAG_BUF(x) BIT(x)
153 #define FLEXCAN_IFLAG_RX_FIFO_OVERFLOW BIT(7)
154 #define FLEXCAN_IFLAG_RX_FIFO_WARN BIT(6)
155 #define FLEXCAN_IFLAG_RX_FIFO_AVAILABLE BIT(5)
156 #define FLEXCAN_IFLAG_DEFAULT \
157 (FLEXCAN_IFLAG_RX_FIFO_OVERFLOW | FLEXCAN_IFLAG_RX_FIFO_AVAILABLE | \
158 FLEXCAN_IFLAG_BUF(FLEXCAN_TX_BUF_ID))
160 /* FLEXCAN message buffers */
161 #define FLEXCAN_MB_CODE_RX_INACTIVE (0x0 << 24)
162 #define FLEXCAN_MB_CODE_RX_EMPTY (0x4 << 24)
163 #define FLEXCAN_MB_CODE_RX_FULL (0x2 << 24)
164 #define FLEXCAN_MB_CODE_RX_OVERRUN (0x6 << 24)
165 #define FLEXCAN_MB_CODE_RX_RANSWER (0xa << 24)
167 #define FLEXCAN_MB_CODE_TX_INACTIVE (0x8 << 24)
168 #define FLEXCAN_MB_CODE_TX_ABORT (0x9 << 24)
169 #define FLEXCAN_MB_CODE_TX_DATA (0xc << 24)
170 #define FLEXCAN_MB_CODE_TX_TANSWER (0xe << 24)
172 #define FLEXCAN_MB_CNT_SRR BIT(22)
173 #define FLEXCAN_MB_CNT_IDE BIT(21)
174 #define FLEXCAN_MB_CNT_RTR BIT(20)
175 #define FLEXCAN_MB_CNT_LENGTH(x) (((x) & 0xf) << 16)
176 #define FLEXCAN_MB_CNT_TIMESTAMP(x) ((x) & 0xffff)
178 #define FLEXCAN_TIMEOUT_US (50)
180 /* FLEXCAN hardware feature flags
182 * Below is some version info we got:
183 * SOC Version IP-Version Glitch- [TR]WRN_INT Memory err RTR re-
184 * Filter? connected? detection ception in MB
185 * MX25 FlexCAN2 03.00.00.00 no no no no
186 * MX28 FlexCAN2 03.00.04.00 yes yes no no
187 * MX35 FlexCAN2 03.00.00.00 no no no no
188 * MX53 FlexCAN2 03.00.00.00 yes no no no
189 * MX6s FlexCAN3 10.00.12.00 yes yes no yes
190 * VF610 FlexCAN3 ? no yes yes yes?
192 * Some SOCs do not have the RX_WARN & TX_WARN interrupt line connected.
194 #define FLEXCAN_HAS_V10_FEATURES BIT(1) /* For core version >= 10 */
195 #define FLEXCAN_HAS_BROKEN_ERR_STATE BIT(2) /* [TR]WRN_INT not connected */
196 #define FLEXCAN_HAS_MECR_FEATURES BIT(3) /* Memory error detection */
198 /* Structure of the message buffer */
205 /* Structure of the hardware registers */
206 struct flexcan_regs {
209 u32 timer; /* 0x08 */
210 u32 _reserved1; /* 0x0c */
211 u32 rxgmask; /* 0x10 */
212 u32 rx14mask; /* 0x14 */
213 u32 rx15mask; /* 0x18 */
216 u32 imask2; /* 0x24 */
217 u32 imask1; /* 0x28 */
218 u32 iflag2; /* 0x2c */
219 u32 iflag1; /* 0x30 */
220 u32 ctrl2; /* 0x34 */
222 u32 imeur; /* 0x3c */
225 u32 rxfgmask; /* 0x48 */
226 u32 rxfir; /* 0x4c */
227 u32 _reserved3[12]; /* 0x50 */
228 struct flexcan_mb cantxfg[64]; /* 0x80 */
231 * 0x080...0x08f 0 RX message buffer
232 * 0x090...0x0df 1-5 reserverd
233 * 0x0e0...0x0ff 6-7 8 entry ID table
234 * (mx25, mx28, mx35, mx53)
235 * 0x0e0...0x2df 6-7..37 8..128 entry ID table
236 * size conf'ed via ctrl2::RFFN
240 u32 mecr; /* 0xae0 */
241 u32 erriar; /* 0xae4 */
242 u32 erridpr; /* 0xae8 */
243 u32 errippr; /* 0xaec */
244 u32 rerrar; /* 0xaf0 */
245 u32 rerrdr; /* 0xaf4 */
246 u32 rerrsynr; /* 0xaf8 */
247 u32 errsr; /* 0xafc */
250 struct flexcan_devtype_data {
251 u32 features; /* hardware controller features */
254 struct flexcan_priv {
256 struct napi_struct napi;
260 u32 reg_ctrl_default;
264 struct flexcan_platform_data *pdata;
265 const struct flexcan_devtype_data *devtype_data;
266 struct regulator *reg_xceiver;
269 static struct flexcan_devtype_data fsl_p1010_devtype_data = {
270 .features = FLEXCAN_HAS_BROKEN_ERR_STATE,
273 static struct flexcan_devtype_data fsl_imx28_devtype_data;
275 static struct flexcan_devtype_data fsl_imx6q_devtype_data = {
276 .features = FLEXCAN_HAS_V10_FEATURES,
279 static struct flexcan_devtype_data fsl_vf610_devtype_data = {
280 .features = FLEXCAN_HAS_V10_FEATURES | FLEXCAN_HAS_MECR_FEATURES,
283 static const struct can_bittiming_const flexcan_bittiming_const = {
295 /* Abstract off the read/write for arm versus ppc. This
296 * assumes that PPC uses big-endian registers and everything
297 * else uses little-endian registers, independent of CPU
300 #if defined(CONFIG_PPC)
301 static inline u32 flexcan_read(void __iomem *addr)
303 return in_be32(addr);
306 static inline void flexcan_write(u32 val, void __iomem *addr)
311 static inline u32 flexcan_read(void __iomem *addr)
316 static inline void flexcan_write(u32 val, void __iomem *addr)
322 static inline int flexcan_transceiver_enable(const struct flexcan_priv *priv)
324 if (!priv->reg_xceiver)
327 return regulator_enable(priv->reg_xceiver);
330 static inline int flexcan_transceiver_disable(const struct flexcan_priv *priv)
332 if (!priv->reg_xceiver)
335 return regulator_disable(priv->reg_xceiver);
338 static inline int flexcan_has_and_handle_berr(const struct flexcan_priv *priv,
341 return (priv->can.ctrlmode & CAN_CTRLMODE_BERR_REPORTING) &&
342 (reg_esr & FLEXCAN_ESR_ERR_BUS);
345 static int flexcan_chip_enable(struct flexcan_priv *priv)
347 struct flexcan_regs __iomem *regs = priv->base;
348 unsigned int timeout = FLEXCAN_TIMEOUT_US / 10;
351 reg = flexcan_read(®s->mcr);
352 reg &= ~FLEXCAN_MCR_MDIS;
353 flexcan_write(reg, ®s->mcr);
355 while (timeout-- && (flexcan_read(®s->mcr) & FLEXCAN_MCR_LPM_ACK))
358 if (flexcan_read(®s->mcr) & FLEXCAN_MCR_LPM_ACK)
364 static int flexcan_chip_disable(struct flexcan_priv *priv)
366 struct flexcan_regs __iomem *regs = priv->base;
367 unsigned int timeout = FLEXCAN_TIMEOUT_US / 10;
370 reg = flexcan_read(®s->mcr);
371 reg |= FLEXCAN_MCR_MDIS;
372 flexcan_write(reg, ®s->mcr);
374 while (timeout-- && !(flexcan_read(®s->mcr) & FLEXCAN_MCR_LPM_ACK))
377 if (!(flexcan_read(®s->mcr) & FLEXCAN_MCR_LPM_ACK))
383 static int flexcan_chip_freeze(struct flexcan_priv *priv)
385 struct flexcan_regs __iomem *regs = priv->base;
386 unsigned int timeout = 1000 * 1000 * 10 / priv->can.bittiming.bitrate;
389 reg = flexcan_read(®s->mcr);
390 reg |= FLEXCAN_MCR_HALT;
391 flexcan_write(reg, ®s->mcr);
393 while (timeout-- && !(flexcan_read(®s->mcr) & FLEXCAN_MCR_FRZ_ACK))
396 if (!(flexcan_read(®s->mcr) & FLEXCAN_MCR_FRZ_ACK))
402 static int flexcan_chip_unfreeze(struct flexcan_priv *priv)
404 struct flexcan_regs __iomem *regs = priv->base;
405 unsigned int timeout = FLEXCAN_TIMEOUT_US / 10;
408 reg = flexcan_read(®s->mcr);
409 reg &= ~FLEXCAN_MCR_HALT;
410 flexcan_write(reg, ®s->mcr);
412 while (timeout-- && (flexcan_read(®s->mcr) & FLEXCAN_MCR_FRZ_ACK))
415 if (flexcan_read(®s->mcr) & FLEXCAN_MCR_FRZ_ACK)
421 static int flexcan_chip_softreset(struct flexcan_priv *priv)
423 struct flexcan_regs __iomem *regs = priv->base;
424 unsigned int timeout = FLEXCAN_TIMEOUT_US / 10;
426 flexcan_write(FLEXCAN_MCR_SOFTRST, ®s->mcr);
427 while (timeout-- && (flexcan_read(®s->mcr) & FLEXCAN_MCR_SOFTRST))
430 if (flexcan_read(®s->mcr) & FLEXCAN_MCR_SOFTRST)
436 static int __flexcan_get_berr_counter(const struct net_device *dev,
437 struct can_berr_counter *bec)
439 const struct flexcan_priv *priv = netdev_priv(dev);
440 struct flexcan_regs __iomem *regs = priv->base;
441 u32 reg = flexcan_read(®s->ecr);
443 bec->txerr = (reg >> 0) & 0xff;
444 bec->rxerr = (reg >> 8) & 0xff;
449 static int flexcan_get_berr_counter(const struct net_device *dev,
450 struct can_berr_counter *bec)
452 const struct flexcan_priv *priv = netdev_priv(dev);
455 err = clk_prepare_enable(priv->clk_ipg);
459 err = clk_prepare_enable(priv->clk_per);
461 goto out_disable_ipg;
463 err = __flexcan_get_berr_counter(dev, bec);
465 clk_disable_unprepare(priv->clk_per);
467 clk_disable_unprepare(priv->clk_ipg);
472 static int flexcan_start_xmit(struct sk_buff *skb, struct net_device *dev)
474 const struct flexcan_priv *priv = netdev_priv(dev);
475 struct flexcan_regs __iomem *regs = priv->base;
476 struct can_frame *cf = (struct can_frame *)skb->data;
479 u32 ctrl = FLEXCAN_MB_CODE_TX_DATA | (cf->can_dlc << 16);
481 if (can_dropped_invalid_skb(dev, skb))
484 netif_stop_queue(dev);
486 if (cf->can_id & CAN_EFF_FLAG) {
487 can_id = cf->can_id & CAN_EFF_MASK;
488 ctrl |= FLEXCAN_MB_CNT_IDE | FLEXCAN_MB_CNT_SRR;
490 can_id = (cf->can_id & CAN_SFF_MASK) << 18;
493 if (cf->can_id & CAN_RTR_FLAG)
494 ctrl |= FLEXCAN_MB_CNT_RTR;
496 if (cf->can_dlc > 0) {
497 data = be32_to_cpup((__be32 *)&cf->data[0]);
498 flexcan_write(data, ®s->cantxfg[FLEXCAN_TX_BUF_ID].data[0]);
500 if (cf->can_dlc > 3) {
501 data = be32_to_cpup((__be32 *)&cf->data[4]);
502 flexcan_write(data, ®s->cantxfg[FLEXCAN_TX_BUF_ID].data[1]);
505 can_put_echo_skb(skb, dev, 0);
507 flexcan_write(can_id, ®s->cantxfg[FLEXCAN_TX_BUF_ID].can_id);
508 flexcan_write(ctrl, ®s->cantxfg[FLEXCAN_TX_BUF_ID].can_ctrl);
510 /* Errata ERR005829 step8:
511 * Write twice INACTIVE(0x8) code to first MB.
513 flexcan_write(FLEXCAN_MB_CODE_TX_INACTIVE,
514 ®s->cantxfg[FLEXCAN_TX_BUF_RESERVED].can_ctrl);
515 flexcan_write(FLEXCAN_MB_CODE_TX_INACTIVE,
516 ®s->cantxfg[FLEXCAN_TX_BUF_RESERVED].can_ctrl);
521 static void do_bus_err(struct net_device *dev,
522 struct can_frame *cf, u32 reg_esr)
524 struct flexcan_priv *priv = netdev_priv(dev);
525 int rx_errors = 0, tx_errors = 0;
527 cf->can_id |= CAN_ERR_PROT | CAN_ERR_BUSERROR;
529 if (reg_esr & FLEXCAN_ESR_BIT1_ERR) {
530 netdev_dbg(dev, "BIT1_ERR irq\n");
531 cf->data[2] |= CAN_ERR_PROT_BIT1;
534 if (reg_esr & FLEXCAN_ESR_BIT0_ERR) {
535 netdev_dbg(dev, "BIT0_ERR irq\n");
536 cf->data[2] |= CAN_ERR_PROT_BIT0;
539 if (reg_esr & FLEXCAN_ESR_ACK_ERR) {
540 netdev_dbg(dev, "ACK_ERR irq\n");
541 cf->can_id |= CAN_ERR_ACK;
542 cf->data[3] |= CAN_ERR_PROT_LOC_ACK;
545 if (reg_esr & FLEXCAN_ESR_CRC_ERR) {
546 netdev_dbg(dev, "CRC_ERR irq\n");
547 cf->data[2] |= CAN_ERR_PROT_BIT;
548 cf->data[3] |= CAN_ERR_PROT_LOC_CRC_SEQ;
551 if (reg_esr & FLEXCAN_ESR_FRM_ERR) {
552 netdev_dbg(dev, "FRM_ERR irq\n");
553 cf->data[2] |= CAN_ERR_PROT_FORM;
556 if (reg_esr & FLEXCAN_ESR_STF_ERR) {
557 netdev_dbg(dev, "STF_ERR irq\n");
558 cf->data[2] |= CAN_ERR_PROT_STUFF;
562 priv->can.can_stats.bus_error++;
564 dev->stats.rx_errors++;
566 dev->stats.tx_errors++;
569 static int flexcan_poll_bus_err(struct net_device *dev, u32 reg_esr)
572 struct can_frame *cf;
574 skb = alloc_can_err_skb(dev, &cf);
578 do_bus_err(dev, cf, reg_esr);
580 dev->stats.rx_packets++;
581 dev->stats.rx_bytes += cf->can_dlc;
582 netif_receive_skb(skb);
587 static int flexcan_poll_state(struct net_device *dev, u32 reg_esr)
589 struct flexcan_priv *priv = netdev_priv(dev);
591 struct can_frame *cf;
592 enum can_state new_state = 0, rx_state = 0, tx_state = 0;
594 struct can_berr_counter bec;
596 flt = reg_esr & FLEXCAN_ESR_FLT_CONF_MASK;
597 if (likely(flt == FLEXCAN_ESR_FLT_CONF_ACTIVE)) {
598 tx_state = unlikely(reg_esr & FLEXCAN_ESR_TX_WRN) ?
599 CAN_STATE_ERROR_WARNING : CAN_STATE_ERROR_ACTIVE;
600 rx_state = unlikely(reg_esr & FLEXCAN_ESR_RX_WRN) ?
601 CAN_STATE_ERROR_WARNING : CAN_STATE_ERROR_ACTIVE;
602 new_state = max(tx_state, rx_state);
604 __flexcan_get_berr_counter(dev, &bec);
605 new_state = flt == FLEXCAN_ESR_FLT_CONF_PASSIVE ?
606 CAN_STATE_ERROR_PASSIVE : CAN_STATE_BUS_OFF;
607 rx_state = bec.rxerr >= bec.txerr ? new_state : 0;
608 tx_state = bec.rxerr <= bec.txerr ? new_state : 0;
611 /* state hasn't changed */
612 if (likely(new_state == priv->can.state))
615 skb = alloc_can_err_skb(dev, &cf);
619 can_change_state(dev, cf, tx_state, rx_state);
621 if (unlikely(new_state == CAN_STATE_BUS_OFF))
624 dev->stats.rx_packets++;
625 dev->stats.rx_bytes += cf->can_dlc;
626 netif_receive_skb(skb);
631 static void flexcan_read_fifo(const struct net_device *dev,
632 struct can_frame *cf)
634 const struct flexcan_priv *priv = netdev_priv(dev);
635 struct flexcan_regs __iomem *regs = priv->base;
636 struct flexcan_mb __iomem *mb = ®s->cantxfg[0];
637 u32 reg_ctrl, reg_id;
639 reg_ctrl = flexcan_read(&mb->can_ctrl);
640 reg_id = flexcan_read(&mb->can_id);
641 if (reg_ctrl & FLEXCAN_MB_CNT_IDE)
642 cf->can_id = ((reg_id >> 0) & CAN_EFF_MASK) | CAN_EFF_FLAG;
644 cf->can_id = (reg_id >> 18) & CAN_SFF_MASK;
646 if (reg_ctrl & FLEXCAN_MB_CNT_RTR)
647 cf->can_id |= CAN_RTR_FLAG;
648 cf->can_dlc = get_can_dlc((reg_ctrl >> 16) & 0xf);
650 *(__be32 *)(cf->data + 0) = cpu_to_be32(flexcan_read(&mb->data[0]));
651 *(__be32 *)(cf->data + 4) = cpu_to_be32(flexcan_read(&mb->data[1]));
654 flexcan_write(FLEXCAN_IFLAG_RX_FIFO_AVAILABLE, ®s->iflag1);
655 flexcan_read(®s->timer);
658 static int flexcan_read_frame(struct net_device *dev)
660 struct net_device_stats *stats = &dev->stats;
661 struct can_frame *cf;
664 skb = alloc_can_skb(dev, &cf);
665 if (unlikely(!skb)) {
670 flexcan_read_fifo(dev, cf);
673 stats->rx_bytes += cf->can_dlc;
674 netif_receive_skb(skb);
676 can_led_event(dev, CAN_LED_EVENT_RX);
681 static int flexcan_poll(struct napi_struct *napi, int quota)
683 struct net_device *dev = napi->dev;
684 const struct flexcan_priv *priv = netdev_priv(dev);
685 struct flexcan_regs __iomem *regs = priv->base;
686 u32 reg_iflag1, reg_esr;
689 /* The error bits are cleared on read,
690 * use saved value from irq handler.
692 reg_esr = flexcan_read(®s->esr) | priv->reg_esr;
694 /* handle state changes */
695 work_done += flexcan_poll_state(dev, reg_esr);
698 reg_iflag1 = flexcan_read(®s->iflag1);
699 while (reg_iflag1 & FLEXCAN_IFLAG_RX_FIFO_AVAILABLE &&
701 work_done += flexcan_read_frame(dev);
702 reg_iflag1 = flexcan_read(®s->iflag1);
705 /* report bus errors */
706 if (flexcan_has_and_handle_berr(priv, reg_esr) && work_done < quota)
707 work_done += flexcan_poll_bus_err(dev, reg_esr);
709 if (work_done < quota) {
712 flexcan_write(FLEXCAN_IFLAG_DEFAULT, ®s->imask1);
713 flexcan_write(priv->reg_ctrl_default, ®s->ctrl);
719 static irqreturn_t flexcan_irq(int irq, void *dev_id)
721 struct net_device *dev = dev_id;
722 struct net_device_stats *stats = &dev->stats;
723 struct flexcan_priv *priv = netdev_priv(dev);
724 struct flexcan_regs __iomem *regs = priv->base;
725 u32 reg_iflag1, reg_esr;
727 reg_iflag1 = flexcan_read(®s->iflag1);
728 reg_esr = flexcan_read(®s->esr);
730 /* ACK all bus error and state change IRQ sources */
731 if (reg_esr & FLEXCAN_ESR_ALL_INT)
732 flexcan_write(reg_esr & FLEXCAN_ESR_ALL_INT, ®s->esr);
734 /* schedule NAPI in case of:
737 * - bus error IRQ and bus error reporting is activated
739 if ((reg_iflag1 & FLEXCAN_IFLAG_RX_FIFO_AVAILABLE) ||
740 (reg_esr & FLEXCAN_ESR_ERR_STATE) ||
741 flexcan_has_and_handle_berr(priv, reg_esr)) {
742 /* The error bits are cleared on read,
743 * save them for later use.
745 priv->reg_esr = reg_esr & FLEXCAN_ESR_ERR_BUS;
746 flexcan_write(FLEXCAN_IFLAG_DEFAULT &
747 ~FLEXCAN_IFLAG_RX_FIFO_AVAILABLE, ®s->imask1);
748 flexcan_write(priv->reg_ctrl_default & ~FLEXCAN_CTRL_ERR_ALL,
750 napi_schedule(&priv->napi);
754 if (reg_iflag1 & FLEXCAN_IFLAG_RX_FIFO_OVERFLOW) {
755 flexcan_write(FLEXCAN_IFLAG_RX_FIFO_OVERFLOW, ®s->iflag1);
756 dev->stats.rx_over_errors++;
757 dev->stats.rx_errors++;
760 /* transmission complete interrupt */
761 if (reg_iflag1 & (1 << FLEXCAN_TX_BUF_ID)) {
762 stats->tx_bytes += can_get_echo_skb(dev, 0);
764 can_led_event(dev, CAN_LED_EVENT_TX);
766 /* after sending a RTR frame MB is in RX mode */
767 flexcan_write(FLEXCAN_MB_CODE_TX_INACTIVE,
768 ®s->cantxfg[FLEXCAN_TX_BUF_ID].can_ctrl);
769 flexcan_write((1 << FLEXCAN_TX_BUF_ID), ®s->iflag1);
770 netif_wake_queue(dev);
776 static void flexcan_set_bittiming(struct net_device *dev)
778 const struct flexcan_priv *priv = netdev_priv(dev);
779 const struct can_bittiming *bt = &priv->can.bittiming;
780 struct flexcan_regs __iomem *regs = priv->base;
783 reg = flexcan_read(®s->ctrl);
784 reg &= ~(FLEXCAN_CTRL_PRESDIV(0xff) |
785 FLEXCAN_CTRL_RJW(0x3) |
786 FLEXCAN_CTRL_PSEG1(0x7) |
787 FLEXCAN_CTRL_PSEG2(0x7) |
788 FLEXCAN_CTRL_PROPSEG(0x7) |
793 reg |= FLEXCAN_CTRL_PRESDIV(bt->brp - 1) |
794 FLEXCAN_CTRL_PSEG1(bt->phase_seg1 - 1) |
795 FLEXCAN_CTRL_PSEG2(bt->phase_seg2 - 1) |
796 FLEXCAN_CTRL_RJW(bt->sjw - 1) |
797 FLEXCAN_CTRL_PROPSEG(bt->prop_seg - 1);
799 if (priv->can.ctrlmode & CAN_CTRLMODE_LOOPBACK)
800 reg |= FLEXCAN_CTRL_LPB;
801 if (priv->can.ctrlmode & CAN_CTRLMODE_LISTENONLY)
802 reg |= FLEXCAN_CTRL_LOM;
803 if (priv->can.ctrlmode & CAN_CTRLMODE_3_SAMPLES)
804 reg |= FLEXCAN_CTRL_SMP;
806 netdev_dbg(dev, "writing ctrl=0x%08x\n", reg);
807 flexcan_write(reg, ®s->ctrl);
809 /* print chip status */
810 netdev_dbg(dev, "%s: mcr=0x%08x ctrl=0x%08x\n", __func__,
811 flexcan_read(®s->mcr), flexcan_read(®s->ctrl));
814 /* flexcan_chip_start
816 * this functions is entered with clocks enabled
819 static int flexcan_chip_start(struct net_device *dev)
821 struct flexcan_priv *priv = netdev_priv(dev);
822 struct flexcan_regs __iomem *regs = priv->base;
823 u32 reg_mcr, reg_ctrl, reg_ctrl2, reg_mecr;
827 err = flexcan_chip_enable(priv);
832 err = flexcan_chip_softreset(priv);
834 goto out_chip_disable;
836 flexcan_set_bittiming(dev);
843 * only supervisor access
848 reg_mcr = flexcan_read(®s->mcr);
849 reg_mcr &= ~FLEXCAN_MCR_MAXMB(0xff);
850 reg_mcr |= FLEXCAN_MCR_FRZ | FLEXCAN_MCR_FEN | FLEXCAN_MCR_HALT |
851 FLEXCAN_MCR_SUPV | FLEXCAN_MCR_WRN_EN |
852 FLEXCAN_MCR_IDAM_C | FLEXCAN_MCR_SRX_DIS |
853 FLEXCAN_MCR_MAXMB(FLEXCAN_TX_BUF_ID);
854 netdev_dbg(dev, "%s: writing mcr=0x%08x", __func__, reg_mcr);
855 flexcan_write(reg_mcr, ®s->mcr);
859 * disable timer sync feature
861 * disable auto busoff recovery
862 * transmit lowest buffer first
864 * enable tx and rx warning interrupt
865 * enable bus off interrupt
866 * (== FLEXCAN_CTRL_ERR_STATE)
868 reg_ctrl = flexcan_read(®s->ctrl);
869 reg_ctrl &= ~FLEXCAN_CTRL_TSYN;
870 reg_ctrl |= FLEXCAN_CTRL_BOFF_REC | FLEXCAN_CTRL_LBUF |
871 FLEXCAN_CTRL_ERR_STATE;
873 /* enable the "error interrupt" (FLEXCAN_CTRL_ERR_MSK),
874 * on most Flexcan cores, too. Otherwise we don't get
875 * any error warning or passive interrupts.
877 if (priv->devtype_data->features & FLEXCAN_HAS_BROKEN_ERR_STATE ||
878 priv->can.ctrlmode & CAN_CTRLMODE_BERR_REPORTING)
879 reg_ctrl |= FLEXCAN_CTRL_ERR_MSK;
881 reg_ctrl &= ~FLEXCAN_CTRL_ERR_MSK;
883 /* save for later use */
884 priv->reg_ctrl_default = reg_ctrl;
885 netdev_dbg(dev, "%s: writing ctrl=0x%08x", __func__, reg_ctrl);
886 flexcan_write(reg_ctrl, ®s->ctrl);
888 /* clear and invalidate all mailboxes first */
889 for (i = FLEXCAN_TX_BUF_ID; i < ARRAY_SIZE(regs->cantxfg); i++) {
890 flexcan_write(FLEXCAN_MB_CODE_RX_INACTIVE,
891 ®s->cantxfg[i].can_ctrl);
894 /* Errata ERR005829: mark first TX mailbox as INACTIVE */
895 flexcan_write(FLEXCAN_MB_CODE_TX_INACTIVE,
896 ®s->cantxfg[FLEXCAN_TX_BUF_RESERVED].can_ctrl);
898 /* mark TX mailbox as INACTIVE */
899 flexcan_write(FLEXCAN_MB_CODE_TX_INACTIVE,
900 ®s->cantxfg[FLEXCAN_TX_BUF_ID].can_ctrl);
902 /* acceptance mask/acceptance code (accept everything) */
903 flexcan_write(0x0, ®s->rxgmask);
904 flexcan_write(0x0, ®s->rx14mask);
905 flexcan_write(0x0, ®s->rx15mask);
907 if (priv->devtype_data->features & FLEXCAN_HAS_V10_FEATURES)
908 flexcan_write(0x0, ®s->rxfgmask);
910 /* On Vybrid, disable memory error detection interrupts
912 * This also works around errata e5295 which generates
913 * false positive memory errors and put the device in
916 if (priv->devtype_data->features & FLEXCAN_HAS_MECR_FEATURES) {
917 /* Follow the protocol as described in "Detection
918 * and Correction of Memory Errors" to write to
921 reg_ctrl2 = flexcan_read(®s->ctrl2);
922 reg_ctrl2 |= FLEXCAN_CTRL2_ECRWRE;
923 flexcan_write(reg_ctrl2, ®s->ctrl2);
925 reg_mecr = flexcan_read(®s->mecr);
926 reg_mecr &= ~FLEXCAN_MECR_ECRWRDIS;
927 flexcan_write(reg_mecr, ®s->mecr);
928 reg_mecr &= ~(FLEXCAN_MECR_NCEFAFRZ | FLEXCAN_MECR_HANCEI_MSK |
929 FLEXCAN_MECR_FANCEI_MSK);
930 flexcan_write(reg_mecr, ®s->mecr);
933 err = flexcan_transceiver_enable(priv);
935 goto out_chip_disable;
937 /* synchronize with the can bus */
938 err = flexcan_chip_unfreeze(priv);
940 goto out_transceiver_disable;
942 priv->can.state = CAN_STATE_ERROR_ACTIVE;
944 /* enable FIFO interrupts */
945 flexcan_write(FLEXCAN_IFLAG_DEFAULT, ®s->imask1);
947 /* print chip status */
948 netdev_dbg(dev, "%s: reading mcr=0x%08x ctrl=0x%08x\n", __func__,
949 flexcan_read(®s->mcr), flexcan_read(®s->ctrl));
953 out_transceiver_disable:
954 flexcan_transceiver_disable(priv);
956 flexcan_chip_disable(priv);
962 * this functions is entered with clocks enabled
964 static void flexcan_chip_stop(struct net_device *dev)
966 struct flexcan_priv *priv = netdev_priv(dev);
967 struct flexcan_regs __iomem *regs = priv->base;
969 /* freeze + disable module */
970 flexcan_chip_freeze(priv);
971 flexcan_chip_disable(priv);
973 /* Disable all interrupts */
974 flexcan_write(0, ®s->imask1);
975 flexcan_write(priv->reg_ctrl_default & ~FLEXCAN_CTRL_ERR_ALL,
978 flexcan_transceiver_disable(priv);
979 priv->can.state = CAN_STATE_STOPPED;
982 static int flexcan_open(struct net_device *dev)
984 struct flexcan_priv *priv = netdev_priv(dev);
987 err = clk_prepare_enable(priv->clk_ipg);
991 err = clk_prepare_enable(priv->clk_per);
993 goto out_disable_ipg;
995 err = open_candev(dev);
997 goto out_disable_per;
999 err = request_irq(dev->irq, flexcan_irq, IRQF_SHARED, dev->name, dev);
1003 /* start chip and queuing */
1004 err = flexcan_chip_start(dev);
1008 can_led_event(dev, CAN_LED_EVENT_OPEN);
1010 napi_enable(&priv->napi);
1011 netif_start_queue(dev);
1016 free_irq(dev->irq, dev);
1020 clk_disable_unprepare(priv->clk_per);
1022 clk_disable_unprepare(priv->clk_ipg);
1027 static int flexcan_close(struct net_device *dev)
1029 struct flexcan_priv *priv = netdev_priv(dev);
1031 netif_stop_queue(dev);
1032 napi_disable(&priv->napi);
1033 flexcan_chip_stop(dev);
1035 free_irq(dev->irq, dev);
1036 clk_disable_unprepare(priv->clk_per);
1037 clk_disable_unprepare(priv->clk_ipg);
1041 can_led_event(dev, CAN_LED_EVENT_STOP);
1046 static int flexcan_set_mode(struct net_device *dev, enum can_mode mode)
1051 case CAN_MODE_START:
1052 err = flexcan_chip_start(dev);
1056 netif_wake_queue(dev);
1066 static const struct net_device_ops flexcan_netdev_ops = {
1067 .ndo_open = flexcan_open,
1068 .ndo_stop = flexcan_close,
1069 .ndo_start_xmit = flexcan_start_xmit,
1070 .ndo_change_mtu = can_change_mtu,
1073 static int register_flexcandev(struct net_device *dev)
1075 struct flexcan_priv *priv = netdev_priv(dev);
1076 struct flexcan_regs __iomem *regs = priv->base;
1079 err = clk_prepare_enable(priv->clk_ipg);
1083 err = clk_prepare_enable(priv->clk_per);
1085 goto out_disable_ipg;
1087 /* select "bus clock", chip must be disabled */
1088 err = flexcan_chip_disable(priv);
1090 goto out_disable_per;
1091 reg = flexcan_read(®s->ctrl);
1092 reg |= FLEXCAN_CTRL_CLK_SRC;
1093 flexcan_write(reg, ®s->ctrl);
1095 err = flexcan_chip_enable(priv);
1097 goto out_chip_disable;
1099 /* set freeze, halt and activate FIFO, restrict register access */
1100 reg = flexcan_read(®s->mcr);
1101 reg |= FLEXCAN_MCR_FRZ | FLEXCAN_MCR_HALT |
1102 FLEXCAN_MCR_FEN | FLEXCAN_MCR_SUPV;
1103 flexcan_write(reg, ®s->mcr);
1105 /* Currently we only support newer versions of this core
1106 * featuring a RX FIFO. Older cores found on some Coldfire
1107 * derivates are not yet supported.
1109 reg = flexcan_read(®s->mcr);
1110 if (!(reg & FLEXCAN_MCR_FEN)) {
1111 netdev_err(dev, "Could not enable RX FIFO, unsupported core\n");
1113 goto out_chip_disable;
1116 err = register_candev(dev);
1118 /* disable core and turn off clocks */
1120 flexcan_chip_disable(priv);
1122 clk_disable_unprepare(priv->clk_per);
1124 clk_disable_unprepare(priv->clk_ipg);
1129 static void unregister_flexcandev(struct net_device *dev)
1131 unregister_candev(dev);
1134 static const struct of_device_id flexcan_of_match[] = {
1135 { .compatible = "fsl,imx6q-flexcan", .data = &fsl_imx6q_devtype_data, },
1136 { .compatible = "fsl,imx28-flexcan", .data = &fsl_imx28_devtype_data, },
1137 { .compatible = "fsl,p1010-flexcan", .data = &fsl_p1010_devtype_data, },
1138 { .compatible = "fsl,vf610-flexcan", .data = &fsl_vf610_devtype_data, },
1141 MODULE_DEVICE_TABLE(of, flexcan_of_match);
1143 static const struct platform_device_id flexcan_id_table[] = {
1144 { .name = "flexcan", .driver_data = (kernel_ulong_t)&fsl_p1010_devtype_data, },
1147 MODULE_DEVICE_TABLE(platform, flexcan_id_table);
1149 static int flexcan_probe(struct platform_device *pdev)
1151 const struct of_device_id *of_id;
1152 const struct flexcan_devtype_data *devtype_data;
1153 struct net_device *dev;
1154 struct flexcan_priv *priv;
1155 struct regulator *reg_xceiver;
1156 struct resource *mem;
1157 struct clk *clk_ipg = NULL, *clk_per = NULL;
1162 reg_xceiver = devm_regulator_get(&pdev->dev, "xceiver");
1163 if (PTR_ERR(reg_xceiver) == -EPROBE_DEFER)
1164 return -EPROBE_DEFER;
1165 else if (IS_ERR(reg_xceiver))
1168 if (pdev->dev.of_node)
1169 of_property_read_u32(pdev->dev.of_node,
1170 "clock-frequency", &clock_freq);
1173 clk_ipg = devm_clk_get(&pdev->dev, "ipg");
1174 if (IS_ERR(clk_ipg)) {
1175 dev_err(&pdev->dev, "no ipg clock defined\n");
1176 return PTR_ERR(clk_ipg);
1179 clk_per = devm_clk_get(&pdev->dev, "per");
1180 if (IS_ERR(clk_per)) {
1181 dev_err(&pdev->dev, "no per clock defined\n");
1182 return PTR_ERR(clk_per);
1184 clock_freq = clk_get_rate(clk_per);
1187 mem = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1188 irq = platform_get_irq(pdev, 0);
1192 base = devm_ioremap_resource(&pdev->dev, mem);
1194 return PTR_ERR(base);
1196 of_id = of_match_device(flexcan_of_match, &pdev->dev);
1198 devtype_data = of_id->data;
1199 } else if (platform_get_device_id(pdev)->driver_data) {
1200 devtype_data = (struct flexcan_devtype_data *)
1201 platform_get_device_id(pdev)->driver_data;
1206 dev = alloc_candev(sizeof(struct flexcan_priv), 1);
1210 dev->netdev_ops = &flexcan_netdev_ops;
1212 dev->flags |= IFF_ECHO;
1214 priv = netdev_priv(dev);
1215 priv->can.clock.freq = clock_freq;
1216 priv->can.bittiming_const = &flexcan_bittiming_const;
1217 priv->can.do_set_mode = flexcan_set_mode;
1218 priv->can.do_get_berr_counter = flexcan_get_berr_counter;
1219 priv->can.ctrlmode_supported = CAN_CTRLMODE_LOOPBACK |
1220 CAN_CTRLMODE_LISTENONLY | CAN_CTRLMODE_3_SAMPLES |
1221 CAN_CTRLMODE_BERR_REPORTING;
1223 priv->clk_ipg = clk_ipg;
1224 priv->clk_per = clk_per;
1225 priv->pdata = dev_get_platdata(&pdev->dev);
1226 priv->devtype_data = devtype_data;
1227 priv->reg_xceiver = reg_xceiver;
1229 netif_napi_add(dev, &priv->napi, flexcan_poll, FLEXCAN_NAPI_WEIGHT);
1231 platform_set_drvdata(pdev, dev);
1232 SET_NETDEV_DEV(dev, &pdev->dev);
1234 err = register_flexcandev(dev);
1236 dev_err(&pdev->dev, "registering netdev failed\n");
1237 goto failed_register;
1240 devm_can_led_init(dev);
1242 dev_info(&pdev->dev, "device registered (reg_base=%p, irq=%d)\n",
1243 priv->base, dev->irq);
1252 static int flexcan_remove(struct platform_device *pdev)
1254 struct net_device *dev = platform_get_drvdata(pdev);
1255 struct flexcan_priv *priv = netdev_priv(dev);
1257 unregister_flexcandev(dev);
1258 netif_napi_del(&priv->napi);
1264 static int __maybe_unused flexcan_suspend(struct device *device)
1266 struct net_device *dev = dev_get_drvdata(device);
1267 struct flexcan_priv *priv = netdev_priv(dev);
1270 err = flexcan_chip_disable(priv);
1274 if (netif_running(dev)) {
1275 netif_stop_queue(dev);
1276 netif_device_detach(dev);
1278 priv->can.state = CAN_STATE_SLEEPING;
1283 static int __maybe_unused flexcan_resume(struct device *device)
1285 struct net_device *dev = dev_get_drvdata(device);
1286 struct flexcan_priv *priv = netdev_priv(dev);
1288 priv->can.state = CAN_STATE_ERROR_ACTIVE;
1289 if (netif_running(dev)) {
1290 netif_device_attach(dev);
1291 netif_start_queue(dev);
1293 return flexcan_chip_enable(priv);
1296 static SIMPLE_DEV_PM_OPS(flexcan_pm_ops, flexcan_suspend, flexcan_resume);
1298 static struct platform_driver flexcan_driver = {
1301 .pm = &flexcan_pm_ops,
1302 .of_match_table = flexcan_of_match,
1304 .probe = flexcan_probe,
1305 .remove = flexcan_remove,
1306 .id_table = flexcan_id_table,
1309 module_platform_driver(flexcan_driver);
1311 MODULE_AUTHOR("Sascha Hauer <kernel@pengutronix.de>, "
1312 "Marc Kleine-Budde <kernel@pengutronix.de>");
1313 MODULE_LICENSE("GPL v2");
1314 MODULE_DESCRIPTION("CAN port driver for flexcan based chip");