2 * CAN bus driver for Bosch M_CAN controller
4 * Copyright (C) 2014 Freescale Semiconductor, Inc.
5 * Dong Aisheng <b29396@freescale.com>
7 * Bosch M_CAN user manual can be obtained from:
8 * http://www.bosch-semiconductors.de/media/pdf_1/ipmodules_1/m_can/
9 * mcan_users_manual_v302.pdf
11 * This file is licensed under the terms of the GNU General Public
12 * License version 2. This program is licensed "as is" without any
13 * warranty of any kind, whether express or implied.
16 #include <linux/clk.h>
17 #include <linux/delay.h>
18 #include <linux/interrupt.h>
20 #include <linux/kernel.h>
21 #include <linux/module.h>
22 #include <linux/netdevice.h>
24 #include <linux/of_device.h>
25 #include <linux/platform_device.h>
27 #include <linux/can/dev.h>
30 #define M_CAN_NAPI_WEIGHT 64
32 /* message ram configuration data length */
33 #define MRAM_CFG_LEN 8
35 /* registers definition */
85 /* m_can lec values */
108 /* Test Register (TEST) */
109 #define TEST_LBCK BIT(4)
111 /* CC Control Register(CCCR) */
112 #define CCCR_TEST BIT(7)
113 #define CCCR_MON BIT(5)
114 #define CCCR_CCE BIT(1)
115 #define CCCR_INIT BIT(0)
117 /* Bit Timing & Prescaler Register (BTP) */
118 #define BTR_BRP_MASK 0x3ff
119 #define BTR_BRP_SHIFT 16
120 #define BTR_TSEG1_SHIFT 8
121 #define BTR_TSEG1_MASK (0x3f << BTR_TSEG1_SHIFT)
122 #define BTR_TSEG2_SHIFT 4
123 #define BTR_TSEG2_MASK (0xf << BTR_TSEG2_SHIFT)
124 #define BTR_SJW_SHIFT 0
125 #define BTR_SJW_MASK 0xf
127 /* Error Counter Register(ECR) */
128 #define ECR_RP BIT(15)
129 #define ECR_REC_SHIFT 8
130 #define ECR_REC_MASK (0x7f << ECR_REC_SHIFT)
131 #define ECR_TEC_SHIFT 0
132 #define ECR_TEC_MASK 0xff
134 /* Protocol Status Register(PSR) */
135 #define PSR_BO BIT(7)
136 #define PSR_EW BIT(6)
137 #define PSR_EP BIT(5)
138 #define PSR_LEC_MASK 0x7
140 /* Interrupt Register(IR) */
141 #define IR_ALL_INT 0xffffffff
142 #define IR_STE BIT(31)
143 #define IR_FOE BIT(30)
144 #define IR_ACKE BIT(29)
145 #define IR_BE BIT(28)
146 #define IR_CRCE BIT(27)
147 #define IR_WDI BIT(26)
148 #define IR_BO BIT(25)
149 #define IR_EW BIT(24)
150 #define IR_EP BIT(23)
151 #define IR_ELO BIT(22)
152 #define IR_BEU BIT(21)
153 #define IR_BEC BIT(20)
154 #define IR_DRX BIT(19)
155 #define IR_TOO BIT(18)
156 #define IR_MRAF BIT(17)
157 #define IR_TSW BIT(16)
158 #define IR_TEFL BIT(15)
159 #define IR_TEFF BIT(14)
160 #define IR_TEFW BIT(13)
161 #define IR_TEFN BIT(12)
162 #define IR_TFE BIT(11)
163 #define IR_TCF BIT(10)
165 #define IR_HPM BIT(8)
166 #define IR_RF1L BIT(7)
167 #define IR_RF1F BIT(6)
168 #define IR_RF1W BIT(5)
169 #define IR_RF1N BIT(4)
170 #define IR_RF0L BIT(3)
171 #define IR_RF0F BIT(2)
172 #define IR_RF0W BIT(1)
173 #define IR_RF0N BIT(0)
174 #define IR_ERR_STATE (IR_BO | IR_EW | IR_EP)
175 #define IR_ERR_LEC (IR_STE | IR_FOE | IR_ACKE | IR_BE | IR_CRCE)
176 #define IR_ERR_BUS (IR_ERR_LEC | IR_WDI | IR_ELO | IR_BEU | \
177 IR_BEC | IR_TOO | IR_MRAF | IR_TSW | IR_TEFL | \
179 #define IR_ERR_ALL (IR_ERR_STATE | IR_ERR_BUS)
181 /* Interrupt Line Select (ILS) */
182 #define ILS_ALL_INT0 0x0
183 #define ILS_ALL_INT1 0xFFFFFFFF
185 /* Interrupt Line Enable (ILE) */
186 #define ILE_EINT0 BIT(0)
187 #define ILE_EINT1 BIT(1)
189 /* Rx FIFO 0/1 Configuration (RXF0C/RXF1C) */
190 #define RXFC_FWM_OFF 24
191 #define RXFC_FWM_MASK 0x7f
192 #define RXFC_FWM_1 (1 << RXFC_FWM_OFF)
193 #define RXFC_FS_OFF 16
194 #define RXFC_FS_MASK 0x7f
196 /* Rx FIFO 0/1 Status (RXF0S/RXF1S) */
197 #define RXFS_RFL BIT(25)
198 #define RXFS_FF BIT(24)
199 #define RXFS_FPI_OFF 16
200 #define RXFS_FPI_MASK 0x3f0000
201 #define RXFS_FGI_OFF 8
202 #define RXFS_FGI_MASK 0x3f00
203 #define RXFS_FFL_MASK 0x7f
205 /* Rx Buffer / FIFO Element Size Configuration (RXESC) */
206 #define M_CAN_RXESC_8BYTES 0x0
208 /* Tx Buffer Configuration(TXBC) */
209 #define TXBC_NDTB_OFF 16
210 #define TXBC_NDTB_MASK 0x3f
212 /* Tx Buffer Element Size Configuration(TXESC) */
213 #define TXESC_TBDS_8BYTES 0x0
215 /* Tx Event FIFO Con.guration (TXEFC) */
216 #define TXEFC_EFS_OFF 16
217 #define TXEFC_EFS_MASK 0x3f
219 /* Message RAM Configuration (in bytes) */
220 #define SIDF_ELEMENT_SIZE 4
221 #define XIDF_ELEMENT_SIZE 8
222 #define RXF0_ELEMENT_SIZE 16
223 #define RXF1_ELEMENT_SIZE 16
224 #define RXB_ELEMENT_SIZE 16
225 #define TXE_ELEMENT_SIZE 8
226 #define TXB_ELEMENT_SIZE 16
228 /* Message RAM Elements */
229 #define M_CAN_FIFO_ID 0x0
230 #define M_CAN_FIFO_DLC 0x4
231 #define M_CAN_FIFO_DATA(n) (0x8 + ((n) << 2))
233 /* Rx Buffer Element */
234 #define RX_BUF_ESI BIT(31)
235 #define RX_BUF_XTD BIT(30)
236 #define RX_BUF_RTR BIT(29)
238 /* Tx Buffer Element */
239 #define TX_BUF_XTD BIT(30)
240 #define TX_BUF_RTR BIT(29)
242 /* address offset and element number for each FIFO/Buffer in the Message RAM */
248 /* m_can private data structure */
250 struct can_priv can; /* must be the first member */
251 struct napi_struct napi;
252 struct net_device *dev;
253 struct device *device;
259 /* message ram configuration */
260 void __iomem *mram_base;
261 struct mram_cfg mcfg[MRAM_CFG_NUM];
264 static inline u32 m_can_read(const struct m_can_priv *priv, enum m_can_reg reg)
266 return readl(priv->base + reg);
269 static inline void m_can_write(const struct m_can_priv *priv,
270 enum m_can_reg reg, u32 val)
272 writel(val, priv->base + reg);
275 static inline u32 m_can_fifo_read(const struct m_can_priv *priv,
276 u32 fgi, unsigned int offset)
278 return readl(priv->mram_base + priv->mcfg[MRAM_RXF0].off +
279 fgi * RXF0_ELEMENT_SIZE + offset);
282 static inline void m_can_fifo_write(const struct m_can_priv *priv,
283 u32 fpi, unsigned int offset, u32 val)
285 return writel(val, priv->mram_base + priv->mcfg[MRAM_TXB].off +
286 fpi * TXB_ELEMENT_SIZE + offset);
289 static inline void m_can_config_endisable(const struct m_can_priv *priv,
292 u32 cccr = m_can_read(priv, M_CAN_CCCR);
297 /* enable m_can configuration */
298 m_can_write(priv, M_CAN_CCCR, cccr | CCCR_INIT);
299 /* CCCR.CCE can only be set/reset while CCCR.INIT = '1' */
300 m_can_write(priv, M_CAN_CCCR, cccr | CCCR_INIT | CCCR_CCE);
302 m_can_write(priv, M_CAN_CCCR, cccr & ~(CCCR_INIT | CCCR_CCE));
305 /* there's a delay for module initialization */
307 val = CCCR_INIT | CCCR_CCE;
309 while ((m_can_read(priv, M_CAN_CCCR) & (CCCR_INIT | CCCR_CCE)) != val) {
311 netdev_warn(priv->dev, "Failed to init module\n");
319 static inline void m_can_enable_all_interrupts(const struct m_can_priv *priv)
321 m_can_write(priv, M_CAN_ILE, ILE_EINT0 | ILE_EINT1);
324 static inline void m_can_disable_all_interrupts(const struct m_can_priv *priv)
326 m_can_write(priv, M_CAN_ILE, 0x0);
329 static void m_can_read_fifo(const struct net_device *dev, struct can_frame *cf,
332 struct m_can_priv *priv = netdev_priv(dev);
335 /* calculate the fifo get index for where to read data */
336 fgi = (rxfs & RXFS_FGI_MASK) >> RXFS_FGI_OFF;
337 id = m_can_fifo_read(priv, fgi, M_CAN_FIFO_ID);
339 cf->can_id = (id & CAN_EFF_MASK) | CAN_EFF_FLAG;
341 cf->can_id = (id >> 18) & CAN_SFF_MASK;
343 if (id & RX_BUF_RTR) {
344 cf->can_id |= CAN_RTR_FLAG;
346 id = m_can_fifo_read(priv, fgi, M_CAN_FIFO_DLC);
347 cf->can_dlc = get_can_dlc((id >> 16) & 0x0F);
348 *(u32 *)(cf->data + 0) = m_can_fifo_read(priv, fgi,
350 *(u32 *)(cf->data + 4) = m_can_fifo_read(priv, fgi,
354 /* acknowledge rx fifo 0 */
355 m_can_write(priv, M_CAN_RXF0A, fgi);
358 static int m_can_do_rx_poll(struct net_device *dev, int quota)
360 struct m_can_priv *priv = netdev_priv(dev);
361 struct net_device_stats *stats = &dev->stats;
363 struct can_frame *frame;
367 rxfs = m_can_read(priv, M_CAN_RXF0S);
368 if (!(rxfs & RXFS_FFL_MASK)) {
369 netdev_dbg(dev, "no messages in fifo0\n");
373 while ((rxfs & RXFS_FFL_MASK) && (quota > 0)) {
375 netdev_warn(dev, "Rx FIFO 0 Message Lost\n");
377 skb = alloc_can_skb(dev, &frame);
383 m_can_read_fifo(dev, frame, rxfs);
386 stats->rx_bytes += frame->can_dlc;
388 netif_receive_skb(skb);
392 rxfs = m_can_read(priv, M_CAN_RXF0S);
396 can_led_event(dev, CAN_LED_EVENT_RX);
401 static int m_can_handle_lost_msg(struct net_device *dev)
403 struct net_device_stats *stats = &dev->stats;
405 struct can_frame *frame;
407 netdev_err(dev, "msg lost in rxf0\n");
410 stats->rx_over_errors++;
412 skb = alloc_can_err_skb(dev, &frame);
416 frame->can_id |= CAN_ERR_CRTL;
417 frame->data[1] = CAN_ERR_CRTL_RX_OVERFLOW;
419 netif_receive_skb(skb);
424 static int m_can_handle_lec_err(struct net_device *dev,
425 enum m_can_lec_type lec_type)
427 struct m_can_priv *priv = netdev_priv(dev);
428 struct net_device_stats *stats = &dev->stats;
429 struct can_frame *cf;
432 priv->can.can_stats.bus_error++;
435 /* propagate the error condition to the CAN stack */
436 skb = alloc_can_err_skb(dev, &cf);
440 /* check for 'last error code' which tells us the
441 * type of the last error to occur on the CAN bus
443 cf->can_id |= CAN_ERR_PROT | CAN_ERR_BUSERROR;
444 cf->data[2] |= CAN_ERR_PROT_UNSPEC;
447 case LEC_STUFF_ERROR:
448 netdev_dbg(dev, "stuff error\n");
449 cf->data[2] |= CAN_ERR_PROT_STUFF;
452 netdev_dbg(dev, "form error\n");
453 cf->data[2] |= CAN_ERR_PROT_FORM;
456 netdev_dbg(dev, "ack error\n");
457 cf->data[3] |= (CAN_ERR_PROT_LOC_ACK |
458 CAN_ERR_PROT_LOC_ACK_DEL);
461 netdev_dbg(dev, "bit1 error\n");
462 cf->data[2] |= CAN_ERR_PROT_BIT1;
465 netdev_dbg(dev, "bit0 error\n");
466 cf->data[2] |= CAN_ERR_PROT_BIT0;
469 netdev_dbg(dev, "CRC error\n");
470 cf->data[3] |= (CAN_ERR_PROT_LOC_CRC_SEQ |
471 CAN_ERR_PROT_LOC_CRC_DEL);
478 stats->rx_bytes += cf->can_dlc;
479 netif_receive_skb(skb);
484 static int m_can_get_berr_counter(const struct net_device *dev,
485 struct can_berr_counter *bec)
487 struct m_can_priv *priv = netdev_priv(dev);
491 err = clk_prepare_enable(priv->hclk);
495 err = clk_prepare_enable(priv->cclk);
497 clk_disable_unprepare(priv->hclk);
501 ecr = m_can_read(priv, M_CAN_ECR);
502 bec->rxerr = (ecr & ECR_REC_MASK) >> ECR_REC_SHIFT;
503 bec->txerr = ecr & ECR_TEC_MASK;
505 clk_disable_unprepare(priv->cclk);
506 clk_disable_unprepare(priv->hclk);
511 static int m_can_handle_state_change(struct net_device *dev,
512 enum can_state new_state)
514 struct m_can_priv *priv = netdev_priv(dev);
515 struct net_device_stats *stats = &dev->stats;
516 struct can_frame *cf;
518 struct can_berr_counter bec;
522 case CAN_STATE_ERROR_ACTIVE:
523 /* error warning state */
524 priv->can.can_stats.error_warning++;
525 priv->can.state = CAN_STATE_ERROR_WARNING;
527 case CAN_STATE_ERROR_PASSIVE:
528 /* error passive state */
529 priv->can.can_stats.error_passive++;
530 priv->can.state = CAN_STATE_ERROR_PASSIVE;
532 case CAN_STATE_BUS_OFF:
534 priv->can.state = CAN_STATE_BUS_OFF;
535 m_can_disable_all_interrupts(priv);
542 /* propagate the error condition to the CAN stack */
543 skb = alloc_can_err_skb(dev, &cf);
547 m_can_get_berr_counter(dev, &bec);
550 case CAN_STATE_ERROR_ACTIVE:
551 /* error warning state */
552 cf->can_id |= CAN_ERR_CRTL;
553 cf->data[1] = (bec.txerr > bec.rxerr) ?
554 CAN_ERR_CRTL_TX_WARNING :
555 CAN_ERR_CRTL_RX_WARNING;
556 cf->data[6] = bec.txerr;
557 cf->data[7] = bec.rxerr;
559 case CAN_STATE_ERROR_PASSIVE:
560 /* error passive state */
561 cf->can_id |= CAN_ERR_CRTL;
562 ecr = m_can_read(priv, M_CAN_ECR);
564 cf->data[1] |= CAN_ERR_CRTL_RX_PASSIVE;
566 cf->data[1] |= CAN_ERR_CRTL_TX_PASSIVE;
567 cf->data[6] = bec.txerr;
568 cf->data[7] = bec.rxerr;
570 case CAN_STATE_BUS_OFF:
572 cf->can_id |= CAN_ERR_BUSOFF;
579 stats->rx_bytes += cf->can_dlc;
580 netif_receive_skb(skb);
585 static int m_can_handle_state_errors(struct net_device *dev, u32 psr)
587 struct m_can_priv *priv = netdev_priv(dev);
590 if ((psr & PSR_EW) &&
591 (priv->can.state != CAN_STATE_ERROR_WARNING)) {
592 netdev_dbg(dev, "entered error warning state\n");
593 work_done += m_can_handle_state_change(dev,
594 CAN_STATE_ERROR_WARNING);
597 if ((psr & PSR_EP) &&
598 (priv->can.state != CAN_STATE_ERROR_PASSIVE)) {
599 netdev_dbg(dev, "entered error warning state\n");
600 work_done += m_can_handle_state_change(dev,
601 CAN_STATE_ERROR_PASSIVE);
604 if ((psr & PSR_BO) &&
605 (priv->can.state != CAN_STATE_BUS_OFF)) {
606 netdev_dbg(dev, "entered error warning state\n");
607 work_done += m_can_handle_state_change(dev,
614 static void m_can_handle_other_err(struct net_device *dev, u32 irqstatus)
616 if (irqstatus & IR_WDI)
617 netdev_err(dev, "Message RAM Watchdog event due to missing READY\n");
618 if (irqstatus & IR_BEU)
619 netdev_err(dev, "Error Logging Overflow\n");
620 if (irqstatus & IR_BEU)
621 netdev_err(dev, "Bit Error Uncorrected\n");
622 if (irqstatus & IR_BEC)
623 netdev_err(dev, "Bit Error Corrected\n");
624 if (irqstatus & IR_TOO)
625 netdev_err(dev, "Timeout reached\n");
626 if (irqstatus & IR_MRAF)
627 netdev_err(dev, "Message RAM access failure occurred\n");
630 static inline bool is_lec_err(u32 psr)
634 return psr && (psr != LEC_UNUSED);
637 static int m_can_handle_bus_errors(struct net_device *dev, u32 irqstatus,
640 struct m_can_priv *priv = netdev_priv(dev);
643 if (irqstatus & IR_RF0L)
644 work_done += m_can_handle_lost_msg(dev);
646 /* handle lec errors on the bus */
647 if ((priv->can.ctrlmode & CAN_CTRLMODE_BERR_REPORTING) &&
649 work_done += m_can_handle_lec_err(dev, psr & LEC_UNUSED);
651 /* other unproccessed error interrupts */
652 m_can_handle_other_err(dev, irqstatus);
657 static int m_can_poll(struct napi_struct *napi, int quota)
659 struct net_device *dev = napi->dev;
660 struct m_can_priv *priv = netdev_priv(dev);
664 irqstatus = priv->irqstatus | m_can_read(priv, M_CAN_IR);
668 psr = m_can_read(priv, M_CAN_PSR);
669 if (irqstatus & IR_ERR_STATE)
670 work_done += m_can_handle_state_errors(dev, psr);
672 if (irqstatus & IR_ERR_BUS)
673 work_done += m_can_handle_bus_errors(dev, irqstatus, psr);
675 if (irqstatus & IR_RF0N)
676 work_done += m_can_do_rx_poll(dev, (quota - work_done));
678 if (work_done < quota) {
680 m_can_enable_all_interrupts(priv);
687 static irqreturn_t m_can_isr(int irq, void *dev_id)
689 struct net_device *dev = (struct net_device *)dev_id;
690 struct m_can_priv *priv = netdev_priv(dev);
691 struct net_device_stats *stats = &dev->stats;
694 ir = m_can_read(priv, M_CAN_IR);
700 m_can_write(priv, M_CAN_IR, ir);
702 /* schedule NAPI in case of
705 * - bus error IRQ and bus error reporting
707 if ((ir & IR_RF0N) || (ir & IR_ERR_ALL)) {
708 priv->irqstatus = ir;
709 m_can_disable_all_interrupts(priv);
710 napi_schedule(&priv->napi);
713 /* transmission complete interrupt */
715 stats->tx_bytes += can_get_echo_skb(dev, 0);
717 can_led_event(dev, CAN_LED_EVENT_TX);
718 netif_wake_queue(dev);
724 static const struct can_bittiming_const m_can_bittiming_const = {
725 .name = KBUILD_MODNAME,
726 .tseg1_min = 2, /* Time segment 1 = prop_seg + phase_seg1 */
728 .tseg2_min = 1, /* Time segment 2 = phase_seg2 */
736 static int m_can_set_bittiming(struct net_device *dev)
738 struct m_can_priv *priv = netdev_priv(dev);
739 const struct can_bittiming *bt = &priv->can.bittiming;
740 u16 brp, sjw, tseg1, tseg2;
745 tseg1 = bt->prop_seg + bt->phase_seg1 - 1;
746 tseg2 = bt->phase_seg2 - 1;
747 reg_btp = (brp << BTR_BRP_SHIFT) | (sjw << BTR_SJW_SHIFT) |
748 (tseg1 << BTR_TSEG1_SHIFT) | (tseg2 << BTR_TSEG2_SHIFT);
749 m_can_write(priv, M_CAN_BTP, reg_btp);
750 netdev_dbg(dev, "setting BTP 0x%x\n", reg_btp);
755 /* Configure M_CAN chip:
756 * - set rx buffer/fifo element size
757 * - configure rx fifo
758 * - accept non-matching frame into fifo 0
759 * - configure tx buffer
763 static void m_can_chip_config(struct net_device *dev)
765 struct m_can_priv *priv = netdev_priv(dev);
768 m_can_config_endisable(priv, true);
770 /* RX Buffer/FIFO Element Size 8 bytes data field */
771 m_can_write(priv, M_CAN_RXESC, M_CAN_RXESC_8BYTES);
773 /* Accept Non-matching Frames Into FIFO 0 */
774 m_can_write(priv, M_CAN_GFC, 0x0);
776 /* only support one Tx Buffer currently */
777 m_can_write(priv, M_CAN_TXBC, (1 << TXBC_NDTB_OFF) |
778 priv->mcfg[MRAM_TXB].off);
780 /* only support 8 bytes firstly */
781 m_can_write(priv, M_CAN_TXESC, TXESC_TBDS_8BYTES);
783 m_can_write(priv, M_CAN_TXEFC, (1 << TXEFC_EFS_OFF) |
784 priv->mcfg[MRAM_TXE].off);
786 /* rx fifo configuration, blocking mode, fifo size 1 */
787 m_can_write(priv, M_CAN_RXF0C,
788 (priv->mcfg[MRAM_RXF0].num << RXFC_FS_OFF) |
789 RXFC_FWM_1 | priv->mcfg[MRAM_RXF0].off);
791 m_can_write(priv, M_CAN_RXF1C,
792 (priv->mcfg[MRAM_RXF1].num << RXFC_FS_OFF) |
793 RXFC_FWM_1 | priv->mcfg[MRAM_RXF1].off);
795 cccr = m_can_read(priv, M_CAN_CCCR);
796 cccr &= ~(CCCR_TEST | CCCR_MON);
797 test = m_can_read(priv, M_CAN_TEST);
800 if (priv->can.ctrlmode & CAN_CTRLMODE_LISTENONLY)
803 if (priv->can.ctrlmode & CAN_CTRLMODE_LOOPBACK) {
808 m_can_write(priv, M_CAN_CCCR, cccr);
809 m_can_write(priv, M_CAN_TEST, test);
811 /* enable interrupts */
812 m_can_write(priv, M_CAN_IR, IR_ALL_INT);
813 if (!(priv->can.ctrlmode & CAN_CTRLMODE_BERR_REPORTING))
814 m_can_write(priv, M_CAN_IE, IR_ALL_INT & ~IR_ERR_LEC);
816 m_can_write(priv, M_CAN_IE, IR_ALL_INT);
818 /* route all interrupts to INT0 */
819 m_can_write(priv, M_CAN_ILS, ILS_ALL_INT0);
821 /* set bittiming params */
822 m_can_set_bittiming(dev);
824 m_can_config_endisable(priv, false);
827 static void m_can_start(struct net_device *dev)
829 struct m_can_priv *priv = netdev_priv(dev);
831 /* basic m_can configuration */
832 m_can_chip_config(dev);
834 priv->can.state = CAN_STATE_ERROR_ACTIVE;
836 m_can_enable_all_interrupts(priv);
839 static int m_can_set_mode(struct net_device *dev, enum can_mode mode)
844 netif_wake_queue(dev);
853 static void free_m_can_dev(struct net_device *dev)
858 static struct net_device *alloc_m_can_dev(void)
860 struct net_device *dev;
861 struct m_can_priv *priv;
863 dev = alloc_candev(sizeof(*priv), 1);
867 priv = netdev_priv(dev);
868 netif_napi_add(dev, &priv->napi, m_can_poll, M_CAN_NAPI_WEIGHT);
871 priv->can.bittiming_const = &m_can_bittiming_const;
872 priv->can.do_set_mode = m_can_set_mode;
873 priv->can.do_get_berr_counter = m_can_get_berr_counter;
874 priv->can.ctrlmode_supported = CAN_CTRLMODE_LOOPBACK |
875 CAN_CTRLMODE_LISTENONLY |
876 CAN_CTRLMODE_BERR_REPORTING;
881 static int m_can_open(struct net_device *dev)
883 struct m_can_priv *priv = netdev_priv(dev);
886 err = clk_prepare_enable(priv->hclk);
890 err = clk_prepare_enable(priv->cclk);
892 goto exit_disable_hclk;
894 /* open the can device */
895 err = open_candev(dev);
897 netdev_err(dev, "failed to open can device\n");
898 goto exit_disable_cclk;
901 /* register interrupt handler */
902 err = request_irq(dev->irq, m_can_isr, IRQF_SHARED, dev->name,
905 netdev_err(dev, "failed to request interrupt\n");
909 /* start the m_can controller */
912 can_led_event(dev, CAN_LED_EVENT_OPEN);
913 napi_enable(&priv->napi);
914 netif_start_queue(dev);
921 clk_disable_unprepare(priv->cclk);
923 clk_disable_unprepare(priv->hclk);
927 static void m_can_stop(struct net_device *dev)
929 struct m_can_priv *priv = netdev_priv(dev);
931 /* disable all interrupts */
932 m_can_disable_all_interrupts(priv);
934 clk_disable_unprepare(priv->hclk);
935 clk_disable_unprepare(priv->cclk);
937 /* set the state as STOPPED */
938 priv->can.state = CAN_STATE_STOPPED;
941 static int m_can_close(struct net_device *dev)
943 struct m_can_priv *priv = netdev_priv(dev);
945 netif_stop_queue(dev);
946 napi_disable(&priv->napi);
948 free_irq(dev->irq, dev);
950 can_led_event(dev, CAN_LED_EVENT_STOP);
955 static netdev_tx_t m_can_start_xmit(struct sk_buff *skb,
956 struct net_device *dev)
958 struct m_can_priv *priv = netdev_priv(dev);
959 struct can_frame *cf = (struct can_frame *)skb->data;
962 if (can_dropped_invalid_skb(dev, skb))
965 netif_stop_queue(dev);
967 if (cf->can_id & CAN_EFF_FLAG) {
968 id = cf->can_id & CAN_EFF_MASK;
971 id = ((cf->can_id & CAN_SFF_MASK) << 18);
974 if (cf->can_id & CAN_RTR_FLAG)
977 /* message ram configuration */
978 m_can_fifo_write(priv, 0, M_CAN_FIFO_ID, id);
979 m_can_fifo_write(priv, 0, M_CAN_FIFO_DLC, cf->can_dlc << 16);
980 m_can_fifo_write(priv, 0, M_CAN_FIFO_DATA(0), *(u32 *)(cf->data + 0));
981 m_can_fifo_write(priv, 0, M_CAN_FIFO_DATA(1), *(u32 *)(cf->data + 4));
982 can_put_echo_skb(skb, dev, 0);
984 /* enable first TX buffer to start transfer */
985 m_can_write(priv, M_CAN_TXBTIE, 0x1);
986 m_can_write(priv, M_CAN_TXBAR, 0x1);
991 static const struct net_device_ops m_can_netdev_ops = {
992 .ndo_open = m_can_open,
993 .ndo_stop = m_can_close,
994 .ndo_start_xmit = m_can_start_xmit,
995 .ndo_change_mtu = can_change_mtu,
998 static int register_m_can_dev(struct net_device *dev)
1000 dev->flags |= IFF_ECHO; /* we support local echo */
1001 dev->netdev_ops = &m_can_netdev_ops;
1003 return register_candev(dev);
1006 static int m_can_of_parse_mram(struct platform_device *pdev,
1007 struct m_can_priv *priv)
1009 struct device_node *np = pdev->dev.of_node;
1010 struct resource *res;
1012 u32 out_val[MRAM_CFG_LEN];
1013 int i, start, end, ret;
1015 /* message ram could be shared */
1016 res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "message_ram");
1020 addr = devm_ioremap(&pdev->dev, res->start, resource_size(res));
1024 /* get message ram configuration */
1025 ret = of_property_read_u32_array(np, "bosch,mram-cfg",
1026 out_val, sizeof(out_val) / 4);
1028 dev_err(&pdev->dev, "can not get message ram configuration\n");
1032 priv->mram_base = addr;
1033 priv->mcfg[MRAM_SIDF].off = out_val[0];
1034 priv->mcfg[MRAM_SIDF].num = out_val[1];
1035 priv->mcfg[MRAM_XIDF].off = priv->mcfg[MRAM_SIDF].off +
1036 priv->mcfg[MRAM_SIDF].num * SIDF_ELEMENT_SIZE;
1037 priv->mcfg[MRAM_XIDF].num = out_val[2];
1038 priv->mcfg[MRAM_RXF0].off = priv->mcfg[MRAM_XIDF].off +
1039 priv->mcfg[MRAM_XIDF].num * XIDF_ELEMENT_SIZE;
1040 priv->mcfg[MRAM_RXF0].num = out_val[3] & RXFC_FS_MASK;
1041 priv->mcfg[MRAM_RXF1].off = priv->mcfg[MRAM_RXF0].off +
1042 priv->mcfg[MRAM_RXF0].num * RXF0_ELEMENT_SIZE;
1043 priv->mcfg[MRAM_RXF1].num = out_val[4] & RXFC_FS_MASK;
1044 priv->mcfg[MRAM_RXB].off = priv->mcfg[MRAM_RXF1].off +
1045 priv->mcfg[MRAM_RXF1].num * RXF1_ELEMENT_SIZE;
1046 priv->mcfg[MRAM_RXB].num = out_val[5];
1047 priv->mcfg[MRAM_TXE].off = priv->mcfg[MRAM_RXB].off +
1048 priv->mcfg[MRAM_RXB].num * RXB_ELEMENT_SIZE;
1049 priv->mcfg[MRAM_TXE].num = out_val[6];
1050 priv->mcfg[MRAM_TXB].off = priv->mcfg[MRAM_TXE].off +
1051 priv->mcfg[MRAM_TXE].num * TXE_ELEMENT_SIZE;
1052 priv->mcfg[MRAM_TXB].num = out_val[7] & TXBC_NDTB_MASK;
1054 dev_dbg(&pdev->dev, "mram_base %p sidf 0x%x %d xidf 0x%x %d rxf0 0x%x %d rxf1 0x%x %d rxb 0x%x %d txe 0x%x %d txb 0x%x %d\n",
1056 priv->mcfg[MRAM_SIDF].off, priv->mcfg[MRAM_SIDF].num,
1057 priv->mcfg[MRAM_XIDF].off, priv->mcfg[MRAM_XIDF].num,
1058 priv->mcfg[MRAM_RXF0].off, priv->mcfg[MRAM_RXF0].num,
1059 priv->mcfg[MRAM_RXF1].off, priv->mcfg[MRAM_RXF1].num,
1060 priv->mcfg[MRAM_RXB].off, priv->mcfg[MRAM_RXB].num,
1061 priv->mcfg[MRAM_TXE].off, priv->mcfg[MRAM_TXE].num,
1062 priv->mcfg[MRAM_TXB].off, priv->mcfg[MRAM_TXB].num);
1064 /* initialize the entire Message RAM in use to avoid possible
1065 * ECC/parity checksum errors when reading an uninitialized buffer
1067 start = priv->mcfg[MRAM_SIDF].off;
1068 end = priv->mcfg[MRAM_TXB].off +
1069 priv->mcfg[MRAM_TXB].num * TXB_ELEMENT_SIZE;
1070 for (i = start; i < end; i += 4)
1071 writel(0x0, priv->mram_base + i);
1076 static int m_can_plat_probe(struct platform_device *pdev)
1078 struct net_device *dev;
1079 struct m_can_priv *priv;
1080 struct resource *res;
1082 struct clk *hclk, *cclk;
1085 hclk = devm_clk_get(&pdev->dev, "hclk");
1086 cclk = devm_clk_get(&pdev->dev, "cclk");
1087 if (IS_ERR(hclk) || IS_ERR(cclk)) {
1088 dev_err(&pdev->dev, "no clock find\n");
1092 res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "m_can");
1093 addr = devm_ioremap_resource(&pdev->dev, res);
1094 irq = platform_get_irq_byname(pdev, "int0");
1095 if (IS_ERR(addr) || irq < 0)
1098 /* allocate the m_can device */
1099 dev = alloc_m_can_dev();
1103 priv = netdev_priv(dev);
1106 priv->device = &pdev->dev;
1109 priv->can.clock.freq = clk_get_rate(cclk);
1111 ret = m_can_of_parse_mram(pdev, priv);
1113 goto failed_free_dev;
1115 platform_set_drvdata(pdev, dev);
1116 SET_NETDEV_DEV(dev, &pdev->dev);
1118 ret = register_m_can_dev(dev);
1120 dev_err(&pdev->dev, "registering %s failed (err=%d)\n",
1121 KBUILD_MODNAME, ret);
1122 goto failed_free_dev;
1125 devm_can_led_init(dev);
1127 dev_info(&pdev->dev, "%s device registered (regs=%p, irq=%d)\n",
1128 KBUILD_MODNAME, priv->base, dev->irq);
1133 free_m_can_dev(dev);
1137 static __maybe_unused int m_can_suspend(struct device *dev)
1139 struct net_device *ndev = dev_get_drvdata(dev);
1140 struct m_can_priv *priv = netdev_priv(ndev);
1142 if (netif_running(ndev)) {
1143 netif_stop_queue(ndev);
1144 netif_device_detach(ndev);
1147 /* TODO: enter low power */
1149 priv->can.state = CAN_STATE_SLEEPING;
1154 static __maybe_unused int m_can_resume(struct device *dev)
1156 struct net_device *ndev = dev_get_drvdata(dev);
1157 struct m_can_priv *priv = netdev_priv(ndev);
1159 /* TODO: exit low power */
1161 priv->can.state = CAN_STATE_ERROR_ACTIVE;
1163 if (netif_running(ndev)) {
1164 netif_device_attach(ndev);
1165 netif_start_queue(ndev);
1171 static void unregister_m_can_dev(struct net_device *dev)
1173 unregister_candev(dev);
1176 static int m_can_plat_remove(struct platform_device *pdev)
1178 struct net_device *dev = platform_get_drvdata(pdev);
1180 unregister_m_can_dev(dev);
1181 platform_set_drvdata(pdev, NULL);
1183 free_m_can_dev(dev);
1188 static const struct dev_pm_ops m_can_pmops = {
1189 SET_SYSTEM_SLEEP_PM_OPS(m_can_suspend, m_can_resume)
1192 static const struct of_device_id m_can_of_table[] = {
1193 { .compatible = "bosch,m_can", .data = NULL },
1196 MODULE_DEVICE_TABLE(of, m_can_of_table);
1198 static struct platform_driver m_can_plat_driver = {
1200 .name = KBUILD_MODNAME,
1201 .of_match_table = m_can_of_table,
1204 .probe = m_can_plat_probe,
1205 .remove = m_can_plat_remove,
1208 module_platform_driver(m_can_plat_driver);
1210 MODULE_AUTHOR("Dong Aisheng <b29396@freescale.com>");
1211 MODULE_LICENSE("GPL v2");
1212 MODULE_DESCRIPTION("CAN bus driver for Bosch M_CAN controller");