2 * Copyright (C) 2011 Ilya Yanok, Emcraft Systems
4 * Based on: mach-davinci/emac_defs.h
5 * Copyright (C) 2007 Sergey Kubushyn <ksi@koi8.net>
7 * SPDX-License-Identifier: GPL-2.0+
10 #ifndef _DAVINCI_EMAC_H_
11 #define _DAVINCI_EMAC_H_
12 /* Ethernet Min/Max packet size */
13 #define EMAC_MIN_ETHERNET_PKT_SIZE 60
14 #define EMAC_MAX_ETHERNET_PKT_SIZE 1518
15 /* Buffer size (should be aligned on 32 byte and cache line) */
16 #define EMAC_RXBUF_SIZE ALIGN(ALIGN(EMAC_MAX_ETHERNET_PKT_SIZE, 32),\
19 /* Number of RX packet buffers
20 * NOTE: Only 1 buffer supported as of now
22 #define EMAC_MAX_RX_BUFFERS 10
25 /***********************************************
26 ******** Internally used macros ***************
27 ***********************************************/
32 /* Each descriptor occupies 4 words, lets start RX desc's at 0 and
33 * reserve space for 64 descriptors max
35 #define EMAC_RX_DESC_BASE 0x0
36 #define EMAC_TX_DESC_BASE 0x1000
38 /* EMAC Teardown value */
39 #define EMAC_TEARDOWN_VALUE 0xfffffffc
41 /* MII Status Register */
42 #define MII_STATUS_REG 1
44 /* Number of statistics registers */
45 #define EMAC_NUM_STATS 36
49 typedef volatile struct _emac_desc
51 u_int32_t next; /* Pointer to next descriptor
53 u_int8_t *buffer; /* Pointer to data buffer */
54 u_int32_t buff_off_len; /* Buffer Offset(MSW) and Length(LSW) */
55 u_int32_t pkt_flag_len; /* Packet Flags(MSW) and Length(LSW) */
58 /* CPPI bit positions */
59 #define EMAC_CPPI_SOP_BIT (0x80000000)
60 #define EMAC_CPPI_EOP_BIT (0x40000000)
61 #define EMAC_CPPI_OWNERSHIP_BIT (0x20000000)
62 #define EMAC_CPPI_EOQ_BIT (0x10000000)
63 #define EMAC_CPPI_TEARDOWN_COMPLETE_BIT (0x08000000)
64 #define EMAC_CPPI_PASS_CRC_BIT (0x04000000)
66 #define EMAC_CPPI_RX_ERROR_FRAME (0x03fc0000)
68 #define EMAC_MACCONTROL_MIIEN_ENABLE (0x20)
69 #define EMAC_MACCONTROL_FULLDUPLEX_ENABLE (0x1)
70 #define EMAC_MACCONTROL_GIGABIT_ENABLE (1 << 7)
71 #define EMAC_MACCONTROL_GIGFORCE (1 << 17)
72 #define EMAC_MACCONTROL_RMIISPEED_100 (1 << 15)
74 #define EMAC_MAC_ADDR_MATCH (1 << 19)
75 #define EMAC_MAC_ADDR_IS_VALID (1 << 20)
77 #define EMAC_RXMBPENABLE_RXCAFEN_ENABLE (0x200000)
78 #define EMAC_RXMBPENABLE_RXBROADEN (0x2000)
81 #define MDIO_CONTROL_IDLE (0x80000000)
82 #define MDIO_CONTROL_ENABLE (0x40000000)
83 #define MDIO_CONTROL_FAULT_ENABLE (0x40000)
84 #define MDIO_CONTROL_FAULT (0x80000)
85 #define MDIO_USERACCESS0_GO (0x80000000)
86 #define MDIO_USERACCESS0_WRITE_READ (0x0)
87 #define MDIO_USERACCESS0_WRITE_WRITE (0x40000000)
88 #define MDIO_USERACCESS0_ACK (0x20000000)
90 /* Ethernet MAC Registers Structure */
101 dv_reg TXINTSTATMASKED;
103 dv_reg TXINTMASKCLEAR;
107 dv_reg RXINTSTATMASKED;
109 dv_reg RXINTMASKCLEAR;
110 dv_reg MACINTSTATRAW;
111 dv_reg MACINTSTATMASKED;
112 dv_reg MACINTMASKSET;
113 dv_reg MACINTMASKCLEAR;
117 dv_reg RXUNICASTCLEAR;
119 dv_reg RXBUFFEROFFSET;
120 dv_reg RXFILTERLOWTHRESH;
122 dv_reg RX0FLOWTHRESH;
123 dv_reg RX1FLOWTHRESH;
124 dv_reg RX2FLOWTHRESH;
125 dv_reg RX3FLOWTHRESH;
126 dv_reg RX4FLOWTHRESH;
127 dv_reg RX5FLOWTHRESH;
128 dv_reg RX6FLOWTHRESH;
129 dv_reg RX7FLOWTHRESH;
130 dv_reg RX0FREEBUFFER;
131 dv_reg RX1FREEBUFFER;
132 dv_reg RX2FREEBUFFER;
133 dv_reg RX3FREEBUFFER;
134 dv_reg RX4FREEBUFFER;
135 dv_reg RX5FREEBUFFER;
136 dv_reg RX6FREEBUFFER;
137 dv_reg RX7FREEBUFFER;
155 dv_reg RXBCASTFRAMES;
156 dv_reg RXMCASTFRAMES;
157 dv_reg RXPAUSEFRAMES;
159 dv_reg RXALIGNCODEERRORS;
165 dv_reg RXQOSFILTERED;
168 dv_reg TXBCASTFRAMES;
169 dv_reg TXMCASTFRAMES;
170 dv_reg TXPAUSEFRAMES;
175 dv_reg TXEXCESSIVECOLL;
178 dv_reg TXCARRIERSENSE;
184 dv_reg FRAME512T1023;
187 dv_reg RXSOFOVERRUNS;
188 dv_reg RXMOFOVERRUNS;
189 dv_reg RXDMAOVERRUNS;
229 /* EMAC Wrapper Registers Structure */
231 #ifdef DAVINCI_EMAC_VERSION2
247 dv_reg c0rxthreshstat;
251 dv_reg c1rxthreshstat;
255 dv_reg c2rxthreshstat;
266 u_int8_t RSVD0[4100];
272 /* EMAC MDIO Registers Structure */
279 dv_reg LINKINTMASKED;
282 dv_reg USERINTMASKED;
283 dv_reg USERINTMASKSET;
284 dv_reg USERINTMASKCLEAR;
292 int davinci_eth_phy_read(u_int8_t phy_addr, u_int8_t reg_num, u_int16_t *data);
293 int davinci_eth_phy_write(u_int8_t phy_addr, u_int8_t reg_num, u_int16_t data);
297 int (*init)(int phy_addr);
298 int (*is_phy_connected)(int phy_addr);
299 int (*get_link_speed)(int phy_addr);
300 int (*auto_negotiate)(int phy_addr);
303 #endif /* _DAVINCI_EMAC_H_ */