2 * Broadcom Starfighter 2 switch register defines
4 * Copyright (C) 2014, Broadcom Corporation
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; either version 2 of the License, or
9 * (at your option) any later version.
11 #ifndef __BCM_SF2_REGS_H
12 #define __BCM_SF2_REGS_H
14 /* Register set relative to 'REG' */
16 enum bcm_sf2_reg_offs {
33 /* Relative to REG_SWITCH_CNTRL */
34 #define MDIO_MASTER_SEL (1 << 0)
36 /* Relative to REG_SWITCH_REVISION */
37 #define SF2_REV_MASK 0xffff
38 #define SWITCH_TOP_REV_SHIFT 16
39 #define SWITCH_TOP_REV_MASK 0xffff
41 /* Relative to REG_PHY_REVISION */
42 #define PHY_REVISION_MASK 0xffff
44 /* Relative to REG_SPHY_CNTRL */
45 #define IDDQ_BIAS (1 << 0)
46 #define EXT_PWR_DOWN (1 << 1)
47 #define FORCE_DLL_EN (1 << 2)
48 #define IDDQ_GLOBAL_PWR (1 << 3)
49 #define CK25_DIS (1 << 4)
50 #define PHY_RESET (1 << 5)
51 #define PHY_PHYAD_SHIFT 8
52 #define PHY_PHYAD_MASK 0x1F
54 #define REG_RGMII_CNTRL_P(x) (REG_RGMII_0_CNTRL + (x))
56 /* Relative to REG_RGMII_CNTRL */
57 #define RGMII_MODE_EN (1 << 0)
58 #define ID_MODE_DIS (1 << 1)
59 #define PORT_MODE_SHIFT 2
60 #define INT_EPHY (0 << PORT_MODE_SHIFT)
61 #define INT_GPHY (1 << PORT_MODE_SHIFT)
62 #define EXT_EPHY (2 << PORT_MODE_SHIFT)
63 #define EXT_GPHY (3 << PORT_MODE_SHIFT)
64 #define EXT_REVMII (4 << PORT_MODE_SHIFT)
65 #define PORT_MODE_MASK 0x7
66 #define RVMII_REF_SEL (1 << 5)
67 #define RX_PAUSE_EN (1 << 6)
68 #define TX_PAUSE_EN (1 << 7)
69 #define TX_CLK_STOP_EN (1 << 8)
70 #define LPI_COUNT_SHIFT 9
71 #define LPI_COUNT_MASK 0x3F
73 #define REG_LED_CNTRL(x) (REG_LED_0_CNTRL + (x))
75 #define SPDLNK_SRC_SEL (1 << 24)
77 /* Register set relative to 'INTRL2_0' and 'INTRL2_1' */
78 #define INTRL2_CPU_STATUS 0x00
79 #define INTRL2_CPU_SET 0x04
80 #define INTRL2_CPU_CLEAR 0x08
81 #define INTRL2_CPU_MASK_STATUS 0x0c
82 #define INTRL2_CPU_MASK_SET 0x10
83 #define INTRL2_CPU_MASK_CLEAR 0x14
85 /* Shared INTRL2_0 and INTRL2_ interrupt sources macros */
86 #define P_LINK_UP_IRQ(x) (1 << (0 + (x)))
87 #define P_LINK_DOWN_IRQ(x) (1 << (1 + (x)))
88 #define P_ENERGY_ON_IRQ(x) (1 << (2 + (x)))
89 #define P_ENERGY_OFF_IRQ(x) (1 << (3 + (x)))
90 #define P_GPHY_IRQ(x) (1 << (4 + (x)))
92 #define P_IRQ_MASK(x) (P_LINK_UP_IRQ((x)) | \
93 P_LINK_DOWN_IRQ((x)) | \
94 P_ENERGY_ON_IRQ((x)) | \
95 P_ENERGY_OFF_IRQ((x)) | \
98 /* INTRL2_0 interrupt sources */
100 #define MEM_DOUBLE_IRQ (1 << 5)
101 #define EEE_LPI_IRQ (1 << 6)
102 #define P5_CPU_WAKE_IRQ (1 << 7)
103 #define P8_CPU_WAKE_IRQ (1 << 8)
104 #define P7_CPU_WAKE_IRQ (1 << 9)
105 #define IEEE1588_IRQ (1 << 10)
106 #define MDIO_ERR_IRQ (1 << 11)
107 #define MDIO_DONE_IRQ (1 << 12)
108 #define GISB_ERR_IRQ (1 << 13)
109 #define UBUS_ERR_IRQ (1 << 14)
110 #define FAILOVER_ON_IRQ (1 << 15)
111 #define FAILOVER_OFF_IRQ (1 << 16)
112 #define TCAM_SOFT_ERR_IRQ (1 << 17)
114 /* INTRL2_1 interrupt sources */
116 #define P_IRQ_OFF(x) ((6 - (x)) * P_NUM_IRQ)
118 /* Register set relative to 'CORE' */
119 #define CORE_G_PCTL_PORT0 0x00000
120 #define CORE_G_PCTL_PORT(x) (CORE_G_PCTL_PORT0 + (x * 0x4))
121 #define CORE_IMP_CTL 0x00020
122 #define RX_DIS (1 << 0)
123 #define TX_DIS (1 << 1)
124 #define RX_BCST_EN (1 << 2)
125 #define RX_MCST_EN (1 << 3)
126 #define RX_UCST_EN (1 << 4)
128 #define CORE_SWMODE 0x0002c
129 #define SW_FWDG_MODE (1 << 0)
130 #define SW_FWDG_EN (1 << 1)
131 #define RTRY_LMT_DIS (1 << 2)
133 #define CORE_STS_OVERRIDE_IMP 0x00038
134 #define GMII_SPEED_UP_2G (1 << 6)
135 #define MII_SW_OR (1 << 7)
137 /* Alternate layout for e.g: 7278 */
138 #define CORE_STS_OVERRIDE_IMP2 0x39040
140 #define CORE_NEW_CTRL 0x00084
141 #define IP_MC (1 << 0)
142 #define OUTRANGEERR_DISCARD (1 << 1)
143 #define INRANGEERR_DISCARD (1 << 2)
144 #define CABLE_DIAG_LEN (1 << 3)
145 #define OVERRIDE_AUTO_PD_WAR (1 << 4)
146 #define EN_AUTO_PD_WAR (1 << 5)
147 #define UC_FWD_EN (1 << 6)
148 #define MC_FWD_EN (1 << 7)
150 #define CORE_SWITCH_CTRL 0x00088
151 #define MII_DUMB_FWDG_EN (1 << 6)
153 #define CORE_SFT_LRN_CTRL 0x000f8
154 #define SW_LEARN_CNTL(x) (1 << (x))
156 #define CORE_STS_OVERRIDE_GMIIP_PORT(x) (0x160 + (x) * 4)
157 #define CORE_STS_OVERRIDE_GMIIP2_PORT(x) (0x39000 + (x) * 8)
158 #define LINK_STS (1 << 0)
159 #define DUPLX_MODE (1 << 1)
160 #define SPEED_SHIFT 2
161 #define SPEED_MASK 0x3
162 #define RXFLOW_CNTL (1 << 4)
163 #define TXFLOW_CNTL (1 << 5)
164 #define SW_OVERRIDE (1 << 6)
166 #define CORE_WATCHDOG_CTRL 0x001e4
167 #define SOFTWARE_RESET (1 << 7)
168 #define EN_CHIP_RST (1 << 6)
169 #define EN_SW_RESET (1 << 4)
171 #define CORE_FAST_AGE_CTRL 0x00220
172 #define EN_FAST_AGE_STATIC (1 << 0)
173 #define EN_AGE_DYNAMIC (1 << 1)
174 #define EN_AGE_PORT (1 << 2)
175 #define EN_AGE_VLAN (1 << 3)
176 #define EN_AGE_SPT (1 << 4)
177 #define EN_AGE_MCAST (1 << 5)
178 #define FAST_AGE_STR_DONE (1 << 7)
180 #define CORE_FAST_AGE_PORT 0x00224
181 #define AGE_PORT_MASK 0xf
183 #define CORE_FAST_AGE_VID 0x00228
184 #define AGE_VID_MASK 0x3fff
186 #define CORE_LNKSTS 0x00400
187 #define LNK_STS_MASK 0x1ff
189 #define CORE_SPDSTS 0x00410
192 #define SPDSTS_1000 2
193 #define SPDSTS_SHIFT 2
194 #define SPDSTS_MASK 0x3
196 #define CORE_DUPSTS 0x00420
197 #define CORE_DUPSTS_MASK 0x1ff
199 #define CORE_PAUSESTS 0x00428
200 #define PAUSESTS_TX_PAUSE_SHIFT 9
202 #define CORE_GMNCFGCFG 0x0800
203 #define RST_MIB_CNT (1 << 0)
204 #define RXBPDU_EN (1 << 1)
206 #define CORE_IMP0_PRT_ID 0x0804
208 #define CORE_BRCM_HDR_CTRL 0x0080c
209 #define BRCM_HDR_EN_P8 (1 << 0)
210 #define BRCM_HDR_EN_P5 (1 << 1)
211 #define BRCM_HDR_EN_P7 (1 << 2)
213 #define CORE_RST_MIB_CNT_EN 0x0950
215 #define CORE_BRCM_HDR_RX_DIS 0x0980
216 #define CORE_BRCM_HDR_TX_DIS 0x0988
218 #define CORE_ARLA_VTBL_RWCTRL 0x1600
219 #define ARLA_VTBL_CMD_WRITE 0
220 #define ARLA_VTBL_CMD_READ 1
221 #define ARLA_VTBL_CMD_CLEAR 2
222 #define ARLA_VTBL_STDN (1 << 7)
224 #define CORE_ARLA_VTBL_ADDR 0x1604
225 #define VTBL_ADDR_INDEX_MASK 0xfff
227 #define CORE_ARLA_VTBL_ENTRY 0x160c
228 #define FWD_MAP_MASK 0x1ff
229 #define UNTAG_MAP_MASK 0x1ff
230 #define UNTAG_MAP_SHIFT 9
231 #define MSTP_INDEX_MASK 0x7
232 #define MSTP_INDEX_SHIFT 18
233 #define FWD_MODE (1 << 21)
235 #define CORE_MEM_PSM_VDD_CTRL 0x2380
236 #define P_TXQ_PSM_VDD_SHIFT 2
237 #define P_TXQ_PSM_VDD_MASK 0x3
238 #define P_TXQ_PSM_VDD(x) (P_TXQ_PSM_VDD_MASK << \
239 ((x) * P_TXQ_PSM_VDD_SHIFT))
241 #define CORE_PORT_VLAN_CTL_PORT(x) (0xc400 + ((x) * 0x8))
242 #define PORT_VLAN_CTRL_MASK 0x1ff
244 #define CORE_DEFAULT_1Q_TAG_P(x) (0xd040 + ((x) * 8))
249 #define CORE_JOIN_ALL_VLAN_EN 0xd140
251 #define CORE_EEE_EN_CTRL 0x24800
252 #define CORE_EEE_LPI_INDICATE 0x24810
254 #endif /* __BCM_SF2_REGS_H */