1 /**************************************************************************
2 Intel Pro 1000 for ppcboot/das-u-boot
3 Drivers are port from Intel's Linux driver e1000-4.3.15
4 and from Etherboot pro 1000 driver by mrakes at vivato dot net
5 tested on both gig copper and gig fiber boards
6 ***************************************************************************/
7 /*******************************************************************************
10 Copyright(c) 1999 - 2002 Intel Corporation. All rights reserved.
12 * SPDX-License-Identifier: GPL-2.0+
15 Linux NICS <linux.nics@intel.com>
16 Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
18 *******************************************************************************/
20 * Copyright (C) Archway Digital Solutions.
22 * written by Chrsitopher Li <cli at arcyway dot com> or <chrisl at gnuchina dot org>
25 * Copyright (C) Linux Networx.
26 * Massive upgrade to work with the new intel gigabit NICs.
27 * <ebiederman at lnxi dot com>
29 * Copyright 2011 Freescale Semiconductor, Inc.
34 #define TOUT_LOOP 100000
36 #define virt_to_bus(devno, v) pci_virt_to_mem(devno, (void *) (v))
37 #define bus_to_phys(devno, a) pci_mem_to_phys(devno, a)
39 #define E1000_DEFAULT_PCI_PBA 0x00000030
40 #define E1000_DEFAULT_PCIE_PBA 0x000a0026
42 /* NIC specific static variables go here */
44 /* Intel i210 needs the DMA descriptor rings aligned to 128b */
45 #define E1000_BUFFER_ALIGN 128
47 DEFINE_ALIGN_BUFFER(struct e1000_tx_desc, tx_base, 16, E1000_BUFFER_ALIGN);
48 DEFINE_ALIGN_BUFFER(struct e1000_rx_desc, rx_base, 16, E1000_BUFFER_ALIGN);
49 DEFINE_ALIGN_BUFFER(unsigned char, packet, 4096, E1000_BUFFER_ALIGN);
52 static int rx_tail, rx_last;
54 static struct pci_device_id e1000_supported[] = {
55 {PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82542},
56 {PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82543GC_FIBER},
57 {PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82543GC_COPPER},
58 {PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82544EI_COPPER},
59 {PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82544EI_FIBER},
60 {PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82544GC_COPPER},
61 {PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82544GC_LOM},
62 {PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82540EM},
63 {PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82545EM_COPPER},
64 {PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82545GM_COPPER},
65 {PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82546EB_COPPER},
66 {PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82545EM_FIBER},
67 {PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82546EB_FIBER},
68 {PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82546GB_COPPER},
69 {PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82540EM_LOM},
70 {PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82541ER},
71 {PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82541GI_LF},
73 {PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82571EB_COPPER},
74 {PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82571EB_FIBER },
75 {PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82571EB_SERDES },
76 {PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82571EB_QUAD_COPPER},
77 {PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82571PT_QUAD_COPPER},
78 {PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82571EB_QUAD_FIBER},
79 {PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82571EB_QUAD_COPPER_LOWPROFILE},
80 {PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82571EB_SERDES_DUAL},
81 {PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82571EB_SERDES_QUAD},
82 {PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82572EI_COPPER},
83 {PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82572EI_FIBER},
84 {PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82572EI_SERDES},
85 {PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82572EI},
86 {PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82573E},
87 {PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82573E_IAMT},
88 {PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82573L},
89 {PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82574L},
90 {PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82546GB_QUAD_COPPER_KSP3},
91 {PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_80003ES2LAN_COPPER_DPT},
92 {PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_80003ES2LAN_SERDES_DPT},
93 {PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_80003ES2LAN_COPPER_SPT},
94 {PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_80003ES2LAN_SERDES_SPT},
95 {PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_I210_UNPROGRAMMED},
96 {PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_I211_UNPROGRAMMED},
97 {PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_I210_COPPER},
98 {PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_I211_COPPER},
99 {PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_I210_COPPER_FLASHLESS},
100 {PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_I210_SERDES},
101 {PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_I210_SERDES_FLASHLESS},
102 {PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_I210_1000BASEKX},
107 /* Function forward declarations */
108 static int e1000_setup_link(struct eth_device *nic);
109 static int e1000_setup_fiber_link(struct eth_device *nic);
110 static int e1000_setup_copper_link(struct eth_device *nic);
111 static int e1000_phy_setup_autoneg(struct e1000_hw *hw);
112 static void e1000_config_collision_dist(struct e1000_hw *hw);
113 static int e1000_config_mac_to_phy(struct e1000_hw *hw);
114 static int e1000_config_fc_after_link_up(struct e1000_hw *hw);
115 static int e1000_check_for_link(struct eth_device *nic);
116 static int e1000_wait_autoneg(struct e1000_hw *hw);
117 static int e1000_get_speed_and_duplex(struct e1000_hw *hw, uint16_t * speed,
119 static int e1000_read_phy_reg(struct e1000_hw *hw, uint32_t reg_addr,
120 uint16_t * phy_data);
121 static int e1000_write_phy_reg(struct e1000_hw *hw, uint32_t reg_addr,
123 static int32_t e1000_phy_hw_reset(struct e1000_hw *hw);
124 static int e1000_phy_reset(struct e1000_hw *hw);
125 static int e1000_detect_gig_phy(struct e1000_hw *hw);
126 static void e1000_set_media_type(struct e1000_hw *hw);
128 static int32_t e1000_swfw_sync_acquire(struct e1000_hw *hw, uint16_t mask);
129 static void e1000_swfw_sync_release(struct e1000_hw *hw, uint16_t mask);
130 static int32_t e1000_check_phy_reset_block(struct e1000_hw *hw);
132 #ifndef CONFIG_E1000_NO_NVM
133 static void e1000_put_hw_eeprom_semaphore(struct e1000_hw *hw);
134 static int32_t e1000_read_eeprom(struct e1000_hw *hw, uint16_t offset,
137 /******************************************************************************
138 * Raises the EEPROM's clock input.
140 * hw - Struct containing variables accessed by shared code
141 * eecd - EECD's current value
142 *****************************************************************************/
143 void e1000_raise_ee_clk(struct e1000_hw *hw, uint32_t * eecd)
145 /* Raise the clock input to the EEPROM (by setting the SK bit), and then
146 * wait 50 microseconds.
148 *eecd = *eecd | E1000_EECD_SK;
149 E1000_WRITE_REG(hw, EECD, *eecd);
150 E1000_WRITE_FLUSH(hw);
154 /******************************************************************************
155 * Lowers the EEPROM's clock input.
157 * hw - Struct containing variables accessed by shared code
158 * eecd - EECD's current value
159 *****************************************************************************/
160 void e1000_lower_ee_clk(struct e1000_hw *hw, uint32_t * eecd)
162 /* Lower the clock input to the EEPROM (by clearing the SK bit), and then
163 * wait 50 microseconds.
165 *eecd = *eecd & ~E1000_EECD_SK;
166 E1000_WRITE_REG(hw, EECD, *eecd);
167 E1000_WRITE_FLUSH(hw);
171 /******************************************************************************
172 * Shift data bits out to the EEPROM.
174 * hw - Struct containing variables accessed by shared code
175 * data - data to send to the EEPROM
176 * count - number of bits to shift out
177 *****************************************************************************/
179 e1000_shift_out_ee_bits(struct e1000_hw *hw, uint16_t data, uint16_t count)
184 /* We need to shift "count" bits out to the EEPROM. So, value in the
185 * "data" parameter will be shifted out to the EEPROM one bit at a time.
186 * In order to do this, "data" must be broken down into bits.
188 mask = 0x01 << (count - 1);
189 eecd = E1000_READ_REG(hw, EECD);
190 eecd &= ~(E1000_EECD_DO | E1000_EECD_DI);
192 /* A "1" is shifted out to the EEPROM by setting bit "DI" to a "1",
193 * and then raising and then lowering the clock (the SK bit controls
194 * the clock input to the EEPROM). A "0" is shifted out to the EEPROM
195 * by setting "DI" to "0" and then raising and then lowering the clock.
197 eecd &= ~E1000_EECD_DI;
200 eecd |= E1000_EECD_DI;
202 E1000_WRITE_REG(hw, EECD, eecd);
203 E1000_WRITE_FLUSH(hw);
207 e1000_raise_ee_clk(hw, &eecd);
208 e1000_lower_ee_clk(hw, &eecd);
214 /* We leave the "DI" bit set to "0" when we leave this routine. */
215 eecd &= ~E1000_EECD_DI;
216 E1000_WRITE_REG(hw, EECD, eecd);
219 /******************************************************************************
220 * Shift data bits in from the EEPROM
222 * hw - Struct containing variables accessed by shared code
223 *****************************************************************************/
225 e1000_shift_in_ee_bits(struct e1000_hw *hw, uint16_t count)
231 /* In order to read a register from the EEPROM, we need to shift 'count'
232 * bits in from the EEPROM. Bits are "shifted in" by raising the clock
233 * input to the EEPROM (setting the SK bit), and then reading the
234 * value of the "DO" bit. During this "shifting in" process the
235 * "DI" bit should always be clear.
238 eecd = E1000_READ_REG(hw, EECD);
240 eecd &= ~(E1000_EECD_DO | E1000_EECD_DI);
243 for (i = 0; i < count; i++) {
245 e1000_raise_ee_clk(hw, &eecd);
247 eecd = E1000_READ_REG(hw, EECD);
249 eecd &= ~(E1000_EECD_DI);
250 if (eecd & E1000_EECD_DO)
253 e1000_lower_ee_clk(hw, &eecd);
259 /******************************************************************************
260 * Returns EEPROM to a "standby" state
262 * hw - Struct containing variables accessed by shared code
263 *****************************************************************************/
264 void e1000_standby_eeprom(struct e1000_hw *hw)
266 struct e1000_eeprom_info *eeprom = &hw->eeprom;
269 eecd = E1000_READ_REG(hw, EECD);
271 if (eeprom->type == e1000_eeprom_microwire) {
272 eecd &= ~(E1000_EECD_CS | E1000_EECD_SK);
273 E1000_WRITE_REG(hw, EECD, eecd);
274 E1000_WRITE_FLUSH(hw);
275 udelay(eeprom->delay_usec);
278 eecd |= E1000_EECD_SK;
279 E1000_WRITE_REG(hw, EECD, eecd);
280 E1000_WRITE_FLUSH(hw);
281 udelay(eeprom->delay_usec);
284 eecd |= E1000_EECD_CS;
285 E1000_WRITE_REG(hw, EECD, eecd);
286 E1000_WRITE_FLUSH(hw);
287 udelay(eeprom->delay_usec);
290 eecd &= ~E1000_EECD_SK;
291 E1000_WRITE_REG(hw, EECD, eecd);
292 E1000_WRITE_FLUSH(hw);
293 udelay(eeprom->delay_usec);
294 } else if (eeprom->type == e1000_eeprom_spi) {
295 /* Toggle CS to flush commands */
296 eecd |= E1000_EECD_CS;
297 E1000_WRITE_REG(hw, EECD, eecd);
298 E1000_WRITE_FLUSH(hw);
299 udelay(eeprom->delay_usec);
300 eecd &= ~E1000_EECD_CS;
301 E1000_WRITE_REG(hw, EECD, eecd);
302 E1000_WRITE_FLUSH(hw);
303 udelay(eeprom->delay_usec);
307 /***************************************************************************
308 * Description: Determines if the onboard NVM is FLASH or EEPROM.
310 * hw - Struct containing variables accessed by shared code
311 ****************************************************************************/
312 static bool e1000_is_onboard_nvm_eeprom(struct e1000_hw *hw)
318 if (hw->mac_type == e1000_ich8lan)
321 if (hw->mac_type == e1000_82573 || hw->mac_type == e1000_82574) {
322 eecd = E1000_READ_REG(hw, EECD);
324 /* Isolate bits 15 & 16 */
325 eecd = ((eecd >> 15) & 0x03);
327 /* If both bits are set, device is Flash type */
334 /******************************************************************************
335 * Prepares EEPROM for access
337 * hw - Struct containing variables accessed by shared code
339 * Lowers EEPROM clock. Clears input pin. Sets the chip select pin. This
340 * function should be called before issuing a command to the EEPROM.
341 *****************************************************************************/
342 int32_t e1000_acquire_eeprom(struct e1000_hw *hw)
344 struct e1000_eeprom_info *eeprom = &hw->eeprom;
345 uint32_t eecd, i = 0;
349 if (e1000_swfw_sync_acquire(hw, E1000_SWFW_EEP_SM))
350 return -E1000_ERR_SWFW_SYNC;
351 eecd = E1000_READ_REG(hw, EECD);
353 if (hw->mac_type != e1000_82573 && hw->mac_type != e1000_82574) {
354 /* Request EEPROM Access */
355 if (hw->mac_type > e1000_82544) {
356 eecd |= E1000_EECD_REQ;
357 E1000_WRITE_REG(hw, EECD, eecd);
358 eecd = E1000_READ_REG(hw, EECD);
359 while ((!(eecd & E1000_EECD_GNT)) &&
360 (i < E1000_EEPROM_GRANT_ATTEMPTS)) {
363 eecd = E1000_READ_REG(hw, EECD);
365 if (!(eecd & E1000_EECD_GNT)) {
366 eecd &= ~E1000_EECD_REQ;
367 E1000_WRITE_REG(hw, EECD, eecd);
368 DEBUGOUT("Could not acquire EEPROM grant\n");
369 return -E1000_ERR_EEPROM;
374 /* Setup EEPROM for Read/Write */
376 if (eeprom->type == e1000_eeprom_microwire) {
377 /* Clear SK and DI */
378 eecd &= ~(E1000_EECD_DI | E1000_EECD_SK);
379 E1000_WRITE_REG(hw, EECD, eecd);
382 eecd |= E1000_EECD_CS;
383 E1000_WRITE_REG(hw, EECD, eecd);
384 } else if (eeprom->type == e1000_eeprom_spi) {
385 /* Clear SK and CS */
386 eecd &= ~(E1000_EECD_CS | E1000_EECD_SK);
387 E1000_WRITE_REG(hw, EECD, eecd);
391 return E1000_SUCCESS;
394 /******************************************************************************
395 * Sets up eeprom variables in the hw struct. Must be called after mac_type
396 * is configured. Additionally, if this is ICH8, the flash controller GbE
397 * registers must be mapped, or this will crash.
399 * hw - Struct containing variables accessed by shared code
400 *****************************************************************************/
401 static int32_t e1000_init_eeprom_params(struct e1000_hw *hw)
403 struct e1000_eeprom_info *eeprom = &hw->eeprom;
405 int32_t ret_val = E1000_SUCCESS;
406 uint16_t eeprom_size;
408 if (hw->mac_type == e1000_igb)
409 eecd = E1000_READ_REG(hw, I210_EECD);
411 eecd = E1000_READ_REG(hw, EECD);
415 switch (hw->mac_type) {
416 case e1000_82542_rev2_0:
417 case e1000_82542_rev2_1:
420 eeprom->type = e1000_eeprom_microwire;
421 eeprom->word_size = 64;
422 eeprom->opcode_bits = 3;
423 eeprom->address_bits = 6;
424 eeprom->delay_usec = 50;
425 eeprom->use_eerd = false;
426 eeprom->use_eewr = false;
430 case e1000_82545_rev_3:
432 case e1000_82546_rev_3:
433 eeprom->type = e1000_eeprom_microwire;
434 eeprom->opcode_bits = 3;
435 eeprom->delay_usec = 50;
436 if (eecd & E1000_EECD_SIZE) {
437 eeprom->word_size = 256;
438 eeprom->address_bits = 8;
440 eeprom->word_size = 64;
441 eeprom->address_bits = 6;
443 eeprom->use_eerd = false;
444 eeprom->use_eewr = false;
447 case e1000_82541_rev_2:
449 case e1000_82547_rev_2:
450 if (eecd & E1000_EECD_TYPE) {
451 eeprom->type = e1000_eeprom_spi;
452 eeprom->opcode_bits = 8;
453 eeprom->delay_usec = 1;
454 if (eecd & E1000_EECD_ADDR_BITS) {
455 eeprom->page_size = 32;
456 eeprom->address_bits = 16;
458 eeprom->page_size = 8;
459 eeprom->address_bits = 8;
462 eeprom->type = e1000_eeprom_microwire;
463 eeprom->opcode_bits = 3;
464 eeprom->delay_usec = 50;
465 if (eecd & E1000_EECD_ADDR_BITS) {
466 eeprom->word_size = 256;
467 eeprom->address_bits = 8;
469 eeprom->word_size = 64;
470 eeprom->address_bits = 6;
473 eeprom->use_eerd = false;
474 eeprom->use_eewr = false;
478 eeprom->type = e1000_eeprom_spi;
479 eeprom->opcode_bits = 8;
480 eeprom->delay_usec = 1;
481 if (eecd & E1000_EECD_ADDR_BITS) {
482 eeprom->page_size = 32;
483 eeprom->address_bits = 16;
485 eeprom->page_size = 8;
486 eeprom->address_bits = 8;
488 eeprom->use_eerd = false;
489 eeprom->use_eewr = false;
493 eeprom->type = e1000_eeprom_spi;
494 eeprom->opcode_bits = 8;
495 eeprom->delay_usec = 1;
496 if (eecd & E1000_EECD_ADDR_BITS) {
497 eeprom->page_size = 32;
498 eeprom->address_bits = 16;
500 eeprom->page_size = 8;
501 eeprom->address_bits = 8;
503 if (e1000_is_onboard_nvm_eeprom(hw) == false) {
504 eeprom->use_eerd = true;
505 eeprom->use_eewr = true;
507 eeprom->type = e1000_eeprom_flash;
508 eeprom->word_size = 2048;
510 /* Ensure that the Autonomous FLASH update bit is cleared due to
511 * Flash update issue on parts which use a FLASH for NVM. */
512 eecd &= ~E1000_EECD_AUPDEN;
513 E1000_WRITE_REG(hw, EECD, eecd);
516 case e1000_80003es2lan:
517 eeprom->type = e1000_eeprom_spi;
518 eeprom->opcode_bits = 8;
519 eeprom->delay_usec = 1;
520 if (eecd & E1000_EECD_ADDR_BITS) {
521 eeprom->page_size = 32;
522 eeprom->address_bits = 16;
524 eeprom->page_size = 8;
525 eeprom->address_bits = 8;
527 eeprom->use_eerd = true;
528 eeprom->use_eewr = false;
531 /* i210 has 4k of iNVM mapped as EEPROM */
532 eeprom->type = e1000_eeprom_invm;
533 eeprom->opcode_bits = 8;
534 eeprom->delay_usec = 1;
535 eeprom->page_size = 32;
536 eeprom->address_bits = 16;
537 eeprom->use_eerd = true;
538 eeprom->use_eewr = false;
541 /* ich8lan does not support currently. if needed, please
542 * add corresponding code and functions.
549 eeprom->type = e1000_eeprom_ich8;
550 eeprom->use_eerd = false;
551 eeprom->use_eewr = false;
552 eeprom->word_size = E1000_SHADOW_RAM_WORDS;
553 uint32_t flash_size = E1000_READ_ICH_FLASH_REG(hw,
555 /* Zero the shadow RAM structure. But don't load it from NVM
556 * so as to save time for driver init */
557 if (hw->eeprom_shadow_ram != NULL) {
558 for (i = 0; i < E1000_SHADOW_RAM_WORDS; i++) {
559 hw->eeprom_shadow_ram[i].modified = false;
560 hw->eeprom_shadow_ram[i].eeprom_word = 0xFFFF;
564 hw->flash_base_addr = (flash_size & ICH_GFPREG_BASE_MASK) *
565 ICH_FLASH_SECTOR_SIZE;
567 hw->flash_bank_size = ((flash_size >> 16)
568 & ICH_GFPREG_BASE_MASK) + 1;
569 hw->flash_bank_size -= (flash_size & ICH_GFPREG_BASE_MASK);
571 hw->flash_bank_size *= ICH_FLASH_SECTOR_SIZE;
573 hw->flash_bank_size /= 2 * sizeof(uint16_t);
581 if (eeprom->type == e1000_eeprom_spi ||
582 eeprom->type == e1000_eeprom_invm) {
583 /* eeprom_size will be an enum [0..8] that maps
584 * to eeprom sizes 128B to
585 * 32KB (incremented by powers of 2).
587 if (hw->mac_type <= e1000_82547_rev_2) {
588 /* Set to default value for initial eeprom read. */
589 eeprom->word_size = 64;
590 ret_val = e1000_read_eeprom(hw, EEPROM_CFG, 1,
594 eeprom_size = (eeprom_size & EEPROM_SIZE_MASK)
595 >> EEPROM_SIZE_SHIFT;
596 /* 256B eeprom size was not supported in earlier
597 * hardware, so we bump eeprom_size up one to
598 * ensure that "1" (which maps to 256B) is never
599 * the result used in the shifting logic below. */
603 eeprom_size = (uint16_t)((eecd &
604 E1000_EECD_SIZE_EX_MASK) >>
605 E1000_EECD_SIZE_EX_SHIFT);
608 eeprom->word_size = 1 << (eeprom_size + EEPROM_WORD_SIZE_SHIFT);
613 /******************************************************************************
614 * Polls the status bit (bit 1) of the EERD to determine when the read is done.
616 * hw - Struct containing variables accessed by shared code
617 *****************************************************************************/
619 e1000_poll_eerd_eewr_done(struct e1000_hw *hw, int eerd)
621 uint32_t attempts = 100000;
623 int32_t done = E1000_ERR_EEPROM;
625 for (i = 0; i < attempts; i++) {
626 if (eerd == E1000_EEPROM_POLL_READ) {
627 if (hw->mac_type == e1000_igb)
628 reg = E1000_READ_REG(hw, I210_EERD);
630 reg = E1000_READ_REG(hw, EERD);
632 if (hw->mac_type == e1000_igb)
633 reg = E1000_READ_REG(hw, I210_EEWR);
635 reg = E1000_READ_REG(hw, EEWR);
638 if (reg & E1000_EEPROM_RW_REG_DONE) {
639 done = E1000_SUCCESS;
648 /******************************************************************************
649 * Reads a 16 bit word from the EEPROM using the EERD register.
651 * hw - Struct containing variables accessed by shared code
652 * offset - offset of word in the EEPROM to read
653 * data - word read from the EEPROM
654 * words - number of words to read
655 *****************************************************************************/
657 e1000_read_eeprom_eerd(struct e1000_hw *hw,
662 uint32_t i, eerd = 0;
665 for (i = 0; i < words; i++) {
666 eerd = ((offset+i) << E1000_EEPROM_RW_ADDR_SHIFT) +
667 E1000_EEPROM_RW_REG_START;
669 if (hw->mac_type == e1000_igb)
670 E1000_WRITE_REG(hw, I210_EERD, eerd);
672 E1000_WRITE_REG(hw, EERD, eerd);
674 error = e1000_poll_eerd_eewr_done(hw, E1000_EEPROM_POLL_READ);
679 if (hw->mac_type == e1000_igb) {
680 data[i] = (E1000_READ_REG(hw, I210_EERD) >>
681 E1000_EEPROM_RW_REG_DATA);
683 data[i] = (E1000_READ_REG(hw, EERD) >>
684 E1000_EEPROM_RW_REG_DATA);
692 void e1000_release_eeprom(struct e1000_hw *hw)
698 eecd = E1000_READ_REG(hw, EECD);
700 if (hw->eeprom.type == e1000_eeprom_spi) {
701 eecd |= E1000_EECD_CS; /* Pull CS high */
702 eecd &= ~E1000_EECD_SK; /* Lower SCK */
704 E1000_WRITE_REG(hw, EECD, eecd);
706 udelay(hw->eeprom.delay_usec);
707 } else if (hw->eeprom.type == e1000_eeprom_microwire) {
710 /* CS on Microwire is active-high */
711 eecd &= ~(E1000_EECD_CS | E1000_EECD_DI);
713 E1000_WRITE_REG(hw, EECD, eecd);
715 /* Rising edge of clock */
716 eecd |= E1000_EECD_SK;
717 E1000_WRITE_REG(hw, EECD, eecd);
718 E1000_WRITE_FLUSH(hw);
719 udelay(hw->eeprom.delay_usec);
721 /* Falling edge of clock */
722 eecd &= ~E1000_EECD_SK;
723 E1000_WRITE_REG(hw, EECD, eecd);
724 E1000_WRITE_FLUSH(hw);
725 udelay(hw->eeprom.delay_usec);
728 /* Stop requesting EEPROM access */
729 if (hw->mac_type > e1000_82544) {
730 eecd &= ~E1000_EECD_REQ;
731 E1000_WRITE_REG(hw, EECD, eecd);
734 e1000_swfw_sync_release(hw, E1000_SWFW_EEP_SM);
737 /******************************************************************************
738 * Reads a 16 bit word from the EEPROM.
740 * hw - Struct containing variables accessed by shared code
741 *****************************************************************************/
743 e1000_spi_eeprom_ready(struct e1000_hw *hw)
745 uint16_t retry_count = 0;
746 uint8_t spi_stat_reg;
750 /* Read "Status Register" repeatedly until the LSB is cleared. The
751 * EEPROM will signal that the command has been completed by clearing
752 * bit 0 of the internal status register. If it's not cleared within
753 * 5 milliseconds, then error out.
757 e1000_shift_out_ee_bits(hw, EEPROM_RDSR_OPCODE_SPI,
758 hw->eeprom.opcode_bits);
759 spi_stat_reg = (uint8_t)e1000_shift_in_ee_bits(hw, 8);
760 if (!(spi_stat_reg & EEPROM_STATUS_RDY_SPI))
766 e1000_standby_eeprom(hw);
767 } while (retry_count < EEPROM_MAX_RETRY_SPI);
769 /* ATMEL SPI write time could vary from 0-20mSec on 3.3V devices (and
770 * only 0-5mSec on 5V devices)
772 if (retry_count >= EEPROM_MAX_RETRY_SPI) {
773 DEBUGOUT("SPI EEPROM Status error\n");
774 return -E1000_ERR_EEPROM;
777 return E1000_SUCCESS;
780 /******************************************************************************
781 * Reads a 16 bit word from the EEPROM.
783 * hw - Struct containing variables accessed by shared code
784 * offset - offset of word in the EEPROM to read
785 * data - word read from the EEPROM
786 *****************************************************************************/
788 e1000_read_eeprom(struct e1000_hw *hw, uint16_t offset,
789 uint16_t words, uint16_t *data)
791 struct e1000_eeprom_info *eeprom = &hw->eeprom;
796 /* If eeprom is not yet detected, do so now */
797 if (eeprom->word_size == 0)
798 e1000_init_eeprom_params(hw);
800 /* A check for invalid values: offset too large, too many words,
801 * and not enough words.
803 if ((offset >= eeprom->word_size) ||
804 (words > eeprom->word_size - offset) ||
806 DEBUGOUT("\"words\" parameter out of bounds."
807 "Words = %d, size = %d\n", offset, eeprom->word_size);
808 return -E1000_ERR_EEPROM;
811 /* EEPROM's that don't use EERD to read require us to bit-bang the SPI
812 * directly. In this case, we need to acquire the EEPROM so that
813 * FW or other port software does not interrupt.
815 if (e1000_is_onboard_nvm_eeprom(hw) == true &&
816 hw->eeprom.use_eerd == false) {
818 /* Prepare the EEPROM for bit-bang reading */
819 if (e1000_acquire_eeprom(hw) != E1000_SUCCESS)
820 return -E1000_ERR_EEPROM;
823 /* Eerd register EEPROM access requires no eeprom aquire/release */
824 if (eeprom->use_eerd == true)
825 return e1000_read_eeprom_eerd(hw, offset, words, data);
827 /* ich8lan does not support currently. if needed, please
828 * add corresponding code and functions.
831 /* ICH EEPROM access is done via the ICH flash controller */
832 if (eeprom->type == e1000_eeprom_ich8)
833 return e1000_read_eeprom_ich8(hw, offset, words, data);
835 /* Set up the SPI or Microwire EEPROM for bit-bang reading. We have
836 * acquired the EEPROM at this point, so any returns should relase it */
837 if (eeprom->type == e1000_eeprom_spi) {
839 uint8_t read_opcode = EEPROM_READ_OPCODE_SPI;
841 if (e1000_spi_eeprom_ready(hw)) {
842 e1000_release_eeprom(hw);
843 return -E1000_ERR_EEPROM;
846 e1000_standby_eeprom(hw);
848 /* Some SPI eeproms use the 8th address bit embedded in
850 if ((eeprom->address_bits == 8) && (offset >= 128))
851 read_opcode |= EEPROM_A8_OPCODE_SPI;
853 /* Send the READ command (opcode + addr) */
854 e1000_shift_out_ee_bits(hw, read_opcode, eeprom->opcode_bits);
855 e1000_shift_out_ee_bits(hw, (uint16_t)(offset*2),
856 eeprom->address_bits);
858 /* Read the data. The address of the eeprom internally
859 * increments with each byte (spi) being read, saving on the
860 * overhead of eeprom setup and tear-down. The address
861 * counter will roll over if reading beyond the size of
862 * the eeprom, thus allowing the entire memory to be read
863 * starting from any offset. */
864 for (i = 0; i < words; i++) {
865 word_in = e1000_shift_in_ee_bits(hw, 16);
866 data[i] = (word_in >> 8) | (word_in << 8);
868 } else if (eeprom->type == e1000_eeprom_microwire) {
869 for (i = 0; i < words; i++) {
870 /* Send the READ command (opcode + addr) */
871 e1000_shift_out_ee_bits(hw,
872 EEPROM_READ_OPCODE_MICROWIRE,
873 eeprom->opcode_bits);
874 e1000_shift_out_ee_bits(hw, (uint16_t)(offset + i),
875 eeprom->address_bits);
877 /* Read the data. For microwire, each word requires
878 * the overhead of eeprom setup and tear-down. */
879 data[i] = e1000_shift_in_ee_bits(hw, 16);
880 e1000_standby_eeprom(hw);
884 /* End this read operation */
885 e1000_release_eeprom(hw);
887 return E1000_SUCCESS;
890 /******************************************************************************
891 * Verifies that the EEPROM has a valid checksum
893 * hw - Struct containing variables accessed by shared code
895 * Reads the first 64 16 bit words of the EEPROM and sums the values read.
896 * If the the sum of the 64 16 bit words is 0xBABA, the EEPROM's checksum is
898 *****************************************************************************/
899 static int e1000_validate_eeprom_checksum(struct e1000_hw *hw)
901 uint16_t i, checksum, checksum_reg, *buf;
905 /* Allocate a temporary buffer */
906 buf = malloc(sizeof(buf[0]) * (EEPROM_CHECKSUM_REG + 1));
908 E1000_ERR(hw->nic, "Unable to allocate EEPROM buffer!\n");
909 return -E1000_ERR_EEPROM;
912 /* Read the EEPROM */
913 if (e1000_read_eeprom(hw, 0, EEPROM_CHECKSUM_REG + 1, buf) < 0) {
914 E1000_ERR(hw->nic, "Unable to read EEPROM!\n");
915 return -E1000_ERR_EEPROM;
918 /* Compute the checksum */
920 for (i = 0; i < EEPROM_CHECKSUM_REG; i++)
922 checksum = ((uint16_t)EEPROM_SUM) - checksum;
923 checksum_reg = buf[i];
926 if (checksum == checksum_reg)
929 /* Hrm, verification failed, print an error */
930 E1000_ERR(hw->nic, "EEPROM checksum is incorrect!\n");
931 E1000_ERR(hw->nic, " ...register was 0x%04hx, calculated 0x%04hx\n",
932 checksum_reg, checksum);
934 return -E1000_ERR_EEPROM;
936 #endif /* CONFIG_E1000_NO_NVM */
938 /*****************************************************************************
939 * Set PHY to class A mode
940 * Assumes the following operations will follow to enable the new class mode.
941 * 1. Do a PHY soft reset
942 * 2. Restart auto-negotiation or force link.
944 * hw - Struct containing variables accessed by shared code
945 ****************************************************************************/
947 e1000_set_phy_mode(struct e1000_hw *hw)
949 #ifndef CONFIG_E1000_NO_NVM
951 uint16_t eeprom_data;
955 if ((hw->mac_type == e1000_82545_rev_3) &&
956 (hw->media_type == e1000_media_type_copper)) {
957 ret_val = e1000_read_eeprom(hw, EEPROM_PHY_CLASS_WORD,
962 if ((eeprom_data != EEPROM_RESERVED_WORD) &&
963 (eeprom_data & EEPROM_PHY_CLASS_A)) {
964 ret_val = e1000_write_phy_reg(hw,
965 M88E1000_PHY_PAGE_SELECT, 0x000B);
968 ret_val = e1000_write_phy_reg(hw,
969 M88E1000_PHY_GEN_CONTROL, 0x8104);
973 hw->phy_reset_disable = false;
977 return E1000_SUCCESS;
980 #ifndef CONFIG_E1000_NO_NVM
981 /***************************************************************************
983 * Obtaining software semaphore bit (SMBI) before resetting PHY.
985 * hw: Struct containing variables accessed by shared code
987 * returns: - E1000_ERR_RESET if fail to obtain semaphore.
988 * E1000_SUCCESS at any other case.
990 ***************************************************************************/
992 e1000_get_software_semaphore(struct e1000_hw *hw)
994 int32_t timeout = hw->eeprom.word_size + 1;
999 swsm = E1000_READ_REG(hw, SWSM);
1000 swsm &= ~E1000_SWSM_SMBI;
1001 E1000_WRITE_REG(hw, SWSM, swsm);
1003 if (hw->mac_type != e1000_80003es2lan)
1004 return E1000_SUCCESS;
1007 swsm = E1000_READ_REG(hw, SWSM);
1008 /* If SMBI bit cleared, it is now set and we hold
1010 if (!(swsm & E1000_SWSM_SMBI))
1017 DEBUGOUT("Driver can't access device - SMBI bit is set.\n");
1018 return -E1000_ERR_RESET;
1021 return E1000_SUCCESS;
1025 /***************************************************************************
1026 * This function clears HW semaphore bits.
1028 * hw: Struct containing variables accessed by shared code
1032 ***************************************************************************/
1034 e1000_put_hw_eeprom_semaphore(struct e1000_hw *hw)
1036 #ifndef CONFIG_E1000_NO_NVM
1041 if (!hw->eeprom_semaphore_present)
1044 swsm = E1000_READ_REG(hw, SWSM);
1045 if (hw->mac_type == e1000_80003es2lan) {
1046 /* Release both semaphores. */
1047 swsm &= ~(E1000_SWSM_SMBI | E1000_SWSM_SWESMBI);
1049 swsm &= ~(E1000_SWSM_SWESMBI);
1050 E1000_WRITE_REG(hw, SWSM, swsm);
1054 /***************************************************************************
1056 * Using the combination of SMBI and SWESMBI semaphore bits when resetting
1057 * adapter or Eeprom access.
1059 * hw: Struct containing variables accessed by shared code
1061 * returns: - E1000_ERR_EEPROM if fail to access EEPROM.
1062 * E1000_SUCCESS at any other case.
1064 ***************************************************************************/
1066 e1000_get_hw_eeprom_semaphore(struct e1000_hw *hw)
1068 #ifndef CONFIG_E1000_NO_NVM
1074 if (!hw->eeprom_semaphore_present)
1075 return E1000_SUCCESS;
1077 if (hw->mac_type == e1000_80003es2lan) {
1078 /* Get the SW semaphore. */
1079 if (e1000_get_software_semaphore(hw) != E1000_SUCCESS)
1080 return -E1000_ERR_EEPROM;
1083 /* Get the FW semaphore. */
1084 timeout = hw->eeprom.word_size + 1;
1086 swsm = E1000_READ_REG(hw, SWSM);
1087 swsm |= E1000_SWSM_SWESMBI;
1088 E1000_WRITE_REG(hw, SWSM, swsm);
1089 /* if we managed to set the bit we got the semaphore. */
1090 swsm = E1000_READ_REG(hw, SWSM);
1091 if (swsm & E1000_SWSM_SWESMBI)
1099 /* Release semaphores */
1100 e1000_put_hw_eeprom_semaphore(hw);
1101 DEBUGOUT("Driver can't access the Eeprom - "
1102 "SWESMBI bit is set.\n");
1103 return -E1000_ERR_EEPROM;
1106 return E1000_SUCCESS;
1109 /* Take ownership of the PHY */
1111 e1000_swfw_sync_acquire(struct e1000_hw *hw, uint16_t mask)
1113 uint32_t swfw_sync = 0;
1114 uint32_t swmask = mask;
1115 uint32_t fwmask = mask << 16;
1116 int32_t timeout = 200;
1120 if (e1000_get_hw_eeprom_semaphore(hw))
1121 return -E1000_ERR_SWFW_SYNC;
1123 if (hw->mac_type == e1000_igb)
1124 swfw_sync = E1000_READ_REG(hw, I210_SW_FW_SYNC);
1126 swfw_sync = E1000_READ_REG(hw, SW_FW_SYNC);
1127 if (!(swfw_sync & (fwmask | swmask)))
1130 /* firmware currently using resource (fwmask) */
1131 /* or other software thread currently using resource (swmask) */
1132 e1000_put_hw_eeprom_semaphore(hw);
1138 DEBUGOUT("Driver can't access resource, SW_FW_SYNC timeout.\n");
1139 return -E1000_ERR_SWFW_SYNC;
1142 swfw_sync |= swmask;
1143 E1000_WRITE_REG(hw, SW_FW_SYNC, swfw_sync);
1145 e1000_put_hw_eeprom_semaphore(hw);
1146 return E1000_SUCCESS;
1149 static void e1000_swfw_sync_release(struct e1000_hw *hw, uint16_t mask)
1151 uint32_t swfw_sync = 0;
1154 while (e1000_get_hw_eeprom_semaphore(hw))
1157 swfw_sync = E1000_READ_REG(hw, SW_FW_SYNC);
1159 E1000_WRITE_REG(hw, SW_FW_SYNC, swfw_sync);
1161 e1000_put_hw_eeprom_semaphore(hw);
1164 static bool e1000_is_second_port(struct e1000_hw *hw)
1166 switch (hw->mac_type) {
1167 case e1000_80003es2lan:
1170 if (E1000_READ_REG(hw, STATUS) & E1000_STATUS_FUNC_1)
1178 #ifndef CONFIG_E1000_NO_NVM
1179 /******************************************************************************
1180 * Reads the adapter's MAC address from the EEPROM and inverts the LSB for the
1181 * second function of dual function devices
1183 * nic - Struct containing variables accessed by shared code
1184 *****************************************************************************/
1186 e1000_read_mac_addr(struct eth_device *nic)
1188 struct e1000_hw *hw = nic->priv;
1190 uint16_t eeprom_data;
1191 uint32_t reg_data = 0;
1196 for (i = 0; i < NODE_ADDRESS_SIZE; i += 2) {
1198 if (hw->mac_type == e1000_igb) {
1199 /* i210 preloads MAC address into RAL/RAH registers */
1201 reg_data = E1000_READ_REG_ARRAY(hw, RA, 0);
1202 else if (offset == 1)
1204 else if (offset == 2)
1205 reg_data = E1000_READ_REG_ARRAY(hw, RA, 1);
1206 eeprom_data = reg_data & 0xffff;
1207 } else if (e1000_read_eeprom(hw, offset, 1, &eeprom_data) < 0) {
1208 DEBUGOUT("EEPROM Read Error\n");
1209 return -E1000_ERR_EEPROM;
1211 nic->enetaddr[i] = eeprom_data & 0xff;
1212 nic->enetaddr[i + 1] = (eeprom_data >> 8) & 0xff;
1215 /* Invert the last bit if this is the second device */
1216 if (e1000_is_second_port(hw))
1217 nic->enetaddr[5] ^= 1;
1219 #ifdef CONFIG_E1000_FALLBACK_MAC
1220 if (!is_valid_ethaddr(nic->enetaddr)) {
1221 unsigned char fb_mac[NODE_ADDRESS_SIZE] = CONFIG_E1000_FALLBACK_MAC;
1223 memcpy (nic->enetaddr, fb_mac, NODE_ADDRESS_SIZE);
1230 /******************************************************************************
1231 * Initializes receive address filters.
1233 * hw - Struct containing variables accessed by shared code
1235 * Places the MAC address in receive address register 0 and clears the rest
1236 * of the receive addresss registers. Clears the multicast table. Assumes
1237 * the receiver is in reset when the routine is called.
1238 *****************************************************************************/
1240 e1000_init_rx_addrs(struct eth_device *nic)
1242 struct e1000_hw *hw = nic->priv;
1249 /* Setup the receive address. */
1250 DEBUGOUT("Programming MAC Address into RAR[0]\n");
1251 addr_low = (nic->enetaddr[0] |
1252 (nic->enetaddr[1] << 8) |
1253 (nic->enetaddr[2] << 16) | (nic->enetaddr[3] << 24));
1255 addr_high = (nic->enetaddr[4] | (nic->enetaddr[5] << 8) | E1000_RAH_AV);
1257 E1000_WRITE_REG_ARRAY(hw, RA, 0, addr_low);
1258 E1000_WRITE_REG_ARRAY(hw, RA, 1, addr_high);
1260 /* Zero out the other 15 receive addresses. */
1261 DEBUGOUT("Clearing RAR[1-15]\n");
1262 for (i = 1; i < E1000_RAR_ENTRIES; i++) {
1263 E1000_WRITE_REG_ARRAY(hw, RA, (i << 1), 0);
1264 E1000_WRITE_REG_ARRAY(hw, RA, ((i << 1) + 1), 0);
1268 /******************************************************************************
1269 * Clears the VLAN filer table
1271 * hw - Struct containing variables accessed by shared code
1272 *****************************************************************************/
1274 e1000_clear_vfta(struct e1000_hw *hw)
1278 for (offset = 0; offset < E1000_VLAN_FILTER_TBL_SIZE; offset++)
1279 E1000_WRITE_REG_ARRAY(hw, VFTA, offset, 0);
1282 /******************************************************************************
1283 * Set the mac type member in the hw struct.
1285 * hw - Struct containing variables accessed by shared code
1286 *****************************************************************************/
1288 e1000_set_mac_type(struct e1000_hw *hw)
1292 switch (hw->device_id) {
1293 case E1000_DEV_ID_82542:
1294 switch (hw->revision_id) {
1295 case E1000_82542_2_0_REV_ID:
1296 hw->mac_type = e1000_82542_rev2_0;
1298 case E1000_82542_2_1_REV_ID:
1299 hw->mac_type = e1000_82542_rev2_1;
1302 /* Invalid 82542 revision ID */
1303 return -E1000_ERR_MAC_TYPE;
1306 case E1000_DEV_ID_82543GC_FIBER:
1307 case E1000_DEV_ID_82543GC_COPPER:
1308 hw->mac_type = e1000_82543;
1310 case E1000_DEV_ID_82544EI_COPPER:
1311 case E1000_DEV_ID_82544EI_FIBER:
1312 case E1000_DEV_ID_82544GC_COPPER:
1313 case E1000_DEV_ID_82544GC_LOM:
1314 hw->mac_type = e1000_82544;
1316 case E1000_DEV_ID_82540EM:
1317 case E1000_DEV_ID_82540EM_LOM:
1318 case E1000_DEV_ID_82540EP:
1319 case E1000_DEV_ID_82540EP_LOM:
1320 case E1000_DEV_ID_82540EP_LP:
1321 hw->mac_type = e1000_82540;
1323 case E1000_DEV_ID_82545EM_COPPER:
1324 case E1000_DEV_ID_82545EM_FIBER:
1325 hw->mac_type = e1000_82545;
1327 case E1000_DEV_ID_82545GM_COPPER:
1328 case E1000_DEV_ID_82545GM_FIBER:
1329 case E1000_DEV_ID_82545GM_SERDES:
1330 hw->mac_type = e1000_82545_rev_3;
1332 case E1000_DEV_ID_82546EB_COPPER:
1333 case E1000_DEV_ID_82546EB_FIBER:
1334 case E1000_DEV_ID_82546EB_QUAD_COPPER:
1335 hw->mac_type = e1000_82546;
1337 case E1000_DEV_ID_82546GB_COPPER:
1338 case E1000_DEV_ID_82546GB_FIBER:
1339 case E1000_DEV_ID_82546GB_SERDES:
1340 case E1000_DEV_ID_82546GB_PCIE:
1341 case E1000_DEV_ID_82546GB_QUAD_COPPER:
1342 case E1000_DEV_ID_82546GB_QUAD_COPPER_KSP3:
1343 hw->mac_type = e1000_82546_rev_3;
1345 case E1000_DEV_ID_82541EI:
1346 case E1000_DEV_ID_82541EI_MOBILE:
1347 case E1000_DEV_ID_82541ER_LOM:
1348 hw->mac_type = e1000_82541;
1350 case E1000_DEV_ID_82541ER:
1351 case E1000_DEV_ID_82541GI:
1352 case E1000_DEV_ID_82541GI_LF:
1353 case E1000_DEV_ID_82541GI_MOBILE:
1354 hw->mac_type = e1000_82541_rev_2;
1356 case E1000_DEV_ID_82547EI:
1357 case E1000_DEV_ID_82547EI_MOBILE:
1358 hw->mac_type = e1000_82547;
1360 case E1000_DEV_ID_82547GI:
1361 hw->mac_type = e1000_82547_rev_2;
1363 case E1000_DEV_ID_82571EB_COPPER:
1364 case E1000_DEV_ID_82571EB_FIBER:
1365 case E1000_DEV_ID_82571EB_SERDES:
1366 case E1000_DEV_ID_82571EB_SERDES_DUAL:
1367 case E1000_DEV_ID_82571EB_SERDES_QUAD:
1368 case E1000_DEV_ID_82571EB_QUAD_COPPER:
1369 case E1000_DEV_ID_82571PT_QUAD_COPPER:
1370 case E1000_DEV_ID_82571EB_QUAD_FIBER:
1371 case E1000_DEV_ID_82571EB_QUAD_COPPER_LOWPROFILE:
1372 hw->mac_type = e1000_82571;
1374 case E1000_DEV_ID_82572EI_COPPER:
1375 case E1000_DEV_ID_82572EI_FIBER:
1376 case E1000_DEV_ID_82572EI_SERDES:
1377 case E1000_DEV_ID_82572EI:
1378 hw->mac_type = e1000_82572;
1380 case E1000_DEV_ID_82573E:
1381 case E1000_DEV_ID_82573E_IAMT:
1382 case E1000_DEV_ID_82573L:
1383 hw->mac_type = e1000_82573;
1385 case E1000_DEV_ID_82574L:
1386 hw->mac_type = e1000_82574;
1388 case E1000_DEV_ID_80003ES2LAN_COPPER_SPT:
1389 case E1000_DEV_ID_80003ES2LAN_SERDES_SPT:
1390 case E1000_DEV_ID_80003ES2LAN_COPPER_DPT:
1391 case E1000_DEV_ID_80003ES2LAN_SERDES_DPT:
1392 hw->mac_type = e1000_80003es2lan;
1394 case E1000_DEV_ID_ICH8_IGP_M_AMT:
1395 case E1000_DEV_ID_ICH8_IGP_AMT:
1396 case E1000_DEV_ID_ICH8_IGP_C:
1397 case E1000_DEV_ID_ICH8_IFE:
1398 case E1000_DEV_ID_ICH8_IFE_GT:
1399 case E1000_DEV_ID_ICH8_IFE_G:
1400 case E1000_DEV_ID_ICH8_IGP_M:
1401 hw->mac_type = e1000_ich8lan;
1403 case PCI_DEVICE_ID_INTEL_I210_UNPROGRAMMED:
1404 case PCI_DEVICE_ID_INTEL_I211_UNPROGRAMMED:
1405 case PCI_DEVICE_ID_INTEL_I210_COPPER:
1406 case PCI_DEVICE_ID_INTEL_I211_COPPER:
1407 case PCI_DEVICE_ID_INTEL_I210_COPPER_FLASHLESS:
1408 case PCI_DEVICE_ID_INTEL_I210_SERDES:
1409 case PCI_DEVICE_ID_INTEL_I210_SERDES_FLASHLESS:
1410 case PCI_DEVICE_ID_INTEL_I210_1000BASEKX:
1411 hw->mac_type = e1000_igb;
1414 /* Should never have loaded on this device */
1415 return -E1000_ERR_MAC_TYPE;
1417 return E1000_SUCCESS;
1420 /******************************************************************************
1421 * Reset the transmit and receive units; mask and clear all interrupts.
1423 * hw - Struct containing variables accessed by shared code
1424 *****************************************************************************/
1426 e1000_reset_hw(struct e1000_hw *hw)
1436 /* get the correct pba value for both PCI and PCIe*/
1437 if (hw->mac_type < e1000_82571)
1438 pba = E1000_DEFAULT_PCI_PBA;
1440 pba = E1000_DEFAULT_PCIE_PBA;
1442 /* For 82542 (rev 2.0), disable MWI before issuing a device reset */
1443 if (hw->mac_type == e1000_82542_rev2_0) {
1444 DEBUGOUT("Disabling MWI on 82542 rev 2.0\n");
1445 pci_write_config_word(hw->pdev, PCI_COMMAND,
1446 hw->pci_cmd_word & ~PCI_COMMAND_INVALIDATE);
1449 /* Clear interrupt mask to stop board from generating interrupts */
1450 DEBUGOUT("Masking off all interrupts\n");
1451 if (hw->mac_type == e1000_igb)
1452 E1000_WRITE_REG(hw, I210_IAM, 0);
1453 E1000_WRITE_REG(hw, IMC, 0xffffffff);
1455 /* Disable the Transmit and Receive units. Then delay to allow
1456 * any pending transactions to complete before we hit the MAC with
1459 E1000_WRITE_REG(hw, RCTL, 0);
1460 E1000_WRITE_REG(hw, TCTL, E1000_TCTL_PSP);
1461 E1000_WRITE_FLUSH(hw);
1463 /* The tbi_compatibility_on Flag must be cleared when Rctl is cleared. */
1464 hw->tbi_compatibility_on = false;
1466 /* Delay to allow any outstanding PCI transactions to complete before
1467 * resetting the device
1471 /* Issue a global reset to the MAC. This will reset the chip's
1472 * transmit, receive, DMA, and link units. It will not effect
1473 * the current PCI configuration. The global reset bit is self-
1474 * clearing, and should clear within a microsecond.
1476 DEBUGOUT("Issuing a global reset to MAC\n");
1477 ctrl = E1000_READ_REG(hw, CTRL);
1479 E1000_WRITE_REG(hw, CTRL, (ctrl | E1000_CTRL_RST));
1481 /* Force a reload from the EEPROM if necessary */
1482 if (hw->mac_type == e1000_igb) {
1484 reg = E1000_READ_REG(hw, STATUS);
1485 if (reg & E1000_STATUS_PF_RST_DONE)
1486 DEBUGOUT("PF OK\n");
1487 reg = E1000_READ_REG(hw, I210_EECD);
1488 if (reg & E1000_EECD_AUTO_RD)
1489 DEBUGOUT("EEC OK\n");
1490 } else if (hw->mac_type < e1000_82540) {
1491 /* Wait for reset to complete */
1493 ctrl_ext = E1000_READ_REG(hw, CTRL_EXT);
1494 ctrl_ext |= E1000_CTRL_EXT_EE_RST;
1495 E1000_WRITE_REG(hw, CTRL_EXT, ctrl_ext);
1496 E1000_WRITE_FLUSH(hw);
1497 /* Wait for EEPROM reload */
1500 /* Wait for EEPROM reload (it happens automatically) */
1502 /* Dissable HW ARPs on ASF enabled adapters */
1503 manc = E1000_READ_REG(hw, MANC);
1504 manc &= ~(E1000_MANC_ARP_EN);
1505 E1000_WRITE_REG(hw, MANC, manc);
1508 /* Clear interrupt mask to stop board from generating interrupts */
1509 DEBUGOUT("Masking off all interrupts\n");
1510 if (hw->mac_type == e1000_igb)
1511 E1000_WRITE_REG(hw, I210_IAM, 0);
1512 E1000_WRITE_REG(hw, IMC, 0xffffffff);
1514 /* Clear any pending interrupt events. */
1515 E1000_READ_REG(hw, ICR);
1517 /* If MWI was previously enabled, reenable it. */
1518 if (hw->mac_type == e1000_82542_rev2_0) {
1519 pci_write_config_word(hw->pdev, PCI_COMMAND, hw->pci_cmd_word);
1521 if (hw->mac_type != e1000_igb)
1522 E1000_WRITE_REG(hw, PBA, pba);
1525 /******************************************************************************
1527 * Initialize a number of hardware-dependent bits
1529 * hw: Struct containing variables accessed by shared code
1531 * This function contains hardware limitation workarounds for PCI-E adapters
1533 *****************************************************************************/
1535 e1000_initialize_hardware_bits(struct e1000_hw *hw)
1537 if ((hw->mac_type >= e1000_82571) &&
1538 (!hw->initialize_hw_bits_disable)) {
1539 /* Settings common to all PCI-express silicon */
1540 uint32_t reg_ctrl, reg_ctrl_ext;
1541 uint32_t reg_tarc0, reg_tarc1;
1543 uint32_t reg_txdctl, reg_txdctl1;
1545 /* link autonegotiation/sync workarounds */
1546 reg_tarc0 = E1000_READ_REG(hw, TARC0);
1547 reg_tarc0 &= ~((1 << 30)|(1 << 29)|(1 << 28)|(1 << 27));
1549 /* Enable not-done TX descriptor counting */
1550 reg_txdctl = E1000_READ_REG(hw, TXDCTL);
1551 reg_txdctl |= E1000_TXDCTL_COUNT_DESC;
1552 E1000_WRITE_REG(hw, TXDCTL, reg_txdctl);
1554 reg_txdctl1 = E1000_READ_REG(hw, TXDCTL1);
1555 reg_txdctl1 |= E1000_TXDCTL_COUNT_DESC;
1556 E1000_WRITE_REG(hw, TXDCTL1, reg_txdctl1);
1559 if (hw->mac_type == e1000_igb)
1562 switch (hw->mac_type) {
1565 /* Clear PHY TX compatible mode bits */
1566 reg_tarc1 = E1000_READ_REG(hw, TARC1);
1567 reg_tarc1 &= ~((1 << 30)|(1 << 29));
1569 /* link autonegotiation/sync workarounds */
1570 reg_tarc0 |= ((1 << 26)|(1 << 25)|(1 << 24)|(1 << 23));
1572 /* TX ring control fixes */
1573 reg_tarc1 |= ((1 << 26)|(1 << 25)|(1 << 24));
1575 /* Multiple read bit is reversed polarity */
1576 reg_tctl = E1000_READ_REG(hw, TCTL);
1577 if (reg_tctl & E1000_TCTL_MULR)
1578 reg_tarc1 &= ~(1 << 28);
1580 reg_tarc1 |= (1 << 28);
1582 E1000_WRITE_REG(hw, TARC1, reg_tarc1);
1586 reg_ctrl_ext = E1000_READ_REG(hw, CTRL_EXT);
1587 reg_ctrl_ext &= ~(1 << 23);
1588 reg_ctrl_ext |= (1 << 22);
1590 /* TX byte count fix */
1591 reg_ctrl = E1000_READ_REG(hw, CTRL);
1592 reg_ctrl &= ~(1 << 29);
1594 E1000_WRITE_REG(hw, CTRL_EXT, reg_ctrl_ext);
1595 E1000_WRITE_REG(hw, CTRL, reg_ctrl);
1597 case e1000_80003es2lan:
1598 /* improve small packet performace for fiber/serdes */
1599 if ((hw->media_type == e1000_media_type_fiber)
1600 || (hw->media_type ==
1601 e1000_media_type_internal_serdes)) {
1602 reg_tarc0 &= ~(1 << 20);
1605 /* Multiple read bit is reversed polarity */
1606 reg_tctl = E1000_READ_REG(hw, TCTL);
1607 reg_tarc1 = E1000_READ_REG(hw, TARC1);
1608 if (reg_tctl & E1000_TCTL_MULR)
1609 reg_tarc1 &= ~(1 << 28);
1611 reg_tarc1 |= (1 << 28);
1613 E1000_WRITE_REG(hw, TARC1, reg_tarc1);
1616 /* Reduce concurrent DMA requests to 3 from 4 */
1617 if ((hw->revision_id < 3) ||
1618 ((hw->device_id != E1000_DEV_ID_ICH8_IGP_M_AMT) &&
1619 (hw->device_id != E1000_DEV_ID_ICH8_IGP_M)))
1620 reg_tarc0 |= ((1 << 29)|(1 << 28));
1622 reg_ctrl_ext = E1000_READ_REG(hw, CTRL_EXT);
1623 reg_ctrl_ext |= (1 << 22);
1624 E1000_WRITE_REG(hw, CTRL_EXT, reg_ctrl_ext);
1626 /* workaround TX hang with TSO=on */
1627 reg_tarc0 |= ((1 << 27)|(1 << 26)|(1 << 24)|(1 << 23));
1629 /* Multiple read bit is reversed polarity */
1630 reg_tctl = E1000_READ_REG(hw, TCTL);
1631 reg_tarc1 = E1000_READ_REG(hw, TARC1);
1632 if (reg_tctl & E1000_TCTL_MULR)
1633 reg_tarc1 &= ~(1 << 28);
1635 reg_tarc1 |= (1 << 28);
1637 /* workaround TX hang with TSO=on */
1638 reg_tarc1 |= ((1 << 30)|(1 << 26)|(1 << 24));
1640 E1000_WRITE_REG(hw, TARC1, reg_tarc1);
1646 E1000_WRITE_REG(hw, TARC0, reg_tarc0);
1650 /******************************************************************************
1651 * Performs basic configuration of the adapter.
1653 * hw - Struct containing variables accessed by shared code
1655 * Assumes that the controller has previously been reset and is in a
1656 * post-reset uninitialized state. Initializes the receive address registers,
1657 * multicast table, and VLAN filter table. Calls routines to setup link
1658 * configuration and flow control settings. Clears all on-chip counters. Leaves
1659 * the transmit and receive units disabled and uninitialized.
1660 *****************************************************************************/
1662 e1000_init_hw(struct eth_device *nic)
1664 struct e1000_hw *hw = nic->priv;
1668 uint16_t pcix_cmd_word;
1669 uint16_t pcix_stat_hi_word;
1671 uint16_t stat_mmrbc;
1676 /* force full DMA clock frequency for 10/100 on ICH8 A0-B0 */
1677 if ((hw->mac_type == e1000_ich8lan) &&
1678 ((hw->revision_id < 3) ||
1679 ((hw->device_id != E1000_DEV_ID_ICH8_IGP_M_AMT) &&
1680 (hw->device_id != E1000_DEV_ID_ICH8_IGP_M)))) {
1681 reg_data = E1000_READ_REG(hw, STATUS);
1682 reg_data &= ~0x80000000;
1683 E1000_WRITE_REG(hw, STATUS, reg_data);
1685 /* Do not need initialize Identification LED */
1687 /* Set the media type and TBI compatibility */
1688 e1000_set_media_type(hw);
1690 /* Must be called after e1000_set_media_type
1691 * because media_type is used */
1692 e1000_initialize_hardware_bits(hw);
1694 /* Disabling VLAN filtering. */
1695 DEBUGOUT("Initializing the IEEE VLAN\n");
1696 /* VET hardcoded to standard value and VFTA removed in ICH8 LAN */
1697 if (hw->mac_type != e1000_ich8lan) {
1698 if (hw->mac_type < e1000_82545_rev_3)
1699 E1000_WRITE_REG(hw, VET, 0);
1700 e1000_clear_vfta(hw);
1703 /* For 82542 (rev 2.0), disable MWI and put the receiver into reset */
1704 if (hw->mac_type == e1000_82542_rev2_0) {
1705 DEBUGOUT("Disabling MWI on 82542 rev 2.0\n");
1706 pci_write_config_word(hw->pdev, PCI_COMMAND,
1708 pci_cmd_word & ~PCI_COMMAND_INVALIDATE);
1709 E1000_WRITE_REG(hw, RCTL, E1000_RCTL_RST);
1710 E1000_WRITE_FLUSH(hw);
1714 /* Setup the receive address. This involves initializing all of the Receive
1715 * Address Registers (RARs 0 - 15).
1717 e1000_init_rx_addrs(nic);
1719 /* For 82542 (rev 2.0), take the receiver out of reset and enable MWI */
1720 if (hw->mac_type == e1000_82542_rev2_0) {
1721 E1000_WRITE_REG(hw, RCTL, 0);
1722 E1000_WRITE_FLUSH(hw);
1724 pci_write_config_word(hw->pdev, PCI_COMMAND, hw->pci_cmd_word);
1727 /* Zero out the Multicast HASH table */
1728 DEBUGOUT("Zeroing the MTA\n");
1729 mta_size = E1000_MC_TBL_SIZE;
1730 if (hw->mac_type == e1000_ich8lan)
1731 mta_size = E1000_MC_TBL_SIZE_ICH8LAN;
1732 for (i = 0; i < mta_size; i++) {
1733 E1000_WRITE_REG_ARRAY(hw, MTA, i, 0);
1734 /* use write flush to prevent Memory Write Block (MWB) from
1735 * occuring when accessing our register space */
1736 E1000_WRITE_FLUSH(hw);
1739 /* Set the PCI priority bit correctly in the CTRL register. This
1740 * determines if the adapter gives priority to receives, or if it
1741 * gives equal priority to transmits and receives. Valid only on
1742 * 82542 and 82543 silicon.
1744 if (hw->dma_fairness && hw->mac_type <= e1000_82543) {
1745 ctrl = E1000_READ_REG(hw, CTRL);
1746 E1000_WRITE_REG(hw, CTRL, ctrl | E1000_CTRL_PRIOR);
1749 switch (hw->mac_type) {
1750 case e1000_82545_rev_3:
1751 case e1000_82546_rev_3:
1755 /* Workaround for PCI-X problem when BIOS sets MMRBC incorrectly. */
1756 if (hw->bus_type == e1000_bus_type_pcix) {
1757 pci_read_config_word(hw->pdev, PCIX_COMMAND_REGISTER,
1759 pci_read_config_word(hw->pdev, PCIX_STATUS_REGISTER_HI,
1760 &pcix_stat_hi_word);
1762 (pcix_cmd_word & PCIX_COMMAND_MMRBC_MASK) >>
1763 PCIX_COMMAND_MMRBC_SHIFT;
1765 (pcix_stat_hi_word & PCIX_STATUS_HI_MMRBC_MASK) >>
1766 PCIX_STATUS_HI_MMRBC_SHIFT;
1767 if (stat_mmrbc == PCIX_STATUS_HI_MMRBC_4K)
1768 stat_mmrbc = PCIX_STATUS_HI_MMRBC_2K;
1769 if (cmd_mmrbc > stat_mmrbc) {
1770 pcix_cmd_word &= ~PCIX_COMMAND_MMRBC_MASK;
1771 pcix_cmd_word |= stat_mmrbc << PCIX_COMMAND_MMRBC_SHIFT;
1772 pci_write_config_word(hw->pdev, PCIX_COMMAND_REGISTER,
1779 /* More time needed for PHY to initialize */
1780 if (hw->mac_type == e1000_ich8lan)
1782 if (hw->mac_type == e1000_igb)
1785 /* Call a subroutine to configure the link and setup flow control. */
1786 ret_val = e1000_setup_link(nic);
1788 /* Set the transmit descriptor write-back policy */
1789 if (hw->mac_type > e1000_82544) {
1790 ctrl = E1000_READ_REG(hw, TXDCTL);
1792 (ctrl & ~E1000_TXDCTL_WTHRESH) |
1793 E1000_TXDCTL_FULL_TX_DESC_WB;
1794 E1000_WRITE_REG(hw, TXDCTL, ctrl);
1797 /* Set the receive descriptor write back policy */
1798 if (hw->mac_type >= e1000_82571) {
1799 ctrl = E1000_READ_REG(hw, RXDCTL);
1801 (ctrl & ~E1000_RXDCTL_WTHRESH) |
1802 E1000_RXDCTL_FULL_RX_DESC_WB;
1803 E1000_WRITE_REG(hw, RXDCTL, ctrl);
1806 switch (hw->mac_type) {
1809 case e1000_80003es2lan:
1810 /* Enable retransmit on late collisions */
1811 reg_data = E1000_READ_REG(hw, TCTL);
1812 reg_data |= E1000_TCTL_RTLC;
1813 E1000_WRITE_REG(hw, TCTL, reg_data);
1815 /* Configure Gigabit Carry Extend Padding */
1816 reg_data = E1000_READ_REG(hw, TCTL_EXT);
1817 reg_data &= ~E1000_TCTL_EXT_GCEX_MASK;
1818 reg_data |= DEFAULT_80003ES2LAN_TCTL_EXT_GCEX;
1819 E1000_WRITE_REG(hw, TCTL_EXT, reg_data);
1821 /* Configure Transmit Inter-Packet Gap */
1822 reg_data = E1000_READ_REG(hw, TIPG);
1823 reg_data &= ~E1000_TIPG_IPGT_MASK;
1824 reg_data |= DEFAULT_80003ES2LAN_TIPG_IPGT_1000;
1825 E1000_WRITE_REG(hw, TIPG, reg_data);
1827 reg_data = E1000_READ_REG_ARRAY(hw, FFLT, 0x0001);
1828 reg_data &= ~0x00100000;
1829 E1000_WRITE_REG_ARRAY(hw, FFLT, 0x0001, reg_data);
1834 ctrl = E1000_READ_REG(hw, TXDCTL1);
1835 ctrl = (ctrl & ~E1000_TXDCTL_WTHRESH)
1836 | E1000_TXDCTL_FULL_TX_DESC_WB;
1837 E1000_WRITE_REG(hw, TXDCTL1, ctrl);
1841 reg_data = E1000_READ_REG(hw, GCR);
1842 reg_data |= E1000_GCR_L1_ACT_WITHOUT_L0S_RX;
1843 E1000_WRITE_REG(hw, GCR, reg_data);
1849 /* Clear all of the statistics registers (clear on read). It is
1850 * important that we do this after we have tried to establish link
1851 * because the symbol error count will increment wildly if there
1854 e1000_clear_hw_cntrs(hw);
1856 /* ICH8 No-snoop bits are opposite polarity.
1857 * Set to snoop by default after reset. */
1858 if (hw->mac_type == e1000_ich8lan)
1859 e1000_set_pci_ex_no_snoop(hw, PCI_EX_82566_SNOOP_ALL);
1862 if (hw->device_id == E1000_DEV_ID_82546GB_QUAD_COPPER ||
1863 hw->device_id == E1000_DEV_ID_82546GB_QUAD_COPPER_KSP3) {
1864 ctrl_ext = E1000_READ_REG(hw, CTRL_EXT);
1865 /* Relaxed ordering must be disabled to avoid a parity
1866 * error crash in a PCI slot. */
1867 ctrl_ext |= E1000_CTRL_EXT_RO_DIS;
1868 E1000_WRITE_REG(hw, CTRL_EXT, ctrl_ext);
1874 /******************************************************************************
1875 * Configures flow control and link settings.
1877 * hw - Struct containing variables accessed by shared code
1879 * Determines which flow control settings to use. Calls the apropriate media-
1880 * specific link configuration function. Configures the flow control settings.
1881 * Assuming the adapter has a valid link partner, a valid link should be
1882 * established. Assumes the hardware has previously been reset and the
1883 * transmitter and receiver are not enabled.
1884 *****************************************************************************/
1886 e1000_setup_link(struct eth_device *nic)
1888 struct e1000_hw *hw = nic->priv;
1890 #ifndef CONFIG_E1000_NO_NVM
1892 uint16_t eeprom_data;
1897 /* In the case of the phy reset being blocked, we already have a link.
1898 * We do not have to set it up again. */
1899 if (e1000_check_phy_reset_block(hw))
1900 return E1000_SUCCESS;
1902 #ifndef CONFIG_E1000_NO_NVM
1903 /* Read and store word 0x0F of the EEPROM. This word contains bits
1904 * that determine the hardware's default PAUSE (flow control) mode,
1905 * a bit that determines whether the HW defaults to enabling or
1906 * disabling auto-negotiation, and the direction of the
1907 * SW defined pins. If there is no SW over-ride of the flow
1908 * control setting, then the variable hw->fc will
1909 * be initialized based on a value in the EEPROM.
1911 if (e1000_read_eeprom(hw, EEPROM_INIT_CONTROL2_REG, 1,
1912 &eeprom_data) < 0) {
1913 DEBUGOUT("EEPROM Read Error\n");
1914 return -E1000_ERR_EEPROM;
1917 if (hw->fc == e1000_fc_default) {
1918 switch (hw->mac_type) {
1923 hw->fc = e1000_fc_full;
1926 #ifndef CONFIG_E1000_NO_NVM
1927 ret_val = e1000_read_eeprom(hw,
1928 EEPROM_INIT_CONTROL2_REG, 1, &eeprom_data);
1930 DEBUGOUT("EEPROM Read Error\n");
1931 return -E1000_ERR_EEPROM;
1933 if ((eeprom_data & EEPROM_WORD0F_PAUSE_MASK) == 0)
1934 hw->fc = e1000_fc_none;
1935 else if ((eeprom_data & EEPROM_WORD0F_PAUSE_MASK) ==
1936 EEPROM_WORD0F_ASM_DIR)
1937 hw->fc = e1000_fc_tx_pause;
1940 hw->fc = e1000_fc_full;
1945 /* We want to save off the original Flow Control configuration just
1946 * in case we get disconnected and then reconnected into a different
1947 * hub or switch with different Flow Control capabilities.
1949 if (hw->mac_type == e1000_82542_rev2_0)
1950 hw->fc &= (~e1000_fc_tx_pause);
1952 if ((hw->mac_type < e1000_82543) && (hw->report_tx_early == 1))
1953 hw->fc &= (~e1000_fc_rx_pause);
1955 hw->original_fc = hw->fc;
1957 DEBUGOUT("After fix-ups FlowControl is now = %x\n", hw->fc);
1959 #ifndef CONFIG_E1000_NO_NVM
1960 /* Take the 4 bits from EEPROM word 0x0F that determine the initial
1961 * polarity value for the SW controlled pins, and setup the
1962 * Extended Device Control reg with that info.
1963 * This is needed because one of the SW controlled pins is used for
1964 * signal detection. So this should be done before e1000_setup_pcs_link()
1965 * or e1000_phy_setup() is called.
1967 if (hw->mac_type == e1000_82543) {
1968 ctrl_ext = ((eeprom_data & EEPROM_WORD0F_SWPDIO_EXT) <<
1970 E1000_WRITE_REG(hw, CTRL_EXT, ctrl_ext);
1974 /* Call the necessary subroutine to configure the link. */
1975 ret_val = (hw->media_type == e1000_media_type_fiber) ?
1976 e1000_setup_fiber_link(nic) : e1000_setup_copper_link(nic);
1981 /* Initialize the flow control address, type, and PAUSE timer
1982 * registers to their default values. This is done even if flow
1983 * control is disabled, because it does not hurt anything to
1984 * initialize these registers.
1986 DEBUGOUT("Initializing the Flow Control address, type"
1987 "and timer regs\n");
1989 /* FCAL/H and FCT are hardcoded to standard values in e1000_ich8lan. */
1990 if (hw->mac_type != e1000_ich8lan) {
1991 E1000_WRITE_REG(hw, FCT, FLOW_CONTROL_TYPE);
1992 E1000_WRITE_REG(hw, FCAH, FLOW_CONTROL_ADDRESS_HIGH);
1993 E1000_WRITE_REG(hw, FCAL, FLOW_CONTROL_ADDRESS_LOW);
1996 E1000_WRITE_REG(hw, FCTTV, hw->fc_pause_time);
1998 /* Set the flow control receive threshold registers. Normally,
1999 * these registers will be set to a default threshold that may be
2000 * adjusted later by the driver's runtime code. However, if the
2001 * ability to transmit pause frames in not enabled, then these
2002 * registers will be set to 0.
2004 if (!(hw->fc & e1000_fc_tx_pause)) {
2005 E1000_WRITE_REG(hw, FCRTL, 0);
2006 E1000_WRITE_REG(hw, FCRTH, 0);
2008 /* We need to set up the Receive Threshold high and low water marks
2009 * as well as (optionally) enabling the transmission of XON frames.
2011 if (hw->fc_send_xon) {
2012 E1000_WRITE_REG(hw, FCRTL,
2013 (hw->fc_low_water | E1000_FCRTL_XONE));
2014 E1000_WRITE_REG(hw, FCRTH, hw->fc_high_water);
2016 E1000_WRITE_REG(hw, FCRTL, hw->fc_low_water);
2017 E1000_WRITE_REG(hw, FCRTH, hw->fc_high_water);
2023 /******************************************************************************
2024 * Sets up link for a fiber based adapter
2026 * hw - Struct containing variables accessed by shared code
2028 * Manipulates Physical Coding Sublayer functions in order to configure
2029 * link. Assumes the hardware has been previously reset and the transmitter
2030 * and receiver are not enabled.
2031 *****************************************************************************/
2033 e1000_setup_fiber_link(struct eth_device *nic)
2035 struct e1000_hw *hw = nic->priv;
2044 /* On adapters with a MAC newer that 82544, SW Defineable pin 1 will be
2045 * set when the optics detect a signal. On older adapters, it will be
2046 * cleared when there is a signal
2048 ctrl = E1000_READ_REG(hw, CTRL);
2049 if ((hw->mac_type > e1000_82544) && !(ctrl & E1000_CTRL_ILOS))
2050 signal = E1000_CTRL_SWDPIN1;
2054 printf("signal for %s is %x (ctrl %08x)!!!!\n", nic->name, signal,
2056 /* Take the link out of reset */
2057 ctrl &= ~(E1000_CTRL_LRST);
2059 e1000_config_collision_dist(hw);
2061 /* Check for a software override of the flow control settings, and setup
2062 * the device accordingly. If auto-negotiation is enabled, then software
2063 * will have to set the "PAUSE" bits to the correct value in the Tranmsit
2064 * Config Word Register (TXCW) and re-start auto-negotiation. However, if
2065 * auto-negotiation is disabled, then software will have to manually
2066 * configure the two flow control enable bits in the CTRL register.
2068 * The possible values of the "fc" parameter are:
2069 * 0: Flow control is completely disabled
2070 * 1: Rx flow control is enabled (we can receive pause frames, but
2071 * not send pause frames).
2072 * 2: Tx flow control is enabled (we can send pause frames but we do
2073 * not support receiving pause frames).
2074 * 3: Both Rx and TX flow control (symmetric) are enabled.
2078 /* Flow control is completely disabled by a software over-ride. */
2079 txcw = (E1000_TXCW_ANE | E1000_TXCW_FD);
2081 case e1000_fc_rx_pause:
2082 /* RX Flow control is enabled and TX Flow control is disabled by a
2083 * software over-ride. Since there really isn't a way to advertise
2084 * that we are capable of RX Pause ONLY, we will advertise that we
2085 * support both symmetric and asymmetric RX PAUSE. Later, we will
2086 * disable the adapter's ability to send PAUSE frames.
2088 txcw = (E1000_TXCW_ANE | E1000_TXCW_FD | E1000_TXCW_PAUSE_MASK);
2090 case e1000_fc_tx_pause:
2091 /* TX Flow control is enabled, and RX Flow control is disabled, by a
2092 * software over-ride.
2094 txcw = (E1000_TXCW_ANE | E1000_TXCW_FD | E1000_TXCW_ASM_DIR);
2097 /* Flow control (both RX and TX) is enabled by a software over-ride. */
2098 txcw = (E1000_TXCW_ANE | E1000_TXCW_FD | E1000_TXCW_PAUSE_MASK);
2101 DEBUGOUT("Flow control param set incorrectly\n");
2102 return -E1000_ERR_CONFIG;
2106 /* Since auto-negotiation is enabled, take the link out of reset (the link
2107 * will be in reset, because we previously reset the chip). This will
2108 * restart auto-negotiation. If auto-neogtiation is successful then the
2109 * link-up status bit will be set and the flow control enable bits (RFCE
2110 * and TFCE) will be set according to their negotiated value.
2112 DEBUGOUT("Auto-negotiation enabled (%#x)\n", txcw);
2114 E1000_WRITE_REG(hw, TXCW, txcw);
2115 E1000_WRITE_REG(hw, CTRL, ctrl);
2116 E1000_WRITE_FLUSH(hw);
2121 /* If we have a signal (the cable is plugged in) then poll for a "Link-Up"
2122 * indication in the Device Status Register. Time-out if a link isn't
2123 * seen in 500 milliseconds seconds (Auto-negotiation should complete in
2124 * less than 500 milliseconds even if the other end is doing it in SW).
2126 if ((E1000_READ_REG(hw, CTRL) & E1000_CTRL_SWDPIN1) == signal) {
2127 DEBUGOUT("Looking for Link\n");
2128 for (i = 0; i < (LINK_UP_TIMEOUT / 10); i++) {
2130 status = E1000_READ_REG(hw, STATUS);
2131 if (status & E1000_STATUS_LU)
2134 if (i == (LINK_UP_TIMEOUT / 10)) {
2135 /* AutoNeg failed to achieve a link, so we'll call
2136 * e1000_check_for_link. This routine will force the link up if we
2137 * detect a signal. This will allow us to communicate with
2138 * non-autonegotiating link partners.
2140 DEBUGOUT("Never got a valid link from auto-neg!!!\n");
2141 hw->autoneg_failed = 1;
2142 ret_val = e1000_check_for_link(nic);
2144 DEBUGOUT("Error while checking for link\n");
2147 hw->autoneg_failed = 0;
2149 hw->autoneg_failed = 0;
2150 DEBUGOUT("Valid Link Found\n");
2153 DEBUGOUT("No Signal Detected\n");
2154 return -E1000_ERR_NOLINK;
2159 /******************************************************************************
2160 * Make sure we have a valid PHY and change PHY mode before link setup.
2162 * hw - Struct containing variables accessed by shared code
2163 ******************************************************************************/
2165 e1000_copper_link_preconfig(struct e1000_hw *hw)
2173 ctrl = E1000_READ_REG(hw, CTRL);
2174 /* With 82543, we need to force speed and duplex on the MAC equal to what
2175 * the PHY speed and duplex configuration is. In addition, we need to
2176 * perform a hardware reset on the PHY to take it out of reset.
2178 if (hw->mac_type > e1000_82543) {
2179 ctrl |= E1000_CTRL_SLU;
2180 ctrl &= ~(E1000_CTRL_FRCSPD | E1000_CTRL_FRCDPX);
2181 E1000_WRITE_REG(hw, CTRL, ctrl);
2183 ctrl |= (E1000_CTRL_FRCSPD | E1000_CTRL_FRCDPX
2185 E1000_WRITE_REG(hw, CTRL, ctrl);
2186 ret_val = e1000_phy_hw_reset(hw);
2191 /* Make sure we have a valid PHY */
2192 ret_val = e1000_detect_gig_phy(hw);
2194 DEBUGOUT("Error, did not detect valid phy.\n");
2197 DEBUGOUT("Phy ID = %x\n", hw->phy_id);
2199 /* Set PHY to class A mode (if necessary) */
2200 ret_val = e1000_set_phy_mode(hw);
2203 if ((hw->mac_type == e1000_82545_rev_3) ||
2204 (hw->mac_type == e1000_82546_rev_3)) {
2205 ret_val = e1000_read_phy_reg(hw, M88E1000_PHY_SPEC_CTRL,
2207 phy_data |= 0x00000008;
2208 ret_val = e1000_write_phy_reg(hw, M88E1000_PHY_SPEC_CTRL,
2212 if (hw->mac_type <= e1000_82543 ||
2213 hw->mac_type == e1000_82541 || hw->mac_type == e1000_82547 ||
2214 hw->mac_type == e1000_82541_rev_2
2215 || hw->mac_type == e1000_82547_rev_2)
2216 hw->phy_reset_disable = false;
2218 return E1000_SUCCESS;
2221 /*****************************************************************************
2223 * This function sets the lplu state according to the active flag. When
2224 * activating lplu this function also disables smart speed and vise versa.
2225 * lplu will not be activated unless the device autonegotiation advertisment
2226 * meets standards of either 10 or 10/100 or 10/100/1000 at all duplexes.
2227 * hw: Struct containing variables accessed by shared code
2228 * active - true to enable lplu false to disable lplu.
2230 * returns: - E1000_ERR_PHY if fail to read/write the PHY
2231 * E1000_SUCCESS at any other case.
2233 ****************************************************************************/
2236 e1000_set_d3_lplu_state(struct e1000_hw *hw, bool active)
2238 uint32_t phy_ctrl = 0;
2243 if (hw->phy_type != e1000_phy_igp && hw->phy_type != e1000_phy_igp_2
2244 && hw->phy_type != e1000_phy_igp_3)
2245 return E1000_SUCCESS;
2247 /* During driver activity LPLU should not be used or it will attain link
2248 * from the lowest speeds starting from 10Mbps. The capability is used
2249 * for Dx transitions and states */
2250 if (hw->mac_type == e1000_82541_rev_2
2251 || hw->mac_type == e1000_82547_rev_2) {
2252 ret_val = e1000_read_phy_reg(hw, IGP01E1000_GMII_FIFO,
2256 } else if (hw->mac_type == e1000_ich8lan) {
2257 /* MAC writes into PHY register based on the state transition
2258 * and start auto-negotiation. SW driver can overwrite the
2259 * settings in CSR PHY power control E1000_PHY_CTRL register. */
2260 phy_ctrl = E1000_READ_REG(hw, PHY_CTRL);
2262 ret_val = e1000_read_phy_reg(hw, IGP02E1000_PHY_POWER_MGMT,
2269 if (hw->mac_type == e1000_82541_rev_2 ||
2270 hw->mac_type == e1000_82547_rev_2) {
2271 phy_data &= ~IGP01E1000_GMII_FLEX_SPD;
2272 ret_val = e1000_write_phy_reg(hw, IGP01E1000_GMII_FIFO,
2277 if (hw->mac_type == e1000_ich8lan) {
2278 phy_ctrl &= ~E1000_PHY_CTRL_NOND0A_LPLU;
2279 E1000_WRITE_REG(hw, PHY_CTRL, phy_ctrl);
2281 phy_data &= ~IGP02E1000_PM_D3_LPLU;
2282 ret_val = e1000_write_phy_reg(hw,
2283 IGP02E1000_PHY_POWER_MGMT, phy_data);
2289 /* LPLU and SmartSpeed are mutually exclusive. LPLU is used during
2290 * Dx states where the power conservation is most important. During
2291 * driver activity we should enable SmartSpeed, so performance is
2293 if (hw->smart_speed == e1000_smart_speed_on) {
2294 ret_val = e1000_read_phy_reg(hw,
2295 IGP01E1000_PHY_PORT_CONFIG, &phy_data);
2299 phy_data |= IGP01E1000_PSCFR_SMART_SPEED;
2300 ret_val = e1000_write_phy_reg(hw,
2301 IGP01E1000_PHY_PORT_CONFIG, phy_data);
2304 } else if (hw->smart_speed == e1000_smart_speed_off) {
2305 ret_val = e1000_read_phy_reg(hw,
2306 IGP01E1000_PHY_PORT_CONFIG, &phy_data);
2310 phy_data &= ~IGP01E1000_PSCFR_SMART_SPEED;
2311 ret_val = e1000_write_phy_reg(hw,
2312 IGP01E1000_PHY_PORT_CONFIG, phy_data);
2317 } else if ((hw->autoneg_advertised == AUTONEG_ADVERTISE_SPEED_DEFAULT)
2318 || (hw->autoneg_advertised == AUTONEG_ADVERTISE_10_ALL) ||
2319 (hw->autoneg_advertised == AUTONEG_ADVERTISE_10_100_ALL)) {
2321 if (hw->mac_type == e1000_82541_rev_2 ||
2322 hw->mac_type == e1000_82547_rev_2) {
2323 phy_data |= IGP01E1000_GMII_FLEX_SPD;
2324 ret_val = e1000_write_phy_reg(hw,
2325 IGP01E1000_GMII_FIFO, phy_data);
2329 if (hw->mac_type == e1000_ich8lan) {
2330 phy_ctrl |= E1000_PHY_CTRL_NOND0A_LPLU;
2331 E1000_WRITE_REG(hw, PHY_CTRL, phy_ctrl);
2333 phy_data |= IGP02E1000_PM_D3_LPLU;
2334 ret_val = e1000_write_phy_reg(hw,
2335 IGP02E1000_PHY_POWER_MGMT, phy_data);
2341 /* When LPLU is enabled we should disable SmartSpeed */
2342 ret_val = e1000_read_phy_reg(hw, IGP01E1000_PHY_PORT_CONFIG,
2347 phy_data &= ~IGP01E1000_PSCFR_SMART_SPEED;
2348 ret_val = e1000_write_phy_reg(hw, IGP01E1000_PHY_PORT_CONFIG,
2353 return E1000_SUCCESS;
2356 /*****************************************************************************
2358 * This function sets the lplu d0 state according to the active flag. When
2359 * activating lplu this function also disables smart speed and vise versa.
2360 * lplu will not be activated unless the device autonegotiation advertisment
2361 * meets standards of either 10 or 10/100 or 10/100/1000 at all duplexes.
2362 * hw: Struct containing variables accessed by shared code
2363 * active - true to enable lplu false to disable lplu.
2365 * returns: - E1000_ERR_PHY if fail to read/write the PHY
2366 * E1000_SUCCESS at any other case.
2368 ****************************************************************************/
2371 e1000_set_d0_lplu_state(struct e1000_hw *hw, bool active)
2373 uint32_t phy_ctrl = 0;
2378 if (hw->mac_type <= e1000_82547_rev_2)
2379 return E1000_SUCCESS;
2381 if (hw->mac_type == e1000_ich8lan) {
2382 phy_ctrl = E1000_READ_REG(hw, PHY_CTRL);
2383 } else if (hw->mac_type == e1000_igb) {
2384 phy_ctrl = E1000_READ_REG(hw, I210_PHY_CTRL);
2386 ret_val = e1000_read_phy_reg(hw, IGP02E1000_PHY_POWER_MGMT,
2393 if (hw->mac_type == e1000_ich8lan) {
2394 phy_ctrl &= ~E1000_PHY_CTRL_D0A_LPLU;
2395 E1000_WRITE_REG(hw, PHY_CTRL, phy_ctrl);
2396 } else if (hw->mac_type == e1000_igb) {
2397 phy_ctrl &= ~E1000_PHY_CTRL_D0A_LPLU;
2398 E1000_WRITE_REG(hw, I210_PHY_CTRL, phy_ctrl);
2400 phy_data &= ~IGP02E1000_PM_D0_LPLU;
2401 ret_val = e1000_write_phy_reg(hw,
2402 IGP02E1000_PHY_POWER_MGMT, phy_data);
2407 if (hw->mac_type == e1000_igb)
2408 return E1000_SUCCESS;
2410 /* LPLU and SmartSpeed are mutually exclusive. LPLU is used during
2411 * Dx states where the power conservation is most important. During
2412 * driver activity we should enable SmartSpeed, so performance is
2414 if (hw->smart_speed == e1000_smart_speed_on) {
2415 ret_val = e1000_read_phy_reg(hw,
2416 IGP01E1000_PHY_PORT_CONFIG, &phy_data);
2420 phy_data |= IGP01E1000_PSCFR_SMART_SPEED;
2421 ret_val = e1000_write_phy_reg(hw,
2422 IGP01E1000_PHY_PORT_CONFIG, phy_data);
2425 } else if (hw->smart_speed == e1000_smart_speed_off) {
2426 ret_val = e1000_read_phy_reg(hw,
2427 IGP01E1000_PHY_PORT_CONFIG, &phy_data);
2431 phy_data &= ~IGP01E1000_PSCFR_SMART_SPEED;
2432 ret_val = e1000_write_phy_reg(hw,
2433 IGP01E1000_PHY_PORT_CONFIG, phy_data);
2441 if (hw->mac_type == e1000_ich8lan) {
2442 phy_ctrl |= E1000_PHY_CTRL_D0A_LPLU;
2443 E1000_WRITE_REG(hw, PHY_CTRL, phy_ctrl);
2444 } else if (hw->mac_type == e1000_igb) {
2445 phy_ctrl |= E1000_PHY_CTRL_D0A_LPLU;
2446 E1000_WRITE_REG(hw, I210_PHY_CTRL, phy_ctrl);
2448 phy_data |= IGP02E1000_PM_D0_LPLU;
2449 ret_val = e1000_write_phy_reg(hw,
2450 IGP02E1000_PHY_POWER_MGMT, phy_data);
2455 if (hw->mac_type == e1000_igb)
2456 return E1000_SUCCESS;
2458 /* When LPLU is enabled we should disable SmartSpeed */
2459 ret_val = e1000_read_phy_reg(hw,
2460 IGP01E1000_PHY_PORT_CONFIG, &phy_data);
2464 phy_data &= ~IGP01E1000_PSCFR_SMART_SPEED;
2465 ret_val = e1000_write_phy_reg(hw,
2466 IGP01E1000_PHY_PORT_CONFIG, phy_data);
2471 return E1000_SUCCESS;
2474 /********************************************************************
2475 * Copper link setup for e1000_phy_igp series.
2477 * hw - Struct containing variables accessed by shared code
2478 *********************************************************************/
2480 e1000_copper_link_igp_setup(struct e1000_hw *hw)
2488 if (hw->phy_reset_disable)
2489 return E1000_SUCCESS;
2491 ret_val = e1000_phy_reset(hw);
2493 DEBUGOUT("Error Resetting the PHY\n");
2497 /* Wait 15ms for MAC to configure PHY from eeprom settings */
2499 if (hw->mac_type != e1000_ich8lan) {
2500 /* Configure activity LED after PHY reset */
2501 led_ctrl = E1000_READ_REG(hw, LEDCTL);
2502 led_ctrl &= IGP_ACTIVITY_LED_MASK;
2503 led_ctrl |= (IGP_ACTIVITY_LED_ENABLE | IGP_LED3_MODE);
2504 E1000_WRITE_REG(hw, LEDCTL, led_ctrl);
2507 /* The NVM settings will configure LPLU in D3 for IGP2 and IGP3 PHYs */
2508 if (hw->phy_type == e1000_phy_igp) {
2509 /* disable lplu d3 during driver init */
2510 ret_val = e1000_set_d3_lplu_state(hw, false);
2512 DEBUGOUT("Error Disabling LPLU D3\n");
2517 /* disable lplu d0 during driver init */
2518 ret_val = e1000_set_d0_lplu_state(hw, false);
2520 DEBUGOUT("Error Disabling LPLU D0\n");
2523 /* Configure mdi-mdix settings */
2524 ret_val = e1000_read_phy_reg(hw, IGP01E1000_PHY_PORT_CTRL, &phy_data);
2528 if ((hw->mac_type == e1000_82541) || (hw->mac_type == e1000_82547)) {
2529 hw->dsp_config_state = e1000_dsp_config_disabled;
2530 /* Force MDI for earlier revs of the IGP PHY */
2531 phy_data &= ~(IGP01E1000_PSCR_AUTO_MDIX
2532 | IGP01E1000_PSCR_FORCE_MDI_MDIX);
2536 hw->dsp_config_state = e1000_dsp_config_enabled;
2537 phy_data &= ~IGP01E1000_PSCR_AUTO_MDIX;
2541 phy_data &= ~IGP01E1000_PSCR_FORCE_MDI_MDIX;
2544 phy_data |= IGP01E1000_PSCR_FORCE_MDI_MDIX;
2548 phy_data |= IGP01E1000_PSCR_AUTO_MDIX;
2552 ret_val = e1000_write_phy_reg(hw, IGP01E1000_PHY_PORT_CTRL, phy_data);
2556 /* set auto-master slave resolution settings */
2558 e1000_ms_type phy_ms_setting = hw->master_slave;
2560 if (hw->ffe_config_state == e1000_ffe_config_active)
2561 hw->ffe_config_state = e1000_ffe_config_enabled;
2563 if (hw->dsp_config_state == e1000_dsp_config_activated)
2564 hw->dsp_config_state = e1000_dsp_config_enabled;
2566 /* when autonegotiation advertisment is only 1000Mbps then we
2567 * should disable SmartSpeed and enable Auto MasterSlave
2568 * resolution as hardware default. */
2569 if (hw->autoneg_advertised == ADVERTISE_1000_FULL) {
2570 /* Disable SmartSpeed */
2571 ret_val = e1000_read_phy_reg(hw,
2572 IGP01E1000_PHY_PORT_CONFIG, &phy_data);
2575 phy_data &= ~IGP01E1000_PSCFR_SMART_SPEED;
2576 ret_val = e1000_write_phy_reg(hw,
2577 IGP01E1000_PHY_PORT_CONFIG, phy_data);
2580 /* Set auto Master/Slave resolution process */
2581 ret_val = e1000_read_phy_reg(hw, PHY_1000T_CTRL,
2585 phy_data &= ~CR_1000T_MS_ENABLE;
2586 ret_val = e1000_write_phy_reg(hw, PHY_1000T_CTRL,
2592 ret_val = e1000_read_phy_reg(hw, PHY_1000T_CTRL, &phy_data);
2596 /* load defaults for future use */
2597 hw->original_master_slave = (phy_data & CR_1000T_MS_ENABLE) ?
2598 ((phy_data & CR_1000T_MS_VALUE) ?
2599 e1000_ms_force_master :
2600 e1000_ms_force_slave) :
2603 switch (phy_ms_setting) {
2604 case e1000_ms_force_master:
2605 phy_data |= (CR_1000T_MS_ENABLE | CR_1000T_MS_VALUE);
2607 case e1000_ms_force_slave:
2608 phy_data |= CR_1000T_MS_ENABLE;
2609 phy_data &= ~(CR_1000T_MS_VALUE);
2612 phy_data &= ~CR_1000T_MS_ENABLE;
2616 ret_val = e1000_write_phy_reg(hw, PHY_1000T_CTRL, phy_data);
2621 return E1000_SUCCESS;
2624 /*****************************************************************************
2625 * This function checks the mode of the firmware.
2627 * returns - true when the mode is IAMT or false.
2628 ****************************************************************************/
2630 e1000_check_mng_mode(struct e1000_hw *hw)
2635 fwsm = E1000_READ_REG(hw, FWSM);
2637 if (hw->mac_type == e1000_ich8lan) {
2638 if ((fwsm & E1000_FWSM_MODE_MASK) ==
2639 (E1000_MNG_ICH_IAMT_MODE << E1000_FWSM_MODE_SHIFT))
2641 } else if ((fwsm & E1000_FWSM_MODE_MASK) ==
2642 (E1000_MNG_IAMT_MODE << E1000_FWSM_MODE_SHIFT))
2649 e1000_write_kmrn_reg(struct e1000_hw *hw, uint32_t reg_addr, uint16_t data)
2651 uint16_t swfw = E1000_SWFW_PHY0_SM;
2655 if (e1000_is_second_port(hw))
2656 swfw = E1000_SWFW_PHY1_SM;
2658 if (e1000_swfw_sync_acquire(hw, swfw))
2659 return -E1000_ERR_SWFW_SYNC;
2661 reg_val = ((reg_addr << E1000_KUMCTRLSTA_OFFSET_SHIFT)
2662 & E1000_KUMCTRLSTA_OFFSET) | data;
2663 E1000_WRITE_REG(hw, KUMCTRLSTA, reg_val);
2666 return E1000_SUCCESS;
2670 e1000_read_kmrn_reg(struct e1000_hw *hw, uint32_t reg_addr, uint16_t *data)
2672 uint16_t swfw = E1000_SWFW_PHY0_SM;
2676 if (e1000_is_second_port(hw))
2677 swfw = E1000_SWFW_PHY1_SM;
2679 if (e1000_swfw_sync_acquire(hw, swfw)) {
2680 debug("%s[%i]\n", __func__, __LINE__);
2681 return -E1000_ERR_SWFW_SYNC;
2684 /* Write register address */
2685 reg_val = ((reg_addr << E1000_KUMCTRLSTA_OFFSET_SHIFT) &
2686 E1000_KUMCTRLSTA_OFFSET) | E1000_KUMCTRLSTA_REN;
2687 E1000_WRITE_REG(hw, KUMCTRLSTA, reg_val);
2690 /* Read the data returned */
2691 reg_val = E1000_READ_REG(hw, KUMCTRLSTA);
2692 *data = (uint16_t)reg_val;
2694 return E1000_SUCCESS;
2697 /********************************************************************
2698 * Copper link setup for e1000_phy_gg82563 series.
2700 * hw - Struct containing variables accessed by shared code
2701 *********************************************************************/
2703 e1000_copper_link_ggp_setup(struct e1000_hw *hw)
2711 if (!hw->phy_reset_disable) {
2712 /* Enable CRS on TX for half-duplex operation. */
2713 ret_val = e1000_read_phy_reg(hw,
2714 GG82563_PHY_MAC_SPEC_CTRL, &phy_data);
2718 phy_data |= GG82563_MSCR_ASSERT_CRS_ON_TX;
2719 /* Use 25MHz for both link down and 1000BASE-T for Tx clock */
2720 phy_data |= GG82563_MSCR_TX_CLK_1000MBPS_25MHZ;
2722 ret_val = e1000_write_phy_reg(hw,
2723 GG82563_PHY_MAC_SPEC_CTRL, phy_data);
2728 * MDI/MDI-X = 0 (default)
2729 * 0 - Auto for all speeds
2732 * 3 - Auto for 1000Base-T only (MDI-X for 10/100Base-T modes)
2734 ret_val = e1000_read_phy_reg(hw,
2735 GG82563_PHY_SPEC_CTRL, &phy_data);
2739 phy_data &= ~GG82563_PSCR_CROSSOVER_MODE_MASK;
2743 phy_data |= GG82563_PSCR_CROSSOVER_MODE_MDI;
2746 phy_data |= GG82563_PSCR_CROSSOVER_MODE_MDIX;
2750 phy_data |= GG82563_PSCR_CROSSOVER_MODE_AUTO;
2755 * disable_polarity_correction = 0 (default)
2756 * Automatic Correction for Reversed Cable Polarity
2760 phy_data &= ~GG82563_PSCR_POLARITY_REVERSAL_DISABLE;
2761 ret_val = e1000_write_phy_reg(hw,
2762 GG82563_PHY_SPEC_CTRL, phy_data);
2767 /* SW Reset the PHY so all changes take effect */
2768 ret_val = e1000_phy_reset(hw);
2770 DEBUGOUT("Error Resetting the PHY\n");
2773 } /* phy_reset_disable */
2775 if (hw->mac_type == e1000_80003es2lan) {
2776 /* Bypass RX and TX FIFO's */
2777 ret_val = e1000_write_kmrn_reg(hw,
2778 E1000_KUMCTRLSTA_OFFSET_FIFO_CTRL,
2779 E1000_KUMCTRLSTA_FIFO_CTRL_RX_BYPASS
2780 | E1000_KUMCTRLSTA_FIFO_CTRL_TX_BYPASS);
2784 ret_val = e1000_read_phy_reg(hw,
2785 GG82563_PHY_SPEC_CTRL_2, &phy_data);
2789 phy_data &= ~GG82563_PSCR2_REVERSE_AUTO_NEG;
2790 ret_val = e1000_write_phy_reg(hw,
2791 GG82563_PHY_SPEC_CTRL_2, phy_data);
2796 reg_data = E1000_READ_REG(hw, CTRL_EXT);
2797 reg_data &= ~(E1000_CTRL_EXT_LINK_MODE_MASK);
2798 E1000_WRITE_REG(hw, CTRL_EXT, reg_data);
2800 ret_val = e1000_read_phy_reg(hw,
2801 GG82563_PHY_PWR_MGMT_CTRL, &phy_data);
2805 /* Do not init these registers when the HW is in IAMT mode, since the
2806 * firmware will have already initialized them. We only initialize
2807 * them if the HW is not in IAMT mode.
2809 if (e1000_check_mng_mode(hw) == false) {
2810 /* Enable Electrical Idle on the PHY */
2811 phy_data |= GG82563_PMCR_ENABLE_ELECTRICAL_IDLE;
2812 ret_val = e1000_write_phy_reg(hw,
2813 GG82563_PHY_PWR_MGMT_CTRL, phy_data);
2817 ret_val = e1000_read_phy_reg(hw,
2818 GG82563_PHY_KMRN_MODE_CTRL, &phy_data);
2822 phy_data &= ~GG82563_KMCR_PASS_FALSE_CARRIER;
2823 ret_val = e1000_write_phy_reg(hw,
2824 GG82563_PHY_KMRN_MODE_CTRL, phy_data);
2830 /* Workaround: Disable padding in Kumeran interface in the MAC
2831 * and in the PHY to avoid CRC errors.
2833 ret_val = e1000_read_phy_reg(hw,
2834 GG82563_PHY_INBAND_CTRL, &phy_data);
2837 phy_data |= GG82563_ICR_DIS_PADDING;
2838 ret_val = e1000_write_phy_reg(hw,
2839 GG82563_PHY_INBAND_CTRL, phy_data);
2843 return E1000_SUCCESS;
2846 /********************************************************************
2847 * Copper link setup for e1000_phy_m88 series.
2849 * hw - Struct containing variables accessed by shared code
2850 *********************************************************************/
2852 e1000_copper_link_mgp_setup(struct e1000_hw *hw)
2859 if (hw->phy_reset_disable)
2860 return E1000_SUCCESS;
2862 /* Enable CRS on TX. This must be set for half-duplex operation. */
2863 ret_val = e1000_read_phy_reg(hw, M88E1000_PHY_SPEC_CTRL, &phy_data);
2867 phy_data |= M88E1000_PSCR_ASSERT_CRS_ON_TX;
2870 * MDI/MDI-X = 0 (default)
2871 * 0 - Auto for all speeds
2874 * 3 - Auto for 1000Base-T only (MDI-X for 10/100Base-T modes)
2876 phy_data &= ~M88E1000_PSCR_AUTO_X_MODE;
2880 phy_data |= M88E1000_PSCR_MDI_MANUAL_MODE;
2883 phy_data |= M88E1000_PSCR_MDIX_MANUAL_MODE;
2886 phy_data |= M88E1000_PSCR_AUTO_X_1000T;
2890 phy_data |= M88E1000_PSCR_AUTO_X_MODE;
2895 * disable_polarity_correction = 0 (default)
2896 * Automatic Correction for Reversed Cable Polarity
2900 phy_data &= ~M88E1000_PSCR_POLARITY_REVERSAL;
2901 ret_val = e1000_write_phy_reg(hw, M88E1000_PHY_SPEC_CTRL, phy_data);
2905 if (hw->phy_revision < M88E1011_I_REV_4) {
2906 /* Force TX_CLK in the Extended PHY Specific Control Register
2909 ret_val = e1000_read_phy_reg(hw,
2910 M88E1000_EXT_PHY_SPEC_CTRL, &phy_data);
2914 phy_data |= M88E1000_EPSCR_TX_CLK_25;
2916 if ((hw->phy_revision == E1000_REVISION_2) &&
2917 (hw->phy_id == M88E1111_I_PHY_ID)) {
2918 /* Vidalia Phy, set the downshift counter to 5x */
2919 phy_data &= ~(M88EC018_EPSCR_DOWNSHIFT_COUNTER_MASK);
2920 phy_data |= M88EC018_EPSCR_DOWNSHIFT_COUNTER_5X;
2921 ret_val = e1000_write_phy_reg(hw,
2922 M88E1000_EXT_PHY_SPEC_CTRL, phy_data);
2926 /* Configure Master and Slave downshift values */
2927 phy_data &= ~(M88E1000_EPSCR_MASTER_DOWNSHIFT_MASK
2928 | M88E1000_EPSCR_SLAVE_DOWNSHIFT_MASK);
2929 phy_data |= (M88E1000_EPSCR_MASTER_DOWNSHIFT_1X
2930 | M88E1000_EPSCR_SLAVE_DOWNSHIFT_1X);
2931 ret_val = e1000_write_phy_reg(hw,
2932 M88E1000_EXT_PHY_SPEC_CTRL, phy_data);
2938 /* SW Reset the PHY so all changes take effect */
2939 ret_val = e1000_phy_reset(hw);
2941 DEBUGOUT("Error Resetting the PHY\n");
2945 return E1000_SUCCESS;
2948 /********************************************************************
2949 * Setup auto-negotiation and flow control advertisements,
2950 * and then perform auto-negotiation.
2952 * hw - Struct containing variables accessed by shared code
2953 *********************************************************************/
2955 e1000_copper_link_autoneg(struct e1000_hw *hw)
2962 /* Perform some bounds checking on the hw->autoneg_advertised
2963 * parameter. If this variable is zero, then set it to the default.
2965 hw->autoneg_advertised &= AUTONEG_ADVERTISE_SPEED_DEFAULT;
2967 /* If autoneg_advertised is zero, we assume it was not defaulted
2968 * by the calling code so we set to advertise full capability.
2970 if (hw->autoneg_advertised == 0)
2971 hw->autoneg_advertised = AUTONEG_ADVERTISE_SPEED_DEFAULT;
2973 /* IFE phy only supports 10/100 */
2974 if (hw->phy_type == e1000_phy_ife)
2975 hw->autoneg_advertised &= AUTONEG_ADVERTISE_10_100_ALL;
2977 DEBUGOUT("Reconfiguring auto-neg advertisement params\n");
2978 ret_val = e1000_phy_setup_autoneg(hw);
2980 DEBUGOUT("Error Setting up Auto-Negotiation\n");
2983 DEBUGOUT("Restarting Auto-Neg\n");
2985 /* Restart auto-negotiation by setting the Auto Neg Enable bit and
2986 * the Auto Neg Restart bit in the PHY control register.
2988 ret_val = e1000_read_phy_reg(hw, PHY_CTRL, &phy_data);
2992 phy_data |= (MII_CR_AUTO_NEG_EN | MII_CR_RESTART_AUTO_NEG);
2993 ret_val = e1000_write_phy_reg(hw, PHY_CTRL, phy_data);
2997 /* Does the user want to wait for Auto-Neg to complete here, or
2998 * check at a later time (for example, callback routine).
3000 /* If we do not wait for autonegtation to complete I
3001 * do not see a valid link status.
3002 * wait_autoneg_complete = 1 .
3004 if (hw->wait_autoneg_complete) {
3005 ret_val = e1000_wait_autoneg(hw);
3007 DEBUGOUT("Error while waiting for autoneg"
3013 hw->get_link_status = true;
3015 return E1000_SUCCESS;
3018 /******************************************************************************
3019 * Config the MAC and the PHY after link is up.
3020 * 1) Set up the MAC to the current PHY speed/duplex
3021 * if we are on 82543. If we
3022 * are on newer silicon, we only need to configure
3023 * collision distance in the Transmit Control Register.
3024 * 2) Set up flow control on the MAC to that established with
3026 * 3) Config DSP to improve Gigabit link quality for some PHY revisions.
3028 * hw - Struct containing variables accessed by shared code
3029 ******************************************************************************/
3031 e1000_copper_link_postconfig(struct e1000_hw *hw)
3036 if (hw->mac_type >= e1000_82544) {
3037 e1000_config_collision_dist(hw);
3039 ret_val = e1000_config_mac_to_phy(hw);
3041 DEBUGOUT("Error configuring MAC to PHY settings\n");
3045 ret_val = e1000_config_fc_after_link_up(hw);
3047 DEBUGOUT("Error Configuring Flow Control\n");
3050 return E1000_SUCCESS;
3053 /******************************************************************************
3054 * Detects which PHY is present and setup the speed and duplex
3056 * hw - Struct containing variables accessed by shared code
3057 ******************************************************************************/
3059 e1000_setup_copper_link(struct eth_device *nic)
3061 struct e1000_hw *hw = nic->priv;
3069 switch (hw->mac_type) {
3070 case e1000_80003es2lan:
3072 /* Set the mac to wait the maximum time between each
3073 * iteration and increase the max iterations when
3074 * polling the phy; this fixes erroneous timeouts at 10Mbps. */
3075 ret_val = e1000_write_kmrn_reg(hw,
3076 GG82563_REG(0x34, 4), 0xFFFF);
3079 ret_val = e1000_read_kmrn_reg(hw,
3080 GG82563_REG(0x34, 9), ®_data);
3084 ret_val = e1000_write_kmrn_reg(hw,
3085 GG82563_REG(0x34, 9), reg_data);
3092 /* Check if it is a valid PHY and set PHY mode if necessary. */
3093 ret_val = e1000_copper_link_preconfig(hw);
3096 switch (hw->mac_type) {
3097 case e1000_80003es2lan:
3098 /* Kumeran registers are written-only */
3100 E1000_KUMCTRLSTA_INB_CTRL_LINK_STATUS_TX_TIMEOUT_DEFAULT;
3101 reg_data |= E1000_KUMCTRLSTA_INB_CTRL_DIS_PADDING;
3102 ret_val = e1000_write_kmrn_reg(hw,
3103 E1000_KUMCTRLSTA_OFFSET_INB_CTRL, reg_data);
3111 if (hw->phy_type == e1000_phy_igp ||
3112 hw->phy_type == e1000_phy_igp_3 ||
3113 hw->phy_type == e1000_phy_igp_2) {
3114 ret_val = e1000_copper_link_igp_setup(hw);
3117 } else if (hw->phy_type == e1000_phy_m88 ||
3118 hw->phy_type == e1000_phy_igb) {
3119 ret_val = e1000_copper_link_mgp_setup(hw);
3122 } else if (hw->phy_type == e1000_phy_gg82563) {
3123 ret_val = e1000_copper_link_ggp_setup(hw);
3129 /* Setup autoneg and flow control advertisement
3130 * and perform autonegotiation */
3131 ret_val = e1000_copper_link_autoneg(hw);
3135 /* Check link status. Wait up to 100 microseconds for link to become
3138 for (i = 0; i < 10; i++) {
3139 ret_val = e1000_read_phy_reg(hw, PHY_STATUS, &phy_data);
3142 ret_val = e1000_read_phy_reg(hw, PHY_STATUS, &phy_data);
3146 if (phy_data & MII_SR_LINK_STATUS) {
3147 /* Config the MAC and PHY after link is up */
3148 ret_val = e1000_copper_link_postconfig(hw);
3152 DEBUGOUT("Valid link established!!!\n");
3153 return E1000_SUCCESS;
3158 DEBUGOUT("Unable to establish link!!!\n");
3159 return E1000_SUCCESS;
3162 /******************************************************************************
3163 * Configures PHY autoneg and flow control advertisement settings
3165 * hw - Struct containing variables accessed by shared code
3166 ******************************************************************************/
3168 e1000_phy_setup_autoneg(struct e1000_hw *hw)
3171 uint16_t mii_autoneg_adv_reg;
3172 uint16_t mii_1000t_ctrl_reg;
3176 /* Read the MII Auto-Neg Advertisement Register (Address 4). */
3177 ret_val = e1000_read_phy_reg(hw, PHY_AUTONEG_ADV, &mii_autoneg_adv_reg);
3181 if (hw->phy_type != e1000_phy_ife) {
3182 /* Read the MII 1000Base-T Control Register (Address 9). */
3183 ret_val = e1000_read_phy_reg(hw, PHY_1000T_CTRL,
3184 &mii_1000t_ctrl_reg);
3188 mii_1000t_ctrl_reg = 0;
3190 /* Need to parse both autoneg_advertised and fc and set up
3191 * the appropriate PHY registers. First we will parse for
3192 * autoneg_advertised software override. Since we can advertise
3193 * a plethora of combinations, we need to check each bit
3197 /* First we clear all the 10/100 mb speed bits in the Auto-Neg
3198 * Advertisement Register (Address 4) and the 1000 mb speed bits in
3199 * the 1000Base-T Control Register (Address 9).
3201 mii_autoneg_adv_reg &= ~REG4_SPEED_MASK;
3202 mii_1000t_ctrl_reg &= ~REG9_SPEED_MASK;
3204 DEBUGOUT("autoneg_advertised %x\n", hw->autoneg_advertised);
3206 /* Do we want to advertise 10 Mb Half Duplex? */
3207 if (hw->autoneg_advertised & ADVERTISE_10_HALF) {
3208 DEBUGOUT("Advertise 10mb Half duplex\n");
3209 mii_autoneg_adv_reg |= NWAY_AR_10T_HD_CAPS;
3212 /* Do we want to advertise 10 Mb Full Duplex? */
3213 if (hw->autoneg_advertised & ADVERTISE_10_FULL) {
3214 DEBUGOUT("Advertise 10mb Full duplex\n");
3215 mii_autoneg_adv_reg |= NWAY_AR_10T_FD_CAPS;
3218 /* Do we want to advertise 100 Mb Half Duplex? */
3219 if (hw->autoneg_advertised & ADVERTISE_100_HALF) {
3220 DEBUGOUT("Advertise 100mb Half duplex\n");
3221 mii_autoneg_adv_reg |= NWAY_AR_100TX_HD_CAPS;
3224 /* Do we want to advertise 100 Mb Full Duplex? */
3225 if (hw->autoneg_advertised & ADVERTISE_100_FULL) {
3226 DEBUGOUT("Advertise 100mb Full duplex\n");
3227 mii_autoneg_adv_reg |= NWAY_AR_100TX_FD_CAPS;
3230 /* We do not allow the Phy to advertise 1000 Mb Half Duplex */
3231 if (hw->autoneg_advertised & ADVERTISE_1000_HALF) {
3233 ("Advertise 1000mb Half duplex requested, request denied!\n");
3236 /* Do we want to advertise 1000 Mb Full Duplex? */
3237 if (hw->autoneg_advertised & ADVERTISE_1000_FULL) {
3238 DEBUGOUT("Advertise 1000mb Full duplex\n");
3239 mii_1000t_ctrl_reg |= CR_1000T_FD_CAPS;
3242 /* Check for a software override of the flow control settings, and
3243 * setup the PHY advertisement registers accordingly. If
3244 * auto-negotiation is enabled, then software will have to set the
3245 * "PAUSE" bits to the correct value in the Auto-Negotiation
3246 * Advertisement Register (PHY_AUTONEG_ADV) and re-start auto-negotiation.
3248 * The possible values of the "fc" parameter are:
3249 * 0: Flow control is completely disabled
3250 * 1: Rx flow control is enabled (we can receive pause frames
3251 * but not send pause frames).
3252 * 2: Tx flow control is enabled (we can send pause frames
3253 * but we do not support receiving pause frames).
3254 * 3: Both Rx and TX flow control (symmetric) are enabled.
3255 * other: No software override. The flow control configuration
3256 * in the EEPROM is used.
3259 case e1000_fc_none: /* 0 */
3260 /* Flow control (RX & TX) is completely disabled by a
3261 * software over-ride.
3263 mii_autoneg_adv_reg &= ~(NWAY_AR_ASM_DIR | NWAY_AR_PAUSE);
3265 case e1000_fc_rx_pause: /* 1 */
3266 /* RX Flow control is enabled, and TX Flow control is
3267 * disabled, by a software over-ride.
3269 /* Since there really isn't a way to advertise that we are
3270 * capable of RX Pause ONLY, we will advertise that we
3271 * support both symmetric and asymmetric RX PAUSE. Later
3272 * (in e1000_config_fc_after_link_up) we will disable the
3273 *hw's ability to send PAUSE frames.
3275 mii_autoneg_adv_reg |= (NWAY_AR_ASM_DIR | NWAY_AR_PAUSE);
3277 case e1000_fc_tx_pause: /* 2 */
3278 /* TX Flow control is enabled, and RX Flow control is
3279 * disabled, by a software over-ride.
3281 mii_autoneg_adv_reg |= NWAY_AR_ASM_DIR;
3282 mii_autoneg_adv_reg &= ~NWAY_AR_PAUSE;
3284 case e1000_fc_full: /* 3 */
3285 /* Flow control (both RX and TX) is enabled by a software
3288 mii_autoneg_adv_reg |= (NWAY_AR_ASM_DIR | NWAY_AR_PAUSE);
3291 DEBUGOUT("Flow control param set incorrectly\n");
3292 return -E1000_ERR_CONFIG;
3295 ret_val = e1000_write_phy_reg(hw, PHY_AUTONEG_ADV, mii_autoneg_adv_reg);
3299 DEBUGOUT("Auto-Neg Advertising %x\n", mii_autoneg_adv_reg);
3301 if (hw->phy_type != e1000_phy_ife) {
3302 ret_val = e1000_write_phy_reg(hw, PHY_1000T_CTRL,
3303 mii_1000t_ctrl_reg);
3308 return E1000_SUCCESS;
3311 /******************************************************************************
3312 * Sets the collision distance in the Transmit Control register
3314 * hw - Struct containing variables accessed by shared code
3316 * Link should have been established previously. Reads the speed and duplex
3317 * information from the Device Status register.
3318 ******************************************************************************/
3320 e1000_config_collision_dist(struct e1000_hw *hw)
3322 uint32_t tctl, coll_dist;
3326 if (hw->mac_type < e1000_82543)
3327 coll_dist = E1000_COLLISION_DISTANCE_82542;
3329 coll_dist = E1000_COLLISION_DISTANCE;
3331 tctl = E1000_READ_REG(hw, TCTL);
3333 tctl &= ~E1000_TCTL_COLD;
3334 tctl |= coll_dist << E1000_COLD_SHIFT;
3336 E1000_WRITE_REG(hw, TCTL, tctl);
3337 E1000_WRITE_FLUSH(hw);
3340 /******************************************************************************
3341 * Sets MAC speed and duplex settings to reflect the those in the PHY
3343 * hw - Struct containing variables accessed by shared code
3344 * mii_reg - data to write to the MII control register
3346 * The contents of the PHY register containing the needed information need to
3348 ******************************************************************************/
3350 e1000_config_mac_to_phy(struct e1000_hw *hw)
3357 /* Read the Device Control Register and set the bits to Force Speed
3360 ctrl = E1000_READ_REG(hw, CTRL);
3361 ctrl |= (E1000_CTRL_FRCSPD | E1000_CTRL_FRCDPX);
3362 ctrl &= ~(E1000_CTRL_ILOS);
3363 ctrl |= (E1000_CTRL_SPD_SEL);
3365 /* Set up duplex in the Device Control and Transmit Control
3366 * registers depending on negotiated values.
3368 if (e1000_read_phy_reg(hw, M88E1000_PHY_SPEC_STATUS, &phy_data) < 0) {
3369 DEBUGOUT("PHY Read Error\n");
3370 return -E1000_ERR_PHY;
3372 if (phy_data & M88E1000_PSSR_DPLX)
3373 ctrl |= E1000_CTRL_FD;
3375 ctrl &= ~E1000_CTRL_FD;
3377 e1000_config_collision_dist(hw);
3379 /* Set up speed in the Device Control register depending on
3380 * negotiated values.
3382 if ((phy_data & M88E1000_PSSR_SPEED) == M88E1000_PSSR_1000MBS)
3383 ctrl |= E1000_CTRL_SPD_1000;
3384 else if ((phy_data & M88E1000_PSSR_SPEED) == M88E1000_PSSR_100MBS)
3385 ctrl |= E1000_CTRL_SPD_100;
3386 /* Write the configured values back to the Device Control Reg. */
3387 E1000_WRITE_REG(hw, CTRL, ctrl);
3391 /******************************************************************************
3392 * Forces the MAC's flow control settings.
3394 * hw - Struct containing variables accessed by shared code
3396 * Sets the TFCE and RFCE bits in the device control register to reflect
3397 * the adapter settings. TFCE and RFCE need to be explicitly set by
3398 * software when a Copper PHY is used because autonegotiation is managed
3399 * by the PHY rather than the MAC. Software must also configure these
3400 * bits when link is forced on a fiber connection.
3401 *****************************************************************************/
3403 e1000_force_mac_fc(struct e1000_hw *hw)
3409 /* Get the current configuration of the Device Control Register */
3410 ctrl = E1000_READ_REG(hw, CTRL);
3412 /* Because we didn't get link via the internal auto-negotiation
3413 * mechanism (we either forced link or we got link via PHY
3414 * auto-neg), we have to manually enable/disable transmit an
3415 * receive flow control.
3417 * The "Case" statement below enables/disable flow control
3418 * according to the "hw->fc" parameter.
3420 * The possible values of the "fc" parameter are:
3421 * 0: Flow control is completely disabled
3422 * 1: Rx flow control is enabled (we can receive pause
3423 * frames but not send pause frames).
3424 * 2: Tx flow control is enabled (we can send pause frames
3425 * frames but we do not receive pause frames).
3426 * 3: Both Rx and TX flow control (symmetric) is enabled.
3427 * other: No other values should be possible at this point.
3432 ctrl &= (~(E1000_CTRL_TFCE | E1000_CTRL_RFCE));
3434 case e1000_fc_rx_pause:
3435 ctrl &= (~E1000_CTRL_TFCE);
3436 ctrl |= E1000_CTRL_RFCE;
3438 case e1000_fc_tx_pause:
3439 ctrl &= (~E1000_CTRL_RFCE);
3440 ctrl |= E1000_CTRL_TFCE;
3443 ctrl |= (E1000_CTRL_TFCE | E1000_CTRL_RFCE);
3446 DEBUGOUT("Flow control param set incorrectly\n");
3447 return -E1000_ERR_CONFIG;
3450 /* Disable TX Flow Control for 82542 (rev 2.0) */
3451 if (hw->mac_type == e1000_82542_rev2_0)
3452 ctrl &= (~E1000_CTRL_TFCE);
3454 E1000_WRITE_REG(hw, CTRL, ctrl);
3458 /******************************************************************************
3459 * Configures flow control settings after link is established
3461 * hw - Struct containing variables accessed by shared code
3463 * Should be called immediately after a valid link has been established.
3464 * Forces MAC flow control settings if link was forced. When in MII/GMII mode
3465 * and autonegotiation is enabled, the MAC flow control settings will be set
3466 * based on the flow control negotiated by the PHY. In TBI mode, the TFCE
3467 * and RFCE bits will be automaticaly set to the negotiated flow control mode.
3468 *****************************************************************************/
3470 e1000_config_fc_after_link_up(struct e1000_hw *hw)
3473 uint16_t mii_status_reg;
3474 uint16_t mii_nway_adv_reg;
3475 uint16_t mii_nway_lp_ability_reg;
3481 /* Check for the case where we have fiber media and auto-neg failed
3482 * so we had to force link. In this case, we need to force the
3483 * configuration of the MAC to match the "fc" parameter.
3485 if (((hw->media_type == e1000_media_type_fiber) && (hw->autoneg_failed))
3486 || ((hw->media_type == e1000_media_type_internal_serdes)
3487 && (hw->autoneg_failed))
3488 || ((hw->media_type == e1000_media_type_copper)
3489 && (!hw->autoneg))) {
3490 ret_val = e1000_force_mac_fc(hw);
3492 DEBUGOUT("Error forcing flow control settings\n");
3497 /* Check for the case where we have copper media and auto-neg is
3498 * enabled. In this case, we need to check and see if Auto-Neg
3499 * has completed, and if so, how the PHY and link partner has
3500 * flow control configured.
3502 if (hw->media_type == e1000_media_type_copper) {
3503 /* Read the MII Status Register and check to see if AutoNeg
3504 * has completed. We read this twice because this reg has
3505 * some "sticky" (latched) bits.
3507 if (e1000_read_phy_reg(hw, PHY_STATUS, &mii_status_reg) < 0) {
3508 DEBUGOUT("PHY Read Error\n");
3509 return -E1000_ERR_PHY;
3511 if (e1000_read_phy_reg(hw, PHY_STATUS, &mii_status_reg) < 0) {
3512 DEBUGOUT("PHY Read Error\n");
3513 return -E1000_ERR_PHY;
3516 if (mii_status_reg & MII_SR_AUTONEG_COMPLETE) {
3517 /* The AutoNeg process has completed, so we now need to
3518 * read both the Auto Negotiation Advertisement Register
3519 * (Address 4) and the Auto_Negotiation Base Page Ability
3520 * Register (Address 5) to determine how flow control was
3523 if (e1000_read_phy_reg
3524 (hw, PHY_AUTONEG_ADV, &mii_nway_adv_reg) < 0) {
3525 DEBUGOUT("PHY Read Error\n");
3526 return -E1000_ERR_PHY;
3528 if (e1000_read_phy_reg
3529 (hw, PHY_LP_ABILITY,
3530 &mii_nway_lp_ability_reg) < 0) {
3531 DEBUGOUT("PHY Read Error\n");
3532 return -E1000_ERR_PHY;
3535 /* Two bits in the Auto Negotiation Advertisement Register
3536 * (Address 4) and two bits in the Auto Negotiation Base
3537 * Page Ability Register (Address 5) determine flow control
3538 * for both the PHY and the link partner. The following
3539 * table, taken out of the IEEE 802.3ab/D6.0 dated March 25,
3540 * 1999, describes these PAUSE resolution bits and how flow
3541 * control is determined based upon these settings.
3542 * NOTE: DC = Don't Care
3544 * LOCAL DEVICE | LINK PARTNER
3545 * PAUSE | ASM_DIR | PAUSE | ASM_DIR | NIC Resolution
3546 *-------|---------|-------|---------|--------------------
3547 * 0 | 0 | DC | DC | e1000_fc_none
3548 * 0 | 1 | 0 | DC | e1000_fc_none
3549 * 0 | 1 | 1 | 0 | e1000_fc_none
3550 * 0 | 1 | 1 | 1 | e1000_fc_tx_pause
3551 * 1 | 0 | 0 | DC | e1000_fc_none
3552 * 1 | DC | 1 | DC | e1000_fc_full
3553 * 1 | 1 | 0 | 0 | e1000_fc_none
3554 * 1 | 1 | 0 | 1 | e1000_fc_rx_pause
3557 /* Are both PAUSE bits set to 1? If so, this implies
3558 * Symmetric Flow Control is enabled at both ends. The
3559 * ASM_DIR bits are irrelevant per the spec.
3561 * For Symmetric Flow Control:
3563 * LOCAL DEVICE | LINK PARTNER
3564 * PAUSE | ASM_DIR | PAUSE | ASM_DIR | Result
3565 *-------|---------|-------|---------|--------------------
3566 * 1 | DC | 1 | DC | e1000_fc_full
3569 if ((mii_nway_adv_reg & NWAY_AR_PAUSE) &&
3570 (mii_nway_lp_ability_reg & NWAY_LPAR_PAUSE)) {
3571 /* Now we need to check if the user selected RX ONLY
3572 * of pause frames. In this case, we had to advertise
3573 * FULL flow control because we could not advertise RX
3574 * ONLY. Hence, we must now check to see if we need to
3575 * turn OFF the TRANSMISSION of PAUSE frames.
3577 if (hw->original_fc == e1000_fc_full) {
3578 hw->fc = e1000_fc_full;
3579 DEBUGOUT("Flow Control = FULL.\r\n");
3581 hw->fc = e1000_fc_rx_pause;
3583 ("Flow Control = RX PAUSE frames only.\r\n");
3586 /* For receiving PAUSE frames ONLY.
3588 * LOCAL DEVICE | LINK PARTNER
3589 * PAUSE | ASM_DIR | PAUSE | ASM_DIR | Result
3590 *-------|---------|-------|---------|--------------------
3591 * 0 | 1 | 1 | 1 | e1000_fc_tx_pause
3594 else if (!(mii_nway_adv_reg & NWAY_AR_PAUSE) &&
3595 (mii_nway_adv_reg & NWAY_AR_ASM_DIR) &&
3596 (mii_nway_lp_ability_reg & NWAY_LPAR_PAUSE) &&
3597 (mii_nway_lp_ability_reg & NWAY_LPAR_ASM_DIR))
3599 hw->fc = e1000_fc_tx_pause;
3601 ("Flow Control = TX PAUSE frames only.\r\n");
3603 /* For transmitting PAUSE frames ONLY.
3605 * LOCAL DEVICE | LINK PARTNER
3606 * PAUSE | ASM_DIR | PAUSE | ASM_DIR | Result
3607 *-------|---------|-------|---------|--------------------
3608 * 1 | 1 | 0 | 1 | e1000_fc_rx_pause
3611 else if ((mii_nway_adv_reg & NWAY_AR_PAUSE) &&
3612 (mii_nway_adv_reg & NWAY_AR_ASM_DIR) &&
3613 !(mii_nway_lp_ability_reg & NWAY_LPAR_PAUSE) &&
3614 (mii_nway_lp_ability_reg & NWAY_LPAR_ASM_DIR))
3616 hw->fc = e1000_fc_rx_pause;
3618 ("Flow Control = RX PAUSE frames only.\r\n");
3620 /* Per the IEEE spec, at this point flow control should be
3621 * disabled. However, we want to consider that we could
3622 * be connected to a legacy switch that doesn't advertise
3623 * desired flow control, but can be forced on the link
3624 * partner. So if we advertised no flow control, that is
3625 * what we will resolve to. If we advertised some kind of
3626 * receive capability (Rx Pause Only or Full Flow Control)
3627 * and the link partner advertised none, we will configure
3628 * ourselves to enable Rx Flow Control only. We can do
3629 * this safely for two reasons: If the link partner really
3630 * didn't want flow control enabled, and we enable Rx, no
3631 * harm done since we won't be receiving any PAUSE frames
3632 * anyway. If the intent on the link partner was to have
3633 * flow control enabled, then by us enabling RX only, we
3634 * can at least receive pause frames and process them.
3635 * This is a good idea because in most cases, since we are
3636 * predominantly a server NIC, more times than not we will
3637 * be asked to delay transmission of packets than asking
3638 * our link partner to pause transmission of frames.
3640 else if (hw->original_fc == e1000_fc_none ||
3641 hw->original_fc == e1000_fc_tx_pause) {
3642 hw->fc = e1000_fc_none;
3643 DEBUGOUT("Flow Control = NONE.\r\n");
3645 hw->fc = e1000_fc_rx_pause;
3647 ("Flow Control = RX PAUSE frames only.\r\n");
3650 /* Now we need to do one last check... If we auto-
3651 * negotiated to HALF DUPLEX, flow control should not be
3652 * enabled per IEEE 802.3 spec.
3654 e1000_get_speed_and_duplex(hw, &speed, &duplex);
3656 if (duplex == HALF_DUPLEX)
3657 hw->fc = e1000_fc_none;
3659 /* Now we call a subroutine to actually force the MAC
3660 * controller to use the correct flow control settings.
3662 ret_val = e1000_force_mac_fc(hw);
3665 ("Error forcing flow control settings\n");
3670 ("Copper PHY and Auto Neg has not completed.\r\n");
3673 return E1000_SUCCESS;
3676 /******************************************************************************
3677 * Checks to see if the link status of the hardware has changed.
3679 * hw - Struct containing variables accessed by shared code
3681 * Called by any function that needs to check the link status of the adapter.
3682 *****************************************************************************/
3684 e1000_check_for_link(struct eth_device *nic)
3686 struct e1000_hw *hw = nic->priv;
3694 uint16_t lp_capability;
3698 /* On adapters with a MAC newer that 82544, SW Defineable pin 1 will be
3699 * set when the optics detect a signal. On older adapters, it will be
3700 * cleared when there is a signal
3702 ctrl = E1000_READ_REG(hw, CTRL);
3703 if ((hw->mac_type > e1000_82544) && !(ctrl & E1000_CTRL_ILOS))
3704 signal = E1000_CTRL_SWDPIN1;
3708 status = E1000_READ_REG(hw, STATUS);
3709 rxcw = E1000_READ_REG(hw, RXCW);
3710 DEBUGOUT("ctrl: %#08x status %#08x rxcw %#08x\n", ctrl, status, rxcw);
3712 /* If we have a copper PHY then we only want to go out to the PHY
3713 * registers to see if Auto-Neg has completed and/or if our link
3714 * status has changed. The get_link_status flag will be set if we
3715 * receive a Link Status Change interrupt or we have Rx Sequence
3718 if ((hw->media_type == e1000_media_type_copper) && hw->get_link_status) {
3719 /* First we want to see if the MII Status Register reports
3720 * link. If so, then we want to get the current speed/duplex
3722 * Read the register twice since the link bit is sticky.
3724 if (e1000_read_phy_reg(hw, PHY_STATUS, &phy_data) < 0) {
3725 DEBUGOUT("PHY Read Error\n");
3726 return -E1000_ERR_PHY;
3728 if (e1000_read_phy_reg(hw, PHY_STATUS, &phy_data) < 0) {
3729 DEBUGOUT("PHY Read Error\n");
3730 return -E1000_ERR_PHY;
3733 if (phy_data & MII_SR_LINK_STATUS) {
3734 hw->get_link_status = false;
3736 /* No link detected */
3737 return -E1000_ERR_NOLINK;
3740 /* We have a M88E1000 PHY and Auto-Neg is enabled. If we
3741 * have Si on board that is 82544 or newer, Auto
3742 * Speed Detection takes care of MAC speed/duplex
3743 * configuration. So we only need to configure Collision
3744 * Distance in the MAC. Otherwise, we need to force
3745 * speed/duplex on the MAC to the current PHY speed/duplex
3748 if (hw->mac_type >= e1000_82544)
3749 e1000_config_collision_dist(hw);
3751 ret_val = e1000_config_mac_to_phy(hw);
3754 ("Error configuring MAC to PHY settings\n");
3759 /* Configure Flow Control now that Auto-Neg has completed. First, we
3760 * need to restore the desired flow control settings because we may
3761 * have had to re-autoneg with a different link partner.
3763 ret_val = e1000_config_fc_after_link_up(hw);
3765 DEBUGOUT("Error configuring flow control\n");
3769 /* At this point we know that we are on copper and we have
3770 * auto-negotiated link. These are conditions for checking the link
3771 * parter capability register. We use the link partner capability to
3772 * determine if TBI Compatibility needs to be turned on or off. If
3773 * the link partner advertises any speed in addition to Gigabit, then
3774 * we assume that they are GMII-based, and TBI compatibility is not
3775 * needed. If no other speeds are advertised, we assume the link
3776 * partner is TBI-based, and we turn on TBI Compatibility.
3778 if (hw->tbi_compatibility_en) {
3779 if (e1000_read_phy_reg
3780 (hw, PHY_LP_ABILITY, &lp_capability) < 0) {
3781 DEBUGOUT("PHY Read Error\n");
3782 return -E1000_ERR_PHY;
3784 if (lp_capability & (NWAY_LPAR_10T_HD_CAPS |
3785 NWAY_LPAR_10T_FD_CAPS |
3786 NWAY_LPAR_100TX_HD_CAPS |
3787 NWAY_LPAR_100TX_FD_CAPS |
3788 NWAY_LPAR_100T4_CAPS)) {
3789 /* If our link partner advertises anything in addition to
3790 * gigabit, we do not need to enable TBI compatibility.
3792 if (hw->tbi_compatibility_on) {
3793 /* If we previously were in the mode, turn it off. */
3794 rctl = E1000_READ_REG(hw, RCTL);
3795 rctl &= ~E1000_RCTL_SBP;
3796 E1000_WRITE_REG(hw, RCTL, rctl);
3797 hw->tbi_compatibility_on = false;
3800 /* If TBI compatibility is was previously off, turn it on. For
3801 * compatibility with a TBI link partner, we will store bad
3802 * packets. Some frames have an additional byte on the end and
3803 * will look like CRC errors to to the hardware.
3805 if (!hw->tbi_compatibility_on) {
3806 hw->tbi_compatibility_on = true;
3807 rctl = E1000_READ_REG(hw, RCTL);
3808 rctl |= E1000_RCTL_SBP;
3809 E1000_WRITE_REG(hw, RCTL, rctl);
3814 /* If we don't have link (auto-negotiation failed or link partner cannot
3815 * auto-negotiate), the cable is plugged in (we have signal), and our
3816 * link partner is not trying to auto-negotiate with us (we are receiving
3817 * idles or data), we need to force link up. We also need to give
3818 * auto-negotiation time to complete, in case the cable was just plugged
3819 * in. The autoneg_failed flag does this.
3821 else if ((hw->media_type == e1000_media_type_fiber) &&
3822 (!(status & E1000_STATUS_LU)) &&
3823 ((ctrl & E1000_CTRL_SWDPIN1) == signal) &&
3824 (!(rxcw & E1000_RXCW_C))) {
3825 if (hw->autoneg_failed == 0) {
3826 hw->autoneg_failed = 1;
3829 DEBUGOUT("NOT RXing /C/, disable AutoNeg and force link.\r\n");
3831 /* Disable auto-negotiation in the TXCW register */
3832 E1000_WRITE_REG(hw, TXCW, (hw->txcw & ~E1000_TXCW_ANE));
3834 /* Force link-up and also force full-duplex. */
3835 ctrl = E1000_READ_REG(hw, CTRL);
3836 ctrl |= (E1000_CTRL_SLU | E1000_CTRL_FD);
3837 E1000_WRITE_REG(hw, CTRL, ctrl);
3839 /* Configure Flow Control after forcing link up. */
3840 ret_val = e1000_config_fc_after_link_up(hw);
3842 DEBUGOUT("Error configuring flow control\n");
3846 /* If we are forcing link and we are receiving /C/ ordered sets, re-enable
3847 * auto-negotiation in the TXCW register and disable forced link in the
3848 * Device Control register in an attempt to auto-negotiate with our link
3851 else if ((hw->media_type == e1000_media_type_fiber) &&
3852 (ctrl & E1000_CTRL_SLU) && (rxcw & E1000_RXCW_C)) {
3854 ("RXing /C/, enable AutoNeg and stop forcing link.\r\n");
3855 E1000_WRITE_REG(hw, TXCW, hw->txcw);
3856 E1000_WRITE_REG(hw, CTRL, (ctrl & ~E1000_CTRL_SLU));
3861 /******************************************************************************
3862 * Configure the MAC-to-PHY interface for 10/100Mbps
3864 * hw - Struct containing variables accessed by shared code
3865 ******************************************************************************/
3867 e1000_configure_kmrn_for_10_100(struct e1000_hw *hw, uint16_t duplex)
3869 int32_t ret_val = E1000_SUCCESS;
3875 reg_data = E1000_KUMCTRLSTA_HD_CTRL_10_100_DEFAULT;
3876 ret_val = e1000_write_kmrn_reg(hw,
3877 E1000_KUMCTRLSTA_OFFSET_HD_CTRL, reg_data);
3881 /* Configure Transmit Inter-Packet Gap */
3882 tipg = E1000_READ_REG(hw, TIPG);
3883 tipg &= ~E1000_TIPG_IPGT_MASK;
3884 tipg |= DEFAULT_80003ES2LAN_TIPG_IPGT_10_100;
3885 E1000_WRITE_REG(hw, TIPG, tipg);
3887 ret_val = e1000_read_phy_reg(hw, GG82563_PHY_KMRN_MODE_CTRL, ®_data);
3892 if (duplex == HALF_DUPLEX)
3893 reg_data |= GG82563_KMCR_PASS_FALSE_CARRIER;
3895 reg_data &= ~GG82563_KMCR_PASS_FALSE_CARRIER;
3897 ret_val = e1000_write_phy_reg(hw, GG82563_PHY_KMRN_MODE_CTRL, reg_data);
3903 e1000_configure_kmrn_for_1000(struct e1000_hw *hw)
3905 int32_t ret_val = E1000_SUCCESS;
3911 reg_data = E1000_KUMCTRLSTA_HD_CTRL_1000_DEFAULT;
3912 ret_val = e1000_write_kmrn_reg(hw,
3913 E1000_KUMCTRLSTA_OFFSET_HD_CTRL, reg_data);
3917 /* Configure Transmit Inter-Packet Gap */
3918 tipg = E1000_READ_REG(hw, TIPG);
3919 tipg &= ~E1000_TIPG_IPGT_MASK;
3920 tipg |= DEFAULT_80003ES2LAN_TIPG_IPGT_1000;
3921 E1000_WRITE_REG(hw, TIPG, tipg);
3923 ret_val = e1000_read_phy_reg(hw, GG82563_PHY_KMRN_MODE_CTRL, ®_data);
3928 reg_data &= ~GG82563_KMCR_PASS_FALSE_CARRIER;
3929 ret_val = e1000_write_phy_reg(hw, GG82563_PHY_KMRN_MODE_CTRL, reg_data);
3934 /******************************************************************************
3935 * Detects the current speed and duplex settings of the hardware.
3937 * hw - Struct containing variables accessed by shared code
3938 * speed - Speed of the connection
3939 * duplex - Duplex setting of the connection
3940 *****************************************************************************/
3942 e1000_get_speed_and_duplex(struct e1000_hw *hw, uint16_t *speed,
3951 if (hw->mac_type >= e1000_82543) {
3952 status = E1000_READ_REG(hw, STATUS);
3953 if (status & E1000_STATUS_SPEED_1000) {
3954 *speed = SPEED_1000;
3955 DEBUGOUT("1000 Mbs, ");
3956 } else if (status & E1000_STATUS_SPEED_100) {
3958 DEBUGOUT("100 Mbs, ");
3961 DEBUGOUT("10 Mbs, ");
3964 if (status & E1000_STATUS_FD) {
3965 *duplex = FULL_DUPLEX;
3966 DEBUGOUT("Full Duplex\r\n");
3968 *duplex = HALF_DUPLEX;
3969 DEBUGOUT(" Half Duplex\r\n");
3972 DEBUGOUT("1000 Mbs, Full Duplex\r\n");
3973 *speed = SPEED_1000;
3974 *duplex = FULL_DUPLEX;
3977 /* IGP01 PHY may advertise full duplex operation after speed downgrade
3978 * even if it is operating at half duplex. Here we set the duplex
3979 * settings to match the duplex in the link partner's capabilities.
3981 if (hw->phy_type == e1000_phy_igp && hw->speed_downgraded) {
3982 ret_val = e1000_read_phy_reg(hw, PHY_AUTONEG_EXP, &phy_data);
3986 if (!(phy_data & NWAY_ER_LP_NWAY_CAPS))
3987 *duplex = HALF_DUPLEX;
3989 ret_val = e1000_read_phy_reg(hw,
3990 PHY_LP_ABILITY, &phy_data);
3993 if ((*speed == SPEED_100 &&
3994 !(phy_data & NWAY_LPAR_100TX_FD_CAPS))
3995 || (*speed == SPEED_10
3996 && !(phy_data & NWAY_LPAR_10T_FD_CAPS)))
3997 *duplex = HALF_DUPLEX;
4001 if ((hw->mac_type == e1000_80003es2lan) &&
4002 (hw->media_type == e1000_media_type_copper)) {
4003 if (*speed == SPEED_1000)
4004 ret_val = e1000_configure_kmrn_for_1000(hw);
4006 ret_val = e1000_configure_kmrn_for_10_100(hw, *duplex);
4010 return E1000_SUCCESS;
4013 /******************************************************************************
4014 * Blocks until autoneg completes or times out (~4.5 seconds)
4016 * hw - Struct containing variables accessed by shared code
4017 ******************************************************************************/
4019 e1000_wait_autoneg(struct e1000_hw *hw)
4025 DEBUGOUT("Waiting for Auto-Neg to complete.\n");
4027 /* We will wait for autoneg to complete or 4.5 seconds to expire. */
4028 for (i = PHY_AUTO_NEG_TIME; i > 0; i--) {
4029 /* Read the MII Status Register and wait for Auto-Neg
4030 * Complete bit to be set.
4032 if (e1000_read_phy_reg(hw, PHY_STATUS, &phy_data) < 0) {
4033 DEBUGOUT("PHY Read Error\n");
4034 return -E1000_ERR_PHY;
4036 if (e1000_read_phy_reg(hw, PHY_STATUS, &phy_data) < 0) {
4037 DEBUGOUT("PHY Read Error\n");
4038 return -E1000_ERR_PHY;
4040 if (phy_data & MII_SR_AUTONEG_COMPLETE) {
4041 DEBUGOUT("Auto-Neg complete.\n");
4046 DEBUGOUT("Auto-Neg timedout.\n");
4047 return -E1000_ERR_TIMEOUT;
4050 /******************************************************************************
4051 * Raises the Management Data Clock
4053 * hw - Struct containing variables accessed by shared code
4054 * ctrl - Device control register's current value
4055 ******************************************************************************/
4057 e1000_raise_mdi_clk(struct e1000_hw *hw, uint32_t * ctrl)
4059 /* Raise the clock input to the Management Data Clock (by setting the MDC
4060 * bit), and then delay 2 microseconds.
4062 E1000_WRITE_REG(hw, CTRL, (*ctrl | E1000_CTRL_MDC));
4063 E1000_WRITE_FLUSH(hw);
4067 /******************************************************************************
4068 * Lowers the Management Data Clock
4070 * hw - Struct containing variables accessed by shared code
4071 * ctrl - Device control register's current value
4072 ******************************************************************************/
4074 e1000_lower_mdi_clk(struct e1000_hw *hw, uint32_t * ctrl)
4076 /* Lower the clock input to the Management Data Clock (by clearing the MDC
4077 * bit), and then delay 2 microseconds.
4079 E1000_WRITE_REG(hw, CTRL, (*ctrl & ~E1000_CTRL_MDC));
4080 E1000_WRITE_FLUSH(hw);
4084 /******************************************************************************
4085 * Shifts data bits out to the PHY
4087 * hw - Struct containing variables accessed by shared code
4088 * data - Data to send out to the PHY
4089 * count - Number of bits to shift out
4091 * Bits are shifted out in MSB to LSB order.
4092 ******************************************************************************/
4094 e1000_shift_out_mdi_bits(struct e1000_hw *hw, uint32_t data, uint16_t count)
4099 /* We need to shift "count" number of bits out to the PHY. So, the value
4100 * in the "data" parameter will be shifted out to the PHY one bit at a
4101 * time. In order to do this, "data" must be broken down into bits.
4104 mask <<= (count - 1);
4106 ctrl = E1000_READ_REG(hw, CTRL);
4108 /* Set MDIO_DIR and MDC_DIR direction bits to be used as output pins. */
4109 ctrl |= (E1000_CTRL_MDIO_DIR | E1000_CTRL_MDC_DIR);
4112 /* A "1" is shifted out to the PHY by setting the MDIO bit to "1" and
4113 * then raising and lowering the Management Data Clock. A "0" is
4114 * shifted out to the PHY by setting the MDIO bit to "0" and then
4115 * raising and lowering the clock.
4118 ctrl |= E1000_CTRL_MDIO;
4120 ctrl &= ~E1000_CTRL_MDIO;
4122 E1000_WRITE_REG(hw, CTRL, ctrl);
4123 E1000_WRITE_FLUSH(hw);
4127 e1000_raise_mdi_clk(hw, &ctrl);
4128 e1000_lower_mdi_clk(hw, &ctrl);
4134 /******************************************************************************
4135 * Shifts data bits in from the PHY
4137 * hw - Struct containing variables accessed by shared code
4139 * Bits are shifted in in MSB to LSB order.
4140 ******************************************************************************/
4142 e1000_shift_in_mdi_bits(struct e1000_hw *hw)
4148 /* In order to read a register from the PHY, we need to shift in a total
4149 * of 18 bits from the PHY. The first two bit (turnaround) times are used
4150 * to avoid contention on the MDIO pin when a read operation is performed.
4151 * These two bits are ignored by us and thrown away. Bits are "shifted in"
4152 * by raising the input to the Management Data Clock (setting the MDC bit),
4153 * and then reading the value of the MDIO bit.
4155 ctrl = E1000_READ_REG(hw, CTRL);
4157 /* Clear MDIO_DIR (SWDPIO1) to indicate this bit is to be used as input. */
4158 ctrl &= ~E1000_CTRL_MDIO_DIR;
4159 ctrl &= ~E1000_CTRL_MDIO;
4161 E1000_WRITE_REG(hw, CTRL, ctrl);
4162 E1000_WRITE_FLUSH(hw);
4164 /* Raise and Lower the clock before reading in the data. This accounts for
4165 * the turnaround bits. The first clock occurred when we clocked out the
4166 * last bit of the Register Address.
4168 e1000_raise_mdi_clk(hw, &ctrl);
4169 e1000_lower_mdi_clk(hw, &ctrl);
4171 for (data = 0, i = 0; i < 16; i++) {
4173 e1000_raise_mdi_clk(hw, &ctrl);
4174 ctrl = E1000_READ_REG(hw, CTRL);
4175 /* Check to see if we shifted in a "1". */
4176 if (ctrl & E1000_CTRL_MDIO)
4178 e1000_lower_mdi_clk(hw, &ctrl);
4181 e1000_raise_mdi_clk(hw, &ctrl);
4182 e1000_lower_mdi_clk(hw, &ctrl);
4187 /*****************************************************************************
4188 * Reads the value from a PHY register
4190 * hw - Struct containing variables accessed by shared code
4191 * reg_addr - address of the PHY register to read
4192 ******************************************************************************/
4194 e1000_read_phy_reg(struct e1000_hw *hw, uint32_t reg_addr, uint16_t * phy_data)
4198 const uint32_t phy_addr = 1;
4200 if (reg_addr > MAX_PHY_REG_ADDRESS) {
4201 DEBUGOUT("PHY Address %d is out of range\n", reg_addr);
4202 return -E1000_ERR_PARAM;
4205 if (hw->mac_type > e1000_82543) {
4206 /* Set up Op-code, Phy Address, and register address in the MDI
4207 * Control register. The MAC will take care of interfacing with the
4208 * PHY to retrieve the desired data.
4210 mdic = ((reg_addr << E1000_MDIC_REG_SHIFT) |
4211 (phy_addr << E1000_MDIC_PHY_SHIFT) |
4212 (E1000_MDIC_OP_READ));
4214 E1000_WRITE_REG(hw, MDIC, mdic);
4216 /* Poll the ready bit to see if the MDI read completed */
4217 for (i = 0; i < 64; i++) {
4219 mdic = E1000_READ_REG(hw, MDIC);
4220 if (mdic & E1000_MDIC_READY)
4223 if (!(mdic & E1000_MDIC_READY)) {
4224 DEBUGOUT("MDI Read did not complete\n");
4225 return -E1000_ERR_PHY;
4227 if (mdic & E1000_MDIC_ERROR) {
4228 DEBUGOUT("MDI Error\n");
4229 return -E1000_ERR_PHY;
4231 *phy_data = (uint16_t) mdic;
4233 /* We must first send a preamble through the MDIO pin to signal the
4234 * beginning of an MII instruction. This is done by sending 32
4235 * consecutive "1" bits.
4237 e1000_shift_out_mdi_bits(hw, PHY_PREAMBLE, PHY_PREAMBLE_SIZE);
4239 /* Now combine the next few fields that are required for a read
4240 * operation. We use this method instead of calling the
4241 * e1000_shift_out_mdi_bits routine five different times. The format of
4242 * a MII read instruction consists of a shift out of 14 bits and is
4243 * defined as follows:
4244 * <Preamble><SOF><Op Code><Phy Addr><Reg Addr>
4245 * followed by a shift in of 18 bits. This first two bits shifted in
4246 * are TurnAround bits used to avoid contention on the MDIO pin when a
4247 * READ operation is performed. These two bits are thrown away
4248 * followed by a shift in of 16 bits which contains the desired data.
4250 mdic = ((reg_addr) | (phy_addr << 5) |
4251 (PHY_OP_READ << 10) | (PHY_SOF << 12));
4253 e1000_shift_out_mdi_bits(hw, mdic, 14);
4255 /* Now that we've shifted out the read command to the MII, we need to
4256 * "shift in" the 16-bit value (18 total bits) of the requested PHY
4259 *phy_data = e1000_shift_in_mdi_bits(hw);
4264 /******************************************************************************
4265 * Writes a value to a PHY register
4267 * hw - Struct containing variables accessed by shared code
4268 * reg_addr - address of the PHY register to write
4269 * data - data to write to the PHY
4270 ******************************************************************************/
4272 e1000_write_phy_reg(struct e1000_hw *hw, uint32_t reg_addr, uint16_t phy_data)
4276 const uint32_t phy_addr = 1;
4278 if (reg_addr > MAX_PHY_REG_ADDRESS) {
4279 DEBUGOUT("PHY Address %d is out of range\n", reg_addr);
4280 return -E1000_ERR_PARAM;
4283 if (hw->mac_type > e1000_82543) {
4284 /* Set up Op-code, Phy Address, register address, and data intended
4285 * for the PHY register in the MDI Control register. The MAC will take
4286 * care of interfacing with the PHY to send the desired data.
4288 mdic = (((uint32_t) phy_data) |
4289 (reg_addr << E1000_MDIC_REG_SHIFT) |
4290 (phy_addr << E1000_MDIC_PHY_SHIFT) |
4291 (E1000_MDIC_OP_WRITE));
4293 E1000_WRITE_REG(hw, MDIC, mdic);
4295 /* Poll the ready bit to see if the MDI read completed */
4296 for (i = 0; i < 64; i++) {
4298 mdic = E1000_READ_REG(hw, MDIC);
4299 if (mdic & E1000_MDIC_READY)
4302 if (!(mdic & E1000_MDIC_READY)) {
4303 DEBUGOUT("MDI Write did not complete\n");
4304 return -E1000_ERR_PHY;
4307 /* We'll need to use the SW defined pins to shift the write command
4308 * out to the PHY. We first send a preamble to the PHY to signal the
4309 * beginning of the MII instruction. This is done by sending 32
4310 * consecutive "1" bits.
4312 e1000_shift_out_mdi_bits(hw, PHY_PREAMBLE, PHY_PREAMBLE_SIZE);
4314 /* Now combine the remaining required fields that will indicate a
4315 * write operation. We use this method instead of calling the
4316 * e1000_shift_out_mdi_bits routine for each field in the command. The
4317 * format of a MII write instruction is as follows:
4318 * <Preamble><SOF><Op Code><Phy Addr><Reg Addr><Turnaround><Data>.
4320 mdic = ((PHY_TURNAROUND) | (reg_addr << 2) | (phy_addr << 7) |
4321 (PHY_OP_WRITE << 12) | (PHY_SOF << 14));
4323 mdic |= (uint32_t) phy_data;
4325 e1000_shift_out_mdi_bits(hw, mdic, 32);
4330 /******************************************************************************
4331 * Checks if PHY reset is blocked due to SOL/IDER session, for example.
4332 * Returning E1000_BLK_PHY_RESET isn't necessarily an error. But it's up to
4333 * the caller to figure out how to deal with it.
4335 * hw - Struct containing variables accessed by shared code
4337 * returns: - E1000_BLK_PHY_RESET
4340 *****************************************************************************/
4342 e1000_check_phy_reset_block(struct e1000_hw *hw)
4347 if (hw->mac_type == e1000_ich8lan) {
4348 fwsm = E1000_READ_REG(hw, FWSM);
4349 return (fwsm & E1000_FWSM_RSPCIPHY) ? E1000_SUCCESS
4350 : E1000_BLK_PHY_RESET;
4353 if (hw->mac_type > e1000_82547_rev_2)
4354 manc = E1000_READ_REG(hw, MANC);
4355 return (manc & E1000_MANC_BLK_PHY_RST_ON_IDE) ?
4356 E1000_BLK_PHY_RESET : E1000_SUCCESS;
4359 /***************************************************************************
4360 * Checks if the PHY configuration is done
4362 * hw: Struct containing variables accessed by shared code
4364 * returns: - E1000_ERR_RESET if fail to reset MAC
4365 * E1000_SUCCESS at any other case.
4367 ***************************************************************************/
4369 e1000_get_phy_cfg_done(struct e1000_hw *hw)
4371 int32_t timeout = PHY_CFG_TIMEOUT;
4372 uint32_t cfg_mask = E1000_EEPROM_CFG_DONE;
4376 switch (hw->mac_type) {
4381 case e1000_80003es2lan:
4382 /* Separate *_CFG_DONE_* bit for each port */
4383 if (e1000_is_second_port(hw))
4384 cfg_mask = E1000_EEPROM_CFG_DONE_PORT_1;
4391 if (hw->mac_type == e1000_igb) {
4392 if (E1000_READ_REG(hw, I210_EEMNGCTL) & cfg_mask)
4395 if (E1000_READ_REG(hw, EEMNGCTL) & cfg_mask)
4402 DEBUGOUT("MNG configuration cycle has not "
4404 return -E1000_ERR_RESET;
4409 return E1000_SUCCESS;
4412 /******************************************************************************
4413 * Returns the PHY to the power-on reset state
4415 * hw - Struct containing variables accessed by shared code
4416 ******************************************************************************/
4418 e1000_phy_hw_reset(struct e1000_hw *hw)
4420 uint16_t swfw = E1000_SWFW_PHY0_SM;
4421 uint32_t ctrl, ctrl_ext;
4427 /* In the case of the phy reset being blocked, it's not an error, we
4428 * simply return success without performing the reset. */
4429 ret_val = e1000_check_phy_reset_block(hw);
4431 return E1000_SUCCESS;
4433 DEBUGOUT("Resetting Phy...\n");
4435 if (hw->mac_type > e1000_82543) {
4436 if (e1000_is_second_port(hw))
4437 swfw = E1000_SWFW_PHY1_SM;
4439 if (e1000_swfw_sync_acquire(hw, swfw)) {
4440 DEBUGOUT("Unable to acquire swfw sync\n");
4441 return -E1000_ERR_SWFW_SYNC;
4444 /* Read the device control register and assert the E1000_CTRL_PHY_RST
4445 * bit. Then, take it out of reset.
4447 ctrl = E1000_READ_REG(hw, CTRL);
4448 E1000_WRITE_REG(hw, CTRL, ctrl | E1000_CTRL_PHY_RST);
4449 E1000_WRITE_FLUSH(hw);
4451 if (hw->mac_type < e1000_82571)
4456 E1000_WRITE_REG(hw, CTRL, ctrl);
4457 E1000_WRITE_FLUSH(hw);
4459 if (hw->mac_type >= e1000_82571)
4462 /* Read the Extended Device Control Register, assert the PHY_RESET_DIR
4463 * bit to put the PHY into reset. Then, take it out of reset.
4465 ctrl_ext = E1000_READ_REG(hw, CTRL_EXT);
4466 ctrl_ext |= E1000_CTRL_EXT_SDP4_DIR;
4467 ctrl_ext &= ~E1000_CTRL_EXT_SDP4_DATA;
4468 E1000_WRITE_REG(hw, CTRL_EXT, ctrl_ext);
4469 E1000_WRITE_FLUSH(hw);
4471 ctrl_ext |= E1000_CTRL_EXT_SDP4_DATA;
4472 E1000_WRITE_REG(hw, CTRL_EXT, ctrl_ext);
4473 E1000_WRITE_FLUSH(hw);
4477 if ((hw->mac_type == e1000_82541) || (hw->mac_type == e1000_82547)) {
4478 /* Configure activity LED after PHY reset */
4479 led_ctrl = E1000_READ_REG(hw, LEDCTL);
4480 led_ctrl &= IGP_ACTIVITY_LED_MASK;
4481 led_ctrl |= (IGP_ACTIVITY_LED_ENABLE | IGP_LED3_MODE);
4482 E1000_WRITE_REG(hw, LEDCTL, led_ctrl);
4485 e1000_swfw_sync_release(hw, swfw);
4487 /* Wait for FW to finish PHY configuration. */
4488 ret_val = e1000_get_phy_cfg_done(hw);
4489 if (ret_val != E1000_SUCCESS)
4495 /******************************************************************************
4496 * IGP phy init script - initializes the GbE PHY
4498 * hw - Struct containing variables accessed by shared code
4499 *****************************************************************************/
4501 e1000_phy_init_script(struct e1000_hw *hw)
4504 uint16_t phy_saved_data;
4507 if (hw->phy_init_script) {
4510 /* Save off the current value of register 0x2F5B to be
4511 * restored at the end of this routine. */
4512 ret_val = e1000_read_phy_reg(hw, 0x2F5B, &phy_saved_data);
4514 /* Disabled the PHY transmitter */
4515 e1000_write_phy_reg(hw, 0x2F5B, 0x0003);
4519 e1000_write_phy_reg(hw, 0x0000, 0x0140);
4523 switch (hw->mac_type) {
4526 e1000_write_phy_reg(hw, 0x1F95, 0x0001);
4528 e1000_write_phy_reg(hw, 0x1F71, 0xBD21);
4530 e1000_write_phy_reg(hw, 0x1F79, 0x0018);
4532 e1000_write_phy_reg(hw, 0x1F30, 0x1600);
4534 e1000_write_phy_reg(hw, 0x1F31, 0x0014);
4536 e1000_write_phy_reg(hw, 0x1F32, 0x161C);
4538 e1000_write_phy_reg(hw, 0x1F94, 0x0003);
4540 e1000_write_phy_reg(hw, 0x1F96, 0x003F);
4542 e1000_write_phy_reg(hw, 0x2010, 0x0008);
4545 case e1000_82541_rev_2:
4546 case e1000_82547_rev_2:
4547 e1000_write_phy_reg(hw, 0x1F73, 0x0099);
4553 e1000_write_phy_reg(hw, 0x0000, 0x3300);
4557 /* Now enable the transmitter */
4559 e1000_write_phy_reg(hw, 0x2F5B, phy_saved_data);
4561 if (hw->mac_type == e1000_82547) {
4562 uint16_t fused, fine, coarse;
4564 /* Move to analog registers page */
4565 e1000_read_phy_reg(hw,
4566 IGP01E1000_ANALOG_SPARE_FUSE_STATUS, &fused);
4568 if (!(fused & IGP01E1000_ANALOG_SPARE_FUSE_ENABLED)) {
4569 e1000_read_phy_reg(hw,
4570 IGP01E1000_ANALOG_FUSE_STATUS, &fused);
4572 fine = fused & IGP01E1000_ANALOG_FUSE_FINE_MASK;
4574 & IGP01E1000_ANALOG_FUSE_COARSE_MASK;
4577 IGP01E1000_ANALOG_FUSE_COARSE_THRESH) {
4579 IGP01E1000_ANALOG_FUSE_COARSE_10;
4580 fine -= IGP01E1000_ANALOG_FUSE_FINE_1;
4582 == IGP01E1000_ANALOG_FUSE_COARSE_THRESH)
4583 fine -= IGP01E1000_ANALOG_FUSE_FINE_10;
4586 & IGP01E1000_ANALOG_FUSE_POLY_MASK) |
4588 & IGP01E1000_ANALOG_FUSE_FINE_MASK) |
4590 & IGP01E1000_ANALOG_FUSE_COARSE_MASK);
4592 e1000_write_phy_reg(hw,
4593 IGP01E1000_ANALOG_FUSE_CONTROL, fused);
4594 e1000_write_phy_reg(hw,
4595 IGP01E1000_ANALOG_FUSE_BYPASS,
4596 IGP01E1000_ANALOG_FUSE_ENABLE_SW_CONTROL);
4602 /******************************************************************************
4605 * hw - Struct containing variables accessed by shared code
4607 * Sets bit 15 of the MII Control register
4608 ******************************************************************************/
4610 e1000_phy_reset(struct e1000_hw *hw)
4617 /* In the case of the phy reset being blocked, it's not an error, we
4618 * simply return success without performing the reset. */
4619 ret_val = e1000_check_phy_reset_block(hw);
4621 return E1000_SUCCESS;
4623 switch (hw->phy_type) {
4625 case e1000_phy_igp_2:
4626 case e1000_phy_igp_3:
4629 ret_val = e1000_phy_hw_reset(hw);
4634 ret_val = e1000_read_phy_reg(hw, PHY_CTRL, &phy_data);
4638 phy_data |= MII_CR_RESET;
4639 ret_val = e1000_write_phy_reg(hw, PHY_CTRL, phy_data);
4647 if (hw->phy_type == e1000_phy_igp || hw->phy_type == e1000_phy_igp_2)
4648 e1000_phy_init_script(hw);
4650 return E1000_SUCCESS;
4653 static int e1000_set_phy_type (struct e1000_hw *hw)
4657 if (hw->mac_type == e1000_undefined)
4658 return -E1000_ERR_PHY_TYPE;
4660 switch (hw->phy_id) {
4661 case M88E1000_E_PHY_ID:
4662 case M88E1000_I_PHY_ID:
4663 case M88E1011_I_PHY_ID:
4664 case M88E1111_I_PHY_ID:
4665 hw->phy_type = e1000_phy_m88;
4667 case IGP01E1000_I_PHY_ID:
4668 if (hw->mac_type == e1000_82541 ||
4669 hw->mac_type == e1000_82541_rev_2 ||
4670 hw->mac_type == e1000_82547 ||
4671 hw->mac_type == e1000_82547_rev_2) {
4672 hw->phy_type = e1000_phy_igp;
4675 case IGP03E1000_E_PHY_ID:
4676 hw->phy_type = e1000_phy_igp_3;
4679 case IFE_PLUS_E_PHY_ID:
4680 case IFE_C_E_PHY_ID:
4681 hw->phy_type = e1000_phy_ife;
4683 case GG82563_E_PHY_ID:
4684 if (hw->mac_type == e1000_80003es2lan) {
4685 hw->phy_type = e1000_phy_gg82563;
4688 case BME1000_E_PHY_ID:
4689 hw->phy_type = e1000_phy_bm;
4692 hw->phy_type = e1000_phy_igb;
4696 /* Should never have loaded on this device */
4697 hw->phy_type = e1000_phy_undefined;
4698 return -E1000_ERR_PHY_TYPE;
4701 return E1000_SUCCESS;
4704 /******************************************************************************
4705 * Probes the expected PHY address for known PHY IDs
4707 * hw - Struct containing variables accessed by shared code
4708 ******************************************************************************/
4710 e1000_detect_gig_phy(struct e1000_hw *hw)
4712 int32_t phy_init_status, ret_val;
4713 uint16_t phy_id_high, phy_id_low;
4718 /* The 82571 firmware may still be configuring the PHY. In this
4719 * case, we cannot access the PHY until the configuration is done. So
4720 * we explicitly set the PHY values. */
4721 if (hw->mac_type == e1000_82571 ||
4722 hw->mac_type == e1000_82572) {
4723 hw->phy_id = IGP01E1000_I_PHY_ID;
4724 hw->phy_type = e1000_phy_igp_2;
4725 return E1000_SUCCESS;
4728 /* ESB-2 PHY reads require e1000_phy_gg82563 to be set because of a
4729 * work- around that forces PHY page 0 to be set or the reads fail.
4730 * The rest of the code in this routine uses e1000_read_phy_reg to
4731 * read the PHY ID. So for ESB-2 we need to have this set so our
4732 * reads won't fail. If the attached PHY is not a e1000_phy_gg82563,
4733 * the routines below will figure this out as well. */
4734 if (hw->mac_type == e1000_80003es2lan)
4735 hw->phy_type = e1000_phy_gg82563;
4737 /* Read the PHY ID Registers to identify which PHY is onboard. */
4738 ret_val = e1000_read_phy_reg(hw, PHY_ID1, &phy_id_high);
4742 hw->phy_id = (uint32_t) (phy_id_high << 16);
4744 ret_val = e1000_read_phy_reg(hw, PHY_ID2, &phy_id_low);
4748 hw->phy_id |= (uint32_t) (phy_id_low & PHY_REVISION_MASK);
4749 hw->phy_revision = (uint32_t) phy_id_low & ~PHY_REVISION_MASK;
4751 switch (hw->mac_type) {
4753 if (hw->phy_id == M88E1000_E_PHY_ID)
4757 if (hw->phy_id == M88E1000_I_PHY_ID)
4762 case e1000_82545_rev_3:
4764 case e1000_82546_rev_3:
4765 if (hw->phy_id == M88E1011_I_PHY_ID)
4769 case e1000_82541_rev_2:
4771 case e1000_82547_rev_2:
4772 if(hw->phy_id == IGP01E1000_I_PHY_ID)
4777 if (hw->phy_id == M88E1111_I_PHY_ID)
4781 if (hw->phy_id == BME1000_E_PHY_ID)
4784 case e1000_80003es2lan:
4785 if (hw->phy_id == GG82563_E_PHY_ID)
4789 if (hw->phy_id == IGP03E1000_E_PHY_ID)
4791 if (hw->phy_id == IFE_E_PHY_ID)
4793 if (hw->phy_id == IFE_PLUS_E_PHY_ID)
4795 if (hw->phy_id == IFE_C_E_PHY_ID)
4799 if (hw->phy_id == I210_I_PHY_ID)
4803 DEBUGOUT("Invalid MAC type %d\n", hw->mac_type);
4804 return -E1000_ERR_CONFIG;
4807 phy_init_status = e1000_set_phy_type(hw);
4809 if ((match) && (phy_init_status == E1000_SUCCESS)) {
4810 DEBUGOUT("PHY ID 0x%X detected\n", hw->phy_id);
4813 DEBUGOUT("Invalid PHY ID 0x%X\n", hw->phy_id);
4814 return -E1000_ERR_PHY;
4817 /*****************************************************************************
4818 * Set media type and TBI compatibility.
4820 * hw - Struct containing variables accessed by shared code
4821 * **************************************************************************/
4823 e1000_set_media_type(struct e1000_hw *hw)
4829 if (hw->mac_type != e1000_82543) {
4830 /* tbi_compatibility is only valid on 82543 */
4831 hw->tbi_compatibility_en = false;
4834 switch (hw->device_id) {
4835 case E1000_DEV_ID_82545GM_SERDES:
4836 case E1000_DEV_ID_82546GB_SERDES:
4837 case E1000_DEV_ID_82571EB_SERDES:
4838 case E1000_DEV_ID_82571EB_SERDES_DUAL:
4839 case E1000_DEV_ID_82571EB_SERDES_QUAD:
4840 case E1000_DEV_ID_82572EI_SERDES:
4841 case E1000_DEV_ID_80003ES2LAN_SERDES_DPT:
4842 hw->media_type = e1000_media_type_internal_serdes;
4845 switch (hw->mac_type) {
4846 case e1000_82542_rev2_0:
4847 case e1000_82542_rev2_1:
4848 hw->media_type = e1000_media_type_fiber;
4854 /* The STATUS_TBIMODE bit is reserved or reused
4855 * for the this device.
4857 hw->media_type = e1000_media_type_copper;
4860 status = E1000_READ_REG(hw, STATUS);
4861 if (status & E1000_STATUS_TBIMODE) {
4862 hw->media_type = e1000_media_type_fiber;
4863 /* tbi_compatibility not valid on fiber */
4864 hw->tbi_compatibility_en = false;
4866 hw->media_type = e1000_media_type_copper;
4874 * e1000_sw_init - Initialize general software structures (struct e1000_adapter)
4876 * e1000_sw_init initializes the Adapter private data structure.
4877 * Fields are initialized based on PCI device information and
4878 * OS network device settings (MTU size).
4882 e1000_sw_init(struct eth_device *nic)
4884 struct e1000_hw *hw = (typeof(hw)) nic->priv;
4887 /* PCI config space info */
4888 pci_read_config_word(hw->pdev, PCI_VENDOR_ID, &hw->vendor_id);
4889 pci_read_config_word(hw->pdev, PCI_DEVICE_ID, &hw->device_id);
4890 pci_read_config_word(hw->pdev, PCI_SUBSYSTEM_VENDOR_ID,
4891 &hw->subsystem_vendor_id);
4892 pci_read_config_word(hw->pdev, PCI_SUBSYSTEM_ID, &hw->subsystem_id);
4894 pci_read_config_byte(hw->pdev, PCI_REVISION_ID, &hw->revision_id);
4895 pci_read_config_word(hw->pdev, PCI_COMMAND, &hw->pci_cmd_word);
4897 /* identify the MAC */
4898 result = e1000_set_mac_type(hw);
4900 E1000_ERR(hw->nic, "Unknown MAC Type\n");
4904 switch (hw->mac_type) {
4909 case e1000_82541_rev_2:
4910 case e1000_82547_rev_2:
4911 hw->phy_init_script = 1;
4915 /* flow control settings */
4916 hw->fc_high_water = E1000_FC_HIGH_THRESH;
4917 hw->fc_low_water = E1000_FC_LOW_THRESH;
4918 hw->fc_pause_time = E1000_FC_PAUSE_TIME;
4919 hw->fc_send_xon = 1;
4921 /* Media type - copper or fiber */
4922 hw->tbi_compatibility_en = true;
4923 e1000_set_media_type(hw);
4925 if (hw->mac_type >= e1000_82543) {
4926 uint32_t status = E1000_READ_REG(hw, STATUS);
4928 if (status & E1000_STATUS_TBIMODE) {
4929 DEBUGOUT("fiber interface\n");
4930 hw->media_type = e1000_media_type_fiber;
4932 DEBUGOUT("copper interface\n");
4933 hw->media_type = e1000_media_type_copper;
4936 hw->media_type = e1000_media_type_fiber;
4939 hw->wait_autoneg_complete = true;
4940 if (hw->mac_type < e1000_82543)
4941 hw->report_tx_early = 0;
4943 hw->report_tx_early = 1;
4945 return E1000_SUCCESS;
4949 fill_rx(struct e1000_hw *hw)
4951 struct e1000_rx_desc *rd;
4952 unsigned long flush_start, flush_end;
4955 rd = rx_base + rx_tail;
4956 rx_tail = (rx_tail + 1) % 8;
4958 rd->buffer_addr = cpu_to_le64((unsigned long)packet);
4961 * Make sure there are no stale data in WB over this area, which
4962 * might get written into the memory while the e1000 also writes
4963 * into the same memory area.
4965 invalidate_dcache_range((unsigned long)packet,
4966 (unsigned long)packet + 4096);
4967 /* Dump the DMA descriptor into RAM. */
4968 flush_start = ((unsigned long)rd) & ~(ARCH_DMA_MINALIGN - 1);
4969 flush_end = flush_start + roundup(sizeof(*rd), ARCH_DMA_MINALIGN);
4970 flush_dcache_range(flush_start, flush_end);
4972 E1000_WRITE_REG(hw, RDT, rx_tail);
4976 * e1000_configure_tx - Configure 8254x Transmit Unit after Reset
4977 * @adapter: board private structure
4979 * Configure the Tx unit of the MAC after a reset.
4983 e1000_configure_tx(struct e1000_hw *hw)
4986 unsigned long tipg, tarc;
4987 uint32_t ipgr1, ipgr2;
4989 E1000_WRITE_REG(hw, TDBAL, (unsigned long)tx_base);
4990 E1000_WRITE_REG(hw, TDBAH, 0);
4992 E1000_WRITE_REG(hw, TDLEN, 128);
4994 /* Setup the HW Tx Head and Tail descriptor pointers */
4995 E1000_WRITE_REG(hw, TDH, 0);
4996 E1000_WRITE_REG(hw, TDT, 0);
4999 /* Set the default values for the Tx Inter Packet Gap timer */
5000 if (hw->mac_type <= e1000_82547_rev_2 &&
5001 (hw->media_type == e1000_media_type_fiber ||
5002 hw->media_type == e1000_media_type_internal_serdes))
5003 tipg = DEFAULT_82543_TIPG_IPGT_FIBER;
5005 tipg = DEFAULT_82543_TIPG_IPGT_COPPER;
5007 /* Set the default values for the Tx Inter Packet Gap timer */
5008 switch (hw->mac_type) {
5009 case e1000_82542_rev2_0:
5010 case e1000_82542_rev2_1:
5011 tipg = DEFAULT_82542_TIPG_IPGT;
5012 ipgr1 = DEFAULT_82542_TIPG_IPGR1;
5013 ipgr2 = DEFAULT_82542_TIPG_IPGR2;
5015 case e1000_80003es2lan:
5016 ipgr1 = DEFAULT_82543_TIPG_IPGR1;
5017 ipgr2 = DEFAULT_80003ES2LAN_TIPG_IPGR2;
5020 ipgr1 = DEFAULT_82543_TIPG_IPGR1;
5021 ipgr2 = DEFAULT_82543_TIPG_IPGR2;
5024 tipg |= ipgr1 << E1000_TIPG_IPGR1_SHIFT;
5025 tipg |= ipgr2 << E1000_TIPG_IPGR2_SHIFT;
5026 E1000_WRITE_REG(hw, TIPG, tipg);
5027 /* Program the Transmit Control Register */
5028 tctl = E1000_READ_REG(hw, TCTL);
5029 tctl &= ~E1000_TCTL_CT;
5030 tctl |= E1000_TCTL_EN | E1000_TCTL_PSP |
5031 (E1000_COLLISION_THRESHOLD << E1000_CT_SHIFT);
5033 if (hw->mac_type == e1000_82571 || hw->mac_type == e1000_82572) {
5034 tarc = E1000_READ_REG(hw, TARC0);
5035 /* set the speed mode bit, we'll clear it if we're not at
5036 * gigabit link later */
5037 /* git bit can be set to 1*/
5038 } else if (hw->mac_type == e1000_80003es2lan) {
5039 tarc = E1000_READ_REG(hw, TARC0);
5041 E1000_WRITE_REG(hw, TARC0, tarc);
5042 tarc = E1000_READ_REG(hw, TARC1);
5044 E1000_WRITE_REG(hw, TARC1, tarc);
5048 e1000_config_collision_dist(hw);
5049 /* Setup Transmit Descriptor Settings for eop descriptor */
5050 hw->txd_cmd = E1000_TXD_CMD_EOP | E1000_TXD_CMD_IFCS;
5052 /* Need to set up RS bit */
5053 if (hw->mac_type < e1000_82543)
5054 hw->txd_cmd |= E1000_TXD_CMD_RPS;
5056 hw->txd_cmd |= E1000_TXD_CMD_RS;
5059 if (hw->mac_type == e1000_igb) {
5060 E1000_WRITE_REG(hw, TCTL_EXT, 0x42 << 10);
5062 uint32_t reg_txdctl = E1000_READ_REG(hw, TXDCTL);
5063 reg_txdctl |= 1 << 25;
5064 E1000_WRITE_REG(hw, TXDCTL, reg_txdctl);
5070 E1000_WRITE_REG(hw, TCTL, tctl);
5076 * e1000_setup_rctl - configure the receive control register
5077 * @adapter: Board private structure
5080 e1000_setup_rctl(struct e1000_hw *hw)
5084 rctl = E1000_READ_REG(hw, RCTL);
5086 rctl &= ~(3 << E1000_RCTL_MO_SHIFT);
5088 rctl |= E1000_RCTL_EN | E1000_RCTL_BAM | E1000_RCTL_LBM_NO
5089 | E1000_RCTL_RDMTS_HALF; /* |
5090 (hw.mc_filter_type << E1000_RCTL_MO_SHIFT); */
5092 if (hw->tbi_compatibility_on == 1)
5093 rctl |= E1000_RCTL_SBP;
5095 rctl &= ~E1000_RCTL_SBP;
5097 rctl &= ~(E1000_RCTL_SZ_4096);
5098 rctl |= E1000_RCTL_SZ_2048;
5099 rctl &= ~(E1000_RCTL_BSEX | E1000_RCTL_LPE);
5100 E1000_WRITE_REG(hw, RCTL, rctl);
5104 * e1000_configure_rx - Configure 8254x Receive Unit after Reset
5105 * @adapter: board private structure
5107 * Configure the Rx unit of the MAC after a reset.
5110 e1000_configure_rx(struct e1000_hw *hw)
5112 unsigned long rctl, ctrl_ext;
5114 /* make sure receives are disabled while setting up the descriptors */
5115 rctl = E1000_READ_REG(hw, RCTL);
5116 E1000_WRITE_REG(hw, RCTL, rctl & ~E1000_RCTL_EN);
5117 if (hw->mac_type >= e1000_82540) {
5118 /* Set the interrupt throttling rate. Value is calculated
5119 * as DEFAULT_ITR = 1/(MAX_INTS_PER_SEC * 256ns) */
5120 #define MAX_INTS_PER_SEC 8000
5121 #define DEFAULT_ITR 1000000000/(MAX_INTS_PER_SEC * 256)
5122 E1000_WRITE_REG(hw, ITR, DEFAULT_ITR);
5125 if (hw->mac_type >= e1000_82571) {
5126 ctrl_ext = E1000_READ_REG(hw, CTRL_EXT);
5127 /* Reset delay timers after every interrupt */
5128 ctrl_ext |= E1000_CTRL_EXT_INT_TIMER_CLR;
5129 E1000_WRITE_REG(hw, CTRL_EXT, ctrl_ext);
5130 E1000_WRITE_FLUSH(hw);
5132 /* Setup the Base and Length of the Rx Descriptor Ring */
5133 E1000_WRITE_REG(hw, RDBAL, (unsigned long)rx_base);
5134 E1000_WRITE_REG(hw, RDBAH, 0);
5136 E1000_WRITE_REG(hw, RDLEN, 128);
5138 /* Setup the HW Rx Head and Tail Descriptor Pointers */
5139 E1000_WRITE_REG(hw, RDH, 0);
5140 E1000_WRITE_REG(hw, RDT, 0);
5141 /* Enable Receives */
5143 if (hw->mac_type == e1000_igb) {
5145 uint32_t reg_rxdctl = E1000_READ_REG(hw, RXDCTL);
5146 reg_rxdctl |= 1 << 25;
5147 E1000_WRITE_REG(hw, RXDCTL, reg_rxdctl);
5151 E1000_WRITE_REG(hw, RCTL, rctl);
5156 /**************************************************************************
5157 POLL - Wait for a frame
5158 ***************************************************************************/
5160 e1000_poll(struct eth_device *nic)
5162 struct e1000_hw *hw = nic->priv;
5163 struct e1000_rx_desc *rd;
5164 unsigned long inval_start, inval_end;
5167 /* return true if there's an ethernet packet ready to read */
5168 rd = rx_base + rx_last;
5170 /* Re-load the descriptor from RAM. */
5171 inval_start = ((unsigned long)rd) & ~(ARCH_DMA_MINALIGN - 1);
5172 inval_end = inval_start + roundup(sizeof(*rd), ARCH_DMA_MINALIGN);
5173 invalidate_dcache_range(inval_start, inval_end);
5175 if (!(le32_to_cpu(rd->status)) & E1000_RXD_STAT_DD)
5177 /* DEBUGOUT("recv: packet len=%d\n", rd->length); */
5178 /* Packet received, make sure the data are re-loaded from RAM. */
5179 len = le32_to_cpu(rd->length);
5180 invalidate_dcache_range((unsigned long)packet,
5181 (unsigned long)packet +
5182 roundup(len, ARCH_DMA_MINALIGN));
5183 net_process_received_packet((uchar *)packet, len);
5188 /**************************************************************************
5189 TRANSMIT - Transmit a frame
5190 ***************************************************************************/
5191 static int e1000_transmit(struct eth_device *nic, void *txpacket, int length)
5193 void *nv_packet = (void *)txpacket;
5194 struct e1000_hw *hw = nic->priv;
5195 struct e1000_tx_desc *txp;
5197 unsigned long flush_start, flush_end;
5199 txp = tx_base + tx_tail;
5200 tx_tail = (tx_tail + 1) % 8;
5202 txp->buffer_addr = cpu_to_le64(virt_to_bus(hw->pdev, nv_packet));
5203 txp->lower.data = cpu_to_le32(hw->txd_cmd | length);
5204 txp->upper.data = 0;
5206 /* Dump the packet into RAM so e1000 can pick them. */
5207 flush_dcache_range((unsigned long)nv_packet,
5208 (unsigned long)nv_packet +
5209 roundup(length, ARCH_DMA_MINALIGN));
5210 /* Dump the descriptor into RAM as well. */
5211 flush_start = ((unsigned long)txp) & ~(ARCH_DMA_MINALIGN - 1);
5212 flush_end = flush_start + roundup(sizeof(*txp), ARCH_DMA_MINALIGN);
5213 flush_dcache_range(flush_start, flush_end);
5215 E1000_WRITE_REG(hw, TDT, tx_tail);
5217 E1000_WRITE_FLUSH(hw);
5219 invalidate_dcache_range(flush_start, flush_end);
5220 if (le32_to_cpu(txp->upper.data) & E1000_TXD_STAT_DD)
5222 if (i++ > TOUT_LOOP) {
5223 DEBUGOUT("e1000: tx timeout\n");
5226 udelay(10); /* give the nic a chance to write to the register */
5233 e1000_reset(struct eth_device *nic)
5235 struct e1000_hw *hw = nic->priv;
5238 if (hw->mac_type >= e1000_82544) {
5239 E1000_WRITE_REG(hw, WUC, 0);
5241 return e1000_init_hw(nic);
5244 /**************************************************************************
5245 DISABLE - Turn off ethernet interface
5246 ***************************************************************************/
5248 e1000_disable(struct eth_device *nic)
5250 struct e1000_hw *hw = nic->priv;
5252 /* Turn off the ethernet interface */
5253 E1000_WRITE_REG(hw, RCTL, 0);
5254 E1000_WRITE_REG(hw, TCTL, 0);
5256 /* Clear the transmit ring */
5257 E1000_WRITE_REG(hw, TDH, 0);
5258 E1000_WRITE_REG(hw, TDT, 0);
5260 /* Clear the receive ring */
5261 E1000_WRITE_REG(hw, RDH, 0);
5262 E1000_WRITE_REG(hw, RDT, 0);
5264 /* put the card in its initial state */
5266 E1000_WRITE_REG(hw, CTRL, E1000_CTRL_RST);
5272 /**************************************************************************
5273 INIT - set up ethernet interface(s)
5274 ***************************************************************************/
5276 e1000_init(struct eth_device *nic, bd_t * bis)
5278 struct e1000_hw *hw = nic->priv;
5281 ret_val = e1000_reset(nic);
5283 if ((ret_val == -E1000_ERR_NOLINK) ||
5284 (ret_val == -E1000_ERR_TIMEOUT)) {
5285 E1000_ERR(hw->nic, "Valid Link not detected\n");
5287 E1000_ERR(hw->nic, "Hardware Initialization Failed\n");
5291 e1000_configure_tx(hw);
5292 e1000_setup_rctl(hw);
5293 e1000_configure_rx(hw);
5297 /******************************************************************************
5298 * Gets the current PCI bus type of hardware
5300 * hw - Struct containing variables accessed by shared code
5301 *****************************************************************************/
5302 void e1000_get_bus_type(struct e1000_hw *hw)
5306 switch (hw->mac_type) {
5307 case e1000_82542_rev2_0:
5308 case e1000_82542_rev2_1:
5309 hw->bus_type = e1000_bus_type_pci;
5315 case e1000_80003es2lan:
5318 hw->bus_type = e1000_bus_type_pci_express;
5321 status = E1000_READ_REG(hw, STATUS);
5322 hw->bus_type = (status & E1000_STATUS_PCIX_MODE) ?
5323 e1000_bus_type_pcix : e1000_bus_type_pci;
5328 /* A list of all registered e1000 devices */
5329 static LIST_HEAD(e1000_hw_list);
5331 /**************************************************************************
5332 PROBE - Look for an adapter, this routine's visible to the outside
5333 You should omit the last argument struct pci_device * for a non-PCI NIC
5334 ***************************************************************************/
5336 e1000_initialize(bd_t * bis)
5343 /* Find and probe all the matching PCI devices */
5344 for (i = 0; (devno = pci_find_devices(e1000_supported, i)) >= 0; i++) {
5348 * These will never get freed due to errors, this allows us to
5349 * perform SPI EEPROM programming from U-boot, for example.
5351 struct eth_device *nic = malloc(sizeof(*nic));
5352 struct e1000_hw *hw = malloc(sizeof(*hw));
5354 printf("e1000#%u: Out of Memory!\n", i);
5360 /* Make sure all of the fields are initially zeroed */
5361 memset(nic, 0, sizeof(*nic));
5362 memset(hw, 0, sizeof(*hw));
5364 /* Assign the passed-in values */
5370 /* Generate a card name */
5371 sprintf(nic->name, "e1000#%u", hw->cardnum);
5373 /* Print a debug message with the IO base address */
5374 pci_read_config_dword(devno, PCI_BASE_ADDRESS_0, &val);
5375 E1000_DBG(nic, "iobase 0x%08x\n", val & 0xfffffff0);
5377 /* Try to enable I/O accesses and bus-mastering */
5378 val = PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER;
5379 pci_write_config_dword(devno, PCI_COMMAND, val);
5381 /* Make sure it worked */
5382 pci_read_config_dword(devno, PCI_COMMAND, &val);
5383 if (!(val & PCI_COMMAND_MEMORY)) {
5384 E1000_ERR(nic, "Can't enable I/O memory\n");
5387 if (!(val & PCI_COMMAND_MASTER)) {
5388 E1000_ERR(nic, "Can't enable bus-mastering\n");
5392 /* Are these variables needed? */
5393 hw->fc = e1000_fc_default;
5394 hw->original_fc = e1000_fc_default;
5395 hw->autoneg_failed = 0;
5397 hw->get_link_status = true;
5398 #ifndef CONFIG_E1000_NO_NVM
5399 hw->eeprom_semaphore_present = true;
5401 hw->hw_addr = pci_map_bar(devno, PCI_BASE_ADDRESS_0,
5403 hw->mac_type = e1000_undefined;
5405 /* MAC and Phy settings */
5406 if (e1000_sw_init(nic) < 0) {
5407 E1000_ERR(nic, "Software init failed\n");
5410 if (e1000_check_phy_reset_block(hw))
5411 E1000_ERR(nic, "PHY Reset is blocked!\n");
5413 /* Basic init was OK, reset the hardware and allow SPI access */
5415 list_add_tail(&hw->list_node, &e1000_hw_list);
5417 #ifndef CONFIG_E1000_NO_NVM
5418 /* Validate the EEPROM and get chipset information */
5419 #if !defined(CONFIG_MVBC_1G)
5420 if (e1000_init_eeprom_params(hw)) {
5421 E1000_ERR(nic, "EEPROM is invalid!\n");
5424 if ((E1000_READ_REG(hw, I210_EECD) & E1000_EECD_FLUPD) &&
5425 e1000_validate_eeprom_checksum(hw))
5428 e1000_read_mac_addr(nic);
5430 e1000_get_bus_type(hw);
5432 #ifndef CONFIG_E1000_NO_NVM
5433 printf("e1000: %02x:%02x:%02x:%02x:%02x:%02x\n ",
5434 nic->enetaddr[0], nic->enetaddr[1], nic->enetaddr[2],
5435 nic->enetaddr[3], nic->enetaddr[4], nic->enetaddr[5]);
5437 memset(nic->enetaddr, 0, 6);
5438 printf("e1000: no NVM\n");
5441 /* Set up the function pointers and register the device */
5442 nic->init = e1000_init;
5443 nic->recv = e1000_poll;
5444 nic->send = e1000_transmit;
5445 nic->halt = e1000_disable;
5452 struct e1000_hw *e1000_find_card(unsigned int cardnum)
5454 struct e1000_hw *hw;
5456 list_for_each_entry(hw, &e1000_hw_list, list_node)
5457 if (hw->cardnum == cardnum)
5463 #ifdef CONFIG_CMD_E1000
5464 static int do_e1000(cmd_tbl_t *cmdtp, int flag,
5465 int argc, char * const argv[])
5467 struct e1000_hw *hw;
5474 /* Make sure we can find the requested e1000 card */
5475 hw = e1000_find_card(simple_strtoul(argv[1], NULL, 10));
5477 printf("e1000: ERROR: No such device: e1000#%s\n", argv[1]);
5481 if (!strcmp(argv[2], "print-mac-address")) {
5482 unsigned char *mac = hw->nic->enetaddr;
5483 printf("%02x:%02x:%02x:%02x:%02x:%02x\n",
5484 mac[0], mac[1], mac[2], mac[3], mac[4], mac[5]);
5488 #ifdef CONFIG_E1000_SPI
5489 /* Handle the "SPI" subcommand */
5490 if (!strcmp(argv[2], "spi"))
5491 return do_e1000_spi(cmdtp, hw, argc - 3, argv + 3);
5499 e1000, 7, 0, do_e1000,
5500 "Intel e1000 controller management",
5501 /* */"<card#> print-mac-address\n"
5502 #ifdef CONFIG_E1000_SPI
5503 "e1000 <card#> spi show [<offset> [<length>]]\n"
5504 "e1000 <card#> spi dump <addr> <offset> <length>\n"
5505 "e1000 <card#> spi program <addr> <offset> <length>\n"
5506 "e1000 <card#> spi checksum [update]\n"
5508 " - Manage the Intel E1000 PCI device"
5510 #endif /* not CONFIG_CMD_E1000 */