1 /* Altera TSE SGDMA and MSGDMA Linux driver
2 * Copyright (C) 2014 Altera Corporation. All rights reserved
4 * This program is free software; you can redistribute it and/or modify it
5 * under the terms and conditions of the GNU General Public License,
6 * version 2, as published by the Free Software Foundation.
8 * This program is distributed in the hope it will be useful, but WITHOUT
9 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
10 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
13 * You should have received a copy of the GNU General Public License along with
14 * this program. If not, see <http://www.gnu.org/licenses/>.
17 #ifndef __ALTERA_MSGDMAHW_H__
18 #define __ALTERA_MSGDMAHW_H__
20 /* mSGDMA extended descriptor format
22 struct msgdma_extended_desc {
23 u32 read_addr_lo; /* data buffer source address low bits */
24 u32 write_addr_lo; /* data buffer destination address low bits */
25 u32 len; /* the number of bytes to transfer
28 u32 burst_seq_num; /* bit 31:24 write burst
29 * bit 23:16 read burst
30 * bit 15:0 sequence number
32 u32 stride; /* bit 31:16 write stride
33 * bit 15:0 read stride
35 u32 read_addr_hi; /* data buffer source address high bits */
36 u32 write_addr_hi; /* data buffer destination address high bits */
37 u32 control; /* characteristics of the transfer */
40 /* mSGDMA descriptor control field bit definitions
42 #define MSGDMA_DESC_CTL_SET_CH(x) ((x) & 0xff)
43 #define MSGDMA_DESC_CTL_GEN_SOP BIT(8)
44 #define MSGDMA_DESC_CTL_GEN_EOP BIT(9)
45 #define MSGDMA_DESC_CTL_PARK_READS BIT(10)
46 #define MSGDMA_DESC_CTL_PARK_WRITES BIT(11)
47 #define MSGDMA_DESC_CTL_END_ON_EOP BIT(12)
48 #define MSGDMA_DESC_CTL_END_ON_LEN BIT(13)
49 #define MSGDMA_DESC_CTL_TR_COMP_IRQ BIT(14)
50 #define MSGDMA_DESC_CTL_EARLY_IRQ BIT(15)
51 #define MSGDMA_DESC_CTL_TR_ERR_IRQ (0xff << 16)
52 #define MSGDMA_DESC_CTL_EARLY_DONE BIT(24)
53 /* Writing ‘1’ to the ‘go’ bit commits the entire descriptor into the
56 #define MSGDMA_DESC_CTL_GO BIT(31)
58 /* Tx buffer control flags
60 #define MSGDMA_DESC_CTL_TX_FIRST (MSGDMA_DESC_CTL_GEN_SOP | \
61 MSGDMA_DESC_CTL_TR_ERR_IRQ | \
64 #define MSGDMA_DESC_CTL_TX_MIDDLE (MSGDMA_DESC_CTL_TR_ERR_IRQ | \
67 #define MSGDMA_DESC_CTL_TX_LAST (MSGDMA_DESC_CTL_GEN_EOP | \
68 MSGDMA_DESC_CTL_TR_COMP_IRQ | \
69 MSGDMA_DESC_CTL_TR_ERR_IRQ | \
72 #define MSGDMA_DESC_CTL_TX_SINGLE (MSGDMA_DESC_CTL_GEN_SOP | \
73 MSGDMA_DESC_CTL_GEN_EOP | \
74 MSGDMA_DESC_CTL_TR_COMP_IRQ | \
75 MSGDMA_DESC_CTL_TR_ERR_IRQ | \
78 #define MSGDMA_DESC_CTL_RX_SINGLE (MSGDMA_DESC_CTL_END_ON_EOP | \
79 MSGDMA_DESC_CTL_END_ON_LEN | \
80 MSGDMA_DESC_CTL_TR_COMP_IRQ | \
81 MSGDMA_DESC_CTL_EARLY_IRQ | \
82 MSGDMA_DESC_CTL_TR_ERR_IRQ | \
85 /* mSGDMA extended descriptor stride definitions
87 #define MSGDMA_DESC_TX_STRIDE (0x00010001)
88 #define MSGDMA_DESC_RX_STRIDE (0x00010001)
90 /* mSGDMA dispatcher control and status register map
93 u32 status; /* Read/Clear */
94 u32 control; /* Read/Write */
95 u32 rw_fill_level; /* bit 31:16 - write fill level
96 * bit 15:0 - read fill level
98 u32 resp_fill_level; /* bit 15:0 */
99 u32 rw_seq_num; /* bit 31:16 - write sequence number
100 * bit 15:0 - read sequence number
102 u32 pad[3]; /* reserved */
105 /* mSGDMA CSR status register bit definitions
107 #define MSGDMA_CSR_STAT_BUSY BIT(0)
108 #define MSGDMA_CSR_STAT_DESC_BUF_EMPTY BIT(1)
109 #define MSGDMA_CSR_STAT_DESC_BUF_FULL BIT(2)
110 #define MSGDMA_CSR_STAT_RESP_BUF_EMPTY BIT(3)
111 #define MSGDMA_CSR_STAT_RESP_BUF_FULL BIT(4)
112 #define MSGDMA_CSR_STAT_STOPPED BIT(5)
113 #define MSGDMA_CSR_STAT_RESETTING BIT(6)
114 #define MSGDMA_CSR_STAT_STOPPED_ON_ERR BIT(7)
115 #define MSGDMA_CSR_STAT_STOPPED_ON_EARLY BIT(8)
116 #define MSGDMA_CSR_STAT_IRQ BIT(9)
117 #define MSGDMA_CSR_STAT_MASK 0x3FF
118 #define MSGDMA_CSR_STAT_MASK_WITHOUT_IRQ 0x1FF
120 #define MSGDMA_CSR_STAT_BUSY_GET(v) GET_BIT_VALUE(v, 0)
121 #define MSGDMA_CSR_STAT_DESC_BUF_EMPTY_GET(v) GET_BIT_VALUE(v, 1)
122 #define MSGDMA_CSR_STAT_DESC_BUF_FULL_GET(v) GET_BIT_VALUE(v, 2)
123 #define MSGDMA_CSR_STAT_RESP_BUF_EMPTY_GET(v) GET_BIT_VALUE(v, 3)
124 #define MSGDMA_CSR_STAT_RESP_BUF_FULL_GET(v) GET_BIT_VALUE(v, 4)
125 #define MSGDMA_CSR_STAT_STOPPED_GET(v) GET_BIT_VALUE(v, 5)
126 #define MSGDMA_CSR_STAT_RESETTING_GET(v) GET_BIT_VALUE(v, 6)
127 #define MSGDMA_CSR_STAT_STOPPED_ON_ERR_GET(v) GET_BIT_VALUE(v, 7)
128 #define MSGDMA_CSR_STAT_STOPPED_ON_EARLY_GET(v) GET_BIT_VALUE(v, 8)
129 #define MSGDMA_CSR_STAT_IRQ_GET(v) GET_BIT_VALUE(v, 9)
131 /* mSGDMA CSR control register bit definitions
133 #define MSGDMA_CSR_CTL_STOP BIT(0)
134 #define MSGDMA_CSR_CTL_RESET BIT(1)
135 #define MSGDMA_CSR_CTL_STOP_ON_ERR BIT(2)
136 #define MSGDMA_CSR_CTL_STOP_ON_EARLY BIT(3)
137 #define MSGDMA_CSR_CTL_GLOBAL_INTR BIT(4)
138 #define MSGDMA_CSR_CTL_STOP_DESCS BIT(5)
140 /* mSGDMA CSR fill level bits
142 #define MSGDMA_CSR_WR_FILL_LEVEL_GET(v) (((v) & 0xffff0000) >> 16)
143 #define MSGDMA_CSR_RD_FILL_LEVEL_GET(v) ((v) & 0x0000ffff)
144 #define MSGDMA_CSR_RESP_FILL_LEVEL_GET(v) ((v) & 0x0000ffff)
146 /* mSGDMA response register map
148 struct msgdma_response {
149 u32 bytes_transferred;
153 #define msgdma_respoffs(a) (offsetof(struct msgdma_response, a))
154 #define msgdma_csroffs(a) (offsetof(struct msgdma_csr, a))
155 #define msgdma_descroffs(a) (offsetof(struct msgdma_extended_desc, a))
157 /* mSGDMA response register bit definitions
159 #define MSGDMA_RESP_EARLY_TERM BIT(8)
160 #define MSGDMA_RESP_ERR_MASK 0xFF
162 #endif /* __ALTERA_MSGDMA_H__*/