1 /* Altera Triple-Speed Ethernet MAC driver
2 * Copyright (C) 2008-2014 Altera Corporation. All rights reserved
15 * Original driver contributed by SLS.
16 * Major updates contributed by GlobalLogic
18 * This program is free software; you can redistribute it and/or modify it
19 * under the terms and conditions of the GNU General Public License,
20 * version 2, as published by the Free Software Foundation.
22 * This program is distributed in the hope it will be useful, but WITHOUT
23 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
24 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
27 * You should have received a copy of the GNU General Public License along with
28 * this program. If not, see <http://www.gnu.org/licenses/>.
31 #include <linux/atomic.h>
32 #include <linux/delay.h>
33 #include <linux/etherdevice.h>
34 #include <linux/if_vlan.h>
35 #include <linux/init.h>
36 #include <linux/interrupt.h>
38 #include <linux/kernel.h>
39 #include <linux/module.h>
40 #include <linux/netdevice.h>
41 #include <linux/of_device.h>
42 #include <linux/of_mdio.h>
43 #include <linux/of_net.h>
44 #include <linux/of_platform.h>
45 #include <linux/phy.h>
46 #include <linux/platform_device.h>
47 #include <linux/skbuff.h>
48 #include <asm/cacheflush.h>
50 #include "altera_utils.h"
51 #include "altera_tse.h"
52 #include "altera_sgdma.h"
53 #include "altera_msgdma.h"
55 static atomic_t instance_count = ATOMIC_INIT(~0);
56 /* Module parameters */
57 static int debug = -1;
58 module_param(debug, int, S_IRUGO | S_IWUSR);
59 MODULE_PARM_DESC(debug, "Message Level (-1: default, 0: no output, 16: all)");
61 static const u32 default_msg_level = (NETIF_MSG_DRV | NETIF_MSG_PROBE |
62 NETIF_MSG_LINK | NETIF_MSG_IFUP |
65 #define RX_DESCRIPTORS 64
66 static int dma_rx_num = RX_DESCRIPTORS;
67 module_param(dma_rx_num, int, S_IRUGO | S_IWUSR);
68 MODULE_PARM_DESC(dma_rx_num, "Number of descriptors in the RX list");
70 #define TX_DESCRIPTORS 64
71 static int dma_tx_num = TX_DESCRIPTORS;
72 module_param(dma_tx_num, int, S_IRUGO | S_IWUSR);
73 MODULE_PARM_DESC(dma_tx_num, "Number of descriptors in the TX list");
78 /* Make sure DMA buffer size is larger than the max frame size
79 * plus some alignment offset and a VLAN header. If the max frame size is
80 * 1518, a VLAN header would be additional 4 bytes and additional
81 * headroom for alignment is 2 bytes, 2048 is just fine.
83 #define ALTERA_RXDMABUFFER_SIZE 2048
85 /* Allow network stack to resume queueing packets after we've
86 * finished transmitting at least 1/4 of the packets in the queue.
88 #define TSE_TX_THRESH(x) (x->tx_ring_size / 4)
90 #define TXQUEUESTOP_THRESHHOLD 2
92 static struct of_device_id altera_tse_ids[];
94 static inline u32 tse_tx_avail(struct altera_tse_private *priv)
96 return priv->tx_cons + priv->tx_ring_size - priv->tx_prod - 1;
99 /* MDIO specific functions
101 static int altera_tse_mdio_read(struct mii_bus *bus, int mii_id, int regnum)
103 struct net_device *ndev = bus->priv;
104 struct altera_tse_private *priv = netdev_priv(ndev);
106 /* set MDIO address */
107 csrwr32((mii_id & 0x1f), priv->mac_dev,
108 tse_csroffs(mdio_phy1_addr));
111 return csrrd32(priv->mac_dev,
112 tse_csroffs(mdio_phy1) + regnum * 4) & 0xffff;
115 static int altera_tse_mdio_write(struct mii_bus *bus, int mii_id, int regnum,
118 struct net_device *ndev = bus->priv;
119 struct altera_tse_private *priv = netdev_priv(ndev);
121 /* set MDIO address */
122 csrwr32((mii_id & 0x1f), priv->mac_dev,
123 tse_csroffs(mdio_phy1_addr));
126 csrwr32(value, priv->mac_dev, tse_csroffs(mdio_phy1) + regnum * 4);
130 static int altera_tse_mdio_create(struct net_device *dev, unsigned int id)
132 struct altera_tse_private *priv = netdev_priv(dev);
135 struct device_node *mdio_node = NULL;
136 struct mii_bus *mdio = NULL;
137 struct device_node *child_node = NULL;
139 for_each_child_of_node(priv->device->of_node, child_node) {
140 if (of_device_is_compatible(child_node, "altr,tse-mdio")) {
141 mdio_node = child_node;
147 netdev_dbg(dev, "FOUND MDIO subnode\n");
149 netdev_dbg(dev, "NO MDIO subnode\n");
153 mdio = mdiobus_alloc();
155 netdev_err(dev, "Error allocating MDIO bus\n");
159 mdio->name = ALTERA_TSE_RESOURCE_NAME;
160 mdio->read = &altera_tse_mdio_read;
161 mdio->write = &altera_tse_mdio_write;
162 snprintf(mdio->id, MII_BUS_ID_SIZE, "%s-%u", mdio->name, id);
164 mdio->irq = kcalloc(PHY_MAX_ADDR, sizeof(int), GFP_KERNEL);
165 if (mdio->irq == NULL) {
169 for (i = 0; i < PHY_MAX_ADDR; i++)
170 mdio->irq[i] = PHY_POLL;
173 mdio->parent = priv->device;
175 ret = of_mdiobus_register(mdio, mdio_node);
177 netdev_err(dev, "Cannot register MDIO bus %s\n",
179 goto out_free_mdio_irq;
182 if (netif_msg_drv(priv))
183 netdev_info(dev, "MDIO bus %s: created\n", mdio->id);
195 static void altera_tse_mdio_destroy(struct net_device *dev)
197 struct altera_tse_private *priv = netdev_priv(dev);
199 if (priv->mdio == NULL)
202 if (netif_msg_drv(priv))
203 netdev_info(dev, "MDIO bus %s: removed\n",
206 mdiobus_unregister(priv->mdio);
207 kfree(priv->mdio->irq);
208 mdiobus_free(priv->mdio);
212 static int tse_init_rx_buffer(struct altera_tse_private *priv,
213 struct tse_buffer *rxbuffer, int len)
215 rxbuffer->skb = netdev_alloc_skb_ip_align(priv->dev, len);
219 rxbuffer->dma_addr = dma_map_single(priv->device, rxbuffer->skb->data,
223 if (dma_mapping_error(priv->device, rxbuffer->dma_addr)) {
224 netdev_err(priv->dev, "%s: DMA mapping error\n", __func__);
225 dev_kfree_skb_any(rxbuffer->skb);
228 rxbuffer->dma_addr &= (dma_addr_t)~3;
233 static void tse_free_rx_buffer(struct altera_tse_private *priv,
234 struct tse_buffer *rxbuffer)
236 struct sk_buff *skb = rxbuffer->skb;
237 dma_addr_t dma_addr = rxbuffer->dma_addr;
241 dma_unmap_single(priv->device, dma_addr,
244 dev_kfree_skb_any(skb);
245 rxbuffer->skb = NULL;
246 rxbuffer->dma_addr = 0;
250 /* Unmap and free Tx buffer resources
252 static void tse_free_tx_buffer(struct altera_tse_private *priv,
253 struct tse_buffer *buffer)
255 if (buffer->dma_addr) {
256 if (buffer->mapped_as_page)
257 dma_unmap_page(priv->device, buffer->dma_addr,
258 buffer->len, DMA_TO_DEVICE);
260 dma_unmap_single(priv->device, buffer->dma_addr,
261 buffer->len, DMA_TO_DEVICE);
262 buffer->dma_addr = 0;
265 dev_kfree_skb_any(buffer->skb);
270 static int alloc_init_skbufs(struct altera_tse_private *priv)
272 unsigned int rx_descs = priv->rx_ring_size;
273 unsigned int tx_descs = priv->tx_ring_size;
277 /* Create Rx ring buffer */
278 priv->rx_ring = kcalloc(rx_descs, sizeof(struct tse_buffer),
283 /* Create Tx ring buffer */
284 priv->tx_ring = kcalloc(tx_descs, sizeof(struct tse_buffer),
293 for (i = 0; i < rx_descs; i++) {
294 ret = tse_init_rx_buffer(priv, &priv->rx_ring[i],
295 priv->rx_dma_buf_sz);
297 goto err_init_rx_buffers;
306 tse_free_rx_buffer(priv, &priv->rx_ring[i]);
307 kfree(priv->tx_ring);
309 kfree(priv->rx_ring);
314 static void free_skbufs(struct net_device *dev)
316 struct altera_tse_private *priv = netdev_priv(dev);
317 unsigned int rx_descs = priv->rx_ring_size;
318 unsigned int tx_descs = priv->tx_ring_size;
321 /* Release the DMA TX/RX socket buffers */
322 for (i = 0; i < rx_descs; i++)
323 tse_free_rx_buffer(priv, &priv->rx_ring[i]);
324 for (i = 0; i < tx_descs; i++)
325 tse_free_tx_buffer(priv, &priv->tx_ring[i]);
328 kfree(priv->tx_ring);
331 /* Reallocate the skb for the reception process
333 static inline void tse_rx_refill(struct altera_tse_private *priv)
335 unsigned int rxsize = priv->rx_ring_size;
339 for (; priv->rx_cons - priv->rx_prod > 0;
341 entry = priv->rx_prod % rxsize;
342 if (likely(priv->rx_ring[entry].skb == NULL)) {
343 ret = tse_init_rx_buffer(priv, &priv->rx_ring[entry],
344 priv->rx_dma_buf_sz);
345 if (unlikely(ret != 0))
347 priv->dmaops->add_rx_desc(priv, &priv->rx_ring[entry]);
352 /* Pull out the VLAN tag and fix up the packet
354 static inline void tse_rx_vlan(struct net_device *dev, struct sk_buff *skb)
356 struct ethhdr *eth_hdr;
358 if ((dev->features & NETIF_F_HW_VLAN_CTAG_RX) &&
359 !__vlan_get_tag(skb, &vid)) {
360 eth_hdr = (struct ethhdr *)skb->data;
361 memmove(skb->data + VLAN_HLEN, eth_hdr, ETH_ALEN * 2);
362 skb_pull(skb, VLAN_HLEN);
363 __vlan_hwaccel_put_tag(skb, htons(ETH_P_8021Q), vid);
367 /* Receive a packet: retrieve and pass over to upper levels
369 static int tse_rx(struct altera_tse_private *priv, int limit)
371 unsigned int count = 0;
372 unsigned int next_entry;
374 unsigned int entry = priv->rx_cons % priv->rx_ring_size;
379 while (((rxstatus = priv->dmaops->get_rx_status(priv)) != 0) &&
381 pktstatus = rxstatus >> 16;
382 pktlength = rxstatus & 0xffff;
384 if ((pktstatus & 0xFF) || (pktlength == 0))
385 netdev_err(priv->dev,
386 "RCV pktstatus %08X pktlength %08X\n",
387 pktstatus, pktlength);
390 next_entry = (++priv->rx_cons) % priv->rx_ring_size;
392 skb = priv->rx_ring[entry].skb;
393 if (unlikely(!skb)) {
394 netdev_err(priv->dev,
395 "%s: Inconsistent Rx descriptor chain\n",
397 priv->dev->stats.rx_dropped++;
400 priv->rx_ring[entry].skb = NULL;
402 skb_put(skb, pktlength);
404 /* make cache consistent with receive packet buffer */
405 dma_sync_single_for_cpu(priv->device,
406 priv->rx_ring[entry].dma_addr,
407 priv->rx_ring[entry].len,
410 dma_unmap_single(priv->device, priv->rx_ring[entry].dma_addr,
411 priv->rx_ring[entry].len, DMA_FROM_DEVICE);
413 if (netif_msg_pktdata(priv)) {
414 netdev_info(priv->dev, "frame received %d bytes\n",
416 print_hex_dump(KERN_ERR, "data: ", DUMP_PREFIX_OFFSET,
417 16, 1, skb->data, pktlength, true);
420 tse_rx_vlan(priv->dev, skb);
422 skb->protocol = eth_type_trans(skb, priv->dev);
423 skb_checksum_none_assert(skb);
425 napi_gro_receive(&priv->napi, skb);
427 priv->dev->stats.rx_packets++;
428 priv->dev->stats.rx_bytes += pktlength;
438 /* Reclaim resources after transmission completes
440 static int tse_tx_complete(struct altera_tse_private *priv)
442 unsigned int txsize = priv->tx_ring_size;
445 struct tse_buffer *tx_buff;
448 spin_lock(&priv->tx_lock);
450 ready = priv->dmaops->tx_completions(priv);
452 /* Free sent buffers */
453 while (ready && (priv->tx_cons != priv->tx_prod)) {
454 entry = priv->tx_cons % txsize;
455 tx_buff = &priv->tx_ring[entry];
457 if (netif_msg_tx_done(priv))
458 netdev_dbg(priv->dev, "%s: curr %d, dirty %d\n",
459 __func__, priv->tx_prod, priv->tx_cons);
461 if (likely(tx_buff->skb))
462 priv->dev->stats.tx_packets++;
464 tse_free_tx_buffer(priv, tx_buff);
471 if (unlikely(netif_queue_stopped(priv->dev) &&
472 tse_tx_avail(priv) > TSE_TX_THRESH(priv))) {
473 netif_tx_lock(priv->dev);
474 if (netif_queue_stopped(priv->dev) &&
475 tse_tx_avail(priv) > TSE_TX_THRESH(priv)) {
476 if (netif_msg_tx_done(priv))
477 netdev_dbg(priv->dev, "%s: restart transmit\n",
479 netif_wake_queue(priv->dev);
481 netif_tx_unlock(priv->dev);
484 spin_unlock(&priv->tx_lock);
488 /* NAPI polling function
490 static int tse_poll(struct napi_struct *napi, int budget)
492 struct altera_tse_private *priv =
493 container_of(napi, struct altera_tse_private, napi);
495 unsigned long int flags;
497 tse_tx_complete(priv);
499 rxcomplete = tse_rx(priv, budget);
501 if (rxcomplete < budget) {
503 napi_gro_flush(napi, false);
504 __napi_complete(napi);
506 netdev_dbg(priv->dev,
507 "NAPI Complete, did %d packets with budget %d\n",
510 spin_lock_irqsave(&priv->rxdma_irq_lock, flags);
511 priv->dmaops->enable_rxirq(priv);
512 priv->dmaops->enable_txirq(priv);
513 spin_unlock_irqrestore(&priv->rxdma_irq_lock, flags);
518 /* DMA TX & RX FIFO interrupt routing
520 static irqreturn_t altera_isr(int irq, void *dev_id)
522 struct net_device *dev = dev_id;
523 struct altera_tse_private *priv;
525 if (unlikely(!dev)) {
526 pr_err("%s: invalid dev pointer\n", __func__);
529 priv = netdev_priv(dev);
531 spin_lock(&priv->rxdma_irq_lock);
533 priv->dmaops->clear_rxirq(priv);
534 priv->dmaops->clear_txirq(priv);
535 spin_unlock(&priv->rxdma_irq_lock);
537 if (likely(napi_schedule_prep(&priv->napi))) {
538 spin_lock(&priv->rxdma_irq_lock);
539 priv->dmaops->disable_rxirq(priv);
540 priv->dmaops->disable_txirq(priv);
541 spin_unlock(&priv->rxdma_irq_lock);
542 __napi_schedule(&priv->napi);
549 /* Transmit a packet (called by the kernel). Dispatches
550 * either the SGDMA method for transmitting or the
551 * MSGDMA method, assumes no scatter/gather support,
552 * implying an assumption that there's only one
553 * physically contiguous fragment starting at
554 * skb->data, for length of skb_headlen(skb).
556 static int tse_start_xmit(struct sk_buff *skb, struct net_device *dev)
558 struct altera_tse_private *priv = netdev_priv(dev);
559 unsigned int txsize = priv->tx_ring_size;
561 struct tse_buffer *buffer = NULL;
562 int nfrags = skb_shinfo(skb)->nr_frags;
563 unsigned int nopaged_len = skb_headlen(skb);
564 enum netdev_tx ret = NETDEV_TX_OK;
567 spin_lock_bh(&priv->tx_lock);
569 if (unlikely(tse_tx_avail(priv) < nfrags + 1)) {
570 if (!netif_queue_stopped(dev)) {
571 netif_stop_queue(dev);
572 /* This is a hard error, log it. */
573 netdev_err(priv->dev,
574 "%s: Tx list full when queue awake\n",
577 ret = NETDEV_TX_BUSY;
581 /* Map the first skb fragment */
582 entry = priv->tx_prod % txsize;
583 buffer = &priv->tx_ring[entry];
585 dma_addr = dma_map_single(priv->device, skb->data, nopaged_len,
587 if (dma_mapping_error(priv->device, dma_addr)) {
588 netdev_err(priv->dev, "%s: DMA mapping error\n", __func__);
594 buffer->dma_addr = dma_addr;
595 buffer->len = nopaged_len;
597 /* Push data out of the cache hierarchy into main memory */
598 dma_sync_single_for_device(priv->device, buffer->dma_addr,
599 buffer->len, DMA_TO_DEVICE);
601 priv->dmaops->tx_buffer(priv, buffer);
603 skb_tx_timestamp(skb);
606 dev->stats.tx_bytes += skb->len;
608 if (unlikely(tse_tx_avail(priv) <= TXQUEUESTOP_THRESHHOLD)) {
609 if (netif_msg_hw(priv))
610 netdev_dbg(priv->dev, "%s: stop transmitted packets\n",
612 netif_stop_queue(dev);
616 spin_unlock_bh(&priv->tx_lock);
621 /* Called every time the controller might need to be made
622 * aware of new link state. The PHY code conveys this
623 * information through variables in the phydev structure, and this
624 * function converts those variables into the appropriate
625 * register values, and can bring down the device if needed.
627 static void altera_tse_adjust_link(struct net_device *dev)
629 struct altera_tse_private *priv = netdev_priv(dev);
630 struct phy_device *phydev = priv->phydev;
633 /* only change config if there is a link */
634 spin_lock(&priv->mac_cfg_lock);
636 /* Read old config */
637 u32 cfg_reg = ioread32(&priv->mac_dev->command_config);
640 if (phydev->duplex != priv->oldduplex) {
642 if (!(phydev->duplex))
643 cfg_reg |= MAC_CMDCFG_HD_ENA;
645 cfg_reg &= ~MAC_CMDCFG_HD_ENA;
647 netdev_dbg(priv->dev, "%s: Link duplex = 0x%x\n",
648 dev->name, phydev->duplex);
650 priv->oldduplex = phydev->duplex;
654 if (phydev->speed != priv->oldspeed) {
656 switch (phydev->speed) {
658 cfg_reg |= MAC_CMDCFG_ETH_SPEED;
659 cfg_reg &= ~MAC_CMDCFG_ENA_10;
662 cfg_reg &= ~MAC_CMDCFG_ETH_SPEED;
663 cfg_reg &= ~MAC_CMDCFG_ENA_10;
666 cfg_reg &= ~MAC_CMDCFG_ETH_SPEED;
667 cfg_reg |= MAC_CMDCFG_ENA_10;
670 if (netif_msg_link(priv))
671 netdev_warn(dev, "Speed (%d) is not 10/100/1000!\n",
675 priv->oldspeed = phydev->speed;
677 iowrite32(cfg_reg, &priv->mac_dev->command_config);
679 if (!priv->oldlink) {
683 } else if (priv->oldlink) {
687 priv->oldduplex = -1;
690 if (new_state && netif_msg_link(priv))
691 phy_print_status(phydev);
693 spin_unlock(&priv->mac_cfg_lock);
695 static struct phy_device *connect_local_phy(struct net_device *dev)
697 struct altera_tse_private *priv = netdev_priv(dev);
698 struct phy_device *phydev = NULL;
699 char phy_id_fmt[MII_BUS_ID_SIZE + 3];
701 if (priv->phy_addr != POLL_PHY) {
702 snprintf(phy_id_fmt, MII_BUS_ID_SIZE + 3, PHY_ID_FMT,
703 priv->mdio->id, priv->phy_addr);
705 netdev_dbg(dev, "trying to attach to %s\n", phy_id_fmt);
707 phydev = phy_connect(dev, phy_id_fmt, &altera_tse_adjust_link,
710 netdev_err(dev, "Could not attach to PHY\n");
714 phydev = phy_find_first(priv->mdio);
715 if (phydev == NULL) {
716 netdev_err(dev, "No PHY found\n");
720 ret = phy_connect_direct(dev, phydev, &altera_tse_adjust_link,
723 netdev_err(dev, "Could not attach to PHY\n");
730 static int altera_tse_phy_get_addr_mdio_create(struct net_device *dev)
732 struct altera_tse_private *priv = netdev_priv(dev);
733 struct device_node *np = priv->device->of_node;
736 priv->phy_iface = of_get_phy_mode(np);
738 /* Avoid get phy addr and create mdio if no phy is present */
739 if (!priv->phy_iface)
742 /* try to get PHY address from device tree, use PHY autodetection if
743 * no valid address is given
746 if (of_property_read_u32(priv->device->of_node, "phy-addr",
748 priv->phy_addr = POLL_PHY;
751 if (!((priv->phy_addr == POLL_PHY) ||
752 ((priv->phy_addr >= 0) && (priv->phy_addr < PHY_MAX_ADDR)))) {
753 netdev_err(dev, "invalid phy-addr specified %d\n",
758 /* Create/attach to MDIO bus */
759 ret = altera_tse_mdio_create(dev,
760 atomic_add_return(1, &instance_count));
768 /* Initialize driver's PHY state, and attach to the PHY
770 static int init_phy(struct net_device *dev)
772 struct altera_tse_private *priv = netdev_priv(dev);
773 struct phy_device *phydev;
774 struct device_node *phynode;
776 /* Avoid init phy in case of no phy present */
777 if (!priv->phy_iface)
782 priv->oldduplex = -1;
784 phynode = of_parse_phandle(priv->device->of_node, "phy-handle", 0);
787 netdev_dbg(dev, "no phy-handle found\n");
790 "No phy-handle nor local mdio specified\n");
793 phydev = connect_local_phy(dev);
795 netdev_dbg(dev, "phy-handle found\n");
796 phydev = of_phy_connect(dev, phynode,
797 &altera_tse_adjust_link, 0, priv->phy_iface);
801 netdev_err(dev, "Could not find the PHY\n");
805 /* Stop Advertising 1000BASE Capability if interface is not GMII
806 * Note: Checkpatch throws CHECKs for the camel case defines below,
809 if ((priv->phy_iface == PHY_INTERFACE_MODE_MII) ||
810 (priv->phy_iface == PHY_INTERFACE_MODE_RMII))
811 phydev->advertising &= ~(SUPPORTED_1000baseT_Half |
812 SUPPORTED_1000baseT_Full);
814 /* Broken HW is sometimes missing the pull-up resistor on the
815 * MDIO line, which results in reads to non-existent devices returning
816 * 0 rather than 0xffff. Catch this here and treat 0 as a non-existent
818 * Note: phydev->phy_id is the result of reading the UID PHY registers.
820 if (phydev->phy_id == 0) {
821 netdev_err(dev, "Bad PHY UID 0x%08x\n", phydev->phy_id);
822 phy_disconnect(phydev);
826 netdev_dbg(dev, "attached to PHY %d UID 0x%08x Link = %d\n",
827 phydev->addr, phydev->phy_id, phydev->link);
829 priv->phydev = phydev;
833 static void tse_update_mac_addr(struct altera_tse_private *priv, u8 *addr)
838 msb = (addr[3] << 24) | (addr[2] << 16) | (addr[1] << 8) | addr[0];
839 lsb = ((addr[5] << 8) | addr[4]) & 0xffff;
841 /* Set primary MAC address */
842 csrwr32(msb, priv->mac_dev, tse_csroffs(mac_addr_0));
843 csrwr32(lsb, priv->mac_dev, tse_csroffs(mac_addr_1));
846 /* MAC software reset.
847 * When reset is triggered, the MAC function completes the current
848 * transmission or reception, and subsequently disables the transmit and
849 * receive logic, flushes the receive FIFO buffer, and resets the statistics
852 static int reset_mac(struct altera_tse_private *priv)
857 dat = csrrd32(priv->mac_dev, tse_csroffs(command_config));
858 dat &= ~(MAC_CMDCFG_TX_ENA | MAC_CMDCFG_RX_ENA);
859 dat |= MAC_CMDCFG_SW_RESET | MAC_CMDCFG_CNT_RESET;
860 csrwr32(dat, priv->mac_dev, tse_csroffs(command_config));
863 while (counter++ < ALTERA_TSE_SW_RESET_WATCHDOG_CNTR) {
864 if (tse_bit_is_clear(priv->mac_dev, tse_csroffs(command_config),
865 MAC_CMDCFG_SW_RESET))
870 if (counter >= ALTERA_TSE_SW_RESET_WATCHDOG_CNTR) {
871 dat = csrrd32(priv->mac_dev, tse_csroffs(command_config));
872 dat &= ~MAC_CMDCFG_SW_RESET;
873 csrwr32(dat, priv->mac_dev, tse_csroffs(command_config));
879 /* Initialize MAC core registers
881 static int init_mac(struct altera_tse_private *priv)
883 unsigned int cmd = 0;
887 csrwr32(priv->rx_fifo_depth - ALTERA_TSE_RX_SECTION_EMPTY,
888 priv->mac_dev, tse_csroffs(rx_section_empty));
890 csrwr32(ALTERA_TSE_RX_SECTION_FULL, priv->mac_dev,
891 tse_csroffs(rx_section_full));
893 csrwr32(ALTERA_TSE_RX_ALMOST_EMPTY, priv->mac_dev,
894 tse_csroffs(rx_almost_empty));
896 csrwr32(ALTERA_TSE_RX_ALMOST_FULL, priv->mac_dev,
897 tse_csroffs(rx_almost_full));
900 csrwr32(priv->tx_fifo_depth - ALTERA_TSE_TX_SECTION_EMPTY,
901 priv->mac_dev, tse_csroffs(tx_section_empty));
903 csrwr32(ALTERA_TSE_TX_SECTION_FULL, priv->mac_dev,
904 tse_csroffs(tx_section_full));
906 csrwr32(ALTERA_TSE_TX_ALMOST_EMPTY, priv->mac_dev,
907 tse_csroffs(tx_almost_empty));
909 csrwr32(ALTERA_TSE_TX_ALMOST_FULL, priv->mac_dev,
910 tse_csroffs(tx_almost_full));
912 /* MAC Address Configuration */
913 tse_update_mac_addr(priv, priv->dev->dev_addr);
915 /* MAC Function Configuration */
916 frm_length = ETH_HLEN + priv->dev->mtu + ETH_FCS_LEN;
917 csrwr32(frm_length, priv->mac_dev, tse_csroffs(frm_length));
919 csrwr32(ALTERA_TSE_TX_IPG_LENGTH, priv->mac_dev,
920 tse_csroffs(tx_ipg_length));
922 /* Disable RX/TX shift 16 for alignment of all received frames on 16-bit
925 tse_set_bit(priv->mac_dev, tse_csroffs(rx_cmd_stat),
926 ALTERA_TSE_RX_CMD_STAT_RX_SHIFT16);
928 tse_clear_bit(priv->mac_dev, tse_csroffs(tx_cmd_stat),
929 ALTERA_TSE_TX_CMD_STAT_TX_SHIFT16 |
930 ALTERA_TSE_TX_CMD_STAT_OMIT_CRC);
932 /* Set the MAC options */
933 cmd = csrrd32(priv->mac_dev, tse_csroffs(command_config));
934 cmd &= ~MAC_CMDCFG_PAD_EN; /* No padding Removal on Receive */
935 cmd &= ~MAC_CMDCFG_CRC_FWD; /* CRC Removal */
936 cmd |= MAC_CMDCFG_RX_ERR_DISC; /* Automatically discard frames
939 cmd |= MAC_CMDCFG_CNTL_FRM_ENA;
940 cmd &= ~MAC_CMDCFG_TX_ENA;
941 cmd &= ~MAC_CMDCFG_RX_ENA;
943 /* Default speed and duplex setting, full/100 */
944 cmd &= ~MAC_CMDCFG_HD_ENA;
945 cmd &= ~MAC_CMDCFG_ETH_SPEED;
946 cmd &= ~MAC_CMDCFG_ENA_10;
948 csrwr32(cmd, priv->mac_dev, tse_csroffs(command_config));
950 csrwr32(ALTERA_TSE_PAUSE_QUANTA, priv->mac_dev,
951 tse_csroffs(pause_quanta));
953 if (netif_msg_hw(priv))
954 dev_dbg(priv->device,
955 "MAC post-initialization: CMD_CONFIG = 0x%08x\n", cmd);
960 /* Start/stop MAC transmission logic
962 static void tse_set_mac(struct altera_tse_private *priv, bool enable)
964 u32 value = csrrd32(priv->mac_dev, tse_csroffs(command_config));
967 value |= MAC_CMDCFG_TX_ENA | MAC_CMDCFG_RX_ENA;
969 value &= ~(MAC_CMDCFG_TX_ENA | MAC_CMDCFG_RX_ENA);
971 csrwr32(value, priv->mac_dev, tse_csroffs(command_config));
976 static int tse_change_mtu(struct net_device *dev, int new_mtu)
978 struct altera_tse_private *priv = netdev_priv(dev);
979 unsigned int max_mtu = priv->max_mtu;
980 unsigned int min_mtu = ETH_ZLEN + ETH_FCS_LEN;
982 if (netif_running(dev)) {
983 netdev_err(dev, "must be stopped to change its MTU\n");
987 if ((new_mtu < min_mtu) || (new_mtu > max_mtu)) {
988 netdev_err(dev, "invalid MTU, max MTU is: %u\n", max_mtu);
993 netdev_update_features(dev);
998 static void altera_tse_set_mcfilter(struct net_device *dev)
1000 struct altera_tse_private *priv = netdev_priv(dev);
1002 struct netdev_hw_addr *ha;
1004 /* clear the hash filter */
1005 for (i = 0; i < 64; i++)
1006 csrwr32(0, priv->mac_dev, tse_csroffs(hash_table) + i * 4);
1008 netdev_for_each_mc_addr(ha, dev) {
1009 unsigned int hash = 0;
1012 for (mac_octet = 5; mac_octet >= 0; mac_octet--) {
1013 unsigned char xor_bit = 0;
1014 unsigned char octet = ha->addr[mac_octet];
1015 unsigned int bitshift;
1017 for (bitshift = 0; bitshift < 8; bitshift++)
1018 xor_bit ^= ((octet >> bitshift) & 0x01);
1020 hash = (hash << 1) | xor_bit;
1022 csrwr32(1, priv->mac_dev, tse_csroffs(hash_table) + hash * 4);
1027 static void altera_tse_set_mcfilterall(struct net_device *dev)
1029 struct altera_tse_private *priv = netdev_priv(dev);
1032 /* set the hash filter */
1033 for (i = 0; i < 64; i++)
1034 csrwr32(1, priv->mac_dev, tse_csroffs(hash_table) + i * 4);
1037 /* Set or clear the multicast filter for this adaptor
1039 static void tse_set_rx_mode_hashfilter(struct net_device *dev)
1041 struct altera_tse_private *priv = netdev_priv(dev);
1043 spin_lock(&priv->mac_cfg_lock);
1045 if (dev->flags & IFF_PROMISC)
1046 tse_set_bit(priv->mac_dev, tse_csroffs(command_config),
1047 MAC_CMDCFG_PROMIS_EN);
1049 if (dev->flags & IFF_ALLMULTI)
1050 altera_tse_set_mcfilterall(dev);
1052 altera_tse_set_mcfilter(dev);
1054 spin_unlock(&priv->mac_cfg_lock);
1057 /* Set or clear the multicast filter for this adaptor
1059 static void tse_set_rx_mode(struct net_device *dev)
1061 struct altera_tse_private *priv = netdev_priv(dev);
1063 spin_lock(&priv->mac_cfg_lock);
1065 if ((dev->flags & IFF_PROMISC) || (dev->flags & IFF_ALLMULTI) ||
1066 !netdev_mc_empty(dev) || !netdev_uc_empty(dev))
1067 tse_set_bit(priv->mac_dev, tse_csroffs(command_config),
1068 MAC_CMDCFG_PROMIS_EN);
1070 tse_clear_bit(priv->mac_dev, tse_csroffs(command_config),
1071 MAC_CMDCFG_PROMIS_EN);
1073 spin_unlock(&priv->mac_cfg_lock);
1076 /* Open and initialize the interface
1078 static int tse_open(struct net_device *dev)
1080 struct altera_tse_private *priv = netdev_priv(dev);
1083 unsigned long int flags;
1085 /* Reset and configure TSE MAC and probe associated PHY */
1086 ret = priv->dmaops->init_dma(priv);
1088 netdev_err(dev, "Cannot initialize DMA\n");
1092 if (netif_msg_ifup(priv))
1093 netdev_warn(dev, "device MAC address %pM\n",
1096 if ((priv->revision < 0xd00) || (priv->revision > 0xe00))
1097 netdev_warn(dev, "TSE revision %x\n", priv->revision);
1099 spin_lock(&priv->mac_cfg_lock);
1100 ret = reset_mac(priv);
1101 /* Note that reset_mac will fail if the clocks are gated by the PHY
1102 * due to the PHY being put into isolation or power down mode.
1103 * This is not an error if reset fails due to no clock.
1106 netdev_dbg(dev, "Cannot reset MAC core (error: %d)\n", ret);
1108 ret = init_mac(priv);
1109 spin_unlock(&priv->mac_cfg_lock);
1111 netdev_err(dev, "Cannot init MAC core (error: %d)\n", ret);
1112 goto alloc_skbuf_error;
1115 priv->dmaops->reset_dma(priv);
1117 /* Create and initialize the TX/RX descriptors chains. */
1118 priv->rx_ring_size = dma_rx_num;
1119 priv->tx_ring_size = dma_tx_num;
1120 ret = alloc_init_skbufs(priv);
1122 netdev_err(dev, "DMA descriptors initialization failed\n");
1123 goto alloc_skbuf_error;
1127 /* Register RX interrupt */
1128 ret = request_irq(priv->rx_irq, altera_isr, IRQF_SHARED,
1131 netdev_err(dev, "Unable to register RX interrupt %d\n",
1136 /* Register TX interrupt */
1137 ret = request_irq(priv->tx_irq, altera_isr, IRQF_SHARED,
1140 netdev_err(dev, "Unable to register TX interrupt %d\n",
1142 goto tx_request_irq_error;
1145 /* Enable DMA interrupts */
1146 spin_lock_irqsave(&priv->rxdma_irq_lock, flags);
1147 priv->dmaops->enable_rxirq(priv);
1148 priv->dmaops->enable_txirq(priv);
1150 /* Setup RX descriptor chain */
1151 for (i = 0; i < priv->rx_ring_size; i++)
1152 priv->dmaops->add_rx_desc(priv, &priv->rx_ring[i]);
1154 spin_unlock_irqrestore(&priv->rxdma_irq_lock, flags);
1157 phy_start(priv->phydev);
1159 napi_enable(&priv->napi);
1160 netif_start_queue(dev);
1162 priv->dmaops->start_rxdma(priv);
1164 /* Start MAC Rx/Tx */
1165 spin_lock(&priv->mac_cfg_lock);
1166 tse_set_mac(priv, true);
1167 spin_unlock(&priv->mac_cfg_lock);
1171 tx_request_irq_error:
1172 free_irq(priv->rx_irq, dev);
1180 /* Stop TSE MAC interface and put the device in an inactive state
1182 static int tse_shutdown(struct net_device *dev)
1184 struct altera_tse_private *priv = netdev_priv(dev);
1186 unsigned long int flags;
1190 phy_stop(priv->phydev);
1192 netif_stop_queue(dev);
1193 napi_disable(&priv->napi);
1195 /* Disable DMA interrupts */
1196 spin_lock_irqsave(&priv->rxdma_irq_lock, flags);
1197 priv->dmaops->disable_rxirq(priv);
1198 priv->dmaops->disable_txirq(priv);
1199 spin_unlock_irqrestore(&priv->rxdma_irq_lock, flags);
1201 /* Free the IRQ lines */
1202 free_irq(priv->rx_irq, dev);
1203 free_irq(priv->tx_irq, dev);
1205 /* disable and reset the MAC, empties fifo */
1206 spin_lock(&priv->mac_cfg_lock);
1207 spin_lock(&priv->tx_lock);
1209 ret = reset_mac(priv);
1210 /* Note that reset_mac will fail if the clocks are gated by the PHY
1211 * due to the PHY being put into isolation or power down mode.
1212 * This is not an error if reset fails due to no clock.
1215 netdev_dbg(dev, "Cannot reset MAC core (error: %d)\n", ret);
1216 priv->dmaops->reset_dma(priv);
1219 spin_unlock(&priv->tx_lock);
1220 spin_unlock(&priv->mac_cfg_lock);
1222 priv->dmaops->uninit_dma(priv);
1227 static struct net_device_ops altera_tse_netdev_ops = {
1228 .ndo_open = tse_open,
1229 .ndo_stop = tse_shutdown,
1230 .ndo_start_xmit = tse_start_xmit,
1231 .ndo_set_mac_address = eth_mac_addr,
1232 .ndo_set_rx_mode = tse_set_rx_mode,
1233 .ndo_change_mtu = tse_change_mtu,
1234 .ndo_validate_addr = eth_validate_addr,
1237 static int request_and_map(struct platform_device *pdev, const char *name,
1238 struct resource **res, void __iomem **ptr)
1240 struct resource *region;
1241 struct device *device = &pdev->dev;
1243 *res = platform_get_resource_byname(pdev, IORESOURCE_MEM, name);
1245 dev_err(device, "resource %s not defined\n", name);
1249 region = devm_request_mem_region(device, (*res)->start,
1250 resource_size(*res), dev_name(device));
1251 if (region == NULL) {
1252 dev_err(device, "unable to request %s\n", name);
1256 *ptr = devm_ioremap_nocache(device, region->start,
1257 resource_size(region));
1259 dev_err(device, "ioremap_nocache of %s failed!", name);
1266 /* Probe Altera TSE MAC device
1268 static int altera_tse_probe(struct platform_device *pdev)
1270 struct net_device *ndev;
1272 struct resource *control_port;
1273 struct resource *dma_res;
1274 struct altera_tse_private *priv;
1275 const unsigned char *macaddr;
1276 void __iomem *descmap;
1277 const struct of_device_id *of_id = NULL;
1279 ndev = alloc_etherdev(sizeof(struct altera_tse_private));
1281 dev_err(&pdev->dev, "Could not allocate network device\n");
1285 SET_NETDEV_DEV(ndev, &pdev->dev);
1287 priv = netdev_priv(ndev);
1288 priv->device = &pdev->dev;
1290 priv->msg_enable = netif_msg_init(debug, default_msg_level);
1292 of_id = of_match_device(altera_tse_ids, &pdev->dev);
1295 priv->dmaops = (struct altera_dmaops *)of_id->data;
1299 priv->dmaops->altera_dtype == ALTERA_DTYPE_SGDMA) {
1300 /* Get the mapped address to the SGDMA descriptor memory */
1301 ret = request_and_map(pdev, "s1", &dma_res, &descmap);
1303 goto err_free_netdev;
1305 /* Start of that memory is for transmit descriptors */
1306 priv->tx_dma_desc = descmap;
1308 /* First half is for tx descriptors, other half for tx */
1309 priv->txdescmem = resource_size(dma_res)/2;
1311 priv->txdescmem_busaddr = (dma_addr_t)dma_res->start;
1313 priv->rx_dma_desc = (void __iomem *)((uintptr_t)(descmap +
1315 priv->rxdescmem = resource_size(dma_res)/2;
1316 priv->rxdescmem_busaddr = dma_res->start;
1317 priv->rxdescmem_busaddr += priv->txdescmem;
1319 if (upper_32_bits(priv->rxdescmem_busaddr)) {
1320 dev_dbg(priv->device,
1321 "SGDMA bus addresses greater than 32-bits\n");
1322 goto err_free_netdev;
1324 if (upper_32_bits(priv->txdescmem_busaddr)) {
1325 dev_dbg(priv->device,
1326 "SGDMA bus addresses greater than 32-bits\n");
1327 goto err_free_netdev;
1329 } else if (priv->dmaops &&
1330 priv->dmaops->altera_dtype == ALTERA_DTYPE_MSGDMA) {
1331 ret = request_and_map(pdev, "rx_resp", &dma_res,
1332 &priv->rx_dma_resp);
1334 goto err_free_netdev;
1336 ret = request_and_map(pdev, "tx_desc", &dma_res,
1337 &priv->tx_dma_desc);
1339 goto err_free_netdev;
1341 priv->txdescmem = resource_size(dma_res);
1342 priv->txdescmem_busaddr = dma_res->start;
1344 ret = request_and_map(pdev, "rx_desc", &dma_res,
1345 &priv->rx_dma_desc);
1347 goto err_free_netdev;
1349 priv->rxdescmem = resource_size(dma_res);
1350 priv->rxdescmem_busaddr = dma_res->start;
1353 goto err_free_netdev;
1356 if (!dma_set_mask(priv->device, DMA_BIT_MASK(priv->dmaops->dmamask)))
1357 dma_set_coherent_mask(priv->device,
1358 DMA_BIT_MASK(priv->dmaops->dmamask));
1359 else if (!dma_set_mask(priv->device, DMA_BIT_MASK(32)))
1360 dma_set_coherent_mask(priv->device, DMA_BIT_MASK(32));
1362 goto err_free_netdev;
1364 /* MAC address space */
1365 ret = request_and_map(pdev, "control_port", &control_port,
1366 (void __iomem **)&priv->mac_dev);
1368 goto err_free_netdev;
1370 /* xSGDMA Rx Dispatcher address space */
1371 ret = request_and_map(pdev, "rx_csr", &dma_res,
1374 goto err_free_netdev;
1377 /* xSGDMA Tx Dispatcher address space */
1378 ret = request_and_map(pdev, "tx_csr", &dma_res,
1381 goto err_free_netdev;
1385 priv->rx_irq = platform_get_irq_byname(pdev, "rx_irq");
1386 if (priv->rx_irq == -ENXIO) {
1387 dev_err(&pdev->dev, "cannot obtain Rx IRQ\n");
1389 goto err_free_netdev;
1393 priv->tx_irq = platform_get_irq_byname(pdev, "tx_irq");
1394 if (priv->tx_irq == -ENXIO) {
1395 dev_err(&pdev->dev, "cannot obtain Tx IRQ\n");
1397 goto err_free_netdev;
1400 /* get FIFO depths from device tree */
1401 if (of_property_read_u32(pdev->dev.of_node, "rx-fifo-depth",
1402 &priv->rx_fifo_depth)) {
1403 dev_err(&pdev->dev, "cannot obtain rx-fifo-depth\n");
1405 goto err_free_netdev;
1408 if (of_property_read_u32(pdev->dev.of_node, "tx-fifo-depth",
1409 &priv->tx_fifo_depth)) {
1410 dev_err(&pdev->dev, "cannot obtain tx-fifo-depth\n");
1412 goto err_free_netdev;
1415 /* get hash filter settings for this instance */
1417 of_property_read_bool(pdev->dev.of_node,
1418 "altr,has-hash-multicast-filter");
1420 /* Set hash filter to not set for now until the
1421 * multicast filter receive issue is debugged
1423 priv->hash_filter = 0;
1425 /* get supplemental address settings for this instance */
1426 priv->added_unicast =
1427 of_property_read_bool(pdev->dev.of_node,
1428 "altr,has-supplementary-unicast");
1430 /* Max MTU is 1500, ETH_DATA_LEN */
1431 priv->max_mtu = ETH_DATA_LEN;
1433 /* Get the max mtu from the device tree. Note that the
1434 * "max-frame-size" parameter is actually max mtu. Definition
1435 * in the ePAPR v1.1 spec and usage differ, so go with usage.
1437 of_property_read_u32(pdev->dev.of_node, "max-frame-size",
1440 /* The DMA buffer size already accounts for an alignment bias
1441 * to avoid unaligned access exceptions for the NIOS processor,
1443 priv->rx_dma_buf_sz = ALTERA_RXDMABUFFER_SIZE;
1445 /* get default MAC address from device tree */
1446 macaddr = of_get_mac_address(pdev->dev.of_node);
1448 ether_addr_copy(ndev->dev_addr, macaddr);
1450 eth_hw_addr_random(ndev);
1452 /* get phy addr and create mdio */
1453 ret = altera_tse_phy_get_addr_mdio_create(ndev);
1456 goto err_free_netdev;
1458 /* initialize netdev */
1459 ndev->mem_start = control_port->start;
1460 ndev->mem_end = control_port->end;
1461 ndev->netdev_ops = &altera_tse_netdev_ops;
1462 altera_tse_set_ethtool_ops(ndev);
1464 altera_tse_netdev_ops.ndo_set_rx_mode = tse_set_rx_mode;
1466 if (priv->hash_filter)
1467 altera_tse_netdev_ops.ndo_set_rx_mode =
1468 tse_set_rx_mode_hashfilter;
1470 /* Scatter/gather IO is not supported,
1471 * so it is turned off
1473 ndev->hw_features &= ~NETIF_F_SG;
1474 ndev->features |= ndev->hw_features | NETIF_F_HIGHDMA;
1476 /* VLAN offloading of tagging, stripping and filtering is not
1477 * supported by hardware, but driver will accommodate the
1478 * extra 4-byte VLAN tag for processing by upper layers
1480 ndev->features |= NETIF_F_HW_VLAN_CTAG_RX;
1482 /* setup NAPI interface */
1483 netif_napi_add(ndev, &priv->napi, tse_poll, NAPI_POLL_WEIGHT);
1485 spin_lock_init(&priv->mac_cfg_lock);
1486 spin_lock_init(&priv->tx_lock);
1487 spin_lock_init(&priv->rxdma_irq_lock);
1489 ret = register_netdev(ndev);
1491 dev_err(&pdev->dev, "failed to register TSE net device\n");
1492 goto err_register_netdev;
1495 platform_set_drvdata(pdev, ndev);
1497 priv->revision = ioread32(&priv->mac_dev->megacore_revision);
1499 if (netif_msg_probe(priv))
1500 dev_info(&pdev->dev, "Altera TSE MAC version %d.%d at 0x%08lx irq %d/%d\n",
1501 (priv->revision >> 8) & 0xff,
1502 priv->revision & 0xff,
1503 (unsigned long) control_port->start, priv->rx_irq,
1506 ret = init_phy(ndev);
1508 netdev_err(ndev, "Cannot attach to PHY (error: %d)\n", ret);
1514 unregister_netdev(ndev);
1515 err_register_netdev:
1516 netif_napi_del(&priv->napi);
1517 altera_tse_mdio_destroy(ndev);
1523 /* Remove Altera TSE MAC device
1525 static int altera_tse_remove(struct platform_device *pdev)
1527 struct net_device *ndev = platform_get_drvdata(pdev);
1528 struct altera_tse_private *priv = netdev_priv(ndev);
1531 phy_disconnect(priv->phydev);
1533 platform_set_drvdata(pdev, NULL);
1534 altera_tse_mdio_destroy(ndev);
1535 unregister_netdev(ndev);
1541 static const struct altera_dmaops altera_dtype_sgdma = {
1542 .altera_dtype = ALTERA_DTYPE_SGDMA,
1544 .reset_dma = sgdma_reset,
1545 .enable_txirq = sgdma_enable_txirq,
1546 .enable_rxirq = sgdma_enable_rxirq,
1547 .disable_txirq = sgdma_disable_txirq,
1548 .disable_rxirq = sgdma_disable_rxirq,
1549 .clear_txirq = sgdma_clear_txirq,
1550 .clear_rxirq = sgdma_clear_rxirq,
1551 .tx_buffer = sgdma_tx_buffer,
1552 .tx_completions = sgdma_tx_completions,
1553 .add_rx_desc = sgdma_add_rx_desc,
1554 .get_rx_status = sgdma_rx_status,
1555 .init_dma = sgdma_initialize,
1556 .uninit_dma = sgdma_uninitialize,
1557 .start_rxdma = sgdma_start_rxdma,
1560 static const struct altera_dmaops altera_dtype_msgdma = {
1561 .altera_dtype = ALTERA_DTYPE_MSGDMA,
1563 .reset_dma = msgdma_reset,
1564 .enable_txirq = msgdma_enable_txirq,
1565 .enable_rxirq = msgdma_enable_rxirq,
1566 .disable_txirq = msgdma_disable_txirq,
1567 .disable_rxirq = msgdma_disable_rxirq,
1568 .clear_txirq = msgdma_clear_txirq,
1569 .clear_rxirq = msgdma_clear_rxirq,
1570 .tx_buffer = msgdma_tx_buffer,
1571 .tx_completions = msgdma_tx_completions,
1572 .add_rx_desc = msgdma_add_rx_desc,
1573 .get_rx_status = msgdma_rx_status,
1574 .init_dma = msgdma_initialize,
1575 .uninit_dma = msgdma_uninitialize,
1576 .start_rxdma = msgdma_start_rxdma,
1579 static struct of_device_id altera_tse_ids[] = {
1580 { .compatible = "altr,tse-msgdma-1.0", .data = &altera_dtype_msgdma, },
1581 { .compatible = "altr,tse-1.0", .data = &altera_dtype_sgdma, },
1582 { .compatible = "ALTR,tse-1.0", .data = &altera_dtype_sgdma, },
1585 MODULE_DEVICE_TABLE(of, altera_tse_ids);
1587 static struct platform_driver altera_tse_driver = {
1588 .probe = altera_tse_probe,
1589 .remove = altera_tse_remove,
1593 .name = ALTERA_TSE_RESOURCE_NAME,
1594 .of_match_table = altera_tse_ids,
1598 module_platform_driver(altera_tse_driver);
1600 MODULE_AUTHOR("Altera Corporation");
1601 MODULE_DESCRIPTION("Altera Triple Speed Ethernet MAC driver");
1602 MODULE_LICENSE("GPL v2");