drivers/net/ethernet/broadcom/bnx2x/bnx2x_ethtool.c

   1 /* bnx2x_ethtool.c: Broadcom Everest network driver.
   2  *
   3  * Copyright (c) 2007-2013 Broadcom Corporation
   4  *
   5  * This program is free software; you can redistribute it and/or modify
   6  * it under the terms of the GNU General Public License as published by
   7  * the Free Software Foundation.
   8  *
   9  * Maintained by: Eilon Greenstein <eilong@broadcom.com>
  10  * Written by: Eliezer Tamir
  11  * Based on code from Michael Chan's bnx2 driver
  12  * UDP CSUM errata workaround by Arik Gendelman
  13  * Slowpath and fastpath rework by Vladislav Zolotarov
  14  * Statistics and Link management by Yitchak Gertner
  15  *
  16  */
  17
  18 #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
  19
  20 #include <linux/ethtool.h>
  21 #include <linux/netdevice.h>
  22 #include <linux/types.h>
  23 #include <linux/sched.h>
  24 #include <linux/crc32.h>
  25 #include "bnx2x.h"
  26 #include "bnx2x_cmn.h"
  27 #include "bnx2x_dump.h"
  28 #include "bnx2x_init.h"
  29
  30 /* Note: in the format strings below %s is replaced by the queue-name which is
  31  * either its index or 'fcoe' for the fcoe queue. Make sure the format string
  32  * length does not exceed ETH_GSTRING_LEN - MAX_QUEUE_NAME_LEN + 2
  33  */
  34 #define MAX_QUEUE_NAME_LEN      4
  35 static const struct {
  36         long offset;
  37         int size;
  38         char string[ETH_GSTRING_LEN];
  39 } bnx2x_q_stats_arr[] = {
  40 /* 1 */ { Q_STATS_OFFSET32(total_bytes_received_hi), 8, "[%s]: rx_bytes" },
  41         { Q_STATS_OFFSET32(total_unicast_packets_received_hi),
  42                                                 8, "[%s]: rx_ucast_packets" },
  43         { Q_STATS_OFFSET32(total_multicast_packets_received_hi),
  44                                                 8, "[%s]: rx_mcast_packets" },
  45         { Q_STATS_OFFSET32(total_broadcast_packets_received_hi),
  46                                                 8, "[%s]: rx_bcast_packets" },
  47         { Q_STATS_OFFSET32(no_buff_discard_hi), 8, "[%s]: rx_discards" },
  48         { Q_STATS_OFFSET32(rx_err_discard_pkt),
  49                                          4, "[%s]: rx_phy_ip_err_discards"},
  50         { Q_STATS_OFFSET32(rx_skb_alloc_failed),
  51                                          4, "[%s]: rx_skb_alloc_discard" },
  52         { Q_STATS_OFFSET32(hw_csum_err), 4, "[%s]: rx_csum_offload_errors" },
  53
  54         { Q_STATS_OFFSET32(total_bytes_transmitted_hi), 8, "[%s]: tx_bytes" },
  55 /* 10 */{ Q_STATS_OFFSET32(total_unicast_packets_transmitted_hi),
  56                                                 8, "[%s]: tx_ucast_packets" },
  57         { Q_STATS_OFFSET32(total_multicast_packets_transmitted_hi),
  58                                                 8, "[%s]: tx_mcast_packets" },
  59         { Q_STATS_OFFSET32(total_broadcast_packets_transmitted_hi),
  60                                                 8, "[%s]: tx_bcast_packets" },
  61         { Q_STATS_OFFSET32(total_tpa_aggregations_hi),
  62                                                 8, "[%s]: tpa_aggregations" },
  63         { Q_STATS_OFFSET32(total_tpa_aggregated_frames_hi),
  64                                         8, "[%s]: tpa_aggregated_frames"},
  65         { Q_STATS_OFFSET32(total_tpa_bytes_hi), 8, "[%s]: tpa_bytes"},
  66         { Q_STATS_OFFSET32(driver_filtered_tx_pkt),
  67                                         4, "[%s]: driver_filtered_tx_pkt" }
  68 };
  69
  70 #define BNX2X_NUM_Q_STATS ARRAY_SIZE(bnx2x_q_stats_arr)
  71
  72 static const struct {
  73         long offset;
  74         int size;
  75         u32 flags;
  76 #define STATS_FLAGS_PORT                1
  77 #define STATS_FLAGS_FUNC                2
  78 #define STATS_FLAGS_BOTH                (STATS_FLAGS_FUNC | STATS_FLAGS_PORT)
  79         char string[ETH_GSTRING_LEN];
  80 } bnx2x_stats_arr[] = {
  81 /* 1 */ { STATS_OFFSET32(total_bytes_received_hi),
  82                                 8, STATS_FLAGS_BOTH, "rx_bytes" },
  83         { STATS_OFFSET32(error_bytes_received_hi),
  84                                 8, STATS_FLAGS_BOTH, "rx_error_bytes" },
  85         { STATS_OFFSET32(total_unicast_packets_received_hi),
  86                                 8, STATS_FLAGS_BOTH, "rx_ucast_packets" },
  87         { STATS_OFFSET32(total_multicast_packets_received_hi),
  88                                 8, STATS_FLAGS_BOTH, "rx_mcast_packets" },
  89         { STATS_OFFSET32(total_broadcast_packets_received_hi),
  90                                 8, STATS_FLAGS_BOTH, "rx_bcast_packets" },
  91         { STATS_OFFSET32(rx_stat_dot3statsfcserrors_hi),
  92                                 8, STATS_FLAGS_PORT, "rx_crc_errors" },
  93         { STATS_OFFSET32(rx_stat_dot3statsalignmenterrors_hi),
  94                                 8, STATS_FLAGS_PORT, "rx_align_errors" },
  95         { STATS_OFFSET32(rx_stat_etherstatsundersizepkts_hi),
  96                                 8, STATS_FLAGS_PORT, "rx_undersize_packets" },
  97         { STATS_OFFSET32(etherstatsoverrsizepkts_hi),
  98                                 8, STATS_FLAGS_PORT, "rx_oversize_packets" },
  99 /* 10 */{ STATS_OFFSET32(rx_stat_etherstatsfragments_hi),
 100                                 8, STATS_FLAGS_PORT, "rx_fragments" },
 101         { STATS_OFFSET32(rx_stat_etherstatsjabbers_hi),
 102                                 8, STATS_FLAGS_PORT, "rx_jabbers" },
 103         { STATS_OFFSET32(no_buff_discard_hi),
 104                                 8, STATS_FLAGS_BOTH, "rx_discards" },
 105         { STATS_OFFSET32(mac_filter_discard),
 106                                 4, STATS_FLAGS_PORT, "rx_filtered_packets" },
 107         { STATS_OFFSET32(mf_tag_discard),
 108                                 4, STATS_FLAGS_PORT, "rx_mf_tag_discard" },
 109         { STATS_OFFSET32(pfc_frames_received_hi),
 110                                 8, STATS_FLAGS_PORT, "pfc_frames_received" },
 111         { STATS_OFFSET32(pfc_frames_sent_hi),
 112                                 8, STATS_FLAGS_PORT, "pfc_frames_sent" },
 113         { STATS_OFFSET32(brb_drop_hi),
 114                                 8, STATS_FLAGS_PORT, "rx_brb_discard" },
 115         { STATS_OFFSET32(brb_truncate_hi),
 116                                 8, STATS_FLAGS_PORT, "rx_brb_truncate" },
 117         { STATS_OFFSET32(pause_frames_received_hi),
 118                                 8, STATS_FLAGS_PORT, "rx_pause_frames" },
 119         { STATS_OFFSET32(rx_stat_maccontrolframesreceived_hi),
 120                                 8, STATS_FLAGS_PORT, "rx_mac_ctrl_frames" },
 121         { STATS_OFFSET32(nig_timer_max),
 122                         4, STATS_FLAGS_PORT, "rx_constant_pause_events" },
 123 /* 20 */{ STATS_OFFSET32(rx_err_discard_pkt),
 124                                 4, STATS_FLAGS_BOTH, "rx_phy_ip_err_discards"},
 125         { STATS_OFFSET32(rx_skb_alloc_failed),
 126                                 4, STATS_FLAGS_BOTH, "rx_skb_alloc_discard" },
 127         { STATS_OFFSET32(hw_csum_err),
 128                                 4, STATS_FLAGS_BOTH, "rx_csum_offload_errors" },
 129
 130         { STATS_OFFSET32(total_bytes_transmitted_hi),
 131                                 8, STATS_FLAGS_BOTH, "tx_bytes" },
 132         { STATS_OFFSET32(tx_stat_ifhcoutbadoctets_hi),
 133                                 8, STATS_FLAGS_PORT, "tx_error_bytes" },
 134         { STATS_OFFSET32(total_unicast_packets_transmitted_hi),
 135                                 8, STATS_FLAGS_BOTH, "tx_ucast_packets" },
 136         { STATS_OFFSET32(total_multicast_packets_transmitted_hi),
 137                                 8, STATS_FLAGS_BOTH, "tx_mcast_packets" },
 138         { STATS_OFFSET32(total_broadcast_packets_transmitted_hi),
 139                                 8, STATS_FLAGS_BOTH, "tx_bcast_packets" },
 140         { STATS_OFFSET32(tx_stat_dot3statsinternalmactransmiterrors_hi),
 141                                 8, STATS_FLAGS_PORT, "tx_mac_errors" },
 142         { STATS_OFFSET32(rx_stat_dot3statscarriersenseerrors_hi),
 143                                 8, STATS_FLAGS_PORT, "tx_carrier_errors" },
 144 /* 30 */{ STATS_OFFSET32(tx_stat_dot3statssinglecollisionframes_hi),
 145                                 8, STATS_FLAGS_PORT, "tx_single_collisions" },
 146         { STATS_OFFSET32(tx_stat_dot3statsmultiplecollisionframes_hi),
 147                                 8, STATS_FLAGS_PORT, "tx_multi_collisions" },
 148         { STATS_OFFSET32(tx_stat_dot3statsdeferredtransmissions_hi),
 149                                 8, STATS_FLAGS_PORT, "tx_deferred" },
 150         { STATS_OFFSET32(tx_stat_dot3statsexcessivecollisions_hi),
 151                                 8, STATS_FLAGS_PORT, "tx_excess_collisions" },
 152         { STATS_OFFSET32(tx_stat_dot3statslatecollisions_hi),
 153                                 8, STATS_FLAGS_PORT, "tx_late_collisions" },
 154         { STATS_OFFSET32(tx_stat_etherstatscollisions_hi),
 155                                 8, STATS_FLAGS_PORT, "tx_total_collisions" },
 156         { STATS_OFFSET32(tx_stat_etherstatspkts64octets_hi),
 157                                 8, STATS_FLAGS_PORT, "tx_64_byte_packets" },
 158         { STATS_OFFSET32(tx_stat_etherstatspkts65octetsto127octets_hi),
 159                         8, STATS_FLAGS_PORT, "tx_65_to_127_byte_packets" },
 160         { STATS_OFFSET32(tx_stat_etherstatspkts128octetsto255octets_hi),
 161                         8, STATS_FLAGS_PORT, "tx_128_to_255_byte_packets" },
 162         { STATS_OFFSET32(tx_stat_etherstatspkts256octetsto511octets_hi),
 163                         8, STATS_FLAGS_PORT, "tx_256_to_511_byte_packets" },
 164 /* 40 */{ STATS_OFFSET32(tx_stat_etherstatspkts512octetsto1023octets_hi),
 165                         8, STATS_FLAGS_PORT, "tx_512_to_1023_byte_packets" },
 166         { STATS_OFFSET32(etherstatspkts1024octetsto1522octets_hi),
 167                         8, STATS_FLAGS_PORT, "tx_1024_to_1522_byte_packets" },
 168         { STATS_OFFSET32(etherstatspktsover1522octets_hi),
 169                         8, STATS_FLAGS_PORT, "tx_1523_to_9022_byte_packets" },
 170         { STATS_OFFSET32(pause_frames_sent_hi),
 171                                 8, STATS_FLAGS_PORT, "tx_pause_frames" },
 172         { STATS_OFFSET32(total_tpa_aggregations_hi),
 173                         8, STATS_FLAGS_FUNC, "tpa_aggregations" },
 174         { STATS_OFFSET32(total_tpa_aggregated_frames_hi),
 175                         8, STATS_FLAGS_FUNC, "tpa_aggregated_frames"},
 176         { STATS_OFFSET32(total_tpa_bytes_hi),
 177                         8, STATS_FLAGS_FUNC, "tpa_bytes"},
 178         { STATS_OFFSET32(recoverable_error),
 179                         4, STATS_FLAGS_FUNC, "recoverable_errors" },
 180         { STATS_OFFSET32(unrecoverable_error),
 181                         4, STATS_FLAGS_FUNC, "unrecoverable_errors" },
 182         { STATS_OFFSET32(driver_filtered_tx_pkt),
 183                         4, STATS_FLAGS_FUNC, "driver_filtered_tx_pkt" },
 184         { STATS_OFFSET32(eee_tx_lpi),
 185                         4, STATS_FLAGS_PORT, "Tx LPI entry count"}
 186 };
 187
 188 #define BNX2X_NUM_STATS         ARRAY_SIZE(bnx2x_stats_arr)
 189
 190 static int bnx2x_get_port_type(struct bnx2x *bp)
 191 {
 192         int port_type;
 193         u32 phy_idx = bnx2x_get_cur_phy_idx(bp);
 194         switch (bp->link_params.phy[phy_idx].media_type) {
 195         case ETH_PHY_SFPP_10G_FIBER:
 196         case ETH_PHY_SFP_1G_FIBER:
 197         case ETH_PHY_XFP_FIBER:
 198         case ETH_PHY_KR:
 199         case ETH_PHY_CX4:
 200                 port_type = PORT_FIBRE;
 201                 break;
 202         case ETH_PHY_DA_TWINAX:
 203                 port_type = PORT_DA;
 204                 break;
 205         case ETH_PHY_BASE_T:
 206                 port_type = PORT_TP;
 207                 break;
 208         case ETH_PHY_NOT_PRESENT:
 209                 port_type = PORT_NONE;
 210                 break;
 211         case ETH_PHY_UNSPECIFIED:
 212         default:
 213                 port_type = PORT_OTHER;
 214                 break;
 215         }
 216         return port_type;
 217 }
 218
 219 static int bnx2x_get_settings(struct net_device *dev, struct ethtool_cmd *cmd)
 220 {
 221         struct bnx2x *bp = netdev_priv(dev);
 222         int cfg_idx = bnx2x_get_link_cfg_idx(bp);
 223
 224         /* Dual Media boards present all available port types */
 225         cmd->supported = bp->port.supported[cfg_idx] |
 226                 (bp->port.supported[cfg_idx ^ 1] &
 227                  (SUPPORTED_TP | SUPPORTED_FIBRE));
 228         cmd->advertising = bp->port.advertising[cfg_idx];
 229         if (bp->link_params.phy[bnx2x_get_cur_phy_idx(bp)].media_type ==
 230             ETH_PHY_SFP_1G_FIBER) {
 231                 cmd->supported &= ~(SUPPORTED_10000baseT_Full);
 232                 cmd->advertising &= ~(ADVERTISED_10000baseT_Full);
 233         }
 234
 235         if ((bp->state == BNX2X_STATE_OPEN) && bp->link_vars.link_up &&
 236             !(bp->flags & MF_FUNC_DIS)) {
 237                 cmd->duplex = bp->link_vars.duplex;
 238
 239                 if (IS_MF(bp) && !BP_NOMCP(bp))
 240                         ethtool_cmd_speed_set(cmd, bnx2x_get_mf_speed(bp));
 241                 else
 242                         ethtool_cmd_speed_set(cmd, bp->link_vars.line_speed);
 243         } else {
 244                 cmd->duplex = DUPLEX_UNKNOWN;
 245                 ethtool_cmd_speed_set(cmd, SPEED_UNKNOWN);
 246         }
 247
 248         cmd->port = bnx2x_get_port_type(bp);
 249
 250         cmd->phy_address = bp->mdio.prtad;
 251         cmd->transceiver = XCVR_INTERNAL;
 252
 253         if (bp->link_params.req_line_speed[cfg_idx] == SPEED_AUTO_NEG)
 254                 cmd->autoneg = AUTONEG_ENABLE;
 255         else
 256                 cmd->autoneg = AUTONEG_DISABLE;
 257
 258         /* Publish LP advertised speeds and FC */
 259         if (bp->link_vars.link_status & LINK_STATUS_AUTO_NEGOTIATE_COMPLETE) {
 260                 u32 status = bp->link_vars.link_status;
 261
 262                 cmd->lp_advertising |= ADVERTISED_Autoneg;
 263                 if (status & LINK_STATUS_LINK_PARTNER_SYMMETRIC_PAUSE)
 264                         cmd->lp_advertising |= ADVERTISED_Pause;
 265                 if (status & LINK_STATUS_LINK_PARTNER_ASYMMETRIC_PAUSE)
 266                         cmd->lp_advertising |= ADVERTISED_Asym_Pause;
 267
 268                 if (status & LINK_STATUS_LINK_PARTNER_10THD_CAPABLE)
 269                         cmd->lp_advertising |= ADVERTISED_10baseT_Half;
 270                 if (status & LINK_STATUS_LINK_PARTNER_10TFD_CAPABLE)
 271                         cmd->lp_advertising |= ADVERTISED_10baseT_Full;
 272                 if (status & LINK_STATUS_LINK_PARTNER_100TXHD_CAPABLE)
 273                         cmd->lp_advertising |= ADVERTISED_100baseT_Half;
 274                 if (status & LINK_STATUS_LINK_PARTNER_100TXFD_CAPABLE)
 275                         cmd->lp_advertising |= ADVERTISED_100baseT_Full;
 276                 if (status & LINK_STATUS_LINK_PARTNER_1000THD_CAPABLE)
 277                         cmd->lp_advertising |= ADVERTISED_1000baseT_Half;
 278                 if (status & LINK_STATUS_LINK_PARTNER_1000TFD_CAPABLE)
 279                         cmd->lp_advertising |= ADVERTISED_1000baseT_Full;
 280                 if (status & LINK_STATUS_LINK_PARTNER_2500XFD_CAPABLE)
 281                         cmd->lp_advertising |= ADVERTISED_2500baseX_Full;
 282                 if (status & LINK_STATUS_LINK_PARTNER_10GXFD_CAPABLE)
 283                         cmd->lp_advertising |= ADVERTISED_10000baseT_Full;
 284                 if (status & LINK_STATUS_LINK_PARTNER_20GXFD_CAPABLE)
 285                         cmd->lp_advertising |= ADVERTISED_20000baseKR2_Full;
 286         }
 287
 288         cmd->maxtxpkt = 0;
 289         cmd->maxrxpkt = 0;
 290
 291         DP(BNX2X_MSG_ETHTOOL, "ethtool_cmd: cmd %d\n"
 292            "  supported 0x%x  advertising 0x%x  speed %u\n"
 293            "  duplex %d  port %d  phy_address %d  transceiver %d\n"
 294            "  autoneg %d  maxtxpkt %d  maxrxpkt %d\n",
 295            cmd->cmd, cmd->supported, cmd->advertising,
 296            ethtool_cmd_speed(cmd),
 297            cmd->duplex, cmd->port, cmd->phy_address, cmd->transceiver,
 298            cmd->autoneg, cmd->maxtxpkt, cmd->maxrxpkt);
 299
 300         return 0;
 301 }
 302
 303 static int bnx2x_set_settings(struct net_device *dev, struct ethtool_cmd *cmd)
 304 {
 305         struct bnx2x *bp = netdev_priv(dev);
 306         u32 advertising, cfg_idx, old_multi_phy_config, new_multi_phy_config;
 307         u32 speed, phy_idx;
 308
 309         if (IS_MF_SD(bp))
 310                 return 0;
 311
 312         DP(BNX2X_MSG_ETHTOOL, "ethtool_cmd: cmd %d\n"
 313            "  supported 0x%x  advertising 0x%x  speed %u\n"
 314            "  duplex %d  port %d  phy_address %d  transceiver %d\n"
 315            "  autoneg %d  maxtxpkt %d  maxrxpkt %d\n",
 316            cmd->cmd, cmd->supported, cmd->advertising,
 317            ethtool_cmd_speed(cmd),
 318            cmd->duplex, cmd->port, cmd->phy_address, cmd->transceiver,
 319            cmd->autoneg, cmd->maxtxpkt, cmd->maxrxpkt);
 320
 321         speed = ethtool_cmd_speed(cmd);
 322
 323         /* If received a request for an unknown duplex, assume full*/
 324         if (cmd->duplex == DUPLEX_UNKNOWN)
 325                 cmd->duplex = DUPLEX_FULL;
 326
 327         if (IS_MF_SI(bp)) {
 328                 u32 part;
 329                 u32 line_speed = bp->link_vars.line_speed;
 330
 331                 /* use 10G if no link detected */
 332                 if (!line_speed)
 333                         line_speed = 10000;
 334
 335                 if (bp->common.bc_ver < REQ_BC_VER_4_SET_MF_BW) {
 336                         DP(BNX2X_MSG_ETHTOOL,
 337                            "To set speed BC %X or higher is required, please upgrade BC\n",
 338                            REQ_BC_VER_4_SET_MF_BW);
 339                         return -EINVAL;
 340                 }
 341
 342                 part = (speed * 100) / line_speed;
 343
 344                 if (line_speed < speed || !part) {
 345                         DP(BNX2X_MSG_ETHTOOL,
 346                            "Speed setting should be in a range from 1%% to 100%% of actual line speed\n");
 347                         return -EINVAL;
 348                 }
 349
 350                 if (bp->state != BNX2X_STATE_OPEN)
 351                         /* store value for following "load" */
 352                         bp->pending_max = part;
 353                 else
 354                         bnx2x_update_max_mf_config(bp, part);
 355
 356                 return 0;
 357         }
 358
 359         cfg_idx = bnx2x_get_link_cfg_idx(bp);
 360         old_multi_phy_config = bp->link_params.multi_phy_config;
 361         switch (cmd->port) {
 362         case PORT_TP:
 363                 if (bp->port.supported[cfg_idx] & SUPPORTED_TP)
 364                         break; /* no port change */
 365
 366                 if (!(bp->port.supported[0] & SUPPORTED_TP ||
 367                       bp->port.supported[1] & SUPPORTED_TP)) {
 368                         DP(BNX2X_MSG_ETHTOOL, "Unsupported port type\n");
 369                         return -EINVAL;
 370                 }
 371                 bp->link_params.multi_phy_config &=
 372                         ~PORT_HW_CFG_PHY_SELECTION_MASK;
 373                 if (bp->link_params.multi_phy_config &
 374                     PORT_HW_CFG_PHY_SWAPPED_ENABLED)
 375                         bp->link_params.multi_phy_config |=
 376                         PORT_HW_CFG_PHY_SELECTION_SECOND_PHY;
 377                 else
 378                         bp->link_params.multi_phy_config |=
 379                         PORT_HW_CFG_PHY_SELECTION_FIRST_PHY;
 380                 break;
 381         case PORT_FIBRE:
 382         case PORT_DA:
 383                 if (bp->port.supported[cfg_idx] & SUPPORTED_FIBRE)
 384                         break; /* no port change */
 385
 386                 if (!(bp->port.supported[0] & SUPPORTED_FIBRE ||
 387                       bp->port.supported[1] & SUPPORTED_FIBRE)) {
 388                         DP(BNX2X_MSG_ETHTOOL, "Unsupported port type\n");
 389                         return -EINVAL;
 390                 }
 391                 bp->link_params.multi_phy_config &=
 392                         ~PORT_HW_CFG_PHY_SELECTION_MASK;
 393                 if (bp->link_params.multi_phy_config &
 394                     PORT_HW_CFG_PHY_SWAPPED_ENABLED)
 395                         bp->link_params.multi_phy_config |=
 396                         PORT_HW_CFG_PHY_SELECTION_FIRST_PHY;
 397                 else
 398                         bp->link_params.multi_phy_config |=
 399                         PORT_HW_CFG_PHY_SELECTION_SECOND_PHY;
 400                 break;
 401         default:
 402                 DP(BNX2X_MSG_ETHTOOL, "Unsupported port type\n");
 403                 return -EINVAL;
 404         }
 405         /* Save new config in case command complete successfully */
 406         new_multi_phy_config = bp->link_params.multi_phy_config;
 407         /* Get the new cfg_idx */
 408         cfg_idx = bnx2x_get_link_cfg_idx(bp);
 409         /* Restore old config in case command failed */
 410         bp->link_params.multi_phy_config = old_multi_phy_config;
 411         DP(BNX2X_MSG_ETHTOOL, "cfg_idx = %x\n", cfg_idx);
 412
 413         if (cmd->autoneg == AUTONEG_ENABLE) {
 414                 u32 an_supported_speed = bp->port.supported[cfg_idx];
 415                 if (bp->link_params.phy[EXT_PHY1].type ==
 416                     PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM84833)
 417                         an_supported_speed |= (SUPPORTED_100baseT_Half |
 418                                                SUPPORTED_100baseT_Full);
 419                 if (!(bp->port.supported[cfg_idx] & SUPPORTED_Autoneg)) {
 420                         DP(BNX2X_MSG_ETHTOOL, "Autoneg not supported\n");
 421                         return -EINVAL;
 422                 }
 423
 424                 /* advertise the requested speed and duplex if supported */
 425                 if (cmd->advertising & ~an_supported_speed) {
 426                         DP(BNX2X_MSG_ETHTOOL,
 427                            "Advertisement parameters are not supported\n");
 428                         return -EINVAL;
 429                 }
 430
 431                 bp->link_params.req_line_speed[cfg_idx] = SPEED_AUTO_NEG;
 432                 bp->link_params.req_duplex[cfg_idx] = cmd->duplex;
 433                 bp->port.advertising[cfg_idx] = (ADVERTISED_Autoneg |
 434                                          cmd->advertising);
 435                 if (cmd->advertising) {
 436
 437                         bp->link_params.speed_cap_mask[cfg_idx] = 0;
 438                         if (cmd->advertising & ADVERTISED_10baseT_Half) {
 439                                 bp->link_params.speed_cap_mask[cfg_idx] |=
 440                                 PORT_HW_CFG_SPEED_CAPABILITY_D0_10M_HALF;
 441                         }
 442                         if (cmd->advertising & ADVERTISED_10baseT_Full)
 443                                 bp->link_params.speed_cap_mask[cfg_idx] |=
 444                                 PORT_HW_CFG_SPEED_CAPABILITY_D0_10M_FULL;
 445
 446                         if (cmd->advertising & ADVERTISED_100baseT_Full)
 447                                 bp->link_params.speed_cap_mask[cfg_idx] |=
 448                                 PORT_HW_CFG_SPEED_CAPABILITY_D0_100M_FULL;
 449
 450                         if (cmd->advertising & ADVERTISED_100baseT_Half) {
 451                                 bp->link_params.speed_cap_mask[cfg_idx] |=
 452                                      PORT_HW_CFG_SPEED_CAPABILITY_D0_100M_HALF;
 453                         }
 454                         if (cmd->advertising & ADVERTISED_1000baseT_Half) {
 455                                 bp->link_params.speed_cap_mask[cfg_idx] |=
 456                                         PORT_HW_CFG_SPEED_CAPABILITY_D0_1G;
 457                         }
 458                         if (cmd->advertising & (ADVERTISED_1000baseT_Full |
 459                                                 ADVERTISED_1000baseKX_Full))
 460                                 bp->link_params.speed_cap_mask[cfg_idx] |=
 461                                         PORT_HW_CFG_SPEED_CAPABILITY_D0_1G;
 462
 463                         if (cmd->advertising & (ADVERTISED_10000baseT_Full |
 464                                                 ADVERTISED_10000baseKX4_Full |
 465                                                 ADVERTISED_10000baseKR_Full))
 466                                 bp->link_params.speed_cap_mask[cfg_idx] |=
 467                                         PORT_HW_CFG_SPEED_CAPABILITY_D0_10G;
 468
 469                         if (cmd->advertising & ADVERTISED_20000baseKR2_Full)
 470                                 bp->link_params.speed_cap_mask[cfg_idx] |=
 471                                         PORT_HW_CFG_SPEED_CAPABILITY_D0_20G;
 472                 }
 473         } else { /* forced speed */
 474                 /* advertise the requested speed and duplex if supported */
 475                 switch (speed) {
 476                 case SPEED_10:
 477                         if (cmd->duplex == DUPLEX_FULL) {
 478                                 if (!(bp->port.supported[cfg_idx] &
 479                                       SUPPORTED_10baseT_Full)) {
 480                                         DP(BNX2X_MSG_ETHTOOL,
 481                                            "10M full not supported\n");
 482                                         return -EINVAL;
 483                                 }
 484
 485                                 advertising = (ADVERTISED_10baseT_Full |
 486                                                ADVERTISED_TP);
 487                         } else {
 488                                 if (!(bp->port.supported[cfg_idx] &
 489                                       SUPPORTED_10baseT_Half)) {
 490                                         DP(BNX2X_MSG_ETHTOOL,
 491                                            "10M half not supported\n");
 492                                         return -EINVAL;
 493                                 }
 494
 495                                 advertising = (ADVERTISED_10baseT_Half |
 496                                                ADVERTISED_TP);
 497                         }
 498                         break;
 499
 500                 case SPEED_100:
 501                         if (cmd->duplex == DUPLEX_FULL) {
 502                                 if (!(bp->port.supported[cfg_idx] &
 503                                                 SUPPORTED_100baseT_Full)) {
 504                                         DP(BNX2X_MSG_ETHTOOL,
 505                                            "100M full not supported\n");
 506                                         return -EINVAL;
 507                                 }
 508
 509                                 advertising = (ADVERTISED_100baseT_Full |
 510                                                ADVERTISED_TP);
 511                         } else {
 512                                 if (!(bp->port.supported[cfg_idx] &
 513                                                 SUPPORTED_100baseT_Half)) {
 514                                         DP(BNX2X_MSG_ETHTOOL,
 515                                            "100M half not supported\n");
 516                                         return -EINVAL;
 517                                 }
 518
 519                                 advertising = (ADVERTISED_100baseT_Half |
 520                                                ADVERTISED_TP);
 521                         }
 522                         break;
 523
 524                 case SPEED_1000:
 525                         if (cmd->duplex != DUPLEX_FULL) {
 526                                 DP(BNX2X_MSG_ETHTOOL,
 527                                    "1G half not supported\n");
 528                                 return -EINVAL;
 529                         }
 530
 531                         if (!(bp->port.supported[cfg_idx] &
 532                               SUPPORTED_1000baseT_Full)) {
 533                                 DP(BNX2X_MSG_ETHTOOL,
 534                                    "1G full not supported\n");
 535                                 return -EINVAL;
 536                         }
 537
 538                         advertising = (ADVERTISED_1000baseT_Full |
 539                                        ADVERTISED_TP);
 540                         break;
 541
 542                 case SPEED_2500:
 543                         if (cmd->duplex != DUPLEX_FULL) {
 544                                 DP(BNX2X_MSG_ETHTOOL,
 545                                    "2.5G half not supported\n");
 546                                 return -EINVAL;
 547                         }
 548
 549                         if (!(bp->port.supported[cfg_idx]
 550                               & SUPPORTED_2500baseX_Full)) {
 551                                 DP(BNX2X_MSG_ETHTOOL,
 552                                    "2.5G full not supported\n");
 553                                 return -EINVAL;
 554                         }
 555
 556                         advertising = (ADVERTISED_2500baseX_Full |
 557                                        ADVERTISED_TP);
 558                         break;
 559
 560                 case SPEED_10000:
 561                         if (cmd->duplex != DUPLEX_FULL) {
 562                                 DP(BNX2X_MSG_ETHTOOL,
 563                                    "10G half not supported\n");
 564                                 return -EINVAL;
 565                         }
 566                         phy_idx = bnx2x_get_cur_phy_idx(bp);
 567                         if (!(bp->port.supported[cfg_idx]
 568                               & SUPPORTED_10000baseT_Full) ||
 569                             (bp->link_params.phy[phy_idx].media_type ==
 570                              ETH_PHY_SFP_1G_FIBER)) {
 571                                 DP(BNX2X_MSG_ETHTOOL,
 572                                    "10G full not supported\n");
 573                                 return -EINVAL;
 574                         }
 575
 576                         advertising = (ADVERTISED_10000baseT_Full |
 577                                        ADVERTISED_FIBRE);
 578                         break;
 579
 580                 default:
 581                         DP(BNX2X_MSG_ETHTOOL, "Unsupported speed %u\n", speed);
 582                         return -EINVAL;
 583                 }
 584
 585                 bp->link_params.req_line_speed[cfg_idx] = speed;
 586                 bp->link_params.req_duplex[cfg_idx] = cmd->duplex;
 587                 bp->port.advertising[cfg_idx] = advertising;
 588         }
 589
 590         DP(BNX2X_MSG_ETHTOOL, "req_line_speed %d\n"
 591            "  req_duplex %d  advertising 0x%x\n",
 592            bp->link_params.req_line_speed[cfg_idx],
 593            bp->link_params.req_duplex[cfg_idx],
 594            bp->port.advertising[cfg_idx]);
 595
 596         /* Set new config */
 597         bp->link_params.multi_phy_config = new_multi_phy_config;
 598         if (netif_running(dev)) {
 599                 bnx2x_stats_handle(bp, STATS_EVENT_STOP);
 600                 bnx2x_link_set(bp);
 601         }
 602
 603         return 0;
 604 }
 605
 606 #define DUMP_ALL_PRESETS                0x1FFF
 607 #define DUMP_MAX_PRESETS                13
 608
 609 static int __bnx2x_get_preset_regs_len(struct bnx2x *bp, u32 preset)
 610 {
 611         if (CHIP_IS_E1(bp))
 612                 return dump_num_registers[0][preset-1];
 613         else if (CHIP_IS_E1H(bp))
 614                 return dump_num_registers[1][preset-1];
 615         else if (CHIP_IS_E2(bp))
 616                 return dump_num_registers[2][preset-1];
 617         else if (CHIP_IS_E3A0(bp))
 618                 return dump_num_registers[3][preset-1];
 619         else if (CHIP_IS_E3B0(bp))
 620                 return dump_num_registers[4][preset-1];
 621         else
 622                 return 0;
 623 }
 624
 625 static int __bnx2x_get_regs_len(struct bnx2x *bp)
 626 {
 627         u32 preset_idx;
 628         int regdump_len = 0;
 629
 630         /* Calculate the total preset regs length */
 631         for (preset_idx = 1; preset_idx <= DUMP_MAX_PRESETS; preset_idx++)
 632                 regdump_len += __bnx2x_get_preset_regs_len(bp, preset_idx);
 633
 634         return regdump_len;
 635 }
 636
 637 static int bnx2x_get_regs_len(struct net_device *dev)
 638 {
 639         struct bnx2x *bp = netdev_priv(dev);
 640         int regdump_len = 0;
 641
 642         if (IS_VF(bp))
 643                 return 0;
 644
 645         regdump_len = __bnx2x_get_regs_len(bp);
 646         regdump_len *= 4;
 647         regdump_len += sizeof(struct dump_header);
 648
 649         return regdump_len;
 650 }
 651
 652 #define IS_E1_REG(chips)        ((chips & DUMP_CHIP_E1) == DUMP_CHIP_E1)
 653 #define IS_E1H_REG(chips)       ((chips & DUMP_CHIP_E1H) == DUMP_CHIP_E1H)
 654 #define IS_E2_REG(chips)        ((chips & DUMP_CHIP_E2) == DUMP_CHIP_E2)
 655 #define IS_E3A0_REG(chips)      ((chips & DUMP_CHIP_E3A0) == DUMP_CHIP_E3A0)
 656 #define IS_E3B0_REG(chips)      ((chips & DUMP_CHIP_E3B0) == DUMP_CHIP_E3B0)
 657
 658 #define IS_REG_IN_PRESET(presets, idx)  \
 659                 ((presets & (1 << (idx-1))) == (1 << (idx-1)))
 660
 661 /******* Paged registers info selectors ********/
 662 static const u32 *__bnx2x_get_page_addr_ar(struct bnx2x *bp)
 663 {
 664         if (CHIP_IS_E2(bp))
 665                 return page_vals_e2;
 666         else if (CHIP_IS_E3(bp))
 667                 return page_vals_e3;
 668         else
 669                 return NULL;
 670 }
 671
 672 static u32 __bnx2x_get_page_reg_num(struct bnx2x *bp)
 673 {
 674         if (CHIP_IS_E2(bp))
 675                 return PAGE_MODE_VALUES_E2;
 676         else if (CHIP_IS_E3(bp))
 677                 return PAGE_MODE_VALUES_E3;
 678         else
 679                 return 0;
 680 }
 681
 682 static const u32 *__bnx2x_get_page_write_ar(struct bnx2x *bp)
 683 {
 684         if (CHIP_IS_E2(bp))
 685                 return page_write_regs_e2;
 686         else if (CHIP_IS_E3(bp))
 687                 return page_write_regs_e3;
 688         else
 689                 return NULL;
 690 }
 691
 692 static u32 __bnx2x_get_page_write_num(struct bnx2x *bp)
 693 {
 694         if (CHIP_IS_E2(bp))
 695                 return PAGE_WRITE_REGS_E2;
 696         else if (CHIP_IS_E3(bp))
 697                 return PAGE_WRITE_REGS_E3;
 698         else
 699                 return 0;
 700 }
 701
 702 static const struct reg_addr *__bnx2x_get_page_read_ar(struct bnx2x *bp)
 703 {
 704         if (CHIP_IS_E2(bp))
 705                 return page_read_regs_e2;
 706         else if (CHIP_IS_E3(bp))
 707                 return page_read_regs_e3;
 708         else
 709                 return NULL;
 710 }
 711
 712 static u32 __bnx2x_get_page_read_num(struct bnx2x *bp)
 713 {
 714         if (CHIP_IS_E2(bp))
 715                 return PAGE_READ_REGS_E2;
 716         else if (CHIP_IS_E3(bp))
 717                 return PAGE_READ_REGS_E3;
 718         else
 719                 return 0;
 720 }
 721
 722 static bool bnx2x_is_reg_in_chip(struct bnx2x *bp,
 723                                        const struct reg_addr *reg_info)
 724 {
 725         if (CHIP_IS_E1(bp))
 726                 return IS_E1_REG(reg_info->chips);
 727         else if (CHIP_IS_E1H(bp))
 728                 return IS_E1H_REG(reg_info->chips);
 729         else if (CHIP_IS_E2(bp))
 730                 return IS_E2_REG(reg_info->chips);
 731         else if (CHIP_IS_E3A0(bp))
 732                 return IS_E3A0_REG(reg_info->chips);
 733         else if (CHIP_IS_E3B0(bp))
 734                 return IS_E3B0_REG(reg_info->chips);
 735         else
 736                 return false;
 737 }
 738
 739 static bool bnx2x_is_wreg_in_chip(struct bnx2x *bp,
 740         const struct wreg_addr *wreg_info)
 741 {
 742         if (CHIP_IS_E1(bp))
 743                 return IS_E1_REG(wreg_info->chips);
 744         else if (CHIP_IS_E1H(bp))
 745                 return IS_E1H_REG(wreg_info->chips);
 746         else if (CHIP_IS_E2(bp))
 747                 return IS_E2_REG(wreg_info->chips);
 748         else if (CHIP_IS_E3A0(bp))
 749                 return IS_E3A0_REG(wreg_info->chips);
 750         else if (CHIP_IS_E3B0(bp))
 751                 return IS_E3B0_REG(wreg_info->chips);
 752         else
 753                 return false;
 754 }
 755
 756 /**
 757  * bnx2x_read_pages_regs - read "paged" registers
 758  *
 759  * @bp          device handle
 760  * @p           output buffer
 761  *
 762  * Reads "paged" memories: memories that may only be read by first writing to a
 763  * specific address ("write address") and then reading from a specific address
 764  * ("read address"). There may be more than one write address per "page" and
 765  * more than one read address per write address.
 766  */
 767 static void bnx2x_read_pages_regs(struct bnx2x *bp, u32 *p, u32 preset)
 768 {
 769         u32 i, j, k, n;
 770
 771         /* addresses of the paged registers */
 772         const u32 *page_addr = __bnx2x_get_page_addr_ar(bp);
 773         /* number of paged registers */
 774         int num_pages = __bnx2x_get_page_reg_num(bp);
 775         /* write addresses */
 776         const u32 *write_addr = __bnx2x_get_page_write_ar(bp);
 777         /* number of write addresses */
 778         int write_num = __bnx2x_get_page_write_num(bp);
 779         /* read addresses info */
 780         const struct reg_addr *read_addr = __bnx2x_get_page_read_ar(bp);
 781         /* number of read addresses */
 782         int read_num = __bnx2x_get_page_read_num(bp);
 783         u32 addr, size;
 784
 785         for (i = 0; i < num_pages; i++) {
 786                 for (j = 0; j < write_num; j++) {
 787                         REG_WR(bp, write_addr[j], page_addr[i]);
 788
 789                         for (k = 0; k < read_num; k++) {
 790                                 if (IS_REG_IN_PRESET(read_addr[k].presets,
 791                                                      preset)) {
 792                                         size = read_addr[k].size;
 793                                         for (n = 0; n < size; n++) {
 794                                                 addr = read_addr[k].addr + n*4;
 795                                                 *p++ = REG_RD(bp, addr);
 796                                         }
 797                                 }
 798                         }
 799                 }
 800         }
 801 }
 802
 803 static int __bnx2x_get_preset_regs(struct bnx2x *bp, u32 *p, u32 preset)
 804 {
 805         u32 i, j, addr;
 806         const struct wreg_addr *wreg_addr_p = NULL;
 807
 808         if (CHIP_IS_E1(bp))
 809                 wreg_addr_p = &wreg_addr_e1;
 810         else if (CHIP_IS_E1H(bp))
 811                 wreg_addr_p = &wreg_addr_e1h;
 812         else if (CHIP_IS_E2(bp))
 813                 wreg_addr_p = &wreg_addr_e2;
 814         else if (CHIP_IS_E3A0(bp))
 815                 wreg_addr_p = &wreg_addr_e3;
 816         else if (CHIP_IS_E3B0(bp))
 817                 wreg_addr_p = &wreg_addr_e3b0;
 818
 819         /* Read the idle_chk registers */
 820         for (i = 0; i < IDLE_REGS_COUNT; i++) {
 821                 if (bnx2x_is_reg_in_chip(bp, &idle_reg_addrs[i]) &&
 822                     IS_REG_IN_PRESET(idle_reg_addrs[i].presets, preset)) {
 823                         for (j = 0; j < idle_reg_addrs[i].size; j++)
 824                                 *p++ = REG_RD(bp, idle_reg_addrs[i].addr + j*4);
 825                 }
 826         }
 827
 828         /* Read the regular registers */
 829         for (i = 0; i < REGS_COUNT; i++) {
 830                 if (bnx2x_is_reg_in_chip(bp, &reg_addrs[i]) &&
 831                     IS_REG_IN_PRESET(reg_addrs[i].presets, preset)) {
 832                         for (j = 0; j < reg_addrs[i].size; j++)
 833                                 *p++ = REG_RD(bp, reg_addrs[i].addr + j*4);
 834                 }
 835         }
 836
 837         /* Read the CAM registers */
 838         if (bnx2x_is_wreg_in_chip(bp, wreg_addr_p) &&
 839             IS_REG_IN_PRESET(wreg_addr_p->presets, preset)) {
 840                 for (i = 0; i < wreg_addr_p->size; i++) {
 841                         *p++ = REG_RD(bp, wreg_addr_p->addr + i*4);
 842
 843                         /* In case of wreg_addr register, read additional
 844                            registers from read_regs array
 845                         */
 846                         for (j = 0; j < wreg_addr_p->read_regs_count; j++) {
 847                                 addr = *(wreg_addr_p->read_regs);
 848                                 *p++ = REG_RD(bp, addr + j*4);
 849                         }
 850                 }
 851         }
 852
 853         /* Paged registers are supported in E2 & E3 only */
 854         if (CHIP_IS_E2(bp) || CHIP_IS_E3(bp)) {
 855                 /* Read "paged" registers */
 856                 bnx2x_read_pages_regs(bp, p, preset);
 857         }
 858
 859         return 0;
 860 }
 861
 862 static void __bnx2x_get_regs(struct bnx2x *bp, u32 *p)
 863 {
 864         u32 preset_idx;
 865
 866         /* Read all registers, by reading all preset registers */
 867         for (preset_idx = 1; preset_idx <= DUMP_MAX_PRESETS; preset_idx++) {
 868                 /* Skip presets with IOR */
 869                 if ((preset_idx == 2) ||
 870                     (preset_idx == 5) ||
 871                     (preset_idx == 8) ||
 872                     (preset_idx == 11))
 873                         continue;
 874                 __bnx2x_get_preset_regs(bp, p, preset_idx);
 875                 p += __bnx2x_get_preset_regs_len(bp, preset_idx);
 876         }
 877 }
 878
 879 static void bnx2x_get_regs(struct net_device *dev,
 880                            struct ethtool_regs *regs, void *_p)
 881 {
 882         u32 *p = _p;
 883         struct bnx2x *bp = netdev_priv(dev);
 884         struct dump_header dump_hdr = {0};
 885
 886         regs->version = 2;
 887         memset(p, 0, regs->len);
 888
 889         if (!netif_running(bp->dev))
 890                 return;
 891
 892         /* Disable parity attentions as long as following dump may
 893          * cause false alarms by reading never written registers. We
 894          * will re-enable parity attentions right after the dump.
 895          */
 896
 897         bnx2x_disable_blocks_parity(bp);
 898
 899         dump_hdr.header_size = (sizeof(struct dump_header) / 4) - 1;
 900         dump_hdr.preset = DUMP_ALL_PRESETS;
 901         dump_hdr.version = BNX2X_DUMP_VERSION;
 902
 903         /* dump_meta_data presents OR of CHIP and PATH. */
 904         if (CHIP_IS_E1(bp)) {
 905                 dump_hdr.dump_meta_data = DUMP_CHIP_E1;
 906         } else if (CHIP_IS_E1H(bp)) {
 907                 dump_hdr.dump_meta_data = DUMP_CHIP_E1H;
 908         } else if (CHIP_IS_E2(bp)) {
 909                 dump_hdr.dump_meta_data = DUMP_CHIP_E2 |
 910                 (BP_PATH(bp) ? DUMP_PATH_1 : DUMP_PATH_0);
 911         } else if (CHIP_IS_E3A0(bp)) {
 912                 dump_hdr.dump_meta_data = DUMP_CHIP_E3A0 |
 913                 (BP_PATH(bp) ? DUMP_PATH_1 : DUMP_PATH_0);
 914         } else if (CHIP_IS_E3B0(bp)) {
 915                 dump_hdr.dump_meta_data = DUMP_CHIP_E3B0 |
 916                 (BP_PATH(bp) ? DUMP_PATH_1 : DUMP_PATH_0);
 917         }
 918
 919         memcpy(p, &dump_hdr, sizeof(struct dump_header));
 920         p += dump_hdr.header_size + 1;
 921
 922         /* Actually read the registers */
 923         __bnx2x_get_regs(bp, p);
 924
 925         /* Re-enable parity attentions */
 926         bnx2x_clear_blocks_parity(bp);
 927         bnx2x_enable_blocks_parity(bp);
 928 }
 929
 930 static int bnx2x_get_preset_regs_len(struct net_device *dev, u32 preset)
 931 {
 932         struct bnx2x *bp = netdev_priv(dev);
 933         int regdump_len = 0;
 934
 935         regdump_len = __bnx2x_get_preset_regs_len(bp, preset);
 936         regdump_len *= 4;
 937         regdump_len += sizeof(struct dump_header);
 938
 939         return regdump_len;
 940 }
 941
 942 static int bnx2x_set_dump(struct net_device *dev, struct ethtool_dump *val)
 943 {
 944         struct bnx2x *bp = netdev_priv(dev);
 945
 946         /* Use the ethtool_dump "flag" field as the dump preset index */
 947         if (val->flag < 1 || val->flag > DUMP_MAX_PRESETS)
 948                 return -EINVAL;
 949
 950         bp->dump_preset_idx = val->flag;
 951         return 0;
 952 }
 953
 954 static int bnx2x_get_dump_flag(struct net_device *dev,
 955                                struct ethtool_dump *dump)
 956 {
 957         struct bnx2x *bp = netdev_priv(dev);
 958
 959         dump->version = BNX2X_DUMP_VERSION;
 960         dump->flag = bp->dump_preset_idx;
 961         /* Calculate the requested preset idx length */
 962         dump->len = bnx2x_get_preset_regs_len(dev, bp->dump_preset_idx);
 963         DP(BNX2X_MSG_ETHTOOL, "Get dump preset %d length=%d\n",
 964            bp->dump_preset_idx, dump->len);
 965         return 0;
 966 }
 967
 968 static int bnx2x_get_dump_data(struct net_device *dev,
 969                                struct ethtool_dump *dump,
 970                                void *buffer)
 971 {
 972         u32 *p = buffer;
 973         struct bnx2x *bp = netdev_priv(dev);
 974         struct dump_header dump_hdr = {0};
 975
 976         /* Disable parity attentions as long as following dump may
 977          * cause false alarms by reading never written registers. We
 978          * will re-enable parity attentions right after the dump.
 979          */
 980
 981         bnx2x_disable_blocks_parity(bp);
 982
 983         dump_hdr.header_size = (sizeof(struct dump_header) / 4) - 1;
 984         dump_hdr.preset = bp->dump_preset_idx;
 985         dump_hdr.version = BNX2X_DUMP_VERSION;
 986
 987         DP(BNX2X_MSG_ETHTOOL, "Get dump data of preset %d\n", dump_hdr.preset);
 988
 989         /* dump_meta_data presents OR of CHIP and PATH. */
 990         if (CHIP_IS_E1(bp)) {
 991                 dump_hdr.dump_meta_data = DUMP_CHIP_E1;
 992         } else if (CHIP_IS_E1H(bp)) {
 993                 dump_hdr.dump_meta_data = DUMP_CHIP_E1H;
 994         } else if (CHIP_IS_E2(bp)) {
 995                 dump_hdr.dump_meta_data = DUMP_CHIP_E2 |
 996                 (BP_PATH(bp) ? DUMP_PATH_1 : DUMP_PATH_0);
 997         } else if (CHIP_IS_E3A0(bp)) {
 998                 dump_hdr.dump_meta_data = DUMP_CHIP_E3A0 |
 999                 (BP_PATH(bp) ? DUMP_PATH_1 : DUMP_PATH_0);
1000         } else if (CHIP_IS_E3B0(bp)) {
1001                 dump_hdr.dump_meta_data = DUMP_CHIP_E3B0 |
1002                 (BP_PATH(bp) ? DUMP_PATH_1 : DUMP_PATH_0);
1003         }
1004
1005         memcpy(p, &dump_hdr, sizeof(struct dump_header));
1006         p += dump_hdr.header_size + 1;
1007
1008         /* Actually read the registers */
1009         __bnx2x_get_preset_regs(bp, p, dump_hdr.preset);
1010
1011         /* Re-enable parity attentions */
1012         bnx2x_clear_blocks_parity(bp);
1013         bnx2x_enable_blocks_parity(bp);
1014
1015         return 0;
1016 }
1017
1018 static void bnx2x_get_drvinfo(struct net_device *dev,
1019                               struct ethtool_drvinfo *info)
1020 {
1021         struct bnx2x *bp = netdev_priv(dev);
1022
1023         strlcpy(info->driver, DRV_MODULE_NAME, sizeof(info->driver));
1024         strlcpy(info->version, DRV_MODULE_VERSION, sizeof(info->version));
1025
1026         bnx2x_fill_fw_str(bp, info->fw_version, sizeof(info->fw_version));
1027
1028         strlcpy(info->bus_info, pci_name(bp->pdev), sizeof(info->bus_info));
1029         info->n_stats = BNX2X_NUM_STATS;
1030         info->testinfo_len = BNX2X_NUM_TESTS(bp);
1031         info->eedump_len = bp->common.flash_size;
1032         info->regdump_len = bnx2x_get_regs_len(dev);
1033 }
1034
1035 static void bnx2x_get_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
1036 {
1037         struct bnx2x *bp = netdev_priv(dev);
1038
1039         if (bp->flags & NO_WOL_FLAG) {
1040                 wol->supported = 0;
1041                 wol->wolopts = 0;
1042         } else {
1043                 wol->supported = WAKE_MAGIC;
1044                 if (bp->wol)
1045                         wol->wolopts = WAKE_MAGIC;
1046                 else
1047                         wol->wolopts = 0;
1048         }
1049         memset(&wol->sopass, 0, sizeof(wol->sopass));
1050 }
1051
1052 static int bnx2x_set_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
1053 {
1054         struct bnx2x *bp = netdev_priv(dev);
1055
1056         if (wol->wolopts & ~WAKE_MAGIC) {
1057                 DP(BNX2X_MSG_ETHTOOL, "WOL not supported\n");
1058                 return -EINVAL;
1059         }
1060
1061         if (wol->wolopts & WAKE_MAGIC) {
1062                 if (bp->flags & NO_WOL_FLAG) {
1063                         DP(BNX2X_MSG_ETHTOOL, "WOL not supported\n");
1064                         return -EINVAL;
1065                 }
1066                 bp->wol = 1;
1067         } else
1068                 bp->wol = 0;
1069
1070         return 0;
1071 }
1072
1073 static u32 bnx2x_get_msglevel(struct net_device *dev)
1074 {
1075         struct bnx2x *bp = netdev_priv(dev);
1076
1077         return bp->msg_enable;
1078 }
1079
1080 static void bnx2x_set_msglevel(struct net_device *dev, u32 level)
1081 {
1082         struct bnx2x *bp = netdev_priv(dev);
1083
1084         if (capable(CAP_NET_ADMIN)) {
1085                 /* dump MCP trace */
1086                 if (IS_PF(bp) && (level & BNX2X_MSG_MCP))
1087                         bnx2x_fw_dump_lvl(bp, KERN_INFO);
1088                 bp->msg_enable = level;
1089         }
1090 }
1091
1092 static int bnx2x_nway_reset(struct net_device *dev)
1093 {
1094         struct bnx2x *bp = netdev_priv(dev);
1095
1096         if (!bp->port.pmf)
1097                 return 0;
1098
1099         if (netif_running(dev)) {
1100                 bnx2x_stats_handle(bp, STATS_EVENT_STOP);
1101                 bnx2x_force_link_reset(bp);
1102                 bnx2x_link_set(bp);
1103         }
1104
1105         return 0;
1106 }
1107
1108 static u32 bnx2x_get_link(struct net_device *dev)
1109 {
1110         struct bnx2x *bp = netdev_priv(dev);
1111
1112         if (bp->flags & MF_FUNC_DIS || (bp->state != BNX2X_STATE_OPEN))
1113                 return 0;
1114
1115         return bp->link_vars.link_up;
1116 }
1117
1118 static int bnx2x_get_eeprom_len(struct net_device *dev)
1119 {
1120         struct bnx2x *bp = netdev_priv(dev);
1121
1122         return bp->common.flash_size;
1123 }
1124
1125 /* Per pf misc lock must be acquired before the per port mcp lock. Otherwise,
1126  * had we done things the other way around, if two pfs from the same port would
1127  * attempt to access nvram at the same time, we could run into a scenario such
1128  * as:
1129  * pf A takes the port lock.
1130  * pf B succeeds in taking the same lock since they are from the same port.
1131  * pf A takes the per pf misc lock. Performs eeprom access.
1132  * pf A finishes. Unlocks the per pf misc lock.
1133  * Pf B takes the lock and proceeds to perform it's own access.
1134  * pf A unlocks the per port lock, while pf B is still working (!).
1135  * mcp takes the per port lock and corrupts pf B's access (and/or has it's own
1136  * access corrupted by pf B)
1137  */
1138 static int bnx2x_acquire_nvram_lock(struct bnx2x *bp)
1139 {
1140         int port = BP_PORT(bp);
1141         int count, i;
1142         u32 val;
1143
1144         /* acquire HW lock: protect against other PFs in PF Direct Assignment */
1145         bnx2x_acquire_hw_lock(bp, HW_LOCK_RESOURCE_NVRAM);
1146
1147         /* adjust timeout for emulation/FPGA */
1148         count = BNX2X_NVRAM_TIMEOUT_COUNT;
1149         if (CHIP_REV_IS_SLOW(bp))
1150                 count *= 100;
1151
1152         /* request access to nvram interface */
1153         REG_WR(bp, MCP_REG_MCPR_NVM_SW_ARB,
1154                (MCPR_NVM_SW_ARB_ARB_REQ_SET1 << port));
1155
1156         for (i = 0; i < count*10; i++) {
1157                 val = REG_RD(bp, MCP_REG_MCPR_NVM_SW_ARB);
1158                 if (val & (MCPR_NVM_SW_ARB_ARB_ARB1 << port))
1159                         break;
1160
1161                 udelay(5);
1162         }
1163
1164         if (!(val & (MCPR_NVM_SW_ARB_ARB_ARB1 << port))) {
1165                 DP(BNX2X_MSG_ETHTOOL | BNX2X_MSG_NVM,
1166                    "cannot get access to nvram interface\n");
1167                 return -EBUSY;
1168         }
1169
1170         return 0;
1171 }
1172
1173 static int bnx2x_release_nvram_lock(struct bnx2x *bp)
1174 {
1175         int port = BP_PORT(bp);
1176         int count, i;
1177         u32 val;
1178
1179         /* adjust timeout for emulation/FPGA */
1180         count = BNX2X_NVRAM_TIMEOUT_COUNT;
1181         if (CHIP_REV_IS_SLOW(bp))
1182                 count *= 100;
1183
1184         /* relinquish nvram interface */
1185         REG_WR(bp, MCP_REG_MCPR_NVM_SW_ARB,
1186                (MCPR_NVM_SW_ARB_ARB_REQ_CLR1 << port));
1187
1188         for (i = 0; i < count*10; i++) {
1189                 val = REG_RD(bp, MCP_REG_MCPR_NVM_SW_ARB);
1190                 if (!(val & (MCPR_NVM_SW_ARB_ARB_ARB1 << port)))
1191                         break;
1192
1193                 udelay(5);
1194         }
1195
1196         if (val & (MCPR_NVM_SW_ARB_ARB_ARB1 << port)) {
1197                 DP(BNX2X_MSG_ETHTOOL | BNX2X_MSG_NVM,
1198                    "cannot free access to nvram interface\n");
1199                 return -EBUSY;
1200         }
1201
1202         /* release HW lock: protect against other PFs in PF Direct Assignment */
1203         bnx2x_release_hw_lock(bp, HW_LOCK_RESOURCE_NVRAM);
1204         return 0;
1205 }
1206
1207 static void bnx2x_enable_nvram_access(struct bnx2x *bp)
1208 {
1209         u32 val;
1210
1211         val = REG_RD(bp, MCP_REG_MCPR_NVM_ACCESS_ENABLE);
1212
1213         /* enable both bits, even on read */
1214         REG_WR(bp, MCP_REG_MCPR_NVM_ACCESS_ENABLE,
1215                (val | MCPR_NVM_ACCESS_ENABLE_EN |
1216                       MCPR_NVM_ACCESS_ENABLE_WR_EN));
1217 }
1218
1219 static void bnx2x_disable_nvram_access(struct bnx2x *bp)
1220 {
1221         u32 val;
1222
1223         val = REG_RD(bp, MCP_REG_MCPR_NVM_ACCESS_ENABLE);
1224
1225         /* disable both bits, even after read */
1226         REG_WR(bp, MCP_REG_MCPR_NVM_ACCESS_ENABLE,
1227                (val & ~(MCPR_NVM_ACCESS_ENABLE_EN |
1228                         MCPR_NVM_ACCESS_ENABLE_WR_EN)));
1229 }
1230
1231 static int bnx2x_nvram_read_dword(struct bnx2x *bp, u32 offset, __be32 *ret_val,
1232                                   u32 cmd_flags)
1233 {
1234         int count, i, rc;
1235         u32 val;
1236
1237         /* build the command word */
1238         cmd_flags |= MCPR_NVM_COMMAND_DOIT;
1239
1240         /* need to clear DONE bit separately */
1241         REG_WR(bp, MCP_REG_MCPR_NVM_COMMAND, MCPR_NVM_COMMAND_DONE);
1242
1243         /* address of the NVRAM to read from */
1244         REG_WR(bp, MCP_REG_MCPR_NVM_ADDR,
1245                (offset & MCPR_NVM_ADDR_NVM_ADDR_VALUE));
1246
1247         /* issue a read command */
1248         REG_WR(bp, MCP_REG_MCPR_NVM_COMMAND, cmd_flags);
1249
1250         /* adjust timeout for emulation/FPGA */
1251         count = BNX2X_NVRAM_TIMEOUT_COUNT;
1252         if (CHIP_REV_IS_SLOW(bp))
1253                 count *= 100;
1254
1255         /* wait for completion */
1256         *ret_val = 0;
1257         rc = -EBUSY;
1258         for (i = 0; i < count; i++) {
1259                 udelay(5);
1260                 val = REG_RD(bp, MCP_REG_MCPR_NVM_COMMAND);
1261
1262                 if (val & MCPR_NVM_COMMAND_DONE) {
1263                         val = REG_RD(bp, MCP_REG_MCPR_NVM_READ);
1264                         /* we read nvram data in cpu order
1265                          * but ethtool sees it as an array of bytes
1266                          * converting to big-endian will do the work
1267                          */
1268                         *ret_val = cpu_to_be32(val);
1269                         rc = 0;
1270                         break;
1271                 }
1272         }
1273         if (rc == -EBUSY)
1274                 DP(BNX2X_MSG_ETHTOOL | BNX2X_MSG_NVM,
1275                    "nvram read timeout expired\n");
1276         return rc;
1277 }
1278
1279 static int bnx2x_nvram_read(struct bnx2x *bp, u32 offset, u8 *ret_buf,
1280                             int buf_size)
1281 {
1282         int rc;
1283         u32 cmd_flags;
1284         __be32 val;
1285
1286         if ((offset & 0x03) || (buf_size & 0x03) || (buf_size == 0)) {
1287                 DP(BNX2X_MSG_ETHTOOL | BNX2X_MSG_NVM,
1288                    "Invalid parameter: offset 0x%x  buf_size 0x%x\n",
1289                    offset, buf_size);
1290                 return -EINVAL;
1291         }
1292
1293         if (offset + buf_size > bp->common.flash_size) {
1294                 DP(BNX2X_MSG_ETHTOOL | BNX2X_MSG_NVM,
1295                    "Invalid parameter: offset (0x%x) + buf_size (0x%x) > flash_size (0x%x)\n",
1296                    offset, buf_size, bp->common.flash_size);
1297                 return -EINVAL;
1298         }
1299
1300         /* request access to nvram interface */
1301         rc = bnx2x_acquire_nvram_lock(bp);
1302         if (rc)
1303                 return rc;
1304
1305         /* enable access to nvram interface */
1306         bnx2x_enable_nvram_access(bp);
1307
1308         /* read the first word(s) */
1309         cmd_flags = MCPR_NVM_COMMAND_FIRST;
1310         while ((buf_size > sizeof(u32)) && (rc == 0)) {
1311                 rc = bnx2x_nvram_read_dword(bp, offset, &val, cmd_flags);
1312                 memcpy(ret_buf, &val, 4);
1313
1314                 /* advance to the next dword */
1315                 offset += sizeof(u32);
1316                 ret_buf += sizeof(u32);
1317                 buf_size -= sizeof(u32);
1318                 cmd_flags = 0;
1319         }
1320
1321         if (rc == 0) {
1322                 cmd_flags |= MCPR_NVM_COMMAND_LAST;
1323                 rc = bnx2x_nvram_read_dword(bp, offset, &val, cmd_flags);
1324                 memcpy(ret_buf, &val, 4);
1325         }
1326
1327         /* disable access to nvram interface */
1328         bnx2x_disable_nvram_access(bp);
1329         bnx2x_release_nvram_lock(bp);
1330
1331         return rc;
1332 }
1333
1334 static int bnx2x_nvram_read32(struct bnx2x *bp, u32 offset, u32 *buf,
1335                               int buf_size)
1336 {
1337         int rc;
1338
1339         rc = bnx2x_nvram_read(bp, offset, (u8 *)buf, buf_size);
1340
1341         if (!rc) {
1342                 __be32 *be = (__be32 *)buf;
1343
1344                 while ((buf_size -= 4) >= 0)
1345                         *buf++ = be32_to_cpu(*be++);
1346         }
1347
1348         return rc;
1349 }
1350
1351 static bool bnx2x_is_nvm_accessible(struct bnx2x *bp)
1352 {
1353         int rc = 1;
1354         u16 pm = 0;
1355         struct net_device *dev = pci_get_drvdata(bp->pdev);
1356
1357         if (bp->pdev->pm_cap)
1358                 rc = pci_read_config_word(bp->pdev,
1359                                           bp->pdev->pm_cap + PCI_PM_CTRL, &pm);
1360
1361         if ((rc && !netif_running(dev)) ||
1362             (!rc && ((pm & PCI_PM_CTRL_STATE_MASK) != (__force u16)PCI_D0)))
1363                 return false;
1364
1365         return true;
1366 }
1367
1368 static int bnx2x_get_eeprom(struct net_device *dev,
1369                             struct ethtool_eeprom *eeprom, u8 *eebuf)
1370 {
1371         struct bnx2x *bp = netdev_priv(dev);
1372
1373         if (!bnx2x_is_nvm_accessible(bp)) {
1374                 DP(BNX2X_MSG_ETHTOOL  | BNX2X_MSG_NVM,
1375                    "cannot access eeprom when the interface is down\n");
1376                 return -EAGAIN;
1377         }
1378
1379         DP(BNX2X_MSG_ETHTOOL | BNX2X_MSG_NVM, "ethtool_eeprom: cmd %d\n"
1380            "  magic 0x%x  offset 0x%x (%d)  len 0x%x (%d)\n",
1381            eeprom->cmd, eeprom->magic, eeprom->offset, eeprom->offset,
1382            eeprom->len, eeprom->len);
1383
1384         /* parameters already validated in ethtool_get_eeprom */
1385
1386         return bnx2x_nvram_read(bp, eeprom->offset, eebuf, eeprom->len);
1387 }
1388
1389 static int bnx2x_get_module_eeprom(struct net_device *dev,
1390                                    struct ethtool_eeprom *ee,
1391                                    u8 *data)
1392 {
1393         struct bnx2x *bp = netdev_priv(dev);
1394         int rc = -EINVAL, phy_idx;
1395         u8 *user_data = data;
1396         unsigned int start_addr = ee->offset, xfer_size = 0;
1397
1398         if (!bnx2x_is_nvm_accessible(bp)) {
1399                 DP(BNX2X_MSG_ETHTOOL | BNX2X_MSG_NVM,
1400                    "cannot access eeprom when the interface is down\n");
1401                 return -EAGAIN;
1402         }
1403
1404         phy_idx = bnx2x_get_cur_phy_idx(bp);
1405
1406         /* Read A0 section */
1407         if (start_addr < ETH_MODULE_SFF_8079_LEN) {
1408                 /* Limit transfer size to the A0 section boundary */
1409                 if (start_addr + ee->len > ETH_MODULE_SFF_8079_LEN)
1410                         xfer_size = ETH_MODULE_SFF_8079_LEN - start_addr;
1411                 else
1412                         xfer_size = ee->len;
1413                 bnx2x_acquire_phy_lock(bp);
1414                 rc = bnx2x_read_sfp_module_eeprom(&bp->link_params.phy[phy_idx],
1415                                                   &bp->link_params,
1416                                                   I2C_DEV_ADDR_A0,
1417                                                   start_addr,
1418                                                   xfer_size,
1419                                                   user_data);
1420                 bnx2x_release_phy_lock(bp);
1421                 if (rc) {
1422                         DP(BNX2X_MSG_ETHTOOL, "Failed reading A0 section\n");
1423
1424                         return -EINVAL;
1425                 }
1426                 user_data += xfer_size;
1427                 start_addr += xfer_size;
1428         }
1429
1430         /* Read A2 section */
1431         if ((start_addr >= ETH_MODULE_SFF_8079_LEN) &&
1432             (start_addr < ETH_MODULE_SFF_8472_LEN)) {
1433                 xfer_size = ee->len - xfer_size;
1434                 /* Limit transfer size to the A2 section boundary */
1435                 if (start_addr + xfer_size > ETH_MODULE_SFF_8472_LEN)
1436                         xfer_size = ETH_MODULE_SFF_8472_LEN - start_addr;
1437                 start_addr -= ETH_MODULE_SFF_8079_LEN;
1438                 bnx2x_acquire_phy_lock(bp);
1439                 rc = bnx2x_read_sfp_module_eeprom(&bp->link_params.phy[phy_idx],
1440                                                   &bp->link_params,
1441                                                   I2C_DEV_ADDR_A2,
1442                                                   start_addr,
1443                                                   xfer_size,
1444                                                   user_data);
1445                 bnx2x_release_phy_lock(bp);
1446                 if (rc) {
1447                         DP(BNX2X_MSG_ETHTOOL, "Failed reading A2 section\n");
1448                         return -EINVAL;
1449                 }
1450         }
1451         return rc;
1452 }
1453
1454 static int bnx2x_get_module_info(struct net_device *dev,
1455                                  struct ethtool_modinfo *modinfo)
1456 {
1457         struct bnx2x *bp = netdev_priv(dev);
1458         int phy_idx, rc;
1459         u8 sff8472_comp, diag_type;
1460
1461         if (!bnx2x_is_nvm_accessible(bp)) {
1462                 DP(BNX2X_MSG_ETHTOOL | BNX2X_MSG_NVM,
1463                    "cannot access eeprom when the interface is down\n");
1464                 return -EAGAIN;
1465         }
1466         phy_idx = bnx2x_get_cur_phy_idx(bp);
1467         bnx2x_acquire_phy_lock(bp);
1468         rc = bnx2x_read_sfp_module_eeprom(&bp->link_params.phy[phy_idx],
1469                                           &bp->link_params,
1470                                           I2C_DEV_ADDR_A0,
1471                                           SFP_EEPROM_SFF_8472_COMP_ADDR,
1472                                           SFP_EEPROM_SFF_8472_COMP_SIZE,
1473                                           &sff8472_comp);
1474         bnx2x_release_phy_lock(bp);
1475         if (rc) {
1476                 DP(BNX2X_MSG_ETHTOOL, "Failed reading SFF-8472 comp field\n");
1477                 return -EINVAL;
1478         }
1479
1480         bnx2x_acquire_phy_lock(bp);
1481         rc = bnx2x_read_sfp_module_eeprom(&bp->link_params.phy[phy_idx],
1482                                           &bp->link_params,
1483                                           I2C_DEV_ADDR_A0,
1484                                           SFP_EEPROM_DIAG_TYPE_ADDR,
1485                                           SFP_EEPROM_DIAG_TYPE_SIZE,
1486                                           &diag_type);
1487         bnx2x_release_phy_lock(bp);
1488         if (rc) {
1489                 DP(BNX2X_MSG_ETHTOOL, "Failed reading Diag Type field\n");
1490                 return -EINVAL;
1491         }
1492
1493         if (!sff8472_comp ||
1494             (diag_type & SFP_EEPROM_DIAG_ADDR_CHANGE_REQ)) {
1495                 modinfo->type = ETH_MODULE_SFF_8079;
1496                 modinfo->eeprom_len = ETH_MODULE_SFF_8079_LEN;
1497         } else {
1498                 modinfo->type = ETH_MODULE_SFF_8472;
1499                 modinfo->eeprom_len = ETH_MODULE_SFF_8472_LEN;
1500         }
1501         return 0;
1502 }
1503
1504 static int bnx2x_nvram_write_dword(struct bnx2x *bp, u32 offset, u32 val,
1505                                    u32 cmd_flags)
1506 {
1507         int count, i, rc;
1508
1509         /* build the command word */
1510         cmd_flags |= MCPR_NVM_COMMAND_DOIT | MCPR_NVM_COMMAND_WR;
1511
1512         /* need to clear DONE bit separately */
1513         REG_WR(bp, MCP_REG_MCPR_NVM_COMMAND, MCPR_NVM_COMMAND_DONE);
1514
1515         /* write the data */
1516         REG_WR(bp, MCP_REG_MCPR_NVM_WRITE, val);
1517
1518         /* address of the NVRAM to write to */
1519         REG_WR(bp, MCP_REG_MCPR_NVM_ADDR,
1520                (offset & MCPR_NVM_ADDR_NVM_ADDR_VALUE));
1521
1522         /* issue the write command */
1523         REG_WR(bp, MCP_REG_MCPR_NVM_COMMAND, cmd_flags);
1524
1525         /* adjust timeout for emulation/FPGA */
1526         count = BNX2X_NVRAM_TIMEOUT_COUNT;
1527         if (CHIP_REV_IS_SLOW(bp))
1528                 count *= 100;
1529
1530         /* wait for completion */
1531         rc = -EBUSY;
1532         for (i = 0; i < count; i++) {
1533                 udelay(5);
1534                 val = REG_RD(bp, MCP_REG_MCPR_NVM_COMMAND);
1535                 if (val & MCPR_NVM_COMMAND_DONE) {
1536                         rc = 0;
1537                         break;
1538                 }
1539         }
1540
1541         if (rc == -EBUSY)
1542                 DP(BNX2X_MSG_ETHTOOL | BNX2X_MSG_NVM,
1543                    "nvram write timeout expired\n");
1544         return rc;
1545 }
1546
1547 #define BYTE_OFFSET(offset)             (8 * (offset & 0x03))
1548
1549 static int bnx2x_nvram_write1(struct bnx2x *bp, u32 offset, u8 *data_buf,
1550                               int buf_size)
1551 {
1552         int rc;
1553         u32 cmd_flags, align_offset, val;
1554         __be32 val_be;
1555
1556         if (offset + buf_size > bp->common.flash_size) {
1557                 DP(BNX2X_MSG_ETHTOOL | BNX2X_MSG_NVM,
1558                    "Invalid parameter: offset (0x%x) + buf_size (0x%x) > flash_size (0x%x)\n",
1559                    offset, buf_size, bp->common.flash_size);
1560                 return -EINVAL;
1561         }
1562
1563         /* request access to nvram interface */
1564         rc = bnx2x_acquire_nvram_lock(bp);
1565         if (rc)
1566                 return rc;
1567
1568         /* enable access to nvram interface */
1569         bnx2x_enable_nvram_access(bp);
1570
1571         cmd_flags = (MCPR_NVM_COMMAND_FIRST | MCPR_NVM_COMMAND_LAST);
1572         align_offset = (offset & ~0x03);
1573         rc = bnx2x_nvram_read_dword(bp, align_offset, &val_be, cmd_flags);
1574
1575         if (rc == 0) {
1576                 /* nvram data is returned as an array of bytes
1577                  * convert it back to cpu order
1578                  */
1579                 val = be32_to_cpu(val_be);
1580
1581                 val &= ~le32_to_cpu((__force __le32)
1582                                     (0xff << BYTE_OFFSET(offset)));
1583                 val |= le32_to_cpu((__force __le32)
1584                                    (*data_buf << BYTE_OFFSET(offset)));
1585
1586                 rc = bnx2x_nvram_write_dword(bp, align_offset, val,
1587                                              cmd_flags);
1588         }
1589
1590         /* disable access to nvram interface */
1591         bnx2x_disable_nvram_access(bp);
1592         bnx2x_release_nvram_lock(bp);
1593
1594         return rc;
1595 }
1596
1597 static int bnx2x_nvram_write(struct bnx2x *bp, u32 offset, u8 *data_buf,
1598                              int buf_size)
1599 {
1600         int rc;
1601         u32 cmd_flags;
1602         u32 val;
1603         u32 written_so_far;
1604
1605         if (buf_size == 1)      /* ethtool */
1606                 return bnx2x_nvram_write1(bp, offset, data_buf, buf_size);
1607
1608         if ((offset & 0x03) || (buf_size & 0x03) || (buf_size == 0)) {
1609                 DP(BNX2X_MSG_ETHTOOL | BNX2X_MSG_NVM,
1610                    "Invalid parameter: offset 0x%x  buf_size 0x%x\n",
1611                    offset, buf_size);
1612                 return -EINVAL;
1613         }
1614
1615         if (offset + buf_size > bp->common.flash_size) {
1616                 DP(BNX2X_MSG_ETHTOOL | BNX2X_MSG_NVM,
1617                    "Invalid parameter: offset (0x%x) + buf_size (0x%x) > flash_size (0x%x)\n",
1618                    offset, buf_size, bp->common.flash_size);
1619                 return -EINVAL;
1620         }
1621
1622         /* request access to nvram interface */
1623         rc = bnx2x_acquire_nvram_lock(bp);
1624         if (rc)
1625                 return rc;
1626
1627         /* enable access to nvram interface */
1628         bnx2x_enable_nvram_access(bp);
1629
1630         written_so_far = 0;
1631         cmd_flags = MCPR_NVM_COMMAND_FIRST;
1632         while ((written_so_far < buf_size) && (rc == 0)) {
1633                 if (written_so_far == (buf_size - sizeof(u32)))
1634                         cmd_flags |= MCPR_NVM_COMMAND_LAST;
1635                 else if (((offset + 4) % BNX2X_NVRAM_PAGE_SIZE) == 0)
1636                         cmd_flags |= MCPR_NVM_COMMAND_LAST;
1637                 else if ((offset % BNX2X_NVRAM_PAGE_SIZE) == 0)
1638                         cmd_flags |= MCPR_NVM_COMMAND_FIRST;
1639
1640                 memcpy(&val, data_buf, 4);
1641
1642                 /* Notice unlike bnx2x_nvram_read_dword() this will not
1643                  * change val using be32_to_cpu(), which causes data to flip
1644                  * if the eeprom is read and then written back. This is due
1645                  * to tools utilizing this functionality that would break
1646                  * if this would be resolved.
1647                  */
1648                 rc = bnx2x_nvram_write_dword(bp, offset, val, cmd_flags);
1649
1650                 /* advance to the next dword */
1651                 offset += sizeof(u32);
1652                 data_buf += sizeof(u32);
1653                 written_so_far += sizeof(u32);
1654                 cmd_flags = 0;
1655         }
1656
1657         /* disable access to nvram interface */
1658         bnx2x_disable_nvram_access(bp);
1659         bnx2x_release_nvram_lock(bp);
1660
1661         return rc;
1662 }
1663
1664 static int bnx2x_set_eeprom(struct net_device *dev,
1665                             struct ethtool_eeprom *eeprom, u8 *eebuf)
1666 {
1667         struct bnx2x *bp = netdev_priv(dev);
1668         int port = BP_PORT(bp);
1669         int rc = 0;
1670         u32 ext_phy_config;
1671
1672         if (!bnx2x_is_nvm_accessible(bp)) {
1673                 DP(BNX2X_MSG_ETHTOOL | BNX2X_MSG_NVM,
1674                    "cannot access eeprom when the interface is down\n");
1675                 return -EAGAIN;
1676         }
1677
1678         DP(BNX2X_MSG_ETHTOOL | BNX2X_MSG_NVM, "ethtool_eeprom: cmd %d\n"
1679            "  magic 0x%x  offset 0x%x (%d)  len 0x%x (%d)\n",
1680            eeprom->cmd, eeprom->magic, eeprom->offset, eeprom->offset,
1681            eeprom->len, eeprom->len);
1682
1683         /* parameters already validated in ethtool_set_eeprom */
1684
1685         /* PHY eeprom can be accessed only by the PMF */
1686         if ((eeprom->magic >= 0x50485900) && (eeprom->magic <= 0x504859FF) &&
1687             !bp->port.pmf) {
1688                 DP(BNX2X_MSG_ETHTOOL | BNX2X_MSG_NVM,
1689                    "wrong magic or interface is not pmf\n");
1690                 return -EINVAL;
1691         }
1692
1693         ext_phy_config =
1694                 SHMEM_RD(bp,
1695                          dev_info.port_hw_config[port].external_phy_config);
1696
1697         if (eeprom->magic == 0x50485950) {
1698                 /* 'PHYP' (0x50485950): prepare phy for FW upgrade */
1699                 bnx2x_stats_handle(bp, STATS_EVENT_STOP);
1700
1701                 bnx2x_acquire_phy_lock(bp);
1702                 rc |= bnx2x_link_reset(&bp->link_params,
1703                                        &bp->link_vars, 0);
1704                 if (XGXS_EXT_PHY_TYPE(ext_phy_config) ==
1705                                         PORT_HW_CFG_XGXS_EXT_PHY_TYPE_SFX7101)
1706                         bnx2x_set_gpio(bp, MISC_REGISTERS_GPIO_0,
1707                                        MISC_REGISTERS_GPIO_HIGH, port);
1708                 bnx2x_release_phy_lock(bp);
1709                 bnx2x_link_report(bp);
1710
1711         } else if (eeprom->magic == 0x50485952) {
1712                 /* 'PHYR' (0x50485952): re-init link after FW upgrade */
1713                 if (bp->state == BNX2X_STATE_OPEN) {
1714                         bnx2x_acquire_phy_lock(bp);
1715                         rc |= bnx2x_link_reset(&bp->link_params,
1716                                                &bp->link_vars, 1);
1717
1718                         rc |= bnx2x_phy_init(&bp->link_params,
1719                                              &bp->link_vars);
1720                         bnx2x_release_phy_lock(bp);
1721                         bnx2x_calc_fc_adv(bp);
1722                 }
1723         } else if (eeprom->magic == 0x53985943) {
1724                 /* 'PHYC' (0x53985943): PHY FW upgrade completed */
1725                 if (XGXS_EXT_PHY_TYPE(ext_phy_config) ==
1726                                        PORT_HW_CFG_XGXS_EXT_PHY_TYPE_SFX7101) {
1727
1728                         /* DSP Remove Download Mode */
1729                         bnx2x_set_gpio(bp, MISC_REGISTERS_GPIO_0,
1730                                        MISC_REGISTERS_GPIO_LOW, port);
1731
1732                         bnx2x_acquire_phy_lock(bp);
1733
1734                         bnx2x_sfx7101_sp_sw_reset(bp,
1735                                                 &bp->link_params.phy[EXT_PHY1]);
1736
1737                         /* wait 0.5 sec to allow it to run */
1738                         msleep(500);
1739                         bnx2x_ext_phy_hw_reset(bp, port);
1740                         msleep(500);
1741                         bnx2x_release_phy_lock(bp);
1742                 }
1743         } else
1744                 rc = bnx2x_nvram_write(bp, eeprom->offset, eebuf, eeprom->len);
1745
1746         return rc;
1747 }
1748
1749 static int bnx2x_get_coalesce(struct net_device *dev,
1750                               struct ethtool_coalesce *coal)
1751 {
1752         struct bnx2x *bp = netdev_priv(dev);
1753
1754         memset(coal, 0, sizeof(struct ethtool_coalesce));
1755
1756         coal->rx_coalesce_usecs = bp->rx_ticks;
1757         coal->tx_coalesce_usecs = bp->tx_ticks;
1758
1759         return 0;
1760 }
1761
1762 static int bnx2x_set_coalesce(struct net_device *dev,
1763                               struct ethtool_coalesce *coal)
1764 {
1765         struct bnx2x *bp = netdev_priv(dev);
1766
1767         bp->rx_ticks = (u16)coal->rx_coalesce_usecs;
1768         if (bp->rx_ticks > BNX2X_MAX_COALESCE_TOUT)
1769                 bp->rx_ticks = BNX2X_MAX_COALESCE_TOUT;
1770
1771         bp->tx_ticks = (u16)coal->tx_coalesce_usecs;
1772         if (bp->tx_ticks > BNX2X_MAX_COALESCE_TOUT)
1773                 bp->tx_ticks = BNX2X_MAX_COALESCE_TOUT;
1774
1775         if (netif_running(dev))
1776                 bnx2x_update_coalesce(bp);
1777
1778         return 0;
1779 }
1780
1781 static void bnx2x_get_ringparam(struct net_device *dev,
1782                                 struct ethtool_ringparam *ering)
1783 {
1784         struct bnx2x *bp = netdev_priv(dev);
1785
1786         ering->rx_max_pending = MAX_RX_AVAIL;
1787
1788         if (bp->rx_ring_size)
1789                 ering->rx_pending = bp->rx_ring_size;
1790         else
1791                 ering->rx_pending = MAX_RX_AVAIL;
1792
1793         ering->tx_max_pending = IS_MF_FCOE_AFEX(bp) ? 0 : MAX_TX_AVAIL;
1794         ering->tx_pending = bp->tx_ring_size;
1795 }
1796
1797 static int bnx2x_set_ringparam(struct net_device *dev,
1798                                struct ethtool_ringparam *ering)
1799 {
1800         struct bnx2x *bp = netdev_priv(dev);
1801
1802         DP(BNX2X_MSG_ETHTOOL,
1803            "set ring params command parameters: rx_pending = %d, tx_pending = %d\n",
1804            ering->rx_pending, ering->tx_pending);
1805
1806         if (bp->recovery_state != BNX2X_RECOVERY_DONE) {
1807                 DP(BNX2X_MSG_ETHTOOL,
1808                    "Handling parity error recovery. Try again later\n");
1809                 return -EAGAIN;
1810         }
1811
1812         if ((ering->rx_pending > MAX_RX_AVAIL) ||
1813             (ering->rx_pending < (bp->disable_tpa ? MIN_RX_SIZE_NONTPA :
1814                                                     MIN_RX_SIZE_TPA)) ||
1815             (ering->tx_pending > (IS_MF_FCOE_AFEX(bp) ? 0 : MAX_TX_AVAIL)) ||
1816             (ering->tx_pending <= MAX_SKB_FRAGS + 4)) {
1817                 DP(BNX2X_MSG_ETHTOOL, "Command parameters not supported\n");
1818                 return -EINVAL;
1819         }
1820
1821         bp->rx_ring_size = ering->rx_pending;
1822         bp->tx_ring_size = ering->tx_pending;
1823
1824         return bnx2x_reload_if_running(dev);
1825 }
1826
1827 static void bnx2x_get_pauseparam(struct net_device *dev,
1828                                  struct ethtool_pauseparam *epause)
1829 {
1830         struct bnx2x *bp = netdev_priv(dev);
1831         int cfg_idx = bnx2x_get_link_cfg_idx(bp);
1832         int cfg_reg;
1833
1834         epause->autoneg = (bp->link_params.req_flow_ctrl[cfg_idx] ==
1835                            BNX2X_FLOW_CTRL_AUTO);
1836
1837         if (!epause->autoneg)
1838                 cfg_reg = bp->link_params.req_flow_ctrl[cfg_idx];
1839         else
1840                 cfg_reg = bp->link_params.req_fc_auto_adv;
1841
1842         epause->rx_pause = ((cfg_reg & BNX2X_FLOW_CTRL_RX) ==
1843                             BNX2X_FLOW_CTRL_RX);
1844         epause->tx_pause = ((cfg_reg & BNX2X_FLOW_CTRL_TX) ==
1845                             BNX2X_FLOW_CTRL_TX);
1846
1847         DP(BNX2X_MSG_ETHTOOL, "ethtool_pauseparam: cmd %d\n"
1848            "  autoneg %d  rx_pause %d  tx_pause %d\n",
1849            epause->cmd, epause->autoneg, epause->rx_pause, epause->tx_pause);
1850 }
1851
1852 static int bnx2x_set_pauseparam(struct net_device *dev,
1853                                 struct ethtool_pauseparam *epause)
1854 {
1855         struct bnx2x *bp = netdev_priv(dev);
1856         u32 cfg_idx = bnx2x_get_link_cfg_idx(bp);
1857         if (IS_MF(bp))
1858                 return 0;
1859
1860         DP(BNX2X_MSG_ETHTOOL, "ethtool_pauseparam: cmd %d\n"
1861            "  autoneg %d  rx_pause %d  tx_pause %d\n",
1862            epause->cmd, epause->autoneg, epause->rx_pause, epause->tx_pause);
1863
1864         bp->link_params.req_flow_ctrl[cfg_idx] = BNX2X_FLOW_CTRL_AUTO;
1865
1866         if (epause->rx_pause)
1867                 bp->link_params.req_flow_ctrl[cfg_idx] |= BNX2X_FLOW_CTRL_RX;
1868
1869         if (epause->tx_pause)
1870                 bp->link_params.req_flow_ctrl[cfg_idx] |= BNX2X_FLOW_CTRL_TX;
1871
1872         if (bp->link_params.req_flow_ctrl[cfg_idx] == BNX2X_FLOW_CTRL_AUTO)
1873                 bp->link_params.req_flow_ctrl[cfg_idx] = BNX2X_FLOW_CTRL_NONE;
1874
1875         if (epause->autoneg) {
1876                 if (!(bp->port.supported[cfg_idx] & SUPPORTED_Autoneg)) {
1877                         DP(BNX2X_MSG_ETHTOOL, "autoneg not supported\n");
1878                         return -EINVAL;
1879                 }
1880
1881                 if (bp->link_params.req_line_speed[cfg_idx] == SPEED_AUTO_NEG) {
1882                         bp->link_params.req_flow_ctrl[cfg_idx] =
1883                                 BNX2X_FLOW_CTRL_AUTO;
1884                 }
1885                 bp->link_params.req_fc_auto_adv = 0;
1886                 if (epause->rx_pause)
1887                         bp->link_params.req_fc_auto_adv |= BNX2X_FLOW_CTRL_RX;
1888
1889                 if (epause->tx_pause)
1890                         bp->link_params.req_fc_auto_adv |= BNX2X_FLOW_CTRL_TX;
1891
1892                 if (!bp->link_params.req_fc_auto_adv)
1893                         bp->link_params.req_fc_auto_adv |= BNX2X_FLOW_CTRL_NONE;
1894         }
1895
1896         DP(BNX2X_MSG_ETHTOOL,
1897            "req_flow_ctrl 0x%x\n", bp->link_params.req_flow_ctrl[cfg_idx]);
1898
1899         if (netif_running(dev)) {
1900                 bnx2x_stats_handle(bp, STATS_EVENT_STOP);
1901                 bnx2x_link_set(bp);
1902         }
1903
1904         return 0;
1905 }
1906
1907 static const char bnx2x_tests_str_arr[BNX2X_NUM_TESTS_SF][ETH_GSTRING_LEN] = {
1908         "register_test (offline)    ",
1909         "memory_test (offline)      ",
1910         "int_loopback_test (offline)",
1911         "ext_loopback_test (offline)",
1912         "nvram_test (online)        ",
1913         "interrupt_test (online)    ",
1914         "link_test (online)         "
1915 };
1916
1917 enum {
1918         BNX2X_PRI_FLAG_ISCSI,
1919         BNX2X_PRI_FLAG_FCOE,
1920         BNX2X_PRI_FLAG_STORAGE,
1921         BNX2X_PRI_FLAG_LEN,
1922 };
1923
1924 static const char bnx2x_private_arr[BNX2X_PRI_FLAG_LEN][ETH_GSTRING_LEN] = {
1925         "iSCSI offload support",
1926         "FCoE offload support",
1927         "Storage only interface"
1928 };
1929
1930 static u32 bnx2x_eee_to_adv(u32 eee_adv)
1931 {
1932         u32 modes = 0;
1933
1934         if (eee_adv & SHMEM_EEE_100M_ADV)
1935                 modes |= ADVERTISED_100baseT_Full;
1936         if (eee_adv & SHMEM_EEE_1G_ADV)
1937                 modes |= ADVERTISED_1000baseT_Full;
1938         if (eee_adv & SHMEM_EEE_10G_ADV)
1939                 modes |= ADVERTISED_10000baseT_Full;
1940
1941         return modes;
1942 }
1943
1944 static u32 bnx2x_adv_to_eee(u32 modes, u32 shift)
1945 {
1946         u32 eee_adv = 0;
1947         if (modes & ADVERTISED_100baseT_Full)
1948                 eee_adv |= SHMEM_EEE_100M_ADV;
1949         if (modes & ADVERTISED_1000baseT_Full)
1950                 eee_adv |= SHMEM_EEE_1G_ADV;
1951         if (modes & ADVERTISED_10000baseT_Full)
1952                 eee_adv |= SHMEM_EEE_10G_ADV;
1953
1954         return eee_adv << shift;
1955 }
1956
1957 static int bnx2x_get_eee(struct net_device *dev, struct ethtool_eee *edata)
1958 {
1959         struct bnx2x *bp = netdev_priv(dev);
1960         u32 eee_cfg;
1961
1962         if (!SHMEM2_HAS(bp, eee_status[BP_PORT(bp)])) {
1963                 DP(BNX2X_MSG_ETHTOOL, "BC Version does not support EEE\n");
1964                 return -EOPNOTSUPP;
1965         }
1966
1967         eee_cfg = bp->link_vars.eee_status;
1968
1969         edata->supported =
1970                 bnx2x_eee_to_adv((eee_cfg & SHMEM_EEE_SUPPORTED_MASK) >>
1971                                  SHMEM_EEE_SUPPORTED_SHIFT);
1972
1973         edata->advertised =
1974                 bnx2x_eee_to_adv((eee_cfg & SHMEM_EEE_ADV_STATUS_MASK) >>
1975                                  SHMEM_EEE_ADV_STATUS_SHIFT);
1976         edata->lp_advertised =
1977                 bnx2x_eee_to_adv((eee_cfg & SHMEM_EEE_LP_ADV_STATUS_MASK) >>
1978                                  SHMEM_EEE_LP_ADV_STATUS_SHIFT);
1979
1980         /* SHMEM value is in 16u units --> Convert to 1u units. */
1981         edata->tx_lpi_timer = (eee_cfg & SHMEM_EEE_TIMER_MASK) << 4;
1982
1983         edata->eee_enabled    = (eee_cfg & SHMEM_EEE_REQUESTED_BIT)     ? 1 : 0;
1984         edata->eee_active     = (eee_cfg & SHMEM_EEE_ACTIVE_BIT)        ? 1 : 0;
1985         edata->tx_lpi_enabled = (eee_cfg & SHMEM_EEE_LPI_REQUESTED_BIT) ? 1 : 0;
1986
1987         return 0;
1988 }
1989
1990 static int bnx2x_set_eee(struct net_device *dev, struct ethtool_eee *edata)
1991 {
1992         struct bnx2x *bp = netdev_priv(dev);
1993         u32 eee_cfg;
1994         u32 advertised;
1995
1996         if (IS_MF(bp))
1997                 return 0;
1998
1999         if (!SHMEM2_HAS(bp, eee_status[BP_PORT(bp)])) {
2000                 DP(BNX2X_MSG_ETHTOOL, "BC Version does not support EEE\n");
2001                 return -EOPNOTSUPP;
2002         }
2003
2004         eee_cfg = bp->link_vars.eee_status;
2005
2006         if (!(eee_cfg & SHMEM_EEE_SUPPORTED_MASK)) {
2007                 DP(BNX2X_MSG_ETHTOOL, "Board does not support EEE!\n");
2008                 return -EOPNOTSUPP;
2009         }
2010
2011         advertised = bnx2x_adv_to_eee(edata->advertised,
2012                                       SHMEM_EEE_ADV_STATUS_SHIFT);
2013         if ((advertised != (eee_cfg & SHMEM_EEE_ADV_STATUS_MASK))) {
2014                 DP(BNX2X_MSG_ETHTOOL,
2015                    "Direct manipulation of EEE advertisement is not supported\n");
2016                 return -EINVAL;
2017         }
2018
2019         if (edata->tx_lpi_timer > EEE_MODE_TIMER_MASK) {
2020                 DP(BNX2X_MSG_ETHTOOL,
2021                    "Maximal Tx Lpi timer supported is %x(u)\n",
2022                    EEE_MODE_TIMER_MASK);
2023                 return -EINVAL;
2024         }
2025         if (edata->tx_lpi_enabled &&
2026             (edata->tx_lpi_timer < EEE_MODE_NVRAM_AGGRESSIVE_TIME)) {
2027                 DP(BNX2X_MSG_ETHTOOL,
2028                    "Minimal Tx Lpi timer supported is %d(u)\n",
2029                    EEE_MODE_NVRAM_AGGRESSIVE_TIME);
2030                 return -EINVAL;
2031         }
2032
2033         /* All is well; Apply changes*/
2034         if (edata->eee_enabled)
2035                 bp->link_params.eee_mode |= EEE_MODE_ADV_LPI;
2036         else
2037                 bp->link_params.eee_mode &= ~EEE_MODE_ADV_LPI;
2038
2039         if (edata->tx_lpi_enabled)
2040                 bp->link_params.eee_mode |= EEE_MODE_ENABLE_LPI;
2041         else
2042                 bp->link_params.eee_mode &= ~EEE_MODE_ENABLE_LPI;
2043
2044         bp->link_params.eee_mode &= ~EEE_MODE_TIMER_MASK;
2045         bp->link_params.eee_mode |= (edata->tx_lpi_timer &
2046                                     EEE_MODE_TIMER_MASK) |
2047                                     EEE_MODE_OVERRIDE_NVRAM |
2048                                     EEE_MODE_OUTPUT_TIME;
2049
2050         /* Restart link to propagate changes */
2051         if (netif_running(dev)) {
2052                 bnx2x_stats_handle(bp, STATS_EVENT_STOP);
2053                 bnx2x_force_link_reset(bp);
2054                 bnx2x_link_set(bp);
2055         }
2056
2057         return 0;
2058 }
2059
2060 enum {
2061         BNX2X_CHIP_E1_OFST = 0,
2062         BNX2X_CHIP_E1H_OFST,
2063         BNX2X_CHIP_E2_OFST,
2064         BNX2X_CHIP_E3_OFST,
2065         BNX2X_CHIP_E3B0_OFST,
2066         BNX2X_CHIP_MAX_OFST
2067 };
2068
2069 #define BNX2X_CHIP_MASK_E1      (1 << BNX2X_CHIP_E1_OFST)
2070 #define BNX2X_CHIP_MASK_E1H     (1 << BNX2X_CHIP_E1H_OFST)
2071 #define BNX2X_CHIP_MASK_E2      (1 << BNX2X_CHIP_E2_OFST)
2072 #define BNX2X_CHIP_MASK_E3      (1 << BNX2X_CHIP_E3_OFST)
2073 #define BNX2X_CHIP_MASK_E3B0    (1 << BNX2X_CHIP_E3B0_OFST)
2074
2075 #define BNX2X_CHIP_MASK_ALL     ((1 << BNX2X_CHIP_MAX_OFST) - 1)
2076 #define BNX2X_CHIP_MASK_E1X     (BNX2X_CHIP_MASK_E1 | BNX2X_CHIP_MASK_E1H)
2077
2078 static int bnx2x_test_registers(struct bnx2x *bp)
2079 {
2080         int idx, i, rc = -ENODEV;
2081         u32 wr_val = 0, hw;
2082         int port = BP_PORT(bp);
2083         static const struct {
2084                 u32 hw;
2085                 u32 offset0;
2086                 u32 offset1;
2087                 u32 mask;
2088         } reg_tbl[] = {
2089 /* 0 */         { BNX2X_CHIP_MASK_ALL,
2090                         BRB1_REG_PAUSE_LOW_THRESHOLD_0, 4, 0x000003ff },
2091                 { BNX2X_CHIP_MASK_ALL,
2092                         DORQ_REG_DB_ADDR0,              4, 0xffffffff },
2093                 { BNX2X_CHIP_MASK_E1X,
2094                         HC_REG_AGG_INT_0,               4, 0x000003ff },
2095                 { BNX2X_CHIP_MASK_ALL,
2096                         PBF_REG_MAC_IF0_ENABLE,         4, 0x00000001 },
2097                 { BNX2X_CHIP_MASK_E1X | BNX2X_CHIP_MASK_E2 | BNX2X_CHIP_MASK_E3,
2098                         PBF_REG_P0_INIT_CRD,            4, 0x000007ff },
2099                 { BNX2X_CHIP_MASK_E3B0,
2100                         PBF_REG_INIT_CRD_Q0,            4, 0x000007ff },
2101                 { BNX2X_CHIP_MASK_ALL,
2102                         PRS_REG_CID_PORT_0,             4, 0x00ffffff },
2103                 { BNX2X_CHIP_MASK_ALL,
2104                         PXP2_REG_PSWRQ_CDU0_L2P,        4, 0x000fffff },
2105                 { BNX2X_CHIP_MASK_ALL,
2106                         PXP2_REG_RQ_CDU0_EFIRST_MEM_ADDR, 8, 0x0003ffff },
2107                 { BNX2X_CHIP_MASK_ALL,
2108                         PXP2_REG_PSWRQ_TM0_L2P,         4, 0x000fffff },
2109 /* 10 */        { BNX2X_CHIP_MASK_ALL,
2110                         PXP2_REG_RQ_USDM0_EFIRST_MEM_ADDR, 8, 0x0003ffff },
2111                 { BNX2X_CHIP_MASK_ALL,
2112                         PXP2_REG_PSWRQ_TSDM0_L2P,       4, 0x000fffff },
2113                 { BNX2X_CHIP_MASK_ALL,
2114                         QM_REG_CONNNUM_0,               4, 0x000fffff },
2115                 { BNX2X_CHIP_MASK_ALL,
2116                         TM_REG_LIN0_MAX_ACTIVE_CID,     4, 0x0003ffff },
2117                 { BNX2X_CHIP_MASK_ALL,
2118                         SRC_REG_KEYRSS0_0,              40, 0xffffffff },
2119                 { BNX2X_CHIP_MASK_ALL,
2120                         SRC_REG_KEYRSS0_7,              40, 0xffffffff },
2121                 { BNX2X_CHIP_MASK_ALL,
2122                         XCM_REG_WU_DA_SET_TMR_CNT_FLG_CMD00, 4, 0x00000001 },
2123                 { BNX2X_CHIP_MASK_ALL,
2124                         XCM_REG_WU_DA_CNT_CMD00,        4, 0x00000003 },
2125                 { BNX2X_CHIP_MASK_ALL,
2126                         XCM_REG_GLB_DEL_ACK_MAX_CNT_0,  4, 0x000000ff },
2127                 { BNX2X_CHIP_MASK_ALL,
2128                         NIG_REG_LLH0_T_BIT,             4, 0x00000001 },
2129 /* 20 */        { BNX2X_CHIP_MASK_E1X | BNX2X_CHIP_MASK_E2,
2130                         NIG_REG_EMAC0_IN_EN,            4, 0x00000001 },
2131                 { BNX2X_CHIP_MASK_E1X | BNX2X_CHIP_MASK_E2,
2132                         NIG_REG_BMAC0_IN_EN,            4, 0x00000001 },
2133                 { BNX2X_CHIP_MASK_ALL,
2134                         NIG_REG_XCM0_OUT_EN,            4, 0x00000001 },
2135                 { BNX2X_CHIP_MASK_ALL,
2136                         NIG_REG_BRB0_OUT_EN,            4, 0x00000001 },
2137                 { BNX2X_CHIP_MASK_ALL,
2138                         NIG_REG_LLH0_XCM_MASK,          4, 0x00000007 },
2139                 { BNX2X_CHIP_MASK_ALL,
2140                         NIG_REG_LLH0_ACPI_PAT_6_LEN,    68, 0x000000ff },
2141                 { BNX2X_CHIP_MASK_ALL,
2142                         NIG_REG_LLH0_ACPI_PAT_0_CRC,    68, 0xffffffff },
2143                 { BNX2X_CHIP_MASK_ALL,
2144                         NIG_REG_LLH0_DEST_MAC_0_0,      160, 0xffffffff },
2145                 { BNX2X_CHIP_MASK_ALL,
2146                         NIG_REG_LLH0_DEST_IP_0_1,       160, 0xffffffff },
2147                 { BNX2X_CHIP_MASK_ALL,
2148                         NIG_REG_LLH0_IPV4_IPV6_0,       160, 0x00000001 },
2149 /* 30 */        { BNX2X_CHIP_MASK_ALL,
2150                         NIG_REG_LLH0_DEST_UDP_0,        160, 0x0000ffff },
2151                 { BNX2X_CHIP_MASK_ALL,
2152                         NIG_REG_LLH0_DEST_TCP_0,        160, 0x0000ffff },
2153                 { BNX2X_CHIP_MASK_ALL,
2154                         NIG_REG_LLH0_VLAN_ID_0, 160, 0x00000fff },
2155                 { BNX2X_CHIP_MASK_E1X | BNX2X_CHIP_MASK_E2,
2156                         NIG_REG_XGXS_SERDES0_MODE_SEL,  4, 0x00000001 },
2157                 { BNX2X_CHIP_MASK_ALL,
2158                         NIG_REG_LED_CONTROL_OVERRIDE_TRAFFIC_P0, 4, 0x00000001},
2159                 { BNX2X_CHIP_MASK_ALL,
2160                         NIG_REG_STATUS_INTERRUPT_PORT0, 4, 0x07ffffff },
2161                 { BNX2X_CHIP_MASK_E1X | BNX2X_CHIP_MASK_E2,
2162                         NIG_REG_XGXS0_CTRL_EXTREMOTEMDIOST, 24, 0x00000001 },
2163                 { BNX2X_CHIP_MASK_E1X | BNX2X_CHIP_MASK_E2,
2164                         NIG_REG_SERDES0_CTRL_PHY_ADDR,  16, 0x0000001f },
2165
2166                 { BNX2X_CHIP_MASK_ALL, 0xffffffff, 0, 0x00000000 }
2167         };
2168
2169         if (!bnx2x_is_nvm_accessible(bp)) {
2170                 DP(BNX2X_MSG_ETHTOOL | BNX2X_MSG_NVM,
2171                    "cannot access eeprom when the interface is down\n");
2172                 return rc;
2173         }
2174
2175         if (CHIP_IS_E1(bp))
2176                 hw = BNX2X_CHIP_MASK_E1;
2177         else if (CHIP_IS_E1H(bp))
2178                 hw = BNX2X_CHIP_MASK_E1H;
2179         else if (CHIP_IS_E2(bp))
2180                 hw = BNX2X_CHIP_MASK_E2;
2181         else if (CHIP_IS_E3B0(bp))
2182                 hw = BNX2X_CHIP_MASK_E3B0;
2183         else /* e3 A0 */
2184                 hw = BNX2X_CHIP_MASK_E3;
2185
2186         /* Repeat the test twice:
2187          * First by writing 0x00000000, second by writing 0xffffffff
2188          */
2189         for (idx = 0; idx < 2; idx++) {
2190
2191                 switch (idx) {
2192                 case 0:
2193                         wr_val = 0;
2194                         break;
2195                 case 1:
2196                         wr_val = 0xffffffff;
2197                         break;
2198                 }
2199
2200                 for (i = 0; reg_tbl[i].offset0 != 0xffffffff; i++) {
2201                         u32 offset, mask, save_val, val;
2202                         if (!(hw & reg_tbl[i].hw))
2203                                 continue;
2204
2205                         offset = reg_tbl[i].offset0 + port*reg_tbl[i].offset1;
2206                         mask = reg_tbl[i].mask;
2207
2208                         save_val = REG_RD(bp, offset);
2209
2210                         REG_WR(bp, offset, wr_val & mask);
2211
2212                         val = REG_RD(bp, offset);
2213
2214                         /* Restore the original register's value */
2215                         REG_WR(bp, offset, save_val);
2216
2217                         /* verify value is as expected */
2218                         if ((val & mask) != (wr_val & mask)) {
2219                                 DP(BNX2X_MSG_ETHTOOL,
2220                                    "offset 0x%x: val 0x%x != 0x%x mask 0x%x\n",
2221                                    offset, val, wr_val, mask);
2222                                 goto test_reg_exit;
2223                         }
2224                 }
2225         }
2226
2227         rc = 0;
2228
2229 test_reg_exit:
2230         return rc;
2231 }
2232
2233 static int bnx2x_test_memory(struct bnx2x *bp)
2234 {
2235         int i, j, rc = -ENODEV;
2236         u32 val, index;
2237         static const struct {
2238                 u32 offset;
2239                 int size;
2240         } mem_tbl[] = {
2241                 { CCM_REG_XX_DESCR_TABLE,   CCM_REG_XX_DESCR_TABLE_SIZE },
2242                 { CFC_REG_ACTIVITY_COUNTER, CFC_REG_ACTIVITY_COUNTER_SIZE },
2243                 { CFC_REG_LINK_LIST,        CFC_REG_LINK_LIST_SIZE },
2244                 { DMAE_REG_CMD_MEM,         DMAE_REG_CMD_MEM_SIZE },
2245                 { TCM_REG_XX_DESCR_TABLE,   TCM_REG_XX_DESCR_TABLE_SIZE },
2246                 { UCM_REG_XX_DESCR_TABLE,   UCM_REG_XX_DESCR_TABLE_SIZE },
2247                 { XCM_REG_XX_DESCR_TABLE,   XCM_REG_XX_DESCR_TABLE_SIZE },
2248
2249                 { 0xffffffff, 0 }
2250         };
2251
2252         static const struct {
2253                 char *name;
2254                 u32 offset;
2255                 u32 hw_mask[BNX2X_CHIP_MAX_OFST];
2256         } prty_tbl[] = {
2257                 { "CCM_PRTY_STS",  CCM_REG_CCM_PRTY_STS,
2258                         {0x3ffc0, 0,   0, 0} },
2259                 { "CFC_PRTY_STS",  CFC_REG_CFC_PRTY_STS,
2260                         {0x2,     0x2, 0, 0} },
2261                 { "DMAE_PRTY_STS", DMAE_REG_DMAE_PRTY_STS,
2262                         {0,       0,   0, 0} },
2263                 { "TCM_PRTY_STS",  TCM_REG_TCM_PRTY_STS,
2264                         {0x3ffc0, 0,   0, 0} },
2265                 { "UCM_PRTY_STS",  UCM_REG_UCM_PRTY_STS,
2266                         {0x3ffc0, 0,   0, 0} },
2267                 { "XCM_PRTY_STS",  XCM_REG_XCM_PRTY_STS,
2268                         {0x3ffc1, 0,   0, 0} },
2269
2270                 { NULL, 0xffffffff, {0, 0, 0, 0} }
2271         };
2272
2273         if (!bnx2x_is_nvm_accessible(bp)) {
2274                 DP(BNX2X_MSG_ETHTOOL | BNX2X_MSG_NVM,
2275                    "cannot access eeprom when the interface is down\n");
2276                 return rc;
2277         }
2278
2279         if (CHIP_IS_E1(bp))
2280                 index = BNX2X_CHIP_E1_OFST;
2281         else if (CHIP_IS_E1H(bp))
2282                 index = BNX2X_CHIP_E1H_OFST;
2283         else if (CHIP_IS_E2(bp))
2284                 index = BNX2X_CHIP_E2_OFST;
2285         else /* e3 */
2286                 index = BNX2X_CHIP_E3_OFST;
2287
2288         /* pre-Check the parity status */
2289         for (i = 0; prty_tbl[i].offset != 0xffffffff; i++) {
2290                 val = REG_RD(bp, prty_tbl[i].offset);
2291                 if (val & ~(prty_tbl[i].hw_mask[index])) {
2292                         DP(BNX2X_MSG_ETHTOOL,
2293                            "%s is 0x%x\n", prty_tbl[i].name, val);
2294                         goto test_mem_exit;
2295                 }
2296         }
2297
2298         /* Go through all the memories */
2299         for (i = 0; mem_tbl[i].offset != 0xffffffff; i++)
2300                 for (j = 0; j < mem_tbl[i].size; j++)
2301                         REG_RD(bp, mem_tbl[i].offset + j*4);
2302
2303         /* Check the parity status */
2304         for (i = 0; prty_tbl[i].offset != 0xffffffff; i++) {
2305                 val = REG_RD(bp, prty_tbl[i].offset);
2306                 if (val & ~(prty_tbl[i].hw_mask[index])) {
2307                         DP(BNX2X_MSG_ETHTOOL,
2308                            "%s is 0x%x\n", prty_tbl[i].name, val);
2309                         goto test_mem_exit;
2310                 }
2311         }
2312
2313         rc = 0;
2314
2315 test_mem_exit:
2316         return rc;
2317 }
2318
2319 static void bnx2x_wait_for_link(struct bnx2x *bp, u8 link_up, u8 is_serdes)
2320 {
2321         int cnt = 1400;
2322
2323         if (link_up) {
2324                 while (bnx2x_link_test(bp, is_serdes) && cnt--)
2325                         msleep(20);
2326
2327                 if (cnt <= 0 && bnx2x_link_test(bp, is_serdes))
2328                         DP(BNX2X_MSG_ETHTOOL, "Timeout waiting for link up\n");
2329
2330                 cnt = 1400;
2331                 while (!bp->link_vars.link_up && cnt--)
2332                         msleep(20);
2333
2334                 if (cnt <= 0 && !bp->link_vars.link_up)
2335                         DP(BNX2X_MSG_ETHTOOL,
2336                            "Timeout waiting for link init\n");
2337         }
2338 }
2339
2340 static int bnx2x_run_loopback(struct bnx2x *bp, int loopback_mode)
2341 {
2342         unsigned int pkt_size, num_pkts, i;
2343         struct sk_buff *skb;
2344         unsigned char *packet;
2345         struct bnx2x_fastpath *fp_rx = &bp->fp[0];
2346         struct bnx2x_fastpath *fp_tx = &bp->fp[0];
2347         struct bnx2x_fp_txdata *txdata = fp_tx->txdata_ptr[0];
2348         u16 tx_start_idx, tx_idx;
2349         u16 rx_start_idx, rx_idx;
2350         u16 pkt_prod, bd_prod;
2351         struct sw_tx_bd *tx_buf;
2352         struct eth_tx_start_bd *tx_start_bd;
2353         dma_addr_t mapping;
2354         union eth_rx_cqe *cqe;
2355         u8 cqe_fp_flags, cqe_fp_type;
2356         struct sw_rx_bd *rx_buf;
2357         u16 len;
2358         int rc = -ENODEV;
2359         u8 *data;
2360         struct netdev_queue *txq = netdev_get_tx_queue(bp->dev,
2361                                                        txdata->txq_index);
2362
2363         /* check the loopback mode */
2364         switch (loopback_mode) {
2365         case BNX2X_PHY_LOOPBACK:
2366                 if (bp->link_params.loopback_mode != LOOPBACK_XGXS) {
2367                         DP(BNX2X_MSG_ETHTOOL, "PHY loopback not supported\n");
2368                         return -EINVAL;
2369                 }
2370                 break;
2371         case BNX2X_MAC_LOOPBACK:
2372                 if (CHIP_IS_E3(bp)) {
2373                         int cfg_idx = bnx2x_get_link_cfg_idx(bp);
2374                         if (bp->port.supported[cfg_idx] &
2375                             (SUPPORTED_10000baseT_Full |
2376                              SUPPORTED_20000baseMLD2_Full |
2377                              SUPPORTED_20000baseKR2_Full))
2378                                 bp->link_params.loopback_mode = LOOPBACK_XMAC;
2379                         else
2380                                 bp->link_params.loopback_mode = LOOPBACK_UMAC;
2381                 } else
2382                         bp->link_params.loopback_mode = LOOPBACK_BMAC;
2383
2384                 bnx2x_phy_init(&bp->link_params, &bp->link_vars);
2385                 break;
2386         case BNX2X_EXT_LOOPBACK:
2387                 if (bp->link_params.loopback_mode != LOOPBACK_EXT) {
2388                         DP(BNX2X_MSG_ETHTOOL,
2389                            "Can't configure external loopback\n");
2390                         return -EINVAL;
2391                 }
2392                 break;
2393         default:
2394                 DP(BNX2X_MSG_ETHTOOL, "Command parameters not supported\n");
2395                 return -EINVAL;
2396         }
2397
2398         /* prepare the loopback packet */
2399         pkt_size = (((bp->dev->mtu < ETH_MAX_PACKET_SIZE) ?
2400                      bp->dev->mtu : ETH_MAX_PACKET_SIZE) + ETH_HLEN);
2401         skb = netdev_alloc_skb(bp->dev, fp_rx->rx_buf_size);
2402         if (!skb) {
2403                 DP(BNX2X_MSG_ETHTOOL, "Can't allocate skb\n");
2404                 rc = -ENOMEM;
2405                 goto test_loopback_exit;
2406         }
2407         packet = skb_put(skb, pkt_size);
2408         memcpy(packet, bp->dev->dev_addr, ETH_ALEN);
2409         memset(packet + ETH_ALEN, 0, ETH_ALEN);
2410         memset(packet + 2*ETH_ALEN, 0x77, (ETH_HLEN - 2*ETH_ALEN));
2411         for (i = ETH_HLEN; i < pkt_size; i++)
2412                 packet[i] = (unsigned char) (i & 0xff);
2413         mapping = dma_map_single(&bp->pdev->dev, skb->data,
2414                                  skb_headlen(skb), DMA_TO_DEVICE);
2415         if (unlikely(dma_mapping_error(&bp->pdev->dev, mapping))) {
2416                 rc = -ENOMEM;
2417                 dev_kfree_skb(skb);
2418                 DP(BNX2X_MSG_ETHTOOL, "Unable to map SKB\n");
2419                 goto test_loopback_exit;
2420         }
2421
2422         /* send the loopback packet */
2423         num_pkts = 0;
2424         tx_start_idx = le16_to_cpu(*txdata->tx_cons_sb);
2425         rx_start_idx = le16_to_cpu(*fp_rx->rx_cons_sb);
2426
2427         netdev_tx_sent_queue(txq, skb->len);
2428
2429         pkt_prod = txdata->tx_pkt_prod++;
2430         tx_buf = &txdata->tx_buf_ring[TX_BD(pkt_prod)];
2431         tx_buf->first_bd = txdata->tx_bd_prod;
2432         tx_buf->skb = skb;
2433         tx_buf->flags = 0;
2434
2435         bd_prod = TX_BD(txdata->tx_bd_prod);
2436         tx_start_bd = &txdata->tx_desc_ring[bd_prod].start_bd;
2437         tx_start_bd->addr_hi = cpu_to_le32(U64_HI(mapping));
2438         tx_start_bd->addr_lo = cpu_to_le32(U64_LO(mapping));
2439         tx_start_bd->nbd = cpu_to_le16(2); /* start + pbd */
2440         tx_start_bd->nbytes = cpu_to_le16(skb_headlen(skb));
2441         tx_start_bd->vlan_or_ethertype = cpu_to_le16(pkt_prod);
2442         tx_start_bd->bd_flags.as_bitfield = ETH_TX_BD_FLAGS_START_BD;
2443         SET_FLAG(tx_start_bd->general_data,
2444                  ETH_TX_START_BD_HDR_NBDS,
2445                  1);
2446         SET_FLAG(tx_start_bd->general_data,
2447                  ETH_TX_START_BD_PARSE_NBDS,
2448                  0);
2449
2450         /* turn on parsing and get a BD */
2451         bd_prod = TX_BD(NEXT_TX_IDX(bd_prod));
2452
2453         if (CHIP_IS_E1x(bp)) {
2454                 u16 global_data = 0;
2455                 struct eth_tx_parse_bd_e1x  *pbd_e1x =
2456                         &txdata->tx_desc_ring[bd_prod].parse_bd_e1x;
2457                 memset(pbd_e1x, 0, sizeof(struct eth_tx_parse_bd_e1x));
2458                 SET_FLAG(global_data,
2459                          ETH_TX_PARSE_BD_E1X_ETH_ADDR_TYPE, UNICAST_ADDRESS);
2460                 pbd_e1x->global_data = cpu_to_le16(global_data);
2461         } else {
2462                 u32 parsing_data = 0;
2463                 struct eth_tx_parse_bd_e2  *pbd_e2 =
2464                         &txdata->tx_desc_ring[bd_prod].parse_bd_e2;
2465                 memset(pbd_e2, 0, sizeof(struct eth_tx_parse_bd_e2));
2466                 SET_FLAG(parsing_data,
2467                          ETH_TX_PARSE_BD_E2_ETH_ADDR_TYPE, UNICAST_ADDRESS);
2468                 pbd_e2->parsing_data = cpu_to_le32(parsing_data);
2469         }
2470         wmb();
2471
2472         txdata->tx_db.data.prod += 2;
2473         barrier();
2474         DOORBELL(bp, txdata->cid, txdata->tx_db.raw);
2475
2476         mmiowb();
2477         barrier();
2478
2479         num_pkts++;
2480         txdata->tx_bd_prod += 2; /* start + pbd */
2481
2482         udelay(100);
2483
2484         tx_idx = le16_to_cpu(*txdata->tx_cons_sb);
2485         if (tx_idx != tx_start_idx + num_pkts)
2486                 goto test_loopback_exit;
2487
2488         /* Unlike HC IGU won't generate an interrupt for status block
2489          * updates that have been performed while interrupts were
2490          * disabled.
2491          */
2492         if (bp->common.int_block == INT_BLOCK_IGU) {
2493                 /* Disable local BHes to prevent a dead-lock situation between
2494                  * sch_direct_xmit() and bnx2x_run_loopback() (calling
2495                  * bnx2x_tx_int()), as both are taking netif_tx_lock().
2496                  */
2497                 local_bh_disable();
2498                 bnx2x_tx_int(bp, txdata);
2499                 local_bh_enable();
2500         }
2501
2502         rx_idx = le16_to_cpu(*fp_rx->rx_cons_sb);
2503         if (rx_idx != rx_start_idx + num_pkts)
2504                 goto test_loopback_exit;
2505
2506         cqe = &fp_rx->rx_comp_ring[RCQ_BD(fp_rx->rx_comp_cons)];
2507         cqe_fp_flags = cqe->fast_path_cqe.type_error_flags;
2508         cqe_fp_type = cqe_fp_flags & ETH_FAST_PATH_RX_CQE_TYPE;
2509         if (!CQE_TYPE_FAST(cqe_fp_type) || (cqe_fp_flags & ETH_RX_ERROR_FALGS))
2510                 goto test_loopback_rx_exit;
2511
2512         len = le16_to_cpu(cqe->fast_path_cqe.pkt_len_or_gro_seg_len);
2513         if (len != pkt_size)
2514                 goto test_loopback_rx_exit;
2515
2516         rx_buf = &fp_rx->rx_buf_ring[RX_BD(fp_rx->rx_bd_cons)];
2517         dma_sync_single_for_cpu(&bp->pdev->dev,
2518                                    dma_unmap_addr(rx_buf, mapping),
2519                                    fp_rx->rx_buf_size, DMA_FROM_DEVICE);
2520         data = rx_buf->data + NET_SKB_PAD + cqe->fast_path_cqe.placement_offset;
2521         for (i = ETH_HLEN; i < pkt_size; i++)
2522                 if (*(data + i) != (unsigned char) (i & 0xff))
2523                         goto test_loopback_rx_exit;
2524
2525         rc = 0;
2526
2527 test_loopback_rx_exit:
2528
2529         fp_rx->rx_bd_cons = NEXT_RX_IDX(fp_rx->rx_bd_cons);
2530         fp_rx->rx_bd_prod = NEXT_RX_IDX(fp_rx->rx_bd_prod);
2531         fp_rx->rx_comp_cons = NEXT_RCQ_IDX(fp_rx->rx_comp_cons);
2532         fp_rx->rx_comp_prod = NEXT_RCQ_IDX(fp_rx->rx_comp_prod);
2533
2534         /* Update producers */
2535         bnx2x_update_rx_prod(bp, fp_rx, fp_rx->rx_bd_prod, fp_rx->rx_comp_prod,
2536                              fp_rx->rx_sge_prod);
2537
2538 test_loopback_exit:
2539         bp->link_params.loopback_mode = LOOPBACK_NONE;
2540
2541         return rc;
2542 }
2543
2544 static int bnx2x_test_loopback(struct bnx2x *bp)
2545 {
2546         int rc = 0, res;
2547
2548         if (BP_NOMCP(bp))
2549                 return rc;
2550
2551         if (!netif_running(bp->dev))
2552                 return BNX2X_LOOPBACK_FAILED;
2553
2554         bnx2x_netif_stop(bp, 1);
2555         bnx2x_acquire_phy_lock(bp);
2556
2557         res = bnx2x_run_loopback(bp, BNX2X_PHY_LOOPBACK);
2558         if (res) {
2559                 DP(BNX2X_MSG_ETHTOOL, "  PHY loopback failed  (res %d)\n", res);
2560                 rc |= BNX2X_PHY_LOOPBACK_FAILED;
2561         }
2562
2563         res = bnx2x_run_loopback(bp, BNX2X_MAC_LOOPBACK);
2564         if (res) {
2565                 DP(BNX2X_MSG_ETHTOOL, "  MAC loopback failed  (res %d)\n", res);
2566                 rc |= BNX2X_MAC_LOOPBACK_FAILED;
2567         }
2568
2569         bnx2x_release_phy_lock(bp);
2570         bnx2x_netif_start(bp);
2571
2572         return rc;
2573 }
2574
2575 static int bnx2x_test_ext_loopback(struct bnx2x *bp)
2576 {
2577         int rc;
2578         u8 is_serdes =
2579                 (bp->link_vars.link_status & LINK_STATUS_SERDES_LINK) > 0;
2580
2581         if (BP_NOMCP(bp))
2582                 return -ENODEV;
2583
2584         if (!netif_running(bp->dev))
2585                 return BNX2X_EXT_LOOPBACK_FAILED;
2586
2587         bnx2x_nic_unload(bp, UNLOAD_NORMAL, false);
2588         rc = bnx2x_nic_load(bp, LOAD_LOOPBACK_EXT);
2589         if (rc) {
2590                 DP(BNX2X_MSG_ETHTOOL,
2591                    "Can't perform self-test, nic_load (for external lb) failed\n");
2592                 return -ENODEV;
2593         }
2594         bnx2x_wait_for_link(bp, 1, is_serdes);
2595
2596         bnx2x_netif_stop(bp, 1);
2597
2598         rc = bnx2x_run_loopback(bp, BNX2X_EXT_LOOPBACK);
2599         if (rc)
2600                 DP(BNX2X_MSG_ETHTOOL, "EXT loopback failed  (res %d)\n", rc);
2601
2602         bnx2x_netif_start(bp);
2603
2604         return rc;
2605 }
2606
2607 struct code_entry {
2608         u32 sram_start_addr;
2609         u32 code_attribute;
2610 #define CODE_IMAGE_TYPE_MASK                    0xf0800003
2611 #define CODE_IMAGE_VNTAG_PROFILES_DATA          0xd0000003
2612 #define CODE_IMAGE_LENGTH_MASK                  0x007ffffc
2613 #define CODE_IMAGE_TYPE_EXTENDED_DIR            0xe0000000
2614         u32 nvm_start_addr;
2615 };
2616
2617 #define CODE_ENTRY_MAX                  16
2618 #define CODE_ENTRY_EXTENDED_DIR_IDX     15
2619 #define MAX_IMAGES_IN_EXTENDED_DIR      64
2620 #define NVRAM_DIR_OFFSET                0x14
2621
2622 #define EXTENDED_DIR_EXISTS(code)                                         \
2623         ((code & CODE_IMAGE_TYPE_MASK) == CODE_IMAGE_TYPE_EXTENDED_DIR && \
2624          (code & CODE_IMAGE_LENGTH_MASK) != 0)
2625
2626 #define CRC32_RESIDUAL                  0xdebb20e3
2627 #define CRC_BUFF_SIZE                   256
2628
2629 static int bnx2x_nvram_crc(struct bnx2x *bp,
2630                            int offset,
2631                            int size,
2632                            u8 *buff)
2633 {
2634         u32 crc = ~0;
2635         int rc = 0, done = 0;
2636
2637         DP(BNX2X_MSG_ETHTOOL | BNX2X_MSG_NVM,
2638            "NVRAM CRC from 0x%08x to 0x%08x\n", offset, offset + size);
2639
2640         while (done < size) {
2641                 int count = min_t(int, size - done, CRC_BUFF_SIZE);
2642
2643                 rc = bnx2x_nvram_read(bp, offset + done, buff, count);
2644
2645                 if (rc)
2646                         return rc;
2647
2648                 crc = crc32_le(crc, buff, count);
2649                 done += count;
2650         }
2651
2652         if (crc != CRC32_RESIDUAL)
2653                 rc = -EINVAL;
2654
2655         return rc;
2656 }
2657
2658 static int bnx2x_test_nvram_dir(struct bnx2x *bp,
2659                                 struct code_entry *entry,
2660                                 u8 *buff)
2661 {
2662         size_t size = entry->code_attribute & CODE_IMAGE_LENGTH_MASK;
2663         u32 type = entry->code_attribute & CODE_IMAGE_TYPE_MASK;
2664         int rc;
2665
2666         /* Zero-length images and AFEX profiles do not have CRC */
2667         if (size == 0 || type == CODE_IMAGE_VNTAG_PROFILES_DATA)
2668                 return 0;
2669
2670         rc = bnx2x_nvram_crc(bp, entry->nvm_start_addr, size, buff);
2671         if (rc)
2672                 DP(BNX2X_MSG_ETHTOOL | BNX2X_MSG_NVM,
2673                    "image %x has failed crc test (rc %d)\n", type, rc);
2674
2675         return rc;
2676 }
2677
2678 static int bnx2x_test_dir_entry(struct bnx2x *bp, u32 addr, u8 *buff)
2679 {
2680         int rc;
2681         struct code_entry entry;
2682
2683         rc = bnx2x_nvram_read32(bp, addr, (u32 *)&entry, sizeof(entry));
2684         if (rc)
2685                 return rc;
2686
2687         return bnx2x_test_nvram_dir(bp, &entry, buff);
2688 }
2689
2690 static int bnx2x_test_nvram_ext_dirs(struct bnx2x *bp, u8 *buff)
2691 {
2692         u32 rc, cnt, dir_offset = NVRAM_DIR_OFFSET;
2693         struct code_entry entry;
2694         int i;
2695
2696         rc = bnx2x_nvram_read32(bp,
2697                                 dir_offset +
2698                                 sizeof(entry) * CODE_ENTRY_EXTENDED_DIR_IDX,
2699                                 (u32 *)&entry, sizeof(entry));
2700         if (rc)
2701                 return rc;
2702
2703         if (!EXTENDED_DIR_EXISTS(entry.code_attribute))
2704                 return 0;
2705
2706         rc = bnx2x_nvram_read32(bp, entry.nvm_start_addr,
2707                                 &cnt, sizeof(u32));
2708         if (rc)
2709                 return rc;
2710
2711         dir_offset = entry.nvm_start_addr + 8;
2712
2713         for (i = 0; i < cnt && i < MAX_IMAGES_IN_EXTENDED_DIR; i++) {
2714                 rc = bnx2x_test_dir_entry(bp, dir_offset +
2715                                               sizeof(struct code_entry) * i,
2716                                           buff);
2717                 if (rc)
2718                         return rc;
2719         }
2720
2721         return 0;
2722 }
2723
2724 static int bnx2x_test_nvram_dirs(struct bnx2x *bp, u8 *buff)
2725 {
2726         u32 rc, dir_offset = NVRAM_DIR_OFFSET;
2727         int i;
2728
2729         DP(BNX2X_MSG_ETHTOOL | BNX2X_MSG_NVM, "NVRAM DIRS CRC test-set\n");
2730
2731         for (i = 0; i < CODE_ENTRY_EXTENDED_DIR_IDX; i++) {
2732                 rc = bnx2x_test_dir_entry(bp, dir_offset +
2733                                               sizeof(struct code_entry) * i,
2734                                           buff);
2735                 if (rc)
2736                         return rc;
2737         }
2738
2739         return bnx2x_test_nvram_ext_dirs(bp, buff);
2740 }
2741
2742 struct crc_pair {
2743         int offset;
2744         int size;
2745 };
2746
2747 static int bnx2x_test_nvram_tbl(struct bnx2x *bp,
2748                                 const struct crc_pair *nvram_tbl, u8 *buf)
2749 {
2750         int i;
2751
2752         for (i = 0; nvram_tbl[i].size; i++) {
2753                 int rc = bnx2x_nvram_crc(bp, nvram_tbl[i].offset,
2754                                          nvram_tbl[i].size, buf);
2755                 if (rc) {
2756                         DP(BNX2X_MSG_ETHTOOL | BNX2X_MSG_NVM,
2757                            "nvram_tbl[%d] has failed crc test (rc %d)\n",
2758                            i, rc);
2759                         return rc;
2760                 }
2761         }
2762
2763         return 0;
2764 }
2765
2766 static int bnx2x_test_nvram(struct bnx2x *bp)
2767 {
2768         const struct crc_pair nvram_tbl[] = {
2769                 {     0,  0x14 }, /* bootstrap */
2770                 {  0x14,  0xec }, /* dir */
2771                 { 0x100, 0x350 }, /* manuf_info */
2772                 { 0x450,  0xf0 }, /* feature_info */
2773                 { 0x640,  0x64 }, /* upgrade_key_info */
2774                 { 0x708,  0x70 }, /* manuf_key_info */
2775                 {     0,     0 }
2776         };
2777         const struct crc_pair nvram_tbl2[] = {
2778                 { 0x7e8, 0x350 }, /* manuf_info2 */
2779                 { 0xb38,  0xf0 }, /* feature_info */
2780                 {     0,     0 }
2781         };
2782
2783         u8 *buf;
2784         int rc;
2785         u32 magic;
2786
2787         if (BP_NOMCP(bp))
2788                 return 0;
2789
2790         buf = kmalloc(CRC_BUFF_SIZE, GFP_KERNEL);
2791         if (!buf) {
2792                 DP(BNX2X_MSG_ETHTOOL | BNX2X_MSG_NVM, "kmalloc failed\n");
2793                 rc = -ENOMEM;
2794                 goto test_nvram_exit;
2795         }
2796
2797         rc = bnx2x_nvram_read32(bp, 0, &magic, sizeof(magic));
2798         if (rc) {
2799                 DP(BNX2X_MSG_ETHTOOL | BNX2X_MSG_NVM,
2800                    "magic value read (rc %d)\n", rc);
2801                 goto test_nvram_exit;
2802         }
2803
2804         if (magic != 0x669955aa) {
2805                 DP(BNX2X_MSG_ETHTOOL | BNX2X_MSG_NVM,
2806                    "wrong magic value (0x%08x)\n", magic);
2807                 rc = -ENODEV;
2808                 goto test_nvram_exit;
2809         }
2810
2811         DP(BNX2X_MSG_ETHTOOL | BNX2X_MSG_NVM, "Port 0 CRC test-set\n");
2812         rc = bnx2x_test_nvram_tbl(bp, nvram_tbl, buf);
2813         if (rc)
2814                 goto test_nvram_exit;
2815
2816         if (!CHIP_IS_E1x(bp) && !CHIP_IS_57811xx(bp)) {
2817                 u32 hide = SHMEM_RD(bp, dev_info.shared_hw_config.config2) &
2818                            SHARED_HW_CFG_HIDE_PORT1;
2819
2820                 if (!hide) {
2821                         DP(BNX2X_MSG_ETHTOOL | BNX2X_MSG_NVM,
2822                            "Port 1 CRC test-set\n");
2823                         rc = bnx2x_test_nvram_tbl(bp, nvram_tbl2, buf);
2824                         if (rc)
2825                                 goto test_nvram_exit;
2826                 }
2827         }
2828
2829         rc = bnx2x_test_nvram_dirs(bp, buf);
2830
2831 test_nvram_exit:
2832         kfree(buf);
2833         return rc;
2834 }
2835
2836 /* Send an EMPTY ramrod on the first queue */
2837 static int bnx2x_test_intr(struct bnx2x *bp)
2838 {
2839         struct bnx2x_queue_state_params params = {NULL};
2840
2841         if (!netif_running(bp->dev)) {
2842                 DP(BNX2X_MSG_ETHTOOL | BNX2X_MSG_NVM,
2843                    "cannot access eeprom when the interface is down\n");
2844                 return -ENODEV;
2845         }
2846
2847         params.q_obj = &bp->sp_objs->q_obj;
2848         params.cmd = BNX2X_Q_CMD_EMPTY;
2849
2850         __set_bit(RAMROD_COMP_WAIT, &params.ramrod_flags);
2851
2852         return bnx2x_queue_state_change(bp, &params);
2853 }
2854
2855 static void bnx2x_self_test(struct net_device *dev,
2856                             struct ethtool_test *etest, u64 *buf)
2857 {
2858         struct bnx2x *bp = netdev_priv(dev);
2859         u8 is_serdes, link_up;
2860         int rc, cnt = 0;
2861
2862         if (bp->recovery_state != BNX2X_RECOVERY_DONE) {
2863                 netdev_err(bp->dev,
2864                            "Handling parity error recovery. Try again later\n");
2865                 etest->flags |= ETH_TEST_FL_FAILED;
2866                 return;
2867         }
2868
2869         DP(BNX2X_MSG_ETHTOOL,
2870            "Self-test command parameters: offline = %d, external_lb = %d\n",
2871            (etest->flags & ETH_TEST_FL_OFFLINE),
2872            (etest->flags & ETH_TEST_FL_EXTERNAL_LB)>>2);
2873
2874         memset(buf, 0, sizeof(u64) * BNX2X_NUM_TESTS(bp));
2875
2876         if (bnx2x_test_nvram(bp) != 0) {
2877                 if (!IS_MF(bp))
2878                         buf[4] = 1;
2879                 else
2880                         buf[0] = 1;
2881                 etest->flags |= ETH_TEST_FL_FAILED;
2882         }
2883
2884         if (!netif_running(dev)) {
2885                 DP(BNX2X_MSG_ETHTOOL, "Interface is down\n");
2886                 return;
2887         }
2888
2889         is_serdes = (bp->link_vars.link_status & LINK_STATUS_SERDES_LINK) > 0;
2890         link_up = bp->link_vars.link_up;
2891         /* offline tests are not supported in MF mode */
2892         if ((etest->flags & ETH_TEST_FL_OFFLINE) && !IS_MF(bp)) {
2893                 int port = BP_PORT(bp);
2894                 u32 val;
2895
2896                 /* save current value of input enable for TX port IF */
2897                 val = REG_RD(bp, NIG_REG_EGRESS_UMP0_IN_EN + port*4);
2898                 /* disable input for TX port IF */
2899                 REG_WR(bp, NIG_REG_EGRESS_UMP0_IN_EN + port*4, 0);
2900
2901                 bnx2x_nic_unload(bp, UNLOAD_NORMAL, false);
2902                 rc = bnx2x_nic_load(bp, LOAD_DIAG);
2903                 if (rc) {
2904                         etest->flags |= ETH_TEST_FL_FAILED;
2905                         DP(BNX2X_MSG_ETHTOOL,
2906                            "Can't perform self-test, nic_load (for offline) failed\n");
2907                         return;
2908                 }
2909
2910                 /* wait until link state is restored */
2911                 bnx2x_wait_for_link(bp, 1, is_serdes);
2912
2913                 if (bnx2x_test_registers(bp) != 0) {
2914                         buf[0] = 1;
2915                         etest->flags |= ETH_TEST_FL_FAILED;
2916                 }
2917                 if (bnx2x_test_memory(bp) != 0) {
2918                         buf[1] = 1;
2919                         etest->flags |= ETH_TEST_FL_FAILED;
2920                 }
2921
2922                 buf[2] = bnx2x_test_loopback(bp); /* internal LB */
2923                 if (buf[2] != 0)
2924                         etest->flags |= ETH_TEST_FL_FAILED;
2925
2926                 if (etest->flags & ETH_TEST_FL_EXTERNAL_LB) {
2927                         buf[3] = bnx2x_test_ext_loopback(bp); /* external LB */
2928                         if (buf[3] != 0)
2929                                 etest->flags |= ETH_TEST_FL_FAILED;
2930                         etest->flags |= ETH_TEST_FL_EXTERNAL_LB_DONE;
2931                 }
2932
2933                 bnx2x_nic_unload(bp, UNLOAD_NORMAL, false);
2934
2935                 /* restore input for TX port IF */
2936                 REG_WR(bp, NIG_REG_EGRESS_UMP0_IN_EN + port*4, val);
2937                 rc = bnx2x_nic_load(bp, LOAD_NORMAL);
2938                 if (rc) {
2939                         etest->flags |= ETH_TEST_FL_FAILED;
2940                         DP(BNX2X_MSG_ETHTOOL,
2941                            "Can't perform self-test, nic_load (for online) failed\n");
2942                         return;
2943                 }
2944                 /* wait until link state is restored */
2945                 bnx2x_wait_for_link(bp, link_up, is_serdes);
2946         }
2947
2948         if (bnx2x_test_intr(bp) != 0) {
2949                 if (!IS_MF(bp))
2950                         buf[5] = 1;
2951                 else
2952                         buf[1] = 1;
2953                 etest->flags |= ETH_TEST_FL_FAILED;
2954         }
2955
2956         if (link_up) {
2957                 cnt = 100;
2958                 while (bnx2x_link_test(bp, is_serdes) && --cnt)
2959                         msleep(20);
2960         }
2961
2962         if (!cnt) {
2963                 if (!IS_MF(bp))
2964                         buf[6] = 1;
2965                 else
2966                         buf[2] = 1;
2967                 etest->flags |= ETH_TEST_FL_FAILED;
2968         }
2969 }
2970
2971 #define IS_PORT_STAT(i) \
2972         ((bnx2x_stats_arr[i].flags & STATS_FLAGS_BOTH) == STATS_FLAGS_PORT)
2973 #define IS_FUNC_STAT(i)         (bnx2x_stats_arr[i].flags & STATS_FLAGS_FUNC)
2974 #define IS_MF_MODE_STAT(bp) \
2975                         (IS_MF(bp) && !(bp->msg_enable & BNX2X_MSG_STATS))
2976
2977 /* ethtool statistics are displayed for all regular ethernet queues and the
2978  * fcoe L2 queue if not disabled
2979  */
2980 static int bnx2x_num_stat_queues(struct bnx2x *bp)
2981 {
2982         return BNX2X_NUM_ETH_QUEUES(bp);
2983 }
2984
2985 static int bnx2x_get_sset_count(struct net_device *dev, int stringset)
2986 {
2987         struct bnx2x *bp = netdev_priv(dev);
2988         int i, num_strings = 0;
2989
2990         switch (stringset) {
2991         case ETH_SS_STATS:
2992                 if (is_multi(bp)) {
2993                         num_strings = bnx2x_num_stat_queues(bp) *
2994                                       BNX2X_NUM_Q_STATS;
2995                 } else
2996                         num_strings = 0;
2997                 if (IS_MF_MODE_STAT(bp)) {
2998                         for (i = 0; i < BNX2X_NUM_STATS; i++)
2999                                 if (IS_FUNC_STAT(i))
3000                                         num_strings++;
3001                 } else
3002                         num_strings += BNX2X_NUM_STATS;
3003
3004                 return num_strings;
3005
3006         case ETH_SS_TEST:
3007                 return BNX2X_NUM_TESTS(bp);
3008
3009         case ETH_SS_PRIV_FLAGS:
3010                 return BNX2X_PRI_FLAG_LEN;
3011
3012         default:
3013                 return -EINVAL;
3014         }
3015 }
3016
3017 static u32 bnx2x_get_private_flags(struct net_device *dev)
3018 {
3019         struct bnx2x *bp = netdev_priv(dev);
3020         u32 flags = 0;
3021
3022         flags |= (!(bp->flags & NO_ISCSI_FLAG) ? 1 : 0) << BNX2X_PRI_FLAG_ISCSI;
3023         flags |= (!(bp->flags & NO_FCOE_FLAG)  ? 1 : 0) << BNX2X_PRI_FLAG_FCOE;
3024         flags |= (!!IS_MF_STORAGE_ONLY(bp)) << BNX2X_PRI_FLAG_STORAGE;
3025
3026         return flags;
3027 }
3028
3029 static void bnx2x_get_strings(struct net_device *dev, u32 stringset, u8 *buf)
3030 {
3031         struct bnx2x *bp = netdev_priv(dev);
3032         int i, j, k, start;
3033         char queue_name[MAX_QUEUE_NAME_LEN+1];
3034
3035         switch (stringset) {
3036         case ETH_SS_STATS:
3037                 k = 0;
3038                 if (is_multi(bp)) {
3039                         for_each_eth_queue(bp, i) {
3040                                 memset(queue_name, 0, sizeof(queue_name));
3041                                 sprintf(queue_name, "%d", i);
3042                                 for (j = 0; j < BNX2X_NUM_Q_STATS; j++)
3043                                         snprintf(buf + (k + j)*ETH_GSTRING_LEN,
3044                                                 ETH_GSTRING_LEN,
3045                                                 bnx2x_q_stats_arr[j].string,
3046                                                 queue_name);
3047                                 k += BNX2X_NUM_Q_STATS;
3048                         }
3049                 }
3050
3051                 for (i = 0, j = 0; i < BNX2X_NUM_STATS; i++) {
3052                         if (IS_MF_MODE_STAT(bp) && IS_PORT_STAT(i))
3053                                 continue;
3054                         strcpy(buf + (k + j)*ETH_GSTRING_LEN,
3055                                    bnx2x_stats_arr[i].string);
3056                         j++;
3057                 }
3058
3059                 break;
3060
3061         case ETH_SS_TEST:
3062                 /* First 4 tests cannot be done in MF mode */
3063                 if (!IS_MF(bp))
3064                         start = 0;
3065                 else
3066                         start = 4;
3067                 memcpy(buf, bnx2x_tests_str_arr + start,
3068                        ETH_GSTRING_LEN * BNX2X_NUM_TESTS(bp));
3069                 break;
3070
3071         case ETH_SS_PRIV_FLAGS:
3072                 memcpy(buf, bnx2x_private_arr,
3073                        ETH_GSTRING_LEN * BNX2X_PRI_FLAG_LEN);
3074                 break;
3075         }
3076 }
3077
3078 static void bnx2x_get_ethtool_stats(struct net_device *dev,
3079                                     struct ethtool_stats *stats, u64 *buf)
3080 {
3081         struct bnx2x *bp = netdev_priv(dev);
3082         u32 *hw_stats, *offset;
3083         int i, j, k = 0;
3084
3085         if (is_multi(bp)) {
3086                 for_each_eth_queue(bp, i) {
3087                         hw_stats = (u32 *)&bp->fp_stats[i].eth_q_stats;
3088                         for (j = 0; j < BNX2X_NUM_Q_STATS; j++) {
3089                                 if (bnx2x_q_stats_arr[j].size == 0) {
3090                                         /* skip this counter */
3091                                         buf[k + j] = 0;
3092                                         continue;
3093                                 }
3094                                 offset = (hw_stats +
3095                                           bnx2x_q_stats_arr[j].offset);
3096                                 if (bnx2x_q_stats_arr[j].size == 4) {
3097                                         /* 4-byte counter */
3098                                         buf[k + j] = (u64) *offset;
3099                                         continue;
3100                                 }
3101                                 /* 8-byte counter */
3102                                 buf[k + j] = HILO_U64(*offset, *(offset + 1));
3103                         }
3104                         k += BNX2X_NUM_Q_STATS;
3105                 }
3106         }
3107
3108         hw_stats = (u32 *)&bp->eth_stats;
3109         for (i = 0, j = 0; i < BNX2X_NUM_STATS; i++) {
3110                 if (IS_MF_MODE_STAT(bp) && IS_PORT_STAT(i))
3111                         continue;
3112                 if (bnx2x_stats_arr[i].size == 0) {
3113                         /* skip this counter */
3114                         buf[k + j] = 0;
3115                         j++;
3116                         continue;
3117                 }
3118                 offset = (hw_stats + bnx2x_stats_arr[i].offset);
3119                 if (bnx2x_stats_arr[i].size == 4) {
3120                         /* 4-byte counter */
3121                         buf[k + j] = (u64) *offset;
3122                         j++;
3123                         continue;
3124                 }
3125                 /* 8-byte counter */
3126                 buf[k + j] = HILO_U64(*offset, *(offset + 1));
3127                 j++;
3128         }
3129 }
3130
3131 static int bnx2x_set_phys_id(struct net_device *dev,
3132                              enum ethtool_phys_id_state state)
3133 {
3134         struct bnx2x *bp = netdev_priv(dev);
3135
3136         if (!bnx2x_is_nvm_accessible(bp)) {
3137                 DP(BNX2X_MSG_ETHTOOL | BNX2X_MSG_NVM,
3138                    "cannot access eeprom when the interface is down\n");
3139                 return -EAGAIN;
3140         }
3141
3142         switch (state) {
3143         case ETHTOOL_ID_ACTIVE:
3144                 return 1;       /* cycle on/off once per second */
3145
3146         case ETHTOOL_ID_ON:
3147                 bnx2x_acquire_phy_lock(bp);
3148                 bnx2x_set_led(&bp->link_params, &bp->link_vars,
3149                               LED_MODE_ON, SPEED_1000);
3150                 bnx2x_release_phy_lock(bp);
3151                 break;
3152
3153         case ETHTOOL_ID_OFF:
3154                 bnx2x_acquire_phy_lock(bp);
3155                 bnx2x_set_led(&bp->link_params, &bp->link_vars,
3156                               LED_MODE_FRONT_PANEL_OFF, 0);
3157                 bnx2x_release_phy_lock(bp);
3158                 break;
3159
3160         case ETHTOOL_ID_INACTIVE:
3161                 bnx2x_acquire_phy_lock(bp);
3162                 bnx2x_set_led(&bp->link_params, &bp->link_vars,
3163                               LED_MODE_OPER,
3164                               bp->link_vars.line_speed);
3165                 bnx2x_release_phy_lock(bp);
3166         }
3167
3168         return 0;
3169 }
3170
3171 static int bnx2x_get_rss_flags(struct bnx2x *bp, struct ethtool_rxnfc *info)
3172 {
3173         switch (info->flow_type) {
3174         case TCP_V4_FLOW:
3175         case TCP_V6_FLOW:
3176                 info->data = RXH_IP_SRC | RXH_IP_DST |
3177                              RXH_L4_B_0_1 | RXH_L4_B_2_3;
3178                 break;
3179         case UDP_V4_FLOW:
3180                 if (bp->rss_conf_obj.udp_rss_v4)
3181                         info->data = RXH_IP_SRC | RXH_IP_DST |
3182                                      RXH_L4_B_0_1 | RXH_L4_B_2_3;
3183                 else
3184                         info->data = RXH_IP_SRC | RXH_IP_DST;
3185                 break;
3186         case UDP_V6_FLOW:
3187                 if (bp->rss_conf_obj.udp_rss_v6)
3188                         info->data = RXH_IP_SRC | RXH_IP_DST |
3189                                      RXH_L4_B_0_1 | RXH_L4_B_2_3;
3190                 else
3191                         info->data = RXH_IP_SRC | RXH_IP_DST;
3192                 break;
3193         case IPV4_FLOW:
3194         case IPV6_FLOW:
3195                 info->data = RXH_IP_SRC | RXH_IP_DST;
3196                 break;
3197         default:
3198                 info->data = 0;
3199                 break;
3200         }
3201
3202         return 0;
3203 }
3204
3205 static int bnx2x_get_rxnfc(struct net_device *dev, struct ethtool_rxnfc *info,
3206                            u32 *rules __always_unused)
3207 {
3208         struct bnx2x *bp = netdev_priv(dev);
3209
3210         switch (info->cmd) {
3211         case ETHTOOL_GRXRINGS:
3212                 info->data = BNX2X_NUM_ETH_QUEUES(bp);
3213                 return 0;
3214         case ETHTOOL_GRXFH:
3215                 return bnx2x_get_rss_flags(bp, info);
3216         default:
3217                 DP(BNX2X_MSG_ETHTOOL, "Command parameters not supported\n");
3218                 return -EOPNOTSUPP;
3219         }
3220 }
3221
3222 static int bnx2x_set_rss_flags(struct bnx2x *bp, struct ethtool_rxnfc *info)
3223 {
3224         int udp_rss_requested;
3225
3226         DP(BNX2X_MSG_ETHTOOL,
3227            "Set rss flags command parameters: flow type = %d, data = %llu\n",
3228            info->flow_type, info->data);
3229
3230         switch (info->flow_type) {
3231         case TCP_V4_FLOW:
3232         case TCP_V6_FLOW:
3233                 /* For TCP only 4-tupple hash is supported */
3234                 if (info->data ^ (RXH_IP_SRC | RXH_IP_DST |
3235                                   RXH_L4_B_0_1 | RXH_L4_B_2_3)) {
3236                         DP(BNX2X_MSG_ETHTOOL,
3237                            "Command parameters not supported\n");
3238                         return -EINVAL;
3239                 }
3240                 return 0;
3241
3242         case UDP_V4_FLOW:
3243         case UDP_V6_FLOW:
3244                 /* For UDP either 2-tupple hash or 4-tupple hash is supported */
3245                 if (info->data == (RXH_IP_SRC | RXH_IP_DST |
3246                                    RXH_L4_B_0_1 | RXH_L4_B_2_3))
3247                         udp_rss_requested = 1;
3248                 else if (info->data == (RXH_IP_SRC | RXH_IP_DST))
3249                         udp_rss_requested = 0;
3250                 else
3251                         return -EINVAL;
3252                 if ((info->flow_type == UDP_V4_FLOW) &&
3253                     (bp->rss_conf_obj.udp_rss_v4 != udp_rss_requested)) {
3254                         bp->rss_conf_obj.udp_rss_v4 = udp_rss_requested;
3255                         DP(BNX2X_MSG_ETHTOOL,
3256                            "rss re-configured, UDP 4-tupple %s\n",
3257                            udp_rss_requested ? "enabled" : "disabled");
3258                         return bnx2x_rss(bp, &bp->rss_conf_obj, false, true);
3259                 } else if ((info->flow_type == UDP_V6_FLOW) &&
3260                            (bp->rss_conf_obj.udp_rss_v6 != udp_rss_requested)) {
3261                         bp->rss_conf_obj.udp_rss_v6 = udp_rss_requested;
3262                         DP(BNX2X_MSG_ETHTOOL,
3263                            "rss re-configured, UDP 4-tupple %s\n",
3264                            udp_rss_requested ? "enabled" : "disabled");
3265                         return bnx2x_rss(bp, &bp->rss_conf_obj, false, true);
3266                 }
3267                 return 0;
3268
3269         case IPV4_FLOW:
3270         case IPV6_FLOW:
3271                 /* For IP only 2-tupple hash is supported */
3272                 if (info->data ^ (RXH_IP_SRC | RXH_IP_DST)) {
3273                         DP(BNX2X_MSG_ETHTOOL,
3274                            "Command parameters not supported\n");
3275                         return -EINVAL;
3276                 }
3277                 return 0;
3278
3279         case SCTP_V4_FLOW:
3280         case AH_ESP_V4_FLOW:
3281         case AH_V4_FLOW:
3282         case ESP_V4_FLOW:
3283         case SCTP_V6_FLOW:
3284         case AH_ESP_V6_FLOW:
3285         case AH_V6_FLOW:
3286         case ESP_V6_FLOW:
3287         case IP_USER_FLOW:
3288         case ETHER_FLOW:
3289                 /* RSS is not supported for these protocols */
3290                 if (info->data) {
3291                         DP(BNX2X_MSG_ETHTOOL,
3292                            "Command parameters not supported\n");
3293                         return -EINVAL;
3294                 }
3295                 return 0;
3296
3297         default:
3298                 return -EINVAL;
3299         }
3300 }
3301
3302 static int bnx2x_set_rxnfc(struct net_device *dev, struct ethtool_rxnfc *info)
3303 {
3304         struct bnx2x *bp = netdev_priv(dev);
3305
3306         switch (info->cmd) {
3307         case ETHTOOL_SRXFH:
3308                 return bnx2x_set_rss_flags(bp, info);
3309         default:
3310                 DP(BNX2X_MSG_ETHTOOL, "Command parameters not supported\n");
3311                 return -EOPNOTSUPP;
3312         }
3313 }
3314
3315 static u32 bnx2x_get_rxfh_indir_size(struct net_device *dev)
3316 {
3317         return T_ETH_INDIRECTION_TABLE_SIZE;
3318 }
3319
3320 static int bnx2x_get_rxfh_indir(struct net_device *dev, u32 *indir)
3321 {
3322         struct bnx2x *bp = netdev_priv(dev);
3323         u8 ind_table[T_ETH_INDIRECTION_TABLE_SIZE] = {0};
3324         size_t i;
3325
3326         /* Get the current configuration of the RSS indirection table */
3327         bnx2x_get_rss_ind_table(&bp->rss_conf_obj, ind_table);
3328
3329         /*
3330          * We can't use a memcpy() as an internal storage of an
3331          * indirection table is a u8 array while indir->ring_index
3332          * points to an array of u32.
3333          *
3334          * Indirection table contains the FW Client IDs, so we need to
3335          * align the returned table to the Client ID of the leading RSS
3336          * queue.
3337          */
3338         for (i = 0; i < T_ETH_INDIRECTION_TABLE_SIZE; i++)
3339                 indir[i] = ind_table[i] - bp->fp->cl_id;
3340
3341         return 0;
3342 }
3343
3344 static int bnx2x_set_rxfh_indir(struct net_device *dev, const u32 *indir)
3345 {
3346         struct bnx2x *bp = netdev_priv(dev);
3347         size_t i;
3348
3349         for (i = 0; i < T_ETH_INDIRECTION_TABLE_SIZE; i++) {
3350                 /*
3351                  * The same as in bnx2x_get_rxfh_indir: we can't use a memcpy()
3352                  * as an internal storage of an indirection table is a u8 array
3353                  * while indir->ring_index points to an array of u32.
3354                  *
3355                  * Indirection table contains the FW Client IDs, so we need to
3356                  * align the received table to the Client ID of the leading RSS
3357                  * queue
3358                  */
3359                 bp->rss_conf_obj.ind_table[i] = indir[i] + bp->fp->cl_id;
3360         }
3361
3362         return bnx2x_config_rss_eth(bp, false);
3363 }
3364
3365 /**
3366  * bnx2x_get_channels - gets the number of RSS queues.
3367  *
3368  * @dev:                net device
3369  * @channels:           returns the number of max / current queues
3370  */
3371 static void bnx2x_get_channels(struct net_device *dev,
3372                                struct ethtool_channels *channels)
3373 {
3374         struct bnx2x *bp = netdev_priv(dev);
3375
3376         channels->max_combined = BNX2X_MAX_RSS_COUNT(bp);
3377         channels->combined_count = BNX2X_NUM_ETH_QUEUES(bp);
3378 }
3379
3380 /**
3381  * bnx2x_change_num_queues - change the number of RSS queues.
3382  *
3383  * @bp:                 bnx2x private structure
3384  *
3385  * Re-configure interrupt mode to get the new number of MSI-X
3386  * vectors and re-add NAPI objects.
3387  */
3388 static void bnx2x_change_num_queues(struct bnx2x *bp, int num_rss)
3389 {
3390         bnx2x_disable_msi(bp);
3391         bp->num_ethernet_queues = num_rss;
3392         bp->num_queues = bp->num_ethernet_queues + bp->num_cnic_queues;
3393         BNX2X_DEV_INFO("set number of queues to %d\n", bp->num_queues);
3394         bnx2x_set_int_mode(bp);
3395 }
3396
3397 /**
3398  * bnx2x_set_channels - sets the number of RSS queues.
3399  *
3400  * @dev:                net device
3401  * @channels:           includes the number of queues requested
3402  */
3403 static int bnx2x_set_channels(struct net_device *dev,
3404                               struct ethtool_channels *channels)
3405 {
3406         struct bnx2x *bp = netdev_priv(dev);
3407
3408         DP(BNX2X_MSG_ETHTOOL,
3409            "set-channels command parameters: rx = %d, tx = %d, other = %d, combined = %d\n",
3410            channels->rx_count, channels->tx_count, channels->other_count,
3411            channels->combined_count);
3412
3413         /* We don't support separate rx / tx channels.
3414          * We don't allow setting 'other' channels.
3415          */
3416         if (channels->rx_count || channels->tx_count || channels->other_count
3417             || (channels->combined_count == 0) ||
3418             (channels->combined_count > BNX2X_MAX_RSS_COUNT(bp))) {
3419                 DP(BNX2X_MSG_ETHTOOL, "command parameters not supported\n");
3420                 return -EINVAL;
3421         }
3422
3423         /* Check if there was a change in the active parameters */
3424         if (channels->combined_count == BNX2X_NUM_ETH_QUEUES(bp)) {
3425                 DP(BNX2X_MSG_ETHTOOL, "No change in active parameters\n");
3426                 return 0;
3427         }
3428
3429         /* Set the requested number of queues in bp context.
3430          * Note that the actual number of queues created during load may be
3431          * less than requested if memory is low.
3432          */
3433         if (unlikely(!netif_running(dev))) {
3434                 bnx2x_change_num_queues(bp, channels->combined_count);
3435                 return 0;
3436         }
3437         bnx2x_nic_unload(bp, UNLOAD_NORMAL, true);
3438         bnx2x_change_num_queues(bp, channels->combined_count);
3439         return bnx2x_nic_load(bp, LOAD_NORMAL);
3440 }
3441
3442 static const struct ethtool_ops bnx2x_ethtool_ops = {
3443         .get_settings           = bnx2x_get_settings,
3444         .set_settings           = bnx2x_set_settings,
3445         .get_drvinfo            = bnx2x_get_drvinfo,
3446         .get_regs_len           = bnx2x_get_regs_len,
3447         .get_regs               = bnx2x_get_regs,
3448         .get_dump_flag          = bnx2x_get_dump_flag,
3449         .get_dump_data          = bnx2x_get_dump_data,
3450         .set_dump               = bnx2x_set_dump,
3451         .get_wol                = bnx2x_get_wol,
3452         .set_wol                = bnx2x_set_wol,
3453         .get_msglevel           = bnx2x_get_msglevel,
3454         .set_msglevel           = bnx2x_set_msglevel,
3455         .nway_reset             = bnx2x_nway_reset,
3456         .get_link               = bnx2x_get_link,
3457         .get_eeprom_len         = bnx2x_get_eeprom_len,
3458         .get_eeprom             = bnx2x_get_eeprom,
3459         .set_eeprom             = bnx2x_set_eeprom,
3460         .get_coalesce           = bnx2x_get_coalesce,
3461         .set_coalesce           = bnx2x_set_coalesce,
3462         .get_ringparam          = bnx2x_get_ringparam,
3463         .set_ringparam          = bnx2x_set_ringparam,
3464         .get_pauseparam         = bnx2x_get_pauseparam,
3465         .set_pauseparam         = bnx2x_set_pauseparam,
3466         .self_test              = bnx2x_self_test,
3467         .get_sset_count         = bnx2x_get_sset_count,
3468         .get_priv_flags         = bnx2x_get_private_flags,
3469         .get_strings            = bnx2x_get_strings,
3470         .set_phys_id            = bnx2x_set_phys_id,
3471         .get_ethtool_stats      = bnx2x_get_ethtool_stats,
3472         .get_rxnfc              = bnx2x_get_rxnfc,
3473         .set_rxnfc              = bnx2x_set_rxnfc,
3474         .get_rxfh_indir_size    = bnx2x_get_rxfh_indir_size,
3475         .get_rxfh_indir         = bnx2x_get_rxfh_indir,
3476         .set_rxfh_indir         = bnx2x_set_rxfh_indir,
3477         .get_channels           = bnx2x_get_channels,
3478         .set_channels           = bnx2x_set_channels,
3479         .get_module_info        = bnx2x_get_module_info,
3480         .get_module_eeprom      = bnx2x_get_module_eeprom,
3481         .get_eee                = bnx2x_get_eee,
3482         .set_eee                = bnx2x_set_eee,
3483         .get_ts_info            = ethtool_op_get_ts_info,
3484 };
3485
3486 static const struct ethtool_ops bnx2x_vf_ethtool_ops = {
3487         .get_settings           = bnx2x_get_settings,
3488         .set_settings           = bnx2x_set_settings,
3489         .get_drvinfo            = bnx2x_get_drvinfo,
3490         .get_msglevel           = bnx2x_get_msglevel,
3491         .set_msglevel           = bnx2x_set_msglevel,
3492         .get_link               = bnx2x_get_link,
3493         .get_coalesce           = bnx2x_get_coalesce,
3494         .get_ringparam          = bnx2x_get_ringparam,
3495         .set_ringparam          = bnx2x_set_ringparam,
3496         .get_sset_count         = bnx2x_get_sset_count,
3497         .get_strings            = bnx2x_get_strings,
3498         .get_ethtool_stats      = bnx2x_get_ethtool_stats,
3499         .get_rxnfc              = bnx2x_get_rxnfc,
3500         .set_rxnfc              = bnx2x_set_rxnfc,
3501         .get_rxfh_indir_size    = bnx2x_get_rxfh_indir_size,
3502         .get_rxfh_indir         = bnx2x_get_rxfh_indir,
3503         .set_rxfh_indir         = bnx2x_set_rxfh_indir,
3504         .get_channels           = bnx2x_get_channels,
3505         .set_channels           = bnx2x_set_channels,
3506 };
3507
3508 void bnx2x_set_ethtool_ops(struct bnx2x *bp, struct net_device *netdev)
3509 {
3510         if (IS_PF(bp))
3511                 SET_ETHTOOL_OPS(netdev, &bnx2x_ethtool_ops);
3512         else /* vf */
3513                 SET_ETHTOOL_OPS(netdev, &bnx2x_vf_ethtool_ops);
3514 }