1 /* bnx2x_hsi.h: Broadcom Everest network driver.
3 * Copyright (c) 2007-2012 Broadcom Corporation
5 * This program is free software; you can redistribute it and/or modify
6 * it under the terms of the GNU General Public License as published by
7 * the Free Software Foundation.
12 #include "bnx2x_fw_defs.h"
13 #include "bnx2x_mfw_req.h"
15 #define FW_ENCODE_32BIT_PATTERN 0x1e1e1e1e
21 #define BNX2X_MAX_ISCSI_TRGT_CONN_MASK 0xFFFF
22 #define BNX2X_MAX_ISCSI_TRGT_CONN_SHIFT 0
23 #define BNX2X_MAX_ISCSI_INIT_CONN_MASK 0xFFFF0000
24 #define BNX2X_MAX_ISCSI_INIT_CONN_SHIFT 16
29 #define BNX2X_MAX_FCOE_TRGT_CONN_MASK 0xFFFF
30 #define BNX2X_MAX_FCOE_TRGT_CONN_SHIFT 0
31 #define BNX2X_MAX_FCOE_INIT_CONN_MASK 0xFFFF0000
32 #define BNX2X_MAX_FCOE_INIT_CONN_SHIFT 16
37 /****************************************************************************
38 * Shared HW configuration *
39 ****************************************************************************/
40 #define PIN_CFG_NA 0x00000000
41 #define PIN_CFG_GPIO0_P0 0x00000001
42 #define PIN_CFG_GPIO1_P0 0x00000002
43 #define PIN_CFG_GPIO2_P0 0x00000003
44 #define PIN_CFG_GPIO3_P0 0x00000004
45 #define PIN_CFG_GPIO0_P1 0x00000005
46 #define PIN_CFG_GPIO1_P1 0x00000006
47 #define PIN_CFG_GPIO2_P1 0x00000007
48 #define PIN_CFG_GPIO3_P1 0x00000008
49 #define PIN_CFG_EPIO0 0x00000009
50 #define PIN_CFG_EPIO1 0x0000000a
51 #define PIN_CFG_EPIO2 0x0000000b
52 #define PIN_CFG_EPIO3 0x0000000c
53 #define PIN_CFG_EPIO4 0x0000000d
54 #define PIN_CFG_EPIO5 0x0000000e
55 #define PIN_CFG_EPIO6 0x0000000f
56 #define PIN_CFG_EPIO7 0x00000010
57 #define PIN_CFG_EPIO8 0x00000011
58 #define PIN_CFG_EPIO9 0x00000012
59 #define PIN_CFG_EPIO10 0x00000013
60 #define PIN_CFG_EPIO11 0x00000014
61 #define PIN_CFG_EPIO12 0x00000015
62 #define PIN_CFG_EPIO13 0x00000016
63 #define PIN_CFG_EPIO14 0x00000017
64 #define PIN_CFG_EPIO15 0x00000018
65 #define PIN_CFG_EPIO16 0x00000019
66 #define PIN_CFG_EPIO17 0x0000001a
67 #define PIN_CFG_EPIO18 0x0000001b
68 #define PIN_CFG_EPIO19 0x0000001c
69 #define PIN_CFG_EPIO20 0x0000001d
70 #define PIN_CFG_EPIO21 0x0000001e
71 #define PIN_CFG_EPIO22 0x0000001f
72 #define PIN_CFG_EPIO23 0x00000020
73 #define PIN_CFG_EPIO24 0x00000021
74 #define PIN_CFG_EPIO25 0x00000022
75 #define PIN_CFG_EPIO26 0x00000023
76 #define PIN_CFG_EPIO27 0x00000024
77 #define PIN_CFG_EPIO28 0x00000025
78 #define PIN_CFG_EPIO29 0x00000026
79 #define PIN_CFG_EPIO30 0x00000027
80 #define PIN_CFG_EPIO31 0x00000028
83 #define EPIO_CFG_NA 0x00000000
84 #define EPIO_CFG_EPIO0 0x00000001
85 #define EPIO_CFG_EPIO1 0x00000002
86 #define EPIO_CFG_EPIO2 0x00000003
87 #define EPIO_CFG_EPIO3 0x00000004
88 #define EPIO_CFG_EPIO4 0x00000005
89 #define EPIO_CFG_EPIO5 0x00000006
90 #define EPIO_CFG_EPIO6 0x00000007
91 #define EPIO_CFG_EPIO7 0x00000008
92 #define EPIO_CFG_EPIO8 0x00000009
93 #define EPIO_CFG_EPIO9 0x0000000a
94 #define EPIO_CFG_EPIO10 0x0000000b
95 #define EPIO_CFG_EPIO11 0x0000000c
96 #define EPIO_CFG_EPIO12 0x0000000d
97 #define EPIO_CFG_EPIO13 0x0000000e
98 #define EPIO_CFG_EPIO14 0x0000000f
99 #define EPIO_CFG_EPIO15 0x00000010
100 #define EPIO_CFG_EPIO16 0x00000011
101 #define EPIO_CFG_EPIO17 0x00000012
102 #define EPIO_CFG_EPIO18 0x00000013
103 #define EPIO_CFG_EPIO19 0x00000014
104 #define EPIO_CFG_EPIO20 0x00000015
105 #define EPIO_CFG_EPIO21 0x00000016
106 #define EPIO_CFG_EPIO22 0x00000017
107 #define EPIO_CFG_EPIO23 0x00000018
108 #define EPIO_CFG_EPIO24 0x00000019
109 #define EPIO_CFG_EPIO25 0x0000001a
110 #define EPIO_CFG_EPIO26 0x0000001b
111 #define EPIO_CFG_EPIO27 0x0000001c
112 #define EPIO_CFG_EPIO28 0x0000001d
113 #define EPIO_CFG_EPIO29 0x0000001e
114 #define EPIO_CFG_EPIO30 0x0000001f
115 #define EPIO_CFG_EPIO31 0x00000020
118 struct shared_hw_cfg { /* NVRAM Offset */
119 /* Up to 16 bytes of NULL-terminated string */
120 u8 part_num[16]; /* 0x104 */
122 u32 config; /* 0x114 */
123 #define SHARED_HW_CFG_MDIO_VOLTAGE_MASK 0x00000001
124 #define SHARED_HW_CFG_MDIO_VOLTAGE_SHIFT 0
125 #define SHARED_HW_CFG_MDIO_VOLTAGE_1_2V 0x00000000
126 #define SHARED_HW_CFG_MDIO_VOLTAGE_2_5V 0x00000001
127 #define SHARED_HW_CFG_MCP_RST_ON_CORE_RST_EN 0x00000002
129 #define SHARED_HW_CFG_PORT_SWAP 0x00000004
131 #define SHARED_HW_CFG_BEACON_WOL_EN 0x00000008
133 #define SHARED_HW_CFG_PCIE_GEN3_DISABLED 0x00000000
134 #define SHARED_HW_CFG_PCIE_GEN3_ENABLED 0x00000010
136 #define SHARED_HW_CFG_MFW_SELECT_MASK 0x00000700
137 #define SHARED_HW_CFG_MFW_SELECT_SHIFT 8
138 /* Whatever MFW found in NVM
139 (if multiple found, priority order is: NC-SI, UMP, IPMI) */
140 #define SHARED_HW_CFG_MFW_SELECT_DEFAULT 0x00000000
141 #define SHARED_HW_CFG_MFW_SELECT_NC_SI 0x00000100
142 #define SHARED_HW_CFG_MFW_SELECT_UMP 0x00000200
143 #define SHARED_HW_CFG_MFW_SELECT_IPMI 0x00000300
144 /* Use SPIO4 as an arbiter between: 0-NC_SI, 1-IPMI
145 (can only be used when an add-in board, not BMC, pulls-down SPIO4) */
146 #define SHARED_HW_CFG_MFW_SELECT_SPIO4_NC_SI_IPMI 0x00000400
147 /* Use SPIO4 as an arbiter between: 0-UMP, 1-IPMI
148 (can only be used when an add-in board, not BMC, pulls-down SPIO4) */
149 #define SHARED_HW_CFG_MFW_SELECT_SPIO4_UMP_IPMI 0x00000500
150 /* Use SPIO4 as an arbiter between: 0-NC-SI, 1-UMP
151 (can only be used when an add-in board, not BMC, pulls-down SPIO4) */
152 #define SHARED_HW_CFG_MFW_SELECT_SPIO4_NC_SI_UMP 0x00000600
154 #define SHARED_HW_CFG_LED_MODE_MASK 0x000f0000
155 #define SHARED_HW_CFG_LED_MODE_SHIFT 16
156 #define SHARED_HW_CFG_LED_MAC1 0x00000000
157 #define SHARED_HW_CFG_LED_PHY1 0x00010000
158 #define SHARED_HW_CFG_LED_PHY2 0x00020000
159 #define SHARED_HW_CFG_LED_PHY3 0x00030000
160 #define SHARED_HW_CFG_LED_MAC2 0x00040000
161 #define SHARED_HW_CFG_LED_PHY4 0x00050000
162 #define SHARED_HW_CFG_LED_PHY5 0x00060000
163 #define SHARED_HW_CFG_LED_PHY6 0x00070000
164 #define SHARED_HW_CFG_LED_MAC3 0x00080000
165 #define SHARED_HW_CFG_LED_PHY7 0x00090000
166 #define SHARED_HW_CFG_LED_PHY9 0x000a0000
167 #define SHARED_HW_CFG_LED_PHY11 0x000b0000
168 #define SHARED_HW_CFG_LED_MAC4 0x000c0000
169 #define SHARED_HW_CFG_LED_PHY8 0x000d0000
170 #define SHARED_HW_CFG_LED_EXTPHY1 0x000e0000
173 #define SHARED_HW_CFG_AN_ENABLE_MASK 0x3f000000
174 #define SHARED_HW_CFG_AN_ENABLE_SHIFT 24
175 #define SHARED_HW_CFG_AN_ENABLE_CL37 0x01000000
176 #define SHARED_HW_CFG_AN_ENABLE_CL73 0x02000000
177 #define SHARED_HW_CFG_AN_ENABLE_BAM 0x04000000
178 #define SHARED_HW_CFG_AN_ENABLE_PARALLEL_DETECTION 0x08000000
179 #define SHARED_HW_CFG_AN_EN_SGMII_FIBER_AUTO_DETECT 0x10000000
180 #define SHARED_HW_CFG_AN_ENABLE_REMOTE_PHY 0x20000000
182 #define SHARED_HW_CFG_SRIOV_MASK 0x40000000
183 #define SHARED_HW_CFG_SRIOV_DISABLED 0x00000000
184 #define SHARED_HW_CFG_SRIOV_ENABLED 0x40000000
186 #define SHARED_HW_CFG_ATC_MASK 0x80000000
187 #define SHARED_HW_CFG_ATC_DISABLED 0x00000000
188 #define SHARED_HW_CFG_ATC_ENABLED 0x80000000
190 u32 config2; /* 0x118 */
191 /* one time auto detect grace period (in sec) */
192 #define SHARED_HW_CFG_GRACE_PERIOD_MASK 0x000000ff
193 #define SHARED_HW_CFG_GRACE_PERIOD_SHIFT 0
195 #define SHARED_HW_CFG_PCIE_GEN2_ENABLED 0x00000100
196 #define SHARED_HW_CFG_PCIE_GEN2_DISABLED 0x00000000
198 /* The default value for the core clock is 250MHz and it is
199 achieved by setting the clock change to 4 */
200 #define SHARED_HW_CFG_CLOCK_CHANGE_MASK 0x00000e00
201 #define SHARED_HW_CFG_CLOCK_CHANGE_SHIFT 9
203 #define SHARED_HW_CFG_SMBUS_TIMING_MASK 0x00001000
204 #define SHARED_HW_CFG_SMBUS_TIMING_100KHZ 0x00000000
205 #define SHARED_HW_CFG_SMBUS_TIMING_400KHZ 0x00001000
207 #define SHARED_HW_CFG_HIDE_PORT1 0x00002000
209 #define SHARED_HW_CFG_WOL_CAPABLE_MASK 0x00004000
210 #define SHARED_HW_CFG_WOL_CAPABLE_DISABLED 0x00000000
211 #define SHARED_HW_CFG_WOL_CAPABLE_ENABLED 0x00004000
213 /* Output low when PERST is asserted */
214 #define SHARED_HW_CFG_SPIO4_FOLLOW_PERST_MASK 0x00008000
215 #define SHARED_HW_CFG_SPIO4_FOLLOW_PERST_DISABLED 0x00000000
216 #define SHARED_HW_CFG_SPIO4_FOLLOW_PERST_ENABLED 0x00008000
218 #define SHARED_HW_CFG_PCIE_GEN2_PREEMPHASIS_MASK 0x00070000
219 #define SHARED_HW_CFG_PCIE_GEN2_PREEMPHASIS_SHIFT 16
220 #define SHARED_HW_CFG_PCIE_GEN2_PREEMPHASIS_HW 0x00000000
221 #define SHARED_HW_CFG_PCIE_GEN2_PREEMPHASIS_0DB 0x00010000
222 #define SHARED_HW_CFG_PCIE_GEN2_PREEMPHASIS_3_5DB 0x00020000
223 #define SHARED_HW_CFG_PCIE_GEN2_PREEMPHASIS_6_0DB 0x00030000
225 /* The fan failure mechanism is usually related to the PHY type
226 since the power consumption of the board is determined by the PHY.
227 Currently, fan is required for most designs with SFX7101, BCM8727
228 and BCM8481. If a fan is not required for a board which uses one
229 of those PHYs, this field should be set to "Disabled". If a fan is
230 required for a different PHY type, this option should be set to
231 "Enabled". The fan failure indication is expected on SPIO5 */
232 #define SHARED_HW_CFG_FAN_FAILURE_MASK 0x00180000
233 #define SHARED_HW_CFG_FAN_FAILURE_SHIFT 19
234 #define SHARED_HW_CFG_FAN_FAILURE_PHY_TYPE 0x00000000
235 #define SHARED_HW_CFG_FAN_FAILURE_DISABLED 0x00080000
236 #define SHARED_HW_CFG_FAN_FAILURE_ENABLED 0x00100000
238 /* ASPM Power Management support */
239 #define SHARED_HW_CFG_ASPM_SUPPORT_MASK 0x00600000
240 #define SHARED_HW_CFG_ASPM_SUPPORT_SHIFT 21
241 #define SHARED_HW_CFG_ASPM_SUPPORT_L0S_L1_ENABLED 0x00000000
242 #define SHARED_HW_CFG_ASPM_SUPPORT_L0S_DISABLED 0x00200000
243 #define SHARED_HW_CFG_ASPM_SUPPORT_L1_DISABLED 0x00400000
244 #define SHARED_HW_CFG_ASPM_SUPPORT_L0S_L1_DISABLED 0x00600000
246 /* The value of PM_TL_IGNORE_REQS (bit0) in PCI register
247 tl_control_0 (register 0x2800) */
248 #define SHARED_HW_CFG_PREVENT_L1_ENTRY_MASK 0x00800000
249 #define SHARED_HW_CFG_PREVENT_L1_ENTRY_DISABLED 0x00000000
250 #define SHARED_HW_CFG_PREVENT_L1_ENTRY_ENABLED 0x00800000
252 #define SHARED_HW_CFG_PORT_MODE_MASK 0x01000000
253 #define SHARED_HW_CFG_PORT_MODE_2 0x00000000
254 #define SHARED_HW_CFG_PORT_MODE_4 0x01000000
256 #define SHARED_HW_CFG_PATH_SWAP_MASK 0x02000000
257 #define SHARED_HW_CFG_PATH_SWAP_DISABLED 0x00000000
258 #define SHARED_HW_CFG_PATH_SWAP_ENABLED 0x02000000
260 /* Set the MDC/MDIO access for the first external phy */
261 #define SHARED_HW_CFG_MDC_MDIO_ACCESS1_MASK 0x1C000000
262 #define SHARED_HW_CFG_MDC_MDIO_ACCESS1_SHIFT 26
263 #define SHARED_HW_CFG_MDC_MDIO_ACCESS1_PHY_TYPE 0x00000000
264 #define SHARED_HW_CFG_MDC_MDIO_ACCESS1_EMAC0 0x04000000
265 #define SHARED_HW_CFG_MDC_MDIO_ACCESS1_EMAC1 0x08000000
266 #define SHARED_HW_CFG_MDC_MDIO_ACCESS1_BOTH 0x0c000000
267 #define SHARED_HW_CFG_MDC_MDIO_ACCESS1_SWAPPED 0x10000000
269 /* Set the MDC/MDIO access for the second external phy */
270 #define SHARED_HW_CFG_MDC_MDIO_ACCESS2_MASK 0xE0000000
271 #define SHARED_HW_CFG_MDC_MDIO_ACCESS2_SHIFT 29
272 #define SHARED_HW_CFG_MDC_MDIO_ACCESS2_PHY_TYPE 0x00000000
273 #define SHARED_HW_CFG_MDC_MDIO_ACCESS2_EMAC0 0x20000000
274 #define SHARED_HW_CFG_MDC_MDIO_ACCESS2_EMAC1 0x40000000
275 #define SHARED_HW_CFG_MDC_MDIO_ACCESS2_BOTH 0x60000000
276 #define SHARED_HW_CFG_MDC_MDIO_ACCESS2_SWAPPED 0x80000000
279 u32 power_dissipated; /* 0x11c */
280 #define SHARED_HW_CFG_POWER_MGNT_SCALE_MASK 0x00ff0000
281 #define SHARED_HW_CFG_POWER_MGNT_SCALE_SHIFT 16
282 #define SHARED_HW_CFG_POWER_MGNT_UNKNOWN_SCALE 0x00000000
283 #define SHARED_HW_CFG_POWER_MGNT_DOT_1_WATT 0x00010000
284 #define SHARED_HW_CFG_POWER_MGNT_DOT_01_WATT 0x00020000
285 #define SHARED_HW_CFG_POWER_MGNT_DOT_001_WATT 0x00030000
287 #define SHARED_HW_CFG_POWER_DIS_CMN_MASK 0xff000000
288 #define SHARED_HW_CFG_POWER_DIS_CMN_SHIFT 24
290 u32 ump_nc_si_config; /* 0x120 */
291 #define SHARED_HW_CFG_UMP_NC_SI_MII_MODE_MASK 0x00000003
292 #define SHARED_HW_CFG_UMP_NC_SI_MII_MODE_SHIFT 0
293 #define SHARED_HW_CFG_UMP_NC_SI_MII_MODE_MAC 0x00000000
294 #define SHARED_HW_CFG_UMP_NC_SI_MII_MODE_PHY 0x00000001
295 #define SHARED_HW_CFG_UMP_NC_SI_MII_MODE_MII 0x00000000
296 #define SHARED_HW_CFG_UMP_NC_SI_MII_MODE_RMII 0x00000002
298 #define SHARED_HW_CFG_UMP_NC_SI_NUM_DEVS_MASK 0x00000f00
299 #define SHARED_HW_CFG_UMP_NC_SI_NUM_DEVS_SHIFT 8
301 #define SHARED_HW_CFG_UMP_NC_SI_EXT_PHY_TYPE_MASK 0x00ff0000
302 #define SHARED_HW_CFG_UMP_NC_SI_EXT_PHY_TYPE_SHIFT 16
303 #define SHARED_HW_CFG_UMP_NC_SI_EXT_PHY_TYPE_NONE 0x00000000
304 #define SHARED_HW_CFG_UMP_NC_SI_EXT_PHY_TYPE_BCM5221 0x00010000
306 u32 board; /* 0x124 */
307 #define SHARED_HW_CFG_E3_I2C_MUX0_MASK 0x0000003F
308 #define SHARED_HW_CFG_E3_I2C_MUX0_SHIFT 0
309 #define SHARED_HW_CFG_E3_I2C_MUX1_MASK 0x00000FC0
310 #define SHARED_HW_CFG_E3_I2C_MUX1_SHIFT 6
311 /* Use the PIN_CFG_XXX defines on top */
312 #define SHARED_HW_CFG_BOARD_REV_MASK 0x00ff0000
313 #define SHARED_HW_CFG_BOARD_REV_SHIFT 16
315 #define SHARED_HW_CFG_BOARD_MAJOR_VER_MASK 0x0f000000
316 #define SHARED_HW_CFG_BOARD_MAJOR_VER_SHIFT 24
318 #define SHARED_HW_CFG_BOARD_MINOR_VER_MASK 0xf0000000
319 #define SHARED_HW_CFG_BOARD_MINOR_VER_SHIFT 28
321 u32 wc_lane_config; /* 0x128 */
322 #define SHARED_HW_CFG_LANE_SWAP_CFG_MASK 0x0000FFFF
323 #define SHARED_HW_CFG_LANE_SWAP_CFG_SHIFT 0
324 #define SHARED_HW_CFG_LANE_SWAP_CFG_32103210 0x00001b1b
325 #define SHARED_HW_CFG_LANE_SWAP_CFG_32100123 0x00001be4
326 #define SHARED_HW_CFG_LANE_SWAP_CFG_01233210 0x0000e41b
327 #define SHARED_HW_CFG_LANE_SWAP_CFG_01230123 0x0000e4e4
328 #define SHARED_HW_CFG_LANE_SWAP_CFG_TX_MASK 0x000000FF
329 #define SHARED_HW_CFG_LANE_SWAP_CFG_TX_SHIFT 0
330 #define SHARED_HW_CFG_LANE_SWAP_CFG_RX_MASK 0x0000FF00
331 #define SHARED_HW_CFG_LANE_SWAP_CFG_RX_SHIFT 8
333 /* TX lane Polarity swap */
334 #define SHARED_HW_CFG_TX_LANE0_POL_FLIP_ENABLED 0x00010000
335 #define SHARED_HW_CFG_TX_LANE1_POL_FLIP_ENABLED 0x00020000
336 #define SHARED_HW_CFG_TX_LANE2_POL_FLIP_ENABLED 0x00040000
337 #define SHARED_HW_CFG_TX_LANE3_POL_FLIP_ENABLED 0x00080000
338 /* TX lane Polarity swap */
339 #define SHARED_HW_CFG_RX_LANE0_POL_FLIP_ENABLED 0x00100000
340 #define SHARED_HW_CFG_RX_LANE1_POL_FLIP_ENABLED 0x00200000
341 #define SHARED_HW_CFG_RX_LANE2_POL_FLIP_ENABLED 0x00400000
342 #define SHARED_HW_CFG_RX_LANE3_POL_FLIP_ENABLED 0x00800000
344 /* Selects the port layout of the board */
345 #define SHARED_HW_CFG_E3_PORT_LAYOUT_MASK 0x0F000000
346 #define SHARED_HW_CFG_E3_PORT_LAYOUT_SHIFT 24
347 #define SHARED_HW_CFG_E3_PORT_LAYOUT_2P_01 0x00000000
348 #define SHARED_HW_CFG_E3_PORT_LAYOUT_2P_10 0x01000000
349 #define SHARED_HW_CFG_E3_PORT_LAYOUT_4P_0123 0x02000000
350 #define SHARED_HW_CFG_E3_PORT_LAYOUT_4P_1032 0x03000000
351 #define SHARED_HW_CFG_E3_PORT_LAYOUT_4P_2301 0x04000000
352 #define SHARED_HW_CFG_E3_PORT_LAYOUT_4P_3210 0x05000000
356 /****************************************************************************
357 * Port HW configuration *
358 ****************************************************************************/
359 struct port_hw_cfg { /* port 0: 0x12c port 1: 0x2bc */
362 #define PORT_HW_CFG_PCI_VENDOR_ID_MASK 0xffff0000
363 #define PORT_HW_CFG_PCI_DEVICE_ID_MASK 0x0000ffff
366 #define PORT_HW_CFG_PCI_SUBSYS_DEVICE_ID_MASK 0xffff0000
367 #define PORT_HW_CFG_PCI_SUBSYS_VENDOR_ID_MASK 0x0000ffff
369 u32 power_dissipated;
370 #define PORT_HW_CFG_POWER_DIS_D0_MASK 0x000000ff
371 #define PORT_HW_CFG_POWER_DIS_D0_SHIFT 0
372 #define PORT_HW_CFG_POWER_DIS_D1_MASK 0x0000ff00
373 #define PORT_HW_CFG_POWER_DIS_D1_SHIFT 8
374 #define PORT_HW_CFG_POWER_DIS_D2_MASK 0x00ff0000
375 #define PORT_HW_CFG_POWER_DIS_D2_SHIFT 16
376 #define PORT_HW_CFG_POWER_DIS_D3_MASK 0xff000000
377 #define PORT_HW_CFG_POWER_DIS_D3_SHIFT 24
380 #define PORT_HW_CFG_POWER_CONS_D0_MASK 0x000000ff
381 #define PORT_HW_CFG_POWER_CONS_D0_SHIFT 0
382 #define PORT_HW_CFG_POWER_CONS_D1_MASK 0x0000ff00
383 #define PORT_HW_CFG_POWER_CONS_D1_SHIFT 8
384 #define PORT_HW_CFG_POWER_CONS_D2_MASK 0x00ff0000
385 #define PORT_HW_CFG_POWER_CONS_D2_SHIFT 16
386 #define PORT_HW_CFG_POWER_CONS_D3_MASK 0xff000000
387 #define PORT_HW_CFG_POWER_CONS_D3_SHIFT 24
390 #define PORT_HW_CFG_UPPERMAC_MASK 0x0000ffff
391 #define PORT_HW_CFG_UPPERMAC_SHIFT 0
394 u32 iscsi_mac_upper; /* Upper 16 bits are always zeroes */
397 u32 rdma_mac_upper; /* Upper 16 bits are always zeroes */
401 #define PORT_HW_CFG_SERDES_TX_DRV_PRE_EMPHASIS_MASK 0x0000ffff
402 #define PORT_HW_CFG_SERDES_TX_DRV_PRE_EMPHASIS_SHIFT 0
404 #define PORT_HW_CFG_SERDES_RX_DRV_EQUALIZER_MASK 0xffff0000
405 #define PORT_HW_CFG_SERDES_RX_DRV_EQUALIZER_SHIFT 16
408 /* Default values: 2P-64, 4P-32 */
409 u32 pf_config; /* 0x158 */
410 #define PORT_HW_CFG_PF_NUM_VF_MASK 0x0000007F
411 #define PORT_HW_CFG_PF_NUM_VF_SHIFT 0
413 /* Default values: 17 */
414 #define PORT_HW_CFG_PF_NUM_MSIX_VECTORS_MASK 0x00007F00
415 #define PORT_HW_CFG_PF_NUM_MSIX_VECTORS_SHIFT 8
417 #define PORT_HW_CFG_ENABLE_FLR_MASK 0x00010000
418 #define PORT_HW_CFG_FLR_ENABLED 0x00010000
420 u32 vf_config; /* 0x15C */
421 #define PORT_HW_CFG_VF_NUM_MSIX_VECTORS_MASK 0x0000007F
422 #define PORT_HW_CFG_VF_NUM_MSIX_VECTORS_SHIFT 0
424 #define PORT_HW_CFG_VF_PCI_DEVICE_ID_MASK 0xFFFF0000
425 #define PORT_HW_CFG_VF_PCI_DEVICE_ID_SHIFT 16
427 u32 mf_pci_id; /* 0x160 */
428 #define PORT_HW_CFG_MF_PCI_DEVICE_ID_MASK 0x0000FFFF
429 #define PORT_HW_CFG_MF_PCI_DEVICE_ID_SHIFT 0
431 /* Controls the TX laser of the SFP+ module */
432 u32 sfp_ctrl; /* 0x164 */
433 #define PORT_HW_CFG_TX_LASER_MASK 0x000000FF
434 #define PORT_HW_CFG_TX_LASER_SHIFT 0
435 #define PORT_HW_CFG_TX_LASER_MDIO 0x00000000
436 #define PORT_HW_CFG_TX_LASER_GPIO0 0x00000001
437 #define PORT_HW_CFG_TX_LASER_GPIO1 0x00000002
438 #define PORT_HW_CFG_TX_LASER_GPIO2 0x00000003
439 #define PORT_HW_CFG_TX_LASER_GPIO3 0x00000004
441 /* Controls the fault module LED of the SFP+ */
442 #define PORT_HW_CFG_FAULT_MODULE_LED_MASK 0x0000FF00
443 #define PORT_HW_CFG_FAULT_MODULE_LED_SHIFT 8
444 #define PORT_HW_CFG_FAULT_MODULE_LED_GPIO0 0x00000000
445 #define PORT_HW_CFG_FAULT_MODULE_LED_GPIO1 0x00000100
446 #define PORT_HW_CFG_FAULT_MODULE_LED_GPIO2 0x00000200
447 #define PORT_HW_CFG_FAULT_MODULE_LED_GPIO3 0x00000300
448 #define PORT_HW_CFG_FAULT_MODULE_LED_DISABLED 0x00000400
450 /* The output pin TX_DIS that controls the TX laser of the SFP+
451 module. Use the PIN_CFG_XXX defines on top */
452 u32 e3_sfp_ctrl; /* 0x168 */
453 #define PORT_HW_CFG_E3_TX_LASER_MASK 0x000000FF
454 #define PORT_HW_CFG_E3_TX_LASER_SHIFT 0
456 /* The output pin for SFPP_TYPE which turns on the Fault module LED */
457 #define PORT_HW_CFG_E3_FAULT_MDL_LED_MASK 0x0000FF00
458 #define PORT_HW_CFG_E3_FAULT_MDL_LED_SHIFT 8
460 /* The input pin MOD_ABS that indicates whether SFP+ module is
461 present or not. Use the PIN_CFG_XXX defines on top */
462 #define PORT_HW_CFG_E3_MOD_ABS_MASK 0x00FF0000
463 #define PORT_HW_CFG_E3_MOD_ABS_SHIFT 16
465 /* The output pin PWRDIS_SFP_X which disable the power of the SFP+
466 module. Use the PIN_CFG_XXX defines on top */
467 #define PORT_HW_CFG_E3_PWR_DIS_MASK 0xFF000000
468 #define PORT_HW_CFG_E3_PWR_DIS_SHIFT 24
471 * The input pin which signals module transmit fault. Use the
472 * PIN_CFG_XXX defines on top
474 u32 e3_cmn_pin_cfg; /* 0x16C */
475 #define PORT_HW_CFG_E3_TX_FAULT_MASK 0x000000FF
476 #define PORT_HW_CFG_E3_TX_FAULT_SHIFT 0
478 /* The output pin which reset the PHY. Use the PIN_CFG_XXX defines on
480 #define PORT_HW_CFG_E3_PHY_RESET_MASK 0x0000FF00
481 #define PORT_HW_CFG_E3_PHY_RESET_SHIFT 8
484 * The output pin which powers down the PHY. Use the PIN_CFG_XXX
487 #define PORT_HW_CFG_E3_PWR_DOWN_MASK 0x00FF0000
488 #define PORT_HW_CFG_E3_PWR_DOWN_SHIFT 16
490 /* The output pin values BSC_SEL which selects the I2C for this port
492 #define PORT_HW_CFG_E3_I2C_MUX0_MASK 0x01000000
493 #define PORT_HW_CFG_E3_I2C_MUX1_MASK 0x02000000
497 * The input pin I_FAULT which indicate over-current has occurred.
498 * Use the PIN_CFG_XXX defines on top
500 u32 e3_cmn_pin_cfg1; /* 0x170 */
501 #define PORT_HW_CFG_E3_OVER_CURRENT_MASK 0x000000FF
502 #define PORT_HW_CFG_E3_OVER_CURRENT_SHIFT 0
503 u32 reserved0[7]; /* 0x174 */
505 u32 aeu_int_mask; /* 0x190 */
507 u32 media_type; /* 0x194 */
508 #define PORT_HW_CFG_MEDIA_TYPE_PHY0_MASK 0x000000FF
509 #define PORT_HW_CFG_MEDIA_TYPE_PHY0_SHIFT 0
511 #define PORT_HW_CFG_MEDIA_TYPE_PHY1_MASK 0x0000FF00
512 #define PORT_HW_CFG_MEDIA_TYPE_PHY1_SHIFT 8
514 #define PORT_HW_CFG_MEDIA_TYPE_PHY2_MASK 0x00FF0000
515 #define PORT_HW_CFG_MEDIA_TYPE_PHY2_SHIFT 16
517 /* 4 times 16 bits for all 4 lanes. In case external PHY is present
518 (not direct mode), those values will not take effect on the 4 XGXS
519 lanes. For some external PHYs (such as 8706 and 8726) the values
520 will be used to configure the external PHY in those cases, not
521 all 4 values are needed. */
522 u16 xgxs_config_rx[4]; /* 0x198 */
523 u16 xgxs_config_tx[4]; /* 0x1A0 */
525 /* For storing FCOE mac on shared memory */
526 u32 fcoe_fip_mac_upper;
527 #define PORT_HW_CFG_FCOE_UPPERMAC_MASK 0x0000ffff
528 #define PORT_HW_CFG_FCOE_UPPERMAC_SHIFT 0
529 u32 fcoe_fip_mac_lower;
531 u32 fcoe_wwn_port_name_upper;
532 u32 fcoe_wwn_port_name_lower;
534 u32 fcoe_wwn_node_name_upper;
535 u32 fcoe_wwn_node_name_lower;
537 u32 Reserved1[49]; /* 0x1C0 */
539 /* Enable RJ45 magjack pair swapping on 10GBase-T PHY (0=default),
541 u32 xgbt_phy_cfg; /* 0x284 */
542 #define PORT_HW_CFG_RJ45_PAIR_SWAP_MASK 0x000000FF
543 #define PORT_HW_CFG_RJ45_PAIR_SWAP_SHIFT 0
545 u32 default_cfg; /* 0x288 */
546 #define PORT_HW_CFG_GPIO0_CONFIG_MASK 0x00000003
547 #define PORT_HW_CFG_GPIO0_CONFIG_SHIFT 0
548 #define PORT_HW_CFG_GPIO0_CONFIG_NA 0x00000000
549 #define PORT_HW_CFG_GPIO0_CONFIG_LOW 0x00000001
550 #define PORT_HW_CFG_GPIO0_CONFIG_HIGH 0x00000002
551 #define PORT_HW_CFG_GPIO0_CONFIG_INPUT 0x00000003
553 #define PORT_HW_CFG_GPIO1_CONFIG_MASK 0x0000000C
554 #define PORT_HW_CFG_GPIO1_CONFIG_SHIFT 2
555 #define PORT_HW_CFG_GPIO1_CONFIG_NA 0x00000000
556 #define PORT_HW_CFG_GPIO1_CONFIG_LOW 0x00000004
557 #define PORT_HW_CFG_GPIO1_CONFIG_HIGH 0x00000008
558 #define PORT_HW_CFG_GPIO1_CONFIG_INPUT 0x0000000c
560 #define PORT_HW_CFG_GPIO2_CONFIG_MASK 0x00000030
561 #define PORT_HW_CFG_GPIO2_CONFIG_SHIFT 4
562 #define PORT_HW_CFG_GPIO2_CONFIG_NA 0x00000000
563 #define PORT_HW_CFG_GPIO2_CONFIG_LOW 0x00000010
564 #define PORT_HW_CFG_GPIO2_CONFIG_HIGH 0x00000020
565 #define PORT_HW_CFG_GPIO2_CONFIG_INPUT 0x00000030
567 #define PORT_HW_CFG_GPIO3_CONFIG_MASK 0x000000C0
568 #define PORT_HW_CFG_GPIO3_CONFIG_SHIFT 6
569 #define PORT_HW_CFG_GPIO3_CONFIG_NA 0x00000000
570 #define PORT_HW_CFG_GPIO3_CONFIG_LOW 0x00000040
571 #define PORT_HW_CFG_GPIO3_CONFIG_HIGH 0x00000080
572 #define PORT_HW_CFG_GPIO3_CONFIG_INPUT 0x000000c0
574 /* When KR link is required to be set to force which is not
575 KR-compliant, this parameter determine what is the trigger for it.
576 When GPIO is selected, low input will force the speed. Currently
577 default speed is 1G. In the future, it may be widen to select the
578 forced speed in with another parameter. Note when force-1G is
579 enabled, it override option 56: Link Speed option. */
580 #define PORT_HW_CFG_FORCE_KR_ENABLER_MASK 0x00000F00
581 #define PORT_HW_CFG_FORCE_KR_ENABLER_SHIFT 8
582 #define PORT_HW_CFG_FORCE_KR_ENABLER_NOT_FORCED 0x00000000
583 #define PORT_HW_CFG_FORCE_KR_ENABLER_GPIO0_P0 0x00000100
584 #define PORT_HW_CFG_FORCE_KR_ENABLER_GPIO1_P0 0x00000200
585 #define PORT_HW_CFG_FORCE_KR_ENABLER_GPIO2_P0 0x00000300
586 #define PORT_HW_CFG_FORCE_KR_ENABLER_GPIO3_P0 0x00000400
587 #define PORT_HW_CFG_FORCE_KR_ENABLER_GPIO0_P1 0x00000500
588 #define PORT_HW_CFG_FORCE_KR_ENABLER_GPIO1_P1 0x00000600
589 #define PORT_HW_CFG_FORCE_KR_ENABLER_GPIO2_P1 0x00000700
590 #define PORT_HW_CFG_FORCE_KR_ENABLER_GPIO3_P1 0x00000800
591 #define PORT_HW_CFG_FORCE_KR_ENABLER_FORCED 0x00000900
592 /* Enable to determine with which GPIO to reset the external phy */
593 #define PORT_HW_CFG_EXT_PHY_GPIO_RST_MASK 0x000F0000
594 #define PORT_HW_CFG_EXT_PHY_GPIO_RST_SHIFT 16
595 #define PORT_HW_CFG_EXT_PHY_GPIO_RST_PHY_TYPE 0x00000000
596 #define PORT_HW_CFG_EXT_PHY_GPIO_RST_GPIO0_P0 0x00010000
597 #define PORT_HW_CFG_EXT_PHY_GPIO_RST_GPIO1_P0 0x00020000
598 #define PORT_HW_CFG_EXT_PHY_GPIO_RST_GPIO2_P0 0x00030000
599 #define PORT_HW_CFG_EXT_PHY_GPIO_RST_GPIO3_P0 0x00040000
600 #define PORT_HW_CFG_EXT_PHY_GPIO_RST_GPIO0_P1 0x00050000
601 #define PORT_HW_CFG_EXT_PHY_GPIO_RST_GPIO1_P1 0x00060000
602 #define PORT_HW_CFG_EXT_PHY_GPIO_RST_GPIO2_P1 0x00070000
603 #define PORT_HW_CFG_EXT_PHY_GPIO_RST_GPIO3_P1 0x00080000
605 /* Enable BAM on KR */
606 #define PORT_HW_CFG_ENABLE_BAM_ON_KR_MASK 0x00100000
607 #define PORT_HW_CFG_ENABLE_BAM_ON_KR_SHIFT 20
608 #define PORT_HW_CFG_ENABLE_BAM_ON_KR_DISABLED 0x00000000
609 #define PORT_HW_CFG_ENABLE_BAM_ON_KR_ENABLED 0x00100000
611 /* Enable Common Mode Sense */
612 #define PORT_HW_CFG_ENABLE_CMS_MASK 0x00200000
613 #define PORT_HW_CFG_ENABLE_CMS_SHIFT 21
614 #define PORT_HW_CFG_ENABLE_CMS_DISABLED 0x00000000
615 #define PORT_HW_CFG_ENABLE_CMS_ENABLED 0x00200000
617 /* Determine the Serdes electrical interface */
618 #define PORT_HW_CFG_NET_SERDES_IF_MASK 0x0F000000
619 #define PORT_HW_CFG_NET_SERDES_IF_SHIFT 24
620 #define PORT_HW_CFG_NET_SERDES_IF_SGMII 0x00000000
621 #define PORT_HW_CFG_NET_SERDES_IF_XFI 0x01000000
622 #define PORT_HW_CFG_NET_SERDES_IF_SFI 0x02000000
623 #define PORT_HW_CFG_NET_SERDES_IF_KR 0x03000000
624 #define PORT_HW_CFG_NET_SERDES_IF_DXGXS 0x04000000
625 #define PORT_HW_CFG_NET_SERDES_IF_KR2 0x05000000
628 u32 speed_capability_mask2; /* 0x28C */
629 #define PORT_HW_CFG_SPEED_CAPABILITY2_D3_MASK 0x0000FFFF
630 #define PORT_HW_CFG_SPEED_CAPABILITY2_D3_SHIFT 0
631 #define PORT_HW_CFG_SPEED_CAPABILITY2_D3_10M_FULL 0x00000001
632 #define PORT_HW_CFG_SPEED_CAPABILITY2_D3__ 0x00000002
633 #define PORT_HW_CFG_SPEED_CAPABILITY2_D3___ 0x00000004
634 #define PORT_HW_CFG_SPEED_CAPABILITY2_D3_100M_FULL 0x00000008
635 #define PORT_HW_CFG_SPEED_CAPABILITY2_D3_1G 0x00000010
636 #define PORT_HW_CFG_SPEED_CAPABILITY2_D3_2_DOT_5G 0x00000020
637 #define PORT_HW_CFG_SPEED_CAPABILITY2_D3_10G 0x00000040
638 #define PORT_HW_CFG_SPEED_CAPABILITY2_D3_20G 0x00000080
640 #define PORT_HW_CFG_SPEED_CAPABILITY2_D0_MASK 0xFFFF0000
641 #define PORT_HW_CFG_SPEED_CAPABILITY2_D0_SHIFT 16
642 #define PORT_HW_CFG_SPEED_CAPABILITY2_D0_10M_FULL 0x00010000
643 #define PORT_HW_CFG_SPEED_CAPABILITY2_D0__ 0x00020000
644 #define PORT_HW_CFG_SPEED_CAPABILITY2_D0___ 0x00040000
645 #define PORT_HW_CFG_SPEED_CAPABILITY2_D0_100M_FULL 0x00080000
646 #define PORT_HW_CFG_SPEED_CAPABILITY2_D0_1G 0x00100000
647 #define PORT_HW_CFG_SPEED_CAPABILITY2_D0_2_DOT_5G 0x00200000
648 #define PORT_HW_CFG_SPEED_CAPABILITY2_D0_10G 0x00400000
649 #define PORT_HW_CFG_SPEED_CAPABILITY2_D0_20G 0x00800000
652 /* In the case where two media types (e.g. copper and fiber) are
653 present and electrically active at the same time, PHY Selection
654 will determine which of the two PHYs will be designated as the
655 Active PHY and used for a connection to the network. */
656 u32 multi_phy_config; /* 0x290 */
657 #define PORT_HW_CFG_PHY_SELECTION_MASK 0x00000007
658 #define PORT_HW_CFG_PHY_SELECTION_SHIFT 0
659 #define PORT_HW_CFG_PHY_SELECTION_HARDWARE_DEFAULT 0x00000000
660 #define PORT_HW_CFG_PHY_SELECTION_FIRST_PHY 0x00000001
661 #define PORT_HW_CFG_PHY_SELECTION_SECOND_PHY 0x00000002
662 #define PORT_HW_CFG_PHY_SELECTION_FIRST_PHY_PRIORITY 0x00000003
663 #define PORT_HW_CFG_PHY_SELECTION_SECOND_PHY_PRIORITY 0x00000004
665 /* When enabled, all second phy nvram parameters will be swapped
666 with the first phy parameters */
667 #define PORT_HW_CFG_PHY_SWAPPED_MASK 0x00000008
668 #define PORT_HW_CFG_PHY_SWAPPED_SHIFT 3
669 #define PORT_HW_CFG_PHY_SWAPPED_DISABLED 0x00000000
670 #define PORT_HW_CFG_PHY_SWAPPED_ENABLED 0x00000008
673 /* Address of the second external phy */
674 u32 external_phy_config2; /* 0x294 */
675 #define PORT_HW_CFG_XGXS_EXT_PHY2_ADDR_MASK 0x000000FF
676 #define PORT_HW_CFG_XGXS_EXT_PHY2_ADDR_SHIFT 0
678 /* The second XGXS external PHY type */
679 #define PORT_HW_CFG_XGXS_EXT_PHY2_TYPE_MASK 0x0000FF00
680 #define PORT_HW_CFG_XGXS_EXT_PHY2_TYPE_SHIFT 8
681 #define PORT_HW_CFG_XGXS_EXT_PHY2_TYPE_DIRECT 0x00000000
682 #define PORT_HW_CFG_XGXS_EXT_PHY2_TYPE_BCM8071 0x00000100
683 #define PORT_HW_CFG_XGXS_EXT_PHY2_TYPE_BCM8072 0x00000200
684 #define PORT_HW_CFG_XGXS_EXT_PHY2_TYPE_BCM8073 0x00000300
685 #define PORT_HW_CFG_XGXS_EXT_PHY2_TYPE_BCM8705 0x00000400
686 #define PORT_HW_CFG_XGXS_EXT_PHY2_TYPE_BCM8706 0x00000500
687 #define PORT_HW_CFG_XGXS_EXT_PHY2_TYPE_BCM8726 0x00000600
688 #define PORT_HW_CFG_XGXS_EXT_PHY2_TYPE_BCM8481 0x00000700
689 #define PORT_HW_CFG_XGXS_EXT_PHY2_TYPE_SFX7101 0x00000800
690 #define PORT_HW_CFG_XGXS_EXT_PHY2_TYPE_BCM8727 0x00000900
691 #define PORT_HW_CFG_XGXS_EXT_PHY2_TYPE_BCM8727_NOC 0x00000a00
692 #define PORT_HW_CFG_XGXS_EXT_PHY2_TYPE_BCM84823 0x00000b00
693 #define PORT_HW_CFG_XGXS_EXT_PHY2_TYPE_BCM54640 0x00000c00
694 #define PORT_HW_CFG_XGXS_EXT_PHY2_TYPE_BCM84833 0x00000d00
695 #define PORT_HW_CFG_XGXS_EXT_PHY2_TYPE_BCM54618SE 0x00000e00
696 #define PORT_HW_CFG_XGXS_EXT_PHY2_TYPE_BCM8722 0x00000f00
697 #define PORT_HW_CFG_XGXS_EXT_PHY2_TYPE_BCM54616 0x00001000
698 #define PORT_HW_CFG_XGXS_EXT_PHY2_TYPE_BCM84834 0x00001100
699 #define PORT_HW_CFG_XGXS_EXT_PHY2_TYPE_FAILURE 0x0000fd00
700 #define PORT_HW_CFG_XGXS_EXT_PHY2_TYPE_NOT_CONN 0x0000ff00
703 /* 4 times 16 bits for all 4 lanes. For some external PHYs (such as
704 8706, 8726 and 8727) not all 4 values are needed. */
705 u16 xgxs_config2_rx[4]; /* 0x296 */
706 u16 xgxs_config2_tx[4]; /* 0x2A0 */
709 #define PORT_HW_CFG_LANE_SWAP_CFG_MASK 0x0000ffff
710 #define PORT_HW_CFG_LANE_SWAP_CFG_SHIFT 0
712 #define PORT_HW_CFG_LANE_SWAP_CFG_01230123 0x00001b1b
714 #define PORT_HW_CFG_LANE_SWAP_CFG_01233210 0x00001be4
716 #define PORT_HW_CFG_LANE_SWAP_CFG_31203120 0x0000d8d8
718 #define PORT_HW_CFG_LANE_SWAP_CFG_32103210 0x0000e4e4
719 #define PORT_HW_CFG_LANE_SWAP_CFG_TX_MASK 0x000000ff
720 #define PORT_HW_CFG_LANE_SWAP_CFG_TX_SHIFT 0
721 #define PORT_HW_CFG_LANE_SWAP_CFG_RX_MASK 0x0000ff00
722 #define PORT_HW_CFG_LANE_SWAP_CFG_RX_SHIFT 8
723 #define PORT_HW_CFG_LANE_SWAP_CFG_MASTER_MASK 0x0000c000
724 #define PORT_HW_CFG_LANE_SWAP_CFG_MASTER_SHIFT 14
726 /* Indicate whether to swap the external phy polarity */
727 #define PORT_HW_CFG_SWAP_PHY_POLARITY_MASK 0x00010000
728 #define PORT_HW_CFG_SWAP_PHY_POLARITY_DISABLED 0x00000000
729 #define PORT_HW_CFG_SWAP_PHY_POLARITY_ENABLED 0x00010000
732 u32 external_phy_config;
733 #define PORT_HW_CFG_XGXS_EXT_PHY_ADDR_MASK 0x000000ff
734 #define PORT_HW_CFG_XGXS_EXT_PHY_ADDR_SHIFT 0
736 #define PORT_HW_CFG_XGXS_EXT_PHY_TYPE_MASK 0x0000ff00
737 #define PORT_HW_CFG_XGXS_EXT_PHY_TYPE_SHIFT 8
738 #define PORT_HW_CFG_XGXS_EXT_PHY_TYPE_DIRECT 0x00000000
739 #define PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8071 0x00000100
740 #define PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8072 0x00000200
741 #define PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8073 0x00000300
742 #define PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8705 0x00000400
743 #define PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8706 0x00000500
744 #define PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8726 0x00000600
745 #define PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8481 0x00000700
746 #define PORT_HW_CFG_XGXS_EXT_PHY_TYPE_SFX7101 0x00000800
747 #define PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8727 0x00000900
748 #define PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8727_NOC 0x00000a00
749 #define PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM84823 0x00000b00
750 #define PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM54640 0x00000c00
751 #define PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM84833 0x00000d00
752 #define PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM54618SE 0x00000e00
753 #define PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8722 0x00000f00
754 #define PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM54616 0x00001000
755 #define PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM84834 0x00001100
756 #define PORT_HW_CFG_XGXS_EXT_PHY_TYPE_DIRECT_WC 0x0000fc00
757 #define PORT_HW_CFG_XGXS_EXT_PHY_TYPE_FAILURE 0x0000fd00
758 #define PORT_HW_CFG_XGXS_EXT_PHY_TYPE_NOT_CONN 0x0000ff00
760 #define PORT_HW_CFG_SERDES_EXT_PHY_ADDR_MASK 0x00ff0000
761 #define PORT_HW_CFG_SERDES_EXT_PHY_ADDR_SHIFT 16
763 #define PORT_HW_CFG_SERDES_EXT_PHY_TYPE_MASK 0xff000000
764 #define PORT_HW_CFG_SERDES_EXT_PHY_TYPE_SHIFT 24
765 #define PORT_HW_CFG_SERDES_EXT_PHY_TYPE_DIRECT 0x00000000
766 #define PORT_HW_CFG_SERDES_EXT_PHY_TYPE_BCM5482 0x01000000
767 #define PORT_HW_CFG_SERDES_EXT_PHY_TYPE_DIRECT_SD 0x02000000
768 #define PORT_HW_CFG_SERDES_EXT_PHY_TYPE_NOT_CONN 0xff000000
770 u32 speed_capability_mask;
771 #define PORT_HW_CFG_SPEED_CAPABILITY_D3_MASK 0x0000ffff
772 #define PORT_HW_CFG_SPEED_CAPABILITY_D3_SHIFT 0
773 #define PORT_HW_CFG_SPEED_CAPABILITY_D3_10M_FULL 0x00000001
774 #define PORT_HW_CFG_SPEED_CAPABILITY_D3_10M_HALF 0x00000002
775 #define PORT_HW_CFG_SPEED_CAPABILITY_D3_100M_HALF 0x00000004
776 #define PORT_HW_CFG_SPEED_CAPABILITY_D3_100M_FULL 0x00000008
777 #define PORT_HW_CFG_SPEED_CAPABILITY_D3_1G 0x00000010
778 #define PORT_HW_CFG_SPEED_CAPABILITY_D3_2_5G 0x00000020
779 #define PORT_HW_CFG_SPEED_CAPABILITY_D3_10G 0x00000040
780 #define PORT_HW_CFG_SPEED_CAPABILITY_D3_20G 0x00000080
781 #define PORT_HW_CFG_SPEED_CAPABILITY_D3_RESERVED 0x0000f000
783 #define PORT_HW_CFG_SPEED_CAPABILITY_D0_MASK 0xffff0000
784 #define PORT_HW_CFG_SPEED_CAPABILITY_D0_SHIFT 16
785 #define PORT_HW_CFG_SPEED_CAPABILITY_D0_10M_FULL 0x00010000
786 #define PORT_HW_CFG_SPEED_CAPABILITY_D0_10M_HALF 0x00020000
787 #define PORT_HW_CFG_SPEED_CAPABILITY_D0_100M_HALF 0x00040000
788 #define PORT_HW_CFG_SPEED_CAPABILITY_D0_100M_FULL 0x00080000
789 #define PORT_HW_CFG_SPEED_CAPABILITY_D0_1G 0x00100000
790 #define PORT_HW_CFG_SPEED_CAPABILITY_D0_2_5G 0x00200000
791 #define PORT_HW_CFG_SPEED_CAPABILITY_D0_10G 0x00400000
792 #define PORT_HW_CFG_SPEED_CAPABILITY_D0_20G 0x00800000
793 #define PORT_HW_CFG_SPEED_CAPABILITY_D0_RESERVED 0xf0000000
795 /* A place to hold the original MAC address as a backup */
796 u32 backup_mac_upper; /* 0x2B4 */
797 u32 backup_mac_lower; /* 0x2B8 */
802 /****************************************************************************
803 * Shared Feature configuration *
804 ****************************************************************************/
805 struct shared_feat_cfg { /* NVRAM Offset */
807 u32 config; /* 0x450 */
808 #define SHARED_FEATURE_BMC_ECHO_MODE_EN 0x00000001
810 /* Use NVRAM values instead of HW default values */
811 #define SHARED_FEAT_CFG_OVERRIDE_PREEMPHASIS_CFG_MASK \
813 #define SHARED_FEAT_CFG_OVERRIDE_PREEMPHASIS_CFG_DISABLED \
815 #define SHARED_FEAT_CFG_OVERRIDE_PREEMPHASIS_CFG_ENABLED \
818 #define SHARED_FEAT_CFG_NCSI_ID_METHOD_MASK 0x00000008
819 #define SHARED_FEAT_CFG_NCSI_ID_METHOD_SPIO 0x00000000
820 #define SHARED_FEAT_CFG_NCSI_ID_METHOD_NVRAM 0x00000008
822 #define SHARED_FEAT_CFG_NCSI_ID_MASK 0x00000030
823 #define SHARED_FEAT_CFG_NCSI_ID_SHIFT 4
825 /* Override the OTP back to single function mode. When using GPIO,
826 high means only SF, 0 is according to CLP configuration */
827 #define SHARED_FEAT_CFG_FORCE_SF_MODE_MASK 0x00000700
828 #define SHARED_FEAT_CFG_FORCE_SF_MODE_SHIFT 8
829 #define SHARED_FEAT_CFG_FORCE_SF_MODE_MF_ALLOWED 0x00000000
830 #define SHARED_FEAT_CFG_FORCE_SF_MODE_FORCED_SF 0x00000100
831 #define SHARED_FEAT_CFG_FORCE_SF_MODE_SPIO4 0x00000200
832 #define SHARED_FEAT_CFG_FORCE_SF_MODE_SWITCH_INDEPT 0x00000300
833 #define SHARED_FEAT_CFG_FORCE_SF_MODE_AFEX_MODE 0x00000400
835 /* The interval in seconds between sending LLDP packets. Set to zero
836 to disable the feature */
837 #define SHARED_FEAT_CFG_LLDP_XMIT_INTERVAL_MASK 0x00ff0000
838 #define SHARED_FEAT_CFG_LLDP_XMIT_INTERVAL_SHIFT 16
840 /* The assigned device type ID for LLDP usage */
841 #define SHARED_FEAT_CFG_LLDP_DEVICE_TYPE_ID_MASK 0xff000000
842 #define SHARED_FEAT_CFG_LLDP_DEVICE_TYPE_ID_SHIFT 24
847 /****************************************************************************
848 * Port Feature configuration *
849 ****************************************************************************/
850 struct port_feat_cfg { /* port 0: 0x454 port 1: 0x4c8 */
853 #define PORT_FEATURE_BAR1_SIZE_MASK 0x0000000f
854 #define PORT_FEATURE_BAR1_SIZE_SHIFT 0
855 #define PORT_FEATURE_BAR1_SIZE_DISABLED 0x00000000
856 #define PORT_FEATURE_BAR1_SIZE_64K 0x00000001
857 #define PORT_FEATURE_BAR1_SIZE_128K 0x00000002
858 #define PORT_FEATURE_BAR1_SIZE_256K 0x00000003
859 #define PORT_FEATURE_BAR1_SIZE_512K 0x00000004
860 #define PORT_FEATURE_BAR1_SIZE_1M 0x00000005
861 #define PORT_FEATURE_BAR1_SIZE_2M 0x00000006
862 #define PORT_FEATURE_BAR1_SIZE_4M 0x00000007
863 #define PORT_FEATURE_BAR1_SIZE_8M 0x00000008
864 #define PORT_FEATURE_BAR1_SIZE_16M 0x00000009
865 #define PORT_FEATURE_BAR1_SIZE_32M 0x0000000a
866 #define PORT_FEATURE_BAR1_SIZE_64M 0x0000000b
867 #define PORT_FEATURE_BAR1_SIZE_128M 0x0000000c
868 #define PORT_FEATURE_BAR1_SIZE_256M 0x0000000d
869 #define PORT_FEATURE_BAR1_SIZE_512M 0x0000000e
870 #define PORT_FEATURE_BAR1_SIZE_1G 0x0000000f
871 #define PORT_FEATURE_BAR2_SIZE_MASK 0x000000f0
872 #define PORT_FEATURE_BAR2_SIZE_SHIFT 4
873 #define PORT_FEATURE_BAR2_SIZE_DISABLED 0x00000000
874 #define PORT_FEATURE_BAR2_SIZE_64K 0x00000010
875 #define PORT_FEATURE_BAR2_SIZE_128K 0x00000020
876 #define PORT_FEATURE_BAR2_SIZE_256K 0x00000030
877 #define PORT_FEATURE_BAR2_SIZE_512K 0x00000040
878 #define PORT_FEATURE_BAR2_SIZE_1M 0x00000050
879 #define PORT_FEATURE_BAR2_SIZE_2M 0x00000060
880 #define PORT_FEATURE_BAR2_SIZE_4M 0x00000070
881 #define PORT_FEATURE_BAR2_SIZE_8M 0x00000080
882 #define PORT_FEATURE_BAR2_SIZE_16M 0x00000090
883 #define PORT_FEATURE_BAR2_SIZE_32M 0x000000a0
884 #define PORT_FEATURE_BAR2_SIZE_64M 0x000000b0
885 #define PORT_FEATURE_BAR2_SIZE_128M 0x000000c0
886 #define PORT_FEATURE_BAR2_SIZE_256M 0x000000d0
887 #define PORT_FEATURE_BAR2_SIZE_512M 0x000000e0
888 #define PORT_FEATURE_BAR2_SIZE_1G 0x000000f0
890 #define PORT_FEAT_CFG_DCBX_MASK 0x00000100
891 #define PORT_FEAT_CFG_DCBX_DISABLED 0x00000000
892 #define PORT_FEAT_CFG_DCBX_ENABLED 0x00000100
894 #define PORT_FEATURE_EN_SIZE_MASK 0x0f000000
895 #define PORT_FEATURE_EN_SIZE_SHIFT 24
896 #define PORT_FEATURE_WOL_ENABLED 0x01000000
897 #define PORT_FEATURE_MBA_ENABLED 0x02000000
898 #define PORT_FEATURE_MFW_ENABLED 0x04000000
900 /* Advertise expansion ROM even if MBA is disabled */
901 #define PORT_FEAT_CFG_FORCE_EXP_ROM_ADV_MASK 0x08000000
902 #define PORT_FEAT_CFG_FORCE_EXP_ROM_ADV_DISABLED 0x00000000
903 #define PORT_FEAT_CFG_FORCE_EXP_ROM_ADV_ENABLED 0x08000000
905 /* Check the optic vendor via i2c against a list of approved modules
906 in a separate nvram image */
907 #define PORT_FEAT_CFG_OPT_MDL_ENFRCMNT_MASK 0xe0000000
908 #define PORT_FEAT_CFG_OPT_MDL_ENFRCMNT_SHIFT 29
909 #define PORT_FEAT_CFG_OPT_MDL_ENFRCMNT_NO_ENFORCEMENT \
911 #define PORT_FEAT_CFG_OPT_MDL_ENFRCMNT_DISABLE_TX_LASER \
913 #define PORT_FEAT_CFG_OPT_MDL_ENFRCMNT_WARNING_MSG 0x40000000
914 #define PORT_FEAT_CFG_OPT_MDL_ENFRCMNT_POWER_DOWN 0x60000000
917 /* Default is used when driver sets to "auto" mode */
918 #define PORT_FEATURE_WOL_DEFAULT_MASK 0x00000003
919 #define PORT_FEATURE_WOL_DEFAULT_SHIFT 0
920 #define PORT_FEATURE_WOL_DEFAULT_DISABLE 0x00000000
921 #define PORT_FEATURE_WOL_DEFAULT_MAGIC 0x00000001
922 #define PORT_FEATURE_WOL_DEFAULT_ACPI 0x00000002
923 #define PORT_FEATURE_WOL_DEFAULT_MAGIC_AND_ACPI 0x00000003
924 #define PORT_FEATURE_WOL_RES_PAUSE_CAP 0x00000004
925 #define PORT_FEATURE_WOL_RES_ASYM_PAUSE_CAP 0x00000008
926 #define PORT_FEATURE_WOL_ACPI_UPON_MGMT 0x00000010
929 #define PORT_FEATURE_MBA_BOOT_AGENT_TYPE_MASK 0x00000007
930 #define PORT_FEATURE_MBA_BOOT_AGENT_TYPE_SHIFT 0
931 #define PORT_FEATURE_MBA_BOOT_AGENT_TYPE_PXE 0x00000000
932 #define PORT_FEATURE_MBA_BOOT_AGENT_TYPE_RPL 0x00000001
933 #define PORT_FEATURE_MBA_BOOT_AGENT_TYPE_BOOTP 0x00000002
934 #define PORT_FEATURE_MBA_BOOT_AGENT_TYPE_ISCSIB 0x00000003
935 #define PORT_FEATURE_MBA_BOOT_AGENT_TYPE_FCOE_BOOT 0x00000004
936 #define PORT_FEATURE_MBA_BOOT_AGENT_TYPE_NONE 0x00000007
938 #define PORT_FEATURE_MBA_BOOT_RETRY_MASK 0x00000038
939 #define PORT_FEATURE_MBA_BOOT_RETRY_SHIFT 3
941 #define PORT_FEATURE_MBA_RES_PAUSE_CAP 0x00000100
942 #define PORT_FEATURE_MBA_RES_ASYM_PAUSE_CAP 0x00000200
943 #define PORT_FEATURE_MBA_SETUP_PROMPT_ENABLE 0x00000400
944 #define PORT_FEATURE_MBA_HOTKEY_MASK 0x00000800
945 #define PORT_FEATURE_MBA_HOTKEY_CTRL_S 0x00000000
946 #define PORT_FEATURE_MBA_HOTKEY_CTRL_B 0x00000800
947 #define PORT_FEATURE_MBA_EXP_ROM_SIZE_MASK 0x000ff000
948 #define PORT_FEATURE_MBA_EXP_ROM_SIZE_SHIFT 12
949 #define PORT_FEATURE_MBA_EXP_ROM_SIZE_DISABLED 0x00000000
950 #define PORT_FEATURE_MBA_EXP_ROM_SIZE_2K 0x00001000
951 #define PORT_FEATURE_MBA_EXP_ROM_SIZE_4K 0x00002000
952 #define PORT_FEATURE_MBA_EXP_ROM_SIZE_8K 0x00003000
953 #define PORT_FEATURE_MBA_EXP_ROM_SIZE_16K 0x00004000
954 #define PORT_FEATURE_MBA_EXP_ROM_SIZE_32K 0x00005000
955 #define PORT_FEATURE_MBA_EXP_ROM_SIZE_64K 0x00006000
956 #define PORT_FEATURE_MBA_EXP_ROM_SIZE_128K 0x00007000
957 #define PORT_FEATURE_MBA_EXP_ROM_SIZE_256K 0x00008000
958 #define PORT_FEATURE_MBA_EXP_ROM_SIZE_512K 0x00009000
959 #define PORT_FEATURE_MBA_EXP_ROM_SIZE_1M 0x0000a000
960 #define PORT_FEATURE_MBA_EXP_ROM_SIZE_2M 0x0000b000
961 #define PORT_FEATURE_MBA_EXP_ROM_SIZE_4M 0x0000c000
962 #define PORT_FEATURE_MBA_EXP_ROM_SIZE_8M 0x0000d000
963 #define PORT_FEATURE_MBA_EXP_ROM_SIZE_16M 0x0000e000
964 #define PORT_FEATURE_MBA_EXP_ROM_SIZE_32M 0x0000f000
965 #define PORT_FEATURE_MBA_MSG_TIMEOUT_MASK 0x00f00000
966 #define PORT_FEATURE_MBA_MSG_TIMEOUT_SHIFT 20
967 #define PORT_FEATURE_MBA_BIOS_BOOTSTRAP_MASK 0x03000000
968 #define PORT_FEATURE_MBA_BIOS_BOOTSTRAP_SHIFT 24
969 #define PORT_FEATURE_MBA_BIOS_BOOTSTRAP_AUTO 0x00000000
970 #define PORT_FEATURE_MBA_BIOS_BOOTSTRAP_BBS 0x01000000
971 #define PORT_FEATURE_MBA_BIOS_BOOTSTRAP_INT18H 0x02000000
972 #define PORT_FEATURE_MBA_BIOS_BOOTSTRAP_INT19H 0x03000000
973 #define PORT_FEATURE_MBA_LINK_SPEED_MASK 0x3c000000
974 #define PORT_FEATURE_MBA_LINK_SPEED_SHIFT 26
975 #define PORT_FEATURE_MBA_LINK_SPEED_AUTO 0x00000000
976 #define PORT_FEATURE_MBA_LINK_SPEED_10HD 0x04000000
977 #define PORT_FEATURE_MBA_LINK_SPEED_10FD 0x08000000
978 #define PORT_FEATURE_MBA_LINK_SPEED_100HD 0x0c000000
979 #define PORT_FEATURE_MBA_LINK_SPEED_100FD 0x10000000
980 #define PORT_FEATURE_MBA_LINK_SPEED_1GBPS 0x14000000
981 #define PORT_FEATURE_MBA_LINK_SPEED_2_5GBPS 0x18000000
982 #define PORT_FEATURE_MBA_LINK_SPEED_10GBPS_CX4 0x1c000000
983 #define PORT_FEATURE_MBA_LINK_SPEED_20GBPS 0x20000000
985 #define PORT_FEATURE_BMC_LINK_OVERRIDE_MASK 0x00000001
986 #define PORT_FEATURE_BMC_LINK_OVERRIDE_DEFAULT 0x00000000
987 #define PORT_FEATURE_BMC_LINK_OVERRIDE_EN 0x00000001
990 #define PORT_FEATURE_MBA_VLAN_TAG_MASK 0x0000ffff
991 #define PORT_FEATURE_MBA_VLAN_TAG_SHIFT 0
992 #define PORT_FEATURE_MBA_VLAN_EN 0x00010000
995 #define PORT_FEATURE_RESOURCE_CFG_VALID 0x00000001
996 #define PORT_FEATURE_RESOURCE_CFG_DIAG 0x00000002
997 #define PORT_FEATURE_RESOURCE_CFG_L2 0x00000004
998 #define PORT_FEATURE_RESOURCE_CFG_ISCSI 0x00000008
999 #define PORT_FEATURE_RESOURCE_CFG_RDMA 0x00000010
1002 #define PORT_FEATURE_SMBUS_ADDR_MASK 0x000000fe
1003 #define PORT_FEATURE_SMBUS_ADDR_SHIFT 1
1006 #define PORT_FEAT_CFG_VF_BAR2_SIZE_MASK 0x0000000f
1007 #define PORT_FEAT_CFG_VF_BAR2_SIZE_SHIFT 0
1008 #define PORT_FEAT_CFG_VF_BAR2_SIZE_DISABLED 0x00000000
1009 #define PORT_FEAT_CFG_VF_BAR2_SIZE_4K 0x00000001
1010 #define PORT_FEAT_CFG_VF_BAR2_SIZE_8K 0x00000002
1011 #define PORT_FEAT_CFG_VF_BAR2_SIZE_16K 0x00000003
1012 #define PORT_FEAT_CFG_VF_BAR2_SIZE_32K 0x00000004
1013 #define PORT_FEAT_CFG_VF_BAR2_SIZE_64K 0x00000005
1014 #define PORT_FEAT_CFG_VF_BAR2_SIZE_128K 0x00000006
1015 #define PORT_FEAT_CFG_VF_BAR2_SIZE_256K 0x00000007
1016 #define PORT_FEAT_CFG_VF_BAR2_SIZE_512K 0x00000008
1017 #define PORT_FEAT_CFG_VF_BAR2_SIZE_1M 0x00000009
1018 #define PORT_FEAT_CFG_VF_BAR2_SIZE_2M 0x0000000a
1019 #define PORT_FEAT_CFG_VF_BAR2_SIZE_4M 0x0000000b
1020 #define PORT_FEAT_CFG_VF_BAR2_SIZE_8M 0x0000000c
1021 #define PORT_FEAT_CFG_VF_BAR2_SIZE_16M 0x0000000d
1022 #define PORT_FEAT_CFG_VF_BAR2_SIZE_32M 0x0000000e
1023 #define PORT_FEAT_CFG_VF_BAR2_SIZE_64M 0x0000000f
1025 u32 link_config; /* Used as HW defaults for the driver */
1026 #define PORT_FEATURE_CONNECTED_SWITCH_MASK 0x03000000
1027 #define PORT_FEATURE_CONNECTED_SWITCH_SHIFT 24
1028 /* (forced) low speed switch (< 10G) */
1029 #define PORT_FEATURE_CON_SWITCH_1G_SWITCH 0x00000000
1030 /* (forced) high speed switch (>= 10G) */
1031 #define PORT_FEATURE_CON_SWITCH_10G_SWITCH 0x01000000
1032 #define PORT_FEATURE_CON_SWITCH_AUTO_DETECT 0x02000000
1033 #define PORT_FEATURE_CON_SWITCH_ONE_TIME_DETECT 0x03000000
1035 #define PORT_FEATURE_LINK_SPEED_MASK 0x000f0000
1036 #define PORT_FEATURE_LINK_SPEED_SHIFT 16
1037 #define PORT_FEATURE_LINK_SPEED_AUTO 0x00000000
1038 #define PORT_FEATURE_LINK_SPEED_10M_FULL 0x00010000
1039 #define PORT_FEATURE_LINK_SPEED_10M_HALF 0x00020000
1040 #define PORT_FEATURE_LINK_SPEED_100M_HALF 0x00030000
1041 #define PORT_FEATURE_LINK_SPEED_100M_FULL 0x00040000
1042 #define PORT_FEATURE_LINK_SPEED_1G 0x00050000
1043 #define PORT_FEATURE_LINK_SPEED_2_5G 0x00060000
1044 #define PORT_FEATURE_LINK_SPEED_10G_CX4 0x00070000
1045 #define PORT_FEATURE_LINK_SPEED_20G 0x00080000
1047 #define PORT_FEATURE_FLOW_CONTROL_MASK 0x00000700
1048 #define PORT_FEATURE_FLOW_CONTROL_SHIFT 8
1049 #define PORT_FEATURE_FLOW_CONTROL_AUTO 0x00000000
1050 #define PORT_FEATURE_FLOW_CONTROL_TX 0x00000100
1051 #define PORT_FEATURE_FLOW_CONTROL_RX 0x00000200
1052 #define PORT_FEATURE_FLOW_CONTROL_BOTH 0x00000300
1053 #define PORT_FEATURE_FLOW_CONTROL_NONE 0x00000400
1055 /* The default for MCP link configuration,
1056 uses the same defines as link_config */
1057 u32 mfw_wol_link_cfg;
1059 /* The default for the driver of the second external phy,
1060 uses the same defines as link_config */
1061 u32 link_config2; /* 0x47C */
1063 /* The default for MCP of the second external phy,
1064 uses the same defines as link_config */
1065 u32 mfw_wol_link_cfg2; /* 0x480 */
1068 /* EEE power saving mode */
1069 u32 eee_power_mode; /* 0x484 */
1070 #define PORT_FEAT_CFG_EEE_POWER_MODE_MASK 0x000000FF
1071 #define PORT_FEAT_CFG_EEE_POWER_MODE_SHIFT 0
1072 #define PORT_FEAT_CFG_EEE_POWER_MODE_DISABLED 0x00000000
1073 #define PORT_FEAT_CFG_EEE_POWER_MODE_BALANCED 0x00000001
1074 #define PORT_FEAT_CFG_EEE_POWER_MODE_AGGRESSIVE 0x00000002
1075 #define PORT_FEAT_CFG_EEE_POWER_MODE_LOW_LATENCY 0x00000003
1078 u32 Reserved2[16]; /* 0x488 */
1082 /****************************************************************************
1083 * Device Information *
1084 ****************************************************************************/
1085 struct shm_dev_info { /* size */
1087 u32 bc_rev; /* 8 bits each: major, minor, build */ /* 4 */
1089 struct shared_hw_cfg shared_hw_config; /* 40 */
1091 struct port_hw_cfg port_hw_config[PORT_MAX]; /* 400*2=800 */
1093 struct shared_feat_cfg shared_feature_config; /* 4 */
1095 struct port_feat_cfg port_feature_config[PORT_MAX];/* 116*2=232 */
1100 #if !defined(__LITTLE_ENDIAN) && !defined(__BIG_ENDIAN)
1101 #error "Missing either LITTLE_ENDIAN or BIG_ENDIAN definition."
1112 #define E1_FUNC_MAX 2
1113 #define E1H_FUNC_MAX 8
1114 #define E2_FUNC_MAX 4 /* per path */
1123 #define E2_VF_MAX 64 /* HC_REG_VF_CONFIGURATION_SIZE */
1124 /* This value (in milliseconds) determines the frequency of the driver
1125 * issuing the PULSE message code. The firmware monitors this periodic
1126 * pulse to determine when to switch to an OS-absent mode. */
1127 #define DRV_PULSE_PERIOD_MS 250
1129 /* This value (in milliseconds) determines how long the driver should
1130 * wait for an acknowledgement from the firmware before timing out. Once
1131 * the firmware has timed out, the driver will assume there is no firmware
1132 * running and there won't be any firmware-driver synchronization during a
1134 #define FW_ACK_TIME_OUT_MS 5000
1136 #define FW_ACK_POLL_TIME_MS 1
1138 #define FW_ACK_NUM_OF_POLL (FW_ACK_TIME_OUT_MS/FW_ACK_POLL_TIME_MS)
1140 #define MFW_TRACE_SIGNATURE 0x54524342
1142 /****************************************************************************
1143 * Driver <-> FW Mailbox *
1144 ****************************************************************************/
1145 struct drv_port_mb {
1148 /* Driver should update this field on any link change event */
1150 #define LINK_STATUS_NONE (0<<0)
1151 #define LINK_STATUS_LINK_FLAG_MASK 0x00000001
1152 #define LINK_STATUS_LINK_UP 0x00000001
1153 #define LINK_STATUS_SPEED_AND_DUPLEX_MASK 0x0000001E
1154 #define LINK_STATUS_SPEED_AND_DUPLEX_AN_NOT_COMPLETE (0<<1)
1155 #define LINK_STATUS_SPEED_AND_DUPLEX_10THD (1<<1)
1156 #define LINK_STATUS_SPEED_AND_DUPLEX_10TFD (2<<1)
1157 #define LINK_STATUS_SPEED_AND_DUPLEX_100TXHD (3<<1)
1158 #define LINK_STATUS_SPEED_AND_DUPLEX_100T4 (4<<1)
1159 #define LINK_STATUS_SPEED_AND_DUPLEX_100TXFD (5<<1)
1160 #define LINK_STATUS_SPEED_AND_DUPLEX_1000THD (6<<1)
1161 #define LINK_STATUS_SPEED_AND_DUPLEX_1000TFD (7<<1)
1162 #define LINK_STATUS_SPEED_AND_DUPLEX_1000XFD (7<<1)
1163 #define LINK_STATUS_SPEED_AND_DUPLEX_2500THD (8<<1)
1164 #define LINK_STATUS_SPEED_AND_DUPLEX_2500TFD (9<<1)
1165 #define LINK_STATUS_SPEED_AND_DUPLEX_2500XFD (9<<1)
1166 #define LINK_STATUS_SPEED_AND_DUPLEX_10GTFD (10<<1)
1167 #define LINK_STATUS_SPEED_AND_DUPLEX_10GXFD (10<<1)
1168 #define LINK_STATUS_SPEED_AND_DUPLEX_20GTFD (11<<1)
1169 #define LINK_STATUS_SPEED_AND_DUPLEX_20GXFD (11<<1)
1171 #define LINK_STATUS_AUTO_NEGOTIATE_FLAG_MASK 0x00000020
1172 #define LINK_STATUS_AUTO_NEGOTIATE_ENABLED 0x00000020
1174 #define LINK_STATUS_AUTO_NEGOTIATE_COMPLETE 0x00000040
1175 #define LINK_STATUS_PARALLEL_DETECTION_FLAG_MASK 0x00000080
1176 #define LINK_STATUS_PARALLEL_DETECTION_USED 0x00000080
1178 #define LINK_STATUS_LINK_PARTNER_1000TFD_CAPABLE 0x00000200
1179 #define LINK_STATUS_LINK_PARTNER_1000THD_CAPABLE 0x00000400
1180 #define LINK_STATUS_LINK_PARTNER_100T4_CAPABLE 0x00000800
1181 #define LINK_STATUS_LINK_PARTNER_100TXFD_CAPABLE 0x00001000
1182 #define LINK_STATUS_LINK_PARTNER_100TXHD_CAPABLE 0x00002000
1183 #define LINK_STATUS_LINK_PARTNER_10TFD_CAPABLE 0x00004000
1184 #define LINK_STATUS_LINK_PARTNER_10THD_CAPABLE 0x00008000
1186 #define LINK_STATUS_TX_FLOW_CONTROL_FLAG_MASK 0x00010000
1187 #define LINK_STATUS_TX_FLOW_CONTROL_ENABLED 0x00010000
1189 #define LINK_STATUS_RX_FLOW_CONTROL_FLAG_MASK 0x00020000
1190 #define LINK_STATUS_RX_FLOW_CONTROL_ENABLED 0x00020000
1192 #define LINK_STATUS_LINK_PARTNER_FLOW_CONTROL_MASK 0x000C0000
1193 #define LINK_STATUS_LINK_PARTNER_NOT_PAUSE_CAPABLE (0<<18)
1194 #define LINK_STATUS_LINK_PARTNER_SYMMETRIC_PAUSE (1<<18)
1195 #define LINK_STATUS_LINK_PARTNER_ASYMMETRIC_PAUSE (2<<18)
1196 #define LINK_STATUS_LINK_PARTNER_BOTH_PAUSE (3<<18)
1198 #define LINK_STATUS_SERDES_LINK 0x00100000
1200 #define LINK_STATUS_LINK_PARTNER_2500XFD_CAPABLE 0x00200000
1201 #define LINK_STATUS_LINK_PARTNER_2500XHD_CAPABLE 0x00400000
1202 #define LINK_STATUS_LINK_PARTNER_10GXFD_CAPABLE 0x00800000
1203 #define LINK_STATUS_LINK_PARTNER_20GXFD_CAPABLE 0x10000000
1205 #define LINK_STATUS_PFC_ENABLED 0x20000000
1207 #define LINK_STATUS_PHYSICAL_LINK_FLAG 0x40000000
1208 #define LINK_STATUS_SFP_TX_FAULT 0x80000000
1214 /* MCP firmware does not use this field */
1215 u32 ext_phy_fw_version;
1220 struct drv_func_mb {
1223 #define DRV_MSG_CODE_MASK 0xffff0000
1224 #define DRV_MSG_CODE_LOAD_REQ 0x10000000
1225 #define DRV_MSG_CODE_LOAD_DONE 0x11000000
1226 #define DRV_MSG_CODE_UNLOAD_REQ_WOL_EN 0x20000000
1227 #define DRV_MSG_CODE_UNLOAD_REQ_WOL_DIS 0x20010000
1228 #define DRV_MSG_CODE_UNLOAD_REQ_WOL_MCP 0x20020000
1229 #define DRV_MSG_CODE_UNLOAD_DONE 0x21000000
1230 #define DRV_MSG_CODE_DCC_OK 0x30000000
1231 #define DRV_MSG_CODE_DCC_FAILURE 0x31000000
1232 #define DRV_MSG_CODE_DIAG_ENTER_REQ 0x50000000
1233 #define DRV_MSG_CODE_DIAG_EXIT_REQ 0x60000000
1234 #define DRV_MSG_CODE_VALIDATE_KEY 0x70000000
1235 #define DRV_MSG_CODE_GET_CURR_KEY 0x80000000
1236 #define DRV_MSG_CODE_GET_UPGRADE_KEY 0x81000000
1237 #define DRV_MSG_CODE_GET_MANUF_KEY 0x82000000
1238 #define DRV_MSG_CODE_LOAD_L2B_PRAM 0x90000000
1240 * The optic module verification command requires bootcode
1241 * v5.0.6 or later, te specific optic module verification command
1242 * requires bootcode v5.2.12 or later
1244 #define DRV_MSG_CODE_VRFY_FIRST_PHY_OPT_MDL 0xa0000000
1245 #define REQ_BC_VER_4_VRFY_FIRST_PHY_OPT_MDL 0x00050006
1246 #define DRV_MSG_CODE_VRFY_SPECIFIC_PHY_OPT_MDL 0xa1000000
1247 #define REQ_BC_VER_4_VRFY_SPECIFIC_PHY_OPT_MDL 0x00050234
1248 #define DRV_MSG_CODE_VRFY_AFEX_SUPPORTED 0xa2000000
1249 #define REQ_BC_VER_4_VRFY_AFEX_SUPPORTED 0x00070002
1250 #define REQ_BC_VER_4_SFP_TX_DISABLE_SUPPORTED 0x00070014
1251 #define REQ_BC_VER_4_MT_SUPPORTED 0x00070201
1252 #define REQ_BC_VER_4_PFC_STATS_SUPPORTED 0x00070201
1253 #define REQ_BC_VER_4_FCOE_FEATURES 0x00070209
1255 #define DRV_MSG_CODE_DCBX_ADMIN_PMF_MSG 0xb0000000
1256 #define DRV_MSG_CODE_DCBX_PMF_DRV_OK 0xb2000000
1257 #define REQ_BC_VER_4_DCBX_ADMIN_MSG_NON_PMF 0x00070401
1259 #define DRV_MSG_CODE_VF_DISABLED_DONE 0xc0000000
1261 #define DRV_MSG_CODE_AFEX_DRIVER_SETMAC 0xd0000000
1262 #define DRV_MSG_CODE_AFEX_LISTGET_ACK 0xd1000000
1263 #define DRV_MSG_CODE_AFEX_LISTSET_ACK 0xd2000000
1264 #define DRV_MSG_CODE_AFEX_STATSGET_ACK 0xd3000000
1265 #define DRV_MSG_CODE_AFEX_VIFSET_ACK 0xd4000000
1267 #define DRV_MSG_CODE_DRV_INFO_ACK 0xd8000000
1268 #define DRV_MSG_CODE_DRV_INFO_NACK 0xd9000000
1270 #define DRV_MSG_CODE_EEE_RESULTS_ACK 0xda000000
1272 #define DRV_MSG_CODE_SET_MF_BW 0xe0000000
1273 #define REQ_BC_VER_4_SET_MF_BW 0x00060202
1274 #define DRV_MSG_CODE_SET_MF_BW_ACK 0xe1000000
1276 #define DRV_MSG_CODE_LINK_STATUS_CHANGED 0x01000000
1278 #define DRV_MSG_CODE_INITIATE_FLR 0x02000000
1279 #define REQ_BC_VER_4_INITIATE_FLR 0x00070213
1281 #define BIOS_MSG_CODE_LIC_CHALLENGE 0xff010000
1282 #define BIOS_MSG_CODE_LIC_RESPONSE 0xff020000
1283 #define BIOS_MSG_CODE_VIRT_MAC_PRIM 0xff030000
1284 #define BIOS_MSG_CODE_VIRT_MAC_ISCSI 0xff040000
1286 #define DRV_MSG_SEQ_NUMBER_MASK 0x0000ffff
1289 #define DRV_MSG_CODE_SET_MF_BW_MIN_MASK 0x00ff0000
1290 #define DRV_MSG_CODE_SET_MF_BW_MAX_MASK 0xff000000
1292 #define DRV_MSG_CODE_UNLOAD_SKIP_LINK_RESET 0x00000002
1294 #define DRV_MSG_CODE_LOAD_REQ_WITH_LFA 0x0000100a
1296 #define FW_MSG_CODE_MASK 0xffff0000
1297 #define FW_MSG_CODE_DRV_LOAD_COMMON 0x10100000
1298 #define FW_MSG_CODE_DRV_LOAD_PORT 0x10110000
1299 #define FW_MSG_CODE_DRV_LOAD_FUNCTION 0x10120000
1300 /* Load common chip is supported from bc 6.0.0 */
1301 #define REQ_BC_VER_4_DRV_LOAD_COMMON_CHIP 0x00060000
1302 #define FW_MSG_CODE_DRV_LOAD_COMMON_CHIP 0x10130000
1304 #define FW_MSG_CODE_DRV_LOAD_REFUSED 0x10200000
1305 #define FW_MSG_CODE_DRV_LOAD_DONE 0x11100000
1306 #define FW_MSG_CODE_DRV_UNLOAD_COMMON 0x20100000
1307 #define FW_MSG_CODE_DRV_UNLOAD_PORT 0x20110000
1308 #define FW_MSG_CODE_DRV_UNLOAD_FUNCTION 0x20120000
1309 #define FW_MSG_CODE_DRV_UNLOAD_DONE 0x21100000
1310 #define FW_MSG_CODE_DCC_DONE 0x30100000
1311 #define FW_MSG_CODE_LLDP_DONE 0x40100000
1312 #define FW_MSG_CODE_DIAG_ENTER_DONE 0x50100000
1313 #define FW_MSG_CODE_DIAG_REFUSE 0x50200000
1314 #define FW_MSG_CODE_DIAG_EXIT_DONE 0x60100000
1315 #define FW_MSG_CODE_VALIDATE_KEY_SUCCESS 0x70100000
1316 #define FW_MSG_CODE_VALIDATE_KEY_FAILURE 0x70200000
1317 #define FW_MSG_CODE_GET_KEY_DONE 0x80100000
1318 #define FW_MSG_CODE_NO_KEY 0x80f00000
1319 #define FW_MSG_CODE_LIC_INFO_NOT_READY 0x80f80000
1320 #define FW_MSG_CODE_L2B_PRAM_LOADED 0x90100000
1321 #define FW_MSG_CODE_L2B_PRAM_T_LOAD_FAILURE 0x90210000
1322 #define FW_MSG_CODE_L2B_PRAM_C_LOAD_FAILURE 0x90220000
1323 #define FW_MSG_CODE_L2B_PRAM_X_LOAD_FAILURE 0x90230000
1324 #define FW_MSG_CODE_L2B_PRAM_U_LOAD_FAILURE 0x90240000
1325 #define FW_MSG_CODE_VRFY_OPT_MDL_SUCCESS 0xa0100000
1326 #define FW_MSG_CODE_VRFY_OPT_MDL_INVLD_IMG 0xa0200000
1327 #define FW_MSG_CODE_VRFY_OPT_MDL_UNAPPROVED 0xa0300000
1328 #define FW_MSG_CODE_VF_DISABLED_DONE 0xb0000000
1329 #define FW_MSG_CODE_HW_SET_INVALID_IMAGE 0xb0100000
1331 #define FW_MSG_CODE_AFEX_DRIVER_SETMAC_DONE 0xd0100000
1332 #define FW_MSG_CODE_AFEX_LISTGET_ACK 0xd1100000
1333 #define FW_MSG_CODE_AFEX_LISTSET_ACK 0xd2100000
1334 #define FW_MSG_CODE_AFEX_STATSGET_ACK 0xd3100000
1335 #define FW_MSG_CODE_AFEX_VIFSET_ACK 0xd4100000
1337 #define FW_MSG_CODE_DRV_INFO_ACK 0xd8100000
1338 #define FW_MSG_CODE_DRV_INFO_NACK 0xd9100000
1340 #define FW_MSG_CODE_EEE_RESULS_ACK 0xda100000
1342 #define FW_MSG_CODE_SET_MF_BW_SENT 0xe0000000
1343 #define FW_MSG_CODE_SET_MF_BW_DONE 0xe1000000
1345 #define FW_MSG_CODE_LINK_CHANGED_ACK 0x01100000
1347 #define FW_MSG_CODE_LIC_CHALLENGE 0xff010000
1348 #define FW_MSG_CODE_LIC_RESPONSE 0xff020000
1349 #define FW_MSG_CODE_VIRT_MAC_PRIM 0xff030000
1350 #define FW_MSG_CODE_VIRT_MAC_ISCSI 0xff040000
1352 #define FW_MSG_SEQ_NUMBER_MASK 0x0000ffff
1357 #define DRV_PULSE_SEQ_MASK 0x00007fff
1358 #define DRV_PULSE_SYSTEM_TIME_MASK 0xffff0000
1360 * The system time is in the format of
1361 * (year-2001)*12*32 + month*32 + day.
1363 #define DRV_PULSE_ALWAYS_ALIVE 0x00008000
1365 * Indicate to the firmware not to go into the
1366 * OS-absent when it is not getting driver pulse.
1367 * This is used for debugging as well for PXE(MBA).
1371 #define MCP_PULSE_SEQ_MASK 0x00007fff
1372 #define MCP_PULSE_ALWAYS_ALIVE 0x00008000
1373 /* Indicates to the driver not to assert due to lack
1374 * of MCP response */
1375 #define MCP_EVENT_MASK 0xffff0000
1376 #define MCP_EVENT_OTHER_DRIVER_RESET_REQ 0x00010000
1378 u32 iscsi_boot_signature;
1379 u32 iscsi_boot_block_offset;
1382 #define DRV_STATUS_PMF 0x00000001
1383 #define DRV_STATUS_VF_DISABLED 0x00000002
1384 #define DRV_STATUS_SET_MF_BW 0x00000004
1385 #define DRV_STATUS_LINK_EVENT 0x00000008
1387 #define DRV_STATUS_DCC_EVENT_MASK 0x0000ff00
1388 #define DRV_STATUS_DCC_DISABLE_ENABLE_PF 0x00000100
1389 #define DRV_STATUS_DCC_BANDWIDTH_ALLOCATION 0x00000200
1390 #define DRV_STATUS_DCC_CHANGE_MAC_ADDRESS 0x00000400
1391 #define DRV_STATUS_DCC_RESERVED1 0x00000800
1392 #define DRV_STATUS_DCC_SET_PROTOCOL 0x00001000
1393 #define DRV_STATUS_DCC_SET_PRIORITY 0x00002000
1395 #define DRV_STATUS_DCBX_EVENT_MASK 0x000f0000
1396 #define DRV_STATUS_DCBX_NEGOTIATION_RESULTS 0x00010000
1397 #define DRV_STATUS_AFEX_EVENT_MASK 0x03f00000
1398 #define DRV_STATUS_AFEX_LISTGET_REQ 0x00100000
1399 #define DRV_STATUS_AFEX_LISTSET_REQ 0x00200000
1400 #define DRV_STATUS_AFEX_STATSGET_REQ 0x00400000
1401 #define DRV_STATUS_AFEX_VIFSET_REQ 0x00800000
1403 #define DRV_STATUS_DRV_INFO_REQ 0x04000000
1405 #define DRV_STATUS_EEE_NEGOTIATION_RESULTS 0x08000000
1408 #define VIRT_MAC_SIGN_MASK 0xffff0000
1409 #define VIRT_MAC_SIGNATURE 0x564d0000
1415 /****************************************************************************
1416 * Management firmware state *
1417 ****************************************************************************/
1418 /* Allocate 440 bytes for management firmware */
1419 #define MGMTFW_STATE_WORD_SIZE 110
1421 struct mgmtfw_state {
1422 u32 opaque[MGMTFW_STATE_WORD_SIZE];
1426 /****************************************************************************
1427 * Multi-Function configuration *
1428 ****************************************************************************/
1429 struct shared_mf_cfg {
1432 #define SHARED_MF_CLP_SET_DEFAULT 0x00000000
1434 #define SHARED_MF_CLP_EXIT 0x00000001
1436 #define SHARED_MF_CLP_EXIT_DONE 0x00010000
1440 struct port_mf_cfg {
1442 u32 dynamic_cfg; /* device control channel */
1443 #define PORT_MF_CFG_E1HOV_TAG_MASK 0x0000ffff
1444 #define PORT_MF_CFG_E1HOV_TAG_SHIFT 0
1445 #define PORT_MF_CFG_E1HOV_TAG_DEFAULT PORT_MF_CFG_E1HOV_TAG_MASK
1451 struct func_mf_cfg {
1455 /* function 0 of each port cannot be hidden */
1456 #define FUNC_MF_CFG_FUNC_HIDE 0x00000001
1458 #define FUNC_MF_CFG_PROTOCOL_MASK 0x00000006
1459 #define FUNC_MF_CFG_PROTOCOL_FCOE 0x00000000
1460 #define FUNC_MF_CFG_PROTOCOL_ETHERNET 0x00000002
1461 #define FUNC_MF_CFG_PROTOCOL_ETHERNET_WITH_RDMA 0x00000004
1462 #define FUNC_MF_CFG_PROTOCOL_ISCSI 0x00000006
1463 #define FUNC_MF_CFG_PROTOCOL_DEFAULT \
1464 FUNC_MF_CFG_PROTOCOL_ETHERNET_WITH_RDMA
1466 #define FUNC_MF_CFG_FUNC_DISABLED 0x00000008
1467 #define FUNC_MF_CFG_FUNC_DELETED 0x00000010
1470 /* 0 - low priority, 3 - high priority */
1471 #define FUNC_MF_CFG_TRANSMIT_PRIORITY_MASK 0x00000300
1472 #define FUNC_MF_CFG_TRANSMIT_PRIORITY_SHIFT 8
1473 #define FUNC_MF_CFG_TRANSMIT_PRIORITY_DEFAULT 0x00000000
1476 /* value range - 0..100, increments in 100Mbps */
1477 #define FUNC_MF_CFG_MIN_BW_MASK 0x00ff0000
1478 #define FUNC_MF_CFG_MIN_BW_SHIFT 16
1479 #define FUNC_MF_CFG_MIN_BW_DEFAULT 0x00000000
1480 #define FUNC_MF_CFG_MAX_BW_MASK 0xff000000
1481 #define FUNC_MF_CFG_MAX_BW_SHIFT 24
1482 #define FUNC_MF_CFG_MAX_BW_DEFAULT 0x64000000
1484 u32 mac_upper; /* MAC */
1485 #define FUNC_MF_CFG_UPPERMAC_MASK 0x0000ffff
1486 #define FUNC_MF_CFG_UPPERMAC_SHIFT 0
1487 #define FUNC_MF_CFG_UPPERMAC_DEFAULT FUNC_MF_CFG_UPPERMAC_MASK
1489 #define FUNC_MF_CFG_LOWERMAC_DEFAULT 0xffffffff
1491 u32 e1hov_tag; /* VNI */
1492 #define FUNC_MF_CFG_E1HOV_TAG_MASK 0x0000ffff
1493 #define FUNC_MF_CFG_E1HOV_TAG_SHIFT 0
1494 #define FUNC_MF_CFG_E1HOV_TAG_DEFAULT FUNC_MF_CFG_E1HOV_TAG_MASK
1496 /* afex default VLAN ID - 12 bits */
1497 #define FUNC_MF_CFG_AFEX_VLAN_MASK 0x0fff0000
1498 #define FUNC_MF_CFG_AFEX_VLAN_SHIFT 16
1501 #define FUNC_MF_CFG_AFEX_COS_FILTER_MASK 0x000000ff
1502 #define FUNC_MF_CFG_AFEX_COS_FILTER_SHIFT 0
1503 #define FUNC_MF_CFG_AFEX_MBA_ENABLED_MASK 0x0000ff00
1504 #define FUNC_MF_CFG_AFEX_MBA_ENABLED_SHIFT 8
1505 #define FUNC_MF_CFG_AFEX_MBA_ENABLED_VAL 0x00000100
1506 #define FUNC_MF_CFG_AFEX_VLAN_MODE_MASK 0x000f0000
1507 #define FUNC_MF_CFG_AFEX_VLAN_MODE_SHIFT 16
1512 enum mf_cfg_afex_vlan_mode {
1513 FUNC_MF_CFG_AFEX_VLAN_TRUNK_MODE = 0,
1514 FUNC_MF_CFG_AFEX_VLAN_ACCESS_MODE,
1515 FUNC_MF_CFG_AFEX_VLAN_TRUNK_TAG_NATIVE_MODE
1518 /* This structure is not applicable and should not be accessed on 57711 */
1519 struct func_ext_cfg {
1521 #define MACP_FUNC_CFG_FLAGS_MASK 0x000000FF
1522 #define MACP_FUNC_CFG_FLAGS_SHIFT 0
1523 #define MACP_FUNC_CFG_FLAGS_ENABLED 0x00000001
1524 #define MACP_FUNC_CFG_FLAGS_ETHERNET 0x00000002
1525 #define MACP_FUNC_CFG_FLAGS_ISCSI_OFFLOAD 0x00000004
1526 #define MACP_FUNC_CFG_FLAGS_FCOE_OFFLOAD 0x00000008
1528 u32 iscsi_mac_addr_upper;
1529 u32 iscsi_mac_addr_lower;
1531 u32 fcoe_mac_addr_upper;
1532 u32 fcoe_mac_addr_lower;
1534 u32 fcoe_wwn_port_name_upper;
1535 u32 fcoe_wwn_port_name_lower;
1537 u32 fcoe_wwn_node_name_upper;
1538 u32 fcoe_wwn_node_name_lower;
1541 #define MF_FUNC_CFG_PRESERVE_L2_MAC (1<<0)
1542 #define MF_FUNC_CFG_PRESERVE_ISCSI_MAC (1<<1)
1543 #define MF_FUNC_CFG_PRESERVE_FCOE_MAC (1<<2)
1544 #define MF_FUNC_CFG_PRESERVE_FCOE_WWN_P (1<<3)
1545 #define MF_FUNC_CFG_PRESERVE_FCOE_WWN_N (1<<4)
1546 #define MF_FUNC_CFG_PRESERVE_TX_BW (1<<5)
1551 struct shared_mf_cfg shared_mf_config; /* 0x4 */
1553 struct port_mf_cfg port_mf_config[NVM_PATH_MAX][PORT_MAX];
1554 /* for all chips, there are 8 mf functions */
1555 struct func_mf_cfg func_mf_config[E1H_FUNC_MAX]; /* 0x18 * 8 = 0xc0 */
1557 * Extended configuration per function - this array does not exist and
1558 * should not be accessed on 57711
1560 struct func_ext_cfg func_ext_config[E1H_FUNC_MAX]; /* 0x28 * 8 = 0x140*/
1563 /****************************************************************************
1564 * Shared Memory Region *
1565 ****************************************************************************/
1566 struct shmem_region { /* SharedMem Offset (size) */
1568 u32 validity_map[PORT_MAX]; /* 0x0 (4*2 = 0x8) */
1569 #define SHR_MEM_FORMAT_REV_MASK 0xff000000
1570 #define SHR_MEM_FORMAT_REV_ID ('A'<<24)
1572 #define SHR_MEM_VALIDITY_PCI_CFG 0x00100000
1573 #define SHR_MEM_VALIDITY_MB 0x00200000
1574 #define SHR_MEM_VALIDITY_DEV_INFO 0x00400000
1575 #define SHR_MEM_VALIDITY_RESERVED 0x00000007
1576 /* One licensing bit should be set */
1577 #define SHR_MEM_VALIDITY_LIC_KEY_IN_EFFECT_MASK 0x00000038
1578 #define SHR_MEM_VALIDITY_LIC_MANUF_KEY_IN_EFFECT 0x00000008
1579 #define SHR_MEM_VALIDITY_LIC_UPGRADE_KEY_IN_EFFECT 0x00000010
1580 #define SHR_MEM_VALIDITY_LIC_NO_KEY_IN_EFFECT 0x00000020
1582 #define SHR_MEM_VALIDITY_ACTIVE_MFW_UNKNOWN 0x00000000
1583 #define SHR_MEM_VALIDITY_ACTIVE_MFW_MASK 0x000001c0
1584 #define SHR_MEM_VALIDITY_ACTIVE_MFW_IPMI 0x00000040
1585 #define SHR_MEM_VALIDITY_ACTIVE_MFW_UMP 0x00000080
1586 #define SHR_MEM_VALIDITY_ACTIVE_MFW_NCSI 0x000000c0
1587 #define SHR_MEM_VALIDITY_ACTIVE_MFW_NONE 0x000001c0
1589 struct shm_dev_info dev_info; /* 0x8 (0x438) */
1591 struct license_key drv_lic_key[PORT_MAX]; /* 0x440 (52*2=0x68) */
1593 /* FW information (for internal FW use) */
1594 u32 fw_info_fio_offset; /* 0x4a8 (0x4) */
1595 struct mgmtfw_state mgmtfw_state; /* 0x4ac (0x1b8) */
1597 struct drv_port_mb port_mb[PORT_MAX]; /* 0x664 (16*2=0x20) */
1600 /* This is a variable length array */
1601 /* the number of function depends on the chip type */
1602 struct drv_func_mb func_mb[1]; /* 0x684 (44*2/4/8=0x58/0xb0/0x160) */
1604 /* the number of function depends on the chip type */
1605 struct drv_func_mb func_mb[]; /* 0x684 (44*2/4/8=0x58/0xb0/0x160) */
1608 }; /* 57710 = 0x6dc | 57711 = 0x7E4 | 57712 = 0x734 */
1610 /****************************************************************************
1611 * Shared Memory 2 Region *
1612 ****************************************************************************/
1613 /* The fw_flr_ack is actually built in the following way: */
1615 /* 64 bit: VF ack */
1616 /* 8 bit: ios_dis_ack */
1617 /* In order to maintain endianity in the mailbox hsi, we want to keep using */
1618 /* u32. The fw must have the VF right after the PF since this is how it */
1619 /* access arrays(it expects always the VF to reside after the PF, and that */
1620 /* makes the calculation much easier for it. ) */
1621 /* In order to answer both limitations, and keep the struct small, the code */
1622 /* will abuse the structure defined here to achieve the actual partition */
1624 /****************************************************************************/
1634 struct fw_flr_ack ack;
1637 struct eee_remote_vals {
1642 /**** SUPPORT FOR SHMEM ARRRAYS ***
1643 * The SHMEM HSI is aligned on 32 bit boundaries which makes it difficult to
1644 * define arrays with storage types smaller then unsigned dwords.
1645 * The macros below add generic support for SHMEM arrays with numeric elements
1646 * that can span 2,4,8 or 16 bits. The array underlying type is a 32 bit dword
1647 * array with individual bit-filed elements accessed using shifts and masks.
1651 /* eb is the bitwidth of a single element */
1652 #define SHMEM_ARRAY_MASK(eb) ((1<<(eb))-1)
1653 #define SHMEM_ARRAY_ENTRY(i, eb) ((i)/(32/(eb)))
1655 /* the bit-position macro allows the used to flip the order of the arrays
1656 * elements on a per byte or word boundary.
1658 * example: an array with 8 entries each 4 bit wide. This array will fit into
1659 * a single dword. The diagrmas below show the array order of the nibbles.
1661 * SHMEM_ARRAY_BITPOS(i, 4, 4) defines the stadard ordering:
1664 * 0 | 1 | 2 | 3 | 4 | 5 | 6 | 7 |
1667 * SHMEM_ARRAY_BITPOS(i, 4, 8) defines a flip ordering per byte:
1670 * 1 | 0 | 3 | 2 | 5 | 4 | 7 | 6 |
1673 * SHMEM_ARRAY_BITPOS(i, 4, 16) defines a flip ordering per word:
1676 * 3 | 2 | 1 | 0 | 7 | 6 | 5 | 4 |
1679 #define SHMEM_ARRAY_BITPOS(i, eb, fb) \
1680 ((((32/(fb)) - 1 - ((i)/((fb)/(eb))) % (32/(fb))) * (fb)) + \
1681 (((i)%((fb)/(eb))) * (eb)))
1683 #define SHMEM_ARRAY_GET(a, i, eb, fb) \
1684 ((a[SHMEM_ARRAY_ENTRY(i, eb)] >> SHMEM_ARRAY_BITPOS(i, eb, fb)) & \
1685 SHMEM_ARRAY_MASK(eb))
1687 #define SHMEM_ARRAY_SET(a, i, eb, fb, val) \
1689 a[SHMEM_ARRAY_ENTRY(i, eb)] &= ~(SHMEM_ARRAY_MASK(eb) << \
1690 SHMEM_ARRAY_BITPOS(i, eb, fb)); \
1691 a[SHMEM_ARRAY_ENTRY(i, eb)] |= (((val) & SHMEM_ARRAY_MASK(eb)) << \
1692 SHMEM_ARRAY_BITPOS(i, eb, fb)); \
1696 /****START OF DCBX STRUCTURES DECLARATIONS****/
1697 #define DCBX_MAX_NUM_PRI_PG_ENTRIES 8
1698 #define DCBX_PRI_PG_BITWIDTH 4
1699 #define DCBX_PRI_PG_FBITS 8
1700 #define DCBX_PRI_PG_GET(a, i) \
1701 SHMEM_ARRAY_GET(a, i, DCBX_PRI_PG_BITWIDTH, DCBX_PRI_PG_FBITS)
1702 #define DCBX_PRI_PG_SET(a, i, val) \
1703 SHMEM_ARRAY_SET(a, i, DCBX_PRI_PG_BITWIDTH, DCBX_PRI_PG_FBITS, val)
1704 #define DCBX_MAX_NUM_PG_BW_ENTRIES 8
1705 #define DCBX_BW_PG_BITWIDTH 8
1706 #define DCBX_PG_BW_GET(a, i) \
1707 SHMEM_ARRAY_GET(a, i, DCBX_BW_PG_BITWIDTH, DCBX_BW_PG_BITWIDTH)
1708 #define DCBX_PG_BW_SET(a, i, val) \
1709 SHMEM_ARRAY_SET(a, i, DCBX_BW_PG_BITWIDTH, DCBX_BW_PG_BITWIDTH, val)
1710 #define DCBX_STRICT_PRI_PG 15
1711 #define DCBX_MAX_APP_PROTOCOL 16
1712 #define FCOE_APP_IDX 0
1713 #define ISCSI_APP_IDX 1
1714 #define PREDEFINED_APP_IDX_MAX 2
1717 /* Big/Little endian have the same representation. */
1718 struct dcbx_ets_feature {
1720 * For Admin MIB - is this feature supported by the
1721 * driver | For Local MIB - should this feature be enabled.
1728 /* Driver structure in LE */
1729 struct dcbx_pfc_feature {
1732 #define DCBX_PFC_PRI_0 0x01
1733 #define DCBX_PFC_PRI_1 0x02
1734 #define DCBX_PFC_PRI_2 0x04
1735 #define DCBX_PFC_PRI_3 0x08
1736 #define DCBX_PFC_PRI_4 0x10
1737 #define DCBX_PFC_PRI_5 0x20
1738 #define DCBX_PFC_PRI_6 0x40
1739 #define DCBX_PFC_PRI_7 0x80
1743 #elif defined(__LITTLE_ENDIAN)
1748 #define DCBX_PFC_PRI_0 0x01
1749 #define DCBX_PFC_PRI_1 0x02
1750 #define DCBX_PFC_PRI_2 0x04
1751 #define DCBX_PFC_PRI_3 0x08
1752 #define DCBX_PFC_PRI_4 0x10
1753 #define DCBX_PFC_PRI_5 0x20
1754 #define DCBX_PFC_PRI_6 0x40
1755 #define DCBX_PFC_PRI_7 0x80
1759 struct dcbx_app_priority_entry {
1764 #define DCBX_APP_ENTRY_VALID 0x01
1765 #define DCBX_APP_ENTRY_SF_MASK 0x30
1766 #define DCBX_APP_ENTRY_SF_SHIFT 4
1767 #define DCBX_APP_SF_ETH_TYPE 0x10
1768 #define DCBX_APP_SF_PORT 0x20
1769 #elif defined(__LITTLE_ENDIAN)
1771 #define DCBX_APP_ENTRY_VALID 0x01
1772 #define DCBX_APP_ENTRY_SF_MASK 0x30
1773 #define DCBX_APP_ENTRY_SF_SHIFT 4
1774 #define DCBX_APP_SF_ETH_TYPE 0x10
1775 #define DCBX_APP_SF_PORT 0x20
1782 /* FW structure in BE */
1783 struct dcbx_app_priority_feature {
1789 #elif defined(__LITTLE_ENDIAN)
1795 struct dcbx_app_priority_entry app_pri_tbl[DCBX_MAX_APP_PROTOCOL];
1798 /* FW structure in BE */
1799 struct dcbx_features {
1801 struct dcbx_ets_feature ets;
1803 struct dcbx_pfc_feature pfc;
1805 struct dcbx_app_priority_feature app;
1808 /* LLDP protocol parameters */
1809 /* FW structure in BE */
1810 struct lldp_params {
1812 u8 msg_fast_tx_interval;
1816 #define LLDP_TX_ONLY 0x01
1817 #define LLDP_RX_ONLY 0x02
1818 #define LLDP_TX_RX 0x03
1819 #define LLDP_DISABLED 0x04
1824 #elif defined(__LITTLE_ENDIAN)
1826 #define LLDP_TX_ONLY 0x01
1827 #define LLDP_RX_ONLY 0x02
1828 #define LLDP_TX_RX 0x03
1829 #define LLDP_DISABLED 0x04
1832 u8 msg_fast_tx_interval;
1838 #define REM_CHASSIS_ID_STAT_LEN 4
1839 #define REM_PORT_ID_STAT_LEN 4
1840 /* Holds remote Chassis ID TLV header, subtype and 9B of payload. */
1841 u32 peer_chassis_id[REM_CHASSIS_ID_STAT_LEN];
1842 /* Holds remote Port ID TLV header, subtype and 9B of payload. */
1843 u32 peer_port_id[REM_PORT_ID_STAT_LEN];
1846 struct lldp_dcbx_stat {
1847 #define LOCAL_CHASSIS_ID_STAT_LEN 2
1848 #define LOCAL_PORT_ID_STAT_LEN 2
1849 /* Holds local Chassis ID 8B payload of constant subtype 4. */
1850 u32 local_chassis_id[LOCAL_CHASSIS_ID_STAT_LEN];
1851 /* Holds local Port ID 8B payload of constant subtype 3. */
1852 u32 local_port_id[LOCAL_PORT_ID_STAT_LEN];
1853 /* Number of DCBX frames transmitted. */
1854 u32 num_tx_dcbx_pkts;
1855 /* Number of DCBX frames received. */
1856 u32 num_rx_dcbx_pkts;
1859 /* ADMIN MIB - DCBX local machine default configuration. */
1860 struct lldp_admin_mib {
1862 #define DCBX_ETS_CONFIG_TX_ENABLED 0x00000001
1863 #define DCBX_PFC_CONFIG_TX_ENABLED 0x00000002
1864 #define DCBX_APP_CONFIG_TX_ENABLED 0x00000004
1865 #define DCBX_ETS_RECO_TX_ENABLED 0x00000008
1866 #define DCBX_ETS_RECO_VALID 0x00000010
1867 #define DCBX_ETS_WILLING 0x00000020
1868 #define DCBX_PFC_WILLING 0x00000040
1869 #define DCBX_APP_WILLING 0x00000080
1870 #define DCBX_VERSION_CEE 0x00000100
1871 #define DCBX_VERSION_IEEE 0x00000200
1872 #define DCBX_DCBX_ENABLED 0x00000400
1873 #define DCBX_CEE_VERSION_MASK 0x0000f000
1874 #define DCBX_CEE_VERSION_SHIFT 12
1875 #define DCBX_CEE_MAX_VERSION_MASK 0x000f0000
1876 #define DCBX_CEE_MAX_VERSION_SHIFT 16
1877 struct dcbx_features features;
1880 /* REMOTE MIB - remote machine DCBX configuration. */
1881 struct lldp_remote_mib {
1884 #define DCBX_ETS_TLV_RX 0x00000001
1885 #define DCBX_PFC_TLV_RX 0x00000002
1886 #define DCBX_APP_TLV_RX 0x00000004
1887 #define DCBX_ETS_RX_ERROR 0x00000010
1888 #define DCBX_PFC_RX_ERROR 0x00000020
1889 #define DCBX_APP_RX_ERROR 0x00000040
1890 #define DCBX_ETS_REM_WILLING 0x00000100
1891 #define DCBX_PFC_REM_WILLING 0x00000200
1892 #define DCBX_APP_REM_WILLING 0x00000400
1893 #define DCBX_REMOTE_ETS_RECO_VALID 0x00001000
1894 #define DCBX_REMOTE_MIB_VALID 0x00002000
1895 struct dcbx_features features;
1899 /* LOCAL MIB - operational DCBX configuration - transmitted on Tx LLDPDU. */
1900 struct lldp_local_mib {
1902 /* Indicates if there is mismatch with negotiation results. */
1904 #define DCBX_LOCAL_ETS_ERROR 0x00000001
1905 #define DCBX_LOCAL_PFC_ERROR 0x00000002
1906 #define DCBX_LOCAL_APP_ERROR 0x00000004
1907 #define DCBX_LOCAL_PFC_MISMATCH 0x00000010
1908 #define DCBX_LOCAL_APP_MISMATCH 0x00000020
1909 #define DCBX_REMOTE_MIB_ERROR 0x00000040
1910 #define DCBX_REMOTE_ETS_TLV_NOT_FOUND 0x00000080
1911 #define DCBX_REMOTE_PFC_TLV_NOT_FOUND 0x00000100
1912 #define DCBX_REMOTE_APP_TLV_NOT_FOUND 0x00000200
1913 struct dcbx_features features;
1916 /***END OF DCBX STRUCTURES DECLARATIONS***/
1918 /***********************************************************/
1920 /***********************************************************/
1921 #define SHMEM_LINK_CONFIG_SIZE 2
1924 #define REQ_DUPLEX_PHY0_MASK 0x0000ffff
1925 #define REQ_DUPLEX_PHY0_SHIFT 0
1926 #define REQ_DUPLEX_PHY1_MASK 0xffff0000
1927 #define REQ_DUPLEX_PHY1_SHIFT 16
1929 #define REQ_FLOW_CTRL_PHY0_MASK 0x0000ffff
1930 #define REQ_FLOW_CTRL_PHY0_SHIFT 0
1931 #define REQ_FLOW_CTRL_PHY1_MASK 0xffff0000
1932 #define REQ_FLOW_CTRL_PHY1_SHIFT 16
1933 u32 req_line_speed; /* Also determine AutoNeg */
1934 #define REQ_LINE_SPD_PHY0_MASK 0x0000ffff
1935 #define REQ_LINE_SPD_PHY0_SHIFT 0
1936 #define REQ_LINE_SPD_PHY1_MASK 0xffff0000
1937 #define REQ_LINE_SPD_PHY1_SHIFT 16
1938 u32 speed_cap_mask[SHMEM_LINK_CONFIG_SIZE];
1939 u32 additional_config;
1940 #define REQ_FC_AUTO_ADV_MASK 0x0000ffff
1941 #define REQ_FC_AUTO_ADV0_SHIFT 0
1942 #define NO_LFA_DUE_TO_DCC_MASK 0x00010000
1944 #define LFA_LINK_FLAP_REASON_OFFSET 0
1945 #define LFA_LINK_FLAP_REASON_MASK 0x000000ff
1946 #define LFA_LINK_DOWN 0x1
1947 #define LFA_LOOPBACK_ENABLED 0x2
1948 #define LFA_DUPLEX_MISMATCH 0x3
1949 #define LFA_MFW_IS_TOO_OLD 0x4
1950 #define LFA_LINK_SPEED_MISMATCH 0x5
1951 #define LFA_FLOW_CTRL_MISMATCH 0x6
1952 #define LFA_SPEED_CAP_MISMATCH 0x7
1953 #define LFA_DCC_LFA_DISABLED 0x8
1954 #define LFA_EEE_MISMATCH 0x9
1956 #define LINK_FLAP_AVOIDANCE_COUNT_OFFSET 8
1957 #define LINK_FLAP_AVOIDANCE_COUNT_MASK 0x0000ff00
1959 #define LINK_FLAP_COUNT_OFFSET 16
1960 #define LINK_FLAP_COUNT_MASK 0x00ff0000
1962 #define LFA_FLAGS_MASK 0xff000000
1963 #define SHMEM_LFA_DONT_CLEAR_STAT (1<<24)
1966 struct ncsi_oem_fcoe_features {
1968 #define FCOE_FEATURES1_IOS_PER_CONNECTION_MASK 0x0000FFFF
1969 #define FCOE_FEATURES1_IOS_PER_CONNECTION_OFFSET 0
1971 #define FCOE_FEATURES1_LOGINS_PER_PORT_MASK 0xFFFF0000
1972 #define FCOE_FEATURES1_LOGINS_PER_PORT_OFFSET 16
1975 #define FCOE_FEATURES2_EXCHANGES_MASK 0x0000FFFF
1976 #define FCOE_FEATURES2_EXCHANGES_OFFSET 0
1978 #define FCOE_FEATURES2_NPIV_WWN_PER_PORT_MASK 0xFFFF0000
1979 #define FCOE_FEATURES2_NPIV_WWN_PER_PORT_OFFSET 16
1982 #define FCOE_FEATURES3_TARGETS_SUPPORTED_MASK 0x0000FFFF
1983 #define FCOE_FEATURES3_TARGETS_SUPPORTED_OFFSET 0
1985 #define FCOE_FEATURES3_OUTSTANDING_COMMANDS_MASK 0xFFFF0000
1986 #define FCOE_FEATURES3_OUTSTANDING_COMMANDS_OFFSET 16
1989 #define FCOE_FEATURES4_FEATURE_SETTINGS_MASK 0x0000000F
1990 #define FCOE_FEATURES4_FEATURE_SETTINGS_OFFSET 0
1993 struct ncsi_oem_data {
1994 u32 driver_version[4];
1995 struct ncsi_oem_fcoe_features ncsi_oem_fcoe_features;
1998 struct shmem2_region {
2000 u32 size; /* 0x0000 */
2002 u32 dcc_support; /* 0x0004 */
2003 #define SHMEM_DCC_SUPPORT_NONE 0x00000000
2004 #define SHMEM_DCC_SUPPORT_DISABLE_ENABLE_PF_TLV 0x00000001
2005 #define SHMEM_DCC_SUPPORT_BANDWIDTH_ALLOCATION_TLV 0x00000004
2006 #define SHMEM_DCC_SUPPORT_CHANGE_MAC_ADDRESS_TLV 0x00000008
2007 #define SHMEM_DCC_SUPPORT_SET_PROTOCOL_TLV 0x00000040
2008 #define SHMEM_DCC_SUPPORT_SET_PRIORITY_TLV 0x00000080
2010 u32 ext_phy_fw_version2[PORT_MAX]; /* 0x0008 */
2012 * For backwards compatibility, if the mf_cfg_addr does not exist
2013 * (the size filed is smaller than 0xc) the mf_cfg resides at the
2014 * end of struct shmem_region
2016 u32 mf_cfg_addr; /* 0x0010 */
2017 #define SHMEM_MF_CFG_ADDR_NONE 0x00000000
2019 struct fw_flr_mb flr_mb; /* 0x0014 */
2020 u32 dcbx_lldp_params_offset; /* 0x0028 */
2021 #define SHMEM_LLDP_DCBX_PARAMS_NONE 0x00000000
2022 u32 dcbx_neg_res_offset; /* 0x002c */
2023 #define SHMEM_DCBX_NEG_RES_NONE 0x00000000
2024 u32 dcbx_remote_mib_offset; /* 0x0030 */
2025 #define SHMEM_DCBX_REMOTE_MIB_NONE 0x00000000
2027 * The other shmemX_base_addr holds the other path's shmem address
2028 * required for example in case of common phy init, or for path1 to know
2029 * the address of mcp debug trace which is located in offset from shmem
2032 u32 other_shmem_base_addr; /* 0x0034 */
2033 u32 other_shmem2_base_addr; /* 0x0038 */
2035 * mcp_vf_disabled is set by the MCP to indicate the driver about VFs
2036 * which were disabled/flred
2038 u32 mcp_vf_disabled[E2_VF_MAX / 32]; /* 0x003c */
2041 * drv_ack_vf_disabled is set by the PF driver to ack handled disabled
2044 u32 drv_ack_vf_disabled[E2_FUNC_MAX][E2_VF_MAX / 32]; /* 0x0044 */
2046 u32 dcbx_lldp_dcbx_stat_offset; /* 0x0064 */
2047 #define SHMEM_LLDP_DCBX_STAT_NONE 0x00000000
2050 * edebug_driver_if field is used to transfer messages between edebug
2051 * app to the driver through shmem2.
2054 * bits 0-2 - function number / instance of driver to perform request
2055 * bits 3-5 - op code / is_ack?
2058 u32 edebug_driver_if[2]; /* 0x0068 */
2059 #define EDEBUG_DRIVER_IF_OP_CODE_GET_PHYS_ADDR 1
2060 #define EDEBUG_DRIVER_IF_OP_CODE_GET_BUS_ADDR 2
2061 #define EDEBUG_DRIVER_IF_OP_CODE_DISABLE_STAT 3
2063 u32 nvm_retain_bitmap_addr; /* 0x0070 */
2065 /* afex support of that driver */
2066 u32 afex_driver_support; /* 0x0074 */
2067 #define SHMEM_AFEX_VERSION_MASK 0x100f
2068 #define SHMEM_AFEX_SUPPORTED_VERSION_ONE 0x1001
2069 #define SHMEM_AFEX_REDUCED_DRV_LOADED 0x8000
2071 /* driver receives addr in scratchpad to which it should respond */
2072 u32 afex_scratchpad_addr_to_write[E2_FUNC_MAX];
2074 /* generic params from MCP to driver (value depends on the msg sent
2077 u32 afex_param1_to_driver[E2_FUNC_MAX]; /* 0x0088 */
2078 u32 afex_param2_to_driver[E2_FUNC_MAX]; /* 0x0098 */
2080 u32 swim_base_addr; /* 0x0108 */
2084 /* bitmap notifying which VIF profiles stored in nvram are enabled by
2087 u32 afex_profiles_enabled[2];
2089 /* generic flags controlled by the driver */
2091 #define DRV_FLAGS_DCB_CONFIGURED 0x1
2093 /* pointer to extended dev_info shared data copied from nvm image */
2094 u32 extended_dev_info_shared_addr;
2095 u32 ncsi_oem_data_addr;
2097 u32 ocsd_host_addr; /* initialized by option ROM */
2098 u32 ocbb_host_addr; /* initialized by option ROM */
2099 u32 ocsd_req_update_interval; /* initialized by option ROM */
2100 u32 temperature_in_half_celsius;
2101 u32 glob_struct_in_host;
2103 u32 dcbx_neg_res_ext_offset;
2104 #define SHMEM_DCBX_NEG_RES_EXT_NONE 0x00000000
2106 u32 drv_capabilities_flag[E2_FUNC_MAX];
2107 #define DRV_FLAGS_CAPABILITIES_LOADED_SUPPORTED 0x00000001
2108 #define DRV_FLAGS_CAPABILITIES_LOADED_L2 0x00000002
2109 #define DRV_FLAGS_CAPABILITIES_LOADED_FCOE 0x00000004
2110 #define DRV_FLAGS_CAPABILITIES_LOADED_ISCSI 0x00000008
2112 u32 extended_dev_info_shared_cfg_size;
2114 u32 dcbx_en[PORT_MAX];
2116 /* The offset points to the multi threaded meta structure */
2117 u32 multi_thread_data_offset;
2119 /* address of DMAable host address holding values from the drivers */
2120 u32 drv_info_host_addr_lo;
2121 u32 drv_info_host_addr_hi;
2123 /* general values written by the MFW (such as current version) */
2124 u32 drv_info_control;
2125 #define DRV_INFO_CONTROL_VER_MASK 0x000000ff
2126 #define DRV_INFO_CONTROL_VER_SHIFT 0
2127 #define DRV_INFO_CONTROL_OP_CODE_MASK 0x0000ff00
2128 #define DRV_INFO_CONTROL_OP_CODE_SHIFT 8
2129 u32 ibft_host_addr; /* initialized by option ROM */
2130 struct eee_remote_vals eee_remote_vals[PORT_MAX];
2131 u32 reserved[E2_FUNC_MAX];
2134 /* the status of EEE auto-negotiation
2135 * bits 15:0 the configured tx-lpi entry timer value. Depends on bit 31.
2136 * bits 19:16 the supported modes for EEE.
2137 * bits 23:20 the speeds advertised for EEE.
2138 * bits 27:24 the speeds the Link partner advertised for EEE.
2139 * The supported/adv. modes in bits 27:19 originate from the
2140 * SHMEM_EEE_XXX_ADV definitions (where XXX is replaced by speed).
2141 * bit 28 when 1'b1 EEE was requested.
2142 * bit 29 when 1'b1 tx lpi was requested.
2143 * bit 30 when 1'b1 EEE was negotiated. Tx lpi will be asserted iff
2145 * bit 31 when 1'b0 bits 15:0 contain a PORT_FEAT_CFG_EEE_ define as
2146 * value. When 1'b1 those bits contains a value times 16 microseconds.
2148 u32 eee_status[PORT_MAX];
2149 #define SHMEM_EEE_TIMER_MASK 0x0000ffff
2150 #define SHMEM_EEE_SUPPORTED_MASK 0x000f0000
2151 #define SHMEM_EEE_SUPPORTED_SHIFT 16
2152 #define SHMEM_EEE_ADV_STATUS_MASK 0x00f00000
2153 #define SHMEM_EEE_100M_ADV (1<<0)
2154 #define SHMEM_EEE_1G_ADV (1<<1)
2155 #define SHMEM_EEE_10G_ADV (1<<2)
2156 #define SHMEM_EEE_ADV_STATUS_SHIFT 20
2157 #define SHMEM_EEE_LP_ADV_STATUS_MASK 0x0f000000
2158 #define SHMEM_EEE_LP_ADV_STATUS_SHIFT 24
2159 #define SHMEM_EEE_REQUESTED_BIT 0x10000000
2160 #define SHMEM_EEE_LPI_REQUESTED_BIT 0x20000000
2161 #define SHMEM_EEE_ACTIVE_BIT 0x40000000
2162 #define SHMEM_EEE_TIME_OUTPUT_BIT 0x80000000
2164 u32 sizeof_port_stats;
2166 /* Link Flap Avoidance */
2167 u32 lfa_host_addr[PORT_MAX];
2170 u32 reserved2; /* Offset 0x148 */
2171 u32 reserved3; /* Offset 0x14C */
2172 u32 reserved4; /* Offset 0x150 */
2173 u32 link_attr_sync[PORT_MAX]; /* Offset 0x154 */
2174 #define LINK_ATTR_SYNC_KR2_ENABLE (1<<0)
2179 u32 rx_stat_ifhcinoctets;
2180 u32 rx_stat_ifhcinbadoctets;
2181 u32 rx_stat_etherstatsfragments;
2182 u32 rx_stat_ifhcinucastpkts;
2183 u32 rx_stat_ifhcinmulticastpkts;
2184 u32 rx_stat_ifhcinbroadcastpkts;
2185 u32 rx_stat_dot3statsfcserrors;
2186 u32 rx_stat_dot3statsalignmenterrors;
2187 u32 rx_stat_dot3statscarriersenseerrors;
2188 u32 rx_stat_xonpauseframesreceived;
2189 u32 rx_stat_xoffpauseframesreceived;
2190 u32 rx_stat_maccontrolframesreceived;
2191 u32 rx_stat_xoffstateentered;
2192 u32 rx_stat_dot3statsframestoolong;
2193 u32 rx_stat_etherstatsjabbers;
2194 u32 rx_stat_etherstatsundersizepkts;
2195 u32 rx_stat_etherstatspkts64octets;
2196 u32 rx_stat_etherstatspkts65octetsto127octets;
2197 u32 rx_stat_etherstatspkts128octetsto255octets;
2198 u32 rx_stat_etherstatspkts256octetsto511octets;
2199 u32 rx_stat_etherstatspkts512octetsto1023octets;
2200 u32 rx_stat_etherstatspkts1024octetsto1522octets;
2201 u32 rx_stat_etherstatspktsover1522octets;
2203 u32 rx_stat_falsecarriererrors;
2205 u32 tx_stat_ifhcoutoctets;
2206 u32 tx_stat_ifhcoutbadoctets;
2207 u32 tx_stat_etherstatscollisions;
2208 u32 tx_stat_outxonsent;
2209 u32 tx_stat_outxoffsent;
2210 u32 tx_stat_flowcontroldone;
2211 u32 tx_stat_dot3statssinglecollisionframes;
2212 u32 tx_stat_dot3statsmultiplecollisionframes;
2213 u32 tx_stat_dot3statsdeferredtransmissions;
2214 u32 tx_stat_dot3statsexcessivecollisions;
2215 u32 tx_stat_dot3statslatecollisions;
2216 u32 tx_stat_ifhcoutucastpkts;
2217 u32 tx_stat_ifhcoutmulticastpkts;
2218 u32 tx_stat_ifhcoutbroadcastpkts;
2219 u32 tx_stat_etherstatspkts64octets;
2220 u32 tx_stat_etherstatspkts65octetsto127octets;
2221 u32 tx_stat_etherstatspkts128octetsto255octets;
2222 u32 tx_stat_etherstatspkts256octetsto511octets;
2223 u32 tx_stat_etherstatspkts512octetsto1023octets;
2224 u32 tx_stat_etherstatspkts1024octetsto1522octets;
2225 u32 tx_stat_etherstatspktsover1522octets;
2226 u32 tx_stat_dot3statsinternalmactransmiterrors;
2230 struct bmac1_stats {
2231 u32 tx_stat_gtpkt_lo;
2232 u32 tx_stat_gtpkt_hi;
2233 u32 tx_stat_gtxpf_lo;
2234 u32 tx_stat_gtxpf_hi;
2235 u32 tx_stat_gtfcs_lo;
2236 u32 tx_stat_gtfcs_hi;
2237 u32 tx_stat_gtmca_lo;
2238 u32 tx_stat_gtmca_hi;
2239 u32 tx_stat_gtbca_lo;
2240 u32 tx_stat_gtbca_hi;
2241 u32 tx_stat_gtfrg_lo;
2242 u32 tx_stat_gtfrg_hi;
2243 u32 tx_stat_gtovr_lo;
2244 u32 tx_stat_gtovr_hi;
2245 u32 tx_stat_gt64_lo;
2246 u32 tx_stat_gt64_hi;
2247 u32 tx_stat_gt127_lo;
2248 u32 tx_stat_gt127_hi;
2249 u32 tx_stat_gt255_lo;
2250 u32 tx_stat_gt255_hi;
2251 u32 tx_stat_gt511_lo;
2252 u32 tx_stat_gt511_hi;
2253 u32 tx_stat_gt1023_lo;
2254 u32 tx_stat_gt1023_hi;
2255 u32 tx_stat_gt1518_lo;
2256 u32 tx_stat_gt1518_hi;
2257 u32 tx_stat_gt2047_lo;
2258 u32 tx_stat_gt2047_hi;
2259 u32 tx_stat_gt4095_lo;
2260 u32 tx_stat_gt4095_hi;
2261 u32 tx_stat_gt9216_lo;
2262 u32 tx_stat_gt9216_hi;
2263 u32 tx_stat_gt16383_lo;
2264 u32 tx_stat_gt16383_hi;
2265 u32 tx_stat_gtmax_lo;
2266 u32 tx_stat_gtmax_hi;
2267 u32 tx_stat_gtufl_lo;
2268 u32 tx_stat_gtufl_hi;
2269 u32 tx_stat_gterr_lo;
2270 u32 tx_stat_gterr_hi;
2271 u32 tx_stat_gtbyt_lo;
2272 u32 tx_stat_gtbyt_hi;
2274 u32 rx_stat_gr64_lo;
2275 u32 rx_stat_gr64_hi;
2276 u32 rx_stat_gr127_lo;
2277 u32 rx_stat_gr127_hi;
2278 u32 rx_stat_gr255_lo;
2279 u32 rx_stat_gr255_hi;
2280 u32 rx_stat_gr511_lo;
2281 u32 rx_stat_gr511_hi;
2282 u32 rx_stat_gr1023_lo;
2283 u32 rx_stat_gr1023_hi;
2284 u32 rx_stat_gr1518_lo;
2285 u32 rx_stat_gr1518_hi;
2286 u32 rx_stat_gr2047_lo;
2287 u32 rx_stat_gr2047_hi;
2288 u32 rx_stat_gr4095_lo;
2289 u32 rx_stat_gr4095_hi;
2290 u32 rx_stat_gr9216_lo;
2291 u32 rx_stat_gr9216_hi;
2292 u32 rx_stat_gr16383_lo;
2293 u32 rx_stat_gr16383_hi;
2294 u32 rx_stat_grmax_lo;
2295 u32 rx_stat_grmax_hi;
2296 u32 rx_stat_grpkt_lo;
2297 u32 rx_stat_grpkt_hi;
2298 u32 rx_stat_grfcs_lo;
2299 u32 rx_stat_grfcs_hi;
2300 u32 rx_stat_grmca_lo;
2301 u32 rx_stat_grmca_hi;
2302 u32 rx_stat_grbca_lo;
2303 u32 rx_stat_grbca_hi;
2304 u32 rx_stat_grxcf_lo;
2305 u32 rx_stat_grxcf_hi;
2306 u32 rx_stat_grxpf_lo;
2307 u32 rx_stat_grxpf_hi;
2308 u32 rx_stat_grxuo_lo;
2309 u32 rx_stat_grxuo_hi;
2310 u32 rx_stat_grjbr_lo;
2311 u32 rx_stat_grjbr_hi;
2312 u32 rx_stat_grovr_lo;
2313 u32 rx_stat_grovr_hi;
2314 u32 rx_stat_grflr_lo;
2315 u32 rx_stat_grflr_hi;
2316 u32 rx_stat_grmeg_lo;
2317 u32 rx_stat_grmeg_hi;
2318 u32 rx_stat_grmeb_lo;
2319 u32 rx_stat_grmeb_hi;
2320 u32 rx_stat_grbyt_lo;
2321 u32 rx_stat_grbyt_hi;
2322 u32 rx_stat_grund_lo;
2323 u32 rx_stat_grund_hi;
2324 u32 rx_stat_grfrg_lo;
2325 u32 rx_stat_grfrg_hi;
2326 u32 rx_stat_grerb_lo;
2327 u32 rx_stat_grerb_hi;
2328 u32 rx_stat_grfre_lo;
2329 u32 rx_stat_grfre_hi;
2330 u32 rx_stat_gripj_lo;
2331 u32 rx_stat_gripj_hi;
2334 struct bmac2_stats {
2335 u32 tx_stat_gtpk_lo; /* gtpok */
2336 u32 tx_stat_gtpk_hi; /* gtpok */
2337 u32 tx_stat_gtxpf_lo; /* gtpf */
2338 u32 tx_stat_gtxpf_hi; /* gtpf */
2339 u32 tx_stat_gtpp_lo; /* NEW BMAC2 */
2340 u32 tx_stat_gtpp_hi; /* NEW BMAC2 */
2341 u32 tx_stat_gtfcs_lo;
2342 u32 tx_stat_gtfcs_hi;
2343 u32 tx_stat_gtuca_lo; /* NEW BMAC2 */
2344 u32 tx_stat_gtuca_hi; /* NEW BMAC2 */
2345 u32 tx_stat_gtmca_lo;
2346 u32 tx_stat_gtmca_hi;
2347 u32 tx_stat_gtbca_lo;
2348 u32 tx_stat_gtbca_hi;
2349 u32 tx_stat_gtovr_lo;
2350 u32 tx_stat_gtovr_hi;
2351 u32 tx_stat_gtfrg_lo;
2352 u32 tx_stat_gtfrg_hi;
2353 u32 tx_stat_gtpkt1_lo; /* gtpkt */
2354 u32 tx_stat_gtpkt1_hi; /* gtpkt */
2355 u32 tx_stat_gt64_lo;
2356 u32 tx_stat_gt64_hi;
2357 u32 tx_stat_gt127_lo;
2358 u32 tx_stat_gt127_hi;
2359 u32 tx_stat_gt255_lo;
2360 u32 tx_stat_gt255_hi;
2361 u32 tx_stat_gt511_lo;
2362 u32 tx_stat_gt511_hi;
2363 u32 tx_stat_gt1023_lo;
2364 u32 tx_stat_gt1023_hi;
2365 u32 tx_stat_gt1518_lo;
2366 u32 tx_stat_gt1518_hi;
2367 u32 tx_stat_gt2047_lo;
2368 u32 tx_stat_gt2047_hi;
2369 u32 tx_stat_gt4095_lo;
2370 u32 tx_stat_gt4095_hi;
2371 u32 tx_stat_gt9216_lo;
2372 u32 tx_stat_gt9216_hi;
2373 u32 tx_stat_gt16383_lo;
2374 u32 tx_stat_gt16383_hi;
2375 u32 tx_stat_gtmax_lo;
2376 u32 tx_stat_gtmax_hi;
2377 u32 tx_stat_gtufl_lo;
2378 u32 tx_stat_gtufl_hi;
2379 u32 tx_stat_gterr_lo;
2380 u32 tx_stat_gterr_hi;
2381 u32 tx_stat_gtbyt_lo;
2382 u32 tx_stat_gtbyt_hi;
2384 u32 rx_stat_gr64_lo;
2385 u32 rx_stat_gr64_hi;
2386 u32 rx_stat_gr127_lo;
2387 u32 rx_stat_gr127_hi;
2388 u32 rx_stat_gr255_lo;
2389 u32 rx_stat_gr255_hi;
2390 u32 rx_stat_gr511_lo;
2391 u32 rx_stat_gr511_hi;
2392 u32 rx_stat_gr1023_lo;
2393 u32 rx_stat_gr1023_hi;
2394 u32 rx_stat_gr1518_lo;
2395 u32 rx_stat_gr1518_hi;
2396 u32 rx_stat_gr2047_lo;
2397 u32 rx_stat_gr2047_hi;
2398 u32 rx_stat_gr4095_lo;
2399 u32 rx_stat_gr4095_hi;
2400 u32 rx_stat_gr9216_lo;
2401 u32 rx_stat_gr9216_hi;
2402 u32 rx_stat_gr16383_lo;
2403 u32 rx_stat_gr16383_hi;
2404 u32 rx_stat_grmax_lo;
2405 u32 rx_stat_grmax_hi;
2406 u32 rx_stat_grpkt_lo;
2407 u32 rx_stat_grpkt_hi;
2408 u32 rx_stat_grfcs_lo;
2409 u32 rx_stat_grfcs_hi;
2410 u32 rx_stat_gruca_lo;
2411 u32 rx_stat_gruca_hi;
2412 u32 rx_stat_grmca_lo;
2413 u32 rx_stat_grmca_hi;
2414 u32 rx_stat_grbca_lo;
2415 u32 rx_stat_grbca_hi;
2416 u32 rx_stat_grxpf_lo; /* grpf */
2417 u32 rx_stat_grxpf_hi; /* grpf */
2418 u32 rx_stat_grpp_lo;
2419 u32 rx_stat_grpp_hi;
2420 u32 rx_stat_grxuo_lo; /* gruo */
2421 u32 rx_stat_grxuo_hi; /* gruo */
2422 u32 rx_stat_grjbr_lo;
2423 u32 rx_stat_grjbr_hi;
2424 u32 rx_stat_grovr_lo;
2425 u32 rx_stat_grovr_hi;
2426 u32 rx_stat_grxcf_lo; /* grcf */
2427 u32 rx_stat_grxcf_hi; /* grcf */
2428 u32 rx_stat_grflr_lo;
2429 u32 rx_stat_grflr_hi;
2430 u32 rx_stat_grpok_lo;
2431 u32 rx_stat_grpok_hi;
2432 u32 rx_stat_grmeg_lo;
2433 u32 rx_stat_grmeg_hi;
2434 u32 rx_stat_grmeb_lo;
2435 u32 rx_stat_grmeb_hi;
2436 u32 rx_stat_grbyt_lo;
2437 u32 rx_stat_grbyt_hi;
2438 u32 rx_stat_grund_lo;
2439 u32 rx_stat_grund_hi;
2440 u32 rx_stat_grfrg_lo;
2441 u32 rx_stat_grfrg_hi;
2442 u32 rx_stat_grerb_lo; /* grerrbyt */
2443 u32 rx_stat_grerb_hi; /* grerrbyt */
2444 u32 rx_stat_grfre_lo; /* grfrerr */
2445 u32 rx_stat_grfre_hi; /* grfrerr */
2446 u32 rx_stat_gripj_lo;
2447 u32 rx_stat_gripj_hi;
2450 struct mstat_stats {
2452 /* OTE MSTAT on E3 has a bug where this register's contents are
2453 * actually tx_gtxpok + tx_gtxpf + (possibly)tx_gtxpp
2497 u32 tx_collisions_lo;
2498 u32 tx_collisions_hi;
2499 u32 tx_singlecollision_lo;
2500 u32 tx_singlecollision_hi;
2501 u32 tx_multiplecollisions_lo;
2502 u32 tx_multiplecollisions_hi;
2505 u32 tx_excessivecollisions_lo;
2506 u32 tx_excessivecollisions_hi;
2507 u32 tx_latecollisions_lo;
2508 u32 tx_latecollisions_hi;
2567 u32 rx_alignmenterrors_lo;
2568 u32 rx_alignmenterrors_hi;
2569 u32 rx_falsecarrier_lo;
2570 u32 rx_falsecarrier_hi;
2571 u32 rx_llfcmsgcnt_lo;
2572 u32 rx_llfcmsgcnt_hi;
2577 struct emac_stats emac_stats;
2578 struct bmac1_stats bmac1_stats;
2579 struct bmac2_stats bmac2_stats;
2580 struct mstat_stats mstat_stats;
2586 u32 rx_stat_ifhcinbadoctets_hi;
2587 u32 rx_stat_ifhcinbadoctets_lo;
2589 /* out_bad_octets */
2590 u32 tx_stat_ifhcoutbadoctets_hi;
2591 u32 tx_stat_ifhcoutbadoctets_lo;
2593 /* crc_receive_errors */
2594 u32 rx_stat_dot3statsfcserrors_hi;
2595 u32 rx_stat_dot3statsfcserrors_lo;
2596 /* alignment_errors */
2597 u32 rx_stat_dot3statsalignmenterrors_hi;
2598 u32 rx_stat_dot3statsalignmenterrors_lo;
2599 /* carrier_sense_errors */
2600 u32 rx_stat_dot3statscarriersenseerrors_hi;
2601 u32 rx_stat_dot3statscarriersenseerrors_lo;
2602 /* false_carrier_detections */
2603 u32 rx_stat_falsecarriererrors_hi;
2604 u32 rx_stat_falsecarriererrors_lo;
2606 /* runt_packets_received */
2607 u32 rx_stat_etherstatsundersizepkts_hi;
2608 u32 rx_stat_etherstatsundersizepkts_lo;
2609 /* jabber_packets_received */
2610 u32 rx_stat_dot3statsframestoolong_hi;
2611 u32 rx_stat_dot3statsframestoolong_lo;
2613 /* error_runt_packets_received */
2614 u32 rx_stat_etherstatsfragments_hi;
2615 u32 rx_stat_etherstatsfragments_lo;
2616 /* error_jabber_packets_received */
2617 u32 rx_stat_etherstatsjabbers_hi;
2618 u32 rx_stat_etherstatsjabbers_lo;
2620 /* control_frames_received */
2621 u32 rx_stat_maccontrolframesreceived_hi;
2622 u32 rx_stat_maccontrolframesreceived_lo;
2623 u32 rx_stat_mac_xpf_hi;
2624 u32 rx_stat_mac_xpf_lo;
2625 u32 rx_stat_mac_xcf_hi;
2626 u32 rx_stat_mac_xcf_lo;
2628 /* xoff_state_entered */
2629 u32 rx_stat_xoffstateentered_hi;
2630 u32 rx_stat_xoffstateentered_lo;
2631 /* pause_xon_frames_received */
2632 u32 rx_stat_xonpauseframesreceived_hi;
2633 u32 rx_stat_xonpauseframesreceived_lo;
2634 /* pause_xoff_frames_received */
2635 u32 rx_stat_xoffpauseframesreceived_hi;
2636 u32 rx_stat_xoffpauseframesreceived_lo;
2637 /* pause_xon_frames_transmitted */
2638 u32 tx_stat_outxonsent_hi;
2639 u32 tx_stat_outxonsent_lo;
2640 /* pause_xoff_frames_transmitted */
2641 u32 tx_stat_outxoffsent_hi;
2642 u32 tx_stat_outxoffsent_lo;
2643 /* flow_control_done */
2644 u32 tx_stat_flowcontroldone_hi;
2645 u32 tx_stat_flowcontroldone_lo;
2647 /* ether_stats_collisions */
2648 u32 tx_stat_etherstatscollisions_hi;
2649 u32 tx_stat_etherstatscollisions_lo;
2650 /* single_collision_transmit_frames */
2651 u32 tx_stat_dot3statssinglecollisionframes_hi;
2652 u32 tx_stat_dot3statssinglecollisionframes_lo;
2653 /* multiple_collision_transmit_frames */
2654 u32 tx_stat_dot3statsmultiplecollisionframes_hi;
2655 u32 tx_stat_dot3statsmultiplecollisionframes_lo;
2656 /* deferred_transmissions */
2657 u32 tx_stat_dot3statsdeferredtransmissions_hi;
2658 u32 tx_stat_dot3statsdeferredtransmissions_lo;
2659 /* excessive_collision_frames */
2660 u32 tx_stat_dot3statsexcessivecollisions_hi;
2661 u32 tx_stat_dot3statsexcessivecollisions_lo;
2662 /* late_collision_frames */
2663 u32 tx_stat_dot3statslatecollisions_hi;
2664 u32 tx_stat_dot3statslatecollisions_lo;
2666 /* frames_transmitted_64_bytes */
2667 u32 tx_stat_etherstatspkts64octets_hi;
2668 u32 tx_stat_etherstatspkts64octets_lo;
2669 /* frames_transmitted_65_127_bytes */
2670 u32 tx_stat_etherstatspkts65octetsto127octets_hi;
2671 u32 tx_stat_etherstatspkts65octetsto127octets_lo;
2672 /* frames_transmitted_128_255_bytes */
2673 u32 tx_stat_etherstatspkts128octetsto255octets_hi;
2674 u32 tx_stat_etherstatspkts128octetsto255octets_lo;
2675 /* frames_transmitted_256_511_bytes */
2676 u32 tx_stat_etherstatspkts256octetsto511octets_hi;
2677 u32 tx_stat_etherstatspkts256octetsto511octets_lo;
2678 /* frames_transmitted_512_1023_bytes */
2679 u32 tx_stat_etherstatspkts512octetsto1023octets_hi;
2680 u32 tx_stat_etherstatspkts512octetsto1023octets_lo;
2681 /* frames_transmitted_1024_1522_bytes */
2682 u32 tx_stat_etherstatspkts1024octetsto1522octets_hi;
2683 u32 tx_stat_etherstatspkts1024octetsto1522octets_lo;
2684 /* frames_transmitted_1523_9022_bytes */
2685 u32 tx_stat_etherstatspktsover1522octets_hi;
2686 u32 tx_stat_etherstatspktsover1522octets_lo;
2687 u32 tx_stat_mac_2047_hi;
2688 u32 tx_stat_mac_2047_lo;
2689 u32 tx_stat_mac_4095_hi;
2690 u32 tx_stat_mac_4095_lo;
2691 u32 tx_stat_mac_9216_hi;
2692 u32 tx_stat_mac_9216_lo;
2693 u32 tx_stat_mac_16383_hi;
2694 u32 tx_stat_mac_16383_lo;
2696 /* internal_mac_transmit_errors */
2697 u32 tx_stat_dot3statsinternalmactransmiterrors_hi;
2698 u32 tx_stat_dot3statsinternalmactransmiterrors_lo;
2700 /* if_out_discards */
2701 u32 tx_stat_mac_ufl_hi;
2702 u32 tx_stat_mac_ufl_lo;
2706 #define MAC_STX_IDX_MAX 2
2708 struct host_port_stats {
2709 u32 host_port_stats_counter;
2711 struct mac_stx mac_stx[MAC_STX_IDX_MAX];
2716 u32 not_used; /* obsolete */
2717 u32 pfc_frames_tx_hi;
2718 u32 pfc_frames_tx_lo;
2719 u32 pfc_frames_rx_hi;
2720 u32 pfc_frames_rx_lo;
2722 u32 eee_lpi_count_hi;
2723 u32 eee_lpi_count_lo;
2727 struct host_func_stats {
2728 u32 host_func_stats_start;
2730 u32 total_bytes_received_hi;
2731 u32 total_bytes_received_lo;
2733 u32 total_bytes_transmitted_hi;
2734 u32 total_bytes_transmitted_lo;
2736 u32 total_unicast_packets_received_hi;
2737 u32 total_unicast_packets_received_lo;
2739 u32 total_multicast_packets_received_hi;
2740 u32 total_multicast_packets_received_lo;
2742 u32 total_broadcast_packets_received_hi;
2743 u32 total_broadcast_packets_received_lo;
2745 u32 total_unicast_packets_transmitted_hi;
2746 u32 total_unicast_packets_transmitted_lo;
2748 u32 total_multicast_packets_transmitted_hi;
2749 u32 total_multicast_packets_transmitted_lo;
2751 u32 total_broadcast_packets_transmitted_hi;
2752 u32 total_broadcast_packets_transmitted_lo;
2754 u32 valid_bytes_received_hi;
2755 u32 valid_bytes_received_lo;
2757 u32 host_func_stats_end;
2760 /* VIC definitions */
2761 #define VICSTATST_UIF_INDEX 2
2764 /* stats collected for afex.
2765 * NOTE: structure is exactly as expected to be received by the switch.
2766 * order must remain exactly as is unless protocol changes !
2769 u32 tx_unicast_frames_hi;
2770 u32 tx_unicast_frames_lo;
2771 u32 tx_unicast_bytes_hi;
2772 u32 tx_unicast_bytes_lo;
2773 u32 tx_multicast_frames_hi;
2774 u32 tx_multicast_frames_lo;
2775 u32 tx_multicast_bytes_hi;
2776 u32 tx_multicast_bytes_lo;
2777 u32 tx_broadcast_frames_hi;
2778 u32 tx_broadcast_frames_lo;
2779 u32 tx_broadcast_bytes_hi;
2780 u32 tx_broadcast_bytes_lo;
2781 u32 tx_frames_discarded_hi;
2782 u32 tx_frames_discarded_lo;
2783 u32 tx_frames_dropped_hi;
2784 u32 tx_frames_dropped_lo;
2786 u32 rx_unicast_frames_hi;
2787 u32 rx_unicast_frames_lo;
2788 u32 rx_unicast_bytes_hi;
2789 u32 rx_unicast_bytes_lo;
2790 u32 rx_multicast_frames_hi;
2791 u32 rx_multicast_frames_lo;
2792 u32 rx_multicast_bytes_hi;
2793 u32 rx_multicast_bytes_lo;
2794 u32 rx_broadcast_frames_hi;
2795 u32 rx_broadcast_frames_lo;
2796 u32 rx_broadcast_bytes_hi;
2797 u32 rx_broadcast_bytes_lo;
2798 u32 rx_frames_discarded_hi;
2799 u32 rx_frames_discarded_lo;
2800 u32 rx_frames_dropped_hi;
2801 u32 rx_frames_dropped_lo;
2804 #define BCM_5710_FW_MAJOR_VERSION 7
2805 #define BCM_5710_FW_MINOR_VERSION 8
2806 #define BCM_5710_FW_REVISION_VERSION 2
2807 #define BCM_5710_FW_ENGINEERING_VERSION 0
2808 #define BCM_5710_FW_COMPILE_FLAGS 1
2814 struct atten_sp_status_block {
2816 __le32 attn_bits_ack;
2819 __le16 attn_bits_index;
2825 * The eth aggregative context of Cstorm
2827 struct cstorm_eth_ag_context {
2828 u32 __reserved0[10];
2833 * dmae command structure
2835 struct dmae_command {
2837 #define DMAE_COMMAND_SRC (0x1<<0)
2838 #define DMAE_COMMAND_SRC_SHIFT 0
2839 #define DMAE_COMMAND_DST (0x3<<1)
2840 #define DMAE_COMMAND_DST_SHIFT 1
2841 #define DMAE_COMMAND_C_DST (0x1<<3)
2842 #define DMAE_COMMAND_C_DST_SHIFT 3
2843 #define DMAE_COMMAND_C_TYPE_ENABLE (0x1<<4)
2844 #define DMAE_COMMAND_C_TYPE_ENABLE_SHIFT 4
2845 #define DMAE_COMMAND_C_TYPE_CRC_ENABLE (0x1<<5)
2846 #define DMAE_COMMAND_C_TYPE_CRC_ENABLE_SHIFT 5
2847 #define DMAE_COMMAND_C_TYPE_CRC_OFFSET (0x7<<6)
2848 #define DMAE_COMMAND_C_TYPE_CRC_OFFSET_SHIFT 6
2849 #define DMAE_COMMAND_ENDIANITY (0x3<<9)
2850 #define DMAE_COMMAND_ENDIANITY_SHIFT 9
2851 #define DMAE_COMMAND_PORT (0x1<<11)
2852 #define DMAE_COMMAND_PORT_SHIFT 11
2853 #define DMAE_COMMAND_CRC_RESET (0x1<<12)
2854 #define DMAE_COMMAND_CRC_RESET_SHIFT 12
2855 #define DMAE_COMMAND_SRC_RESET (0x1<<13)
2856 #define DMAE_COMMAND_SRC_RESET_SHIFT 13
2857 #define DMAE_COMMAND_DST_RESET (0x1<<14)
2858 #define DMAE_COMMAND_DST_RESET_SHIFT 14
2859 #define DMAE_COMMAND_E1HVN (0x3<<15)
2860 #define DMAE_COMMAND_E1HVN_SHIFT 15
2861 #define DMAE_COMMAND_DST_VN (0x3<<17)
2862 #define DMAE_COMMAND_DST_VN_SHIFT 17
2863 #define DMAE_COMMAND_C_FUNC (0x1<<19)
2864 #define DMAE_COMMAND_C_FUNC_SHIFT 19
2865 #define DMAE_COMMAND_ERR_POLICY (0x3<<20)
2866 #define DMAE_COMMAND_ERR_POLICY_SHIFT 20
2867 #define DMAE_COMMAND_RESERVED0 (0x3FF<<22)
2868 #define DMAE_COMMAND_RESERVED0_SHIFT 22
2873 #if defined(__BIG_ENDIAN)
2875 #define DMAE_COMMAND_SRC_VFID (0x3F<<0)
2876 #define DMAE_COMMAND_SRC_VFID_SHIFT 0
2877 #define DMAE_COMMAND_SRC_VFPF (0x1<<6)
2878 #define DMAE_COMMAND_SRC_VFPF_SHIFT 6
2879 #define DMAE_COMMAND_RESERVED1 (0x1<<7)
2880 #define DMAE_COMMAND_RESERVED1_SHIFT 7
2881 #define DMAE_COMMAND_DST_VFID (0x3F<<8)
2882 #define DMAE_COMMAND_DST_VFID_SHIFT 8
2883 #define DMAE_COMMAND_DST_VFPF (0x1<<14)
2884 #define DMAE_COMMAND_DST_VFPF_SHIFT 14
2885 #define DMAE_COMMAND_RESERVED2 (0x1<<15)
2886 #define DMAE_COMMAND_RESERVED2_SHIFT 15
2888 #elif defined(__LITTLE_ENDIAN)
2891 #define DMAE_COMMAND_SRC_VFID (0x3F<<0)
2892 #define DMAE_COMMAND_SRC_VFID_SHIFT 0
2893 #define DMAE_COMMAND_SRC_VFPF (0x1<<6)
2894 #define DMAE_COMMAND_SRC_VFPF_SHIFT 6
2895 #define DMAE_COMMAND_RESERVED1 (0x1<<7)
2896 #define DMAE_COMMAND_RESERVED1_SHIFT 7
2897 #define DMAE_COMMAND_DST_VFID (0x3F<<8)
2898 #define DMAE_COMMAND_DST_VFID_SHIFT 8
2899 #define DMAE_COMMAND_DST_VFPF (0x1<<14)
2900 #define DMAE_COMMAND_DST_VFPF_SHIFT 14
2901 #define DMAE_COMMAND_RESERVED2 (0x1<<15)
2902 #define DMAE_COMMAND_RESERVED2_SHIFT 15
2909 #if defined(__BIG_ENDIAN)
2912 #elif defined(__LITTLE_ENDIAN)
2916 #if defined(__BIG_ENDIAN)
2919 #elif defined(__LITTLE_ENDIAN)
2923 #if defined(__BIG_ENDIAN)
2926 #elif defined(__LITTLE_ENDIAN)
2934 * common data for all protocols
2936 struct doorbell_hdr {
2938 #define DOORBELL_HDR_RX (0x1<<0)
2939 #define DOORBELL_HDR_RX_SHIFT 0
2940 #define DOORBELL_HDR_DB_TYPE (0x1<<1)
2941 #define DOORBELL_HDR_DB_TYPE_SHIFT 1
2942 #define DOORBELL_HDR_DPM_SIZE (0x3<<2)
2943 #define DOORBELL_HDR_DPM_SIZE_SHIFT 2
2944 #define DOORBELL_HDR_CONN_TYPE (0xF<<4)
2945 #define DOORBELL_HDR_CONN_TYPE_SHIFT 4
2951 struct eth_tx_doorbell {
2952 #if defined(__BIG_ENDIAN)
2955 #define ETH_TX_DOORBELL_NUM_BDS (0x3F<<0)
2956 #define ETH_TX_DOORBELL_NUM_BDS_SHIFT 0
2957 #define ETH_TX_DOORBELL_RESERVED_TX_FIN_FLAG (0x1<<6)
2958 #define ETH_TX_DOORBELL_RESERVED_TX_FIN_FLAG_SHIFT 6
2959 #define ETH_TX_DOORBELL_SPARE (0x1<<7)
2960 #define ETH_TX_DOORBELL_SPARE_SHIFT 7
2961 struct doorbell_hdr hdr;
2962 #elif defined(__LITTLE_ENDIAN)
2963 struct doorbell_hdr hdr;
2965 #define ETH_TX_DOORBELL_NUM_BDS (0x3F<<0)
2966 #define ETH_TX_DOORBELL_NUM_BDS_SHIFT 0
2967 #define ETH_TX_DOORBELL_RESERVED_TX_FIN_FLAG (0x1<<6)
2968 #define ETH_TX_DOORBELL_RESERVED_TX_FIN_FLAG_SHIFT 6
2969 #define ETH_TX_DOORBELL_SPARE (0x1<<7)
2970 #define ETH_TX_DOORBELL_SPARE_SHIFT 7
2977 * 3 lines. status block
2979 struct hc_status_block_e1x {
2980 __le16 index_values[HC_SB_MAX_INDICES_E1X];
2981 __le16 running_index[HC_SB_MAX_SM];
2988 struct host_hc_status_block_e1x {
2989 struct hc_status_block_e1x sb;
2994 * 3 lines. status block
2996 struct hc_status_block_e2 {
2997 __le16 index_values[HC_SB_MAX_INDICES_E2];
2998 __le16 running_index[HC_SB_MAX_SM];
2999 __le32 reserved[11];
3005 struct host_hc_status_block_e2 {
3006 struct hc_status_block_e2 sb;
3011 * 5 lines. slow-path status block
3013 struct hc_sp_status_block {
3014 __le16 index_values[HC_SP_SB_MAX_INDICES];
3015 __le16 running_index;
3023 struct host_sp_status_block {
3024 struct atten_sp_status_block atten_status_block;
3025 struct hc_sp_status_block sp_sb;
3030 * IGU driver acknowledgment register
3032 struct igu_ack_register {
3033 #if defined(__BIG_ENDIAN)
3034 u16 sb_id_and_flags;
3035 #define IGU_ACK_REGISTER_STATUS_BLOCK_ID (0x1F<<0)
3036 #define IGU_ACK_REGISTER_STATUS_BLOCK_ID_SHIFT 0
3037 #define IGU_ACK_REGISTER_STORM_ID (0x7<<5)
3038 #define IGU_ACK_REGISTER_STORM_ID_SHIFT 5
3039 #define IGU_ACK_REGISTER_UPDATE_INDEX (0x1<<8)
3040 #define IGU_ACK_REGISTER_UPDATE_INDEX_SHIFT 8
3041 #define IGU_ACK_REGISTER_INTERRUPT_MODE (0x3<<9)
3042 #define IGU_ACK_REGISTER_INTERRUPT_MODE_SHIFT 9
3043 #define IGU_ACK_REGISTER_RESERVED (0x1F<<11)
3044 #define IGU_ACK_REGISTER_RESERVED_SHIFT 11
3045 u16 status_block_index;
3046 #elif defined(__LITTLE_ENDIAN)
3047 u16 status_block_index;
3048 u16 sb_id_and_flags;
3049 #define IGU_ACK_REGISTER_STATUS_BLOCK_ID (0x1F<<0)
3050 #define IGU_ACK_REGISTER_STATUS_BLOCK_ID_SHIFT 0
3051 #define IGU_ACK_REGISTER_STORM_ID (0x7<<5)
3052 #define IGU_ACK_REGISTER_STORM_ID_SHIFT 5
3053 #define IGU_ACK_REGISTER_UPDATE_INDEX (0x1<<8)
3054 #define IGU_ACK_REGISTER_UPDATE_INDEX_SHIFT 8
3055 #define IGU_ACK_REGISTER_INTERRUPT_MODE (0x3<<9)
3056 #define IGU_ACK_REGISTER_INTERRUPT_MODE_SHIFT 9
3057 #define IGU_ACK_REGISTER_RESERVED (0x1F<<11)
3058 #define IGU_ACK_REGISTER_RESERVED_SHIFT 11
3064 * IGU driver acknowledgement register
3066 struct igu_backward_compatible {
3067 u32 sb_id_and_flags;
3068 #define IGU_BACKWARD_COMPATIBLE_SB_INDEX (0xFFFF<<0)
3069 #define IGU_BACKWARD_COMPATIBLE_SB_INDEX_SHIFT 0
3070 #define IGU_BACKWARD_COMPATIBLE_SB_SELECT (0x1F<<16)
3071 #define IGU_BACKWARD_COMPATIBLE_SB_SELECT_SHIFT 16
3072 #define IGU_BACKWARD_COMPATIBLE_SEGMENT_ACCESS (0x7<<21)
3073 #define IGU_BACKWARD_COMPATIBLE_SEGMENT_ACCESS_SHIFT 21
3074 #define IGU_BACKWARD_COMPATIBLE_BUPDATE (0x1<<24)
3075 #define IGU_BACKWARD_COMPATIBLE_BUPDATE_SHIFT 24
3076 #define IGU_BACKWARD_COMPATIBLE_ENABLE_INT (0x3<<25)
3077 #define IGU_BACKWARD_COMPATIBLE_ENABLE_INT_SHIFT 25
3078 #define IGU_BACKWARD_COMPATIBLE_RESERVED_0 (0x1F<<27)
3079 #define IGU_BACKWARD_COMPATIBLE_RESERVED_0_SHIFT 27
3085 * IGU driver acknowledgement register
3087 struct igu_regular {
3088 u32 sb_id_and_flags;
3089 #define IGU_REGULAR_SB_INDEX (0xFFFFF<<0)
3090 #define IGU_REGULAR_SB_INDEX_SHIFT 0
3091 #define IGU_REGULAR_RESERVED0 (0x1<<20)
3092 #define IGU_REGULAR_RESERVED0_SHIFT 20
3093 #define IGU_REGULAR_SEGMENT_ACCESS (0x7<<21)
3094 #define IGU_REGULAR_SEGMENT_ACCESS_SHIFT 21
3095 #define IGU_REGULAR_BUPDATE (0x1<<24)
3096 #define IGU_REGULAR_BUPDATE_SHIFT 24
3097 #define IGU_REGULAR_ENABLE_INT (0x3<<25)
3098 #define IGU_REGULAR_ENABLE_INT_SHIFT 25
3099 #define IGU_REGULAR_RESERVED_1 (0x1<<27)
3100 #define IGU_REGULAR_RESERVED_1_SHIFT 27
3101 #define IGU_REGULAR_CLEANUP_TYPE (0x3<<28)
3102 #define IGU_REGULAR_CLEANUP_TYPE_SHIFT 28
3103 #define IGU_REGULAR_CLEANUP_SET (0x1<<30)
3104 #define IGU_REGULAR_CLEANUP_SET_SHIFT 30
3105 #define IGU_REGULAR_BCLEANUP (0x1<<31)
3106 #define IGU_REGULAR_BCLEANUP_SHIFT 31
3111 * IGU driver acknowledgement register
3113 union igu_consprod_reg {
3114 struct igu_regular regular;
3115 struct igu_backward_compatible backward_compatible;
3120 * Igu control commands
3123 IGU_CTRL_CMD_TYPE_RD,
3124 IGU_CTRL_CMD_TYPE_WR,
3130 * Control register for the IGU command register
3132 struct igu_ctrl_reg {
3134 #define IGU_CTRL_REG_ADDRESS (0xFFF<<0)
3135 #define IGU_CTRL_REG_ADDRESS_SHIFT 0
3136 #define IGU_CTRL_REG_FID (0x7F<<12)
3137 #define IGU_CTRL_REG_FID_SHIFT 12
3138 #define IGU_CTRL_REG_RESERVED (0x1<<19)
3139 #define IGU_CTRL_REG_RESERVED_SHIFT 19
3140 #define IGU_CTRL_REG_TYPE (0x1<<20)
3141 #define IGU_CTRL_REG_TYPE_SHIFT 20
3142 #define IGU_CTRL_REG_UNUSED (0x7FF<<21)
3143 #define IGU_CTRL_REG_UNUSED_SHIFT 21
3148 * Igu interrupt command
3162 enum igu_seg_access {
3163 IGU_SEG_ACCESS_NORM,
3165 IGU_SEG_ACCESS_ATTN,
3171 * Parser parsing flags field
3173 struct parsing_flags {
3175 #define PARSING_FLAGS_ETHERNET_ADDRESS_TYPE (0x1<<0)
3176 #define PARSING_FLAGS_ETHERNET_ADDRESS_TYPE_SHIFT 0
3177 #define PARSING_FLAGS_VLAN (0x1<<1)
3178 #define PARSING_FLAGS_VLAN_SHIFT 1
3179 #define PARSING_FLAGS_EXTRA_VLAN (0x1<<2)
3180 #define PARSING_FLAGS_EXTRA_VLAN_SHIFT 2
3181 #define PARSING_FLAGS_OVER_ETHERNET_PROTOCOL (0x3<<3)
3182 #define PARSING_FLAGS_OVER_ETHERNET_PROTOCOL_SHIFT 3
3183 #define PARSING_FLAGS_IP_OPTIONS (0x1<<5)
3184 #define PARSING_FLAGS_IP_OPTIONS_SHIFT 5
3185 #define PARSING_FLAGS_FRAGMENTATION_STATUS (0x1<<6)
3186 #define PARSING_FLAGS_FRAGMENTATION_STATUS_SHIFT 6
3187 #define PARSING_FLAGS_OVER_IP_PROTOCOL (0x3<<7)
3188 #define PARSING_FLAGS_OVER_IP_PROTOCOL_SHIFT 7
3189 #define PARSING_FLAGS_PURE_ACK_INDICATION (0x1<<9)
3190 #define PARSING_FLAGS_PURE_ACK_INDICATION_SHIFT 9
3191 #define PARSING_FLAGS_TCP_OPTIONS_EXIST (0x1<<10)
3192 #define PARSING_FLAGS_TCP_OPTIONS_EXIST_SHIFT 10
3193 #define PARSING_FLAGS_TIME_STAMP_EXIST_FLAG (0x1<<11)
3194 #define PARSING_FLAGS_TIME_STAMP_EXIST_FLAG_SHIFT 11
3195 #define PARSING_FLAGS_CONNECTION_MATCH (0x1<<12)
3196 #define PARSING_FLAGS_CONNECTION_MATCH_SHIFT 12
3197 #define PARSING_FLAGS_LLC_SNAP (0x1<<13)
3198 #define PARSING_FLAGS_LLC_SNAP_SHIFT 13
3199 #define PARSING_FLAGS_RESERVED0 (0x3<<14)
3200 #define PARSING_FLAGS_RESERVED0_SHIFT 14
3205 * Parsing flags for TCP ACK type
3207 enum prs_flags_ack_type {
3208 PRS_FLAG_PUREACK_PIGGY,
3209 PRS_FLAG_PUREACK_PURE,
3210 MAX_PRS_FLAGS_ACK_TYPE
3215 * Parsing flags for Ethernet address type
3217 enum prs_flags_eth_addr_type {
3218 PRS_FLAG_ETHTYPE_NON_UNICAST,
3219 PRS_FLAG_ETHTYPE_UNICAST,
3220 MAX_PRS_FLAGS_ETH_ADDR_TYPE
3225 * Parsing flags for over-ethernet protocol
3227 enum prs_flags_over_eth {
3228 PRS_FLAG_OVERETH_UNKNOWN,
3229 PRS_FLAG_OVERETH_IPV4,
3230 PRS_FLAG_OVERETH_IPV6,
3231 PRS_FLAG_OVERETH_LLCSNAP_UNKNOWN,
3232 MAX_PRS_FLAGS_OVER_ETH
3237 * Parsing flags for over-IP protocol
3239 enum prs_flags_over_ip {
3240 PRS_FLAG_OVERIP_UNKNOWN,
3241 PRS_FLAG_OVERIP_TCP,
3242 PRS_FLAG_OVERIP_UDP,
3243 MAX_PRS_FLAGS_OVER_IP
3248 * SDM operation gen command (generate aggregative interrupt)
3252 #define SDM_OP_GEN_COMP_PARAM (0x1F<<0)
3253 #define SDM_OP_GEN_COMP_PARAM_SHIFT 0
3254 #define SDM_OP_GEN_COMP_TYPE (0x7<<5)
3255 #define SDM_OP_GEN_COMP_TYPE_SHIFT 5
3256 #define SDM_OP_GEN_AGG_VECT_IDX (0xFF<<8)
3257 #define SDM_OP_GEN_AGG_VECT_IDX_SHIFT 8
3258 #define SDM_OP_GEN_AGG_VECT_IDX_VALID (0x1<<16)
3259 #define SDM_OP_GEN_AGG_VECT_IDX_VALID_SHIFT 16
3260 #define SDM_OP_GEN_RESERVED (0x7FFF<<17)
3261 #define SDM_OP_GEN_RESERVED_SHIFT 17
3266 * Timers connection context
3268 struct timers_block_context {
3273 #define __TIMERS_BLOCK_CONTEXT_NUM_OF_ACTIVE_TIMERS (0x3<<0)
3274 #define __TIMERS_BLOCK_CONTEXT_NUM_OF_ACTIVE_TIMERS_SHIFT 0
3275 #define TIMERS_BLOCK_CONTEXT_CONN_VALID_FLG (0x1<<2)
3276 #define TIMERS_BLOCK_CONTEXT_CONN_VALID_FLG_SHIFT 2
3277 #define __TIMERS_BLOCK_CONTEXT_RESERVED0 (0x1FFFFFFF<<3)
3278 #define __TIMERS_BLOCK_CONTEXT_RESERVED0_SHIFT 3
3283 * The eth aggregative context of Tstorm
3285 struct tstorm_eth_ag_context {
3286 u32 __reserved0[14];
3291 * The eth aggregative context of Ustorm
3293 struct ustorm_eth_ag_context {
3295 #if defined(__BIG_ENDIAN)
3299 #elif defined(__LITTLE_ENDIAN)
3309 * The eth aggregative context of Xstorm
3311 struct xstorm_eth_ag_context {
3313 #if defined(__BIG_ENDIAN)
3317 #elif defined(__LITTLE_ENDIAN)
3327 * doorbell message sent to the chip
3330 #if defined(__BIG_ENDIAN)
3333 struct doorbell_hdr header;
3334 #elif defined(__LITTLE_ENDIAN)
3335 struct doorbell_hdr header;
3343 * doorbell message sent to the chip
3345 struct doorbell_set_prod {
3346 #if defined(__BIG_ENDIAN)
3349 struct doorbell_hdr header;
3350 #elif defined(__LITTLE_ENDIAN)
3351 struct doorbell_hdr header;
3365 * Classify rule opcodes in E2/E3
3367 enum classify_rule {
3368 CLASSIFY_RULE_OPCODE_MAC,
3369 CLASSIFY_RULE_OPCODE_VLAN,
3370 CLASSIFY_RULE_OPCODE_PAIR,
3376 * Classify rule types in E2/E3
3378 enum classify_rule_action_type {
3379 CLASSIFY_RULE_REMOVE,
3381 MAX_CLASSIFY_RULE_ACTION_TYPE
3386 * client init ramrod data
3388 struct client_init_general_data {
3390 u8 statistics_counter_id;
3391 u8 statistics_en_flg;
3396 u8 statistics_zero_flg;
3405 * client init rx data
3407 struct client_init_rx_data {
3409 #define CLIENT_INIT_RX_DATA_TPA_EN_IPV4 (0x1<<0)
3410 #define CLIENT_INIT_RX_DATA_TPA_EN_IPV4_SHIFT 0
3411 #define CLIENT_INIT_RX_DATA_TPA_EN_IPV6 (0x1<<1)
3412 #define CLIENT_INIT_RX_DATA_TPA_EN_IPV6_SHIFT 1
3413 #define CLIENT_INIT_RX_DATA_TPA_MODE (0x1<<2)
3414 #define CLIENT_INIT_RX_DATA_TPA_MODE_SHIFT 2
3415 #define CLIENT_INIT_RX_DATA_RESERVED5 (0x1F<<3)
3416 #define CLIENT_INIT_RX_DATA_RESERVED5_SHIFT 3
3417 u8 vmqueue_mode_en_flg;
3418 u8 extra_data_over_sgl_en_flg;
3419 u8 cache_line_alignment_log_size;
3420 u8 enable_dynamic_hc;
3421 u8 max_sges_for_packet;
3423 u8 drop_ip_cs_err_flg;
3424 u8 drop_tcp_cs_err_flg;
3426 u8 drop_udp_cs_err_flg;
3427 u8 inner_vlan_removal_enable_flg;
3428 u8 outer_vlan_removal_enable_flg;
3430 u8 rx_sb_index_number;
3431 u8 dont_verify_rings_pause_thr_flg;
3433 u8 silent_vlan_removal_flg;
3434 __le16 max_bytes_on_bd;
3435 __le16 sge_buff_size;
3436 u8 approx_mcast_engine_id;
3438 struct regpair bd_page_base;
3439 struct regpair sge_page_base;
3440 struct regpair cqe_page_base;
3443 __le16 max_agg_size;
3445 #define CLIENT_INIT_RX_DATA_UCAST_DROP_ALL (0x1<<0)
3446 #define CLIENT_INIT_RX_DATA_UCAST_DROP_ALL_SHIFT 0
3447 #define CLIENT_INIT_RX_DATA_UCAST_ACCEPT_ALL (0x1<<1)
3448 #define CLIENT_INIT_RX_DATA_UCAST_ACCEPT_ALL_SHIFT 1
3449 #define CLIENT_INIT_RX_DATA_UCAST_ACCEPT_UNMATCHED (0x1<<2)
3450 #define CLIENT_INIT_RX_DATA_UCAST_ACCEPT_UNMATCHED_SHIFT 2
3451 #define CLIENT_INIT_RX_DATA_MCAST_DROP_ALL (0x1<<3)
3452 #define CLIENT_INIT_RX_DATA_MCAST_DROP_ALL_SHIFT 3
3453 #define CLIENT_INIT_RX_DATA_MCAST_ACCEPT_ALL (0x1<<4)
3454 #define CLIENT_INIT_RX_DATA_MCAST_ACCEPT_ALL_SHIFT 4
3455 #define CLIENT_INIT_RX_DATA_BCAST_ACCEPT_ALL (0x1<<5)
3456 #define CLIENT_INIT_RX_DATA_BCAST_ACCEPT_ALL_SHIFT 5
3457 #define CLIENT_INIT_RX_DATA_ACCEPT_ANY_VLAN (0x1<<6)
3458 #define CLIENT_INIT_RX_DATA_ACCEPT_ANY_VLAN_SHIFT 6
3459 #define CLIENT_INIT_RX_DATA_RESERVED2 (0x1FF<<7)
3460 #define CLIENT_INIT_RX_DATA_RESERVED2_SHIFT 7
3461 __le16 cqe_pause_thr_low;
3462 __le16 cqe_pause_thr_high;
3463 __le16 bd_pause_thr_low;
3464 __le16 bd_pause_thr_high;
3465 __le16 sge_pause_thr_low;
3466 __le16 sge_pause_thr_high;
3468 __le16 silent_vlan_value;
3469 __le16 silent_vlan_mask;
3470 __le32 reserved6[2];
3474 * client init tx data
3476 struct client_init_tx_data {
3477 u8 enforce_security_flg;
3478 u8 tx_status_block_id;
3479 u8 tx_sb_index_number;
3480 u8 tss_leading_client_id;
3481 u8 tx_switching_flg;
3482 u8 anti_spoofing_flg;
3483 __le16 default_vlan;
3484 struct regpair tx_bd_page_base;
3486 #define CLIENT_INIT_TX_DATA_UCAST_ACCEPT_ALL (0x1<<0)
3487 #define CLIENT_INIT_TX_DATA_UCAST_ACCEPT_ALL_SHIFT 0
3488 #define CLIENT_INIT_TX_DATA_MCAST_ACCEPT_ALL (0x1<<1)
3489 #define CLIENT_INIT_TX_DATA_MCAST_ACCEPT_ALL_SHIFT 1
3490 #define CLIENT_INIT_TX_DATA_BCAST_ACCEPT_ALL (0x1<<2)
3491 #define CLIENT_INIT_TX_DATA_BCAST_ACCEPT_ALL_SHIFT 2
3492 #define CLIENT_INIT_TX_DATA_ACCEPT_ANY_VLAN (0x1<<3)
3493 #define CLIENT_INIT_TX_DATA_ACCEPT_ANY_VLAN_SHIFT 3
3494 #define CLIENT_INIT_TX_DATA_RESERVED1 (0xFFF<<4)
3495 #define CLIENT_INIT_TX_DATA_RESERVED1_SHIFT 4
3496 u8 default_vlan_flg;
3497 u8 force_default_pri_flg;
3502 * client init ramrod data
3504 struct client_init_ramrod_data {
3505 struct client_init_general_data general;
3506 struct client_init_rx_data rx;
3507 struct client_init_tx_data tx;
3512 * client update ramrod data
3514 struct client_update_ramrod_data {
3517 u8 inner_vlan_removal_enable_flg;
3518 u8 inner_vlan_removal_change_flg;
3519 u8 outer_vlan_removal_enable_flg;
3520 u8 outer_vlan_removal_change_flg;
3521 u8 anti_spoofing_enable_flg;
3522 u8 anti_spoofing_change_flg;
3524 u8 activate_change_flg;
3525 __le16 default_vlan;
3526 u8 default_vlan_enable_flg;
3527 u8 default_vlan_change_flg;
3528 __le16 silent_vlan_value;
3529 __le16 silent_vlan_mask;
3530 u8 silent_vlan_removal_flg;
3531 u8 silent_vlan_change_flg;
3537 * The eth storm context of Cstorm
3539 struct cstorm_eth_st_context {
3544 struct double_regpair {
3553 * Ethernet address typesm used in ethernet tx BDs
3555 enum eth_addr_type {
3567 struct eth_classify_cmd_header {
3568 u8 cmd_general_data;
3569 #define ETH_CLASSIFY_CMD_HEADER_RX_CMD (0x1<<0)
3570 #define ETH_CLASSIFY_CMD_HEADER_RX_CMD_SHIFT 0
3571 #define ETH_CLASSIFY_CMD_HEADER_TX_CMD (0x1<<1)
3572 #define ETH_CLASSIFY_CMD_HEADER_TX_CMD_SHIFT 1
3573 #define ETH_CLASSIFY_CMD_HEADER_OPCODE (0x3<<2)
3574 #define ETH_CLASSIFY_CMD_HEADER_OPCODE_SHIFT 2
3575 #define ETH_CLASSIFY_CMD_HEADER_IS_ADD (0x1<<4)
3576 #define ETH_CLASSIFY_CMD_HEADER_IS_ADD_SHIFT 4
3577 #define ETH_CLASSIFY_CMD_HEADER_RESERVED0 (0x7<<5)
3578 #define ETH_CLASSIFY_CMD_HEADER_RESERVED0_SHIFT 5
3586 * header for eth classification config ramrod
3588 struct eth_classify_header {
3597 * Command for adding/removing a MAC classification rule
3599 struct eth_classify_mac_cmd {
3600 struct eth_classify_cmd_header header;
3610 * Command for adding/removing a MAC-VLAN pair classification rule
3612 struct eth_classify_pair_cmd {
3613 struct eth_classify_cmd_header header;
3623 * Command for adding/removing a VLAN classification rule
3625 struct eth_classify_vlan_cmd {
3626 struct eth_classify_cmd_header header;
3634 * union for eth classification rule
3636 union eth_classify_rule_cmd {
3637 struct eth_classify_mac_cmd mac;
3638 struct eth_classify_vlan_cmd vlan;
3639 struct eth_classify_pair_cmd pair;
3643 * parameters for eth classification configuration ramrod
3645 struct eth_classify_rules_ramrod_data {
3646 struct eth_classify_header header;
3647 union eth_classify_rule_cmd rules[CLASSIFY_RULES_COUNT];
3652 * The data contain client ID need to the ramrod
3654 struct eth_common_ramrod_data {
3661 * The eth storm context of Ustorm
3663 struct ustorm_eth_st_context {
3668 * The eth storm context of Tstorm
3670 struct tstorm_eth_st_context {
3671 u32 __reserved0[28];
3675 * The eth storm context of Xstorm
3677 struct xstorm_eth_st_context {
3682 * Ethernet connection context
3684 struct eth_context {
3685 struct ustorm_eth_st_context ustorm_st_context;
3686 struct tstorm_eth_st_context tstorm_st_context;
3687 struct xstorm_eth_ag_context xstorm_ag_context;
3688 struct tstorm_eth_ag_context tstorm_ag_context;
3689 struct cstorm_eth_ag_context cstorm_ag_context;
3690 struct ustorm_eth_ag_context ustorm_ag_context;
3691 struct timers_block_context timers_context;
3692 struct xstorm_eth_st_context xstorm_st_context;
3693 struct cstorm_eth_st_context cstorm_st_context;
3698 * union for sgl and raw data.
3700 union eth_sgl_or_raw_data {
3706 * eth FP end aggregation CQE parameters struct
3708 struct eth_end_agg_rx_cqe {
3709 u8 type_error_flags;
3710 #define ETH_END_AGG_RX_CQE_TYPE (0x3<<0)
3711 #define ETH_END_AGG_RX_CQE_TYPE_SHIFT 0
3712 #define ETH_END_AGG_RX_CQE_SGL_RAW_SEL (0x1<<2)
3713 #define ETH_END_AGG_RX_CQE_SGL_RAW_SEL_SHIFT 2
3714 #define ETH_END_AGG_RX_CQE_RESERVED0 (0x1F<<3)
3715 #define ETH_END_AGG_RX_CQE_RESERVED0_SHIFT 3
3719 __le32 timestamp_delta;
3720 __le16 num_of_coalesced_segs;
3725 union eth_sgl_or_raw_data sgl_or_raw_data;
3726 __le32 reserved5[8];
3731 * regular eth FP CQE parameters struct
3733 struct eth_fast_path_rx_cqe {
3734 u8 type_error_flags;
3735 #define ETH_FAST_PATH_RX_CQE_TYPE (0x3<<0)
3736 #define ETH_FAST_PATH_RX_CQE_TYPE_SHIFT 0
3737 #define ETH_FAST_PATH_RX_CQE_SGL_RAW_SEL (0x1<<2)
3738 #define ETH_FAST_PATH_RX_CQE_SGL_RAW_SEL_SHIFT 2
3739 #define ETH_FAST_PATH_RX_CQE_PHY_DECODE_ERR_FLG (0x1<<3)
3740 #define ETH_FAST_PATH_RX_CQE_PHY_DECODE_ERR_FLG_SHIFT 3
3741 #define ETH_FAST_PATH_RX_CQE_IP_BAD_XSUM_FLG (0x1<<4)
3742 #define ETH_FAST_PATH_RX_CQE_IP_BAD_XSUM_FLG_SHIFT 4
3743 #define ETH_FAST_PATH_RX_CQE_L4_BAD_XSUM_FLG (0x1<<5)
3744 #define ETH_FAST_PATH_RX_CQE_L4_BAD_XSUM_FLG_SHIFT 5
3745 #define ETH_FAST_PATH_RX_CQE_RESERVED0 (0x3<<6)
3746 #define ETH_FAST_PATH_RX_CQE_RESERVED0_SHIFT 6
3748 #define ETH_FAST_PATH_RX_CQE_RSS_HASH_TYPE (0x7<<0)
3749 #define ETH_FAST_PATH_RX_CQE_RSS_HASH_TYPE_SHIFT 0
3750 #define ETH_FAST_PATH_RX_CQE_RSS_HASH_FLG (0x1<<3)
3751 #define ETH_FAST_PATH_RX_CQE_RSS_HASH_FLG_SHIFT 3
3752 #define ETH_FAST_PATH_RX_CQE_BROADCAST_FLG (0x1<<4)
3753 #define ETH_FAST_PATH_RX_CQE_BROADCAST_FLG_SHIFT 4
3754 #define ETH_FAST_PATH_RX_CQE_MAC_MATCH_FLG (0x1<<5)
3755 #define ETH_FAST_PATH_RX_CQE_MAC_MATCH_FLG_SHIFT 5
3756 #define ETH_FAST_PATH_RX_CQE_IP_XSUM_NO_VALIDATION_FLG (0x1<<6)
3757 #define ETH_FAST_PATH_RX_CQE_IP_XSUM_NO_VALIDATION_FLG_SHIFT 6
3758 #define ETH_FAST_PATH_RX_CQE_L4_XSUM_NO_VALIDATION_FLG (0x1<<7)
3759 #define ETH_FAST_PATH_RX_CQE_L4_XSUM_NO_VALIDATION_FLG_SHIFT 7
3761 u8 placement_offset;
3762 __le32 rss_hash_result;
3764 __le16 pkt_len_or_gro_seg_len;
3766 struct parsing_flags pars_flags;
3767 union eth_sgl_or_raw_data sgl_or_raw_data;
3768 __le32 reserved1[8];
3773 * Command for setting classification flags for a client
3775 struct eth_filter_rules_cmd {
3776 u8 cmd_general_data;
3777 #define ETH_FILTER_RULES_CMD_RX_CMD (0x1<<0)
3778 #define ETH_FILTER_RULES_CMD_RX_CMD_SHIFT 0
3779 #define ETH_FILTER_RULES_CMD_TX_CMD (0x1<<1)
3780 #define ETH_FILTER_RULES_CMD_TX_CMD_SHIFT 1
3781 #define ETH_FILTER_RULES_CMD_RESERVED0 (0x3F<<2)
3782 #define ETH_FILTER_RULES_CMD_RESERVED0_SHIFT 2
3787 #define ETH_FILTER_RULES_CMD_UCAST_DROP_ALL (0x1<<0)
3788 #define ETH_FILTER_RULES_CMD_UCAST_DROP_ALL_SHIFT 0
3789 #define ETH_FILTER_RULES_CMD_UCAST_ACCEPT_ALL (0x1<<1)
3790 #define ETH_FILTER_RULES_CMD_UCAST_ACCEPT_ALL_SHIFT 1
3791 #define ETH_FILTER_RULES_CMD_UCAST_ACCEPT_UNMATCHED (0x1<<2)
3792 #define ETH_FILTER_RULES_CMD_UCAST_ACCEPT_UNMATCHED_SHIFT 2
3793 #define ETH_FILTER_RULES_CMD_MCAST_DROP_ALL (0x1<<3)
3794 #define ETH_FILTER_RULES_CMD_MCAST_DROP_ALL_SHIFT 3
3795 #define ETH_FILTER_RULES_CMD_MCAST_ACCEPT_ALL (0x1<<4)
3796 #define ETH_FILTER_RULES_CMD_MCAST_ACCEPT_ALL_SHIFT 4
3797 #define ETH_FILTER_RULES_CMD_BCAST_ACCEPT_ALL (0x1<<5)
3798 #define ETH_FILTER_RULES_CMD_BCAST_ACCEPT_ALL_SHIFT 5
3799 #define ETH_FILTER_RULES_CMD_ACCEPT_ANY_VLAN (0x1<<6)
3800 #define ETH_FILTER_RULES_CMD_ACCEPT_ANY_VLAN_SHIFT 6
3801 #define ETH_FILTER_RULES_CMD_RESERVED2 (0x1FF<<7)
3802 #define ETH_FILTER_RULES_CMD_RESERVED2_SHIFT 7
3804 struct regpair reserved4;
3809 * parameters for eth classification filters ramrod
3811 struct eth_filter_rules_ramrod_data {
3812 struct eth_classify_header header;
3813 struct eth_filter_rules_cmd rules[FILTER_RULES_COUNT];
3818 * parameters for eth classification configuration ramrod
3820 struct eth_general_rules_ramrod_data {
3821 struct eth_classify_header header;
3822 union eth_classify_rule_cmd rules[CLASSIFY_RULES_COUNT];
3827 * The data for Halt ramrod
3829 struct eth_halt_ramrod_data {
3836 * Command for setting multicast classification for a client
3838 struct eth_multicast_rules_cmd {
3839 u8 cmd_general_data;
3840 #define ETH_MULTICAST_RULES_CMD_RX_CMD (0x1<<0)
3841 #define ETH_MULTICAST_RULES_CMD_RX_CMD_SHIFT 0
3842 #define ETH_MULTICAST_RULES_CMD_TX_CMD (0x1<<1)
3843 #define ETH_MULTICAST_RULES_CMD_TX_CMD_SHIFT 1
3844 #define ETH_MULTICAST_RULES_CMD_IS_ADD (0x1<<2)
3845 #define ETH_MULTICAST_RULES_CMD_IS_ADD_SHIFT 2
3846 #define ETH_MULTICAST_RULES_CMD_RESERVED0 (0x1F<<3)
3847 #define ETH_MULTICAST_RULES_CMD_RESERVED0_SHIFT 3
3852 struct regpair reserved3;
3857 * parameters for multicast classification ramrod
3859 struct eth_multicast_rules_ramrod_data {
3860 struct eth_classify_header header;
3861 struct eth_multicast_rules_cmd rules[MULTICAST_RULES_COUNT];
3866 * Place holder for ramrods protocol specific data
3868 struct ramrod_data {
3874 * union for ramrod data for Ethernet protocol (CQE) (force size of 16 bits)
3876 union eth_ramrod_data {
3877 struct ramrod_data general;
3882 * RSS toeplitz hash type, as reported in CQE
3884 enum eth_rss_hash_type {
3891 E1HOV_PRI_HASH_TYPE,
3893 MAX_ETH_RSS_HASH_TYPE
3901 ETH_RSS_MODE_DISABLED,
3902 ETH_RSS_MODE_REGULAR,
3903 ETH_RSS_MODE_VLAN_PRI,
3904 ETH_RSS_MODE_E1HOV_PRI,
3905 ETH_RSS_MODE_IP_DSCP,
3911 * parameters for RSS update ramrod (E2)
3913 struct eth_rss_update_ramrod_data {
3916 #define ETH_RSS_UPDATE_RAMROD_DATA_IPV4_CAPABILITY (0x1<<0)
3917 #define ETH_RSS_UPDATE_RAMROD_DATA_IPV4_CAPABILITY_SHIFT 0
3918 #define ETH_RSS_UPDATE_RAMROD_DATA_IPV4_TCP_CAPABILITY (0x1<<1)
3919 #define ETH_RSS_UPDATE_RAMROD_DATA_IPV4_TCP_CAPABILITY_SHIFT 1
3920 #define ETH_RSS_UPDATE_RAMROD_DATA_IPV4_UDP_CAPABILITY (0x1<<2)
3921 #define ETH_RSS_UPDATE_RAMROD_DATA_IPV4_UDP_CAPABILITY_SHIFT 2
3922 #define ETH_RSS_UPDATE_RAMROD_DATA_IPV6_CAPABILITY (0x1<<3)
3923 #define ETH_RSS_UPDATE_RAMROD_DATA_IPV6_CAPABILITY_SHIFT 3
3924 #define ETH_RSS_UPDATE_RAMROD_DATA_IPV6_TCP_CAPABILITY (0x1<<4)
3925 #define ETH_RSS_UPDATE_RAMROD_DATA_IPV6_TCP_CAPABILITY_SHIFT 4
3926 #define ETH_RSS_UPDATE_RAMROD_DATA_IPV6_UDP_CAPABILITY (0x1<<5)
3927 #define ETH_RSS_UPDATE_RAMROD_DATA_IPV6_UDP_CAPABILITY_SHIFT 5
3928 #define ETH_RSS_UPDATE_RAMROD_DATA_UPDATE_RSS_KEY (0x1<<7)
3929 #define ETH_RSS_UPDATE_RAMROD_DATA_UPDATE_RSS_KEY_SHIFT 7
3933 u8 indirection_table[T_ETH_INDIRECTION_TABLE_SIZE];
3934 __le32 rss_key[T_ETH_RSS_KEY];
3941 * The eth Rx Buffer Descriptor
3950 * Eth Rx Cqe structure- general structure for ramrods
3952 struct common_ramrod_eth_rx_cqe {
3954 #define COMMON_RAMROD_ETH_RX_CQE_TYPE (0x3<<0)
3955 #define COMMON_RAMROD_ETH_RX_CQE_TYPE_SHIFT 0
3956 #define COMMON_RAMROD_ETH_RX_CQE_ERROR (0x1<<2)
3957 #define COMMON_RAMROD_ETH_RX_CQE_ERROR_SHIFT 2
3958 #define COMMON_RAMROD_ETH_RX_CQE_RESERVED0 (0x1F<<3)
3959 #define COMMON_RAMROD_ETH_RX_CQE_RESERVED0_SHIFT 3
3962 __le32 conn_and_cmd_data;
3963 #define COMMON_RAMROD_ETH_RX_CQE_CID (0xFFFFFF<<0)
3964 #define COMMON_RAMROD_ETH_RX_CQE_CID_SHIFT 0
3965 #define COMMON_RAMROD_ETH_RX_CQE_CMD_ID (0xFF<<24)
3966 #define COMMON_RAMROD_ETH_RX_CQE_CMD_ID_SHIFT 24
3967 struct ramrod_data protocol_data;
3969 __le32 reserved2[11];
3973 * Rx Last CQE in page (in ETH)
3975 struct eth_rx_cqe_next_page {
3978 __le32 reserved[14];
3982 * union for all eth rx cqe types (fix their sizes)
3985 struct eth_fast_path_rx_cqe fast_path_cqe;
3986 struct common_ramrod_eth_rx_cqe ramrod_cqe;
3987 struct eth_rx_cqe_next_page next_page_cqe;
3988 struct eth_end_agg_rx_cqe end_agg_cqe;
3993 * Values for RX ETH CQE type field
3995 enum eth_rx_cqe_type {
3996 RX_ETH_CQE_TYPE_ETH_FASTPATH,
3997 RX_ETH_CQE_TYPE_ETH_RAMROD,
3998 RX_ETH_CQE_TYPE_ETH_START_AGG,
3999 RX_ETH_CQE_TYPE_ETH_STOP_AGG,
4005 * Type of SGL/Raw field in ETH RX fast path CQE
4007 enum eth_rx_fp_sel {
4015 * The eth Rx SGE Descriptor
4024 * common data for all protocols
4027 __le32 conn_and_cmd_data;
4028 #define SPE_HDR_CID (0xFFFFFF<<0)
4029 #define SPE_HDR_CID_SHIFT 0
4030 #define SPE_HDR_CMD_ID (0xFF<<24)
4031 #define SPE_HDR_CMD_ID_SHIFT 24
4033 #define SPE_HDR_CONN_TYPE (0xFF<<0)
4034 #define SPE_HDR_CONN_TYPE_SHIFT 0
4035 #define SPE_HDR_FUNCTION_ID (0xFF<<8)
4036 #define SPE_HDR_FUNCTION_ID_SHIFT 8
4041 * specific data for ethernet slow path element
4043 union eth_specific_data {
4044 u8 protocol_data[8];
4045 struct regpair client_update_ramrod_data;
4046 struct regpair client_init_ramrod_init_data;
4047 struct eth_halt_ramrod_data halt_ramrod_data;
4048 struct regpair update_data_addr;
4049 struct eth_common_ramrod_data common_ramrod_data;
4050 struct regpair classify_cfg_addr;
4051 struct regpair filter_cfg_addr;
4052 struct regpair mcast_cfg_addr;
4056 * Ethernet slow path element
4060 union eth_specific_data data;
4065 * Ethernet command ID for slow path elements
4067 enum eth_spqe_cmd_id {
4068 RAMROD_CMD_ID_ETH_UNUSED,
4069 RAMROD_CMD_ID_ETH_CLIENT_SETUP,
4070 RAMROD_CMD_ID_ETH_HALT,
4071 RAMROD_CMD_ID_ETH_FORWARD_SETUP,
4072 RAMROD_CMD_ID_ETH_TX_QUEUE_SETUP,
4073 RAMROD_CMD_ID_ETH_CLIENT_UPDATE,
4074 RAMROD_CMD_ID_ETH_EMPTY,
4075 RAMROD_CMD_ID_ETH_TERMINATE,
4076 RAMROD_CMD_ID_ETH_TPA_UPDATE,
4077 RAMROD_CMD_ID_ETH_CLASSIFICATION_RULES,
4078 RAMROD_CMD_ID_ETH_FILTER_RULES,
4079 RAMROD_CMD_ID_ETH_MULTICAST_RULES,
4080 RAMROD_CMD_ID_ETH_RSS_UPDATE,
4081 RAMROD_CMD_ID_ETH_SET_MAC,
4087 * eth tpa update command
4089 enum eth_tpa_update_command {
4090 TPA_UPDATE_NONE_COMMAND,
4091 TPA_UPDATE_ENABLE_COMMAND,
4092 TPA_UPDATE_DISABLE_COMMAND,
4093 MAX_ETH_TPA_UPDATE_COMMAND
4098 * Tx regular BD structure
4103 __le16 total_pkt_bytes;
4110 * structure for easy accessibility to assembler
4112 struct eth_tx_bd_flags {
4114 #define ETH_TX_BD_FLAGS_IP_CSUM (0x1<<0)
4115 #define ETH_TX_BD_FLAGS_IP_CSUM_SHIFT 0
4116 #define ETH_TX_BD_FLAGS_L4_CSUM (0x1<<1)
4117 #define ETH_TX_BD_FLAGS_L4_CSUM_SHIFT 1
4118 #define ETH_TX_BD_FLAGS_VLAN_MODE (0x3<<2)
4119 #define ETH_TX_BD_FLAGS_VLAN_MODE_SHIFT 2
4120 #define ETH_TX_BD_FLAGS_START_BD (0x1<<4)
4121 #define ETH_TX_BD_FLAGS_START_BD_SHIFT 4
4122 #define ETH_TX_BD_FLAGS_IS_UDP (0x1<<5)
4123 #define ETH_TX_BD_FLAGS_IS_UDP_SHIFT 5
4124 #define ETH_TX_BD_FLAGS_SW_LSO (0x1<<6)
4125 #define ETH_TX_BD_FLAGS_SW_LSO_SHIFT 6
4126 #define ETH_TX_BD_FLAGS_IPV6 (0x1<<7)
4127 #define ETH_TX_BD_FLAGS_IPV6_SHIFT 7
4131 * The eth Tx Buffer Descriptor
4133 struct eth_tx_start_bd {
4138 __le16 vlan_or_ethertype;
4139 struct eth_tx_bd_flags bd_flags;
4141 #define ETH_TX_START_BD_HDR_NBDS (0xF<<0)
4142 #define ETH_TX_START_BD_HDR_NBDS_SHIFT 0
4143 #define ETH_TX_START_BD_FORCE_VLAN_MODE (0x1<<4)
4144 #define ETH_TX_START_BD_FORCE_VLAN_MODE_SHIFT 4
4145 #define ETH_TX_START_BD_PARSE_NBDS (0x3<<5)
4146 #define ETH_TX_START_BD_PARSE_NBDS_SHIFT 5
4147 #define ETH_TX_START_BD_RESREVED (0x1<<7)
4148 #define ETH_TX_START_BD_RESREVED_SHIFT 7
4152 * Tx parsing BD structure for ETH E1/E1h
4154 struct eth_tx_parse_bd_e1x {
4156 #define ETH_TX_PARSE_BD_E1X_IP_HDR_START_OFFSET_W (0xF<<0)
4157 #define ETH_TX_PARSE_BD_E1X_IP_HDR_START_OFFSET_W_SHIFT 0
4158 #define ETH_TX_PARSE_BD_E1X_ETH_ADDR_TYPE (0x3<<4)
4159 #define ETH_TX_PARSE_BD_E1X_ETH_ADDR_TYPE_SHIFT 4
4160 #define ETH_TX_PARSE_BD_E1X_PSEUDO_CS_WITHOUT_LEN (0x1<<6)
4161 #define ETH_TX_PARSE_BD_E1X_PSEUDO_CS_WITHOUT_LEN_SHIFT 6
4162 #define ETH_TX_PARSE_BD_E1X_LLC_SNAP_EN (0x1<<7)
4163 #define ETH_TX_PARSE_BD_E1X_LLC_SNAP_EN_SHIFT 7
4164 #define ETH_TX_PARSE_BD_E1X_NS_FLG (0x1<<8)
4165 #define ETH_TX_PARSE_BD_E1X_NS_FLG_SHIFT 8
4166 #define ETH_TX_PARSE_BD_E1X_RESERVED0 (0x7F<<9)
4167 #define ETH_TX_PARSE_BD_E1X_RESERVED0_SHIFT 9
4169 #define ETH_TX_PARSE_BD_E1X_FIN_FLG (0x1<<0)
4170 #define ETH_TX_PARSE_BD_E1X_FIN_FLG_SHIFT 0
4171 #define ETH_TX_PARSE_BD_E1X_SYN_FLG (0x1<<1)
4172 #define ETH_TX_PARSE_BD_E1X_SYN_FLG_SHIFT 1
4173 #define ETH_TX_PARSE_BD_E1X_RST_FLG (0x1<<2)
4174 #define ETH_TX_PARSE_BD_E1X_RST_FLG_SHIFT 2
4175 #define ETH_TX_PARSE_BD_E1X_PSH_FLG (0x1<<3)
4176 #define ETH_TX_PARSE_BD_E1X_PSH_FLG_SHIFT 3
4177 #define ETH_TX_PARSE_BD_E1X_ACK_FLG (0x1<<4)
4178 #define ETH_TX_PARSE_BD_E1X_ACK_FLG_SHIFT 4
4179 #define ETH_TX_PARSE_BD_E1X_URG_FLG (0x1<<5)
4180 #define ETH_TX_PARSE_BD_E1X_URG_FLG_SHIFT 5
4181 #define ETH_TX_PARSE_BD_E1X_ECE_FLG (0x1<<6)
4182 #define ETH_TX_PARSE_BD_E1X_ECE_FLG_SHIFT 6
4183 #define ETH_TX_PARSE_BD_E1X_CWR_FLG (0x1<<7)
4184 #define ETH_TX_PARSE_BD_E1X_CWR_FLG_SHIFT 7
4186 __le16 total_hlen_w;
4187 __le16 tcp_pseudo_csum;
4190 __le32 tcp_send_seq;
4194 * Tx parsing BD structure for ETH E2
4196 struct eth_tx_parse_bd_e2 {
4197 __le16 dst_mac_addr_lo;
4198 __le16 dst_mac_addr_mid;
4199 __le16 dst_mac_addr_hi;
4200 __le16 src_mac_addr_lo;
4201 __le16 src_mac_addr_mid;
4202 __le16 src_mac_addr_hi;
4203 __le32 parsing_data;
4204 #define ETH_TX_PARSE_BD_E2_TCP_HDR_START_OFFSET_W (0x7FF<<0)
4205 #define ETH_TX_PARSE_BD_E2_TCP_HDR_START_OFFSET_W_SHIFT 0
4206 #define ETH_TX_PARSE_BD_E2_TCP_HDR_LENGTH_DW (0xF<<11)
4207 #define ETH_TX_PARSE_BD_E2_TCP_HDR_LENGTH_DW_SHIFT 11
4208 #define ETH_TX_PARSE_BD_E2_IPV6_WITH_EXT_HDR (0x1<<15)
4209 #define ETH_TX_PARSE_BD_E2_IPV6_WITH_EXT_HDR_SHIFT 15
4210 #define ETH_TX_PARSE_BD_E2_LSO_MSS (0x3FFF<<16)
4211 #define ETH_TX_PARSE_BD_E2_LSO_MSS_SHIFT 16
4212 #define ETH_TX_PARSE_BD_E2_ETH_ADDR_TYPE (0x3<<30)
4213 #define ETH_TX_PARSE_BD_E2_ETH_ADDR_TYPE_SHIFT 30
4217 * The last BD in the BD memory will hold a pointer to the next BD memory
4219 struct eth_tx_next_bd {
4226 * union for 4 Bd types
4228 union eth_tx_bd_types {
4229 struct eth_tx_start_bd start_bd;
4230 struct eth_tx_bd reg_bd;
4231 struct eth_tx_parse_bd_e1x parse_bd_e1x;
4232 struct eth_tx_parse_bd_e2 parse_bd_e2;
4233 struct eth_tx_next_bd next_bd;
4237 * array of 13 bds as appears in the eth xstorm context
4239 struct eth_tx_bds_array {
4240 union eth_tx_bd_types bds[13];
4245 * VLAN mode on TX BDs
4247 enum eth_tx_vlan_type {
4251 X_ETH_FW_ADDED_VLAN,
4252 MAX_ETH_TX_VLAN_TYPE
4257 * Ethernet VLAN filtering mode in E1x
4259 enum eth_vlan_filter_mode {
4260 ETH_VLAN_FILTER_ANY_VLAN,
4261 ETH_VLAN_FILTER_SPECIFIC_VLAN,
4262 ETH_VLAN_FILTER_CLASSIFY,
4263 MAX_ETH_VLAN_FILTER_MODE
4268 * MAC filtering configuration command header
4270 struct mac_configuration_hdr {
4278 * MAC address in list for ramrod
4280 struct mac_configuration_entry {
4281 __le16 lsb_mac_addr;
4282 __le16 middle_mac_addr;
4283 __le16 msb_mac_addr;
4287 #define MAC_CONFIGURATION_ENTRY_ACTION_TYPE (0x1<<0)
4288 #define MAC_CONFIGURATION_ENTRY_ACTION_TYPE_SHIFT 0
4289 #define MAC_CONFIGURATION_ENTRY_RDMA_MAC (0x1<<1)
4290 #define MAC_CONFIGURATION_ENTRY_RDMA_MAC_SHIFT 1
4291 #define MAC_CONFIGURATION_ENTRY_VLAN_FILTERING_MODE (0x3<<2)
4292 #define MAC_CONFIGURATION_ENTRY_VLAN_FILTERING_MODE_SHIFT 2
4293 #define MAC_CONFIGURATION_ENTRY_OVERRIDE_VLAN_REMOVAL (0x1<<4)
4294 #define MAC_CONFIGURATION_ENTRY_OVERRIDE_VLAN_REMOVAL_SHIFT 4
4295 #define MAC_CONFIGURATION_ENTRY_BROADCAST (0x1<<5)
4296 #define MAC_CONFIGURATION_ENTRY_BROADCAST_SHIFT 5
4297 #define MAC_CONFIGURATION_ENTRY_RESERVED1 (0x3<<6)
4298 #define MAC_CONFIGURATION_ENTRY_RESERVED1_SHIFT 6
4300 __le32 clients_bit_vector;
4304 * MAC filtering configuration command
4306 struct mac_configuration_cmd {
4307 struct mac_configuration_hdr hdr;
4308 struct mac_configuration_entry config_table[64];
4313 * Set-MAC command type (in E1x)
4315 enum set_mac_action_type {
4316 T_ETH_MAC_COMMAND_INVALIDATE,
4317 T_ETH_MAC_COMMAND_SET,
4318 MAX_SET_MAC_ACTION_TYPE
4323 * Ethernet TPA Modes
4332 * tpa update ramrod data
4334 struct tpa_update_ramrod_data {
4339 u8 max_sges_for_packet;
4340 u8 complete_on_both_clients;
4341 u8 dont_verify_rings_pause_thr_flg;
4343 __le16 sge_buff_size;
4344 __le16 max_agg_size;
4345 __le32 sge_page_base_lo;
4346 __le32 sge_page_base_hi;
4347 __le16 sge_pause_thr_low;
4348 __le16 sge_pause_thr_high;
4353 * approximate-match multicast filtering for E1H per function in Tstorm
4355 struct tstorm_eth_approximate_match_multicast_filtering {
4356 u32 mcast_add_hash_bit_array[8];
4361 * Common configuration parameters per function in Tstorm
4363 struct tstorm_eth_function_common_config {
4364 __le16 config_flags;
4365 #define TSTORM_ETH_FUNCTION_COMMON_CONFIG_RSS_IPV4_CAPABILITY (0x1<<0)
4366 #define TSTORM_ETH_FUNCTION_COMMON_CONFIG_RSS_IPV4_CAPABILITY_SHIFT 0
4367 #define TSTORM_ETH_FUNCTION_COMMON_CONFIG_RSS_IPV4_TCP_CAPABILITY (0x1<<1)
4368 #define TSTORM_ETH_FUNCTION_COMMON_CONFIG_RSS_IPV4_TCP_CAPABILITY_SHIFT 1
4369 #define TSTORM_ETH_FUNCTION_COMMON_CONFIG_RSS_IPV6_CAPABILITY (0x1<<2)
4370 #define TSTORM_ETH_FUNCTION_COMMON_CONFIG_RSS_IPV6_CAPABILITY_SHIFT 2
4371 #define TSTORM_ETH_FUNCTION_COMMON_CONFIG_RSS_IPV6_TCP_CAPABILITY (0x1<<3)
4372 #define TSTORM_ETH_FUNCTION_COMMON_CONFIG_RSS_IPV6_TCP_CAPABILITY_SHIFT 3
4373 #define TSTORM_ETH_FUNCTION_COMMON_CONFIG_RSS_MODE (0x7<<4)
4374 #define TSTORM_ETH_FUNCTION_COMMON_CONFIG_RSS_MODE_SHIFT 4
4375 #define TSTORM_ETH_FUNCTION_COMMON_CONFIG_VLAN_FILTERING_ENABLE (0x1<<7)
4376 #define TSTORM_ETH_FUNCTION_COMMON_CONFIG_VLAN_FILTERING_ENABLE_SHIFT 7
4377 #define __TSTORM_ETH_FUNCTION_COMMON_CONFIG_RESERVED0 (0xFF<<8)
4378 #define __TSTORM_ETH_FUNCTION_COMMON_CONFIG_RESERVED0_SHIFT 8
4386 * MAC filtering configuration parameters per port in Tstorm
4388 struct tstorm_eth_mac_filter_config {
4389 __le32 ucast_drop_all;
4390 __le32 ucast_accept_all;
4391 __le32 mcast_drop_all;
4392 __le32 mcast_accept_all;
4393 __le32 bcast_accept_all;
4394 __le32 vlan_filter[2];
4395 __le32 unmatched_unicast;
4400 * tx only queue init ramrod data
4402 struct tx_queue_init_ramrod_data {
4403 struct client_init_general_data general;
4404 struct client_init_tx_data tx;
4409 * Three RX producers for ETH
4411 struct ustorm_eth_rx_producers {
4412 #if defined(__BIG_ENDIAN)
4415 #elif defined(__LITTLE_ENDIAN)
4419 #if defined(__BIG_ENDIAN)
4422 #elif defined(__LITTLE_ENDIAN)
4430 * FCoE RX statistics parameters section#0
4432 struct fcoe_rx_stat_params_section0 {
4433 __le32 fcoe_rx_pkt_cnt;
4434 __le32 fcoe_rx_byte_cnt;
4439 * FCoE RX statistics parameters section#1
4441 struct fcoe_rx_stat_params_section1 {
4442 __le32 fcoe_ver_cnt;
4443 __le32 fcoe_rx_drop_pkt_cnt;
4448 * FCoE RX statistics parameters section#2
4450 struct fcoe_rx_stat_params_section2 {
4452 __le32 eofa_del_cnt;
4453 __le32 miss_frame_cnt;
4454 __le32 seq_timeout_cnt;
4455 __le32 drop_seq_cnt;
4456 __le32 fcoe_rx_drop_pkt_cnt;
4457 __le32 fcp_rx_pkt_cnt;
4463 * FCoE TX statistics parameters
4465 struct fcoe_tx_stat_params {
4466 __le32 fcoe_tx_pkt_cnt;
4467 __le32 fcoe_tx_byte_cnt;
4468 __le32 fcp_tx_pkt_cnt;
4473 * FCoE statistics parameters
4475 struct fcoe_statistics_params {
4476 struct fcoe_tx_stat_params tx_stat;
4477 struct fcoe_rx_stat_params_section0 rx_stat0;
4478 struct fcoe_rx_stat_params_section1 rx_stat1;
4479 struct fcoe_rx_stat_params_section2 rx_stat2;
4484 * The data afex vif list ramrod need
4486 struct afex_vif_list_ramrod_data {
4487 u8 afex_vif_list_command;
4489 __le16 vif_list_index;
4497 * cfc delete event data
4499 struct cfc_del_event_data {
4507 * per-port SAFC demo variables
4509 struct cmng_flags_per_port {
4511 #define CMNG_FLAGS_PER_PORT_FAIRNESS_VN (0x1<<0)
4512 #define CMNG_FLAGS_PER_PORT_FAIRNESS_VN_SHIFT 0
4513 #define CMNG_FLAGS_PER_PORT_RATE_SHAPING_VN (0x1<<1)
4514 #define CMNG_FLAGS_PER_PORT_RATE_SHAPING_VN_SHIFT 1
4515 #define CMNG_FLAGS_PER_PORT_FAIRNESS_COS (0x1<<2)
4516 #define CMNG_FLAGS_PER_PORT_FAIRNESS_COS_SHIFT 2
4517 #define CMNG_FLAGS_PER_PORT_FAIRNESS_COS_MODE (0x1<<3)
4518 #define CMNG_FLAGS_PER_PORT_FAIRNESS_COS_MODE_SHIFT 3
4519 #define __CMNG_FLAGS_PER_PORT_RESERVED0 (0xFFFFFFF<<4)
4520 #define __CMNG_FLAGS_PER_PORT_RESERVED0_SHIFT 4
4526 * per-port rate shaping variables
4528 struct rate_shaping_vars_per_port {
4529 u32 rs_periodic_timeout;
4534 * per-port fairness variables
4536 struct fairness_vars_per_port {
4539 u32 fairness_timeout;
4544 * per-port SAFC variables
4546 struct safc_struct_per_port {
4547 #if defined(__BIG_ENDIAN)
4550 u8 safc_timeout_usec;
4551 #elif defined(__LITTLE_ENDIAN)
4552 u8 safc_timeout_usec;
4556 u8 cos_to_traffic_types[MAX_COS_NUMBER];
4557 u16 cos_to_pause_mask[NUM_OF_SAFC_BITS];
4561 * Per-port congestion management variables
4563 struct cmng_struct_per_port {
4564 struct rate_shaping_vars_per_port rs_vars;
4565 struct fairness_vars_per_port fair_vars;
4566 struct safc_struct_per_port safc_vars;
4567 struct cmng_flags_per_port flags;
4571 * a single rate shaping counter. can be used as protocol or vnic counter
4573 struct rate_shaping_counter {
4575 #if defined(__BIG_ENDIAN)
4578 #elif defined(__LITTLE_ENDIAN)
4585 * per-vnic rate shaping variables
4587 struct rate_shaping_vars_per_vn {
4588 struct rate_shaping_counter vn_counter;
4592 * per-vnic fairness variables
4594 struct fairness_vars_per_vn {
4595 u32 cos_credit_delta[MAX_COS_NUMBER];
4596 u32 vn_credit_delta;
4601 * cmng port init state
4604 struct rate_shaping_vars_per_vn vnic_max_rate[4];
4605 struct fairness_vars_per_vn vnic_min_rate[4];
4609 * cmng port init state
4612 struct cmng_struct_per_port port;
4613 struct cmng_vnic vnic;
4618 * driver parameters for congestion management init, all rates are in Mbps
4620 struct cmng_init_input {
4622 u16 vnic_min_rate[4];
4623 u16 vnic_max_rate[4];
4624 u16 cos_min_rate[MAX_COS_NUMBER];
4625 u16 cos_to_pause_mask[MAX_COS_NUMBER];
4626 struct cmng_flags_per_port flags;
4631 * Protocol-common command ID for slow path elements
4633 enum common_spqe_cmd_id {
4634 RAMROD_CMD_ID_COMMON_UNUSED,
4635 RAMROD_CMD_ID_COMMON_FUNCTION_START,
4636 RAMROD_CMD_ID_COMMON_FUNCTION_STOP,
4637 RAMROD_CMD_ID_COMMON_FUNCTION_UPDATE,
4638 RAMROD_CMD_ID_COMMON_CFC_DEL,
4639 RAMROD_CMD_ID_COMMON_CFC_DEL_WB,
4640 RAMROD_CMD_ID_COMMON_STAT_QUERY,
4641 RAMROD_CMD_ID_COMMON_STOP_TRAFFIC,
4642 RAMROD_CMD_ID_COMMON_START_TRAFFIC,
4643 RAMROD_CMD_ID_COMMON_AFEX_VIF_LISTS,
4644 MAX_COMMON_SPQE_CMD_ID
4649 * Per-protocol connection types
4651 enum connection_type {
4652 ETH_CONNECTION_TYPE,
4653 TOE_CONNECTION_TYPE,
4654 RDMA_CONNECTION_TYPE,
4655 ISCSI_CONNECTION_TYPE,
4656 FCOE_CONNECTION_TYPE,
4657 RESERVED_CONNECTION_TYPE_0,
4658 RESERVED_CONNECTION_TYPE_1,
4659 RESERVED_CONNECTION_TYPE_2,
4660 NONE_CONNECTION_TYPE,
4677 * Dynamic HC counters set by the driver
4679 struct hc_dynamic_drv_counter {
4680 u32 val[HC_SB_MAX_DYNAMIC_INDICES];
4684 * zone A per-queue data
4686 struct cstorm_queue_zone_data {
4687 struct hc_dynamic_drv_counter hc_dyn_drv_cnt;
4688 struct regpair reserved[2];
4693 * Vf-PF channel data in cstorm ram (non-triggered zone)
4695 struct vf_pf_channel_zone_data {
4701 * zone for VF non-triggered data
4703 struct non_trigger_vf_zone {
4704 struct vf_pf_channel_zone_data vf_pf_channel;
4708 * Vf-PF channel trigger zone in cstorm ram
4710 struct vf_pf_channel_zone_trigger {
4715 * zone that triggers the in-bound interrupt
4717 struct trigger_vf_zone {
4718 #if defined(__BIG_ENDIAN)
4721 struct vf_pf_channel_zone_trigger vf_pf_channel;
4722 #elif defined(__LITTLE_ENDIAN)
4723 struct vf_pf_channel_zone_trigger vf_pf_channel;
4731 * zone B per-VF data
4733 struct cstorm_vf_zone_data {
4734 struct non_trigger_vf_zone non_trigger;
4735 struct trigger_vf_zone trigger;
4740 * Dynamic host coalescing init parameters, per state machine
4742 struct dynamic_hc_sm_config {
4744 u8 shift_per_protocol[HC_SB_MAX_DYNAMIC_INDICES];
4745 u8 hc_timeout0[HC_SB_MAX_DYNAMIC_INDICES];
4746 u8 hc_timeout1[HC_SB_MAX_DYNAMIC_INDICES];
4747 u8 hc_timeout2[HC_SB_MAX_DYNAMIC_INDICES];
4748 u8 hc_timeout3[HC_SB_MAX_DYNAMIC_INDICES];
4752 * Dynamic host coalescing init parameters
4754 struct dynamic_hc_config {
4755 struct dynamic_hc_sm_config sm_config[HC_SB_MAX_SM];
4759 struct e2_integ_data {
4760 #if defined(__BIG_ENDIAN)
4762 #define E2_INTEG_DATA_TESTING_EN (0x1<<0)
4763 #define E2_INTEG_DATA_TESTING_EN_SHIFT 0
4764 #define E2_INTEG_DATA_LB_TX (0x1<<1)
4765 #define E2_INTEG_DATA_LB_TX_SHIFT 1
4766 #define E2_INTEG_DATA_COS_TX (0x1<<2)
4767 #define E2_INTEG_DATA_COS_TX_SHIFT 2
4768 #define E2_INTEG_DATA_OPPORTUNISTICQM (0x1<<3)
4769 #define E2_INTEG_DATA_OPPORTUNISTICQM_SHIFT 3
4770 #define E2_INTEG_DATA_DPMTESTRELEASEDQ (0x1<<4)
4771 #define E2_INTEG_DATA_DPMTESTRELEASEDQ_SHIFT 4
4772 #define E2_INTEG_DATA_RESERVED (0x7<<5)
4773 #define E2_INTEG_DATA_RESERVED_SHIFT 5
4777 #elif defined(__LITTLE_ENDIAN)
4782 #define E2_INTEG_DATA_TESTING_EN (0x1<<0)
4783 #define E2_INTEG_DATA_TESTING_EN_SHIFT 0
4784 #define E2_INTEG_DATA_LB_TX (0x1<<1)
4785 #define E2_INTEG_DATA_LB_TX_SHIFT 1
4786 #define E2_INTEG_DATA_COS_TX (0x1<<2)
4787 #define E2_INTEG_DATA_COS_TX_SHIFT 2
4788 #define E2_INTEG_DATA_OPPORTUNISTICQM (0x1<<3)
4789 #define E2_INTEG_DATA_OPPORTUNISTICQM_SHIFT 3
4790 #define E2_INTEG_DATA_DPMTESTRELEASEDQ (0x1<<4)
4791 #define E2_INTEG_DATA_DPMTESTRELEASEDQ_SHIFT 4
4792 #define E2_INTEG_DATA_RESERVED (0x7<<5)
4793 #define E2_INTEG_DATA_RESERVED_SHIFT 5
4795 #if defined(__BIG_ENDIAN)
4799 #elif defined(__LITTLE_ENDIAN)
4808 * set mac event data
4810 struct eth_event_data {
4820 struct vf_pf_event_data {
4831 struct vf_flr_event_data {
4840 * malicious VF event data
4842 struct malicious_vf_event_data {
4851 * vif list event data
4853 struct vif_list_event_data {
4861 /* function update event data */
4862 struct function_update_event_data {
4871 /* union for all event ring message types */
4873 struct vf_pf_event_data vf_pf_event;
4874 struct eth_event_data eth_event;
4875 struct cfc_del_event_data cfc_del_event;
4876 struct vf_flr_event_data vf_flr_event;
4877 struct malicious_vf_event_data malicious_vf_event;
4878 struct vif_list_event_data vif_list_event;
4879 struct function_update_event_data function_update_event;
4884 * per PF event ring data
4886 struct event_ring_data {
4887 struct regpair base_addr;
4888 #if defined(__BIG_ENDIAN)
4892 #elif defined(__LITTLE_ENDIAN)
4902 * event ring message element (each element is 128 bits)
4904 struct event_ring_msg {
4908 union event_data data;
4912 * event ring next page element (128 bits)
4914 struct event_ring_next {
4915 struct regpair addr;
4920 * union for event ring element types (each element is 128 bits)
4922 union event_ring_elem {
4923 struct event_ring_msg message;
4924 struct event_ring_next next_page;
4929 * Common event ring opcodes
4931 enum event_ring_opcode {
4932 EVENT_RING_OPCODE_VF_PF_CHANNEL,
4933 EVENT_RING_OPCODE_FUNCTION_START,
4934 EVENT_RING_OPCODE_FUNCTION_STOP,
4935 EVENT_RING_OPCODE_CFC_DEL,
4936 EVENT_RING_OPCODE_CFC_DEL_WB,
4937 EVENT_RING_OPCODE_STAT_QUERY,
4938 EVENT_RING_OPCODE_STOP_TRAFFIC,
4939 EVENT_RING_OPCODE_START_TRAFFIC,
4940 EVENT_RING_OPCODE_VF_FLR,
4941 EVENT_RING_OPCODE_MALICIOUS_VF,
4942 EVENT_RING_OPCODE_FORWARD_SETUP,
4943 EVENT_RING_OPCODE_RSS_UPDATE_RULES,
4944 EVENT_RING_OPCODE_FUNCTION_UPDATE,
4945 EVENT_RING_OPCODE_AFEX_VIF_LISTS,
4946 EVENT_RING_OPCODE_SET_MAC,
4947 EVENT_RING_OPCODE_CLASSIFICATION_RULES,
4948 EVENT_RING_OPCODE_FILTERS_RULES,
4949 EVENT_RING_OPCODE_MULTICAST_RULES,
4950 MAX_EVENT_RING_OPCODE
4955 * Modes for fairness algorithm
4957 enum fairness_mode {
4958 FAIRNESS_COS_WRR_MODE,
4959 FAIRNESS_COS_ETS_MODE,
4967 struct priority_cos {
4974 * The data for flow control configuration
4976 struct flow_control_configuration {
4977 struct priority_cos traffic_type_to_priority_cos[MAX_TRAFFIC_TYPES];
4980 u8 dont_add_pri_0_en;
4989 struct function_start_data {
4995 u8 network_cos_mode;
4999 struct function_update_data {
5000 u8 vif_id_change_flg;
5001 u8 afex_default_vlan_change_flg;
5002 u8 allowed_priorities_change_flg;
5003 u8 network_cos_mode_change_flg;
5005 __le16 afex_default_vlan;
5006 u8 allowed_priorities;
5007 u8 network_cos_mode;
5009 u8 tx_switch_suspend_change_flg;
5010 u8 tx_switch_suspend;
5017 * FW version stored in the Xstorm RAM
5020 #if defined(__BIG_ENDIAN)
5025 #elif defined(__LITTLE_ENDIAN)
5032 #define FW_VERSION_OPTIMIZED (0x1<<0)
5033 #define FW_VERSION_OPTIMIZED_SHIFT 0
5034 #define FW_VERSION_BIG_ENDIEN (0x1<<1)
5035 #define FW_VERSION_BIG_ENDIEN_SHIFT 1
5036 #define FW_VERSION_CHIP_VERSION (0x3<<2)
5037 #define FW_VERSION_CHIP_VERSION_SHIFT 2
5038 #define __FW_VERSION_RESERVED (0xFFFFFFF<<4)
5039 #define __FW_VERSION_RESERVED_SHIFT 4
5044 * Dynamic Host-Coalescing - Driver(host) counters
5046 struct hc_dynamic_sb_drv_counters {
5047 u32 dynamic_hc_drv_counter[HC_SB_MAX_DYNAMIC_INDICES];
5052 * 2 bytes. configuration/state parameters for a single protocol index
5054 struct hc_index_data {
5055 #if defined(__BIG_ENDIAN)
5057 #define HC_INDEX_DATA_SM_ID (0x1<<0)
5058 #define HC_INDEX_DATA_SM_ID_SHIFT 0
5059 #define HC_INDEX_DATA_HC_ENABLED (0x1<<1)
5060 #define HC_INDEX_DATA_HC_ENABLED_SHIFT 1
5061 #define HC_INDEX_DATA_DYNAMIC_HC_ENABLED (0x1<<2)
5062 #define HC_INDEX_DATA_DYNAMIC_HC_ENABLED_SHIFT 2
5063 #define HC_INDEX_DATA_RESERVE (0x1F<<3)
5064 #define HC_INDEX_DATA_RESERVE_SHIFT 3
5066 #elif defined(__LITTLE_ENDIAN)
5069 #define HC_INDEX_DATA_SM_ID (0x1<<0)
5070 #define HC_INDEX_DATA_SM_ID_SHIFT 0
5071 #define HC_INDEX_DATA_HC_ENABLED (0x1<<1)
5072 #define HC_INDEX_DATA_HC_ENABLED_SHIFT 1
5073 #define HC_INDEX_DATA_DYNAMIC_HC_ENABLED (0x1<<2)
5074 #define HC_INDEX_DATA_DYNAMIC_HC_ENABLED_SHIFT 2
5075 #define HC_INDEX_DATA_RESERVE (0x1F<<3)
5076 #define HC_INDEX_DATA_RESERVE_SHIFT 3
5084 struct hc_status_block_sm {
5085 #if defined(__BIG_ENDIAN)
5090 #elif defined(__LITTLE_ENDIAN)
5100 * hold PCI identification variables- used in various places in firmware
5103 #if defined(__BIG_ENDIAN)
5108 #elif defined(__LITTLE_ENDIAN)
5117 * The fast-path status block meta-data, common to all chips
5120 struct regpair host_sb_addr;
5121 struct hc_status_block_sm state_machine[HC_SB_MAX_SM];
5122 struct pci_entity p_func;
5123 #if defined(__BIG_ENDIAN)
5128 #elif defined(__LITTLE_ENDIAN)
5134 struct regpair rsrv1[2];
5139 * Segment types for host coaslescing
5149 * The fast-path status block meta-data
5151 struct hc_sp_status_block_data {
5152 struct regpair host_sb_addr;
5153 #if defined(__BIG_ENDIAN)
5158 #elif defined(__LITTLE_ENDIAN)
5164 struct pci_entity p_func;
5169 * The fast-path status block meta-data
5171 struct hc_status_block_data_e1x {
5172 struct hc_index_data index_data[HC_SB_MAX_INDICES_E1X];
5173 struct hc_sb_data common;
5178 * The fast-path status block meta-data
5180 struct hc_status_block_data_e2 {
5181 struct hc_index_data index_data[HC_SB_MAX_INDICES_E2];
5182 struct hc_sb_data common;
5187 * IGU block operartion modes (in Everest2)
5207 * Multi-function modes
5213 MULTI_FUNCTION_AFEX,
5218 * Protocol-common statistics collected by the Tstorm (per pf)
5220 struct tstorm_per_pf_stats {
5221 struct regpair rcv_error_bytes;
5227 struct per_pf_stats {
5228 struct tstorm_per_pf_stats tstorm_pf_statistics;
5233 * Protocol-common statistics collected by the Tstorm (per port)
5235 struct tstorm_per_port_stats {
5237 __le32 mac_filter_discard;
5238 __le32 brb_truncate_discard;
5239 __le32 mf_tag_discard;
5247 struct per_port_stats {
5248 struct tstorm_per_port_stats tstorm_port_statistics;
5253 * Protocol-common statistics collected by the Tstorm (per client)
5255 struct tstorm_per_queue_stats {
5256 struct regpair rcv_ucast_bytes;
5257 __le32 rcv_ucast_pkts;
5258 __le32 checksum_discard;
5259 struct regpair rcv_bcast_bytes;
5260 __le32 rcv_bcast_pkts;
5261 __le32 pkts_too_big_discard;
5262 struct regpair rcv_mcast_bytes;
5263 __le32 rcv_mcast_pkts;
5264 __le32 ttl0_discard;
5265 __le16 no_buff_discard;
5271 * Protocol-common statistics collected by the Ustorm (per client)
5273 struct ustorm_per_queue_stats {
5274 struct regpair ucast_no_buff_bytes;
5275 struct regpair mcast_no_buff_bytes;
5276 struct regpair bcast_no_buff_bytes;
5277 __le32 ucast_no_buff_pkts;
5278 __le32 mcast_no_buff_pkts;
5279 __le32 bcast_no_buff_pkts;
5280 __le32 coalesced_pkts;
5281 struct regpair coalesced_bytes;
5282 __le32 coalesced_events;
5283 __le32 coalesced_aborts;
5287 * Protocol-common statistics collected by the Xstorm (per client)
5289 struct xstorm_per_queue_stats {
5290 struct regpair ucast_bytes_sent;
5291 struct regpair mcast_bytes_sent;
5292 struct regpair bcast_bytes_sent;
5293 __le32 ucast_pkts_sent;
5294 __le32 mcast_pkts_sent;
5295 __le32 bcast_pkts_sent;
5296 __le32 error_drop_pkts;
5302 struct per_queue_stats {
5303 struct tstorm_per_queue_stats tstorm_queue_statistics;
5304 struct ustorm_per_queue_stats ustorm_queue_statistics;
5305 struct xstorm_per_queue_stats xstorm_queue_statistics;
5310 * FW version stored in first line of pram
5312 struct pram_fw_version {
5318 #define PRAM_FW_VERSION_OPTIMIZED (0x1<<0)
5319 #define PRAM_FW_VERSION_OPTIMIZED_SHIFT 0
5320 #define PRAM_FW_VERSION_STORM_ID (0x3<<1)
5321 #define PRAM_FW_VERSION_STORM_ID_SHIFT 1
5322 #define PRAM_FW_VERSION_BIG_ENDIEN (0x1<<3)
5323 #define PRAM_FW_VERSION_BIG_ENDIEN_SHIFT 3
5324 #define PRAM_FW_VERSION_CHIP_VERSION (0x3<<4)
5325 #define PRAM_FW_VERSION_CHIP_VERSION_SHIFT 4
5326 #define __PRAM_FW_VERSION_RESERVED0 (0x3<<6)
5327 #define __PRAM_FW_VERSION_RESERVED0_SHIFT 6
5332 * Ethernet slow path element
5334 union protocol_common_specific_data {
5335 u8 protocol_data[8];
5336 struct regpair phy_address;
5337 struct regpair mac_config_addr;
5338 struct afex_vif_list_ramrod_data afex_vif_list_data;
5342 * The send queue element
5344 struct protocol_common_spe {
5346 union protocol_common_specific_data data;
5351 * The send queue element
5353 struct slow_path_element {
5355 struct regpair protocol_data;
5360 * Protocol-common statistics counter
5362 struct stats_counter {
5363 __le16 xstats_counter;
5366 __le16 tstats_counter;
5369 __le16 ustats_counter;
5372 __le16 cstats_counter;
5381 struct stats_query_entry {
5386 struct regpair address;
5392 struct stats_query_cmd_group {
5393 struct stats_query_entry query[STATS_QUERY_CMD_COUNT];
5398 * statistic command header
5400 struct stats_query_header {
5403 __le16 drv_stats_counter;
5405 struct regpair stats_counters_addrs;
5410 * Types of statistcis query entry
5412 enum stats_query_type {
5418 MAX_STATS_QUERY_TYPE
5423 * Indicate of the function status block state
5425 enum status_block_state {
5429 MAX_STATUS_BLOCK_STATE
5434 * Storm IDs (including attentions for IGU related enums)
5447 * Taffic types used in ETS and flow control algorithms
5450 LLFC_TRAFFIC_TYPE_NW,
5451 LLFC_TRAFFIC_TYPE_FCOE,
5452 LLFC_TRAFFIC_TYPE_ISCSI,
5458 * zone A per-queue data
5460 struct tstorm_queue_zone_data {
5461 struct regpair reserved[4];
5466 * zone B per-VF data
5468 struct tstorm_vf_zone_data {
5469 struct regpair reserved;
5474 * zone A per-queue data
5476 struct ustorm_queue_zone_data {
5477 struct ustorm_eth_rx_producers eth_rx_producers;
5478 struct regpair reserved[3];
5483 * zone B per-VF data
5485 struct ustorm_vf_zone_data {
5486 struct regpair reserved;
5491 * data per VF-PF channel
5493 struct vf_pf_channel_data {
5494 #if defined(__BIG_ENDIAN)
5498 #elif defined(__LITTLE_ENDIAN)
5508 * State of VF-PF channel
5510 enum vf_pf_channel_state {
5511 VF_PF_CHANNEL_STATE_READY,
5512 VF_PF_CHANNEL_STATE_WAITING_FOR_ACK,
5513 MAX_VF_PF_CHANNEL_STATE
5518 * vif_list_rule_kind
5520 enum vif_list_rule_kind {
5523 VIF_LIST_RULE_CLEAR_ALL,
5524 VIF_LIST_RULE_CLEAR_FUNC,
5525 MAX_VIF_LIST_RULE_KIND
5530 * zone A per-queue data
5532 struct xstorm_queue_zone_data {
5533 struct regpair reserved[4];
5538 * zone B per-VF data
5540 struct xstorm_vf_zone_data {
5541 struct regpair reserved;
5544 #endif /* BNX2X_HSI_H */
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