drivers/net/ethernet/broadcom/bnx2x/bnx2x_link.c

   1 /* Copyright 2008-2011 Broadcom Corporation
   2  *
   3  * Unless you and Broadcom execute a separate written software license
   4  * agreement governing use of this software, this software is licensed to you
   5  * under the terms of the GNU General Public License version 2, available
   6  * at http://www.gnu.org/licenses/old-licenses/gpl-2.0.html (the "GPL").
   7  *
   8  * Notwithstanding the above, under no circumstances may you combine this
   9  * software in any way with any other Broadcom software provided under a
  10  * license other than the GPL, without Broadcom's express prior written
  11  * consent.
  12  *
  13  * Written by Yaniv Rosner
  14  *
  15  */
  16
  17 #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
  18
  19 #include <linux/kernel.h>
  20 #include <linux/errno.h>
  21 #include <linux/pci.h>
  22 #include <linux/netdevice.h>
  23 #include <linux/delay.h>
  24 #include <linux/ethtool.h>
  25 #include <linux/mutex.h>
  26
  27 #include "bnx2x.h"
  28 #include "bnx2x_cmn.h"
  29
  30
  31 /********************************************************/
  32 #define ETH_HLEN                        14
  33 /* L2 header size + 2*VLANs (8 bytes) + LLC SNAP (8 bytes) */
  34 #define ETH_OVREHEAD                    (ETH_HLEN + 8 + 8)
  35 #define ETH_MIN_PACKET_SIZE             60
  36 #define ETH_MAX_PACKET_SIZE             1500
  37 #define ETH_MAX_JUMBO_PACKET_SIZE       9600
  38 #define MDIO_ACCESS_TIMEOUT             1000
  39 #define BMAC_CONTROL_RX_ENABLE          2
  40 #define WC_LANE_MAX                     4
  41 #define I2C_SWITCH_WIDTH                2
  42 #define I2C_BSC0                        0
  43 #define I2C_BSC1                        1
  44 #define I2C_WA_RETRY_CNT                3
  45 #define MCPR_IMC_COMMAND_READ_OP        1
  46 #define MCPR_IMC_COMMAND_WRITE_OP       2
  47
  48 /* LED Blink rate that will achieve ~15.9Hz */
  49 #define LED_BLINK_RATE_VAL_E3           354
  50 #define LED_BLINK_RATE_VAL_E1X_E2       480
  51 /***********************************************************/
  52 /*                      Shortcut definitions               */
  53 /***********************************************************/
  54
  55 #define NIG_LATCH_BC_ENABLE_MI_INT 0
  56
  57 #define NIG_STATUS_EMAC0_MI_INT \
  58                 NIG_STATUS_INTERRUPT_PORT0_REG_STATUS_EMAC0_MISC_MI_INT
  59 #define NIG_STATUS_XGXS0_LINK10G \
  60                 NIG_STATUS_INTERRUPT_PORT0_REG_STATUS_XGXS0_LINK10G
  61 #define NIG_STATUS_XGXS0_LINK_STATUS \
  62                 NIG_STATUS_INTERRUPT_PORT0_REG_STATUS_XGXS0_LINK_STATUS
  63 #define NIG_STATUS_XGXS0_LINK_STATUS_SIZE \
  64                 NIG_STATUS_INTERRUPT_PORT0_REG_STATUS_XGXS0_LINK_STATUS_SIZE
  65 #define NIG_STATUS_SERDES0_LINK_STATUS \
  66                 NIG_STATUS_INTERRUPT_PORT0_REG_STATUS_SERDES0_LINK_STATUS
  67 #define NIG_MASK_MI_INT \
  68                 NIG_MASK_INTERRUPT_PORT0_REG_MASK_EMAC0_MISC_MI_INT
  69 #define NIG_MASK_XGXS0_LINK10G \
  70                 NIG_MASK_INTERRUPT_PORT0_REG_MASK_XGXS0_LINK10G
  71 #define NIG_MASK_XGXS0_LINK_STATUS \
  72                 NIG_MASK_INTERRUPT_PORT0_REG_MASK_XGXS0_LINK_STATUS
  73 #define NIG_MASK_SERDES0_LINK_STATUS \
  74                 NIG_MASK_INTERRUPT_PORT0_REG_MASK_SERDES0_LINK_STATUS
  75
  76 #define MDIO_AN_CL73_OR_37_COMPLETE \
  77                 (MDIO_GP_STATUS_TOP_AN_STATUS1_CL73_AUTONEG_COMPLETE | \
  78                  MDIO_GP_STATUS_TOP_AN_STATUS1_CL37_AUTONEG_COMPLETE)
  79
  80 #define XGXS_RESET_BITS \
  81         (MISC_REGISTERS_RESET_REG_3_MISC_NIG_MUX_XGXS0_RSTB_HW |   \
  82          MISC_REGISTERS_RESET_REG_3_MISC_NIG_MUX_XGXS0_IDDQ |      \
  83          MISC_REGISTERS_RESET_REG_3_MISC_NIG_MUX_XGXS0_PWRDWN |    \
  84          MISC_REGISTERS_RESET_REG_3_MISC_NIG_MUX_XGXS0_PWRDWN_SD | \
  85          MISC_REGISTERS_RESET_REG_3_MISC_NIG_MUX_XGXS0_TXD_FIFO_RSTB)
  86
  87 #define SERDES_RESET_BITS \
  88         (MISC_REGISTERS_RESET_REG_3_MISC_NIG_MUX_SERDES0_RSTB_HW | \
  89          MISC_REGISTERS_RESET_REG_3_MISC_NIG_MUX_SERDES0_IDDQ |    \
  90          MISC_REGISTERS_RESET_REG_3_MISC_NIG_MUX_SERDES0_PWRDWN |  \
  91          MISC_REGISTERS_RESET_REG_3_MISC_NIG_MUX_SERDES0_PWRDWN_SD)
  92
  93 #define AUTONEG_CL37            SHARED_HW_CFG_AN_ENABLE_CL37
  94 #define AUTONEG_CL73            SHARED_HW_CFG_AN_ENABLE_CL73
  95 #define AUTONEG_BAM             SHARED_HW_CFG_AN_ENABLE_BAM
  96 #define AUTONEG_PARALLEL \
  97                                 SHARED_HW_CFG_AN_ENABLE_PARALLEL_DETECTION
  98 #define AUTONEG_SGMII_FIBER_AUTODET \
  99                                 SHARED_HW_CFG_AN_EN_SGMII_FIBER_AUTO_DETECT
 100 #define AUTONEG_REMOTE_PHY      SHARED_HW_CFG_AN_ENABLE_REMOTE_PHY
 101
 102 #define GP_STATUS_PAUSE_RSOLUTION_TXSIDE \
 103                         MDIO_GP_STATUS_TOP_AN_STATUS1_PAUSE_RSOLUTION_TXSIDE
 104 #define GP_STATUS_PAUSE_RSOLUTION_RXSIDE \
 105                         MDIO_GP_STATUS_TOP_AN_STATUS1_PAUSE_RSOLUTION_RXSIDE
 106 #define GP_STATUS_SPEED_MASK \
 107                         MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_MASK
 108 #define GP_STATUS_10M   MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_10M
 109 #define GP_STATUS_100M  MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_100M
 110 #define GP_STATUS_1G    MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_1G
 111 #define GP_STATUS_2_5G  MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_2_5G
 112 #define GP_STATUS_5G    MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_5G
 113 #define GP_STATUS_6G    MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_6G
 114 #define GP_STATUS_10G_HIG \
 115                         MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_10G_HIG
 116 #define GP_STATUS_10G_CX4 \
 117                         MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_10G_CX4
 118 #define GP_STATUS_1G_KX MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_1G_KX
 119 #define GP_STATUS_10G_KX4 \
 120                         MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_10G_KX4
 121 #define GP_STATUS_10G_KR MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_10G_KR
 122 #define GP_STATUS_10G_XFI   MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_10G_XFI
 123 #define GP_STATUS_20G_DXGXS MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_20G_DXGXS
 124 #define GP_STATUS_10G_SFI   MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_10G_SFI
 125 #define LINK_10THD              LINK_STATUS_SPEED_AND_DUPLEX_10THD
 126 #define LINK_10TFD              LINK_STATUS_SPEED_AND_DUPLEX_10TFD
 127 #define LINK_100TXHD            LINK_STATUS_SPEED_AND_DUPLEX_100TXHD
 128 #define LINK_100T4              LINK_STATUS_SPEED_AND_DUPLEX_100T4
 129 #define LINK_100TXFD            LINK_STATUS_SPEED_AND_DUPLEX_100TXFD
 130 #define LINK_1000THD            LINK_STATUS_SPEED_AND_DUPLEX_1000THD
 131 #define LINK_1000TFD            LINK_STATUS_SPEED_AND_DUPLEX_1000TFD
 132 #define LINK_1000XFD            LINK_STATUS_SPEED_AND_DUPLEX_1000XFD
 133 #define LINK_2500THD            LINK_STATUS_SPEED_AND_DUPLEX_2500THD
 134 #define LINK_2500TFD            LINK_STATUS_SPEED_AND_DUPLEX_2500TFD
 135 #define LINK_2500XFD            LINK_STATUS_SPEED_AND_DUPLEX_2500XFD
 136 #define LINK_10GTFD             LINK_STATUS_SPEED_AND_DUPLEX_10GTFD
 137 #define LINK_10GXFD             LINK_STATUS_SPEED_AND_DUPLEX_10GXFD
 138 #define LINK_20GTFD             LINK_STATUS_SPEED_AND_DUPLEX_20GTFD
 139 #define LINK_20GXFD             LINK_STATUS_SPEED_AND_DUPLEX_20GXFD
 140
 141
 142
 143 /* */
 144 #define SFP_EEPROM_CON_TYPE_ADDR                0x2
 145         #define SFP_EEPROM_CON_TYPE_VAL_LC      0x7
 146         #define SFP_EEPROM_CON_TYPE_VAL_COPPER  0x21
 147
 148
 149 #define SFP_EEPROM_COMP_CODE_ADDR               0x3
 150         #define SFP_EEPROM_COMP_CODE_SR_MASK    (1<<4)
 151         #define SFP_EEPROM_COMP_CODE_LR_MASK    (1<<5)
 152         #define SFP_EEPROM_COMP_CODE_LRM_MASK   (1<<6)
 153
 154 #define SFP_EEPROM_FC_TX_TECH_ADDR              0x8
 155         #define SFP_EEPROM_FC_TX_TECH_BITMASK_COPPER_PASSIVE 0x4
 156         #define SFP_EEPROM_FC_TX_TECH_BITMASK_COPPER_ACTIVE  0x8
 157
 158 #define SFP_EEPROM_OPTIONS_ADDR                 0x40
 159         #define SFP_EEPROM_OPTIONS_LINEAR_RX_OUT_MASK 0x1
 160 #define SFP_EEPROM_OPTIONS_SIZE                 2
 161
 162 #define EDC_MODE_LINEAR                         0x0022
 163 #define EDC_MODE_LIMITING                               0x0044
 164 #define EDC_MODE_PASSIVE_DAC                    0x0055
 165
 166
 167 /* BRB thresholds for E2*/
 168 #define PFC_E2_BRB_MAC_PAUSE_XOFF_THR_PAUSE             170
 169 #define PFC_E2_BRB_MAC_PAUSE_XOFF_THR_NON_PAUSE         0
 170
 171 #define PFC_E2_BRB_MAC_PAUSE_XON_THR_PAUSE              250
 172 #define PFC_E2_BRB_MAC_PAUSE_XON_THR_NON_PAUSE          0
 173
 174 #define PFC_E2_BRB_MAC_FULL_XOFF_THR_PAUSE              10
 175 #define PFC_E2_BRB_MAC_FULL_XOFF_THR_NON_PAUSE          90
 176
 177 #define PFC_E2_BRB_MAC_FULL_XON_THR_PAUSE                       50
 178 #define PFC_E2_BRB_MAC_FULL_XON_THR_NON_PAUSE           250
 179
 180 /* BRB thresholds for E3A0 */
 181 #define PFC_E3A0_BRB_MAC_PAUSE_XOFF_THR_PAUSE           290
 182 #define PFC_E3A0_BRB_MAC_PAUSE_XOFF_THR_NON_PAUSE               0
 183
 184 #define PFC_E3A0_BRB_MAC_PAUSE_XON_THR_PAUSE            410
 185 #define PFC_E3A0_BRB_MAC_PAUSE_XON_THR_NON_PAUSE                0
 186
 187 #define PFC_E3A0_BRB_MAC_FULL_XOFF_THR_PAUSE            10
 188 #define PFC_E3A0_BRB_MAC_FULL_XOFF_THR_NON_PAUSE                170
 189
 190 #define PFC_E3A0_BRB_MAC_FULL_XON_THR_PAUSE             50
 191 #define PFC_E3A0_BRB_MAC_FULL_XON_THR_NON_PAUSE         410
 192
 193
 194 /* BRB thresholds for E3B0 2 port mode*/
 195 #define PFC_E3B0_2P_BRB_MAC_PAUSE_XOFF_THR_PAUSE                1025
 196 #define PFC_E3B0_2P_BRB_MAC_PAUSE_XOFF_THR_NON_PAUSE    0
 197
 198 #define PFC_E3B0_2P_BRB_MAC_PAUSE_XON_THR_PAUSE         1025
 199 #define PFC_E3B0_2P_BRB_MAC_PAUSE_XON_THR_NON_PAUSE     0
 200
 201 #define PFC_E3B0_2P_BRB_MAC_FULL_XOFF_THR_PAUSE         10
 202 #define PFC_E3B0_2P_BRB_MAC_FULL_XOFF_THR_NON_PAUSE     1025
 203
 204 #define PFC_E3B0_2P_BRB_MAC_FULL_XON_THR_PAUSE          50
 205 #define PFC_E3B0_2P_BRB_MAC_FULL_XON_THR_NON_PAUSE      1025
 206
 207 /* only for E3B0*/
 208 #define PFC_E3B0_2P_BRB_FULL_LB_XOFF_THR                        1025
 209 #define PFC_E3B0_2P_BRB_FULL_LB_XON_THR                 1025
 210
 211 /* Lossy +Lossless GUARANTIED == GUART */
 212 #define PFC_E3B0_2P_MIX_PAUSE_LB_GUART                  284
 213 /* Lossless +Lossless*/
 214 #define PFC_E3B0_2P_PAUSE_LB_GUART                      236
 215 /* Lossy +Lossy*/
 216 #define PFC_E3B0_2P_NON_PAUSE_LB_GUART                  342
 217
 218 /* Lossy +Lossless*/
 219 #define PFC_E3B0_2P_MIX_PAUSE_MAC_0_CLASS_T_GUART               284
 220 /* Lossless +Lossless*/
 221 #define PFC_E3B0_2P_PAUSE_MAC_0_CLASS_T_GUART           236
 222 /* Lossy +Lossy*/
 223 #define PFC_E3B0_2P_NON_PAUSE_MAC_0_CLASS_T_GUART               336
 224 #define PFC_E3B0_2P_BRB_MAC_0_CLASS_T_GUART_HYST                80
 225
 226 #define PFC_E3B0_2P_BRB_MAC_1_CLASS_T_GUART             0
 227 #define PFC_E3B0_2P_BRB_MAC_1_CLASS_T_GUART_HYST                0
 228
 229 /* BRB thresholds for E3B0 4 port mode */
 230 #define PFC_E3B0_4P_BRB_MAC_PAUSE_XOFF_THR_PAUSE                304
 231 #define PFC_E3B0_4P_BRB_MAC_PAUSE_XOFF_THR_NON_PAUSE    0
 232
 233 #define PFC_E3B0_4P_BRB_MAC_PAUSE_XON_THR_PAUSE         384
 234 #define PFC_E3B0_4P_BRB_MAC_PAUSE_XON_THR_NON_PAUSE     0
 235
 236 #define PFC_E3B0_4P_BRB_MAC_FULL_XOFF_THR_PAUSE         10
 237 #define PFC_E3B0_4P_BRB_MAC_FULL_XOFF_THR_NON_PAUSE     304
 238
 239 #define PFC_E3B0_4P_BRB_MAC_FULL_XON_THR_PAUSE          50
 240 #define PFC_E3B0_4P_BRB_MAC_FULL_XON_THR_NON_PAUSE      384
 241
 242
 243 /* only for E3B0*/
 244 #define PFC_E3B0_4P_BRB_FULL_LB_XOFF_THR                        304
 245 #define PFC_E3B0_4P_BRB_FULL_LB_XON_THR                 384
 246 #define PFC_E3B0_4P_LB_GUART                            120
 247
 248 #define PFC_E3B0_4P_BRB_MAC_0_CLASS_T_GUART             120
 249 #define PFC_E3B0_4P_BRB_MAC_0_CLASS_T_GUART_HYST                80
 250
 251 #define PFC_E3B0_4P_BRB_MAC_1_CLASS_T_GUART             80
 252 #define PFC_E3B0_4P_BRB_MAC_1_CLASS_T_GUART_HYST                120
 253
 254 #define DCBX_INVALID_COS                                        (0xFF)
 255
 256 #define ETS_BW_LIMIT_CREDIT_UPPER_BOUND         (0x5000)
 257 #define ETS_BW_LIMIT_CREDIT_WEIGHT              (0x5000)
 258 #define ETS_E3B0_NIG_MIN_W_VAL_UP_TO_10GBPS             (1360)
 259 #define ETS_E3B0_NIG_MIN_W_VAL_20GBPS                   (2720)
 260 #define ETS_E3B0_PBF_MIN_W_VAL                          (10000)
 261
 262 #define MAX_PACKET_SIZE                                 (9700)
 263 #define WC_UC_TIMEOUT                                   100
 264 #define MAX_KR_LINK_RETRY                               4
 265
 266 /**********************************************************/
 267 /*                     INTERFACE                          */
 268 /**********************************************************/
 269
 270 #define CL22_WR_OVER_CL45(_bp, _phy, _bank, _addr, _val) \
 271         bnx2x_cl45_write(_bp, _phy, \
 272                 (_phy)->def_md_devad, \
 273                 (_bank + (_addr & 0xf)), \
 274                 _val)
 275
 276 #define CL22_RD_OVER_CL45(_bp, _phy, _bank, _addr, _val) \
 277         bnx2x_cl45_read(_bp, _phy, \
 278                 (_phy)->def_md_devad, \
 279                 (_bank + (_addr & 0xf)), \
 280                 _val)
 281
 282 static u32 bnx2x_bits_en(struct bnx2x *bp, u32 reg, u32 bits)
 283 {
 284         u32 val = REG_RD(bp, reg);
 285
 286         val |= bits;
 287         REG_WR(bp, reg, val);
 288         return val;
 289 }
 290
 291 static u32 bnx2x_bits_dis(struct bnx2x *bp, u32 reg, u32 bits)
 292 {
 293         u32 val = REG_RD(bp, reg);
 294
 295         val &= ~bits;
 296         REG_WR(bp, reg, val);
 297         return val;
 298 }
 299
 300 /******************************************************************/
 301 /*                      EPIO/GPIO section                         */
 302 /******************************************************************/
 303 static void bnx2x_get_epio(struct bnx2x *bp, u32 epio_pin, u32 *en)
 304 {
 305         u32 epio_mask, gp_oenable;
 306         *en = 0;
 307         /* Sanity check */
 308         if (epio_pin > 31) {
 309                 DP(NETIF_MSG_LINK, "Invalid EPIO pin %d to get\n", epio_pin);
 310                 return;
 311         }
 312
 313         epio_mask = 1 << epio_pin;
 314         /* Set this EPIO to output */
 315         gp_oenable = REG_RD(bp, MCP_REG_MCPR_GP_OENABLE);
 316         REG_WR(bp, MCP_REG_MCPR_GP_OENABLE, gp_oenable & ~epio_mask);
 317
 318         *en = (REG_RD(bp, MCP_REG_MCPR_GP_INPUTS) & epio_mask) >> epio_pin;
 319 }
 320 static void bnx2x_set_epio(struct bnx2x *bp, u32 epio_pin, u32 en)
 321 {
 322         u32 epio_mask, gp_output, gp_oenable;
 323
 324         /* Sanity check */
 325         if (epio_pin > 31) {
 326                 DP(NETIF_MSG_LINK, "Invalid EPIO pin %d to set\n", epio_pin);
 327                 return;
 328         }
 329         DP(NETIF_MSG_LINK, "Setting EPIO pin %d to %d\n", epio_pin, en);
 330         epio_mask = 1 << epio_pin;
 331         /* Set this EPIO to output */
 332         gp_output = REG_RD(bp, MCP_REG_MCPR_GP_OUTPUTS);
 333         if (en)
 334                 gp_output |= epio_mask;
 335         else
 336                 gp_output &= ~epio_mask;
 337
 338         REG_WR(bp, MCP_REG_MCPR_GP_OUTPUTS, gp_output);
 339
 340         /* Set the value for this EPIO */
 341         gp_oenable = REG_RD(bp, MCP_REG_MCPR_GP_OENABLE);
 342         REG_WR(bp, MCP_REG_MCPR_GP_OENABLE, gp_oenable | epio_mask);
 343 }
 344
 345 static void bnx2x_set_cfg_pin(struct bnx2x *bp, u32 pin_cfg, u32 val)
 346 {
 347         if (pin_cfg == PIN_CFG_NA)
 348                 return;
 349         if (pin_cfg >= PIN_CFG_EPIO0) {
 350                 bnx2x_set_epio(bp, pin_cfg - PIN_CFG_EPIO0, val);
 351         } else {
 352                 u8 gpio_num = (pin_cfg - PIN_CFG_GPIO0_P0) & 0x3;
 353                 u8 gpio_port = (pin_cfg - PIN_CFG_GPIO0_P0) >> 2;
 354                 bnx2x_set_gpio(bp, gpio_num, (u8)val, gpio_port);
 355         }
 356 }
 357
 358 static u32 bnx2x_get_cfg_pin(struct bnx2x *bp, u32 pin_cfg, u32 *val)
 359 {
 360         if (pin_cfg == PIN_CFG_NA)
 361                 return -EINVAL;
 362         if (pin_cfg >= PIN_CFG_EPIO0) {
 363                 bnx2x_get_epio(bp, pin_cfg - PIN_CFG_EPIO0, val);
 364         } else {
 365                 u8 gpio_num = (pin_cfg - PIN_CFG_GPIO0_P0) & 0x3;
 366                 u8 gpio_port = (pin_cfg - PIN_CFG_GPIO0_P0) >> 2;
 367                 *val = bnx2x_get_gpio(bp, gpio_num, gpio_port);
 368         }
 369         return 0;
 370
 371 }
 372 /******************************************************************/
 373 /*                              ETS section                       */
 374 /******************************************************************/
 375 static void bnx2x_ets_e2e3a0_disabled(struct link_params *params)
 376 {
 377         /* ETS disabled configuration*/
 378         struct bnx2x *bp = params->bp;
 379
 380         DP(NETIF_MSG_LINK, "ETS E2E3 disabled configuration\n");
 381
 382         /*
 383          * mapping between entry  priority to client number (0,1,2 -debug and
 384          * management clients, 3 - COS0 client, 4 - COS client)(HIGHEST)
 385          * 3bits client num.
 386          *   PRI4    |    PRI3    |    PRI2    |    PRI1    |    PRI0
 387          * cos1-100     cos0-011     dbg1-010     dbg0-001     MCP-000
 388          */
 389
 390         REG_WR(bp, NIG_REG_P0_TX_ARB_PRIORITY_CLIENT, 0x4688);
 391         /*
 392          * Bitmap of 5bits length. Each bit specifies whether the entry behaves
 393          * as strict.  Bits 0,1,2 - debug and management entries, 3 -
 394          * COS0 entry, 4 - COS1 entry.
 395          * COS1 | COS0 | DEBUG1 | DEBUG0 | MGMT
 396          * bit4   bit3    bit2   bit1     bit0
 397          * MCP and debug are strict
 398          */
 399
 400         REG_WR(bp, NIG_REG_P0_TX_ARB_CLIENT_IS_STRICT, 0x7);
 401         /* defines which entries (clients) are subjected to WFQ arbitration */
 402         REG_WR(bp, NIG_REG_P0_TX_ARB_CLIENT_IS_SUBJECT2WFQ, 0);
 403         /*
 404          * For strict priority entries defines the number of consecutive
 405          * slots for the highest priority.
 406          */
 407         REG_WR(bp, NIG_REG_P0_TX_ARB_NUM_STRICT_ARB_SLOTS, 0x100);
 408         /*
 409          * mapping between the CREDIT_WEIGHT registers and actual client
 410          * numbers
 411          */
 412         REG_WR(bp, NIG_REG_P0_TX_ARB_CLIENT_CREDIT_MAP, 0);
 413         REG_WR(bp, NIG_REG_P0_TX_ARB_CREDIT_WEIGHT_0, 0);
 414         REG_WR(bp, NIG_REG_P0_TX_ARB_CREDIT_WEIGHT_1, 0);
 415
 416         REG_WR(bp, NIG_REG_P0_TX_ARB_CREDIT_UPPER_BOUND_0, 0);
 417         REG_WR(bp, NIG_REG_P0_TX_ARB_CREDIT_UPPER_BOUND_1, 0);
 418         REG_WR(bp, PBF_REG_HIGH_PRIORITY_COS_NUM, 0);
 419         /* ETS mode disable */
 420         REG_WR(bp, PBF_REG_ETS_ENABLED, 0);
 421         /*
 422          * If ETS mode is enabled (there is no strict priority) defines a WFQ
 423          * weight for COS0/COS1.
 424          */
 425         REG_WR(bp, PBF_REG_COS0_WEIGHT, 0x2710);
 426         REG_WR(bp, PBF_REG_COS1_WEIGHT, 0x2710);
 427         /* Upper bound that COS0_WEIGHT can reach in the WFQ arbiter */
 428         REG_WR(bp, PBF_REG_COS0_UPPER_BOUND, 0x989680);
 429         REG_WR(bp, PBF_REG_COS1_UPPER_BOUND, 0x989680);
 430         /* Defines the number of consecutive slots for the strict priority */
 431         REG_WR(bp, PBF_REG_NUM_STRICT_ARB_SLOTS, 0);
 432 }
 433 /******************************************************************************
 434 * Description:
 435 *       Getting min_w_val will be set according to line speed .
 436 *.
 437 ******************************************************************************/
 438 static u32 bnx2x_ets_get_min_w_val_nig(const struct link_vars *vars)
 439 {
 440         u32 min_w_val = 0;
 441         /* Calculate min_w_val.*/
 442         if (vars->link_up) {
 443                 if (SPEED_20000 == vars->line_speed)
 444                         min_w_val = ETS_E3B0_NIG_MIN_W_VAL_20GBPS;
 445                 else
 446                         min_w_val = ETS_E3B0_NIG_MIN_W_VAL_UP_TO_10GBPS;
 447         } else
 448                 min_w_val = ETS_E3B0_NIG_MIN_W_VAL_20GBPS;
 449         /**
 450          *  If the link isn't up (static configuration for example ) The
 451          *  link will be according to 20GBPS.
 452         */
 453         return min_w_val;
 454 }
 455 /******************************************************************************
 456 * Description:
 457 *       Getting credit upper bound form min_w_val.
 458 *.
 459 ******************************************************************************/
 460 static u32 bnx2x_ets_get_credit_upper_bound(const u32 min_w_val)
 461 {
 462         const u32 credit_upper_bound = (u32)MAXVAL((150 * min_w_val),
 463                                                 MAX_PACKET_SIZE);
 464         return credit_upper_bound;
 465 }
 466 /******************************************************************************
 467 * Description:
 468 *       Set credit upper bound for NIG.
 469 *.
 470 ******************************************************************************/
 471 static void bnx2x_ets_e3b0_set_credit_upper_bound_nig(
 472         const struct link_params *params,
 473         const u32 min_w_val)
 474 {
 475         struct bnx2x *bp = params->bp;
 476         const u8 port = params->port;
 477         const u32 credit_upper_bound =
 478             bnx2x_ets_get_credit_upper_bound(min_w_val);
 479
 480         REG_WR(bp, (port) ? NIG_REG_P1_TX_ARB_CREDIT_UPPER_BOUND_0 :
 481                 NIG_REG_P0_TX_ARB_CREDIT_UPPER_BOUND_0, credit_upper_bound);
 482         REG_WR(bp, (port) ? NIG_REG_P1_TX_ARB_CREDIT_UPPER_BOUND_1 :
 483                    NIG_REG_P0_TX_ARB_CREDIT_UPPER_BOUND_1, credit_upper_bound);
 484         REG_WR(bp, (port) ? NIG_REG_P1_TX_ARB_CREDIT_UPPER_BOUND_2 :
 485                    NIG_REG_P0_TX_ARB_CREDIT_UPPER_BOUND_2, credit_upper_bound);
 486         REG_WR(bp, (port) ? NIG_REG_P1_TX_ARB_CREDIT_UPPER_BOUND_3 :
 487                    NIG_REG_P0_TX_ARB_CREDIT_UPPER_BOUND_3, credit_upper_bound);
 488         REG_WR(bp, (port) ? NIG_REG_P1_TX_ARB_CREDIT_UPPER_BOUND_4 :
 489                    NIG_REG_P0_TX_ARB_CREDIT_UPPER_BOUND_4, credit_upper_bound);
 490         REG_WR(bp, (port) ? NIG_REG_P1_TX_ARB_CREDIT_UPPER_BOUND_5 :
 491                    NIG_REG_P0_TX_ARB_CREDIT_UPPER_BOUND_5, credit_upper_bound);
 492
 493         if (0 == port) {
 494                 REG_WR(bp, NIG_REG_P0_TX_ARB_CREDIT_UPPER_BOUND_6,
 495                         credit_upper_bound);
 496                 REG_WR(bp, NIG_REG_P0_TX_ARB_CREDIT_UPPER_BOUND_7,
 497                         credit_upper_bound);
 498                 REG_WR(bp, NIG_REG_P0_TX_ARB_CREDIT_UPPER_BOUND_8,
 499                         credit_upper_bound);
 500         }
 501 }
 502 /******************************************************************************
 503 * Description:
 504 *       Will return the NIG ETS registers to init values.Except
 505 *       credit_upper_bound.
 506 *       That isn't used in this configuration (No WFQ is enabled) and will be
 507 *       configured acording to spec
 508 *.
 509 ******************************************************************************/
 510 static void bnx2x_ets_e3b0_nig_disabled(const struct link_params *params,
 511                                         const struct link_vars *vars)
 512 {
 513         struct bnx2x *bp = params->bp;
 514         const u8 port = params->port;
 515         const u32 min_w_val = bnx2x_ets_get_min_w_val_nig(vars);
 516         /**
 517          * mapping between entry  priority to client number (0,1,2 -debug and
 518          * management clients, 3 - COS0 client, 4 - COS1, ... 8 -
 519          * COS5)(HIGHEST) 4bits client num.TODO_ETS - Should be done by
 520          * reset value or init tool
 521          */
 522         if (port) {
 523                 REG_WR(bp, NIG_REG_P1_TX_ARB_PRIORITY_CLIENT2_LSB, 0x543210);
 524                 REG_WR(bp, NIG_REG_P1_TX_ARB_PRIORITY_CLIENT2_MSB, 0x0);
 525         } else {
 526                 REG_WR(bp, NIG_REG_P0_TX_ARB_PRIORITY_CLIENT2_LSB, 0x76543210);
 527                 REG_WR(bp, NIG_REG_P0_TX_ARB_PRIORITY_CLIENT2_MSB, 0x8);
 528         }
 529         /**
 530         * For strict priority entries defines the number of consecutive
 531         * slots for the highest priority.
 532         */
 533         /* TODO_ETS - Should be done by reset value or init tool */
 534         REG_WR(bp, (port) ? NIG_REG_P1_TX_ARB_NUM_STRICT_ARB_SLOTS :
 535                    NIG_REG_P1_TX_ARB_NUM_STRICT_ARB_SLOTS, 0x100);
 536         /**
 537          * mapping between the CREDIT_WEIGHT registers and actual client
 538          * numbers
 539          */
 540         /* TODO_ETS - Should be done by reset value or init tool */
 541         if (port) {
 542                 /*Port 1 has 6 COS*/
 543                 REG_WR(bp, NIG_REG_P1_TX_ARB_CLIENT_CREDIT_MAP2_LSB, 0x210543);
 544                 REG_WR(bp, NIG_REG_P1_TX_ARB_CLIENT_CREDIT_MAP2_MSB, 0x0);
 545         } else {
 546                 /*Port 0 has 9 COS*/
 547                 REG_WR(bp, NIG_REG_P0_TX_ARB_CLIENT_CREDIT_MAP2_LSB,
 548                        0x43210876);
 549                 REG_WR(bp, NIG_REG_P0_TX_ARB_CLIENT_CREDIT_MAP2_MSB, 0x5);
 550         }
 551
 552         /**
 553          * Bitmap of 5bits length. Each bit specifies whether the entry behaves
 554          * as strict.  Bits 0,1,2 - debug and management entries, 3 -
 555          * COS0 entry, 4 - COS1 entry.
 556          * COS1 | COS0 | DEBUG1 | DEBUG0 | MGMT
 557          * bit4   bit3    bit2   bit1     bit0
 558          * MCP and debug are strict
 559          */
 560         if (port)
 561                 REG_WR(bp, NIG_REG_P1_TX_ARB_CLIENT_IS_STRICT, 0x3f);
 562         else
 563                 REG_WR(bp, NIG_REG_P0_TX_ARB_CLIENT_IS_STRICT, 0x1ff);
 564         /* defines which entries (clients) are subjected to WFQ arbitration */
 565         REG_WR(bp, (port) ? NIG_REG_P1_TX_ARB_CLIENT_IS_SUBJECT2WFQ :
 566                    NIG_REG_P0_TX_ARB_CLIENT_IS_SUBJECT2WFQ, 0);
 567
 568         /**
 569         * Please notice the register address are note continuous and a
 570         * for here is note appropriate.In 2 port mode port0 only COS0-5
 571         * can be used. DEBUG1,DEBUG1,MGMT are never used for WFQ* In 4
 572         * port mode port1 only COS0-2 can be used. DEBUG1,DEBUG1,MGMT
 573         * are never used for WFQ
 574         */
 575         REG_WR(bp, (port) ? NIG_REG_P1_TX_ARB_CREDIT_WEIGHT_0 :
 576                    NIG_REG_P0_TX_ARB_CREDIT_WEIGHT_0, 0x0);
 577         REG_WR(bp, (port) ? NIG_REG_P1_TX_ARB_CREDIT_WEIGHT_1 :
 578                    NIG_REG_P0_TX_ARB_CREDIT_WEIGHT_1, 0x0);
 579         REG_WR(bp, (port) ? NIG_REG_P1_TX_ARB_CREDIT_WEIGHT_2 :
 580                    NIG_REG_P0_TX_ARB_CREDIT_WEIGHT_2, 0x0);
 581         REG_WR(bp, (port) ? NIG_REG_P1_TX_ARB_CREDIT_WEIGHT_3 :
 582                    NIG_REG_P0_TX_ARB_CREDIT_WEIGHT_3, 0x0);
 583         REG_WR(bp, (port) ? NIG_REG_P1_TX_ARB_CREDIT_WEIGHT_4 :
 584                    NIG_REG_P0_TX_ARB_CREDIT_WEIGHT_4, 0x0);
 585         REG_WR(bp, (port) ? NIG_REG_P1_TX_ARB_CREDIT_WEIGHT_5 :
 586                    NIG_REG_P0_TX_ARB_CREDIT_WEIGHT_5, 0x0);
 587         if (0 == port) {
 588                 REG_WR(bp, NIG_REG_P0_TX_ARB_CREDIT_WEIGHT_6, 0x0);
 589                 REG_WR(bp, NIG_REG_P0_TX_ARB_CREDIT_WEIGHT_7, 0x0);
 590                 REG_WR(bp, NIG_REG_P0_TX_ARB_CREDIT_WEIGHT_8, 0x0);
 591         }
 592
 593         bnx2x_ets_e3b0_set_credit_upper_bound_nig(params, min_w_val);
 594 }
 595 /******************************************************************************
 596 * Description:
 597 *       Set credit upper bound for PBF.
 598 *.
 599 ******************************************************************************/
 600 static void bnx2x_ets_e3b0_set_credit_upper_bound_pbf(
 601         const struct link_params *params,
 602         const u32 min_w_val)
 603 {
 604         struct bnx2x *bp = params->bp;
 605         const u32 credit_upper_bound =
 606             bnx2x_ets_get_credit_upper_bound(min_w_val);
 607         const u8 port = params->port;
 608         u32 base_upper_bound = 0;
 609         u8 max_cos = 0;
 610         u8 i = 0;
 611         /**
 612         * In 2 port mode port0 has COS0-5 that can be used for WFQ.In 4
 613         * port mode port1 has COS0-2 that can be used for WFQ.
 614         */
 615         if (0 == port) {
 616                 base_upper_bound = PBF_REG_COS0_UPPER_BOUND_P0;
 617                 max_cos = DCBX_E3B0_MAX_NUM_COS_PORT0;
 618         } else {
 619                 base_upper_bound = PBF_REG_COS0_UPPER_BOUND_P1;
 620                 max_cos = DCBX_E3B0_MAX_NUM_COS_PORT1;
 621         }
 622
 623         for (i = 0; i < max_cos; i++)
 624                 REG_WR(bp, base_upper_bound + (i << 2), credit_upper_bound);
 625 }
 626
 627 /******************************************************************************
 628 * Description:
 629 *       Will return the PBF ETS registers to init values.Except
 630 *       credit_upper_bound.
 631 *       That isn't used in this configuration (No WFQ is enabled) and will be
 632 *       configured acording to spec
 633 *.
 634 ******************************************************************************/
 635 static void bnx2x_ets_e3b0_pbf_disabled(const struct link_params *params)
 636 {
 637         struct bnx2x *bp = params->bp;
 638         const u8 port = params->port;
 639         const u32 min_w_val_pbf = ETS_E3B0_PBF_MIN_W_VAL;
 640         u8 i = 0;
 641         u32 base_weight = 0;
 642         u8 max_cos = 0;
 643
 644         /**
 645          * mapping between entry  priority to client number 0 - COS0
 646          * client, 2 - COS1, ... 5 - COS5)(HIGHEST) 4bits client num.
 647          * TODO_ETS - Should be done by reset value or init tool
 648          */
 649         if (port)
 650                 /*  0x688 (|011|0 10|00 1|000) */
 651                 REG_WR(bp, PBF_REG_ETS_ARB_PRIORITY_CLIENT_P1 , 0x688);
 652         else
 653                 /*  (10 1|100 |011|0 10|00 1|000) */
 654                 REG_WR(bp, PBF_REG_ETS_ARB_PRIORITY_CLIENT_P0 , 0x2C688);
 655
 656         /* TODO_ETS - Should be done by reset value or init tool */
 657         if (port)
 658                 /* 0x688 (|011|0 10|00 1|000)*/
 659                 REG_WR(bp, PBF_REG_ETS_ARB_CLIENT_CREDIT_MAP_P1, 0x688);
 660         else
 661         /* 0x2C688 (10 1|100 |011|0 10|00 1|000) */
 662         REG_WR(bp, PBF_REG_ETS_ARB_CLIENT_CREDIT_MAP_P0, 0x2C688);
 663
 664         REG_WR(bp, (port) ? PBF_REG_ETS_ARB_NUM_STRICT_ARB_SLOTS_P1 :
 665                    PBF_REG_ETS_ARB_NUM_STRICT_ARB_SLOTS_P0 , 0x100);
 666
 667
 668         REG_WR(bp, (port) ? PBF_REG_ETS_ARB_CLIENT_IS_STRICT_P1 :
 669                    PBF_REG_ETS_ARB_CLIENT_IS_STRICT_P0 , 0);
 670
 671         REG_WR(bp, (port) ? PBF_REG_ETS_ARB_CLIENT_IS_SUBJECT2WFQ_P1 :
 672                    PBF_REG_ETS_ARB_CLIENT_IS_SUBJECT2WFQ_P0 , 0);
 673         /**
 674         * In 2 port mode port0 has COS0-5 that can be used for WFQ.
 675         * In 4 port mode port1 has COS0-2 that can be used for WFQ.
 676         */
 677         if (0 == port) {
 678                 base_weight = PBF_REG_COS0_WEIGHT_P0;
 679                 max_cos = DCBX_E3B0_MAX_NUM_COS_PORT0;
 680         } else {
 681                 base_weight = PBF_REG_COS0_WEIGHT_P1;
 682                 max_cos = DCBX_E3B0_MAX_NUM_COS_PORT1;
 683         }
 684
 685         for (i = 0; i < max_cos; i++)
 686                 REG_WR(bp, base_weight + (0x4 * i), 0);
 687
 688         bnx2x_ets_e3b0_set_credit_upper_bound_pbf(params, min_w_val_pbf);
 689 }
 690 /******************************************************************************
 691 * Description:
 692 *       E3B0 disable will return basicly the values to init values.
 693 *.
 694 ******************************************************************************/
 695 static int bnx2x_ets_e3b0_disabled(const struct link_params *params,
 696                                    const struct link_vars *vars)
 697 {
 698         struct bnx2x *bp = params->bp;
 699
 700         if (!CHIP_IS_E3B0(bp)) {
 701                 DP(NETIF_MSG_LINK,
 702                    "bnx2x_ets_e3b0_disabled the chip isn't E3B0\n");
 703                 return -EINVAL;
 704         }
 705
 706         bnx2x_ets_e3b0_nig_disabled(params, vars);
 707
 708         bnx2x_ets_e3b0_pbf_disabled(params);
 709
 710         return 0;
 711 }
 712
 713 /******************************************************************************
 714 * Description:
 715 *       Disable will return basicly the values to init values.
 716 *.
 717 ******************************************************************************/
 718 int bnx2x_ets_disabled(struct link_params *params,
 719                       struct link_vars *vars)
 720 {
 721         struct bnx2x *bp = params->bp;
 722         int bnx2x_status = 0;
 723
 724         if ((CHIP_IS_E2(bp)) || (CHIP_IS_E3A0(bp)))
 725                 bnx2x_ets_e2e3a0_disabled(params);
 726         else if (CHIP_IS_E3B0(bp))
 727                 bnx2x_status = bnx2x_ets_e3b0_disabled(params, vars);
 728         else {
 729                 DP(NETIF_MSG_LINK, "bnx2x_ets_disabled - chip not supported\n");
 730                 return -EINVAL;
 731         }
 732
 733         return bnx2x_status;
 734 }
 735
 736 /******************************************************************************
 737 * Description
 738 *       Set the COS mappimg to SP and BW until this point all the COS are not
 739 *       set as SP or BW.
 740 ******************************************************************************/
 741 static int bnx2x_ets_e3b0_cli_map(const struct link_params *params,
 742                                   const struct bnx2x_ets_params *ets_params,
 743                                   const u8 cos_sp_bitmap,
 744                                   const u8 cos_bw_bitmap)
 745 {
 746         struct bnx2x *bp = params->bp;
 747         const u8 port = params->port;
 748         const u8 nig_cli_sp_bitmap = 0x7 | (cos_sp_bitmap << 3);
 749         const u8 pbf_cli_sp_bitmap = cos_sp_bitmap;
 750         const u8 nig_cli_subject2wfq_bitmap = cos_bw_bitmap << 3;
 751         const u8 pbf_cli_subject2wfq_bitmap = cos_bw_bitmap;
 752
 753         REG_WR(bp, (port) ? NIG_REG_P1_TX_ARB_CLIENT_IS_STRICT :
 754                NIG_REG_P0_TX_ARB_CLIENT_IS_STRICT, nig_cli_sp_bitmap);
 755
 756         REG_WR(bp, (port) ? PBF_REG_ETS_ARB_CLIENT_IS_STRICT_P1 :
 757                PBF_REG_ETS_ARB_CLIENT_IS_STRICT_P0 , pbf_cli_sp_bitmap);
 758
 759         REG_WR(bp, (port) ? NIG_REG_P1_TX_ARB_CLIENT_IS_SUBJECT2WFQ :
 760                NIG_REG_P0_TX_ARB_CLIENT_IS_SUBJECT2WFQ,
 761                nig_cli_subject2wfq_bitmap);
 762
 763         REG_WR(bp, (port) ? PBF_REG_ETS_ARB_CLIENT_IS_SUBJECT2WFQ_P1 :
 764                PBF_REG_ETS_ARB_CLIENT_IS_SUBJECT2WFQ_P0,
 765                pbf_cli_subject2wfq_bitmap);
 766
 767         return 0;
 768 }
 769
 770 /******************************************************************************
 771 * Description:
 772 *       This function is needed because NIG ARB_CREDIT_WEIGHT_X are
 773 *       not continues and ARB_CREDIT_WEIGHT_0 + offset is suitable.
 774 ******************************************************************************/
 775 static int bnx2x_ets_e3b0_set_cos_bw(struct bnx2x *bp,
 776                                      const u8 cos_entry,
 777                                      const u32 min_w_val_nig,
 778                                      const u32 min_w_val_pbf,
 779                                      const u16 total_bw,
 780                                      const u8 bw,
 781                                      const u8 port)
 782 {
 783         u32 nig_reg_adress_crd_weight = 0;
 784         u32 pbf_reg_adress_crd_weight = 0;
 785         /* Calculate and set BW for this COS - use 1 instead of 0 for BW */
 786         const u32 cos_bw_nig = ((bw ? bw : 1) * min_w_val_nig) / total_bw;
 787         const u32 cos_bw_pbf = ((bw ? bw : 1) * min_w_val_pbf) / total_bw;
 788
 789         switch (cos_entry) {
 790         case 0:
 791             nig_reg_adress_crd_weight =
 792                  (port) ? NIG_REG_P1_TX_ARB_CREDIT_WEIGHT_0 :
 793                      NIG_REG_P0_TX_ARB_CREDIT_WEIGHT_0;
 794              pbf_reg_adress_crd_weight = (port) ?
 795                  PBF_REG_COS0_WEIGHT_P1 : PBF_REG_COS0_WEIGHT_P0;
 796              break;
 797         case 1:
 798              nig_reg_adress_crd_weight = (port) ?
 799                  NIG_REG_P1_TX_ARB_CREDIT_WEIGHT_1 :
 800                  NIG_REG_P0_TX_ARB_CREDIT_WEIGHT_1;
 801              pbf_reg_adress_crd_weight = (port) ?
 802                  PBF_REG_COS1_WEIGHT_P1 : PBF_REG_COS1_WEIGHT_P0;
 803              break;
 804         case 2:
 805              nig_reg_adress_crd_weight = (port) ?
 806                  NIG_REG_P1_TX_ARB_CREDIT_WEIGHT_2 :
 807                  NIG_REG_P0_TX_ARB_CREDIT_WEIGHT_2;
 808
 809                  pbf_reg_adress_crd_weight = (port) ?
 810                      PBF_REG_COS2_WEIGHT_P1 : PBF_REG_COS2_WEIGHT_P0;
 811              break;
 812         case 3:
 813             if (port)
 814                         return -EINVAL;
 815              nig_reg_adress_crd_weight =
 816                  NIG_REG_P0_TX_ARB_CREDIT_WEIGHT_3;
 817              pbf_reg_adress_crd_weight =
 818                  PBF_REG_COS3_WEIGHT_P0;
 819              break;
 820         case 4:
 821             if (port)
 822                 return -EINVAL;
 823              nig_reg_adress_crd_weight =
 824                  NIG_REG_P0_TX_ARB_CREDIT_WEIGHT_4;
 825              pbf_reg_adress_crd_weight = PBF_REG_COS4_WEIGHT_P0;
 826              break;
 827         case 5:
 828             if (port)
 829                 return -EINVAL;
 830              nig_reg_adress_crd_weight =
 831                  NIG_REG_P0_TX_ARB_CREDIT_WEIGHT_5;
 832              pbf_reg_adress_crd_weight = PBF_REG_COS5_WEIGHT_P0;
 833              break;
 834         }
 835
 836         REG_WR(bp, nig_reg_adress_crd_weight, cos_bw_nig);
 837
 838         REG_WR(bp, pbf_reg_adress_crd_weight, cos_bw_pbf);
 839
 840         return 0;
 841 }
 842 /******************************************************************************
 843 * Description:
 844 *       Calculate the total BW.A value of 0 isn't legal.
 845 *.
 846 ******************************************************************************/
 847 static int bnx2x_ets_e3b0_get_total_bw(
 848         const struct link_params *params,
 849         const struct bnx2x_ets_params *ets_params,
 850         u16 *total_bw)
 851 {
 852         struct bnx2x *bp = params->bp;
 853         u8 cos_idx = 0;
 854
 855         *total_bw = 0 ;
 856         /* Calculate total BW requested */
 857         for (cos_idx = 0; cos_idx < ets_params->num_of_cos; cos_idx++) {
 858                 if (bnx2x_cos_state_bw == ets_params->cos[cos_idx].state) {
 859                         *total_bw +=
 860                                 ets_params->cos[cos_idx].params.bw_params.bw;
 861                 }
 862         }
 863
 864         /* Check total BW is valid */
 865         if ((100 != *total_bw) || (0 == *total_bw)) {
 866                 if (0 == *total_bw) {
 867                         DP(NETIF_MSG_LINK,
 868                            "bnx2x_ets_E3B0_config toatl BW shouldn't be 0\n");
 869                         return -EINVAL;
 870                 }
 871                 DP(NETIF_MSG_LINK,
 872                    "bnx2x_ets_E3B0_config toatl BW should be 100\n");
 873                 /**
 874                 *   We can handle a case whre the BW isn't 100 this can happen
 875                 *   if the TC are joined.
 876                 */
 877         }
 878         return 0;
 879 }
 880
 881 /******************************************************************************
 882 * Description:
 883 *       Invalidate all the sp_pri_to_cos.
 884 *.
 885 ******************************************************************************/
 886 static void bnx2x_ets_e3b0_sp_pri_to_cos_init(u8 *sp_pri_to_cos)
 887 {
 888         u8 pri = 0;
 889         for (pri = 0; pri < DCBX_MAX_NUM_COS; pri++)
 890                 sp_pri_to_cos[pri] = DCBX_INVALID_COS;
 891 }
 892 /******************************************************************************
 893 * Description:
 894 *       Calculate and set the SP (ARB_PRIORITY_CLIENT) NIG and PBF registers
 895 *       according to sp_pri_to_cos.
 896 *.
 897 ******************************************************************************/
 898 static int bnx2x_ets_e3b0_sp_pri_to_cos_set(const struct link_params *params,
 899                                             u8 *sp_pri_to_cos, const u8 pri,
 900                                             const u8 cos_entry)
 901 {
 902         struct bnx2x *bp = params->bp;
 903         const u8 port = params->port;
 904         const u8 max_num_of_cos = (port) ? DCBX_E3B0_MAX_NUM_COS_PORT1 :
 905                 DCBX_E3B0_MAX_NUM_COS_PORT0;
 906
 907         if (DCBX_INVALID_COS != sp_pri_to_cos[pri]) {
 908                 DP(NETIF_MSG_LINK, "bnx2x_ets_e3b0_sp_pri_to_cos_set invalid "
 909                                    "parameter There can't be two COS's with "
 910                                    "the same strict pri\n");
 911                 return -EINVAL;
 912         }
 913
 914         if (pri > max_num_of_cos) {
 915                 DP(NETIF_MSG_LINK, "bnx2x_ets_e3b0_sp_pri_to_cos_set invalid "
 916                                "parameter Illegal strict priority\n");
 917             return -EINVAL;
 918         }
 919
 920         sp_pri_to_cos[pri] = cos_entry;
 921         return 0;
 922
 923 }
 924
 925 /******************************************************************************
 926 * Description:
 927 *       Returns the correct value according to COS and priority in
 928 *       the sp_pri_cli register.
 929 *.
 930 ******************************************************************************/
 931 static u64 bnx2x_e3b0_sp_get_pri_cli_reg(const u8 cos, const u8 cos_offset,
 932                                          const u8 pri_set,
 933                                          const u8 pri_offset,
 934                                          const u8 entry_size)
 935 {
 936         u64 pri_cli_nig = 0;
 937         pri_cli_nig = ((u64)(cos + cos_offset)) << (entry_size *
 938                                                     (pri_set + pri_offset));
 939
 940         return pri_cli_nig;
 941 }
 942 /******************************************************************************
 943 * Description:
 944 *       Returns the correct value according to COS and priority in the
 945 *       sp_pri_cli register for NIG.
 946 *.
 947 ******************************************************************************/
 948 static u64 bnx2x_e3b0_sp_get_pri_cli_reg_nig(const u8 cos, const u8 pri_set)
 949 {
 950         /* MCP Dbg0 and dbg1 are always with higher strict pri*/
 951         const u8 nig_cos_offset = 3;
 952         const u8 nig_pri_offset = 3;
 953
 954         return bnx2x_e3b0_sp_get_pri_cli_reg(cos, nig_cos_offset, pri_set,
 955                 nig_pri_offset, 4);
 956
 957 }
 958 /******************************************************************************
 959 * Description:
 960 *       Returns the correct value according to COS and priority in the
 961 *       sp_pri_cli register for PBF.
 962 *.
 963 ******************************************************************************/
 964 static u64 bnx2x_e3b0_sp_get_pri_cli_reg_pbf(const u8 cos, const u8 pri_set)
 965 {
 966         const u8 pbf_cos_offset = 0;
 967         const u8 pbf_pri_offset = 0;
 968
 969         return bnx2x_e3b0_sp_get_pri_cli_reg(cos, pbf_cos_offset, pri_set,
 970                 pbf_pri_offset, 3);
 971
 972 }
 973
 974 /******************************************************************************
 975 * Description:
 976 *       Calculate and set the SP (ARB_PRIORITY_CLIENT) NIG and PBF registers
 977 *       according to sp_pri_to_cos.(which COS has higher priority)
 978 *.
 979 ******************************************************************************/
 980 static int bnx2x_ets_e3b0_sp_set_pri_cli_reg(const struct link_params *params,
 981                                              u8 *sp_pri_to_cos)
 982 {
 983         struct bnx2x *bp = params->bp;
 984         u8 i = 0;
 985         const u8 port = params->port;
 986         /* MCP Dbg0 and dbg1 are always with higher strict pri*/
 987         u64 pri_cli_nig = 0x210;
 988         u32 pri_cli_pbf = 0x0;
 989         u8 pri_set = 0;
 990         u8 pri_bitmask = 0;
 991         const u8 max_num_of_cos = (port) ? DCBX_E3B0_MAX_NUM_COS_PORT1 :
 992                 DCBX_E3B0_MAX_NUM_COS_PORT0;
 993
 994         u8 cos_bit_to_set = (1 << max_num_of_cos) - 1;
 995
 996         /* Set all the strict priority first */
 997         for (i = 0; i < max_num_of_cos; i++) {
 998                 if (DCBX_INVALID_COS != sp_pri_to_cos[i]) {
 999                         if (DCBX_MAX_NUM_COS <= sp_pri_to_cos[i]) {
1000                                 DP(NETIF_MSG_LINK,
1001                                            "bnx2x_ets_e3b0_sp_set_pri_cli_reg "
1002                                            "invalid cos entry\n");
1003                                 return -EINVAL;
1004                         }
1005
1006                         pri_cli_nig |= bnx2x_e3b0_sp_get_pri_cli_reg_nig(
1007                             sp_pri_to_cos[i], pri_set);
1008
1009                         pri_cli_pbf |= bnx2x_e3b0_sp_get_pri_cli_reg_pbf(
1010                             sp_pri_to_cos[i], pri_set);
1011                         pri_bitmask = 1 << sp_pri_to_cos[i];
1012                         /* COS is used remove it from bitmap.*/
1013                         if (0 == (pri_bitmask & cos_bit_to_set)) {
1014                                 DP(NETIF_MSG_LINK,
1015                                         "bnx2x_ets_e3b0_sp_set_pri_cli_reg "
1016                                         "invalid There can't be two COS's with"
1017                                         " the same strict pri\n");
1018                                 return -EINVAL;
1019                         }
1020                         cos_bit_to_set &= ~pri_bitmask;
1021                         pri_set++;
1022                 }
1023         }
1024
1025         /* Set all the Non strict priority i= COS*/
1026         for (i = 0; i < max_num_of_cos; i++) {
1027                 pri_bitmask = 1 << i;
1028                 /* Check if COS was already used for SP */
1029                 if (pri_bitmask & cos_bit_to_set) {
1030                         /* COS wasn't used for SP */
1031                         pri_cli_nig |= bnx2x_e3b0_sp_get_pri_cli_reg_nig(
1032                             i, pri_set);
1033
1034                         pri_cli_pbf |= bnx2x_e3b0_sp_get_pri_cli_reg_pbf(
1035                             i, pri_set);
1036                         /* COS is used remove it from bitmap.*/
1037                         cos_bit_to_set &= ~pri_bitmask;
1038                         pri_set++;
1039                 }
1040         }
1041
1042         if (pri_set != max_num_of_cos) {
1043                 DP(NETIF_MSG_LINK, "bnx2x_ets_e3b0_sp_set_pri_cli_reg not all "
1044                                    "entries were set\n");
1045                 return -EINVAL;
1046         }
1047
1048         if (port) {
1049                 /* Only 6 usable clients*/
1050                 REG_WR(bp, NIG_REG_P1_TX_ARB_PRIORITY_CLIENT2_LSB,
1051                        (u32)pri_cli_nig);
1052
1053                 REG_WR(bp, PBF_REG_ETS_ARB_PRIORITY_CLIENT_P1 , pri_cli_pbf);
1054         } else {
1055                 /* Only 9 usable clients*/
1056                 const u32 pri_cli_nig_lsb = (u32) (pri_cli_nig);
1057                 const u32 pri_cli_nig_msb = (u32) ((pri_cli_nig >> 32) & 0xF);
1058
1059                 REG_WR(bp, NIG_REG_P0_TX_ARB_PRIORITY_CLIENT2_LSB,
1060                        pri_cli_nig_lsb);
1061                 REG_WR(bp, NIG_REG_P0_TX_ARB_PRIORITY_CLIENT2_MSB,
1062                        pri_cli_nig_msb);
1063
1064                 REG_WR(bp, PBF_REG_ETS_ARB_PRIORITY_CLIENT_P0 , pri_cli_pbf);
1065         }
1066         return 0;
1067 }
1068
1069 /******************************************************************************
1070 * Description:
1071 *       Configure the COS to ETS according to BW and SP settings.
1072 ******************************************************************************/
1073 int bnx2x_ets_e3b0_config(const struct link_params *params,
1074                          const struct link_vars *vars,
1075                          const struct bnx2x_ets_params *ets_params)
1076 {
1077         struct bnx2x *bp = params->bp;
1078         int bnx2x_status = 0;
1079         const u8 port = params->port;
1080         u16 total_bw = 0;
1081         const u32 min_w_val_nig = bnx2x_ets_get_min_w_val_nig(vars);
1082         const u32 min_w_val_pbf = ETS_E3B0_PBF_MIN_W_VAL;
1083         u8 cos_bw_bitmap = 0;
1084         u8 cos_sp_bitmap = 0;
1085         u8 sp_pri_to_cos[DCBX_MAX_NUM_COS] = {0};
1086         const u8 max_num_of_cos = (port) ? DCBX_E3B0_MAX_NUM_COS_PORT1 :
1087                 DCBX_E3B0_MAX_NUM_COS_PORT0;
1088         u8 cos_entry = 0;
1089
1090         if (!CHIP_IS_E3B0(bp)) {
1091                 DP(NETIF_MSG_LINK,
1092                    "bnx2x_ets_e3b0_disabled the chip isn't E3B0\n");
1093                 return -EINVAL;
1094         }
1095
1096         if ((ets_params->num_of_cos > max_num_of_cos)) {
1097                 DP(NETIF_MSG_LINK, "bnx2x_ets_E3B0_config the number of COS "
1098                                    "isn't supported\n");
1099                 return -EINVAL;
1100         }
1101
1102         /* Prepare sp strict priority parameters*/
1103         bnx2x_ets_e3b0_sp_pri_to_cos_init(sp_pri_to_cos);
1104
1105         /* Prepare BW parameters*/
1106         bnx2x_status = bnx2x_ets_e3b0_get_total_bw(params, ets_params,
1107                                                    &total_bw);
1108         if (0 != bnx2x_status) {
1109                 DP(NETIF_MSG_LINK,
1110                    "bnx2x_ets_E3B0_config get_total_bw failed\n");
1111                 return -EINVAL;
1112         }
1113
1114         /**
1115          *  Upper bound is set according to current link speed (min_w_val
1116          *  should be the same for upper bound and COS credit val).
1117          */
1118         bnx2x_ets_e3b0_set_credit_upper_bound_nig(params, min_w_val_nig);
1119         bnx2x_ets_e3b0_set_credit_upper_bound_pbf(params, min_w_val_pbf);
1120
1121
1122         for (cos_entry = 0; cos_entry < ets_params->num_of_cos; cos_entry++) {
1123                 if (bnx2x_cos_state_bw == ets_params->cos[cos_entry].state) {
1124                         cos_bw_bitmap |= (1 << cos_entry);
1125                         /**
1126                          * The function also sets the BW in HW(not the mappin
1127                          * yet)
1128                          */
1129                         bnx2x_status = bnx2x_ets_e3b0_set_cos_bw(
1130                                 bp, cos_entry, min_w_val_nig, min_w_val_pbf,
1131                                 total_bw,
1132                                 ets_params->cos[cos_entry].params.bw_params.bw,
1133                                  port);
1134                 } else if (bnx2x_cos_state_strict ==
1135                         ets_params->cos[cos_entry].state){
1136                         cos_sp_bitmap |= (1 << cos_entry);
1137
1138                         bnx2x_status = bnx2x_ets_e3b0_sp_pri_to_cos_set(
1139                                 params,
1140                                 sp_pri_to_cos,
1141                                 ets_params->cos[cos_entry].params.sp_params.pri,
1142                                 cos_entry);
1143
1144                 } else {
1145                         DP(NETIF_MSG_LINK,
1146                            "bnx2x_ets_e3b0_config cos state not valid\n");
1147                         return -EINVAL;
1148                 }
1149                 if (0 != bnx2x_status) {
1150                         DP(NETIF_MSG_LINK,
1151                            "bnx2x_ets_e3b0_config set cos bw failed\n");
1152                         return bnx2x_status;
1153                 }
1154         }
1155
1156         /* Set SP register (which COS has higher priority) */
1157         bnx2x_status = bnx2x_ets_e3b0_sp_set_pri_cli_reg(params,
1158                                                          sp_pri_to_cos);
1159
1160         if (0 != bnx2x_status) {
1161                 DP(NETIF_MSG_LINK,
1162                    "bnx2x_ets_E3B0_config set_pri_cli_reg failed\n");
1163                 return bnx2x_status;
1164         }
1165
1166         /* Set client mapping of BW and strict */
1167         bnx2x_status = bnx2x_ets_e3b0_cli_map(params, ets_params,
1168                                               cos_sp_bitmap,
1169                                               cos_bw_bitmap);
1170
1171         if (0 != bnx2x_status) {
1172                 DP(NETIF_MSG_LINK, "bnx2x_ets_E3B0_config SP failed\n");
1173                 return bnx2x_status;
1174         }
1175         return 0;
1176 }
1177 static void bnx2x_ets_bw_limit_common(const struct link_params *params)
1178 {
1179         /* ETS disabled configuration */
1180         struct bnx2x *bp = params->bp;
1181         DP(NETIF_MSG_LINK, "ETS enabled BW limit configuration\n");
1182         /*
1183          * defines which entries (clients) are subjected to WFQ arbitration
1184          * COS0 0x8
1185          * COS1 0x10
1186          */
1187         REG_WR(bp, NIG_REG_P0_TX_ARB_CLIENT_IS_SUBJECT2WFQ, 0x18);
1188         /*
1189          * mapping between the ARB_CREDIT_WEIGHT registers and actual
1190          * client numbers (WEIGHT_0 does not actually have to represent
1191          * client 0)
1192          *    PRI4    |    PRI3    |    PRI2    |    PRI1    |    PRI0
1193          *  cos1-001     cos0-000     dbg1-100     dbg0-011     MCP-010
1194          */
1195         REG_WR(bp, NIG_REG_P0_TX_ARB_CLIENT_CREDIT_MAP, 0x111A);
1196
1197         REG_WR(bp, NIG_REG_P0_TX_ARB_CREDIT_UPPER_BOUND_0,
1198                ETS_BW_LIMIT_CREDIT_UPPER_BOUND);
1199         REG_WR(bp, NIG_REG_P0_TX_ARB_CREDIT_UPPER_BOUND_1,
1200                ETS_BW_LIMIT_CREDIT_UPPER_BOUND);
1201
1202         /* ETS mode enabled*/
1203         REG_WR(bp, PBF_REG_ETS_ENABLED, 1);
1204
1205         /* Defines the number of consecutive slots for the strict priority */
1206         REG_WR(bp, PBF_REG_NUM_STRICT_ARB_SLOTS, 0);
1207         /*
1208          * Bitmap of 5bits length. Each bit specifies whether the entry behaves
1209          * as strict.  Bits 0,1,2 - debug and management entries, 3 - COS0
1210          * entry, 4 - COS1 entry.
1211          * COS1 | COS0 | DEBUG21 | DEBUG0 | MGMT
1212          * bit4   bit3    bit2     bit1    bit0
1213          * MCP and debug are strict
1214          */
1215         REG_WR(bp, NIG_REG_P0_TX_ARB_CLIENT_IS_STRICT, 0x7);
1216
1217         /* Upper bound that COS0_WEIGHT can reach in the WFQ arbiter.*/
1218         REG_WR(bp, PBF_REG_COS0_UPPER_BOUND,
1219                ETS_BW_LIMIT_CREDIT_UPPER_BOUND);
1220         REG_WR(bp, PBF_REG_COS1_UPPER_BOUND,
1221                ETS_BW_LIMIT_CREDIT_UPPER_BOUND);
1222 }
1223
1224 void bnx2x_ets_bw_limit(const struct link_params *params, const u32 cos0_bw,
1225                         const u32 cos1_bw)
1226 {
1227         /* ETS disabled configuration*/
1228         struct bnx2x *bp = params->bp;
1229         const u32 total_bw = cos0_bw + cos1_bw;
1230         u32 cos0_credit_weight = 0;
1231         u32 cos1_credit_weight = 0;
1232
1233         DP(NETIF_MSG_LINK, "ETS enabled BW limit configuration\n");
1234
1235         if ((0 == total_bw) ||
1236             (0 == cos0_bw) ||
1237             (0 == cos1_bw)) {
1238                 DP(NETIF_MSG_LINK, "Total BW can't be zero\n");
1239                 return;
1240         }
1241
1242         cos0_credit_weight = (cos0_bw * ETS_BW_LIMIT_CREDIT_WEIGHT)/
1243                 total_bw;
1244         cos1_credit_weight = (cos1_bw * ETS_BW_LIMIT_CREDIT_WEIGHT)/
1245                 total_bw;
1246
1247         bnx2x_ets_bw_limit_common(params);
1248
1249         REG_WR(bp, NIG_REG_P0_TX_ARB_CREDIT_WEIGHT_0, cos0_credit_weight);
1250         REG_WR(bp, NIG_REG_P0_TX_ARB_CREDIT_WEIGHT_1, cos1_credit_weight);
1251
1252         REG_WR(bp, PBF_REG_COS0_WEIGHT, cos0_credit_weight);
1253         REG_WR(bp, PBF_REG_COS1_WEIGHT, cos1_credit_weight);
1254 }
1255
1256 int bnx2x_ets_strict(const struct link_params *params, const u8 strict_cos)
1257 {
1258         /* ETS disabled configuration*/
1259         struct bnx2x *bp = params->bp;
1260         u32 val = 0;
1261
1262         DP(NETIF_MSG_LINK, "ETS enabled strict configuration\n");
1263         /*
1264          * Bitmap of 5bits length. Each bit specifies whether the entry behaves
1265          * as strict.  Bits 0,1,2 - debug and management entries,
1266          * 3 - COS0 entry, 4 - COS1 entry.
1267          *  COS1 | COS0 | DEBUG21 | DEBUG0 | MGMT
1268          *  bit4   bit3   bit2      bit1     bit0
1269          * MCP and debug are strict
1270          */
1271         REG_WR(bp, NIG_REG_P0_TX_ARB_CLIENT_IS_STRICT, 0x1F);
1272         /*
1273          * For strict priority entries defines the number of consecutive slots
1274          * for the highest priority.
1275          */
1276         REG_WR(bp, NIG_REG_P0_TX_ARB_NUM_STRICT_ARB_SLOTS, 0x100);
1277         /* ETS mode disable */
1278         REG_WR(bp, PBF_REG_ETS_ENABLED, 0);
1279         /* Defines the number of consecutive slots for the strict priority */
1280         REG_WR(bp, PBF_REG_NUM_STRICT_ARB_SLOTS, 0x100);
1281
1282         /* Defines the number of consecutive slots for the strict priority */
1283         REG_WR(bp, PBF_REG_HIGH_PRIORITY_COS_NUM, strict_cos);
1284
1285         /*
1286          * mapping between entry  priority to client number (0,1,2 -debug and
1287          * management clients, 3 - COS0 client, 4 - COS client)(HIGHEST)
1288          * 3bits client num.
1289          *   PRI4    |    PRI3    |    PRI2    |    PRI1    |    PRI0
1290          * dbg0-010     dbg1-001     cos1-100     cos0-011     MCP-000
1291          * dbg0-010     dbg1-001     cos0-011     cos1-100     MCP-000
1292          */
1293         val = (0 == strict_cos) ? 0x2318 : 0x22E0;
1294         REG_WR(bp, NIG_REG_P0_TX_ARB_PRIORITY_CLIENT, val);
1295
1296         return 0;
1297 }
1298 /******************************************************************/
1299 /*                      PFC section                               */
1300 /******************************************************************/
1301
1302 static void bnx2x_update_pfc_xmac(struct link_params *params,
1303                                   struct link_vars *vars,
1304                                   u8 is_lb)
1305 {
1306         struct bnx2x *bp = params->bp;
1307         u32 xmac_base;
1308         u32 pause_val, pfc0_val, pfc1_val;
1309
1310         /* XMAC base adrr */
1311         xmac_base = (params->port) ? GRCBASE_XMAC1 : GRCBASE_XMAC0;
1312
1313         /* Initialize pause and pfc registers */
1314         pause_val = 0x18000;
1315         pfc0_val = 0xFFFF8000;
1316         pfc1_val = 0x2;
1317
1318         /* No PFC support */
1319         if (!(params->feature_config_flags &
1320               FEATURE_CONFIG_PFC_ENABLED)) {
1321
1322                 /*
1323                  * RX flow control - Process pause frame in receive direction
1324                  */
1325                 if (vars->flow_ctrl & BNX2X_FLOW_CTRL_RX)
1326                         pause_val |= XMAC_PAUSE_CTRL_REG_RX_PAUSE_EN;
1327
1328                 /*
1329                  * TX flow control - Send pause packet when buffer is full
1330                  */
1331                 if (vars->flow_ctrl & BNX2X_FLOW_CTRL_TX)
1332                         pause_val |= XMAC_PAUSE_CTRL_REG_TX_PAUSE_EN;
1333         } else {/* PFC support */
1334                 pfc1_val |= XMAC_PFC_CTRL_HI_REG_PFC_REFRESH_EN |
1335                         XMAC_PFC_CTRL_HI_REG_PFC_STATS_EN |
1336                         XMAC_PFC_CTRL_HI_REG_RX_PFC_EN |
1337                         XMAC_PFC_CTRL_HI_REG_TX_PFC_EN;
1338         }
1339
1340         /* Write pause and PFC registers */
1341         REG_WR(bp, xmac_base + XMAC_REG_PAUSE_CTRL, pause_val);
1342         REG_WR(bp, xmac_base + XMAC_REG_PFC_CTRL, pfc0_val);
1343         REG_WR(bp, xmac_base + XMAC_REG_PFC_CTRL_HI, pfc1_val);
1344
1345
1346         /* Set MAC address for source TX Pause/PFC frames */
1347         REG_WR(bp, xmac_base + XMAC_REG_CTRL_SA_LO,
1348                ((params->mac_addr[2] << 24) |
1349                 (params->mac_addr[3] << 16) |
1350                 (params->mac_addr[4] << 8) |
1351                 (params->mac_addr[5])));
1352         REG_WR(bp, xmac_base + XMAC_REG_CTRL_SA_HI,
1353                ((params->mac_addr[0] << 8) |
1354                 (params->mac_addr[1])));
1355
1356         udelay(30);
1357 }
1358
1359
1360 static void bnx2x_emac_get_pfc_stat(struct link_params *params,
1361                                     u32 pfc_frames_sent[2],
1362                                     u32 pfc_frames_received[2])
1363 {
1364         /* Read pfc statistic */
1365         struct bnx2x *bp = params->bp;
1366         u32 emac_base = params->port ? GRCBASE_EMAC1 : GRCBASE_EMAC0;
1367         u32 val_xon = 0;
1368         u32 val_xoff = 0;
1369
1370         DP(NETIF_MSG_LINK, "pfc statistic read from EMAC\n");
1371
1372         /* PFC received frames */
1373         val_xoff = REG_RD(bp, emac_base +
1374                                 EMAC_REG_RX_PFC_STATS_XOFF_RCVD);
1375         val_xoff &= EMAC_REG_RX_PFC_STATS_XOFF_RCVD_COUNT;
1376         val_xon = REG_RD(bp, emac_base + EMAC_REG_RX_PFC_STATS_XON_RCVD);
1377         val_xon &= EMAC_REG_RX_PFC_STATS_XON_RCVD_COUNT;
1378
1379         pfc_frames_received[0] = val_xon + val_xoff;
1380
1381         /* PFC received sent */
1382         val_xoff = REG_RD(bp, emac_base +
1383                                 EMAC_REG_RX_PFC_STATS_XOFF_SENT);
1384         val_xoff &= EMAC_REG_RX_PFC_STATS_XOFF_SENT_COUNT;
1385         val_xon = REG_RD(bp, emac_base + EMAC_REG_RX_PFC_STATS_XON_SENT);
1386         val_xon &= EMAC_REG_RX_PFC_STATS_XON_SENT_COUNT;
1387
1388         pfc_frames_sent[0] = val_xon + val_xoff;
1389 }
1390
1391 /* Read pfc statistic*/
1392 void bnx2x_pfc_statistic(struct link_params *params, struct link_vars *vars,
1393                          u32 pfc_frames_sent[2],
1394                          u32 pfc_frames_received[2])
1395 {
1396         /* Read pfc statistic */
1397         struct bnx2x *bp = params->bp;
1398
1399         DP(NETIF_MSG_LINK, "pfc statistic\n");
1400
1401         if (!vars->link_up)
1402                 return;
1403
1404         if (MAC_TYPE_EMAC == vars->mac_type) {
1405                 DP(NETIF_MSG_LINK, "About to read PFC stats from EMAC\n");
1406                 bnx2x_emac_get_pfc_stat(params, pfc_frames_sent,
1407                                         pfc_frames_received);
1408         }
1409 }
1410 /******************************************************************/
1411 /*                      MAC/PBF section                           */
1412 /******************************************************************/
1413 static void bnx2x_set_mdio_clk(struct bnx2x *bp, u32 chip_id, u8 port)
1414 {
1415         u32 mode, emac_base;
1416         /**
1417          * Set clause 45 mode, slow down the MDIO clock to 2.5MHz
1418          * (a value of 49==0x31) and make sure that the AUTO poll is off
1419          */
1420
1421         if (CHIP_IS_E2(bp))
1422                 emac_base = GRCBASE_EMAC0;
1423         else
1424                 emac_base = (port) ? GRCBASE_EMAC1 : GRCBASE_EMAC0;
1425         mode = REG_RD(bp, emac_base + EMAC_REG_EMAC_MDIO_MODE);
1426         mode &= ~(EMAC_MDIO_MODE_AUTO_POLL |
1427                   EMAC_MDIO_MODE_CLOCK_CNT);
1428         if (USES_WARPCORE(bp))
1429                 mode |= (74L << EMAC_MDIO_MODE_CLOCK_CNT_BITSHIFT);
1430         else
1431                 mode |= (49L << EMAC_MDIO_MODE_CLOCK_CNT_BITSHIFT);
1432
1433         mode |= (EMAC_MDIO_MODE_CLAUSE_45);
1434         REG_WR(bp, emac_base + EMAC_REG_EMAC_MDIO_MODE, mode);
1435
1436         udelay(40);
1437 }
1438
1439 static void bnx2x_emac_init(struct link_params *params,
1440                             struct link_vars *vars)
1441 {
1442         /* reset and unreset the emac core */
1443         struct bnx2x *bp = params->bp;
1444         u8 port = params->port;
1445         u32 emac_base = port ? GRCBASE_EMAC1 : GRCBASE_EMAC0;
1446         u32 val;
1447         u16 timeout;
1448
1449         REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_2_CLEAR,
1450                (MISC_REGISTERS_RESET_REG_2_RST_EMAC0_HARD_CORE << port));
1451         udelay(5);
1452         REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_2_SET,
1453                (MISC_REGISTERS_RESET_REG_2_RST_EMAC0_HARD_CORE << port));
1454
1455         /* init emac - use read-modify-write */
1456         /* self clear reset */
1457         val = REG_RD(bp, emac_base + EMAC_REG_EMAC_MODE);
1458         EMAC_WR(bp, EMAC_REG_EMAC_MODE, (val | EMAC_MODE_RESET));
1459
1460         timeout = 200;
1461         do {
1462                 val = REG_RD(bp, emac_base + EMAC_REG_EMAC_MODE);
1463                 DP(NETIF_MSG_LINK, "EMAC reset reg is %u\n", val);
1464                 if (!timeout) {
1465                         DP(NETIF_MSG_LINK, "EMAC timeout!\n");
1466                         return;
1467                 }
1468                 timeout--;
1469         } while (val & EMAC_MODE_RESET);
1470         bnx2x_set_mdio_clk(bp, params->chip_id, port);
1471         /* Set mac address */
1472         val = ((params->mac_addr[0] << 8) |
1473                 params->mac_addr[1]);
1474         EMAC_WR(bp, EMAC_REG_EMAC_MAC_MATCH, val);
1475
1476         val = ((params->mac_addr[2] << 24) |
1477                (params->mac_addr[3] << 16) |
1478                (params->mac_addr[4] << 8) |
1479                 params->mac_addr[5]);
1480         EMAC_WR(bp, EMAC_REG_EMAC_MAC_MATCH + 4, val);
1481 }
1482
1483 static void bnx2x_set_xumac_nig(struct link_params *params,
1484                                 u16 tx_pause_en,
1485                                 u8 enable)
1486 {
1487         struct bnx2x *bp = params->bp;
1488
1489         REG_WR(bp, params->port ? NIG_REG_P1_MAC_IN_EN : NIG_REG_P0_MAC_IN_EN,
1490                enable);
1491         REG_WR(bp, params->port ? NIG_REG_P1_MAC_OUT_EN : NIG_REG_P0_MAC_OUT_EN,
1492                enable);
1493         REG_WR(bp, params->port ? NIG_REG_P1_MAC_PAUSE_OUT_EN :
1494                NIG_REG_P0_MAC_PAUSE_OUT_EN, tx_pause_en);
1495 }
1496
1497 static void bnx2x_umac_disable(struct link_params *params)
1498 {
1499         u32 umac_base = params->port ? GRCBASE_UMAC1 : GRCBASE_UMAC0;
1500         struct bnx2x *bp = params->bp;
1501         if (!(REG_RD(bp, MISC_REG_RESET_REG_2) &
1502                    (MISC_REGISTERS_RESET_REG_2_UMAC0 << params->port)))
1503                 return;
1504
1505         /* Disable RX and TX */
1506         REG_WR(bp, umac_base + UMAC_REG_COMMAND_CONFIG, 0);
1507 }
1508
1509 static void bnx2x_umac_enable(struct link_params *params,
1510                             struct link_vars *vars, u8 lb)
1511 {
1512         u32 val;
1513         u32 umac_base = params->port ? GRCBASE_UMAC1 : GRCBASE_UMAC0;
1514         struct bnx2x *bp = params->bp;
1515         /* Reset UMAC */
1516         REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_2_CLEAR,
1517                (MISC_REGISTERS_RESET_REG_2_UMAC0 << params->port));
1518         usleep_range(1000, 1000);
1519
1520         REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_2_SET,
1521                (MISC_REGISTERS_RESET_REG_2_UMAC0 << params->port));
1522
1523         DP(NETIF_MSG_LINK, "enabling UMAC\n");
1524
1525         /**
1526          * This register determines on which events the MAC will assert
1527          * error on the i/f to the NIG along w/ EOP.
1528          */
1529
1530         /**
1531          * BD REG_WR(bp, NIG_REG_P0_MAC_RSV_ERR_MASK +
1532          * params->port*0x14,      0xfffff.
1533          */
1534         /* This register opens the gate for the UMAC despite its name */
1535         REG_WR(bp, NIG_REG_EGRESS_EMAC0_PORT + params->port*4, 1);
1536
1537         val = UMAC_COMMAND_CONFIG_REG_PROMIS_EN |
1538                 UMAC_COMMAND_CONFIG_REG_PAD_EN |
1539                 UMAC_COMMAND_CONFIG_REG_SW_RESET |
1540                 UMAC_COMMAND_CONFIG_REG_NO_LGTH_CHECK;
1541         switch (vars->line_speed) {
1542         case SPEED_10:
1543                 val |= (0<<2);
1544                 break;
1545         case SPEED_100:
1546                 val |= (1<<2);
1547                 break;
1548         case SPEED_1000:
1549                 val |= (2<<2);
1550                 break;
1551         case SPEED_2500:
1552                 val |= (3<<2);
1553                 break;
1554         default:
1555                 DP(NETIF_MSG_LINK, "Invalid speed for UMAC %d\n",
1556                                vars->line_speed);
1557                 break;
1558         }
1559         if (!(vars->flow_ctrl & BNX2X_FLOW_CTRL_TX))
1560                 val |= UMAC_COMMAND_CONFIG_REG_IGNORE_TX_PAUSE;
1561
1562         if (!(vars->flow_ctrl & BNX2X_FLOW_CTRL_RX))
1563                 val |= UMAC_COMMAND_CONFIG_REG_PAUSE_IGNORE;
1564
1565         REG_WR(bp, umac_base + UMAC_REG_COMMAND_CONFIG, val);
1566         udelay(50);
1567
1568         /* Set MAC address for source TX Pause/PFC frames (under SW reset) */
1569         REG_WR(bp, umac_base + UMAC_REG_MAC_ADDR0,
1570                ((params->mac_addr[2] << 24) |
1571                 (params->mac_addr[3] << 16) |
1572                 (params->mac_addr[4] << 8) |
1573                 (params->mac_addr[5])));
1574         REG_WR(bp, umac_base + UMAC_REG_MAC_ADDR1,
1575                ((params->mac_addr[0] << 8) |
1576                 (params->mac_addr[1])));
1577
1578         /* Enable RX and TX */
1579         val &= ~UMAC_COMMAND_CONFIG_REG_PAD_EN;
1580         val |= UMAC_COMMAND_CONFIG_REG_TX_ENA |
1581                 UMAC_COMMAND_CONFIG_REG_RX_ENA;
1582         REG_WR(bp, umac_base + UMAC_REG_COMMAND_CONFIG, val);
1583         udelay(50);
1584
1585         /* Remove SW Reset */
1586         val &= ~UMAC_COMMAND_CONFIG_REG_SW_RESET;
1587
1588         /* Check loopback mode */
1589         if (lb)
1590                 val |= UMAC_COMMAND_CONFIG_REG_LOOP_ENA;
1591         REG_WR(bp, umac_base + UMAC_REG_COMMAND_CONFIG, val);
1592
1593         /*
1594          * Maximum Frame Length (RW). Defines a 14-Bit maximum frame
1595          * length used by the MAC receive logic to check frames.
1596          */
1597         REG_WR(bp, umac_base + UMAC_REG_MAXFR, 0x2710);
1598         bnx2x_set_xumac_nig(params,
1599                             ((vars->flow_ctrl & BNX2X_FLOW_CTRL_TX) != 0), 1);
1600         vars->mac_type = MAC_TYPE_UMAC;
1601
1602 }
1603
1604 static u8 bnx2x_is_4_port_mode(struct bnx2x *bp)
1605 {
1606         u32 port4mode_ovwr_val;
1607         /* Check 4-port override enabled */
1608         port4mode_ovwr_val = REG_RD(bp, MISC_REG_PORT4MODE_EN_OVWR);
1609         if (port4mode_ovwr_val & (1<<0)) {
1610                 /* Return 4-port mode override value */
1611                 return ((port4mode_ovwr_val & (1<<1)) == (1<<1));
1612         }
1613         /* Return 4-port mode from input pin */
1614         return (u8)REG_RD(bp, MISC_REG_PORT4MODE_EN);
1615 }
1616
1617 /* Define the XMAC mode */
1618 static void bnx2x_xmac_init(struct link_params *params, u32 max_speed)
1619 {
1620         struct bnx2x *bp = params->bp;
1621         u32 is_port4mode = bnx2x_is_4_port_mode(bp);
1622
1623         /**
1624         * In 4-port mode, need to set the mode only once, so if XMAC is
1625         * already out of reset, it means the mode has already been set,
1626         * and it must not* reset the XMAC again, since it controls both
1627         * ports of the path
1628         **/
1629
1630         if ((CHIP_NUM(bp) == CHIP_NUM_57840) &&
1631             (REG_RD(bp, MISC_REG_RESET_REG_2) &
1632              MISC_REGISTERS_RESET_REG_2_XMAC)) {
1633                 DP(NETIF_MSG_LINK,
1634                    "XMAC already out of reset in 4-port mode\n");
1635                 return;
1636         }
1637
1638         /* Hard reset */
1639         REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_2_CLEAR,
1640                MISC_REGISTERS_RESET_REG_2_XMAC);
1641         usleep_range(1000, 1000);
1642
1643         REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_2_SET,
1644                MISC_REGISTERS_RESET_REG_2_XMAC);
1645         if (is_port4mode) {
1646                 DP(NETIF_MSG_LINK, "Init XMAC to 2 ports x 10G per path\n");
1647
1648                 /*  Set the number of ports on the system side to up to 2 */
1649                 REG_WR(bp, MISC_REG_XMAC_CORE_PORT_MODE, 1);
1650
1651                 /* Set the number of ports on the Warp Core to 10G */
1652                 REG_WR(bp, MISC_REG_XMAC_PHY_PORT_MODE, 3);
1653         } else {
1654                 /*  Set the number of ports on the system side to 1 */
1655                 REG_WR(bp, MISC_REG_XMAC_CORE_PORT_MODE, 0);
1656                 if (max_speed == SPEED_10000) {
1657                         DP(NETIF_MSG_LINK,
1658                            "Init XMAC to 10G x 1 port per path\n");
1659                         /* Set the number of ports on the Warp Core to 10G */
1660                         REG_WR(bp, MISC_REG_XMAC_PHY_PORT_MODE, 3);
1661                 } else {
1662                         DP(NETIF_MSG_LINK,
1663                            "Init XMAC to 20G x 2 ports per path\n");
1664                         /* Set the number of ports on the Warp Core to 20G */
1665                         REG_WR(bp, MISC_REG_XMAC_PHY_PORT_MODE, 1);
1666                 }
1667         }
1668         /* Soft reset */
1669         REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_2_CLEAR,
1670                MISC_REGISTERS_RESET_REG_2_XMAC_SOFT);
1671         usleep_range(1000, 1000);
1672
1673         REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_2_SET,
1674                MISC_REGISTERS_RESET_REG_2_XMAC_SOFT);
1675
1676 }
1677
1678 static void bnx2x_xmac_disable(struct link_params *params)
1679 {
1680         u8 port = params->port;
1681         struct bnx2x *bp = params->bp;
1682         u32 pfc_ctrl, xmac_base = (port) ? GRCBASE_XMAC1 : GRCBASE_XMAC0;
1683
1684         if (REG_RD(bp, MISC_REG_RESET_REG_2) &
1685             MISC_REGISTERS_RESET_REG_2_XMAC) {
1686                 /*
1687                  * Send an indication to change the state in the NIG back to XON
1688                  * Clearing this bit enables the next set of this bit to get
1689                  * rising edge
1690                  */
1691                 pfc_ctrl = REG_RD(bp, xmac_base + XMAC_REG_PFC_CTRL_HI);
1692                 REG_WR(bp, xmac_base + XMAC_REG_PFC_CTRL_HI,
1693                        (pfc_ctrl & ~(1<<1)));
1694                 REG_WR(bp, xmac_base + XMAC_REG_PFC_CTRL_HI,
1695                        (pfc_ctrl | (1<<1)));
1696                 DP(NETIF_MSG_LINK, "Disable XMAC on port %x\n", port);
1697                 REG_WR(bp, xmac_base + XMAC_REG_CTRL, 0);
1698         }
1699 }
1700
1701 static int bnx2x_xmac_enable(struct link_params *params,
1702                              struct link_vars *vars, u8 lb)
1703 {
1704         u32 val, xmac_base;
1705         struct bnx2x *bp = params->bp;
1706         DP(NETIF_MSG_LINK, "enabling XMAC\n");
1707
1708         xmac_base = (params->port) ? GRCBASE_XMAC1 : GRCBASE_XMAC0;
1709
1710         bnx2x_xmac_init(params, vars->line_speed);
1711
1712         /*
1713          * This register determines on which events the MAC will assert
1714          * error on the i/f to the NIG along w/ EOP.
1715          */
1716
1717         /*
1718          * This register tells the NIG whether to send traffic to UMAC
1719          * or XMAC
1720          */
1721         REG_WR(bp, NIG_REG_EGRESS_EMAC0_PORT + params->port*4, 0);
1722
1723         /* Set Max packet size */
1724         REG_WR(bp, xmac_base + XMAC_REG_RX_MAX_SIZE, 0x2710);
1725
1726         /* CRC append for Tx packets */
1727         REG_WR(bp, xmac_base + XMAC_REG_TX_CTRL, 0xC800);
1728
1729         /* update PFC */
1730         bnx2x_update_pfc_xmac(params, vars, 0);
1731
1732         /* Enable TX and RX */
1733         val = XMAC_CTRL_REG_TX_EN | XMAC_CTRL_REG_RX_EN;
1734
1735         /* Check loopback mode */
1736         if (lb)
1737                 val |= XMAC_CTRL_REG_LINE_LOCAL_LPBK;
1738         REG_WR(bp, xmac_base + XMAC_REG_CTRL, val);
1739         bnx2x_set_xumac_nig(params,
1740                             ((vars->flow_ctrl & BNX2X_FLOW_CTRL_TX) != 0), 1);
1741
1742         vars->mac_type = MAC_TYPE_XMAC;
1743
1744         return 0;
1745 }
1746 static int bnx2x_emac_enable(struct link_params *params,
1747                              struct link_vars *vars, u8 lb)
1748 {
1749         struct bnx2x *bp = params->bp;
1750         u8 port = params->port;
1751         u32 emac_base = port ? GRCBASE_EMAC1 : GRCBASE_EMAC0;
1752         u32 val;
1753
1754         DP(NETIF_MSG_LINK, "enabling EMAC\n");
1755
1756         /* Disable BMAC */
1757         REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_2_CLEAR,
1758                (MISC_REGISTERS_RESET_REG_2_RST_BMAC0 << port));
1759
1760         /* enable emac and not bmac */
1761         REG_WR(bp, NIG_REG_EGRESS_EMAC0_PORT + port*4, 1);
1762
1763         /* ASIC */
1764         if (vars->phy_flags & PHY_XGXS_FLAG) {
1765                 u32 ser_lane = ((params->lane_config &
1766                                  PORT_HW_CFG_LANE_SWAP_CFG_MASTER_MASK) >>
1767                                 PORT_HW_CFG_LANE_SWAP_CFG_MASTER_SHIFT);
1768
1769                 DP(NETIF_MSG_LINK, "XGXS\n");
1770                 /* select the master lanes (out of 0-3) */
1771                 REG_WR(bp, NIG_REG_XGXS_LANE_SEL_P0 + port*4, ser_lane);
1772                 /* select XGXS */
1773                 REG_WR(bp, NIG_REG_XGXS_SERDES0_MODE_SEL + port*4, 1);
1774
1775         } else { /* SerDes */
1776                 DP(NETIF_MSG_LINK, "SerDes\n");
1777                 /* select SerDes */
1778                 REG_WR(bp, NIG_REG_XGXS_SERDES0_MODE_SEL + port*4, 0);
1779         }
1780
1781         bnx2x_bits_en(bp, emac_base + EMAC_REG_EMAC_RX_MODE,
1782                       EMAC_RX_MODE_RESET);
1783         bnx2x_bits_en(bp, emac_base + EMAC_REG_EMAC_TX_MODE,
1784                       EMAC_TX_MODE_RESET);
1785
1786         if (CHIP_REV_IS_SLOW(bp)) {
1787                 /* config GMII mode */
1788                 val = REG_RD(bp, emac_base + EMAC_REG_EMAC_MODE);
1789                 EMAC_WR(bp, EMAC_REG_EMAC_MODE, (val | EMAC_MODE_PORT_GMII));
1790         } else { /* ASIC */
1791                 /* pause enable/disable */
1792                 bnx2x_bits_dis(bp, emac_base + EMAC_REG_EMAC_RX_MODE,
1793                                EMAC_RX_MODE_FLOW_EN);
1794
1795                 bnx2x_bits_dis(bp,  emac_base + EMAC_REG_EMAC_TX_MODE,
1796                                (EMAC_TX_MODE_EXT_PAUSE_EN |
1797                                 EMAC_TX_MODE_FLOW_EN));
1798                 if (!(params->feature_config_flags &
1799                       FEATURE_CONFIG_PFC_ENABLED)) {
1800                         if (vars->flow_ctrl & BNX2X_FLOW_CTRL_RX)
1801                                 bnx2x_bits_en(bp, emac_base +
1802                                               EMAC_REG_EMAC_RX_MODE,
1803                                               EMAC_RX_MODE_FLOW_EN);
1804
1805                         if (vars->flow_ctrl & BNX2X_FLOW_CTRL_TX)
1806                                 bnx2x_bits_en(bp, emac_base +
1807                                               EMAC_REG_EMAC_TX_MODE,
1808                                               (EMAC_TX_MODE_EXT_PAUSE_EN |
1809                                                EMAC_TX_MODE_FLOW_EN));
1810                 } else
1811                         bnx2x_bits_en(bp, emac_base + EMAC_REG_EMAC_TX_MODE,
1812                                       EMAC_TX_MODE_FLOW_EN);
1813         }
1814
1815         /* KEEP_VLAN_TAG, promiscuous */
1816         val = REG_RD(bp, emac_base + EMAC_REG_EMAC_RX_MODE);
1817         val |= EMAC_RX_MODE_KEEP_VLAN_TAG | EMAC_RX_MODE_PROMISCUOUS;
1818
1819         /*
1820          * Setting this bit causes MAC control frames (except for pause
1821          * frames) to be passed on for processing. This setting has no
1822          * affect on the operation of the pause frames. This bit effects
1823          * all packets regardless of RX Parser packet sorting logic.
1824          * Turn the PFC off to make sure we are in Xon state before
1825          * enabling it.
1826          */
1827         EMAC_WR(bp, EMAC_REG_RX_PFC_MODE, 0);
1828         if (params->feature_config_flags & FEATURE_CONFIG_PFC_ENABLED) {
1829                 DP(NETIF_MSG_LINK, "PFC is enabled\n");
1830                 /* Enable PFC again */
1831                 EMAC_WR(bp, EMAC_REG_RX_PFC_MODE,
1832                         EMAC_REG_RX_PFC_MODE_RX_EN |
1833                         EMAC_REG_RX_PFC_MODE_TX_EN |
1834                         EMAC_REG_RX_PFC_MODE_PRIORITIES);
1835
1836                 EMAC_WR(bp, EMAC_REG_RX_PFC_PARAM,
1837                         ((0x0101 <<
1838                           EMAC_REG_RX_PFC_PARAM_OPCODE_BITSHIFT) |
1839                          (0x00ff <<
1840                           EMAC_REG_RX_PFC_PARAM_PRIORITY_EN_BITSHIFT)));
1841                 val |= EMAC_RX_MODE_KEEP_MAC_CONTROL;
1842         }
1843         EMAC_WR(bp, EMAC_REG_EMAC_RX_MODE, val);
1844
1845         /* Set Loopback */
1846         val = REG_RD(bp, emac_base + EMAC_REG_EMAC_MODE);
1847         if (lb)
1848                 val |= 0x810;
1849         else
1850                 val &= ~0x810;
1851         EMAC_WR(bp, EMAC_REG_EMAC_MODE, val);
1852
1853         /* enable emac */
1854         REG_WR(bp, NIG_REG_NIG_EMAC0_EN + port*4, 1);
1855
1856         /* enable emac for jumbo packets */
1857         EMAC_WR(bp, EMAC_REG_EMAC_RX_MTU_SIZE,
1858                 (EMAC_RX_MTU_SIZE_JUMBO_ENA |
1859                  (ETH_MAX_JUMBO_PACKET_SIZE + ETH_OVREHEAD)));
1860
1861         /* strip CRC */
1862         REG_WR(bp, NIG_REG_NIG_INGRESS_EMAC0_NO_CRC + port*4, 0x1);
1863
1864         /* disable the NIG in/out to the bmac */
1865         REG_WR(bp, NIG_REG_BMAC0_IN_EN + port*4, 0x0);
1866         REG_WR(bp, NIG_REG_BMAC0_PAUSE_OUT_EN + port*4, 0x0);
1867         REG_WR(bp, NIG_REG_BMAC0_OUT_EN + port*4, 0x0);
1868
1869         /* enable the NIG in/out to the emac */
1870         REG_WR(bp, NIG_REG_EMAC0_IN_EN + port*4, 0x1);
1871         val = 0;
1872         if ((params->feature_config_flags &
1873               FEATURE_CONFIG_PFC_ENABLED) ||
1874             (vars->flow_ctrl & BNX2X_FLOW_CTRL_TX))
1875                 val = 1;
1876
1877         REG_WR(bp, NIG_REG_EMAC0_PAUSE_OUT_EN + port*4, val);
1878         REG_WR(bp, NIG_REG_EGRESS_EMAC0_OUT_EN + port*4, 0x1);
1879
1880         REG_WR(bp, NIG_REG_BMAC0_REGS_OUT_EN + port*4, 0x0);
1881
1882         vars->mac_type = MAC_TYPE_EMAC;
1883         return 0;
1884 }
1885
1886 static void bnx2x_update_pfc_bmac1(struct link_params *params,
1887                                    struct link_vars *vars)
1888 {
1889         u32 wb_data[2];
1890         struct bnx2x *bp = params->bp;
1891         u32 bmac_addr =  params->port ? NIG_REG_INGRESS_BMAC1_MEM :
1892                 NIG_REG_INGRESS_BMAC0_MEM;
1893
1894         u32 val = 0x14;
1895         if ((!(params->feature_config_flags &
1896               FEATURE_CONFIG_PFC_ENABLED)) &&
1897                 (vars->flow_ctrl & BNX2X_FLOW_CTRL_RX))
1898                 /* Enable BigMAC to react on received Pause packets */
1899                 val |= (1<<5);
1900         wb_data[0] = val;
1901         wb_data[1] = 0;
1902         REG_WR_DMAE(bp, bmac_addr + BIGMAC_REGISTER_RX_CONTROL, wb_data, 2);
1903
1904         /* tx control */
1905         val = 0xc0;
1906         if (!(params->feature_config_flags &
1907               FEATURE_CONFIG_PFC_ENABLED) &&
1908                 (vars->flow_ctrl & BNX2X_FLOW_CTRL_TX))
1909                 val |= 0x800000;
1910         wb_data[0] = val;
1911         wb_data[1] = 0;
1912         REG_WR_DMAE(bp, bmac_addr + BIGMAC_REGISTER_TX_CONTROL, wb_data, 2);
1913 }
1914
1915 static void bnx2x_update_pfc_bmac2(struct link_params *params,
1916                                    struct link_vars *vars,
1917                                    u8 is_lb)
1918 {
1919         /*
1920          * Set rx control: Strip CRC and enable BigMAC to relay
1921          * control packets to the system as well
1922          */
1923         u32 wb_data[2];
1924         struct bnx2x *bp = params->bp;
1925         u32 bmac_addr = params->port ? NIG_REG_INGRESS_BMAC1_MEM :
1926                 NIG_REG_INGRESS_BMAC0_MEM;
1927         u32 val = 0x14;
1928
1929         if ((!(params->feature_config_flags &
1930               FEATURE_CONFIG_PFC_ENABLED)) &&
1931                 (vars->flow_ctrl & BNX2X_FLOW_CTRL_RX))
1932                 /* Enable BigMAC to react on received Pause packets */
1933                 val |= (1<<5);
1934         wb_data[0] = val;
1935         wb_data[1] = 0;
1936         REG_WR_DMAE(bp, bmac_addr + BIGMAC2_REGISTER_RX_CONTROL, wb_data, 2);
1937         udelay(30);
1938
1939         /* Tx control */
1940         val = 0xc0;
1941         if (!(params->feature_config_flags &
1942                                 FEATURE_CONFIG_PFC_ENABLED) &&
1943             (vars->flow_ctrl & BNX2X_FLOW_CTRL_TX))
1944                 val |= 0x800000;
1945         wb_data[0] = val;
1946         wb_data[1] = 0;
1947         REG_WR_DMAE(bp, bmac_addr + BIGMAC2_REGISTER_TX_CONTROL, wb_data, 2);
1948
1949         if (params->feature_config_flags & FEATURE_CONFIG_PFC_ENABLED) {
1950                 DP(NETIF_MSG_LINK, "PFC is enabled\n");
1951                 /* Enable PFC RX & TX & STATS and set 8 COS  */
1952                 wb_data[0] = 0x0;
1953                 wb_data[0] |= (1<<0);  /* RX */
1954                 wb_data[0] |= (1<<1);  /* TX */
1955                 wb_data[0] |= (1<<2);  /* Force initial Xon */
1956                 wb_data[0] |= (1<<3);  /* 8 cos */
1957                 wb_data[0] |= (1<<5);  /* STATS */
1958                 wb_data[1] = 0;
1959                 REG_WR_DMAE(bp, bmac_addr + BIGMAC2_REGISTER_PFC_CONTROL,
1960                             wb_data, 2);
1961                 /* Clear the force Xon */
1962                 wb_data[0] &= ~(1<<2);
1963         } else {
1964                 DP(NETIF_MSG_LINK, "PFC is disabled\n");
1965                 /* disable PFC RX & TX & STATS and set 8 COS */
1966                 wb_data[0] = 0x8;
1967                 wb_data[1] = 0;
1968         }
1969
1970         REG_WR_DMAE(bp, bmac_addr + BIGMAC2_REGISTER_PFC_CONTROL, wb_data, 2);
1971
1972         /*
1973          * Set Time (based unit is 512 bit time) between automatic
1974          * re-sending of PP packets amd enable automatic re-send of
1975          * Per-Priroity Packet as long as pp_gen is asserted and
1976          * pp_disable is low.
1977          */
1978         val = 0x8000;
1979         if (params->feature_config_flags & FEATURE_CONFIG_PFC_ENABLED)
1980                 val |= (1<<16); /* enable automatic re-send */
1981
1982         wb_data[0] = val;
1983         wb_data[1] = 0;
1984         REG_WR_DMAE(bp, bmac_addr + BIGMAC2_REGISTER_TX_PAUSE_CONTROL,
1985                     wb_data, 2);
1986
1987         /* mac control */
1988         val = 0x3; /* Enable RX and TX */
1989         if (is_lb) {
1990                 val |= 0x4; /* Local loopback */
1991                 DP(NETIF_MSG_LINK, "enable bmac loopback\n");
1992         }
1993         /* When PFC enabled, Pass pause frames towards the NIG. */
1994         if (params->feature_config_flags & FEATURE_CONFIG_PFC_ENABLED)
1995                 val |= ((1<<6)|(1<<5));
1996
1997         wb_data[0] = val;
1998         wb_data[1] = 0;
1999         REG_WR_DMAE(bp, bmac_addr + BIGMAC2_REGISTER_BMAC_CONTROL, wb_data, 2);
2000 }
2001
2002
2003 /* PFC BRB internal port configuration params */
2004 struct bnx2x_pfc_brb_threshold_val {
2005         u32 pause_xoff;
2006         u32 pause_xon;
2007         u32 full_xoff;
2008         u32 full_xon;
2009 };
2010
2011 struct bnx2x_pfc_brb_e3b0_val {
2012         u32 full_lb_xoff_th;
2013         u32 full_lb_xon_threshold;
2014         u32 lb_guarantied;
2015         u32 mac_0_class_t_guarantied;
2016         u32 mac_0_class_t_guarantied_hyst;
2017         u32 mac_1_class_t_guarantied;
2018         u32 mac_1_class_t_guarantied_hyst;
2019 };
2020
2021 struct bnx2x_pfc_brb_th_val {
2022         struct bnx2x_pfc_brb_threshold_val pauseable_th;
2023         struct bnx2x_pfc_brb_threshold_val non_pauseable_th;
2024 };
2025 static int bnx2x_pfc_brb_get_config_params(
2026                                 struct link_params *params,
2027                                 struct bnx2x_pfc_brb_th_val *config_val)
2028 {
2029         struct bnx2x *bp = params->bp;
2030         DP(NETIF_MSG_LINK, "Setting PFC BRB configuration\n");
2031         if (CHIP_IS_E2(bp)) {
2032                 config_val->pauseable_th.pause_xoff =
2033                     PFC_E2_BRB_MAC_PAUSE_XOFF_THR_PAUSE;
2034                 config_val->pauseable_th.pause_xon =
2035                     PFC_E2_BRB_MAC_PAUSE_XON_THR_PAUSE;
2036                 config_val->pauseable_th.full_xoff =
2037                     PFC_E2_BRB_MAC_FULL_XOFF_THR_PAUSE;
2038                 config_val->pauseable_th.full_xon =
2039                     PFC_E2_BRB_MAC_FULL_XON_THR_PAUSE;
2040                 /* non pause able*/
2041                 config_val->non_pauseable_th.pause_xoff =
2042                     PFC_E2_BRB_MAC_PAUSE_XOFF_THR_NON_PAUSE;
2043                 config_val->non_pauseable_th.pause_xon =
2044                     PFC_E2_BRB_MAC_PAUSE_XON_THR_NON_PAUSE;
2045                 config_val->non_pauseable_th.full_xoff =
2046                     PFC_E2_BRB_MAC_FULL_XOFF_THR_NON_PAUSE;
2047                 config_val->non_pauseable_th.full_xon =
2048                     PFC_E2_BRB_MAC_FULL_XON_THR_NON_PAUSE;
2049         } else if (CHIP_IS_E3A0(bp)) {
2050                 config_val->pauseable_th.pause_xoff =
2051                     PFC_E3A0_BRB_MAC_PAUSE_XOFF_THR_PAUSE;
2052                 config_val->pauseable_th.pause_xon =
2053                     PFC_E3A0_BRB_MAC_PAUSE_XON_THR_PAUSE;
2054                 config_val->pauseable_th.full_xoff =
2055                     PFC_E3A0_BRB_MAC_FULL_XOFF_THR_PAUSE;
2056                 config_val->pauseable_th.full_xon =
2057                     PFC_E3A0_BRB_MAC_FULL_XON_THR_PAUSE;
2058                 /* non pause able*/
2059                 config_val->non_pauseable_th.pause_xoff =
2060                     PFC_E3A0_BRB_MAC_PAUSE_XOFF_THR_NON_PAUSE;
2061                 config_val->non_pauseable_th.pause_xon =
2062                     PFC_E3A0_BRB_MAC_PAUSE_XON_THR_NON_PAUSE;
2063                 config_val->non_pauseable_th.full_xoff =
2064                     PFC_E3A0_BRB_MAC_FULL_XOFF_THR_NON_PAUSE;
2065                 config_val->non_pauseable_th.full_xon =
2066                     PFC_E3A0_BRB_MAC_FULL_XON_THR_NON_PAUSE;
2067         } else if (CHIP_IS_E3B0(bp)) {
2068                 if (params->phy[INT_PHY].flags &
2069                     FLAGS_4_PORT_MODE) {
2070                         config_val->pauseable_th.pause_xoff =
2071                             PFC_E3B0_4P_BRB_MAC_PAUSE_XOFF_THR_PAUSE;
2072                         config_val->pauseable_th.pause_xon =
2073                             PFC_E3B0_4P_BRB_MAC_PAUSE_XON_THR_PAUSE;
2074                         config_val->pauseable_th.full_xoff =
2075                             PFC_E3B0_4P_BRB_MAC_FULL_XOFF_THR_PAUSE;
2076                         config_val->pauseable_th.full_xon =
2077                             PFC_E3B0_4P_BRB_MAC_FULL_XON_THR_PAUSE;
2078                         /* non pause able*/
2079                         config_val->non_pauseable_th.pause_xoff =
2080                             PFC_E3B0_4P_BRB_MAC_PAUSE_XOFF_THR_NON_PAUSE;
2081                         config_val->non_pauseable_th.pause_xon =
2082                             PFC_E3B0_4P_BRB_MAC_PAUSE_XON_THR_NON_PAUSE;
2083                         config_val->non_pauseable_th.full_xoff =
2084                             PFC_E3B0_4P_BRB_MAC_FULL_XOFF_THR_NON_PAUSE;
2085                         config_val->non_pauseable_th.full_xon =
2086                             PFC_E3B0_4P_BRB_MAC_FULL_XON_THR_NON_PAUSE;
2087             } else {
2088                 config_val->pauseable_th.pause_xoff =
2089                     PFC_E3B0_2P_BRB_MAC_PAUSE_XOFF_THR_PAUSE;
2090                 config_val->pauseable_th.pause_xon =
2091                     PFC_E3B0_2P_BRB_MAC_PAUSE_XON_THR_PAUSE;
2092                 config_val->pauseable_th.full_xoff =
2093                     PFC_E3B0_2P_BRB_MAC_FULL_XOFF_THR_PAUSE;
2094                 config_val->pauseable_th.full_xon =
2095                         PFC_E3B0_2P_BRB_MAC_FULL_XON_THR_PAUSE;
2096                 /* non pause able*/
2097                 config_val->non_pauseable_th.pause_xoff =
2098                     PFC_E3B0_2P_BRB_MAC_PAUSE_XOFF_THR_NON_PAUSE;
2099                 config_val->non_pauseable_th.pause_xon =
2100                     PFC_E3B0_2P_BRB_MAC_PAUSE_XON_THR_NON_PAUSE;
2101                 config_val->non_pauseable_th.full_xoff =
2102                     PFC_E3B0_2P_BRB_MAC_FULL_XOFF_THR_NON_PAUSE;
2103                 config_val->non_pauseable_th.full_xon =
2104                     PFC_E3B0_2P_BRB_MAC_FULL_XON_THR_NON_PAUSE;
2105             }
2106         } else
2107             return -EINVAL;
2108
2109         return 0;
2110 }
2111
2112
2113 static void bnx2x_pfc_brb_get_e3b0_config_params(struct link_params *params,
2114                                                  struct bnx2x_pfc_brb_e3b0_val
2115                                                  *e3b0_val,
2116                                                  u32 cos0_pauseable,
2117                                                  u32 cos1_pauseable)
2118 {
2119         if (params->phy[INT_PHY].flags & FLAGS_4_PORT_MODE) {
2120                 e3b0_val->full_lb_xoff_th =
2121                     PFC_E3B0_4P_BRB_FULL_LB_XOFF_THR;
2122                 e3b0_val->full_lb_xon_threshold =
2123                     PFC_E3B0_4P_BRB_FULL_LB_XON_THR;
2124                 e3b0_val->lb_guarantied =
2125                     PFC_E3B0_4P_LB_GUART;
2126                 e3b0_val->mac_0_class_t_guarantied =
2127                     PFC_E3B0_4P_BRB_MAC_0_CLASS_T_GUART;
2128                 e3b0_val->mac_0_class_t_guarantied_hyst =
2129                     PFC_E3B0_4P_BRB_MAC_0_CLASS_T_GUART_HYST;
2130                 e3b0_val->mac_1_class_t_guarantied =
2131                     PFC_E3B0_4P_BRB_MAC_1_CLASS_T_GUART;
2132                 e3b0_val->mac_1_class_t_guarantied_hyst =
2133                     PFC_E3B0_4P_BRB_MAC_1_CLASS_T_GUART_HYST;
2134         } else {
2135                 e3b0_val->full_lb_xoff_th =
2136                     PFC_E3B0_2P_BRB_FULL_LB_XOFF_THR;
2137                 e3b0_val->full_lb_xon_threshold =
2138                     PFC_E3B0_2P_BRB_FULL_LB_XON_THR;
2139                 e3b0_val->mac_0_class_t_guarantied_hyst =
2140                     PFC_E3B0_2P_BRB_MAC_0_CLASS_T_GUART_HYST;
2141                 e3b0_val->mac_1_class_t_guarantied =
2142                     PFC_E3B0_2P_BRB_MAC_1_CLASS_T_GUART;
2143                 e3b0_val->mac_1_class_t_guarantied_hyst =
2144                     PFC_E3B0_2P_BRB_MAC_1_CLASS_T_GUART_HYST;
2145
2146                 if (cos0_pauseable != cos1_pauseable) {
2147                         /* nonpauseable= Lossy + pauseable = Lossless*/
2148                         e3b0_val->lb_guarantied =
2149                             PFC_E3B0_2P_MIX_PAUSE_LB_GUART;
2150                         e3b0_val->mac_0_class_t_guarantied =
2151                             PFC_E3B0_2P_MIX_PAUSE_MAC_0_CLASS_T_GUART;
2152                 } else if (cos0_pauseable) {
2153                         /* Lossless +Lossless*/
2154                         e3b0_val->lb_guarantied =
2155                             PFC_E3B0_2P_PAUSE_LB_GUART;
2156                         e3b0_val->mac_0_class_t_guarantied =
2157                             PFC_E3B0_2P_PAUSE_MAC_0_CLASS_T_GUART;
2158                 } else {
2159                         /* Lossy +Lossy*/
2160                         e3b0_val->lb_guarantied =
2161                             PFC_E3B0_2P_NON_PAUSE_LB_GUART;
2162                         e3b0_val->mac_0_class_t_guarantied =
2163                             PFC_E3B0_2P_NON_PAUSE_MAC_0_CLASS_T_GUART;
2164                 }
2165         }
2166 }
2167 static int bnx2x_update_pfc_brb(struct link_params *params,
2168                                 struct link_vars *vars,
2169                                 struct bnx2x_nig_brb_pfc_port_params
2170                                 *pfc_params)
2171 {
2172         struct bnx2x *bp = params->bp;
2173         struct bnx2x_pfc_brb_th_val config_val = { {0} };
2174         struct bnx2x_pfc_brb_threshold_val *reg_th_config =
2175             &config_val.pauseable_th;
2176         struct bnx2x_pfc_brb_e3b0_val e3b0_val = {0};
2177         int set_pfc = params->feature_config_flags &
2178                 FEATURE_CONFIG_PFC_ENABLED;
2179         int bnx2x_status = 0;
2180         u8 port = params->port;
2181
2182         /* default - pause configuration */
2183         reg_th_config = &config_val.pauseable_th;
2184         bnx2x_status = bnx2x_pfc_brb_get_config_params(params, &config_val);
2185         if (0 != bnx2x_status)
2186                 return bnx2x_status;
2187
2188         if (set_pfc && pfc_params)
2189                 /* First COS */
2190                 if (!pfc_params->cos0_pauseable)
2191                         reg_th_config = &config_val.non_pauseable_th;
2192         /*
2193          * The number of free blocks below which the pause signal to class 0
2194          * of MAC #n is asserted. n=0,1
2195          */
2196         REG_WR(bp, (port) ? BRB1_REG_PAUSE_0_XOFF_THRESHOLD_1 :
2197                BRB1_REG_PAUSE_0_XOFF_THRESHOLD_0 ,
2198                reg_th_config->pause_xoff);
2199         /*
2200          * The number of free blocks above which the pause signal to class 0
2201          * of MAC #n is de-asserted. n=0,1
2202          */
2203         REG_WR(bp, (port) ? BRB1_REG_PAUSE_0_XON_THRESHOLD_1 :
2204                BRB1_REG_PAUSE_0_XON_THRESHOLD_0 , reg_th_config->pause_xon);
2205         /*
2206          * The number of free blocks below which the full signal to class 0
2207          * of MAC #n is asserted. n=0,1
2208          */
2209         REG_WR(bp, (port) ? BRB1_REG_FULL_0_XOFF_THRESHOLD_1 :
2210                BRB1_REG_FULL_0_XOFF_THRESHOLD_0 , reg_th_config->full_xoff);
2211         /*
2212          * The number of free blocks above which the full signal to class 0
2213          * of MAC #n is de-asserted. n=0,1
2214          */
2215         REG_WR(bp, (port) ? BRB1_REG_FULL_0_XON_THRESHOLD_1 :
2216                BRB1_REG_FULL_0_XON_THRESHOLD_0 , reg_th_config->full_xon);
2217
2218         if (set_pfc && pfc_params) {
2219                 /* Second COS */
2220                 if (pfc_params->cos1_pauseable)
2221                         reg_th_config = &config_val.pauseable_th;
2222                 else
2223                         reg_th_config = &config_val.non_pauseable_th;
2224                 /*
2225                  * The number of free blocks below which the pause signal to
2226                  * class 1 of MAC #n is asserted. n=0,1
2227                 **/
2228                 REG_WR(bp, (port) ? BRB1_REG_PAUSE_1_XOFF_THRESHOLD_1 :
2229                        BRB1_REG_PAUSE_1_XOFF_THRESHOLD_0,
2230                        reg_th_config->pause_xoff);
2231                 /*
2232                  * The number of free blocks above which the pause signal to
2233                  * class 1 of MAC #n is de-asserted. n=0,1
2234                  */
2235                 REG_WR(bp, (port) ? BRB1_REG_PAUSE_1_XON_THRESHOLD_1 :
2236                        BRB1_REG_PAUSE_1_XON_THRESHOLD_0,
2237                        reg_th_config->pause_xon);
2238                 /*
2239                  * The number of free blocks below which the full signal to
2240                  * class 1 of MAC #n is asserted. n=0,1
2241                  */
2242                 REG_WR(bp, (port) ? BRB1_REG_FULL_1_XOFF_THRESHOLD_1 :
2243                        BRB1_REG_FULL_1_XOFF_THRESHOLD_0,
2244                        reg_th_config->full_xoff);
2245                 /*
2246                  * The number of free blocks above which the full signal to
2247                  * class 1 of MAC #n is de-asserted. n=0,1
2248                  */
2249                 REG_WR(bp, (port) ? BRB1_REG_FULL_1_XON_THRESHOLD_1 :
2250                        BRB1_REG_FULL_1_XON_THRESHOLD_0,
2251                        reg_th_config->full_xon);
2252
2253
2254                 if (CHIP_IS_E3B0(bp)) {
2255                         /*Should be done by init tool */
2256                         /*
2257                         * BRB_empty_for_dup = BRB1_REG_BRB_EMPTY_THRESHOLD
2258                         * reset value
2259                         * 944
2260                         */
2261
2262                         /**
2263                          * The hysteresis on the guarantied buffer space for the Lb port
2264                          * before signaling XON.
2265                          **/
2266                         REG_WR(bp, BRB1_REG_LB_GUARANTIED_HYST, 80);
2267
2268                         bnx2x_pfc_brb_get_e3b0_config_params(
2269                             params,
2270                             &e3b0_val,
2271                             pfc_params->cos0_pauseable,
2272                             pfc_params->cos1_pauseable);
2273                         /**
2274                          * The number of free blocks below which the full signal to the
2275                          * LB port is asserted.
2276                         */
2277                         REG_WR(bp, BRB1_REG_FULL_LB_XOFF_THRESHOLD,
2278                                    e3b0_val.full_lb_xoff_th);
2279                         /**
2280                          * The number of free blocks above which the full signal to the
2281                          * LB port is de-asserted.
2282                         */
2283                         REG_WR(bp, BRB1_REG_FULL_LB_XON_THRESHOLD,
2284                                    e3b0_val.full_lb_xon_threshold);
2285                         /**
2286                         * The number of blocks guarantied for the MAC #n port. n=0,1
2287                         */
2288
2289                         /*The number of blocks guarantied for the LB port.*/
2290                         REG_WR(bp, BRB1_REG_LB_GUARANTIED,
2291                                e3b0_val.lb_guarantied);
2292
2293                         /**
2294                          * The number of blocks guarantied for the MAC #n port.
2295                         */
2296                         REG_WR(bp, BRB1_REG_MAC_GUARANTIED_0,
2297                                    2 * e3b0_val.mac_0_class_t_guarantied);
2298                         REG_WR(bp, BRB1_REG_MAC_GUARANTIED_1,
2299                                    2 * e3b0_val.mac_1_class_t_guarantied);
2300                         /**
2301                          * The number of blocks guarantied for class #t in MAC0. t=0,1
2302                         */
2303                         REG_WR(bp, BRB1_REG_MAC_0_CLASS_0_GUARANTIED,
2304                                e3b0_val.mac_0_class_t_guarantied);
2305                         REG_WR(bp, BRB1_REG_MAC_0_CLASS_1_GUARANTIED,
2306                                e3b0_val.mac_0_class_t_guarantied);
2307                         /**
2308                          * The hysteresis on the guarantied buffer space for class in
2309                          * MAC0.  t=0,1
2310                         */
2311                         REG_WR(bp, BRB1_REG_MAC_0_CLASS_0_GUARANTIED_HYST,
2312                                e3b0_val.mac_0_class_t_guarantied_hyst);
2313                         REG_WR(bp, BRB1_REG_MAC_0_CLASS_1_GUARANTIED_HYST,
2314                                e3b0_val.mac_0_class_t_guarantied_hyst);
2315
2316                         /**
2317                          * The number of blocks guarantied for class #t in MAC1.t=0,1
2318                         */
2319                         REG_WR(bp, BRB1_REG_MAC_1_CLASS_0_GUARANTIED,
2320                                e3b0_val.mac_1_class_t_guarantied);
2321                         REG_WR(bp, BRB1_REG_MAC_1_CLASS_1_GUARANTIED,
2322                                e3b0_val.mac_1_class_t_guarantied);
2323                         /**
2324                          * The hysteresis on the guarantied buffer space for class #t
2325                         * in MAC1.  t=0,1
2326                         */
2327                         REG_WR(bp, BRB1_REG_MAC_1_CLASS_0_GUARANTIED_HYST,
2328                                e3b0_val.mac_1_class_t_guarantied_hyst);
2329                         REG_WR(bp, BRB1_REG_MAC_1_CLASS_1_GUARANTIED_HYST,
2330                                e3b0_val.mac_1_class_t_guarantied_hyst);
2331
2332             }
2333
2334         }
2335
2336         return bnx2x_status;
2337 }
2338
2339 /******************************************************************************
2340 * Description:
2341 *  This function is needed because NIG ARB_CREDIT_WEIGHT_X are
2342 *  not continues and ARB_CREDIT_WEIGHT_0 + offset is suitable.
2343 ******************************************************************************/
2344 int bnx2x_pfc_nig_rx_priority_mask(struct bnx2x *bp,
2345                                               u8 cos_entry,
2346                                               u32 priority_mask, u8 port)
2347 {
2348         u32 nig_reg_rx_priority_mask_add = 0;
2349
2350         switch (cos_entry) {
2351         case 0:
2352              nig_reg_rx_priority_mask_add = (port) ?
2353                  NIG_REG_P1_RX_COS0_PRIORITY_MASK :
2354                  NIG_REG_P0_RX_COS0_PRIORITY_MASK;
2355              break;
2356         case 1:
2357             nig_reg_rx_priority_mask_add = (port) ?
2358                 NIG_REG_P1_RX_COS1_PRIORITY_MASK :
2359                 NIG_REG_P0_RX_COS1_PRIORITY_MASK;
2360             break;
2361         case 2:
2362             nig_reg_rx_priority_mask_add = (port) ?
2363                 NIG_REG_P1_RX_COS2_PRIORITY_MASK :
2364                 NIG_REG_P0_RX_COS2_PRIORITY_MASK;
2365             break;
2366         case 3:
2367             if (port)
2368                 return -EINVAL;
2369             nig_reg_rx_priority_mask_add = NIG_REG_P0_RX_COS3_PRIORITY_MASK;
2370             break;
2371         case 4:
2372             if (port)
2373                 return -EINVAL;
2374             nig_reg_rx_priority_mask_add = NIG_REG_P0_RX_COS4_PRIORITY_MASK;
2375             break;
2376         case 5:
2377             if (port)
2378                 return -EINVAL;
2379             nig_reg_rx_priority_mask_add = NIG_REG_P0_RX_COS5_PRIORITY_MASK;
2380             break;
2381         }
2382
2383         REG_WR(bp, nig_reg_rx_priority_mask_add, priority_mask);
2384
2385         return 0;
2386 }
2387 static void bnx2x_update_mng(struct link_params *params, u32 link_status)
2388 {
2389         struct bnx2x *bp = params->bp;
2390
2391         REG_WR(bp, params->shmem_base +
2392                offsetof(struct shmem_region,
2393                         port_mb[params->port].link_status), link_status);
2394 }
2395
2396 static void bnx2x_update_pfc_nig(struct link_params *params,
2397                 struct link_vars *vars,
2398                 struct bnx2x_nig_brb_pfc_port_params *nig_params)
2399 {
2400         u32 xcm_mask = 0, ppp_enable = 0, pause_enable = 0, llfc_out_en = 0;
2401         u32 llfc_enable = 0, xcm0_out_en = 0, p0_hwpfc_enable = 0;
2402         u32 pkt_priority_to_cos = 0;
2403         struct bnx2x *bp = params->bp;
2404         u8 port = params->port;
2405
2406         int set_pfc = params->feature_config_flags &
2407                 FEATURE_CONFIG_PFC_ENABLED;
2408         DP(NETIF_MSG_LINK, "updating pfc nig parameters\n");
2409
2410         /*
2411          * When NIG_LLH0_XCM_MASK_REG_LLHX_XCM_MASK_BCN bit is set
2412          * MAC control frames (that are not pause packets)
2413          * will be forwarded to the XCM.
2414          */
2415         xcm_mask = REG_RD(bp,
2416                                 port ? NIG_REG_LLH1_XCM_MASK :
2417                                 NIG_REG_LLH0_XCM_MASK);
2418         /*
2419          * nig params will override non PFC params, since it's possible to
2420          * do transition from PFC to SAFC
2421          */
2422         if (set_pfc) {
2423                 pause_enable = 0;
2424                 llfc_out_en = 0;
2425                 llfc_enable = 0;
2426                 if (CHIP_IS_E3(bp))
2427                         ppp_enable = 0;
2428                 else
2429                 ppp_enable = 1;
2430                 xcm_mask &= ~(port ? NIG_LLH1_XCM_MASK_REG_LLH1_XCM_MASK_BCN :
2431                                      NIG_LLH0_XCM_MASK_REG_LLH0_XCM_MASK_BCN);
2432                 xcm0_out_en = 0;
2433                 p0_hwpfc_enable = 1;
2434         } else  {
2435                 if (nig_params) {
2436                         llfc_out_en = nig_params->llfc_out_en;
2437                         llfc_enable = nig_params->llfc_enable;
2438                         pause_enable = nig_params->pause_enable;
2439                 } else  /*defaul non PFC mode - PAUSE */
2440                         pause_enable = 1;
2441
2442                 xcm_mask |= (port ? NIG_LLH1_XCM_MASK_REG_LLH1_XCM_MASK_BCN :
2443                         NIG_LLH0_XCM_MASK_REG_LLH0_XCM_MASK_BCN);
2444                 xcm0_out_en = 1;
2445         }
2446
2447         if (CHIP_IS_E3(bp))
2448                 REG_WR(bp, port ? NIG_REG_BRB1_PAUSE_IN_EN :
2449                        NIG_REG_BRB0_PAUSE_IN_EN, pause_enable);
2450         REG_WR(bp, port ? NIG_REG_LLFC_OUT_EN_1 :
2451                NIG_REG_LLFC_OUT_EN_0, llfc_out_en);
2452         REG_WR(bp, port ? NIG_REG_LLFC_ENABLE_1 :
2453                NIG_REG_LLFC_ENABLE_0, llfc_enable);
2454         REG_WR(bp, port ? NIG_REG_PAUSE_ENABLE_1 :
2455                NIG_REG_PAUSE_ENABLE_0, pause_enable);
2456
2457         REG_WR(bp, port ? NIG_REG_PPP_ENABLE_1 :
2458                NIG_REG_PPP_ENABLE_0, ppp_enable);
2459
2460         REG_WR(bp, port ? NIG_REG_LLH1_XCM_MASK :
2461                NIG_REG_LLH0_XCM_MASK, xcm_mask);
2462
2463         REG_WR(bp,  NIG_REG_LLFC_EGRESS_SRC_ENABLE_0, 0x7);
2464
2465         /* output enable for RX_XCM # IF */
2466         REG_WR(bp, NIG_REG_XCM0_OUT_EN, xcm0_out_en);
2467
2468         /* HW PFC TX enable */
2469         REG_WR(bp, NIG_REG_P0_HWPFC_ENABLE, p0_hwpfc_enable);
2470
2471         if (nig_params) {
2472                 u8 i = 0;
2473                 pkt_priority_to_cos = nig_params->pkt_priority_to_cos;
2474
2475                 for (i = 0; i < nig_params->num_of_rx_cos_priority_mask; i++)
2476                         bnx2x_pfc_nig_rx_priority_mask(bp, i,
2477                 nig_params->rx_cos_priority_mask[i], port);
2478
2479                 REG_WR(bp, port ? NIG_REG_LLFC_HIGH_PRIORITY_CLASSES_1 :
2480                        NIG_REG_LLFC_HIGH_PRIORITY_CLASSES_0,
2481                        nig_params->llfc_high_priority_classes);
2482
2483                 REG_WR(bp, port ? NIG_REG_LLFC_LOW_PRIORITY_CLASSES_1 :
2484                        NIG_REG_LLFC_LOW_PRIORITY_CLASSES_0,
2485                        nig_params->llfc_low_priority_classes);
2486         }
2487         REG_WR(bp, port ? NIG_REG_P1_PKT_PRIORITY_TO_COS :
2488                NIG_REG_P0_PKT_PRIORITY_TO_COS,
2489                pkt_priority_to_cos);
2490 }
2491
2492 int bnx2x_update_pfc(struct link_params *params,
2493                       struct link_vars *vars,
2494                       struct bnx2x_nig_brb_pfc_port_params *pfc_params)
2495 {
2496         /*
2497          * The PFC and pause are orthogonal to one another, meaning when
2498          * PFC is enabled, the pause are disabled, and when PFC is
2499          * disabled, pause are set according to the pause result.
2500          */
2501         u32 val;
2502         struct bnx2x *bp = params->bp;
2503         int bnx2x_status = 0;
2504         u8 bmac_loopback = (params->loopback_mode == LOOPBACK_BMAC);
2505
2506         if (params->feature_config_flags & FEATURE_CONFIG_PFC_ENABLED)
2507                 vars->link_status |= LINK_STATUS_PFC_ENABLED;
2508         else
2509                 vars->link_status &= ~LINK_STATUS_PFC_ENABLED;
2510
2511         bnx2x_update_mng(params, vars->link_status);
2512
2513         /* update NIG params */
2514         bnx2x_update_pfc_nig(params, vars, pfc_params);
2515
2516         /* update BRB params */
2517         bnx2x_status = bnx2x_update_pfc_brb(params, vars, pfc_params);
2518         if (0 != bnx2x_status)
2519                 return bnx2x_status;
2520
2521         if (!vars->link_up)
2522                 return bnx2x_status;
2523
2524         DP(NETIF_MSG_LINK, "About to update PFC in BMAC\n");
2525         if (CHIP_IS_E3(bp))
2526                 bnx2x_update_pfc_xmac(params, vars, 0);
2527         else {
2528                 val = REG_RD(bp, MISC_REG_RESET_REG_2);
2529                 if ((val &
2530                      (MISC_REGISTERS_RESET_REG_2_RST_BMAC0 << params->port))
2531                     == 0) {
2532                         DP(NETIF_MSG_LINK, "About to update PFC in EMAC\n");
2533                         bnx2x_emac_enable(params, vars, 0);
2534                         return bnx2x_status;
2535                 }
2536
2537                 if (CHIP_IS_E2(bp))
2538                         bnx2x_update_pfc_bmac2(params, vars, bmac_loopback);
2539                 else
2540                         bnx2x_update_pfc_bmac1(params, vars);
2541
2542                 val = 0;
2543                 if ((params->feature_config_flags &
2544                      FEATURE_CONFIG_PFC_ENABLED) ||
2545                     (vars->flow_ctrl & BNX2X_FLOW_CTRL_TX))
2546                         val = 1;
2547                 REG_WR(bp, NIG_REG_BMAC0_PAUSE_OUT_EN + params->port*4, val);
2548         }
2549         return bnx2x_status;
2550 }
2551
2552
2553 static int bnx2x_bmac1_enable(struct link_params *params,
2554                               struct link_vars *vars,
2555                               u8 is_lb)
2556 {
2557         struct bnx2x *bp = params->bp;
2558         u8 port = params->port;
2559         u32 bmac_addr = port ? NIG_REG_INGRESS_BMAC1_MEM :
2560                                NIG_REG_INGRESS_BMAC0_MEM;
2561         u32 wb_data[2];
2562         u32 val;
2563
2564         DP(NETIF_MSG_LINK, "Enabling BigMAC1\n");
2565
2566         /* XGXS control */
2567         wb_data[0] = 0x3c;
2568         wb_data[1] = 0;
2569         REG_WR_DMAE(bp, bmac_addr + BIGMAC_REGISTER_BMAC_XGXS_CONTROL,
2570                     wb_data, 2);
2571
2572         /* tx MAC SA */
2573         wb_data[0] = ((params->mac_addr[2] << 24) |
2574                        (params->mac_addr[3] << 16) |
2575                        (params->mac_addr[4] << 8) |
2576                         params->mac_addr[5]);
2577         wb_data[1] = ((params->mac_addr[0] << 8) |
2578                         params->mac_addr[1]);
2579         REG_WR_DMAE(bp, bmac_addr + BIGMAC_REGISTER_TX_SOURCE_ADDR, wb_data, 2);
2580
2581         /* mac control */
2582         val = 0x3;
2583         if (is_lb) {
2584                 val |= 0x4;
2585                 DP(NETIF_MSG_LINK, "enable bmac loopback\n");
2586         }
2587         wb_data[0] = val;
2588         wb_data[1] = 0;
2589         REG_WR_DMAE(bp, bmac_addr + BIGMAC_REGISTER_BMAC_CONTROL, wb_data, 2);
2590
2591         /* set rx mtu */
2592         wb_data[0] = ETH_MAX_JUMBO_PACKET_SIZE + ETH_OVREHEAD;
2593         wb_data[1] = 0;
2594         REG_WR_DMAE(bp, bmac_addr + BIGMAC_REGISTER_RX_MAX_SIZE, wb_data, 2);
2595
2596         bnx2x_update_pfc_bmac1(params, vars);
2597
2598         /* set tx mtu */
2599         wb_data[0] = ETH_MAX_JUMBO_PACKET_SIZE + ETH_OVREHEAD;
2600         wb_data[1] = 0;
2601         REG_WR_DMAE(bp, bmac_addr + BIGMAC_REGISTER_TX_MAX_SIZE, wb_data, 2);
2602
2603         /* set cnt max size */
2604         wb_data[0] = ETH_MAX_JUMBO_PACKET_SIZE + ETH_OVREHEAD;
2605         wb_data[1] = 0;
2606         REG_WR_DMAE(bp, bmac_addr + BIGMAC_REGISTER_CNT_MAX_SIZE, wb_data, 2);
2607
2608         /* configure safc */
2609         wb_data[0] = 0x1000200;
2610         wb_data[1] = 0;
2611         REG_WR_DMAE(bp, bmac_addr + BIGMAC_REGISTER_RX_LLFC_MSG_FLDS,
2612                     wb_data, 2);
2613
2614         return 0;
2615 }
2616
2617 static int bnx2x_bmac2_enable(struct link_params *params,
2618                               struct link_vars *vars,
2619                               u8 is_lb)
2620 {
2621         struct bnx2x *bp = params->bp;
2622         u8 port = params->port;
2623         u32 bmac_addr = port ? NIG_REG_INGRESS_BMAC1_MEM :
2624                                NIG_REG_INGRESS_BMAC0_MEM;
2625         u32 wb_data[2];
2626
2627         DP(NETIF_MSG_LINK, "Enabling BigMAC2\n");
2628
2629         wb_data[0] = 0;
2630         wb_data[1] = 0;
2631         REG_WR_DMAE(bp, bmac_addr + BIGMAC2_REGISTER_BMAC_CONTROL, wb_data, 2);
2632         udelay(30);
2633
2634         /* XGXS control: Reset phy HW, MDIO registers, PHY PLL and BMAC */
2635         wb_data[0] = 0x3c;
2636         wb_data[1] = 0;
2637         REG_WR_DMAE(bp, bmac_addr + BIGMAC2_REGISTER_BMAC_XGXS_CONTROL,
2638                     wb_data, 2);
2639
2640         udelay(30);
2641
2642         /* tx MAC SA */
2643         wb_data[0] = ((params->mac_addr[2] << 24) |
2644                        (params->mac_addr[3] << 16) |
2645                        (params->mac_addr[4] << 8) |
2646                         params->mac_addr[5]);
2647         wb_data[1] = ((params->mac_addr[0] << 8) |
2648                         params->mac_addr[1]);
2649         REG_WR_DMAE(bp, bmac_addr + BIGMAC2_REGISTER_TX_SOURCE_ADDR,
2650                     wb_data, 2);
2651
2652         udelay(30);
2653
2654         /* Configure SAFC */
2655         wb_data[0] = 0x1000200;
2656         wb_data[1] = 0;
2657         REG_WR_DMAE(bp, bmac_addr + BIGMAC2_REGISTER_RX_LLFC_MSG_FLDS,
2658                     wb_data, 2);
2659         udelay(30);
2660
2661         /* set rx mtu */
2662         wb_data[0] = ETH_MAX_JUMBO_PACKET_SIZE + ETH_OVREHEAD;
2663         wb_data[1] = 0;
2664         REG_WR_DMAE(bp, bmac_addr + BIGMAC2_REGISTER_RX_MAX_SIZE, wb_data, 2);
2665         udelay(30);
2666
2667         /* set tx mtu */
2668         wb_data[0] = ETH_MAX_JUMBO_PACKET_SIZE + ETH_OVREHEAD;
2669         wb_data[1] = 0;
2670         REG_WR_DMAE(bp, bmac_addr + BIGMAC2_REGISTER_TX_MAX_SIZE, wb_data, 2);
2671         udelay(30);
2672         /* set cnt max size */
2673         wb_data[0] = ETH_MAX_JUMBO_PACKET_SIZE + ETH_OVREHEAD - 2;
2674         wb_data[1] = 0;
2675         REG_WR_DMAE(bp, bmac_addr + BIGMAC2_REGISTER_CNT_MAX_SIZE, wb_data, 2);
2676         udelay(30);
2677         bnx2x_update_pfc_bmac2(params, vars, is_lb);
2678
2679         return 0;
2680 }
2681
2682 static int bnx2x_bmac_enable(struct link_params *params,
2683                              struct link_vars *vars,
2684                              u8 is_lb)
2685 {
2686         int rc = 0;
2687         u8 port = params->port;
2688         struct bnx2x *bp = params->bp;
2689         u32 val;
2690         /* reset and unreset the BigMac */
2691         REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_2_CLEAR,
2692                (MISC_REGISTERS_RESET_REG_2_RST_BMAC0 << port));
2693         msleep(1);
2694
2695         REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_2_SET,
2696                (MISC_REGISTERS_RESET_REG_2_RST_BMAC0 << port));
2697
2698         /* enable access for bmac registers */
2699         REG_WR(bp, NIG_REG_BMAC0_REGS_OUT_EN + port*4, 0x1);
2700
2701         /* Enable BMAC according to BMAC type*/
2702         if (CHIP_IS_E2(bp))
2703                 rc = bnx2x_bmac2_enable(params, vars, is_lb);
2704         else
2705                 rc = bnx2x_bmac1_enable(params, vars, is_lb);
2706         REG_WR(bp, NIG_REG_XGXS_SERDES0_MODE_SEL + port*4, 0x1);
2707         REG_WR(bp, NIG_REG_XGXS_LANE_SEL_P0 + port*4, 0x0);
2708         REG_WR(bp, NIG_REG_EGRESS_EMAC0_PORT + port*4, 0x0);
2709         val = 0;
2710         if ((params->feature_config_flags &
2711               FEATURE_CONFIG_PFC_ENABLED) ||
2712             (vars->flow_ctrl & BNX2X_FLOW_CTRL_TX))
2713                 val = 1;
2714         REG_WR(bp, NIG_REG_BMAC0_PAUSE_OUT_EN + port*4, val);
2715         REG_WR(bp, NIG_REG_EGRESS_EMAC0_OUT_EN + port*4, 0x0);
2716         REG_WR(bp, NIG_REG_EMAC0_IN_EN + port*4, 0x0);
2717         REG_WR(bp, NIG_REG_EMAC0_PAUSE_OUT_EN + port*4, 0x0);
2718         REG_WR(bp, NIG_REG_BMAC0_IN_EN + port*4, 0x1);
2719         REG_WR(bp, NIG_REG_BMAC0_OUT_EN + port*4, 0x1);
2720
2721         vars->mac_type = MAC_TYPE_BMAC;
2722         return rc;
2723 }
2724
2725 static void bnx2x_bmac_rx_disable(struct bnx2x *bp, u8 port)
2726 {
2727         u32 bmac_addr = port ? NIG_REG_INGRESS_BMAC1_MEM :
2728                         NIG_REG_INGRESS_BMAC0_MEM;
2729         u32 wb_data[2];
2730         u32 nig_bmac_enable = REG_RD(bp, NIG_REG_BMAC0_REGS_OUT_EN + port*4);
2731
2732         /* Only if the bmac is out of reset */
2733         if (REG_RD(bp, MISC_REG_RESET_REG_2) &
2734                         (MISC_REGISTERS_RESET_REG_2_RST_BMAC0 << port) &&
2735             nig_bmac_enable) {
2736
2737                 if (CHIP_IS_E2(bp)) {
2738                         /* Clear Rx Enable bit in BMAC_CONTROL register */
2739                         REG_RD_DMAE(bp, bmac_addr +
2740                                     BIGMAC2_REGISTER_BMAC_CONTROL,
2741                                     wb_data, 2);
2742                         wb_data[0] &= ~BMAC_CONTROL_RX_ENABLE;
2743                         REG_WR_DMAE(bp, bmac_addr +
2744                                     BIGMAC2_REGISTER_BMAC_CONTROL,
2745                                     wb_data, 2);
2746                 } else {
2747                         /* Clear Rx Enable bit in BMAC_CONTROL register */
2748                         REG_RD_DMAE(bp, bmac_addr +
2749                                         BIGMAC_REGISTER_BMAC_CONTROL,
2750                                         wb_data, 2);
2751                         wb_data[0] &= ~BMAC_CONTROL_RX_ENABLE;
2752                         REG_WR_DMAE(bp, bmac_addr +
2753                                         BIGMAC_REGISTER_BMAC_CONTROL,
2754                                         wb_data, 2);
2755                 }
2756                 msleep(1);
2757         }
2758 }
2759
2760 static int bnx2x_pbf_update(struct link_params *params, u32 flow_ctrl,
2761                             u32 line_speed)
2762 {
2763         struct bnx2x *bp = params->bp;
2764         u8 port = params->port;
2765         u32 init_crd, crd;
2766         u32 count = 1000;
2767
2768         /* disable port */
2769         REG_WR(bp, PBF_REG_DISABLE_NEW_TASK_PROC_P0 + port*4, 0x1);
2770
2771         /* wait for init credit */
2772         init_crd = REG_RD(bp, PBF_REG_P0_INIT_CRD + port*4);
2773         crd = REG_RD(bp, PBF_REG_P0_CREDIT + port*8);
2774         DP(NETIF_MSG_LINK, "init_crd 0x%x  crd 0x%x\n", init_crd, crd);
2775
2776         while ((init_crd != crd) && count) {
2777                 msleep(5);
2778
2779                 crd = REG_RD(bp, PBF_REG_P0_CREDIT + port*8);
2780                 count--;
2781         }
2782         crd = REG_RD(bp, PBF_REG_P0_CREDIT + port*8);
2783         if (init_crd != crd) {
2784                 DP(NETIF_MSG_LINK, "BUG! init_crd 0x%x != crd 0x%x\n",
2785                           init_crd, crd);
2786                 return -EINVAL;
2787         }
2788
2789         if (flow_ctrl & BNX2X_FLOW_CTRL_RX ||
2790             line_speed == SPEED_10 ||
2791             line_speed == SPEED_100 ||
2792             line_speed == SPEED_1000 ||
2793             line_speed == SPEED_2500) {
2794                 REG_WR(bp, PBF_REG_P0_PAUSE_ENABLE + port*4, 1);
2795                 /* update threshold */
2796                 REG_WR(bp, PBF_REG_P0_ARB_THRSH + port*4, 0);
2797                 /* update init credit */
2798                 init_crd = 778;         /* (800-18-4) */
2799
2800         } else {
2801                 u32 thresh = (ETH_MAX_JUMBO_PACKET_SIZE +
2802                               ETH_OVREHEAD)/16;
2803                 REG_WR(bp, PBF_REG_P0_PAUSE_ENABLE + port*4, 0);
2804                 /* update threshold */
2805                 REG_WR(bp, PBF_REG_P0_ARB_THRSH + port*4, thresh);
2806                 /* update init credit */
2807                 switch (line_speed) {
2808                 case SPEED_10000:
2809                         init_crd = thresh + 553 - 22;
2810                         break;
2811                 default:
2812                         DP(NETIF_MSG_LINK, "Invalid line_speed 0x%x\n",
2813                                   line_speed);
2814                         return -EINVAL;
2815                 }
2816         }
2817         REG_WR(bp, PBF_REG_P0_INIT_CRD + port*4, init_crd);
2818         DP(NETIF_MSG_LINK, "PBF updated to speed %d credit %d\n",
2819                  line_speed, init_crd);
2820
2821         /* probe the credit changes */
2822         REG_WR(bp, PBF_REG_INIT_P0 + port*4, 0x1);
2823         msleep(5);
2824         REG_WR(bp, PBF_REG_INIT_P0 + port*4, 0x0);
2825
2826         /* enable port */
2827         REG_WR(bp, PBF_REG_DISABLE_NEW_TASK_PROC_P0 + port*4, 0x0);
2828         return 0;
2829 }
2830
2831 /**
2832  * bnx2x_get_emac_base - retrive emac base address
2833  *
2834  * @bp:                 driver handle
2835  * @mdc_mdio_access:    access type
2836  * @port:               port id
2837  *
2838  * This function selects the MDC/MDIO access (through emac0 or
2839  * emac1) depend on the mdc_mdio_access, port, port swapped. Each
2840  * phy has a default access mode, which could also be overridden
2841  * by nvram configuration. This parameter, whether this is the
2842  * default phy configuration, or the nvram overrun
2843  * configuration, is passed here as mdc_mdio_access and selects
2844  * the emac_base for the CL45 read/writes operations
2845  */
2846 static u32 bnx2x_get_emac_base(struct bnx2x *bp,
2847                                u32 mdc_mdio_access, u8 port)
2848 {
2849         u32 emac_base = 0;
2850         switch (mdc_mdio_access) {
2851         case SHARED_HW_CFG_MDC_MDIO_ACCESS1_PHY_TYPE:
2852                 break;
2853         case SHARED_HW_CFG_MDC_MDIO_ACCESS1_EMAC0:
2854                 if (REG_RD(bp, NIG_REG_PORT_SWAP))
2855                         emac_base = GRCBASE_EMAC1;
2856                 else
2857                         emac_base = GRCBASE_EMAC0;
2858                 break;
2859         case SHARED_HW_CFG_MDC_MDIO_ACCESS1_EMAC1:
2860                 if (REG_RD(bp, NIG_REG_PORT_SWAP))
2861                         emac_base = GRCBASE_EMAC0;
2862                 else
2863                         emac_base = GRCBASE_EMAC1;
2864                 break;
2865         case SHARED_HW_CFG_MDC_MDIO_ACCESS1_BOTH:
2866                 emac_base = (port) ? GRCBASE_EMAC1 : GRCBASE_EMAC0;
2867                 break;
2868         case SHARED_HW_CFG_MDC_MDIO_ACCESS1_SWAPPED:
2869                 emac_base = (port) ? GRCBASE_EMAC0 : GRCBASE_EMAC1;
2870                 break;
2871         default:
2872                 break;
2873         }
2874         return emac_base;
2875
2876 }
2877
2878 /******************************************************************/
2879 /*                      CL22 access functions                     */
2880 /******************************************************************/
2881 static int bnx2x_cl22_write(struct bnx2x *bp,
2882                                        struct bnx2x_phy *phy,
2883                                        u16 reg, u16 val)
2884 {
2885         u32 tmp, mode;
2886         u8 i;
2887         int rc = 0;
2888         /* Switch to CL22 */
2889         mode = REG_RD(bp, phy->mdio_ctrl + EMAC_REG_EMAC_MDIO_MODE);
2890         REG_WR(bp, phy->mdio_ctrl + EMAC_REG_EMAC_MDIO_MODE,
2891                mode & ~EMAC_MDIO_MODE_CLAUSE_45);
2892
2893         /* address */
2894         tmp = ((phy->addr << 21) | (reg << 16) | val |
2895                EMAC_MDIO_COMM_COMMAND_WRITE_22 |
2896                EMAC_MDIO_COMM_START_BUSY);
2897         REG_WR(bp, phy->mdio_ctrl + EMAC_REG_EMAC_MDIO_COMM, tmp);
2898
2899         for (i = 0; i < 50; i++) {
2900                 udelay(10);
2901
2902                 tmp = REG_RD(bp, phy->mdio_ctrl + EMAC_REG_EMAC_MDIO_COMM);
2903                 if (!(tmp & EMAC_MDIO_COMM_START_BUSY)) {
2904                         udelay(5);
2905                         break;
2906                 }
2907         }
2908         if (tmp & EMAC_MDIO_COMM_START_BUSY) {
2909                 DP(NETIF_MSG_LINK, "write phy register failed\n");
2910                 rc = -EFAULT;
2911         }
2912         REG_WR(bp, phy->mdio_ctrl + EMAC_REG_EMAC_MDIO_MODE, mode);
2913         return rc;
2914 }
2915
2916 static int bnx2x_cl22_read(struct bnx2x *bp,
2917                                       struct bnx2x_phy *phy,
2918                                       u16 reg, u16 *ret_val)
2919 {
2920         u32 val, mode;
2921         u16 i;
2922         int rc = 0;
2923
2924         /* Switch to CL22 */
2925         mode = REG_RD(bp, phy->mdio_ctrl + EMAC_REG_EMAC_MDIO_MODE);
2926         REG_WR(bp, phy->mdio_ctrl + EMAC_REG_EMAC_MDIO_MODE,
2927                mode & ~EMAC_MDIO_MODE_CLAUSE_45);
2928
2929         /* address */
2930         val = ((phy->addr << 21) | (reg << 16) |
2931                EMAC_MDIO_COMM_COMMAND_READ_22 |
2932                EMAC_MDIO_COMM_START_BUSY);
2933         REG_WR(bp, phy->mdio_ctrl + EMAC_REG_EMAC_MDIO_COMM, val);
2934
2935         for (i = 0; i < 50; i++) {
2936                 udelay(10);
2937
2938                 val = REG_RD(bp, phy->mdio_ctrl + EMAC_REG_EMAC_MDIO_COMM);
2939                 if (!(val & EMAC_MDIO_COMM_START_BUSY)) {
2940                         *ret_val = (u16)(val & EMAC_MDIO_COMM_DATA);
2941                         udelay(5);
2942                         break;
2943                 }
2944         }
2945         if (val & EMAC_MDIO_COMM_START_BUSY) {
2946                 DP(NETIF_MSG_LINK, "read phy register failed\n");
2947
2948                 *ret_val = 0;
2949                 rc = -EFAULT;
2950         }
2951         REG_WR(bp, phy->mdio_ctrl + EMAC_REG_EMAC_MDIO_MODE, mode);
2952         return rc;
2953 }
2954
2955 /******************************************************************/
2956 /*                      CL45 access functions                     */
2957 /******************************************************************/
2958 static int bnx2x_cl45_read(struct bnx2x *bp, struct bnx2x_phy *phy,
2959                            u8 devad, u16 reg, u16 *ret_val)
2960 {
2961         u32 val;
2962         u16 i;
2963         int rc = 0;
2964         if (phy->flags & FLAGS_MDC_MDIO_WA_B0)
2965                 bnx2x_bits_en(bp, phy->mdio_ctrl + EMAC_REG_EMAC_MDIO_STATUS,
2966                               EMAC_MDIO_STATUS_10MB);
2967         /* address */
2968         val = ((phy->addr << 21) | (devad << 16) | reg |
2969                EMAC_MDIO_COMM_COMMAND_ADDRESS |
2970                EMAC_MDIO_COMM_START_BUSY);
2971         REG_WR(bp, phy->mdio_ctrl + EMAC_REG_EMAC_MDIO_COMM, val);
2972
2973         for (i = 0; i < 50; i++) {
2974                 udelay(10);
2975
2976                 val = REG_RD(bp, phy->mdio_ctrl + EMAC_REG_EMAC_MDIO_COMM);
2977                 if (!(val & EMAC_MDIO_COMM_START_BUSY)) {
2978                         udelay(5);
2979                         break;
2980                 }
2981         }
2982         if (val & EMAC_MDIO_COMM_START_BUSY) {
2983                 DP(NETIF_MSG_LINK, "read phy register failed\n");
2984                 netdev_err(bp->dev,  "MDC/MDIO access timeout\n");
2985                 *ret_val = 0;
2986                 rc = -EFAULT;
2987         } else {
2988                 /* data */
2989                 val = ((phy->addr << 21) | (devad << 16) |
2990                        EMAC_MDIO_COMM_COMMAND_READ_45 |
2991                        EMAC_MDIO_COMM_START_BUSY);
2992                 REG_WR(bp, phy->mdio_ctrl + EMAC_REG_EMAC_MDIO_COMM, val);
2993
2994                 for (i = 0; i < 50; i++) {
2995                         udelay(10);
2996
2997                         val = REG_RD(bp, phy->mdio_ctrl +
2998                                      EMAC_REG_EMAC_MDIO_COMM);
2999                         if (!(val & EMAC_MDIO_COMM_START_BUSY)) {
3000                                 *ret_val = (u16)(val & EMAC_MDIO_COMM_DATA);
3001                                 break;
3002                         }
3003                 }
3004                 if (val & EMAC_MDIO_COMM_START_BUSY) {
3005                         DP(NETIF_MSG_LINK, "read phy register failed\n");
3006                         netdev_err(bp->dev,  "MDC/MDIO access timeout\n");
3007                         *ret_val = 0;
3008                         rc = -EFAULT;
3009                 }
3010         }
3011         /* Work around for E3 A0 */
3012         if (phy->flags & FLAGS_MDC_MDIO_WA) {
3013                 phy->flags ^= FLAGS_DUMMY_READ;
3014                 if (phy->flags & FLAGS_DUMMY_READ) {
3015                         u16 temp_val;
3016                         bnx2x_cl45_read(bp, phy, devad, 0xf, &temp_val);
3017                 }
3018         }
3019
3020         if (phy->flags & FLAGS_MDC_MDIO_WA_B0)
3021                 bnx2x_bits_dis(bp, phy->mdio_ctrl + EMAC_REG_EMAC_MDIO_STATUS,
3022                                EMAC_MDIO_STATUS_10MB);
3023         return rc;
3024 }
3025
3026 static int bnx2x_cl45_write(struct bnx2x *bp, struct bnx2x_phy *phy,
3027                             u8 devad, u16 reg, u16 val)
3028 {
3029         u32 tmp;
3030         u8 i;
3031         int rc = 0;
3032         if (phy->flags & FLAGS_MDC_MDIO_WA_B0)
3033                 bnx2x_bits_en(bp, phy->mdio_ctrl + EMAC_REG_EMAC_MDIO_STATUS,
3034                               EMAC_MDIO_STATUS_10MB);
3035
3036         /* address */
3037
3038         tmp = ((phy->addr << 21) | (devad << 16) | reg |
3039                EMAC_MDIO_COMM_COMMAND_ADDRESS |
3040                EMAC_MDIO_COMM_START_BUSY);
3041         REG_WR(bp, phy->mdio_ctrl + EMAC_REG_EMAC_MDIO_COMM, tmp);
3042
3043         for (i = 0; i < 50; i++) {
3044                 udelay(10);
3045
3046                 tmp = REG_RD(bp, phy->mdio_ctrl + EMAC_REG_EMAC_MDIO_COMM);
3047                 if (!(tmp & EMAC_MDIO_COMM_START_BUSY)) {
3048                         udelay(5);
3049                         break;
3050                 }
3051         }
3052         if (tmp & EMAC_MDIO_COMM_START_BUSY) {
3053                 DP(NETIF_MSG_LINK, "write phy register failed\n");
3054                 netdev_err(bp->dev,  "MDC/MDIO access timeout\n");
3055                 rc = -EFAULT;
3056
3057         } else {
3058                 /* data */
3059                 tmp = ((phy->addr << 21) | (devad << 16) | val |
3060                        EMAC_MDIO_COMM_COMMAND_WRITE_45 |
3061                        EMAC_MDIO_COMM_START_BUSY);
3062                 REG_WR(bp, phy->mdio_ctrl + EMAC_REG_EMAC_MDIO_COMM, tmp);
3063
3064                 for (i = 0; i < 50; i++) {
3065                         udelay(10);
3066
3067                         tmp = REG_RD(bp, phy->mdio_ctrl +
3068                                      EMAC_REG_EMAC_MDIO_COMM);
3069                         if (!(tmp & EMAC_MDIO_COMM_START_BUSY)) {
3070                                 udelay(5);
3071                                 break;
3072                         }
3073                 }
3074                 if (tmp & EMAC_MDIO_COMM_START_BUSY) {
3075                         DP(NETIF_MSG_LINK, "write phy register failed\n");
3076                         netdev_err(bp->dev,  "MDC/MDIO access timeout\n");
3077                         rc = -EFAULT;
3078                 }
3079         }
3080         /* Work around for E3 A0 */
3081         if (phy->flags & FLAGS_MDC_MDIO_WA) {
3082                 phy->flags ^= FLAGS_DUMMY_READ;
3083                 if (phy->flags & FLAGS_DUMMY_READ) {
3084                         u16 temp_val;
3085                         bnx2x_cl45_read(bp, phy, devad, 0xf, &temp_val);
3086                 }
3087         }
3088         if (phy->flags & FLAGS_MDC_MDIO_WA_B0)
3089                 bnx2x_bits_dis(bp, phy->mdio_ctrl + EMAC_REG_EMAC_MDIO_STATUS,
3090                                EMAC_MDIO_STATUS_10MB);
3091         return rc;
3092 }
3093
3094
3095 /******************************************************************/
3096 /*                      BSC access functions from E3              */
3097 /******************************************************************/
3098 static void bnx2x_bsc_module_sel(struct link_params *params)
3099 {
3100         int idx;
3101         u32 board_cfg, sfp_ctrl;
3102         u32 i2c_pins[I2C_SWITCH_WIDTH], i2c_val[I2C_SWITCH_WIDTH];
3103         struct bnx2x *bp = params->bp;
3104         u8 port = params->port;
3105         /* Read I2C output PINs */
3106         board_cfg = REG_RD(bp, params->shmem_base +
3107                            offsetof(struct shmem_region,
3108                                     dev_info.shared_hw_config.board));
3109         i2c_pins[I2C_BSC0] = board_cfg & SHARED_HW_CFG_E3_I2C_MUX0_MASK;
3110         i2c_pins[I2C_BSC1] = (board_cfg & SHARED_HW_CFG_E3_I2C_MUX1_MASK) >>
3111                         SHARED_HW_CFG_E3_I2C_MUX1_SHIFT;
3112
3113         /* Read I2C output value */
3114         sfp_ctrl = REG_RD(bp, params->shmem_base +
3115                           offsetof(struct shmem_region,
3116                                  dev_info.port_hw_config[port].e3_cmn_pin_cfg));
3117         i2c_val[I2C_BSC0] = (sfp_ctrl & PORT_HW_CFG_E3_I2C_MUX0_MASK) > 0;
3118         i2c_val[I2C_BSC1] = (sfp_ctrl & PORT_HW_CFG_E3_I2C_MUX1_MASK) > 0;
3119         DP(NETIF_MSG_LINK, "Setting BSC switch\n");
3120         for (idx = 0; idx < I2C_SWITCH_WIDTH; idx++)
3121                 bnx2x_set_cfg_pin(bp, i2c_pins[idx], i2c_val[idx]);
3122 }
3123
3124 static int bnx2x_bsc_read(struct link_params *params,
3125                           struct bnx2x_phy *phy,
3126                           u8 sl_devid,
3127                           u16 sl_addr,
3128                           u8 lc_addr,
3129                           u8 xfer_cnt,
3130                           u32 *data_array)
3131 {
3132         u32 val, i;
3133         int rc = 0;
3134         struct bnx2x *bp = params->bp;
3135
3136         if ((sl_devid != 0xa0) && (sl_devid != 0xa2)) {
3137                 DP(NETIF_MSG_LINK, "invalid sl_devid 0x%x\n", sl_devid);
3138                 return -EINVAL;
3139         }
3140
3141         if (xfer_cnt > 16) {
3142                 DP(NETIF_MSG_LINK, "invalid xfer_cnt %d. Max is 16 bytes\n",
3143                                         xfer_cnt);
3144                 return -EINVAL;
3145         }
3146         bnx2x_bsc_module_sel(params);
3147
3148         xfer_cnt = 16 - lc_addr;
3149
3150         /* enable the engine */
3151         val = REG_RD(bp, MCP_REG_MCPR_IMC_COMMAND);
3152         val |= MCPR_IMC_COMMAND_ENABLE;
3153         REG_WR(bp, MCP_REG_MCPR_IMC_COMMAND, val);
3154
3155         /* program slave device ID */
3156         val = (sl_devid << 16) | sl_addr;
3157         REG_WR(bp, MCP_REG_MCPR_IMC_SLAVE_CONTROL, val);
3158
3159         /* start xfer with 0 byte to update the address pointer ???*/
3160         val = (MCPR_IMC_COMMAND_ENABLE) |
3161               (MCPR_IMC_COMMAND_WRITE_OP <<
3162                 MCPR_IMC_COMMAND_OPERATION_BITSHIFT) |
3163                 (lc_addr << MCPR_IMC_COMMAND_TRANSFER_ADDRESS_BITSHIFT) | (0);
3164         REG_WR(bp, MCP_REG_MCPR_IMC_COMMAND, val);
3165
3166         /* poll for completion */
3167         i = 0;
3168         val = REG_RD(bp, MCP_REG_MCPR_IMC_COMMAND);
3169         while (((val >> MCPR_IMC_COMMAND_IMC_STATUS_BITSHIFT) & 0x3) != 1) {
3170                 udelay(10);
3171                 val = REG_RD(bp, MCP_REG_MCPR_IMC_COMMAND);
3172                 if (i++ > 1000) {
3173                         DP(NETIF_MSG_LINK, "wr 0 byte timed out after %d try\n",
3174                                                                 i);
3175                         rc = -EFAULT;
3176                         break;
3177                 }
3178         }
3179         if (rc == -EFAULT)
3180                 return rc;
3181
3182         /* start xfer with read op */
3183         val = (MCPR_IMC_COMMAND_ENABLE) |
3184                 (MCPR_IMC_COMMAND_READ_OP <<
3185                 MCPR_IMC_COMMAND_OPERATION_BITSHIFT) |
3186                 (lc_addr << MCPR_IMC_COMMAND_TRANSFER_ADDRESS_BITSHIFT) |
3187                   (xfer_cnt);
3188         REG_WR(bp, MCP_REG_MCPR_IMC_COMMAND, val);
3189
3190         /* poll for completion */
3191         i = 0;
3192         val = REG_RD(bp, MCP_REG_MCPR_IMC_COMMAND);
3193         while (((val >> MCPR_IMC_COMMAND_IMC_STATUS_BITSHIFT) & 0x3) != 1) {
3194                 udelay(10);
3195                 val = REG_RD(bp, MCP_REG_MCPR_IMC_COMMAND);
3196                 if (i++ > 1000) {
3197                         DP(NETIF_MSG_LINK, "rd op timed out after %d try\n", i);
3198                         rc = -EFAULT;
3199                         break;
3200                 }
3201         }
3202         if (rc == -EFAULT)
3203                 return rc;
3204
3205         for (i = (lc_addr >> 2); i < 4; i++) {
3206                 data_array[i] = REG_RD(bp, (MCP_REG_MCPR_IMC_DATAREG0 + i*4));
3207 #ifdef __BIG_ENDIAN
3208                 data_array[i] = ((data_array[i] & 0x000000ff) << 24) |
3209                                 ((data_array[i] & 0x0000ff00) << 8) |
3210                                 ((data_array[i] & 0x00ff0000) >> 8) |
3211                                 ((data_array[i] & 0xff000000) >> 24);
3212 #endif
3213         }
3214         return rc;
3215 }
3216
3217 static void bnx2x_cl45_read_or_write(struct bnx2x *bp, struct bnx2x_phy *phy,
3218                                      u8 devad, u16 reg, u16 or_val)
3219 {
3220         u16 val;
3221         bnx2x_cl45_read(bp, phy, devad, reg, &val);
3222         bnx2x_cl45_write(bp, phy, devad, reg, val | or_val);
3223 }
3224
3225 int bnx2x_phy_read(struct link_params *params, u8 phy_addr,
3226                    u8 devad, u16 reg, u16 *ret_val)
3227 {
3228         u8 phy_index;
3229         /*
3230          * Probe for the phy according to the given phy_addr, and execute
3231          * the read request on it
3232          */
3233         for (phy_index = 0; phy_index < params->num_phys; phy_index++) {
3234                 if (params->phy[phy_index].addr == phy_addr) {
3235                         return bnx2x_cl45_read(params->bp,
3236                                                &params->phy[phy_index], devad,
3237                                                reg, ret_val);
3238                 }
3239         }
3240         return -EINVAL;
3241 }
3242
3243 int bnx2x_phy_write(struct link_params *params, u8 phy_addr,
3244                     u8 devad, u16 reg, u16 val)
3245 {
3246         u8 phy_index;
3247         /*
3248          * Probe for the phy according to the given phy_addr, and execute
3249          * the write request on it
3250          */
3251         for (phy_index = 0; phy_index < params->num_phys; phy_index++) {
3252                 if (params->phy[phy_index].addr == phy_addr) {
3253                         return bnx2x_cl45_write(params->bp,
3254                                                 &params->phy[phy_index], devad,
3255                                                 reg, val);
3256                 }
3257         }
3258         return -EINVAL;
3259 }
3260 static u8 bnx2x_get_warpcore_lane(struct bnx2x_phy *phy,
3261                                   struct link_params *params)
3262 {
3263         u8 lane = 0;
3264         struct bnx2x *bp = params->bp;
3265         u32 path_swap, path_swap_ovr;
3266         u8 path, port;
3267
3268         path = BP_PATH(bp);
3269         port = params->port;
3270
3271         if (bnx2x_is_4_port_mode(bp)) {
3272                 u32 port_swap, port_swap_ovr;
3273
3274                 /*figure out path swap value */
3275                 path_swap_ovr = REG_RD(bp, MISC_REG_FOUR_PORT_PATH_SWAP_OVWR);
3276                 if (path_swap_ovr & 0x1)
3277                         path_swap = (path_swap_ovr & 0x2);
3278                 else
3279                         path_swap = REG_RD(bp, MISC_REG_FOUR_PORT_PATH_SWAP);
3280
3281                 if (path_swap)
3282                         path = path ^ 1;
3283
3284                 /*figure out port swap value */
3285                 port_swap_ovr = REG_RD(bp, MISC_REG_FOUR_PORT_PORT_SWAP_OVWR);
3286                 if (port_swap_ovr & 0x1)
3287                         port_swap = (port_swap_ovr & 0x2);
3288                 else
3289                         port_swap = REG_RD(bp, MISC_REG_FOUR_PORT_PORT_SWAP);
3290
3291                 if (port_swap)
3292                         port = port ^ 1;
3293
3294                 lane = (port<<1) + path;
3295         } else { /* two port mode - no port swap */
3296
3297                 /*figure out path swap value */
3298                 path_swap_ovr =
3299                         REG_RD(bp, MISC_REG_TWO_PORT_PATH_SWAP_OVWR);
3300                 if (path_swap_ovr & 0x1) {
3301                         path_swap = (path_swap_ovr & 0x2);
3302                 } else {
3303                         path_swap =
3304                                 REG_RD(bp, MISC_REG_TWO_PORT_PATH_SWAP);
3305                 }
3306                 if (path_swap)
3307                         path = path ^ 1;
3308
3309                 lane = path << 1 ;
3310         }
3311         return lane;
3312 }
3313
3314 static void bnx2x_set_aer_mmd(struct link_params *params,
3315                               struct bnx2x_phy *phy)
3316 {
3317         u32 ser_lane;
3318         u16 offset, aer_val;
3319         struct bnx2x *bp = params->bp;
3320         ser_lane = ((params->lane_config &
3321                      PORT_HW_CFG_LANE_SWAP_CFG_MASTER_MASK) >>
3322                      PORT_HW_CFG_LANE_SWAP_CFG_MASTER_SHIFT);
3323
3324         offset = (phy->type == PORT_HW_CFG_XGXS_EXT_PHY_TYPE_DIRECT) ?
3325                 (phy->addr + ser_lane) : 0;
3326
3327         if (USES_WARPCORE(bp)) {
3328                 aer_val = bnx2x_get_warpcore_lane(phy, params);
3329                 /*
3330                  * In Dual-lane mode, two lanes are joined together,
3331                  * so in order to configure them, the AER broadcast method is
3332                  * used here.
3333                  * 0x200 is the broadcast address for lanes 0,1
3334                  * 0x201 is the broadcast address for lanes 2,3
3335                  */
3336                 if (phy->flags & FLAGS_WC_DUAL_MODE)
3337                         aer_val = (aer_val >> 1) | 0x200;
3338         } else if (CHIP_IS_E2(bp))
3339                 aer_val = 0x3800 + offset - 1;
3340         else
3341                 aer_val = 0x3800 + offset;
3342         DP(NETIF_MSG_LINK, "Set AER to 0x%x\n", aer_val);
3343         CL22_WR_OVER_CL45(bp, phy, MDIO_REG_BANK_AER_BLOCK,
3344                           MDIO_AER_BLOCK_AER_REG, aer_val);
3345
3346 }
3347
3348 /******************************************************************/
3349 /*                      Internal phy section                      */
3350 /******************************************************************/
3351
3352 static void bnx2x_set_serdes_access(struct bnx2x *bp, u8 port)
3353 {
3354         u32 emac_base = (port) ? GRCBASE_EMAC1 : GRCBASE_EMAC0;
3355
3356         /* Set Clause 22 */
3357         REG_WR(bp, NIG_REG_SERDES0_CTRL_MD_ST + port*0x10, 1);
3358         REG_WR(bp, emac_base + EMAC_REG_EMAC_MDIO_COMM, 0x245f8000);
3359         udelay(500);
3360         REG_WR(bp, emac_base + EMAC_REG_EMAC_MDIO_COMM, 0x245d000f);
3361         udelay(500);
3362          /* Set Clause 45 */
3363         REG_WR(bp, NIG_REG_SERDES0_CTRL_MD_ST + port*0x10, 0);
3364 }
3365
3366 static void bnx2x_serdes_deassert(struct bnx2x *bp, u8 port)
3367 {
3368         u32 val;
3369
3370         DP(NETIF_MSG_LINK, "bnx2x_serdes_deassert\n");
3371
3372         val = SERDES_RESET_BITS << (port*16);
3373
3374         /* reset and unreset the SerDes/XGXS */
3375         REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_3_CLEAR, val);
3376         udelay(500);
3377         REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_3_SET, val);
3378
3379         bnx2x_set_serdes_access(bp, port);
3380
3381         REG_WR(bp, NIG_REG_SERDES0_CTRL_MD_DEVAD + port*0x10,
3382                DEFAULT_PHY_DEV_ADDR);
3383 }
3384
3385 static void bnx2x_xgxs_deassert(struct link_params *params)
3386 {
3387         struct bnx2x *bp = params->bp;
3388         u8 port;
3389         u32 val;
3390         DP(NETIF_MSG_LINK, "bnx2x_xgxs_deassert\n");
3391         port = params->port;
3392
3393         val = XGXS_RESET_BITS << (port*16);
3394
3395         /* reset and unreset the SerDes/XGXS */
3396         REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_3_CLEAR, val);
3397         udelay(500);
3398         REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_3_SET, val);
3399
3400         REG_WR(bp, NIG_REG_XGXS0_CTRL_MD_ST + port*0x18, 0);
3401         REG_WR(bp, NIG_REG_XGXS0_CTRL_MD_DEVAD + port*0x18,
3402                params->phy[INT_PHY].def_md_devad);
3403 }
3404
3405 static void bnx2x_calc_ieee_aneg_adv(struct bnx2x_phy *phy,
3406                                      struct link_params *params, u16 *ieee_fc)
3407 {
3408         struct bnx2x *bp = params->bp;
3409         *ieee_fc = MDIO_COMBO_IEEE0_AUTO_NEG_ADV_FULL_DUPLEX;
3410         /**
3411          * resolve pause mode and advertisement Please refer to Table
3412          * 28B-3 of the 802.3ab-1999 spec
3413          */
3414
3415         switch (phy->req_flow_ctrl) {
3416         case BNX2X_FLOW_CTRL_AUTO:
3417                 if (params->req_fc_auto_adv == BNX2X_FLOW_CTRL_BOTH)
3418                         *ieee_fc |= MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_BOTH;
3419                 else
3420                         *ieee_fc |=
3421                         MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_ASYMMETRIC;
3422                 break;
3423
3424         case BNX2X_FLOW_CTRL_TX:
3425                 *ieee_fc |= MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_ASYMMETRIC;
3426                 break;
3427
3428         case BNX2X_FLOW_CTRL_RX:
3429         case BNX2X_FLOW_CTRL_BOTH:
3430                 *ieee_fc |= MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_BOTH;
3431                 break;
3432
3433         case BNX2X_FLOW_CTRL_NONE:
3434         default:
3435                 *ieee_fc |= MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_NONE;
3436                 break;
3437         }
3438         DP(NETIF_MSG_LINK, "ieee_fc = 0x%x\n", *ieee_fc);
3439 }
3440
3441 static void set_phy_vars(struct link_params *params,
3442                          struct link_vars *vars)
3443 {
3444         struct bnx2x *bp = params->bp;
3445         u8 actual_phy_idx, phy_index, link_cfg_idx;
3446         u8 phy_config_swapped = params->multi_phy_config &
3447                         PORT_HW_CFG_PHY_SWAPPED_ENABLED;
3448         for (phy_index = INT_PHY; phy_index < params->num_phys;
3449               phy_index++) {
3450                 link_cfg_idx = LINK_CONFIG_IDX(phy_index);
3451                 actual_phy_idx = phy_index;
3452                 if (phy_config_swapped) {
3453                         if (phy_index == EXT_PHY1)
3454                                 actual_phy_idx = EXT_PHY2;
3455                         else if (phy_index == EXT_PHY2)
3456                                 actual_phy_idx = EXT_PHY1;
3457                 }
3458                 params->phy[actual_phy_idx].req_flow_ctrl =
3459                         params->req_flow_ctrl[link_cfg_idx];
3460
3461                 params->phy[actual_phy_idx].req_line_speed =
3462                         params->req_line_speed[link_cfg_idx];
3463
3464                 params->phy[actual_phy_idx].speed_cap_mask =
3465                         params->speed_cap_mask[link_cfg_idx];
3466
3467                 params->phy[actual_phy_idx].req_duplex =
3468                         params->req_duplex[link_cfg_idx];
3469
3470                 if (params->req_line_speed[link_cfg_idx] ==
3471                     SPEED_AUTO_NEG)
3472                         vars->link_status |= LINK_STATUS_AUTO_NEGOTIATE_ENABLED;
3473
3474                 DP(NETIF_MSG_LINK, "req_flow_ctrl %x, req_line_speed %x,"
3475                            " speed_cap_mask %x\n",
3476                            params->phy[actual_phy_idx].req_flow_ctrl,
3477                            params->phy[actual_phy_idx].req_line_speed,
3478                            params->phy[actual_phy_idx].speed_cap_mask);
3479         }
3480 }
3481
3482 static void bnx2x_ext_phy_set_pause(struct link_params *params,
3483                                     struct bnx2x_phy *phy,
3484                                     struct link_vars *vars)
3485 {
3486         u16 val;
3487         struct bnx2x *bp = params->bp;
3488         /* read modify write pause advertizing */
3489         bnx2x_cl45_read(bp, phy, MDIO_AN_DEVAD, MDIO_AN_REG_ADV_PAUSE, &val);
3490
3491         val &= ~MDIO_AN_REG_ADV_PAUSE_BOTH;
3492
3493         /* Please refer to Table 28B-3 of 802.3ab-1999 spec. */
3494         bnx2x_calc_ieee_aneg_adv(phy, params, &vars->ieee_fc);
3495         if ((vars->ieee_fc &
3496             MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_ASYMMETRIC) ==
3497             MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_ASYMMETRIC) {
3498                 val |= MDIO_AN_REG_ADV_PAUSE_ASYMMETRIC;
3499         }
3500         if ((vars->ieee_fc &
3501             MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_BOTH) ==
3502             MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_BOTH) {
3503                 val |= MDIO_AN_REG_ADV_PAUSE_PAUSE;
3504         }
3505         DP(NETIF_MSG_LINK, "Ext phy AN advertize 0x%x\n", val);
3506         bnx2x_cl45_write(bp, phy, MDIO_AN_DEVAD, MDIO_AN_REG_ADV_PAUSE, val);
3507 }
3508
3509 static void bnx2x_pause_resolve(struct link_vars *vars, u32 pause_result)
3510 {                                               /*  LD      LP   */
3511         switch (pause_result) {                 /* ASYM P ASYM P */
3512         case 0xb:                               /*   1  0   1  1 */
3513                 vars->flow_ctrl = BNX2X_FLOW_CTRL_TX;
3514                 break;
3515
3516         case 0xe:                               /*   1  1   1  0 */
3517                 vars->flow_ctrl = BNX2X_FLOW_CTRL_RX;
3518                 break;
3519
3520         case 0x5:                               /*   0  1   0  1 */
3521         case 0x7:                               /*   0  1   1  1 */
3522         case 0xd:                               /*   1  1   0  1 */
3523         case 0xf:                               /*   1  1   1  1 */
3524                 vars->flow_ctrl = BNX2X_FLOW_CTRL_BOTH;
3525                 break;
3526
3527         default:
3528                 break;
3529         }
3530         if (pause_result & (1<<0))
3531                 vars->link_status |= LINK_STATUS_LINK_PARTNER_SYMMETRIC_PAUSE;
3532         if (pause_result & (1<<1))
3533                 vars->link_status |= LINK_STATUS_LINK_PARTNER_ASYMMETRIC_PAUSE;
3534 }
3535
3536 static u8 bnx2x_ext_phy_resolve_fc(struct bnx2x_phy *phy,
3537                                    struct link_params *params,
3538                                    struct link_vars *vars)
3539 {
3540         struct bnx2x *bp = params->bp;
3541         u16 ld_pause;           /* local */
3542         u16 lp_pause;           /* link partner */
3543         u16 pause_result;
3544         u8 ret = 0;
3545         /* read twice */
3546
3547         vars->flow_ctrl = BNX2X_FLOW_CTRL_NONE;
3548
3549         if (phy->req_flow_ctrl != BNX2X_FLOW_CTRL_AUTO)
3550                 vars->flow_ctrl = phy->req_flow_ctrl;
3551         else if (phy->req_line_speed != SPEED_AUTO_NEG)
3552                 vars->flow_ctrl = params->req_fc_auto_adv;
3553         else if (vars->link_status & LINK_STATUS_AUTO_NEGOTIATE_COMPLETE) {
3554                 ret = 1;
3555                 if (phy->type == PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM54618SE) {
3556                         bnx2x_cl22_read(bp, phy,
3557                                         0x4, &ld_pause);
3558                         bnx2x_cl22_read(bp, phy,
3559                                         0x5, &lp_pause);
3560                 } else {
3561                         bnx2x_cl45_read(bp, phy,
3562                                         MDIO_AN_DEVAD,
3563                                         MDIO_AN_REG_ADV_PAUSE, &ld_pause);
3564                         bnx2x_cl45_read(bp, phy,
3565                                         MDIO_AN_DEVAD,
3566                                         MDIO_AN_REG_LP_AUTO_NEG, &lp_pause);
3567                 }
3568                 pause_result = (ld_pause &
3569                                 MDIO_AN_REG_ADV_PAUSE_MASK) >> 8;
3570                 pause_result |= (lp_pause &
3571                                  MDIO_AN_REG_ADV_PAUSE_MASK) >> 10;
3572                 DP(NETIF_MSG_LINK, "Ext PHY pause result 0x%x\n",
3573                    pause_result);
3574                 bnx2x_pause_resolve(vars, pause_result);
3575         }
3576         return ret;
3577 }
3578 /******************************************************************/
3579 /*                      Warpcore section                          */
3580 /******************************************************************/
3581 /* The init_internal_warpcore should mirror the xgxs,
3582  * i.e. reset the lane (if needed), set aer for the
3583  * init configuration, and set/clear SGMII flag. Internal
3584  * phy init is done purely in phy_init stage.
3585  */
3586 static void bnx2x_warpcore_enable_AN_KR(struct bnx2x_phy *phy,
3587                                         struct link_params *params,
3588                                         struct link_vars *vars) {
3589         u16 val16 = 0, lane, bam37 = 0;
3590         struct bnx2x *bp = params->bp;
3591         DP(NETIF_MSG_LINK, "Enable Auto Negotiation for KR\n");
3592
3593         /* Disable Autoneg: re-enable it after adv is done. */
3594         bnx2x_cl45_write(bp, phy, MDIO_AN_DEVAD,
3595                          MDIO_WC_REG_IEEE0BLK_MIICNTL, 0);
3596
3597         /* Check adding advertisement for 1G KX */
3598         if (((vars->line_speed == SPEED_AUTO_NEG) &&
3599              (phy->speed_cap_mask & PORT_HW_CFG_SPEED_CAPABILITY_D0_1G)) ||
3600             (vars->line_speed == SPEED_1000)) {
3601                 u16 sd_digital;
3602                 val16 |= (1<<5);
3603
3604                 /* Enable CL37 1G Parallel Detect */
3605                 bnx2x_cl45_read(bp, phy, MDIO_WC_DEVAD,
3606                         MDIO_WC_REG_SERDESDIGITAL_CONTROL1000X2, &sd_digital);
3607                 bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,
3608                          MDIO_WC_REG_SERDESDIGITAL_CONTROL1000X2,
3609                                  (sd_digital | 0x1));
3610
3611                 DP(NETIF_MSG_LINK, "Advertize 1G\n");
3612         }
3613         if (((vars->line_speed == SPEED_AUTO_NEG) &&
3614              (phy->speed_cap_mask & PORT_HW_CFG_SPEED_CAPABILITY_D0_10G)) ||
3615             (vars->line_speed ==  SPEED_10000)) {
3616                 /* Check adding advertisement for 10G KR */
3617                 val16 |= (1<<7);
3618                 /* Enable 10G Parallel Detect */
3619                 bnx2x_cl45_write(bp, phy, MDIO_AN_DEVAD,
3620                                 MDIO_WC_REG_PAR_DET_10G_CTRL, 1);
3621
3622                 DP(NETIF_MSG_LINK, "Advertize 10G\n");
3623         }
3624
3625         /* Set Transmit PMD settings */
3626         lane = bnx2x_get_warpcore_lane(phy, params);
3627         bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,
3628                       MDIO_WC_REG_TX0_TX_DRIVER + 0x10*lane,
3629                      ((0x02 << MDIO_WC_REG_TX0_TX_DRIVER_POST2_COEFF_OFFSET) |
3630                       (0x06 << MDIO_WC_REG_TX0_TX_DRIVER_IDRIVER_OFFSET) |
3631                       (0x09 << MDIO_WC_REG_TX0_TX_DRIVER_IPRE_DRIVER_OFFSET)));
3632         bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,
3633                          MDIO_WC_REG_CL72_USERB0_CL72_OS_DEF_CTRL,
3634                          0x03f0);
3635         bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,
3636                          MDIO_WC_REG_CL72_USERB0_CL72_2P5_DEF_CTRL,
3637                          0x03f0);
3638
3639         /* Advertised speeds */
3640         bnx2x_cl45_write(bp, phy, MDIO_AN_DEVAD,
3641                          MDIO_WC_REG_AN_IEEE1BLK_AN_ADVERTISEMENT1, val16);
3642
3643         /* Advertised and set FEC (Forward Error Correction) */
3644         bnx2x_cl45_write(bp, phy, MDIO_AN_DEVAD,
3645                          MDIO_WC_REG_AN_IEEE1BLK_AN_ADVERTISEMENT2,
3646                          (MDIO_WC_REG_AN_IEEE1BLK_AN_ADV2_FEC_ABILITY |
3647                           MDIO_WC_REG_AN_IEEE1BLK_AN_ADV2_FEC_REQ));
3648
3649         /* Enable CL37 BAM */
3650         if (REG_RD(bp, params->shmem_base +
3651                    offsetof(struct shmem_region, dev_info.
3652                             port_hw_config[params->port].default_cfg)) &
3653             PORT_HW_CFG_ENABLE_BAM_ON_KR_ENABLED) {
3654                 bnx2x_cl45_read(bp, phy, MDIO_WC_DEVAD,
3655                                 MDIO_WC_REG_DIGITAL6_MP5_NEXTPAGECTRL, &bam37);
3656                 bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,
3657                         MDIO_WC_REG_DIGITAL6_MP5_NEXTPAGECTRL, bam37 | 1);
3658                 DP(NETIF_MSG_LINK, "Enable CL37 BAM on KR\n");
3659         }
3660
3661         /* Advertise pause */
3662         bnx2x_ext_phy_set_pause(params, phy, vars);
3663
3664         vars->rx_tx_asic_rst = MAX_KR_LINK_RETRY;
3665
3666         bnx2x_cl45_read(bp, phy, MDIO_WC_DEVAD,
3667                         MDIO_WC_REG_DIGITAL5_MISC7, &val16);
3668
3669         bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,
3670                          MDIO_WC_REG_DIGITAL5_MISC7, val16 | 0x100);
3671
3672         /* Over 1G - AN local device user page 1 */
3673         bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,
3674                         MDIO_WC_REG_DIGITAL3_UP1, 0x1f);
3675
3676         /* Enable Autoneg */
3677         bnx2x_cl45_write(bp, phy, MDIO_AN_DEVAD,
3678                          MDIO_WC_REG_IEEE0BLK_MIICNTL, 0x1000);
3679
3680 }
3681
3682 static void bnx2x_warpcore_set_10G_KR(struct bnx2x_phy *phy,
3683                                       struct link_params *params,
3684                                       struct link_vars *vars)
3685 {
3686         struct bnx2x *bp = params->bp;
3687         u16 val;
3688
3689         /* Disable Autoneg */
3690         bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,
3691                          MDIO_WC_REG_SERDESDIGITAL_CONTROL1000X2, 0x7);
3692
3693         bnx2x_cl45_write(bp, phy, MDIO_AN_DEVAD,
3694                          MDIO_WC_REG_PAR_DET_10G_CTRL, 0);
3695
3696         bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,
3697                          MDIO_WC_REG_CL72_USERB0_CL72_MISC1_CONTROL, 0x3f00);
3698
3699         bnx2x_cl45_write(bp, phy, MDIO_AN_DEVAD,
3700                          MDIO_WC_REG_AN_IEEE1BLK_AN_ADVERTISEMENT1, 0);
3701
3702         bnx2x_cl45_write(bp, phy, MDIO_AN_DEVAD,
3703                          MDIO_WC_REG_IEEE0BLK_MIICNTL, 0x0);
3704
3705         bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,
3706                         MDIO_WC_REG_DIGITAL3_UP1, 0x1);
3707
3708         bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,
3709                          MDIO_WC_REG_DIGITAL5_MISC7, 0xa);
3710
3711         /* Disable CL36 PCS Tx */
3712         bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,
3713                         MDIO_WC_REG_XGXSBLK1_LANECTRL0, 0x0);
3714
3715         /* Double Wide Single Data Rate @ pll rate */
3716         bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,
3717                         MDIO_WC_REG_XGXSBLK1_LANECTRL1, 0xFFFF);
3718
3719         /* Leave cl72 training enable, needed for KR */
3720         bnx2x_cl45_write(bp, phy, MDIO_PMA_DEVAD,
3721                 MDIO_WC_REG_PMD_IEEE9BLK_TENGBASE_KR_PMD_CONTROL_REGISTER_150,
3722                 0x2);
3723
3724         /* Leave CL72 enabled */
3725         bnx2x_cl45_read(bp, phy, MDIO_WC_DEVAD,
3726                          MDIO_WC_REG_CL72_USERB0_CL72_MISC1_CONTROL,
3727                          &val);
3728         bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,
3729                          MDIO_WC_REG_CL72_USERB0_CL72_MISC1_CONTROL,
3730                          val | 0x3800);
3731
3732         /* Set speed via PMA/PMD register */
3733         bnx2x_cl45_write(bp, phy, MDIO_PMA_DEVAD,
3734                          MDIO_WC_REG_IEEE0BLK_MIICNTL, 0x2040);
3735
3736         bnx2x_cl45_write(bp, phy, MDIO_PMA_DEVAD,
3737                          MDIO_WC_REG_IEEE0BLK_AUTONEGNP, 0xB);
3738
3739         /*Enable encoded forced speed */
3740         bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,
3741                          MDIO_WC_REG_SERDESDIGITAL_MISC2, 0x30);
3742
3743         /* Turn TX scramble payload only the 64/66 scrambler */
3744         bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,
3745                          MDIO_WC_REG_TX66_CONTROL, 0x9);
3746
3747         /* Turn RX scramble payload only the 64/66 scrambler */
3748         bnx2x_cl45_read_or_write(bp, phy, MDIO_WC_DEVAD,
3749                                  MDIO_WC_REG_RX66_CONTROL, 0xF9);
3750
3751         /* set and clear loopback to cause a reset to 64/66 decoder */
3752         bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,
3753                          MDIO_WC_REG_IEEE0BLK_MIICNTL, 0x4000);
3754         bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,
3755                          MDIO_WC_REG_IEEE0BLK_MIICNTL, 0x0);
3756
3757 }
3758
3759 static void bnx2x_warpcore_set_10G_XFI(struct bnx2x_phy *phy,
3760                                        struct link_params *params,
3761                                        u8 is_xfi)
3762 {
3763         struct bnx2x *bp = params->bp;
3764         u16 misc1_val, tap_val, tx_driver_val, lane, val;
3765         /* Hold rxSeqStart */
3766         bnx2x_cl45_read(bp, phy, MDIO_WC_DEVAD,
3767                         MDIO_WC_REG_DSC2B0_DSC_MISC_CTRL0, &val);
3768         bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,
3769                          MDIO_WC_REG_DSC2B0_DSC_MISC_CTRL0, (val | 0x8000));
3770
3771         /* Hold tx_fifo_reset */
3772         bnx2x_cl45_read(bp, phy, MDIO_WC_DEVAD,
3773                         MDIO_WC_REG_SERDESDIGITAL_CONTROL1000X3, &val);
3774         bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,
3775                          MDIO_WC_REG_SERDESDIGITAL_CONTROL1000X3, (val | 0x1));
3776
3777         /* Disable CL73 AN */
3778         bnx2x_cl45_write(bp, phy, MDIO_AN_DEVAD, MDIO_AN_REG_CTRL, 0);
3779
3780         /* Disable 100FX Enable and Auto-Detect */
3781         bnx2x_cl45_read(bp, phy, MDIO_WC_DEVAD,
3782                         MDIO_WC_REG_FX100_CTRL1, &val);
3783         bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,
3784                          MDIO_WC_REG_FX100_CTRL1, (val & 0xFFFA));
3785
3786         /* Disable 100FX Idle detect */
3787         bnx2x_cl45_read(bp, phy, MDIO_WC_DEVAD,
3788                         MDIO_WC_REG_FX100_CTRL3, &val);
3789         bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,
3790                          MDIO_WC_REG_FX100_CTRL3, (val | 0x0080));
3791
3792         /* Set Block address to Remote PHY & Clear forced_speed[5] */
3793         bnx2x_cl45_read(bp, phy, MDIO_WC_DEVAD,
3794                         MDIO_WC_REG_DIGITAL4_MISC3, &val);
3795         bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,
3796                          MDIO_WC_REG_DIGITAL4_MISC3, (val & 0xFF7F));
3797
3798         /* Turn off auto-detect & fiber mode */
3799         bnx2x_cl45_read(bp, phy, MDIO_WC_DEVAD,
3800                         MDIO_WC_REG_SERDESDIGITAL_CONTROL1000X1, &val);
3801         bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,
3802                          MDIO_WC_REG_SERDESDIGITAL_CONTROL1000X1,
3803                          (val & 0xFFEE));
3804
3805         /* Set filter_force_link, disable_false_link and parallel_detect */
3806         bnx2x_cl45_read(bp, phy, MDIO_WC_DEVAD,
3807                         MDIO_WC_REG_SERDESDIGITAL_CONTROL1000X2, &val);
3808         bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,
3809                          MDIO_WC_REG_SERDESDIGITAL_CONTROL1000X2,
3810                          ((val | 0x0006) & 0xFFFE));
3811
3812         /* Set XFI / SFI */
3813         bnx2x_cl45_read(bp, phy, MDIO_WC_DEVAD,
3814                         MDIO_WC_REG_SERDESDIGITAL_MISC1, &misc1_val);
3815
3816         misc1_val &= ~(0x1f);
3817
3818         if (is_xfi) {
3819                 misc1_val |= 0x5;
3820                 tap_val = ((0x08 << MDIO_WC_REG_TX_FIR_TAP_POST_TAP_OFFSET) |
3821                            (0x37 << MDIO_WC_REG_TX_FIR_TAP_MAIN_TAP_OFFSET) |
3822                            (0x00 << MDIO_WC_REG_TX_FIR_TAP_PRE_TAP_OFFSET));
3823                 tx_driver_val =
3824                       ((0x00 << MDIO_WC_REG_TX0_TX_DRIVER_POST2_COEFF_OFFSET) |
3825                        (0x02 << MDIO_WC_REG_TX0_TX_DRIVER_IDRIVER_OFFSET) |
3826                        (0x03 << MDIO_WC_REG_TX0_TX_DRIVER_IPRE_DRIVER_OFFSET));
3827
3828         } else {
3829                 misc1_val |= 0x9;
3830                 tap_val = ((0x12 << MDIO_WC_REG_TX_FIR_TAP_POST_TAP_OFFSET) |
3831                            (0x2d << MDIO_WC_REG_TX_FIR_TAP_MAIN_TAP_OFFSET) |
3832                            (0x00 << MDIO_WC_REG_TX_FIR_TAP_PRE_TAP_OFFSET));
3833                 tx_driver_val =
3834                       ((0x02 << MDIO_WC_REG_TX0_TX_DRIVER_POST2_COEFF_OFFSET) |
3835                        (0x02 << MDIO_WC_REG_TX0_TX_DRIVER_IDRIVER_OFFSET) |
3836                        (0x02 << MDIO_WC_REG_TX0_TX_DRIVER_IPRE_DRIVER_OFFSET));
3837         }
3838         bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,
3839                          MDIO_WC_REG_SERDESDIGITAL_MISC1, misc1_val);
3840
3841         /* Set Transmit PMD settings */
3842         lane = bnx2x_get_warpcore_lane(phy, params);
3843         bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,
3844                          MDIO_WC_REG_TX_FIR_TAP,
3845                          tap_val | MDIO_WC_REG_TX_FIR_TAP_ENABLE);
3846         bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,
3847                          MDIO_WC_REG_TX0_TX_DRIVER + 0x10*lane,
3848                          tx_driver_val);
3849
3850         /* Enable fiber mode, enable and invert sig_det */
3851         bnx2x_cl45_read(bp, phy, MDIO_WC_DEVAD,
3852                         MDIO_WC_REG_SERDESDIGITAL_CONTROL1000X1, &val);
3853         bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,
3854                          MDIO_WC_REG_SERDESDIGITAL_CONTROL1000X1, val | 0xd);
3855
3856         /* Set Block address to Remote PHY & Set forced_speed[5], 40bit mode */
3857         bnx2x_cl45_read(bp, phy, MDIO_WC_DEVAD,
3858                         MDIO_WC_REG_DIGITAL4_MISC3, &val);
3859         bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,
3860                          MDIO_WC_REG_DIGITAL4_MISC3, val | 0x8080);
3861
3862         /* 10G XFI Full Duplex */
3863         bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,
3864                          MDIO_WC_REG_IEEE0BLK_MIICNTL, 0x100);
3865
3866         /* Release tx_fifo_reset */
3867         bnx2x_cl45_read(bp, phy, MDIO_WC_DEVAD,
3868                         MDIO_WC_REG_SERDESDIGITAL_CONTROL1000X3, &val);
3869         bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,
3870                          MDIO_WC_REG_SERDESDIGITAL_CONTROL1000X3, val & 0xFFFE);
3871
3872         /* Release rxSeqStart */
3873         bnx2x_cl45_read(bp, phy, MDIO_WC_DEVAD,
3874                         MDIO_WC_REG_DSC2B0_DSC_MISC_CTRL0, &val);
3875         bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,
3876                          MDIO_WC_REG_DSC2B0_DSC_MISC_CTRL0, (val & 0x7FFF));
3877 }
3878
3879 static void bnx2x_warpcore_set_20G_KR2(struct bnx2x *bp,
3880                                        struct bnx2x_phy *phy)
3881 {
3882         DP(NETIF_MSG_LINK, "KR2 still not supported !!!\n");
3883 }
3884
3885 static void bnx2x_warpcore_set_20G_DXGXS(struct bnx2x *bp,
3886                                          struct bnx2x_phy *phy,
3887                                          u16 lane)
3888 {
3889         /* Rx0 anaRxControl1G */
3890         bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,
3891                          MDIO_WC_REG_RX0_ANARXCONTROL1G, 0x90);
3892
3893         /* Rx2 anaRxControl1G */
3894         bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,
3895                          MDIO_WC_REG_RX2_ANARXCONTROL1G, 0x90);
3896
3897         bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,
3898                          MDIO_WC_REG_RX66_SCW0, 0xE070);
3899
3900         bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,
3901                          MDIO_WC_REG_RX66_SCW1, 0xC0D0);
3902
3903         bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,
3904                          MDIO_WC_REG_RX66_SCW2, 0xA0B0);
3905
3906         bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,
3907                          MDIO_WC_REG_RX66_SCW3, 0x8090);
3908
3909         bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,
3910                          MDIO_WC_REG_RX66_SCW0_MASK, 0xF0F0);
3911
3912         bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,
3913                          MDIO_WC_REG_RX66_SCW1_MASK, 0xF0F0);
3914
3915         bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,
3916                          MDIO_WC_REG_RX66_SCW2_MASK, 0xF0F0);
3917
3918         bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,
3919                          MDIO_WC_REG_RX66_SCW3_MASK, 0xF0F0);
3920
3921         /* Serdes Digital Misc1 */
3922         bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,
3923                          MDIO_WC_REG_SERDESDIGITAL_MISC1, 0x6008);
3924
3925         /* Serdes Digital4 Misc3 */
3926         bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,
3927                          MDIO_WC_REG_DIGITAL4_MISC3, 0x8088);
3928
3929         /* Set Transmit PMD settings */
3930         bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,
3931                          MDIO_WC_REG_TX_FIR_TAP,
3932                         ((0x12 << MDIO_WC_REG_TX_FIR_TAP_POST_TAP_OFFSET) |
3933                          (0x2d << MDIO_WC_REG_TX_FIR_TAP_MAIN_TAP_OFFSET) |
3934                          (0x00 << MDIO_WC_REG_TX_FIR_TAP_PRE_TAP_OFFSET) |
3935                          MDIO_WC_REG_TX_FIR_TAP_ENABLE));
3936         bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,
3937                       MDIO_WC_REG_TX0_TX_DRIVER + 0x10*lane,
3938                      ((0x02 << MDIO_WC_REG_TX0_TX_DRIVER_POST2_COEFF_OFFSET) |
3939                       (0x02 << MDIO_WC_REG_TX0_TX_DRIVER_IDRIVER_OFFSET) |
3940                       (0x02 << MDIO_WC_REG_TX0_TX_DRIVER_IPRE_DRIVER_OFFSET)));
3941 }
3942
3943 static void bnx2x_warpcore_set_sgmii_speed(struct bnx2x_phy *phy,
3944                                            struct link_params *params,
3945                                            u8 fiber_mode)
3946 {
3947         struct bnx2x *bp = params->bp;
3948         u16 val16, digctrl_kx1, digctrl_kx2;
3949         u8 lane;
3950
3951         lane = bnx2x_get_warpcore_lane(phy, params);
3952
3953         /* Clear XFI clock comp in non-10G single lane mode. */
3954         bnx2x_cl45_read(bp, phy, MDIO_WC_DEVAD,
3955                         MDIO_WC_REG_RX66_CONTROL, &val16);
3956         bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,
3957                          MDIO_WC_REG_RX66_CONTROL, val16 & ~(3<<13));
3958
3959         if (phy->req_line_speed == SPEED_AUTO_NEG) {
3960                 /* SGMII Autoneg */
3961                 bnx2x_cl45_read(bp, phy, MDIO_WC_DEVAD,
3962                                 MDIO_WC_REG_COMBO_IEEE0_MIICTRL, &val16);
3963                 bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,
3964                                  MDIO_WC_REG_COMBO_IEEE0_MIICTRL,
3965                                  val16 | 0x1000);
3966                 DP(NETIF_MSG_LINK, "set SGMII AUTONEG\n");
3967         } else {
3968                 bnx2x_cl45_read(bp, phy, MDIO_WC_DEVAD,
3969                                 MDIO_WC_REG_COMBO_IEEE0_MIICTRL, &val16);
3970                 val16 &= 0xcfbf;
3971                 switch (phy->req_line_speed) {
3972                 case SPEED_10:
3973                         break;
3974                 case SPEED_100:
3975                         val16 |= 0x2000;
3976                         break;
3977                 case SPEED_1000:
3978                         val16 |= 0x0040;
3979                         break;
3980                 default:
3981                         DP(NETIF_MSG_LINK,
3982                            "Speed not supported: 0x%x\n", phy->req_line_speed);
3983                         return;
3984                 }
3985
3986                 if (phy->req_duplex == DUPLEX_FULL)
3987                         val16 |= 0x0100;
3988
3989                 bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,
3990                                 MDIO_WC_REG_COMBO_IEEE0_MIICTRL, val16);
3991
3992                 DP(NETIF_MSG_LINK, "set SGMII force speed %d\n",
3993                                phy->req_line_speed);
3994                 bnx2x_cl45_read(bp, phy, MDIO_WC_DEVAD,
3995                                 MDIO_WC_REG_COMBO_IEEE0_MIICTRL, &val16);
3996                 DP(NETIF_MSG_LINK, "  (readback) %x\n", val16);
3997         }
3998
3999         /* SGMII Slave mode and disable signal detect */
4000         bnx2x_cl45_read(bp, phy, MDIO_WC_DEVAD,
4001                         MDIO_WC_REG_SERDESDIGITAL_CONTROL1000X1, &digctrl_kx1);
4002         if (fiber_mode)
4003                 digctrl_kx1 = 1;
4004         else
4005                 digctrl_kx1 &= 0xff4a;
4006
4007         bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,
4008                         MDIO_WC_REG_SERDESDIGITAL_CONTROL1000X1,
4009                         digctrl_kx1);
4010
4011         /* Turn off parallel detect */
4012         bnx2x_cl45_read(bp, phy, MDIO_WC_DEVAD,
4013                         MDIO_WC_REG_SERDESDIGITAL_CONTROL1000X2, &digctrl_kx2);
4014         bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,
4015                         MDIO_WC_REG_SERDESDIGITAL_CONTROL1000X2,
4016                         (digctrl_kx2 & ~(1<<2)));
4017
4018         /* Re-enable parallel detect */
4019         bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,
4020                         MDIO_WC_REG_SERDESDIGITAL_CONTROL1000X2,
4021                         (digctrl_kx2 | (1<<2)));
4022
4023         /* Enable autodet */
4024         bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,
4025                         MDIO_WC_REG_SERDESDIGITAL_CONTROL1000X1,
4026                         (digctrl_kx1 | 0x10));
4027 }
4028
4029 static void bnx2x_warpcore_reset_lane(struct bnx2x *bp,
4030                                       struct bnx2x_phy *phy,
4031                                       u8 reset)
4032 {
4033         u16 val;
4034         /* Take lane out of reset after configuration is finished */
4035         bnx2x_cl45_read(bp, phy, MDIO_WC_DEVAD,
4036                         MDIO_WC_REG_DIGITAL5_MISC6, &val);
4037         if (reset)
4038                 val |= 0xC000;
4039         else
4040                 val &= 0x3FFF;
4041         bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,
4042                          MDIO_WC_REG_DIGITAL5_MISC6, val);
4043         bnx2x_cl45_read(bp, phy, MDIO_WC_DEVAD,
4044                          MDIO_WC_REG_DIGITAL5_MISC6, &val);
4045 }
4046
4047
4048         /* Clear SFI/XFI link settings registers */
4049 static void bnx2x_warpcore_clear_regs(struct bnx2x_phy *phy,
4050                                       struct link_params *params,
4051                                       u16 lane)
4052 {
4053         struct bnx2x *bp = params->bp;
4054         u16 val16;
4055
4056         /* Set XFI clock comp as default. */
4057         bnx2x_cl45_read(bp, phy, MDIO_WC_DEVAD,
4058                         MDIO_WC_REG_RX66_CONTROL, &val16);
4059         bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,
4060                          MDIO_WC_REG_RX66_CONTROL, val16 | (3<<13));
4061
4062         bnx2x_warpcore_reset_lane(bp, phy, 1);
4063         bnx2x_cl45_write(bp, phy, MDIO_AN_DEVAD, MDIO_AN_REG_CTRL, 0);
4064         bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,
4065                          MDIO_WC_REG_FX100_CTRL1, 0x014a);
4066         bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,
4067                          MDIO_WC_REG_FX100_CTRL3, 0x0800);
4068         bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,
4069                          MDIO_WC_REG_DIGITAL4_MISC3, 0x8008);
4070         bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,
4071                          MDIO_WC_REG_SERDESDIGITAL_CONTROL1000X1, 0x0195);
4072         bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,
4073                          MDIO_WC_REG_SERDESDIGITAL_CONTROL1000X2, 0x0007);
4074         bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,
4075                          MDIO_WC_REG_SERDESDIGITAL_CONTROL1000X3, 0x0002);
4076         bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,
4077                          MDIO_WC_REG_SERDESDIGITAL_MISC1, 0x6000);
4078         lane = bnx2x_get_warpcore_lane(phy, params);
4079         bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,
4080                          MDIO_WC_REG_TX_FIR_TAP, 0x0000);
4081         bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,
4082                          MDIO_WC_REG_TX0_TX_DRIVER + 0x10*lane, 0x0990);
4083         bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,
4084                          MDIO_WC_REG_IEEE0BLK_MIICNTL, 0x2040);
4085         bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,
4086                          MDIO_WC_REG_COMBO_IEEE0_MIICTRL, 0x0140);
4087         bnx2x_warpcore_reset_lane(bp, phy, 0);
4088 }
4089
4090 static int bnx2x_get_mod_abs_int_cfg(struct bnx2x *bp,
4091                                                 u32 chip_id,
4092                                                 u32 shmem_base, u8 port,
4093                                                 u8 *gpio_num, u8 *gpio_port)
4094 {
4095         u32 cfg_pin;
4096         *gpio_num = 0;
4097         *gpio_port = 0;
4098         if (CHIP_IS_E3(bp)) {
4099                 cfg_pin = (REG_RD(bp, shmem_base +
4100                                 offsetof(struct shmem_region,
4101                                 dev_info.port_hw_config[port].e3_sfp_ctrl)) &
4102                                 PORT_HW_CFG_E3_MOD_ABS_MASK) >>
4103                                 PORT_HW_CFG_E3_MOD_ABS_SHIFT;
4104
4105                 /*
4106                  * Should not happen. This function called upon interrupt
4107                  * triggered by GPIO ( since EPIO can only generate interrupts
4108                  * to MCP).
4109                  * So if this function was called and none of the GPIOs was set,
4110                  * it means the shit hit the fan.
4111                  */
4112                 if ((cfg_pin < PIN_CFG_GPIO0_P0) ||
4113                     (cfg_pin > PIN_CFG_GPIO3_P1)) {
4114                         DP(NETIF_MSG_LINK,
4115                            "ERROR: Invalid cfg pin %x for module detect indication\n",
4116                            cfg_pin);
4117                         return -EINVAL;
4118                 }
4119
4120                 *gpio_num = (cfg_pin - PIN_CFG_GPIO0_P0) & 0x3;
4121                 *gpio_port = (cfg_pin - PIN_CFG_GPIO0_P0) >> 2;
4122         } else {
4123                 *gpio_num = MISC_REGISTERS_GPIO_3;
4124                 *gpio_port = port;
4125         }
4126         DP(NETIF_MSG_LINK, "MOD_ABS int GPIO%d_P%d\n", *gpio_num, *gpio_port);
4127         return 0;
4128 }
4129
4130 static int bnx2x_is_sfp_module_plugged(struct bnx2x_phy *phy,
4131                                        struct link_params *params)
4132 {
4133         struct bnx2x *bp = params->bp;
4134         u8 gpio_num, gpio_port;
4135         u32 gpio_val;
4136         if (bnx2x_get_mod_abs_int_cfg(bp, params->chip_id,
4137                                       params->shmem_base, params->port,
4138                                       &gpio_num, &gpio_port) != 0)
4139                 return 0;
4140         gpio_val = bnx2x_get_gpio(bp, gpio_num, gpio_port);
4141
4142         /* Call the handling function in case module is detected */
4143         if (gpio_val == 0)
4144                 return 1;
4145         else
4146                 return 0;
4147 }
4148 static int bnx2x_warpcore_get_sigdet(struct bnx2x_phy *phy,
4149                                         struct link_params *params)
4150 {
4151         u16 gp2_status_reg0, lane;
4152         struct bnx2x *bp = params->bp;
4153
4154         lane = bnx2x_get_warpcore_lane(phy, params);
4155
4156         bnx2x_cl45_read(bp, phy, MDIO_WC_DEVAD, MDIO_WC_REG_GP2_STATUS_GP_2_0,
4157                                  &gp2_status_reg0);
4158
4159         return (gp2_status_reg0 >> (8+lane)) & 0x1;
4160 }
4161
4162 static void bnx2x_warpcore_config_runtime(struct bnx2x_phy *phy,
4163                                        struct link_params *params,
4164                                        struct link_vars *vars)
4165 {
4166         struct bnx2x *bp = params->bp;
4167         u32 serdes_net_if;
4168         u16 gp_status1 = 0, lnkup = 0, lnkup_kr = 0;
4169         u16 lane = bnx2x_get_warpcore_lane(phy, params);
4170
4171         vars->turn_to_run_wc_rt = vars->turn_to_run_wc_rt ? 0 : 1;
4172
4173         if (!vars->turn_to_run_wc_rt)
4174                 return;
4175
4176         /* return if there is no link partner */
4177         if (!(bnx2x_warpcore_get_sigdet(phy, params))) {
4178                 DP(NETIF_MSG_LINK, "bnx2x_warpcore_get_sigdet false\n");
4179                 return;
4180         }
4181
4182         if (vars->rx_tx_asic_rst) {
4183                 serdes_net_if = (REG_RD(bp, params->shmem_base +
4184                                 offsetof(struct shmem_region, dev_info.
4185                                 port_hw_config[params->port].default_cfg)) &
4186                                 PORT_HW_CFG_NET_SERDES_IF_MASK);
4187
4188                 switch (serdes_net_if) {
4189                 case PORT_HW_CFG_NET_SERDES_IF_KR:
4190                         /* Do we get link yet? */
4191                         bnx2x_cl45_read(bp, phy, MDIO_WC_DEVAD, 0x81d1,
4192                                                                 &gp_status1);
4193                         lnkup = (gp_status1 >> (8+lane)) & 0x1;/* 1G */
4194                                 /*10G KR*/
4195                         lnkup_kr = (gp_status1 >> (12+lane)) & 0x1;
4196
4197                         DP(NETIF_MSG_LINK,
4198                                 "gp_status1 0x%x\n", gp_status1);
4199
4200                         if (lnkup_kr || lnkup) {
4201                                         vars->rx_tx_asic_rst = 0;
4202                                         DP(NETIF_MSG_LINK,
4203                                         "link up, rx_tx_asic_rst 0x%x\n",
4204                                         vars->rx_tx_asic_rst);
4205                         } else {
4206                                 /*reset the lane to see if link comes up.*/
4207                                 bnx2x_warpcore_reset_lane(bp, phy, 1);
4208                                 bnx2x_warpcore_reset_lane(bp, phy, 0);
4209
4210                                 /* restart Autoneg */
4211                                 bnx2x_cl45_write(bp, phy, MDIO_AN_DEVAD,
4212                                         MDIO_WC_REG_IEEE0BLK_MIICNTL, 0x1200);
4213
4214                                 vars->rx_tx_asic_rst--;
4215                                 DP(NETIF_MSG_LINK, "0x%x retry left\n",
4216                                 vars->rx_tx_asic_rst);
4217                         }
4218                         break;
4219
4220                 default:
4221                         break;
4222                 }
4223
4224         } /*params->rx_tx_asic_rst*/
4225
4226 }
4227
4228 static void bnx2x_warpcore_config_init(struct bnx2x_phy *phy,
4229                                        struct link_params *params,
4230                                        struct link_vars *vars)
4231 {
4232         struct bnx2x *bp = params->bp;
4233         u32 serdes_net_if;
4234         u8 fiber_mode;
4235         u16 lane = bnx2x_get_warpcore_lane(phy, params);
4236         serdes_net_if = (REG_RD(bp, params->shmem_base +
4237                          offsetof(struct shmem_region, dev_info.
4238                                   port_hw_config[params->port].default_cfg)) &
4239                          PORT_HW_CFG_NET_SERDES_IF_MASK);
4240         DP(NETIF_MSG_LINK, "Begin Warpcore init, link_speed %d, "
4241                            "serdes_net_if = 0x%x\n",
4242                        vars->line_speed, serdes_net_if);
4243         bnx2x_set_aer_mmd(params, phy);
4244
4245         vars->phy_flags |= PHY_XGXS_FLAG;
4246         if ((serdes_net_if == PORT_HW_CFG_NET_SERDES_IF_SGMII) ||
4247             (phy->req_line_speed &&
4248              ((phy->req_line_speed == SPEED_100) ||
4249               (phy->req_line_speed == SPEED_10)))) {
4250                 vars->phy_flags |= PHY_SGMII_FLAG;
4251                 DP(NETIF_MSG_LINK, "Setting SGMII mode\n");
4252                 bnx2x_warpcore_clear_regs(phy, params, lane);
4253                 bnx2x_warpcore_set_sgmii_speed(phy, params, 0);
4254         } else {
4255                 switch (serdes_net_if) {
4256                 case PORT_HW_CFG_NET_SERDES_IF_KR:
4257                         /* Enable KR Auto Neg */
4258                         if (params->loopback_mode == LOOPBACK_NONE)
4259                                 bnx2x_warpcore_enable_AN_KR(phy, params, vars);
4260                         else {
4261                                 DP(NETIF_MSG_LINK, "Setting KR 10G-Force\n");
4262                                 bnx2x_warpcore_set_10G_KR(phy, params, vars);
4263                         }
4264                         break;
4265
4266                 case PORT_HW_CFG_NET_SERDES_IF_XFI:
4267                         bnx2x_warpcore_clear_regs(phy, params, lane);
4268                         if (vars->line_speed == SPEED_10000) {
4269                                 DP(NETIF_MSG_LINK, "Setting 10G XFI\n");
4270                                 bnx2x_warpcore_set_10G_XFI(phy, params, 1);
4271                         } else {
4272                                 if (SINGLE_MEDIA_DIRECT(params)) {
4273                                         DP(NETIF_MSG_LINK, "1G Fiber\n");
4274                                         fiber_mode = 1;
4275                                 } else {
4276                                         DP(NETIF_MSG_LINK, "10/100/1G SGMII\n");
4277                                         fiber_mode = 0;
4278                                 }
4279                                 bnx2x_warpcore_set_sgmii_speed(phy,
4280                                                                 params,
4281                                                                 fiber_mode);
4282                         }
4283
4284                         break;
4285
4286                 case PORT_HW_CFG_NET_SERDES_IF_SFI:
4287
4288                         bnx2x_warpcore_clear_regs(phy, params, lane);
4289                         if (vars->line_speed == SPEED_10000) {
4290                                 DP(NETIF_MSG_LINK, "Setting 10G SFI\n");
4291                                 bnx2x_warpcore_set_10G_XFI(phy, params, 0);
4292                         } else if (vars->line_speed == SPEED_1000) {
4293                                 DP(NETIF_MSG_LINK, "Setting 1G Fiber\n");
4294                                 bnx2x_warpcore_set_sgmii_speed(phy, params, 1);
4295                         }
4296                         /* Issue Module detection */
4297                         if (bnx2x_is_sfp_module_plugged(phy, params))
4298                                 bnx2x_sfp_module_detection(phy, params);
4299                         break;
4300
4301                 case PORT_HW_CFG_NET_SERDES_IF_DXGXS:
4302                         if (vars->line_speed != SPEED_20000) {
4303                                 DP(NETIF_MSG_LINK, "Speed not supported yet\n");
4304                                 return;
4305                         }
4306                         DP(NETIF_MSG_LINK, "Setting 20G DXGXS\n");
4307                         bnx2x_warpcore_set_20G_DXGXS(bp, phy, lane);
4308                         /* Issue Module detection */
4309
4310                         bnx2x_sfp_module_detection(phy, params);
4311                         break;
4312
4313                 case PORT_HW_CFG_NET_SERDES_IF_KR2:
4314                         if (vars->line_speed != SPEED_20000) {
4315                                 DP(NETIF_MSG_LINK, "Speed not supported yet\n");
4316                                 return;
4317                         }
4318                         DP(NETIF_MSG_LINK, "Setting 20G KR2\n");
4319                         bnx2x_warpcore_set_20G_KR2(bp, phy);
4320                         break;
4321
4322                 default:
4323                         DP(NETIF_MSG_LINK,
4324                            "Unsupported Serdes Net Interface 0x%x\n",
4325                            serdes_net_if);
4326                         return;
4327                 }
4328         }
4329
4330         /* Take lane out of reset after configuration is finished */
4331         bnx2x_warpcore_reset_lane(bp, phy, 0);
4332         DP(NETIF_MSG_LINK, "Exit config init\n");
4333 }
4334
4335 static void bnx2x_sfp_e3_set_transmitter(struct link_params *params,
4336                                          struct bnx2x_phy *phy,
4337                                          u8 tx_en)
4338 {
4339         struct bnx2x *bp = params->bp;
4340         u32 cfg_pin;
4341         u8 port = params->port;
4342
4343         cfg_pin = REG_RD(bp, params->shmem_base +
4344                                 offsetof(struct shmem_region,
4345                                 dev_info.port_hw_config[port].e3_sfp_ctrl)) &
4346                                 PORT_HW_CFG_TX_LASER_MASK;
4347         /* Set the !tx_en since this pin is DISABLE_TX_LASER */
4348         DP(NETIF_MSG_LINK, "Setting WC TX to %d\n", tx_en);
4349         /* For 20G, the expected pin to be used is 3 pins after the current */
4350
4351         bnx2x_set_cfg_pin(bp, cfg_pin, tx_en ^ 1);
4352         if (phy->speed_cap_mask & PORT_HW_CFG_SPEED_CAPABILITY_D0_20G)
4353                 bnx2x_set_cfg_pin(bp, cfg_pin + 3, tx_en ^ 1);
4354 }
4355
4356 static void bnx2x_warpcore_link_reset(struct bnx2x_phy *phy,
4357                                       struct link_params *params)
4358 {
4359         struct bnx2x *bp = params->bp;
4360         u16 val16;
4361         bnx2x_sfp_e3_set_transmitter(params, phy, 0);
4362         bnx2x_set_mdio_clk(bp, params->chip_id, params->port);
4363         bnx2x_set_aer_mmd(params, phy);
4364         /* Global register */
4365         bnx2x_warpcore_reset_lane(bp, phy, 1);
4366
4367         /* Clear loopback settings (if any) */
4368         /* 10G & 20G */
4369         bnx2x_cl45_read(bp, phy, MDIO_WC_DEVAD,
4370                         MDIO_WC_REG_COMBO_IEEE0_MIICTRL, &val16);
4371         bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,
4372                          MDIO_WC_REG_COMBO_IEEE0_MIICTRL, val16 &
4373                          0xBFFF);
4374
4375         bnx2x_cl45_read(bp, phy, MDIO_WC_DEVAD,
4376                         MDIO_WC_REG_IEEE0BLK_MIICNTL, &val16);
4377         bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,
4378                         MDIO_WC_REG_IEEE0BLK_MIICNTL, val16 & 0xfffe);
4379
4380         /* Update those 1-copy registers */
4381         CL22_WR_OVER_CL45(bp, phy, MDIO_REG_BANK_AER_BLOCK,
4382                           MDIO_AER_BLOCK_AER_REG, 0);
4383                 /* Enable 1G MDIO (1-copy) */
4384         bnx2x_cl45_read(bp, phy, MDIO_WC_DEVAD,
4385                         MDIO_WC_REG_XGXSBLK0_XGXSCONTROL,
4386                         &val16);
4387         bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,
4388                          MDIO_WC_REG_XGXSBLK0_XGXSCONTROL,
4389                          val16 & ~0x10);
4390
4391         bnx2x_cl45_read(bp, phy, MDIO_WC_DEVAD,
4392                         MDIO_WC_REG_XGXSBLK1_LANECTRL2, &val16);
4393         bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,
4394                          MDIO_WC_REG_XGXSBLK1_LANECTRL2,
4395                          val16 & 0xff00);
4396
4397 }
4398
4399 static void bnx2x_set_warpcore_loopback(struct bnx2x_phy *phy,
4400                                         struct link_params *params)
4401 {
4402         struct bnx2x *bp = params->bp;
4403         u16 val16;
4404         u32 lane;
4405         DP(NETIF_MSG_LINK, "Setting Warpcore loopback type %x, speed %d\n",
4406                        params->loopback_mode, phy->req_line_speed);
4407
4408         if (phy->req_line_speed < SPEED_10000) {
4409                 /* 10/100/1000 */
4410
4411                 /* Update those 1-copy registers */
4412                 CL22_WR_OVER_CL45(bp, phy, MDIO_REG_BANK_AER_BLOCK,
4413                                   MDIO_AER_BLOCK_AER_REG, 0);
4414                 /* Enable 1G MDIO (1-copy) */
4415                 bnx2x_cl45_read(bp, phy, MDIO_WC_DEVAD,
4416                                 MDIO_WC_REG_XGXSBLK0_XGXSCONTROL,
4417                                 &val16);
4418                 bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,
4419                                 MDIO_WC_REG_XGXSBLK0_XGXSCONTROL,
4420                                 val16 | 0x10);
4421                 /* Set 1G loopback based on lane (1-copy) */
4422                 lane = bnx2x_get_warpcore_lane(phy, params);
4423                 bnx2x_cl45_read(bp, phy, MDIO_WC_DEVAD,
4424                                 MDIO_WC_REG_XGXSBLK1_LANECTRL2, &val16);
4425                 bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,
4426                                 MDIO_WC_REG_XGXSBLK1_LANECTRL2,
4427                                 val16 | (1<<lane));
4428
4429                 /* Switch back to 4-copy registers */
4430                 bnx2x_set_aer_mmd(params, phy);
4431                 /* Global loopback, not recommended. */
4432                 bnx2x_cl45_read(bp, phy, MDIO_WC_DEVAD,
4433                                 MDIO_WC_REG_COMBO_IEEE0_MIICTRL, &val16);
4434                 bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,
4435                                 MDIO_WC_REG_COMBO_IEEE0_MIICTRL, val16 |
4436                                 0x4000);
4437         } else {
4438                 /* 10G & 20G */
4439                 bnx2x_cl45_read(bp, phy, MDIO_WC_DEVAD,
4440                                 MDIO_WC_REG_COMBO_IEEE0_MIICTRL, &val16);
4441                 bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,
4442                                 MDIO_WC_REG_COMBO_IEEE0_MIICTRL, val16 |
4443                                  0x4000);
4444
4445                 bnx2x_cl45_read(bp, phy, MDIO_WC_DEVAD,
4446                                 MDIO_WC_REG_IEEE0BLK_MIICNTL, &val16);
4447                 bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,
4448                                 MDIO_WC_REG_IEEE0BLK_MIICNTL, val16 | 0x1);
4449         }
4450 }
4451
4452
4453 void bnx2x_link_status_update(struct link_params *params,
4454                               struct link_vars *vars)
4455 {
4456         struct bnx2x *bp = params->bp;
4457         u8 link_10g_plus;
4458         u8 port = params->port;
4459         u32 sync_offset, media_types;
4460         /* Update PHY configuration */
4461         set_phy_vars(params, vars);
4462
4463         vars->link_status = REG_RD(bp, params->shmem_base +
4464                                    offsetof(struct shmem_region,
4465                                             port_mb[port].link_status));
4466
4467         vars->link_up = (vars->link_status & LINK_STATUS_LINK_UP);
4468         vars->phy_flags = PHY_XGXS_FLAG;
4469         if (vars->link_status & LINK_STATUS_PHYSICAL_LINK_FLAG)
4470                 vars->phy_flags |= PHY_PHYSICAL_LINK_FLAG;
4471
4472         if (vars->link_up) {
4473                 DP(NETIF_MSG_LINK, "phy link up\n");
4474
4475                 vars->phy_link_up = 1;
4476                 vars->duplex = DUPLEX_FULL;
4477                 switch (vars->link_status &
4478                         LINK_STATUS_SPEED_AND_DUPLEX_MASK) {
4479                         case LINK_10THD:
4480                                 vars->duplex = DUPLEX_HALF;
4481                                 /* fall thru */
4482                         case LINK_10TFD:
4483                                 vars->line_speed = SPEED_10;
4484                                 break;
4485
4486                         case LINK_100TXHD:
4487                                 vars->duplex = DUPLEX_HALF;
4488                                 /* fall thru */
4489                         case LINK_100T4:
4490                         case LINK_100TXFD:
4491                                 vars->line_speed = SPEED_100;
4492                                 break;
4493
4494                         case LINK_1000THD:
4495                                 vars->duplex = DUPLEX_HALF;
4496                                 /* fall thru */
4497                         case LINK_1000TFD:
4498                                 vars->line_speed = SPEED_1000;
4499                                 break;
4500
4501                         case LINK_2500THD:
4502                                 vars->duplex = DUPLEX_HALF;
4503                                 /* fall thru */
4504                         case LINK_2500TFD:
4505                                 vars->line_speed = SPEED_2500;
4506                                 break;
4507
4508                         case LINK_10GTFD:
4509                                 vars->line_speed = SPEED_10000;
4510                                 break;
4511                         case LINK_20GTFD:
4512                                 vars->line_speed = SPEED_20000;
4513                                 break;
4514                         default:
4515                                 break;
4516                 }
4517                 vars->flow_ctrl = 0;
4518                 if (vars->link_status & LINK_STATUS_TX_FLOW_CONTROL_ENABLED)
4519                         vars->flow_ctrl |= BNX2X_FLOW_CTRL_TX;
4520
4521                 if (vars->link_status & LINK_STATUS_RX_FLOW_CONTROL_ENABLED)
4522                         vars->flow_ctrl |= BNX2X_FLOW_CTRL_RX;
4523
4524                 if (!vars->flow_ctrl)
4525                         vars->flow_ctrl = BNX2X_FLOW_CTRL_NONE;
4526
4527                 if (vars->line_speed &&
4528                     ((vars->line_speed == SPEED_10) ||
4529                      (vars->line_speed == SPEED_100))) {
4530                         vars->phy_flags |= PHY_SGMII_FLAG;
4531                 } else {
4532                         vars->phy_flags &= ~PHY_SGMII_FLAG;
4533                 }
4534                 if (vars->line_speed &&
4535                     USES_WARPCORE(bp) &&
4536                     (vars->line_speed == SPEED_1000))
4537                         vars->phy_flags |= PHY_SGMII_FLAG;
4538                 /* anything 10 and over uses the bmac */
4539                 link_10g_plus = (vars->line_speed >= SPEED_10000);
4540
4541                 if (link_10g_plus) {
4542                         if (USES_WARPCORE(bp))
4543                                 vars->mac_type = MAC_TYPE_XMAC;
4544                         else
4545                                 vars->mac_type = MAC_TYPE_BMAC;
4546                 } else {
4547                         if (USES_WARPCORE(bp))
4548                                 vars->mac_type = MAC_TYPE_UMAC;
4549                         else
4550                                 vars->mac_type = MAC_TYPE_EMAC;
4551                 }
4552         } else { /* link down */
4553                 DP(NETIF_MSG_LINK, "phy link down\n");
4554
4555                 vars->phy_link_up = 0;
4556
4557                 vars->line_speed = 0;
4558                 vars->duplex = DUPLEX_FULL;
4559                 vars->flow_ctrl = BNX2X_FLOW_CTRL_NONE;
4560
4561                 /* indicate no mac active */
4562                 vars->mac_type = MAC_TYPE_NONE;
4563                 if (vars->link_status & LINK_STATUS_PHYSICAL_LINK_FLAG)
4564                         vars->phy_flags |= PHY_HALF_OPEN_CONN_FLAG;
4565         }
4566
4567         /* Sync media type */
4568         sync_offset = params->shmem_base +
4569                         offsetof(struct shmem_region,
4570                                  dev_info.port_hw_config[port].media_type);
4571         media_types = REG_RD(bp, sync_offset);
4572
4573         params->phy[INT_PHY].media_type =
4574                 (media_types & PORT_HW_CFG_MEDIA_TYPE_PHY0_MASK) >>
4575                 PORT_HW_CFG_MEDIA_TYPE_PHY0_SHIFT;
4576         params->phy[EXT_PHY1].media_type =
4577                 (media_types & PORT_HW_CFG_MEDIA_TYPE_PHY1_MASK) >>
4578                 PORT_HW_CFG_MEDIA_TYPE_PHY1_SHIFT;
4579         params->phy[EXT_PHY2].media_type =
4580                 (media_types & PORT_HW_CFG_MEDIA_TYPE_PHY2_MASK) >>
4581                 PORT_HW_CFG_MEDIA_TYPE_PHY2_SHIFT;
4582         DP(NETIF_MSG_LINK, "media_types = 0x%x\n", media_types);
4583
4584         /* Sync AEU offset */
4585         sync_offset = params->shmem_base +
4586                         offsetof(struct shmem_region,
4587                                  dev_info.port_hw_config[port].aeu_int_mask);
4588
4589         vars->aeu_int_mask = REG_RD(bp, sync_offset);
4590
4591         /* Sync PFC status */
4592         if (vars->link_status & LINK_STATUS_PFC_ENABLED)
4593                 params->feature_config_flags |=
4594                                         FEATURE_CONFIG_PFC_ENABLED;
4595         else
4596                 params->feature_config_flags &=
4597                                         ~FEATURE_CONFIG_PFC_ENABLED;
4598
4599         DP(NETIF_MSG_LINK, "link_status 0x%x  phy_link_up %x int_mask 0x%x\n",
4600                  vars->link_status, vars->phy_link_up, vars->aeu_int_mask);
4601         DP(NETIF_MSG_LINK, "line_speed %x  duplex %x  flow_ctrl 0x%x\n",
4602                  vars->line_speed, vars->duplex, vars->flow_ctrl);
4603 }
4604
4605
4606 static void bnx2x_set_master_ln(struct link_params *params,
4607                                 struct bnx2x_phy *phy)
4608 {
4609         struct bnx2x *bp = params->bp;
4610         u16 new_master_ln, ser_lane;
4611         ser_lane = ((params->lane_config &
4612                      PORT_HW_CFG_LANE_SWAP_CFG_MASTER_MASK) >>
4613                     PORT_HW_CFG_LANE_SWAP_CFG_MASTER_SHIFT);
4614
4615         /* set the master_ln for AN */
4616         CL22_RD_OVER_CL45(bp, phy,
4617                           MDIO_REG_BANK_XGXS_BLOCK2,
4618                           MDIO_XGXS_BLOCK2_TEST_MODE_LANE,
4619                           &new_master_ln);
4620
4621         CL22_WR_OVER_CL45(bp, phy,
4622                           MDIO_REG_BANK_XGXS_BLOCK2 ,
4623                           MDIO_XGXS_BLOCK2_TEST_MODE_LANE,
4624                           (new_master_ln | ser_lane));
4625 }
4626
4627 static int bnx2x_reset_unicore(struct link_params *params,
4628                                struct bnx2x_phy *phy,
4629                                u8 set_serdes)
4630 {
4631         struct bnx2x *bp = params->bp;
4632         u16 mii_control;
4633         u16 i;
4634         CL22_RD_OVER_CL45(bp, phy,
4635                           MDIO_REG_BANK_COMBO_IEEE0,
4636                           MDIO_COMBO_IEEE0_MII_CONTROL, &mii_control);
4637
4638         /* reset the unicore */
4639         CL22_WR_OVER_CL45(bp, phy,
4640                           MDIO_REG_BANK_COMBO_IEEE0,
4641                           MDIO_COMBO_IEEE0_MII_CONTROL,
4642                           (mii_control |
4643                            MDIO_COMBO_IEEO_MII_CONTROL_RESET));
4644         if (set_serdes)
4645                 bnx2x_set_serdes_access(bp, params->port);
4646
4647         /* wait for the reset to self clear */
4648         for (i = 0; i < MDIO_ACCESS_TIMEOUT; i++) {
4649                 udelay(5);
4650
4651                 /* the reset erased the previous bank value */
4652                 CL22_RD_OVER_CL45(bp, phy,
4653                                   MDIO_REG_BANK_COMBO_IEEE0,
4654                                   MDIO_COMBO_IEEE0_MII_CONTROL,
4655                                   &mii_control);
4656
4657                 if (!(mii_control & MDIO_COMBO_IEEO_MII_CONTROL_RESET)) {
4658                         udelay(5);
4659                         return 0;
4660                 }
4661         }
4662
4663         netdev_err(bp->dev,  "Warning: PHY was not initialized,"
4664                               " Port %d\n",
4665                          params->port);
4666         DP(NETIF_MSG_LINK, "BUG! XGXS is still in reset!\n");
4667         return -EINVAL;
4668
4669 }
4670
4671 static void bnx2x_set_swap_lanes(struct link_params *params,
4672                                  struct bnx2x_phy *phy)
4673 {
4674         struct bnx2x *bp = params->bp;
4675         /*
4676          *  Each two bits represents a lane number:
4677          *  No swap is 0123 => 0x1b no need to enable the swap
4678          */
4679         u16 ser_lane, rx_lane_swap, tx_lane_swap;
4680
4681         ser_lane = ((params->lane_config &
4682                      PORT_HW_CFG_LANE_SWAP_CFG_MASTER_MASK) >>
4683                     PORT_HW_CFG_LANE_SWAP_CFG_MASTER_SHIFT);
4684         rx_lane_swap = ((params->lane_config &
4685                          PORT_HW_CFG_LANE_SWAP_CFG_RX_MASK) >>
4686                         PORT_HW_CFG_LANE_SWAP_CFG_RX_SHIFT);
4687         tx_lane_swap = ((params->lane_config &
4688                          PORT_HW_CFG_LANE_SWAP_CFG_TX_MASK) >>
4689                         PORT_HW_CFG_LANE_SWAP_CFG_TX_SHIFT);
4690
4691         if (rx_lane_swap != 0x1b) {
4692                 CL22_WR_OVER_CL45(bp, phy,
4693                                   MDIO_REG_BANK_XGXS_BLOCK2,
4694                                   MDIO_XGXS_BLOCK2_RX_LN_SWAP,
4695                                   (rx_lane_swap |
4696                                    MDIO_XGXS_BLOCK2_RX_LN_SWAP_ENABLE |
4697                                    MDIO_XGXS_BLOCK2_RX_LN_SWAP_FORCE_ENABLE));
4698         } else {
4699                 CL22_WR_OVER_CL45(bp, phy,
4700                                   MDIO_REG_BANK_XGXS_BLOCK2,
4701                                   MDIO_XGXS_BLOCK2_RX_LN_SWAP, 0);
4702         }
4703
4704         if (tx_lane_swap != 0x1b) {
4705                 CL22_WR_OVER_CL45(bp, phy,
4706                                   MDIO_REG_BANK_XGXS_BLOCK2,
4707                                   MDIO_XGXS_BLOCK2_TX_LN_SWAP,
4708                                   (tx_lane_swap |
4709                                    MDIO_XGXS_BLOCK2_TX_LN_SWAP_ENABLE));
4710         } else {
4711                 CL22_WR_OVER_CL45(bp, phy,
4712                                   MDIO_REG_BANK_XGXS_BLOCK2,
4713                                   MDIO_XGXS_BLOCK2_TX_LN_SWAP, 0);
4714         }
4715 }
4716
4717 static void bnx2x_set_parallel_detection(struct bnx2x_phy *phy,
4718                                          struct link_params *params)
4719 {
4720         struct bnx2x *bp = params->bp;
4721         u16 control2;
4722         CL22_RD_OVER_CL45(bp, phy,
4723                           MDIO_REG_BANK_SERDES_DIGITAL,
4724                           MDIO_SERDES_DIGITAL_A_1000X_CONTROL2,
4725                           &control2);
4726         if (phy->speed_cap_mask & PORT_HW_CFG_SPEED_CAPABILITY_D0_1G)
4727                 control2 |= MDIO_SERDES_DIGITAL_A_1000X_CONTROL2_PRL_DT_EN;
4728         else
4729                 control2 &= ~MDIO_SERDES_DIGITAL_A_1000X_CONTROL2_PRL_DT_EN;
4730         DP(NETIF_MSG_LINK, "phy->speed_cap_mask = 0x%x, control2 = 0x%x\n",
4731                 phy->speed_cap_mask, control2);
4732         CL22_WR_OVER_CL45(bp, phy,
4733                           MDIO_REG_BANK_SERDES_DIGITAL,
4734                           MDIO_SERDES_DIGITAL_A_1000X_CONTROL2,
4735                           control2);
4736
4737         if ((phy->type == PORT_HW_CFG_XGXS_EXT_PHY_TYPE_DIRECT) &&
4738              (phy->speed_cap_mask &
4739                     PORT_HW_CFG_SPEED_CAPABILITY_D0_10G)) {
4740                 DP(NETIF_MSG_LINK, "XGXS\n");
4741
4742                 CL22_WR_OVER_CL45(bp, phy,
4743                                  MDIO_REG_BANK_10G_PARALLEL_DETECT,
4744                                  MDIO_10G_PARALLEL_DETECT_PAR_DET_10G_LINK,
4745                                  MDIO_10G_PARALLEL_DETECT_PAR_DET_10G_LINK_CNT);
4746
4747                 CL22_RD_OVER_CL45(bp, phy,
4748                                   MDIO_REG_BANK_10G_PARALLEL_DETECT,
4749                                   MDIO_10G_PARALLEL_DETECT_PAR_DET_10G_CONTROL,
4750                                   &control2);
4751
4752
4753                 control2 |=
4754                     MDIO_10G_PARALLEL_DETECT_PAR_DET_10G_CONTROL_PARDET10G_EN;
4755
4756                 CL22_WR_OVER_CL45(bp, phy,
4757                                   MDIO_REG_BANK_10G_PARALLEL_DETECT,
4758                                   MDIO_10G_PARALLEL_DETECT_PAR_DET_10G_CONTROL,
4759                                   control2);
4760
4761                 /* Disable parallel detection of HiG */
4762                 CL22_WR_OVER_CL45(bp, phy,
4763                                   MDIO_REG_BANK_XGXS_BLOCK2,
4764                                   MDIO_XGXS_BLOCK2_UNICORE_MODE_10G,
4765                                   MDIO_XGXS_BLOCK2_UNICORE_MODE_10G_CX4_XGXS |
4766                                   MDIO_XGXS_BLOCK2_UNICORE_MODE_10G_HIGIG_XGXS);
4767         }
4768 }
4769
4770 static void bnx2x_set_autoneg(struct bnx2x_phy *phy,
4771                               struct link_params *params,
4772                               struct link_vars *vars,
4773                               u8 enable_cl73)
4774 {
4775         struct bnx2x *bp = params->bp;
4776         u16 reg_val;
4777
4778         /* CL37 Autoneg */
4779         CL22_RD_OVER_CL45(bp, phy,
4780                           MDIO_REG_BANK_COMBO_IEEE0,
4781                           MDIO_COMBO_IEEE0_MII_CONTROL, &reg_val);
4782
4783         /* CL37 Autoneg Enabled */
4784         if (vars->line_speed == SPEED_AUTO_NEG)
4785                 reg_val |= MDIO_COMBO_IEEO_MII_CONTROL_AN_EN;
4786         else /* CL37 Autoneg Disabled */
4787                 reg_val &= ~(MDIO_COMBO_IEEO_MII_CONTROL_AN_EN |
4788                              MDIO_COMBO_IEEO_MII_CONTROL_RESTART_AN);
4789
4790         CL22_WR_OVER_CL45(bp, phy,
4791                           MDIO_REG_BANK_COMBO_IEEE0,
4792                           MDIO_COMBO_IEEE0_MII_CONTROL, reg_val);
4793
4794         /* Enable/Disable Autodetection */
4795
4796         CL22_RD_OVER_CL45(bp, phy,
4797                           MDIO_REG_BANK_SERDES_DIGITAL,
4798                           MDIO_SERDES_DIGITAL_A_1000X_CONTROL1, &reg_val);
4799         reg_val &= ~(MDIO_SERDES_DIGITAL_A_1000X_CONTROL1_SIGNAL_DETECT_EN |
4800                     MDIO_SERDES_DIGITAL_A_1000X_CONTROL1_INVERT_SIGNAL_DETECT);
4801         reg_val |= MDIO_SERDES_DIGITAL_A_1000X_CONTROL1_FIBER_MODE;
4802         if (vars->line_speed == SPEED_AUTO_NEG)
4803                 reg_val |= MDIO_SERDES_DIGITAL_A_1000X_CONTROL1_AUTODET;
4804         else
4805                 reg_val &= ~MDIO_SERDES_DIGITAL_A_1000X_CONTROL1_AUTODET;
4806
4807         CL22_WR_OVER_CL45(bp, phy,
4808                           MDIO_REG_BANK_SERDES_DIGITAL,
4809                           MDIO_SERDES_DIGITAL_A_1000X_CONTROL1, reg_val);
4810
4811         /* Enable TetonII and BAM autoneg */
4812         CL22_RD_OVER_CL45(bp, phy,
4813                           MDIO_REG_BANK_BAM_NEXT_PAGE,
4814                           MDIO_BAM_NEXT_PAGE_MP5_NEXT_PAGE_CTRL,
4815                           &reg_val);
4816         if (vars->line_speed == SPEED_AUTO_NEG) {
4817                 /* Enable BAM aneg Mode and TetonII aneg Mode */
4818                 reg_val |= (MDIO_BAM_NEXT_PAGE_MP5_NEXT_PAGE_CTRL_BAM_MODE |
4819                             MDIO_BAM_NEXT_PAGE_MP5_NEXT_PAGE_CTRL_TETON_AN);
4820         } else {
4821                 /* TetonII and BAM Autoneg Disabled */
4822                 reg_val &= ~(MDIO_BAM_NEXT_PAGE_MP5_NEXT_PAGE_CTRL_BAM_MODE |
4823                              MDIO_BAM_NEXT_PAGE_MP5_NEXT_PAGE_CTRL_TETON_AN);
4824         }
4825         CL22_WR_OVER_CL45(bp, phy,
4826                           MDIO_REG_BANK_BAM_NEXT_PAGE,
4827                           MDIO_BAM_NEXT_PAGE_MP5_NEXT_PAGE_CTRL,
4828                           reg_val);
4829
4830         if (enable_cl73) {
4831                 /* Enable Cl73 FSM status bits */
4832                 CL22_WR_OVER_CL45(bp, phy,
4833                                   MDIO_REG_BANK_CL73_USERB0,
4834                                   MDIO_CL73_USERB0_CL73_UCTRL,
4835                                   0xe);
4836
4837                 /* Enable BAM Station Manager*/
4838                 CL22_WR_OVER_CL45(bp, phy,
4839                         MDIO_REG_BANK_CL73_USERB0,
4840                         MDIO_CL73_USERB0_CL73_BAM_CTRL1,
4841                         MDIO_CL73_USERB0_CL73_BAM_CTRL1_BAM_EN |
4842                         MDIO_CL73_USERB0_CL73_BAM_CTRL1_BAM_STATION_MNGR_EN |
4843                         MDIO_CL73_USERB0_CL73_BAM_CTRL1_BAM_NP_AFTER_BP_EN);
4844
4845                 /* Advertise CL73 link speeds */
4846                 CL22_RD_OVER_CL45(bp, phy,
4847                                   MDIO_REG_BANK_CL73_IEEEB1,
4848                                   MDIO_CL73_IEEEB1_AN_ADV2,
4849                                   &reg_val);
4850                 if (phy->speed_cap_mask &
4851                     PORT_HW_CFG_SPEED_CAPABILITY_D0_10G)
4852                         reg_val |= MDIO_CL73_IEEEB1_AN_ADV2_ADVR_10G_KX4;
4853                 if (phy->speed_cap_mask &
4854                     PORT_HW_CFG_SPEED_CAPABILITY_D0_1G)
4855                         reg_val |= MDIO_CL73_IEEEB1_AN_ADV2_ADVR_1000M_KX;
4856
4857                 CL22_WR_OVER_CL45(bp, phy,
4858                                   MDIO_REG_BANK_CL73_IEEEB1,
4859                                   MDIO_CL73_IEEEB1_AN_ADV2,
4860                                   reg_val);
4861
4862                 /* CL73 Autoneg Enabled */
4863                 reg_val = MDIO_CL73_IEEEB0_CL73_AN_CONTROL_AN_EN;
4864
4865         } else /* CL73 Autoneg Disabled */
4866                 reg_val = 0;
4867
4868         CL22_WR_OVER_CL45(bp, phy,
4869                           MDIO_REG_BANK_CL73_IEEEB0,
4870                           MDIO_CL73_IEEEB0_CL73_AN_CONTROL, reg_val);
4871 }
4872
4873 /* program SerDes, forced speed */
4874 static void bnx2x_program_serdes(struct bnx2x_phy *phy,
4875                                  struct link_params *params,
4876                                  struct link_vars *vars)
4877 {
4878         struct bnx2x *bp = params->bp;
4879         u16 reg_val;
4880
4881         /* program duplex, disable autoneg and sgmii*/
4882         CL22_RD_OVER_CL45(bp, phy,
4883                           MDIO_REG_BANK_COMBO_IEEE0,
4884                           MDIO_COMBO_IEEE0_MII_CONTROL, &reg_val);
4885         reg_val &= ~(MDIO_COMBO_IEEO_MII_CONTROL_FULL_DUPLEX |
4886                      MDIO_COMBO_IEEO_MII_CONTROL_AN_EN |
4887                      MDIO_COMBO_IEEO_MII_CONTROL_MAN_SGMII_SP_MASK);
4888         if (phy->req_duplex == DUPLEX_FULL)
4889                 reg_val |= MDIO_COMBO_IEEO_MII_CONTROL_FULL_DUPLEX;
4890         CL22_WR_OVER_CL45(bp, phy,
4891                           MDIO_REG_BANK_COMBO_IEEE0,
4892                           MDIO_COMBO_IEEE0_MII_CONTROL, reg_val);
4893
4894         /*
4895          * program speed
4896          *  - needed only if the speed is greater than 1G (2.5G or 10G)
4897          */
4898         CL22_RD_OVER_CL45(bp, phy,
4899                           MDIO_REG_BANK_SERDES_DIGITAL,
4900                           MDIO_SERDES_DIGITAL_MISC1, &reg_val);
4901         /* clearing the speed value before setting the right speed */
4902         DP(NETIF_MSG_LINK, "MDIO_REG_BANK_SERDES_DIGITAL = 0x%x\n", reg_val);
4903
4904         reg_val &= ~(MDIO_SERDES_DIGITAL_MISC1_FORCE_SPEED_MASK |
4905                      MDIO_SERDES_DIGITAL_MISC1_FORCE_SPEED_SEL);
4906
4907         if (!((vars->line_speed == SPEED_1000) ||
4908               (vars->line_speed == SPEED_100) ||
4909               (vars->line_speed == SPEED_10))) {
4910
4911                 reg_val |= (MDIO_SERDES_DIGITAL_MISC1_REFCLK_SEL_156_25M |
4912                             MDIO_SERDES_DIGITAL_MISC1_FORCE_SPEED_SEL);
4913                 if (vars->line_speed == SPEED_10000)
4914                         reg_val |=
4915                                 MDIO_SERDES_DIGITAL_MISC1_FORCE_SPEED_10G_CX4;
4916         }
4917
4918         CL22_WR_OVER_CL45(bp, phy,
4919                           MDIO_REG_BANK_SERDES_DIGITAL,
4920                           MDIO_SERDES_DIGITAL_MISC1, reg_val);
4921
4922 }
4923
4924 static void bnx2x_set_brcm_cl37_advertisement(struct bnx2x_phy *phy,
4925                                               struct link_params *params)
4926 {
4927         struct bnx2x *bp = params->bp;
4928         u16 val = 0;
4929
4930         /* configure the 48 bits for BAM AN */
4931
4932         /* set extended capabilities */
4933         if (phy->speed_cap_mask & PORT_HW_CFG_SPEED_CAPABILITY_D0_2_5G)
4934                 val |= MDIO_OVER_1G_UP1_2_5G;
4935         if (phy->speed_cap_mask & PORT_HW_CFG_SPEED_CAPABILITY_D0_10G)
4936                 val |= MDIO_OVER_1G_UP1_10G;
4937         CL22_WR_OVER_CL45(bp, phy,
4938                           MDIO_REG_BANK_OVER_1G,
4939                           MDIO_OVER_1G_UP1, val);
4940
4941         CL22_WR_OVER_CL45(bp, phy,
4942                           MDIO_REG_BANK_OVER_1G,
4943                           MDIO_OVER_1G_UP3, 0x400);
4944 }
4945
4946 static void bnx2x_set_ieee_aneg_advertisement(struct bnx2x_phy *phy,
4947                                               struct link_params *params,
4948                                               u16 ieee_fc)
4949 {
4950         struct bnx2x *bp = params->bp;
4951         u16 val;
4952         /* for AN, we are always publishing full duplex */
4953
4954         CL22_WR_OVER_CL45(bp, phy,
4955                           MDIO_REG_BANK_COMBO_IEEE0,
4956                           MDIO_COMBO_IEEE0_AUTO_NEG_ADV, ieee_fc);
4957         CL22_RD_OVER_CL45(bp, phy,
4958                           MDIO_REG_BANK_CL73_IEEEB1,
4959                           MDIO_CL73_IEEEB1_AN_ADV1, &val);
4960         val &= ~MDIO_CL73_IEEEB1_AN_ADV1_PAUSE_BOTH;
4961         val |= ((ieee_fc<<3) & MDIO_CL73_IEEEB1_AN_ADV1_PAUSE_MASK);
4962         CL22_WR_OVER_CL45(bp, phy,
4963                           MDIO_REG_BANK_CL73_IEEEB1,
4964                           MDIO_CL73_IEEEB1_AN_ADV1, val);
4965 }
4966
4967 static void bnx2x_restart_autoneg(struct bnx2x_phy *phy,
4968                                   struct link_params *params,
4969                                   u8 enable_cl73)
4970 {
4971         struct bnx2x *bp = params->bp;
4972         u16 mii_control;
4973
4974         DP(NETIF_MSG_LINK, "bnx2x_restart_autoneg\n");
4975         /* Enable and restart BAM/CL37 aneg */
4976
4977         if (enable_cl73) {
4978                 CL22_RD_OVER_CL45(bp, phy,
4979                                   MDIO_REG_BANK_CL73_IEEEB0,
4980                                   MDIO_CL73_IEEEB0_CL73_AN_CONTROL,
4981                                   &mii_control);
4982
4983                 CL22_WR_OVER_CL45(bp, phy,
4984                                   MDIO_REG_BANK_CL73_IEEEB0,
4985                                   MDIO_CL73_IEEEB0_CL73_AN_CONTROL,
4986                                   (mii_control |
4987                                   MDIO_CL73_IEEEB0_CL73_AN_CONTROL_AN_EN |
4988                                   MDIO_CL73_IEEEB0_CL73_AN_CONTROL_RESTART_AN));
4989         } else {
4990
4991                 CL22_RD_OVER_CL45(bp, phy,
4992                                   MDIO_REG_BANK_COMBO_IEEE0,
4993                                   MDIO_COMBO_IEEE0_MII_CONTROL,
4994                                   &mii_control);
4995                 DP(NETIF_MSG_LINK,
4996                          "bnx2x_restart_autoneg mii_control before = 0x%x\n",
4997                          mii_control);
4998                 CL22_WR_OVER_CL45(bp, phy,
4999                                   MDIO_REG_BANK_COMBO_IEEE0,
5000                                   MDIO_COMBO_IEEE0_MII_CONTROL,
5001                                   (mii_control |
5002                                    MDIO_COMBO_IEEO_MII_CONTROL_AN_EN |
5003                                    MDIO_COMBO_IEEO_MII_CONTROL_RESTART_AN));
5004         }
5005 }
5006
5007 static void bnx2x_initialize_sgmii_process(struct bnx2x_phy *phy,
5008                                            struct link_params *params,
5009                                            struct link_vars *vars)
5010 {
5011         struct bnx2x *bp = params->bp;
5012         u16 control1;
5013
5014         /* in SGMII mode, the unicore is always slave */
5015
5016         CL22_RD_OVER_CL45(bp, phy,
5017                           MDIO_REG_BANK_SERDES_DIGITAL,
5018                           MDIO_SERDES_DIGITAL_A_1000X_CONTROL1,
5019                           &control1);
5020         control1 |= MDIO_SERDES_DIGITAL_A_1000X_CONTROL1_INVERT_SIGNAL_DETECT;
5021         /* set sgmii mode (and not fiber) */
5022         control1 &= ~(MDIO_SERDES_DIGITAL_A_1000X_CONTROL1_FIBER_MODE |
5023                       MDIO_SERDES_DIGITAL_A_1000X_CONTROL1_AUTODET |
5024                       MDIO_SERDES_DIGITAL_A_1000X_CONTROL1_MSTR_MODE);
5025         CL22_WR_OVER_CL45(bp, phy,
5026                           MDIO_REG_BANK_SERDES_DIGITAL,
5027                           MDIO_SERDES_DIGITAL_A_1000X_CONTROL1,
5028                           control1);
5029
5030         /* if forced speed */
5031         if (!(vars->line_speed == SPEED_AUTO_NEG)) {
5032                 /* set speed, disable autoneg */
5033                 u16 mii_control;
5034
5035                 CL22_RD_OVER_CL45(bp, phy,
5036                                   MDIO_REG_BANK_COMBO_IEEE0,
5037                                   MDIO_COMBO_IEEE0_MII_CONTROL,
5038                                   &mii_control);
5039                 mii_control &= ~(MDIO_COMBO_IEEO_MII_CONTROL_AN_EN |
5040                                  MDIO_COMBO_IEEO_MII_CONTROL_MAN_SGMII_SP_MASK|
5041                                  MDIO_COMBO_IEEO_MII_CONTROL_FULL_DUPLEX);
5042
5043                 switch (vars->line_speed) {
5044                 case SPEED_100:
5045                         mii_control |=
5046                                 MDIO_COMBO_IEEO_MII_CONTROL_MAN_SGMII_SP_100;
5047                         break;
5048                 case SPEED_1000:
5049                         mii_control |=
5050                                 MDIO_COMBO_IEEO_MII_CONTROL_MAN_SGMII_SP_1000;
5051                         break;
5052                 case SPEED_10:
5053                         /* there is nothing to set for 10M */
5054                         break;
5055                 default:
5056                         /* invalid speed for SGMII */
5057                         DP(NETIF_MSG_LINK, "Invalid line_speed 0x%x\n",
5058                                   vars->line_speed);
5059                         break;
5060                 }
5061
5062                 /* setting the full duplex */
5063                 if (phy->req_duplex == DUPLEX_FULL)
5064                         mii_control |=
5065                                 MDIO_COMBO_IEEO_MII_CONTROL_FULL_DUPLEX;
5066                 CL22_WR_OVER_CL45(bp, phy,
5067                                   MDIO_REG_BANK_COMBO_IEEE0,
5068                                   MDIO_COMBO_IEEE0_MII_CONTROL,
5069                                   mii_control);
5070
5071         } else { /* AN mode */
5072                 /* enable and restart AN */
5073                 bnx2x_restart_autoneg(phy, params, 0);
5074         }
5075 }
5076
5077
5078 /*
5079  * link management
5080  */
5081
5082 static int bnx2x_direct_parallel_detect_used(struct bnx2x_phy *phy,
5083                                              struct link_params *params)
5084 {
5085         struct bnx2x *bp = params->bp;
5086         u16 pd_10g, status2_1000x;
5087         if (phy->req_line_speed != SPEED_AUTO_NEG)
5088                 return 0;
5089         CL22_RD_OVER_CL45(bp, phy,
5090                           MDIO_REG_BANK_SERDES_DIGITAL,
5091                           MDIO_SERDES_DIGITAL_A_1000X_STATUS2,
5092                           &status2_1000x);
5093         CL22_RD_OVER_CL45(bp, phy,
5094                           MDIO_REG_BANK_SERDES_DIGITAL,
5095                           MDIO_SERDES_DIGITAL_A_1000X_STATUS2,
5096                           &status2_1000x);
5097         if (status2_1000x & MDIO_SERDES_DIGITAL_A_1000X_STATUS2_AN_DISABLED) {
5098                 DP(NETIF_MSG_LINK, "1G parallel detect link on port %d\n",
5099                          params->port);
5100                 return 1;
5101         }
5102
5103         CL22_RD_OVER_CL45(bp, phy,
5104                           MDIO_REG_BANK_10G_PARALLEL_DETECT,
5105                           MDIO_10G_PARALLEL_DETECT_PAR_DET_10G_STATUS,
5106                           &pd_10g);
5107
5108         if (pd_10g & MDIO_10G_PARALLEL_DETECT_PAR_DET_10G_STATUS_PD_LINK) {
5109                 DP(NETIF_MSG_LINK, "10G parallel detect link on port %d\n",
5110                          params->port);
5111                 return 1;
5112         }
5113         return 0;
5114 }
5115
5116 static void bnx2x_flow_ctrl_resolve(struct bnx2x_phy *phy,
5117                                     struct link_params *params,
5118                                     struct link_vars *vars,
5119                                     u32 gp_status)
5120 {
5121         struct bnx2x *bp = params->bp;
5122         u16 ld_pause;   /* local driver */
5123         u16 lp_pause;   /* link partner */
5124         u16 pause_result;
5125
5126         vars->flow_ctrl = BNX2X_FLOW_CTRL_NONE;
5127
5128         /* resolve from gp_status in case of AN complete and not sgmii */
5129         if (phy->req_flow_ctrl != BNX2X_FLOW_CTRL_AUTO)
5130                 vars->flow_ctrl = phy->req_flow_ctrl;
5131         else if (phy->req_line_speed != SPEED_AUTO_NEG)
5132                 vars->flow_ctrl = params->req_fc_auto_adv;
5133         else if ((gp_status & MDIO_AN_CL73_OR_37_COMPLETE) &&
5134                  (!(vars->phy_flags & PHY_SGMII_FLAG))) {
5135                 if (bnx2x_direct_parallel_detect_used(phy, params)) {
5136                         vars->flow_ctrl = params->req_fc_auto_adv;
5137                         return;
5138                 }
5139                 if ((gp_status &
5140                     (MDIO_GP_STATUS_TOP_AN_STATUS1_CL73_AUTONEG_COMPLETE |
5141                      MDIO_GP_STATUS_TOP_AN_STATUS1_CL73_MR_LP_NP_AN_ABLE)) ==
5142                     (MDIO_GP_STATUS_TOP_AN_STATUS1_CL73_AUTONEG_COMPLETE |
5143                      MDIO_GP_STATUS_TOP_AN_STATUS1_CL73_MR_LP_NP_AN_ABLE)) {
5144
5145                         CL22_RD_OVER_CL45(bp, phy,
5146                                           MDIO_REG_BANK_CL73_IEEEB1,
5147                                           MDIO_CL73_IEEEB1_AN_ADV1,
5148                                           &ld_pause);
5149                         CL22_RD_OVER_CL45(bp, phy,
5150                                           MDIO_REG_BANK_CL73_IEEEB1,
5151                                           MDIO_CL73_IEEEB1_AN_LP_ADV1,
5152                                           &lp_pause);
5153                         pause_result = (ld_pause &
5154                                         MDIO_CL73_IEEEB1_AN_ADV1_PAUSE_MASK)
5155                                         >> 8;
5156                         pause_result |= (lp_pause &
5157                                         MDIO_CL73_IEEEB1_AN_LP_ADV1_PAUSE_MASK)
5158                                         >> 10;
5159                         DP(NETIF_MSG_LINK, "pause_result CL73 0x%x\n",
5160                                  pause_result);
5161                 } else {
5162                         CL22_RD_OVER_CL45(bp, phy,
5163                                           MDIO_REG_BANK_COMBO_IEEE0,
5164                                           MDIO_COMBO_IEEE0_AUTO_NEG_ADV,
5165                                           &ld_pause);
5166                         CL22_RD_OVER_CL45(bp, phy,
5167                                 MDIO_REG_BANK_COMBO_IEEE0,
5168                                 MDIO_COMBO_IEEE0_AUTO_NEG_LINK_PARTNER_ABILITY1,
5169                                 &lp_pause);
5170                         pause_result = (ld_pause &
5171                                 MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_MASK)>>5;
5172                         pause_result |= (lp_pause &
5173                                 MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_MASK)>>7;
5174                         DP(NETIF_MSG_LINK, "pause_result CL37 0x%x\n",
5175                                  pause_result);
5176                 }
5177                 bnx2x_pause_resolve(vars, pause_result);
5178         }
5179         DP(NETIF_MSG_LINK, "flow_ctrl 0x%x\n", vars->flow_ctrl);
5180 }
5181
5182 static void bnx2x_check_fallback_to_cl37(struct bnx2x_phy *phy,
5183                                          struct link_params *params)
5184 {
5185         struct bnx2x *bp = params->bp;
5186         u16 rx_status, ustat_val, cl37_fsm_received;
5187         DP(NETIF_MSG_LINK, "bnx2x_check_fallback_to_cl37\n");
5188         /* Step 1: Make sure signal is detected */
5189         CL22_RD_OVER_CL45(bp, phy,
5190                           MDIO_REG_BANK_RX0,
5191                           MDIO_RX0_RX_STATUS,
5192                           &rx_status);
5193         if ((rx_status & MDIO_RX0_RX_STATUS_SIGDET) !=
5194             (MDIO_RX0_RX_STATUS_SIGDET)) {
5195                 DP(NETIF_MSG_LINK, "Signal is not detected. Restoring CL73."
5196                              "rx_status(0x80b0) = 0x%x\n", rx_status);
5197                 CL22_WR_OVER_CL45(bp, phy,
5198                                   MDIO_REG_BANK_CL73_IEEEB0,
5199                                   MDIO_CL73_IEEEB0_CL73_AN_CONTROL,
5200                                   MDIO_CL73_IEEEB0_CL73_AN_CONTROL_AN_EN);
5201                 return;
5202         }
5203         /* Step 2: Check CL73 state machine */
5204         CL22_RD_OVER_CL45(bp, phy,
5205                           MDIO_REG_BANK_CL73_USERB0,
5206                           MDIO_CL73_USERB0_CL73_USTAT1,
5207                           &ustat_val);
5208         if ((ustat_val &
5209              (MDIO_CL73_USERB0_CL73_USTAT1_LINK_STATUS_CHECK |
5210               MDIO_CL73_USERB0_CL73_USTAT1_AN_GOOD_CHECK_BAM37)) !=
5211             (MDIO_CL73_USERB0_CL73_USTAT1_LINK_STATUS_CHECK |
5212               MDIO_CL73_USERB0_CL73_USTAT1_AN_GOOD_CHECK_BAM37)) {
5213                 DP(NETIF_MSG_LINK, "CL73 state-machine is not stable. "
5214                              "ustat_val(0x8371) = 0x%x\n", ustat_val);
5215                 return;
5216         }
5217         /*
5218          * Step 3: Check CL37 Message Pages received to indicate LP
5219          * supports only CL37
5220          */
5221         CL22_RD_OVER_CL45(bp, phy,
5222                           MDIO_REG_BANK_REMOTE_PHY,
5223                           MDIO_REMOTE_PHY_MISC_RX_STATUS,
5224                           &cl37_fsm_received);
5225         if ((cl37_fsm_received &
5226              (MDIO_REMOTE_PHY_MISC_RX_STATUS_CL37_FSM_RECEIVED_OVER1G_MSG |
5227              MDIO_REMOTE_PHY_MISC_RX_STATUS_CL37_FSM_RECEIVED_BRCM_OUI_MSG)) !=
5228             (MDIO_REMOTE_PHY_MISC_RX_STATUS_CL37_FSM_RECEIVED_OVER1G_MSG |
5229               MDIO_REMOTE_PHY_MISC_RX_STATUS_CL37_FSM_RECEIVED_BRCM_OUI_MSG)) {
5230                 DP(NETIF_MSG_LINK, "No CL37 FSM were received. "
5231                              "misc_rx_status(0x8330) = 0x%x\n",
5232                          cl37_fsm_received);
5233                 return;
5234         }
5235         /*
5236          * The combined cl37/cl73 fsm state information indicating that
5237          * we are connected to a device which does not support cl73, but
5238          * does support cl37 BAM. In this case we disable cl73 and
5239          * restart cl37 auto-neg
5240          */
5241
5242         /* Disable CL73 */
5243         CL22_WR_OVER_CL45(bp, phy,
5244                           MDIO_REG_BANK_CL73_IEEEB0,
5245                           MDIO_CL73_IEEEB0_CL73_AN_CONTROL,
5246                           0);
5247         /* Restart CL37 autoneg */
5248         bnx2x_restart_autoneg(phy, params, 0);
5249         DP(NETIF_MSG_LINK, "Disabling CL73, and restarting CL37 autoneg\n");
5250 }
5251
5252 static void bnx2x_xgxs_an_resolve(struct bnx2x_phy *phy,
5253                                   struct link_params *params,
5254                                   struct link_vars *vars,
5255                                   u32 gp_status)
5256 {
5257         if (gp_status & MDIO_AN_CL73_OR_37_COMPLETE)
5258                 vars->link_status |=
5259                         LINK_STATUS_AUTO_NEGOTIATE_COMPLETE;
5260
5261         if (bnx2x_direct_parallel_detect_used(phy, params))
5262                 vars->link_status |=
5263                         LINK_STATUS_PARALLEL_DETECTION_USED;
5264 }
5265 static int bnx2x_get_link_speed_duplex(struct bnx2x_phy *phy,
5266                                      struct link_params *params,
5267                                       struct link_vars *vars,
5268                                       u16 is_link_up,
5269                                       u16 speed_mask,
5270                                       u16 is_duplex)
5271 {
5272         struct bnx2x *bp = params->bp;
5273         if (phy->req_line_speed == SPEED_AUTO_NEG)
5274                 vars->link_status |= LINK_STATUS_AUTO_NEGOTIATE_ENABLED;
5275         if (is_link_up) {
5276                 DP(NETIF_MSG_LINK, "phy link up\n");
5277
5278                 vars->phy_link_up = 1;
5279                 vars->link_status |= LINK_STATUS_LINK_UP;
5280
5281                 switch (speed_mask) {
5282                 case GP_STATUS_10M:
5283                         vars->line_speed = SPEED_10;
5284                         if (vars->duplex == DUPLEX_FULL)
5285                                 vars->link_status |= LINK_10TFD;
5286                         else
5287                                 vars->link_status |= LINK_10THD;
5288                         break;
5289
5290                 case GP_STATUS_100M:
5291                         vars->line_speed = SPEED_100;
5292                         if (vars->duplex == DUPLEX_FULL)
5293                                 vars->link_status |= LINK_100TXFD;
5294                         else
5295                                 vars->link_status |= LINK_100TXHD;
5296                         break;
5297
5298                 case GP_STATUS_1G:
5299                 case GP_STATUS_1G_KX:
5300                         vars->line_speed = SPEED_1000;
5301                         if (vars->duplex == DUPLEX_FULL)
5302                                 vars->link_status |= LINK_1000TFD;
5303                         else
5304                                 vars->link_status |= LINK_1000THD;
5305                         break;
5306
5307                 case GP_STATUS_2_5G:
5308                         vars->line_speed = SPEED_2500;
5309                         if (vars->duplex == DUPLEX_FULL)
5310                                 vars->link_status |= LINK_2500TFD;
5311                         else
5312                                 vars->link_status |= LINK_2500THD;
5313                         break;
5314
5315                 case GP_STATUS_5G:
5316                 case GP_STATUS_6G:
5317                         DP(NETIF_MSG_LINK,
5318                                  "link speed unsupported  gp_status 0x%x\n",
5319                                   speed_mask);
5320                         return -EINVAL;
5321
5322                 case GP_STATUS_10G_KX4:
5323                 case GP_STATUS_10G_HIG:
5324                 case GP_STATUS_10G_CX4:
5325                 case GP_STATUS_10G_KR:
5326                 case GP_STATUS_10G_SFI:
5327                 case GP_STATUS_10G_XFI:
5328                         vars->line_speed = SPEED_10000;
5329                         vars->link_status |= LINK_10GTFD;
5330                         break;
5331                 case GP_STATUS_20G_DXGXS:
5332                         vars->line_speed = SPEED_20000;
5333                         vars->link_status |= LINK_20GTFD;
5334                         break;
5335                 default:
5336                         DP(NETIF_MSG_LINK,
5337                                   "link speed unsupported gp_status 0x%x\n",
5338                                   speed_mask);
5339                         return -EINVAL;
5340                 }
5341         } else { /* link_down */
5342                 DP(NETIF_MSG_LINK, "phy link down\n");
5343
5344                 vars->phy_link_up = 0;
5345
5346                 vars->duplex = DUPLEX_FULL;
5347                 vars->flow_ctrl = BNX2X_FLOW_CTRL_NONE;
5348                 vars->mac_type = MAC_TYPE_NONE;
5349         }
5350         DP(NETIF_MSG_LINK, " phy_link_up %x line_speed %d\n",
5351                     vars->phy_link_up, vars->line_speed);
5352         return 0;
5353 }
5354
5355 static int bnx2x_link_settings_status(struct bnx2x_phy *phy,
5356                                       struct link_params *params,
5357                                       struct link_vars *vars)
5358 {
5359
5360         struct bnx2x *bp = params->bp;
5361
5362         u16 gp_status, duplex = DUPLEX_HALF, link_up = 0, speed_mask;
5363         int rc = 0;
5364
5365         /* Read gp_status */
5366         CL22_RD_OVER_CL45(bp, phy,
5367                           MDIO_REG_BANK_GP_STATUS,
5368                           MDIO_GP_STATUS_TOP_AN_STATUS1,
5369                           &gp_status);
5370         if (gp_status & MDIO_GP_STATUS_TOP_AN_STATUS1_DUPLEX_STATUS)
5371                 duplex = DUPLEX_FULL;
5372         if (gp_status & MDIO_GP_STATUS_TOP_AN_STATUS1_LINK_STATUS)
5373                 link_up = 1;
5374         speed_mask = gp_status & GP_STATUS_SPEED_MASK;
5375         DP(NETIF_MSG_LINK, "gp_status 0x%x, is_link_up %d, speed_mask 0x%x\n",
5376                        gp_status, link_up, speed_mask);
5377         rc = bnx2x_get_link_speed_duplex(phy, params, vars, link_up, speed_mask,
5378                                          duplex);
5379         if (rc == -EINVAL)
5380                 return rc;
5381
5382         if (gp_status & MDIO_GP_STATUS_TOP_AN_STATUS1_LINK_STATUS) {
5383                 if (SINGLE_MEDIA_DIRECT(params)) {
5384                         bnx2x_flow_ctrl_resolve(phy, params, vars, gp_status);
5385                         if (phy->req_line_speed == SPEED_AUTO_NEG)
5386                                 bnx2x_xgxs_an_resolve(phy, params, vars,
5387                                                       gp_status);
5388                 }
5389         } else { /* link_down */
5390                 if ((phy->req_line_speed == SPEED_AUTO_NEG) &&
5391                     SINGLE_MEDIA_DIRECT(params)) {
5392                         /* Check signal is detected */
5393                         bnx2x_check_fallback_to_cl37(phy, params);
5394                 }
5395         }
5396
5397         DP(NETIF_MSG_LINK, "duplex %x  flow_ctrl 0x%x link_status 0x%x\n",
5398                    vars->duplex, vars->flow_ctrl, vars->link_status);
5399         return rc;
5400 }
5401
5402 static int bnx2x_warpcore_read_status(struct bnx2x_phy *phy,
5403                                      struct link_params *params,
5404                                      struct link_vars *vars)
5405 {
5406
5407         struct bnx2x *bp = params->bp;
5408
5409         u8 lane;
5410         u16 gp_status1, gp_speed, link_up, duplex = DUPLEX_FULL;
5411         int rc = 0;
5412         lane = bnx2x_get_warpcore_lane(phy, params);
5413         /* Read gp_status */
5414         if (phy->req_line_speed > SPEED_10000) {
5415                 u16 temp_link_up;
5416                 bnx2x_cl45_read(bp, phy, MDIO_WC_DEVAD,
5417                                 1, &temp_link_up);
5418                 bnx2x_cl45_read(bp, phy, MDIO_WC_DEVAD,
5419                                 1, &link_up);
5420                 DP(NETIF_MSG_LINK, "PCS RX link status = 0x%x-->0x%x\n",
5421                                temp_link_up, link_up);
5422                 link_up &= (1<<2);
5423                 if (link_up)
5424                         bnx2x_ext_phy_resolve_fc(phy, params, vars);
5425         } else {
5426                 bnx2x_cl45_read(bp, phy, MDIO_WC_DEVAD,
5427                                 MDIO_WC_REG_GP2_STATUS_GP_2_1, &gp_status1);
5428                 DP(NETIF_MSG_LINK, "0x81d1 = 0x%x\n", gp_status1);
5429                 /* Check for either KR or generic link up. */
5430                 gp_status1 = ((gp_status1 >> 8) & 0xf) |
5431                         ((gp_status1 >> 12) & 0xf);
5432                 link_up = gp_status1 & (1 << lane);
5433                 if (link_up && SINGLE_MEDIA_DIRECT(params)) {
5434                         u16 pd, gp_status4;
5435                         if (phy->req_line_speed == SPEED_AUTO_NEG) {
5436                                 /* Check Autoneg complete */
5437                                 bnx2x_cl45_read(bp, phy, MDIO_WC_DEVAD,
5438                                                 MDIO_WC_REG_GP2_STATUS_GP_2_4,
5439                                                 &gp_status4);
5440                                 if (gp_status4 & ((1<<12)<<lane))
5441                                         vars->link_status |=
5442                                         LINK_STATUS_AUTO_NEGOTIATE_COMPLETE;
5443
5444                                 /* Check parallel detect used */
5445                                 bnx2x_cl45_read(bp, phy, MDIO_WC_DEVAD,
5446                                                 MDIO_WC_REG_PAR_DET_10G_STATUS,
5447                                                 &pd);
5448                                 if (pd & (1<<15))
5449                                         vars->link_status |=
5450                                         LINK_STATUS_PARALLEL_DETECTION_USED;
5451                         }
5452                         bnx2x_ext_phy_resolve_fc(phy, params, vars);
5453                 }
5454         }
5455
5456         if (lane < 2) {
5457                 bnx2x_cl45_read(bp, phy, MDIO_WC_DEVAD,
5458                                 MDIO_WC_REG_GP2_STATUS_GP_2_2, &gp_speed);
5459         } else {
5460                 bnx2x_cl45_read(bp, phy, MDIO_WC_DEVAD,
5461                                 MDIO_WC_REG_GP2_STATUS_GP_2_3, &gp_speed);
5462         }
5463         DP(NETIF_MSG_LINK, "lane %d gp_speed 0x%x\n", lane, gp_speed);
5464
5465         if ((lane & 1) == 0)
5466                 gp_speed <<= 8;
5467         gp_speed &= 0x3f00;
5468
5469
5470         rc = bnx2x_get_link_speed_duplex(phy, params, vars, link_up, gp_speed,
5471                                          duplex);
5472
5473         DP(NETIF_MSG_LINK, "duplex %x  flow_ctrl 0x%x link_status 0x%x\n",
5474                    vars->duplex, vars->flow_ctrl, vars->link_status);
5475         return rc;
5476 }
5477 static void bnx2x_set_gmii_tx_driver(struct link_params *params)
5478 {
5479         struct bnx2x *bp = params->bp;
5480         struct bnx2x_phy *phy = &params->phy[INT_PHY];
5481         u16 lp_up2;
5482         u16 tx_driver;
5483         u16 bank;
5484
5485         /* read precomp */
5486         CL22_RD_OVER_CL45(bp, phy,
5487                           MDIO_REG_BANK_OVER_1G,
5488                           MDIO_OVER_1G_LP_UP2, &lp_up2);
5489
5490         /* bits [10:7] at lp_up2, positioned at [15:12] */
5491         lp_up2 = (((lp_up2 & MDIO_OVER_1G_LP_UP2_PREEMPHASIS_MASK) >>
5492                    MDIO_OVER_1G_LP_UP2_PREEMPHASIS_SHIFT) <<
5493                   MDIO_TX0_TX_DRIVER_PREEMPHASIS_SHIFT);
5494
5495         if (lp_up2 == 0)
5496                 return;
5497
5498         for (bank = MDIO_REG_BANK_TX0; bank <= MDIO_REG_BANK_TX3;
5499               bank += (MDIO_REG_BANK_TX1 - MDIO_REG_BANK_TX0)) {
5500                 CL22_RD_OVER_CL45(bp, phy,
5501                                   bank,
5502                                   MDIO_TX0_TX_DRIVER, &tx_driver);
5503
5504                 /* replace tx_driver bits [15:12] */
5505                 if (lp_up2 !=
5506                     (tx_driver & MDIO_TX0_TX_DRIVER_PREEMPHASIS_MASK)) {
5507                         tx_driver &= ~MDIO_TX0_TX_DRIVER_PREEMPHASIS_MASK;
5508                         tx_driver |= lp_up2;
5509                         CL22_WR_OVER_CL45(bp, phy,
5510                                           bank,
5511                                           MDIO_TX0_TX_DRIVER, tx_driver);
5512                 }
5513         }
5514 }
5515
5516 static int bnx2x_emac_program(struct link_params *params,
5517                               struct link_vars *vars)
5518 {
5519         struct bnx2x *bp = params->bp;
5520         u8 port = params->port;
5521         u16 mode = 0;
5522
5523         DP(NETIF_MSG_LINK, "setting link speed & duplex\n");
5524         bnx2x_bits_dis(bp, GRCBASE_EMAC0 + port*0x400 +
5525                        EMAC_REG_EMAC_MODE,
5526                        (EMAC_MODE_25G_MODE |
5527                         EMAC_MODE_PORT_MII_10M |
5528                         EMAC_MODE_HALF_DUPLEX));
5529         switch (vars->line_speed) {
5530         case SPEED_10:
5531                 mode |= EMAC_MODE_PORT_MII_10M;
5532                 break;
5533
5534         case SPEED_100:
5535                 mode |= EMAC_MODE_PORT_MII;
5536                 break;
5537
5538         case SPEED_1000:
5539                 mode |= EMAC_MODE_PORT_GMII;
5540                 break;
5541
5542         case SPEED_2500:
5543                 mode |= (EMAC_MODE_25G_MODE | EMAC_MODE_PORT_GMII);
5544                 break;
5545
5546         default:
5547                 /* 10G not valid for EMAC */
5548                 DP(NETIF_MSG_LINK, "Invalid line_speed 0x%x\n",
5549                            vars->line_speed);
5550                 return -EINVAL;
5551         }
5552
5553         if (vars->duplex == DUPLEX_HALF)
5554                 mode |= EMAC_MODE_HALF_DUPLEX;
5555         bnx2x_bits_en(bp,
5556                       GRCBASE_EMAC0 + port*0x400 + EMAC_REG_EMAC_MODE,
5557                       mode);
5558
5559         bnx2x_set_led(params, vars, LED_MODE_OPER, vars->line_speed);
5560         return 0;
5561 }
5562
5563 static void bnx2x_set_preemphasis(struct bnx2x_phy *phy,
5564                                   struct link_params *params)
5565 {
5566
5567         u16 bank, i = 0;
5568         struct bnx2x *bp = params->bp;
5569
5570         for (bank = MDIO_REG_BANK_RX0, i = 0; bank <= MDIO_REG_BANK_RX3;
5571               bank += (MDIO_REG_BANK_RX1-MDIO_REG_BANK_RX0), i++) {
5572                         CL22_WR_OVER_CL45(bp, phy,
5573                                           bank,
5574                                           MDIO_RX0_RX_EQ_BOOST,
5575                                           phy->rx_preemphasis[i]);
5576         }
5577
5578         for (bank = MDIO_REG_BANK_TX0, i = 0; bank <= MDIO_REG_BANK_TX3;
5579                       bank += (MDIO_REG_BANK_TX1 - MDIO_REG_BANK_TX0), i++) {
5580                         CL22_WR_OVER_CL45(bp, phy,
5581                                           bank,
5582                                           MDIO_TX0_TX_DRIVER,
5583                                           phy->tx_preemphasis[i]);
5584         }
5585 }
5586
5587 static void bnx2x_xgxs_config_init(struct bnx2x_phy *phy,
5588                                    struct link_params *params,
5589                                    struct link_vars *vars)
5590 {
5591         struct bnx2x *bp = params->bp;
5592         u8 enable_cl73 = (SINGLE_MEDIA_DIRECT(params) ||
5593                           (params->loopback_mode == LOOPBACK_XGXS));
5594         if (!(vars->phy_flags & PHY_SGMII_FLAG)) {
5595                 if (SINGLE_MEDIA_DIRECT(params) &&
5596                     (params->feature_config_flags &
5597                      FEATURE_CONFIG_OVERRIDE_PREEMPHASIS_ENABLED))
5598                         bnx2x_set_preemphasis(phy, params);
5599
5600                 /* forced speed requested? */
5601                 if (vars->line_speed != SPEED_AUTO_NEG ||
5602                     (SINGLE_MEDIA_DIRECT(params) &&
5603                      params->loopback_mode == LOOPBACK_EXT)) {
5604                         DP(NETIF_MSG_LINK, "not SGMII, no AN\n");
5605
5606                         /* disable autoneg */
5607                         bnx2x_set_autoneg(phy, params, vars, 0);
5608
5609                         /* program speed and duplex */
5610                         bnx2x_program_serdes(phy, params, vars);
5611
5612                 } else { /* AN_mode */
5613                         DP(NETIF_MSG_LINK, "not SGMII, AN\n");
5614
5615                         /* AN enabled */
5616                         bnx2x_set_brcm_cl37_advertisement(phy, params);
5617
5618                         /* program duplex & pause advertisement (for aneg) */
5619                         bnx2x_set_ieee_aneg_advertisement(phy, params,
5620                                                           vars->ieee_fc);
5621
5622                         /* enable autoneg */
5623                         bnx2x_set_autoneg(phy, params, vars, enable_cl73);
5624
5625                         /* enable and restart AN */
5626                         bnx2x_restart_autoneg(phy, params, enable_cl73);
5627                 }
5628
5629         } else { /* SGMII mode */
5630                 DP(NETIF_MSG_LINK, "SGMII\n");
5631
5632                 bnx2x_initialize_sgmii_process(phy, params, vars);
5633         }
5634 }
5635
5636 static int bnx2x_prepare_xgxs(struct bnx2x_phy *phy,
5637                           struct link_params *params,
5638                           struct link_vars *vars)
5639 {
5640         int rc;
5641         vars->phy_flags |= PHY_XGXS_FLAG;
5642         if ((phy->req_line_speed &&
5643              ((phy->req_line_speed == SPEED_100) ||
5644               (phy->req_line_speed == SPEED_10))) ||
5645             (!phy->req_line_speed &&
5646              (phy->speed_cap_mask >=
5647               PORT_HW_CFG_SPEED_CAPABILITY_D0_10M_FULL) &&
5648              (phy->speed_cap_mask <
5649               PORT_HW_CFG_SPEED_CAPABILITY_D0_1G)) ||
5650             (phy->type == PORT_HW_CFG_SERDES_EXT_PHY_TYPE_DIRECT_SD))
5651                 vars->phy_flags |= PHY_SGMII_FLAG;
5652         else
5653                 vars->phy_flags &= ~PHY_SGMII_FLAG;
5654
5655         bnx2x_calc_ieee_aneg_adv(phy, params, &vars->ieee_fc);
5656         bnx2x_set_aer_mmd(params, phy);
5657         if (phy->type == PORT_HW_CFG_XGXS_EXT_PHY_TYPE_DIRECT)
5658                 bnx2x_set_master_ln(params, phy);
5659
5660         rc = bnx2x_reset_unicore(params, phy, 0);
5661         /* reset the SerDes and wait for reset bit return low */
5662         if (rc != 0)
5663                 return rc;
5664
5665         bnx2x_set_aer_mmd(params, phy);
5666         /* setting the masterLn_def again after the reset */
5667         if (phy->type == PORT_HW_CFG_XGXS_EXT_PHY_TYPE_DIRECT) {
5668                 bnx2x_set_master_ln(params, phy);
5669                 bnx2x_set_swap_lanes(params, phy);
5670         }
5671
5672         return rc;
5673 }
5674
5675 static u16 bnx2x_wait_reset_complete(struct bnx2x *bp,
5676                                      struct bnx2x_phy *phy,
5677                                      struct link_params *params)
5678 {
5679         u16 cnt, ctrl;
5680         /* Wait for soft reset to get cleared up to 1 sec */
5681         for (cnt = 0; cnt < 1000; cnt++) {
5682                 if (phy->type == PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM54618SE)
5683                         bnx2x_cl22_read(bp, phy,
5684                                 MDIO_PMA_REG_CTRL, &ctrl);
5685                 else
5686                         bnx2x_cl45_read(bp, phy,
5687                                 MDIO_PMA_DEVAD,
5688                                 MDIO_PMA_REG_CTRL, &ctrl);
5689                 if (!(ctrl & (1<<15)))
5690                         break;
5691                 msleep(1);
5692         }
5693
5694         if (cnt == 1000)
5695                 netdev_err(bp->dev,  "Warning: PHY was not initialized,"
5696                                       " Port %d\n",
5697                          params->port);
5698         DP(NETIF_MSG_LINK, "control reg 0x%x (after %d ms)\n", ctrl, cnt);
5699         return cnt;
5700 }
5701
5702 static void bnx2x_link_int_enable(struct link_params *params)
5703 {
5704         u8 port = params->port;
5705         u32 mask;
5706         struct bnx2x *bp = params->bp;
5707
5708         /* Setting the status to report on link up for either XGXS or SerDes */
5709         if (CHIP_IS_E3(bp)) {
5710                 mask = NIG_MASK_XGXS0_LINK_STATUS;
5711                 if (!(SINGLE_MEDIA_DIRECT(params)))
5712                         mask |= NIG_MASK_MI_INT;
5713         } else if (params->switch_cfg == SWITCH_CFG_10G) {
5714                 mask = (NIG_MASK_XGXS0_LINK10G |
5715                         NIG_MASK_XGXS0_LINK_STATUS);
5716                 DP(NETIF_MSG_LINK, "enabled XGXS interrupt\n");
5717                 if (!(SINGLE_MEDIA_DIRECT(params)) &&
5718                         params->phy[INT_PHY].type !=
5719                                 PORT_HW_CFG_XGXS_EXT_PHY_TYPE_FAILURE) {
5720                         mask |= NIG_MASK_MI_INT;
5721                         DP(NETIF_MSG_LINK, "enabled external phy int\n");
5722                 }
5723
5724         } else { /* SerDes */
5725                 mask = NIG_MASK_SERDES0_LINK_STATUS;
5726                 DP(NETIF_MSG_LINK, "enabled SerDes interrupt\n");
5727                 if (!(SINGLE_MEDIA_DIRECT(params)) &&
5728                         params->phy[INT_PHY].type !=
5729                                 PORT_HW_CFG_SERDES_EXT_PHY_TYPE_NOT_CONN) {
5730                         mask |= NIG_MASK_MI_INT;
5731                         DP(NETIF_MSG_LINK, "enabled external phy int\n");
5732                 }
5733         }
5734         bnx2x_bits_en(bp,
5735                       NIG_REG_MASK_INTERRUPT_PORT0 + port*4,
5736                       mask);
5737
5738         DP(NETIF_MSG_LINK, "port %x, is_xgxs %x, int_status 0x%x\n", port,
5739                  (params->switch_cfg == SWITCH_CFG_10G),
5740                  REG_RD(bp, NIG_REG_STATUS_INTERRUPT_PORT0 + port*4));
5741         DP(NETIF_MSG_LINK, " int_mask 0x%x, MI_INT %x, SERDES_LINK %x\n",
5742                  REG_RD(bp, NIG_REG_MASK_INTERRUPT_PORT0 + port*4),
5743                  REG_RD(bp, NIG_REG_EMAC0_STATUS_MISC_MI_INT + port*0x18),
5744                  REG_RD(bp, NIG_REG_SERDES0_STATUS_LINK_STATUS+port*0x3c));
5745         DP(NETIF_MSG_LINK, " 10G %x, XGXS_LINK %x\n",
5746            REG_RD(bp, NIG_REG_XGXS0_STATUS_LINK10G + port*0x68),
5747            REG_RD(bp, NIG_REG_XGXS0_STATUS_LINK_STATUS + port*0x68));
5748 }
5749
5750 static void bnx2x_rearm_latch_signal(struct bnx2x *bp, u8 port,
5751                                      u8 exp_mi_int)
5752 {
5753         u32 latch_status = 0;
5754
5755         /*
5756          * Disable the MI INT ( external phy int ) by writing 1 to the
5757          * status register. Link down indication is high-active-signal,
5758          * so in this case we need to write the status to clear the XOR
5759          */
5760         /* Read Latched signals */
5761         latch_status = REG_RD(bp,
5762                                     NIG_REG_LATCH_STATUS_0 + port*8);
5763         DP(NETIF_MSG_LINK, "latch_status = 0x%x\n", latch_status);
5764         /* Handle only those with latched-signal=up.*/
5765         if (exp_mi_int)
5766                 bnx2x_bits_en(bp,
5767                               NIG_REG_STATUS_INTERRUPT_PORT0
5768                               + port*4,
5769                               NIG_STATUS_EMAC0_MI_INT);
5770         else
5771                 bnx2x_bits_dis(bp,
5772                                NIG_REG_STATUS_INTERRUPT_PORT0
5773                                + port*4,
5774                                NIG_STATUS_EMAC0_MI_INT);
5775
5776         if (latch_status & 1) {
5777
5778                 /* For all latched-signal=up : Re-Arm Latch signals */
5779                 REG_WR(bp, NIG_REG_LATCH_STATUS_0 + port*8,
5780                        (latch_status & 0xfffe) | (latch_status & 1));
5781         }
5782         /* For all latched-signal=up,Write original_signal to status */
5783 }
5784
5785 static void bnx2x_link_int_ack(struct link_params *params,
5786                                struct link_vars *vars, u8 is_10g_plus)
5787 {
5788         struct bnx2x *bp = params->bp;
5789         u8 port = params->port;
5790         u32 mask;
5791         /*
5792          * First reset all status we assume only one line will be
5793          * change at a time
5794          */
5795         bnx2x_bits_dis(bp, NIG_REG_STATUS_INTERRUPT_PORT0 + port*4,
5796                        (NIG_STATUS_XGXS0_LINK10G |
5797                         NIG_STATUS_XGXS0_LINK_STATUS |
5798                         NIG_STATUS_SERDES0_LINK_STATUS));
5799         if (vars->phy_link_up) {
5800                 if (USES_WARPCORE(bp))
5801                         mask = NIG_STATUS_XGXS0_LINK_STATUS;
5802                 else {
5803                         if (is_10g_plus)
5804                                 mask = NIG_STATUS_XGXS0_LINK10G;
5805                         else if (params->switch_cfg == SWITCH_CFG_10G) {
5806                                 /*
5807                                  * Disable the link interrupt by writing 1 to
5808                                  * the relevant lane in the status register
5809                                  */
5810                                 u32 ser_lane =
5811                                         ((params->lane_config &
5812                                     PORT_HW_CFG_LANE_SWAP_CFG_MASTER_MASK) >>
5813                                     PORT_HW_CFG_LANE_SWAP_CFG_MASTER_SHIFT);
5814                                 mask = ((1 << ser_lane) <<
5815                                        NIG_STATUS_XGXS0_LINK_STATUS_SIZE);
5816                         } else
5817                                 mask = NIG_STATUS_SERDES0_LINK_STATUS;
5818                 }
5819                 DP(NETIF_MSG_LINK, "Ack link up interrupt with mask 0x%x\n",
5820                                mask);
5821                 bnx2x_bits_en(bp,
5822                               NIG_REG_STATUS_INTERRUPT_PORT0 + port*4,
5823                               mask);
5824         }
5825 }
5826
5827 static int bnx2x_format_ver(u32 num, u8 *str, u16 *len)
5828 {
5829         u8 *str_ptr = str;
5830         u32 mask = 0xf0000000;
5831         u8 shift = 8*4;
5832         u8 digit;
5833         u8 remove_leading_zeros = 1;
5834         if (*len < 10) {
5835                 /* Need more than 10chars for this format */
5836                 *str_ptr = '\0';
5837                 (*len)--;
5838                 return -EINVAL;
5839         }
5840         while (shift > 0) {
5841
5842                 shift -= 4;
5843                 digit = ((num & mask) >> shift);
5844                 if (digit == 0 && remove_leading_zeros) {
5845                         mask = mask >> 4;
5846                         continue;
5847                 } else if (digit < 0xa)
5848                         *str_ptr = digit + '0';
5849                 else
5850                         *str_ptr = digit - 0xa + 'a';
5851                 remove_leading_zeros = 0;
5852                 str_ptr++;
5853                 (*len)--;
5854                 mask = mask >> 4;
5855                 if (shift == 4*4) {
5856                         *str_ptr = '.';
5857                         str_ptr++;
5858                         (*len)--;
5859                         remove_leading_zeros = 1;
5860                 }
5861         }
5862         return 0;
5863 }
5864
5865
5866 static int bnx2x_null_format_ver(u32 spirom_ver, u8 *str, u16 *len)
5867 {
5868         str[0] = '\0';
5869         (*len)--;
5870         return 0;
5871 }
5872
5873 int bnx2x_get_ext_phy_fw_version(struct link_params *params, u8 driver_loaded,
5874                                  u8 *version, u16 len)
5875 {
5876         struct bnx2x *bp;
5877         u32 spirom_ver = 0;
5878         int status = 0;
5879         u8 *ver_p = version;
5880         u16 remain_len = len;
5881         if (version == NULL || params == NULL)
5882                 return -EINVAL;
5883         bp = params->bp;
5884
5885         /* Extract first external phy*/
5886         version[0] = '\0';
5887         spirom_ver = REG_RD(bp, params->phy[EXT_PHY1].ver_addr);
5888
5889         if (params->phy[EXT_PHY1].format_fw_ver) {
5890                 status |= params->phy[EXT_PHY1].format_fw_ver(spirom_ver,
5891                                                               ver_p,
5892                                                               &remain_len);
5893                 ver_p += (len - remain_len);
5894         }
5895         if ((params->num_phys == MAX_PHYS) &&
5896             (params->phy[EXT_PHY2].ver_addr != 0)) {
5897                 spirom_ver = REG_RD(bp, params->phy[EXT_PHY2].ver_addr);
5898                 if (params->phy[EXT_PHY2].format_fw_ver) {
5899                         *ver_p = '/';
5900                         ver_p++;
5901                         remain_len--;
5902                         status |= params->phy[EXT_PHY2].format_fw_ver(
5903                                 spirom_ver,
5904                                 ver_p,
5905                                 &remain_len);
5906                         ver_p = version + (len - remain_len);
5907                 }
5908         }
5909         *ver_p = '\0';
5910         return status;
5911 }
5912
5913 static void bnx2x_set_xgxs_loopback(struct bnx2x_phy *phy,
5914                                     struct link_params *params)
5915 {
5916         u8 port = params->port;
5917         struct bnx2x *bp = params->bp;
5918
5919         if (phy->req_line_speed != SPEED_1000) {
5920                 u32 md_devad = 0;
5921
5922                 DP(NETIF_MSG_LINK, "XGXS 10G loopback enable\n");
5923
5924                 if (!CHIP_IS_E3(bp)) {
5925                         /* change the uni_phy_addr in the nig */
5926                         md_devad = REG_RD(bp, (NIG_REG_XGXS0_CTRL_MD_DEVAD +
5927                                                port*0x18));
5928
5929                         REG_WR(bp, NIG_REG_XGXS0_CTRL_MD_DEVAD + port*0x18,
5930                                0x5);
5931                 }
5932
5933                 bnx2x_cl45_write(bp, phy,
5934                                  5,
5935                                  (MDIO_REG_BANK_AER_BLOCK +
5936                                   (MDIO_AER_BLOCK_AER_REG & 0xf)),
5937                                  0x2800);
5938
5939                 bnx2x_cl45_write(bp, phy,
5940                                  5,
5941                                  (MDIO_REG_BANK_CL73_IEEEB0 +
5942                                   (MDIO_CL73_IEEEB0_CL73_AN_CONTROL & 0xf)),
5943                                  0x6041);
5944                 msleep(200);
5945                 /* set aer mmd back */
5946                 bnx2x_set_aer_mmd(params, phy);
5947
5948                 if (!CHIP_IS_E3(bp)) {
5949                         /* and md_devad */
5950                         REG_WR(bp, NIG_REG_XGXS0_CTRL_MD_DEVAD + port*0x18,
5951                                md_devad);
5952                 }
5953         } else {
5954                 u16 mii_ctrl;
5955                 DP(NETIF_MSG_LINK, "XGXS 1G loopback enable\n");
5956                 bnx2x_cl45_read(bp, phy, 5,
5957                                 (MDIO_REG_BANK_COMBO_IEEE0 +
5958                                 (MDIO_COMBO_IEEE0_MII_CONTROL & 0xf)),
5959                                 &mii_ctrl);
5960                 bnx2x_cl45_write(bp, phy, 5,
5961                                  (MDIO_REG_BANK_COMBO_IEEE0 +
5962                                  (MDIO_COMBO_IEEE0_MII_CONTROL & 0xf)),
5963                                  mii_ctrl |
5964                                  MDIO_COMBO_IEEO_MII_CONTROL_LOOPBACK);
5965         }
5966 }
5967
5968 int bnx2x_set_led(struct link_params *params,
5969                   struct link_vars *vars, u8 mode, u32 speed)
5970 {
5971         u8 port = params->port;
5972         u16 hw_led_mode = params->hw_led_mode;
5973         int rc = 0;
5974         u8 phy_idx;
5975         u32 tmp;
5976         u32 emac_base = port ? GRCBASE_EMAC1 : GRCBASE_EMAC0;
5977         struct bnx2x *bp = params->bp;
5978         DP(NETIF_MSG_LINK, "bnx2x_set_led: port %x, mode %d\n", port, mode);
5979         DP(NETIF_MSG_LINK, "speed 0x%x, hw_led_mode 0x%x\n",
5980                  speed, hw_led_mode);
5981         /* In case */
5982         for (phy_idx = EXT_PHY1; phy_idx < MAX_PHYS; phy_idx++) {
5983                 if (params->phy[phy_idx].set_link_led) {
5984                         params->phy[phy_idx].set_link_led(
5985                                 &params->phy[phy_idx], params, mode);
5986                 }
5987         }
5988
5989         switch (mode) {
5990         case LED_MODE_FRONT_PANEL_OFF:
5991         case LED_MODE_OFF:
5992                 REG_WR(bp, NIG_REG_LED_10G_P0 + port*4, 0);
5993                 REG_WR(bp, NIG_REG_LED_MODE_P0 + port*4,
5994                        SHARED_HW_CFG_LED_MAC1);
5995
5996                 tmp = EMAC_RD(bp, EMAC_REG_EMAC_LED);
5997                 EMAC_WR(bp, EMAC_REG_EMAC_LED, (tmp | EMAC_LED_OVERRIDE));
5998                 break;
5999
6000         case LED_MODE_OPER:
6001                 /*
6002                  * For all other phys, OPER mode is same as ON, so in case
6003                  * link is down, do nothing
6004                  */
6005                 if (!vars->link_up)
6006                         break;
6007         case LED_MODE_ON:
6008                 if (((params->phy[EXT_PHY1].type ==
6009                           PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8727) ||
6010                          (params->phy[EXT_PHY1].type ==
6011                           PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8722)) &&
6012                     CHIP_IS_E2(bp) && params->num_phys == 2) {
6013                         /*
6014                          * This is a work-around for E2+8727 Configurations
6015                          */
6016                         if (mode == LED_MODE_ON ||
6017                                 speed == SPEED_10000){
6018                                 REG_WR(bp, NIG_REG_LED_MODE_P0 + port*4, 0);
6019                                 REG_WR(bp, NIG_REG_LED_10G_P0 + port*4, 1);
6020
6021                                 tmp = EMAC_RD(bp, EMAC_REG_EMAC_LED);
6022                                 EMAC_WR(bp, EMAC_REG_EMAC_LED,
6023                                         (tmp | EMAC_LED_OVERRIDE));
6024                                 /*
6025                                  * return here without enabling traffic
6026                                  * LED blink and setting rate in ON mode.
6027                                  * In oper mode, enabling LED blink
6028                                  * and setting rate is needed.
6029                                  */
6030                                 if (mode == LED_MODE_ON)
6031                                         return rc;
6032                         }
6033                 } else if (SINGLE_MEDIA_DIRECT(params)) {
6034                         /*
6035                          * This is a work-around for HW issue found when link
6036                          * is up in CL73
6037                          */
6038                         if ((!CHIP_IS_E3(bp)) ||
6039                             (CHIP_IS_E3(bp) &&
6040                              mode == LED_MODE_ON))
6041                                 REG_WR(bp, NIG_REG_LED_10G_P0 + port*4, 1);
6042
6043                         if (CHIP_IS_E1x(bp) ||
6044                             CHIP_IS_E2(bp) ||
6045                             (mode == LED_MODE_ON))
6046                                 REG_WR(bp, NIG_REG_LED_MODE_P0 + port*4, 0);
6047                         else
6048                                 REG_WR(bp, NIG_REG_LED_MODE_P0 + port*4,
6049                                        hw_led_mode);
6050                 } else
6051                         REG_WR(bp, NIG_REG_LED_MODE_P0 + port*4, hw_led_mode);
6052
6053                 REG_WR(bp, NIG_REG_LED_CONTROL_OVERRIDE_TRAFFIC_P0 + port*4, 0);
6054                 /* Set blinking rate to ~15.9Hz */
6055                 if (CHIP_IS_E3(bp))
6056                         REG_WR(bp, NIG_REG_LED_CONTROL_BLINK_RATE_P0 + port*4,
6057                                LED_BLINK_RATE_VAL_E3);
6058                 else
6059                         REG_WR(bp, NIG_REG_LED_CONTROL_BLINK_RATE_P0 + port*4,
6060                                LED_BLINK_RATE_VAL_E1X_E2);
6061                 REG_WR(bp, NIG_REG_LED_CONTROL_BLINK_RATE_ENA_P0 +
6062                        port*4, 1);
6063                 tmp = EMAC_RD(bp, EMAC_REG_EMAC_LED);
6064                 EMAC_WR(bp, EMAC_REG_EMAC_LED, (tmp & (~EMAC_LED_OVERRIDE)));
6065
6066                 if (CHIP_IS_E1(bp) &&
6067                     ((speed == SPEED_2500) ||
6068                      (speed == SPEED_1000) ||
6069                      (speed == SPEED_100) ||
6070                      (speed == SPEED_10))) {
6071                         /*
6072                          * On Everest 1 Ax chip versions for speeds less than
6073                          * 10G LED scheme is different
6074                          */
6075                         REG_WR(bp, NIG_REG_LED_CONTROL_OVERRIDE_TRAFFIC_P0
6076                                + port*4, 1);
6077                         REG_WR(bp, NIG_REG_LED_CONTROL_TRAFFIC_P0 +
6078                                port*4, 0);
6079                         REG_WR(bp, NIG_REG_LED_CONTROL_BLINK_TRAFFIC_P0 +
6080                                port*4, 1);
6081                 }
6082                 break;
6083
6084         default:
6085                 rc = -EINVAL;
6086                 DP(NETIF_MSG_LINK, "bnx2x_set_led: Invalid led mode %d\n",
6087                          mode);
6088                 break;
6089         }
6090         return rc;
6091
6092 }
6093
6094 /*
6095  * This function comes to reflect the actual link state read DIRECTLY from the
6096  * HW
6097  */
6098 int bnx2x_test_link(struct link_params *params, struct link_vars *vars,
6099                     u8 is_serdes)
6100 {
6101         struct bnx2x *bp = params->bp;
6102         u16 gp_status = 0, phy_index = 0;
6103         u8 ext_phy_link_up = 0, serdes_phy_type;
6104         struct link_vars temp_vars;
6105         struct bnx2x_phy *int_phy = &params->phy[INT_PHY];
6106
6107         if (CHIP_IS_E3(bp)) {
6108                 u16 link_up;
6109                 if (params->req_line_speed[LINK_CONFIG_IDX(INT_PHY)]
6110                     > SPEED_10000) {
6111                         /* Check 20G link */
6112                         bnx2x_cl45_read(bp, int_phy, MDIO_WC_DEVAD,
6113                                         1, &link_up);
6114                         bnx2x_cl45_read(bp, int_phy, MDIO_WC_DEVAD,
6115                                         1, &link_up);
6116                         link_up &= (1<<2);
6117                 } else {
6118                         /* Check 10G link and below*/
6119                         u8 lane = bnx2x_get_warpcore_lane(int_phy, params);
6120                         bnx2x_cl45_read(bp, int_phy, MDIO_WC_DEVAD,
6121                                         MDIO_WC_REG_GP2_STATUS_GP_2_1,
6122                                         &gp_status);
6123                         gp_status = ((gp_status >> 8) & 0xf) |
6124                                 ((gp_status >> 12) & 0xf);
6125                         link_up = gp_status & (1 << lane);
6126                 }
6127                 if (!link_up)
6128                         return -ESRCH;
6129         } else {
6130                 CL22_RD_OVER_CL45(bp, int_phy,
6131                           MDIO_REG_BANK_GP_STATUS,
6132                           MDIO_GP_STATUS_TOP_AN_STATUS1,
6133                           &gp_status);
6134         /* link is up only if both local phy and external phy are up */
6135         if (!(gp_status & MDIO_GP_STATUS_TOP_AN_STATUS1_LINK_STATUS))
6136                 return -ESRCH;
6137         }
6138         /* In XGXS loopback mode, do not check external PHY */
6139         if (params->loopback_mode == LOOPBACK_XGXS)
6140                 return 0;
6141
6142         switch (params->num_phys) {
6143         case 1:
6144                 /* No external PHY */
6145                 return 0;
6146         case 2:
6147                 ext_phy_link_up = params->phy[EXT_PHY1].read_status(
6148                         &params->phy[EXT_PHY1],
6149                         params, &temp_vars);
6150                 break;
6151         case 3: /* Dual Media */
6152                 for (phy_index = EXT_PHY1; phy_index < params->num_phys;
6153                       phy_index++) {
6154                         serdes_phy_type = ((params->phy[phy_index].media_type ==
6155                                             ETH_PHY_SFP_FIBER) ||
6156                                            (params->phy[phy_index].media_type ==
6157                                             ETH_PHY_XFP_FIBER) ||
6158                                            (params->phy[phy_index].media_type ==
6159                                             ETH_PHY_DA_TWINAX));
6160
6161                         if (is_serdes != serdes_phy_type)
6162                                 continue;
6163                         if (params->phy[phy_index].read_status) {
6164                                 ext_phy_link_up |=
6165                                         params->phy[phy_index].read_status(
6166                                                 &params->phy[phy_index],
6167                                                 params, &temp_vars);
6168                         }
6169                 }
6170                 break;
6171         }
6172         if (ext_phy_link_up)
6173                 return 0;
6174         return -ESRCH;
6175 }
6176
6177 static int bnx2x_link_initialize(struct link_params *params,
6178                                  struct link_vars *vars)
6179 {
6180         int rc = 0;
6181         u8 phy_index, non_ext_phy;
6182         struct bnx2x *bp = params->bp;
6183         /*
6184          * In case of external phy existence, the line speed would be the
6185          * line speed linked up by the external phy. In case it is direct
6186          * only, then the line_speed during initialization will be
6187          * equal to the req_line_speed
6188          */
6189         vars->line_speed = params->phy[INT_PHY].req_line_speed;
6190
6191         /*
6192          * Initialize the internal phy in case this is a direct board
6193          * (no external phys), or this board has external phy which requires
6194          * to first.
6195          */
6196         if (!USES_WARPCORE(bp))
6197                 bnx2x_prepare_xgxs(&params->phy[INT_PHY], params, vars);
6198         /* init ext phy and enable link state int */
6199         non_ext_phy = (SINGLE_MEDIA_DIRECT(params) ||
6200                        (params->loopback_mode == LOOPBACK_XGXS));
6201
6202         if (non_ext_phy ||
6203             (params->phy[EXT_PHY1].flags & FLAGS_INIT_XGXS_FIRST) ||
6204             (params->loopback_mode == LOOPBACK_EXT_PHY)) {
6205                 struct bnx2x_phy *phy = &params->phy[INT_PHY];
6206                 if (vars->line_speed == SPEED_AUTO_NEG &&
6207                     (CHIP_IS_E1x(bp) ||
6208                      CHIP_IS_E2(bp)))
6209                         bnx2x_set_parallel_detection(phy, params);
6210                         if (params->phy[INT_PHY].config_init)
6211                                 params->phy[INT_PHY].config_init(phy,
6212                                                                  params,
6213                                                                  vars);
6214         }
6215
6216         /* Init external phy*/
6217         if (non_ext_phy) {
6218                 if (params->phy[INT_PHY].supported &
6219                     SUPPORTED_FIBRE)
6220                         vars->link_status |= LINK_STATUS_SERDES_LINK;
6221         } else {
6222                 for (phy_index = EXT_PHY1; phy_index < params->num_phys;
6223                       phy_index++) {
6224                         /*
6225                          * No need to initialize second phy in case of first
6226                          * phy only selection. In case of second phy, we do
6227                          * need to initialize the first phy, since they are
6228                          * connected.
6229                          */
6230                         if (params->phy[phy_index].supported &
6231                             SUPPORTED_FIBRE)
6232                                 vars->link_status |= LINK_STATUS_SERDES_LINK;
6233
6234                         if (phy_index == EXT_PHY2 &&
6235                             (bnx2x_phy_selection(params) ==
6236                              PORT_HW_CFG_PHY_SELECTION_FIRST_PHY)) {
6237                                 DP(NETIF_MSG_LINK,
6238                                    "Not initializing second phy\n");
6239                                 continue;
6240                         }
6241                         params->phy[phy_index].config_init(
6242                                 &params->phy[phy_index],
6243                                 params, vars);
6244                 }
6245         }
6246         /* Reset the interrupt indication after phy was initialized */
6247         bnx2x_bits_dis(bp, NIG_REG_STATUS_INTERRUPT_PORT0 +
6248                        params->port*4,
6249                        (NIG_STATUS_XGXS0_LINK10G |
6250                         NIG_STATUS_XGXS0_LINK_STATUS |
6251                         NIG_STATUS_SERDES0_LINK_STATUS |
6252                         NIG_MASK_MI_INT));
6253         bnx2x_update_mng(params, vars->link_status);
6254         return rc;
6255 }
6256
6257 static void bnx2x_int_link_reset(struct bnx2x_phy *phy,
6258                                  struct link_params *params)
6259 {
6260         /* reset the SerDes/XGXS */
6261         REG_WR(params->bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_3_CLEAR,
6262                (0x1ff << (params->port*16)));
6263 }
6264
6265 static void bnx2x_common_ext_link_reset(struct bnx2x_phy *phy,
6266                                         struct link_params *params)
6267 {
6268         struct bnx2x *bp = params->bp;
6269         u8 gpio_port;
6270         /* HW reset */
6271         if (CHIP_IS_E2(bp))
6272                 gpio_port = BP_PATH(bp);
6273         else
6274                 gpio_port = params->port;
6275         bnx2x_set_gpio(bp, MISC_REGISTERS_GPIO_1,
6276                        MISC_REGISTERS_GPIO_OUTPUT_LOW,
6277                        gpio_port);
6278         bnx2x_set_gpio(bp, MISC_REGISTERS_GPIO_2,
6279                        MISC_REGISTERS_GPIO_OUTPUT_LOW,
6280                        gpio_port);
6281         DP(NETIF_MSG_LINK, "reset external PHY\n");
6282 }
6283
6284 static int bnx2x_update_link_down(struct link_params *params,
6285                                   struct link_vars *vars)
6286 {
6287         struct bnx2x *bp = params->bp;
6288         u8 port = params->port;
6289
6290         DP(NETIF_MSG_LINK, "Port %x: Link is down\n", port);
6291         bnx2x_set_led(params, vars, LED_MODE_OFF, 0);
6292         vars->phy_flags &= ~PHY_PHYSICAL_LINK_FLAG;
6293         /* indicate no mac active */
6294         vars->mac_type = MAC_TYPE_NONE;
6295
6296         /* update shared memory */
6297         vars->link_status &= ~(LINK_STATUS_SPEED_AND_DUPLEX_MASK |
6298                                LINK_STATUS_LINK_UP |
6299                                LINK_STATUS_PHYSICAL_LINK_FLAG |
6300                                LINK_STATUS_AUTO_NEGOTIATE_COMPLETE |
6301                                LINK_STATUS_RX_FLOW_CONTROL_FLAG_MASK |
6302                                LINK_STATUS_TX_FLOW_CONTROL_FLAG_MASK |
6303                                LINK_STATUS_PARALLEL_DETECTION_FLAG_MASK);
6304         vars->line_speed = 0;
6305         bnx2x_update_mng(params, vars->link_status);
6306
6307         /* activate nig drain */
6308         REG_WR(bp, NIG_REG_EGRESS_DRAIN0_MODE + port*4, 1);
6309
6310         /* disable emac */
6311         if (!CHIP_IS_E3(bp))
6312                 REG_WR(bp, NIG_REG_NIG_EMAC0_EN + port*4, 0);
6313
6314         msleep(10);
6315         /* reset BigMac/Xmac */
6316         if (CHIP_IS_E1x(bp) ||
6317             CHIP_IS_E2(bp)) {
6318                 bnx2x_bmac_rx_disable(bp, params->port);
6319                 REG_WR(bp, GRCBASE_MISC +
6320                        MISC_REGISTERS_RESET_REG_2_CLEAR,
6321                (MISC_REGISTERS_RESET_REG_2_RST_BMAC0 << port));
6322         }
6323         if (CHIP_IS_E3(bp)) {
6324                 bnx2x_xmac_disable(params);
6325                 bnx2x_umac_disable(params);
6326         }
6327
6328         return 0;
6329 }
6330
6331 static int bnx2x_update_link_up(struct link_params *params,
6332                                 struct link_vars *vars,
6333                                 u8 link_10g)
6334 {
6335         struct bnx2x *bp = params->bp;
6336         u8 port = params->port;
6337         int rc = 0;
6338
6339         vars->link_status |= (LINK_STATUS_LINK_UP |
6340                               LINK_STATUS_PHYSICAL_LINK_FLAG);
6341         vars->phy_flags |= PHY_PHYSICAL_LINK_FLAG;
6342
6343         if (vars->flow_ctrl & BNX2X_FLOW_CTRL_TX)
6344                 vars->link_status |=
6345                         LINK_STATUS_TX_FLOW_CONTROL_ENABLED;
6346
6347         if (vars->flow_ctrl & BNX2X_FLOW_CTRL_RX)
6348                 vars->link_status |=
6349                         LINK_STATUS_RX_FLOW_CONTROL_ENABLED;
6350         if (USES_WARPCORE(bp)) {
6351                 if (link_10g) {
6352                         if (bnx2x_xmac_enable(params, vars, 0) ==
6353                             -ESRCH) {
6354                                 DP(NETIF_MSG_LINK, "Found errors on XMAC\n");
6355                                 vars->link_up = 0;
6356                                 vars->phy_flags |= PHY_HALF_OPEN_CONN_FLAG;
6357                                 vars->link_status &= ~LINK_STATUS_LINK_UP;
6358                         }
6359                 } else
6360                         bnx2x_umac_enable(params, vars, 0);
6361                 bnx2x_set_led(params, vars,
6362                               LED_MODE_OPER, vars->line_speed);
6363         }
6364         if ((CHIP_IS_E1x(bp) ||
6365              CHIP_IS_E2(bp))) {
6366                 if (link_10g) {
6367                         if (bnx2x_bmac_enable(params, vars, 0) ==
6368                             -ESRCH) {
6369                                 DP(NETIF_MSG_LINK, "Found errors on BMAC\n");
6370                                 vars->link_up = 0;
6371                                 vars->phy_flags |= PHY_HALF_OPEN_CONN_FLAG;
6372                                 vars->link_status &= ~LINK_STATUS_LINK_UP;
6373                         }
6374
6375                         bnx2x_set_led(params, vars,
6376                                       LED_MODE_OPER, SPEED_10000);
6377                 } else {
6378                         rc = bnx2x_emac_program(params, vars);
6379                         bnx2x_emac_enable(params, vars, 0);
6380
6381                         /* AN complete? */
6382                         if ((vars->link_status &
6383                              LINK_STATUS_AUTO_NEGOTIATE_COMPLETE)
6384                             && (!(vars->phy_flags & PHY_SGMII_FLAG)) &&
6385                             SINGLE_MEDIA_DIRECT(params))
6386                                 bnx2x_set_gmii_tx_driver(params);
6387                 }
6388         }
6389
6390         /* PBF - link up */
6391         if (CHIP_IS_E1x(bp))
6392                 rc |= bnx2x_pbf_update(params, vars->flow_ctrl,
6393                                        vars->line_speed);
6394
6395         /* disable drain */
6396         REG_WR(bp, NIG_REG_EGRESS_DRAIN0_MODE + port*4, 0);
6397
6398         /* update shared memory */
6399         bnx2x_update_mng(params, vars->link_status);
6400         msleep(20);
6401         return rc;
6402 }
6403 /*
6404  * The bnx2x_link_update function should be called upon link
6405  * interrupt.
6406  * Link is considered up as follows:
6407  * - DIRECT_SINGLE_MEDIA - Only XGXS link (internal link) needs
6408  *   to be up
6409  * - SINGLE_MEDIA - The link between the 577xx and the external
6410  *   phy (XGXS) need to up as well as the external link of the
6411  *   phy (PHY_EXT1)
6412  * - DUAL_MEDIA - The link between the 577xx and the first
6413  *   external phy needs to be up, and at least one of the 2
6414  *   external phy link must be up.
6415  */
6416 int bnx2x_link_update(struct link_params *params, struct link_vars *vars)
6417 {
6418         struct bnx2x *bp = params->bp;
6419         struct link_vars phy_vars[MAX_PHYS];
6420         u8 port = params->port;
6421         u8 link_10g_plus, phy_index;
6422         u8 ext_phy_link_up = 0, cur_link_up;
6423         int rc = 0;
6424         u8 is_mi_int = 0;
6425         u16 ext_phy_line_speed = 0, prev_line_speed = vars->line_speed;
6426         u8 active_external_phy = INT_PHY;
6427         vars->phy_flags &= ~PHY_HALF_OPEN_CONN_FLAG;
6428         for (phy_index = INT_PHY; phy_index < params->num_phys;
6429               phy_index++) {
6430                 phy_vars[phy_index].flow_ctrl = 0;
6431                 phy_vars[phy_index].link_status = 0;
6432                 phy_vars[phy_index].line_speed = 0;
6433                 phy_vars[phy_index].duplex = DUPLEX_FULL;
6434                 phy_vars[phy_index].phy_link_up = 0;
6435                 phy_vars[phy_index].link_up = 0;
6436                 phy_vars[phy_index].fault_detected = 0;
6437         }
6438
6439         if (USES_WARPCORE(bp))
6440                 bnx2x_set_aer_mmd(params, &params->phy[INT_PHY]);
6441
6442         DP(NETIF_MSG_LINK, "port %x, XGXS?%x, int_status 0x%x\n",
6443                  port, (vars->phy_flags & PHY_XGXS_FLAG),
6444                  REG_RD(bp, NIG_REG_STATUS_INTERRUPT_PORT0 + port*4));
6445
6446         is_mi_int = (u8)(REG_RD(bp, NIG_REG_EMAC0_STATUS_MISC_MI_INT +
6447                                 port*0x18) > 0);
6448         DP(NETIF_MSG_LINK, "int_mask 0x%x MI_INT %x, SERDES_LINK %x\n",
6449                  REG_RD(bp, NIG_REG_MASK_INTERRUPT_PORT0 + port*4),
6450                  is_mi_int,
6451                  REG_RD(bp, NIG_REG_SERDES0_STATUS_LINK_STATUS + port*0x3c));
6452
6453         DP(NETIF_MSG_LINK, " 10G %x, XGXS_LINK %x\n",
6454           REG_RD(bp, NIG_REG_XGXS0_STATUS_LINK10G + port*0x68),
6455           REG_RD(bp, NIG_REG_XGXS0_STATUS_LINK_STATUS + port*0x68));
6456
6457         /* disable emac */
6458         if (!CHIP_IS_E3(bp))
6459                 REG_WR(bp, NIG_REG_NIG_EMAC0_EN + port*4, 0);
6460
6461         /*
6462          * Step 1:
6463          * Check external link change only for external phys, and apply
6464          * priority selection between them in case the link on both phys
6465          * is up. Note that instead of the common vars, a temporary
6466          * vars argument is used since each phy may have different link/
6467          * speed/duplex result
6468          */
6469         for (phy_index = EXT_PHY1; phy_index < params->num_phys;
6470               phy_index++) {
6471                 struct bnx2x_phy *phy = &params->phy[phy_index];
6472                 if (!phy->read_status)
6473                         continue;
6474                 /* Read link status and params of this ext phy */
6475                 cur_link_up = phy->read_status(phy, params,
6476                                                &phy_vars[phy_index]);
6477                 if (cur_link_up) {
6478                         DP(NETIF_MSG_LINK, "phy in index %d link is up\n",
6479                                    phy_index);
6480                 } else {
6481                         DP(NETIF_MSG_LINK, "phy in index %d link is down\n",
6482                                    phy_index);
6483                         continue;
6484                 }
6485
6486                 if (!ext_phy_link_up) {
6487                         ext_phy_link_up = 1;
6488                         active_external_phy = phy_index;
6489                 } else {
6490                         switch (bnx2x_phy_selection(params)) {
6491                         case PORT_HW_CFG_PHY_SELECTION_HARDWARE_DEFAULT:
6492                         case PORT_HW_CFG_PHY_SELECTION_FIRST_PHY_PRIORITY:
6493                         /*
6494                          * In this option, the first PHY makes sure to pass the
6495                          * traffic through itself only.
6496                          * Its not clear how to reset the link on the second phy
6497                          */
6498                                 active_external_phy = EXT_PHY1;
6499                                 break;
6500                         case PORT_HW_CFG_PHY_SELECTION_SECOND_PHY_PRIORITY:
6501                         /*
6502                          * In this option, the first PHY makes sure to pass the
6503                          * traffic through the second PHY.
6504                          */
6505                                 active_external_phy = EXT_PHY2;
6506                                 break;
6507                         default:
6508                         /*
6509                          * Link indication on both PHYs with the following cases
6510                          * is invalid:
6511                          * - FIRST_PHY means that second phy wasn't initialized,
6512                          * hence its link is expected to be down
6513                          * - SECOND_PHY means that first phy should not be able
6514                          * to link up by itself (using configuration)
6515                          * - DEFAULT should be overriden during initialiazation
6516                          */
6517                                 DP(NETIF_MSG_LINK, "Invalid link indication"
6518                                            "mpc=0x%x. DISABLING LINK !!!\n",
6519                                            params->multi_phy_config);
6520                                 ext_phy_link_up = 0;
6521                                 break;
6522                         }
6523                 }
6524         }
6525         prev_line_speed = vars->line_speed;
6526         /*
6527          * Step 2:
6528          * Read the status of the internal phy. In case of
6529          * DIRECT_SINGLE_MEDIA board, this link is the external link,
6530          * otherwise this is the link between the 577xx and the first
6531          * external phy
6532          */
6533         if (params->phy[INT_PHY].read_status)
6534                 params->phy[INT_PHY].read_status(
6535                         &params->phy[INT_PHY],
6536                         params, vars);
6537         /*
6538          * The INT_PHY flow control reside in the vars. This include the
6539          * case where the speed or flow control are not set to AUTO.
6540          * Otherwise, the active external phy flow control result is set
6541          * to the vars. The ext_phy_line_speed is needed to check if the
6542          * speed is different between the internal phy and external phy.
6543          * This case may be result of intermediate link speed change.
6544          */
6545         if (active_external_phy > INT_PHY) {
6546                 vars->flow_ctrl = phy_vars[active_external_phy].flow_ctrl;
6547                 /*
6548                  * Link speed is taken from the XGXS. AN and FC result from
6549                  * the external phy.
6550                  */
6551                 vars->link_status |= phy_vars[active_external_phy].link_status;
6552
6553                 /*
6554                  * if active_external_phy is first PHY and link is up - disable
6555                  * disable TX on second external PHY
6556                  */
6557                 if (active_external_phy == EXT_PHY1) {
6558                         if (params->phy[EXT_PHY2].phy_specific_func) {
6559                                 DP(NETIF_MSG_LINK,
6560                                    "Disabling TX on EXT_PHY2\n");
6561                                 params->phy[EXT_PHY2].phy_specific_func(
6562                                         &params->phy[EXT_PHY2],
6563                                         params, DISABLE_TX);
6564                         }
6565                 }
6566
6567                 ext_phy_line_speed = phy_vars[active_external_phy].line_speed;
6568                 vars->duplex = phy_vars[active_external_phy].duplex;
6569                 if (params->phy[active_external_phy].supported &
6570                     SUPPORTED_FIBRE)
6571                         vars->link_status |= LINK_STATUS_SERDES_LINK;
6572                 else
6573                         vars->link_status &= ~LINK_STATUS_SERDES_LINK;
6574                 DP(NETIF_MSG_LINK, "Active external phy selected: %x\n",
6575                            active_external_phy);
6576         }
6577
6578         for (phy_index = EXT_PHY1; phy_index < params->num_phys;
6579               phy_index++) {
6580                 if (params->phy[phy_index].flags &
6581                     FLAGS_REARM_LATCH_SIGNAL) {
6582                         bnx2x_rearm_latch_signal(bp, port,
6583                                                  phy_index ==
6584                                                  active_external_phy);
6585                         break;
6586                 }
6587         }
6588         DP(NETIF_MSG_LINK, "vars->flow_ctrl = 0x%x, vars->link_status = 0x%x,"
6589                    " ext_phy_line_speed = %d\n", vars->flow_ctrl,
6590                    vars->link_status, ext_phy_line_speed);
6591         /*
6592          * Upon link speed change set the NIG into drain mode. Comes to
6593          * deals with possible FIFO glitch due to clk change when speed
6594          * is decreased without link down indicator
6595          */
6596
6597         if (vars->phy_link_up) {
6598                 if (!(SINGLE_MEDIA_DIRECT(params)) && ext_phy_link_up &&
6599                     (ext_phy_line_speed != vars->line_speed)) {
6600                         DP(NETIF_MSG_LINK, "Internal link speed %d is"
6601                                    " different than the external"
6602                                    " link speed %d\n", vars->line_speed,
6603                                    ext_phy_line_speed);
6604                         vars->phy_link_up = 0;
6605                 } else if (prev_line_speed != vars->line_speed) {
6606                         REG_WR(bp, NIG_REG_EGRESS_DRAIN0_MODE + params->port*4,
6607                                0);
6608                         msleep(1);
6609                 }
6610         }
6611
6612         /* anything 10 and over uses the bmac */
6613         link_10g_plus = (vars->line_speed >= SPEED_10000);
6614
6615         bnx2x_link_int_ack(params, vars, link_10g_plus);
6616
6617         /*
6618          * In case external phy link is up, and internal link is down
6619          * (not initialized yet probably after link initialization, it
6620          * needs to be initialized.
6621          * Note that after link down-up as result of cable plug, the xgxs
6622          * link would probably become up again without the need
6623          * initialize it
6624          */
6625         if (!(SINGLE_MEDIA_DIRECT(params))) {
6626                 DP(NETIF_MSG_LINK, "ext_phy_link_up = %d, int_link_up = %d,"
6627                            " init_preceding = %d\n", ext_phy_link_up,
6628                            vars->phy_link_up,
6629                            params->phy[EXT_PHY1].flags &
6630                            FLAGS_INIT_XGXS_FIRST);
6631                 if (!(params->phy[EXT_PHY1].flags &
6632                       FLAGS_INIT_XGXS_FIRST)
6633                     && ext_phy_link_up && !vars->phy_link_up) {
6634                         vars->line_speed = ext_phy_line_speed;
6635                         if (vars->line_speed < SPEED_1000)
6636                                 vars->phy_flags |= PHY_SGMII_FLAG;
6637                         else
6638                                 vars->phy_flags &= ~PHY_SGMII_FLAG;
6639
6640                         if (params->phy[INT_PHY].config_init)
6641                                 params->phy[INT_PHY].config_init(
6642                                         &params->phy[INT_PHY], params,
6643                                                 vars);
6644                 }
6645         }
6646         /*
6647          * Link is up only if both local phy and external phy (in case of
6648          * non-direct board) are up and no fault detected on active PHY.
6649          */
6650         vars->link_up = (vars->phy_link_up &&
6651                          (ext_phy_link_up ||
6652                           SINGLE_MEDIA_DIRECT(params)) &&
6653                          (phy_vars[active_external_phy].fault_detected == 0));
6654
6655         if (vars->link_up)
6656                 rc = bnx2x_update_link_up(params, vars, link_10g_plus);
6657         else
6658                 rc = bnx2x_update_link_down(params, vars);
6659
6660         return rc;
6661 }
6662
6663
6664 /*****************************************************************************/
6665 /*                          External Phy section                             */
6666 /*****************************************************************************/
6667 void bnx2x_ext_phy_hw_reset(struct bnx2x *bp, u8 port)
6668 {
6669         bnx2x_set_gpio(bp, MISC_REGISTERS_GPIO_1,
6670                        MISC_REGISTERS_GPIO_OUTPUT_LOW, port);
6671         msleep(1);
6672         bnx2x_set_gpio(bp, MISC_REGISTERS_GPIO_1,
6673                        MISC_REGISTERS_GPIO_OUTPUT_HIGH, port);
6674 }
6675
6676 static void bnx2x_save_spirom_version(struct bnx2x *bp, u8 port,
6677                                       u32 spirom_ver, u32 ver_addr)
6678 {
6679         DP(NETIF_MSG_LINK, "FW version 0x%x:0x%x for port %d\n",
6680                  (u16)(spirom_ver>>16), (u16)spirom_ver, port);
6681
6682         if (ver_addr)
6683                 REG_WR(bp, ver_addr, spirom_ver);
6684 }
6685
6686 static void bnx2x_save_bcm_spirom_ver(struct bnx2x *bp,
6687                                       struct bnx2x_phy *phy,
6688                                       u8 port)
6689 {
6690         u16 fw_ver1, fw_ver2;
6691
6692         bnx2x_cl45_read(bp, phy, MDIO_PMA_DEVAD,
6693                         MDIO_PMA_REG_ROM_VER1, &fw_ver1);
6694         bnx2x_cl45_read(bp, phy, MDIO_PMA_DEVAD,
6695                         MDIO_PMA_REG_ROM_VER2, &fw_ver2);
6696         bnx2x_save_spirom_version(bp, port, (u32)(fw_ver1<<16 | fw_ver2),
6697                                   phy->ver_addr);
6698 }
6699
6700 static void bnx2x_ext_phy_10G_an_resolve(struct bnx2x *bp,
6701                                        struct bnx2x_phy *phy,
6702                                        struct link_vars *vars)
6703 {
6704         u16 val;
6705         bnx2x_cl45_read(bp, phy,
6706                         MDIO_AN_DEVAD,
6707                         MDIO_AN_REG_STATUS, &val);
6708         bnx2x_cl45_read(bp, phy,
6709                         MDIO_AN_DEVAD,
6710                         MDIO_AN_REG_STATUS, &val);
6711         if (val & (1<<5))
6712                 vars->link_status |= LINK_STATUS_AUTO_NEGOTIATE_COMPLETE;
6713         if ((val & (1<<0)) == 0)
6714                 vars->link_status |= LINK_STATUS_PARALLEL_DETECTION_USED;
6715 }
6716
6717 /******************************************************************/
6718 /*              common BCM8073/BCM8727 PHY SECTION                */
6719 /******************************************************************/
6720 static void bnx2x_8073_resolve_fc(struct bnx2x_phy *phy,
6721                                   struct link_params *params,
6722                                   struct link_vars *vars)
6723 {
6724         struct bnx2x *bp = params->bp;
6725         if (phy->req_line_speed == SPEED_10 ||
6726             phy->req_line_speed == SPEED_100) {
6727                 vars->flow_ctrl = phy->req_flow_ctrl;
6728                 return;
6729         }
6730
6731         if (bnx2x_ext_phy_resolve_fc(phy, params, vars) &&
6732             (vars->flow_ctrl == BNX2X_FLOW_CTRL_NONE)) {
6733                 u16 pause_result;
6734                 u16 ld_pause;           /* local */
6735                 u16 lp_pause;           /* link partner */
6736                 bnx2x_cl45_read(bp, phy,
6737                                 MDIO_AN_DEVAD,
6738                                 MDIO_AN_REG_CL37_FC_LD, &ld_pause);
6739
6740                 bnx2x_cl45_read(bp, phy,
6741                                 MDIO_AN_DEVAD,
6742                                 MDIO_AN_REG_CL37_FC_LP, &lp_pause);
6743                 pause_result = (ld_pause &
6744                                 MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_BOTH) >> 5;
6745                 pause_result |= (lp_pause &
6746                                  MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_BOTH) >> 7;
6747
6748                 bnx2x_pause_resolve(vars, pause_result);
6749                 DP(NETIF_MSG_LINK, "Ext PHY CL37 pause result 0x%x\n",
6750                            pause_result);
6751         }
6752 }
6753 static int bnx2x_8073_8727_external_rom_boot(struct bnx2x *bp,
6754                                              struct bnx2x_phy *phy,
6755                                              u8 port)
6756 {
6757         u32 count = 0;
6758         u16 fw_ver1, fw_msgout;
6759         int rc = 0;
6760
6761         /* Boot port from external ROM  */
6762         /* EDC grst */
6763         bnx2x_cl45_write(bp, phy,
6764                          MDIO_PMA_DEVAD,
6765                          MDIO_PMA_REG_GEN_CTRL,
6766                          0x0001);
6767
6768         /* ucode reboot and rst */
6769         bnx2x_cl45_write(bp, phy,
6770                          MDIO_PMA_DEVAD,
6771                          MDIO_PMA_REG_GEN_CTRL,
6772                          0x008c);
6773
6774         bnx2x_cl45_write(bp, phy,
6775                          MDIO_PMA_DEVAD,
6776                          MDIO_PMA_REG_MISC_CTRL1, 0x0001);
6777
6778         /* Reset internal microprocessor */
6779         bnx2x_cl45_write(bp, phy,
6780                          MDIO_PMA_DEVAD,
6781                          MDIO_PMA_REG_GEN_CTRL,
6782                          MDIO_PMA_REG_GEN_CTRL_ROM_MICRO_RESET);
6783
6784         /* Release srst bit */
6785         bnx2x_cl45_write(bp, phy,
6786                          MDIO_PMA_DEVAD,
6787                          MDIO_PMA_REG_GEN_CTRL,
6788                          MDIO_PMA_REG_GEN_CTRL_ROM_RESET_INTERNAL_MP);
6789
6790         /* Delay 100ms per the PHY specifications */
6791         msleep(100);
6792
6793         /* 8073 sometimes taking longer to download */
6794         do {
6795                 count++;
6796                 if (count > 300) {
6797                         DP(NETIF_MSG_LINK,
6798                                  "bnx2x_8073_8727_external_rom_boot port %x:"
6799                                  "Download failed. fw version = 0x%x\n",
6800                                  port, fw_ver1);
6801                         rc = -EINVAL;
6802                         break;
6803                 }
6804
6805                 bnx2x_cl45_read(bp, phy,
6806                                 MDIO_PMA_DEVAD,
6807                                 MDIO_PMA_REG_ROM_VER1, &fw_ver1);
6808                 bnx2x_cl45_read(bp, phy,
6809                                 MDIO_PMA_DEVAD,
6810                                 MDIO_PMA_REG_M8051_MSGOUT_REG, &fw_msgout);
6811
6812                 msleep(1);
6813         } while (fw_ver1 == 0 || fw_ver1 == 0x4321 ||
6814                         ((fw_msgout & 0xff) != 0x03 && (phy->type ==
6815                         PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8073)));
6816
6817         /* Clear ser_boot_ctl bit */
6818         bnx2x_cl45_write(bp, phy,
6819                          MDIO_PMA_DEVAD,
6820                          MDIO_PMA_REG_MISC_CTRL1, 0x0000);
6821         bnx2x_save_bcm_spirom_ver(bp, phy, port);
6822
6823         DP(NETIF_MSG_LINK,
6824                  "bnx2x_8073_8727_external_rom_boot port %x:"
6825                  "Download complete. fw version = 0x%x\n",
6826                  port, fw_ver1);
6827
6828         return rc;
6829 }
6830
6831 /******************************************************************/
6832 /*                      BCM8073 PHY SECTION                       */
6833 /******************************************************************/
6834 static int bnx2x_8073_is_snr_needed(struct bnx2x *bp, struct bnx2x_phy *phy)
6835 {
6836         /* This is only required for 8073A1, version 102 only */
6837         u16 val;
6838
6839         /* Read 8073 HW revision*/
6840         bnx2x_cl45_read(bp, phy,
6841                         MDIO_PMA_DEVAD,
6842                         MDIO_PMA_REG_8073_CHIP_REV, &val);
6843
6844         if (val != 1) {
6845                 /* No need to workaround in 8073 A1 */
6846                 return 0;
6847         }
6848
6849         bnx2x_cl45_read(bp, phy,
6850                         MDIO_PMA_DEVAD,
6851                         MDIO_PMA_REG_ROM_VER2, &val);
6852
6853         /* SNR should be applied only for version 0x102 */
6854         if (val != 0x102)
6855                 return 0;
6856
6857         return 1;
6858 }
6859
6860 static int bnx2x_8073_xaui_wa(struct bnx2x *bp, struct bnx2x_phy *phy)
6861 {
6862         u16 val, cnt, cnt1 ;
6863
6864         bnx2x_cl45_read(bp, phy,
6865                         MDIO_PMA_DEVAD,
6866                         MDIO_PMA_REG_8073_CHIP_REV, &val);
6867
6868         if (val > 0) {
6869                 /* No need to workaround in 8073 A1 */
6870                 return 0;
6871         }
6872         /* XAUI workaround in 8073 A0: */
6873
6874         /*
6875          * After loading the boot ROM and restarting Autoneg, poll
6876          * Dev1, Reg $C820:
6877          */
6878
6879         for (cnt = 0; cnt < 1000; cnt++) {
6880                 bnx2x_cl45_read(bp, phy,
6881                                 MDIO_PMA_DEVAD,
6882                                 MDIO_PMA_REG_8073_SPEED_LINK_STATUS,
6883                                 &val);
6884                   /*
6885                    * If bit [14] = 0 or bit [13] = 0, continue on with
6886                    * system initialization (XAUI work-around not required, as
6887                    * these bits indicate 2.5G or 1G link up).
6888                    */
6889                 if (!(val & (1<<14)) || !(val & (1<<13))) {
6890                         DP(NETIF_MSG_LINK, "XAUI work-around not required\n");
6891                         return 0;
6892                 } else if (!(val & (1<<15))) {
6893                         DP(NETIF_MSG_LINK, "bit 15 went off\n");
6894                         /*
6895                          * If bit 15 is 0, then poll Dev1, Reg $C841 until it's
6896                          * MSB (bit15) goes to 1 (indicating that the XAUI
6897                          * workaround has completed), then continue on with
6898                          * system initialization.
6899                          */
6900                         for (cnt1 = 0; cnt1 < 1000; cnt1++) {
6901                                 bnx2x_cl45_read(bp, phy,
6902                                         MDIO_PMA_DEVAD,
6903                                         MDIO_PMA_REG_8073_XAUI_WA, &val);
6904                                 if (val & (1<<15)) {
6905                                         DP(NETIF_MSG_LINK,
6906                                           "XAUI workaround has completed\n");
6907                                         return 0;
6908                                  }
6909                                  msleep(3);
6910                         }
6911                         break;
6912                 }
6913                 msleep(3);
6914         }
6915         DP(NETIF_MSG_LINK, "Warning: XAUI work-around timeout !!!\n");
6916         return -EINVAL;
6917 }
6918
6919 static void bnx2x_807x_force_10G(struct bnx2x *bp, struct bnx2x_phy *phy)
6920 {
6921         /* Force KR or KX */
6922         bnx2x_cl45_write(bp, phy,
6923                          MDIO_PMA_DEVAD, MDIO_PMA_REG_CTRL, 0x2040);
6924         bnx2x_cl45_write(bp, phy,
6925                          MDIO_PMA_DEVAD, MDIO_PMA_REG_10G_CTRL2, 0x000b);
6926         bnx2x_cl45_write(bp, phy,
6927                          MDIO_PMA_DEVAD, MDIO_PMA_REG_BCM_CTRL, 0x0000);
6928         bnx2x_cl45_write(bp, phy,
6929                          MDIO_AN_DEVAD, MDIO_AN_REG_CTRL, 0x0000);
6930 }
6931
6932 static void bnx2x_8073_set_pause_cl37(struct link_params *params,
6933                                       struct bnx2x_phy *phy,
6934                                       struct link_vars *vars)
6935 {
6936         u16 cl37_val;
6937         struct bnx2x *bp = params->bp;
6938         bnx2x_cl45_read(bp, phy,
6939                         MDIO_AN_DEVAD, MDIO_AN_REG_CL37_FC_LD, &cl37_val);
6940
6941         cl37_val &= ~MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_BOTH;
6942         /* Please refer to Table 28B-3 of 802.3ab-1999 spec. */
6943         bnx2x_calc_ieee_aneg_adv(phy, params, &vars->ieee_fc);
6944         if ((vars->ieee_fc &
6945             MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_SYMMETRIC) ==
6946             MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_SYMMETRIC) {
6947                 cl37_val |=  MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_SYMMETRIC;
6948         }
6949         if ((vars->ieee_fc &
6950             MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_ASYMMETRIC) ==
6951             MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_ASYMMETRIC) {
6952                 cl37_val |=  MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_ASYMMETRIC;
6953         }
6954         if ((vars->ieee_fc &
6955             MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_BOTH) ==
6956             MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_BOTH) {
6957                 cl37_val |= MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_BOTH;
6958         }
6959         DP(NETIF_MSG_LINK,
6960                  "Ext phy AN advertize cl37 0x%x\n", cl37_val);
6961
6962         bnx2x_cl45_write(bp, phy,
6963                          MDIO_AN_DEVAD, MDIO_AN_REG_CL37_FC_LD, cl37_val);
6964         msleep(500);
6965 }
6966
6967 static int bnx2x_8073_config_init(struct bnx2x_phy *phy,
6968                                   struct link_params *params,
6969                                   struct link_vars *vars)
6970 {
6971         struct bnx2x *bp = params->bp;
6972         u16 val = 0, tmp1;
6973         u8 gpio_port;
6974         DP(NETIF_MSG_LINK, "Init 8073\n");
6975
6976         if (CHIP_IS_E2(bp))
6977                 gpio_port = BP_PATH(bp);
6978         else
6979                 gpio_port = params->port;
6980         /* Restore normal power mode*/
6981         bnx2x_set_gpio(bp, MISC_REGISTERS_GPIO_2,
6982                        MISC_REGISTERS_GPIO_OUTPUT_HIGH, gpio_port);
6983
6984         bnx2x_set_gpio(bp, MISC_REGISTERS_GPIO_1,
6985                        MISC_REGISTERS_GPIO_OUTPUT_HIGH, gpio_port);
6986
6987         /* enable LASI */
6988         bnx2x_cl45_write(bp, phy,
6989                          MDIO_PMA_DEVAD, MDIO_PMA_LASI_RXCTRL, (1<<2));
6990         bnx2x_cl45_write(bp, phy,
6991                          MDIO_PMA_DEVAD, MDIO_PMA_LASI_CTRL,  0x0004);
6992
6993         bnx2x_8073_set_pause_cl37(params, phy, vars);
6994
6995         bnx2x_cl45_read(bp, phy,
6996                         MDIO_PMA_DEVAD, MDIO_PMA_REG_M8051_MSGOUT_REG, &tmp1);
6997
6998         bnx2x_cl45_read(bp, phy,
6999                         MDIO_PMA_DEVAD, MDIO_PMA_LASI_RXSTAT, &tmp1);
7000
7001         DP(NETIF_MSG_LINK, "Before rom RX_ALARM(port1): 0x%x\n", tmp1);
7002
7003         /* Swap polarity if required - Must be done only in non-1G mode */
7004         if (params->lane_config & PORT_HW_CFG_SWAP_PHY_POLARITY_ENABLED) {
7005                 /* Configure the 8073 to swap _P and _N of the KR lines */
7006                 DP(NETIF_MSG_LINK, "Swapping polarity for the 8073\n");
7007                 /* 10G Rx/Tx and 1G Tx signal polarity swap */
7008                 bnx2x_cl45_read(bp, phy,
7009                                 MDIO_PMA_DEVAD,
7010                                 MDIO_PMA_REG_8073_OPT_DIGITAL_CTRL, &val);
7011                 bnx2x_cl45_write(bp, phy,
7012                                  MDIO_PMA_DEVAD,
7013                                  MDIO_PMA_REG_8073_OPT_DIGITAL_CTRL,
7014                                  (val | (3<<9)));
7015         }
7016
7017
7018         /* Enable CL37 BAM */
7019         if (REG_RD(bp, params->shmem_base +
7020                          offsetof(struct shmem_region, dev_info.
7021                                   port_hw_config[params->port].default_cfg)) &
7022             PORT_HW_CFG_ENABLE_BAM_ON_KR_ENABLED) {
7023
7024                 bnx2x_cl45_read(bp, phy,
7025                                 MDIO_AN_DEVAD,
7026                                 MDIO_AN_REG_8073_BAM, &val);
7027                 bnx2x_cl45_write(bp, phy,
7028                                  MDIO_AN_DEVAD,
7029                                  MDIO_AN_REG_8073_BAM, val | 1);
7030                 DP(NETIF_MSG_LINK, "Enable CL37 BAM on KR\n");
7031         }
7032         if (params->loopback_mode == LOOPBACK_EXT) {
7033                 bnx2x_807x_force_10G(bp, phy);
7034                 DP(NETIF_MSG_LINK, "Forced speed 10G on 807X\n");
7035                 return 0;
7036         } else {
7037                 bnx2x_cl45_write(bp, phy,
7038                                  MDIO_PMA_DEVAD, MDIO_PMA_REG_BCM_CTRL, 0x0002);
7039         }
7040         if (phy->req_line_speed != SPEED_AUTO_NEG) {
7041                 if (phy->req_line_speed == SPEED_10000) {
7042                         val = (1<<7);
7043                 } else if (phy->req_line_speed ==  SPEED_2500) {
7044                         val = (1<<5);
7045                         /*
7046                          * Note that 2.5G works only when used with 1G
7047                          * advertisement
7048                          */
7049                 } else
7050                         val = (1<<5);
7051         } else {
7052                 val = 0;
7053                 if (phy->speed_cap_mask &
7054                         PORT_HW_CFG_SPEED_CAPABILITY_D0_10G)
7055                         val |= (1<<7);
7056
7057                 /* Note that 2.5G works only when used with 1G advertisement */
7058                 if (phy->speed_cap_mask &
7059                         (PORT_HW_CFG_SPEED_CAPABILITY_D0_1G |
7060                          PORT_HW_CFG_SPEED_CAPABILITY_D0_2_5G))
7061                         val |= (1<<5);
7062                 DP(NETIF_MSG_LINK, "807x autoneg val = 0x%x\n", val);
7063         }
7064
7065         bnx2x_cl45_write(bp, phy, MDIO_AN_DEVAD, MDIO_AN_REG_ADV, val);
7066         bnx2x_cl45_read(bp, phy, MDIO_AN_DEVAD, MDIO_AN_REG_8073_2_5G, &tmp1);
7067
7068         if (((phy->speed_cap_mask & PORT_HW_CFG_SPEED_CAPABILITY_D0_2_5G) &&
7069              (phy->req_line_speed == SPEED_AUTO_NEG)) ||
7070             (phy->req_line_speed == SPEED_2500)) {
7071                 u16 phy_ver;
7072                 /* Allow 2.5G for A1 and above */
7073                 bnx2x_cl45_read(bp, phy,
7074                                 MDIO_PMA_DEVAD, MDIO_PMA_REG_8073_CHIP_REV,
7075                                 &phy_ver);
7076                 DP(NETIF_MSG_LINK, "Add 2.5G\n");
7077                 if (phy_ver > 0)
7078                         tmp1 |= 1;
7079                 else
7080                         tmp1 &= 0xfffe;
7081         } else {
7082                 DP(NETIF_MSG_LINK, "Disable 2.5G\n");
7083                 tmp1 &= 0xfffe;
7084         }
7085
7086         bnx2x_cl45_write(bp, phy, MDIO_AN_DEVAD, MDIO_AN_REG_8073_2_5G, tmp1);
7087         /* Add support for CL37 (passive mode) II */
7088
7089         bnx2x_cl45_read(bp, phy, MDIO_AN_DEVAD, MDIO_AN_REG_CL37_FC_LD, &tmp1);
7090         bnx2x_cl45_write(bp, phy, MDIO_AN_DEVAD, MDIO_AN_REG_CL37_FC_LD,
7091                          (tmp1 | ((phy->req_duplex == DUPLEX_FULL) ?
7092                                   0x20 : 0x40)));
7093
7094         /* Add support for CL37 (passive mode) III */
7095         bnx2x_cl45_write(bp, phy, MDIO_AN_DEVAD, MDIO_AN_REG_CL37_AN, 0x1000);
7096
7097         /*
7098          * The SNR will improve about 2db by changing BW and FEE main
7099          * tap. Rest commands are executed after link is up
7100          * Change FFE main cursor to 5 in EDC register
7101          */
7102         if (bnx2x_8073_is_snr_needed(bp, phy))
7103                 bnx2x_cl45_write(bp, phy,
7104                                  MDIO_PMA_DEVAD, MDIO_PMA_REG_EDC_FFE_MAIN,
7105                                  0xFB0C);
7106
7107         /* Enable FEC (Forware Error Correction) Request in the AN */
7108         bnx2x_cl45_read(bp, phy, MDIO_AN_DEVAD, MDIO_AN_REG_ADV2, &tmp1);
7109         tmp1 |= (1<<15);
7110         bnx2x_cl45_write(bp, phy, MDIO_AN_DEVAD, MDIO_AN_REG_ADV2, tmp1);
7111
7112         bnx2x_ext_phy_set_pause(params, phy, vars);
7113
7114         /* Restart autoneg */
7115         msleep(500);
7116         bnx2x_cl45_write(bp, phy, MDIO_AN_DEVAD, MDIO_AN_REG_CTRL, 0x1200);
7117         DP(NETIF_MSG_LINK, "807x Autoneg Restart: Advertise 1G=%x, 10G=%x\n",
7118                    ((val & (1<<5)) > 0), ((val & (1<<7)) > 0));
7119         return 0;
7120 }
7121
7122 static u8 bnx2x_8073_read_status(struct bnx2x_phy *phy,
7123                                  struct link_params *params,
7124                                  struct link_vars *vars)
7125 {
7126         struct bnx2x *bp = params->bp;
7127         u8 link_up = 0;
7128         u16 val1, val2;
7129         u16 link_status = 0;
7130         u16 an1000_status = 0;
7131
7132         bnx2x_cl45_read(bp, phy,
7133                         MDIO_PMA_DEVAD, MDIO_PMA_LASI_STAT, &val1);
7134
7135         DP(NETIF_MSG_LINK, "8703 LASI status 0x%x\n", val1);
7136
7137         /* clear the interrupt LASI status register */
7138         bnx2x_cl45_read(bp, phy,
7139                         MDIO_PCS_DEVAD, MDIO_PCS_REG_STATUS, &val2);
7140         bnx2x_cl45_read(bp, phy,
7141                         MDIO_PCS_DEVAD, MDIO_PCS_REG_STATUS, &val1);
7142         DP(NETIF_MSG_LINK, "807x PCS status 0x%x->0x%x\n", val2, val1);
7143         /* Clear MSG-OUT */
7144         bnx2x_cl45_read(bp, phy,
7145                         MDIO_PMA_DEVAD, MDIO_PMA_REG_M8051_MSGOUT_REG, &val1);
7146
7147         /* Check the LASI */
7148         bnx2x_cl45_read(bp, phy,
7149                         MDIO_PMA_DEVAD, MDIO_PMA_LASI_RXSTAT, &val2);
7150
7151         DP(NETIF_MSG_LINK, "KR 0x9003 0x%x\n", val2);
7152
7153         /* Check the link status */
7154         bnx2x_cl45_read(bp, phy,
7155                         MDIO_PCS_DEVAD, MDIO_PCS_REG_STATUS, &val2);
7156         DP(NETIF_MSG_LINK, "KR PCS status 0x%x\n", val2);
7157
7158         bnx2x_cl45_read(bp, phy,
7159                         MDIO_PMA_DEVAD, MDIO_PMA_REG_STATUS, &val2);
7160         bnx2x_cl45_read(bp, phy,
7161                         MDIO_PMA_DEVAD, MDIO_PMA_REG_STATUS, &val1);
7162         link_up = ((val1 & 4) == 4);
7163         DP(NETIF_MSG_LINK, "PMA_REG_STATUS=0x%x\n", val1);
7164
7165         if (link_up &&
7166              ((phy->req_line_speed != SPEED_10000))) {
7167                 if (bnx2x_8073_xaui_wa(bp, phy) != 0)
7168                         return 0;
7169         }
7170         bnx2x_cl45_read(bp, phy,
7171                         MDIO_AN_DEVAD, MDIO_AN_REG_LINK_STATUS, &an1000_status);
7172         bnx2x_cl45_read(bp, phy,
7173                         MDIO_AN_DEVAD, MDIO_AN_REG_LINK_STATUS, &an1000_status);
7174
7175         /* Check the link status on 1.1.2 */
7176         bnx2x_cl45_read(bp, phy,
7177                         MDIO_PMA_DEVAD, MDIO_PMA_REG_STATUS, &val2);
7178         bnx2x_cl45_read(bp, phy,
7179                         MDIO_PMA_DEVAD, MDIO_PMA_REG_STATUS, &val1);
7180         DP(NETIF_MSG_LINK, "KR PMA status 0x%x->0x%x,"
7181                    "an_link_status=0x%x\n", val2, val1, an1000_status);
7182
7183         link_up = (((val1 & 4) == 4) || (an1000_status & (1<<1)));
7184         if (link_up && bnx2x_8073_is_snr_needed(bp, phy)) {
7185                 /*
7186                  * The SNR will improve about 2dbby changing the BW and FEE main
7187                  * tap. The 1st write to change FFE main tap is set before
7188                  * restart AN. Change PLL Bandwidth in EDC register
7189                  */
7190                 bnx2x_cl45_write(bp, phy,
7191                                  MDIO_PMA_DEVAD, MDIO_PMA_REG_PLL_BANDWIDTH,
7192                                  0x26BC);
7193
7194                 /* Change CDR Bandwidth in EDC register */
7195                 bnx2x_cl45_write(bp, phy,
7196                                  MDIO_PMA_DEVAD, MDIO_PMA_REG_CDR_BANDWIDTH,
7197                                  0x0333);
7198         }
7199         bnx2x_cl45_read(bp, phy,
7200                         MDIO_PMA_DEVAD, MDIO_PMA_REG_8073_SPEED_LINK_STATUS,
7201                         &link_status);
7202
7203         /* Bits 0..2 --> speed detected, bits 13..15--> link is down */
7204         if ((link_status & (1<<2)) && (!(link_status & (1<<15)))) {
7205                 link_up = 1;
7206                 vars->line_speed = SPEED_10000;
7207                 DP(NETIF_MSG_LINK, "port %x: External link up in 10G\n",
7208                            params->port);
7209         } else if ((link_status & (1<<1)) && (!(link_status & (1<<14)))) {
7210                 link_up = 1;
7211                 vars->line_speed = SPEED_2500;
7212                 DP(NETIF_MSG_LINK, "port %x: External link up in 2.5G\n",
7213                            params->port);
7214         } else if ((link_status & (1<<0)) && (!(link_status & (1<<13)))) {
7215                 link_up = 1;
7216                 vars->line_speed = SPEED_1000;
7217                 DP(NETIF_MSG_LINK, "port %x: External link up in 1G\n",
7218                            params->port);
7219         } else {
7220                 link_up = 0;
7221                 DP(NETIF_MSG_LINK, "port %x: External link is down\n",
7222                            params->port);
7223         }
7224
7225         if (link_up) {
7226                 /* Swap polarity if required */
7227                 if (params->lane_config &
7228                     PORT_HW_CFG_SWAP_PHY_POLARITY_ENABLED) {
7229                         /* Configure the 8073 to swap P and N of the KR lines */
7230                         bnx2x_cl45_read(bp, phy,
7231                                         MDIO_XS_DEVAD,
7232                                         MDIO_XS_REG_8073_RX_CTRL_PCIE, &val1);
7233                         /*
7234                          * Set bit 3 to invert Rx in 1G mode and clear this bit
7235                          * when it`s in 10G mode.
7236                          */
7237                         if (vars->line_speed == SPEED_1000) {
7238                                 DP(NETIF_MSG_LINK, "Swapping 1G polarity for"
7239                                               "the 8073\n");
7240                                 val1 |= (1<<3);
7241                         } else
7242                                 val1 &= ~(1<<3);
7243
7244                         bnx2x_cl45_write(bp, phy,
7245                                          MDIO_XS_DEVAD,
7246                                          MDIO_XS_REG_8073_RX_CTRL_PCIE,
7247                                          val1);
7248                 }
7249                 bnx2x_ext_phy_10G_an_resolve(bp, phy, vars);
7250                 bnx2x_8073_resolve_fc(phy, params, vars);
7251                 vars->duplex = DUPLEX_FULL;
7252         }
7253         return link_up;
7254 }
7255
7256 static void bnx2x_8073_link_reset(struct bnx2x_phy *phy,
7257                                   struct link_params *params)
7258 {
7259         struct bnx2x *bp = params->bp;
7260         u8 gpio_port;
7261         if (CHIP_IS_E2(bp))
7262                 gpio_port = BP_PATH(bp);
7263         else
7264                 gpio_port = params->port;
7265         DP(NETIF_MSG_LINK, "Setting 8073 port %d into low power mode\n",
7266            gpio_port);
7267         bnx2x_set_gpio(bp, MISC_REGISTERS_GPIO_2,
7268                        MISC_REGISTERS_GPIO_OUTPUT_LOW,
7269                        gpio_port);
7270 }
7271
7272 /******************************************************************/
7273 /*                      BCM8705 PHY SECTION                       */
7274 /******************************************************************/
7275 static int bnx2x_8705_config_init(struct bnx2x_phy *phy,
7276                                   struct link_params *params,
7277                                   struct link_vars *vars)
7278 {
7279         struct bnx2x *bp = params->bp;
7280         DP(NETIF_MSG_LINK, "init 8705\n");
7281         /* Restore normal power mode*/
7282         bnx2x_set_gpio(bp, MISC_REGISTERS_GPIO_2,
7283                        MISC_REGISTERS_GPIO_OUTPUT_HIGH, params->port);
7284         /* HW reset */
7285         bnx2x_ext_phy_hw_reset(bp, params->port);
7286         bnx2x_cl45_write(bp, phy, MDIO_PMA_DEVAD, MDIO_PMA_REG_CTRL, 0xa040);
7287         bnx2x_wait_reset_complete(bp, phy, params);
7288
7289         bnx2x_cl45_write(bp, phy,
7290                          MDIO_PMA_DEVAD, MDIO_PMA_REG_MISC_CTRL, 0x8288);
7291         bnx2x_cl45_write(bp, phy,
7292                          MDIO_PMA_DEVAD, MDIO_PMA_REG_PHY_IDENTIFIER, 0x7fbf);
7293         bnx2x_cl45_write(bp, phy,
7294                          MDIO_PMA_DEVAD, MDIO_PMA_REG_CMU_PLL_BYPASS, 0x0100);
7295         bnx2x_cl45_write(bp, phy,
7296                          MDIO_WIS_DEVAD, MDIO_WIS_REG_LASI_CNTL, 0x1);
7297         /* BCM8705 doesn't have microcode, hence the 0 */
7298         bnx2x_save_spirom_version(bp, params->port, params->shmem_base, 0);
7299         return 0;
7300 }
7301
7302 static u8 bnx2x_8705_read_status(struct bnx2x_phy *phy,
7303                                  struct link_params *params,
7304                                  struct link_vars *vars)
7305 {
7306         u8 link_up = 0;
7307         u16 val1, rx_sd;
7308         struct bnx2x *bp = params->bp;
7309         DP(NETIF_MSG_LINK, "read status 8705\n");
7310         bnx2x_cl45_read(bp, phy,
7311                       MDIO_WIS_DEVAD, MDIO_WIS_REG_LASI_STATUS, &val1);
7312         DP(NETIF_MSG_LINK, "8705 LASI status 0x%x\n", val1);
7313
7314         bnx2x_cl45_read(bp, phy,
7315                       MDIO_WIS_DEVAD, MDIO_WIS_REG_LASI_STATUS, &val1);
7316         DP(NETIF_MSG_LINK, "8705 LASI status 0x%x\n", val1);
7317
7318         bnx2x_cl45_read(bp, phy,
7319                       MDIO_PMA_DEVAD, MDIO_PMA_REG_RX_SD, &rx_sd);
7320
7321         bnx2x_cl45_read(bp, phy,
7322                       MDIO_PMA_DEVAD, 0xc809, &val1);
7323         bnx2x_cl45_read(bp, phy,
7324                       MDIO_PMA_DEVAD, 0xc809, &val1);
7325
7326         DP(NETIF_MSG_LINK, "8705 1.c809 val=0x%x\n", val1);
7327         link_up = ((rx_sd & 0x1) && (val1 & (1<<9)) && ((val1 & (1<<8)) == 0));
7328         if (link_up) {
7329                 vars->line_speed = SPEED_10000;
7330                 bnx2x_ext_phy_resolve_fc(phy, params, vars);
7331         }
7332         return link_up;
7333 }
7334
7335 /******************************************************************/
7336 /*                      SFP+ module Section                       */
7337 /******************************************************************/
7338 static void bnx2x_set_disable_pmd_transmit(struct link_params *params,
7339                                            struct bnx2x_phy *phy,
7340                                            u8 pmd_dis)
7341 {
7342         struct bnx2x *bp = params->bp;
7343         /*
7344          * Disable transmitter only for bootcodes which can enable it afterwards
7345          * (for D3 link)
7346          */
7347         if (pmd_dis) {
7348                 if (params->feature_config_flags &
7349                      FEATURE_CONFIG_BC_SUPPORTS_SFP_TX_DISABLED)
7350                         DP(NETIF_MSG_LINK, "Disabling PMD transmitter\n");
7351                 else {
7352                         DP(NETIF_MSG_LINK, "NOT disabling PMD transmitter\n");
7353                         return;
7354                 }
7355         } else
7356                 DP(NETIF_MSG_LINK, "Enabling PMD transmitter\n");
7357         bnx2x_cl45_write(bp, phy,
7358                          MDIO_PMA_DEVAD,
7359                          MDIO_PMA_REG_TX_DISABLE, pmd_dis);
7360 }
7361
7362 static u8 bnx2x_get_gpio_port(struct link_params *params)
7363 {
7364         u8 gpio_port;
7365         u32 swap_val, swap_override;
7366         struct bnx2x *bp = params->bp;
7367         if (CHIP_IS_E2(bp))
7368                 gpio_port = BP_PATH(bp);
7369         else
7370                 gpio_port = params->port;
7371         swap_val = REG_RD(bp, NIG_REG_PORT_SWAP);
7372         swap_override = REG_RD(bp, NIG_REG_STRAP_OVERRIDE);
7373         return gpio_port ^ (swap_val && swap_override);
7374 }
7375
7376 static void bnx2x_sfp_e1e2_set_transmitter(struct link_params *params,
7377                                            struct bnx2x_phy *phy,
7378                                            u8 tx_en)
7379 {
7380         u16 val;
7381         u8 port = params->port;
7382         struct bnx2x *bp = params->bp;
7383         u32 tx_en_mode;
7384
7385         /* Disable/Enable transmitter ( TX laser of the SFP+ module.)*/
7386         tx_en_mode = REG_RD(bp, params->shmem_base +
7387                             offsetof(struct shmem_region,
7388                                      dev_info.port_hw_config[port].sfp_ctrl)) &
7389                 PORT_HW_CFG_TX_LASER_MASK;
7390         DP(NETIF_MSG_LINK, "Setting transmitter tx_en=%x for port %x "
7391                            "mode = %x\n", tx_en, port, tx_en_mode);
7392         switch (tx_en_mode) {
7393         case PORT_HW_CFG_TX_LASER_MDIO:
7394
7395                 bnx2x_cl45_read(bp, phy,
7396                                 MDIO_PMA_DEVAD,
7397                                 MDIO_PMA_REG_PHY_IDENTIFIER,
7398                                 &val);
7399
7400                 if (tx_en)
7401                         val &= ~(1<<15);
7402                 else
7403                         val |= (1<<15);
7404
7405                 bnx2x_cl45_write(bp, phy,
7406                                  MDIO_PMA_DEVAD,
7407                                  MDIO_PMA_REG_PHY_IDENTIFIER,
7408                                  val);
7409         break;
7410         case PORT_HW_CFG_TX_LASER_GPIO0:
7411         case PORT_HW_CFG_TX_LASER_GPIO1:
7412         case PORT_HW_CFG_TX_LASER_GPIO2:
7413         case PORT_HW_CFG_TX_LASER_GPIO3:
7414         {
7415                 u16 gpio_pin;
7416                 u8 gpio_port, gpio_mode;
7417                 if (tx_en)
7418                         gpio_mode = MISC_REGISTERS_GPIO_OUTPUT_HIGH;
7419                 else
7420                         gpio_mode = MISC_REGISTERS_GPIO_OUTPUT_LOW;
7421
7422                 gpio_pin = tx_en_mode - PORT_HW_CFG_TX_LASER_GPIO0;
7423                 gpio_port = bnx2x_get_gpio_port(params);
7424                 bnx2x_set_gpio(bp, gpio_pin, gpio_mode, gpio_port);
7425                 break;
7426         }
7427         default:
7428                 DP(NETIF_MSG_LINK, "Invalid TX_LASER_MDIO 0x%x\n", tx_en_mode);
7429                 break;
7430         }
7431 }
7432
7433 static void bnx2x_sfp_set_transmitter(struct link_params *params,
7434                                       struct bnx2x_phy *phy,
7435                                       u8 tx_en)
7436 {
7437         struct bnx2x *bp = params->bp;
7438         DP(NETIF_MSG_LINK, "Setting SFP+ transmitter to %d\n", tx_en);
7439         if (CHIP_IS_E3(bp))
7440                 bnx2x_sfp_e3_set_transmitter(params, phy, tx_en);
7441         else
7442                 bnx2x_sfp_e1e2_set_transmitter(params, phy, tx_en);
7443 }
7444
7445 static int bnx2x_8726_read_sfp_module_eeprom(struct bnx2x_phy *phy,
7446                                              struct link_params *params,
7447                                              u16 addr, u8 byte_cnt, u8 *o_buf)
7448 {
7449         struct bnx2x *bp = params->bp;
7450         u16 val = 0;
7451         u16 i;
7452         if (byte_cnt > 16) {
7453                 DP(NETIF_MSG_LINK,
7454                    "Reading from eeprom is limited to 0xf\n");
7455                 return -EINVAL;
7456         }
7457         /* Set the read command byte count */
7458         bnx2x_cl45_write(bp, phy,
7459                          MDIO_PMA_DEVAD, MDIO_PMA_REG_SFP_TWO_WIRE_BYTE_CNT,
7460                          (byte_cnt | 0xa000));
7461
7462         /* Set the read command address */
7463         bnx2x_cl45_write(bp, phy,
7464                          MDIO_PMA_DEVAD, MDIO_PMA_REG_SFP_TWO_WIRE_MEM_ADDR,
7465                          addr);
7466
7467         /* Activate read command */
7468         bnx2x_cl45_write(bp, phy,
7469                          MDIO_PMA_DEVAD, MDIO_PMA_REG_SFP_TWO_WIRE_CTRL,
7470                          0x2c0f);
7471
7472         /* Wait up to 500us for command complete status */
7473         for (i = 0; i < 100; i++) {
7474                 bnx2x_cl45_read(bp, phy,
7475                                 MDIO_PMA_DEVAD,
7476                                 MDIO_PMA_REG_SFP_TWO_WIRE_CTRL, &val);
7477                 if ((val & MDIO_PMA_REG_SFP_TWO_WIRE_CTRL_STATUS_MASK) ==
7478                     MDIO_PMA_REG_SFP_TWO_WIRE_STATUS_COMPLETE)
7479                         break;
7480                 udelay(5);
7481         }
7482
7483         if ((val & MDIO_PMA_REG_SFP_TWO_WIRE_CTRL_STATUS_MASK) !=
7484                     MDIO_PMA_REG_SFP_TWO_WIRE_STATUS_COMPLETE) {
7485                 DP(NETIF_MSG_LINK,
7486                          "Got bad status 0x%x when reading from SFP+ EEPROM\n",
7487                          (val & MDIO_PMA_REG_SFP_TWO_WIRE_CTRL_STATUS_MASK));
7488                 return -EINVAL;
7489         }
7490
7491         /* Read the buffer */
7492         for (i = 0; i < byte_cnt; i++) {
7493                 bnx2x_cl45_read(bp, phy,
7494                                 MDIO_PMA_DEVAD,
7495                                 MDIO_PMA_REG_8726_TWO_WIRE_DATA_BUF + i, &val);
7496                 o_buf[i] = (u8)(val & MDIO_PMA_REG_8726_TWO_WIRE_DATA_MASK);
7497         }
7498
7499         for (i = 0; i < 100; i++) {
7500                 bnx2x_cl45_read(bp, phy,
7501                                 MDIO_PMA_DEVAD,
7502                                 MDIO_PMA_REG_SFP_TWO_WIRE_CTRL, &val);
7503                 if ((val & MDIO_PMA_REG_SFP_TWO_WIRE_CTRL_STATUS_MASK) ==
7504                     MDIO_PMA_REG_SFP_TWO_WIRE_STATUS_IDLE)
7505                         return 0;
7506                 msleep(1);
7507         }
7508         return -EINVAL;
7509 }
7510
7511 static int bnx2x_warpcore_read_sfp_module_eeprom(struct bnx2x_phy *phy,
7512                                                  struct link_params *params,
7513                                                  u16 addr, u8 byte_cnt,
7514                                                  u8 *o_buf)
7515 {
7516         int rc = 0;
7517         u8 i, j = 0, cnt = 0;
7518         u32 data_array[4];
7519         u16 addr32;
7520         struct bnx2x *bp = params->bp;
7521         /*DP(NETIF_MSG_LINK, "bnx2x_direct_read_sfp_module_eeprom:"
7522                                         " addr %d, cnt %d\n",
7523                                         addr, byte_cnt);*/
7524         if (byte_cnt > 16) {
7525                 DP(NETIF_MSG_LINK,
7526                    "Reading from eeprom is limited to 16 bytes\n");
7527                 return -EINVAL;
7528         }
7529
7530         /* 4 byte aligned address */
7531         addr32 = addr & (~0x3);
7532         do {
7533                 rc = bnx2x_bsc_read(params, phy, 0xa0, addr32, 0, byte_cnt,
7534                                     data_array);
7535         } while ((rc != 0) && (++cnt < I2C_WA_RETRY_CNT));
7536
7537         if (rc == 0) {
7538                 for (i = (addr - addr32); i < byte_cnt + (addr - addr32); i++) {
7539                         o_buf[j] = *((u8 *)data_array + i);
7540                         j++;
7541                 }
7542         }
7543
7544         return rc;
7545 }
7546
7547 static int bnx2x_8727_read_sfp_module_eeprom(struct bnx2x_phy *phy,
7548                                              struct link_params *params,
7549                                              u16 addr, u8 byte_cnt, u8 *o_buf)
7550 {
7551         struct bnx2x *bp = params->bp;
7552         u16 val, i;
7553
7554         if (byte_cnt > 16) {
7555                 DP(NETIF_MSG_LINK,
7556                    "Reading from eeprom is limited to 0xf\n");
7557                 return -EINVAL;
7558         }
7559
7560         /* Need to read from 1.8000 to clear it */
7561         bnx2x_cl45_read(bp, phy,
7562                         MDIO_PMA_DEVAD,
7563                         MDIO_PMA_REG_SFP_TWO_WIRE_CTRL,
7564                         &val);
7565
7566         /* Set the read command byte count */
7567         bnx2x_cl45_write(bp, phy,
7568                          MDIO_PMA_DEVAD,
7569                          MDIO_PMA_REG_SFP_TWO_WIRE_BYTE_CNT,
7570                          ((byte_cnt < 2) ? 2 : byte_cnt));
7571
7572         /* Set the read command address */
7573         bnx2x_cl45_write(bp, phy,
7574                          MDIO_PMA_DEVAD,
7575                          MDIO_PMA_REG_SFP_TWO_WIRE_MEM_ADDR,
7576                          addr);
7577         /* Set the destination address */
7578         bnx2x_cl45_write(bp, phy,
7579                          MDIO_PMA_DEVAD,
7580                          0x8004,
7581                          MDIO_PMA_REG_8727_TWO_WIRE_DATA_BUF);
7582
7583         /* Activate read command */
7584         bnx2x_cl45_write(bp, phy,
7585                          MDIO_PMA_DEVAD,
7586                          MDIO_PMA_REG_SFP_TWO_WIRE_CTRL,
7587                          0x8002);
7588         /*
7589          * Wait appropriate time for two-wire command to finish before
7590          * polling the status register
7591          */
7592         msleep(1);
7593
7594         /* Wait up to 500us for command complete status */
7595         for (i = 0; i < 100; i++) {
7596                 bnx2x_cl45_read(bp, phy,
7597                                 MDIO_PMA_DEVAD,
7598                                 MDIO_PMA_REG_SFP_TWO_WIRE_CTRL, &val);
7599                 if ((val & MDIO_PMA_REG_SFP_TWO_WIRE_CTRL_STATUS_MASK) ==
7600                     MDIO_PMA_REG_SFP_TWO_WIRE_STATUS_COMPLETE)
7601                         break;
7602                 udelay(5);
7603         }
7604
7605         if ((val & MDIO_PMA_REG_SFP_TWO_WIRE_CTRL_STATUS_MASK) !=
7606                     MDIO_PMA_REG_SFP_TWO_WIRE_STATUS_COMPLETE) {
7607                 DP(NETIF_MSG_LINK,
7608                          "Got bad status 0x%x when reading from SFP+ EEPROM\n",
7609                          (val & MDIO_PMA_REG_SFP_TWO_WIRE_CTRL_STATUS_MASK));
7610                 return -EFAULT;
7611         }
7612
7613         /* Read the buffer */
7614         for (i = 0; i < byte_cnt; i++) {
7615                 bnx2x_cl45_read(bp, phy,
7616                                 MDIO_PMA_DEVAD,
7617                                 MDIO_PMA_REG_8727_TWO_WIRE_DATA_BUF + i, &val);
7618                 o_buf[i] = (u8)(val & MDIO_PMA_REG_8727_TWO_WIRE_DATA_MASK);
7619         }
7620
7621         for (i = 0; i < 100; i++) {
7622                 bnx2x_cl45_read(bp, phy,
7623                                 MDIO_PMA_DEVAD,
7624                                 MDIO_PMA_REG_SFP_TWO_WIRE_CTRL, &val);
7625                 if ((val & MDIO_PMA_REG_SFP_TWO_WIRE_CTRL_STATUS_MASK) ==
7626                     MDIO_PMA_REG_SFP_TWO_WIRE_STATUS_IDLE)
7627                         return 0;
7628                 msleep(1);
7629         }
7630
7631         return -EINVAL;
7632 }
7633
7634 int bnx2x_read_sfp_module_eeprom(struct bnx2x_phy *phy,
7635                                  struct link_params *params, u16 addr,
7636                                  u8 byte_cnt, u8 *o_buf)
7637 {
7638         int rc = -EINVAL;
7639         switch (phy->type) {
7640         case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8726:
7641                 rc = bnx2x_8726_read_sfp_module_eeprom(phy, params, addr,
7642                                                        byte_cnt, o_buf);
7643         break;
7644         case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8727:
7645         case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8722:
7646                 rc = bnx2x_8727_read_sfp_module_eeprom(phy, params, addr,
7647                                                        byte_cnt, o_buf);
7648         break;
7649         case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_DIRECT:
7650                 rc = bnx2x_warpcore_read_sfp_module_eeprom(phy, params, addr,
7651                                                            byte_cnt, o_buf);
7652         break;
7653         }
7654         return rc;
7655 }
7656
7657 static int bnx2x_get_edc_mode(struct bnx2x_phy *phy,
7658                               struct link_params *params,
7659                               u16 *edc_mode)
7660 {
7661         struct bnx2x *bp = params->bp;
7662         u32 sync_offset = 0, phy_idx, media_types;
7663         u8 val, check_limiting_mode = 0;
7664         *edc_mode = EDC_MODE_LIMITING;
7665
7666         phy->media_type = ETH_PHY_UNSPECIFIED;
7667         /* First check for copper cable */
7668         if (bnx2x_read_sfp_module_eeprom(phy,
7669                                          params,
7670                                          SFP_EEPROM_CON_TYPE_ADDR,
7671                                          1,
7672                                          &val) != 0) {
7673                 DP(NETIF_MSG_LINK, "Failed to read from SFP+ module EEPROM\n");
7674                 return -EINVAL;
7675         }
7676
7677         switch (val) {
7678         case SFP_EEPROM_CON_TYPE_VAL_COPPER:
7679         {
7680                 u8 copper_module_type;
7681                 phy->media_type = ETH_PHY_DA_TWINAX;
7682                 /*
7683                  * Check if its active cable (includes SFP+ module)
7684                  * of passive cable
7685                  */
7686                 if (bnx2x_read_sfp_module_eeprom(phy,
7687                                                params,
7688                                                SFP_EEPROM_FC_TX_TECH_ADDR,
7689                                                1,
7690                                                &copper_module_type) != 0) {
7691                         DP(NETIF_MSG_LINK,
7692                                 "Failed to read copper-cable-type"
7693                                 " from SFP+ EEPROM\n");
7694                         return -EINVAL;
7695                 }
7696
7697                 if (copper_module_type &
7698                     SFP_EEPROM_FC_TX_TECH_BITMASK_COPPER_ACTIVE) {
7699                         DP(NETIF_MSG_LINK, "Active Copper cable detected\n");
7700                         check_limiting_mode = 1;
7701                 } else if (copper_module_type &
7702                         SFP_EEPROM_FC_TX_TECH_BITMASK_COPPER_PASSIVE) {
7703                                 DP(NETIF_MSG_LINK,
7704                                    "Passive Copper cable detected\n");
7705                                 *edc_mode =
7706                                       EDC_MODE_PASSIVE_DAC;
7707                 } else {
7708                         DP(NETIF_MSG_LINK,
7709                            "Unknown copper-cable-type 0x%x !!!\n",
7710                            copper_module_type);
7711                         return -EINVAL;
7712                 }
7713                 break;
7714         }
7715         case SFP_EEPROM_CON_TYPE_VAL_LC:
7716                 phy->media_type = ETH_PHY_SFP_FIBER;
7717                 DP(NETIF_MSG_LINK, "Optic module detected\n");
7718                 check_limiting_mode = 1;
7719                 break;
7720         default:
7721                 DP(NETIF_MSG_LINK, "Unable to determine module type 0x%x !!!\n",
7722                          val);
7723                 return -EINVAL;
7724         }
7725         sync_offset = params->shmem_base +
7726                 offsetof(struct shmem_region,
7727                          dev_info.port_hw_config[params->port].media_type);
7728         media_types = REG_RD(bp, sync_offset);
7729         /* Update media type for non-PMF sync */
7730         for (phy_idx = INT_PHY; phy_idx < MAX_PHYS; phy_idx++) {
7731                 if (&(params->phy[phy_idx]) == phy) {
7732                         media_types &= ~(PORT_HW_CFG_MEDIA_TYPE_PHY0_MASK <<
7733                                 (PORT_HW_CFG_MEDIA_TYPE_PHY1_SHIFT * phy_idx));
7734                         media_types |= ((phy->media_type &
7735                                         PORT_HW_CFG_MEDIA_TYPE_PHY0_MASK) <<
7736                                 (PORT_HW_CFG_MEDIA_TYPE_PHY1_SHIFT * phy_idx));
7737                         break;
7738                 }
7739         }
7740         REG_WR(bp, sync_offset, media_types);
7741         if (check_limiting_mode) {
7742                 u8 options[SFP_EEPROM_OPTIONS_SIZE];
7743                 if (bnx2x_read_sfp_module_eeprom(phy,
7744                                                  params,
7745                                                  SFP_EEPROM_OPTIONS_ADDR,
7746                                                  SFP_EEPROM_OPTIONS_SIZE,
7747                                                  options) != 0) {
7748                         DP(NETIF_MSG_LINK,
7749                            "Failed to read Option field from module EEPROM\n");
7750                         return -EINVAL;
7751                 }
7752                 if ((options[0] & SFP_EEPROM_OPTIONS_LINEAR_RX_OUT_MASK))
7753                         *edc_mode = EDC_MODE_LINEAR;
7754                 else
7755                         *edc_mode = EDC_MODE_LIMITING;
7756         }
7757         DP(NETIF_MSG_LINK, "EDC mode is set to 0x%x\n", *edc_mode);
7758         return 0;
7759 }
7760 /*
7761  * This function read the relevant field from the module (SFP+), and verify it
7762  * is compliant with this board
7763  */
7764 static int bnx2x_verify_sfp_module(struct bnx2x_phy *phy,
7765                                    struct link_params *params)
7766 {
7767         struct bnx2x *bp = params->bp;
7768         u32 val, cmd;
7769         u32 fw_resp, fw_cmd_param;
7770         char vendor_name[SFP_EEPROM_VENDOR_NAME_SIZE+1];
7771         char vendor_pn[SFP_EEPROM_PART_NO_SIZE+1];
7772         phy->flags &= ~FLAGS_SFP_NOT_APPROVED;
7773         val = REG_RD(bp, params->shmem_base +
7774                          offsetof(struct shmem_region, dev_info.
7775                                   port_feature_config[params->port].config));
7776         if ((val & PORT_FEAT_CFG_OPT_MDL_ENFRCMNT_MASK) ==
7777             PORT_FEAT_CFG_OPT_MDL_ENFRCMNT_NO_ENFORCEMENT) {
7778                 DP(NETIF_MSG_LINK, "NOT enforcing module verification\n");
7779                 return 0;
7780         }
7781
7782         if (params->feature_config_flags &
7783             FEATURE_CONFIG_BC_SUPPORTS_DUAL_PHY_OPT_MDL_VRFY) {
7784                 /* Use specific phy request */
7785                 cmd = DRV_MSG_CODE_VRFY_SPECIFIC_PHY_OPT_MDL;
7786         } else if (params->feature_config_flags &
7787                    FEATURE_CONFIG_BC_SUPPORTS_OPT_MDL_VRFY) {
7788                 /* Use first phy request only in case of non-dual media*/
7789                 if (DUAL_MEDIA(params)) {
7790                         DP(NETIF_MSG_LINK,
7791                            "FW does not support OPT MDL verification\n");
7792                         return -EINVAL;
7793                 }
7794                 cmd = DRV_MSG_CODE_VRFY_FIRST_PHY_OPT_MDL;
7795         } else {
7796                 /* No support in OPT MDL detection */
7797                 DP(NETIF_MSG_LINK,
7798                    "FW does not support OPT MDL verification\n");
7799                 return -EINVAL;
7800         }
7801
7802         fw_cmd_param = FW_PARAM_SET(phy->addr, phy->type, phy->mdio_ctrl);
7803         fw_resp = bnx2x_fw_command(bp, cmd, fw_cmd_param);
7804         if (fw_resp == FW_MSG_CODE_VRFY_OPT_MDL_SUCCESS) {
7805                 DP(NETIF_MSG_LINK, "Approved module\n");
7806                 return 0;
7807         }
7808
7809         /* format the warning message */
7810         if (bnx2x_read_sfp_module_eeprom(phy,
7811                                          params,
7812                                          SFP_EEPROM_VENDOR_NAME_ADDR,
7813                                          SFP_EEPROM_VENDOR_NAME_SIZE,
7814                                          (u8 *)vendor_name))
7815                 vendor_name[0] = '\0';
7816         else
7817                 vendor_name[SFP_EEPROM_VENDOR_NAME_SIZE] = '\0';
7818         if (bnx2x_read_sfp_module_eeprom(phy,
7819                                          params,
7820                                          SFP_EEPROM_PART_NO_ADDR,
7821                                          SFP_EEPROM_PART_NO_SIZE,
7822                                          (u8 *)vendor_pn))
7823                 vendor_pn[0] = '\0';
7824         else
7825                 vendor_pn[SFP_EEPROM_PART_NO_SIZE] = '\0';
7826
7827         netdev_err(bp->dev,  "Warning: Unqualified SFP+ module detected,"
7828                               " Port %d from %s part number %s\n",
7829                          params->port, vendor_name, vendor_pn);
7830         phy->flags |= FLAGS_SFP_NOT_APPROVED;
7831         return -EINVAL;
7832 }
7833
7834 static int bnx2x_wait_for_sfp_module_initialized(struct bnx2x_phy *phy,
7835                                                  struct link_params *params)
7836
7837 {
7838         u8 val;
7839         struct bnx2x *bp = params->bp;
7840         u16 timeout;
7841         /*
7842          * Initialization time after hot-plug may take up to 300ms for
7843          * some phys type ( e.g. JDSU )
7844          */
7845
7846         for (timeout = 0; timeout < 60; timeout++) {
7847                 if (bnx2x_read_sfp_module_eeprom(phy, params, 1, 1, &val)
7848                     == 0) {
7849                         DP(NETIF_MSG_LINK,
7850                            "SFP+ module initialization took %d ms\n",
7851                            timeout * 5);
7852                         return 0;
7853                 }
7854                 msleep(5);
7855         }
7856         return -EINVAL;
7857 }
7858
7859 static void bnx2x_8727_power_module(struct bnx2x *bp,
7860                                     struct bnx2x_phy *phy,
7861                                     u8 is_power_up) {
7862         /* Make sure GPIOs are not using for LED mode */
7863         u16 val;
7864         /*
7865          * In the GPIO register, bit 4 is use to determine if the GPIOs are
7866          * operating as INPUT or as OUTPUT. Bit 1 is for input, and 0 for
7867          * output
7868          * Bits 0-1 determine the GPIOs value for OUTPUT in case bit 4 val is 0
7869          * Bits 8-9 determine the GPIOs value for INPUT in case bit 4 val is 1
7870          * where the 1st bit is the over-current(only input), and 2nd bit is
7871          * for power( only output )
7872          *
7873          * In case of NOC feature is disabled and power is up, set GPIO control
7874          *  as input to enable listening of over-current indication
7875          */
7876         if (phy->flags & FLAGS_NOC)
7877                 return;
7878         if (is_power_up)
7879                 val = (1<<4);
7880         else
7881                 /*
7882                  * Set GPIO control to OUTPUT, and set the power bit
7883                  * to according to the is_power_up
7884                  */
7885                 val = (1<<1);
7886
7887         bnx2x_cl45_write(bp, phy,
7888                          MDIO_PMA_DEVAD,
7889                          MDIO_PMA_REG_8727_GPIO_CTRL,
7890                          val);
7891 }
7892
7893 static int bnx2x_8726_set_limiting_mode(struct bnx2x *bp,
7894                                         struct bnx2x_phy *phy,
7895                                         u16 edc_mode)
7896 {
7897         u16 cur_limiting_mode;
7898
7899         bnx2x_cl45_read(bp, phy,
7900                         MDIO_PMA_DEVAD,
7901                         MDIO_PMA_REG_ROM_VER2,
7902                         &cur_limiting_mode);
7903         DP(NETIF_MSG_LINK, "Current Limiting mode is 0x%x\n",
7904                  cur_limiting_mode);
7905
7906         if (edc_mode == EDC_MODE_LIMITING) {
7907                 DP(NETIF_MSG_LINK, "Setting LIMITING MODE\n");
7908                 bnx2x_cl45_write(bp, phy,
7909                                  MDIO_PMA_DEVAD,
7910                                  MDIO_PMA_REG_ROM_VER2,
7911                                  EDC_MODE_LIMITING);
7912         } else { /* LRM mode ( default )*/
7913
7914                 DP(NETIF_MSG_LINK, "Setting LRM MODE\n");
7915
7916                 /*
7917                  * Changing to LRM mode takes quite few seconds. So do it only
7918                  * if current mode is limiting (default is LRM)
7919                  */
7920                 if (cur_limiting_mode != EDC_MODE_LIMITING)
7921                         return 0;
7922
7923                 bnx2x_cl45_write(bp, phy,
7924                                  MDIO_PMA_DEVAD,
7925                                  MDIO_PMA_REG_LRM_MODE,
7926                                  0);
7927                 bnx2x_cl45_write(bp, phy,
7928                                  MDIO_PMA_DEVAD,
7929                                  MDIO_PMA_REG_ROM_VER2,
7930                                  0x128);
7931                 bnx2x_cl45_write(bp, phy,
7932                                  MDIO_PMA_DEVAD,
7933                                  MDIO_PMA_REG_MISC_CTRL0,
7934                                  0x4008);
7935                 bnx2x_cl45_write(bp, phy,
7936                                  MDIO_PMA_DEVAD,
7937                                  MDIO_PMA_REG_LRM_MODE,
7938                                  0xaaaa);
7939         }
7940         return 0;
7941 }
7942
7943 static int bnx2x_8727_set_limiting_mode(struct bnx2x *bp,
7944                                         struct bnx2x_phy *phy,
7945                                         u16 edc_mode)
7946 {
7947         u16 phy_identifier;
7948         u16 rom_ver2_val;
7949         bnx2x_cl45_read(bp, phy,
7950                         MDIO_PMA_DEVAD,
7951                         MDIO_PMA_REG_PHY_IDENTIFIER,
7952                         &phy_identifier);
7953
7954         bnx2x_cl45_write(bp, phy,
7955                          MDIO_PMA_DEVAD,
7956                          MDIO_PMA_REG_PHY_IDENTIFIER,
7957                          (phy_identifier & ~(1<<9)));
7958
7959         bnx2x_cl45_read(bp, phy,
7960                         MDIO_PMA_DEVAD,
7961                         MDIO_PMA_REG_ROM_VER2,
7962                         &rom_ver2_val);
7963         /* Keep the MSB 8-bits, and set the LSB 8-bits with the edc_mode */
7964         bnx2x_cl45_write(bp, phy,
7965                          MDIO_PMA_DEVAD,
7966                          MDIO_PMA_REG_ROM_VER2,
7967                          (rom_ver2_val & 0xff00) | (edc_mode & 0x00ff));
7968
7969         bnx2x_cl45_write(bp, phy,
7970                          MDIO_PMA_DEVAD,
7971                          MDIO_PMA_REG_PHY_IDENTIFIER,
7972                          (phy_identifier | (1<<9)));
7973
7974         return 0;
7975 }
7976
7977 static void bnx2x_8727_specific_func(struct bnx2x_phy *phy,
7978                                      struct link_params *params,
7979                                      u32 action)
7980 {
7981         struct bnx2x *bp = params->bp;
7982
7983         switch (action) {
7984         case DISABLE_TX:
7985                 bnx2x_sfp_set_transmitter(params, phy, 0);
7986                 break;
7987         case ENABLE_TX:
7988                 if (!(phy->flags & FLAGS_SFP_NOT_APPROVED))
7989                         bnx2x_sfp_set_transmitter(params, phy, 1);
7990                 break;
7991         default:
7992                 DP(NETIF_MSG_LINK, "Function 0x%x not supported by 8727\n",
7993                    action);
7994                 return;
7995         }
7996 }
7997
7998 static void bnx2x_set_e1e2_module_fault_led(struct link_params *params,
7999                                            u8 gpio_mode)
8000 {
8001         struct bnx2x *bp = params->bp;
8002
8003         u32 fault_led_gpio = REG_RD(bp, params->shmem_base +
8004                             offsetof(struct shmem_region,
8005                         dev_info.port_hw_config[params->port].sfp_ctrl)) &
8006                 PORT_HW_CFG_FAULT_MODULE_LED_MASK;
8007         switch (fault_led_gpio) {
8008         case PORT_HW_CFG_FAULT_MODULE_LED_DISABLED:
8009                 return;
8010         case PORT_HW_CFG_FAULT_MODULE_LED_GPIO0:
8011         case PORT_HW_CFG_FAULT_MODULE_LED_GPIO1:
8012         case PORT_HW_CFG_FAULT_MODULE_LED_GPIO2:
8013         case PORT_HW_CFG_FAULT_MODULE_LED_GPIO3:
8014         {
8015                 u8 gpio_port = bnx2x_get_gpio_port(params);
8016                 u16 gpio_pin = fault_led_gpio -
8017                         PORT_HW_CFG_FAULT_MODULE_LED_GPIO0;
8018                 DP(NETIF_MSG_LINK, "Set fault module-detected led "
8019                                    "pin %x port %x mode %x\n",
8020                                gpio_pin, gpio_port, gpio_mode);
8021                 bnx2x_set_gpio(bp, gpio_pin, gpio_mode, gpio_port);
8022         }
8023         break;
8024         default:
8025                 DP(NETIF_MSG_LINK, "Error: Invalid fault led mode 0x%x\n",
8026                                fault_led_gpio);
8027         }
8028 }
8029
8030 static void bnx2x_set_e3_module_fault_led(struct link_params *params,
8031                                           u8 gpio_mode)
8032 {
8033         u32 pin_cfg;
8034         u8 port = params->port;
8035         struct bnx2x *bp = params->bp;
8036         pin_cfg = (REG_RD(bp, params->shmem_base +
8037                          offsetof(struct shmem_region,
8038                                   dev_info.port_hw_config[port].e3_sfp_ctrl)) &
8039                 PORT_HW_CFG_E3_FAULT_MDL_LED_MASK) >>
8040                 PORT_HW_CFG_E3_FAULT_MDL_LED_SHIFT;
8041         DP(NETIF_MSG_LINK, "Setting Fault LED to %d using pin cfg %d\n",
8042                        gpio_mode, pin_cfg);
8043         bnx2x_set_cfg_pin(bp, pin_cfg, gpio_mode);
8044 }
8045
8046 static void bnx2x_set_sfp_module_fault_led(struct link_params *params,
8047                                            u8 gpio_mode)
8048 {
8049         struct bnx2x *bp = params->bp;
8050         DP(NETIF_MSG_LINK, "Setting SFP+ module fault LED to %d\n", gpio_mode);
8051         if (CHIP_IS_E3(bp)) {
8052                 /*
8053                  * Low ==> if SFP+ module is supported otherwise
8054                  * High ==> if SFP+ module is not on the approved vendor list
8055                  */
8056                 bnx2x_set_e3_module_fault_led(params, gpio_mode);
8057         } else
8058                 bnx2x_set_e1e2_module_fault_led(params, gpio_mode);
8059 }
8060
8061 static void bnx2x_warpcore_power_module(struct link_params *params,
8062                                         struct bnx2x_phy *phy,
8063                                         u8 power)
8064 {
8065         u32 pin_cfg;
8066         struct bnx2x *bp = params->bp;
8067
8068         pin_cfg = (REG_RD(bp, params->shmem_base +
8069                           offsetof(struct shmem_region,
8070                         dev_info.port_hw_config[params->port].e3_sfp_ctrl)) &
8071                         PORT_HW_CFG_E3_PWR_DIS_MASK) >>
8072                         PORT_HW_CFG_E3_PWR_DIS_SHIFT;
8073
8074         if (pin_cfg == PIN_CFG_NA)
8075                 return;
8076         DP(NETIF_MSG_LINK, "Setting SFP+ module power to %d using pin cfg %d\n",
8077                        power, pin_cfg);
8078         /*
8079          * Low ==> corresponding SFP+ module is powered
8080          * high ==> the SFP+ module is powered down
8081          */
8082         bnx2x_set_cfg_pin(bp, pin_cfg, power ^ 1);
8083 }
8084
8085 static void bnx2x_warpcore_hw_reset(struct bnx2x_phy *phy,
8086                                     struct link_params *params)
8087 {
8088         bnx2x_warpcore_power_module(params, phy, 0);
8089 }
8090
8091 static void bnx2x_power_sfp_module(struct link_params *params,
8092                                    struct bnx2x_phy *phy,
8093                                    u8 power)
8094 {
8095         struct bnx2x *bp = params->bp;
8096         DP(NETIF_MSG_LINK, "Setting SFP+ power to %x\n", power);
8097
8098         switch (phy->type) {
8099         case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8727:
8100         case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8722:
8101                 bnx2x_8727_power_module(params->bp, phy, power);
8102                 break;
8103         case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_DIRECT:
8104                 bnx2x_warpcore_power_module(params, phy, power);
8105                 break;
8106         default:
8107                 break;
8108         }
8109 }
8110 static void bnx2x_warpcore_set_limiting_mode(struct link_params *params,
8111                                              struct bnx2x_phy *phy,
8112                                              u16 edc_mode)
8113 {
8114         u16 val = 0;
8115         u16 mode = MDIO_WC_REG_UC_INFO_B1_FIRMWARE_MODE_DEFAULT;
8116         struct bnx2x *bp = params->bp;
8117
8118         u8 lane = bnx2x_get_warpcore_lane(phy, params);
8119         /* This is a global register which controls all lanes */
8120         bnx2x_cl45_read(bp, phy, MDIO_WC_DEVAD,
8121                         MDIO_WC_REG_UC_INFO_B1_FIRMWARE_MODE, &val);
8122         val &= ~(0xf << (lane << 2));
8123
8124         switch (edc_mode) {
8125         case EDC_MODE_LINEAR:
8126         case EDC_MODE_LIMITING:
8127                 mode = MDIO_WC_REG_UC_INFO_B1_FIRMWARE_MODE_DEFAULT;
8128                 break;
8129         case EDC_MODE_PASSIVE_DAC:
8130                 mode = MDIO_WC_REG_UC_INFO_B1_FIRMWARE_MODE_SFP_DAC;
8131                 break;
8132         default:
8133                 break;
8134         }
8135
8136         val |= (mode << (lane << 2));
8137         bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,
8138                          MDIO_WC_REG_UC_INFO_B1_FIRMWARE_MODE, val);
8139         /* A must read */
8140         bnx2x_cl45_read(bp, phy, MDIO_WC_DEVAD,
8141                         MDIO_WC_REG_UC_INFO_B1_FIRMWARE_MODE, &val);
8142
8143         /* Restart microcode to re-read the new mode */
8144         bnx2x_warpcore_reset_lane(bp, phy, 1);
8145         bnx2x_warpcore_reset_lane(bp, phy, 0);
8146
8147 }
8148
8149 static void bnx2x_set_limiting_mode(struct link_params *params,
8150                                     struct bnx2x_phy *phy,
8151                                     u16 edc_mode)
8152 {
8153         switch (phy->type) {
8154         case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8726:
8155                 bnx2x_8726_set_limiting_mode(params->bp, phy, edc_mode);
8156                 break;
8157         case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8727:
8158         case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8722:
8159                 bnx2x_8727_set_limiting_mode(params->bp, phy, edc_mode);
8160                 break;
8161         case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_DIRECT:
8162                 bnx2x_warpcore_set_limiting_mode(params, phy, edc_mode);
8163                 break;
8164         }
8165 }
8166
8167 int bnx2x_sfp_module_detection(struct bnx2x_phy *phy,
8168                                struct link_params *params)
8169 {
8170         struct bnx2x *bp = params->bp;
8171         u16 edc_mode;
8172         int rc = 0;
8173
8174         u32 val = REG_RD(bp, params->shmem_base +
8175                              offsetof(struct shmem_region, dev_info.
8176                                      port_feature_config[params->port].config));
8177
8178         DP(NETIF_MSG_LINK, "SFP+ module plugged in/out detected on port %d\n",
8179                  params->port);
8180         /* Power up module */
8181         bnx2x_power_sfp_module(params, phy, 1);
8182         if (bnx2x_get_edc_mode(phy, params, &edc_mode) != 0) {
8183                 DP(NETIF_MSG_LINK, "Failed to get valid module type\n");
8184                 return -EINVAL;
8185         } else if (bnx2x_verify_sfp_module(phy, params) != 0) {
8186                 /* check SFP+ module compatibility */
8187                 DP(NETIF_MSG_LINK, "Module verification failed!!\n");
8188                 rc = -EINVAL;
8189                 /* Turn on fault module-detected led */
8190                 bnx2x_set_sfp_module_fault_led(params,
8191                                                MISC_REGISTERS_GPIO_HIGH);
8192
8193                 /* Check if need to power down the SFP+ module */
8194                 if ((val & PORT_FEAT_CFG_OPT_MDL_ENFRCMNT_MASK) ==
8195                      PORT_FEAT_CFG_OPT_MDL_ENFRCMNT_POWER_DOWN) {
8196                         DP(NETIF_MSG_LINK, "Shutdown SFP+ module!!\n");
8197                         bnx2x_power_sfp_module(params, phy, 0);
8198                         return rc;
8199                 }
8200         } else {
8201                 /* Turn off fault module-detected led */
8202                 bnx2x_set_sfp_module_fault_led(params, MISC_REGISTERS_GPIO_LOW);
8203         }
8204
8205         /*
8206          * Check and set limiting mode / LRM mode on 8726. On 8727 it
8207          * is done automatically
8208          */
8209         bnx2x_set_limiting_mode(params, phy, edc_mode);
8210
8211         /*
8212          * Enable transmit for this module if the module is approved, or
8213          * if unapproved modules should also enable the Tx laser
8214          */
8215         if (rc == 0 ||
8216             (val & PORT_FEAT_CFG_OPT_MDL_ENFRCMNT_MASK) !=
8217             PORT_FEAT_CFG_OPT_MDL_ENFRCMNT_DISABLE_TX_LASER)
8218                 bnx2x_sfp_set_transmitter(params, phy, 1);
8219         else
8220                 bnx2x_sfp_set_transmitter(params, phy, 0);
8221
8222         return rc;
8223 }
8224
8225 void bnx2x_handle_module_detect_int(struct link_params *params)
8226 {
8227         struct bnx2x *bp = params->bp;
8228         struct bnx2x_phy *phy;
8229         u32 gpio_val;
8230         u8 gpio_num, gpio_port;
8231         if (CHIP_IS_E3(bp))
8232                 phy = &params->phy[INT_PHY];
8233         else
8234                 phy = &params->phy[EXT_PHY1];
8235
8236         if (bnx2x_get_mod_abs_int_cfg(bp, params->chip_id, params->shmem_base,
8237                                       params->port, &gpio_num, &gpio_port) ==
8238             -EINVAL) {
8239                 DP(NETIF_MSG_LINK, "Failed to get MOD_ABS interrupt config\n");
8240                 return;
8241         }
8242
8243         /* Set valid module led off */
8244         bnx2x_set_sfp_module_fault_led(params, MISC_REGISTERS_GPIO_HIGH);
8245
8246         /* Get current gpio val reflecting module plugged in / out*/
8247         gpio_val = bnx2x_get_gpio(bp, gpio_num, gpio_port);
8248
8249         /* Call the handling function in case module is detected */
8250         if (gpio_val == 0) {
8251                 bnx2x_power_sfp_module(params, phy, 1);
8252                 bnx2x_set_gpio_int(bp, gpio_num,
8253                                    MISC_REGISTERS_GPIO_INT_OUTPUT_CLR,
8254                                    gpio_port);
8255                 if (bnx2x_wait_for_sfp_module_initialized(phy, params) == 0)
8256                         bnx2x_sfp_module_detection(phy, params);
8257                 else
8258                         DP(NETIF_MSG_LINK, "SFP+ module is not initialized\n");
8259         } else {
8260                 u32 val = REG_RD(bp, params->shmem_base +
8261                                  offsetof(struct shmem_region, dev_info.
8262                                           port_feature_config[params->port].
8263                                           config));
8264                 bnx2x_set_gpio_int(bp, gpio_num,
8265                                    MISC_REGISTERS_GPIO_INT_OUTPUT_SET,
8266                                    gpio_port);
8267                 /*
8268                  * Module was plugged out.
8269                  * Disable transmit for this module
8270                  */
8271                 phy->media_type = ETH_PHY_NOT_PRESENT;
8272                 if (((val & PORT_FEAT_CFG_OPT_MDL_ENFRCMNT_MASK) ==
8273                      PORT_FEAT_CFG_OPT_MDL_ENFRCMNT_DISABLE_TX_LASER) ||
8274                     CHIP_IS_E3(bp))
8275                         bnx2x_sfp_set_transmitter(params, phy, 0);
8276         }
8277 }
8278
8279 /******************************************************************/
8280 /*              Used by 8706 and 8727                             */
8281 /******************************************************************/
8282 static void bnx2x_sfp_mask_fault(struct bnx2x *bp,
8283                                  struct bnx2x_phy *phy,
8284                                  u16 alarm_status_offset,
8285                                  u16 alarm_ctrl_offset)
8286 {
8287         u16 alarm_status, val;
8288         bnx2x_cl45_read(bp, phy,
8289                         MDIO_PMA_DEVAD, alarm_status_offset,
8290                         &alarm_status);
8291         bnx2x_cl45_read(bp, phy,
8292                         MDIO_PMA_DEVAD, alarm_status_offset,
8293                         &alarm_status);
8294         /* Mask or enable the fault event. */
8295         bnx2x_cl45_read(bp, phy, MDIO_PMA_DEVAD, alarm_ctrl_offset, &val);
8296         if (alarm_status & (1<<0))
8297                 val &= ~(1<<0);
8298         else
8299                 val |= (1<<0);
8300         bnx2x_cl45_write(bp, phy, MDIO_PMA_DEVAD, alarm_ctrl_offset, val);
8301 }
8302 /******************************************************************/
8303 /*              common BCM8706/BCM8726 PHY SECTION                */
8304 /******************************************************************/
8305 static u8 bnx2x_8706_8726_read_status(struct bnx2x_phy *phy,
8306                                       struct link_params *params,
8307                                       struct link_vars *vars)
8308 {
8309         u8 link_up = 0;
8310         u16 val1, val2, rx_sd, pcs_status;
8311         struct bnx2x *bp = params->bp;
8312         DP(NETIF_MSG_LINK, "XGXS 8706/8726\n");
8313         /* Clear RX Alarm*/
8314         bnx2x_cl45_read(bp, phy,
8315                         MDIO_PMA_DEVAD, MDIO_PMA_LASI_RXSTAT, &val2);
8316
8317         bnx2x_sfp_mask_fault(bp, phy, MDIO_PMA_LASI_TXSTAT,
8318                              MDIO_PMA_LASI_TXCTRL);
8319
8320         /* clear LASI indication*/
8321         bnx2x_cl45_read(bp, phy,
8322                         MDIO_PMA_DEVAD, MDIO_PMA_LASI_STAT, &val1);
8323         bnx2x_cl45_read(bp, phy,
8324                         MDIO_PMA_DEVAD, MDIO_PMA_LASI_STAT, &val2);
8325         DP(NETIF_MSG_LINK, "8706/8726 LASI status 0x%x--> 0x%x\n", val1, val2);
8326
8327         bnx2x_cl45_read(bp, phy,
8328                         MDIO_PMA_DEVAD, MDIO_PMA_REG_RX_SD, &rx_sd);
8329         bnx2x_cl45_read(bp, phy,
8330                         MDIO_PCS_DEVAD, MDIO_PCS_REG_STATUS, &pcs_status);
8331         bnx2x_cl45_read(bp, phy,
8332                         MDIO_AN_DEVAD, MDIO_AN_REG_LINK_STATUS, &val2);
8333         bnx2x_cl45_read(bp, phy,
8334                         MDIO_AN_DEVAD, MDIO_AN_REG_LINK_STATUS, &val2);
8335
8336         DP(NETIF_MSG_LINK, "8706/8726 rx_sd 0x%x pcs_status 0x%x 1Gbps"
8337                         " link_status 0x%x\n", rx_sd, pcs_status, val2);
8338         /*
8339          * link is up if both bit 0 of pmd_rx_sd and bit 0 of pcs_status
8340          * are set, or if the autoneg bit 1 is set
8341          */
8342         link_up = ((rx_sd & pcs_status & 0x1) || (val2 & (1<<1)));
8343         if (link_up) {
8344                 if (val2 & (1<<1))
8345                         vars->line_speed = SPEED_1000;
8346                 else
8347                         vars->line_speed = SPEED_10000;
8348                 bnx2x_ext_phy_resolve_fc(phy, params, vars);
8349                 vars->duplex = DUPLEX_FULL;
8350         }
8351
8352         /* Capture 10G link fault. Read twice to clear stale value. */
8353         if (vars->line_speed == SPEED_10000) {
8354                 bnx2x_cl45_read(bp, phy, MDIO_PMA_DEVAD,
8355                             MDIO_PMA_LASI_TXSTAT, &val1);
8356                 bnx2x_cl45_read(bp, phy, MDIO_PMA_DEVAD,
8357                             MDIO_PMA_LASI_TXSTAT, &val1);
8358                 if (val1 & (1<<0))
8359                         vars->fault_detected = 1;
8360         }
8361
8362         return link_up;
8363 }
8364
8365 /******************************************************************/
8366 /*                      BCM8706 PHY SECTION                       */
8367 /******************************************************************/
8368 static u8 bnx2x_8706_config_init(struct bnx2x_phy *phy,
8369                                  struct link_params *params,
8370                                  struct link_vars *vars)
8371 {
8372         u32 tx_en_mode;
8373         u16 cnt, val, tmp1;
8374         struct bnx2x *bp = params->bp;
8375
8376         bnx2x_set_gpio(bp, MISC_REGISTERS_GPIO_2,
8377                        MISC_REGISTERS_GPIO_OUTPUT_HIGH, params->port);
8378         /* HW reset */
8379         bnx2x_ext_phy_hw_reset(bp, params->port);
8380         bnx2x_cl45_write(bp, phy, MDIO_PMA_DEVAD, MDIO_PMA_REG_CTRL, 0xa040);
8381         bnx2x_wait_reset_complete(bp, phy, params);
8382
8383         /* Wait until fw is loaded */
8384         for (cnt = 0; cnt < 100; cnt++) {
8385                 bnx2x_cl45_read(bp, phy,
8386                                 MDIO_PMA_DEVAD, MDIO_PMA_REG_ROM_VER1, &val);
8387                 if (val)
8388                         break;
8389                 msleep(10);
8390         }
8391         DP(NETIF_MSG_LINK, "XGXS 8706 is initialized after %d ms\n", cnt);
8392         if ((params->feature_config_flags &
8393              FEATURE_CONFIG_OVERRIDE_PREEMPHASIS_ENABLED)) {
8394                 u8 i;
8395                 u16 reg;
8396                 for (i = 0; i < 4; i++) {
8397                         reg = MDIO_XS_8706_REG_BANK_RX0 +
8398                                 i*(MDIO_XS_8706_REG_BANK_RX1 -
8399                                    MDIO_XS_8706_REG_BANK_RX0);
8400                         bnx2x_cl45_read(bp, phy, MDIO_XS_DEVAD, reg, &val);
8401                         /* Clear first 3 bits of the control */
8402                         val &= ~0x7;
8403                         /* Set control bits according to configuration */
8404                         val |= (phy->rx_preemphasis[i] & 0x7);
8405                         DP(NETIF_MSG_LINK, "Setting RX Equalizer to BCM8706"
8406                                    " reg 0x%x <-- val 0x%x\n", reg, val);
8407                         bnx2x_cl45_write(bp, phy, MDIO_XS_DEVAD, reg, val);
8408                 }
8409         }
8410         /* Force speed */
8411         if (phy->req_line_speed == SPEED_10000) {
8412                 DP(NETIF_MSG_LINK, "XGXS 8706 force 10Gbps\n");
8413
8414                 bnx2x_cl45_write(bp, phy,
8415                                  MDIO_PMA_DEVAD,
8416                                  MDIO_PMA_REG_DIGITAL_CTRL, 0x400);
8417                 bnx2x_cl45_write(bp, phy,
8418                                  MDIO_PMA_DEVAD, MDIO_PMA_LASI_TXCTRL,
8419                                  0);
8420                 /* Arm LASI for link and Tx fault. */
8421                 bnx2x_cl45_write(bp, phy,
8422                                  MDIO_PMA_DEVAD, MDIO_PMA_LASI_CTRL, 3);
8423         } else {
8424                 /* Force 1Gbps using autoneg with 1G advertisement */
8425
8426                 /* Allow CL37 through CL73 */
8427                 DP(NETIF_MSG_LINK, "XGXS 8706 AutoNeg\n");
8428                 bnx2x_cl45_write(bp, phy,
8429                                  MDIO_AN_DEVAD, MDIO_AN_REG_CL37_CL73, 0x040c);
8430
8431                 /* Enable Full-Duplex advertisement on CL37 */
8432                 bnx2x_cl45_write(bp, phy,
8433                                  MDIO_AN_DEVAD, MDIO_AN_REG_CL37_FC_LP, 0x0020);
8434                 /* Enable CL37 AN */
8435                 bnx2x_cl45_write(bp, phy,
8436                                  MDIO_AN_DEVAD, MDIO_AN_REG_CL37_AN, 0x1000);
8437                 /* 1G support */
8438                 bnx2x_cl45_write(bp, phy,
8439                                  MDIO_AN_DEVAD, MDIO_AN_REG_ADV, (1<<5));
8440
8441                 /* Enable clause 73 AN */
8442                 bnx2x_cl45_write(bp, phy,
8443                                  MDIO_AN_DEVAD, MDIO_AN_REG_CTRL, 0x1200);
8444                 bnx2x_cl45_write(bp, phy,
8445                                  MDIO_PMA_DEVAD, MDIO_PMA_LASI_RXCTRL,
8446                                  0x0400);
8447                 bnx2x_cl45_write(bp, phy,
8448                                  MDIO_PMA_DEVAD, MDIO_PMA_LASI_CTRL,
8449                                  0x0004);
8450         }
8451         bnx2x_save_bcm_spirom_ver(bp, phy, params->port);
8452
8453         /*
8454          * If TX Laser is controlled by GPIO_0, do not let PHY go into low
8455          * power mode, if TX Laser is disabled
8456          */
8457
8458         tx_en_mode = REG_RD(bp, params->shmem_base +
8459                             offsetof(struct shmem_region,
8460                                 dev_info.port_hw_config[params->port].sfp_ctrl))
8461                         & PORT_HW_CFG_TX_LASER_MASK;
8462
8463         if (tx_en_mode == PORT_HW_CFG_TX_LASER_GPIO0) {
8464                 DP(NETIF_MSG_LINK, "Enabling TXONOFF_PWRDN_DIS\n");
8465                 bnx2x_cl45_read(bp, phy,
8466                         MDIO_PMA_DEVAD, MDIO_PMA_REG_DIGITAL_CTRL, &tmp1);
8467                 tmp1 |= 0x1;
8468                 bnx2x_cl45_write(bp, phy,
8469                         MDIO_PMA_DEVAD, MDIO_PMA_REG_DIGITAL_CTRL, tmp1);
8470         }
8471
8472         return 0;
8473 }
8474
8475 static int bnx2x_8706_read_status(struct bnx2x_phy *phy,
8476                                   struct link_params *params,
8477                                   struct link_vars *vars)
8478 {
8479         return bnx2x_8706_8726_read_status(phy, params, vars);
8480 }
8481
8482 /******************************************************************/
8483 /*                      BCM8726 PHY SECTION                       */
8484 /******************************************************************/
8485 static void bnx2x_8726_config_loopback(struct bnx2x_phy *phy,
8486                                        struct link_params *params)
8487 {
8488         struct bnx2x *bp = params->bp;
8489         DP(NETIF_MSG_LINK, "PMA/PMD ext_phy_loopback: 8726\n");
8490         bnx2x_cl45_write(bp, phy, MDIO_PMA_DEVAD, MDIO_PMA_REG_CTRL, 0x0001);
8491 }
8492
8493 static void bnx2x_8726_external_rom_boot(struct bnx2x_phy *phy,
8494                                          struct link_params *params)
8495 {
8496         struct bnx2x *bp = params->bp;
8497         /* Need to wait 100ms after reset */
8498         msleep(100);
8499
8500         /* Micro controller re-boot */
8501         bnx2x_cl45_write(bp, phy,
8502                          MDIO_PMA_DEVAD, MDIO_PMA_REG_GEN_CTRL, 0x018B);
8503
8504         /* Set soft reset */
8505         bnx2x_cl45_write(bp, phy,
8506                          MDIO_PMA_DEVAD,
8507                          MDIO_PMA_REG_GEN_CTRL,
8508                          MDIO_PMA_REG_GEN_CTRL_ROM_MICRO_RESET);
8509
8510         bnx2x_cl45_write(bp, phy,
8511                          MDIO_PMA_DEVAD,
8512                          MDIO_PMA_REG_MISC_CTRL1, 0x0001);
8513
8514         bnx2x_cl45_write(bp, phy,
8515                          MDIO_PMA_DEVAD,
8516                          MDIO_PMA_REG_GEN_CTRL,
8517                          MDIO_PMA_REG_GEN_CTRL_ROM_RESET_INTERNAL_MP);
8518
8519         /* wait for 150ms for microcode load */
8520         msleep(150);
8521
8522         /* Disable serial boot control, tristates pins SS_N, SCK, MOSI, MISO */
8523         bnx2x_cl45_write(bp, phy,
8524                          MDIO_PMA_DEVAD,
8525                          MDIO_PMA_REG_MISC_CTRL1, 0x0000);
8526
8527         msleep(200);
8528         bnx2x_save_bcm_spirom_ver(bp, phy, params->port);
8529 }
8530
8531 static u8 bnx2x_8726_read_status(struct bnx2x_phy *phy,
8532                                  struct link_params *params,
8533                                  struct link_vars *vars)
8534 {
8535         struct bnx2x *bp = params->bp;
8536         u16 val1;
8537         u8 link_up = bnx2x_8706_8726_read_status(phy, params, vars);
8538         if (link_up) {
8539                 bnx2x_cl45_read(bp, phy,
8540                                 MDIO_PMA_DEVAD, MDIO_PMA_REG_PHY_IDENTIFIER,
8541                                 &val1);
8542                 if (val1 & (1<<15)) {
8543                         DP(NETIF_MSG_LINK, "Tx is disabled\n");
8544                         link_up = 0;
8545                         vars->line_speed = 0;
8546                 }
8547         }
8548         return link_up;
8549 }
8550
8551
8552 static int bnx2x_8726_config_init(struct bnx2x_phy *phy,
8553                                   struct link_params *params,
8554                                   struct link_vars *vars)
8555 {
8556         struct bnx2x *bp = params->bp;
8557         DP(NETIF_MSG_LINK, "Initializing BCM8726\n");
8558
8559         bnx2x_cl45_write(bp, phy, MDIO_PMA_DEVAD, MDIO_PMA_REG_CTRL, 1<<15);
8560         bnx2x_wait_reset_complete(bp, phy, params);
8561
8562         bnx2x_8726_external_rom_boot(phy, params);
8563
8564         /*
8565          * Need to call module detected on initialization since the module
8566          * detection triggered by actual module insertion might occur before
8567          * driver is loaded, and when driver is loaded, it reset all
8568          * registers, including the transmitter
8569          */
8570         bnx2x_sfp_module_detection(phy, params);
8571
8572         if (phy->req_line_speed == SPEED_1000) {
8573                 DP(NETIF_MSG_LINK, "Setting 1G force\n");
8574                 bnx2x_cl45_write(bp, phy,
8575                                  MDIO_PMA_DEVAD, MDIO_PMA_REG_CTRL, 0x40);
8576                 bnx2x_cl45_write(bp, phy,
8577                                  MDIO_PMA_DEVAD, MDIO_PMA_REG_10G_CTRL2, 0xD);
8578                 bnx2x_cl45_write(bp, phy,
8579                                  MDIO_PMA_DEVAD, MDIO_PMA_LASI_CTRL, 0x5);
8580                 bnx2x_cl45_write(bp, phy,
8581                                  MDIO_PMA_DEVAD, MDIO_PMA_LASI_RXCTRL,
8582                                  0x400);
8583         } else if ((phy->req_line_speed == SPEED_AUTO_NEG) &&
8584                    (phy->speed_cap_mask &
8585                       PORT_HW_CFG_SPEED_CAPABILITY_D0_1G) &&
8586                    ((phy->speed_cap_mask &
8587                       PORT_HW_CFG_SPEED_CAPABILITY_D0_10G) !=
8588                     PORT_HW_CFG_SPEED_CAPABILITY_D0_10G)) {
8589                 DP(NETIF_MSG_LINK, "Setting 1G clause37\n");
8590                 /* Set Flow control */
8591                 bnx2x_ext_phy_set_pause(params, phy, vars);
8592                 bnx2x_cl45_write(bp, phy,
8593                                  MDIO_AN_DEVAD, MDIO_AN_REG_ADV, 0x20);
8594                 bnx2x_cl45_write(bp, phy,
8595                                  MDIO_AN_DEVAD, MDIO_AN_REG_CL37_CL73, 0x040c);
8596                 bnx2x_cl45_write(bp, phy,
8597                                  MDIO_AN_DEVAD, MDIO_AN_REG_CL37_FC_LD, 0x0020);
8598                 bnx2x_cl45_write(bp, phy,
8599                                  MDIO_AN_DEVAD, MDIO_AN_REG_CL37_AN, 0x1000);
8600                 bnx2x_cl45_write(bp, phy,
8601                                 MDIO_AN_DEVAD, MDIO_AN_REG_CTRL, 0x1200);
8602                 /*
8603                  * Enable RX-ALARM control to receive interrupt for 1G speed
8604                  * change
8605                  */
8606                 bnx2x_cl45_write(bp, phy,
8607                                  MDIO_PMA_DEVAD, MDIO_PMA_LASI_CTRL, 0x4);
8608                 bnx2x_cl45_write(bp, phy,
8609                                  MDIO_PMA_DEVAD, MDIO_PMA_LASI_RXCTRL,
8610                                  0x400);
8611
8612         } else { /* Default 10G. Set only LASI control */
8613                 bnx2x_cl45_write(bp, phy,
8614                                  MDIO_PMA_DEVAD, MDIO_PMA_LASI_CTRL, 1);
8615         }
8616
8617         /* Set TX PreEmphasis if needed */
8618         if ((params->feature_config_flags &
8619              FEATURE_CONFIG_OVERRIDE_PREEMPHASIS_ENABLED)) {
8620                 DP(NETIF_MSG_LINK,
8621                    "Setting TX_CTRL1 0x%x, TX_CTRL2 0x%x\n",
8622                          phy->tx_preemphasis[0],
8623                          phy->tx_preemphasis[1]);
8624                 bnx2x_cl45_write(bp, phy,
8625                                  MDIO_PMA_DEVAD,
8626                                  MDIO_PMA_REG_8726_TX_CTRL1,
8627                                  phy->tx_preemphasis[0]);
8628
8629                 bnx2x_cl45_write(bp, phy,
8630                                  MDIO_PMA_DEVAD,
8631                                  MDIO_PMA_REG_8726_TX_CTRL2,
8632                                  phy->tx_preemphasis[1]);
8633         }
8634
8635         return 0;
8636
8637 }
8638
8639 static void bnx2x_8726_link_reset(struct bnx2x_phy *phy,
8640                                   struct link_params *params)
8641 {
8642         struct bnx2x *bp = params->bp;
8643         DP(NETIF_MSG_LINK, "bnx2x_8726_link_reset port %d\n", params->port);
8644         /* Set serial boot control for external load */
8645         bnx2x_cl45_write(bp, phy,
8646                          MDIO_PMA_DEVAD,
8647                          MDIO_PMA_REG_GEN_CTRL, 0x0001);
8648 }
8649
8650 /******************************************************************/
8651 /*                      BCM8727 PHY SECTION                       */
8652 /******************************************************************/
8653
8654 static void bnx2x_8727_set_link_led(struct bnx2x_phy *phy,
8655                                     struct link_params *params, u8 mode)
8656 {
8657         struct bnx2x *bp = params->bp;
8658         u16 led_mode_bitmask = 0;
8659         u16 gpio_pins_bitmask = 0;
8660         u16 val;
8661         /* Only NOC flavor requires to set the LED specifically */
8662         if (!(phy->flags & FLAGS_NOC))
8663                 return;
8664         switch (mode) {
8665         case LED_MODE_FRONT_PANEL_OFF:
8666         case LED_MODE_OFF:
8667                 led_mode_bitmask = 0;
8668                 gpio_pins_bitmask = 0x03;
8669                 break;
8670         case LED_MODE_ON:
8671                 led_mode_bitmask = 0;
8672                 gpio_pins_bitmask = 0x02;
8673                 break;
8674         case LED_MODE_OPER:
8675                 led_mode_bitmask = 0x60;
8676                 gpio_pins_bitmask = 0x11;
8677                 break;
8678         }
8679         bnx2x_cl45_read(bp, phy,
8680                         MDIO_PMA_DEVAD,
8681                         MDIO_PMA_REG_8727_PCS_OPT_CTRL,
8682                         &val);
8683         val &= 0xff8f;
8684         val |= led_mode_bitmask;
8685         bnx2x_cl45_write(bp, phy,
8686                          MDIO_PMA_DEVAD,
8687                          MDIO_PMA_REG_8727_PCS_OPT_CTRL,
8688                          val);
8689         bnx2x_cl45_read(bp, phy,
8690                         MDIO_PMA_DEVAD,
8691                         MDIO_PMA_REG_8727_GPIO_CTRL,
8692                         &val);
8693         val &= 0xffe0;
8694         val |= gpio_pins_bitmask;
8695         bnx2x_cl45_write(bp, phy,
8696                          MDIO_PMA_DEVAD,
8697                          MDIO_PMA_REG_8727_GPIO_CTRL,
8698                          val);
8699 }
8700 static void bnx2x_8727_hw_reset(struct bnx2x_phy *phy,
8701                                 struct link_params *params) {
8702         u32 swap_val, swap_override;
8703         u8 port;
8704         /*
8705          * The PHY reset is controlled by GPIO 1. Fake the port number
8706          * to cancel the swap done in set_gpio()
8707          */
8708         struct bnx2x *bp = params->bp;
8709         swap_val = REG_RD(bp, NIG_REG_PORT_SWAP);
8710         swap_override = REG_RD(bp, NIG_REG_STRAP_OVERRIDE);
8711         port = (swap_val && swap_override) ^ 1;
8712         bnx2x_set_gpio(bp, MISC_REGISTERS_GPIO_1,
8713                        MISC_REGISTERS_GPIO_OUTPUT_LOW, port);
8714 }
8715
8716 static int bnx2x_8727_config_init(struct bnx2x_phy *phy,
8717                                   struct link_params *params,
8718                                   struct link_vars *vars)
8719 {
8720         u32 tx_en_mode;
8721         u16 tmp1, val, mod_abs, tmp2;
8722         u16 rx_alarm_ctrl_val;
8723         u16 lasi_ctrl_val;
8724         struct bnx2x *bp = params->bp;
8725         /* Enable PMD link, MOD_ABS_FLT, and 1G link alarm */
8726
8727         bnx2x_wait_reset_complete(bp, phy, params);
8728         rx_alarm_ctrl_val = (1<<2) | (1<<5) ;
8729         /* Should be 0x6 to enable XS on Tx side. */
8730         lasi_ctrl_val = 0x0006;
8731
8732         DP(NETIF_MSG_LINK, "Initializing BCM8727\n");
8733         /* enable LASI */
8734         bnx2x_cl45_write(bp, phy,
8735                          MDIO_PMA_DEVAD, MDIO_PMA_LASI_RXCTRL,
8736                          rx_alarm_ctrl_val);
8737         bnx2x_cl45_write(bp, phy,
8738                          MDIO_PMA_DEVAD, MDIO_PMA_LASI_TXCTRL,
8739                          0);
8740         bnx2x_cl45_write(bp, phy,
8741                          MDIO_PMA_DEVAD, MDIO_PMA_LASI_CTRL, lasi_ctrl_val);
8742
8743         /*
8744          * Initially configure MOD_ABS to interrupt when module is
8745          * presence( bit 8)
8746          */
8747         bnx2x_cl45_read(bp, phy,
8748                         MDIO_PMA_DEVAD, MDIO_PMA_REG_PHY_IDENTIFIER, &mod_abs);
8749         /*
8750          * Set EDC off by setting OPTXLOS signal input to low (bit 9).
8751          * When the EDC is off it locks onto a reference clock and avoids
8752          * becoming 'lost'
8753          */
8754         mod_abs &= ~(1<<8);
8755         if (!(phy->flags & FLAGS_NOC))
8756                 mod_abs &= ~(1<<9);
8757         bnx2x_cl45_write(bp, phy,
8758                          MDIO_PMA_DEVAD, MDIO_PMA_REG_PHY_IDENTIFIER, mod_abs);
8759
8760
8761         /* Enable/Disable PHY transmitter output */
8762         bnx2x_set_disable_pmd_transmit(params, phy, 0);
8763
8764         /* Make MOD_ABS give interrupt on change */
8765         bnx2x_cl45_read(bp, phy, MDIO_PMA_DEVAD, MDIO_PMA_REG_8727_PCS_OPT_CTRL,
8766                         &val);
8767         val |= (1<<12);
8768         if (phy->flags & FLAGS_NOC)
8769                 val |= (3<<5);
8770
8771         /*
8772          * Set 8727 GPIOs to input to allow reading from the 8727 GPIO0
8773          * status which reflect SFP+ module over-current
8774          */
8775         if (!(phy->flags & FLAGS_NOC))
8776                 val &= 0xff8f; /* Reset bits 4-6 */
8777         bnx2x_cl45_write(bp, phy,
8778                          MDIO_PMA_DEVAD, MDIO_PMA_REG_8727_PCS_OPT_CTRL, val);
8779
8780         bnx2x_8727_power_module(bp, phy, 1);
8781
8782         bnx2x_cl45_read(bp, phy,
8783                         MDIO_PMA_DEVAD, MDIO_PMA_REG_M8051_MSGOUT_REG, &tmp1);
8784
8785         bnx2x_cl45_read(bp, phy,
8786                         MDIO_PMA_DEVAD, MDIO_PMA_LASI_RXSTAT, &tmp1);
8787
8788         /* Set option 1G speed */
8789         if (phy->req_line_speed == SPEED_1000) {
8790                 DP(NETIF_MSG_LINK, "Setting 1G force\n");
8791                 bnx2x_cl45_write(bp, phy,
8792                                  MDIO_PMA_DEVAD, MDIO_PMA_REG_CTRL, 0x40);
8793                 bnx2x_cl45_write(bp, phy,
8794                                  MDIO_PMA_DEVAD, MDIO_PMA_REG_10G_CTRL2, 0xD);
8795                 bnx2x_cl45_read(bp, phy,
8796                                 MDIO_PMA_DEVAD, MDIO_PMA_REG_10G_CTRL2, &tmp1);
8797                 DP(NETIF_MSG_LINK, "1.7 = 0x%x\n", tmp1);
8798                 /*
8799                  * Power down the XAUI until link is up in case of dual-media
8800                  * and 1G
8801                  */
8802                 if (DUAL_MEDIA(params)) {
8803                         bnx2x_cl45_read(bp, phy,
8804                                         MDIO_PMA_DEVAD,
8805                                         MDIO_PMA_REG_8727_PCS_GP, &val);
8806                         val |= (3<<10);
8807                         bnx2x_cl45_write(bp, phy,
8808                                          MDIO_PMA_DEVAD,
8809                                          MDIO_PMA_REG_8727_PCS_GP, val);
8810                 }
8811         } else if ((phy->req_line_speed == SPEED_AUTO_NEG) &&
8812                    ((phy->speed_cap_mask &
8813                      PORT_HW_CFG_SPEED_CAPABILITY_D0_1G)) &&
8814                    ((phy->speed_cap_mask &
8815                       PORT_HW_CFG_SPEED_CAPABILITY_D0_10G) !=
8816                    PORT_HW_CFG_SPEED_CAPABILITY_D0_10G)) {
8817
8818                 DP(NETIF_MSG_LINK, "Setting 1G clause37\n");
8819                 bnx2x_cl45_write(bp, phy,
8820                                  MDIO_AN_DEVAD, MDIO_AN_REG_8727_MISC_CTRL, 0);
8821                 bnx2x_cl45_write(bp, phy,
8822                                  MDIO_AN_DEVAD, MDIO_AN_REG_CL37_AN, 0x1300);
8823         } else {
8824                 /*
8825                  * Since the 8727 has only single reset pin, need to set the 10G
8826                  * registers although it is default
8827                  */
8828                 bnx2x_cl45_write(bp, phy,
8829                                  MDIO_AN_DEVAD, MDIO_AN_REG_8727_MISC_CTRL,
8830                                  0x0020);
8831                 bnx2x_cl45_write(bp, phy,
8832                                  MDIO_AN_DEVAD, MDIO_AN_REG_CL37_AN, 0x0100);
8833                 bnx2x_cl45_write(bp, phy,
8834                                  MDIO_PMA_DEVAD, MDIO_PMA_REG_CTRL, 0x2040);
8835                 bnx2x_cl45_write(bp, phy,
8836                                  MDIO_PMA_DEVAD, MDIO_PMA_REG_10G_CTRL2,
8837                                  0x0008);
8838         }
8839
8840         /*
8841          * Set 2-wire transfer rate of SFP+ module EEPROM
8842          * to 100Khz since some DACs(direct attached cables) do
8843          * not work at 400Khz.
8844          */
8845         bnx2x_cl45_write(bp, phy,
8846                          MDIO_PMA_DEVAD, MDIO_PMA_REG_8727_TWO_WIRE_SLAVE_ADDR,
8847                          0xa001);
8848
8849         /* Set TX PreEmphasis if needed */
8850         if ((params->feature_config_flags &
8851              FEATURE_CONFIG_OVERRIDE_PREEMPHASIS_ENABLED)) {
8852                 DP(NETIF_MSG_LINK, "Setting TX_CTRL1 0x%x, TX_CTRL2 0x%x\n",
8853                            phy->tx_preemphasis[0],
8854                            phy->tx_preemphasis[1]);
8855                 bnx2x_cl45_write(bp, phy,
8856                                  MDIO_PMA_DEVAD, MDIO_PMA_REG_8727_TX_CTRL1,
8857                                  phy->tx_preemphasis[0]);
8858
8859                 bnx2x_cl45_write(bp, phy,
8860                                  MDIO_PMA_DEVAD, MDIO_PMA_REG_8727_TX_CTRL2,
8861                                  phy->tx_preemphasis[1]);
8862         }
8863
8864         /*
8865          * If TX Laser is controlled by GPIO_0, do not let PHY go into low
8866          * power mode, if TX Laser is disabled
8867          */
8868         tx_en_mode = REG_RD(bp, params->shmem_base +
8869                             offsetof(struct shmem_region,
8870                                 dev_info.port_hw_config[params->port].sfp_ctrl))
8871                         & PORT_HW_CFG_TX_LASER_MASK;
8872
8873         if (tx_en_mode == PORT_HW_CFG_TX_LASER_GPIO0) {
8874
8875                 DP(NETIF_MSG_LINK, "Enabling TXONOFF_PWRDN_DIS\n");
8876                 bnx2x_cl45_read(bp, phy,
8877                         MDIO_PMA_DEVAD, MDIO_PMA_REG_8727_OPT_CFG_REG, &tmp2);
8878                 tmp2 |= 0x1000;
8879                 tmp2 &= 0xFFEF;
8880                 bnx2x_cl45_write(bp, phy,
8881                         MDIO_PMA_DEVAD, MDIO_PMA_REG_8727_OPT_CFG_REG, tmp2);
8882         }
8883
8884         return 0;
8885 }
8886
8887 static void bnx2x_8727_handle_mod_abs(struct bnx2x_phy *phy,
8888                                       struct link_params *params)
8889 {
8890         struct bnx2x *bp = params->bp;
8891         u16 mod_abs, rx_alarm_status;
8892         u32 val = REG_RD(bp, params->shmem_base +
8893                              offsetof(struct shmem_region, dev_info.
8894                                       port_feature_config[params->port].
8895                                       config));
8896         bnx2x_cl45_read(bp, phy,
8897                         MDIO_PMA_DEVAD,
8898                         MDIO_PMA_REG_PHY_IDENTIFIER, &mod_abs);
8899         if (mod_abs & (1<<8)) {
8900
8901                 /* Module is absent */
8902                 DP(NETIF_MSG_LINK,
8903                    "MOD_ABS indication show module is absent\n");
8904                 phy->media_type = ETH_PHY_NOT_PRESENT;
8905                 /*
8906                  * 1. Set mod_abs to detect next module
8907                  *    presence event
8908                  * 2. Set EDC off by setting OPTXLOS signal input to low
8909                  *    (bit 9).
8910                  *    When the EDC is off it locks onto a reference clock and
8911                  *    avoids becoming 'lost'.
8912                  */
8913                 mod_abs &= ~(1<<8);
8914                 if (!(phy->flags & FLAGS_NOC))
8915                         mod_abs &= ~(1<<9);
8916                 bnx2x_cl45_write(bp, phy,
8917                                  MDIO_PMA_DEVAD,
8918                                  MDIO_PMA_REG_PHY_IDENTIFIER, mod_abs);
8919
8920                 /*
8921                  * Clear RX alarm since it stays up as long as
8922                  * the mod_abs wasn't changed
8923                  */
8924                 bnx2x_cl45_read(bp, phy,
8925                                 MDIO_PMA_DEVAD,
8926                                 MDIO_PMA_LASI_RXSTAT, &rx_alarm_status);
8927
8928         } else {
8929                 /* Module is present */
8930                 DP(NETIF_MSG_LINK,
8931                    "MOD_ABS indication show module is present\n");
8932                 /*
8933                  * First disable transmitter, and if the module is ok, the
8934                  * module_detection will enable it
8935                  * 1. Set mod_abs to detect next module absent event ( bit 8)
8936                  * 2. Restore the default polarity of the OPRXLOS signal and
8937                  * this signal will then correctly indicate the presence or
8938                  * absence of the Rx signal. (bit 9)
8939                  */
8940                 mod_abs |= (1<<8);
8941                 if (!(phy->flags & FLAGS_NOC))
8942                         mod_abs |= (1<<9);
8943                 bnx2x_cl45_write(bp, phy,
8944                                  MDIO_PMA_DEVAD,
8945                                  MDIO_PMA_REG_PHY_IDENTIFIER, mod_abs);
8946
8947                 /*
8948                  * Clear RX alarm since it stays up as long as the mod_abs
8949                  * wasn't changed. This is need to be done before calling the
8950                  * module detection, otherwise it will clear* the link update
8951                  * alarm
8952                  */
8953                 bnx2x_cl45_read(bp, phy,
8954                                 MDIO_PMA_DEVAD,
8955                                 MDIO_PMA_LASI_RXSTAT, &rx_alarm_status);
8956
8957
8958                 if ((val & PORT_FEAT_CFG_OPT_MDL_ENFRCMNT_MASK) ==
8959                     PORT_FEAT_CFG_OPT_MDL_ENFRCMNT_DISABLE_TX_LASER)
8960                         bnx2x_sfp_set_transmitter(params, phy, 0);
8961
8962                 if (bnx2x_wait_for_sfp_module_initialized(phy, params) == 0)
8963                         bnx2x_sfp_module_detection(phy, params);
8964                 else
8965                         DP(NETIF_MSG_LINK, "SFP+ module is not initialized\n");
8966         }
8967
8968         DP(NETIF_MSG_LINK, "8727 RX_ALARM_STATUS 0x%x\n",
8969                    rx_alarm_status);
8970         /* No need to check link status in case of module plugged in/out */
8971 }
8972
8973 static u8 bnx2x_8727_read_status(struct bnx2x_phy *phy,
8974                                  struct link_params *params,
8975                                  struct link_vars *vars)
8976
8977 {
8978         struct bnx2x *bp = params->bp;
8979         u8 link_up = 0, oc_port = params->port;
8980         u16 link_status = 0;
8981         u16 rx_alarm_status, lasi_ctrl, val1;
8982
8983         /* If PHY is not initialized, do not check link status */
8984         bnx2x_cl45_read(bp, phy,
8985                         MDIO_PMA_DEVAD, MDIO_PMA_LASI_CTRL,
8986                         &lasi_ctrl);
8987         if (!lasi_ctrl)
8988                 return 0;
8989
8990         /* Check the LASI on Rx */
8991         bnx2x_cl45_read(bp, phy,
8992                         MDIO_PMA_DEVAD, MDIO_PMA_LASI_RXSTAT,
8993                         &rx_alarm_status);
8994         vars->line_speed = 0;
8995         DP(NETIF_MSG_LINK, "8727 RX_ALARM_STATUS  0x%x\n", rx_alarm_status);
8996
8997         bnx2x_sfp_mask_fault(bp, phy, MDIO_PMA_LASI_TXSTAT,
8998                              MDIO_PMA_LASI_TXCTRL);
8999
9000         bnx2x_cl45_read(bp, phy,
9001                         MDIO_PMA_DEVAD, MDIO_PMA_LASI_STAT, &val1);
9002
9003         DP(NETIF_MSG_LINK, "8727 LASI status 0x%x\n", val1);
9004
9005         /* Clear MSG-OUT */
9006         bnx2x_cl45_read(bp, phy,
9007                         MDIO_PMA_DEVAD, MDIO_PMA_REG_M8051_MSGOUT_REG, &val1);
9008
9009         /*
9010          * If a module is present and there is need to check
9011          * for over current
9012          */
9013         if (!(phy->flags & FLAGS_NOC) && !(rx_alarm_status & (1<<5))) {
9014                 /* Check over-current using 8727 GPIO0 input*/
9015                 bnx2x_cl45_read(bp, phy,
9016                                 MDIO_PMA_DEVAD, MDIO_PMA_REG_8727_GPIO_CTRL,
9017                                 &val1);
9018
9019                 if ((val1 & (1<<8)) == 0) {
9020                         if (!CHIP_IS_E1x(bp))
9021                                 oc_port = BP_PATH(bp) + (params->port << 1);
9022                         DP(NETIF_MSG_LINK,
9023                            "8727 Power fault has been detected on port %d\n",
9024                            oc_port);
9025                         netdev_err(bp->dev, "Error:  Power fault on Port %d has"
9026                                             " been detected and the power to "
9027                                             "that SFP+ module has been removed"
9028                                             " to prevent failure of the card."
9029                                             " Please remove the SFP+ module and"
9030                                             " restart the system to clear this"
9031                                             " error.\n",
9032                          oc_port);
9033                         /* Disable all RX_ALARMs except for mod_abs */
9034                         bnx2x_cl45_write(bp, phy,
9035                                          MDIO_PMA_DEVAD,
9036                                          MDIO_PMA_LASI_RXCTRL, (1<<5));
9037
9038                         bnx2x_cl45_read(bp, phy,
9039                                         MDIO_PMA_DEVAD,
9040                                         MDIO_PMA_REG_PHY_IDENTIFIER, &val1);
9041                         /* Wait for module_absent_event */
9042                         val1 |= (1<<8);
9043                         bnx2x_cl45_write(bp, phy,
9044                                          MDIO_PMA_DEVAD,
9045                                          MDIO_PMA_REG_PHY_IDENTIFIER, val1);
9046                         /* Clear RX alarm */
9047                         bnx2x_cl45_read(bp, phy,
9048                                 MDIO_PMA_DEVAD,
9049                                 MDIO_PMA_LASI_RXSTAT, &rx_alarm_status);
9050                         return 0;
9051                 }
9052         } /* Over current check */
9053
9054         /* When module absent bit is set, check module */
9055         if (rx_alarm_status & (1<<5)) {
9056                 bnx2x_8727_handle_mod_abs(phy, params);
9057                 /* Enable all mod_abs and link detection bits */
9058                 bnx2x_cl45_write(bp, phy,
9059                                  MDIO_PMA_DEVAD, MDIO_PMA_LASI_RXCTRL,
9060                                  ((1<<5) | (1<<2)));
9061         }
9062         DP(NETIF_MSG_LINK, "Enabling 8727 TX laser if SFP is approved\n");
9063         bnx2x_8727_specific_func(phy, params, ENABLE_TX);
9064         /* If transmitter is disabled, ignore false link up indication */
9065         bnx2x_cl45_read(bp, phy,
9066                         MDIO_PMA_DEVAD, MDIO_PMA_REG_PHY_IDENTIFIER, &val1);
9067         if (val1 & (1<<15)) {
9068                 DP(NETIF_MSG_LINK, "Tx is disabled\n");
9069                 return 0;
9070         }
9071
9072         bnx2x_cl45_read(bp, phy,
9073                         MDIO_PMA_DEVAD,
9074                         MDIO_PMA_REG_8073_SPEED_LINK_STATUS, &link_status);
9075
9076         /*
9077          * Bits 0..2 --> speed detected,
9078          * Bits 13..15--> link is down
9079          */
9080         if ((link_status & (1<<2)) && (!(link_status & (1<<15)))) {
9081                 link_up = 1;
9082                 vars->line_speed = SPEED_10000;
9083                 DP(NETIF_MSG_LINK, "port %x: External link up in 10G\n",
9084                            params->port);
9085         } else if ((link_status & (1<<0)) && (!(link_status & (1<<13)))) {
9086                 link_up = 1;
9087                 vars->line_speed = SPEED_1000;
9088                 DP(NETIF_MSG_LINK, "port %x: External link up in 1G\n",
9089                            params->port);
9090         } else {
9091                 link_up = 0;
9092                 DP(NETIF_MSG_LINK, "port %x: External link is down\n",
9093                            params->port);
9094         }
9095
9096         /* Capture 10G link fault. */
9097         if (vars->line_speed == SPEED_10000) {
9098                 bnx2x_cl45_read(bp, phy, MDIO_PMA_DEVAD,
9099                             MDIO_PMA_LASI_TXSTAT, &val1);
9100
9101                 bnx2x_cl45_read(bp, phy, MDIO_PMA_DEVAD,
9102                             MDIO_PMA_LASI_TXSTAT, &val1);
9103
9104                 if (val1 & (1<<0)) {
9105                         vars->fault_detected = 1;
9106                 }
9107         }
9108
9109         if (link_up) {
9110                 bnx2x_ext_phy_resolve_fc(phy, params, vars);
9111                 vars->duplex = DUPLEX_FULL;
9112                 DP(NETIF_MSG_LINK, "duplex = 0x%x\n", vars->duplex);
9113         }
9114
9115         if ((DUAL_MEDIA(params)) &&
9116             (phy->req_line_speed == SPEED_1000)) {
9117                 bnx2x_cl45_read(bp, phy,
9118                                 MDIO_PMA_DEVAD,
9119                                 MDIO_PMA_REG_8727_PCS_GP, &val1);
9120                 /*
9121                  * In case of dual-media board and 1G, power up the XAUI side,
9122                  * otherwise power it down. For 10G it is done automatically
9123                  */
9124                 if (link_up)
9125                         val1 &= ~(3<<10);
9126                 else
9127                         val1 |= (3<<10);
9128                 bnx2x_cl45_write(bp, phy,
9129                                  MDIO_PMA_DEVAD,
9130                                  MDIO_PMA_REG_8727_PCS_GP, val1);
9131         }
9132         return link_up;
9133 }
9134
9135 static void bnx2x_8727_link_reset(struct bnx2x_phy *phy,
9136                                   struct link_params *params)
9137 {
9138         struct bnx2x *bp = params->bp;
9139
9140         /* Enable/Disable PHY transmitter output */
9141         bnx2x_set_disable_pmd_transmit(params, phy, 1);
9142
9143         /* Disable Transmitter */
9144         bnx2x_sfp_set_transmitter(params, phy, 0);
9145         /* Clear LASI */
9146         bnx2x_cl45_write(bp, phy, MDIO_PMA_DEVAD, MDIO_PMA_LASI_CTRL, 0);
9147
9148 }
9149
9150 /******************************************************************/
9151 /*              BCM8481/BCM84823/BCM84833 PHY SECTION             */
9152 /******************************************************************/
9153 static void bnx2x_save_848xx_spirom_version(struct bnx2x_phy *phy,
9154                                            struct link_params *params)
9155 {
9156         u16 val, fw_ver1, fw_ver2, cnt;
9157         u8 port;
9158         struct bnx2x *bp = params->bp;
9159
9160         port = params->port;
9161
9162         /* For the 32 bits registers in 848xx, access via MDIO2ARM interface.*/
9163         /* (1) set register 0xc200_0014(SPI_BRIDGE_CTRL_2) to 0x03000000 */
9164         bnx2x_cl45_write(bp, phy, MDIO_PMA_DEVAD, 0xA819, 0x0014);
9165         bnx2x_cl45_write(bp, phy, MDIO_PMA_DEVAD, 0xA81A, 0xc200);
9166         bnx2x_cl45_write(bp, phy, MDIO_PMA_DEVAD, 0xA81B, 0x0000);
9167         bnx2x_cl45_write(bp, phy, MDIO_PMA_DEVAD, 0xA81C, 0x0300);
9168         bnx2x_cl45_write(bp, phy, MDIO_PMA_DEVAD, 0xA817, 0x0009);
9169
9170         for (cnt = 0; cnt < 100; cnt++) {
9171                 bnx2x_cl45_read(bp, phy, MDIO_PMA_DEVAD, 0xA818, &val);
9172                 if (val & 1)
9173                         break;
9174                 udelay(5);
9175         }
9176         if (cnt == 100) {
9177                 DP(NETIF_MSG_LINK, "Unable to read 848xx phy fw version(1)\n");
9178                 bnx2x_save_spirom_version(bp, port, 0,
9179                                           phy->ver_addr);
9180                 return;
9181         }
9182
9183
9184         /* 2) read register 0xc200_0000 (SPI_FW_STATUS) */
9185         bnx2x_cl45_write(bp, phy, MDIO_PMA_DEVAD, 0xA819, 0x0000);
9186         bnx2x_cl45_write(bp, phy, MDIO_PMA_DEVAD, 0xA81A, 0xc200);
9187         bnx2x_cl45_write(bp, phy, MDIO_PMA_DEVAD, 0xA817, 0x000A);
9188         for (cnt = 0; cnt < 100; cnt++) {
9189                 bnx2x_cl45_read(bp, phy, MDIO_PMA_DEVAD, 0xA818, &val);
9190                 if (val & 1)
9191                         break;
9192                 udelay(5);
9193         }
9194         if (cnt == 100) {
9195                 DP(NETIF_MSG_LINK, "Unable to read 848xx phy fw version(2)\n");
9196                 bnx2x_save_spirom_version(bp, port, 0,
9197                                           phy->ver_addr);
9198                 return;
9199         }
9200
9201         /* lower 16 bits of the register SPI_FW_STATUS */
9202         bnx2x_cl45_read(bp, phy, MDIO_PMA_DEVAD, 0xA81B, &fw_ver1);
9203         /* upper 16 bits of register SPI_FW_STATUS */
9204         bnx2x_cl45_read(bp, phy, MDIO_PMA_DEVAD, 0xA81C, &fw_ver2);
9205
9206         bnx2x_save_spirom_version(bp, port, (fw_ver2<<16) | fw_ver1,
9207                                   phy->ver_addr);
9208 }
9209
9210 static void bnx2x_848xx_set_led(struct bnx2x *bp,
9211                                 struct bnx2x_phy *phy)
9212 {
9213         u16 val;
9214
9215         /* PHYC_CTL_LED_CTL */
9216         bnx2x_cl45_read(bp, phy,
9217                         MDIO_PMA_DEVAD,
9218                         MDIO_PMA_REG_8481_LINK_SIGNAL, &val);
9219         val &= 0xFE00;
9220         val |= 0x0092;
9221
9222         bnx2x_cl45_write(bp, phy,
9223                          MDIO_PMA_DEVAD,
9224                          MDIO_PMA_REG_8481_LINK_SIGNAL, val);
9225
9226         bnx2x_cl45_write(bp, phy,
9227                          MDIO_PMA_DEVAD,
9228                          MDIO_PMA_REG_8481_LED1_MASK,
9229                          0x80);
9230
9231         bnx2x_cl45_write(bp, phy,
9232                          MDIO_PMA_DEVAD,
9233                          MDIO_PMA_REG_8481_LED2_MASK,
9234                          0x18);
9235
9236         /* Select activity source by Tx and Rx, as suggested by PHY AE */
9237         bnx2x_cl45_write(bp, phy,
9238                          MDIO_PMA_DEVAD,
9239                          MDIO_PMA_REG_8481_LED3_MASK,
9240                          0x0006);
9241
9242         /* Select the closest activity blink rate to that in 10/100/1000 */
9243         bnx2x_cl45_write(bp, phy,
9244                         MDIO_PMA_DEVAD,
9245                         MDIO_PMA_REG_8481_LED3_BLINK,
9246                         0);
9247
9248         bnx2x_cl45_read(bp, phy,
9249                         MDIO_PMA_DEVAD,
9250                         MDIO_PMA_REG_84823_CTL_LED_CTL_1, &val);
9251         val |= MDIO_PMA_REG_84823_LED3_STRETCH_EN; /* stretch_en for LED3*/
9252
9253         bnx2x_cl45_write(bp, phy,
9254                          MDIO_PMA_DEVAD,
9255                          MDIO_PMA_REG_84823_CTL_LED_CTL_1, val);
9256
9257         /* 'Interrupt Mask' */
9258         bnx2x_cl45_write(bp, phy,
9259                          MDIO_AN_DEVAD,
9260                          0xFFFB, 0xFFFD);
9261 }
9262
9263 static int bnx2x_848xx_cmn_config_init(struct bnx2x_phy *phy,
9264                                        struct link_params *params,
9265                                        struct link_vars *vars)
9266 {
9267         struct bnx2x *bp = params->bp;
9268         u16 autoneg_val, an_1000_val, an_10_100_val;
9269         u16 tmp_req_line_speed;
9270
9271         tmp_req_line_speed = phy->req_line_speed;
9272         if (phy->type == PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM84833)
9273                 if (phy->req_line_speed == SPEED_10000)
9274                         phy->req_line_speed = SPEED_AUTO_NEG;
9275
9276         /*
9277          * This phy uses the NIG latch mechanism since link indication
9278          * arrives through its LED4 and not via its LASI signal, so we
9279          * get steady signal instead of clear on read
9280          */
9281         bnx2x_bits_en(bp, NIG_REG_LATCH_BC_0 + params->port*4,
9282                       1 << NIG_LATCH_BC_ENABLE_MI_INT);
9283
9284         bnx2x_cl45_write(bp, phy,
9285                          MDIO_PMA_DEVAD, MDIO_PMA_REG_CTRL, 0x0000);
9286
9287         bnx2x_848xx_set_led(bp, phy);
9288
9289         /* set 1000 speed advertisement */
9290         bnx2x_cl45_read(bp, phy,
9291                         MDIO_AN_DEVAD, MDIO_AN_REG_8481_1000T_CTRL,
9292                         &an_1000_val);
9293
9294         bnx2x_ext_phy_set_pause(params, phy, vars);
9295         bnx2x_cl45_read(bp, phy,
9296                         MDIO_AN_DEVAD,
9297                         MDIO_AN_REG_8481_LEGACY_AN_ADV,
9298                         &an_10_100_val);
9299         bnx2x_cl45_read(bp, phy,
9300                         MDIO_AN_DEVAD, MDIO_AN_REG_8481_LEGACY_MII_CTRL,
9301                         &autoneg_val);
9302         /* Disable forced speed */
9303         autoneg_val &= ~((1<<6) | (1<<8) | (1<<9) | (1<<12) | (1<<13));
9304         an_10_100_val &= ~((1<<5) | (1<<6) | (1<<7) | (1<<8));
9305
9306         if (((phy->req_line_speed == SPEED_AUTO_NEG) &&
9307              (phy->speed_cap_mask &
9308              PORT_HW_CFG_SPEED_CAPABILITY_D0_1G)) ||
9309             (phy->req_line_speed == SPEED_1000)) {
9310                 an_1000_val |= (1<<8);
9311                 autoneg_val |= (1<<9 | 1<<12);
9312                 if (phy->req_duplex == DUPLEX_FULL)
9313                         an_1000_val |= (1<<9);
9314                 DP(NETIF_MSG_LINK, "Advertising 1G\n");
9315         } else
9316                 an_1000_val &= ~((1<<8) | (1<<9));
9317
9318         bnx2x_cl45_write(bp, phy,
9319                          MDIO_AN_DEVAD, MDIO_AN_REG_8481_1000T_CTRL,
9320                          an_1000_val);
9321
9322         /* set 100 speed advertisement */
9323         if (((phy->req_line_speed == SPEED_AUTO_NEG) &&
9324              (phy->speed_cap_mask &
9325               (PORT_HW_CFG_SPEED_CAPABILITY_D0_100M_FULL |
9326                PORT_HW_CFG_SPEED_CAPABILITY_D0_100M_HALF)) &&
9327              (phy->supported &
9328               (SUPPORTED_100baseT_Half |
9329                SUPPORTED_100baseT_Full)))) {
9330                 an_10_100_val |= (1<<7);
9331                 /* Enable autoneg and restart autoneg for legacy speeds */
9332                 autoneg_val |= (1<<9 | 1<<12);
9333
9334                 if (phy->req_duplex == DUPLEX_FULL)
9335                         an_10_100_val |= (1<<8);
9336                 DP(NETIF_MSG_LINK, "Advertising 100M\n");
9337         }
9338         /* set 10 speed advertisement */
9339         if (((phy->req_line_speed == SPEED_AUTO_NEG) &&
9340              (phy->speed_cap_mask &
9341               (PORT_HW_CFG_SPEED_CAPABILITY_D0_10M_FULL |
9342                PORT_HW_CFG_SPEED_CAPABILITY_D0_10M_HALF)) &&
9343              (phy->supported &
9344               (SUPPORTED_10baseT_Half |
9345                SUPPORTED_10baseT_Full)))) {
9346                 an_10_100_val |= (1<<5);
9347                 autoneg_val |= (1<<9 | 1<<12);
9348                 if (phy->req_duplex == DUPLEX_FULL)
9349                         an_10_100_val |= (1<<6);
9350                 DP(NETIF_MSG_LINK, "Advertising 10M\n");
9351         }
9352
9353         /* Only 10/100 are allowed to work in FORCE mode */
9354         if ((phy->req_line_speed == SPEED_100) &&
9355             (phy->supported &
9356              (SUPPORTED_100baseT_Half |
9357               SUPPORTED_100baseT_Full))) {
9358                 autoneg_val |= (1<<13);
9359                 /* Enabled AUTO-MDIX when autoneg is disabled */
9360                 bnx2x_cl45_write(bp, phy,
9361                                  MDIO_AN_DEVAD, MDIO_AN_REG_8481_AUX_CTRL,
9362                                  (1<<15 | 1<<9 | 7<<0));
9363                 DP(NETIF_MSG_LINK, "Setting 100M force\n");
9364         }
9365         if ((phy->req_line_speed == SPEED_10) &&
9366             (phy->supported &
9367              (SUPPORTED_10baseT_Half |
9368               SUPPORTED_10baseT_Full))) {
9369                 /* Enabled AUTO-MDIX when autoneg is disabled */
9370                 bnx2x_cl45_write(bp, phy,
9371                                  MDIO_AN_DEVAD, MDIO_AN_REG_8481_AUX_CTRL,
9372                                  (1<<15 | 1<<9 | 7<<0));
9373                 DP(NETIF_MSG_LINK, "Setting 10M force\n");
9374         }
9375
9376         bnx2x_cl45_write(bp, phy,
9377                          MDIO_AN_DEVAD, MDIO_AN_REG_8481_LEGACY_AN_ADV,
9378                          an_10_100_val);
9379
9380         if (phy->req_duplex == DUPLEX_FULL)
9381                 autoneg_val |= (1<<8);
9382
9383         /*
9384          * Always write this if this is not 84833.
9385          * For 84833, write it only when it's a forced speed.
9386          */
9387         if ((phy->type != PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM84833) ||
9388                 ((autoneg_val & (1<<12)) == 0))
9389                 bnx2x_cl45_write(bp, phy,
9390                          MDIO_AN_DEVAD,
9391                          MDIO_AN_REG_8481_LEGACY_MII_CTRL, autoneg_val);
9392
9393         if (((phy->req_line_speed == SPEED_AUTO_NEG) &&
9394             (phy->speed_cap_mask &
9395              PORT_HW_CFG_SPEED_CAPABILITY_D0_10G)) ||
9396                 (phy->req_line_speed == SPEED_10000)) {
9397                         DP(NETIF_MSG_LINK, "Advertising 10G\n");
9398                         /* Restart autoneg for 10G*/
9399
9400                         bnx2x_cl45_write(bp, phy,
9401                                  MDIO_AN_DEVAD, MDIO_AN_REG_CTRL,
9402                                  0x3200);
9403         } else
9404                 bnx2x_cl45_write(bp, phy,
9405                                  MDIO_AN_DEVAD,
9406                                  MDIO_AN_REG_8481_10GBASE_T_AN_CTRL,
9407                                  1);
9408
9409         /* Save spirom version */
9410         bnx2x_save_848xx_spirom_version(phy, params);
9411
9412         phy->req_line_speed = tmp_req_line_speed;
9413
9414         return 0;
9415 }
9416
9417 static int bnx2x_8481_config_init(struct bnx2x_phy *phy,
9418                                   struct link_params *params,
9419                                   struct link_vars *vars)
9420 {
9421         struct bnx2x *bp = params->bp;
9422         /* Restore normal power mode*/
9423         bnx2x_set_gpio(bp, MISC_REGISTERS_GPIO_2,
9424                        MISC_REGISTERS_GPIO_OUTPUT_HIGH, params->port);
9425
9426         /* HW reset */
9427         bnx2x_ext_phy_hw_reset(bp, params->port);
9428         bnx2x_wait_reset_complete(bp, phy, params);
9429
9430         bnx2x_cl45_write(bp, phy, MDIO_PMA_DEVAD, MDIO_PMA_REG_CTRL, 1<<15);
9431         return bnx2x_848xx_cmn_config_init(phy, params, vars);
9432 }
9433
9434
9435 #define PHY84833_HDSHK_WAIT 300
9436 static int bnx2x_84833_pair_swap_cfg(struct bnx2x_phy *phy,
9437                                    struct link_params *params,
9438                                    struct link_vars *vars)
9439 {
9440         u32 idx;
9441         u32 pair_swap;
9442         u16 val;
9443         u16 data;
9444         struct bnx2x *bp = params->bp;
9445         /* Do pair swap */
9446
9447         /* Check for configuration. */
9448         pair_swap = REG_RD(bp, params->shmem_base +
9449                            offsetof(struct shmem_region,
9450                         dev_info.port_hw_config[params->port].xgbt_phy_cfg)) &
9451                 PORT_HW_CFG_RJ45_PAIR_SWAP_MASK;
9452
9453         if (pair_swap == 0)
9454                 return 0;
9455
9456         data = (u16)pair_swap;
9457
9458         /* Write CMD_OPEN_OVERRIDE to STATUS reg */
9459         bnx2x_cl45_write(bp, phy, MDIO_CTL_DEVAD,
9460                         MDIO_84833_TOP_CFG_SCRATCH_REG2,
9461                         PHY84833_CMD_OPEN_OVERRIDE);
9462         for (idx = 0; idx < PHY84833_HDSHK_WAIT; idx++) {
9463                 bnx2x_cl45_read(bp, phy, MDIO_CTL_DEVAD,
9464                                 MDIO_84833_TOP_CFG_SCRATCH_REG2, &val);
9465                 if (val == PHY84833_CMD_OPEN_FOR_CMDS)
9466                         break;
9467                 msleep(1);
9468         }
9469         if (idx >= PHY84833_HDSHK_WAIT) {
9470                 DP(NETIF_MSG_LINK, "Pairswap: FW not ready.\n");
9471                 return -EINVAL;
9472         }
9473
9474         bnx2x_cl45_write(bp, phy, MDIO_CTL_DEVAD,
9475                         MDIO_84833_TOP_CFG_SCRATCH_REG4,
9476                         data);
9477         /* Issue pair swap command */
9478         bnx2x_cl45_write(bp, phy, MDIO_CTL_DEVAD,
9479                         MDIO_84833_TOP_CFG_SCRATCH_REG0,
9480                         PHY84833_DIAG_CMD_PAIR_SWAP_CHANGE);
9481         for (idx = 0; idx < PHY84833_HDSHK_WAIT; idx++) {
9482                 bnx2x_cl45_read(bp, phy, MDIO_CTL_DEVAD,
9483                                 MDIO_84833_TOP_CFG_SCRATCH_REG2, &val);
9484                 if ((val == PHY84833_CMD_COMPLETE_PASS) ||
9485                         (val == PHY84833_CMD_COMPLETE_ERROR))
9486                         break;
9487                 msleep(1);
9488         }
9489         if ((idx >= PHY84833_HDSHK_WAIT) ||
9490                 (val == PHY84833_CMD_COMPLETE_ERROR)) {
9491                 DP(NETIF_MSG_LINK, "Pairswap: override failed.\n");
9492                 return -EINVAL;
9493         }
9494         bnx2x_cl45_write(bp, phy, MDIO_CTL_DEVAD,
9495                         MDIO_84833_TOP_CFG_SCRATCH_REG2,
9496                         PHY84833_CMD_CLEAR_COMPLETE);
9497         DP(NETIF_MSG_LINK, "Pairswap OK, val=0x%x\n", data);
9498         return 0;
9499 }
9500
9501
9502 static u8 bnx2x_84833_get_reset_gpios(struct bnx2x *bp,
9503                                       u32 shmem_base_path[],
9504                                       u32 chip_id)
9505 {
9506         u32 reset_pin[2];
9507         u32 idx;
9508         u8 reset_gpios;
9509         if (CHIP_IS_E3(bp)) {
9510                 /* Assume that these will be GPIOs, not EPIOs. */
9511                 for (idx = 0; idx < 2; idx++) {
9512                         /* Map config param to register bit. */
9513                         reset_pin[idx] = REG_RD(bp, shmem_base_path[idx] +
9514                                 offsetof(struct shmem_region,
9515                                 dev_info.port_hw_config[0].e3_cmn_pin_cfg));
9516                         reset_pin[idx] = (reset_pin[idx] &
9517                                 PORT_HW_CFG_E3_PHY_RESET_MASK) >>
9518                                 PORT_HW_CFG_E3_PHY_RESET_SHIFT;
9519                         reset_pin[idx] -= PIN_CFG_GPIO0_P0;
9520                         reset_pin[idx] = (1 << reset_pin[idx]);
9521                 }
9522                 reset_gpios = (u8)(reset_pin[0] | reset_pin[1]);
9523         } else {
9524                 /* E2, look from diff place of shmem. */
9525                 for (idx = 0; idx < 2; idx++) {
9526                         reset_pin[idx] = REG_RD(bp, shmem_base_path[idx] +
9527                                 offsetof(struct shmem_region,
9528                                 dev_info.port_hw_config[0].default_cfg));
9529                         reset_pin[idx] &= PORT_HW_CFG_EXT_PHY_GPIO_RST_MASK;
9530                         reset_pin[idx] -= PORT_HW_CFG_EXT_PHY_GPIO_RST_GPIO0_P0;
9531                         reset_pin[idx] >>= PORT_HW_CFG_EXT_PHY_GPIO_RST_SHIFT;
9532                         reset_pin[idx] = (1 << reset_pin[idx]);
9533                 }
9534                 reset_gpios = (u8)(reset_pin[0] | reset_pin[1]);
9535         }
9536
9537         return reset_gpios;
9538 }
9539
9540 static int bnx2x_84833_hw_reset_phy(struct bnx2x_phy *phy,
9541                                 struct link_params *params)
9542 {
9543         struct bnx2x *bp = params->bp;
9544         u8 reset_gpios;
9545         u32 other_shmem_base_addr = REG_RD(bp, params->shmem2_base +
9546                                 offsetof(struct shmem2_region,
9547                                 other_shmem_base_addr));
9548
9549         u32 shmem_base_path[2];
9550         shmem_base_path[0] = params->shmem_base;
9551         shmem_base_path[1] = other_shmem_base_addr;
9552
9553         reset_gpios = bnx2x_84833_get_reset_gpios(bp, shmem_base_path,
9554                                                   params->chip_id);
9555
9556         bnx2x_set_mult_gpio(bp, reset_gpios, MISC_REGISTERS_GPIO_OUTPUT_LOW);
9557         udelay(10);
9558         DP(NETIF_MSG_LINK, "84833 hw reset on pin values 0x%x\n",
9559                 reset_gpios);
9560
9561         return 0;
9562 }
9563
9564 static int bnx2x_84833_common_init_phy(struct bnx2x *bp,
9565                                                 u32 shmem_base_path[],
9566                                                 u32 chip_id)
9567 {
9568         u8 reset_gpios;
9569
9570         reset_gpios = bnx2x_84833_get_reset_gpios(bp, shmem_base_path, chip_id);
9571
9572         bnx2x_set_mult_gpio(bp, reset_gpios, MISC_REGISTERS_GPIO_OUTPUT_LOW);
9573         udelay(10);
9574         bnx2x_set_mult_gpio(bp, reset_gpios, MISC_REGISTERS_GPIO_OUTPUT_HIGH);
9575         msleep(800);
9576         DP(NETIF_MSG_LINK, "84833 reset pulse on pin values 0x%x\n",
9577                 reset_gpios);
9578
9579         return 0;
9580 }
9581
9582 #define PHY84833_CONSTANT_LATENCY 1193
9583 static int bnx2x_848x3_config_init(struct bnx2x_phy *phy,
9584                                    struct link_params *params,
9585                                    struct link_vars *vars)
9586 {
9587         struct bnx2x *bp = params->bp;
9588         u8 port, initialize = 1;
9589         u16 val;
9590         u16 temp;
9591         u32 actual_phy_selection, cms_enable, idx;
9592         int rc = 0;
9593
9594         msleep(1);
9595
9596         if (!(CHIP_IS_E1(bp)))
9597                 port = BP_PATH(bp);
9598         else
9599                 port = params->port;
9600
9601         if (phy->type == PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM84823) {
9602                 bnx2x_set_gpio(bp, MISC_REGISTERS_GPIO_3,
9603                                MISC_REGISTERS_GPIO_OUTPUT_HIGH,
9604                                port);
9605         } else {
9606                 /* MDIO reset */
9607                 bnx2x_cl45_write(bp, phy,
9608                                 MDIO_PMA_DEVAD,
9609                                 MDIO_PMA_REG_CTRL, 0x8000);
9610                 /* Bring PHY out of super isolate mode */
9611                 bnx2x_cl45_read(bp, phy,
9612                                 MDIO_CTL_DEVAD,
9613                                 MDIO_84833_TOP_CFG_XGPHY_STRAP1, &val);
9614                 val &= ~MDIO_84833_SUPER_ISOLATE;
9615                 bnx2x_cl45_write(bp, phy,
9616                                 MDIO_CTL_DEVAD,
9617                                 MDIO_84833_TOP_CFG_XGPHY_STRAP1, val);
9618         }
9619
9620         bnx2x_wait_reset_complete(bp, phy, params);
9621
9622         /* Wait for GPHY to come out of reset */
9623         msleep(50);
9624
9625         if (phy->type == PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM84833)
9626                 bnx2x_84833_pair_swap_cfg(phy, params, vars);
9627
9628         /*
9629          * BCM84823 requires that XGXS links up first @ 10G for normal behavior
9630          */
9631         temp = vars->line_speed;
9632         vars->line_speed = SPEED_10000;
9633         bnx2x_set_autoneg(&params->phy[INT_PHY], params, vars, 0);
9634         bnx2x_program_serdes(&params->phy[INT_PHY], params, vars);
9635         vars->line_speed = temp;
9636
9637         /* Set dual-media configuration according to configuration */
9638
9639         bnx2x_cl45_read(bp, phy, MDIO_CTL_DEVAD,
9640                         MDIO_CTL_REG_84823_MEDIA, &val);
9641         val &= ~(MDIO_CTL_REG_84823_MEDIA_MAC_MASK |
9642                  MDIO_CTL_REG_84823_MEDIA_LINE_MASK |
9643                  MDIO_CTL_REG_84823_MEDIA_COPPER_CORE_DOWN |
9644                  MDIO_CTL_REG_84823_MEDIA_PRIORITY_MASK |
9645                  MDIO_CTL_REG_84823_MEDIA_FIBER_1G);
9646
9647         if (CHIP_IS_E3(bp)) {
9648                 val &= ~(MDIO_CTL_REG_84823_MEDIA_MAC_MASK |
9649                          MDIO_CTL_REG_84823_MEDIA_LINE_MASK);
9650         } else {
9651                 val |= (MDIO_CTL_REG_84823_CTRL_MAC_XFI |
9652                         MDIO_CTL_REG_84823_MEDIA_LINE_XAUI_L);
9653         }
9654
9655         actual_phy_selection = bnx2x_phy_selection(params);
9656
9657         switch (actual_phy_selection) {
9658         case PORT_HW_CFG_PHY_SELECTION_HARDWARE_DEFAULT:
9659                 /* Do nothing. Essentially this is like the priority copper */
9660                 break;
9661         case PORT_HW_CFG_PHY_SELECTION_FIRST_PHY_PRIORITY:
9662                 val |= MDIO_CTL_REG_84823_MEDIA_PRIORITY_COPPER;
9663                 break;
9664         case PORT_HW_CFG_PHY_SELECTION_SECOND_PHY_PRIORITY:
9665                 val |= MDIO_CTL_REG_84823_MEDIA_PRIORITY_FIBER;
9666                 break;
9667         case PORT_HW_CFG_PHY_SELECTION_FIRST_PHY:
9668                 /* Do nothing here. The first PHY won't be initialized at all */
9669                 break;
9670         case PORT_HW_CFG_PHY_SELECTION_SECOND_PHY:
9671                 val |= MDIO_CTL_REG_84823_MEDIA_COPPER_CORE_DOWN;
9672                 initialize = 0;
9673                 break;
9674         }
9675         if (params->phy[EXT_PHY2].req_line_speed == SPEED_1000)
9676                 val |= MDIO_CTL_REG_84823_MEDIA_FIBER_1G;
9677
9678         bnx2x_cl45_write(bp, phy, MDIO_CTL_DEVAD,
9679                          MDIO_CTL_REG_84823_MEDIA, val);
9680         DP(NETIF_MSG_LINK, "Multi_phy config = 0x%x, Media control = 0x%x\n",
9681                    params->multi_phy_config, val);
9682
9683         /* AutogrEEEn */
9684         if (params->feature_config_flags &
9685                 FEATURE_CONFIG_AUTOGREEEN_ENABLED) {
9686                 /* Ensure that f/w is ready */
9687                 for (idx = 0; idx < PHY84833_HDSHK_WAIT; idx++) {
9688                         bnx2x_cl45_read(bp, phy, MDIO_CTL_DEVAD,
9689                                         MDIO_84833_TOP_CFG_SCRATCH_REG2, &val);
9690                         if (val == PHY84833_CMD_OPEN_FOR_CMDS)
9691                                 break;
9692                         usleep_range(1000, 1000);
9693                 }
9694                 if (idx >= PHY84833_HDSHK_WAIT) {
9695                         DP(NETIF_MSG_LINK, "AutogrEEEn: FW not ready.\n");
9696                         return -EINVAL;
9697                 }
9698
9699                 /* Select EEE mode */
9700                 bnx2x_cl45_write(bp, phy, MDIO_CTL_DEVAD,
9701                                 MDIO_84833_TOP_CFG_SCRATCH_REG3,
9702                                 0x2);
9703
9704                 /* Set Idle and Latency */
9705                 bnx2x_cl45_write(bp, phy, MDIO_CTL_DEVAD,
9706                                 MDIO_84833_TOP_CFG_SCRATCH_REG4,
9707                                 PHY84833_CONSTANT_LATENCY + 1);
9708
9709                 bnx2x_cl45_write(bp, phy, MDIO_CTL_DEVAD,
9710                                 MDIO_84833_TOP_CFG_DATA3_REG,
9711                                 PHY84833_CONSTANT_LATENCY + 1);
9712
9713                 bnx2x_cl45_write(bp, phy, MDIO_CTL_DEVAD,
9714                                 MDIO_84833_TOP_CFG_DATA4_REG,
9715                                 PHY84833_CONSTANT_LATENCY);
9716
9717                 /* Send EEE instruction to command register */
9718                 bnx2x_cl45_write(bp, phy, MDIO_CTL_DEVAD,
9719                                 MDIO_84833_TOP_CFG_SCRATCH_REG0,
9720                                 PHY84833_DIAG_CMD_SET_EEE_MODE);
9721
9722                 /* Ensure that the command has completed */
9723                 for (idx = 0; idx < PHY84833_HDSHK_WAIT; idx++) {
9724                         bnx2x_cl45_read(bp, phy, MDIO_CTL_DEVAD,
9725                                         MDIO_84833_TOP_CFG_SCRATCH_REG2, &val);
9726                         if ((val == PHY84833_CMD_COMPLETE_PASS) ||
9727                                 (val == PHY84833_CMD_COMPLETE_ERROR))
9728                                 break;
9729                         usleep_range(1000, 1000);
9730                 }
9731                 if ((idx >= PHY84833_HDSHK_WAIT) ||
9732                         (val == PHY84833_CMD_COMPLETE_ERROR)) {
9733                         DP(NETIF_MSG_LINK, "AutogrEEEn: command failed.\n");
9734                         return -EINVAL;
9735                 }
9736
9737                 /* Reset command handler */
9738                 bnx2x_cl45_write(bp, phy, MDIO_CTL_DEVAD,
9739                             MDIO_84833_TOP_CFG_SCRATCH_REG2,
9740                             PHY84833_CMD_CLEAR_COMPLETE);
9741         }
9742
9743         if (initialize)
9744                 rc = bnx2x_848xx_cmn_config_init(phy, params, vars);
9745         else
9746                 bnx2x_save_848xx_spirom_version(phy, params);
9747         /* 84833 PHY has a better feature and doesn't need to support this. */
9748         if (phy->type == PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM84823) {
9749                 cms_enable = REG_RD(bp, params->shmem_base +
9750                         offsetof(struct shmem_region,
9751                         dev_info.port_hw_config[params->port].default_cfg)) &
9752                         PORT_HW_CFG_ENABLE_CMS_MASK;
9753
9754                 bnx2x_cl45_read(bp, phy, MDIO_CTL_DEVAD,
9755                                 MDIO_CTL_REG_84823_USER_CTRL_REG, &val);
9756                 if (cms_enable)
9757                         val |= MDIO_CTL_REG_84823_USER_CTRL_CMS;
9758                 else
9759                         val &= ~MDIO_CTL_REG_84823_USER_CTRL_CMS;
9760                 bnx2x_cl45_write(bp, phy, MDIO_CTL_DEVAD,
9761                                  MDIO_CTL_REG_84823_USER_CTRL_REG, val);
9762         }
9763
9764         return rc;
9765 }
9766
9767 static u8 bnx2x_848xx_read_status(struct bnx2x_phy *phy,
9768                                   struct link_params *params,
9769                                   struct link_vars *vars)
9770 {
9771         struct bnx2x *bp = params->bp;
9772         u16 val, val1, val2;
9773         u8 link_up = 0;
9774
9775
9776         /* Check 10G-BaseT link status */
9777         /* Check PMD signal ok */
9778         bnx2x_cl45_read(bp, phy,
9779                         MDIO_AN_DEVAD, 0xFFFA, &val1);
9780         bnx2x_cl45_read(bp, phy,
9781                         MDIO_PMA_DEVAD, MDIO_PMA_REG_8481_PMD_SIGNAL,
9782                         &val2);
9783         DP(NETIF_MSG_LINK, "BCM848xx: PMD_SIGNAL 1.a811 = 0x%x\n", val2);
9784
9785         /* Check link 10G */
9786         if (val2 & (1<<11)) {
9787                 vars->line_speed = SPEED_10000;
9788                 vars->duplex = DUPLEX_FULL;
9789                 link_up = 1;
9790                 bnx2x_ext_phy_10G_an_resolve(bp, phy, vars);
9791         } else { /* Check Legacy speed link */
9792                 u16 legacy_status, legacy_speed;
9793
9794                 /* Enable expansion register 0x42 (Operation mode status) */
9795                 bnx2x_cl45_write(bp, phy,
9796                                  MDIO_AN_DEVAD,
9797                                  MDIO_AN_REG_8481_EXPANSION_REG_ACCESS, 0xf42);
9798
9799                 /* Get legacy speed operation status */
9800                 bnx2x_cl45_read(bp, phy,
9801                                 MDIO_AN_DEVAD,
9802                                 MDIO_AN_REG_8481_EXPANSION_REG_RD_RW,
9803                                 &legacy_status);
9804
9805                 DP(NETIF_MSG_LINK, "Legacy speed status = 0x%x\n",
9806                    legacy_status);
9807                 link_up = ((legacy_status & (1<<11)) == (1<<11));
9808                 if (link_up) {
9809                         legacy_speed = (legacy_status & (3<<9));
9810                         if (legacy_speed == (0<<9))
9811                                 vars->line_speed = SPEED_10;
9812                         else if (legacy_speed == (1<<9))
9813                                 vars->line_speed = SPEED_100;
9814                         else if (legacy_speed == (2<<9))
9815                                 vars->line_speed = SPEED_1000;
9816                         else /* Should not happen */
9817                                 vars->line_speed = 0;
9818
9819                         if (legacy_status & (1<<8))
9820                                 vars->duplex = DUPLEX_FULL;
9821                         else
9822                                 vars->duplex = DUPLEX_HALF;
9823
9824                         DP(NETIF_MSG_LINK,
9825                            "Link is up in %dMbps, is_duplex_full= %d\n",
9826                            vars->line_speed,
9827                            (vars->duplex == DUPLEX_FULL));
9828                         /* Check legacy speed AN resolution */
9829                         bnx2x_cl45_read(bp, phy,
9830                                         MDIO_AN_DEVAD,
9831                                         MDIO_AN_REG_8481_LEGACY_MII_STATUS,
9832                                         &val);
9833                         if (val & (1<<5))
9834                                 vars->link_status |=
9835                                         LINK_STATUS_AUTO_NEGOTIATE_COMPLETE;
9836                         bnx2x_cl45_read(bp, phy,
9837                                         MDIO_AN_DEVAD,
9838                                         MDIO_AN_REG_8481_LEGACY_AN_EXPANSION,
9839                                         &val);
9840                         if ((val & (1<<0)) == 0)
9841                                 vars->link_status |=
9842                                         LINK_STATUS_PARALLEL_DETECTION_USED;
9843                 }
9844         }
9845         if (link_up) {
9846                 DP(NETIF_MSG_LINK, "BCM84823: link speed is %d\n",
9847                            vars->line_speed);
9848                 bnx2x_ext_phy_resolve_fc(phy, params, vars);
9849         }
9850
9851         return link_up;
9852 }
9853
9854
9855 static int bnx2x_848xx_format_ver(u32 raw_ver, u8 *str, u16 *len)
9856 {
9857         int status = 0;
9858         u32 spirom_ver;
9859         spirom_ver = ((raw_ver & 0xF80) >> 7) << 16 | (raw_ver & 0x7F);
9860         status = bnx2x_format_ver(spirom_ver, str, len);
9861         return status;
9862 }
9863
9864 static void bnx2x_8481_hw_reset(struct bnx2x_phy *phy,
9865                                 struct link_params *params)
9866 {
9867         bnx2x_set_gpio(params->bp, MISC_REGISTERS_GPIO_1,
9868                        MISC_REGISTERS_GPIO_OUTPUT_LOW, 0);
9869         bnx2x_set_gpio(params->bp, MISC_REGISTERS_GPIO_1,
9870                        MISC_REGISTERS_GPIO_OUTPUT_LOW, 1);
9871 }
9872
9873 static void bnx2x_8481_link_reset(struct bnx2x_phy *phy,
9874                                         struct link_params *params)
9875 {
9876         bnx2x_cl45_write(params->bp, phy,
9877                          MDIO_AN_DEVAD, MDIO_AN_REG_CTRL, 0x0000);
9878         bnx2x_cl45_write(params->bp, phy,
9879                          MDIO_PMA_DEVAD, MDIO_PMA_REG_CTRL, 1);
9880 }
9881
9882 static void bnx2x_848x3_link_reset(struct bnx2x_phy *phy,
9883                                    struct link_params *params)
9884 {
9885         struct bnx2x *bp = params->bp;
9886         u8 port;
9887         u16 val16;
9888
9889         if (!(CHIP_IS_E1(bp)))
9890                 port = BP_PATH(bp);
9891         else
9892                 port = params->port;
9893
9894         if (phy->type == PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM84823) {
9895                 bnx2x_set_gpio(bp, MISC_REGISTERS_GPIO_3,
9896                                MISC_REGISTERS_GPIO_OUTPUT_LOW,
9897                                port);
9898         } else {
9899                 bnx2x_cl45_read(bp, phy,
9900                                 MDIO_CTL_DEVAD,
9901                                 0x400f, &val16);
9902                 bnx2x_cl45_write(bp, phy,
9903                                 MDIO_PMA_DEVAD,
9904                                 MDIO_PMA_REG_CTRL, 0x800);
9905         }
9906 }
9907
9908 static void bnx2x_848xx_set_link_led(struct bnx2x_phy *phy,
9909                                      struct link_params *params, u8 mode)
9910 {
9911         struct bnx2x *bp = params->bp;
9912         u16 val;
9913         u8 port;
9914
9915         if (!(CHIP_IS_E1(bp)))
9916                 port = BP_PATH(bp);
9917         else
9918                 port = params->port;
9919
9920         switch (mode) {
9921         case LED_MODE_OFF:
9922
9923                 DP(NETIF_MSG_LINK, "Port 0x%x: LED MODE OFF\n", port);
9924
9925                 if ((params->hw_led_mode << SHARED_HW_CFG_LED_MODE_SHIFT) ==
9926                     SHARED_HW_CFG_LED_EXTPHY1) {
9927
9928                         /* Set LED masks */
9929                         bnx2x_cl45_write(bp, phy,
9930                                         MDIO_PMA_DEVAD,
9931                                         MDIO_PMA_REG_8481_LED1_MASK,
9932                                         0x0);
9933
9934                         bnx2x_cl45_write(bp, phy,
9935                                         MDIO_PMA_DEVAD,
9936                                         MDIO_PMA_REG_8481_LED2_MASK,
9937                                         0x0);
9938
9939                         bnx2x_cl45_write(bp, phy,
9940                                         MDIO_PMA_DEVAD,
9941                                         MDIO_PMA_REG_8481_LED3_MASK,
9942                                         0x0);
9943
9944                         bnx2x_cl45_write(bp, phy,
9945                                         MDIO_PMA_DEVAD,
9946                                         MDIO_PMA_REG_8481_LED5_MASK,
9947                                         0x0);
9948
9949                 } else {
9950                         bnx2x_cl45_write(bp, phy,
9951                                          MDIO_PMA_DEVAD,
9952                                          MDIO_PMA_REG_8481_LED1_MASK,
9953                                          0x0);
9954                 }
9955                 break;
9956         case LED_MODE_FRONT_PANEL_OFF:
9957
9958                 DP(NETIF_MSG_LINK, "Port 0x%x: LED MODE FRONT PANEL OFF\n",
9959                    port);
9960
9961                 if ((params->hw_led_mode << SHARED_HW_CFG_LED_MODE_SHIFT) ==
9962                     SHARED_HW_CFG_LED_EXTPHY1) {
9963
9964                         /* Set LED masks */
9965                         bnx2x_cl45_write(bp, phy,
9966                                          MDIO_PMA_DEVAD,
9967                                          MDIO_PMA_REG_8481_LED1_MASK,
9968                                          0x0);
9969
9970                         bnx2x_cl45_write(bp, phy,
9971                                          MDIO_PMA_DEVAD,
9972                                          MDIO_PMA_REG_8481_LED2_MASK,
9973                                          0x0);
9974
9975                         bnx2x_cl45_write(bp, phy,
9976                                          MDIO_PMA_DEVAD,
9977                                          MDIO_PMA_REG_8481_LED3_MASK,
9978                                          0x0);
9979
9980                         bnx2x_cl45_write(bp, phy,
9981                                          MDIO_PMA_DEVAD,
9982                                          MDIO_PMA_REG_8481_LED5_MASK,
9983                                          0x20);
9984
9985                 } else {
9986                         bnx2x_cl45_write(bp, phy,
9987                                          MDIO_PMA_DEVAD,
9988                                          MDIO_PMA_REG_8481_LED1_MASK,
9989                                          0x0);
9990                 }
9991                 break;
9992         case LED_MODE_ON:
9993
9994                 DP(NETIF_MSG_LINK, "Port 0x%x: LED MODE ON\n", port);
9995
9996                 if ((params->hw_led_mode << SHARED_HW_CFG_LED_MODE_SHIFT) ==
9997                     SHARED_HW_CFG_LED_EXTPHY1) {
9998                         /* Set control reg */
9999                         bnx2x_cl45_read(bp, phy,
10000                                         MDIO_PMA_DEVAD,
10001                                         MDIO_PMA_REG_8481_LINK_SIGNAL,
10002                                         &val);
10003                         val &= 0x8000;
10004                         val |= 0x2492;
10005
10006                         bnx2x_cl45_write(bp, phy,
10007                                          MDIO_PMA_DEVAD,
10008                                          MDIO_PMA_REG_8481_LINK_SIGNAL,
10009                                          val);
10010
10011                         /* Set LED masks */
10012                         bnx2x_cl45_write(bp, phy,
10013                                          MDIO_PMA_DEVAD,
10014                                          MDIO_PMA_REG_8481_LED1_MASK,
10015                                          0x0);
10016
10017                         bnx2x_cl45_write(bp, phy,
10018                                          MDIO_PMA_DEVAD,
10019                                          MDIO_PMA_REG_8481_LED2_MASK,
10020                                          0x20);
10021
10022                         bnx2x_cl45_write(bp, phy,
10023                                          MDIO_PMA_DEVAD,
10024                                          MDIO_PMA_REG_8481_LED3_MASK,
10025                                          0x20);
10026
10027                         bnx2x_cl45_write(bp, phy,
10028                                          MDIO_PMA_DEVAD,
10029                                          MDIO_PMA_REG_8481_LED5_MASK,
10030                                          0x0);
10031                 } else {
10032                         bnx2x_cl45_write(bp, phy,
10033                                          MDIO_PMA_DEVAD,
10034                                          MDIO_PMA_REG_8481_LED1_MASK,
10035                                          0x20);
10036                 }
10037                 break;
10038
10039         case LED_MODE_OPER:
10040
10041                 DP(NETIF_MSG_LINK, "Port 0x%x: LED MODE OPER\n", port);
10042
10043                 if ((params->hw_led_mode << SHARED_HW_CFG_LED_MODE_SHIFT) ==
10044                     SHARED_HW_CFG_LED_EXTPHY1) {
10045
10046                         /* Set control reg */
10047                         bnx2x_cl45_read(bp, phy,
10048                                         MDIO_PMA_DEVAD,
10049                                         MDIO_PMA_REG_8481_LINK_SIGNAL,
10050                                         &val);
10051
10052                         if (!((val &
10053                                MDIO_PMA_REG_8481_LINK_SIGNAL_LED4_ENABLE_MASK)
10054                           >> MDIO_PMA_REG_8481_LINK_SIGNAL_LED4_ENABLE_SHIFT)) {
10055                                 DP(NETIF_MSG_LINK, "Setting LINK_SIGNAL\n");
10056                                 bnx2x_cl45_write(bp, phy,
10057                                                  MDIO_PMA_DEVAD,
10058                                                  MDIO_PMA_REG_8481_LINK_SIGNAL,
10059                                                  0xa492);
10060                         }
10061
10062                         /* Set LED masks */
10063                         bnx2x_cl45_write(bp, phy,
10064                                          MDIO_PMA_DEVAD,
10065                                          MDIO_PMA_REG_8481_LED1_MASK,
10066                                          0x10);
10067
10068                         bnx2x_cl45_write(bp, phy,
10069                                          MDIO_PMA_DEVAD,
10070                                          MDIO_PMA_REG_8481_LED2_MASK,
10071                                          0x80);
10072
10073                         bnx2x_cl45_write(bp, phy,
10074                                          MDIO_PMA_DEVAD,
10075                                          MDIO_PMA_REG_8481_LED3_MASK,
10076                                          0x98);
10077
10078                         bnx2x_cl45_write(bp, phy,
10079                                          MDIO_PMA_DEVAD,
10080                                          MDIO_PMA_REG_8481_LED5_MASK,
10081                                          0x40);
10082
10083                 } else {
10084                         bnx2x_cl45_write(bp, phy,
10085                                          MDIO_PMA_DEVAD,
10086                                          MDIO_PMA_REG_8481_LED1_MASK,
10087                                          0x80);
10088
10089                         /* Tell LED3 to blink on source */
10090                         bnx2x_cl45_read(bp, phy,
10091                                         MDIO_PMA_DEVAD,
10092                                         MDIO_PMA_REG_8481_LINK_SIGNAL,
10093                                         &val);
10094                         val &= ~(7<<6);
10095                         val |= (1<<6); /* A83B[8:6]= 1 */
10096                         bnx2x_cl45_write(bp, phy,
10097                                          MDIO_PMA_DEVAD,
10098                                          MDIO_PMA_REG_8481_LINK_SIGNAL,
10099                                          val);
10100                 }
10101                 break;
10102         }
10103
10104         /*
10105          * This is a workaround for E3+84833 until autoneg
10106          * restart is fixed in f/w
10107          */
10108         if (CHIP_IS_E3(bp)) {
10109                 bnx2x_cl45_read(bp, phy, MDIO_WC_DEVAD,
10110                                 MDIO_WC_REG_GP2_STATUS_GP_2_1, &val);
10111         }
10112 }
10113
10114 /******************************************************************/
10115 /*                      54618SE PHY SECTION                       */
10116 /******************************************************************/
10117 static int bnx2x_54618se_config_init(struct bnx2x_phy *phy,
10118                                                struct link_params *params,
10119                                                struct link_vars *vars)
10120 {
10121         struct bnx2x *bp = params->bp;
10122         u8 port;
10123         u16 autoneg_val, an_1000_val, an_10_100_val, fc_val, temp;
10124         u32 cfg_pin;
10125
10126         DP(NETIF_MSG_LINK, "54618SE cfg init\n");
10127         usleep_range(1000, 1000);
10128
10129         /* This works with E3 only, no need to check the chip
10130            before determining the port. */
10131         port = params->port;
10132
10133         cfg_pin = (REG_RD(bp, params->shmem_base +
10134                         offsetof(struct shmem_region,
10135                         dev_info.port_hw_config[port].e3_cmn_pin_cfg)) &
10136                         PORT_HW_CFG_E3_PHY_RESET_MASK) >>
10137                         PORT_HW_CFG_E3_PHY_RESET_SHIFT;
10138
10139         /* Drive pin high to bring the GPHY out of reset. */
10140         bnx2x_set_cfg_pin(bp, cfg_pin, 1);
10141
10142         /* wait for GPHY to reset */
10143         msleep(50);
10144
10145         /* reset phy */
10146         bnx2x_cl22_write(bp, phy,
10147                          MDIO_PMA_REG_CTRL, 0x8000);
10148         bnx2x_wait_reset_complete(bp, phy, params);
10149
10150         /*wait for GPHY to reset */
10151         msleep(50);
10152
10153         /* Configure LED4: set to INTR (0x6). */
10154         /* Accessing shadow register 0xe. */
10155         bnx2x_cl22_write(bp, phy,
10156                         MDIO_REG_GPHY_SHADOW,
10157                         MDIO_REG_GPHY_SHADOW_LED_SEL2);
10158         bnx2x_cl22_read(bp, phy,
10159                         MDIO_REG_GPHY_SHADOW,
10160                         &temp);
10161         temp &= ~(0xf << 4);
10162         temp |= (0x6 << 4);
10163         bnx2x_cl22_write(bp, phy,
10164                         MDIO_REG_GPHY_SHADOW,
10165                         MDIO_REG_GPHY_SHADOW_WR_ENA | temp);
10166         /* Configure INTR based on link status change. */
10167         bnx2x_cl22_write(bp, phy,
10168                         MDIO_REG_INTR_MASK,
10169                         ~MDIO_REG_INTR_MASK_LINK_STATUS);
10170
10171         /* Flip the signal detect polarity (set 0x1c.0x1e[8]). */
10172         bnx2x_cl22_write(bp, phy,
10173                         MDIO_REG_GPHY_SHADOW,
10174                         MDIO_REG_GPHY_SHADOW_AUTO_DET_MED);
10175         bnx2x_cl22_read(bp, phy,
10176                         MDIO_REG_GPHY_SHADOW,
10177                         &temp);
10178         temp |= MDIO_REG_GPHY_SHADOW_INVERT_FIB_SD;
10179         bnx2x_cl22_write(bp, phy,
10180                         MDIO_REG_GPHY_SHADOW,
10181                         MDIO_REG_GPHY_SHADOW_WR_ENA | temp);
10182
10183         /* Set up fc */
10184         /* Please refer to Table 28B-3 of 802.3ab-1999 spec. */
10185         bnx2x_calc_ieee_aneg_adv(phy, params, &vars->ieee_fc);
10186         fc_val = 0;
10187         if ((vars->ieee_fc & MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_ASYMMETRIC) ==
10188                         MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_ASYMMETRIC)
10189                 fc_val |= MDIO_AN_REG_ADV_PAUSE_ASYMMETRIC;
10190
10191         if ((vars->ieee_fc & MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_BOTH) ==
10192                         MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_BOTH)
10193                 fc_val |= MDIO_AN_REG_ADV_PAUSE_PAUSE;
10194
10195         /* read all advertisement */
10196         bnx2x_cl22_read(bp, phy,
10197                         0x09,
10198                         &an_1000_val);
10199
10200         bnx2x_cl22_read(bp, phy,
10201                         0x04,
10202                         &an_10_100_val);
10203
10204         bnx2x_cl22_read(bp, phy,
10205                         MDIO_PMA_REG_CTRL,
10206                         &autoneg_val);
10207
10208         /* Disable forced speed */
10209         autoneg_val &= ~((1<<6) | (1<<8) | (1<<9) | (1<<12) | (1<<13));
10210         an_10_100_val &= ~((1<<5) | (1<<6) | (1<<7) | (1<<8) | (1<<10) |
10211                            (1<<11));
10212
10213         if (((phy->req_line_speed == SPEED_AUTO_NEG) &&
10214                         (phy->speed_cap_mask &
10215                         PORT_HW_CFG_SPEED_CAPABILITY_D0_1G)) ||
10216                         (phy->req_line_speed == SPEED_1000)) {
10217                 an_1000_val |= (1<<8);
10218                 autoneg_val |= (1<<9 | 1<<12);
10219                 if (phy->req_duplex == DUPLEX_FULL)
10220                         an_1000_val |= (1<<9);
10221                 DP(NETIF_MSG_LINK, "Advertising 1G\n");
10222         } else
10223                 an_1000_val &= ~((1<<8) | (1<<9));
10224
10225         bnx2x_cl22_write(bp, phy,
10226                         0x09,
10227                         an_1000_val);
10228         bnx2x_cl22_read(bp, phy,
10229                         0x09,
10230                         &an_1000_val);
10231
10232         /* set 100 speed advertisement */
10233         if (((phy->req_line_speed == SPEED_AUTO_NEG) &&
10234                         (phy->speed_cap_mask &
10235                         (PORT_HW_CFG_SPEED_CAPABILITY_D0_100M_FULL |
10236                         PORT_HW_CFG_SPEED_CAPABILITY_D0_100M_HALF)))) {
10237                 an_10_100_val |= (1<<7);
10238                 /* Enable autoneg and restart autoneg for legacy speeds */
10239                 autoneg_val |= (1<<9 | 1<<12);
10240
10241                 if (phy->req_duplex == DUPLEX_FULL)
10242                         an_10_100_val |= (1<<8);
10243                 DP(NETIF_MSG_LINK, "Advertising 100M\n");
10244         }
10245
10246         /* set 10 speed advertisement */
10247         if (((phy->req_line_speed == SPEED_AUTO_NEG) &&
10248                         (phy->speed_cap_mask &
10249                         (PORT_HW_CFG_SPEED_CAPABILITY_D0_10M_FULL |
10250                         PORT_HW_CFG_SPEED_CAPABILITY_D0_10M_HALF)))) {
10251                 an_10_100_val |= (1<<5);
10252                 autoneg_val |= (1<<9 | 1<<12);
10253                 if (phy->req_duplex == DUPLEX_FULL)
10254                         an_10_100_val |= (1<<6);
10255                 DP(NETIF_MSG_LINK, "Advertising 10M\n");
10256         }
10257
10258         /* Only 10/100 are allowed to work in FORCE mode */
10259         if (phy->req_line_speed == SPEED_100) {
10260                 autoneg_val |= (1<<13);
10261                 /* Enabled AUTO-MDIX when autoneg is disabled */
10262                 bnx2x_cl22_write(bp, phy,
10263                                 0x18,
10264                                 (1<<15 | 1<<9 | 7<<0));
10265                 DP(NETIF_MSG_LINK, "Setting 100M force\n");
10266         }
10267         if (phy->req_line_speed == SPEED_10) {
10268                 /* Enabled AUTO-MDIX when autoneg is disabled */
10269                 bnx2x_cl22_write(bp, phy,
10270                                 0x18,
10271                                 (1<<15 | 1<<9 | 7<<0));
10272                 DP(NETIF_MSG_LINK, "Setting 10M force\n");
10273         }
10274
10275         /* Check if we should turn on Auto-GrEEEn */
10276         bnx2x_cl22_read(bp, phy, MDIO_REG_GPHY_PHYID_LSB, &temp);
10277         if (temp == MDIO_REG_GPHY_ID_54618SE) {
10278                 if (params->feature_config_flags &
10279                     FEATURE_CONFIG_AUTOGREEEN_ENABLED) {
10280                         temp = 6;
10281                         DP(NETIF_MSG_LINK, "Enabling Auto-GrEEEn\n");
10282                 } else {
10283                         temp = 0;
10284                         DP(NETIF_MSG_LINK, "Disabling Auto-GrEEEn\n");
10285                 }
10286                 bnx2x_cl22_write(bp, phy,
10287                                  MDIO_REG_GPHY_CL45_ADDR_REG, MDIO_AN_DEVAD);
10288                 bnx2x_cl22_write(bp, phy,
10289                                  MDIO_REG_GPHY_CL45_DATA_REG,
10290                                  MDIO_REG_GPHY_EEE_ADV);
10291                 bnx2x_cl22_write(bp, phy,
10292                                  MDIO_REG_GPHY_CL45_ADDR_REG,
10293                                  (0x1 << 14) | MDIO_AN_DEVAD);
10294                 bnx2x_cl22_write(bp, phy,
10295                                  MDIO_REG_GPHY_CL45_DATA_REG,
10296                                  temp);
10297         }
10298
10299         bnx2x_cl22_write(bp, phy,
10300                         0x04,
10301                         an_10_100_val | fc_val);
10302
10303         if (phy->req_duplex == DUPLEX_FULL)
10304                 autoneg_val |= (1<<8);
10305
10306         bnx2x_cl22_write(bp, phy,
10307                         MDIO_PMA_REG_CTRL, autoneg_val);
10308
10309         return 0;
10310 }
10311
10312 static void bnx2x_54618se_set_link_led(struct bnx2x_phy *phy,
10313                                        struct link_params *params, u8 mode)
10314 {
10315         struct bnx2x *bp = params->bp;
10316         DP(NETIF_MSG_LINK, "54618SE set link led (mode=%x)\n", mode);
10317         switch (mode) {
10318         case LED_MODE_FRONT_PANEL_OFF:
10319         case LED_MODE_OFF:
10320         case LED_MODE_OPER:
10321         case LED_MODE_ON:
10322         default:
10323                 break;
10324         }
10325         return;
10326 }
10327
10328 static void bnx2x_54618se_link_reset(struct bnx2x_phy *phy,
10329                                      struct link_params *params)
10330 {
10331         struct bnx2x *bp = params->bp;
10332         u32 cfg_pin;
10333         u8 port;
10334
10335         /*
10336          * In case of no EPIO routed to reset the GPHY, put it
10337          * in low power mode.
10338          */
10339         bnx2x_cl22_write(bp, phy, MDIO_PMA_REG_CTRL, 0x800);
10340         /*
10341          * This works with E3 only, no need to check the chip
10342          * before determining the port.
10343          */
10344         port = params->port;
10345         cfg_pin = (REG_RD(bp, params->shmem_base +
10346                         offsetof(struct shmem_region,
10347                         dev_info.port_hw_config[port].e3_cmn_pin_cfg)) &
10348                         PORT_HW_CFG_E3_PHY_RESET_MASK) >>
10349                         PORT_HW_CFG_E3_PHY_RESET_SHIFT;
10350
10351         /* Drive pin low to put GPHY in reset. */
10352         bnx2x_set_cfg_pin(bp, cfg_pin, 0);
10353 }
10354
10355 static u8 bnx2x_54618se_read_status(struct bnx2x_phy *phy,
10356                                     struct link_params *params,
10357                                     struct link_vars *vars)
10358 {
10359         struct bnx2x *bp = params->bp;
10360         u16 val;
10361         u8 link_up = 0;
10362         u16 legacy_status, legacy_speed;
10363
10364         /* Get speed operation status */
10365         bnx2x_cl22_read(bp, phy,
10366                         0x19,
10367                         &legacy_status);
10368         DP(NETIF_MSG_LINK, "54618SE read_status: 0x%x\n", legacy_status);
10369
10370         /* Read status to clear the PHY interrupt. */
10371         bnx2x_cl22_read(bp, phy,
10372                         MDIO_REG_INTR_STATUS,
10373                         &val);
10374
10375         link_up = ((legacy_status & (1<<2)) == (1<<2));
10376
10377         if (link_up) {
10378                 legacy_speed = (legacy_status & (7<<8));
10379                 if (legacy_speed == (7<<8)) {
10380                         vars->line_speed = SPEED_1000;
10381                         vars->duplex = DUPLEX_FULL;
10382                 } else if (legacy_speed == (6<<8)) {
10383                         vars->line_speed = SPEED_1000;
10384                         vars->duplex = DUPLEX_HALF;
10385                 } else if (legacy_speed == (5<<8)) {
10386                         vars->line_speed = SPEED_100;
10387                         vars->duplex = DUPLEX_FULL;
10388                 }
10389                 /* Omitting 100Base-T4 for now */
10390                 else if (legacy_speed == (3<<8)) {
10391                         vars->line_speed = SPEED_100;
10392                         vars->duplex = DUPLEX_HALF;
10393                 } else if (legacy_speed == (2<<8)) {
10394                         vars->line_speed = SPEED_10;
10395                         vars->duplex = DUPLEX_FULL;
10396                 } else if (legacy_speed == (1<<8)) {
10397                         vars->line_speed = SPEED_10;
10398                         vars->duplex = DUPLEX_HALF;
10399                 } else /* Should not happen */
10400                         vars->line_speed = 0;
10401
10402                 DP(NETIF_MSG_LINK,
10403                    "Link is up in %dMbps, is_duplex_full= %d\n",
10404                    vars->line_speed,
10405                    (vars->duplex == DUPLEX_FULL));
10406
10407                 /* Check legacy speed AN resolution */
10408                 bnx2x_cl22_read(bp, phy,
10409                                 0x01,
10410                                 &val);
10411                 if (val & (1<<5))
10412                         vars->link_status |=
10413                                 LINK_STATUS_AUTO_NEGOTIATE_COMPLETE;
10414                 bnx2x_cl22_read(bp, phy,
10415                                 0x06,
10416                                 &val);
10417                 if ((val & (1<<0)) == 0)
10418                         vars->link_status |=
10419                                 LINK_STATUS_PARALLEL_DETECTION_USED;
10420
10421                 DP(NETIF_MSG_LINK, "BCM54618SE: link speed is %d\n",
10422                            vars->line_speed);
10423
10424                 /* Report whether EEE is resolved. */
10425                 bnx2x_cl22_read(bp, phy, MDIO_REG_GPHY_PHYID_LSB, &val);
10426                 if (val == MDIO_REG_GPHY_ID_54618SE) {
10427                         if (vars->link_status &
10428                             LINK_STATUS_AUTO_NEGOTIATE_COMPLETE)
10429                                 val = 0;
10430                         else {
10431                                 bnx2x_cl22_write(bp, phy,
10432                                         MDIO_REG_GPHY_CL45_ADDR_REG,
10433                                         MDIO_AN_DEVAD);
10434                                 bnx2x_cl22_write(bp, phy,
10435                                         MDIO_REG_GPHY_CL45_DATA_REG,
10436                                         MDIO_REG_GPHY_EEE_RESOLVED);
10437                                 bnx2x_cl22_write(bp, phy,
10438                                         MDIO_REG_GPHY_CL45_ADDR_REG,
10439                                         (0x1 << 14) | MDIO_AN_DEVAD);
10440                                 bnx2x_cl22_read(bp, phy,
10441                                         MDIO_REG_GPHY_CL45_DATA_REG,
10442                                         &val);
10443                         }
10444                         DP(NETIF_MSG_LINK, "EEE resolution: 0x%x\n", val);
10445                 }
10446
10447                 bnx2x_ext_phy_resolve_fc(phy, params, vars);
10448         }
10449         return link_up;
10450 }
10451
10452 static void bnx2x_54618se_config_loopback(struct bnx2x_phy *phy,
10453                                           struct link_params *params)
10454 {
10455         struct bnx2x *bp = params->bp;
10456         u16 val;
10457         u32 umac_base = params->port ? GRCBASE_UMAC1 : GRCBASE_UMAC0;
10458
10459         DP(NETIF_MSG_LINK, "2PMA/PMD ext_phy_loopback: 54618se\n");
10460
10461         /* Enable master/slave manual mmode and set to master */
10462         /* mii write 9 [bits set 11 12] */
10463         bnx2x_cl22_write(bp, phy, 0x09, 3<<11);
10464
10465         /* forced 1G and disable autoneg */
10466         /* set val [mii read 0] */
10467         /* set val [expr $val & [bits clear 6 12 13]] */
10468         /* set val [expr $val | [bits set 6 8]] */
10469         /* mii write 0 $val */
10470         bnx2x_cl22_read(bp, phy, 0x00, &val);
10471         val &= ~((1<<6) | (1<<12) | (1<<13));
10472         val |= (1<<6) | (1<<8);
10473         bnx2x_cl22_write(bp, phy, 0x00, val);
10474
10475         /* Set external loopback and Tx using 6dB coding */
10476         /* mii write 0x18 7 */
10477         /* set val [mii read 0x18] */
10478         /* mii write 0x18 [expr $val | [bits set 10 15]] */
10479         bnx2x_cl22_write(bp, phy, 0x18, 7);
10480         bnx2x_cl22_read(bp, phy, 0x18, &val);
10481         bnx2x_cl22_write(bp, phy, 0x18, val | (1<<10) | (1<<15));
10482
10483         /* This register opens the gate for the UMAC despite its name */
10484         REG_WR(bp, NIG_REG_EGRESS_EMAC0_PORT + params->port*4, 1);
10485
10486         /*
10487          * Maximum Frame Length (RW). Defines a 14-Bit maximum frame
10488          * length used by the MAC receive logic to check frames.
10489          */
10490         REG_WR(bp, umac_base + UMAC_REG_MAXFR, 0x2710);
10491 }
10492
10493 /******************************************************************/
10494 /*                      SFX7101 PHY SECTION                       */
10495 /******************************************************************/
10496 static void bnx2x_7101_config_loopback(struct bnx2x_phy *phy,
10497                                        struct link_params *params)
10498 {
10499         struct bnx2x *bp = params->bp;
10500         /* SFX7101_XGXS_TEST1 */
10501         bnx2x_cl45_write(bp, phy,
10502                          MDIO_XS_DEVAD, MDIO_XS_SFX7101_XGXS_TEST1, 0x100);
10503 }
10504
10505 static int bnx2x_7101_config_init(struct bnx2x_phy *phy,
10506                                   struct link_params *params,
10507                                   struct link_vars *vars)
10508 {
10509         u16 fw_ver1, fw_ver2, val;
10510         struct bnx2x *bp = params->bp;
10511         DP(NETIF_MSG_LINK, "Setting the SFX7101 LASI indication\n");
10512
10513         /* Restore normal power mode*/
10514         bnx2x_set_gpio(bp, MISC_REGISTERS_GPIO_2,
10515                        MISC_REGISTERS_GPIO_OUTPUT_HIGH, params->port);
10516         /* HW reset */
10517         bnx2x_ext_phy_hw_reset(bp, params->port);
10518         bnx2x_wait_reset_complete(bp, phy, params);
10519
10520         bnx2x_cl45_write(bp, phy,
10521                          MDIO_PMA_DEVAD, MDIO_PMA_LASI_CTRL, 0x1);
10522         DP(NETIF_MSG_LINK, "Setting the SFX7101 LED to blink on traffic\n");
10523         bnx2x_cl45_write(bp, phy,
10524                          MDIO_PMA_DEVAD, MDIO_PMA_REG_7107_LED_CNTL, (1<<3));
10525
10526         bnx2x_ext_phy_set_pause(params, phy, vars);
10527         /* Restart autoneg */
10528         bnx2x_cl45_read(bp, phy,
10529                         MDIO_AN_DEVAD, MDIO_AN_REG_CTRL, &val);
10530         val |= 0x200;
10531         bnx2x_cl45_write(bp, phy,
10532                          MDIO_AN_DEVAD, MDIO_AN_REG_CTRL, val);
10533
10534         /* Save spirom version */
10535         bnx2x_cl45_read(bp, phy,
10536                         MDIO_PMA_DEVAD, MDIO_PMA_REG_7101_VER1, &fw_ver1);
10537
10538         bnx2x_cl45_read(bp, phy,
10539                         MDIO_PMA_DEVAD, MDIO_PMA_REG_7101_VER2, &fw_ver2);
10540         bnx2x_save_spirom_version(bp, params->port,
10541                                   (u32)(fw_ver1<<16 | fw_ver2), phy->ver_addr);
10542         return 0;
10543 }
10544
10545 static u8 bnx2x_7101_read_status(struct bnx2x_phy *phy,
10546                                  struct link_params *params,
10547                                  struct link_vars *vars)
10548 {
10549         struct bnx2x *bp = params->bp;
10550         u8 link_up;
10551         u16 val1, val2;
10552         bnx2x_cl45_read(bp, phy,
10553                         MDIO_PMA_DEVAD, MDIO_PMA_LASI_STAT, &val2);
10554         bnx2x_cl45_read(bp, phy,
10555                         MDIO_PMA_DEVAD, MDIO_PMA_LASI_STAT, &val1);
10556         DP(NETIF_MSG_LINK, "10G-base-T LASI status 0x%x->0x%x\n",
10557                    val2, val1);
10558         bnx2x_cl45_read(bp, phy,
10559                         MDIO_PMA_DEVAD, MDIO_PMA_REG_STATUS, &val2);
10560         bnx2x_cl45_read(bp, phy,
10561                         MDIO_PMA_DEVAD, MDIO_PMA_REG_STATUS, &val1);
10562         DP(NETIF_MSG_LINK, "10G-base-T PMA status 0x%x->0x%x\n",
10563                    val2, val1);
10564         link_up = ((val1 & 4) == 4);
10565         /* if link is up print the AN outcome of the SFX7101 PHY */
10566         if (link_up) {
10567                 bnx2x_cl45_read(bp, phy,
10568                                 MDIO_AN_DEVAD, MDIO_AN_REG_MASTER_STATUS,
10569                                 &val2);
10570                 vars->line_speed = SPEED_10000;
10571                 vars->duplex = DUPLEX_FULL;
10572                 DP(NETIF_MSG_LINK, "SFX7101 AN status 0x%x->Master=%x\n",
10573                            val2, (val2 & (1<<14)));
10574                 bnx2x_ext_phy_10G_an_resolve(bp, phy, vars);
10575                 bnx2x_ext_phy_resolve_fc(phy, params, vars);
10576         }
10577         return link_up;
10578 }
10579
10580 static int bnx2x_7101_format_ver(u32 spirom_ver, u8 *str, u16 *len)
10581 {
10582         if (*len < 5)
10583                 return -EINVAL;
10584         str[0] = (spirom_ver & 0xFF);
10585         str[1] = (spirom_ver & 0xFF00) >> 8;
10586         str[2] = (spirom_ver & 0xFF0000) >> 16;
10587         str[3] = (spirom_ver & 0xFF000000) >> 24;
10588         str[4] = '\0';
10589         *len -= 5;
10590         return 0;
10591 }
10592
10593 void bnx2x_sfx7101_sp_sw_reset(struct bnx2x *bp, struct bnx2x_phy *phy)
10594 {
10595         u16 val, cnt;
10596
10597         bnx2x_cl45_read(bp, phy,
10598                         MDIO_PMA_DEVAD,
10599                         MDIO_PMA_REG_7101_RESET, &val);
10600
10601         for (cnt = 0; cnt < 10; cnt++) {
10602                 msleep(50);
10603                 /* Writes a self-clearing reset */
10604                 bnx2x_cl45_write(bp, phy,
10605                                  MDIO_PMA_DEVAD,
10606                                  MDIO_PMA_REG_7101_RESET,
10607                                  (val | (1<<15)));
10608                 /* Wait for clear */
10609                 bnx2x_cl45_read(bp, phy,
10610                                 MDIO_PMA_DEVAD,
10611                                 MDIO_PMA_REG_7101_RESET, &val);
10612
10613                 if ((val & (1<<15)) == 0)
10614                         break;
10615         }
10616 }
10617
10618 static void bnx2x_7101_hw_reset(struct bnx2x_phy *phy,
10619                                 struct link_params *params) {
10620         /* Low power mode is controlled by GPIO 2 */
10621         bnx2x_set_gpio(params->bp, MISC_REGISTERS_GPIO_2,
10622                        MISC_REGISTERS_GPIO_OUTPUT_LOW, params->port);
10623         /* The PHY reset is controlled by GPIO 1 */
10624         bnx2x_set_gpio(params->bp, MISC_REGISTERS_GPIO_1,
10625                        MISC_REGISTERS_GPIO_OUTPUT_LOW, params->port);
10626 }
10627
10628 static void bnx2x_7101_set_link_led(struct bnx2x_phy *phy,
10629                                     struct link_params *params, u8 mode)
10630 {
10631         u16 val = 0;
10632         struct bnx2x *bp = params->bp;
10633         switch (mode) {
10634         case LED_MODE_FRONT_PANEL_OFF:
10635         case LED_MODE_OFF:
10636                 val = 2;
10637                 break;
10638         case LED_MODE_ON:
10639                 val = 1;
10640                 break;
10641         case LED_MODE_OPER:
10642                 val = 0;
10643                 break;
10644         }
10645         bnx2x_cl45_write(bp, phy,
10646                          MDIO_PMA_DEVAD,
10647                          MDIO_PMA_REG_7107_LINK_LED_CNTL,
10648                          val);
10649 }
10650
10651 /******************************************************************/
10652 /*                      STATIC PHY DECLARATION                    */
10653 /******************************************************************/
10654
10655 static struct bnx2x_phy phy_null = {
10656         .type           = PORT_HW_CFG_XGXS_EXT_PHY_TYPE_NOT_CONN,
10657         .addr           = 0,
10658         .def_md_devad   = 0,
10659         .flags          = FLAGS_INIT_XGXS_FIRST,
10660         .rx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff},
10661         .tx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff},
10662         .mdio_ctrl      = 0,
10663         .supported      = 0,
10664         .media_type     = ETH_PHY_NOT_PRESENT,
10665         .ver_addr       = 0,
10666         .req_flow_ctrl  = 0,
10667         .req_line_speed = 0,
10668         .speed_cap_mask = 0,
10669         .req_duplex     = 0,
10670         .rsrv           = 0,
10671         .config_init    = (config_init_t)NULL,
10672         .read_status    = (read_status_t)NULL,
10673         .link_reset     = (link_reset_t)NULL,
10674         .config_loopback = (config_loopback_t)NULL,
10675         .format_fw_ver  = (format_fw_ver_t)NULL,
10676         .hw_reset       = (hw_reset_t)NULL,
10677         .set_link_led   = (set_link_led_t)NULL,
10678         .phy_specific_func = (phy_specific_func_t)NULL
10679 };
10680
10681 static struct bnx2x_phy phy_serdes = {
10682         .type           = PORT_HW_CFG_SERDES_EXT_PHY_TYPE_DIRECT,
10683         .addr           = 0xff,
10684         .def_md_devad   = 0,
10685         .flags          = 0,
10686         .rx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff},
10687         .tx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff},
10688         .mdio_ctrl      = 0,
10689         .supported      = (SUPPORTED_10baseT_Half |
10690                            SUPPORTED_10baseT_Full |
10691                            SUPPORTED_100baseT_Half |
10692                            SUPPORTED_100baseT_Full |
10693                            SUPPORTED_1000baseT_Full |
10694                            SUPPORTED_2500baseX_Full |
10695                            SUPPORTED_TP |
10696                            SUPPORTED_Autoneg |
10697                            SUPPORTED_Pause |
10698                            SUPPORTED_Asym_Pause),
10699         .media_type     = ETH_PHY_BASE_T,
10700         .ver_addr       = 0,
10701         .req_flow_ctrl  = 0,
10702         .req_line_speed = 0,
10703         .speed_cap_mask = 0,
10704         .req_duplex     = 0,
10705         .rsrv           = 0,
10706         .config_init    = (config_init_t)bnx2x_xgxs_config_init,
10707         .read_status    = (read_status_t)bnx2x_link_settings_status,
10708         .link_reset     = (link_reset_t)bnx2x_int_link_reset,
10709         .config_loopback = (config_loopback_t)NULL,
10710         .format_fw_ver  = (format_fw_ver_t)NULL,
10711         .hw_reset       = (hw_reset_t)NULL,
10712         .set_link_led   = (set_link_led_t)NULL,
10713         .phy_specific_func = (phy_specific_func_t)NULL
10714 };
10715
10716 static struct bnx2x_phy phy_xgxs = {
10717         .type           = PORT_HW_CFG_XGXS_EXT_PHY_TYPE_DIRECT,
10718         .addr           = 0xff,
10719         .def_md_devad   = 0,
10720         .flags          = 0,
10721         .rx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff},
10722         .tx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff},
10723         .mdio_ctrl      = 0,
10724         .supported      = (SUPPORTED_10baseT_Half |
10725                            SUPPORTED_10baseT_Full |
10726                            SUPPORTED_100baseT_Half |
10727                            SUPPORTED_100baseT_Full |
10728                            SUPPORTED_1000baseT_Full |
10729                            SUPPORTED_2500baseX_Full |
10730                            SUPPORTED_10000baseT_Full |
10731                            SUPPORTED_FIBRE |
10732                            SUPPORTED_Autoneg |
10733                            SUPPORTED_Pause |
10734                            SUPPORTED_Asym_Pause),
10735         .media_type     = ETH_PHY_CX4,
10736         .ver_addr       = 0,
10737         .req_flow_ctrl  = 0,
10738         .req_line_speed = 0,
10739         .speed_cap_mask = 0,
10740         .req_duplex     = 0,
10741         .rsrv           = 0,
10742         .config_init    = (config_init_t)bnx2x_xgxs_config_init,
10743         .read_status    = (read_status_t)bnx2x_link_settings_status,
10744         .link_reset     = (link_reset_t)bnx2x_int_link_reset,
10745         .config_loopback = (config_loopback_t)bnx2x_set_xgxs_loopback,
10746         .format_fw_ver  = (format_fw_ver_t)NULL,
10747         .hw_reset       = (hw_reset_t)NULL,
10748         .set_link_led   = (set_link_led_t)NULL,
10749         .phy_specific_func = (phy_specific_func_t)NULL
10750 };
10751 static struct bnx2x_phy phy_warpcore = {
10752         .type           = PORT_HW_CFG_XGXS_EXT_PHY_TYPE_DIRECT,
10753         .addr           = 0xff,
10754         .def_md_devad   = 0,
10755         .flags          = FLAGS_HW_LOCK_REQUIRED,
10756         .rx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff},
10757         .tx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff},
10758         .mdio_ctrl      = 0,
10759         .supported      = (SUPPORTED_10baseT_Half |
10760                              SUPPORTED_10baseT_Full |
10761                              SUPPORTED_100baseT_Half |
10762                              SUPPORTED_100baseT_Full |
10763                              SUPPORTED_1000baseT_Full |
10764                              SUPPORTED_10000baseT_Full |
10765                              SUPPORTED_20000baseKR2_Full |
10766                              SUPPORTED_20000baseMLD2_Full |
10767                              SUPPORTED_FIBRE |
10768                              SUPPORTED_Autoneg |
10769                              SUPPORTED_Pause |
10770                              SUPPORTED_Asym_Pause),
10771         .media_type     = ETH_PHY_UNSPECIFIED,
10772         .ver_addr       = 0,
10773         .req_flow_ctrl  = 0,
10774         .req_line_speed = 0,
10775         .speed_cap_mask = 0,
10776         /* req_duplex = */0,
10777         /* rsrv = */0,
10778         .config_init    = (config_init_t)bnx2x_warpcore_config_init,
10779         .read_status    = (read_status_t)bnx2x_warpcore_read_status,
10780         .link_reset     = (link_reset_t)bnx2x_warpcore_link_reset,
10781         .config_loopback = (config_loopback_t)bnx2x_set_warpcore_loopback,
10782         .format_fw_ver  = (format_fw_ver_t)NULL,
10783         .hw_reset       = (hw_reset_t)bnx2x_warpcore_hw_reset,
10784         .set_link_led   = (set_link_led_t)NULL,
10785         .phy_specific_func = (phy_specific_func_t)NULL
10786 };
10787
10788
10789 static struct bnx2x_phy phy_7101 = {
10790         .type           = PORT_HW_CFG_XGXS_EXT_PHY_TYPE_SFX7101,
10791         .addr           = 0xff,
10792         .def_md_devad   = 0,
10793         .flags          = FLAGS_FAN_FAILURE_DET_REQ,
10794         .rx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff},
10795         .tx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff},
10796         .mdio_ctrl      = 0,
10797         .supported      = (SUPPORTED_10000baseT_Full |
10798                            SUPPORTED_TP |
10799                            SUPPORTED_Autoneg |
10800                            SUPPORTED_Pause |
10801                            SUPPORTED_Asym_Pause),
10802         .media_type     = ETH_PHY_BASE_T,
10803         .ver_addr       = 0,
10804         .req_flow_ctrl  = 0,
10805         .req_line_speed = 0,
10806         .speed_cap_mask = 0,
10807         .req_duplex     = 0,
10808         .rsrv           = 0,
10809         .config_init    = (config_init_t)bnx2x_7101_config_init,
10810         .read_status    = (read_status_t)bnx2x_7101_read_status,
10811         .link_reset     = (link_reset_t)bnx2x_common_ext_link_reset,
10812         .config_loopback = (config_loopback_t)bnx2x_7101_config_loopback,
10813         .format_fw_ver  = (format_fw_ver_t)bnx2x_7101_format_ver,
10814         .hw_reset       = (hw_reset_t)bnx2x_7101_hw_reset,
10815         .set_link_led   = (set_link_led_t)bnx2x_7101_set_link_led,
10816         .phy_specific_func = (phy_specific_func_t)NULL
10817 };
10818 static struct bnx2x_phy phy_8073 = {
10819         .type           = PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8073,
10820         .addr           = 0xff,
10821         .def_md_devad   = 0,
10822         .flags          = FLAGS_HW_LOCK_REQUIRED,
10823         .rx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff},
10824         .tx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff},
10825         .mdio_ctrl      = 0,
10826         .supported      = (SUPPORTED_10000baseT_Full |
10827                            SUPPORTED_2500baseX_Full |
10828                            SUPPORTED_1000baseT_Full |
10829                            SUPPORTED_FIBRE |
10830                            SUPPORTED_Autoneg |
10831                            SUPPORTED_Pause |
10832                            SUPPORTED_Asym_Pause),
10833         .media_type     = ETH_PHY_KR,
10834         .ver_addr       = 0,
10835         .req_flow_ctrl  = 0,
10836         .req_line_speed = 0,
10837         .speed_cap_mask = 0,
10838         .req_duplex     = 0,
10839         .rsrv           = 0,
10840         .config_init    = (config_init_t)bnx2x_8073_config_init,
10841         .read_status    = (read_status_t)bnx2x_8073_read_status,
10842         .link_reset     = (link_reset_t)bnx2x_8073_link_reset,
10843         .config_loopback = (config_loopback_t)NULL,
10844         .format_fw_ver  = (format_fw_ver_t)bnx2x_format_ver,
10845         .hw_reset       = (hw_reset_t)NULL,
10846         .set_link_led   = (set_link_led_t)NULL,
10847         .phy_specific_func = (phy_specific_func_t)NULL
10848 };
10849 static struct bnx2x_phy phy_8705 = {
10850         .type           = PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8705,
10851         .addr           = 0xff,
10852         .def_md_devad   = 0,
10853         .flags          = FLAGS_INIT_XGXS_FIRST,
10854         .rx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff},
10855         .tx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff},
10856         .mdio_ctrl      = 0,
10857         .supported      = (SUPPORTED_10000baseT_Full |
10858                            SUPPORTED_FIBRE |
10859                            SUPPORTED_Pause |
10860                            SUPPORTED_Asym_Pause),
10861         .media_type     = ETH_PHY_XFP_FIBER,
10862         .ver_addr       = 0,
10863         .req_flow_ctrl  = 0,
10864         .req_line_speed = 0,
10865         .speed_cap_mask = 0,
10866         .req_duplex     = 0,
10867         .rsrv           = 0,
10868         .config_init    = (config_init_t)bnx2x_8705_config_init,
10869         .read_status    = (read_status_t)bnx2x_8705_read_status,
10870         .link_reset     = (link_reset_t)bnx2x_common_ext_link_reset,
10871         .config_loopback = (config_loopback_t)NULL,
10872         .format_fw_ver  = (format_fw_ver_t)bnx2x_null_format_ver,
10873         .hw_reset       = (hw_reset_t)NULL,
10874         .set_link_led   = (set_link_led_t)NULL,
10875         .phy_specific_func = (phy_specific_func_t)NULL
10876 };
10877 static struct bnx2x_phy phy_8706 = {
10878         .type           = PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8706,
10879         .addr           = 0xff,
10880         .def_md_devad   = 0,
10881         .flags          = FLAGS_INIT_XGXS_FIRST,
10882         .rx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff},
10883         .tx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff},
10884         .mdio_ctrl      = 0,
10885         .supported      = (SUPPORTED_10000baseT_Full |
10886                            SUPPORTED_1000baseT_Full |
10887                            SUPPORTED_FIBRE |
10888                            SUPPORTED_Pause |
10889                            SUPPORTED_Asym_Pause),
10890         .media_type     = ETH_PHY_SFP_FIBER,
10891         .ver_addr       = 0,
10892         .req_flow_ctrl  = 0,
10893         .req_line_speed = 0,
10894         .speed_cap_mask = 0,
10895         .req_duplex     = 0,
10896         .rsrv           = 0,
10897         .config_init    = (config_init_t)bnx2x_8706_config_init,
10898         .read_status    = (read_status_t)bnx2x_8706_read_status,
10899         .link_reset     = (link_reset_t)bnx2x_common_ext_link_reset,
10900         .config_loopback = (config_loopback_t)NULL,
10901         .format_fw_ver  = (format_fw_ver_t)bnx2x_format_ver,
10902         .hw_reset       = (hw_reset_t)NULL,
10903         .set_link_led   = (set_link_led_t)NULL,
10904         .phy_specific_func = (phy_specific_func_t)NULL
10905 };
10906
10907 static struct bnx2x_phy phy_8726 = {
10908         .type           = PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8726,
10909         .addr           = 0xff,
10910         .def_md_devad   = 0,
10911         .flags          = (FLAGS_HW_LOCK_REQUIRED |
10912                            FLAGS_INIT_XGXS_FIRST),
10913         .rx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff},
10914         .tx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff},
10915         .mdio_ctrl      = 0,
10916         .supported      = (SUPPORTED_10000baseT_Full |
10917                            SUPPORTED_1000baseT_Full |
10918                            SUPPORTED_Autoneg |
10919                            SUPPORTED_FIBRE |
10920                            SUPPORTED_Pause |
10921                            SUPPORTED_Asym_Pause),
10922         .media_type     = ETH_PHY_NOT_PRESENT,
10923         .ver_addr       = 0,
10924         .req_flow_ctrl  = 0,
10925         .req_line_speed = 0,
10926         .speed_cap_mask = 0,
10927         .req_duplex     = 0,
10928         .rsrv           = 0,
10929         .config_init    = (config_init_t)bnx2x_8726_config_init,
10930         .read_status    = (read_status_t)bnx2x_8726_read_status,
10931         .link_reset     = (link_reset_t)bnx2x_8726_link_reset,
10932         .config_loopback = (config_loopback_t)bnx2x_8726_config_loopback,
10933         .format_fw_ver  = (format_fw_ver_t)bnx2x_format_ver,
10934         .hw_reset       = (hw_reset_t)NULL,
10935         .set_link_led   = (set_link_led_t)NULL,
10936         .phy_specific_func = (phy_specific_func_t)NULL
10937 };
10938
10939 static struct bnx2x_phy phy_8727 = {
10940         .type           = PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8727,
10941         .addr           = 0xff,
10942         .def_md_devad   = 0,
10943         .flags          = FLAGS_FAN_FAILURE_DET_REQ,
10944         .rx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff},
10945         .tx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff},
10946         .mdio_ctrl      = 0,
10947         .supported      = (SUPPORTED_10000baseT_Full |
10948                            SUPPORTED_1000baseT_Full |
10949                            SUPPORTED_FIBRE |
10950                            SUPPORTED_Pause |
10951                            SUPPORTED_Asym_Pause),
10952         .media_type     = ETH_PHY_NOT_PRESENT,
10953         .ver_addr       = 0,
10954         .req_flow_ctrl  = 0,
10955         .req_line_speed = 0,
10956         .speed_cap_mask = 0,
10957         .req_duplex     = 0,
10958         .rsrv           = 0,
10959         .config_init    = (config_init_t)bnx2x_8727_config_init,
10960         .read_status    = (read_status_t)bnx2x_8727_read_status,
10961         .link_reset     = (link_reset_t)bnx2x_8727_link_reset,
10962         .config_loopback = (config_loopback_t)NULL,
10963         .format_fw_ver  = (format_fw_ver_t)bnx2x_format_ver,
10964         .hw_reset       = (hw_reset_t)bnx2x_8727_hw_reset,
10965         .set_link_led   = (set_link_led_t)bnx2x_8727_set_link_led,
10966         .phy_specific_func = (phy_specific_func_t)bnx2x_8727_specific_func
10967 };
10968 static struct bnx2x_phy phy_8481 = {
10969         .type           = PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8481,
10970         .addr           = 0xff,
10971         .def_md_devad   = 0,
10972         .flags          = FLAGS_FAN_FAILURE_DET_REQ |
10973                           FLAGS_REARM_LATCH_SIGNAL,
10974         .rx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff},
10975         .tx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff},
10976         .mdio_ctrl      = 0,
10977         .supported      = (SUPPORTED_10baseT_Half |
10978                            SUPPORTED_10baseT_Full |
10979                            SUPPORTED_100baseT_Half |
10980                            SUPPORTED_100baseT_Full |
10981                            SUPPORTED_1000baseT_Full |
10982                            SUPPORTED_10000baseT_Full |
10983                            SUPPORTED_TP |
10984                            SUPPORTED_Autoneg |
10985                            SUPPORTED_Pause |
10986                            SUPPORTED_Asym_Pause),
10987         .media_type     = ETH_PHY_BASE_T,
10988         .ver_addr       = 0,
10989         .req_flow_ctrl  = 0,
10990         .req_line_speed = 0,
10991         .speed_cap_mask = 0,
10992         .req_duplex     = 0,
10993         .rsrv           = 0,
10994         .config_init    = (config_init_t)bnx2x_8481_config_init,
10995         .read_status    = (read_status_t)bnx2x_848xx_read_status,
10996         .link_reset     = (link_reset_t)bnx2x_8481_link_reset,
10997         .config_loopback = (config_loopback_t)NULL,
10998         .format_fw_ver  = (format_fw_ver_t)bnx2x_848xx_format_ver,
10999         .hw_reset       = (hw_reset_t)bnx2x_8481_hw_reset,
11000         .set_link_led   = (set_link_led_t)bnx2x_848xx_set_link_led,
11001         .phy_specific_func = (phy_specific_func_t)NULL
11002 };
11003
11004 static struct bnx2x_phy phy_84823 = {
11005         .type           = PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM84823,
11006         .addr           = 0xff,
11007         .def_md_devad   = 0,
11008         .flags          = FLAGS_FAN_FAILURE_DET_REQ |
11009                           FLAGS_REARM_LATCH_SIGNAL,
11010         .rx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff},
11011         .tx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff},
11012         .mdio_ctrl      = 0,
11013         .supported      = (SUPPORTED_10baseT_Half |
11014                            SUPPORTED_10baseT_Full |
11015                            SUPPORTED_100baseT_Half |
11016                            SUPPORTED_100baseT_Full |
11017                            SUPPORTED_1000baseT_Full |
11018                            SUPPORTED_10000baseT_Full |
11019                            SUPPORTED_TP |
11020                            SUPPORTED_Autoneg |
11021                            SUPPORTED_Pause |
11022                            SUPPORTED_Asym_Pause),
11023         .media_type     = ETH_PHY_BASE_T,
11024         .ver_addr       = 0,
11025         .req_flow_ctrl  = 0,
11026         .req_line_speed = 0,
11027         .speed_cap_mask = 0,
11028         .req_duplex     = 0,
11029         .rsrv           = 0,
11030         .config_init    = (config_init_t)bnx2x_848x3_config_init,
11031         .read_status    = (read_status_t)bnx2x_848xx_read_status,
11032         .link_reset     = (link_reset_t)bnx2x_848x3_link_reset,
11033         .config_loopback = (config_loopback_t)NULL,
11034         .format_fw_ver  = (format_fw_ver_t)bnx2x_848xx_format_ver,
11035         .hw_reset       = (hw_reset_t)NULL,
11036         .set_link_led   = (set_link_led_t)bnx2x_848xx_set_link_led,
11037         .phy_specific_func = (phy_specific_func_t)NULL
11038 };
11039
11040 static struct bnx2x_phy phy_84833 = {
11041         .type           = PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM84833,
11042         .addr           = 0xff,
11043         .def_md_devad   = 0,
11044         .flags          = FLAGS_FAN_FAILURE_DET_REQ |
11045                             FLAGS_REARM_LATCH_SIGNAL,
11046         .rx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff},
11047         .tx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff},
11048         .mdio_ctrl      = 0,
11049         .supported      = (SUPPORTED_100baseT_Half |
11050                            SUPPORTED_100baseT_Full |
11051                            SUPPORTED_1000baseT_Full |
11052                            SUPPORTED_10000baseT_Full |
11053                            SUPPORTED_TP |
11054                            SUPPORTED_Autoneg |
11055                            SUPPORTED_Pause |
11056                            SUPPORTED_Asym_Pause),
11057         .media_type     = ETH_PHY_BASE_T,
11058         .ver_addr       = 0,
11059         .req_flow_ctrl  = 0,
11060         .req_line_speed = 0,
11061         .speed_cap_mask = 0,
11062         .req_duplex     = 0,
11063         .rsrv           = 0,
11064         .config_init    = (config_init_t)bnx2x_848x3_config_init,
11065         .read_status    = (read_status_t)bnx2x_848xx_read_status,
11066         .link_reset     = (link_reset_t)bnx2x_848x3_link_reset,
11067         .config_loopback = (config_loopback_t)NULL,
11068         .format_fw_ver  = (format_fw_ver_t)bnx2x_848xx_format_ver,
11069         .hw_reset       = (hw_reset_t)bnx2x_84833_hw_reset_phy,
11070         .set_link_led   = (set_link_led_t)bnx2x_848xx_set_link_led,
11071         .phy_specific_func = (phy_specific_func_t)NULL
11072 };
11073
11074 static struct bnx2x_phy phy_54618se = {
11075         .type           = PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM54618SE,
11076         .addr           = 0xff,
11077         .def_md_devad   = 0,
11078         .flags          = FLAGS_INIT_XGXS_FIRST,
11079         .rx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff},
11080         .tx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff},
11081         .mdio_ctrl      = 0,
11082         .supported      = (SUPPORTED_10baseT_Half |
11083                            SUPPORTED_10baseT_Full |
11084                            SUPPORTED_100baseT_Half |
11085                            SUPPORTED_100baseT_Full |
11086                            SUPPORTED_1000baseT_Full |
11087                            SUPPORTED_TP |
11088                            SUPPORTED_Autoneg |
11089                            SUPPORTED_Pause |
11090                            SUPPORTED_Asym_Pause),
11091         .media_type     = ETH_PHY_BASE_T,
11092         .ver_addr       = 0,
11093         .req_flow_ctrl  = 0,
11094         .req_line_speed = 0,
11095         .speed_cap_mask = 0,
11096         /* req_duplex = */0,
11097         /* rsrv = */0,
11098         .config_init    = (config_init_t)bnx2x_54618se_config_init,
11099         .read_status    = (read_status_t)bnx2x_54618se_read_status,
11100         .link_reset     = (link_reset_t)bnx2x_54618se_link_reset,
11101         .config_loopback = (config_loopback_t)bnx2x_54618se_config_loopback,
11102         .format_fw_ver  = (format_fw_ver_t)NULL,
11103         .hw_reset       = (hw_reset_t)NULL,
11104         .set_link_led   = (set_link_led_t)bnx2x_54618se_set_link_led,
11105         .phy_specific_func = (phy_specific_func_t)NULL
11106 };
11107 /*****************************************************************/
11108 /*                                                               */
11109 /* Populate the phy according. Main function: bnx2x_populate_phy   */
11110 /*                                                               */
11111 /*****************************************************************/
11112
11113 static void bnx2x_populate_preemphasis(struct bnx2x *bp, u32 shmem_base,
11114                                      struct bnx2x_phy *phy, u8 port,
11115                                      u8 phy_index)
11116 {
11117         /* Get the 4 lanes xgxs config rx and tx */
11118         u32 rx = 0, tx = 0, i;
11119         for (i = 0; i < 2; i++) {
11120                 /*
11121                  * INT_PHY and EXT_PHY1 share the same value location in the
11122                  * shmem. When num_phys is greater than 1, than this value
11123                  * applies only to EXT_PHY1
11124                  */
11125                 if (phy_index == INT_PHY || phy_index == EXT_PHY1) {
11126                         rx = REG_RD(bp, shmem_base +
11127                                     offsetof(struct shmem_region,
11128                           dev_info.port_hw_config[port].xgxs_config_rx[i<<1]));
11129
11130                         tx = REG_RD(bp, shmem_base +
11131                                     offsetof(struct shmem_region,
11132                           dev_info.port_hw_config[port].xgxs_config_tx[i<<1]));
11133                 } else {
11134                         rx = REG_RD(bp, shmem_base +
11135                                     offsetof(struct shmem_region,
11136                          dev_info.port_hw_config[port].xgxs_config2_rx[i<<1]));
11137
11138                         tx = REG_RD(bp, shmem_base +
11139                                     offsetof(struct shmem_region,
11140                          dev_info.port_hw_config[port].xgxs_config2_rx[i<<1]));
11141                 }
11142
11143                 phy->rx_preemphasis[i << 1] = ((rx>>16) & 0xffff);
11144                 phy->rx_preemphasis[(i << 1) + 1] = (rx & 0xffff);
11145
11146                 phy->tx_preemphasis[i << 1] = ((tx>>16) & 0xffff);
11147                 phy->tx_preemphasis[(i << 1) + 1] = (tx & 0xffff);
11148         }
11149 }
11150
11151 static u32 bnx2x_get_ext_phy_config(struct bnx2x *bp, u32 shmem_base,
11152                                     u8 phy_index, u8 port)
11153 {
11154         u32 ext_phy_config = 0;
11155         switch (phy_index) {
11156         case EXT_PHY1:
11157                 ext_phy_config = REG_RD(bp, shmem_base +
11158                                               offsetof(struct shmem_region,
11159                         dev_info.port_hw_config[port].external_phy_config));
11160                 break;
11161         case EXT_PHY2:
11162                 ext_phy_config = REG_RD(bp, shmem_base +
11163                                               offsetof(struct shmem_region,
11164                         dev_info.port_hw_config[port].external_phy_config2));
11165                 break;
11166         default:
11167                 DP(NETIF_MSG_LINK, "Invalid phy_index %d\n", phy_index);
11168                 return -EINVAL;
11169         }
11170
11171         return ext_phy_config;
11172 }
11173 static int bnx2x_populate_int_phy(struct bnx2x *bp, u32 shmem_base, u8 port,
11174                                   struct bnx2x_phy *phy)
11175 {
11176         u32 phy_addr;
11177         u32 chip_id;
11178         u32 switch_cfg = (REG_RD(bp, shmem_base +
11179                                        offsetof(struct shmem_region,
11180                         dev_info.port_feature_config[port].link_config)) &
11181                           PORT_FEATURE_CONNECTED_SWITCH_MASK);
11182         chip_id = REG_RD(bp, MISC_REG_CHIP_NUM) << 16;
11183         DP(NETIF_MSG_LINK, ":chip_id = 0x%x\n", chip_id);
11184         if (USES_WARPCORE(bp)) {
11185                 u32 serdes_net_if;
11186                 phy_addr = REG_RD(bp,
11187                                   MISC_REG_WC0_CTRL_PHY_ADDR);
11188                 *phy = phy_warpcore;
11189                 if (REG_RD(bp, MISC_REG_PORT4MODE_EN_OVWR) == 0x3)
11190                         phy->flags |= FLAGS_4_PORT_MODE;
11191                 else
11192                         phy->flags &= ~FLAGS_4_PORT_MODE;
11193                         /* Check Dual mode */
11194                 serdes_net_if = (REG_RD(bp, shmem_base +
11195                                         offsetof(struct shmem_region, dev_info.
11196                                         port_hw_config[port].default_cfg)) &
11197                                  PORT_HW_CFG_NET_SERDES_IF_MASK);
11198                 /*
11199                  * Set the appropriate supported and flags indications per
11200                  * interface type of the chip
11201                  */
11202                 switch (serdes_net_if) {
11203                 case PORT_HW_CFG_NET_SERDES_IF_SGMII:
11204                         phy->supported &= (SUPPORTED_10baseT_Half |
11205                                            SUPPORTED_10baseT_Full |
11206                                            SUPPORTED_100baseT_Half |
11207                                            SUPPORTED_100baseT_Full |
11208                                            SUPPORTED_1000baseT_Full |
11209                                            SUPPORTED_FIBRE |
11210                                            SUPPORTED_Autoneg |
11211                                            SUPPORTED_Pause |
11212                                            SUPPORTED_Asym_Pause);
11213                         phy->media_type = ETH_PHY_BASE_T;
11214                         break;
11215                 case PORT_HW_CFG_NET_SERDES_IF_XFI:
11216                         phy->media_type = ETH_PHY_XFP_FIBER;
11217                         break;
11218                 case PORT_HW_CFG_NET_SERDES_IF_SFI:
11219                         phy->supported &= (SUPPORTED_1000baseT_Full |
11220                                            SUPPORTED_10000baseT_Full |
11221                                            SUPPORTED_FIBRE |
11222                                            SUPPORTED_Pause |
11223                                            SUPPORTED_Asym_Pause);
11224                         phy->media_type = ETH_PHY_SFP_FIBER;
11225                         break;
11226                 case PORT_HW_CFG_NET_SERDES_IF_KR:
11227                         phy->media_type = ETH_PHY_KR;
11228                         phy->supported &= (SUPPORTED_1000baseT_Full |
11229                                            SUPPORTED_10000baseT_Full |
11230                                            SUPPORTED_FIBRE |
11231                                            SUPPORTED_Autoneg |
11232                                            SUPPORTED_Pause |
11233                                            SUPPORTED_Asym_Pause);
11234                         break;
11235                 case PORT_HW_CFG_NET_SERDES_IF_DXGXS:
11236                         phy->media_type = ETH_PHY_KR;
11237                         phy->flags |= FLAGS_WC_DUAL_MODE;
11238                         phy->supported &= (SUPPORTED_20000baseMLD2_Full |
11239                                            SUPPORTED_FIBRE |
11240                                            SUPPORTED_Pause |
11241                                            SUPPORTED_Asym_Pause);
11242                         break;
11243                 case PORT_HW_CFG_NET_SERDES_IF_KR2:
11244                         phy->media_type = ETH_PHY_KR;
11245                         phy->flags |= FLAGS_WC_DUAL_MODE;
11246                         phy->supported &= (SUPPORTED_20000baseKR2_Full |
11247                                            SUPPORTED_FIBRE |
11248                                            SUPPORTED_Pause |
11249                                            SUPPORTED_Asym_Pause);
11250                         break;
11251                 default:
11252                         DP(NETIF_MSG_LINK, "Unknown WC interface type 0x%x\n",
11253                                        serdes_net_if);
11254                         break;
11255                 }
11256
11257                 /*
11258                  * Enable MDC/MDIO work-around for E3 A0 since free running MDC
11259                  * was not set as expected. For B0, ECO will be enabled so there
11260                  * won't be an issue there
11261                  */
11262                 if (CHIP_REV(bp) == CHIP_REV_Ax)
11263                         phy->flags |= FLAGS_MDC_MDIO_WA;
11264                 else
11265                         phy->flags |= FLAGS_MDC_MDIO_WA_B0;
11266         } else {
11267                 switch (switch_cfg) {
11268                 case SWITCH_CFG_1G:
11269                         phy_addr = REG_RD(bp,
11270                                           NIG_REG_SERDES0_CTRL_PHY_ADDR +
11271                                           port * 0x10);
11272                         *phy = phy_serdes;
11273                         break;
11274                 case SWITCH_CFG_10G:
11275                         phy_addr = REG_RD(bp,
11276                                           NIG_REG_XGXS0_CTRL_PHY_ADDR +
11277                                           port * 0x18);
11278                         *phy = phy_xgxs;
11279                         break;
11280                 default:
11281                         DP(NETIF_MSG_LINK, "Invalid switch_cfg\n");
11282                         return -EINVAL;
11283                 }
11284         }
11285         phy->addr = (u8)phy_addr;
11286         phy->mdio_ctrl = bnx2x_get_emac_base(bp,
11287                                             SHARED_HW_CFG_MDC_MDIO_ACCESS1_BOTH,
11288                                             port);
11289         if (CHIP_IS_E2(bp))
11290                 phy->def_md_devad = E2_DEFAULT_PHY_DEV_ADDR;
11291         else
11292                 phy->def_md_devad = DEFAULT_PHY_DEV_ADDR;
11293
11294         DP(NETIF_MSG_LINK, "Internal phy port=%d, addr=0x%x, mdio_ctl=0x%x\n",
11295                    port, phy->addr, phy->mdio_ctrl);
11296
11297         bnx2x_populate_preemphasis(bp, shmem_base, phy, port, INT_PHY);
11298         return 0;
11299 }
11300
11301 static int bnx2x_populate_ext_phy(struct bnx2x *bp,
11302                                   u8 phy_index,
11303                                   u32 shmem_base,
11304                                   u32 shmem2_base,
11305                                   u8 port,
11306                                   struct bnx2x_phy *phy)
11307 {
11308         u32 ext_phy_config, phy_type, config2;
11309         u32 mdc_mdio_access = SHARED_HW_CFG_MDC_MDIO_ACCESS1_BOTH;
11310         ext_phy_config = bnx2x_get_ext_phy_config(bp, shmem_base,
11311                                                   phy_index, port);
11312         phy_type = XGXS_EXT_PHY_TYPE(ext_phy_config);
11313         /* Select the phy type */
11314         switch (phy_type) {
11315         case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8073:
11316                 mdc_mdio_access = SHARED_HW_CFG_MDC_MDIO_ACCESS1_SWAPPED;
11317                 *phy = phy_8073;
11318                 break;
11319         case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8705:
11320                 *phy = phy_8705;
11321                 break;
11322         case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8706:
11323                 *phy = phy_8706;
11324                 break;
11325         case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8726:
11326                 mdc_mdio_access = SHARED_HW_CFG_MDC_MDIO_ACCESS1_EMAC1;
11327                 *phy = phy_8726;
11328                 break;
11329         case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8727_NOC:
11330                 /* BCM8727_NOC => BCM8727 no over current */
11331                 mdc_mdio_access = SHARED_HW_CFG_MDC_MDIO_ACCESS1_EMAC1;
11332                 *phy = phy_8727;
11333                 phy->flags |= FLAGS_NOC;
11334                 break;
11335         case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8722:
11336         case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8727:
11337                 mdc_mdio_access = SHARED_HW_CFG_MDC_MDIO_ACCESS1_EMAC1;
11338                 *phy = phy_8727;
11339                 break;
11340         case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8481:
11341                 *phy = phy_8481;
11342                 break;
11343         case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM84823:
11344                 *phy = phy_84823;
11345                 break;
11346         case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM84833:
11347                 *phy = phy_84833;
11348                 break;
11349         case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM54616:
11350         case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM54618SE:
11351                 *phy = phy_54618se;
11352                 break;
11353         case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_SFX7101:
11354                 *phy = phy_7101;
11355                 break;
11356         case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_FAILURE:
11357                 *phy = phy_null;
11358                 return -EINVAL;
11359         default:
11360                 *phy = phy_null;
11361                 return 0;
11362         }
11363
11364         phy->addr = XGXS_EXT_PHY_ADDR(ext_phy_config);
11365         bnx2x_populate_preemphasis(bp, shmem_base, phy, port, phy_index);
11366
11367         /*
11368          * The shmem address of the phy version is located on different
11369          * structures. In case this structure is too old, do not set
11370          * the address
11371          */
11372         config2 = REG_RD(bp, shmem_base + offsetof(struct shmem_region,
11373                                         dev_info.shared_hw_config.config2));
11374         if (phy_index == EXT_PHY1) {
11375                 phy->ver_addr = shmem_base + offsetof(struct shmem_region,
11376                                 port_mb[port].ext_phy_fw_version);
11377
11378                 /* Check specific mdc mdio settings */
11379                 if (config2 & SHARED_HW_CFG_MDC_MDIO_ACCESS1_MASK)
11380                         mdc_mdio_access = config2 &
11381                         SHARED_HW_CFG_MDC_MDIO_ACCESS1_MASK;
11382         } else {
11383                 u32 size = REG_RD(bp, shmem2_base);
11384
11385                 if (size >
11386                     offsetof(struct shmem2_region, ext_phy_fw_version2)) {
11387                         phy->ver_addr = shmem2_base +
11388                             offsetof(struct shmem2_region,
11389                                      ext_phy_fw_version2[port]);
11390                 }
11391                 /* Check specific mdc mdio settings */
11392                 if (config2 & SHARED_HW_CFG_MDC_MDIO_ACCESS2_MASK)
11393                         mdc_mdio_access = (config2 &
11394                         SHARED_HW_CFG_MDC_MDIO_ACCESS2_MASK) >>
11395                         (SHARED_HW_CFG_MDC_MDIO_ACCESS2_SHIFT -
11396                          SHARED_HW_CFG_MDC_MDIO_ACCESS1_SHIFT);
11397         }
11398         phy->mdio_ctrl = bnx2x_get_emac_base(bp, mdc_mdio_access, port);
11399
11400         /*
11401          * In case mdc/mdio_access of the external phy is different than the
11402          * mdc/mdio access of the XGXS, a HW lock must be taken in each access
11403          * to prevent one port interfere with another port's CL45 operations.
11404          */
11405         if (mdc_mdio_access != SHARED_HW_CFG_MDC_MDIO_ACCESS1_BOTH)
11406                 phy->flags |= FLAGS_HW_LOCK_REQUIRED;
11407         DP(NETIF_MSG_LINK, "phy_type 0x%x port %d found in index %d\n",
11408                    phy_type, port, phy_index);
11409         DP(NETIF_MSG_LINK, "             addr=0x%x, mdio_ctl=0x%x\n",
11410                    phy->addr, phy->mdio_ctrl);
11411         return 0;
11412 }
11413
11414 static int bnx2x_populate_phy(struct bnx2x *bp, u8 phy_index, u32 shmem_base,
11415                               u32 shmem2_base, u8 port, struct bnx2x_phy *phy)
11416 {
11417         int status = 0;
11418         phy->type = PORT_HW_CFG_XGXS_EXT_PHY_TYPE_NOT_CONN;
11419         if (phy_index == INT_PHY)
11420                 return bnx2x_populate_int_phy(bp, shmem_base, port, phy);
11421         status = bnx2x_populate_ext_phy(bp, phy_index, shmem_base, shmem2_base,
11422                                         port, phy);
11423         return status;
11424 }
11425
11426 static void bnx2x_phy_def_cfg(struct link_params *params,
11427                               struct bnx2x_phy *phy,
11428                               u8 phy_index)
11429 {
11430         struct bnx2x *bp = params->bp;
11431         u32 link_config;
11432         /* Populate the default phy configuration for MF mode */
11433         if (phy_index == EXT_PHY2) {
11434                 link_config = REG_RD(bp, params->shmem_base +
11435                                      offsetof(struct shmem_region, dev_info.
11436                         port_feature_config[params->port].link_config2));
11437                 phy->speed_cap_mask = REG_RD(bp, params->shmem_base +
11438                                              offsetof(struct shmem_region,
11439                                                       dev_info.
11440                         port_hw_config[params->port].speed_capability_mask2));
11441         } else {
11442                 link_config = REG_RD(bp, params->shmem_base +
11443                                      offsetof(struct shmem_region, dev_info.
11444                                 port_feature_config[params->port].link_config));
11445                 phy->speed_cap_mask = REG_RD(bp, params->shmem_base +
11446                                              offsetof(struct shmem_region,
11447                                                       dev_info.
11448                         port_hw_config[params->port].speed_capability_mask));
11449         }
11450         DP(NETIF_MSG_LINK,
11451            "Default config phy idx %x cfg 0x%x speed_cap_mask 0x%x\n",
11452            phy_index, link_config, phy->speed_cap_mask);
11453
11454         phy->req_duplex = DUPLEX_FULL;
11455         switch (link_config  & PORT_FEATURE_LINK_SPEED_MASK) {
11456         case PORT_FEATURE_LINK_SPEED_10M_HALF:
11457                 phy->req_duplex = DUPLEX_HALF;
11458         case PORT_FEATURE_LINK_SPEED_10M_FULL:
11459                 phy->req_line_speed = SPEED_10;
11460                 break;
11461         case PORT_FEATURE_LINK_SPEED_100M_HALF:
11462                 phy->req_duplex = DUPLEX_HALF;
11463         case PORT_FEATURE_LINK_SPEED_100M_FULL:
11464                 phy->req_line_speed = SPEED_100;
11465                 break;
11466         case PORT_FEATURE_LINK_SPEED_1G:
11467                 phy->req_line_speed = SPEED_1000;
11468                 break;
11469         case PORT_FEATURE_LINK_SPEED_2_5G:
11470                 phy->req_line_speed = SPEED_2500;
11471                 break;
11472         case PORT_FEATURE_LINK_SPEED_10G_CX4:
11473                 phy->req_line_speed = SPEED_10000;
11474                 break;
11475         default:
11476                 phy->req_line_speed = SPEED_AUTO_NEG;
11477                 break;
11478         }
11479
11480         switch (link_config  & PORT_FEATURE_FLOW_CONTROL_MASK) {
11481         case PORT_FEATURE_FLOW_CONTROL_AUTO:
11482                 phy->req_flow_ctrl = BNX2X_FLOW_CTRL_AUTO;
11483                 break;
11484         case PORT_FEATURE_FLOW_CONTROL_TX:
11485                 phy->req_flow_ctrl = BNX2X_FLOW_CTRL_TX;
11486                 break;
11487         case PORT_FEATURE_FLOW_CONTROL_RX:
11488                 phy->req_flow_ctrl = BNX2X_FLOW_CTRL_RX;
11489                 break;
11490         case PORT_FEATURE_FLOW_CONTROL_BOTH:
11491                 phy->req_flow_ctrl = BNX2X_FLOW_CTRL_BOTH;
11492                 break;
11493         default:
11494                 phy->req_flow_ctrl = BNX2X_FLOW_CTRL_NONE;
11495                 break;
11496         }
11497 }
11498
11499 u32 bnx2x_phy_selection(struct link_params *params)
11500 {
11501         u32 phy_config_swapped, prio_cfg;
11502         u32 return_cfg = PORT_HW_CFG_PHY_SELECTION_HARDWARE_DEFAULT;
11503
11504         phy_config_swapped = params->multi_phy_config &
11505                 PORT_HW_CFG_PHY_SWAPPED_ENABLED;
11506
11507         prio_cfg = params->multi_phy_config &
11508                         PORT_HW_CFG_PHY_SELECTION_MASK;
11509
11510         if (phy_config_swapped) {
11511                 switch (prio_cfg) {
11512                 case PORT_HW_CFG_PHY_SELECTION_FIRST_PHY_PRIORITY:
11513                      return_cfg = PORT_HW_CFG_PHY_SELECTION_SECOND_PHY_PRIORITY;
11514                      break;
11515                 case PORT_HW_CFG_PHY_SELECTION_SECOND_PHY_PRIORITY:
11516                      return_cfg = PORT_HW_CFG_PHY_SELECTION_FIRST_PHY_PRIORITY;
11517                      break;
11518                 case PORT_HW_CFG_PHY_SELECTION_SECOND_PHY:
11519                      return_cfg = PORT_HW_CFG_PHY_SELECTION_FIRST_PHY;
11520                      break;
11521                 case PORT_HW_CFG_PHY_SELECTION_FIRST_PHY:
11522                      return_cfg = PORT_HW_CFG_PHY_SELECTION_SECOND_PHY;
11523                      break;
11524                 }
11525         } else
11526                 return_cfg = prio_cfg;
11527
11528         return return_cfg;
11529 }
11530
11531
11532 int bnx2x_phy_probe(struct link_params *params)
11533 {
11534         u8 phy_index, actual_phy_idx, link_cfg_idx;
11535         u32 phy_config_swapped, sync_offset, media_types;
11536         struct bnx2x *bp = params->bp;
11537         struct bnx2x_phy *phy;
11538         params->num_phys = 0;
11539         DP(NETIF_MSG_LINK, "Begin phy probe\n");
11540         phy_config_swapped = params->multi_phy_config &
11541                 PORT_HW_CFG_PHY_SWAPPED_ENABLED;
11542
11543         for (phy_index = INT_PHY; phy_index < MAX_PHYS;
11544               phy_index++) {
11545                 link_cfg_idx = LINK_CONFIG_IDX(phy_index);
11546                 actual_phy_idx = phy_index;
11547                 if (phy_config_swapped) {
11548                         if (phy_index == EXT_PHY1)
11549                                 actual_phy_idx = EXT_PHY2;
11550                         else if (phy_index == EXT_PHY2)
11551                                 actual_phy_idx = EXT_PHY1;
11552                 }
11553                 DP(NETIF_MSG_LINK, "phy_config_swapped %x, phy_index %x,"
11554                                " actual_phy_idx %x\n", phy_config_swapped,
11555                            phy_index, actual_phy_idx);
11556                 phy = &params->phy[actual_phy_idx];
11557                 if (bnx2x_populate_phy(bp, phy_index, params->shmem_base,
11558                                        params->shmem2_base, params->port,
11559                                        phy) != 0) {
11560                         params->num_phys = 0;
11561                         DP(NETIF_MSG_LINK, "phy probe failed in phy index %d\n",
11562                                    phy_index);
11563                         for (phy_index = INT_PHY;
11564                               phy_index < MAX_PHYS;
11565                               phy_index++)
11566                                 *phy = phy_null;
11567                         return -EINVAL;
11568                 }
11569                 if (phy->type == PORT_HW_CFG_XGXS_EXT_PHY_TYPE_NOT_CONN)
11570                         break;
11571
11572                 sync_offset = params->shmem_base +
11573                         offsetof(struct shmem_region,
11574                         dev_info.port_hw_config[params->port].media_type);
11575                 media_types = REG_RD(bp, sync_offset);
11576
11577                 /*
11578                  * Update media type for non-PMF sync only for the first time
11579                  * In case the media type changes afterwards, it will be updated
11580                  * using the update_status function
11581                  */
11582                 if ((media_types & (PORT_HW_CFG_MEDIA_TYPE_PHY0_MASK <<
11583                                     (PORT_HW_CFG_MEDIA_TYPE_PHY1_SHIFT *
11584                                      actual_phy_idx))) == 0) {
11585                         media_types |= ((phy->media_type &
11586                                         PORT_HW_CFG_MEDIA_TYPE_PHY0_MASK) <<
11587                                 (PORT_HW_CFG_MEDIA_TYPE_PHY1_SHIFT *
11588                                  actual_phy_idx));
11589                 }
11590                 REG_WR(bp, sync_offset, media_types);
11591
11592                 bnx2x_phy_def_cfg(params, phy, phy_index);
11593                 params->num_phys++;
11594         }
11595
11596         DP(NETIF_MSG_LINK, "End phy probe. #phys found %x\n", params->num_phys);
11597         return 0;
11598 }
11599
11600 void bnx2x_init_bmac_loopback(struct link_params *params,
11601                               struct link_vars *vars)
11602 {
11603         struct bnx2x *bp = params->bp;
11604                 vars->link_up = 1;
11605                 vars->line_speed = SPEED_10000;
11606                 vars->duplex = DUPLEX_FULL;
11607                 vars->flow_ctrl = BNX2X_FLOW_CTRL_NONE;
11608                 vars->mac_type = MAC_TYPE_BMAC;
11609
11610                 vars->phy_flags = PHY_XGXS_FLAG;
11611
11612                 bnx2x_xgxs_deassert(params);
11613
11614                 /* set bmac loopback */
11615                 bnx2x_bmac_enable(params, vars, 1);
11616
11617                 REG_WR(bp, NIG_REG_EGRESS_DRAIN0_MODE + params->port*4, 0);
11618 }
11619
11620 void bnx2x_init_emac_loopback(struct link_params *params,
11621                               struct link_vars *vars)
11622 {
11623         struct bnx2x *bp = params->bp;
11624                 vars->link_up = 1;
11625                 vars->line_speed = SPEED_1000;
11626                 vars->duplex = DUPLEX_FULL;
11627                 vars->flow_ctrl = BNX2X_FLOW_CTRL_NONE;
11628                 vars->mac_type = MAC_TYPE_EMAC;
11629
11630                 vars->phy_flags = PHY_XGXS_FLAG;
11631
11632                 bnx2x_xgxs_deassert(params);
11633                 /* set bmac loopback */
11634                 bnx2x_emac_enable(params, vars, 1);
11635                 bnx2x_emac_program(params, vars);
11636                 REG_WR(bp, NIG_REG_EGRESS_DRAIN0_MODE + params->port*4, 0);
11637 }
11638
11639 void bnx2x_init_xmac_loopback(struct link_params *params,
11640                               struct link_vars *vars)
11641 {
11642         struct bnx2x *bp = params->bp;
11643         vars->link_up = 1;
11644         if (!params->req_line_speed[0])
11645                 vars->line_speed = SPEED_10000;
11646         else
11647                 vars->line_speed = params->req_line_speed[0];
11648         vars->duplex = DUPLEX_FULL;
11649         vars->flow_ctrl = BNX2X_FLOW_CTRL_NONE;
11650         vars->mac_type = MAC_TYPE_XMAC;
11651         vars->phy_flags = PHY_XGXS_FLAG;
11652         /*
11653          * Set WC to loopback mode since link is required to provide clock
11654          * to the XMAC in 20G mode
11655          */
11656         bnx2x_set_aer_mmd(params, &params->phy[0]);
11657         bnx2x_warpcore_reset_lane(bp, &params->phy[0], 0);
11658         params->phy[INT_PHY].config_loopback(
11659                         &params->phy[INT_PHY],
11660                         params);
11661
11662         bnx2x_xmac_enable(params, vars, 1);
11663         REG_WR(bp, NIG_REG_EGRESS_DRAIN0_MODE + params->port*4, 0);
11664 }
11665
11666 void bnx2x_init_umac_loopback(struct link_params *params,
11667                               struct link_vars *vars)
11668 {
11669         struct bnx2x *bp = params->bp;
11670         vars->link_up = 1;
11671         vars->line_speed = SPEED_1000;
11672         vars->duplex = DUPLEX_FULL;
11673         vars->flow_ctrl = BNX2X_FLOW_CTRL_NONE;
11674         vars->mac_type = MAC_TYPE_UMAC;
11675         vars->phy_flags = PHY_XGXS_FLAG;
11676         bnx2x_umac_enable(params, vars, 1);
11677
11678         REG_WR(bp, NIG_REG_EGRESS_DRAIN0_MODE + params->port*4, 0);
11679 }
11680
11681 void bnx2x_init_xgxs_loopback(struct link_params *params,
11682                               struct link_vars *vars)
11683 {
11684         struct bnx2x *bp = params->bp;
11685                 vars->link_up = 1;
11686                 vars->flow_ctrl = BNX2X_FLOW_CTRL_NONE;
11687                 vars->duplex = DUPLEX_FULL;
11688         if (params->req_line_speed[0] == SPEED_1000)
11689                         vars->line_speed = SPEED_1000;
11690         else
11691                         vars->line_speed = SPEED_10000;
11692
11693         if (!USES_WARPCORE(bp))
11694                 bnx2x_xgxs_deassert(params);
11695         bnx2x_link_initialize(params, vars);
11696
11697         if (params->req_line_speed[0] == SPEED_1000) {
11698                 if (USES_WARPCORE(bp))
11699                         bnx2x_umac_enable(params, vars, 0);
11700                 else {
11701                         bnx2x_emac_program(params, vars);
11702                         bnx2x_emac_enable(params, vars, 0);
11703                 }
11704         } else {
11705                 if (USES_WARPCORE(bp))
11706                         bnx2x_xmac_enable(params, vars, 0);
11707                 else
11708                         bnx2x_bmac_enable(params, vars, 0);
11709         }
11710
11711                 if (params->loopback_mode == LOOPBACK_XGXS) {
11712                         /* set 10G XGXS loopback */
11713                         params->phy[INT_PHY].config_loopback(
11714                                 &params->phy[INT_PHY],
11715                                 params);
11716
11717                 } else {
11718                         /* set external phy loopback */
11719                         u8 phy_index;
11720                         for (phy_index = EXT_PHY1;
11721                               phy_index < params->num_phys; phy_index++) {
11722                                 if (params->phy[phy_index].config_loopback)
11723                                         params->phy[phy_index].config_loopback(
11724                                                 &params->phy[phy_index],
11725                                                 params);
11726                         }
11727                 }
11728                 REG_WR(bp, NIG_REG_EGRESS_DRAIN0_MODE + params->port*4, 0);
11729
11730         bnx2x_set_led(params, vars, LED_MODE_OPER, vars->line_speed);
11731 }
11732
11733 int bnx2x_phy_init(struct link_params *params, struct link_vars *vars)
11734 {
11735         struct bnx2x *bp = params->bp;
11736         DP(NETIF_MSG_LINK, "Phy Initialization started\n");
11737         DP(NETIF_MSG_LINK, "(1) req_speed %d, req_flowctrl %d\n",
11738                    params->req_line_speed[0], params->req_flow_ctrl[0]);
11739         DP(NETIF_MSG_LINK, "(2) req_speed %d, req_flowctrl %d\n",
11740                    params->req_line_speed[1], params->req_flow_ctrl[1]);
11741         vars->link_status = 0;
11742         vars->phy_link_up = 0;
11743         vars->link_up = 0;
11744         vars->line_speed = 0;
11745         vars->duplex = DUPLEX_FULL;
11746         vars->flow_ctrl = BNX2X_FLOW_CTRL_NONE;
11747         vars->mac_type = MAC_TYPE_NONE;
11748         vars->phy_flags = 0;
11749
11750         /* disable attentions */
11751         bnx2x_bits_dis(bp, NIG_REG_MASK_INTERRUPT_PORT0 + params->port*4,
11752                        (NIG_MASK_XGXS0_LINK_STATUS |
11753                         NIG_MASK_XGXS0_LINK10G |
11754                         NIG_MASK_SERDES0_LINK_STATUS |
11755                         NIG_MASK_MI_INT));
11756
11757         bnx2x_emac_init(params, vars);
11758
11759         if (params->num_phys == 0) {
11760                 DP(NETIF_MSG_LINK, "No phy found for initialization !!\n");
11761                 return -EINVAL;
11762         }
11763         set_phy_vars(params, vars);
11764
11765         DP(NETIF_MSG_LINK, "Num of phys on board: %d\n", params->num_phys);
11766         switch (params->loopback_mode) {
11767         case LOOPBACK_BMAC:
11768                 bnx2x_init_bmac_loopback(params, vars);
11769                 break;
11770         case LOOPBACK_EMAC:
11771                 bnx2x_init_emac_loopback(params, vars);
11772                 break;
11773         case LOOPBACK_XMAC:
11774                 bnx2x_init_xmac_loopback(params, vars);
11775                 break;
11776         case LOOPBACK_UMAC:
11777                 bnx2x_init_umac_loopback(params, vars);
11778                 break;
11779         case LOOPBACK_XGXS:
11780         case LOOPBACK_EXT_PHY:
11781                 bnx2x_init_xgxs_loopback(params, vars);
11782                 break;
11783         default:
11784                 if (!CHIP_IS_E3(bp)) {
11785                         if (params->switch_cfg == SWITCH_CFG_10G)
11786                                 bnx2x_xgxs_deassert(params);
11787                         else
11788                                 bnx2x_serdes_deassert(bp, params->port);
11789                 }
11790                 bnx2x_link_initialize(params, vars);
11791                 msleep(30);
11792                 bnx2x_link_int_enable(params);
11793                 break;
11794         }
11795         return 0;
11796 }
11797
11798 int bnx2x_link_reset(struct link_params *params, struct link_vars *vars,
11799                      u8 reset_ext_phy)
11800 {
11801         struct bnx2x *bp = params->bp;
11802         u8 phy_index, port = params->port, clear_latch_ind = 0;
11803         DP(NETIF_MSG_LINK, "Resetting the link of port %d\n", port);
11804         /* disable attentions */
11805         vars->link_status = 0;
11806         bnx2x_update_mng(params, vars->link_status);
11807         bnx2x_bits_dis(bp, NIG_REG_MASK_INTERRUPT_PORT0 + port*4,
11808                        (NIG_MASK_XGXS0_LINK_STATUS |
11809                         NIG_MASK_XGXS0_LINK10G |
11810                         NIG_MASK_SERDES0_LINK_STATUS |
11811                         NIG_MASK_MI_INT));
11812
11813         /* activate nig drain */
11814         REG_WR(bp, NIG_REG_EGRESS_DRAIN0_MODE + port*4, 1);
11815
11816         /* disable nig egress interface */
11817         if (!CHIP_IS_E3(bp)) {
11818                 REG_WR(bp, NIG_REG_BMAC0_OUT_EN + port*4, 0);
11819                 REG_WR(bp, NIG_REG_EGRESS_EMAC0_OUT_EN + port*4, 0);
11820         }
11821
11822         /* Stop BigMac rx */
11823         if (!CHIP_IS_E3(bp))
11824                 bnx2x_bmac_rx_disable(bp, port);
11825         else {
11826                 bnx2x_xmac_disable(params);
11827                 bnx2x_umac_disable(params);
11828         }
11829         /* disable emac */
11830         if (!CHIP_IS_E3(bp))
11831                 REG_WR(bp, NIG_REG_NIG_EMAC0_EN + port*4, 0);
11832
11833         msleep(10);
11834         /* The PHY reset is controlled by GPIO 1
11835          * Hold it as vars low
11836          */
11837          /* clear link led */
11838         bnx2x_set_led(params, vars, LED_MODE_OFF, 0);
11839
11840         if (reset_ext_phy) {
11841                 bnx2x_set_mdio_clk(bp, params->chip_id, port);
11842                 for (phy_index = EXT_PHY1; phy_index < params->num_phys;
11843                       phy_index++) {
11844                         if (params->phy[phy_index].link_reset) {
11845                                 bnx2x_set_aer_mmd(params,
11846                                                   &params->phy[phy_index]);
11847                                 params->phy[phy_index].link_reset(
11848                                         &params->phy[phy_index],
11849                                         params);
11850                         }
11851                         if (params->phy[phy_index].flags &
11852                             FLAGS_REARM_LATCH_SIGNAL)
11853                                 clear_latch_ind = 1;
11854                 }
11855         }
11856
11857         if (clear_latch_ind) {
11858                 /* Clear latching indication */
11859                 bnx2x_rearm_latch_signal(bp, port, 0);
11860                 bnx2x_bits_dis(bp, NIG_REG_LATCH_BC_0 + port*4,
11861                                1 << NIG_LATCH_BC_ENABLE_MI_INT);
11862         }
11863         if (params->phy[INT_PHY].link_reset)
11864                 params->phy[INT_PHY].link_reset(
11865                         &params->phy[INT_PHY], params);
11866
11867         /* disable nig ingress interface */
11868         if (!CHIP_IS_E3(bp)) {
11869                 /* reset BigMac */
11870                 REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_2_CLEAR,
11871                        (MISC_REGISTERS_RESET_REG_2_RST_BMAC0 << port));
11872                 REG_WR(bp, NIG_REG_BMAC0_IN_EN + port*4, 0);
11873                 REG_WR(bp, NIG_REG_EMAC0_IN_EN + port*4, 0);
11874         } else {
11875                 u32 xmac_base = (params->port) ? GRCBASE_XMAC1 : GRCBASE_XMAC0;
11876                 bnx2x_set_xumac_nig(params, 0, 0);
11877                 if (REG_RD(bp, MISC_REG_RESET_REG_2) &
11878                     MISC_REGISTERS_RESET_REG_2_XMAC)
11879                         REG_WR(bp, xmac_base + XMAC_REG_CTRL,
11880                                XMAC_CTRL_REG_SOFT_RESET);
11881         }
11882         vars->link_up = 0;
11883         vars->phy_flags = 0;
11884         return 0;
11885 }
11886
11887 /****************************************************************************/
11888 /*                              Common function                             */
11889 /****************************************************************************/
11890 static int bnx2x_8073_common_init_phy(struct bnx2x *bp,
11891                                       u32 shmem_base_path[],
11892                                       u32 shmem2_base_path[], u8 phy_index,
11893                                       u32 chip_id)
11894 {
11895         struct bnx2x_phy phy[PORT_MAX];
11896         struct bnx2x_phy *phy_blk[PORT_MAX];
11897         u16 val;
11898         s8 port = 0;
11899         s8 port_of_path = 0;
11900         u32 swap_val, swap_override;
11901         swap_val = REG_RD(bp,  NIG_REG_PORT_SWAP);
11902         swap_override = REG_RD(bp,  NIG_REG_STRAP_OVERRIDE);
11903         port ^= (swap_val && swap_override);
11904         bnx2x_ext_phy_hw_reset(bp, port);
11905         /* PART1 - Reset both phys */
11906         for (port = PORT_MAX - 1; port >= PORT_0; port--) {
11907                 u32 shmem_base, shmem2_base;
11908                 /* In E2, same phy is using for port0 of the two paths */
11909                 if (CHIP_IS_E1x(bp)) {
11910                         shmem_base = shmem_base_path[0];
11911                         shmem2_base = shmem2_base_path[0];
11912                         port_of_path = port;
11913                 } else {
11914                         shmem_base = shmem_base_path[port];
11915                         shmem2_base = shmem2_base_path[port];
11916                         port_of_path = 0;
11917                 }
11918
11919                 /* Extract the ext phy address for the port */
11920                 if (bnx2x_populate_phy(bp, phy_index, shmem_base, shmem2_base,
11921                                        port_of_path, &phy[port]) !=
11922                     0) {
11923                         DP(NETIF_MSG_LINK, "populate_phy failed\n");
11924                         return -EINVAL;
11925                 }
11926                 /* disable attentions */
11927                 bnx2x_bits_dis(bp, NIG_REG_MASK_INTERRUPT_PORT0 +
11928                                port_of_path*4,
11929                                (NIG_MASK_XGXS0_LINK_STATUS |
11930                                 NIG_MASK_XGXS0_LINK10G |
11931                                 NIG_MASK_SERDES0_LINK_STATUS |
11932                                 NIG_MASK_MI_INT));
11933
11934                 /* Need to take the phy out of low power mode in order
11935                         to write to access its registers */
11936                 bnx2x_set_gpio(bp, MISC_REGISTERS_GPIO_2,
11937                                MISC_REGISTERS_GPIO_OUTPUT_HIGH,
11938                                port);
11939
11940                 /* Reset the phy */
11941                 bnx2x_cl45_write(bp, &phy[port],
11942                                  MDIO_PMA_DEVAD,
11943                                  MDIO_PMA_REG_CTRL,
11944                                  1<<15);
11945         }
11946
11947         /* Add delay of 150ms after reset */
11948         msleep(150);
11949
11950         if (phy[PORT_0].addr & 0x1) {
11951                 phy_blk[PORT_0] = &(phy[PORT_1]);
11952                 phy_blk[PORT_1] = &(phy[PORT_0]);
11953         } else {
11954                 phy_blk[PORT_0] = &(phy[PORT_0]);
11955                 phy_blk[PORT_1] = &(phy[PORT_1]);
11956         }
11957
11958         /* PART2 - Download firmware to both phys */
11959         for (port = PORT_MAX - 1; port >= PORT_0; port--) {
11960                 if (CHIP_IS_E1x(bp))
11961                         port_of_path = port;
11962                 else
11963                         port_of_path = 0;
11964
11965                 DP(NETIF_MSG_LINK, "Loading spirom for phy address 0x%x\n",
11966                            phy_blk[port]->addr);
11967                 if (bnx2x_8073_8727_external_rom_boot(bp, phy_blk[port],
11968                                                       port_of_path))
11969                         return -EINVAL;
11970
11971                 /* Only set bit 10 = 1 (Tx power down) */
11972                 bnx2x_cl45_read(bp, phy_blk[port],
11973                                 MDIO_PMA_DEVAD,
11974                                 MDIO_PMA_REG_TX_POWER_DOWN, &val);
11975
11976                 /* Phase1 of TX_POWER_DOWN reset */
11977                 bnx2x_cl45_write(bp, phy_blk[port],
11978                                  MDIO_PMA_DEVAD,
11979                                  MDIO_PMA_REG_TX_POWER_DOWN,
11980                                  (val | 1<<10));
11981         }
11982
11983         /*
11984          * Toggle Transmitter: Power down and then up with 600ms delay
11985          * between
11986          */
11987         msleep(600);
11988
11989         /* PART3 - complete TX_POWER_DOWN process, and set GPIO2 back to low */
11990         for (port = PORT_MAX - 1; port >= PORT_0; port--) {
11991                 /* Phase2 of POWER_DOWN_RESET */
11992                 /* Release bit 10 (Release Tx power down) */
11993                 bnx2x_cl45_read(bp, phy_blk[port],
11994                                 MDIO_PMA_DEVAD,
11995                                 MDIO_PMA_REG_TX_POWER_DOWN, &val);
11996
11997                 bnx2x_cl45_write(bp, phy_blk[port],
11998                                 MDIO_PMA_DEVAD,
11999                                 MDIO_PMA_REG_TX_POWER_DOWN, (val & (~(1<<10))));
12000                 msleep(15);
12001
12002                 /* Read modify write the SPI-ROM version select register */
12003                 bnx2x_cl45_read(bp, phy_blk[port],
12004                                 MDIO_PMA_DEVAD,
12005                                 MDIO_PMA_REG_EDC_FFE_MAIN, &val);
12006                 bnx2x_cl45_write(bp, phy_blk[port],
12007                                  MDIO_PMA_DEVAD,
12008                                  MDIO_PMA_REG_EDC_FFE_MAIN, (val | (1<<12)));
12009
12010                 /* set GPIO2 back to LOW */
12011                 bnx2x_set_gpio(bp, MISC_REGISTERS_GPIO_2,
12012                                MISC_REGISTERS_GPIO_OUTPUT_LOW, port);
12013         }
12014         return 0;
12015 }
12016 static int bnx2x_8726_common_init_phy(struct bnx2x *bp,
12017                                       u32 shmem_base_path[],
12018                                       u32 shmem2_base_path[], u8 phy_index,
12019                                       u32 chip_id)
12020 {
12021         u32 val;
12022         s8 port;
12023         struct bnx2x_phy phy;
12024         /* Use port1 because of the static port-swap */
12025         /* Enable the module detection interrupt */
12026         val = REG_RD(bp, MISC_REG_GPIO_EVENT_EN);
12027         val |= ((1<<MISC_REGISTERS_GPIO_3)|
12028                 (1<<(MISC_REGISTERS_GPIO_3 + MISC_REGISTERS_GPIO_PORT_SHIFT)));
12029         REG_WR(bp, MISC_REG_GPIO_EVENT_EN, val);
12030
12031         bnx2x_ext_phy_hw_reset(bp, 0);
12032         msleep(5);
12033         for (port = 0; port < PORT_MAX; port++) {
12034                 u32 shmem_base, shmem2_base;
12035
12036                 /* In E2, same phy is using for port0 of the two paths */
12037                 if (CHIP_IS_E1x(bp)) {
12038                         shmem_base = shmem_base_path[0];
12039                         shmem2_base = shmem2_base_path[0];
12040                 } else {
12041                         shmem_base = shmem_base_path[port];
12042                         shmem2_base = shmem2_base_path[port];
12043                 }
12044                 /* Extract the ext phy address for the port */
12045                 if (bnx2x_populate_phy(bp, phy_index, shmem_base, shmem2_base,
12046                                        port, &phy) !=
12047                     0) {
12048                         DP(NETIF_MSG_LINK, "populate phy failed\n");
12049                         return -EINVAL;
12050                 }
12051
12052                 /* Reset phy*/
12053                 bnx2x_cl45_write(bp, &phy,
12054                                  MDIO_PMA_DEVAD, MDIO_PMA_REG_GEN_CTRL, 0x0001);
12055
12056
12057                 /* Set fault module detected LED on */
12058                 bnx2x_set_gpio(bp, MISC_REGISTERS_GPIO_0,
12059                                MISC_REGISTERS_GPIO_HIGH,
12060                                port);
12061         }
12062
12063         return 0;
12064 }
12065 static void bnx2x_get_ext_phy_reset_gpio(struct bnx2x *bp, u32 shmem_base,
12066                                          u8 *io_gpio, u8 *io_port)
12067 {
12068
12069         u32 phy_gpio_reset = REG_RD(bp, shmem_base +
12070                                           offsetof(struct shmem_region,
12071                                 dev_info.port_hw_config[PORT_0].default_cfg));
12072         switch (phy_gpio_reset) {
12073         case PORT_HW_CFG_EXT_PHY_GPIO_RST_GPIO0_P0:
12074                 *io_gpio = 0;
12075                 *io_port = 0;
12076                 break;
12077         case PORT_HW_CFG_EXT_PHY_GPIO_RST_GPIO1_P0:
12078                 *io_gpio = 1;
12079                 *io_port = 0;
12080                 break;
12081         case PORT_HW_CFG_EXT_PHY_GPIO_RST_GPIO2_P0:
12082                 *io_gpio = 2;
12083                 *io_port = 0;
12084                 break;
12085         case PORT_HW_CFG_EXT_PHY_GPIO_RST_GPIO3_P0:
12086                 *io_gpio = 3;
12087                 *io_port = 0;
12088                 break;
12089         case PORT_HW_CFG_EXT_PHY_GPIO_RST_GPIO0_P1:
12090                 *io_gpio = 0;
12091                 *io_port = 1;
12092                 break;
12093         case PORT_HW_CFG_EXT_PHY_GPIO_RST_GPIO1_P1:
12094                 *io_gpio = 1;
12095                 *io_port = 1;
12096                 break;
12097         case PORT_HW_CFG_EXT_PHY_GPIO_RST_GPIO2_P1:
12098                 *io_gpio = 2;
12099                 *io_port = 1;
12100                 break;
12101         case PORT_HW_CFG_EXT_PHY_GPIO_RST_GPIO3_P1:
12102                 *io_gpio = 3;
12103                 *io_port = 1;
12104                 break;
12105         default:
12106                 /* Don't override the io_gpio and io_port */
12107                 break;
12108         }
12109 }
12110
12111 static int bnx2x_8727_common_init_phy(struct bnx2x *bp,
12112                                       u32 shmem_base_path[],
12113                                       u32 shmem2_base_path[], u8 phy_index,
12114                                       u32 chip_id)
12115 {
12116         s8 port, reset_gpio;
12117         u32 swap_val, swap_override;
12118         struct bnx2x_phy phy[PORT_MAX];
12119         struct bnx2x_phy *phy_blk[PORT_MAX];
12120         s8 port_of_path;
12121         swap_val = REG_RD(bp, NIG_REG_PORT_SWAP);
12122         swap_override = REG_RD(bp, NIG_REG_STRAP_OVERRIDE);
12123
12124         reset_gpio = MISC_REGISTERS_GPIO_1;
12125         port = 1;
12126
12127         /*
12128          * Retrieve the reset gpio/port which control the reset.
12129          * Default is GPIO1, PORT1
12130          */
12131         bnx2x_get_ext_phy_reset_gpio(bp, shmem_base_path[0],
12132                                      (u8 *)&reset_gpio, (u8 *)&port);
12133
12134         /* Calculate the port based on port swap */
12135         port ^= (swap_val && swap_override);
12136
12137         /* Initiate PHY reset*/
12138         bnx2x_set_gpio(bp, reset_gpio, MISC_REGISTERS_GPIO_OUTPUT_LOW,
12139                        port);
12140         msleep(1);
12141         bnx2x_set_gpio(bp, reset_gpio, MISC_REGISTERS_GPIO_OUTPUT_HIGH,
12142                        port);
12143
12144         msleep(5);
12145
12146         /* PART1 - Reset both phys */
12147         for (port = PORT_MAX - 1; port >= PORT_0; port--) {
12148                 u32 shmem_base, shmem2_base;
12149
12150                 /* In E2, same phy is using for port0 of the two paths */
12151                 if (CHIP_IS_E1x(bp)) {
12152                         shmem_base = shmem_base_path[0];
12153                         shmem2_base = shmem2_base_path[0];
12154                         port_of_path = port;
12155                 } else {
12156                         shmem_base = shmem_base_path[port];
12157                         shmem2_base = shmem2_base_path[port];
12158                         port_of_path = 0;
12159                 }
12160
12161                 /* Extract the ext phy address for the port */
12162                 if (bnx2x_populate_phy(bp, phy_index, shmem_base, shmem2_base,
12163                                        port_of_path, &phy[port]) !=
12164                                        0) {
12165                         DP(NETIF_MSG_LINK, "populate phy failed\n");
12166                         return -EINVAL;
12167                 }
12168                 /* disable attentions */
12169                 bnx2x_bits_dis(bp, NIG_REG_MASK_INTERRUPT_PORT0 +
12170                                port_of_path*4,
12171                                (NIG_MASK_XGXS0_LINK_STATUS |
12172                                 NIG_MASK_XGXS0_LINK10G |
12173                                 NIG_MASK_SERDES0_LINK_STATUS |
12174                                 NIG_MASK_MI_INT));
12175
12176
12177                 /* Reset the phy */
12178                 bnx2x_cl45_write(bp, &phy[port],
12179                                  MDIO_PMA_DEVAD, MDIO_PMA_REG_CTRL, 1<<15);
12180         }
12181
12182         /* Add delay of 150ms after reset */
12183         msleep(150);
12184         if (phy[PORT_0].addr & 0x1) {
12185                 phy_blk[PORT_0] = &(phy[PORT_1]);
12186                 phy_blk[PORT_1] = &(phy[PORT_0]);
12187         } else {
12188                 phy_blk[PORT_0] = &(phy[PORT_0]);
12189                 phy_blk[PORT_1] = &(phy[PORT_1]);
12190         }
12191         /* PART2 - Download firmware to both phys */
12192         for (port = PORT_MAX - 1; port >= PORT_0; port--) {
12193                 if (CHIP_IS_E1x(bp))
12194                         port_of_path = port;
12195                 else
12196                         port_of_path = 0;
12197                 DP(NETIF_MSG_LINK, "Loading spirom for phy address 0x%x\n",
12198                            phy_blk[port]->addr);
12199                 if (bnx2x_8073_8727_external_rom_boot(bp, phy_blk[port],
12200                                                       port_of_path))
12201                         return -EINVAL;
12202                 /* Disable PHY transmitter output */
12203                 bnx2x_cl45_write(bp, phy_blk[port],
12204                                  MDIO_PMA_DEVAD,
12205                                  MDIO_PMA_REG_TX_DISABLE, 1);
12206
12207         }
12208         return 0;
12209 }
12210
12211 static int bnx2x_ext_phy_common_init(struct bnx2x *bp, u32 shmem_base_path[],
12212                                      u32 shmem2_base_path[], u8 phy_index,
12213                                      u32 ext_phy_type, u32 chip_id)
12214 {
12215         int rc = 0;
12216
12217         switch (ext_phy_type) {
12218         case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8073:
12219                 rc = bnx2x_8073_common_init_phy(bp, shmem_base_path,
12220                                                 shmem2_base_path,
12221                                                 phy_index, chip_id);
12222                 break;
12223         case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8722:
12224         case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8727:
12225         case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8727_NOC:
12226                 rc = bnx2x_8727_common_init_phy(bp, shmem_base_path,
12227                                                 shmem2_base_path,
12228                                                 phy_index, chip_id);
12229                 break;
12230
12231         case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8726:
12232                 /*
12233                  * GPIO1 affects both ports, so there's need to pull
12234                  * it for single port alone
12235                  */
12236                 rc = bnx2x_8726_common_init_phy(bp, shmem_base_path,
12237                                                 shmem2_base_path,
12238                                                 phy_index, chip_id);
12239                 break;
12240         case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM84833:
12241                 /*
12242                  * GPIO3's are linked, and so both need to be toggled
12243                  * to obtain required 2us pulse.
12244                  */
12245                 rc = bnx2x_84833_common_init_phy(bp, shmem_base_path, chip_id);
12246                 break;
12247         case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_FAILURE:
12248                 rc = -EINVAL;
12249                 break;
12250         default:
12251                 DP(NETIF_MSG_LINK,
12252                            "ext_phy 0x%x common init not required\n",
12253                            ext_phy_type);
12254                 break;
12255         }
12256
12257         if (rc != 0)
12258                 netdev_err(bp->dev,  "Warning: PHY was not initialized,"
12259                                       " Port %d\n",
12260                          0);
12261         return rc;
12262 }
12263
12264 int bnx2x_common_init_phy(struct bnx2x *bp, u32 shmem_base_path[],
12265                           u32 shmem2_base_path[], u32 chip_id)
12266 {
12267         int rc = 0;
12268         u32 phy_ver, val;
12269         u8 phy_index = 0;
12270         u32 ext_phy_type, ext_phy_config;
12271         bnx2x_set_mdio_clk(bp, chip_id, PORT_0);
12272         bnx2x_set_mdio_clk(bp, chip_id, PORT_1);
12273         DP(NETIF_MSG_LINK, "Begin common phy init\n");
12274         if (CHIP_IS_E3(bp)) {
12275                 /* Enable EPIO */
12276                 val = REG_RD(bp, MISC_REG_GEN_PURP_HWG);
12277                 REG_WR(bp, MISC_REG_GEN_PURP_HWG, val | 1);
12278         }
12279         /* Check if common init was already done */
12280         phy_ver = REG_RD(bp, shmem_base_path[0] +
12281                          offsetof(struct shmem_region,
12282                                   port_mb[PORT_0].ext_phy_fw_version));
12283         if (phy_ver) {
12284                 DP(NETIF_MSG_LINK, "Not doing common init; phy ver is 0x%x\n",
12285                                phy_ver);
12286                 return 0;
12287         }
12288
12289         /* Read the ext_phy_type for arbitrary port(0) */
12290         for (phy_index = EXT_PHY1; phy_index < MAX_PHYS;
12291               phy_index++) {
12292                 ext_phy_config = bnx2x_get_ext_phy_config(bp,
12293                                                           shmem_base_path[0],
12294                                                           phy_index, 0);
12295                 ext_phy_type = XGXS_EXT_PHY_TYPE(ext_phy_config);
12296                 rc |= bnx2x_ext_phy_common_init(bp, shmem_base_path,
12297                                                 shmem2_base_path,
12298                                                 phy_index, ext_phy_type,
12299                                                 chip_id);
12300         }
12301         return rc;
12302 }
12303
12304 static void bnx2x_check_over_curr(struct link_params *params,
12305                                   struct link_vars *vars)
12306 {
12307         struct bnx2x *bp = params->bp;
12308         u32 cfg_pin;
12309         u8 port = params->port;
12310         u32 pin_val;
12311
12312         cfg_pin = (REG_RD(bp, params->shmem_base +
12313                           offsetof(struct shmem_region,
12314                                dev_info.port_hw_config[port].e3_cmn_pin_cfg1)) &
12315                    PORT_HW_CFG_E3_OVER_CURRENT_MASK) >>
12316                 PORT_HW_CFG_E3_OVER_CURRENT_SHIFT;
12317
12318         /* Ignore check if no external input PIN available */
12319         if (bnx2x_get_cfg_pin(bp, cfg_pin, &pin_val) != 0)
12320                 return;
12321
12322         if (!pin_val) {
12323                 if ((vars->phy_flags & PHY_OVER_CURRENT_FLAG) == 0) {
12324                         netdev_err(bp->dev, "Error:  Power fault on Port %d has"
12325                                             " been detected and the power to "
12326                                             "that SFP+ module has been removed"
12327                                             " to prevent failure of the card."
12328                                             " Please remove the SFP+ module and"
12329                                             " restart the system to clear this"
12330                                             " error.\n",
12331                          params->port);
12332                         vars->phy_flags |= PHY_OVER_CURRENT_FLAG;
12333                 }
12334         } else
12335                 vars->phy_flags &= ~PHY_OVER_CURRENT_FLAG;
12336 }
12337
12338 static void bnx2x_analyze_link_error(struct link_params *params,
12339                                      struct link_vars *vars, u32 lss_status)
12340 {
12341         struct bnx2x *bp = params->bp;
12342         /* Compare new value with previous value */
12343         u8 led_mode;
12344         u32 half_open_conn = (vars->phy_flags & PHY_HALF_OPEN_CONN_FLAG) > 0;
12345
12346         if ((lss_status ^ half_open_conn) == 0)
12347                 return;
12348
12349         /* If values differ */
12350         DP(NETIF_MSG_LINK, "Link changed:%x %x->%x\n", vars->link_up,
12351                        half_open_conn, lss_status);
12352
12353         /*
12354          * a. Update shmem->link_status accordingly
12355          * b. Update link_vars->link_up
12356          */
12357         if (lss_status) {
12358                 DP(NETIF_MSG_LINK, "Remote Fault detected !!!\n");
12359                 vars->link_status &= ~LINK_STATUS_LINK_UP;
12360                 vars->link_up = 0;
12361                 vars->phy_flags |= PHY_HALF_OPEN_CONN_FLAG;
12362                 /*
12363                  * Set LED mode to off since the PHY doesn't know about these
12364                  * errors
12365                  */
12366                 led_mode = LED_MODE_OFF;
12367         } else {
12368                 DP(NETIF_MSG_LINK, "Remote Fault cleared\n");
12369                 vars->link_status |= LINK_STATUS_LINK_UP;
12370                 vars->link_up = 1;
12371                 vars->phy_flags &= ~PHY_HALF_OPEN_CONN_FLAG;
12372                 led_mode = LED_MODE_OPER;
12373         }
12374         /* Update the LED according to the link state */
12375         bnx2x_set_led(params, vars, led_mode, SPEED_10000);
12376
12377         /* Update link status in the shared memory */
12378         bnx2x_update_mng(params, vars->link_status);
12379
12380         /* C. Trigger General Attention */
12381         vars->periodic_flags |= PERIODIC_FLAGS_LINK_EVENT;
12382         bnx2x_notify_link_changed(bp);
12383 }
12384
12385 /******************************************************************************
12386 * Description:
12387 *       This function checks for half opened connection change indication.
12388 *       When such change occurs, it calls the bnx2x_analyze_link_error
12389 *       to check if Remote Fault is set or cleared. Reception of remote fault
12390 *       status message in the MAC indicates that the peer's MAC has detected
12391 *       a fault, for example, due to break in the TX side of fiber.
12392 *
12393 ******************************************************************************/
12394 static void bnx2x_check_half_open_conn(struct link_params *params,
12395                                        struct link_vars *vars)
12396 {
12397         struct bnx2x *bp = params->bp;
12398         u32 lss_status = 0;
12399         u32 mac_base;
12400         /* In case link status is physically up @ 10G do */
12401         if ((vars->phy_flags & PHY_PHYSICAL_LINK_FLAG) == 0)
12402                 return;
12403
12404         if (CHIP_IS_E3(bp) &&
12405             (REG_RD(bp, MISC_REG_RESET_REG_2) &
12406               (MISC_REGISTERS_RESET_REG_2_XMAC))) {
12407                 /* Check E3 XMAC */
12408                 /*
12409                  * Note that link speed cannot be queried here, since it may be
12410                  * zero while link is down. In case UMAC is active, LSS will
12411                  * simply not be set
12412                  */
12413                 mac_base = (params->port) ? GRCBASE_XMAC1 : GRCBASE_XMAC0;
12414
12415                 /* Clear stick bits (Requires rising edge) */
12416                 REG_WR(bp, mac_base + XMAC_REG_CLEAR_RX_LSS_STATUS, 0);
12417                 REG_WR(bp, mac_base + XMAC_REG_CLEAR_RX_LSS_STATUS,
12418                        XMAC_CLEAR_RX_LSS_STATUS_REG_CLEAR_LOCAL_FAULT_STATUS |
12419                        XMAC_CLEAR_RX_LSS_STATUS_REG_CLEAR_REMOTE_FAULT_STATUS);
12420                 if (REG_RD(bp, mac_base + XMAC_REG_RX_LSS_STATUS))
12421                         lss_status = 1;
12422
12423                 bnx2x_analyze_link_error(params, vars, lss_status);
12424         } else if (REG_RD(bp, MISC_REG_RESET_REG_2) &
12425                    (MISC_REGISTERS_RESET_REG_2_RST_BMAC0 << params->port)) {
12426                 /* Check E1X / E2 BMAC */
12427                 u32 lss_status_reg;
12428                 u32 wb_data[2];
12429                 mac_base = params->port ? NIG_REG_INGRESS_BMAC1_MEM :
12430                         NIG_REG_INGRESS_BMAC0_MEM;
12431                 /*  Read BIGMAC_REGISTER_RX_LSS_STATUS */
12432                 if (CHIP_IS_E2(bp))
12433                         lss_status_reg = BIGMAC2_REGISTER_RX_LSS_STAT;
12434                 else
12435                         lss_status_reg = BIGMAC_REGISTER_RX_LSS_STATUS;
12436
12437                 REG_RD_DMAE(bp, mac_base + lss_status_reg, wb_data, 2);
12438                 lss_status = (wb_data[0] > 0);
12439
12440                 bnx2x_analyze_link_error(params, vars, lss_status);
12441         }
12442 }
12443
12444 void bnx2x_period_func(struct link_params *params, struct link_vars *vars)
12445 {
12446         struct bnx2x *bp = params->bp;
12447         u16 phy_idx;
12448         for (phy_idx = INT_PHY; phy_idx < MAX_PHYS; phy_idx++) {
12449                 if (params->phy[phy_idx].flags & FLAGS_TX_ERROR_CHECK) {
12450                         bnx2x_set_aer_mmd(params, &params->phy[phy_idx]);
12451                         bnx2x_check_half_open_conn(params, vars);
12452                         break;
12453                 }
12454         }
12455
12456         if (CHIP_IS_E3(bp)) {
12457                 struct bnx2x_phy *phy = &params->phy[INT_PHY];
12458                 bnx2x_set_aer_mmd(params, phy);
12459                 bnx2x_check_over_curr(params, vars);
12460                 bnx2x_warpcore_config_runtime(phy, params, vars);
12461         }
12462
12463 }
12464
12465 u8 bnx2x_hw_lock_required(struct bnx2x *bp, u32 shmem_base, u32 shmem2_base)
12466 {
12467         u8 phy_index;
12468         struct bnx2x_phy phy;
12469         for (phy_index = INT_PHY; phy_index < MAX_PHYS;
12470               phy_index++) {
12471                 if (bnx2x_populate_phy(bp, phy_index, shmem_base, shmem2_base,
12472                                        0, &phy) != 0) {
12473                         DP(NETIF_MSG_LINK, "populate phy failed\n");
12474                         return 0;
12475                 }
12476
12477                 if (phy.flags & FLAGS_HW_LOCK_REQUIRED)
12478                         return 1;
12479         }
12480         return 0;
12481 }
12482
12483 u8 bnx2x_fan_failure_det_req(struct bnx2x *bp,
12484                              u32 shmem_base,
12485                              u32 shmem2_base,
12486                              u8 port)
12487 {
12488         u8 phy_index, fan_failure_det_req = 0;
12489         struct bnx2x_phy phy;
12490         for (phy_index = EXT_PHY1; phy_index < MAX_PHYS;
12491               phy_index++) {
12492                 if (bnx2x_populate_phy(bp, phy_index, shmem_base, shmem2_base,
12493                                        port, &phy)
12494                     != 0) {
12495                         DP(NETIF_MSG_LINK, "populate phy failed\n");
12496                         return 0;
12497                 }
12498                 fan_failure_det_req |= (phy.flags &
12499                                         FLAGS_FAN_FAILURE_DET_REQ);
12500         }
12501         return fan_failure_det_req;
12502 }
12503
12504 void bnx2x_hw_reset_phy(struct link_params *params)
12505 {
12506         u8 phy_index;
12507         struct bnx2x *bp = params->bp;
12508         bnx2x_update_mng(params, 0);
12509         bnx2x_bits_dis(bp, NIG_REG_MASK_INTERRUPT_PORT0 + params->port*4,
12510                        (NIG_MASK_XGXS0_LINK_STATUS |
12511                         NIG_MASK_XGXS0_LINK10G |
12512                         NIG_MASK_SERDES0_LINK_STATUS |
12513                         NIG_MASK_MI_INT));
12514
12515         for (phy_index = INT_PHY; phy_index < MAX_PHYS;
12516               phy_index++) {
12517                 if (params->phy[phy_index].hw_reset) {
12518                         params->phy[phy_index].hw_reset(
12519                                 &params->phy[phy_index],
12520                                 params);
12521                         params->phy[phy_index] = phy_null;
12522                 }
12523         }
12524 }
12525
12526 void bnx2x_init_mod_abs_int(struct bnx2x *bp, struct link_vars *vars,
12527                             u32 chip_id, u32 shmem_base, u32 shmem2_base,
12528                             u8 port)
12529 {
12530         u8 gpio_num = 0xff, gpio_port = 0xff, phy_index;
12531         u32 val;
12532         u32 offset, aeu_mask, swap_val, swap_override, sync_offset;
12533         if (CHIP_IS_E3(bp)) {
12534                 if (bnx2x_get_mod_abs_int_cfg(bp, chip_id,
12535                                               shmem_base,
12536                                               port,
12537                                               &gpio_num,
12538                                               &gpio_port) != 0)
12539                         return;
12540         } else {
12541                 struct bnx2x_phy phy;
12542                 for (phy_index = EXT_PHY1; phy_index < MAX_PHYS;
12543                       phy_index++) {
12544                         if (bnx2x_populate_phy(bp, phy_index, shmem_base,
12545                                                shmem2_base, port, &phy)
12546                             != 0) {
12547                                 DP(NETIF_MSG_LINK, "populate phy failed\n");
12548                                 return;
12549                         }
12550                         if (phy.type == PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8726) {
12551                                 gpio_num = MISC_REGISTERS_GPIO_3;
12552                                 gpio_port = port;
12553                                 break;
12554                         }
12555                 }
12556         }
12557
12558         if (gpio_num == 0xff)
12559                 return;
12560
12561         /* Set GPIO3 to trigger SFP+ module insertion/removal */
12562         bnx2x_set_gpio(bp, gpio_num, MISC_REGISTERS_GPIO_INPUT_HI_Z, gpio_port);
12563
12564         swap_val = REG_RD(bp, NIG_REG_PORT_SWAP);
12565         swap_override = REG_RD(bp, NIG_REG_STRAP_OVERRIDE);
12566         gpio_port ^= (swap_val && swap_override);
12567
12568         vars->aeu_int_mask = AEU_INPUTS_ATTN_BITS_GPIO0_FUNCTION_0 <<
12569                 (gpio_num + (gpio_port << 2));
12570
12571         sync_offset = shmem_base +
12572                 offsetof(struct shmem_region,
12573                          dev_info.port_hw_config[port].aeu_int_mask);
12574         REG_WR(bp, sync_offset, vars->aeu_int_mask);
12575
12576         DP(NETIF_MSG_LINK, "Setting MOD_ABS (GPIO%d_P%d) AEU to 0x%x\n",
12577                        gpio_num, gpio_port, vars->aeu_int_mask);
12578
12579         if (port == 0)
12580                 offset = MISC_REG_AEU_ENABLE1_FUNC_0_OUT_0;
12581         else
12582                 offset = MISC_REG_AEU_ENABLE1_FUNC_1_OUT_0;
12583
12584         /* Open appropriate AEU for interrupts */
12585         aeu_mask = REG_RD(bp, offset);
12586         aeu_mask |= vars->aeu_int_mask;
12587         REG_WR(bp, offset, aeu_mask);
12588
12589         /* Enable the GPIO to trigger interrupt */
12590         val = REG_RD(bp, MISC_REG_GPIO_EVENT_EN);
12591         val |= 1 << (gpio_num + (gpio_port << 2));
12592         REG_WR(bp, MISC_REG_GPIO_EVENT_EN, val);
12593 }