drivers/net/ethernet/broadcom/bnx2x/bnx2x_link.c

   1 /* Copyright 2008-2012 Broadcom Corporation
   2  *
   3  * Unless you and Broadcom execute a separate written software license
   4  * agreement governing use of this software, this software is licensed to you
   5  * under the terms of the GNU General Public License version 2, available
   6  * at http://www.gnu.org/licenses/old-licenses/gpl-2.0.html (the "GPL").
   7  *
   8  * Notwithstanding the above, under no circumstances may you combine this
   9  * software in any way with any other Broadcom software provided under a
  10  * license other than the GPL, without Broadcom's express prior written
  11  * consent.
  12  *
  13  * Written by Yaniv Rosner
  14  *
  15  */
  16
  17 #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
  18
  19 #include <linux/kernel.h>
  20 #include <linux/errno.h>
  21 #include <linux/pci.h>
  22 #include <linux/netdevice.h>
  23 #include <linux/delay.h>
  24 #include <linux/ethtool.h>
  25 #include <linux/mutex.h>
  26
  27 #include "bnx2x.h"
  28 #include "bnx2x_cmn.h"
  29
  30 /********************************************************/
  31 #define ETH_HLEN                        14
  32 /* L2 header size + 2*VLANs (8 bytes) + LLC SNAP (8 bytes) */
  33 #define ETH_OVREHEAD                    (ETH_HLEN + 8 + 8)
  34 #define ETH_MIN_PACKET_SIZE             60
  35 #define ETH_MAX_PACKET_SIZE             1500
  36 #define ETH_MAX_JUMBO_PACKET_SIZE       9600
  37 #define MDIO_ACCESS_TIMEOUT             1000
  38 #define WC_LANE_MAX                     4
  39 #define I2C_SWITCH_WIDTH                2
  40 #define I2C_BSC0                        0
  41 #define I2C_BSC1                        1
  42 #define I2C_WA_RETRY_CNT                3
  43 #define MCPR_IMC_COMMAND_READ_OP        1
  44 #define MCPR_IMC_COMMAND_WRITE_OP       2
  45
  46 /* LED Blink rate that will achieve ~15.9Hz */
  47 #define LED_BLINK_RATE_VAL_E3           354
  48 #define LED_BLINK_RATE_VAL_E1X_E2       480
  49 /***********************************************************/
  50 /*                      Shortcut definitions               */
  51 /***********************************************************/
  52
  53 #define NIG_LATCH_BC_ENABLE_MI_INT 0
  54
  55 #define NIG_STATUS_EMAC0_MI_INT \
  56                 NIG_STATUS_INTERRUPT_PORT0_REG_STATUS_EMAC0_MISC_MI_INT
  57 #define NIG_STATUS_XGXS0_LINK10G \
  58                 NIG_STATUS_INTERRUPT_PORT0_REG_STATUS_XGXS0_LINK10G
  59 #define NIG_STATUS_XGXS0_LINK_STATUS \
  60                 NIG_STATUS_INTERRUPT_PORT0_REG_STATUS_XGXS0_LINK_STATUS
  61 #define NIG_STATUS_XGXS0_LINK_STATUS_SIZE \
  62                 NIG_STATUS_INTERRUPT_PORT0_REG_STATUS_XGXS0_LINK_STATUS_SIZE
  63 #define NIG_STATUS_SERDES0_LINK_STATUS \
  64                 NIG_STATUS_INTERRUPT_PORT0_REG_STATUS_SERDES0_LINK_STATUS
  65 #define NIG_MASK_MI_INT \
  66                 NIG_MASK_INTERRUPT_PORT0_REG_MASK_EMAC0_MISC_MI_INT
  67 #define NIG_MASK_XGXS0_LINK10G \
  68                 NIG_MASK_INTERRUPT_PORT0_REG_MASK_XGXS0_LINK10G
  69 #define NIG_MASK_XGXS0_LINK_STATUS \
  70                 NIG_MASK_INTERRUPT_PORT0_REG_MASK_XGXS0_LINK_STATUS
  71 #define NIG_MASK_SERDES0_LINK_STATUS \
  72                 NIG_MASK_INTERRUPT_PORT0_REG_MASK_SERDES0_LINK_STATUS
  73
  74 #define MDIO_AN_CL73_OR_37_COMPLETE \
  75                 (MDIO_GP_STATUS_TOP_AN_STATUS1_CL73_AUTONEG_COMPLETE | \
  76                  MDIO_GP_STATUS_TOP_AN_STATUS1_CL37_AUTONEG_COMPLETE)
  77
  78 #define XGXS_RESET_BITS \
  79         (MISC_REGISTERS_RESET_REG_3_MISC_NIG_MUX_XGXS0_RSTB_HW |   \
  80          MISC_REGISTERS_RESET_REG_3_MISC_NIG_MUX_XGXS0_IDDQ |      \
  81          MISC_REGISTERS_RESET_REG_3_MISC_NIG_MUX_XGXS0_PWRDWN |    \
  82          MISC_REGISTERS_RESET_REG_3_MISC_NIG_MUX_XGXS0_PWRDWN_SD | \
  83          MISC_REGISTERS_RESET_REG_3_MISC_NIG_MUX_XGXS0_TXD_FIFO_RSTB)
  84
  85 #define SERDES_RESET_BITS \
  86         (MISC_REGISTERS_RESET_REG_3_MISC_NIG_MUX_SERDES0_RSTB_HW | \
  87          MISC_REGISTERS_RESET_REG_3_MISC_NIG_MUX_SERDES0_IDDQ |    \
  88          MISC_REGISTERS_RESET_REG_3_MISC_NIG_MUX_SERDES0_PWRDWN |  \
  89          MISC_REGISTERS_RESET_REG_3_MISC_NIG_MUX_SERDES0_PWRDWN_SD)
  90
  91 #define AUTONEG_CL37            SHARED_HW_CFG_AN_ENABLE_CL37
  92 #define AUTONEG_CL73            SHARED_HW_CFG_AN_ENABLE_CL73
  93 #define AUTONEG_BAM             SHARED_HW_CFG_AN_ENABLE_BAM
  94 #define AUTONEG_PARALLEL \
  95                                 SHARED_HW_CFG_AN_ENABLE_PARALLEL_DETECTION
  96 #define AUTONEG_SGMII_FIBER_AUTODET \
  97                                 SHARED_HW_CFG_AN_EN_SGMII_FIBER_AUTO_DETECT
  98 #define AUTONEG_REMOTE_PHY      SHARED_HW_CFG_AN_ENABLE_REMOTE_PHY
  99
 100 #define GP_STATUS_PAUSE_RSOLUTION_TXSIDE \
 101                         MDIO_GP_STATUS_TOP_AN_STATUS1_PAUSE_RSOLUTION_TXSIDE
 102 #define GP_STATUS_PAUSE_RSOLUTION_RXSIDE \
 103                         MDIO_GP_STATUS_TOP_AN_STATUS1_PAUSE_RSOLUTION_RXSIDE
 104 #define GP_STATUS_SPEED_MASK \
 105                         MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_MASK
 106 #define GP_STATUS_10M   MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_10M
 107 #define GP_STATUS_100M  MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_100M
 108 #define GP_STATUS_1G    MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_1G
 109 #define GP_STATUS_2_5G  MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_2_5G
 110 #define GP_STATUS_5G    MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_5G
 111 #define GP_STATUS_6G    MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_6G
 112 #define GP_STATUS_10G_HIG \
 113                         MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_10G_HIG
 114 #define GP_STATUS_10G_CX4 \
 115                         MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_10G_CX4
 116 #define GP_STATUS_1G_KX MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_1G_KX
 117 #define GP_STATUS_10G_KX4 \
 118                         MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_10G_KX4
 119 #define GP_STATUS_10G_KR MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_10G_KR
 120 #define GP_STATUS_10G_XFI   MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_10G_XFI
 121 #define GP_STATUS_20G_DXGXS MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_20G_DXGXS
 122 #define GP_STATUS_10G_SFI   MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_10G_SFI
 123 #define LINK_10THD              LINK_STATUS_SPEED_AND_DUPLEX_10THD
 124 #define LINK_10TFD              LINK_STATUS_SPEED_AND_DUPLEX_10TFD
 125 #define LINK_100TXHD            LINK_STATUS_SPEED_AND_DUPLEX_100TXHD
 126 #define LINK_100T4              LINK_STATUS_SPEED_AND_DUPLEX_100T4
 127 #define LINK_100TXFD            LINK_STATUS_SPEED_AND_DUPLEX_100TXFD
 128 #define LINK_1000THD            LINK_STATUS_SPEED_AND_DUPLEX_1000THD
 129 #define LINK_1000TFD            LINK_STATUS_SPEED_AND_DUPLEX_1000TFD
 130 #define LINK_1000XFD            LINK_STATUS_SPEED_AND_DUPLEX_1000XFD
 131 #define LINK_2500THD            LINK_STATUS_SPEED_AND_DUPLEX_2500THD
 132 #define LINK_2500TFD            LINK_STATUS_SPEED_AND_DUPLEX_2500TFD
 133 #define LINK_2500XFD            LINK_STATUS_SPEED_AND_DUPLEX_2500XFD
 134 #define LINK_10GTFD             LINK_STATUS_SPEED_AND_DUPLEX_10GTFD
 135 #define LINK_10GXFD             LINK_STATUS_SPEED_AND_DUPLEX_10GXFD
 136 #define LINK_20GTFD             LINK_STATUS_SPEED_AND_DUPLEX_20GTFD
 137 #define LINK_20GXFD             LINK_STATUS_SPEED_AND_DUPLEX_20GXFD
 138
 139
 140
 141 /* */
 142 #define SFP_EEPROM_CON_TYPE_ADDR                0x2
 143         #define SFP_EEPROM_CON_TYPE_VAL_LC      0x7
 144         #define SFP_EEPROM_CON_TYPE_VAL_COPPER  0x21
 145
 146
 147 #define SFP_EEPROM_COMP_CODE_ADDR               0x3
 148         #define SFP_EEPROM_COMP_CODE_SR_MASK    (1<<4)
 149         #define SFP_EEPROM_COMP_CODE_LR_MASK    (1<<5)
 150         #define SFP_EEPROM_COMP_CODE_LRM_MASK   (1<<6)
 151
 152 #define SFP_EEPROM_FC_TX_TECH_ADDR              0x8
 153         #define SFP_EEPROM_FC_TX_TECH_BITMASK_COPPER_PASSIVE 0x4
 154         #define SFP_EEPROM_FC_TX_TECH_BITMASK_COPPER_ACTIVE  0x8
 155
 156 #define SFP_EEPROM_OPTIONS_ADDR                 0x40
 157         #define SFP_EEPROM_OPTIONS_LINEAR_RX_OUT_MASK 0x1
 158 #define SFP_EEPROM_OPTIONS_SIZE                 2
 159
 160 #define EDC_MODE_LINEAR                         0x0022
 161 #define EDC_MODE_LIMITING                               0x0044
 162 #define EDC_MODE_PASSIVE_DAC                    0x0055
 163
 164 /* BRB default for class 0 E2 */
 165 #define DEFAULT0_E2_BRB_MAC_PAUSE_XOFF_THR      170
 166 #define DEFAULT0_E2_BRB_MAC_PAUSE_XON_THR               250
 167 #define DEFAULT0_E2_BRB_MAC_FULL_XOFF_THR               10
 168 #define DEFAULT0_E2_BRB_MAC_FULL_XON_THR                50
 169
 170 /* BRB thresholds for E2*/
 171 #define PFC_E2_BRB_MAC_PAUSE_XOFF_THR_PAUSE             170
 172 #define PFC_E2_BRB_MAC_PAUSE_XOFF_THR_NON_PAUSE         0
 173
 174 #define PFC_E2_BRB_MAC_PAUSE_XON_THR_PAUSE              250
 175 #define PFC_E2_BRB_MAC_PAUSE_XON_THR_NON_PAUSE          0
 176
 177 #define PFC_E2_BRB_MAC_FULL_XOFF_THR_PAUSE              10
 178 #define PFC_E2_BRB_MAC_FULL_XOFF_THR_NON_PAUSE          90
 179
 180 #define PFC_E2_BRB_MAC_FULL_XON_THR_PAUSE                       50
 181 #define PFC_E2_BRB_MAC_FULL_XON_THR_NON_PAUSE           250
 182
 183 /* BRB default for class 0 E3A0 */
 184 #define DEFAULT0_E3A0_BRB_MAC_PAUSE_XOFF_THR    290
 185 #define DEFAULT0_E3A0_BRB_MAC_PAUSE_XON_THR     410
 186 #define DEFAULT0_E3A0_BRB_MAC_FULL_XOFF_THR     10
 187 #define DEFAULT0_E3A0_BRB_MAC_FULL_XON_THR      50
 188
 189 /* BRB thresholds for E3A0 */
 190 #define PFC_E3A0_BRB_MAC_PAUSE_XOFF_THR_PAUSE           290
 191 #define PFC_E3A0_BRB_MAC_PAUSE_XOFF_THR_NON_PAUSE               0
 192
 193 #define PFC_E3A0_BRB_MAC_PAUSE_XON_THR_PAUSE            410
 194 #define PFC_E3A0_BRB_MAC_PAUSE_XON_THR_NON_PAUSE                0
 195
 196 #define PFC_E3A0_BRB_MAC_FULL_XOFF_THR_PAUSE            10
 197 #define PFC_E3A0_BRB_MAC_FULL_XOFF_THR_NON_PAUSE                170
 198
 199 #define PFC_E3A0_BRB_MAC_FULL_XON_THR_PAUSE             50
 200 #define PFC_E3A0_BRB_MAC_FULL_XON_THR_NON_PAUSE         410
 201
 202 /* BRB default for E3B0 */
 203 #define DEFAULT0_E3B0_BRB_MAC_PAUSE_XOFF_THR    330
 204 #define DEFAULT0_E3B0_BRB_MAC_PAUSE_XON_THR     490
 205 #define DEFAULT0_E3B0_BRB_MAC_FULL_XOFF_THR     15
 206 #define DEFAULT0_E3B0_BRB_MAC_FULL_XON_THR      55
 207
 208 /* BRB thresholds for E3B0 2 port mode*/
 209 #define PFC_E3B0_2P_BRB_MAC_PAUSE_XOFF_THR_PAUSE                1025
 210 #define PFC_E3B0_2P_BRB_MAC_PAUSE_XOFF_THR_NON_PAUSE    0
 211
 212 #define PFC_E3B0_2P_BRB_MAC_PAUSE_XON_THR_PAUSE         1025
 213 #define PFC_E3B0_2P_BRB_MAC_PAUSE_XON_THR_NON_PAUSE     0
 214
 215 #define PFC_E3B0_2P_BRB_MAC_FULL_XOFF_THR_PAUSE         10
 216 #define PFC_E3B0_2P_BRB_MAC_FULL_XOFF_THR_NON_PAUSE     1025
 217
 218 #define PFC_E3B0_2P_BRB_MAC_FULL_XON_THR_PAUSE          50
 219 #define PFC_E3B0_2P_BRB_MAC_FULL_XON_THR_NON_PAUSE      1025
 220
 221 /* only for E3B0*/
 222 #define PFC_E3B0_2P_BRB_FULL_LB_XOFF_THR                        1025
 223 #define PFC_E3B0_2P_BRB_FULL_LB_XON_THR                 1025
 224
 225 /* Lossy +Lossless GUARANTIED == GUART */
 226 #define PFC_E3B0_2P_MIX_PAUSE_LB_GUART                  284
 227 /* Lossless +Lossless*/
 228 #define PFC_E3B0_2P_PAUSE_LB_GUART                      236
 229 /* Lossy +Lossy*/
 230 #define PFC_E3B0_2P_NON_PAUSE_LB_GUART                  342
 231
 232 /* Lossy +Lossless*/
 233 #define PFC_E3B0_2P_MIX_PAUSE_MAC_0_CLASS_T_GUART               284
 234 /* Lossless +Lossless*/
 235 #define PFC_E3B0_2P_PAUSE_MAC_0_CLASS_T_GUART           236
 236 /* Lossy +Lossy*/
 237 #define PFC_E3B0_2P_NON_PAUSE_MAC_0_CLASS_T_GUART               336
 238 #define PFC_E3B0_2P_BRB_MAC_0_CLASS_T_GUART_HYST                80
 239
 240 #define PFC_E3B0_2P_BRB_MAC_1_CLASS_T_GUART             0
 241 #define PFC_E3B0_2P_BRB_MAC_1_CLASS_T_GUART_HYST                0
 242
 243 /* BRB thresholds for E3B0 4 port mode */
 244 #define PFC_E3B0_4P_BRB_MAC_PAUSE_XOFF_THR_PAUSE                304
 245 #define PFC_E3B0_4P_BRB_MAC_PAUSE_XOFF_THR_NON_PAUSE    0
 246
 247 #define PFC_E3B0_4P_BRB_MAC_PAUSE_XON_THR_PAUSE         384
 248 #define PFC_E3B0_4P_BRB_MAC_PAUSE_XON_THR_NON_PAUSE     0
 249
 250 #define PFC_E3B0_4P_BRB_MAC_FULL_XOFF_THR_PAUSE         10
 251 #define PFC_E3B0_4P_BRB_MAC_FULL_XOFF_THR_NON_PAUSE     304
 252
 253 #define PFC_E3B0_4P_BRB_MAC_FULL_XON_THR_PAUSE          50
 254 #define PFC_E3B0_4P_BRB_MAC_FULL_XON_THR_NON_PAUSE      384
 255
 256 /* only for E3B0*/
 257 #define PFC_E3B0_4P_BRB_FULL_LB_XOFF_THR                        304
 258 #define PFC_E3B0_4P_BRB_FULL_LB_XON_THR                 384
 259 #define PFC_E3B0_4P_LB_GUART            120
 260
 261 #define PFC_E3B0_4P_BRB_MAC_0_CLASS_T_GUART             120
 262 #define PFC_E3B0_4P_BRB_MAC_0_CLASS_T_GUART_HYST        80
 263
 264 #define PFC_E3B0_4P_BRB_MAC_1_CLASS_T_GUART             80
 265 #define PFC_E3B0_4P_BRB_MAC_1_CLASS_T_GUART_HYST        120
 266
 267 /* Pause defines*/
 268 #define DEFAULT_E3B0_BRB_FULL_LB_XOFF_THR                       330
 269 #define DEFAULT_E3B0_BRB_FULL_LB_XON_THR                        490
 270 #define DEFAULT_E3B0_LB_GUART           40
 271
 272 #define DEFAULT_E3B0_BRB_MAC_0_CLASS_T_GUART            40
 273 #define DEFAULT_E3B0_BRB_MAC_0_CLASS_T_GUART_HYST       0
 274
 275 #define DEFAULT_E3B0_BRB_MAC_1_CLASS_T_GUART            40
 276 #define DEFAULT_E3B0_BRB_MAC_1_CLASS_T_GUART_HYST       0
 277
 278 /* ETS defines*/
 279 #define DCBX_INVALID_COS                                        (0xFF)
 280
 281 #define ETS_BW_LIMIT_CREDIT_UPPER_BOUND         (0x5000)
 282 #define ETS_BW_LIMIT_CREDIT_WEIGHT              (0x5000)
 283 #define ETS_E3B0_NIG_MIN_W_VAL_UP_TO_10GBPS             (1360)
 284 #define ETS_E3B0_NIG_MIN_W_VAL_20GBPS                   (2720)
 285 #define ETS_E3B0_PBF_MIN_W_VAL                          (10000)
 286
 287 #define MAX_PACKET_SIZE                                 (9700)
 288 #define WC_UC_TIMEOUT                                   100
 289 #define MAX_KR_LINK_RETRY                               4
 290
 291 /**********************************************************/
 292 /*                     INTERFACE                          */
 293 /**********************************************************/
 294
 295 #define CL22_WR_OVER_CL45(_bp, _phy, _bank, _addr, _val) \
 296         bnx2x_cl45_write(_bp, _phy, \
 297                 (_phy)->def_md_devad, \
 298                 (_bank + (_addr & 0xf)), \
 299                 _val)
 300
 301 #define CL22_RD_OVER_CL45(_bp, _phy, _bank, _addr, _val) \
 302         bnx2x_cl45_read(_bp, _phy, \
 303                 (_phy)->def_md_devad, \
 304                 (_bank + (_addr & 0xf)), \
 305                 _val)
 306
 307 static u32 bnx2x_bits_en(struct bnx2x *bp, u32 reg, u32 bits)
 308 {
 309         u32 val = REG_RD(bp, reg);
 310
 311         val |= bits;
 312         REG_WR(bp, reg, val);
 313         return val;
 314 }
 315
 316 static u32 bnx2x_bits_dis(struct bnx2x *bp, u32 reg, u32 bits)
 317 {
 318         u32 val = REG_RD(bp, reg);
 319
 320         val &= ~bits;
 321         REG_WR(bp, reg, val);
 322         return val;
 323 }
 324
 325 /******************************************************************/
 326 /*                      EPIO/GPIO section                         */
 327 /******************************************************************/
 328 static void bnx2x_get_epio(struct bnx2x *bp, u32 epio_pin, u32 *en)
 329 {
 330         u32 epio_mask, gp_oenable;
 331         *en = 0;
 332         /* Sanity check */
 333         if (epio_pin > 31) {
 334                 DP(NETIF_MSG_LINK, "Invalid EPIO pin %d to get\n", epio_pin);
 335                 return;
 336         }
 337
 338         epio_mask = 1 << epio_pin;
 339         /* Set this EPIO to output */
 340         gp_oenable = REG_RD(bp, MCP_REG_MCPR_GP_OENABLE);
 341         REG_WR(bp, MCP_REG_MCPR_GP_OENABLE, gp_oenable & ~epio_mask);
 342
 343         *en = (REG_RD(bp, MCP_REG_MCPR_GP_INPUTS) & epio_mask) >> epio_pin;
 344 }
 345 static void bnx2x_set_epio(struct bnx2x *bp, u32 epio_pin, u32 en)
 346 {
 347         u32 epio_mask, gp_output, gp_oenable;
 348
 349         /* Sanity check */
 350         if (epio_pin > 31) {
 351                 DP(NETIF_MSG_LINK, "Invalid EPIO pin %d to set\n", epio_pin);
 352                 return;
 353         }
 354         DP(NETIF_MSG_LINK, "Setting EPIO pin %d to %d\n", epio_pin, en);
 355         epio_mask = 1 << epio_pin;
 356         /* Set this EPIO to output */
 357         gp_output = REG_RD(bp, MCP_REG_MCPR_GP_OUTPUTS);
 358         if (en)
 359                 gp_output |= epio_mask;
 360         else
 361                 gp_output &= ~epio_mask;
 362
 363         REG_WR(bp, MCP_REG_MCPR_GP_OUTPUTS, gp_output);
 364
 365         /* Set the value for this EPIO */
 366         gp_oenable = REG_RD(bp, MCP_REG_MCPR_GP_OENABLE);
 367         REG_WR(bp, MCP_REG_MCPR_GP_OENABLE, gp_oenable | epio_mask);
 368 }
 369
 370 static void bnx2x_set_cfg_pin(struct bnx2x *bp, u32 pin_cfg, u32 val)
 371 {
 372         if (pin_cfg == PIN_CFG_NA)
 373                 return;
 374         if (pin_cfg >= PIN_CFG_EPIO0) {
 375                 bnx2x_set_epio(bp, pin_cfg - PIN_CFG_EPIO0, val);
 376         } else {
 377                 u8 gpio_num = (pin_cfg - PIN_CFG_GPIO0_P0) & 0x3;
 378                 u8 gpio_port = (pin_cfg - PIN_CFG_GPIO0_P0) >> 2;
 379                 bnx2x_set_gpio(bp, gpio_num, (u8)val, gpio_port);
 380         }
 381 }
 382
 383 static u32 bnx2x_get_cfg_pin(struct bnx2x *bp, u32 pin_cfg, u32 *val)
 384 {
 385         if (pin_cfg == PIN_CFG_NA)
 386                 return -EINVAL;
 387         if (pin_cfg >= PIN_CFG_EPIO0) {
 388                 bnx2x_get_epio(bp, pin_cfg - PIN_CFG_EPIO0, val);
 389         } else {
 390                 u8 gpio_num = (pin_cfg - PIN_CFG_GPIO0_P0) & 0x3;
 391                 u8 gpio_port = (pin_cfg - PIN_CFG_GPIO0_P0) >> 2;
 392                 *val = bnx2x_get_gpio(bp, gpio_num, gpio_port);
 393         }
 394         return 0;
 395
 396 }
 397 /******************************************************************/
 398 /*                              ETS section                       */
 399 /******************************************************************/
 400 static void bnx2x_ets_e2e3a0_disabled(struct link_params *params)
 401 {
 402         /* ETS disabled configuration*/
 403         struct bnx2x *bp = params->bp;
 404
 405         DP(NETIF_MSG_LINK, "ETS E2E3 disabled configuration\n");
 406
 407         /*
 408          * mapping between entry  priority to client number (0,1,2 -debug and
 409          * management clients, 3 - COS0 client, 4 - COS client)(HIGHEST)
 410          * 3bits client num.
 411          *   PRI4    |    PRI3    |    PRI2    |    PRI1    |    PRI0
 412          * cos1-100     cos0-011     dbg1-010     dbg0-001     MCP-000
 413          */
 414
 415         REG_WR(bp, NIG_REG_P0_TX_ARB_PRIORITY_CLIENT, 0x4688);
 416         /*
 417          * Bitmap of 5bits length. Each bit specifies whether the entry behaves
 418          * as strict.  Bits 0,1,2 - debug and management entries, 3 -
 419          * COS0 entry, 4 - COS1 entry.
 420          * COS1 | COS0 | DEBUG1 | DEBUG0 | MGMT
 421          * bit4   bit3    bit2   bit1     bit0
 422          * MCP and debug are strict
 423          */
 424
 425         REG_WR(bp, NIG_REG_P0_TX_ARB_CLIENT_IS_STRICT, 0x7);
 426         /* defines which entries (clients) are subjected to WFQ arbitration */
 427         REG_WR(bp, NIG_REG_P0_TX_ARB_CLIENT_IS_SUBJECT2WFQ, 0);
 428         /*
 429          * For strict priority entries defines the number of consecutive
 430          * slots for the highest priority.
 431          */
 432         REG_WR(bp, NIG_REG_P0_TX_ARB_NUM_STRICT_ARB_SLOTS, 0x100);
 433         /*
 434          * mapping between the CREDIT_WEIGHT registers and actual client
 435          * numbers
 436          */
 437         REG_WR(bp, NIG_REG_P0_TX_ARB_CLIENT_CREDIT_MAP, 0);
 438         REG_WR(bp, NIG_REG_P0_TX_ARB_CREDIT_WEIGHT_0, 0);
 439         REG_WR(bp, NIG_REG_P0_TX_ARB_CREDIT_WEIGHT_1, 0);
 440
 441         REG_WR(bp, NIG_REG_P0_TX_ARB_CREDIT_UPPER_BOUND_0, 0);
 442         REG_WR(bp, NIG_REG_P0_TX_ARB_CREDIT_UPPER_BOUND_1, 0);
 443         REG_WR(bp, PBF_REG_HIGH_PRIORITY_COS_NUM, 0);
 444         /* ETS mode disable */
 445         REG_WR(bp, PBF_REG_ETS_ENABLED, 0);
 446         /*
 447          * If ETS mode is enabled (there is no strict priority) defines a WFQ
 448          * weight for COS0/COS1.
 449          */
 450         REG_WR(bp, PBF_REG_COS0_WEIGHT, 0x2710);
 451         REG_WR(bp, PBF_REG_COS1_WEIGHT, 0x2710);
 452         /* Upper bound that COS0_WEIGHT can reach in the WFQ arbiter */
 453         REG_WR(bp, PBF_REG_COS0_UPPER_BOUND, 0x989680);
 454         REG_WR(bp, PBF_REG_COS1_UPPER_BOUND, 0x989680);
 455         /* Defines the number of consecutive slots for the strict priority */
 456         REG_WR(bp, PBF_REG_NUM_STRICT_ARB_SLOTS, 0);
 457 }
 458 /******************************************************************************
 459 * Description:
 460 *       Getting min_w_val will be set according to line speed .
 461 *.
 462 ******************************************************************************/
 463 static u32 bnx2x_ets_get_min_w_val_nig(const struct link_vars *vars)
 464 {
 465         u32 min_w_val = 0;
 466         /* Calculate min_w_val.*/
 467         if (vars->link_up) {
 468                 if (vars->line_speed == SPEED_20000)
 469                         min_w_val = ETS_E3B0_NIG_MIN_W_VAL_20GBPS;
 470                 else
 471                         min_w_val = ETS_E3B0_NIG_MIN_W_VAL_UP_TO_10GBPS;
 472         } else
 473                 min_w_val = ETS_E3B0_NIG_MIN_W_VAL_20GBPS;
 474         /**
 475          *  If the link isn't up (static configuration for example ) The
 476          *  link will be according to 20GBPS.
 477         */
 478         return min_w_val;
 479 }
 480 /******************************************************************************
 481 * Description:
 482 *       Getting credit upper bound form min_w_val.
 483 *.
 484 ******************************************************************************/
 485 static u32 bnx2x_ets_get_credit_upper_bound(const u32 min_w_val)
 486 {
 487         const u32 credit_upper_bound = (u32)MAXVAL((150 * min_w_val),
 488                                                 MAX_PACKET_SIZE);
 489         return credit_upper_bound;
 490 }
 491 /******************************************************************************
 492 * Description:
 493 *       Set credit upper bound for NIG.
 494 *.
 495 ******************************************************************************/
 496 static void bnx2x_ets_e3b0_set_credit_upper_bound_nig(
 497         const struct link_params *params,
 498         const u32 min_w_val)
 499 {
 500         struct bnx2x *bp = params->bp;
 501         const u8 port = params->port;
 502         const u32 credit_upper_bound =
 503             bnx2x_ets_get_credit_upper_bound(min_w_val);
 504
 505         REG_WR(bp, (port) ? NIG_REG_P1_TX_ARB_CREDIT_UPPER_BOUND_0 :
 506                 NIG_REG_P0_TX_ARB_CREDIT_UPPER_BOUND_0, credit_upper_bound);
 507         REG_WR(bp, (port) ? NIG_REG_P1_TX_ARB_CREDIT_UPPER_BOUND_1 :
 508                    NIG_REG_P0_TX_ARB_CREDIT_UPPER_BOUND_1, credit_upper_bound);
 509         REG_WR(bp, (port) ? NIG_REG_P1_TX_ARB_CREDIT_UPPER_BOUND_2 :
 510                    NIG_REG_P0_TX_ARB_CREDIT_UPPER_BOUND_2, credit_upper_bound);
 511         REG_WR(bp, (port) ? NIG_REG_P1_TX_ARB_CREDIT_UPPER_BOUND_3 :
 512                    NIG_REG_P0_TX_ARB_CREDIT_UPPER_BOUND_3, credit_upper_bound);
 513         REG_WR(bp, (port) ? NIG_REG_P1_TX_ARB_CREDIT_UPPER_BOUND_4 :
 514                    NIG_REG_P0_TX_ARB_CREDIT_UPPER_BOUND_4, credit_upper_bound);
 515         REG_WR(bp, (port) ? NIG_REG_P1_TX_ARB_CREDIT_UPPER_BOUND_5 :
 516                    NIG_REG_P0_TX_ARB_CREDIT_UPPER_BOUND_5, credit_upper_bound);
 517
 518         if (!port) {
 519                 REG_WR(bp, NIG_REG_P0_TX_ARB_CREDIT_UPPER_BOUND_6,
 520                         credit_upper_bound);
 521                 REG_WR(bp, NIG_REG_P0_TX_ARB_CREDIT_UPPER_BOUND_7,
 522                         credit_upper_bound);
 523                 REG_WR(bp, NIG_REG_P0_TX_ARB_CREDIT_UPPER_BOUND_8,
 524                         credit_upper_bound);
 525         }
 526 }
 527 /******************************************************************************
 528 * Description:
 529 *       Will return the NIG ETS registers to init values.Except
 530 *       credit_upper_bound.
 531 *       That isn't used in this configuration (No WFQ is enabled) and will be
 532 *       configured acording to spec
 533 *.
 534 ******************************************************************************/
 535 static void bnx2x_ets_e3b0_nig_disabled(const struct link_params *params,
 536                                         const struct link_vars *vars)
 537 {
 538         struct bnx2x *bp = params->bp;
 539         const u8 port = params->port;
 540         const u32 min_w_val = bnx2x_ets_get_min_w_val_nig(vars);
 541         /**
 542          * mapping between entry  priority to client number (0,1,2 -debug and
 543          * management clients, 3 - COS0 client, 4 - COS1, ... 8 -
 544          * COS5)(HIGHEST) 4bits client num.TODO_ETS - Should be done by
 545          * reset value or init tool
 546          */
 547         if (port) {
 548                 REG_WR(bp, NIG_REG_P1_TX_ARB_PRIORITY_CLIENT2_LSB, 0x543210);
 549                 REG_WR(bp, NIG_REG_P1_TX_ARB_PRIORITY_CLIENT2_MSB, 0x0);
 550         } else {
 551                 REG_WR(bp, NIG_REG_P0_TX_ARB_PRIORITY_CLIENT2_LSB, 0x76543210);
 552                 REG_WR(bp, NIG_REG_P0_TX_ARB_PRIORITY_CLIENT2_MSB, 0x8);
 553         }
 554         /**
 555         * For strict priority entries defines the number of consecutive
 556         * slots for the highest priority.
 557         */
 558         /* TODO_ETS - Should be done by reset value or init tool */
 559         REG_WR(bp, (port) ? NIG_REG_P1_TX_ARB_NUM_STRICT_ARB_SLOTS :
 560                    NIG_REG_P1_TX_ARB_NUM_STRICT_ARB_SLOTS, 0x100);
 561         /**
 562          * mapping between the CREDIT_WEIGHT registers and actual client
 563          * numbers
 564          */
 565         /* TODO_ETS - Should be done by reset value or init tool */
 566         if (port) {
 567                 /*Port 1 has 6 COS*/
 568                 REG_WR(bp, NIG_REG_P1_TX_ARB_CLIENT_CREDIT_MAP2_LSB, 0x210543);
 569                 REG_WR(bp, NIG_REG_P1_TX_ARB_CLIENT_CREDIT_MAP2_MSB, 0x0);
 570         } else {
 571                 /*Port 0 has 9 COS*/
 572                 REG_WR(bp, NIG_REG_P0_TX_ARB_CLIENT_CREDIT_MAP2_LSB,
 573                        0x43210876);
 574                 REG_WR(bp, NIG_REG_P0_TX_ARB_CLIENT_CREDIT_MAP2_MSB, 0x5);
 575         }
 576
 577         /**
 578          * Bitmap of 5bits length. Each bit specifies whether the entry behaves
 579          * as strict.  Bits 0,1,2 - debug and management entries, 3 -
 580          * COS0 entry, 4 - COS1 entry.
 581          * COS1 | COS0 | DEBUG1 | DEBUG0 | MGMT
 582          * bit4   bit3    bit2   bit1     bit0
 583          * MCP and debug are strict
 584          */
 585         if (port)
 586                 REG_WR(bp, NIG_REG_P1_TX_ARB_CLIENT_IS_STRICT, 0x3f);
 587         else
 588                 REG_WR(bp, NIG_REG_P0_TX_ARB_CLIENT_IS_STRICT, 0x1ff);
 589         /* defines which entries (clients) are subjected to WFQ arbitration */
 590         REG_WR(bp, (port) ? NIG_REG_P1_TX_ARB_CLIENT_IS_SUBJECT2WFQ :
 591                    NIG_REG_P0_TX_ARB_CLIENT_IS_SUBJECT2WFQ, 0);
 592
 593         /**
 594         * Please notice the register address are note continuous and a
 595         * for here is note appropriate.In 2 port mode port0 only COS0-5
 596         * can be used. DEBUG1,DEBUG1,MGMT are never used for WFQ* In 4
 597         * port mode port1 only COS0-2 can be used. DEBUG1,DEBUG1,MGMT
 598         * are never used for WFQ
 599         */
 600         REG_WR(bp, (port) ? NIG_REG_P1_TX_ARB_CREDIT_WEIGHT_0 :
 601                    NIG_REG_P0_TX_ARB_CREDIT_WEIGHT_0, 0x0);
 602         REG_WR(bp, (port) ? NIG_REG_P1_TX_ARB_CREDIT_WEIGHT_1 :
 603                    NIG_REG_P0_TX_ARB_CREDIT_WEIGHT_1, 0x0);
 604         REG_WR(bp, (port) ? NIG_REG_P1_TX_ARB_CREDIT_WEIGHT_2 :
 605                    NIG_REG_P0_TX_ARB_CREDIT_WEIGHT_2, 0x0);
 606         REG_WR(bp, (port) ? NIG_REG_P1_TX_ARB_CREDIT_WEIGHT_3 :
 607                    NIG_REG_P0_TX_ARB_CREDIT_WEIGHT_3, 0x0);
 608         REG_WR(bp, (port) ? NIG_REG_P1_TX_ARB_CREDIT_WEIGHT_4 :
 609                    NIG_REG_P0_TX_ARB_CREDIT_WEIGHT_4, 0x0);
 610         REG_WR(bp, (port) ? NIG_REG_P1_TX_ARB_CREDIT_WEIGHT_5 :
 611                    NIG_REG_P0_TX_ARB_CREDIT_WEIGHT_5, 0x0);
 612         if (!port) {
 613                 REG_WR(bp, NIG_REG_P0_TX_ARB_CREDIT_WEIGHT_6, 0x0);
 614                 REG_WR(bp, NIG_REG_P0_TX_ARB_CREDIT_WEIGHT_7, 0x0);
 615                 REG_WR(bp, NIG_REG_P0_TX_ARB_CREDIT_WEIGHT_8, 0x0);
 616         }
 617
 618         bnx2x_ets_e3b0_set_credit_upper_bound_nig(params, min_w_val);
 619 }
 620 /******************************************************************************
 621 * Description:
 622 *       Set credit upper bound for PBF.
 623 *.
 624 ******************************************************************************/
 625 static void bnx2x_ets_e3b0_set_credit_upper_bound_pbf(
 626         const struct link_params *params,
 627         const u32 min_w_val)
 628 {
 629         struct bnx2x *bp = params->bp;
 630         const u32 credit_upper_bound =
 631             bnx2x_ets_get_credit_upper_bound(min_w_val);
 632         const u8 port = params->port;
 633         u32 base_upper_bound = 0;
 634         u8 max_cos = 0;
 635         u8 i = 0;
 636         /**
 637         * In 2 port mode port0 has COS0-5 that can be used for WFQ.In 4
 638         * port mode port1 has COS0-2 that can be used for WFQ.
 639         */
 640         if (!port) {
 641                 base_upper_bound = PBF_REG_COS0_UPPER_BOUND_P0;
 642                 max_cos = DCBX_E3B0_MAX_NUM_COS_PORT0;
 643         } else {
 644                 base_upper_bound = PBF_REG_COS0_UPPER_BOUND_P1;
 645                 max_cos = DCBX_E3B0_MAX_NUM_COS_PORT1;
 646         }
 647
 648         for (i = 0; i < max_cos; i++)
 649                 REG_WR(bp, base_upper_bound + (i << 2), credit_upper_bound);
 650 }
 651
 652 /******************************************************************************
 653 * Description:
 654 *       Will return the PBF ETS registers to init values.Except
 655 *       credit_upper_bound.
 656 *       That isn't used in this configuration (No WFQ is enabled) and will be
 657 *       configured acording to spec
 658 *.
 659 ******************************************************************************/
 660 static void bnx2x_ets_e3b0_pbf_disabled(const struct link_params *params)
 661 {
 662         struct bnx2x *bp = params->bp;
 663         const u8 port = params->port;
 664         const u32 min_w_val_pbf = ETS_E3B0_PBF_MIN_W_VAL;
 665         u8 i = 0;
 666         u32 base_weight = 0;
 667         u8 max_cos = 0;
 668
 669         /**
 670          * mapping between entry  priority to client number 0 - COS0
 671          * client, 2 - COS1, ... 5 - COS5)(HIGHEST) 4bits client num.
 672          * TODO_ETS - Should be done by reset value or init tool
 673          */
 674         if (port)
 675                 /*  0x688 (|011|0 10|00 1|000) */
 676                 REG_WR(bp, PBF_REG_ETS_ARB_PRIORITY_CLIENT_P1 , 0x688);
 677         else
 678                 /*  (10 1|100 |011|0 10|00 1|000) */
 679                 REG_WR(bp, PBF_REG_ETS_ARB_PRIORITY_CLIENT_P0 , 0x2C688);
 680
 681         /* TODO_ETS - Should be done by reset value or init tool */
 682         if (port)
 683                 /* 0x688 (|011|0 10|00 1|000)*/
 684                 REG_WR(bp, PBF_REG_ETS_ARB_CLIENT_CREDIT_MAP_P1, 0x688);
 685         else
 686         /* 0x2C688 (10 1|100 |011|0 10|00 1|000) */
 687         REG_WR(bp, PBF_REG_ETS_ARB_CLIENT_CREDIT_MAP_P0, 0x2C688);
 688
 689         REG_WR(bp, (port) ? PBF_REG_ETS_ARB_NUM_STRICT_ARB_SLOTS_P1 :
 690                    PBF_REG_ETS_ARB_NUM_STRICT_ARB_SLOTS_P0 , 0x100);
 691
 692
 693         REG_WR(bp, (port) ? PBF_REG_ETS_ARB_CLIENT_IS_STRICT_P1 :
 694                    PBF_REG_ETS_ARB_CLIENT_IS_STRICT_P0 , 0);
 695
 696         REG_WR(bp, (port) ? PBF_REG_ETS_ARB_CLIENT_IS_SUBJECT2WFQ_P1 :
 697                    PBF_REG_ETS_ARB_CLIENT_IS_SUBJECT2WFQ_P0 , 0);
 698         /**
 699         * In 2 port mode port0 has COS0-5 that can be used for WFQ.
 700         * In 4 port mode port1 has COS0-2 that can be used for WFQ.
 701         */
 702         if (!port) {
 703                 base_weight = PBF_REG_COS0_WEIGHT_P0;
 704                 max_cos = DCBX_E3B0_MAX_NUM_COS_PORT0;
 705         } else {
 706                 base_weight = PBF_REG_COS0_WEIGHT_P1;
 707                 max_cos = DCBX_E3B0_MAX_NUM_COS_PORT1;
 708         }
 709
 710         for (i = 0; i < max_cos; i++)
 711                 REG_WR(bp, base_weight + (0x4 * i), 0);
 712
 713         bnx2x_ets_e3b0_set_credit_upper_bound_pbf(params, min_w_val_pbf);
 714 }
 715 /******************************************************************************
 716 * Description:
 717 *       E3B0 disable will return basicly the values to init values.
 718 *.
 719 ******************************************************************************/
 720 static int bnx2x_ets_e3b0_disabled(const struct link_params *params,
 721                                    const struct link_vars *vars)
 722 {
 723         struct bnx2x *bp = params->bp;
 724
 725         if (!CHIP_IS_E3B0(bp)) {
 726                 DP(NETIF_MSG_LINK,
 727                    "bnx2x_ets_e3b0_disabled the chip isn't E3B0\n");
 728                 return -EINVAL;
 729         }
 730
 731         bnx2x_ets_e3b0_nig_disabled(params, vars);
 732
 733         bnx2x_ets_e3b0_pbf_disabled(params);
 734
 735         return 0;
 736 }
 737
 738 /******************************************************************************
 739 * Description:
 740 *       Disable will return basicly the values to init values.
 741 *.
 742 ******************************************************************************/
 743 int bnx2x_ets_disabled(struct link_params *params,
 744                       struct link_vars *vars)
 745 {
 746         struct bnx2x *bp = params->bp;
 747         int bnx2x_status = 0;
 748
 749         if ((CHIP_IS_E2(bp)) || (CHIP_IS_E3A0(bp)))
 750                 bnx2x_ets_e2e3a0_disabled(params);
 751         else if (CHIP_IS_E3B0(bp))
 752                 bnx2x_status = bnx2x_ets_e3b0_disabled(params, vars);
 753         else {
 754                 DP(NETIF_MSG_LINK, "bnx2x_ets_disabled - chip not supported\n");
 755                 return -EINVAL;
 756         }
 757
 758         return bnx2x_status;
 759 }
 760
 761 /******************************************************************************
 762 * Description
 763 *       Set the COS mappimg to SP and BW until this point all the COS are not
 764 *       set as SP or BW.
 765 ******************************************************************************/
 766 static int bnx2x_ets_e3b0_cli_map(const struct link_params *params,
 767                                   const struct bnx2x_ets_params *ets_params,
 768                                   const u8 cos_sp_bitmap,
 769                                   const u8 cos_bw_bitmap)
 770 {
 771         struct bnx2x *bp = params->bp;
 772         const u8 port = params->port;
 773         const u8 nig_cli_sp_bitmap = 0x7 | (cos_sp_bitmap << 3);
 774         const u8 pbf_cli_sp_bitmap = cos_sp_bitmap;
 775         const u8 nig_cli_subject2wfq_bitmap = cos_bw_bitmap << 3;
 776         const u8 pbf_cli_subject2wfq_bitmap = cos_bw_bitmap;
 777
 778         REG_WR(bp, (port) ? NIG_REG_P1_TX_ARB_CLIENT_IS_STRICT :
 779                NIG_REG_P0_TX_ARB_CLIENT_IS_STRICT, nig_cli_sp_bitmap);
 780
 781         REG_WR(bp, (port) ? PBF_REG_ETS_ARB_CLIENT_IS_STRICT_P1 :
 782                PBF_REG_ETS_ARB_CLIENT_IS_STRICT_P0 , pbf_cli_sp_bitmap);
 783
 784         REG_WR(bp, (port) ? NIG_REG_P1_TX_ARB_CLIENT_IS_SUBJECT2WFQ :
 785                NIG_REG_P0_TX_ARB_CLIENT_IS_SUBJECT2WFQ,
 786                nig_cli_subject2wfq_bitmap);
 787
 788         REG_WR(bp, (port) ? PBF_REG_ETS_ARB_CLIENT_IS_SUBJECT2WFQ_P1 :
 789                PBF_REG_ETS_ARB_CLIENT_IS_SUBJECT2WFQ_P0,
 790                pbf_cli_subject2wfq_bitmap);
 791
 792         return 0;
 793 }
 794
 795 /******************************************************************************
 796 * Description:
 797 *       This function is needed because NIG ARB_CREDIT_WEIGHT_X are
 798 *       not continues and ARB_CREDIT_WEIGHT_0 + offset is suitable.
 799 ******************************************************************************/
 800 static int bnx2x_ets_e3b0_set_cos_bw(struct bnx2x *bp,
 801                                      const u8 cos_entry,
 802                                      const u32 min_w_val_nig,
 803                                      const u32 min_w_val_pbf,
 804                                      const u16 total_bw,
 805                                      const u8 bw,
 806                                      const u8 port)
 807 {
 808         u32 nig_reg_adress_crd_weight = 0;
 809         u32 pbf_reg_adress_crd_weight = 0;
 810         /* Calculate and set BW for this COS - use 1 instead of 0 for BW */
 811         const u32 cos_bw_nig = ((bw ? bw : 1) * min_w_val_nig) / total_bw;
 812         const u32 cos_bw_pbf = ((bw ? bw : 1) * min_w_val_pbf) / total_bw;
 813
 814         switch (cos_entry) {
 815         case 0:
 816             nig_reg_adress_crd_weight =
 817                  (port) ? NIG_REG_P1_TX_ARB_CREDIT_WEIGHT_0 :
 818                      NIG_REG_P0_TX_ARB_CREDIT_WEIGHT_0;
 819              pbf_reg_adress_crd_weight = (port) ?
 820                  PBF_REG_COS0_WEIGHT_P1 : PBF_REG_COS0_WEIGHT_P0;
 821              break;
 822         case 1:
 823              nig_reg_adress_crd_weight = (port) ?
 824                  NIG_REG_P1_TX_ARB_CREDIT_WEIGHT_1 :
 825                  NIG_REG_P0_TX_ARB_CREDIT_WEIGHT_1;
 826              pbf_reg_adress_crd_weight = (port) ?
 827                  PBF_REG_COS1_WEIGHT_P1 : PBF_REG_COS1_WEIGHT_P0;
 828              break;
 829         case 2:
 830              nig_reg_adress_crd_weight = (port) ?
 831                  NIG_REG_P1_TX_ARB_CREDIT_WEIGHT_2 :
 832                  NIG_REG_P0_TX_ARB_CREDIT_WEIGHT_2;
 833
 834                  pbf_reg_adress_crd_weight = (port) ?
 835                      PBF_REG_COS2_WEIGHT_P1 : PBF_REG_COS2_WEIGHT_P0;
 836              break;
 837         case 3:
 838             if (port)
 839                         return -EINVAL;
 840              nig_reg_adress_crd_weight =
 841                  NIG_REG_P0_TX_ARB_CREDIT_WEIGHT_3;
 842              pbf_reg_adress_crd_weight =
 843                  PBF_REG_COS3_WEIGHT_P0;
 844              break;
 845         case 4:
 846             if (port)
 847                 return -EINVAL;
 848              nig_reg_adress_crd_weight =
 849                  NIG_REG_P0_TX_ARB_CREDIT_WEIGHT_4;
 850              pbf_reg_adress_crd_weight = PBF_REG_COS4_WEIGHT_P0;
 851              break;
 852         case 5:
 853             if (port)
 854                 return -EINVAL;
 855              nig_reg_adress_crd_weight =
 856                  NIG_REG_P0_TX_ARB_CREDIT_WEIGHT_5;
 857              pbf_reg_adress_crd_weight = PBF_REG_COS5_WEIGHT_P0;
 858              break;
 859         }
 860
 861         REG_WR(bp, nig_reg_adress_crd_weight, cos_bw_nig);
 862
 863         REG_WR(bp, pbf_reg_adress_crd_weight, cos_bw_pbf);
 864
 865         return 0;
 866 }
 867 /******************************************************************************
 868 * Description:
 869 *       Calculate the total BW.A value of 0 isn't legal.
 870 *.
 871 ******************************************************************************/
 872 static int bnx2x_ets_e3b0_get_total_bw(
 873         const struct link_params *params,
 874         struct bnx2x_ets_params *ets_params,
 875         u16 *total_bw)
 876 {
 877         struct bnx2x *bp = params->bp;
 878         u8 cos_idx = 0;
 879         u8 is_bw_cos_exist = 0;
 880
 881         *total_bw = 0 ;
 882
 883         /* Calculate total BW requested */
 884         for (cos_idx = 0; cos_idx < ets_params->num_of_cos; cos_idx++) {
 885                 if (ets_params->cos[cos_idx].state == bnx2x_cos_state_bw) {
 886                         is_bw_cos_exist = 1;
 887                         if (!ets_params->cos[cos_idx].params.bw_params.bw) {
 888                                 DP(NETIF_MSG_LINK, "bnx2x_ets_E3B0_config BW"
 889                                                    "was set to 0\n");
 890                                 /*
 891                                  * This is to prevent a state when ramrods
 892                                  * can't be sent
 893                                 */
 894                                 ets_params->cos[cos_idx].params.bw_params.bw
 895                                          = 1;
 896                         }
 897                         *total_bw +=
 898                                 ets_params->cos[cos_idx].params.bw_params.bw;
 899                 }
 900         }
 901
 902         /* Check total BW is valid */
 903         if ((is_bw_cos_exist == 1) && (*total_bw != 100)) {
 904                 if (*total_bw == 0) {
 905                         DP(NETIF_MSG_LINK,
 906                            "bnx2x_ets_E3B0_config total BW shouldn't be 0\n");
 907                         return -EINVAL;
 908                 }
 909                 DP(NETIF_MSG_LINK,
 910                    "bnx2x_ets_E3B0_config total BW should be 100\n");
 911                 /*
 912                  * We can handle a case whre the BW isn't 100 this can happen
 913                  * if the TC are joined.
 914                  */
 915         }
 916         return 0;
 917 }
 918
 919 /******************************************************************************
 920 * Description:
 921 *       Invalidate all the sp_pri_to_cos.
 922 *.
 923 ******************************************************************************/
 924 static void bnx2x_ets_e3b0_sp_pri_to_cos_init(u8 *sp_pri_to_cos)
 925 {
 926         u8 pri = 0;
 927         for (pri = 0; pri < DCBX_MAX_NUM_COS; pri++)
 928                 sp_pri_to_cos[pri] = DCBX_INVALID_COS;
 929 }
 930 /******************************************************************************
 931 * Description:
 932 *       Calculate and set the SP (ARB_PRIORITY_CLIENT) NIG and PBF registers
 933 *       according to sp_pri_to_cos.
 934 *.
 935 ******************************************************************************/
 936 static int bnx2x_ets_e3b0_sp_pri_to_cos_set(const struct link_params *params,
 937                                             u8 *sp_pri_to_cos, const u8 pri,
 938                                             const u8 cos_entry)
 939 {
 940         struct bnx2x *bp = params->bp;
 941         const u8 port = params->port;
 942         const u8 max_num_of_cos = (port) ? DCBX_E3B0_MAX_NUM_COS_PORT1 :
 943                 DCBX_E3B0_MAX_NUM_COS_PORT0;
 944
 945         if (sp_pri_to_cos[pri] != DCBX_INVALID_COS) {
 946                 DP(NETIF_MSG_LINK, "bnx2x_ets_e3b0_sp_pri_to_cos_set invalid "
 947                                    "parameter There can't be two COS's with "
 948                                    "the same strict pri\n");
 949                 return -EINVAL;
 950         }
 951
 952         if (pri > max_num_of_cos) {
 953                 DP(NETIF_MSG_LINK, "bnx2x_ets_e3b0_sp_pri_to_cos_set invalid "
 954                    "parameter Illegal strict priority\n");
 955             return -EINVAL;
 956         }
 957
 958         sp_pri_to_cos[pri] = cos_entry;
 959         return 0;
 960
 961 }
 962
 963 /******************************************************************************
 964 * Description:
 965 *       Returns the correct value according to COS and priority in
 966 *       the sp_pri_cli register.
 967 *.
 968 ******************************************************************************/
 969 static u64 bnx2x_e3b0_sp_get_pri_cli_reg(const u8 cos, const u8 cos_offset,
 970                                          const u8 pri_set,
 971                                          const u8 pri_offset,
 972                                          const u8 entry_size)
 973 {
 974         u64 pri_cli_nig = 0;
 975         pri_cli_nig = ((u64)(cos + cos_offset)) << (entry_size *
 976                                                     (pri_set + pri_offset));
 977
 978         return pri_cli_nig;
 979 }
 980 /******************************************************************************
 981 * Description:
 982 *       Returns the correct value according to COS and priority in the
 983 *       sp_pri_cli register for NIG.
 984 *.
 985 ******************************************************************************/
 986 static u64 bnx2x_e3b0_sp_get_pri_cli_reg_nig(const u8 cos, const u8 pri_set)
 987 {
 988         /* MCP Dbg0 and dbg1 are always with higher strict pri*/
 989         const u8 nig_cos_offset = 3;
 990         const u8 nig_pri_offset = 3;
 991
 992         return bnx2x_e3b0_sp_get_pri_cli_reg(cos, nig_cos_offset, pri_set,
 993                 nig_pri_offset, 4);
 994
 995 }
 996 /******************************************************************************
 997 * Description:
 998 *       Returns the correct value according to COS and priority in the
 999 *       sp_pri_cli register for PBF.
1000 *.
1001 ******************************************************************************/
1002 static u64 bnx2x_e3b0_sp_get_pri_cli_reg_pbf(const u8 cos, const u8 pri_set)
1003 {
1004         const u8 pbf_cos_offset = 0;
1005         const u8 pbf_pri_offset = 0;
1006
1007         return bnx2x_e3b0_sp_get_pri_cli_reg(cos, pbf_cos_offset, pri_set,
1008                 pbf_pri_offset, 3);
1009
1010 }
1011
1012 /******************************************************************************
1013 * Description:
1014 *       Calculate and set the SP (ARB_PRIORITY_CLIENT) NIG and PBF registers
1015 *       according to sp_pri_to_cos.(which COS has higher priority)
1016 *.
1017 ******************************************************************************/
1018 static int bnx2x_ets_e3b0_sp_set_pri_cli_reg(const struct link_params *params,
1019                                              u8 *sp_pri_to_cos)
1020 {
1021         struct bnx2x *bp = params->bp;
1022         u8 i = 0;
1023         const u8 port = params->port;
1024         /* MCP Dbg0 and dbg1 are always with higher strict pri*/
1025         u64 pri_cli_nig = 0x210;
1026         u32 pri_cli_pbf = 0x0;
1027         u8 pri_set = 0;
1028         u8 pri_bitmask = 0;
1029         const u8 max_num_of_cos = (port) ? DCBX_E3B0_MAX_NUM_COS_PORT1 :
1030                 DCBX_E3B0_MAX_NUM_COS_PORT0;
1031
1032         u8 cos_bit_to_set = (1 << max_num_of_cos) - 1;
1033
1034         /* Set all the strict priority first */
1035         for (i = 0; i < max_num_of_cos; i++) {
1036                 if (sp_pri_to_cos[i] != DCBX_INVALID_COS) {
1037                         if (sp_pri_to_cos[i] >= DCBX_MAX_NUM_COS) {
1038                                 DP(NETIF_MSG_LINK,
1039                                            "bnx2x_ets_e3b0_sp_set_pri_cli_reg "
1040                                            "invalid cos entry\n");
1041                                 return -EINVAL;
1042                         }
1043
1044                         pri_cli_nig |= bnx2x_e3b0_sp_get_pri_cli_reg_nig(
1045                             sp_pri_to_cos[i], pri_set);
1046
1047                         pri_cli_pbf |= bnx2x_e3b0_sp_get_pri_cli_reg_pbf(
1048                             sp_pri_to_cos[i], pri_set);
1049                         pri_bitmask = 1 << sp_pri_to_cos[i];
1050                         /* COS is used remove it from bitmap.*/
1051                         if (!(pri_bitmask & cos_bit_to_set)) {
1052                                 DP(NETIF_MSG_LINK,
1053                                         "bnx2x_ets_e3b0_sp_set_pri_cli_reg "
1054                                         "invalid There can't be two COS's with"
1055                                         " the same strict pri\n");
1056                                 return -EINVAL;
1057                         }
1058                         cos_bit_to_set &= ~pri_bitmask;
1059                         pri_set++;
1060                 }
1061         }
1062
1063         /* Set all the Non strict priority i= COS*/
1064         for (i = 0; i < max_num_of_cos; i++) {
1065                 pri_bitmask = 1 << i;
1066                 /* Check if COS was already used for SP */
1067                 if (pri_bitmask & cos_bit_to_set) {
1068                         /* COS wasn't used for SP */
1069                         pri_cli_nig |= bnx2x_e3b0_sp_get_pri_cli_reg_nig(
1070                             i, pri_set);
1071
1072                         pri_cli_pbf |= bnx2x_e3b0_sp_get_pri_cli_reg_pbf(
1073                             i, pri_set);
1074                         /* COS is used remove it from bitmap.*/
1075                         cos_bit_to_set &= ~pri_bitmask;
1076                         pri_set++;
1077                 }
1078         }
1079
1080         if (pri_set != max_num_of_cos) {
1081                 DP(NETIF_MSG_LINK, "bnx2x_ets_e3b0_sp_set_pri_cli_reg not all "
1082                                    "entries were set\n");
1083                 return -EINVAL;
1084         }
1085
1086         if (port) {
1087                 /* Only 6 usable clients*/
1088                 REG_WR(bp, NIG_REG_P1_TX_ARB_PRIORITY_CLIENT2_LSB,
1089                        (u32)pri_cli_nig);
1090
1091                 REG_WR(bp, PBF_REG_ETS_ARB_PRIORITY_CLIENT_P1 , pri_cli_pbf);
1092         } else {
1093                 /* Only 9 usable clients*/
1094                 const u32 pri_cli_nig_lsb = (u32) (pri_cli_nig);
1095                 const u32 pri_cli_nig_msb = (u32) ((pri_cli_nig >> 32) & 0xF);
1096
1097                 REG_WR(bp, NIG_REG_P0_TX_ARB_PRIORITY_CLIENT2_LSB,
1098                        pri_cli_nig_lsb);
1099                 REG_WR(bp, NIG_REG_P0_TX_ARB_PRIORITY_CLIENT2_MSB,
1100                        pri_cli_nig_msb);
1101
1102                 REG_WR(bp, PBF_REG_ETS_ARB_PRIORITY_CLIENT_P0 , pri_cli_pbf);
1103         }
1104         return 0;
1105 }
1106
1107 /******************************************************************************
1108 * Description:
1109 *       Configure the COS to ETS according to BW and SP settings.
1110 ******************************************************************************/
1111 int bnx2x_ets_e3b0_config(const struct link_params *params,
1112                          const struct link_vars *vars,
1113                          struct bnx2x_ets_params *ets_params)
1114 {
1115         struct bnx2x *bp = params->bp;
1116         int bnx2x_status = 0;
1117         const u8 port = params->port;
1118         u16 total_bw = 0;
1119         const u32 min_w_val_nig = bnx2x_ets_get_min_w_val_nig(vars);
1120         const u32 min_w_val_pbf = ETS_E3B0_PBF_MIN_W_VAL;
1121         u8 cos_bw_bitmap = 0;
1122         u8 cos_sp_bitmap = 0;
1123         u8 sp_pri_to_cos[DCBX_MAX_NUM_COS] = {0};
1124         const u8 max_num_of_cos = (port) ? DCBX_E3B0_MAX_NUM_COS_PORT1 :
1125                 DCBX_E3B0_MAX_NUM_COS_PORT0;
1126         u8 cos_entry = 0;
1127
1128         if (!CHIP_IS_E3B0(bp)) {
1129                 DP(NETIF_MSG_LINK,
1130                    "bnx2x_ets_e3b0_disabled the chip isn't E3B0\n");
1131                 return -EINVAL;
1132         }
1133
1134         if ((ets_params->num_of_cos > max_num_of_cos)) {
1135                 DP(NETIF_MSG_LINK, "bnx2x_ets_E3B0_config the number of COS "
1136                                    "isn't supported\n");
1137                 return -EINVAL;
1138         }
1139
1140         /* Prepare sp strict priority parameters*/
1141         bnx2x_ets_e3b0_sp_pri_to_cos_init(sp_pri_to_cos);
1142
1143         /* Prepare BW parameters*/
1144         bnx2x_status = bnx2x_ets_e3b0_get_total_bw(params, ets_params,
1145                                                    &total_bw);
1146         if (bnx2x_status) {
1147                 DP(NETIF_MSG_LINK,
1148                    "bnx2x_ets_E3B0_config get_total_bw failed\n");
1149                 return -EINVAL;
1150         }
1151
1152         /*
1153          * Upper bound is set according to current link speed (min_w_val
1154          * should be the same for upper bound and COS credit val).
1155          */
1156         bnx2x_ets_e3b0_set_credit_upper_bound_nig(params, min_w_val_nig);
1157         bnx2x_ets_e3b0_set_credit_upper_bound_pbf(params, min_w_val_pbf);
1158
1159
1160         for (cos_entry = 0; cos_entry < ets_params->num_of_cos; cos_entry++) {
1161                 if (bnx2x_cos_state_bw == ets_params->cos[cos_entry].state) {
1162                         cos_bw_bitmap |= (1 << cos_entry);
1163                         /*
1164                          * The function also sets the BW in HW(not the mappin
1165                          * yet)
1166                          */
1167                         bnx2x_status = bnx2x_ets_e3b0_set_cos_bw(
1168                                 bp, cos_entry, min_w_val_nig, min_w_val_pbf,
1169                                 total_bw,
1170                                 ets_params->cos[cos_entry].params.bw_params.bw,
1171                                  port);
1172                 } else if (bnx2x_cos_state_strict ==
1173                         ets_params->cos[cos_entry].state){
1174                         cos_sp_bitmap |= (1 << cos_entry);
1175
1176                         bnx2x_status = bnx2x_ets_e3b0_sp_pri_to_cos_set(
1177                                 params,
1178                                 sp_pri_to_cos,
1179                                 ets_params->cos[cos_entry].params.sp_params.pri,
1180                                 cos_entry);
1181
1182                 } else {
1183                         DP(NETIF_MSG_LINK,
1184                            "bnx2x_ets_e3b0_config cos state not valid\n");
1185                         return -EINVAL;
1186                 }
1187                 if (bnx2x_status) {
1188                         DP(NETIF_MSG_LINK,
1189                            "bnx2x_ets_e3b0_config set cos bw failed\n");
1190                         return bnx2x_status;
1191                 }
1192         }
1193
1194         /* Set SP register (which COS has higher priority) */
1195         bnx2x_status = bnx2x_ets_e3b0_sp_set_pri_cli_reg(params,
1196                                                          sp_pri_to_cos);
1197
1198         if (bnx2x_status) {
1199                 DP(NETIF_MSG_LINK,
1200                    "bnx2x_ets_E3B0_config set_pri_cli_reg failed\n");
1201                 return bnx2x_status;
1202         }
1203
1204         /* Set client mapping of BW and strict */
1205         bnx2x_status = bnx2x_ets_e3b0_cli_map(params, ets_params,
1206                                               cos_sp_bitmap,
1207                                               cos_bw_bitmap);
1208
1209         if (bnx2x_status) {
1210                 DP(NETIF_MSG_LINK, "bnx2x_ets_E3B0_config SP failed\n");
1211                 return bnx2x_status;
1212         }
1213         return 0;
1214 }
1215 static void bnx2x_ets_bw_limit_common(const struct link_params *params)
1216 {
1217         /* ETS disabled configuration */
1218         struct bnx2x *bp = params->bp;
1219         DP(NETIF_MSG_LINK, "ETS enabled BW limit configuration\n");
1220         /*
1221          * defines which entries (clients) are subjected to WFQ arbitration
1222          * COS0 0x8
1223          * COS1 0x10
1224          */
1225         REG_WR(bp, NIG_REG_P0_TX_ARB_CLIENT_IS_SUBJECT2WFQ, 0x18);
1226         /*
1227          * mapping between the ARB_CREDIT_WEIGHT registers and actual
1228          * client numbers (WEIGHT_0 does not actually have to represent
1229          * client 0)
1230          *    PRI4    |    PRI3    |    PRI2    |    PRI1    |    PRI0
1231          *  cos1-001     cos0-000     dbg1-100     dbg0-011     MCP-010
1232          */
1233         REG_WR(bp, NIG_REG_P0_TX_ARB_CLIENT_CREDIT_MAP, 0x111A);
1234
1235         REG_WR(bp, NIG_REG_P0_TX_ARB_CREDIT_UPPER_BOUND_0,
1236                ETS_BW_LIMIT_CREDIT_UPPER_BOUND);
1237         REG_WR(bp, NIG_REG_P0_TX_ARB_CREDIT_UPPER_BOUND_1,
1238                ETS_BW_LIMIT_CREDIT_UPPER_BOUND);
1239
1240         /* ETS mode enabled*/
1241         REG_WR(bp, PBF_REG_ETS_ENABLED, 1);
1242
1243         /* Defines the number of consecutive slots for the strict priority */
1244         REG_WR(bp, PBF_REG_NUM_STRICT_ARB_SLOTS, 0);
1245         /*
1246          * Bitmap of 5bits length. Each bit specifies whether the entry behaves
1247          * as strict.  Bits 0,1,2 - debug and management entries, 3 - COS0
1248          * entry, 4 - COS1 entry.
1249          * COS1 | COS0 | DEBUG21 | DEBUG0 | MGMT
1250          * bit4   bit3    bit2     bit1    bit0
1251          * MCP and debug are strict
1252          */
1253         REG_WR(bp, NIG_REG_P0_TX_ARB_CLIENT_IS_STRICT, 0x7);
1254
1255         /* Upper bound that COS0_WEIGHT can reach in the WFQ arbiter.*/
1256         REG_WR(bp, PBF_REG_COS0_UPPER_BOUND,
1257                ETS_BW_LIMIT_CREDIT_UPPER_BOUND);
1258         REG_WR(bp, PBF_REG_COS1_UPPER_BOUND,
1259                ETS_BW_LIMIT_CREDIT_UPPER_BOUND);
1260 }
1261
1262 void bnx2x_ets_bw_limit(const struct link_params *params, const u32 cos0_bw,
1263                         const u32 cos1_bw)
1264 {
1265         /* ETS disabled configuration*/
1266         struct bnx2x *bp = params->bp;
1267         const u32 total_bw = cos0_bw + cos1_bw;
1268         u32 cos0_credit_weight = 0;
1269         u32 cos1_credit_weight = 0;
1270
1271         DP(NETIF_MSG_LINK, "ETS enabled BW limit configuration\n");
1272
1273         if ((!total_bw) ||
1274             (!cos0_bw) ||
1275             (!cos1_bw)) {
1276                 DP(NETIF_MSG_LINK, "Total BW can't be zero\n");
1277                 return;
1278         }
1279
1280         cos0_credit_weight = (cos0_bw * ETS_BW_LIMIT_CREDIT_WEIGHT)/
1281                 total_bw;
1282         cos1_credit_weight = (cos1_bw * ETS_BW_LIMIT_CREDIT_WEIGHT)/
1283                 total_bw;
1284
1285         bnx2x_ets_bw_limit_common(params);
1286
1287         REG_WR(bp, NIG_REG_P0_TX_ARB_CREDIT_WEIGHT_0, cos0_credit_weight);
1288         REG_WR(bp, NIG_REG_P0_TX_ARB_CREDIT_WEIGHT_1, cos1_credit_weight);
1289
1290         REG_WR(bp, PBF_REG_COS0_WEIGHT, cos0_credit_weight);
1291         REG_WR(bp, PBF_REG_COS1_WEIGHT, cos1_credit_weight);
1292 }
1293
1294 int bnx2x_ets_strict(const struct link_params *params, const u8 strict_cos)
1295 {
1296         /* ETS disabled configuration*/
1297         struct bnx2x *bp = params->bp;
1298         u32 val = 0;
1299
1300         DP(NETIF_MSG_LINK, "ETS enabled strict configuration\n");
1301         /*
1302          * Bitmap of 5bits length. Each bit specifies whether the entry behaves
1303          * as strict.  Bits 0,1,2 - debug and management entries,
1304          * 3 - COS0 entry, 4 - COS1 entry.
1305          *  COS1 | COS0 | DEBUG21 | DEBUG0 | MGMT
1306          *  bit4   bit3   bit2      bit1     bit0
1307          * MCP and debug are strict
1308          */
1309         REG_WR(bp, NIG_REG_P0_TX_ARB_CLIENT_IS_STRICT, 0x1F);
1310         /*
1311          * For strict priority entries defines the number of consecutive slots
1312          * for the highest priority.
1313          */
1314         REG_WR(bp, NIG_REG_P0_TX_ARB_NUM_STRICT_ARB_SLOTS, 0x100);
1315         /* ETS mode disable */
1316         REG_WR(bp, PBF_REG_ETS_ENABLED, 0);
1317         /* Defines the number of consecutive slots for the strict priority */
1318         REG_WR(bp, PBF_REG_NUM_STRICT_ARB_SLOTS, 0x100);
1319
1320         /* Defines the number of consecutive slots for the strict priority */
1321         REG_WR(bp, PBF_REG_HIGH_PRIORITY_COS_NUM, strict_cos);
1322
1323         /*
1324          * mapping between entry  priority to client number (0,1,2 -debug and
1325          * management clients, 3 - COS0 client, 4 - COS client)(HIGHEST)
1326          * 3bits client num.
1327          *   PRI4    |    PRI3    |    PRI2    |    PRI1    |    PRI0
1328          * dbg0-010     dbg1-001     cos1-100     cos0-011     MCP-000
1329          * dbg0-010     dbg1-001     cos0-011     cos1-100     MCP-000
1330          */
1331         val = (!strict_cos) ? 0x2318 : 0x22E0;
1332         REG_WR(bp, NIG_REG_P0_TX_ARB_PRIORITY_CLIENT, val);
1333
1334         return 0;
1335 }
1336 /******************************************************************/
1337 /*                      PFC section                               */
1338 /******************************************************************/
1339 static void bnx2x_update_pfc_xmac(struct link_params *params,
1340                                   struct link_vars *vars,
1341                                   u8 is_lb)
1342 {
1343         struct bnx2x *bp = params->bp;
1344         u32 xmac_base;
1345         u32 pause_val, pfc0_val, pfc1_val;
1346
1347         /* XMAC base adrr */
1348         xmac_base = (params->port) ? GRCBASE_XMAC1 : GRCBASE_XMAC0;
1349
1350         /* Initialize pause and pfc registers */
1351         pause_val = 0x18000;
1352         pfc0_val = 0xFFFF8000;
1353         pfc1_val = 0x2;
1354
1355         /* No PFC support */
1356         if (!(params->feature_config_flags &
1357               FEATURE_CONFIG_PFC_ENABLED)) {
1358
1359                 /*
1360                  * RX flow control - Process pause frame in receive direction
1361                  */
1362                 if (vars->flow_ctrl & BNX2X_FLOW_CTRL_RX)
1363                         pause_val |= XMAC_PAUSE_CTRL_REG_RX_PAUSE_EN;
1364
1365                 /*
1366                  * TX flow control - Send pause packet when buffer is full
1367                  */
1368                 if (vars->flow_ctrl & BNX2X_FLOW_CTRL_TX)
1369                         pause_val |= XMAC_PAUSE_CTRL_REG_TX_PAUSE_EN;
1370         } else {/* PFC support */
1371                 pfc1_val |= XMAC_PFC_CTRL_HI_REG_PFC_REFRESH_EN |
1372                         XMAC_PFC_CTRL_HI_REG_PFC_STATS_EN |
1373                         XMAC_PFC_CTRL_HI_REG_RX_PFC_EN |
1374                         XMAC_PFC_CTRL_HI_REG_TX_PFC_EN |
1375                         XMAC_PFC_CTRL_HI_REG_FORCE_PFC_XON;
1376                 /* Write pause and PFC registers */
1377                 REG_WR(bp, xmac_base + XMAC_REG_PAUSE_CTRL, pause_val);
1378                 REG_WR(bp, xmac_base + XMAC_REG_PFC_CTRL, pfc0_val);
1379                 REG_WR(bp, xmac_base + XMAC_REG_PFC_CTRL_HI, pfc1_val);
1380                 pfc1_val &= ~XMAC_PFC_CTRL_HI_REG_FORCE_PFC_XON;
1381
1382         }
1383
1384         /* Write pause and PFC registers */
1385         REG_WR(bp, xmac_base + XMAC_REG_PAUSE_CTRL, pause_val);
1386         REG_WR(bp, xmac_base + XMAC_REG_PFC_CTRL, pfc0_val);
1387         REG_WR(bp, xmac_base + XMAC_REG_PFC_CTRL_HI, pfc1_val);
1388
1389
1390         /* Set MAC address for source TX Pause/PFC frames */
1391         REG_WR(bp, xmac_base + XMAC_REG_CTRL_SA_LO,
1392                ((params->mac_addr[2] << 24) |
1393                 (params->mac_addr[3] << 16) |
1394                 (params->mac_addr[4] << 8) |
1395                 (params->mac_addr[5])));
1396         REG_WR(bp, xmac_base + XMAC_REG_CTRL_SA_HI,
1397                ((params->mac_addr[0] << 8) |
1398                 (params->mac_addr[1])));
1399
1400         udelay(30);
1401 }
1402
1403
1404 static void bnx2x_emac_get_pfc_stat(struct link_params *params,
1405                                     u32 pfc_frames_sent[2],
1406                                     u32 pfc_frames_received[2])
1407 {
1408         /* Read pfc statistic */
1409         struct bnx2x *bp = params->bp;
1410         u32 emac_base = params->port ? GRCBASE_EMAC1 : GRCBASE_EMAC0;
1411         u32 val_xon = 0;
1412         u32 val_xoff = 0;
1413
1414         DP(NETIF_MSG_LINK, "pfc statistic read from EMAC\n");
1415
1416         /* PFC received frames */
1417         val_xoff = REG_RD(bp, emac_base +
1418                                 EMAC_REG_RX_PFC_STATS_XOFF_RCVD);
1419         val_xoff &= EMAC_REG_RX_PFC_STATS_XOFF_RCVD_COUNT;
1420         val_xon = REG_RD(bp, emac_base + EMAC_REG_RX_PFC_STATS_XON_RCVD);
1421         val_xon &= EMAC_REG_RX_PFC_STATS_XON_RCVD_COUNT;
1422
1423         pfc_frames_received[0] = val_xon + val_xoff;
1424
1425         /* PFC received sent */
1426         val_xoff = REG_RD(bp, emac_base +
1427                                 EMAC_REG_RX_PFC_STATS_XOFF_SENT);
1428         val_xoff &= EMAC_REG_RX_PFC_STATS_XOFF_SENT_COUNT;
1429         val_xon = REG_RD(bp, emac_base + EMAC_REG_RX_PFC_STATS_XON_SENT);
1430         val_xon &= EMAC_REG_RX_PFC_STATS_XON_SENT_COUNT;
1431
1432         pfc_frames_sent[0] = val_xon + val_xoff;
1433 }
1434
1435 /* Read pfc statistic*/
1436 void bnx2x_pfc_statistic(struct link_params *params, struct link_vars *vars,
1437                          u32 pfc_frames_sent[2],
1438                          u32 pfc_frames_received[2])
1439 {
1440         /* Read pfc statistic */
1441         struct bnx2x *bp = params->bp;
1442
1443         DP(NETIF_MSG_LINK, "pfc statistic\n");
1444
1445         if (!vars->link_up)
1446                 return;
1447
1448         if (vars->mac_type == MAC_TYPE_EMAC) {
1449                 DP(NETIF_MSG_LINK, "About to read PFC stats from EMAC\n");
1450                 bnx2x_emac_get_pfc_stat(params, pfc_frames_sent,
1451                                         pfc_frames_received);
1452         }
1453 }
1454 /******************************************************************/
1455 /*                      MAC/PBF section                           */
1456 /******************************************************************/
1457 static void bnx2x_set_mdio_clk(struct bnx2x *bp, u32 chip_id, u8 port)
1458 {
1459         u32 mode, emac_base;
1460         /**
1461          * Set clause 45 mode, slow down the MDIO clock to 2.5MHz
1462          * (a value of 49==0x31) and make sure that the AUTO poll is off
1463          */
1464
1465         if (CHIP_IS_E2(bp))
1466                 emac_base = GRCBASE_EMAC0;
1467         else
1468                 emac_base = (port) ? GRCBASE_EMAC1 : GRCBASE_EMAC0;
1469         mode = REG_RD(bp, emac_base + EMAC_REG_EMAC_MDIO_MODE);
1470         mode &= ~(EMAC_MDIO_MODE_AUTO_POLL |
1471                   EMAC_MDIO_MODE_CLOCK_CNT);
1472         if (USES_WARPCORE(bp))
1473                 mode |= (74L << EMAC_MDIO_MODE_CLOCK_CNT_BITSHIFT);
1474         else
1475                 mode |= (49L << EMAC_MDIO_MODE_CLOCK_CNT_BITSHIFT);
1476
1477         mode |= (EMAC_MDIO_MODE_CLAUSE_45);
1478         REG_WR(bp, emac_base + EMAC_REG_EMAC_MDIO_MODE, mode);
1479
1480         udelay(40);
1481 }
1482 static u8 bnx2x_is_4_port_mode(struct bnx2x *bp)
1483 {
1484         u32 port4mode_ovwr_val;
1485         /* Check 4-port override enabled */
1486         port4mode_ovwr_val = REG_RD(bp, MISC_REG_PORT4MODE_EN_OVWR);
1487         if (port4mode_ovwr_val & (1<<0)) {
1488                 /* Return 4-port mode override value */
1489                 return ((port4mode_ovwr_val & (1<<1)) == (1<<1));
1490         }
1491         /* Return 4-port mode from input pin */
1492         return (u8)REG_RD(bp, MISC_REG_PORT4MODE_EN);
1493 }
1494
1495 static void bnx2x_emac_init(struct link_params *params,
1496                             struct link_vars *vars)
1497 {
1498         /* reset and unreset the emac core */
1499         struct bnx2x *bp = params->bp;
1500         u8 port = params->port;
1501         u32 emac_base = port ? GRCBASE_EMAC1 : GRCBASE_EMAC0;
1502         u32 val;
1503         u16 timeout;
1504
1505         REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_2_CLEAR,
1506                (MISC_REGISTERS_RESET_REG_2_RST_EMAC0_HARD_CORE << port));
1507         udelay(5);
1508         REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_2_SET,
1509                (MISC_REGISTERS_RESET_REG_2_RST_EMAC0_HARD_CORE << port));
1510
1511         /* init emac - use read-modify-write */
1512         /* self clear reset */
1513         val = REG_RD(bp, emac_base + EMAC_REG_EMAC_MODE);
1514         EMAC_WR(bp, EMAC_REG_EMAC_MODE, (val | EMAC_MODE_RESET));
1515
1516         timeout = 200;
1517         do {
1518                 val = REG_RD(bp, emac_base + EMAC_REG_EMAC_MODE);
1519                 DP(NETIF_MSG_LINK, "EMAC reset reg is %u\n", val);
1520                 if (!timeout) {
1521                         DP(NETIF_MSG_LINK, "EMAC timeout!\n");
1522                         return;
1523                 }
1524                 timeout--;
1525         } while (val & EMAC_MODE_RESET);
1526         bnx2x_set_mdio_clk(bp, params->chip_id, port);
1527         /* Set mac address */
1528         val = ((params->mac_addr[0] << 8) |
1529                 params->mac_addr[1]);
1530         EMAC_WR(bp, EMAC_REG_EMAC_MAC_MATCH, val);
1531
1532         val = ((params->mac_addr[2] << 24) |
1533                (params->mac_addr[3] << 16) |
1534                (params->mac_addr[4] << 8) |
1535                 params->mac_addr[5]);
1536         EMAC_WR(bp, EMAC_REG_EMAC_MAC_MATCH + 4, val);
1537 }
1538
1539 static void bnx2x_set_xumac_nig(struct link_params *params,
1540                                 u16 tx_pause_en,
1541                                 u8 enable)
1542 {
1543         struct bnx2x *bp = params->bp;
1544
1545         REG_WR(bp, params->port ? NIG_REG_P1_MAC_IN_EN : NIG_REG_P0_MAC_IN_EN,
1546                enable);
1547         REG_WR(bp, params->port ? NIG_REG_P1_MAC_OUT_EN : NIG_REG_P0_MAC_OUT_EN,
1548                enable);
1549         REG_WR(bp, params->port ? NIG_REG_P1_MAC_PAUSE_OUT_EN :
1550                NIG_REG_P0_MAC_PAUSE_OUT_EN, tx_pause_en);
1551 }
1552
1553 static void bnx2x_umac_disable(struct link_params *params)
1554 {
1555         u32 umac_base = params->port ? GRCBASE_UMAC1 : GRCBASE_UMAC0;
1556         struct bnx2x *bp = params->bp;
1557         if (!(REG_RD(bp, MISC_REG_RESET_REG_2) &
1558                    (MISC_REGISTERS_RESET_REG_2_UMAC0 << params->port)))
1559                 return;
1560
1561         /* Disable RX and TX */
1562         REG_WR(bp, umac_base + UMAC_REG_COMMAND_CONFIG, 0);
1563 }
1564
1565 static void bnx2x_umac_enable(struct link_params *params,
1566                             struct link_vars *vars, u8 lb)
1567 {
1568         u32 val;
1569         u32 umac_base = params->port ? GRCBASE_UMAC1 : GRCBASE_UMAC0;
1570         struct bnx2x *bp = params->bp;
1571         /* Reset UMAC */
1572         REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_2_CLEAR,
1573                (MISC_REGISTERS_RESET_REG_2_UMAC0 << params->port));
1574         usleep_range(1000, 1000);
1575
1576         REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_2_SET,
1577                (MISC_REGISTERS_RESET_REG_2_UMAC0 << params->port));
1578
1579         DP(NETIF_MSG_LINK, "enabling UMAC\n");
1580
1581         /**
1582          * This register determines on which events the MAC will assert
1583          * error on the i/f to the NIG along w/ EOP.
1584          */
1585
1586         /**
1587          * BD REG_WR(bp, NIG_REG_P0_MAC_RSV_ERR_MASK +
1588          * params->port*0x14,      0xfffff.
1589          */
1590         /* This register opens the gate for the UMAC despite its name */
1591         REG_WR(bp, NIG_REG_EGRESS_EMAC0_PORT + params->port*4, 1);
1592
1593         val = UMAC_COMMAND_CONFIG_REG_PROMIS_EN |
1594                 UMAC_COMMAND_CONFIG_REG_PAD_EN |
1595                 UMAC_COMMAND_CONFIG_REG_SW_RESET |
1596                 UMAC_COMMAND_CONFIG_REG_NO_LGTH_CHECK;
1597         switch (vars->line_speed) {
1598         case SPEED_10:
1599                 val |= (0<<2);
1600                 break;
1601         case SPEED_100:
1602                 val |= (1<<2);
1603                 break;
1604         case SPEED_1000:
1605                 val |= (2<<2);
1606                 break;
1607         case SPEED_2500:
1608                 val |= (3<<2);
1609                 break;
1610         default:
1611                 DP(NETIF_MSG_LINK, "Invalid speed for UMAC %d\n",
1612                                vars->line_speed);
1613                 break;
1614         }
1615         if (!(vars->flow_ctrl & BNX2X_FLOW_CTRL_TX))
1616                 val |= UMAC_COMMAND_CONFIG_REG_IGNORE_TX_PAUSE;
1617
1618         if (!(vars->flow_ctrl & BNX2X_FLOW_CTRL_RX))
1619                 val |= UMAC_COMMAND_CONFIG_REG_PAUSE_IGNORE;
1620
1621         if (vars->duplex == DUPLEX_HALF)
1622                 val |= UMAC_COMMAND_CONFIG_REG_HD_ENA;
1623
1624         REG_WR(bp, umac_base + UMAC_REG_COMMAND_CONFIG, val);
1625         udelay(50);
1626
1627         /* Set MAC address for source TX Pause/PFC frames (under SW reset) */
1628         REG_WR(bp, umac_base + UMAC_REG_MAC_ADDR0,
1629                ((params->mac_addr[2] << 24) |
1630                 (params->mac_addr[3] << 16) |
1631                 (params->mac_addr[4] << 8) |
1632                 (params->mac_addr[5])));
1633         REG_WR(bp, umac_base + UMAC_REG_MAC_ADDR1,
1634                ((params->mac_addr[0] << 8) |
1635                 (params->mac_addr[1])));
1636
1637         /* Enable RX and TX */
1638         val &= ~UMAC_COMMAND_CONFIG_REG_PAD_EN;
1639         val |= UMAC_COMMAND_CONFIG_REG_TX_ENA |
1640                 UMAC_COMMAND_CONFIG_REG_RX_ENA;
1641         REG_WR(bp, umac_base + UMAC_REG_COMMAND_CONFIG, val);
1642         udelay(50);
1643
1644         /* Remove SW Reset */
1645         val &= ~UMAC_COMMAND_CONFIG_REG_SW_RESET;
1646
1647         /* Check loopback mode */
1648         if (lb)
1649                 val |= UMAC_COMMAND_CONFIG_REG_LOOP_ENA;
1650         REG_WR(bp, umac_base + UMAC_REG_COMMAND_CONFIG, val);
1651
1652         /*
1653          * Maximum Frame Length (RW). Defines a 14-Bit maximum frame
1654          * length used by the MAC receive logic to check frames.
1655          */
1656         REG_WR(bp, umac_base + UMAC_REG_MAXFR, 0x2710);
1657         bnx2x_set_xumac_nig(params,
1658                             ((vars->flow_ctrl & BNX2X_FLOW_CTRL_TX) != 0), 1);
1659         vars->mac_type = MAC_TYPE_UMAC;
1660
1661 }
1662
1663 /* Define the XMAC mode */
1664 static void bnx2x_xmac_init(struct link_params *params, u32 max_speed)
1665 {
1666         struct bnx2x *bp = params->bp;
1667         u32 is_port4mode = bnx2x_is_4_port_mode(bp);
1668
1669         /*
1670          * In 4-port mode, need to set the mode only once, so if XMAC is
1671          * already out of reset, it means the mode has already been set,
1672          * and it must not* reset the XMAC again, since it controls both
1673          * ports of the path
1674          */
1675
1676         if ((CHIP_NUM(bp) == CHIP_NUM_57840) &&
1677             (REG_RD(bp, MISC_REG_RESET_REG_2) &
1678              MISC_REGISTERS_RESET_REG_2_XMAC)) {
1679                 DP(NETIF_MSG_LINK,
1680                    "XMAC already out of reset in 4-port mode\n");
1681                 return;
1682         }
1683
1684         /* Hard reset */
1685         REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_2_CLEAR,
1686                MISC_REGISTERS_RESET_REG_2_XMAC);
1687         usleep_range(1000, 1000);
1688
1689         REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_2_SET,
1690                MISC_REGISTERS_RESET_REG_2_XMAC);
1691         if (is_port4mode) {
1692                 DP(NETIF_MSG_LINK, "Init XMAC to 2 ports x 10G per path\n");
1693
1694                 /*  Set the number of ports on the system side to up to 2 */
1695                 REG_WR(bp, MISC_REG_XMAC_CORE_PORT_MODE, 1);
1696
1697                 /* Set the number of ports on the Warp Core to 10G */
1698                 REG_WR(bp, MISC_REG_XMAC_PHY_PORT_MODE, 3);
1699         } else {
1700                 /*  Set the number of ports on the system side to 1 */
1701                 REG_WR(bp, MISC_REG_XMAC_CORE_PORT_MODE, 0);
1702                 if (max_speed == SPEED_10000) {
1703                         DP(NETIF_MSG_LINK,
1704                            "Init XMAC to 10G x 1 port per path\n");
1705                         /* Set the number of ports on the Warp Core to 10G */
1706                         REG_WR(bp, MISC_REG_XMAC_PHY_PORT_MODE, 3);
1707                 } else {
1708                         DP(NETIF_MSG_LINK,
1709                            "Init XMAC to 20G x 2 ports per path\n");
1710                         /* Set the number of ports on the Warp Core to 20G */
1711                         REG_WR(bp, MISC_REG_XMAC_PHY_PORT_MODE, 1);
1712                 }
1713         }
1714         /* Soft reset */
1715         REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_2_CLEAR,
1716                MISC_REGISTERS_RESET_REG_2_XMAC_SOFT);
1717         usleep_range(1000, 1000);
1718
1719         REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_2_SET,
1720                MISC_REGISTERS_RESET_REG_2_XMAC_SOFT);
1721
1722 }
1723
1724 static void bnx2x_xmac_disable(struct link_params *params)
1725 {
1726         u8 port = params->port;
1727         struct bnx2x *bp = params->bp;
1728         u32 pfc_ctrl, xmac_base = (port) ? GRCBASE_XMAC1 : GRCBASE_XMAC0;
1729
1730         if (REG_RD(bp, MISC_REG_RESET_REG_2) &
1731             MISC_REGISTERS_RESET_REG_2_XMAC) {
1732                 /*
1733                  * Send an indication to change the state in the NIG back to XON
1734                  * Clearing this bit enables the next set of this bit to get
1735                  * rising edge
1736                  */
1737                 pfc_ctrl = REG_RD(bp, xmac_base + XMAC_REG_PFC_CTRL_HI);
1738                 REG_WR(bp, xmac_base + XMAC_REG_PFC_CTRL_HI,
1739                        (pfc_ctrl & ~(1<<1)));
1740                 REG_WR(bp, xmac_base + XMAC_REG_PFC_CTRL_HI,
1741                        (pfc_ctrl | (1<<1)));
1742                 DP(NETIF_MSG_LINK, "Disable XMAC on port %x\n", port);
1743                 REG_WR(bp, xmac_base + XMAC_REG_CTRL, 0);
1744         }
1745 }
1746
1747 static int bnx2x_xmac_enable(struct link_params *params,
1748                              struct link_vars *vars, u8 lb)
1749 {
1750         u32 val, xmac_base;
1751         struct bnx2x *bp = params->bp;
1752         DP(NETIF_MSG_LINK, "enabling XMAC\n");
1753
1754         xmac_base = (params->port) ? GRCBASE_XMAC1 : GRCBASE_XMAC0;
1755
1756         bnx2x_xmac_init(params, vars->line_speed);
1757
1758         /*
1759          * This register determines on which events the MAC will assert
1760          * error on the i/f to the NIG along w/ EOP.
1761          */
1762
1763         /*
1764          * This register tells the NIG whether to send traffic to UMAC
1765          * or XMAC
1766          */
1767         REG_WR(bp, NIG_REG_EGRESS_EMAC0_PORT + params->port*4, 0);
1768
1769         /* Set Max packet size */
1770         REG_WR(bp, xmac_base + XMAC_REG_RX_MAX_SIZE, 0x2710);
1771
1772         /* CRC append for Tx packets */
1773         REG_WR(bp, xmac_base + XMAC_REG_TX_CTRL, 0xC800);
1774
1775         /* update PFC */
1776         bnx2x_update_pfc_xmac(params, vars, 0);
1777
1778         /* Enable TX and RX */
1779         val = XMAC_CTRL_REG_TX_EN | XMAC_CTRL_REG_RX_EN;
1780
1781         /* Check loopback mode */
1782         if (lb)
1783                 val |= XMAC_CTRL_REG_LINE_LOCAL_LPBK;
1784         REG_WR(bp, xmac_base + XMAC_REG_CTRL, val);
1785         bnx2x_set_xumac_nig(params,
1786                             ((vars->flow_ctrl & BNX2X_FLOW_CTRL_TX) != 0), 1);
1787
1788         vars->mac_type = MAC_TYPE_XMAC;
1789
1790         return 0;
1791 }
1792
1793 static int bnx2x_emac_enable(struct link_params *params,
1794                              struct link_vars *vars, u8 lb)
1795 {
1796         struct bnx2x *bp = params->bp;
1797         u8 port = params->port;
1798         u32 emac_base = port ? GRCBASE_EMAC1 : GRCBASE_EMAC0;
1799         u32 val;
1800
1801         DP(NETIF_MSG_LINK, "enabling EMAC\n");
1802
1803         /* Disable BMAC */
1804         REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_2_CLEAR,
1805                (MISC_REGISTERS_RESET_REG_2_RST_BMAC0 << port));
1806
1807         /* enable emac and not bmac */
1808         REG_WR(bp, NIG_REG_EGRESS_EMAC0_PORT + port*4, 1);
1809
1810         /* ASIC */
1811         if (vars->phy_flags & PHY_XGXS_FLAG) {
1812                 u32 ser_lane = ((params->lane_config &
1813                                  PORT_HW_CFG_LANE_SWAP_CFG_MASTER_MASK) >>
1814                                 PORT_HW_CFG_LANE_SWAP_CFG_MASTER_SHIFT);
1815
1816                 DP(NETIF_MSG_LINK, "XGXS\n");
1817                 /* select the master lanes (out of 0-3) */
1818                 REG_WR(bp, NIG_REG_XGXS_LANE_SEL_P0 + port*4, ser_lane);
1819                 /* select XGXS */
1820                 REG_WR(bp, NIG_REG_XGXS_SERDES0_MODE_SEL + port*4, 1);
1821
1822         } else { /* SerDes */
1823                 DP(NETIF_MSG_LINK, "SerDes\n");
1824                 /* select SerDes */
1825                 REG_WR(bp, NIG_REG_XGXS_SERDES0_MODE_SEL + port*4, 0);
1826         }
1827
1828         bnx2x_bits_en(bp, emac_base + EMAC_REG_EMAC_RX_MODE,
1829                       EMAC_RX_MODE_RESET);
1830         bnx2x_bits_en(bp, emac_base + EMAC_REG_EMAC_TX_MODE,
1831                       EMAC_TX_MODE_RESET);
1832
1833         if (CHIP_REV_IS_SLOW(bp)) {
1834                 /* config GMII mode */
1835                 val = REG_RD(bp, emac_base + EMAC_REG_EMAC_MODE);
1836                 EMAC_WR(bp, EMAC_REG_EMAC_MODE, (val | EMAC_MODE_PORT_GMII));
1837         } else { /* ASIC */
1838                 /* pause enable/disable */
1839                 bnx2x_bits_dis(bp, emac_base + EMAC_REG_EMAC_RX_MODE,
1840                                EMAC_RX_MODE_FLOW_EN);
1841
1842                 bnx2x_bits_dis(bp,  emac_base + EMAC_REG_EMAC_TX_MODE,
1843                                (EMAC_TX_MODE_EXT_PAUSE_EN |
1844                                 EMAC_TX_MODE_FLOW_EN));
1845                 if (!(params->feature_config_flags &
1846                       FEATURE_CONFIG_PFC_ENABLED)) {
1847                         if (vars->flow_ctrl & BNX2X_FLOW_CTRL_RX)
1848                                 bnx2x_bits_en(bp, emac_base +
1849                                               EMAC_REG_EMAC_RX_MODE,
1850                                               EMAC_RX_MODE_FLOW_EN);
1851
1852                         if (vars->flow_ctrl & BNX2X_FLOW_CTRL_TX)
1853                                 bnx2x_bits_en(bp, emac_base +
1854                                               EMAC_REG_EMAC_TX_MODE,
1855                                               (EMAC_TX_MODE_EXT_PAUSE_EN |
1856                                                EMAC_TX_MODE_FLOW_EN));
1857                 } else
1858                         bnx2x_bits_en(bp, emac_base + EMAC_REG_EMAC_TX_MODE,
1859                                       EMAC_TX_MODE_FLOW_EN);
1860         }
1861
1862         /* KEEP_VLAN_TAG, promiscuous */
1863         val = REG_RD(bp, emac_base + EMAC_REG_EMAC_RX_MODE);
1864         val |= EMAC_RX_MODE_KEEP_VLAN_TAG | EMAC_RX_MODE_PROMISCUOUS;
1865
1866         /*
1867          * Setting this bit causes MAC control frames (except for pause
1868          * frames) to be passed on for processing. This setting has no
1869          * affect on the operation of the pause frames. This bit effects
1870          * all packets regardless of RX Parser packet sorting logic.
1871          * Turn the PFC off to make sure we are in Xon state before
1872          * enabling it.
1873          */
1874         EMAC_WR(bp, EMAC_REG_RX_PFC_MODE, 0);
1875         if (params->feature_config_flags & FEATURE_CONFIG_PFC_ENABLED) {
1876                 DP(NETIF_MSG_LINK, "PFC is enabled\n");
1877                 /* Enable PFC again */
1878                 EMAC_WR(bp, EMAC_REG_RX_PFC_MODE,
1879                         EMAC_REG_RX_PFC_MODE_RX_EN |
1880                         EMAC_REG_RX_PFC_MODE_TX_EN |
1881                         EMAC_REG_RX_PFC_MODE_PRIORITIES);
1882
1883                 EMAC_WR(bp, EMAC_REG_RX_PFC_PARAM,
1884                         ((0x0101 <<
1885                           EMAC_REG_RX_PFC_PARAM_OPCODE_BITSHIFT) |
1886                          (0x00ff <<
1887                           EMAC_REG_RX_PFC_PARAM_PRIORITY_EN_BITSHIFT)));
1888                 val |= EMAC_RX_MODE_KEEP_MAC_CONTROL;
1889         }
1890         EMAC_WR(bp, EMAC_REG_EMAC_RX_MODE, val);
1891
1892         /* Set Loopback */
1893         val = REG_RD(bp, emac_base + EMAC_REG_EMAC_MODE);
1894         if (lb)
1895                 val |= 0x810;
1896         else
1897                 val &= ~0x810;
1898         EMAC_WR(bp, EMAC_REG_EMAC_MODE, val);
1899
1900         /* enable emac */
1901         REG_WR(bp, NIG_REG_NIG_EMAC0_EN + port*4, 1);
1902
1903         /* enable emac for jumbo packets */
1904         EMAC_WR(bp, EMAC_REG_EMAC_RX_MTU_SIZE,
1905                 (EMAC_RX_MTU_SIZE_JUMBO_ENA |
1906                  (ETH_MAX_JUMBO_PACKET_SIZE + ETH_OVREHEAD)));
1907
1908         /* strip CRC */
1909         REG_WR(bp, NIG_REG_NIG_INGRESS_EMAC0_NO_CRC + port*4, 0x1);
1910
1911         /* disable the NIG in/out to the bmac */
1912         REG_WR(bp, NIG_REG_BMAC0_IN_EN + port*4, 0x0);
1913         REG_WR(bp, NIG_REG_BMAC0_PAUSE_OUT_EN + port*4, 0x0);
1914         REG_WR(bp, NIG_REG_BMAC0_OUT_EN + port*4, 0x0);
1915
1916         /* enable the NIG in/out to the emac */
1917         REG_WR(bp, NIG_REG_EMAC0_IN_EN + port*4, 0x1);
1918         val = 0;
1919         if ((params->feature_config_flags &
1920               FEATURE_CONFIG_PFC_ENABLED) ||
1921             (vars->flow_ctrl & BNX2X_FLOW_CTRL_TX))
1922                 val = 1;
1923
1924         REG_WR(bp, NIG_REG_EMAC0_PAUSE_OUT_EN + port*4, val);
1925         REG_WR(bp, NIG_REG_EGRESS_EMAC0_OUT_EN + port*4, 0x1);
1926
1927         REG_WR(bp, NIG_REG_BMAC0_REGS_OUT_EN + port*4, 0x0);
1928
1929         vars->mac_type = MAC_TYPE_EMAC;
1930         return 0;
1931 }
1932
1933 static void bnx2x_update_pfc_bmac1(struct link_params *params,
1934                                    struct link_vars *vars)
1935 {
1936         u32 wb_data[2];
1937         struct bnx2x *bp = params->bp;
1938         u32 bmac_addr =  params->port ? NIG_REG_INGRESS_BMAC1_MEM :
1939                 NIG_REG_INGRESS_BMAC0_MEM;
1940
1941         u32 val = 0x14;
1942         if ((!(params->feature_config_flags &
1943               FEATURE_CONFIG_PFC_ENABLED)) &&
1944                 (vars->flow_ctrl & BNX2X_FLOW_CTRL_RX))
1945                 /* Enable BigMAC to react on received Pause packets */
1946                 val |= (1<<5);
1947         wb_data[0] = val;
1948         wb_data[1] = 0;
1949         REG_WR_DMAE(bp, bmac_addr + BIGMAC_REGISTER_RX_CONTROL, wb_data, 2);
1950
1951         /* tx control */
1952         val = 0xc0;
1953         if (!(params->feature_config_flags &
1954               FEATURE_CONFIG_PFC_ENABLED) &&
1955                 (vars->flow_ctrl & BNX2X_FLOW_CTRL_TX))
1956                 val |= 0x800000;
1957         wb_data[0] = val;
1958         wb_data[1] = 0;
1959         REG_WR_DMAE(bp, bmac_addr + BIGMAC_REGISTER_TX_CONTROL, wb_data, 2);
1960 }
1961
1962 static void bnx2x_update_pfc_bmac2(struct link_params *params,
1963                                    struct link_vars *vars,
1964                                    u8 is_lb)
1965 {
1966         /*
1967          * Set rx control: Strip CRC and enable BigMAC to relay
1968          * control packets to the system as well
1969          */
1970         u32 wb_data[2];
1971         struct bnx2x *bp = params->bp;
1972         u32 bmac_addr = params->port ? NIG_REG_INGRESS_BMAC1_MEM :
1973                 NIG_REG_INGRESS_BMAC0_MEM;
1974         u32 val = 0x14;
1975
1976         if ((!(params->feature_config_flags &
1977               FEATURE_CONFIG_PFC_ENABLED)) &&
1978                 (vars->flow_ctrl & BNX2X_FLOW_CTRL_RX))
1979                 /* Enable BigMAC to react on received Pause packets */
1980                 val |= (1<<5);
1981         wb_data[0] = val;
1982         wb_data[1] = 0;
1983         REG_WR_DMAE(bp, bmac_addr + BIGMAC2_REGISTER_RX_CONTROL, wb_data, 2);
1984         udelay(30);
1985
1986         /* Tx control */
1987         val = 0xc0;
1988         if (!(params->feature_config_flags &
1989                                 FEATURE_CONFIG_PFC_ENABLED) &&
1990             (vars->flow_ctrl & BNX2X_FLOW_CTRL_TX))
1991                 val |= 0x800000;
1992         wb_data[0] = val;
1993         wb_data[1] = 0;
1994         REG_WR_DMAE(bp, bmac_addr + BIGMAC2_REGISTER_TX_CONTROL, wb_data, 2);
1995
1996         if (params->feature_config_flags & FEATURE_CONFIG_PFC_ENABLED) {
1997                 DP(NETIF_MSG_LINK, "PFC is enabled\n");
1998                 /* Enable PFC RX & TX & STATS and set 8 COS  */
1999                 wb_data[0] = 0x0;
2000                 wb_data[0] |= (1<<0);  /* RX */
2001                 wb_data[0] |= (1<<1);  /* TX */
2002                 wb_data[0] |= (1<<2);  /* Force initial Xon */
2003                 wb_data[0] |= (1<<3);  /* 8 cos */
2004                 wb_data[0] |= (1<<5);  /* STATS */
2005                 wb_data[1] = 0;
2006                 REG_WR_DMAE(bp, bmac_addr + BIGMAC2_REGISTER_PFC_CONTROL,
2007                             wb_data, 2);
2008                 /* Clear the force Xon */
2009                 wb_data[0] &= ~(1<<2);
2010         } else {
2011                 DP(NETIF_MSG_LINK, "PFC is disabled\n");
2012                 /* disable PFC RX & TX & STATS and set 8 COS */
2013                 wb_data[0] = 0x8;
2014                 wb_data[1] = 0;
2015         }
2016
2017         REG_WR_DMAE(bp, bmac_addr + BIGMAC2_REGISTER_PFC_CONTROL, wb_data, 2);
2018
2019         /*
2020          * Set Time (based unit is 512 bit time) between automatic
2021          * re-sending of PP packets amd enable automatic re-send of
2022          * Per-Priroity Packet as long as pp_gen is asserted and
2023          * pp_disable is low.
2024          */
2025         val = 0x8000;
2026         if (params->feature_config_flags & FEATURE_CONFIG_PFC_ENABLED)
2027                 val |= (1<<16); /* enable automatic re-send */
2028
2029         wb_data[0] = val;
2030         wb_data[1] = 0;
2031         REG_WR_DMAE(bp, bmac_addr + BIGMAC2_REGISTER_TX_PAUSE_CONTROL,
2032                     wb_data, 2);
2033
2034         /* mac control */
2035         val = 0x3; /* Enable RX and TX */
2036         if (is_lb) {
2037                 val |= 0x4; /* Local loopback */
2038                 DP(NETIF_MSG_LINK, "enable bmac loopback\n");
2039         }
2040         /* When PFC enabled, Pass pause frames towards the NIG. */
2041         if (params->feature_config_flags & FEATURE_CONFIG_PFC_ENABLED)
2042                 val |= ((1<<6)|(1<<5));
2043
2044         wb_data[0] = val;
2045         wb_data[1] = 0;
2046         REG_WR_DMAE(bp, bmac_addr + BIGMAC2_REGISTER_BMAC_CONTROL, wb_data, 2);
2047 }
2048
2049 /* PFC BRB internal port configuration params */
2050 struct bnx2x_pfc_brb_threshold_val {
2051         u32 pause_xoff;
2052         u32 pause_xon;
2053         u32 full_xoff;
2054         u32 full_xon;
2055 };
2056
2057 struct bnx2x_pfc_brb_e3b0_val {
2058         u32 per_class_guaranty_mode;
2059         u32 lb_guarantied_hyst;
2060         u32 full_lb_xoff_th;
2061         u32 full_lb_xon_threshold;
2062         u32 lb_guarantied;
2063         u32 mac_0_class_t_guarantied;
2064         u32 mac_0_class_t_guarantied_hyst;
2065         u32 mac_1_class_t_guarantied;
2066         u32 mac_1_class_t_guarantied_hyst;
2067 };
2068
2069 struct bnx2x_pfc_brb_th_val {
2070         struct bnx2x_pfc_brb_threshold_val pauseable_th;
2071         struct bnx2x_pfc_brb_threshold_val non_pauseable_th;
2072         struct bnx2x_pfc_brb_threshold_val default_class0;
2073         struct bnx2x_pfc_brb_threshold_val default_class1;
2074
2075 };
2076 static int bnx2x_pfc_brb_get_config_params(
2077                                 struct link_params *params,
2078                                 struct bnx2x_pfc_brb_th_val *config_val)
2079 {
2080         struct bnx2x *bp = params->bp;
2081         DP(NETIF_MSG_LINK, "Setting PFC BRB configuration\n");
2082
2083         config_val->default_class1.pause_xoff = 0;
2084         config_val->default_class1.pause_xon = 0;
2085         config_val->default_class1.full_xoff = 0;
2086         config_val->default_class1.full_xon = 0;
2087
2088         if (CHIP_IS_E2(bp)) {
2089                 /*  class0 defaults */
2090                 config_val->default_class0.pause_xoff =
2091                         DEFAULT0_E2_BRB_MAC_PAUSE_XOFF_THR;
2092                 config_val->default_class0.pause_xon =
2093                         DEFAULT0_E2_BRB_MAC_PAUSE_XON_THR;
2094                 config_val->default_class0.full_xoff =
2095                         DEFAULT0_E2_BRB_MAC_FULL_XOFF_THR;
2096                 config_val->default_class0.full_xon =
2097                         DEFAULT0_E2_BRB_MAC_FULL_XON_THR;
2098                 /*  pause able*/
2099                 config_val->pauseable_th.pause_xoff =
2100                         PFC_E2_BRB_MAC_PAUSE_XOFF_THR_PAUSE;
2101                 config_val->pauseable_th.pause_xon =
2102                         PFC_E2_BRB_MAC_PAUSE_XON_THR_PAUSE;
2103                 config_val->pauseable_th.full_xoff =
2104                         PFC_E2_BRB_MAC_FULL_XOFF_THR_PAUSE;
2105                 config_val->pauseable_th.full_xon =
2106                         PFC_E2_BRB_MAC_FULL_XON_THR_PAUSE;
2107                 /* non pause able*/
2108                 config_val->non_pauseable_th.pause_xoff =
2109                         PFC_E2_BRB_MAC_PAUSE_XOFF_THR_NON_PAUSE;
2110                 config_val->non_pauseable_th.pause_xon =
2111                         PFC_E2_BRB_MAC_PAUSE_XON_THR_NON_PAUSE;
2112                 config_val->non_pauseable_th.full_xoff =
2113                         PFC_E2_BRB_MAC_FULL_XOFF_THR_NON_PAUSE;
2114                 config_val->non_pauseable_th.full_xon =
2115                         PFC_E2_BRB_MAC_FULL_XON_THR_NON_PAUSE;
2116         } else if (CHIP_IS_E3A0(bp)) {
2117                 /*  class0 defaults */
2118                 config_val->default_class0.pause_xoff =
2119                         DEFAULT0_E3A0_BRB_MAC_PAUSE_XOFF_THR;
2120                 config_val->default_class0.pause_xon =
2121                         DEFAULT0_E3A0_BRB_MAC_PAUSE_XON_THR;
2122                 config_val->default_class0.full_xoff =
2123                         DEFAULT0_E3A0_BRB_MAC_FULL_XOFF_THR;
2124                 config_val->default_class0.full_xon =
2125                         DEFAULT0_E3A0_BRB_MAC_FULL_XON_THR;
2126                 /*  pause able */
2127                 config_val->pauseable_th.pause_xoff =
2128                         PFC_E3A0_BRB_MAC_PAUSE_XOFF_THR_PAUSE;
2129                 config_val->pauseable_th.pause_xon =
2130                         PFC_E3A0_BRB_MAC_PAUSE_XON_THR_PAUSE;
2131                 config_val->pauseable_th.full_xoff =
2132                         PFC_E3A0_BRB_MAC_FULL_XOFF_THR_PAUSE;
2133                 config_val->pauseable_th.full_xon =
2134                         PFC_E3A0_BRB_MAC_FULL_XON_THR_PAUSE;
2135                 /* non pause able*/
2136                 config_val->non_pauseable_th.pause_xoff =
2137                         PFC_E3A0_BRB_MAC_PAUSE_XOFF_THR_NON_PAUSE;
2138                 config_val->non_pauseable_th.pause_xon =
2139                         PFC_E3A0_BRB_MAC_PAUSE_XON_THR_NON_PAUSE;
2140                 config_val->non_pauseable_th.full_xoff =
2141                         PFC_E3A0_BRB_MAC_FULL_XOFF_THR_NON_PAUSE;
2142                 config_val->non_pauseable_th.full_xon =
2143                         PFC_E3A0_BRB_MAC_FULL_XON_THR_NON_PAUSE;
2144         } else if (CHIP_IS_E3B0(bp)) {
2145                 /*  class0 defaults */
2146                 config_val->default_class0.pause_xoff =
2147                         DEFAULT0_E3B0_BRB_MAC_PAUSE_XOFF_THR;
2148                 config_val->default_class0.pause_xon =
2149                     DEFAULT0_E3B0_BRB_MAC_PAUSE_XON_THR;
2150                 config_val->default_class0.full_xoff =
2151                     DEFAULT0_E3B0_BRB_MAC_FULL_XOFF_THR;
2152                 config_val->default_class0.full_xon =
2153                     DEFAULT0_E3B0_BRB_MAC_FULL_XON_THR;
2154
2155                 if (params->phy[INT_PHY].flags &
2156                     FLAGS_4_PORT_MODE) {
2157                         config_val->pauseable_th.pause_xoff =
2158                                 PFC_E3B0_4P_BRB_MAC_PAUSE_XOFF_THR_PAUSE;
2159                         config_val->pauseable_th.pause_xon =
2160                                 PFC_E3B0_4P_BRB_MAC_PAUSE_XON_THR_PAUSE;
2161                         config_val->pauseable_th.full_xoff =
2162                                 PFC_E3B0_4P_BRB_MAC_FULL_XOFF_THR_PAUSE;
2163                         config_val->pauseable_th.full_xon =
2164                                 PFC_E3B0_4P_BRB_MAC_FULL_XON_THR_PAUSE;
2165                         /* non pause able*/
2166                         config_val->non_pauseable_th.pause_xoff =
2167                         PFC_E3B0_4P_BRB_MAC_PAUSE_XOFF_THR_NON_PAUSE;
2168                         config_val->non_pauseable_th.pause_xon =
2169                         PFC_E3B0_4P_BRB_MAC_PAUSE_XON_THR_NON_PAUSE;
2170                         config_val->non_pauseable_th.full_xoff =
2171                         PFC_E3B0_4P_BRB_MAC_FULL_XOFF_THR_NON_PAUSE;
2172                         config_val->non_pauseable_th.full_xon =
2173                         PFC_E3B0_4P_BRB_MAC_FULL_XON_THR_NON_PAUSE;
2174                 } else {
2175                         config_val->pauseable_th.pause_xoff =
2176                                 PFC_E3B0_2P_BRB_MAC_PAUSE_XOFF_THR_PAUSE;
2177                         config_val->pauseable_th.pause_xon =
2178                                 PFC_E3B0_2P_BRB_MAC_PAUSE_XON_THR_PAUSE;
2179                         config_val->pauseable_th.full_xoff =
2180                                 PFC_E3B0_2P_BRB_MAC_FULL_XOFF_THR_PAUSE;
2181                         config_val->pauseable_th.full_xon =
2182                                 PFC_E3B0_2P_BRB_MAC_FULL_XON_THR_PAUSE;
2183                         /* non pause able*/
2184                         config_val->non_pauseable_th.pause_xoff =
2185                                 PFC_E3B0_2P_BRB_MAC_PAUSE_XOFF_THR_NON_PAUSE;
2186                         config_val->non_pauseable_th.pause_xon =
2187                                 PFC_E3B0_2P_BRB_MAC_PAUSE_XON_THR_NON_PAUSE;
2188                         config_val->non_pauseable_th.full_xoff =
2189                                 PFC_E3B0_2P_BRB_MAC_FULL_XOFF_THR_NON_PAUSE;
2190                         config_val->non_pauseable_th.full_xon =
2191                                 PFC_E3B0_2P_BRB_MAC_FULL_XON_THR_NON_PAUSE;
2192                 }
2193         } else
2194             return -EINVAL;
2195
2196         return 0;
2197 }
2198
2199 static void bnx2x_pfc_brb_get_e3b0_config_params(
2200                 struct link_params *params,
2201                 struct bnx2x_pfc_brb_e3b0_val
2202                 *e3b0_val,
2203                 struct bnx2x_nig_brb_pfc_port_params *pfc_params,
2204                 const u8 pfc_enabled)
2205 {
2206         if (pfc_enabled && pfc_params) {
2207                 e3b0_val->per_class_guaranty_mode = 1;
2208                 e3b0_val->lb_guarantied_hyst = 80;
2209
2210                 if (params->phy[INT_PHY].flags &
2211                     FLAGS_4_PORT_MODE) {
2212                         e3b0_val->full_lb_xoff_th =
2213                                 PFC_E3B0_4P_BRB_FULL_LB_XOFF_THR;
2214                         e3b0_val->full_lb_xon_threshold =
2215                                 PFC_E3B0_4P_BRB_FULL_LB_XON_THR;
2216                         e3b0_val->lb_guarantied =
2217                                 PFC_E3B0_4P_LB_GUART;
2218                         e3b0_val->mac_0_class_t_guarantied =
2219                                 PFC_E3B0_4P_BRB_MAC_0_CLASS_T_GUART;
2220                         e3b0_val->mac_0_class_t_guarantied_hyst =
2221                                 PFC_E3B0_4P_BRB_MAC_0_CLASS_T_GUART_HYST;
2222                         e3b0_val->mac_1_class_t_guarantied =
2223                                 PFC_E3B0_4P_BRB_MAC_1_CLASS_T_GUART;
2224                         e3b0_val->mac_1_class_t_guarantied_hyst =
2225                                 PFC_E3B0_4P_BRB_MAC_1_CLASS_T_GUART_HYST;
2226                 } else {
2227                         e3b0_val->full_lb_xoff_th =
2228                                 PFC_E3B0_2P_BRB_FULL_LB_XOFF_THR;
2229                         e3b0_val->full_lb_xon_threshold =
2230                                 PFC_E3B0_2P_BRB_FULL_LB_XON_THR;
2231                         e3b0_val->mac_0_class_t_guarantied_hyst =
2232                                 PFC_E3B0_2P_BRB_MAC_0_CLASS_T_GUART_HYST;
2233                         e3b0_val->mac_1_class_t_guarantied =
2234                                 PFC_E3B0_2P_BRB_MAC_1_CLASS_T_GUART;
2235                         e3b0_val->mac_1_class_t_guarantied_hyst =
2236                                 PFC_E3B0_2P_BRB_MAC_1_CLASS_T_GUART_HYST;
2237
2238                         if (pfc_params->cos0_pauseable !=
2239                                 pfc_params->cos1_pauseable) {
2240                                 /* nonpauseable= Lossy + pauseable = Lossless*/
2241                                 e3b0_val->lb_guarantied =
2242                                         PFC_E3B0_2P_MIX_PAUSE_LB_GUART;
2243                                 e3b0_val->mac_0_class_t_guarantied =
2244                                PFC_E3B0_2P_MIX_PAUSE_MAC_0_CLASS_T_GUART;
2245                         } else if (pfc_params->cos0_pauseable) {
2246                                 /* Lossless +Lossless*/
2247                                 e3b0_val->lb_guarantied =
2248                                         PFC_E3B0_2P_PAUSE_LB_GUART;
2249                                 e3b0_val->mac_0_class_t_guarantied =
2250                                    PFC_E3B0_2P_PAUSE_MAC_0_CLASS_T_GUART;
2251                         } else {
2252                                 /* Lossy +Lossy*/
2253                                 e3b0_val->lb_guarantied =
2254                                         PFC_E3B0_2P_NON_PAUSE_LB_GUART;
2255                                 e3b0_val->mac_0_class_t_guarantied =
2256                                PFC_E3B0_2P_NON_PAUSE_MAC_0_CLASS_T_GUART;
2257                         }
2258                 }
2259         } else {
2260                 e3b0_val->per_class_guaranty_mode = 0;
2261                 e3b0_val->lb_guarantied_hyst = 0;
2262                 e3b0_val->full_lb_xoff_th =
2263                         DEFAULT_E3B0_BRB_FULL_LB_XOFF_THR;
2264                 e3b0_val->full_lb_xon_threshold =
2265                         DEFAULT_E3B0_BRB_FULL_LB_XON_THR;
2266                 e3b0_val->lb_guarantied =
2267                         DEFAULT_E3B0_LB_GUART;
2268                 e3b0_val->mac_0_class_t_guarantied =
2269                         DEFAULT_E3B0_BRB_MAC_0_CLASS_T_GUART;
2270                 e3b0_val->mac_0_class_t_guarantied_hyst =
2271                         DEFAULT_E3B0_BRB_MAC_0_CLASS_T_GUART_HYST;
2272                 e3b0_val->mac_1_class_t_guarantied =
2273                         DEFAULT_E3B0_BRB_MAC_1_CLASS_T_GUART;
2274                 e3b0_val->mac_1_class_t_guarantied_hyst =
2275                         DEFAULT_E3B0_BRB_MAC_1_CLASS_T_GUART_HYST;
2276         }
2277 }
2278 static int bnx2x_update_pfc_brb(struct link_params *params,
2279                                 struct link_vars *vars,
2280                                 struct bnx2x_nig_brb_pfc_port_params
2281                                 *pfc_params)
2282 {
2283         struct bnx2x *bp = params->bp;
2284         struct bnx2x_pfc_brb_th_val config_val = { {0} };
2285         struct bnx2x_pfc_brb_threshold_val *reg_th_config =
2286                 &config_val.pauseable_th;
2287         struct bnx2x_pfc_brb_e3b0_val e3b0_val = {0};
2288         const int set_pfc = params->feature_config_flags &
2289                 FEATURE_CONFIG_PFC_ENABLED;
2290         const u8 pfc_enabled = (set_pfc && pfc_params);
2291         int bnx2x_status = 0;
2292         u8 port = params->port;
2293
2294         /* default - pause configuration */
2295         reg_th_config = &config_val.pauseable_th;
2296         bnx2x_status = bnx2x_pfc_brb_get_config_params(params, &config_val);
2297         if (bnx2x_status)
2298                 return bnx2x_status;
2299
2300         if (pfc_enabled) {
2301                 /* First COS */
2302                 if (pfc_params->cos0_pauseable)
2303                         reg_th_config = &config_val.pauseable_th;
2304                 else
2305                         reg_th_config = &config_val.non_pauseable_th;
2306         } else
2307                 reg_th_config = &config_val.default_class0;
2308         /*
2309          * The number of free blocks below which the pause signal to class 0
2310          * of MAC #n is asserted. n=0,1
2311          */
2312         REG_WR(bp, (port) ? BRB1_REG_PAUSE_0_XOFF_THRESHOLD_1 :
2313                BRB1_REG_PAUSE_0_XOFF_THRESHOLD_0 ,
2314                reg_th_config->pause_xoff);
2315         /*
2316          * The number of free blocks above which the pause signal to class 0
2317          * of MAC #n is de-asserted. n=0,1
2318          */
2319         REG_WR(bp, (port) ? BRB1_REG_PAUSE_0_XON_THRESHOLD_1 :
2320                BRB1_REG_PAUSE_0_XON_THRESHOLD_0 , reg_th_config->pause_xon);
2321         /*
2322          * The number of free blocks below which the full signal to class 0
2323          * of MAC #n is asserted. n=0,1
2324          */
2325         REG_WR(bp, (port) ? BRB1_REG_FULL_0_XOFF_THRESHOLD_1 :
2326                BRB1_REG_FULL_0_XOFF_THRESHOLD_0 , reg_th_config->full_xoff);
2327         /*
2328          * The number of free blocks above which the full signal to class 0
2329          * of MAC #n is de-asserted. n=0,1
2330          */
2331         REG_WR(bp, (port) ? BRB1_REG_FULL_0_XON_THRESHOLD_1 :
2332                BRB1_REG_FULL_0_XON_THRESHOLD_0 , reg_th_config->full_xon);
2333
2334         if (pfc_enabled) {
2335                 /* Second COS */
2336                 if (pfc_params->cos1_pauseable)
2337                         reg_th_config = &config_val.pauseable_th;
2338                 else
2339                         reg_th_config = &config_val.non_pauseable_th;
2340         } else
2341                 reg_th_config = &config_val.default_class1;
2342         /*
2343          * The number of free blocks below which the pause signal to
2344          * class 1 of MAC #n is asserted. n=0,1
2345          */
2346         REG_WR(bp, (port) ? BRB1_REG_PAUSE_1_XOFF_THRESHOLD_1 :
2347                BRB1_REG_PAUSE_1_XOFF_THRESHOLD_0,
2348                reg_th_config->pause_xoff);
2349
2350         /*
2351          * The number of free blocks above which the pause signal to
2352          * class 1 of MAC #n is de-asserted. n=0,1
2353          */
2354         REG_WR(bp, (port) ? BRB1_REG_PAUSE_1_XON_THRESHOLD_1 :
2355                BRB1_REG_PAUSE_1_XON_THRESHOLD_0,
2356                reg_th_config->pause_xon);
2357         /*
2358          * The number of free blocks below which the full signal to
2359          * class 1 of MAC #n is asserted. n=0,1
2360          */
2361         REG_WR(bp, (port) ? BRB1_REG_FULL_1_XOFF_THRESHOLD_1 :
2362                BRB1_REG_FULL_1_XOFF_THRESHOLD_0,
2363                reg_th_config->full_xoff);
2364         /*
2365          * The number of free blocks above which the full signal to
2366          * class 1 of MAC #n is de-asserted. n=0,1
2367          */
2368         REG_WR(bp, (port) ? BRB1_REG_FULL_1_XON_THRESHOLD_1 :
2369                BRB1_REG_FULL_1_XON_THRESHOLD_0,
2370                reg_th_config->full_xon);
2371
2372         if (CHIP_IS_E3B0(bp)) {
2373                 bnx2x_pfc_brb_get_e3b0_config_params(
2374                         params,
2375                         &e3b0_val,
2376                         pfc_params,
2377                         pfc_enabled);
2378
2379                 REG_WR(bp, BRB1_REG_PER_CLASS_GUARANTY_MODE,
2380                            e3b0_val.per_class_guaranty_mode);
2381
2382                 /*
2383                  * The hysteresis on the guarantied buffer space for the Lb
2384                  * port before signaling XON.
2385                  */
2386                 REG_WR(bp, BRB1_REG_LB_GUARANTIED_HYST,
2387                            e3b0_val.lb_guarantied_hyst);
2388
2389                 /*
2390                  * The number of free blocks below which the full signal to the
2391                  * LB port is asserted.
2392                  */
2393                 REG_WR(bp, BRB1_REG_FULL_LB_XOFF_THRESHOLD,
2394                        e3b0_val.full_lb_xoff_th);
2395                 /*
2396                  * The number of free blocks above which the full signal to the
2397                  * LB port is de-asserted.
2398                  */
2399                 REG_WR(bp, BRB1_REG_FULL_LB_XON_THRESHOLD,
2400                        e3b0_val.full_lb_xon_threshold);
2401                 /*
2402                  * The number of blocks guarantied for the MAC #n port. n=0,1
2403                  */
2404
2405                 /* The number of blocks guarantied for the LB port.*/
2406                 REG_WR(bp, BRB1_REG_LB_GUARANTIED,
2407                        e3b0_val.lb_guarantied);
2408
2409                 /*
2410                  * The number of blocks guarantied for the MAC #n port.
2411                  */
2412                 REG_WR(bp, BRB1_REG_MAC_GUARANTIED_0,
2413                        2 * e3b0_val.mac_0_class_t_guarantied);
2414                 REG_WR(bp, BRB1_REG_MAC_GUARANTIED_1,
2415                        2 * e3b0_val.mac_1_class_t_guarantied);
2416                 /*
2417                  * The number of blocks guarantied for class #t in MAC0. t=0,1
2418                  */
2419                 REG_WR(bp, BRB1_REG_MAC_0_CLASS_0_GUARANTIED,
2420                        e3b0_val.mac_0_class_t_guarantied);
2421                 REG_WR(bp, BRB1_REG_MAC_0_CLASS_1_GUARANTIED,
2422                        e3b0_val.mac_0_class_t_guarantied);
2423                 /*
2424                  * The hysteresis on the guarantied buffer space for class in
2425                  * MAC0.  t=0,1
2426                  */
2427                 REG_WR(bp, BRB1_REG_MAC_0_CLASS_0_GUARANTIED_HYST,
2428                        e3b0_val.mac_0_class_t_guarantied_hyst);
2429                 REG_WR(bp, BRB1_REG_MAC_0_CLASS_1_GUARANTIED_HYST,
2430                        e3b0_val.mac_0_class_t_guarantied_hyst);
2431
2432                 /*
2433                  * The number of blocks guarantied for class #t in MAC1.t=0,1
2434                  */
2435                 REG_WR(bp, BRB1_REG_MAC_1_CLASS_0_GUARANTIED,
2436                        e3b0_val.mac_1_class_t_guarantied);
2437                 REG_WR(bp, BRB1_REG_MAC_1_CLASS_1_GUARANTIED,
2438                        e3b0_val.mac_1_class_t_guarantied);
2439                 /*
2440                  * The hysteresis on the guarantied buffer space for class #t
2441                  * in MAC1.  t=0,1
2442                  */
2443                 REG_WR(bp, BRB1_REG_MAC_1_CLASS_0_GUARANTIED_HYST,
2444                        e3b0_val.mac_1_class_t_guarantied_hyst);
2445                 REG_WR(bp, BRB1_REG_MAC_1_CLASS_1_GUARANTIED_HYST,
2446                        e3b0_val.mac_1_class_t_guarantied_hyst);
2447         }
2448
2449         return bnx2x_status;
2450 }
2451
2452 /******************************************************************************
2453 * Description:
2454 *  This function is needed because NIG ARB_CREDIT_WEIGHT_X are
2455 *  not continues and ARB_CREDIT_WEIGHT_0 + offset is suitable.
2456 ******************************************************************************/
2457 int bnx2x_pfc_nig_rx_priority_mask(struct bnx2x *bp,
2458                                               u8 cos_entry,
2459                                               u32 priority_mask, u8 port)
2460 {
2461         u32 nig_reg_rx_priority_mask_add = 0;
2462
2463         switch (cos_entry) {
2464         case 0:
2465              nig_reg_rx_priority_mask_add = (port) ?
2466                  NIG_REG_P1_RX_COS0_PRIORITY_MASK :
2467                  NIG_REG_P0_RX_COS0_PRIORITY_MASK;
2468              break;
2469         case 1:
2470             nig_reg_rx_priority_mask_add = (port) ?
2471                 NIG_REG_P1_RX_COS1_PRIORITY_MASK :
2472                 NIG_REG_P0_RX_COS1_PRIORITY_MASK;
2473             break;
2474         case 2:
2475             nig_reg_rx_priority_mask_add = (port) ?
2476                 NIG_REG_P1_RX_COS2_PRIORITY_MASK :
2477                 NIG_REG_P0_RX_COS2_PRIORITY_MASK;
2478             break;
2479         case 3:
2480             if (port)
2481                 return -EINVAL;
2482             nig_reg_rx_priority_mask_add = NIG_REG_P0_RX_COS3_PRIORITY_MASK;
2483             break;
2484         case 4:
2485             if (port)
2486                 return -EINVAL;
2487             nig_reg_rx_priority_mask_add = NIG_REG_P0_RX_COS4_PRIORITY_MASK;
2488             break;
2489         case 5:
2490             if (port)
2491                 return -EINVAL;
2492             nig_reg_rx_priority_mask_add = NIG_REG_P0_RX_COS5_PRIORITY_MASK;
2493             break;
2494         }
2495
2496         REG_WR(bp, nig_reg_rx_priority_mask_add, priority_mask);
2497
2498         return 0;
2499 }
2500 static void bnx2x_update_mng(struct link_params *params, u32 link_status)
2501 {
2502         struct bnx2x *bp = params->bp;
2503
2504         REG_WR(bp, params->shmem_base +
2505                offsetof(struct shmem_region,
2506                         port_mb[params->port].link_status), link_status);
2507 }
2508
2509 static void bnx2x_update_pfc_nig(struct link_params *params,
2510                 struct link_vars *vars,
2511                 struct bnx2x_nig_brb_pfc_port_params *nig_params)
2512 {
2513         u32 xcm_mask = 0, ppp_enable = 0, pause_enable = 0, llfc_out_en = 0;
2514         u32 llfc_enable = 0, xcm_out_en = 0, hwpfc_enable = 0;
2515         u32 pkt_priority_to_cos = 0;
2516         struct bnx2x *bp = params->bp;
2517         u8 port = params->port;
2518
2519         int set_pfc = params->feature_config_flags &
2520                 FEATURE_CONFIG_PFC_ENABLED;
2521         DP(NETIF_MSG_LINK, "updating pfc nig parameters\n");
2522
2523         /*
2524          * When NIG_LLH0_XCM_MASK_REG_LLHX_XCM_MASK_BCN bit is set
2525          * MAC control frames (that are not pause packets)
2526          * will be forwarded to the XCM.
2527          */
2528         xcm_mask = REG_RD(bp, port ? NIG_REG_LLH1_XCM_MASK :
2529                           NIG_REG_LLH0_XCM_MASK);
2530         /*
2531          * nig params will override non PFC params, since it's possible to
2532          * do transition from PFC to SAFC
2533          */
2534         if (set_pfc) {
2535                 pause_enable = 0;
2536                 llfc_out_en = 0;
2537                 llfc_enable = 0;
2538                 if (CHIP_IS_E3(bp))
2539                         ppp_enable = 0;
2540                 else
2541                 ppp_enable = 1;
2542                 xcm_mask &= ~(port ? NIG_LLH1_XCM_MASK_REG_LLH1_XCM_MASK_BCN :
2543                                      NIG_LLH0_XCM_MASK_REG_LLH0_XCM_MASK_BCN);
2544                 xcm_out_en = 0;
2545                 hwpfc_enable = 1;
2546         } else  {
2547                 if (nig_params) {
2548                         llfc_out_en = nig_params->llfc_out_en;
2549                         llfc_enable = nig_params->llfc_enable;
2550                         pause_enable = nig_params->pause_enable;
2551                 } else  /*defaul non PFC mode - PAUSE */
2552                         pause_enable = 1;
2553
2554                 xcm_mask |= (port ? NIG_LLH1_XCM_MASK_REG_LLH1_XCM_MASK_BCN :
2555                         NIG_LLH0_XCM_MASK_REG_LLH0_XCM_MASK_BCN);
2556                 xcm_out_en = 1;
2557         }
2558
2559         if (CHIP_IS_E3(bp))
2560                 REG_WR(bp, port ? NIG_REG_BRB1_PAUSE_IN_EN :
2561                        NIG_REG_BRB0_PAUSE_IN_EN, pause_enable);
2562         REG_WR(bp, port ? NIG_REG_LLFC_OUT_EN_1 :
2563                NIG_REG_LLFC_OUT_EN_0, llfc_out_en);
2564         REG_WR(bp, port ? NIG_REG_LLFC_ENABLE_1 :
2565                NIG_REG_LLFC_ENABLE_0, llfc_enable);
2566         REG_WR(bp, port ? NIG_REG_PAUSE_ENABLE_1 :
2567                NIG_REG_PAUSE_ENABLE_0, pause_enable);
2568
2569         REG_WR(bp, port ? NIG_REG_PPP_ENABLE_1 :
2570                NIG_REG_PPP_ENABLE_0, ppp_enable);
2571
2572         REG_WR(bp, port ? NIG_REG_LLH1_XCM_MASK :
2573                NIG_REG_LLH0_XCM_MASK, xcm_mask);
2574
2575         REG_WR(bp, port ? NIG_REG_LLFC_EGRESS_SRC_ENABLE_1 :
2576                NIG_REG_LLFC_EGRESS_SRC_ENABLE_0, 0x7);
2577
2578         /* output enable for RX_XCM # IF */
2579         REG_WR(bp, port ? NIG_REG_XCM1_OUT_EN :
2580                NIG_REG_XCM0_OUT_EN, xcm_out_en);
2581
2582         /* HW PFC TX enable */
2583         REG_WR(bp, port ? NIG_REG_P1_HWPFC_ENABLE :
2584                NIG_REG_P0_HWPFC_ENABLE, hwpfc_enable);
2585
2586         if (nig_params) {
2587                 u8 i = 0;
2588                 pkt_priority_to_cos = nig_params->pkt_priority_to_cos;
2589
2590                 for (i = 0; i < nig_params->num_of_rx_cos_priority_mask; i++)
2591                         bnx2x_pfc_nig_rx_priority_mask(bp, i,
2592                 nig_params->rx_cos_priority_mask[i], port);
2593
2594                 REG_WR(bp, port ? NIG_REG_LLFC_HIGH_PRIORITY_CLASSES_1 :
2595                        NIG_REG_LLFC_HIGH_PRIORITY_CLASSES_0,
2596                        nig_params->llfc_high_priority_classes);
2597
2598                 REG_WR(bp, port ? NIG_REG_LLFC_LOW_PRIORITY_CLASSES_1 :
2599                        NIG_REG_LLFC_LOW_PRIORITY_CLASSES_0,
2600                        nig_params->llfc_low_priority_classes);
2601         }
2602         REG_WR(bp, port ? NIG_REG_P1_PKT_PRIORITY_TO_COS :
2603                NIG_REG_P0_PKT_PRIORITY_TO_COS,
2604                pkt_priority_to_cos);
2605 }
2606
2607 int bnx2x_update_pfc(struct link_params *params,
2608                       struct link_vars *vars,
2609                       struct bnx2x_nig_brb_pfc_port_params *pfc_params)
2610 {
2611         /*
2612          * The PFC and pause are orthogonal to one another, meaning when
2613          * PFC is enabled, the pause are disabled, and when PFC is
2614          * disabled, pause are set according to the pause result.
2615          */
2616         u32 val;
2617         struct bnx2x *bp = params->bp;
2618         int bnx2x_status = 0;
2619         u8 bmac_loopback = (params->loopback_mode == LOOPBACK_BMAC);
2620
2621         if (params->feature_config_flags & FEATURE_CONFIG_PFC_ENABLED)
2622                 vars->link_status |= LINK_STATUS_PFC_ENABLED;
2623         else
2624                 vars->link_status &= ~LINK_STATUS_PFC_ENABLED;
2625
2626         bnx2x_update_mng(params, vars->link_status);
2627
2628         /* update NIG params */
2629         bnx2x_update_pfc_nig(params, vars, pfc_params);
2630
2631         /* update BRB params */
2632         bnx2x_status = bnx2x_update_pfc_brb(params, vars, pfc_params);
2633         if (bnx2x_status)
2634                 return bnx2x_status;
2635
2636         if (!vars->link_up)
2637                 return bnx2x_status;
2638
2639         DP(NETIF_MSG_LINK, "About to update PFC in BMAC\n");
2640         if (CHIP_IS_E3(bp))
2641                 bnx2x_update_pfc_xmac(params, vars, 0);
2642         else {
2643                 val = REG_RD(bp, MISC_REG_RESET_REG_2);
2644                 if ((val &
2645                      (MISC_REGISTERS_RESET_REG_2_RST_BMAC0 << params->port))
2646                     == 0) {
2647                         DP(NETIF_MSG_LINK, "About to update PFC in EMAC\n");
2648                         bnx2x_emac_enable(params, vars, 0);
2649                         return bnx2x_status;
2650                 }
2651                 if (CHIP_IS_E2(bp))
2652                         bnx2x_update_pfc_bmac2(params, vars, bmac_loopback);
2653                 else
2654                         bnx2x_update_pfc_bmac1(params, vars);
2655
2656                 val = 0;
2657                 if ((params->feature_config_flags &
2658                      FEATURE_CONFIG_PFC_ENABLED) ||
2659                     (vars->flow_ctrl & BNX2X_FLOW_CTRL_TX))
2660                         val = 1;
2661                 REG_WR(bp, NIG_REG_BMAC0_PAUSE_OUT_EN + params->port*4, val);
2662         }
2663         return bnx2x_status;
2664 }
2665
2666
2667 static int bnx2x_bmac1_enable(struct link_params *params,
2668                               struct link_vars *vars,
2669                               u8 is_lb)
2670 {
2671         struct bnx2x *bp = params->bp;
2672         u8 port = params->port;
2673         u32 bmac_addr = port ? NIG_REG_INGRESS_BMAC1_MEM :
2674                                NIG_REG_INGRESS_BMAC0_MEM;
2675         u32 wb_data[2];
2676         u32 val;
2677
2678         DP(NETIF_MSG_LINK, "Enabling BigMAC1\n");
2679
2680         /* XGXS control */
2681         wb_data[0] = 0x3c;
2682         wb_data[1] = 0;
2683         REG_WR_DMAE(bp, bmac_addr + BIGMAC_REGISTER_BMAC_XGXS_CONTROL,
2684                     wb_data, 2);
2685
2686         /* tx MAC SA */
2687         wb_data[0] = ((params->mac_addr[2] << 24) |
2688                        (params->mac_addr[3] << 16) |
2689                        (params->mac_addr[4] << 8) |
2690                         params->mac_addr[5]);
2691         wb_data[1] = ((params->mac_addr[0] << 8) |
2692                         params->mac_addr[1]);
2693         REG_WR_DMAE(bp, bmac_addr + BIGMAC_REGISTER_TX_SOURCE_ADDR, wb_data, 2);
2694
2695         /* mac control */
2696         val = 0x3;
2697         if (is_lb) {
2698                 val |= 0x4;
2699                 DP(NETIF_MSG_LINK, "enable bmac loopback\n");
2700         }
2701         wb_data[0] = val;
2702         wb_data[1] = 0;
2703         REG_WR_DMAE(bp, bmac_addr + BIGMAC_REGISTER_BMAC_CONTROL, wb_data, 2);
2704
2705         /* set rx mtu */
2706         wb_data[0] = ETH_MAX_JUMBO_PACKET_SIZE + ETH_OVREHEAD;
2707         wb_data[1] = 0;
2708         REG_WR_DMAE(bp, bmac_addr + BIGMAC_REGISTER_RX_MAX_SIZE, wb_data, 2);
2709
2710         bnx2x_update_pfc_bmac1(params, vars);
2711
2712         /* set tx mtu */
2713         wb_data[0] = ETH_MAX_JUMBO_PACKET_SIZE + ETH_OVREHEAD;
2714         wb_data[1] = 0;
2715         REG_WR_DMAE(bp, bmac_addr + BIGMAC_REGISTER_TX_MAX_SIZE, wb_data, 2);
2716
2717         /* set cnt max size */
2718         wb_data[0] = ETH_MAX_JUMBO_PACKET_SIZE + ETH_OVREHEAD;
2719         wb_data[1] = 0;
2720         REG_WR_DMAE(bp, bmac_addr + BIGMAC_REGISTER_CNT_MAX_SIZE, wb_data, 2);
2721
2722         /* configure safc */
2723         wb_data[0] = 0x1000200;
2724         wb_data[1] = 0;
2725         REG_WR_DMAE(bp, bmac_addr + BIGMAC_REGISTER_RX_LLFC_MSG_FLDS,
2726                     wb_data, 2);
2727
2728         return 0;
2729 }
2730
2731 static int bnx2x_bmac2_enable(struct link_params *params,
2732                               struct link_vars *vars,
2733                               u8 is_lb)
2734 {
2735         struct bnx2x *bp = params->bp;
2736         u8 port = params->port;
2737         u32 bmac_addr = port ? NIG_REG_INGRESS_BMAC1_MEM :
2738                                NIG_REG_INGRESS_BMAC0_MEM;
2739         u32 wb_data[2];
2740
2741         DP(NETIF_MSG_LINK, "Enabling BigMAC2\n");
2742
2743         wb_data[0] = 0;
2744         wb_data[1] = 0;
2745         REG_WR_DMAE(bp, bmac_addr + BIGMAC2_REGISTER_BMAC_CONTROL, wb_data, 2);
2746         udelay(30);
2747
2748         /* XGXS control: Reset phy HW, MDIO registers, PHY PLL and BMAC */
2749         wb_data[0] = 0x3c;
2750         wb_data[1] = 0;
2751         REG_WR_DMAE(bp, bmac_addr + BIGMAC2_REGISTER_BMAC_XGXS_CONTROL,
2752                     wb_data, 2);
2753
2754         udelay(30);
2755
2756         /* tx MAC SA */
2757         wb_data[0] = ((params->mac_addr[2] << 24) |
2758                        (params->mac_addr[3] << 16) |
2759                        (params->mac_addr[4] << 8) |
2760                         params->mac_addr[5]);
2761         wb_data[1] = ((params->mac_addr[0] << 8) |
2762                         params->mac_addr[1]);
2763         REG_WR_DMAE(bp, bmac_addr + BIGMAC2_REGISTER_TX_SOURCE_ADDR,
2764                     wb_data, 2);
2765
2766         udelay(30);
2767
2768         /* Configure SAFC */
2769         wb_data[0] = 0x1000200;
2770         wb_data[1] = 0;
2771         REG_WR_DMAE(bp, bmac_addr + BIGMAC2_REGISTER_RX_LLFC_MSG_FLDS,
2772                     wb_data, 2);
2773         udelay(30);
2774
2775         /* set rx mtu */
2776         wb_data[0] = ETH_MAX_JUMBO_PACKET_SIZE + ETH_OVREHEAD;
2777         wb_data[1] = 0;
2778         REG_WR_DMAE(bp, bmac_addr + BIGMAC2_REGISTER_RX_MAX_SIZE, wb_data, 2);
2779         udelay(30);
2780
2781         /* set tx mtu */
2782         wb_data[0] = ETH_MAX_JUMBO_PACKET_SIZE + ETH_OVREHEAD;
2783         wb_data[1] = 0;
2784         REG_WR_DMAE(bp, bmac_addr + BIGMAC2_REGISTER_TX_MAX_SIZE, wb_data, 2);
2785         udelay(30);
2786         /* set cnt max size */
2787         wb_data[0] = ETH_MAX_JUMBO_PACKET_SIZE + ETH_OVREHEAD - 2;
2788         wb_data[1] = 0;
2789         REG_WR_DMAE(bp, bmac_addr + BIGMAC2_REGISTER_CNT_MAX_SIZE, wb_data, 2);
2790         udelay(30);
2791         bnx2x_update_pfc_bmac2(params, vars, is_lb);
2792
2793         return 0;
2794 }
2795
2796 static int bnx2x_bmac_enable(struct link_params *params,
2797                              struct link_vars *vars,
2798                              u8 is_lb)
2799 {
2800         int rc = 0;
2801         u8 port = params->port;
2802         struct bnx2x *bp = params->bp;
2803         u32 val;
2804         /* reset and unreset the BigMac */
2805         REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_2_CLEAR,
2806                (MISC_REGISTERS_RESET_REG_2_RST_BMAC0 << port));
2807         msleep(1);
2808
2809         REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_2_SET,
2810                (MISC_REGISTERS_RESET_REG_2_RST_BMAC0 << port));
2811
2812         /* enable access for bmac registers */
2813         REG_WR(bp, NIG_REG_BMAC0_REGS_OUT_EN + port*4, 0x1);
2814
2815         /* Enable BMAC according to BMAC type*/
2816         if (CHIP_IS_E2(bp))
2817                 rc = bnx2x_bmac2_enable(params, vars, is_lb);
2818         else
2819                 rc = bnx2x_bmac1_enable(params, vars, is_lb);
2820         REG_WR(bp, NIG_REG_XGXS_SERDES0_MODE_SEL + port*4, 0x1);
2821         REG_WR(bp, NIG_REG_XGXS_LANE_SEL_P0 + port*4, 0x0);
2822         REG_WR(bp, NIG_REG_EGRESS_EMAC0_PORT + port*4, 0x0);
2823         val = 0;
2824         if ((params->feature_config_flags &
2825               FEATURE_CONFIG_PFC_ENABLED) ||
2826             (vars->flow_ctrl & BNX2X_FLOW_CTRL_TX))
2827                 val = 1;
2828         REG_WR(bp, NIG_REG_BMAC0_PAUSE_OUT_EN + port*4, val);
2829         REG_WR(bp, NIG_REG_EGRESS_EMAC0_OUT_EN + port*4, 0x0);
2830         REG_WR(bp, NIG_REG_EMAC0_IN_EN + port*4, 0x0);
2831         REG_WR(bp, NIG_REG_EMAC0_PAUSE_OUT_EN + port*4, 0x0);
2832         REG_WR(bp, NIG_REG_BMAC0_IN_EN + port*4, 0x1);
2833         REG_WR(bp, NIG_REG_BMAC0_OUT_EN + port*4, 0x1);
2834
2835         vars->mac_type = MAC_TYPE_BMAC;
2836         return rc;
2837 }
2838
2839 static void bnx2x_bmac_rx_disable(struct bnx2x *bp, u8 port)
2840 {
2841         u32 bmac_addr = port ? NIG_REG_INGRESS_BMAC1_MEM :
2842                         NIG_REG_INGRESS_BMAC0_MEM;
2843         u32 wb_data[2];
2844         u32 nig_bmac_enable = REG_RD(bp, NIG_REG_BMAC0_REGS_OUT_EN + port*4);
2845
2846         /* Only if the bmac is out of reset */
2847         if (REG_RD(bp, MISC_REG_RESET_REG_2) &
2848                         (MISC_REGISTERS_RESET_REG_2_RST_BMAC0 << port) &&
2849             nig_bmac_enable) {
2850
2851                 if (CHIP_IS_E2(bp)) {
2852                         /* Clear Rx Enable bit in BMAC_CONTROL register */
2853                         REG_RD_DMAE(bp, bmac_addr +
2854                                     BIGMAC2_REGISTER_BMAC_CONTROL,
2855                                     wb_data, 2);
2856                         wb_data[0] &= ~BMAC_CONTROL_RX_ENABLE;
2857                         REG_WR_DMAE(bp, bmac_addr +
2858                                     BIGMAC2_REGISTER_BMAC_CONTROL,
2859                                     wb_data, 2);
2860                 } else {
2861                         /* Clear Rx Enable bit in BMAC_CONTROL register */
2862                         REG_RD_DMAE(bp, bmac_addr +
2863                                         BIGMAC_REGISTER_BMAC_CONTROL,
2864                                         wb_data, 2);
2865                         wb_data[0] &= ~BMAC_CONTROL_RX_ENABLE;
2866                         REG_WR_DMAE(bp, bmac_addr +
2867                                         BIGMAC_REGISTER_BMAC_CONTROL,
2868                                         wb_data, 2);
2869                 }
2870                 msleep(1);
2871         }
2872 }
2873
2874 static int bnx2x_pbf_update(struct link_params *params, u32 flow_ctrl,
2875                             u32 line_speed)
2876 {
2877         struct bnx2x *bp = params->bp;
2878         u8 port = params->port;
2879         u32 init_crd, crd;
2880         u32 count = 1000;
2881
2882         /* disable port */
2883         REG_WR(bp, PBF_REG_DISABLE_NEW_TASK_PROC_P0 + port*4, 0x1);
2884
2885         /* wait for init credit */
2886         init_crd = REG_RD(bp, PBF_REG_P0_INIT_CRD + port*4);
2887         crd = REG_RD(bp, PBF_REG_P0_CREDIT + port*8);
2888         DP(NETIF_MSG_LINK, "init_crd 0x%x  crd 0x%x\n", init_crd, crd);
2889
2890         while ((init_crd != crd) && count) {
2891                 msleep(5);
2892
2893                 crd = REG_RD(bp, PBF_REG_P0_CREDIT + port*8);
2894                 count--;
2895         }
2896         crd = REG_RD(bp, PBF_REG_P0_CREDIT + port*8);
2897         if (init_crd != crd) {
2898                 DP(NETIF_MSG_LINK, "BUG! init_crd 0x%x != crd 0x%x\n",
2899                           init_crd, crd);
2900                 return -EINVAL;
2901         }
2902
2903         if (flow_ctrl & BNX2X_FLOW_CTRL_RX ||
2904             line_speed == SPEED_10 ||
2905             line_speed == SPEED_100 ||
2906             line_speed == SPEED_1000 ||
2907             line_speed == SPEED_2500) {
2908                 REG_WR(bp, PBF_REG_P0_PAUSE_ENABLE + port*4, 1);
2909                 /* update threshold */
2910                 REG_WR(bp, PBF_REG_P0_ARB_THRSH + port*4, 0);
2911                 /* update init credit */
2912                 init_crd = 778;         /* (800-18-4) */
2913
2914         } else {
2915                 u32 thresh = (ETH_MAX_JUMBO_PACKET_SIZE +
2916                               ETH_OVREHEAD)/16;
2917                 REG_WR(bp, PBF_REG_P0_PAUSE_ENABLE + port*4, 0);
2918                 /* update threshold */
2919                 REG_WR(bp, PBF_REG_P0_ARB_THRSH + port*4, thresh);
2920                 /* update init credit */
2921                 switch (line_speed) {
2922                 case SPEED_10000:
2923                         init_crd = thresh + 553 - 22;
2924                         break;
2925                 default:
2926                         DP(NETIF_MSG_LINK, "Invalid line_speed 0x%x\n",
2927                                   line_speed);
2928                         return -EINVAL;
2929                 }
2930         }
2931         REG_WR(bp, PBF_REG_P0_INIT_CRD + port*4, init_crd);
2932         DP(NETIF_MSG_LINK, "PBF updated to speed %d credit %d\n",
2933                  line_speed, init_crd);
2934
2935         /* probe the credit changes */
2936         REG_WR(bp, PBF_REG_INIT_P0 + port*4, 0x1);
2937         msleep(5);
2938         REG_WR(bp, PBF_REG_INIT_P0 + port*4, 0x0);
2939
2940         /* enable port */
2941         REG_WR(bp, PBF_REG_DISABLE_NEW_TASK_PROC_P0 + port*4, 0x0);
2942         return 0;
2943 }
2944
2945 /**
2946  * bnx2x_get_emac_base - retrive emac base address
2947  *
2948  * @bp:                 driver handle
2949  * @mdc_mdio_access:    access type
2950  * @port:               port id
2951  *
2952  * This function selects the MDC/MDIO access (through emac0 or
2953  * emac1) depend on the mdc_mdio_access, port, port swapped. Each
2954  * phy has a default access mode, which could also be overridden
2955  * by nvram configuration. This parameter, whether this is the
2956  * default phy configuration, or the nvram overrun
2957  * configuration, is passed here as mdc_mdio_access and selects
2958  * the emac_base for the CL45 read/writes operations
2959  */
2960 static u32 bnx2x_get_emac_base(struct bnx2x *bp,
2961                                u32 mdc_mdio_access, u8 port)
2962 {
2963         u32 emac_base = 0;
2964         switch (mdc_mdio_access) {
2965         case SHARED_HW_CFG_MDC_MDIO_ACCESS1_PHY_TYPE:
2966                 break;
2967         case SHARED_HW_CFG_MDC_MDIO_ACCESS1_EMAC0:
2968                 if (REG_RD(bp, NIG_REG_PORT_SWAP))
2969                         emac_base = GRCBASE_EMAC1;
2970                 else
2971                         emac_base = GRCBASE_EMAC0;
2972                 break;
2973         case SHARED_HW_CFG_MDC_MDIO_ACCESS1_EMAC1:
2974                 if (REG_RD(bp, NIG_REG_PORT_SWAP))
2975                         emac_base = GRCBASE_EMAC0;
2976                 else
2977                         emac_base = GRCBASE_EMAC1;
2978                 break;
2979         case SHARED_HW_CFG_MDC_MDIO_ACCESS1_BOTH:
2980                 emac_base = (port) ? GRCBASE_EMAC1 : GRCBASE_EMAC0;
2981                 break;
2982         case SHARED_HW_CFG_MDC_MDIO_ACCESS1_SWAPPED:
2983                 emac_base = (port) ? GRCBASE_EMAC0 : GRCBASE_EMAC1;
2984                 break;
2985         default:
2986                 break;
2987         }
2988         return emac_base;
2989
2990 }
2991
2992 /******************************************************************/
2993 /*                      CL22 access functions                     */
2994 /******************************************************************/
2995 static int bnx2x_cl22_write(struct bnx2x *bp,
2996                                        struct bnx2x_phy *phy,
2997                                        u16 reg, u16 val)
2998 {
2999         u32 tmp, mode;
3000         u8 i;
3001         int rc = 0;
3002         /* Switch to CL22 */
3003         mode = REG_RD(bp, phy->mdio_ctrl + EMAC_REG_EMAC_MDIO_MODE);
3004         REG_WR(bp, phy->mdio_ctrl + EMAC_REG_EMAC_MDIO_MODE,
3005                mode & ~EMAC_MDIO_MODE_CLAUSE_45);
3006
3007         /* address */
3008         tmp = ((phy->addr << 21) | (reg << 16) | val |
3009                EMAC_MDIO_COMM_COMMAND_WRITE_22 |
3010                EMAC_MDIO_COMM_START_BUSY);
3011         REG_WR(bp, phy->mdio_ctrl + EMAC_REG_EMAC_MDIO_COMM, tmp);
3012
3013         for (i = 0; i < 50; i++) {
3014                 udelay(10);
3015
3016                 tmp = REG_RD(bp, phy->mdio_ctrl + EMAC_REG_EMAC_MDIO_COMM);
3017                 if (!(tmp & EMAC_MDIO_COMM_START_BUSY)) {
3018                         udelay(5);
3019                         break;
3020                 }
3021         }
3022         if (tmp & EMAC_MDIO_COMM_START_BUSY) {
3023                 DP(NETIF_MSG_LINK, "write phy register failed\n");
3024                 rc = -EFAULT;
3025         }
3026         REG_WR(bp, phy->mdio_ctrl + EMAC_REG_EMAC_MDIO_MODE, mode);
3027         return rc;
3028 }
3029
3030 static int bnx2x_cl22_read(struct bnx2x *bp,
3031                                       struct bnx2x_phy *phy,
3032                                       u16 reg, u16 *ret_val)
3033 {
3034         u32 val, mode;
3035         u16 i;
3036         int rc = 0;
3037
3038         /* Switch to CL22 */
3039         mode = REG_RD(bp, phy->mdio_ctrl + EMAC_REG_EMAC_MDIO_MODE);
3040         REG_WR(bp, phy->mdio_ctrl + EMAC_REG_EMAC_MDIO_MODE,
3041                mode & ~EMAC_MDIO_MODE_CLAUSE_45);
3042
3043         /* address */
3044         val = ((phy->addr << 21) | (reg << 16) |
3045                EMAC_MDIO_COMM_COMMAND_READ_22 |
3046                EMAC_MDIO_COMM_START_BUSY);
3047         REG_WR(bp, phy->mdio_ctrl + EMAC_REG_EMAC_MDIO_COMM, val);
3048
3049         for (i = 0; i < 50; i++) {
3050                 udelay(10);
3051
3052                 val = REG_RD(bp, phy->mdio_ctrl + EMAC_REG_EMAC_MDIO_COMM);
3053                 if (!(val & EMAC_MDIO_COMM_START_BUSY)) {
3054                         *ret_val = (u16)(val & EMAC_MDIO_COMM_DATA);
3055                         udelay(5);
3056                         break;
3057                 }
3058         }
3059         if (val & EMAC_MDIO_COMM_START_BUSY) {
3060                 DP(NETIF_MSG_LINK, "read phy register failed\n");
3061
3062                 *ret_val = 0;
3063                 rc = -EFAULT;
3064         }
3065         REG_WR(bp, phy->mdio_ctrl + EMAC_REG_EMAC_MDIO_MODE, mode);
3066         return rc;
3067 }
3068
3069 /******************************************************************/
3070 /*                      CL45 access functions                     */
3071 /******************************************************************/
3072 static int bnx2x_cl45_read(struct bnx2x *bp, struct bnx2x_phy *phy,
3073                            u8 devad, u16 reg, u16 *ret_val)
3074 {
3075         u32 val;
3076         u16 i;
3077         int rc = 0;
3078         if (phy->flags & FLAGS_MDC_MDIO_WA_B0)
3079                 bnx2x_bits_en(bp, phy->mdio_ctrl + EMAC_REG_EMAC_MDIO_STATUS,
3080                               EMAC_MDIO_STATUS_10MB);
3081         /* address */
3082         val = ((phy->addr << 21) | (devad << 16) | reg |
3083                EMAC_MDIO_COMM_COMMAND_ADDRESS |
3084                EMAC_MDIO_COMM_START_BUSY);
3085         REG_WR(bp, phy->mdio_ctrl + EMAC_REG_EMAC_MDIO_COMM, val);
3086
3087         for (i = 0; i < 50; i++) {
3088                 udelay(10);
3089
3090                 val = REG_RD(bp, phy->mdio_ctrl + EMAC_REG_EMAC_MDIO_COMM);
3091                 if (!(val & EMAC_MDIO_COMM_START_BUSY)) {
3092                         udelay(5);
3093                         break;
3094                 }
3095         }
3096         if (val & EMAC_MDIO_COMM_START_BUSY) {
3097                 DP(NETIF_MSG_LINK, "read phy register failed\n");
3098                 netdev_err(bp->dev,  "MDC/MDIO access timeout\n");
3099                 *ret_val = 0;
3100                 rc = -EFAULT;
3101         } else {
3102                 /* data */
3103                 val = ((phy->addr << 21) | (devad << 16) |
3104                        EMAC_MDIO_COMM_COMMAND_READ_45 |
3105                        EMAC_MDIO_COMM_START_BUSY);
3106                 REG_WR(bp, phy->mdio_ctrl + EMAC_REG_EMAC_MDIO_COMM, val);
3107
3108                 for (i = 0; i < 50; i++) {
3109                         udelay(10);
3110
3111                         val = REG_RD(bp, phy->mdio_ctrl +
3112                                      EMAC_REG_EMAC_MDIO_COMM);
3113                         if (!(val & EMAC_MDIO_COMM_START_BUSY)) {
3114                                 *ret_val = (u16)(val & EMAC_MDIO_COMM_DATA);
3115                                 break;
3116                         }
3117                 }
3118                 if (val & EMAC_MDIO_COMM_START_BUSY) {
3119                         DP(NETIF_MSG_LINK, "read phy register failed\n");
3120                         netdev_err(bp->dev,  "MDC/MDIO access timeout\n");
3121                         *ret_val = 0;
3122                         rc = -EFAULT;
3123                 }
3124         }
3125         /* Work around for E3 A0 */
3126         if (phy->flags & FLAGS_MDC_MDIO_WA) {
3127                 phy->flags ^= FLAGS_DUMMY_READ;
3128                 if (phy->flags & FLAGS_DUMMY_READ) {
3129                         u16 temp_val;
3130                         bnx2x_cl45_read(bp, phy, devad, 0xf, &temp_val);
3131                 }
3132         }
3133
3134         if (phy->flags & FLAGS_MDC_MDIO_WA_B0)
3135                 bnx2x_bits_dis(bp, phy->mdio_ctrl + EMAC_REG_EMAC_MDIO_STATUS,
3136                                EMAC_MDIO_STATUS_10MB);
3137         return rc;
3138 }
3139
3140 static int bnx2x_cl45_write(struct bnx2x *bp, struct bnx2x_phy *phy,
3141                             u8 devad, u16 reg, u16 val)
3142 {
3143         u32 tmp;
3144         u8 i;
3145         int rc = 0;
3146         if (phy->flags & FLAGS_MDC_MDIO_WA_B0)
3147                 bnx2x_bits_en(bp, phy->mdio_ctrl + EMAC_REG_EMAC_MDIO_STATUS,
3148                               EMAC_MDIO_STATUS_10MB);
3149
3150         /* address */
3151
3152         tmp = ((phy->addr << 21) | (devad << 16) | reg |
3153                EMAC_MDIO_COMM_COMMAND_ADDRESS |
3154                EMAC_MDIO_COMM_START_BUSY);
3155         REG_WR(bp, phy->mdio_ctrl + EMAC_REG_EMAC_MDIO_COMM, tmp);
3156
3157         for (i = 0; i < 50; i++) {
3158                 udelay(10);
3159
3160                 tmp = REG_RD(bp, phy->mdio_ctrl + EMAC_REG_EMAC_MDIO_COMM);
3161                 if (!(tmp & EMAC_MDIO_COMM_START_BUSY)) {
3162                         udelay(5);
3163                         break;
3164                 }
3165         }
3166         if (tmp & EMAC_MDIO_COMM_START_BUSY) {
3167                 DP(NETIF_MSG_LINK, "write phy register failed\n");
3168                 netdev_err(bp->dev,  "MDC/MDIO access timeout\n");
3169                 rc = -EFAULT;
3170         } else {
3171                 /* data */
3172                 tmp = ((phy->addr << 21) | (devad << 16) | val |
3173                        EMAC_MDIO_COMM_COMMAND_WRITE_45 |
3174                        EMAC_MDIO_COMM_START_BUSY);
3175                 REG_WR(bp, phy->mdio_ctrl + EMAC_REG_EMAC_MDIO_COMM, tmp);
3176
3177                 for (i = 0; i < 50; i++) {
3178                         udelay(10);
3179
3180                         tmp = REG_RD(bp, phy->mdio_ctrl +
3181                                      EMAC_REG_EMAC_MDIO_COMM);
3182                         if (!(tmp & EMAC_MDIO_COMM_START_BUSY)) {
3183                                 udelay(5);
3184                                 break;
3185                         }
3186                 }
3187                 if (tmp & EMAC_MDIO_COMM_START_BUSY) {
3188                         DP(NETIF_MSG_LINK, "write phy register failed\n");
3189                         netdev_err(bp->dev,  "MDC/MDIO access timeout\n");
3190                         rc = -EFAULT;
3191                 }
3192         }
3193         /* Work around for E3 A0 */
3194         if (phy->flags & FLAGS_MDC_MDIO_WA) {
3195                 phy->flags ^= FLAGS_DUMMY_READ;
3196                 if (phy->flags & FLAGS_DUMMY_READ) {
3197                         u16 temp_val;
3198                         bnx2x_cl45_read(bp, phy, devad, 0xf, &temp_val);
3199                 }
3200         }
3201         if (phy->flags & FLAGS_MDC_MDIO_WA_B0)
3202                 bnx2x_bits_dis(bp, phy->mdio_ctrl + EMAC_REG_EMAC_MDIO_STATUS,
3203                                EMAC_MDIO_STATUS_10MB);
3204         return rc;
3205 }
3206 /******************************************************************/
3207 /*                      BSC access functions from E3              */
3208 /******************************************************************/
3209 static void bnx2x_bsc_module_sel(struct link_params *params)
3210 {
3211         int idx;
3212         u32 board_cfg, sfp_ctrl;
3213         u32 i2c_pins[I2C_SWITCH_WIDTH], i2c_val[I2C_SWITCH_WIDTH];
3214         struct bnx2x *bp = params->bp;
3215         u8 port = params->port;
3216         /* Read I2C output PINs */
3217         board_cfg = REG_RD(bp, params->shmem_base +
3218                            offsetof(struct shmem_region,
3219                                     dev_info.shared_hw_config.board));
3220         i2c_pins[I2C_BSC0] = board_cfg & SHARED_HW_CFG_E3_I2C_MUX0_MASK;
3221         i2c_pins[I2C_BSC1] = (board_cfg & SHARED_HW_CFG_E3_I2C_MUX1_MASK) >>
3222                         SHARED_HW_CFG_E3_I2C_MUX1_SHIFT;
3223
3224         /* Read I2C output value */
3225         sfp_ctrl = REG_RD(bp, params->shmem_base +
3226                           offsetof(struct shmem_region,
3227                                  dev_info.port_hw_config[port].e3_cmn_pin_cfg));
3228         i2c_val[I2C_BSC0] = (sfp_ctrl & PORT_HW_CFG_E3_I2C_MUX0_MASK) > 0;
3229         i2c_val[I2C_BSC1] = (sfp_ctrl & PORT_HW_CFG_E3_I2C_MUX1_MASK) > 0;
3230         DP(NETIF_MSG_LINK, "Setting BSC switch\n");
3231         for (idx = 0; idx < I2C_SWITCH_WIDTH; idx++)
3232                 bnx2x_set_cfg_pin(bp, i2c_pins[idx], i2c_val[idx]);
3233 }
3234
3235 static int bnx2x_bsc_read(struct link_params *params,
3236                           struct bnx2x_phy *phy,
3237                           u8 sl_devid,
3238                           u16 sl_addr,
3239                           u8 lc_addr,
3240                           u8 xfer_cnt,
3241                           u32 *data_array)
3242 {
3243         u32 val, i;
3244         int rc = 0;
3245         struct bnx2x *bp = params->bp;
3246
3247         if ((sl_devid != 0xa0) && (sl_devid != 0xa2)) {
3248                 DP(NETIF_MSG_LINK, "invalid sl_devid 0x%x\n", sl_devid);
3249                 return -EINVAL;
3250         }
3251
3252         if (xfer_cnt > 16) {
3253                 DP(NETIF_MSG_LINK, "invalid xfer_cnt %d. Max is 16 bytes\n",
3254                                         xfer_cnt);
3255                 return -EINVAL;
3256         }
3257         bnx2x_bsc_module_sel(params);
3258
3259         xfer_cnt = 16 - lc_addr;
3260
3261         /* enable the engine */
3262         val = REG_RD(bp, MCP_REG_MCPR_IMC_COMMAND);
3263         val |= MCPR_IMC_COMMAND_ENABLE;
3264         REG_WR(bp, MCP_REG_MCPR_IMC_COMMAND, val);
3265
3266         /* program slave device ID */
3267         val = (sl_devid << 16) | sl_addr;
3268         REG_WR(bp, MCP_REG_MCPR_IMC_SLAVE_CONTROL, val);
3269
3270         /* start xfer with 0 byte to update the address pointer ???*/
3271         val = (MCPR_IMC_COMMAND_ENABLE) |
3272               (MCPR_IMC_COMMAND_WRITE_OP <<
3273                 MCPR_IMC_COMMAND_OPERATION_BITSHIFT) |
3274                 (lc_addr << MCPR_IMC_COMMAND_TRANSFER_ADDRESS_BITSHIFT) | (0);
3275         REG_WR(bp, MCP_REG_MCPR_IMC_COMMAND, val);
3276
3277         /* poll for completion */
3278         i = 0;
3279         val = REG_RD(bp, MCP_REG_MCPR_IMC_COMMAND);
3280         while (((val >> MCPR_IMC_COMMAND_IMC_STATUS_BITSHIFT) & 0x3) != 1) {
3281                 udelay(10);
3282                 val = REG_RD(bp, MCP_REG_MCPR_IMC_COMMAND);
3283                 if (i++ > 1000) {
3284                         DP(NETIF_MSG_LINK, "wr 0 byte timed out after %d try\n",
3285                                                                 i);
3286                         rc = -EFAULT;
3287                         break;
3288                 }
3289         }
3290         if (rc == -EFAULT)
3291                 return rc;
3292
3293         /* start xfer with read op */
3294         val = (MCPR_IMC_COMMAND_ENABLE) |
3295                 (MCPR_IMC_COMMAND_READ_OP <<
3296                 MCPR_IMC_COMMAND_OPERATION_BITSHIFT) |
3297                 (lc_addr << MCPR_IMC_COMMAND_TRANSFER_ADDRESS_BITSHIFT) |
3298                   (xfer_cnt);
3299         REG_WR(bp, MCP_REG_MCPR_IMC_COMMAND, val);
3300
3301         /* poll for completion */
3302         i = 0;
3303         val = REG_RD(bp, MCP_REG_MCPR_IMC_COMMAND);
3304         while (((val >> MCPR_IMC_COMMAND_IMC_STATUS_BITSHIFT) & 0x3) != 1) {
3305                 udelay(10);
3306                 val = REG_RD(bp, MCP_REG_MCPR_IMC_COMMAND);
3307                 if (i++ > 1000) {
3308                         DP(NETIF_MSG_LINK, "rd op timed out after %d try\n", i);
3309                         rc = -EFAULT;
3310                         break;
3311                 }
3312         }
3313         if (rc == -EFAULT)
3314                 return rc;
3315
3316         for (i = (lc_addr >> 2); i < 4; i++) {
3317                 data_array[i] = REG_RD(bp, (MCP_REG_MCPR_IMC_DATAREG0 + i*4));
3318 #ifdef __BIG_ENDIAN
3319                 data_array[i] = ((data_array[i] & 0x000000ff) << 24) |
3320                                 ((data_array[i] & 0x0000ff00) << 8) |
3321                                 ((data_array[i] & 0x00ff0000) >> 8) |
3322                                 ((data_array[i] & 0xff000000) >> 24);
3323 #endif
3324         }
3325         return rc;
3326 }
3327
3328 static void bnx2x_cl45_read_or_write(struct bnx2x *bp, struct bnx2x_phy *phy,
3329                                      u8 devad, u16 reg, u16 or_val)
3330 {
3331         u16 val;
3332         bnx2x_cl45_read(bp, phy, devad, reg, &val);
3333         bnx2x_cl45_write(bp, phy, devad, reg, val | or_val);
3334 }
3335
3336 int bnx2x_phy_read(struct link_params *params, u8 phy_addr,
3337                    u8 devad, u16 reg, u16 *ret_val)
3338 {
3339         u8 phy_index;
3340         /*
3341          * Probe for the phy according to the given phy_addr, and execute
3342          * the read request on it
3343          */
3344         for (phy_index = 0; phy_index < params->num_phys; phy_index++) {
3345                 if (params->phy[phy_index].addr == phy_addr) {
3346                         return bnx2x_cl45_read(params->bp,
3347                                                &params->phy[phy_index], devad,
3348                                                reg, ret_val);
3349                 }
3350         }
3351         return -EINVAL;
3352 }
3353
3354 int bnx2x_phy_write(struct link_params *params, u8 phy_addr,
3355                     u8 devad, u16 reg, u16 val)
3356 {
3357         u8 phy_index;
3358         /*
3359          * Probe for the phy according to the given phy_addr, and execute
3360          * the write request on it
3361          */
3362         for (phy_index = 0; phy_index < params->num_phys; phy_index++) {
3363                 if (params->phy[phy_index].addr == phy_addr) {
3364                         return bnx2x_cl45_write(params->bp,
3365                                                 &params->phy[phy_index], devad,
3366                                                 reg, val);
3367                 }
3368         }
3369         return -EINVAL;
3370 }
3371 static u8 bnx2x_get_warpcore_lane(struct bnx2x_phy *phy,
3372                                   struct link_params *params)
3373 {
3374         u8 lane = 0;
3375         struct bnx2x *bp = params->bp;
3376         u32 path_swap, path_swap_ovr;
3377         u8 path, port;
3378
3379         path = BP_PATH(bp);
3380         port = params->port;
3381
3382         if (bnx2x_is_4_port_mode(bp)) {
3383                 u32 port_swap, port_swap_ovr;
3384
3385                 /*figure out path swap value */
3386                 path_swap_ovr = REG_RD(bp, MISC_REG_FOUR_PORT_PATH_SWAP_OVWR);
3387                 if (path_swap_ovr & 0x1)
3388                         path_swap = (path_swap_ovr & 0x2);
3389                 else
3390                         path_swap = REG_RD(bp, MISC_REG_FOUR_PORT_PATH_SWAP);
3391
3392                 if (path_swap)
3393                         path = path ^ 1;
3394
3395                 /*figure out port swap value */
3396                 port_swap_ovr = REG_RD(bp, MISC_REG_FOUR_PORT_PORT_SWAP_OVWR);
3397                 if (port_swap_ovr & 0x1)
3398                         port_swap = (port_swap_ovr & 0x2);
3399                 else
3400                         port_swap = REG_RD(bp, MISC_REG_FOUR_PORT_PORT_SWAP);
3401
3402                 if (port_swap)
3403                         port = port ^ 1;
3404
3405                 lane = (port<<1) + path;
3406         } else { /* two port mode - no port swap */
3407
3408                 /*figure out path swap value */
3409                 path_swap_ovr =
3410                         REG_RD(bp, MISC_REG_TWO_PORT_PATH_SWAP_OVWR);
3411                 if (path_swap_ovr & 0x1) {
3412                         path_swap = (path_swap_ovr & 0x2);
3413                 } else {
3414                         path_swap =
3415                                 REG_RD(bp, MISC_REG_TWO_PORT_PATH_SWAP);
3416                 }
3417                 if (path_swap)
3418                         path = path ^ 1;
3419
3420                 lane = path << 1 ;
3421         }
3422         return lane;
3423 }
3424
3425 static void bnx2x_set_aer_mmd(struct link_params *params,
3426                               struct bnx2x_phy *phy)
3427 {
3428         u32 ser_lane;
3429         u16 offset, aer_val;
3430         struct bnx2x *bp = params->bp;
3431         ser_lane = ((params->lane_config &
3432                      PORT_HW_CFG_LANE_SWAP_CFG_MASTER_MASK) >>
3433                      PORT_HW_CFG_LANE_SWAP_CFG_MASTER_SHIFT);
3434
3435         offset = (phy->type == PORT_HW_CFG_XGXS_EXT_PHY_TYPE_DIRECT) ?
3436                 (phy->addr + ser_lane) : 0;
3437
3438         if (USES_WARPCORE(bp)) {
3439                 aer_val = bnx2x_get_warpcore_lane(phy, params);
3440                 /*
3441                  * In Dual-lane mode, two lanes are joined together,
3442                  * so in order to configure them, the AER broadcast method is
3443                  * used here.
3444                  * 0x200 is the broadcast address for lanes 0,1
3445                  * 0x201 is the broadcast address for lanes 2,3
3446                  */
3447                 if (phy->flags & FLAGS_WC_DUAL_MODE)
3448                         aer_val = (aer_val >> 1) | 0x200;
3449         } else if (CHIP_IS_E2(bp))
3450                 aer_val = 0x3800 + offset - 1;
3451         else
3452                 aer_val = 0x3800 + offset;
3453
3454         CL22_WR_OVER_CL45(bp, phy, MDIO_REG_BANK_AER_BLOCK,
3455                           MDIO_AER_BLOCK_AER_REG, aer_val);
3456
3457 }
3458
3459 /******************************************************************/
3460 /*                      Internal phy section                      */
3461 /******************************************************************/
3462
3463 static void bnx2x_set_serdes_access(struct bnx2x *bp, u8 port)
3464 {
3465         u32 emac_base = (port) ? GRCBASE_EMAC1 : GRCBASE_EMAC0;
3466
3467         /* Set Clause 22 */
3468         REG_WR(bp, NIG_REG_SERDES0_CTRL_MD_ST + port*0x10, 1);
3469         REG_WR(bp, emac_base + EMAC_REG_EMAC_MDIO_COMM, 0x245f8000);
3470         udelay(500);
3471         REG_WR(bp, emac_base + EMAC_REG_EMAC_MDIO_COMM, 0x245d000f);
3472         udelay(500);
3473          /* Set Clause 45 */
3474         REG_WR(bp, NIG_REG_SERDES0_CTRL_MD_ST + port*0x10, 0);
3475 }
3476
3477 static void bnx2x_serdes_deassert(struct bnx2x *bp, u8 port)
3478 {
3479         u32 val;
3480
3481         DP(NETIF_MSG_LINK, "bnx2x_serdes_deassert\n");
3482
3483         val = SERDES_RESET_BITS << (port*16);
3484
3485         /* reset and unreset the SerDes/XGXS */
3486         REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_3_CLEAR, val);
3487         udelay(500);
3488         REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_3_SET, val);
3489
3490         bnx2x_set_serdes_access(bp, port);
3491
3492         REG_WR(bp, NIG_REG_SERDES0_CTRL_MD_DEVAD + port*0x10,
3493                DEFAULT_PHY_DEV_ADDR);
3494 }
3495
3496 static void bnx2x_xgxs_deassert(struct link_params *params)
3497 {
3498         struct bnx2x *bp = params->bp;
3499         u8 port;
3500         u32 val;
3501         DP(NETIF_MSG_LINK, "bnx2x_xgxs_deassert\n");
3502         port = params->port;
3503
3504         val = XGXS_RESET_BITS << (port*16);
3505
3506         /* reset and unreset the SerDes/XGXS */
3507         REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_3_CLEAR, val);
3508         udelay(500);
3509         REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_3_SET, val);
3510
3511         REG_WR(bp, NIG_REG_XGXS0_CTRL_MD_ST + port*0x18, 0);
3512         REG_WR(bp, NIG_REG_XGXS0_CTRL_MD_DEVAD + port*0x18,
3513                params->phy[INT_PHY].def_md_devad);
3514 }
3515
3516 static void bnx2x_calc_ieee_aneg_adv(struct bnx2x_phy *phy,
3517                                      struct link_params *params, u16 *ieee_fc)
3518 {
3519         struct bnx2x *bp = params->bp;
3520         *ieee_fc = MDIO_COMBO_IEEE0_AUTO_NEG_ADV_FULL_DUPLEX;
3521         /**
3522          * resolve pause mode and advertisement Please refer to Table
3523          * 28B-3 of the 802.3ab-1999 spec
3524          */
3525
3526         switch (phy->req_flow_ctrl) {
3527         case BNX2X_FLOW_CTRL_AUTO:
3528                 if (params->req_fc_auto_adv == BNX2X_FLOW_CTRL_BOTH)
3529                         *ieee_fc |= MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_BOTH;
3530                 else
3531                         *ieee_fc |=
3532                         MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_ASYMMETRIC;
3533                 break;
3534
3535         case BNX2X_FLOW_CTRL_TX:
3536                 *ieee_fc |= MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_ASYMMETRIC;
3537                 break;
3538
3539         case BNX2X_FLOW_CTRL_RX:
3540         case BNX2X_FLOW_CTRL_BOTH:
3541                 *ieee_fc |= MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_BOTH;
3542                 break;
3543
3544         case BNX2X_FLOW_CTRL_NONE:
3545         default:
3546                 *ieee_fc |= MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_NONE;
3547                 break;
3548         }
3549         DP(NETIF_MSG_LINK, "ieee_fc = 0x%x\n", *ieee_fc);
3550 }
3551
3552 static void set_phy_vars(struct link_params *params,
3553                          struct link_vars *vars)
3554 {
3555         struct bnx2x *bp = params->bp;
3556         u8 actual_phy_idx, phy_index, link_cfg_idx;
3557         u8 phy_config_swapped = params->multi_phy_config &
3558                         PORT_HW_CFG_PHY_SWAPPED_ENABLED;
3559         for (phy_index = INT_PHY; phy_index < params->num_phys;
3560               phy_index++) {
3561                 link_cfg_idx = LINK_CONFIG_IDX(phy_index);
3562                 actual_phy_idx = phy_index;
3563                 if (phy_config_swapped) {
3564                         if (phy_index == EXT_PHY1)
3565                                 actual_phy_idx = EXT_PHY2;
3566                         else if (phy_index == EXT_PHY2)
3567                                 actual_phy_idx = EXT_PHY1;
3568                 }
3569                 params->phy[actual_phy_idx].req_flow_ctrl =
3570                         params->req_flow_ctrl[link_cfg_idx];
3571
3572                 params->phy[actual_phy_idx].req_line_speed =
3573                         params->req_line_speed[link_cfg_idx];
3574
3575                 params->phy[actual_phy_idx].speed_cap_mask =
3576                         params->speed_cap_mask[link_cfg_idx];
3577
3578                 params->phy[actual_phy_idx].req_duplex =
3579                         params->req_duplex[link_cfg_idx];
3580
3581                 if (params->req_line_speed[link_cfg_idx] ==
3582                     SPEED_AUTO_NEG)
3583                         vars->link_status |= LINK_STATUS_AUTO_NEGOTIATE_ENABLED;
3584
3585                 DP(NETIF_MSG_LINK, "req_flow_ctrl %x, req_line_speed %x,"
3586                            " speed_cap_mask %x\n",
3587                            params->phy[actual_phy_idx].req_flow_ctrl,
3588                            params->phy[actual_phy_idx].req_line_speed,
3589                            params->phy[actual_phy_idx].speed_cap_mask);
3590         }
3591 }
3592
3593 static void bnx2x_ext_phy_set_pause(struct link_params *params,
3594                                     struct bnx2x_phy *phy,
3595                                     struct link_vars *vars)
3596 {
3597         u16 val;
3598         struct bnx2x *bp = params->bp;
3599         /* read modify write pause advertizing */
3600         bnx2x_cl45_read(bp, phy, MDIO_AN_DEVAD, MDIO_AN_REG_ADV_PAUSE, &val);
3601
3602         val &= ~MDIO_AN_REG_ADV_PAUSE_BOTH;
3603
3604         /* Please refer to Table 28B-3 of 802.3ab-1999 spec. */
3605         bnx2x_calc_ieee_aneg_adv(phy, params, &vars->ieee_fc);
3606         if ((vars->ieee_fc &
3607             MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_ASYMMETRIC) ==
3608             MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_ASYMMETRIC) {
3609                 val |= MDIO_AN_REG_ADV_PAUSE_ASYMMETRIC;
3610         }
3611         if ((vars->ieee_fc &
3612             MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_BOTH) ==
3613             MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_BOTH) {
3614                 val |= MDIO_AN_REG_ADV_PAUSE_PAUSE;
3615         }
3616         DP(NETIF_MSG_LINK, "Ext phy AN advertize 0x%x\n", val);
3617         bnx2x_cl45_write(bp, phy, MDIO_AN_DEVAD, MDIO_AN_REG_ADV_PAUSE, val);
3618 }
3619
3620 static void bnx2x_pause_resolve(struct link_vars *vars, u32 pause_result)
3621 {                                               /*  LD      LP   */
3622         switch (pause_result) {                 /* ASYM P ASYM P */
3623         case 0xb:                               /*   1  0   1  1 */
3624                 vars->flow_ctrl = BNX2X_FLOW_CTRL_TX;
3625                 break;
3626
3627         case 0xe:                               /*   1  1   1  0 */
3628                 vars->flow_ctrl = BNX2X_FLOW_CTRL_RX;
3629                 break;
3630
3631         case 0x5:                               /*   0  1   0  1 */
3632         case 0x7:                               /*   0  1   1  1 */
3633         case 0xd:                               /*   1  1   0  1 */
3634         case 0xf:                               /*   1  1   1  1 */
3635                 vars->flow_ctrl = BNX2X_FLOW_CTRL_BOTH;
3636                 break;
3637
3638         default:
3639                 break;
3640         }
3641         if (pause_result & (1<<0))
3642                 vars->link_status |= LINK_STATUS_LINK_PARTNER_SYMMETRIC_PAUSE;
3643         if (pause_result & (1<<1))
3644                 vars->link_status |= LINK_STATUS_LINK_PARTNER_ASYMMETRIC_PAUSE;
3645 }
3646
3647 static void bnx2x_ext_phy_update_adv_fc(struct bnx2x_phy *phy,
3648                                         struct link_params *params,
3649                                         struct link_vars *vars)
3650 {
3651         u16 ld_pause;           /* local */
3652         u16 lp_pause;           /* link partner */
3653         u16 pause_result;
3654         struct bnx2x *bp = params->bp;
3655         if (phy->type == PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM54618SE) {
3656                 bnx2x_cl22_read(bp, phy, 0x4, &ld_pause);
3657                 bnx2x_cl22_read(bp, phy, 0x5, &lp_pause);
3658         } else {
3659                 bnx2x_cl45_read(bp, phy,
3660                                 MDIO_AN_DEVAD,
3661                                 MDIO_AN_REG_ADV_PAUSE, &ld_pause);
3662                 bnx2x_cl45_read(bp, phy,
3663                                 MDIO_AN_DEVAD,
3664                                 MDIO_AN_REG_LP_AUTO_NEG, &lp_pause);
3665         }
3666         pause_result = (ld_pause &
3667                         MDIO_AN_REG_ADV_PAUSE_MASK) >> 8;
3668         pause_result |= (lp_pause &
3669                          MDIO_AN_REG_ADV_PAUSE_MASK) >> 10;
3670         DP(NETIF_MSG_LINK, "Ext PHY pause result 0x%x\n", pause_result);
3671         bnx2x_pause_resolve(vars, pause_result);
3672
3673 }
3674 static u8 bnx2x_ext_phy_resolve_fc(struct bnx2x_phy *phy,
3675                                    struct link_params *params,
3676                                    struct link_vars *vars)
3677 {
3678         u8 ret = 0;
3679         vars->flow_ctrl = BNX2X_FLOW_CTRL_NONE;
3680         if (phy->req_flow_ctrl != BNX2X_FLOW_CTRL_AUTO) {
3681                 /* Update the advertised flow-controled of LD/LP in AN */
3682                 if (phy->req_line_speed == SPEED_AUTO_NEG)
3683                         bnx2x_ext_phy_update_adv_fc(phy, params, vars);
3684                 /* But set the flow-control result as the requested one */
3685                 vars->flow_ctrl = phy->req_flow_ctrl;
3686         } else if (phy->req_line_speed != SPEED_AUTO_NEG)
3687                 vars->flow_ctrl = params->req_fc_auto_adv;
3688         else if (vars->link_status & LINK_STATUS_AUTO_NEGOTIATE_COMPLETE) {
3689                 ret = 1;
3690                 bnx2x_ext_phy_update_adv_fc(phy, params, vars);
3691         }
3692         return ret;
3693 }
3694 /******************************************************************/
3695 /*                      Warpcore section                          */
3696 /******************************************************************/
3697 /* The init_internal_warpcore should mirror the xgxs,
3698  * i.e. reset the lane (if needed), set aer for the
3699  * init configuration, and set/clear SGMII flag. Internal
3700  * phy init is done purely in phy_init stage.
3701  */
3702 static void bnx2x_warpcore_enable_AN_KR(struct bnx2x_phy *phy,
3703                                         struct link_params *params,
3704                                         struct link_vars *vars) {
3705         u16 val16 = 0, lane, bam37 = 0;
3706         struct bnx2x *bp = params->bp;
3707         DP(NETIF_MSG_LINK, "Enable Auto Negotiation for KR\n");
3708
3709         /* Disable Autoneg: re-enable it after adv is done. */
3710         bnx2x_cl45_write(bp, phy, MDIO_AN_DEVAD,
3711                          MDIO_WC_REG_IEEE0BLK_MIICNTL, 0);
3712
3713         /* Check adding advertisement for 1G KX */
3714         if (((vars->line_speed == SPEED_AUTO_NEG) &&
3715              (phy->speed_cap_mask & PORT_HW_CFG_SPEED_CAPABILITY_D0_1G)) ||
3716             (vars->line_speed == SPEED_1000)) {
3717                 u16 sd_digital;
3718                 val16 |= (1<<5);
3719
3720                 /* Enable CL37 1G Parallel Detect */
3721                 bnx2x_cl45_read(bp, phy, MDIO_WC_DEVAD,
3722                         MDIO_WC_REG_SERDESDIGITAL_CONTROL1000X2, &sd_digital);
3723                 bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,
3724                          MDIO_WC_REG_SERDESDIGITAL_CONTROL1000X2,
3725                                  (sd_digital | 0x1));
3726
3727                 DP(NETIF_MSG_LINK, "Advertize 1G\n");
3728         }
3729         if (((vars->line_speed == SPEED_AUTO_NEG) &&
3730              (phy->speed_cap_mask & PORT_HW_CFG_SPEED_CAPABILITY_D0_10G)) ||
3731             (vars->line_speed ==  SPEED_10000)) {
3732                 /* Check adding advertisement for 10G KR */
3733                 val16 |= (1<<7);
3734                 /* Enable 10G Parallel Detect */
3735                 bnx2x_cl45_write(bp, phy, MDIO_AN_DEVAD,
3736                                 MDIO_WC_REG_PAR_DET_10G_CTRL, 1);
3737
3738                 DP(NETIF_MSG_LINK, "Advertize 10G\n");
3739         }
3740
3741         /* Set Transmit PMD settings */
3742         lane = bnx2x_get_warpcore_lane(phy, params);
3743         bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,
3744                       MDIO_WC_REG_TX0_TX_DRIVER + 0x10*lane,
3745                      ((0x02 << MDIO_WC_REG_TX0_TX_DRIVER_POST2_COEFF_OFFSET) |
3746                       (0x06 << MDIO_WC_REG_TX0_TX_DRIVER_IDRIVER_OFFSET) |
3747                       (0x09 << MDIO_WC_REG_TX0_TX_DRIVER_IPRE_DRIVER_OFFSET)));
3748         bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,
3749                          MDIO_WC_REG_CL72_USERB0_CL72_OS_DEF_CTRL,
3750                          0x03f0);
3751         bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,
3752                          MDIO_WC_REG_CL72_USERB0_CL72_2P5_DEF_CTRL,
3753                          0x03f0);
3754
3755         /* Advertised speeds */
3756         bnx2x_cl45_write(bp, phy, MDIO_AN_DEVAD,
3757                          MDIO_WC_REG_AN_IEEE1BLK_AN_ADVERTISEMENT1, val16);
3758
3759         /* Advertised and set FEC (Forward Error Correction) */
3760         bnx2x_cl45_write(bp, phy, MDIO_AN_DEVAD,
3761                          MDIO_WC_REG_AN_IEEE1BLK_AN_ADVERTISEMENT2,
3762                          (MDIO_WC_REG_AN_IEEE1BLK_AN_ADV2_FEC_ABILITY |
3763                           MDIO_WC_REG_AN_IEEE1BLK_AN_ADV2_FEC_REQ));
3764
3765         /* Enable CL37 BAM */
3766         if (REG_RD(bp, params->shmem_base +
3767                    offsetof(struct shmem_region, dev_info.
3768                             port_hw_config[params->port].default_cfg)) &
3769             PORT_HW_CFG_ENABLE_BAM_ON_KR_ENABLED) {
3770                 bnx2x_cl45_read(bp, phy, MDIO_WC_DEVAD,
3771                                 MDIO_WC_REG_DIGITAL6_MP5_NEXTPAGECTRL, &bam37);
3772                 bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,
3773                         MDIO_WC_REG_DIGITAL6_MP5_NEXTPAGECTRL, bam37 | 1);
3774                 DP(NETIF_MSG_LINK, "Enable CL37 BAM on KR\n");
3775         }
3776
3777         /* Advertise pause */
3778         bnx2x_ext_phy_set_pause(params, phy, vars);
3779
3780         /*
3781          * Set KR Autoneg Work-Around flag for Warpcore version older than D108
3782          */
3783         bnx2x_cl45_read(bp, phy, MDIO_WC_DEVAD,
3784                         MDIO_WC_REG_UC_INFO_B1_VERSION, &val16);
3785         if (val16 < 0xd108) {
3786                 DP(NETIF_MSG_LINK, "Enable AN KR work-around\n");
3787                 vars->rx_tx_asic_rst = MAX_KR_LINK_RETRY;
3788         }
3789
3790         bnx2x_cl45_read(bp, phy, MDIO_WC_DEVAD,
3791                         MDIO_WC_REG_DIGITAL5_MISC7, &val16);
3792
3793         bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,
3794                          MDIO_WC_REG_DIGITAL5_MISC7, val16 | 0x100);
3795
3796         /* Over 1G - AN local device user page 1 */
3797         bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,
3798                         MDIO_WC_REG_DIGITAL3_UP1, 0x1f);
3799
3800         /* Enable Autoneg */
3801         bnx2x_cl45_write(bp, phy, MDIO_AN_DEVAD,
3802                          MDIO_WC_REG_IEEE0BLK_MIICNTL, 0x1200);
3803
3804 }
3805
3806 static void bnx2x_warpcore_set_10G_KR(struct bnx2x_phy *phy,
3807                                       struct link_params *params,
3808                                       struct link_vars *vars)
3809 {
3810         struct bnx2x *bp = params->bp;
3811         u16 val;
3812
3813         /* Disable Autoneg */
3814         bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,
3815                          MDIO_WC_REG_SERDESDIGITAL_CONTROL1000X2, 0x7);
3816
3817         bnx2x_cl45_write(bp, phy, MDIO_AN_DEVAD,
3818                          MDIO_WC_REG_PAR_DET_10G_CTRL, 0);
3819
3820         bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,
3821                          MDIO_WC_REG_CL72_USERB0_CL72_MISC1_CONTROL, 0x3f00);
3822
3823         bnx2x_cl45_write(bp, phy, MDIO_AN_DEVAD,
3824                          MDIO_WC_REG_AN_IEEE1BLK_AN_ADVERTISEMENT1, 0);
3825
3826         bnx2x_cl45_write(bp, phy, MDIO_AN_DEVAD,
3827                          MDIO_WC_REG_IEEE0BLK_MIICNTL, 0x0);
3828
3829         bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,
3830                         MDIO_WC_REG_DIGITAL3_UP1, 0x1);
3831
3832         bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,
3833                          MDIO_WC_REG_DIGITAL5_MISC7, 0xa);
3834
3835         /* Disable CL36 PCS Tx */
3836         bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,
3837                         MDIO_WC_REG_XGXSBLK1_LANECTRL0, 0x0);
3838
3839         /* Double Wide Single Data Rate @ pll rate */
3840         bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,
3841                         MDIO_WC_REG_XGXSBLK1_LANECTRL1, 0xFFFF);
3842
3843         /* Leave cl72 training enable, needed for KR */
3844         bnx2x_cl45_write(bp, phy, MDIO_PMA_DEVAD,
3845                 MDIO_WC_REG_PMD_IEEE9BLK_TENGBASE_KR_PMD_CONTROL_REGISTER_150,
3846                 0x2);
3847
3848         /* Leave CL72 enabled */
3849         bnx2x_cl45_read(bp, phy, MDIO_WC_DEVAD,
3850                          MDIO_WC_REG_CL72_USERB0_CL72_MISC1_CONTROL,
3851                          &val);
3852         bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,
3853                          MDIO_WC_REG_CL72_USERB0_CL72_MISC1_CONTROL,
3854                          val | 0x3800);
3855
3856         /* Set speed via PMA/PMD register */
3857         bnx2x_cl45_write(bp, phy, MDIO_PMA_DEVAD,
3858                          MDIO_WC_REG_IEEE0BLK_MIICNTL, 0x2040);
3859
3860         bnx2x_cl45_write(bp, phy, MDIO_PMA_DEVAD,
3861                          MDIO_WC_REG_IEEE0BLK_AUTONEGNP, 0xB);
3862
3863         /*Enable encoded forced speed */
3864         bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,
3865                          MDIO_WC_REG_SERDESDIGITAL_MISC2, 0x30);
3866
3867         /* Turn TX scramble payload only the 64/66 scrambler */
3868         bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,
3869                          MDIO_WC_REG_TX66_CONTROL, 0x9);
3870
3871         /* Turn RX scramble payload only the 64/66 scrambler */
3872         bnx2x_cl45_read_or_write(bp, phy, MDIO_WC_DEVAD,
3873                                  MDIO_WC_REG_RX66_CONTROL, 0xF9);
3874
3875         /* set and clear loopback to cause a reset to 64/66 decoder */
3876         bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,
3877                          MDIO_WC_REG_IEEE0BLK_MIICNTL, 0x4000);
3878         bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,
3879                          MDIO_WC_REG_IEEE0BLK_MIICNTL, 0x0);
3880
3881 }
3882
3883 static void bnx2x_warpcore_set_10G_XFI(struct bnx2x_phy *phy,
3884                                        struct link_params *params,
3885                                        u8 is_xfi)
3886 {
3887         struct bnx2x *bp = params->bp;
3888         u16 misc1_val, tap_val, tx_driver_val, lane, val;
3889         /* Hold rxSeqStart */
3890         bnx2x_cl45_read(bp, phy, MDIO_WC_DEVAD,
3891                         MDIO_WC_REG_DSC2B0_DSC_MISC_CTRL0, &val);
3892         bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,
3893                          MDIO_WC_REG_DSC2B0_DSC_MISC_CTRL0, (val | 0x8000));
3894
3895         /* Hold tx_fifo_reset */
3896         bnx2x_cl45_read(bp, phy, MDIO_WC_DEVAD,
3897                         MDIO_WC_REG_SERDESDIGITAL_CONTROL1000X3, &val);
3898         bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,
3899                          MDIO_WC_REG_SERDESDIGITAL_CONTROL1000X3, (val | 0x1));
3900
3901         /* Disable CL73 AN */
3902         bnx2x_cl45_write(bp, phy, MDIO_AN_DEVAD, MDIO_AN_REG_CTRL, 0);
3903
3904         /* Disable 100FX Enable and Auto-Detect */
3905         bnx2x_cl45_read(bp, phy, MDIO_WC_DEVAD,
3906                         MDIO_WC_REG_FX100_CTRL1, &val);
3907         bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,
3908                          MDIO_WC_REG_FX100_CTRL1, (val & 0xFFFA));
3909
3910         /* Disable 100FX Idle detect */
3911         bnx2x_cl45_read(bp, phy, MDIO_WC_DEVAD,
3912                         MDIO_WC_REG_FX100_CTRL3, &val);
3913         bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,
3914                          MDIO_WC_REG_FX100_CTRL3, (val | 0x0080));
3915
3916         /* Set Block address to Remote PHY & Clear forced_speed[5] */
3917         bnx2x_cl45_read(bp, phy, MDIO_WC_DEVAD,
3918                         MDIO_WC_REG_DIGITAL4_MISC3, &val);
3919         bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,
3920                          MDIO_WC_REG_DIGITAL4_MISC3, (val & 0xFF7F));
3921
3922         /* Turn off auto-detect & fiber mode */
3923         bnx2x_cl45_read(bp, phy, MDIO_WC_DEVAD,
3924                         MDIO_WC_REG_SERDESDIGITAL_CONTROL1000X1, &val);
3925         bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,
3926                          MDIO_WC_REG_SERDESDIGITAL_CONTROL1000X1,
3927                          (val & 0xFFEE));
3928
3929         /* Set filter_force_link, disable_false_link and parallel_detect */
3930         bnx2x_cl45_read(bp, phy, MDIO_WC_DEVAD,
3931                         MDIO_WC_REG_SERDESDIGITAL_CONTROL1000X2, &val);
3932         bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,
3933                          MDIO_WC_REG_SERDESDIGITAL_CONTROL1000X2,
3934                          ((val | 0x0006) & 0xFFFE));
3935
3936         /* Set XFI / SFI */
3937         bnx2x_cl45_read(bp, phy, MDIO_WC_DEVAD,
3938                         MDIO_WC_REG_SERDESDIGITAL_MISC1, &misc1_val);
3939
3940         misc1_val &= ~(0x1f);
3941
3942         if (is_xfi) {
3943                 misc1_val |= 0x5;
3944                 tap_val = ((0x08 << MDIO_WC_REG_TX_FIR_TAP_POST_TAP_OFFSET) |
3945                            (0x37 << MDIO_WC_REG_TX_FIR_TAP_MAIN_TAP_OFFSET) |
3946                            (0x00 << MDIO_WC_REG_TX_FIR_TAP_PRE_TAP_OFFSET));
3947                 tx_driver_val =
3948                       ((0x00 << MDIO_WC_REG_TX0_TX_DRIVER_POST2_COEFF_OFFSET) |
3949                        (0x02 << MDIO_WC_REG_TX0_TX_DRIVER_IDRIVER_OFFSET) |
3950                        (0x03 << MDIO_WC_REG_TX0_TX_DRIVER_IPRE_DRIVER_OFFSET));
3951
3952         } else {
3953                 misc1_val |= 0x9;
3954                 tap_val = ((0x12 << MDIO_WC_REG_TX_FIR_TAP_POST_TAP_OFFSET) |
3955                            (0x2d << MDIO_WC_REG_TX_FIR_TAP_MAIN_TAP_OFFSET) |
3956                            (0x00 << MDIO_WC_REG_TX_FIR_TAP_PRE_TAP_OFFSET));
3957                 tx_driver_val =
3958                       ((0x02 << MDIO_WC_REG_TX0_TX_DRIVER_POST2_COEFF_OFFSET) |
3959                        (0x02 << MDIO_WC_REG_TX0_TX_DRIVER_IDRIVER_OFFSET) |
3960                        (0x02 << MDIO_WC_REG_TX0_TX_DRIVER_IPRE_DRIVER_OFFSET));
3961         }
3962         bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,
3963                          MDIO_WC_REG_SERDESDIGITAL_MISC1, misc1_val);
3964
3965         /* Set Transmit PMD settings */
3966         lane = bnx2x_get_warpcore_lane(phy, params);
3967         bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,
3968                          MDIO_WC_REG_TX_FIR_TAP,
3969                          tap_val | MDIO_WC_REG_TX_FIR_TAP_ENABLE);
3970         bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,
3971                          MDIO_WC_REG_TX0_TX_DRIVER + 0x10*lane,
3972                          tx_driver_val);
3973
3974         /* Enable fiber mode, enable and invert sig_det */
3975         bnx2x_cl45_read(bp, phy, MDIO_WC_DEVAD,
3976                         MDIO_WC_REG_SERDESDIGITAL_CONTROL1000X1, &val);
3977         bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,
3978                          MDIO_WC_REG_SERDESDIGITAL_CONTROL1000X1, val | 0xd);
3979
3980         /* Set Block address to Remote PHY & Set forced_speed[5], 40bit mode */
3981         bnx2x_cl45_read(bp, phy, MDIO_WC_DEVAD,
3982                         MDIO_WC_REG_DIGITAL4_MISC3, &val);
3983         bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,
3984                          MDIO_WC_REG_DIGITAL4_MISC3, val | 0x8080);
3985
3986         /* 10G XFI Full Duplex */
3987         bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,
3988                          MDIO_WC_REG_IEEE0BLK_MIICNTL, 0x100);
3989
3990         /* Release tx_fifo_reset */
3991         bnx2x_cl45_read(bp, phy, MDIO_WC_DEVAD,
3992                         MDIO_WC_REG_SERDESDIGITAL_CONTROL1000X3, &val);
3993         bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,
3994                          MDIO_WC_REG_SERDESDIGITAL_CONTROL1000X3, val & 0xFFFE);
3995
3996         /* Release rxSeqStart */
3997         bnx2x_cl45_read(bp, phy, MDIO_WC_DEVAD,
3998                         MDIO_WC_REG_DSC2B0_DSC_MISC_CTRL0, &val);
3999         bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,
4000                          MDIO_WC_REG_DSC2B0_DSC_MISC_CTRL0, (val & 0x7FFF));
4001 }
4002
4003 static void bnx2x_warpcore_set_20G_KR2(struct bnx2x *bp,
4004                                        struct bnx2x_phy *phy)
4005 {
4006         DP(NETIF_MSG_LINK, "KR2 still not supported !!!\n");
4007 }
4008
4009 static void bnx2x_warpcore_set_20G_DXGXS(struct bnx2x *bp,
4010                                          struct bnx2x_phy *phy,
4011                                          u16 lane)
4012 {
4013         /* Rx0 anaRxControl1G */
4014         bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,
4015                          MDIO_WC_REG_RX0_ANARXCONTROL1G, 0x90);
4016
4017         /* Rx2 anaRxControl1G */
4018         bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,
4019                          MDIO_WC_REG_RX2_ANARXCONTROL1G, 0x90);
4020
4021         bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,
4022                          MDIO_WC_REG_RX66_SCW0, 0xE070);
4023
4024         bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,
4025                          MDIO_WC_REG_RX66_SCW1, 0xC0D0);
4026
4027         bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,
4028                          MDIO_WC_REG_RX66_SCW2, 0xA0B0);
4029
4030         bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,
4031                          MDIO_WC_REG_RX66_SCW3, 0x8090);
4032
4033         bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,
4034                          MDIO_WC_REG_RX66_SCW0_MASK, 0xF0F0);
4035
4036         bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,
4037                          MDIO_WC_REG_RX66_SCW1_MASK, 0xF0F0);
4038
4039         bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,
4040                          MDIO_WC_REG_RX66_SCW2_MASK, 0xF0F0);
4041
4042         bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,
4043                          MDIO_WC_REG_RX66_SCW3_MASK, 0xF0F0);
4044
4045         /* Serdes Digital Misc1 */
4046         bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,
4047                          MDIO_WC_REG_SERDESDIGITAL_MISC1, 0x6008);
4048
4049         /* Serdes Digital4 Misc3 */
4050         bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,
4051                          MDIO_WC_REG_DIGITAL4_MISC3, 0x8088);
4052
4053         /* Set Transmit PMD settings */
4054         bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,
4055                          MDIO_WC_REG_TX_FIR_TAP,
4056                         ((0x12 << MDIO_WC_REG_TX_FIR_TAP_POST_TAP_OFFSET) |
4057                          (0x2d << MDIO_WC_REG_TX_FIR_TAP_MAIN_TAP_OFFSET) |
4058                          (0x00 << MDIO_WC_REG_TX_FIR_TAP_PRE_TAP_OFFSET) |
4059                          MDIO_WC_REG_TX_FIR_TAP_ENABLE));
4060         bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,
4061                       MDIO_WC_REG_TX0_TX_DRIVER + 0x10*lane,
4062                      ((0x02 << MDIO_WC_REG_TX0_TX_DRIVER_POST2_COEFF_OFFSET) |
4063                       (0x02 << MDIO_WC_REG_TX0_TX_DRIVER_IDRIVER_OFFSET) |
4064                       (0x02 << MDIO_WC_REG_TX0_TX_DRIVER_IPRE_DRIVER_OFFSET)));
4065 }
4066
4067 static void bnx2x_warpcore_set_sgmii_speed(struct bnx2x_phy *phy,
4068                                            struct link_params *params,
4069                                            u8 fiber_mode,
4070                                            u8 always_autoneg)
4071 {
4072         struct bnx2x *bp = params->bp;
4073         u16 val16, digctrl_kx1, digctrl_kx2;
4074
4075         /* Clear XFI clock comp in non-10G single lane mode. */
4076         bnx2x_cl45_read(bp, phy, MDIO_WC_DEVAD,
4077                         MDIO_WC_REG_RX66_CONTROL, &val16);
4078         bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,
4079                          MDIO_WC_REG_RX66_CONTROL, val16 & ~(3<<13));
4080
4081         if (always_autoneg || phy->req_line_speed == SPEED_AUTO_NEG) {
4082                 /* SGMII Autoneg */
4083                 bnx2x_cl45_read(bp, phy, MDIO_WC_DEVAD,
4084                                 MDIO_WC_REG_COMBO_IEEE0_MIICTRL, &val16);
4085                 bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,
4086                                  MDIO_WC_REG_COMBO_IEEE0_MIICTRL,
4087                                  val16 | 0x1000);
4088                 DP(NETIF_MSG_LINK, "set SGMII AUTONEG\n");
4089         } else {
4090                 bnx2x_cl45_read(bp, phy, MDIO_WC_DEVAD,
4091                                 MDIO_WC_REG_COMBO_IEEE0_MIICTRL, &val16);
4092                 val16 &= 0xcebf;
4093                 switch (phy->req_line_speed) {
4094                 case SPEED_10:
4095                         break;
4096                 case SPEED_100:
4097                         val16 |= 0x2000;
4098                         break;
4099                 case SPEED_1000:
4100                         val16 |= 0x0040;
4101                         break;
4102                 default:
4103                         DP(NETIF_MSG_LINK,
4104                            "Speed not supported: 0x%x\n", phy->req_line_speed);
4105                         return;
4106                 }
4107
4108                 if (phy->req_duplex == DUPLEX_FULL)
4109                         val16 |= 0x0100;
4110
4111                 bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,
4112                                 MDIO_WC_REG_COMBO_IEEE0_MIICTRL, val16);
4113
4114                 DP(NETIF_MSG_LINK, "set SGMII force speed %d\n",
4115                                phy->req_line_speed);
4116                 bnx2x_cl45_read(bp, phy, MDIO_WC_DEVAD,
4117                                 MDIO_WC_REG_COMBO_IEEE0_MIICTRL, &val16);
4118                 DP(NETIF_MSG_LINK, "  (readback) %x\n", val16);
4119         }
4120
4121         /* SGMII Slave mode and disable signal detect */
4122         bnx2x_cl45_read(bp, phy, MDIO_WC_DEVAD,
4123                         MDIO_WC_REG_SERDESDIGITAL_CONTROL1000X1, &digctrl_kx1);
4124         if (fiber_mode)
4125                 digctrl_kx1 = 1;
4126         else
4127                 digctrl_kx1 &= 0xff4a;
4128
4129         bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,
4130                         MDIO_WC_REG_SERDESDIGITAL_CONTROL1000X1,
4131                         digctrl_kx1);
4132
4133         /* Turn off parallel detect */
4134         bnx2x_cl45_read(bp, phy, MDIO_WC_DEVAD,
4135                         MDIO_WC_REG_SERDESDIGITAL_CONTROL1000X2, &digctrl_kx2);
4136         bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,
4137                         MDIO_WC_REG_SERDESDIGITAL_CONTROL1000X2,
4138                         (digctrl_kx2 & ~(1<<2)));
4139
4140         /* Re-enable parallel detect */
4141         bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,
4142                         MDIO_WC_REG_SERDESDIGITAL_CONTROL1000X2,
4143                         (digctrl_kx2 | (1<<2)));
4144
4145         /* Enable autodet */
4146         bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,
4147                         MDIO_WC_REG_SERDESDIGITAL_CONTROL1000X1,
4148                         (digctrl_kx1 | 0x10));
4149 }
4150
4151 static void bnx2x_warpcore_reset_lane(struct bnx2x *bp,
4152                                       struct bnx2x_phy *phy,
4153                                       u8 reset)
4154 {
4155         u16 val;
4156         /* Take lane out of reset after configuration is finished */
4157         bnx2x_cl45_read(bp, phy, MDIO_WC_DEVAD,
4158                         MDIO_WC_REG_DIGITAL5_MISC6, &val);
4159         if (reset)
4160                 val |= 0xC000;
4161         else
4162                 val &= 0x3FFF;
4163         bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,
4164                          MDIO_WC_REG_DIGITAL5_MISC6, val);
4165         bnx2x_cl45_read(bp, phy, MDIO_WC_DEVAD,
4166                          MDIO_WC_REG_DIGITAL5_MISC6, &val);
4167 }
4168 /* Clear SFI/XFI link settings registers */
4169 static void bnx2x_warpcore_clear_regs(struct bnx2x_phy *phy,
4170                                       struct link_params *params,
4171                                       u16 lane)
4172 {
4173         struct bnx2x *bp = params->bp;
4174         u16 val16;
4175
4176         /* Set XFI clock comp as default. */
4177         bnx2x_cl45_read(bp, phy, MDIO_WC_DEVAD,
4178                         MDIO_WC_REG_RX66_CONTROL, &val16);
4179         bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,
4180                          MDIO_WC_REG_RX66_CONTROL, val16 | (3<<13));
4181
4182         bnx2x_warpcore_reset_lane(bp, phy, 1);
4183         bnx2x_cl45_write(bp, phy, MDIO_AN_DEVAD, MDIO_AN_REG_CTRL, 0);
4184         bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,
4185                          MDIO_WC_REG_FX100_CTRL1, 0x014a);
4186         bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,
4187                          MDIO_WC_REG_FX100_CTRL3, 0x0800);
4188         bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,
4189                          MDIO_WC_REG_DIGITAL4_MISC3, 0x8008);
4190         bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,
4191                          MDIO_WC_REG_SERDESDIGITAL_CONTROL1000X1, 0x0195);
4192         bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,
4193                          MDIO_WC_REG_SERDESDIGITAL_CONTROL1000X2, 0x0007);
4194         bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,
4195                          MDIO_WC_REG_SERDESDIGITAL_CONTROL1000X3, 0x0002);
4196         bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,
4197                          MDIO_WC_REG_SERDESDIGITAL_MISC1, 0x6000);
4198         lane = bnx2x_get_warpcore_lane(phy, params);
4199         bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,
4200                          MDIO_WC_REG_TX_FIR_TAP, 0x0000);
4201         bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,
4202                          MDIO_WC_REG_TX0_TX_DRIVER + 0x10*lane, 0x0990);
4203         bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,
4204                          MDIO_WC_REG_IEEE0BLK_MIICNTL, 0x2040);
4205         bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,
4206                          MDIO_WC_REG_COMBO_IEEE0_MIICTRL, 0x0140);
4207         bnx2x_warpcore_reset_lane(bp, phy, 0);
4208 }
4209
4210 static int bnx2x_get_mod_abs_int_cfg(struct bnx2x *bp,
4211                                                 u32 chip_id,
4212                                                 u32 shmem_base, u8 port,
4213                                                 u8 *gpio_num, u8 *gpio_port)
4214 {
4215         u32 cfg_pin;
4216         *gpio_num = 0;
4217         *gpio_port = 0;
4218         if (CHIP_IS_E3(bp)) {
4219                 cfg_pin = (REG_RD(bp, shmem_base +
4220                                 offsetof(struct shmem_region,
4221                                 dev_info.port_hw_config[port].e3_sfp_ctrl)) &
4222                                 PORT_HW_CFG_E3_MOD_ABS_MASK) >>
4223                                 PORT_HW_CFG_E3_MOD_ABS_SHIFT;
4224
4225                 /*
4226                  * Should not happen. This function called upon interrupt
4227                  * triggered by GPIO ( since EPIO can only generate interrupts
4228                  * to MCP).
4229                  * So if this function was called and none of the GPIOs was set,
4230                  * it means the shit hit the fan.
4231                  */
4232                 if ((cfg_pin < PIN_CFG_GPIO0_P0) ||
4233                     (cfg_pin > PIN_CFG_GPIO3_P1)) {
4234                         DP(NETIF_MSG_LINK,
4235                            "ERROR: Invalid cfg pin %x for module detect indication\n",
4236                            cfg_pin);
4237                         return -EINVAL;
4238                 }
4239
4240                 *gpio_num = (cfg_pin - PIN_CFG_GPIO0_P0) & 0x3;
4241                 *gpio_port = (cfg_pin - PIN_CFG_GPIO0_P0) >> 2;
4242         } else {
4243                 *gpio_num = MISC_REGISTERS_GPIO_3;
4244                 *gpio_port = port;
4245         }
4246         DP(NETIF_MSG_LINK, "MOD_ABS int GPIO%d_P%d\n", *gpio_num, *gpio_port);
4247         return 0;
4248 }
4249
4250 static int bnx2x_is_sfp_module_plugged(struct bnx2x_phy *phy,
4251                                        struct link_params *params)
4252 {
4253         struct bnx2x *bp = params->bp;
4254         u8 gpio_num, gpio_port;
4255         u32 gpio_val;
4256         if (bnx2x_get_mod_abs_int_cfg(bp, params->chip_id,
4257                                       params->shmem_base, params->port,
4258                                       &gpio_num, &gpio_port) != 0)
4259                 return 0;
4260         gpio_val = bnx2x_get_gpio(bp, gpio_num, gpio_port);
4261
4262         /* Call the handling function in case module is detected */
4263         if (gpio_val == 0)
4264                 return 1;
4265         else
4266                 return 0;
4267 }
4268 static int bnx2x_warpcore_get_sigdet(struct bnx2x_phy *phy,
4269                                         struct link_params *params)
4270 {
4271         u16 gp2_status_reg0, lane;
4272         struct bnx2x *bp = params->bp;
4273
4274         lane = bnx2x_get_warpcore_lane(phy, params);
4275
4276         bnx2x_cl45_read(bp, phy, MDIO_WC_DEVAD, MDIO_WC_REG_GP2_STATUS_GP_2_0,
4277                                  &gp2_status_reg0);
4278
4279         return (gp2_status_reg0 >> (8+lane)) & 0x1;
4280 }
4281
4282 static void bnx2x_warpcore_config_runtime(struct bnx2x_phy *phy,
4283                                        struct link_params *params,
4284                                        struct link_vars *vars)
4285 {
4286         struct bnx2x *bp = params->bp;
4287         u32 serdes_net_if;
4288         u16 gp_status1 = 0, lnkup = 0, lnkup_kr = 0;
4289         u16 lane = bnx2x_get_warpcore_lane(phy, params);
4290
4291         vars->turn_to_run_wc_rt = vars->turn_to_run_wc_rt ? 0 : 1;
4292
4293         if (!vars->turn_to_run_wc_rt)
4294                 return;
4295
4296         /* return if there is no link partner */
4297         if (!(bnx2x_warpcore_get_sigdet(phy, params))) {
4298                 DP(NETIF_MSG_LINK, "bnx2x_warpcore_get_sigdet false\n");
4299                 return;
4300         }
4301
4302         if (vars->rx_tx_asic_rst) {
4303                 serdes_net_if = (REG_RD(bp, params->shmem_base +
4304                                 offsetof(struct shmem_region, dev_info.
4305                                 port_hw_config[params->port].default_cfg)) &
4306                                 PORT_HW_CFG_NET_SERDES_IF_MASK);
4307
4308                 switch (serdes_net_if) {
4309                 case PORT_HW_CFG_NET_SERDES_IF_KR:
4310                         /* Do we get link yet? */
4311                         bnx2x_cl45_read(bp, phy, MDIO_WC_DEVAD, 0x81d1,
4312                                                                 &gp_status1);
4313                         lnkup = (gp_status1 >> (8+lane)) & 0x1;/* 1G */
4314                                 /*10G KR*/
4315                         lnkup_kr = (gp_status1 >> (12+lane)) & 0x1;
4316
4317                         DP(NETIF_MSG_LINK,
4318                                 "gp_status1 0x%x\n", gp_status1);
4319
4320                         if (lnkup_kr || lnkup) {
4321                                         vars->rx_tx_asic_rst = 0;
4322                                         DP(NETIF_MSG_LINK,
4323                                         "link up, rx_tx_asic_rst 0x%x\n",
4324                                         vars->rx_tx_asic_rst);
4325                         } else {
4326                                 /*reset the lane to see if link comes up.*/
4327                                 bnx2x_warpcore_reset_lane(bp, phy, 1);
4328                                 bnx2x_warpcore_reset_lane(bp, phy, 0);
4329
4330                                 /* restart Autoneg */
4331                                 bnx2x_cl45_write(bp, phy, MDIO_AN_DEVAD,
4332                                         MDIO_WC_REG_IEEE0BLK_MIICNTL, 0x1200);
4333
4334                                 vars->rx_tx_asic_rst--;
4335                                 DP(NETIF_MSG_LINK, "0x%x retry left\n",
4336                                 vars->rx_tx_asic_rst);
4337                         }
4338                         break;
4339
4340                 default:
4341                         break;
4342                 }
4343
4344         } /*params->rx_tx_asic_rst*/
4345
4346 }
4347
4348 static void bnx2x_warpcore_config_init(struct bnx2x_phy *phy,
4349                                        struct link_params *params,
4350                                        struct link_vars *vars)
4351 {
4352         struct bnx2x *bp = params->bp;
4353         u32 serdes_net_if;
4354         u8 fiber_mode;
4355         u16 lane = bnx2x_get_warpcore_lane(phy, params);
4356         serdes_net_if = (REG_RD(bp, params->shmem_base +
4357                          offsetof(struct shmem_region, dev_info.
4358                                   port_hw_config[params->port].default_cfg)) &
4359                          PORT_HW_CFG_NET_SERDES_IF_MASK);
4360         DP(NETIF_MSG_LINK, "Begin Warpcore init, link_speed %d, "
4361                            "serdes_net_if = 0x%x\n",
4362                        vars->line_speed, serdes_net_if);
4363         bnx2x_set_aer_mmd(params, phy);
4364
4365         vars->phy_flags |= PHY_XGXS_FLAG;
4366         if ((serdes_net_if == PORT_HW_CFG_NET_SERDES_IF_SGMII) ||
4367             (phy->req_line_speed &&
4368              ((phy->req_line_speed == SPEED_100) ||
4369               (phy->req_line_speed == SPEED_10)))) {
4370                 vars->phy_flags |= PHY_SGMII_FLAG;
4371                 DP(NETIF_MSG_LINK, "Setting SGMII mode\n");
4372                 bnx2x_warpcore_clear_regs(phy, params, lane);
4373                 bnx2x_warpcore_set_sgmii_speed(phy, params, 0, 1);
4374         } else {
4375                 switch (serdes_net_if) {
4376                 case PORT_HW_CFG_NET_SERDES_IF_KR:
4377                         /* Enable KR Auto Neg */
4378                         if (params->loopback_mode == LOOPBACK_NONE)
4379                                 bnx2x_warpcore_enable_AN_KR(phy, params, vars);
4380                         else {
4381                                 DP(NETIF_MSG_LINK, "Setting KR 10G-Force\n");
4382                                 bnx2x_warpcore_set_10G_KR(phy, params, vars);
4383                         }
4384                         break;
4385
4386                 case PORT_HW_CFG_NET_SERDES_IF_XFI:
4387                         bnx2x_warpcore_clear_regs(phy, params, lane);
4388                         if (vars->line_speed == SPEED_10000) {
4389                                 DP(NETIF_MSG_LINK, "Setting 10G XFI\n");
4390                                 bnx2x_warpcore_set_10G_XFI(phy, params, 1);
4391                         } else {
4392                                 if (SINGLE_MEDIA_DIRECT(params)) {
4393                                         DP(NETIF_MSG_LINK, "1G Fiber\n");
4394                                         fiber_mode = 1;
4395                                 } else {
4396                                         DP(NETIF_MSG_LINK, "10/100/1G SGMII\n");
4397                                         fiber_mode = 0;
4398                                 }
4399                                 bnx2x_warpcore_set_sgmii_speed(phy,
4400                                                                 params,
4401                                                                 fiber_mode,
4402                                                                 0);
4403                         }
4404
4405                         break;
4406
4407                 case PORT_HW_CFG_NET_SERDES_IF_SFI:
4408
4409                         bnx2x_warpcore_clear_regs(phy, params, lane);
4410                         if (vars->line_speed == SPEED_10000) {
4411                                 DP(NETIF_MSG_LINK, "Setting 10G SFI\n");
4412                                 bnx2x_warpcore_set_10G_XFI(phy, params, 0);
4413                         } else if (vars->line_speed == SPEED_1000) {
4414                                 DP(NETIF_MSG_LINK, "Setting 1G Fiber\n");
4415                                 bnx2x_warpcore_set_sgmii_speed(
4416                                                 phy, params, 1, 0);
4417                         }
4418                         /* Issue Module detection */
4419                         if (bnx2x_is_sfp_module_plugged(phy, params))
4420                                 bnx2x_sfp_module_detection(phy, params);
4421                         break;
4422
4423                 case PORT_HW_CFG_NET_SERDES_IF_DXGXS:
4424                         if (vars->line_speed != SPEED_20000) {
4425                                 DP(NETIF_MSG_LINK, "Speed not supported yet\n");
4426                                 return;
4427                         }
4428                         DP(NETIF_MSG_LINK, "Setting 20G DXGXS\n");
4429                         bnx2x_warpcore_set_20G_DXGXS(bp, phy, lane);
4430                         /* Issue Module detection */
4431
4432                         bnx2x_sfp_module_detection(phy, params);
4433                         break;
4434
4435                 case PORT_HW_CFG_NET_SERDES_IF_KR2:
4436                         if (vars->line_speed != SPEED_20000) {
4437                                 DP(NETIF_MSG_LINK, "Speed not supported yet\n");
4438                                 return;
4439                         }
4440                         DP(NETIF_MSG_LINK, "Setting 20G KR2\n");
4441                         bnx2x_warpcore_set_20G_KR2(bp, phy);
4442                         break;
4443
4444                 default:
4445                         DP(NETIF_MSG_LINK,
4446                            "Unsupported Serdes Net Interface 0x%x\n",
4447                            serdes_net_if);
4448                         return;
4449                 }
4450         }
4451
4452         /* Take lane out of reset after configuration is finished */
4453         bnx2x_warpcore_reset_lane(bp, phy, 0);
4454         DP(NETIF_MSG_LINK, "Exit config init\n");
4455 }
4456
4457 static void bnx2x_sfp_e3_set_transmitter(struct link_params *params,
4458                                          struct bnx2x_phy *phy,
4459                                          u8 tx_en)
4460 {
4461         struct bnx2x *bp = params->bp;
4462         u32 cfg_pin;
4463         u8 port = params->port;
4464
4465         cfg_pin = REG_RD(bp, params->shmem_base +
4466                                 offsetof(struct shmem_region,
4467                                 dev_info.port_hw_config[port].e3_sfp_ctrl)) &
4468                                 PORT_HW_CFG_TX_LASER_MASK;
4469         /* Set the !tx_en since this pin is DISABLE_TX_LASER */
4470         DP(NETIF_MSG_LINK, "Setting WC TX to %d\n", tx_en);
4471         /* For 20G, the expected pin to be used is 3 pins after the current */
4472
4473         bnx2x_set_cfg_pin(bp, cfg_pin, tx_en ^ 1);
4474         if (phy->speed_cap_mask & PORT_HW_CFG_SPEED_CAPABILITY_D0_20G)
4475                 bnx2x_set_cfg_pin(bp, cfg_pin + 3, tx_en ^ 1);
4476 }
4477
4478 static void bnx2x_warpcore_link_reset(struct bnx2x_phy *phy,
4479                                       struct link_params *params)
4480 {
4481         struct bnx2x *bp = params->bp;
4482         u16 val16;
4483         bnx2x_sfp_e3_set_transmitter(params, phy, 0);
4484         bnx2x_set_mdio_clk(bp, params->chip_id, params->port);
4485         bnx2x_set_aer_mmd(params, phy);
4486         /* Global register */
4487         bnx2x_warpcore_reset_lane(bp, phy, 1);
4488
4489         /* Clear loopback settings (if any) */
4490         /* 10G & 20G */
4491         bnx2x_cl45_read(bp, phy, MDIO_WC_DEVAD,
4492                         MDIO_WC_REG_COMBO_IEEE0_MIICTRL, &val16);
4493         bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,
4494                          MDIO_WC_REG_COMBO_IEEE0_MIICTRL, val16 &
4495                          0xBFFF);
4496
4497         bnx2x_cl45_read(bp, phy, MDIO_WC_DEVAD,
4498                         MDIO_WC_REG_IEEE0BLK_MIICNTL, &val16);
4499         bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,
4500                         MDIO_WC_REG_IEEE0BLK_MIICNTL, val16 & 0xfffe);
4501
4502         /* Update those 1-copy registers */
4503         CL22_WR_OVER_CL45(bp, phy, MDIO_REG_BANK_AER_BLOCK,
4504                           MDIO_AER_BLOCK_AER_REG, 0);
4505                 /* Enable 1G MDIO (1-copy) */
4506         bnx2x_cl45_read(bp, phy, MDIO_WC_DEVAD,
4507                         MDIO_WC_REG_XGXSBLK0_XGXSCONTROL,
4508                         &val16);
4509         bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,
4510                          MDIO_WC_REG_XGXSBLK0_XGXSCONTROL,
4511                          val16 & ~0x10);
4512
4513         bnx2x_cl45_read(bp, phy, MDIO_WC_DEVAD,
4514                         MDIO_WC_REG_XGXSBLK1_LANECTRL2, &val16);
4515         bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,
4516                          MDIO_WC_REG_XGXSBLK1_LANECTRL2,
4517                          val16 & 0xff00);
4518
4519 }
4520
4521 static void bnx2x_set_warpcore_loopback(struct bnx2x_phy *phy,
4522                                         struct link_params *params)
4523 {
4524         struct bnx2x *bp = params->bp;
4525         u16 val16;
4526         u32 lane;
4527         DP(NETIF_MSG_LINK, "Setting Warpcore loopback type %x, speed %d\n",
4528                        params->loopback_mode, phy->req_line_speed);
4529
4530         if (phy->req_line_speed < SPEED_10000) {
4531                 /* 10/100/1000 */
4532
4533                 /* Update those 1-copy registers */
4534                 CL22_WR_OVER_CL45(bp, phy, MDIO_REG_BANK_AER_BLOCK,
4535                                   MDIO_AER_BLOCK_AER_REG, 0);
4536                 /* Enable 1G MDIO (1-copy) */
4537                 bnx2x_cl45_read(bp, phy, MDIO_WC_DEVAD,
4538                                 MDIO_WC_REG_XGXSBLK0_XGXSCONTROL,
4539                                 &val16);
4540                 bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,
4541                                 MDIO_WC_REG_XGXSBLK0_XGXSCONTROL,
4542                                 val16 | 0x10);
4543                 /* Set 1G loopback based on lane (1-copy) */
4544                 lane = bnx2x_get_warpcore_lane(phy, params);
4545                 bnx2x_cl45_read(bp, phy, MDIO_WC_DEVAD,
4546                                 MDIO_WC_REG_XGXSBLK1_LANECTRL2, &val16);
4547                 bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,
4548                                 MDIO_WC_REG_XGXSBLK1_LANECTRL2,
4549                                 val16 | (1<<lane));
4550
4551                 /* Switch back to 4-copy registers */
4552                 bnx2x_set_aer_mmd(params, phy);
4553         } else {
4554                 /* 10G & 20G */
4555                 bnx2x_cl45_read(bp, phy, MDIO_WC_DEVAD,
4556                                 MDIO_WC_REG_COMBO_IEEE0_MIICTRL, &val16);
4557                 bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,
4558                                 MDIO_WC_REG_COMBO_IEEE0_MIICTRL, val16 |
4559                                  0x4000);
4560
4561                 bnx2x_cl45_read(bp, phy, MDIO_WC_DEVAD,
4562                                 MDIO_WC_REG_IEEE0BLK_MIICNTL, &val16);
4563                 bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,
4564                                 MDIO_WC_REG_IEEE0BLK_MIICNTL, val16 | 0x1);
4565         }
4566 }
4567
4568
4569 void bnx2x_sync_link(struct link_params *params,
4570                            struct link_vars *vars)
4571 {
4572         struct bnx2x *bp = params->bp;
4573         u8 link_10g_plus;
4574         if (vars->link_status & LINK_STATUS_PHYSICAL_LINK_FLAG)
4575                 vars->phy_flags |= PHY_PHYSICAL_LINK_FLAG;
4576         vars->link_up = (vars->link_status & LINK_STATUS_LINK_UP);
4577         if (vars->link_up) {
4578                 DP(NETIF_MSG_LINK, "phy link up\n");
4579
4580                 vars->phy_link_up = 1;
4581                 vars->duplex = DUPLEX_FULL;
4582                 switch (vars->link_status &
4583                         LINK_STATUS_SPEED_AND_DUPLEX_MASK) {
4584                         case LINK_10THD:
4585                                 vars->duplex = DUPLEX_HALF;
4586                                 /* fall thru */
4587                         case LINK_10TFD:
4588                                 vars->line_speed = SPEED_10;
4589                                 break;
4590
4591                         case LINK_100TXHD:
4592                                 vars->duplex = DUPLEX_HALF;
4593                                 /* fall thru */
4594                         case LINK_100T4:
4595                         case LINK_100TXFD:
4596                                 vars->line_speed = SPEED_100;
4597                                 break;
4598
4599                         case LINK_1000THD:
4600                                 vars->duplex = DUPLEX_HALF;
4601                                 /* fall thru */
4602                         case LINK_1000TFD:
4603                                 vars->line_speed = SPEED_1000;
4604                                 break;
4605
4606                         case LINK_2500THD:
4607                                 vars->duplex = DUPLEX_HALF;
4608                                 /* fall thru */
4609                         case LINK_2500TFD:
4610                                 vars->line_speed = SPEED_2500;
4611                                 break;
4612
4613                         case LINK_10GTFD:
4614                                 vars->line_speed = SPEED_10000;
4615                                 break;
4616                         case LINK_20GTFD:
4617                                 vars->line_speed = SPEED_20000;
4618                                 break;
4619                         default:
4620                                 break;
4621                 }
4622                 vars->flow_ctrl = 0;
4623                 if (vars->link_status & LINK_STATUS_TX_FLOW_CONTROL_ENABLED)
4624                         vars->flow_ctrl |= BNX2X_FLOW_CTRL_TX;
4625
4626                 if (vars->link_status & LINK_STATUS_RX_FLOW_CONTROL_ENABLED)
4627                         vars->flow_ctrl |= BNX2X_FLOW_CTRL_RX;
4628
4629                 if (!vars->flow_ctrl)
4630                         vars->flow_ctrl = BNX2X_FLOW_CTRL_NONE;
4631
4632                 if (vars->line_speed &&
4633                     ((vars->line_speed == SPEED_10) ||
4634                      (vars->line_speed == SPEED_100))) {
4635                         vars->phy_flags |= PHY_SGMII_FLAG;
4636                 } else {
4637                         vars->phy_flags &= ~PHY_SGMII_FLAG;
4638                 }
4639                 if (vars->line_speed &&
4640                     USES_WARPCORE(bp) &&
4641                     (vars->line_speed == SPEED_1000))
4642                         vars->phy_flags |= PHY_SGMII_FLAG;
4643                 /* anything 10 and over uses the bmac */
4644                 link_10g_plus = (vars->line_speed >= SPEED_10000);
4645
4646                 if (link_10g_plus) {
4647                         if (USES_WARPCORE(bp))
4648                                 vars->mac_type = MAC_TYPE_XMAC;
4649                         else
4650                                 vars->mac_type = MAC_TYPE_BMAC;
4651                 } else {
4652                         if (USES_WARPCORE(bp))
4653                                 vars->mac_type = MAC_TYPE_UMAC;
4654                         else
4655                                 vars->mac_type = MAC_TYPE_EMAC;
4656                 }
4657         } else { /* link down */
4658                 DP(NETIF_MSG_LINK, "phy link down\n");
4659
4660                 vars->phy_link_up = 0;
4661
4662                 vars->line_speed = 0;
4663                 vars->duplex = DUPLEX_FULL;
4664                 vars->flow_ctrl = BNX2X_FLOW_CTRL_NONE;
4665
4666                 /* indicate no mac active */
4667                 vars->mac_type = MAC_TYPE_NONE;
4668                 if (vars->link_status & LINK_STATUS_PHYSICAL_LINK_FLAG)
4669                         vars->phy_flags |= PHY_HALF_OPEN_CONN_FLAG;
4670         }
4671 }
4672
4673 void bnx2x_link_status_update(struct link_params *params,
4674                               struct link_vars *vars)
4675 {
4676         struct bnx2x *bp = params->bp;
4677         u8 port = params->port;
4678         u32 sync_offset, media_types;
4679         /* Update PHY configuration */
4680         set_phy_vars(params, vars);
4681
4682         vars->link_status = REG_RD(bp, params->shmem_base +
4683                                    offsetof(struct shmem_region,
4684                                             port_mb[port].link_status));
4685
4686         vars->phy_flags = PHY_XGXS_FLAG;
4687         bnx2x_sync_link(params, vars);
4688         /* Sync media type */
4689         sync_offset = params->shmem_base +
4690                         offsetof(struct shmem_region,
4691                                  dev_info.port_hw_config[port].media_type);
4692         media_types = REG_RD(bp, sync_offset);
4693
4694         params->phy[INT_PHY].media_type =
4695                 (media_types & PORT_HW_CFG_MEDIA_TYPE_PHY0_MASK) >>
4696                 PORT_HW_CFG_MEDIA_TYPE_PHY0_SHIFT;
4697         params->phy[EXT_PHY1].media_type =
4698                 (media_types & PORT_HW_CFG_MEDIA_TYPE_PHY1_MASK) >>
4699                 PORT_HW_CFG_MEDIA_TYPE_PHY1_SHIFT;
4700         params->phy[EXT_PHY2].media_type =
4701                 (media_types & PORT_HW_CFG_MEDIA_TYPE_PHY2_MASK) >>
4702                 PORT_HW_CFG_MEDIA_TYPE_PHY2_SHIFT;
4703         DP(NETIF_MSG_LINK, "media_types = 0x%x\n", media_types);
4704
4705         /* Sync AEU offset */
4706         sync_offset = params->shmem_base +
4707                         offsetof(struct shmem_region,
4708                                  dev_info.port_hw_config[port].aeu_int_mask);
4709
4710         vars->aeu_int_mask = REG_RD(bp, sync_offset);
4711
4712         /* Sync PFC status */
4713         if (vars->link_status & LINK_STATUS_PFC_ENABLED)
4714                 params->feature_config_flags |=
4715                                         FEATURE_CONFIG_PFC_ENABLED;
4716         else
4717                 params->feature_config_flags &=
4718                                         ~FEATURE_CONFIG_PFC_ENABLED;
4719
4720         DP(NETIF_MSG_LINK, "link_status 0x%x  phy_link_up %x int_mask 0x%x\n",
4721                  vars->link_status, vars->phy_link_up, vars->aeu_int_mask);
4722         DP(NETIF_MSG_LINK, "line_speed %x  duplex %x  flow_ctrl 0x%x\n",
4723                  vars->line_speed, vars->duplex, vars->flow_ctrl);
4724 }
4725
4726 static void bnx2x_set_master_ln(struct link_params *params,
4727                                 struct bnx2x_phy *phy)
4728 {
4729         struct bnx2x *bp = params->bp;
4730         u16 new_master_ln, ser_lane;
4731         ser_lane = ((params->lane_config &
4732                      PORT_HW_CFG_LANE_SWAP_CFG_MASTER_MASK) >>
4733                     PORT_HW_CFG_LANE_SWAP_CFG_MASTER_SHIFT);
4734
4735         /* set the master_ln for AN */
4736         CL22_RD_OVER_CL45(bp, phy,
4737                           MDIO_REG_BANK_XGXS_BLOCK2,
4738                           MDIO_XGXS_BLOCK2_TEST_MODE_LANE,
4739                           &new_master_ln);
4740
4741         CL22_WR_OVER_CL45(bp, phy,
4742                           MDIO_REG_BANK_XGXS_BLOCK2 ,
4743                           MDIO_XGXS_BLOCK2_TEST_MODE_LANE,
4744                           (new_master_ln | ser_lane));
4745 }
4746
4747 static int bnx2x_reset_unicore(struct link_params *params,
4748                                struct bnx2x_phy *phy,
4749                                u8 set_serdes)
4750 {
4751         struct bnx2x *bp = params->bp;
4752         u16 mii_control;
4753         u16 i;
4754         CL22_RD_OVER_CL45(bp, phy,
4755                           MDIO_REG_BANK_COMBO_IEEE0,
4756                           MDIO_COMBO_IEEE0_MII_CONTROL, &mii_control);
4757
4758         /* reset the unicore */
4759         CL22_WR_OVER_CL45(bp, phy,
4760                           MDIO_REG_BANK_COMBO_IEEE0,
4761                           MDIO_COMBO_IEEE0_MII_CONTROL,
4762                           (mii_control |
4763                            MDIO_COMBO_IEEO_MII_CONTROL_RESET));
4764         if (set_serdes)
4765                 bnx2x_set_serdes_access(bp, params->port);
4766
4767         /* wait for the reset to self clear */
4768         for (i = 0; i < MDIO_ACCESS_TIMEOUT; i++) {
4769                 udelay(5);
4770
4771                 /* the reset erased the previous bank value */
4772                 CL22_RD_OVER_CL45(bp, phy,
4773                                   MDIO_REG_BANK_COMBO_IEEE0,
4774                                   MDIO_COMBO_IEEE0_MII_CONTROL,
4775                                   &mii_control);
4776
4777                 if (!(mii_control & MDIO_COMBO_IEEO_MII_CONTROL_RESET)) {
4778                         udelay(5);
4779                         return 0;
4780                 }
4781         }
4782
4783         netdev_err(bp->dev,  "Warning: PHY was not initialized,"
4784                               " Port %d\n",
4785                          params->port);
4786         DP(NETIF_MSG_LINK, "BUG! XGXS is still in reset!\n");
4787         return -EINVAL;
4788
4789 }
4790
4791 static void bnx2x_set_swap_lanes(struct link_params *params,
4792                                  struct bnx2x_phy *phy)
4793 {
4794         struct bnx2x *bp = params->bp;
4795         /*
4796          *  Each two bits represents a lane number:
4797          *  No swap is 0123 => 0x1b no need to enable the swap
4798          */
4799         u16 rx_lane_swap, tx_lane_swap;
4800
4801         rx_lane_swap = ((params->lane_config &
4802                          PORT_HW_CFG_LANE_SWAP_CFG_RX_MASK) >>
4803                         PORT_HW_CFG_LANE_SWAP_CFG_RX_SHIFT);
4804         tx_lane_swap = ((params->lane_config &
4805                          PORT_HW_CFG_LANE_SWAP_CFG_TX_MASK) >>
4806                         PORT_HW_CFG_LANE_SWAP_CFG_TX_SHIFT);
4807
4808         if (rx_lane_swap != 0x1b) {
4809                 CL22_WR_OVER_CL45(bp, phy,
4810                                   MDIO_REG_BANK_XGXS_BLOCK2,
4811                                   MDIO_XGXS_BLOCK2_RX_LN_SWAP,
4812                                   (rx_lane_swap |
4813                                    MDIO_XGXS_BLOCK2_RX_LN_SWAP_ENABLE |
4814                                    MDIO_XGXS_BLOCK2_RX_LN_SWAP_FORCE_ENABLE));
4815         } else {
4816                 CL22_WR_OVER_CL45(bp, phy,
4817                                   MDIO_REG_BANK_XGXS_BLOCK2,
4818                                   MDIO_XGXS_BLOCK2_RX_LN_SWAP, 0);
4819         }
4820
4821         if (tx_lane_swap != 0x1b) {
4822                 CL22_WR_OVER_CL45(bp, phy,
4823                                   MDIO_REG_BANK_XGXS_BLOCK2,
4824                                   MDIO_XGXS_BLOCK2_TX_LN_SWAP,
4825                                   (tx_lane_swap |
4826                                    MDIO_XGXS_BLOCK2_TX_LN_SWAP_ENABLE));
4827         } else {
4828                 CL22_WR_OVER_CL45(bp, phy,
4829                                   MDIO_REG_BANK_XGXS_BLOCK2,
4830                                   MDIO_XGXS_BLOCK2_TX_LN_SWAP, 0);
4831         }
4832 }
4833
4834 static void bnx2x_set_parallel_detection(struct bnx2x_phy *phy,
4835                                          struct link_params *params)
4836 {
4837         struct bnx2x *bp = params->bp;
4838         u16 control2;
4839         CL22_RD_OVER_CL45(bp, phy,
4840                           MDIO_REG_BANK_SERDES_DIGITAL,
4841                           MDIO_SERDES_DIGITAL_A_1000X_CONTROL2,
4842                           &control2);
4843         if (phy->speed_cap_mask & PORT_HW_CFG_SPEED_CAPABILITY_D0_1G)
4844                 control2 |= MDIO_SERDES_DIGITAL_A_1000X_CONTROL2_PRL_DT_EN;
4845         else
4846                 control2 &= ~MDIO_SERDES_DIGITAL_A_1000X_CONTROL2_PRL_DT_EN;
4847         DP(NETIF_MSG_LINK, "phy->speed_cap_mask = 0x%x, control2 = 0x%x\n",
4848                 phy->speed_cap_mask, control2);
4849         CL22_WR_OVER_CL45(bp, phy,
4850                           MDIO_REG_BANK_SERDES_DIGITAL,
4851                           MDIO_SERDES_DIGITAL_A_1000X_CONTROL2,
4852                           control2);
4853
4854         if ((phy->type == PORT_HW_CFG_XGXS_EXT_PHY_TYPE_DIRECT) &&
4855              (phy->speed_cap_mask &
4856                     PORT_HW_CFG_SPEED_CAPABILITY_D0_10G)) {
4857                 DP(NETIF_MSG_LINK, "XGXS\n");
4858
4859                 CL22_WR_OVER_CL45(bp, phy,
4860                                  MDIO_REG_BANK_10G_PARALLEL_DETECT,
4861                                  MDIO_10G_PARALLEL_DETECT_PAR_DET_10G_LINK,
4862                                  MDIO_10G_PARALLEL_DETECT_PAR_DET_10G_LINK_CNT);
4863
4864                 CL22_RD_OVER_CL45(bp, phy,
4865                                   MDIO_REG_BANK_10G_PARALLEL_DETECT,
4866                                   MDIO_10G_PARALLEL_DETECT_PAR_DET_10G_CONTROL,
4867                                   &control2);
4868
4869
4870                 control2 |=
4871                     MDIO_10G_PARALLEL_DETECT_PAR_DET_10G_CONTROL_PARDET10G_EN;
4872
4873                 CL22_WR_OVER_CL45(bp, phy,
4874                                   MDIO_REG_BANK_10G_PARALLEL_DETECT,
4875                                   MDIO_10G_PARALLEL_DETECT_PAR_DET_10G_CONTROL,
4876                                   control2);
4877
4878                 /* Disable parallel detection of HiG */
4879                 CL22_WR_OVER_CL45(bp, phy,
4880                                   MDIO_REG_BANK_XGXS_BLOCK2,
4881                                   MDIO_XGXS_BLOCK2_UNICORE_MODE_10G,
4882                                   MDIO_XGXS_BLOCK2_UNICORE_MODE_10G_CX4_XGXS |
4883                                   MDIO_XGXS_BLOCK2_UNICORE_MODE_10G_HIGIG_XGXS);
4884         }
4885 }
4886
4887 static void bnx2x_set_autoneg(struct bnx2x_phy *phy,
4888                               struct link_params *params,
4889                               struct link_vars *vars,
4890                               u8 enable_cl73)
4891 {
4892         struct bnx2x *bp = params->bp;
4893         u16 reg_val;
4894
4895         /* CL37 Autoneg */
4896         CL22_RD_OVER_CL45(bp, phy,
4897                           MDIO_REG_BANK_COMBO_IEEE0,
4898                           MDIO_COMBO_IEEE0_MII_CONTROL, &reg_val);
4899
4900         /* CL37 Autoneg Enabled */
4901         if (vars->line_speed == SPEED_AUTO_NEG)
4902                 reg_val |= MDIO_COMBO_IEEO_MII_CONTROL_AN_EN;
4903         else /* CL37 Autoneg Disabled */
4904                 reg_val &= ~(MDIO_COMBO_IEEO_MII_CONTROL_AN_EN |
4905                              MDIO_COMBO_IEEO_MII_CONTROL_RESTART_AN);
4906
4907         CL22_WR_OVER_CL45(bp, phy,
4908                           MDIO_REG_BANK_COMBO_IEEE0,
4909                           MDIO_COMBO_IEEE0_MII_CONTROL, reg_val);
4910
4911         /* Enable/Disable Autodetection */
4912
4913         CL22_RD_OVER_CL45(bp, phy,
4914                           MDIO_REG_BANK_SERDES_DIGITAL,
4915                           MDIO_SERDES_DIGITAL_A_1000X_CONTROL1, &reg_val);
4916         reg_val &= ~(MDIO_SERDES_DIGITAL_A_1000X_CONTROL1_SIGNAL_DETECT_EN |
4917                     MDIO_SERDES_DIGITAL_A_1000X_CONTROL1_INVERT_SIGNAL_DETECT);
4918         reg_val |= MDIO_SERDES_DIGITAL_A_1000X_CONTROL1_FIBER_MODE;
4919         if (vars->line_speed == SPEED_AUTO_NEG)
4920                 reg_val |= MDIO_SERDES_DIGITAL_A_1000X_CONTROL1_AUTODET;
4921         else
4922                 reg_val &= ~MDIO_SERDES_DIGITAL_A_1000X_CONTROL1_AUTODET;
4923
4924         CL22_WR_OVER_CL45(bp, phy,
4925                           MDIO_REG_BANK_SERDES_DIGITAL,
4926                           MDIO_SERDES_DIGITAL_A_1000X_CONTROL1, reg_val);
4927
4928         /* Enable TetonII and BAM autoneg */
4929         CL22_RD_OVER_CL45(bp, phy,
4930                           MDIO_REG_BANK_BAM_NEXT_PAGE,
4931                           MDIO_BAM_NEXT_PAGE_MP5_NEXT_PAGE_CTRL,
4932                           &reg_val);
4933         if (vars->line_speed == SPEED_AUTO_NEG) {
4934                 /* Enable BAM aneg Mode and TetonII aneg Mode */
4935                 reg_val |= (MDIO_BAM_NEXT_PAGE_MP5_NEXT_PAGE_CTRL_BAM_MODE |
4936                             MDIO_BAM_NEXT_PAGE_MP5_NEXT_PAGE_CTRL_TETON_AN);
4937         } else {
4938                 /* TetonII and BAM Autoneg Disabled */
4939                 reg_val &= ~(MDIO_BAM_NEXT_PAGE_MP5_NEXT_PAGE_CTRL_BAM_MODE |
4940                              MDIO_BAM_NEXT_PAGE_MP5_NEXT_PAGE_CTRL_TETON_AN);
4941         }
4942         CL22_WR_OVER_CL45(bp, phy,
4943                           MDIO_REG_BANK_BAM_NEXT_PAGE,
4944                           MDIO_BAM_NEXT_PAGE_MP5_NEXT_PAGE_CTRL,
4945                           reg_val);
4946
4947         if (enable_cl73) {
4948                 /* Enable Cl73 FSM status bits */
4949                 CL22_WR_OVER_CL45(bp, phy,
4950                                   MDIO_REG_BANK_CL73_USERB0,
4951                                   MDIO_CL73_USERB0_CL73_UCTRL,
4952                                   0xe);
4953
4954                 /* Enable BAM Station Manager*/
4955                 CL22_WR_OVER_CL45(bp, phy,
4956                         MDIO_REG_BANK_CL73_USERB0,
4957                         MDIO_CL73_USERB0_CL73_BAM_CTRL1,
4958                         MDIO_CL73_USERB0_CL73_BAM_CTRL1_BAM_EN |
4959                         MDIO_CL73_USERB0_CL73_BAM_CTRL1_BAM_STATION_MNGR_EN |
4960                         MDIO_CL73_USERB0_CL73_BAM_CTRL1_BAM_NP_AFTER_BP_EN);
4961
4962                 /* Advertise CL73 link speeds */
4963                 CL22_RD_OVER_CL45(bp, phy,
4964                                   MDIO_REG_BANK_CL73_IEEEB1,
4965                                   MDIO_CL73_IEEEB1_AN_ADV2,
4966                                   &reg_val);
4967                 if (phy->speed_cap_mask &
4968                     PORT_HW_CFG_SPEED_CAPABILITY_D0_10G)
4969                         reg_val |= MDIO_CL73_IEEEB1_AN_ADV2_ADVR_10G_KX4;
4970                 if (phy->speed_cap_mask &
4971                     PORT_HW_CFG_SPEED_CAPABILITY_D0_1G)
4972                         reg_val |= MDIO_CL73_IEEEB1_AN_ADV2_ADVR_1000M_KX;
4973
4974                 CL22_WR_OVER_CL45(bp, phy,
4975                                   MDIO_REG_BANK_CL73_IEEEB1,
4976                                   MDIO_CL73_IEEEB1_AN_ADV2,
4977                                   reg_val);
4978
4979                 /* CL73 Autoneg Enabled */
4980                 reg_val = MDIO_CL73_IEEEB0_CL73_AN_CONTROL_AN_EN;
4981
4982         } else /* CL73 Autoneg Disabled */
4983                 reg_val = 0;
4984
4985         CL22_WR_OVER_CL45(bp, phy,
4986                           MDIO_REG_BANK_CL73_IEEEB0,
4987                           MDIO_CL73_IEEEB0_CL73_AN_CONTROL, reg_val);
4988 }
4989
4990 /* program SerDes, forced speed */
4991 static void bnx2x_program_serdes(struct bnx2x_phy *phy,
4992                                  struct link_params *params,
4993                                  struct link_vars *vars)
4994 {
4995         struct bnx2x *bp = params->bp;
4996         u16 reg_val;
4997
4998         /* program duplex, disable autoneg and sgmii*/
4999         CL22_RD_OVER_CL45(bp, phy,
5000                           MDIO_REG_BANK_COMBO_IEEE0,
5001                           MDIO_COMBO_IEEE0_MII_CONTROL, &reg_val);
5002         reg_val &= ~(MDIO_COMBO_IEEO_MII_CONTROL_FULL_DUPLEX |
5003                      MDIO_COMBO_IEEO_MII_CONTROL_AN_EN |
5004                      MDIO_COMBO_IEEO_MII_CONTROL_MAN_SGMII_SP_MASK);
5005         if (phy->req_duplex == DUPLEX_FULL)
5006                 reg_val |= MDIO_COMBO_IEEO_MII_CONTROL_FULL_DUPLEX;
5007         CL22_WR_OVER_CL45(bp, phy,
5008                           MDIO_REG_BANK_COMBO_IEEE0,
5009                           MDIO_COMBO_IEEE0_MII_CONTROL, reg_val);
5010
5011         /*
5012          * program speed
5013          *  - needed only if the speed is greater than 1G (2.5G or 10G)
5014          */
5015         CL22_RD_OVER_CL45(bp, phy,
5016                           MDIO_REG_BANK_SERDES_DIGITAL,
5017                           MDIO_SERDES_DIGITAL_MISC1, &reg_val);
5018         /* clearing the speed value before setting the right speed */
5019         DP(NETIF_MSG_LINK, "MDIO_REG_BANK_SERDES_DIGITAL = 0x%x\n", reg_val);
5020
5021         reg_val &= ~(MDIO_SERDES_DIGITAL_MISC1_FORCE_SPEED_MASK |
5022                      MDIO_SERDES_DIGITAL_MISC1_FORCE_SPEED_SEL);
5023
5024         if (!((vars->line_speed == SPEED_1000) ||
5025               (vars->line_speed == SPEED_100) ||
5026               (vars->line_speed == SPEED_10))) {
5027
5028                 reg_val |= (MDIO_SERDES_DIGITAL_MISC1_REFCLK_SEL_156_25M |
5029                             MDIO_SERDES_DIGITAL_MISC1_FORCE_SPEED_SEL);
5030                 if (vars->line_speed == SPEED_10000)
5031                         reg_val |=
5032                                 MDIO_SERDES_DIGITAL_MISC1_FORCE_SPEED_10G_CX4;
5033         }
5034
5035         CL22_WR_OVER_CL45(bp, phy,
5036                           MDIO_REG_BANK_SERDES_DIGITAL,
5037                           MDIO_SERDES_DIGITAL_MISC1, reg_val);
5038
5039 }
5040
5041 static void bnx2x_set_brcm_cl37_advertisement(struct bnx2x_phy *phy,
5042                                               struct link_params *params)
5043 {
5044         struct bnx2x *bp = params->bp;
5045         u16 val = 0;
5046
5047         /* configure the 48 bits for BAM AN */
5048
5049         /* set extended capabilities */
5050         if (phy->speed_cap_mask & PORT_HW_CFG_SPEED_CAPABILITY_D0_2_5G)
5051                 val |= MDIO_OVER_1G_UP1_2_5G;
5052         if (phy->speed_cap_mask & PORT_HW_CFG_SPEED_CAPABILITY_D0_10G)
5053                 val |= MDIO_OVER_1G_UP1_10G;
5054         CL22_WR_OVER_CL45(bp, phy,
5055                           MDIO_REG_BANK_OVER_1G,
5056                           MDIO_OVER_1G_UP1, val);
5057
5058         CL22_WR_OVER_CL45(bp, phy,
5059                           MDIO_REG_BANK_OVER_1G,
5060                           MDIO_OVER_1G_UP3, 0x400);
5061 }
5062
5063 static void bnx2x_set_ieee_aneg_advertisement(struct bnx2x_phy *phy,
5064                                               struct link_params *params,
5065                                               u16 ieee_fc)
5066 {
5067         struct bnx2x *bp = params->bp;
5068         u16 val;
5069         /* for AN, we are always publishing full duplex */
5070
5071         CL22_WR_OVER_CL45(bp, phy,
5072                           MDIO_REG_BANK_COMBO_IEEE0,
5073                           MDIO_COMBO_IEEE0_AUTO_NEG_ADV, ieee_fc);
5074         CL22_RD_OVER_CL45(bp, phy,
5075                           MDIO_REG_BANK_CL73_IEEEB1,
5076                           MDIO_CL73_IEEEB1_AN_ADV1, &val);
5077         val &= ~MDIO_CL73_IEEEB1_AN_ADV1_PAUSE_BOTH;
5078         val |= ((ieee_fc<<3) & MDIO_CL73_IEEEB1_AN_ADV1_PAUSE_MASK);
5079         CL22_WR_OVER_CL45(bp, phy,
5080                           MDIO_REG_BANK_CL73_IEEEB1,
5081                           MDIO_CL73_IEEEB1_AN_ADV1, val);
5082 }
5083
5084 static void bnx2x_restart_autoneg(struct bnx2x_phy *phy,
5085                                   struct link_params *params,
5086                                   u8 enable_cl73)
5087 {
5088         struct bnx2x *bp = params->bp;
5089         u16 mii_control;
5090
5091         DP(NETIF_MSG_LINK, "bnx2x_restart_autoneg\n");
5092         /* Enable and restart BAM/CL37 aneg */
5093
5094         if (enable_cl73) {
5095                 CL22_RD_OVER_CL45(bp, phy,
5096                                   MDIO_REG_BANK_CL73_IEEEB0,
5097                                   MDIO_CL73_IEEEB0_CL73_AN_CONTROL,
5098                                   &mii_control);
5099
5100                 CL22_WR_OVER_CL45(bp, phy,
5101                                   MDIO_REG_BANK_CL73_IEEEB0,
5102                                   MDIO_CL73_IEEEB0_CL73_AN_CONTROL,
5103                                   (mii_control |
5104                                   MDIO_CL73_IEEEB0_CL73_AN_CONTROL_AN_EN |
5105                                   MDIO_CL73_IEEEB0_CL73_AN_CONTROL_RESTART_AN));
5106         } else {
5107
5108                 CL22_RD_OVER_CL45(bp, phy,
5109                                   MDIO_REG_BANK_COMBO_IEEE0,
5110                                   MDIO_COMBO_IEEE0_MII_CONTROL,
5111                                   &mii_control);
5112                 DP(NETIF_MSG_LINK,
5113                          "bnx2x_restart_autoneg mii_control before = 0x%x\n",
5114                          mii_control);
5115                 CL22_WR_OVER_CL45(bp, phy,
5116                                   MDIO_REG_BANK_COMBO_IEEE0,
5117                                   MDIO_COMBO_IEEE0_MII_CONTROL,
5118                                   (mii_control |
5119                                    MDIO_COMBO_IEEO_MII_CONTROL_AN_EN |
5120                                    MDIO_COMBO_IEEO_MII_CONTROL_RESTART_AN));
5121         }
5122 }
5123
5124 static void bnx2x_initialize_sgmii_process(struct bnx2x_phy *phy,
5125                                            struct link_params *params,
5126                                            struct link_vars *vars)
5127 {
5128         struct bnx2x *bp = params->bp;
5129         u16 control1;
5130
5131         /* in SGMII mode, the unicore is always slave */
5132
5133         CL22_RD_OVER_CL45(bp, phy,
5134                           MDIO_REG_BANK_SERDES_DIGITAL,
5135                           MDIO_SERDES_DIGITAL_A_1000X_CONTROL1,
5136                           &control1);
5137         control1 |= MDIO_SERDES_DIGITAL_A_1000X_CONTROL1_INVERT_SIGNAL_DETECT;
5138         /* set sgmii mode (and not fiber) */
5139         control1 &= ~(MDIO_SERDES_DIGITAL_A_1000X_CONTROL1_FIBER_MODE |
5140                       MDIO_SERDES_DIGITAL_A_1000X_CONTROL1_AUTODET |
5141                       MDIO_SERDES_DIGITAL_A_1000X_CONTROL1_MSTR_MODE);
5142         CL22_WR_OVER_CL45(bp, phy,
5143                           MDIO_REG_BANK_SERDES_DIGITAL,
5144                           MDIO_SERDES_DIGITAL_A_1000X_CONTROL1,
5145                           control1);
5146
5147         /* if forced speed */
5148         if (!(vars->line_speed == SPEED_AUTO_NEG)) {
5149                 /* set speed, disable autoneg */
5150                 u16 mii_control;
5151
5152                 CL22_RD_OVER_CL45(bp, phy,
5153                                   MDIO_REG_BANK_COMBO_IEEE0,
5154                                   MDIO_COMBO_IEEE0_MII_CONTROL,
5155                                   &mii_control);
5156                 mii_control &= ~(MDIO_COMBO_IEEO_MII_CONTROL_AN_EN |
5157                                  MDIO_COMBO_IEEO_MII_CONTROL_MAN_SGMII_SP_MASK|
5158                                  MDIO_COMBO_IEEO_MII_CONTROL_FULL_DUPLEX);
5159
5160                 switch (vars->line_speed) {
5161                 case SPEED_100:
5162                         mii_control |=
5163                                 MDIO_COMBO_IEEO_MII_CONTROL_MAN_SGMII_SP_100;
5164                         break;
5165                 case SPEED_1000:
5166                         mii_control |=
5167                                 MDIO_COMBO_IEEO_MII_CONTROL_MAN_SGMII_SP_1000;
5168                         break;
5169                 case SPEED_10:
5170                         /* there is nothing to set for 10M */
5171                         break;
5172                 default:
5173                         /* invalid speed for SGMII */
5174                         DP(NETIF_MSG_LINK, "Invalid line_speed 0x%x\n",
5175                                   vars->line_speed);
5176                         break;
5177                 }
5178
5179                 /* setting the full duplex */
5180                 if (phy->req_duplex == DUPLEX_FULL)
5181                         mii_control |=
5182                                 MDIO_COMBO_IEEO_MII_CONTROL_FULL_DUPLEX;
5183                 CL22_WR_OVER_CL45(bp, phy,
5184                                   MDIO_REG_BANK_COMBO_IEEE0,
5185                                   MDIO_COMBO_IEEE0_MII_CONTROL,
5186                                   mii_control);
5187
5188         } else { /* AN mode */
5189                 /* enable and restart AN */
5190                 bnx2x_restart_autoneg(phy, params, 0);
5191         }
5192 }
5193
5194
5195 /*
5196  * link management
5197  */
5198
5199 static int bnx2x_direct_parallel_detect_used(struct bnx2x_phy *phy,
5200                                              struct link_params *params)
5201 {
5202         struct bnx2x *bp = params->bp;
5203         u16 pd_10g, status2_1000x;
5204         if (phy->req_line_speed != SPEED_AUTO_NEG)
5205                 return 0;
5206         CL22_RD_OVER_CL45(bp, phy,
5207                           MDIO_REG_BANK_SERDES_DIGITAL,
5208                           MDIO_SERDES_DIGITAL_A_1000X_STATUS2,
5209                           &status2_1000x);
5210         CL22_RD_OVER_CL45(bp, phy,
5211                           MDIO_REG_BANK_SERDES_DIGITAL,
5212                           MDIO_SERDES_DIGITAL_A_1000X_STATUS2,
5213                           &status2_1000x);
5214         if (status2_1000x & MDIO_SERDES_DIGITAL_A_1000X_STATUS2_AN_DISABLED) {
5215                 DP(NETIF_MSG_LINK, "1G parallel detect link on port %d\n",
5216                          params->port);
5217                 return 1;
5218         }
5219
5220         CL22_RD_OVER_CL45(bp, phy,
5221                           MDIO_REG_BANK_10G_PARALLEL_DETECT,
5222                           MDIO_10G_PARALLEL_DETECT_PAR_DET_10G_STATUS,
5223                           &pd_10g);
5224
5225         if (pd_10g & MDIO_10G_PARALLEL_DETECT_PAR_DET_10G_STATUS_PD_LINK) {
5226                 DP(NETIF_MSG_LINK, "10G parallel detect link on port %d\n",
5227                          params->port);
5228                 return 1;
5229         }
5230         return 0;
5231 }
5232
5233 static void bnx2x_update_adv_fc(struct bnx2x_phy *phy,
5234                                 struct link_params *params,
5235                                 struct link_vars *vars,
5236                                 u32 gp_status)
5237 {
5238         u16 ld_pause;   /* local driver */
5239         u16 lp_pause;   /* link partner */
5240         u16 pause_result;
5241         struct bnx2x *bp = params->bp;
5242         if ((gp_status &
5243              (MDIO_GP_STATUS_TOP_AN_STATUS1_CL73_AUTONEG_COMPLETE |
5244               MDIO_GP_STATUS_TOP_AN_STATUS1_CL73_MR_LP_NP_AN_ABLE)) ==
5245             (MDIO_GP_STATUS_TOP_AN_STATUS1_CL73_AUTONEG_COMPLETE |
5246              MDIO_GP_STATUS_TOP_AN_STATUS1_CL73_MR_LP_NP_AN_ABLE)) {
5247
5248                 CL22_RD_OVER_CL45(bp, phy,
5249                                   MDIO_REG_BANK_CL73_IEEEB1,
5250                                   MDIO_CL73_IEEEB1_AN_ADV1,
5251                                   &ld_pause);
5252                 CL22_RD_OVER_CL45(bp, phy,
5253                                   MDIO_REG_BANK_CL73_IEEEB1,
5254                                   MDIO_CL73_IEEEB1_AN_LP_ADV1,
5255                                   &lp_pause);
5256                 pause_result = (ld_pause &
5257                                 MDIO_CL73_IEEEB1_AN_ADV1_PAUSE_MASK) >> 8;
5258                 pause_result |= (lp_pause &
5259                                  MDIO_CL73_IEEEB1_AN_LP_ADV1_PAUSE_MASK) >> 10;
5260                 DP(NETIF_MSG_LINK, "pause_result CL73 0x%x\n", pause_result);
5261         } else {
5262                 CL22_RD_OVER_CL45(bp, phy,
5263                                   MDIO_REG_BANK_COMBO_IEEE0,
5264                                   MDIO_COMBO_IEEE0_AUTO_NEG_ADV,
5265                                   &ld_pause);
5266                 CL22_RD_OVER_CL45(bp, phy,
5267                         MDIO_REG_BANK_COMBO_IEEE0,
5268                         MDIO_COMBO_IEEE0_AUTO_NEG_LINK_PARTNER_ABILITY1,
5269                         &lp_pause);
5270                 pause_result = (ld_pause &
5271                                 MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_MASK)>>5;
5272                 pause_result |= (lp_pause &
5273                                  MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_MASK)>>7;
5274                 DP(NETIF_MSG_LINK, "pause_result CL37 0x%x\n", pause_result);
5275         }
5276         bnx2x_pause_resolve(vars, pause_result);
5277
5278 }
5279
5280 static void bnx2x_flow_ctrl_resolve(struct bnx2x_phy *phy,
5281                                     struct link_params *params,
5282                                     struct link_vars *vars,
5283                                     u32 gp_status)
5284 {
5285         struct bnx2x *bp = params->bp;
5286         vars->flow_ctrl = BNX2X_FLOW_CTRL_NONE;
5287
5288         /* resolve from gp_status in case of AN complete and not sgmii */
5289         if (phy->req_flow_ctrl != BNX2X_FLOW_CTRL_AUTO) {
5290                 /* Update the advertised flow-controled of LD/LP in AN */
5291                 if (phy->req_line_speed == SPEED_AUTO_NEG)
5292                         bnx2x_update_adv_fc(phy, params, vars, gp_status);
5293                 /* But set the flow-control result as the requested one */
5294                 vars->flow_ctrl = phy->req_flow_ctrl;
5295         } else if (phy->req_line_speed != SPEED_AUTO_NEG)
5296                 vars->flow_ctrl = params->req_fc_auto_adv;
5297         else if ((gp_status & MDIO_AN_CL73_OR_37_COMPLETE) &&
5298                  (!(vars->phy_flags & PHY_SGMII_FLAG))) {
5299                 if (bnx2x_direct_parallel_detect_used(phy, params)) {
5300                         vars->flow_ctrl = params->req_fc_auto_adv;
5301                         return;
5302                 }
5303                 bnx2x_update_adv_fc(phy, params, vars, gp_status);
5304         }
5305         DP(NETIF_MSG_LINK, "flow_ctrl 0x%x\n", vars->flow_ctrl);
5306 }
5307
5308 static void bnx2x_check_fallback_to_cl37(struct bnx2x_phy *phy,
5309                                          struct link_params *params)
5310 {
5311         struct bnx2x *bp = params->bp;
5312         u16 rx_status, ustat_val, cl37_fsm_received;
5313         DP(NETIF_MSG_LINK, "bnx2x_check_fallback_to_cl37\n");
5314         /* Step 1: Make sure signal is detected */
5315         CL22_RD_OVER_CL45(bp, phy,
5316                           MDIO_REG_BANK_RX0,
5317                           MDIO_RX0_RX_STATUS,
5318                           &rx_status);
5319         if ((rx_status & MDIO_RX0_RX_STATUS_SIGDET) !=
5320             (MDIO_RX0_RX_STATUS_SIGDET)) {
5321                 DP(NETIF_MSG_LINK, "Signal is not detected. Restoring CL73."
5322                              "rx_status(0x80b0) = 0x%x\n", rx_status);
5323                 CL22_WR_OVER_CL45(bp, phy,
5324                                   MDIO_REG_BANK_CL73_IEEEB0,
5325                                   MDIO_CL73_IEEEB0_CL73_AN_CONTROL,
5326                                   MDIO_CL73_IEEEB0_CL73_AN_CONTROL_AN_EN);
5327                 return;
5328         }
5329         /* Step 2: Check CL73 state machine */
5330         CL22_RD_OVER_CL45(bp, phy,
5331                           MDIO_REG_BANK_CL73_USERB0,
5332                           MDIO_CL73_USERB0_CL73_USTAT1,
5333                           &ustat_val);
5334         if ((ustat_val &
5335              (MDIO_CL73_USERB0_CL73_USTAT1_LINK_STATUS_CHECK |
5336               MDIO_CL73_USERB0_CL73_USTAT1_AN_GOOD_CHECK_BAM37)) !=
5337             (MDIO_CL73_USERB0_CL73_USTAT1_LINK_STATUS_CHECK |
5338               MDIO_CL73_USERB0_CL73_USTAT1_AN_GOOD_CHECK_BAM37)) {
5339                 DP(NETIF_MSG_LINK, "CL73 state-machine is not stable. "
5340                              "ustat_val(0x8371) = 0x%x\n", ustat_val);
5341                 return;
5342         }
5343         /*
5344          * Step 3: Check CL37 Message Pages received to indicate LP
5345          * supports only CL37
5346          */
5347         CL22_RD_OVER_CL45(bp, phy,
5348                           MDIO_REG_BANK_REMOTE_PHY,
5349                           MDIO_REMOTE_PHY_MISC_RX_STATUS,
5350                           &cl37_fsm_received);
5351         if ((cl37_fsm_received &
5352              (MDIO_REMOTE_PHY_MISC_RX_STATUS_CL37_FSM_RECEIVED_OVER1G_MSG |
5353              MDIO_REMOTE_PHY_MISC_RX_STATUS_CL37_FSM_RECEIVED_BRCM_OUI_MSG)) !=
5354             (MDIO_REMOTE_PHY_MISC_RX_STATUS_CL37_FSM_RECEIVED_OVER1G_MSG |
5355               MDIO_REMOTE_PHY_MISC_RX_STATUS_CL37_FSM_RECEIVED_BRCM_OUI_MSG)) {
5356                 DP(NETIF_MSG_LINK, "No CL37 FSM were received. "
5357                              "misc_rx_status(0x8330) = 0x%x\n",
5358                          cl37_fsm_received);
5359                 return;
5360         }
5361         /*
5362          * The combined cl37/cl73 fsm state information indicating that
5363          * we are connected to a device which does not support cl73, but
5364          * does support cl37 BAM. In this case we disable cl73 and
5365          * restart cl37 auto-neg
5366          */
5367
5368         /* Disable CL73 */
5369         CL22_WR_OVER_CL45(bp, phy,
5370                           MDIO_REG_BANK_CL73_IEEEB0,
5371                           MDIO_CL73_IEEEB0_CL73_AN_CONTROL,
5372                           0);
5373         /* Restart CL37 autoneg */
5374         bnx2x_restart_autoneg(phy, params, 0);
5375         DP(NETIF_MSG_LINK, "Disabling CL73, and restarting CL37 autoneg\n");
5376 }
5377
5378 static void bnx2x_xgxs_an_resolve(struct bnx2x_phy *phy,
5379                                   struct link_params *params,
5380                                   struct link_vars *vars,
5381                                   u32 gp_status)
5382 {
5383         if (gp_status & MDIO_AN_CL73_OR_37_COMPLETE)
5384                 vars->link_status |=
5385                         LINK_STATUS_AUTO_NEGOTIATE_COMPLETE;
5386
5387         if (bnx2x_direct_parallel_detect_used(phy, params))
5388                 vars->link_status |=
5389                         LINK_STATUS_PARALLEL_DETECTION_USED;
5390 }
5391 static int bnx2x_get_link_speed_duplex(struct bnx2x_phy *phy,
5392                                      struct link_params *params,
5393                                       struct link_vars *vars,
5394                                       u16 is_link_up,
5395                                       u16 speed_mask,
5396                                       u16 is_duplex)
5397 {
5398         struct bnx2x *bp = params->bp;
5399         if (phy->req_line_speed == SPEED_AUTO_NEG)
5400                 vars->link_status |= LINK_STATUS_AUTO_NEGOTIATE_ENABLED;
5401         if (is_link_up) {
5402                 DP(NETIF_MSG_LINK, "phy link up\n");
5403
5404                 vars->phy_link_up = 1;
5405                 vars->link_status |= LINK_STATUS_LINK_UP;
5406
5407                 switch (speed_mask) {
5408                 case GP_STATUS_10M:
5409                         vars->line_speed = SPEED_10;
5410                         if (vars->duplex == DUPLEX_FULL)
5411                                 vars->link_status |= LINK_10TFD;
5412                         else
5413                                 vars->link_status |= LINK_10THD;
5414                         break;
5415
5416                 case GP_STATUS_100M:
5417                         vars->line_speed = SPEED_100;
5418                         if (vars->duplex == DUPLEX_FULL)
5419                                 vars->link_status |= LINK_100TXFD;
5420                         else
5421                                 vars->link_status |= LINK_100TXHD;
5422                         break;
5423
5424                 case GP_STATUS_1G:
5425                 case GP_STATUS_1G_KX:
5426                         vars->line_speed = SPEED_1000;
5427                         if (vars->duplex == DUPLEX_FULL)
5428                                 vars->link_status |= LINK_1000TFD;
5429                         else
5430                                 vars->link_status |= LINK_1000THD;
5431                         break;
5432
5433                 case GP_STATUS_2_5G:
5434                         vars->line_speed = SPEED_2500;
5435                         if (vars->duplex == DUPLEX_FULL)
5436                                 vars->link_status |= LINK_2500TFD;
5437                         else
5438                                 vars->link_status |= LINK_2500THD;
5439                         break;
5440
5441                 case GP_STATUS_5G:
5442                 case GP_STATUS_6G:
5443                         DP(NETIF_MSG_LINK,
5444                                  "link speed unsupported  gp_status 0x%x\n",
5445                                   speed_mask);
5446                         return -EINVAL;
5447
5448                 case GP_STATUS_10G_KX4:
5449                 case GP_STATUS_10G_HIG:
5450                 case GP_STATUS_10G_CX4:
5451                 case GP_STATUS_10G_KR:
5452                 case GP_STATUS_10G_SFI:
5453                 case GP_STATUS_10G_XFI:
5454                         vars->line_speed = SPEED_10000;
5455                         vars->link_status |= LINK_10GTFD;
5456                         break;
5457                 case GP_STATUS_20G_DXGXS:
5458                         vars->line_speed = SPEED_20000;
5459                         vars->link_status |= LINK_20GTFD;
5460                         break;
5461                 default:
5462                         DP(NETIF_MSG_LINK,
5463                                   "link speed unsupported gp_status 0x%x\n",
5464                                   speed_mask);
5465                         return -EINVAL;
5466                 }
5467         } else { /* link_down */
5468                 DP(NETIF_MSG_LINK, "phy link down\n");
5469
5470                 vars->phy_link_up = 0;
5471
5472                 vars->duplex = DUPLEX_FULL;
5473                 vars->flow_ctrl = BNX2X_FLOW_CTRL_NONE;
5474                 vars->mac_type = MAC_TYPE_NONE;
5475         }
5476         DP(NETIF_MSG_LINK, " phy_link_up %x line_speed %d\n",
5477                     vars->phy_link_up, vars->line_speed);
5478         return 0;
5479 }
5480
5481 static int bnx2x_link_settings_status(struct bnx2x_phy *phy,
5482                                       struct link_params *params,
5483                                       struct link_vars *vars)
5484 {
5485         struct bnx2x *bp = params->bp;
5486
5487         u16 gp_status, duplex = DUPLEX_HALF, link_up = 0, speed_mask;
5488         int rc = 0;
5489
5490         /* Read gp_status */
5491         CL22_RD_OVER_CL45(bp, phy,
5492                           MDIO_REG_BANK_GP_STATUS,
5493                           MDIO_GP_STATUS_TOP_AN_STATUS1,
5494                           &gp_status);
5495         if (gp_status & MDIO_GP_STATUS_TOP_AN_STATUS1_DUPLEX_STATUS)
5496                 duplex = DUPLEX_FULL;
5497         if (gp_status & MDIO_GP_STATUS_TOP_AN_STATUS1_LINK_STATUS)
5498                 link_up = 1;
5499         speed_mask = gp_status & GP_STATUS_SPEED_MASK;
5500         DP(NETIF_MSG_LINK, "gp_status 0x%x, is_link_up %d, speed_mask 0x%x\n",
5501                        gp_status, link_up, speed_mask);
5502         rc = bnx2x_get_link_speed_duplex(phy, params, vars, link_up, speed_mask,
5503                                          duplex);
5504         if (rc == -EINVAL)
5505                 return rc;
5506
5507         if (gp_status & MDIO_GP_STATUS_TOP_AN_STATUS1_LINK_STATUS) {
5508                 if (SINGLE_MEDIA_DIRECT(params)) {
5509                         bnx2x_flow_ctrl_resolve(phy, params, vars, gp_status);
5510                         if (phy->req_line_speed == SPEED_AUTO_NEG)
5511                                 bnx2x_xgxs_an_resolve(phy, params, vars,
5512                                                       gp_status);
5513                 }
5514         } else { /* link_down */
5515                 if ((phy->req_line_speed == SPEED_AUTO_NEG) &&
5516                     SINGLE_MEDIA_DIRECT(params)) {
5517                         /* Check signal is detected */
5518                         bnx2x_check_fallback_to_cl37(phy, params);
5519                 }
5520         }
5521
5522         /* Read LP advertised speeds*/
5523         if (SINGLE_MEDIA_DIRECT(params) &&
5524             (vars->link_status & LINK_STATUS_AUTO_NEGOTIATE_COMPLETE)) {
5525                 u16 val;
5526
5527                 CL22_RD_OVER_CL45(bp, phy, MDIO_REG_BANK_CL73_IEEEB1,
5528                                   MDIO_CL73_IEEEB1_AN_LP_ADV2, &val);
5529
5530                 if (val & MDIO_CL73_IEEEB1_AN_ADV2_ADVR_1000M_KX)
5531                         vars->link_status |=
5532                                 LINK_STATUS_LINK_PARTNER_1000TFD_CAPABLE;
5533                 if (val & (MDIO_CL73_IEEEB1_AN_ADV2_ADVR_10G_KX4 |
5534                            MDIO_CL73_IEEEB1_AN_ADV2_ADVR_10G_KR))
5535                         vars->link_status |=
5536                                 LINK_STATUS_LINK_PARTNER_10GXFD_CAPABLE;
5537
5538                 CL22_RD_OVER_CL45(bp, phy, MDIO_REG_BANK_OVER_1G,
5539                                   MDIO_OVER_1G_LP_UP1, &val);
5540
5541                 if (val & MDIO_OVER_1G_UP1_2_5G)
5542                         vars->link_status |=
5543                                 LINK_STATUS_LINK_PARTNER_2500XFD_CAPABLE;
5544                 if (val & (MDIO_OVER_1G_UP1_10G | MDIO_OVER_1G_UP1_10GH))
5545                         vars->link_status |=
5546                                 LINK_STATUS_LINK_PARTNER_10GXFD_CAPABLE;
5547         }
5548
5549         DP(NETIF_MSG_LINK, "duplex %x  flow_ctrl 0x%x link_status 0x%x\n",
5550                    vars->duplex, vars->flow_ctrl, vars->link_status);
5551         return rc;
5552 }
5553
5554 static int bnx2x_warpcore_read_status(struct bnx2x_phy *phy,
5555                                      struct link_params *params,
5556                                      struct link_vars *vars)
5557 {
5558         struct bnx2x *bp = params->bp;
5559         u8 lane;
5560         u16 gp_status1, gp_speed, link_up, duplex = DUPLEX_FULL;
5561         int rc = 0;
5562         lane = bnx2x_get_warpcore_lane(phy, params);
5563         /* Read gp_status */
5564         if (phy->req_line_speed > SPEED_10000) {
5565                 u16 temp_link_up;
5566                 bnx2x_cl45_read(bp, phy, MDIO_WC_DEVAD,
5567                                 1, &temp_link_up);
5568                 bnx2x_cl45_read(bp, phy, MDIO_WC_DEVAD,
5569                                 1, &link_up);
5570                 DP(NETIF_MSG_LINK, "PCS RX link status = 0x%x-->0x%x\n",
5571                                temp_link_up, link_up);
5572                 link_up &= (1<<2);
5573                 if (link_up)
5574                         bnx2x_ext_phy_resolve_fc(phy, params, vars);
5575         } else {
5576                 bnx2x_cl45_read(bp, phy, MDIO_WC_DEVAD,
5577                                 MDIO_WC_REG_GP2_STATUS_GP_2_1, &gp_status1);
5578                 DP(NETIF_MSG_LINK, "0x81d1 = 0x%x\n", gp_status1);
5579                 /* Check for either KR or generic link up. */
5580                 gp_status1 = ((gp_status1 >> 8) & 0xf) |
5581                         ((gp_status1 >> 12) & 0xf);
5582                 link_up = gp_status1 & (1 << lane);
5583                 if (link_up && SINGLE_MEDIA_DIRECT(params)) {
5584                         u16 pd, gp_status4;
5585                         if (phy->req_line_speed == SPEED_AUTO_NEG) {
5586                                 /* Check Autoneg complete */
5587                                 bnx2x_cl45_read(bp, phy, MDIO_WC_DEVAD,
5588                                                 MDIO_WC_REG_GP2_STATUS_GP_2_4,
5589                                                 &gp_status4);
5590                                 if (gp_status4 & ((1<<12)<<lane))
5591                                         vars->link_status |=
5592                                         LINK_STATUS_AUTO_NEGOTIATE_COMPLETE;
5593
5594                                 /* Check parallel detect used */
5595                                 bnx2x_cl45_read(bp, phy, MDIO_WC_DEVAD,
5596                                                 MDIO_WC_REG_PAR_DET_10G_STATUS,
5597                                                 &pd);
5598                                 if (pd & (1<<15))
5599                                         vars->link_status |=
5600                                         LINK_STATUS_PARALLEL_DETECTION_USED;
5601                         }
5602                         bnx2x_ext_phy_resolve_fc(phy, params, vars);
5603                 }
5604         }
5605
5606         if ((vars->link_status & LINK_STATUS_AUTO_NEGOTIATE_COMPLETE) &&
5607             SINGLE_MEDIA_DIRECT(params)) {
5608                 u16 val;
5609
5610                 bnx2x_cl45_read(bp, phy, MDIO_AN_DEVAD,
5611                                 MDIO_AN_REG_LP_AUTO_NEG2, &val);
5612
5613                 if (val & MDIO_CL73_IEEEB1_AN_ADV2_ADVR_1000M_KX)
5614                         vars->link_status |=
5615                                 LINK_STATUS_LINK_PARTNER_1000TFD_CAPABLE;
5616                 if (val & (MDIO_CL73_IEEEB1_AN_ADV2_ADVR_10G_KX4 |
5617                            MDIO_CL73_IEEEB1_AN_ADV2_ADVR_10G_KR))
5618                         vars->link_status |=
5619                                 LINK_STATUS_LINK_PARTNER_10GXFD_CAPABLE;
5620
5621                 bnx2x_cl45_read(bp, phy, MDIO_WC_DEVAD,
5622                                 MDIO_WC_REG_DIGITAL3_LP_UP1, &val);
5623
5624                 if (val & MDIO_OVER_1G_UP1_2_5G)
5625                         vars->link_status |=
5626                                 LINK_STATUS_LINK_PARTNER_2500XFD_CAPABLE;
5627                 if (val & (MDIO_OVER_1G_UP1_10G | MDIO_OVER_1G_UP1_10GH))
5628                         vars->link_status |=
5629                                 LINK_STATUS_LINK_PARTNER_10GXFD_CAPABLE;
5630
5631         }
5632
5633
5634         if (lane < 2) {
5635                 bnx2x_cl45_read(bp, phy, MDIO_WC_DEVAD,
5636                                 MDIO_WC_REG_GP2_STATUS_GP_2_2, &gp_speed);
5637         } else {
5638                 bnx2x_cl45_read(bp, phy, MDIO_WC_DEVAD,
5639                                 MDIO_WC_REG_GP2_STATUS_GP_2_3, &gp_speed);
5640         }
5641         DP(NETIF_MSG_LINK, "lane %d gp_speed 0x%x\n", lane, gp_speed);
5642
5643         if ((lane & 1) == 0)
5644                 gp_speed <<= 8;
5645         gp_speed &= 0x3f00;
5646
5647
5648         rc = bnx2x_get_link_speed_duplex(phy, params, vars, link_up, gp_speed,
5649                                          duplex);
5650
5651         DP(NETIF_MSG_LINK, "duplex %x  flow_ctrl 0x%x link_status 0x%x\n",
5652                    vars->duplex, vars->flow_ctrl, vars->link_status);
5653         return rc;
5654 }
5655 static void bnx2x_set_gmii_tx_driver(struct link_params *params)
5656 {
5657         struct bnx2x *bp = params->bp;
5658         struct bnx2x_phy *phy = &params->phy[INT_PHY];
5659         u16 lp_up2;
5660         u16 tx_driver;
5661         u16 bank;
5662
5663         /* read precomp */
5664         CL22_RD_OVER_CL45(bp, phy,
5665                           MDIO_REG_BANK_OVER_1G,
5666                           MDIO_OVER_1G_LP_UP2, &lp_up2);
5667
5668         /* bits [10:7] at lp_up2, positioned at [15:12] */
5669         lp_up2 = (((lp_up2 & MDIO_OVER_1G_LP_UP2_PREEMPHASIS_MASK) >>
5670                    MDIO_OVER_1G_LP_UP2_PREEMPHASIS_SHIFT) <<
5671                   MDIO_TX0_TX_DRIVER_PREEMPHASIS_SHIFT);
5672
5673         if (lp_up2 == 0)
5674                 return;
5675
5676         for (bank = MDIO_REG_BANK_TX0; bank <= MDIO_REG_BANK_TX3;
5677               bank += (MDIO_REG_BANK_TX1 - MDIO_REG_BANK_TX0)) {
5678                 CL22_RD_OVER_CL45(bp, phy,
5679                                   bank,
5680                                   MDIO_TX0_TX_DRIVER, &tx_driver);
5681
5682                 /* replace tx_driver bits [15:12] */
5683                 if (lp_up2 !=
5684                     (tx_driver & MDIO_TX0_TX_DRIVER_PREEMPHASIS_MASK)) {
5685                         tx_driver &= ~MDIO_TX0_TX_DRIVER_PREEMPHASIS_MASK;
5686                         tx_driver |= lp_up2;
5687                         CL22_WR_OVER_CL45(bp, phy,
5688                                           bank,
5689                                           MDIO_TX0_TX_DRIVER, tx_driver);
5690                 }
5691         }
5692 }
5693
5694 static int bnx2x_emac_program(struct link_params *params,
5695                               struct link_vars *vars)
5696 {
5697         struct bnx2x *bp = params->bp;
5698         u8 port = params->port;
5699         u16 mode = 0;
5700
5701         DP(NETIF_MSG_LINK, "setting link speed & duplex\n");
5702         bnx2x_bits_dis(bp, GRCBASE_EMAC0 + port*0x400 +
5703                        EMAC_REG_EMAC_MODE,
5704                        (EMAC_MODE_25G_MODE |
5705                         EMAC_MODE_PORT_MII_10M |
5706                         EMAC_MODE_HALF_DUPLEX));
5707         switch (vars->line_speed) {
5708         case SPEED_10:
5709                 mode |= EMAC_MODE_PORT_MII_10M;
5710                 break;
5711
5712         case SPEED_100:
5713                 mode |= EMAC_MODE_PORT_MII;
5714                 break;
5715
5716         case SPEED_1000:
5717                 mode |= EMAC_MODE_PORT_GMII;
5718                 break;
5719
5720         case SPEED_2500:
5721                 mode |= (EMAC_MODE_25G_MODE | EMAC_MODE_PORT_GMII);
5722                 break;
5723
5724         default:
5725                 /* 10G not valid for EMAC */
5726                 DP(NETIF_MSG_LINK, "Invalid line_speed 0x%x\n",
5727                            vars->line_speed);
5728                 return -EINVAL;
5729         }
5730
5731         if (vars->duplex == DUPLEX_HALF)
5732                 mode |= EMAC_MODE_HALF_DUPLEX;
5733         bnx2x_bits_en(bp,
5734                       GRCBASE_EMAC0 + port*0x400 + EMAC_REG_EMAC_MODE,
5735                       mode);
5736
5737         bnx2x_set_led(params, vars, LED_MODE_OPER, vars->line_speed);
5738         return 0;
5739 }
5740
5741 static void bnx2x_set_preemphasis(struct bnx2x_phy *phy,
5742                                   struct link_params *params)
5743 {
5744
5745         u16 bank, i = 0;
5746         struct bnx2x *bp = params->bp;
5747
5748         for (bank = MDIO_REG_BANK_RX0, i = 0; bank <= MDIO_REG_BANK_RX3;
5749               bank += (MDIO_REG_BANK_RX1-MDIO_REG_BANK_RX0), i++) {
5750                         CL22_WR_OVER_CL45(bp, phy,
5751                                           bank,
5752                                           MDIO_RX0_RX_EQ_BOOST,
5753                                           phy->rx_preemphasis[i]);
5754         }
5755
5756         for (bank = MDIO_REG_BANK_TX0, i = 0; bank <= MDIO_REG_BANK_TX3;
5757                       bank += (MDIO_REG_BANK_TX1 - MDIO_REG_BANK_TX0), i++) {
5758                         CL22_WR_OVER_CL45(bp, phy,
5759                                           bank,
5760                                           MDIO_TX0_TX_DRIVER,
5761                                           phy->tx_preemphasis[i]);
5762         }
5763 }
5764
5765 static void bnx2x_xgxs_config_init(struct bnx2x_phy *phy,
5766                                    struct link_params *params,
5767                                    struct link_vars *vars)
5768 {
5769         struct bnx2x *bp = params->bp;
5770         u8 enable_cl73 = (SINGLE_MEDIA_DIRECT(params) ||
5771                           (params->loopback_mode == LOOPBACK_XGXS));
5772         if (!(vars->phy_flags & PHY_SGMII_FLAG)) {
5773                 if (SINGLE_MEDIA_DIRECT(params) &&
5774                     (params->feature_config_flags &
5775                      FEATURE_CONFIG_OVERRIDE_PREEMPHASIS_ENABLED))
5776                         bnx2x_set_preemphasis(phy, params);
5777
5778                 /* forced speed requested? */
5779                 if (vars->line_speed != SPEED_AUTO_NEG ||
5780                     (SINGLE_MEDIA_DIRECT(params) &&
5781                      params->loopback_mode == LOOPBACK_EXT)) {
5782                         DP(NETIF_MSG_LINK, "not SGMII, no AN\n");
5783
5784                         /* disable autoneg */
5785                         bnx2x_set_autoneg(phy, params, vars, 0);
5786
5787                         /* program speed and duplex */
5788                         bnx2x_program_serdes(phy, params, vars);
5789
5790                 } else { /* AN_mode */
5791                         DP(NETIF_MSG_LINK, "not SGMII, AN\n");
5792
5793                         /* AN enabled */
5794                         bnx2x_set_brcm_cl37_advertisement(phy, params);
5795
5796                         /* program duplex & pause advertisement (for aneg) */
5797                         bnx2x_set_ieee_aneg_advertisement(phy, params,
5798                                                           vars->ieee_fc);
5799
5800                         /* enable autoneg */
5801                         bnx2x_set_autoneg(phy, params, vars, enable_cl73);
5802
5803                         /* enable and restart AN */
5804                         bnx2x_restart_autoneg(phy, params, enable_cl73);
5805                 }
5806
5807         } else { /* SGMII mode */
5808                 DP(NETIF_MSG_LINK, "SGMII\n");
5809
5810                 bnx2x_initialize_sgmii_process(phy, params, vars);
5811         }
5812 }
5813
5814 static int bnx2x_prepare_xgxs(struct bnx2x_phy *phy,
5815                           struct link_params *params,
5816                           struct link_vars *vars)
5817 {
5818         int rc;
5819         vars->phy_flags |= PHY_XGXS_FLAG;
5820         if ((phy->req_line_speed &&
5821              ((phy->req_line_speed == SPEED_100) ||
5822               (phy->req_line_speed == SPEED_10))) ||
5823             (!phy->req_line_speed &&
5824              (phy->speed_cap_mask >=
5825               PORT_HW_CFG_SPEED_CAPABILITY_D0_10M_FULL) &&
5826              (phy->speed_cap_mask <
5827               PORT_HW_CFG_SPEED_CAPABILITY_D0_1G)) ||
5828             (phy->type == PORT_HW_CFG_SERDES_EXT_PHY_TYPE_DIRECT_SD))
5829                 vars->phy_flags |= PHY_SGMII_FLAG;
5830         else
5831                 vars->phy_flags &= ~PHY_SGMII_FLAG;
5832
5833         bnx2x_calc_ieee_aneg_adv(phy, params, &vars->ieee_fc);
5834         bnx2x_set_aer_mmd(params, phy);
5835         if (phy->type == PORT_HW_CFG_XGXS_EXT_PHY_TYPE_DIRECT)
5836                 bnx2x_set_master_ln(params, phy);
5837
5838         rc = bnx2x_reset_unicore(params, phy, 0);
5839         /* reset the SerDes and wait for reset bit return low */
5840         if (rc != 0)
5841                 return rc;
5842
5843         bnx2x_set_aer_mmd(params, phy);
5844         /* setting the masterLn_def again after the reset */
5845         if (phy->type == PORT_HW_CFG_XGXS_EXT_PHY_TYPE_DIRECT) {
5846                 bnx2x_set_master_ln(params, phy);
5847                 bnx2x_set_swap_lanes(params, phy);
5848         }
5849
5850         return rc;
5851 }
5852
5853 static u16 bnx2x_wait_reset_complete(struct bnx2x *bp,
5854                                      struct bnx2x_phy *phy,
5855                                      struct link_params *params)
5856 {
5857         u16 cnt, ctrl;
5858         /* Wait for soft reset to get cleared up to 1 sec */
5859         for (cnt = 0; cnt < 1000; cnt++) {
5860                 if (phy->type == PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM54618SE)
5861                         bnx2x_cl22_read(bp, phy,
5862                                 MDIO_PMA_REG_CTRL, &ctrl);
5863                 else
5864                         bnx2x_cl45_read(bp, phy,
5865                                 MDIO_PMA_DEVAD,
5866                                 MDIO_PMA_REG_CTRL, &ctrl);
5867                 if (!(ctrl & (1<<15)))
5868                         break;
5869                 msleep(1);
5870         }
5871
5872         if (cnt == 1000)
5873                 netdev_err(bp->dev,  "Warning: PHY was not initialized,"
5874                                       " Port %d\n",
5875                          params->port);
5876         DP(NETIF_MSG_LINK, "control reg 0x%x (after %d ms)\n", ctrl, cnt);
5877         return cnt;
5878 }
5879
5880 static void bnx2x_link_int_enable(struct link_params *params)
5881 {
5882         u8 port = params->port;
5883         u32 mask;
5884         struct bnx2x *bp = params->bp;
5885
5886         /* Setting the status to report on link up for either XGXS or SerDes */
5887         if (CHIP_IS_E3(bp)) {
5888                 mask = NIG_MASK_XGXS0_LINK_STATUS;
5889                 if (!(SINGLE_MEDIA_DIRECT(params)))
5890                         mask |= NIG_MASK_MI_INT;
5891         } else if (params->switch_cfg == SWITCH_CFG_10G) {
5892                 mask = (NIG_MASK_XGXS0_LINK10G |
5893                         NIG_MASK_XGXS0_LINK_STATUS);
5894                 DP(NETIF_MSG_LINK, "enabled XGXS interrupt\n");
5895                 if (!(SINGLE_MEDIA_DIRECT(params)) &&
5896                         params->phy[INT_PHY].type !=
5897                                 PORT_HW_CFG_XGXS_EXT_PHY_TYPE_FAILURE) {
5898                         mask |= NIG_MASK_MI_INT;
5899                         DP(NETIF_MSG_LINK, "enabled external phy int\n");
5900                 }
5901
5902         } else { /* SerDes */
5903                 mask = NIG_MASK_SERDES0_LINK_STATUS;
5904                 DP(NETIF_MSG_LINK, "enabled SerDes interrupt\n");
5905                 if (!(SINGLE_MEDIA_DIRECT(params)) &&
5906                         params->phy[INT_PHY].type !=
5907                                 PORT_HW_CFG_SERDES_EXT_PHY_TYPE_NOT_CONN) {
5908                         mask |= NIG_MASK_MI_INT;
5909                         DP(NETIF_MSG_LINK, "enabled external phy int\n");
5910                 }
5911         }
5912         bnx2x_bits_en(bp,
5913                       NIG_REG_MASK_INTERRUPT_PORT0 + port*4,
5914                       mask);
5915
5916         DP(NETIF_MSG_LINK, "port %x, is_xgxs %x, int_status 0x%x\n", port,
5917                  (params->switch_cfg == SWITCH_CFG_10G),
5918                  REG_RD(bp, NIG_REG_STATUS_INTERRUPT_PORT0 + port*4));
5919         DP(NETIF_MSG_LINK, " int_mask 0x%x, MI_INT %x, SERDES_LINK %x\n",
5920                  REG_RD(bp, NIG_REG_MASK_INTERRUPT_PORT0 + port*4),
5921                  REG_RD(bp, NIG_REG_EMAC0_STATUS_MISC_MI_INT + port*0x18),
5922                  REG_RD(bp, NIG_REG_SERDES0_STATUS_LINK_STATUS+port*0x3c));
5923         DP(NETIF_MSG_LINK, " 10G %x, XGXS_LINK %x\n",
5924            REG_RD(bp, NIG_REG_XGXS0_STATUS_LINK10G + port*0x68),
5925            REG_RD(bp, NIG_REG_XGXS0_STATUS_LINK_STATUS + port*0x68));
5926 }
5927
5928 static void bnx2x_rearm_latch_signal(struct bnx2x *bp, u8 port,
5929                                      u8 exp_mi_int)
5930 {
5931         u32 latch_status = 0;
5932
5933         /*
5934          * Disable the MI INT ( external phy int ) by writing 1 to the
5935          * status register. Link down indication is high-active-signal,
5936          * so in this case we need to write the status to clear the XOR
5937          */
5938         /* Read Latched signals */
5939         latch_status = REG_RD(bp,
5940                                     NIG_REG_LATCH_STATUS_0 + port*8);
5941         DP(NETIF_MSG_LINK, "latch_status = 0x%x\n", latch_status);
5942         /* Handle only those with latched-signal=up.*/
5943         if (exp_mi_int)
5944                 bnx2x_bits_en(bp,
5945                               NIG_REG_STATUS_INTERRUPT_PORT0
5946                               + port*4,
5947                               NIG_STATUS_EMAC0_MI_INT);
5948         else
5949                 bnx2x_bits_dis(bp,
5950                                NIG_REG_STATUS_INTERRUPT_PORT0
5951                                + port*4,
5952                                NIG_STATUS_EMAC0_MI_INT);
5953
5954         if (latch_status & 1) {
5955
5956                 /* For all latched-signal=up : Re-Arm Latch signals */
5957                 REG_WR(bp, NIG_REG_LATCH_STATUS_0 + port*8,
5958                        (latch_status & 0xfffe) | (latch_status & 1));
5959         }
5960         /* For all latched-signal=up,Write original_signal to status */
5961 }
5962
5963 static void bnx2x_link_int_ack(struct link_params *params,
5964                                struct link_vars *vars, u8 is_10g_plus)
5965 {
5966         struct bnx2x *bp = params->bp;
5967         u8 port = params->port;
5968         u32 mask;
5969         /*
5970          * First reset all status we assume only one line will be
5971          * change at a time
5972          */
5973         bnx2x_bits_dis(bp, NIG_REG_STATUS_INTERRUPT_PORT0 + port*4,
5974                        (NIG_STATUS_XGXS0_LINK10G |
5975                         NIG_STATUS_XGXS0_LINK_STATUS |
5976                         NIG_STATUS_SERDES0_LINK_STATUS));
5977         if (vars->phy_link_up) {
5978                 if (USES_WARPCORE(bp))
5979                         mask = NIG_STATUS_XGXS0_LINK_STATUS;
5980                 else {
5981                         if (is_10g_plus)
5982                                 mask = NIG_STATUS_XGXS0_LINK10G;
5983                         else if (params->switch_cfg == SWITCH_CFG_10G) {
5984                                 /*
5985                                  * Disable the link interrupt by writing 1 to
5986                                  * the relevant lane in the status register
5987                                  */
5988                                 u32 ser_lane =
5989                                         ((params->lane_config &
5990                                     PORT_HW_CFG_LANE_SWAP_CFG_MASTER_MASK) >>
5991                                     PORT_HW_CFG_LANE_SWAP_CFG_MASTER_SHIFT);
5992                                 mask = ((1 << ser_lane) <<
5993                                        NIG_STATUS_XGXS0_LINK_STATUS_SIZE);
5994                         } else
5995                                 mask = NIG_STATUS_SERDES0_LINK_STATUS;
5996                 }
5997                 DP(NETIF_MSG_LINK, "Ack link up interrupt with mask 0x%x\n",
5998                                mask);
5999                 bnx2x_bits_en(bp,
6000                               NIG_REG_STATUS_INTERRUPT_PORT0 + port*4,
6001                               mask);
6002         }
6003 }
6004
6005 static int bnx2x_format_ver(u32 num, u8 *str, u16 *len)
6006 {
6007         u8 *str_ptr = str;
6008         u32 mask = 0xf0000000;
6009         u8 shift = 8*4;
6010         u8 digit;
6011         u8 remove_leading_zeros = 1;
6012         if (*len < 10) {
6013                 /* Need more than 10chars for this format */
6014                 *str_ptr = '\0';
6015                 (*len)--;
6016                 return -EINVAL;
6017         }
6018         while (shift > 0) {
6019
6020                 shift -= 4;
6021                 digit = ((num & mask) >> shift);
6022                 if (digit == 0 && remove_leading_zeros) {
6023                         mask = mask >> 4;
6024                         continue;
6025                 } else if (digit < 0xa)
6026                         *str_ptr = digit + '0';
6027                 else
6028                         *str_ptr = digit - 0xa + 'a';
6029                 remove_leading_zeros = 0;
6030                 str_ptr++;
6031                 (*len)--;
6032                 mask = mask >> 4;
6033                 if (shift == 4*4) {
6034                         *str_ptr = '.';
6035                         str_ptr++;
6036                         (*len)--;
6037                         remove_leading_zeros = 1;
6038                 }
6039         }
6040         return 0;
6041 }
6042
6043
6044 static int bnx2x_null_format_ver(u32 spirom_ver, u8 *str, u16 *len)
6045 {
6046         str[0] = '\0';
6047         (*len)--;
6048         return 0;
6049 }
6050
6051 int bnx2x_get_ext_phy_fw_version(struct link_params *params, u8 *version,
6052                                  u16 len)
6053 {
6054         struct bnx2x *bp;
6055         u32 spirom_ver = 0;
6056         int status = 0;
6057         u8 *ver_p = version;
6058         u16 remain_len = len;
6059         if (version == NULL || params == NULL)
6060                 return -EINVAL;
6061         bp = params->bp;
6062
6063         /* Extract first external phy*/
6064         version[0] = '\0';
6065         spirom_ver = REG_RD(bp, params->phy[EXT_PHY1].ver_addr);
6066
6067         if (params->phy[EXT_PHY1].format_fw_ver) {
6068                 status |= params->phy[EXT_PHY1].format_fw_ver(spirom_ver,
6069                                                               ver_p,
6070                                                               &remain_len);
6071                 ver_p += (len - remain_len);
6072         }
6073         if ((params->num_phys == MAX_PHYS) &&
6074             (params->phy[EXT_PHY2].ver_addr != 0)) {
6075                 spirom_ver = REG_RD(bp, params->phy[EXT_PHY2].ver_addr);
6076                 if (params->phy[EXT_PHY2].format_fw_ver) {
6077                         *ver_p = '/';
6078                         ver_p++;
6079                         remain_len--;
6080                         status |= params->phy[EXT_PHY2].format_fw_ver(
6081                                 spirom_ver,
6082                                 ver_p,
6083                                 &remain_len);
6084                         ver_p = version + (len - remain_len);
6085                 }
6086         }
6087         *ver_p = '\0';
6088         return status;
6089 }
6090
6091 static void bnx2x_set_xgxs_loopback(struct bnx2x_phy *phy,
6092                                     struct link_params *params)
6093 {
6094         u8 port = params->port;
6095         struct bnx2x *bp = params->bp;
6096
6097         if (phy->req_line_speed != SPEED_1000) {
6098                 u32 md_devad = 0;
6099
6100                 DP(NETIF_MSG_LINK, "XGXS 10G loopback enable\n");
6101
6102                 if (!CHIP_IS_E3(bp)) {
6103                         /* change the uni_phy_addr in the nig */
6104                         md_devad = REG_RD(bp, (NIG_REG_XGXS0_CTRL_MD_DEVAD +
6105                                                port*0x18));
6106
6107                         REG_WR(bp, NIG_REG_XGXS0_CTRL_MD_DEVAD + port*0x18,
6108                                0x5);
6109                 }
6110
6111                 bnx2x_cl45_write(bp, phy,
6112                                  5,
6113                                  (MDIO_REG_BANK_AER_BLOCK +
6114                                   (MDIO_AER_BLOCK_AER_REG & 0xf)),
6115                                  0x2800);
6116
6117                 bnx2x_cl45_write(bp, phy,
6118                                  5,
6119                                  (MDIO_REG_BANK_CL73_IEEEB0 +
6120                                   (MDIO_CL73_IEEEB0_CL73_AN_CONTROL & 0xf)),
6121                                  0x6041);
6122                 msleep(200);
6123                 /* set aer mmd back */
6124                 bnx2x_set_aer_mmd(params, phy);
6125
6126                 if (!CHIP_IS_E3(bp)) {
6127                         /* and md_devad */
6128                         REG_WR(bp, NIG_REG_XGXS0_CTRL_MD_DEVAD + port*0x18,
6129                                md_devad);
6130                 }
6131         } else {
6132                 u16 mii_ctrl;
6133                 DP(NETIF_MSG_LINK, "XGXS 1G loopback enable\n");
6134                 bnx2x_cl45_read(bp, phy, 5,
6135                                 (MDIO_REG_BANK_COMBO_IEEE0 +
6136                                 (MDIO_COMBO_IEEE0_MII_CONTROL & 0xf)),
6137                                 &mii_ctrl);
6138                 bnx2x_cl45_write(bp, phy, 5,
6139                                  (MDIO_REG_BANK_COMBO_IEEE0 +
6140                                  (MDIO_COMBO_IEEE0_MII_CONTROL & 0xf)),
6141                                  mii_ctrl |
6142                                  MDIO_COMBO_IEEO_MII_CONTROL_LOOPBACK);
6143         }
6144 }
6145
6146 int bnx2x_set_led(struct link_params *params,
6147                   struct link_vars *vars, u8 mode, u32 speed)
6148 {
6149         u8 port = params->port;
6150         u16 hw_led_mode = params->hw_led_mode;
6151         int rc = 0;
6152         u8 phy_idx;
6153         u32 tmp;
6154         u32 emac_base = port ? GRCBASE_EMAC1 : GRCBASE_EMAC0;
6155         struct bnx2x *bp = params->bp;
6156         DP(NETIF_MSG_LINK, "bnx2x_set_led: port %x, mode %d\n", port, mode);
6157         DP(NETIF_MSG_LINK, "speed 0x%x, hw_led_mode 0x%x\n",
6158                  speed, hw_led_mode);
6159         /* In case */
6160         for (phy_idx = EXT_PHY1; phy_idx < MAX_PHYS; phy_idx++) {
6161                 if (params->phy[phy_idx].set_link_led) {
6162                         params->phy[phy_idx].set_link_led(
6163                                 &params->phy[phy_idx], params, mode);
6164                 }
6165         }
6166
6167         switch (mode) {
6168         case LED_MODE_FRONT_PANEL_OFF:
6169         case LED_MODE_OFF:
6170                 REG_WR(bp, NIG_REG_LED_10G_P0 + port*4, 0);
6171                 REG_WR(bp, NIG_REG_LED_MODE_P0 + port*4,
6172                        SHARED_HW_CFG_LED_MAC1);
6173
6174                 tmp = EMAC_RD(bp, EMAC_REG_EMAC_LED);
6175                 if (params->phy[EXT_PHY1].type ==
6176                           PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM54618SE)
6177                         EMAC_WR(bp, EMAC_REG_EMAC_LED, tmp & 0xfff1);
6178                 else {
6179                         EMAC_WR(bp, EMAC_REG_EMAC_LED,
6180                                 (tmp | EMAC_LED_OVERRIDE));
6181                 }
6182                 break;
6183
6184         case LED_MODE_OPER:
6185                 /*
6186                  * For all other phys, OPER mode is same as ON, so in case
6187                  * link is down, do nothing
6188                  */
6189                 if (!vars->link_up)
6190                         break;
6191         case LED_MODE_ON:
6192                 if (((params->phy[EXT_PHY1].type ==
6193                           PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8727) ||
6194                          (params->phy[EXT_PHY1].type ==
6195                           PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8722)) &&
6196                     CHIP_IS_E2(bp) && params->num_phys == 2) {
6197                         /*
6198                          * This is a work-around for E2+8727 Configurations
6199                          */
6200                         if (mode == LED_MODE_ON ||
6201                                 speed == SPEED_10000){
6202                                 REG_WR(bp, NIG_REG_LED_MODE_P0 + port*4, 0);
6203                                 REG_WR(bp, NIG_REG_LED_10G_P0 + port*4, 1);
6204
6205                                 tmp = EMAC_RD(bp, EMAC_REG_EMAC_LED);
6206                                 EMAC_WR(bp, EMAC_REG_EMAC_LED,
6207                                         (tmp | EMAC_LED_OVERRIDE));
6208                                 /*
6209                                  * return here without enabling traffic
6210                                  * LED blink and setting rate in ON mode.
6211                                  * In oper mode, enabling LED blink
6212                                  * and setting rate is needed.
6213                                  */
6214                                 if (mode == LED_MODE_ON)
6215                                         return rc;
6216                         }
6217                 } else if (SINGLE_MEDIA_DIRECT(params)) {
6218                         /*
6219                          * This is a work-around for HW issue found when link
6220                          * is up in CL73
6221                          */
6222                         if ((!CHIP_IS_E3(bp)) ||
6223                             (CHIP_IS_E3(bp) &&
6224                              mode == LED_MODE_ON))
6225                                 REG_WR(bp, NIG_REG_LED_10G_P0 + port*4, 1);
6226
6227                         if (CHIP_IS_E1x(bp) ||
6228                             CHIP_IS_E2(bp) ||
6229                             (mode == LED_MODE_ON))
6230                                 REG_WR(bp, NIG_REG_LED_MODE_P0 + port*4, 0);
6231                         else
6232                                 REG_WR(bp, NIG_REG_LED_MODE_P0 + port*4,
6233                                        hw_led_mode);
6234                 } else if ((params->phy[EXT_PHY1].type ==
6235                             PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM54618SE) &&
6236                            (mode != LED_MODE_OPER)) {
6237                         REG_WR(bp, NIG_REG_LED_MODE_P0 + port*4, 0);
6238                         tmp = EMAC_RD(bp, EMAC_REG_EMAC_LED);
6239                         EMAC_WR(bp, EMAC_REG_EMAC_LED, tmp | 0x3);
6240                 } else
6241                         REG_WR(bp, NIG_REG_LED_MODE_P0 + port*4,
6242                                hw_led_mode);
6243
6244                 REG_WR(bp, NIG_REG_LED_CONTROL_OVERRIDE_TRAFFIC_P0 + port*4, 0);
6245                 /* Set blinking rate to ~15.9Hz */
6246                 if (CHIP_IS_E3(bp))
6247                         REG_WR(bp, NIG_REG_LED_CONTROL_BLINK_RATE_P0 + port*4,
6248                                LED_BLINK_RATE_VAL_E3);
6249                 else
6250                         REG_WR(bp, NIG_REG_LED_CONTROL_BLINK_RATE_P0 + port*4,
6251                                LED_BLINK_RATE_VAL_E1X_E2);
6252                 REG_WR(bp, NIG_REG_LED_CONTROL_BLINK_RATE_ENA_P0 +
6253                        port*4, 1);
6254                 if ((params->phy[EXT_PHY1].type !=
6255                      PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM54618SE) &&
6256                     (mode != LED_MODE_OPER)) {
6257                         tmp = EMAC_RD(bp, EMAC_REG_EMAC_LED);
6258                         EMAC_WR(bp, EMAC_REG_EMAC_LED,
6259                                 (tmp & (~EMAC_LED_OVERRIDE)));
6260                 }
6261
6262                 if (CHIP_IS_E1(bp) &&
6263                     ((speed == SPEED_2500) ||
6264                      (speed == SPEED_1000) ||
6265                      (speed == SPEED_100) ||
6266                      (speed == SPEED_10))) {
6267                         /*
6268                          * On Everest 1 Ax chip versions for speeds less than
6269                          * 10G LED scheme is different
6270                          */
6271                         REG_WR(bp, NIG_REG_LED_CONTROL_OVERRIDE_TRAFFIC_P0
6272                                + port*4, 1);
6273                         REG_WR(bp, NIG_REG_LED_CONTROL_TRAFFIC_P0 +
6274                                port*4, 0);
6275                         REG_WR(bp, NIG_REG_LED_CONTROL_BLINK_TRAFFIC_P0 +
6276                                port*4, 1);
6277                 }
6278                 break;
6279
6280         default:
6281                 rc = -EINVAL;
6282                 DP(NETIF_MSG_LINK, "bnx2x_set_led: Invalid led mode %d\n",
6283                          mode);
6284                 break;
6285         }
6286         return rc;
6287
6288 }
6289
6290 /*
6291  * This function comes to reflect the actual link state read DIRECTLY from the
6292  * HW
6293  */
6294 int bnx2x_test_link(struct link_params *params, struct link_vars *vars,
6295                     u8 is_serdes)
6296 {
6297         struct bnx2x *bp = params->bp;
6298         u16 gp_status = 0, phy_index = 0;
6299         u8 ext_phy_link_up = 0, serdes_phy_type;
6300         struct link_vars temp_vars;
6301         struct bnx2x_phy *int_phy = &params->phy[INT_PHY];
6302
6303         if (CHIP_IS_E3(bp)) {
6304                 u16 link_up;
6305                 if (params->req_line_speed[LINK_CONFIG_IDX(INT_PHY)]
6306                     > SPEED_10000) {
6307                         /* Check 20G link */
6308                         bnx2x_cl45_read(bp, int_phy, MDIO_WC_DEVAD,
6309                                         1, &link_up);
6310                         bnx2x_cl45_read(bp, int_phy, MDIO_WC_DEVAD,
6311                                         1, &link_up);
6312                         link_up &= (1<<2);
6313                 } else {
6314                         /* Check 10G link and below*/
6315                         u8 lane = bnx2x_get_warpcore_lane(int_phy, params);
6316                         bnx2x_cl45_read(bp, int_phy, MDIO_WC_DEVAD,
6317                                         MDIO_WC_REG_GP2_STATUS_GP_2_1,
6318                                         &gp_status);
6319                         gp_status = ((gp_status >> 8) & 0xf) |
6320                                 ((gp_status >> 12) & 0xf);
6321                         link_up = gp_status & (1 << lane);
6322                 }
6323                 if (!link_up)
6324                         return -ESRCH;
6325         } else {
6326                 CL22_RD_OVER_CL45(bp, int_phy,
6327                           MDIO_REG_BANK_GP_STATUS,
6328                           MDIO_GP_STATUS_TOP_AN_STATUS1,
6329                           &gp_status);
6330         /* link is up only if both local phy and external phy are up */
6331         if (!(gp_status & MDIO_GP_STATUS_TOP_AN_STATUS1_LINK_STATUS))
6332                 return -ESRCH;
6333         }
6334         /* In XGXS loopback mode, do not check external PHY */
6335         if (params->loopback_mode == LOOPBACK_XGXS)
6336                 return 0;
6337
6338         switch (params->num_phys) {
6339         case 1:
6340                 /* No external PHY */
6341                 return 0;
6342         case 2:
6343                 ext_phy_link_up = params->phy[EXT_PHY1].read_status(
6344                         &params->phy[EXT_PHY1],
6345                         params, &temp_vars);
6346                 break;
6347         case 3: /* Dual Media */
6348                 for (phy_index = EXT_PHY1; phy_index < params->num_phys;
6349                       phy_index++) {
6350                         serdes_phy_type = ((params->phy[phy_index].media_type ==
6351                                             ETH_PHY_SFP_FIBER) ||
6352                                            (params->phy[phy_index].media_type ==
6353                                             ETH_PHY_XFP_FIBER) ||
6354                                            (params->phy[phy_index].media_type ==
6355                                             ETH_PHY_DA_TWINAX));
6356
6357                         if (is_serdes != serdes_phy_type)
6358                                 continue;
6359                         if (params->phy[phy_index].read_status) {
6360                                 ext_phy_link_up |=
6361                                         params->phy[phy_index].read_status(
6362                                                 &params->phy[phy_index],
6363                                                 params, &temp_vars);
6364                         }
6365                 }
6366                 break;
6367         }
6368         if (ext_phy_link_up)
6369                 return 0;
6370         return -ESRCH;
6371 }
6372
6373 static int bnx2x_link_initialize(struct link_params *params,
6374                                  struct link_vars *vars)
6375 {
6376         int rc = 0;
6377         u8 phy_index, non_ext_phy;
6378         struct bnx2x *bp = params->bp;
6379         /*
6380          * In case of external phy existence, the line speed would be the
6381          * line speed linked up by the external phy. In case it is direct
6382          * only, then the line_speed during initialization will be
6383          * equal to the req_line_speed
6384          */
6385         vars->line_speed = params->phy[INT_PHY].req_line_speed;
6386
6387         /*
6388          * Initialize the internal phy in case this is a direct board
6389          * (no external phys), or this board has external phy which requires
6390          * to first.
6391          */
6392         if (!USES_WARPCORE(bp))
6393                 bnx2x_prepare_xgxs(&params->phy[INT_PHY], params, vars);
6394         /* init ext phy and enable link state int */
6395         non_ext_phy = (SINGLE_MEDIA_DIRECT(params) ||
6396                        (params->loopback_mode == LOOPBACK_XGXS));
6397
6398         if (non_ext_phy ||
6399             (params->phy[EXT_PHY1].flags & FLAGS_INIT_XGXS_FIRST) ||
6400             (params->loopback_mode == LOOPBACK_EXT_PHY)) {
6401                 struct bnx2x_phy *phy = &params->phy[INT_PHY];
6402                 if (vars->line_speed == SPEED_AUTO_NEG &&
6403                     (CHIP_IS_E1x(bp) ||
6404                      CHIP_IS_E2(bp)))
6405                         bnx2x_set_parallel_detection(phy, params);
6406                         if (params->phy[INT_PHY].config_init)
6407                                 params->phy[INT_PHY].config_init(phy,
6408                                                                  params,
6409                                                                  vars);
6410         }
6411
6412         /* Init external phy*/
6413         if (non_ext_phy) {
6414                 if (params->phy[INT_PHY].supported &
6415                     SUPPORTED_FIBRE)
6416                         vars->link_status |= LINK_STATUS_SERDES_LINK;
6417         } else {
6418                 for (phy_index = EXT_PHY1; phy_index < params->num_phys;
6419                       phy_index++) {
6420                         /*
6421                          * No need to initialize second phy in case of first
6422                          * phy only selection. In case of second phy, we do
6423                          * need to initialize the first phy, since they are
6424                          * connected.
6425                          */
6426                         if (params->phy[phy_index].supported &
6427                             SUPPORTED_FIBRE)
6428                                 vars->link_status |= LINK_STATUS_SERDES_LINK;
6429
6430                         if (phy_index == EXT_PHY2 &&
6431                             (bnx2x_phy_selection(params) ==
6432                              PORT_HW_CFG_PHY_SELECTION_FIRST_PHY)) {
6433                                 DP(NETIF_MSG_LINK,
6434                                    "Not initializing second phy\n");
6435                                 continue;
6436                         }
6437                         params->phy[phy_index].config_init(
6438                                 &params->phy[phy_index],
6439                                 params, vars);
6440                 }
6441         }
6442         /* Reset the interrupt indication after phy was initialized */
6443         bnx2x_bits_dis(bp, NIG_REG_STATUS_INTERRUPT_PORT0 +
6444                        params->port*4,
6445                        (NIG_STATUS_XGXS0_LINK10G |
6446                         NIG_STATUS_XGXS0_LINK_STATUS |
6447                         NIG_STATUS_SERDES0_LINK_STATUS |
6448                         NIG_MASK_MI_INT));
6449         bnx2x_update_mng(params, vars->link_status);
6450         return rc;
6451 }
6452
6453 static void bnx2x_int_link_reset(struct bnx2x_phy *phy,
6454                                  struct link_params *params)
6455 {
6456         /* reset the SerDes/XGXS */
6457         REG_WR(params->bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_3_CLEAR,
6458                (0x1ff << (params->port*16)));
6459 }
6460
6461 static void bnx2x_common_ext_link_reset(struct bnx2x_phy *phy,
6462                                         struct link_params *params)
6463 {
6464         struct bnx2x *bp = params->bp;
6465         u8 gpio_port;
6466         /* HW reset */
6467         if (CHIP_IS_E2(bp))
6468                 gpio_port = BP_PATH(bp);
6469         else
6470                 gpio_port = params->port;
6471         bnx2x_set_gpio(bp, MISC_REGISTERS_GPIO_1,
6472                        MISC_REGISTERS_GPIO_OUTPUT_LOW,
6473                        gpio_port);
6474         bnx2x_set_gpio(bp, MISC_REGISTERS_GPIO_2,
6475                        MISC_REGISTERS_GPIO_OUTPUT_LOW,
6476                        gpio_port);
6477         DP(NETIF_MSG_LINK, "reset external PHY\n");
6478 }
6479
6480 static int bnx2x_update_link_down(struct link_params *params,
6481                                   struct link_vars *vars)
6482 {
6483         struct bnx2x *bp = params->bp;
6484         u8 port = params->port;
6485
6486         DP(NETIF_MSG_LINK, "Port %x: Link is down\n", port);
6487         bnx2x_set_led(params, vars, LED_MODE_OFF, 0);
6488         vars->phy_flags &= ~PHY_PHYSICAL_LINK_FLAG;
6489         /* indicate no mac active */
6490         vars->mac_type = MAC_TYPE_NONE;
6491
6492         /* update shared memory */
6493         vars->link_status &= ~(LINK_STATUS_SPEED_AND_DUPLEX_MASK |
6494                                LINK_STATUS_LINK_UP |
6495                                LINK_STATUS_PHYSICAL_LINK_FLAG |
6496                                LINK_STATUS_AUTO_NEGOTIATE_COMPLETE |
6497                                LINK_STATUS_RX_FLOW_CONTROL_FLAG_MASK |
6498                                LINK_STATUS_TX_FLOW_CONTROL_FLAG_MASK |
6499                                LINK_STATUS_PARALLEL_DETECTION_FLAG_MASK |
6500                                LINK_STATUS_LINK_PARTNER_SYMMETRIC_PAUSE |
6501                                LINK_STATUS_LINK_PARTNER_ASYMMETRIC_PAUSE);
6502         vars->line_speed = 0;
6503         bnx2x_update_mng(params, vars->link_status);
6504
6505         /* activate nig drain */
6506         REG_WR(bp, NIG_REG_EGRESS_DRAIN0_MODE + port*4, 1);
6507
6508         /* disable emac */
6509         if (!CHIP_IS_E3(bp))
6510                 REG_WR(bp, NIG_REG_NIG_EMAC0_EN + port*4, 0);
6511
6512         msleep(10);
6513         /* reset BigMac/Xmac */
6514         if (CHIP_IS_E1x(bp) ||
6515             CHIP_IS_E2(bp)) {
6516                 bnx2x_bmac_rx_disable(bp, params->port);
6517                 REG_WR(bp, GRCBASE_MISC +
6518                        MISC_REGISTERS_RESET_REG_2_CLEAR,
6519                (MISC_REGISTERS_RESET_REG_2_RST_BMAC0 << port));
6520         }
6521         if (CHIP_IS_E3(bp)) {
6522                 bnx2x_xmac_disable(params);
6523                 bnx2x_umac_disable(params);
6524         }
6525
6526         return 0;
6527 }
6528
6529 static int bnx2x_update_link_up(struct link_params *params,
6530                                 struct link_vars *vars,
6531                                 u8 link_10g)
6532 {
6533         struct bnx2x *bp = params->bp;
6534         u8 port = params->port;
6535         int rc = 0;
6536
6537         vars->link_status |= (LINK_STATUS_LINK_UP |
6538                               LINK_STATUS_PHYSICAL_LINK_FLAG);
6539         vars->phy_flags |= PHY_PHYSICAL_LINK_FLAG;
6540
6541         if (vars->flow_ctrl & BNX2X_FLOW_CTRL_TX)
6542                 vars->link_status |=
6543                         LINK_STATUS_TX_FLOW_CONTROL_ENABLED;
6544
6545         if (vars->flow_ctrl & BNX2X_FLOW_CTRL_RX)
6546                 vars->link_status |=
6547                         LINK_STATUS_RX_FLOW_CONTROL_ENABLED;
6548         if (USES_WARPCORE(bp)) {
6549                 if (link_10g) {
6550                         if (bnx2x_xmac_enable(params, vars, 0) ==
6551                             -ESRCH) {
6552                                 DP(NETIF_MSG_LINK, "Found errors on XMAC\n");
6553                                 vars->link_up = 0;
6554                                 vars->phy_flags |= PHY_HALF_OPEN_CONN_FLAG;
6555                                 vars->link_status &= ~LINK_STATUS_LINK_UP;
6556                         }
6557                 } else
6558                         bnx2x_umac_enable(params, vars, 0);
6559                 bnx2x_set_led(params, vars,
6560                               LED_MODE_OPER, vars->line_speed);
6561         }
6562         if ((CHIP_IS_E1x(bp) ||
6563              CHIP_IS_E2(bp))) {
6564                 if (link_10g) {
6565                         if (bnx2x_bmac_enable(params, vars, 0) ==
6566                             -ESRCH) {
6567                                 DP(NETIF_MSG_LINK, "Found errors on BMAC\n");
6568                                 vars->link_up = 0;
6569                                 vars->phy_flags |= PHY_HALF_OPEN_CONN_FLAG;
6570                                 vars->link_status &= ~LINK_STATUS_LINK_UP;
6571                         }
6572
6573                         bnx2x_set_led(params, vars,
6574                                       LED_MODE_OPER, SPEED_10000);
6575                 } else {
6576                         rc = bnx2x_emac_program(params, vars);
6577                         bnx2x_emac_enable(params, vars, 0);
6578
6579                         /* AN complete? */
6580                         if ((vars->link_status &
6581                              LINK_STATUS_AUTO_NEGOTIATE_COMPLETE)
6582                             && (!(vars->phy_flags & PHY_SGMII_FLAG)) &&
6583                             SINGLE_MEDIA_DIRECT(params))
6584                                 bnx2x_set_gmii_tx_driver(params);
6585                 }
6586         }
6587
6588         /* PBF - link up */
6589         if (CHIP_IS_E1x(bp))
6590                 rc |= bnx2x_pbf_update(params, vars->flow_ctrl,
6591                                        vars->line_speed);
6592
6593         /* disable drain */
6594         REG_WR(bp, NIG_REG_EGRESS_DRAIN0_MODE + port*4, 0);
6595
6596         /* update shared memory */
6597         bnx2x_update_mng(params, vars->link_status);
6598         msleep(20);
6599         return rc;
6600 }
6601 /*
6602  * The bnx2x_link_update function should be called upon link
6603  * interrupt.
6604  * Link is considered up as follows:
6605  * - DIRECT_SINGLE_MEDIA - Only XGXS link (internal link) needs
6606  *   to be up
6607  * - SINGLE_MEDIA - The link between the 577xx and the external
6608  *   phy (XGXS) need to up as well as the external link of the
6609  *   phy (PHY_EXT1)
6610  * - DUAL_MEDIA - The link between the 577xx and the first
6611  *   external phy needs to be up, and at least one of the 2
6612  *   external phy link must be up.
6613  */
6614 int bnx2x_link_update(struct link_params *params, struct link_vars *vars)
6615 {
6616         struct bnx2x *bp = params->bp;
6617         struct link_vars phy_vars[MAX_PHYS];
6618         u8 port = params->port;
6619         u8 link_10g_plus, phy_index;
6620         u8 ext_phy_link_up = 0, cur_link_up;
6621         int rc = 0;
6622         u8 is_mi_int = 0;
6623         u16 ext_phy_line_speed = 0, prev_line_speed = vars->line_speed;
6624         u8 active_external_phy = INT_PHY;
6625         vars->phy_flags &= ~PHY_HALF_OPEN_CONN_FLAG;
6626         for (phy_index = INT_PHY; phy_index < params->num_phys;
6627               phy_index++) {
6628                 phy_vars[phy_index].flow_ctrl = 0;
6629                 phy_vars[phy_index].link_status = 0;
6630                 phy_vars[phy_index].line_speed = 0;
6631                 phy_vars[phy_index].duplex = DUPLEX_FULL;
6632                 phy_vars[phy_index].phy_link_up = 0;
6633                 phy_vars[phy_index].link_up = 0;
6634                 phy_vars[phy_index].fault_detected = 0;
6635         }
6636
6637         if (USES_WARPCORE(bp))
6638                 bnx2x_set_aer_mmd(params, &params->phy[INT_PHY]);
6639
6640         DP(NETIF_MSG_LINK, "port %x, XGXS?%x, int_status 0x%x\n",
6641                  port, (vars->phy_flags & PHY_XGXS_FLAG),
6642                  REG_RD(bp, NIG_REG_STATUS_INTERRUPT_PORT0 + port*4));
6643
6644         is_mi_int = (u8)(REG_RD(bp, NIG_REG_EMAC0_STATUS_MISC_MI_INT +
6645                                 port*0x18) > 0);
6646         DP(NETIF_MSG_LINK, "int_mask 0x%x MI_INT %x, SERDES_LINK %x\n",
6647                  REG_RD(bp, NIG_REG_MASK_INTERRUPT_PORT0 + port*4),
6648                  is_mi_int,
6649                  REG_RD(bp, NIG_REG_SERDES0_STATUS_LINK_STATUS + port*0x3c));
6650
6651         DP(NETIF_MSG_LINK, " 10G %x, XGXS_LINK %x\n",
6652           REG_RD(bp, NIG_REG_XGXS0_STATUS_LINK10G + port*0x68),
6653           REG_RD(bp, NIG_REG_XGXS0_STATUS_LINK_STATUS + port*0x68));
6654
6655         /* disable emac */
6656         if (!CHIP_IS_E3(bp))
6657                 REG_WR(bp, NIG_REG_NIG_EMAC0_EN + port*4, 0);
6658
6659         /*
6660          * Step 1:
6661          * Check external link change only for external phys, and apply
6662          * priority selection between them in case the link on both phys
6663          * is up. Note that instead of the common vars, a temporary
6664          * vars argument is used since each phy may have different link/
6665          * speed/duplex result
6666          */
6667         for (phy_index = EXT_PHY1; phy_index < params->num_phys;
6668               phy_index++) {
6669                 struct bnx2x_phy *phy = &params->phy[phy_index];
6670                 if (!phy->read_status)
6671                         continue;
6672                 /* Read link status and params of this ext phy */
6673                 cur_link_up = phy->read_status(phy, params,
6674                                                &phy_vars[phy_index]);
6675                 if (cur_link_up) {
6676                         DP(NETIF_MSG_LINK, "phy in index %d link is up\n",
6677                                    phy_index);
6678                 } else {
6679                         DP(NETIF_MSG_LINK, "phy in index %d link is down\n",
6680                                    phy_index);
6681                         continue;
6682                 }
6683
6684                 if (!ext_phy_link_up) {
6685                         ext_phy_link_up = 1;
6686                         active_external_phy = phy_index;
6687                 } else {
6688                         switch (bnx2x_phy_selection(params)) {
6689                         case PORT_HW_CFG_PHY_SELECTION_HARDWARE_DEFAULT:
6690                         case PORT_HW_CFG_PHY_SELECTION_FIRST_PHY_PRIORITY:
6691                         /*
6692                          * In this option, the first PHY makes sure to pass the
6693                          * traffic through itself only.
6694                          * Its not clear how to reset the link on the second phy
6695                          */
6696                                 active_external_phy = EXT_PHY1;
6697                                 break;
6698                         case PORT_HW_CFG_PHY_SELECTION_SECOND_PHY_PRIORITY:
6699                         /*
6700                          * In this option, the first PHY makes sure to pass the
6701                          * traffic through the second PHY.
6702                          */
6703                                 active_external_phy = EXT_PHY2;
6704                                 break;
6705                         default:
6706                         /*
6707                          * Link indication on both PHYs with the following cases
6708                          * is invalid:
6709                          * - FIRST_PHY means that second phy wasn't initialized,
6710                          * hence its link is expected to be down
6711                          * - SECOND_PHY means that first phy should not be able
6712                          * to link up by itself (using configuration)
6713                          * - DEFAULT should be overriden during initialiazation
6714                          */
6715                                 DP(NETIF_MSG_LINK, "Invalid link indication"
6716                                            "mpc=0x%x. DISABLING LINK !!!\n",
6717                                            params->multi_phy_config);
6718                                 ext_phy_link_up = 0;
6719                                 break;
6720                         }
6721                 }
6722         }
6723         prev_line_speed = vars->line_speed;
6724         /*
6725          * Step 2:
6726          * Read the status of the internal phy. In case of
6727          * DIRECT_SINGLE_MEDIA board, this link is the external link,
6728          * otherwise this is the link between the 577xx and the first
6729          * external phy
6730          */
6731         if (params->phy[INT_PHY].read_status)
6732                 params->phy[INT_PHY].read_status(
6733                         &params->phy[INT_PHY],
6734                         params, vars);
6735         /*
6736          * The INT_PHY flow control reside in the vars. This include the
6737          * case where the speed or flow control are not set to AUTO.
6738          * Otherwise, the active external phy flow control result is set
6739          * to the vars. The ext_phy_line_speed is needed to check if the
6740          * speed is different between the internal phy and external phy.
6741          * This case may be result of intermediate link speed change.
6742          */
6743         if (active_external_phy > INT_PHY) {
6744                 vars->flow_ctrl = phy_vars[active_external_phy].flow_ctrl;
6745                 /*
6746                  * Link speed is taken from the XGXS. AN and FC result from
6747                  * the external phy.
6748                  */
6749                 vars->link_status |= phy_vars[active_external_phy].link_status;
6750
6751                 /*
6752                  * if active_external_phy is first PHY and link is up - disable
6753                  * disable TX on second external PHY
6754                  */
6755                 if (active_external_phy == EXT_PHY1) {
6756                         if (params->phy[EXT_PHY2].phy_specific_func) {
6757                                 DP(NETIF_MSG_LINK,
6758                                    "Disabling TX on EXT_PHY2\n");
6759                                 params->phy[EXT_PHY2].phy_specific_func(
6760                                         &params->phy[EXT_PHY2],
6761                                         params, DISABLE_TX);
6762                         }
6763                 }
6764
6765                 ext_phy_line_speed = phy_vars[active_external_phy].line_speed;
6766                 vars->duplex = phy_vars[active_external_phy].duplex;
6767                 if (params->phy[active_external_phy].supported &
6768                     SUPPORTED_FIBRE)
6769                         vars->link_status |= LINK_STATUS_SERDES_LINK;
6770                 else
6771                         vars->link_status &= ~LINK_STATUS_SERDES_LINK;
6772                 DP(NETIF_MSG_LINK, "Active external phy selected: %x\n",
6773                            active_external_phy);
6774         }
6775
6776         for (phy_index = EXT_PHY1; phy_index < params->num_phys;
6777               phy_index++) {
6778                 if (params->phy[phy_index].flags &
6779                     FLAGS_REARM_LATCH_SIGNAL) {
6780                         bnx2x_rearm_latch_signal(bp, port,
6781                                                  phy_index ==
6782                                                  active_external_phy);
6783                         break;
6784                 }
6785         }
6786         DP(NETIF_MSG_LINK, "vars->flow_ctrl = 0x%x, vars->link_status = 0x%x,"
6787                    " ext_phy_line_speed = %d\n", vars->flow_ctrl,
6788                    vars->link_status, ext_phy_line_speed);
6789         /*
6790          * Upon link speed change set the NIG into drain mode. Comes to
6791          * deals with possible FIFO glitch due to clk change when speed
6792          * is decreased without link down indicator
6793          */
6794
6795         if (vars->phy_link_up) {
6796                 if (!(SINGLE_MEDIA_DIRECT(params)) && ext_phy_link_up &&
6797                     (ext_phy_line_speed != vars->line_speed)) {
6798                         DP(NETIF_MSG_LINK, "Internal link speed %d is"
6799                                    " different than the external"
6800                                    " link speed %d\n", vars->line_speed,
6801                                    ext_phy_line_speed);
6802                         vars->phy_link_up = 0;
6803                 } else if (prev_line_speed != vars->line_speed) {
6804                         REG_WR(bp, NIG_REG_EGRESS_DRAIN0_MODE + params->port*4,
6805                                0);
6806                         msleep(1);
6807                 }
6808         }
6809
6810         /* anything 10 and over uses the bmac */
6811         link_10g_plus = (vars->line_speed >= SPEED_10000);
6812
6813         bnx2x_link_int_ack(params, vars, link_10g_plus);
6814
6815         /*
6816          * In case external phy link is up, and internal link is down
6817          * (not initialized yet probably after link initialization, it
6818          * needs to be initialized.
6819          * Note that after link down-up as result of cable plug, the xgxs
6820          * link would probably become up again without the need
6821          * initialize it
6822          */
6823         if (!(SINGLE_MEDIA_DIRECT(params))) {
6824                 DP(NETIF_MSG_LINK, "ext_phy_link_up = %d, int_link_up = %d,"
6825                            " init_preceding = %d\n", ext_phy_link_up,
6826                            vars->phy_link_up,
6827                            params->phy[EXT_PHY1].flags &
6828                            FLAGS_INIT_XGXS_FIRST);
6829                 if (!(params->phy[EXT_PHY1].flags &
6830                       FLAGS_INIT_XGXS_FIRST)
6831                     && ext_phy_link_up && !vars->phy_link_up) {
6832                         vars->line_speed = ext_phy_line_speed;
6833                         if (vars->line_speed < SPEED_1000)
6834                                 vars->phy_flags |= PHY_SGMII_FLAG;
6835                         else
6836                                 vars->phy_flags &= ~PHY_SGMII_FLAG;
6837
6838                         if (params->phy[INT_PHY].config_init)
6839                                 params->phy[INT_PHY].config_init(
6840                                         &params->phy[INT_PHY], params,
6841                                                 vars);
6842                 }
6843         }
6844         /*
6845          * Link is up only if both local phy and external phy (in case of
6846          * non-direct board) are up and no fault detected on active PHY.
6847          */
6848         vars->link_up = (vars->phy_link_up &&
6849                          (ext_phy_link_up ||
6850                           SINGLE_MEDIA_DIRECT(params)) &&
6851                          (phy_vars[active_external_phy].fault_detected == 0));
6852
6853         /* Update the PFC configuration in case it was changed */
6854         if (params->feature_config_flags & FEATURE_CONFIG_PFC_ENABLED)
6855                 vars->link_status |= LINK_STATUS_PFC_ENABLED;
6856         else
6857                 vars->link_status &= ~LINK_STATUS_PFC_ENABLED;
6858
6859         if (vars->link_up)
6860                 rc = bnx2x_update_link_up(params, vars, link_10g_plus);
6861         else
6862                 rc = bnx2x_update_link_down(params, vars);
6863
6864         return rc;
6865 }
6866
6867 /*****************************************************************************/
6868 /*                          External Phy section                             */
6869 /*****************************************************************************/
6870 void bnx2x_ext_phy_hw_reset(struct bnx2x *bp, u8 port)
6871 {
6872         bnx2x_set_gpio(bp, MISC_REGISTERS_GPIO_1,
6873                        MISC_REGISTERS_GPIO_OUTPUT_LOW, port);
6874         msleep(1);
6875         bnx2x_set_gpio(bp, MISC_REGISTERS_GPIO_1,
6876                        MISC_REGISTERS_GPIO_OUTPUT_HIGH, port);
6877 }
6878
6879 static void bnx2x_save_spirom_version(struct bnx2x *bp, u8 port,
6880                                       u32 spirom_ver, u32 ver_addr)
6881 {
6882         DP(NETIF_MSG_LINK, "FW version 0x%x:0x%x for port %d\n",
6883                  (u16)(spirom_ver>>16), (u16)spirom_ver, port);
6884
6885         if (ver_addr)
6886                 REG_WR(bp, ver_addr, spirom_ver);
6887 }
6888
6889 static void bnx2x_save_bcm_spirom_ver(struct bnx2x *bp,
6890                                       struct bnx2x_phy *phy,
6891                                       u8 port)
6892 {
6893         u16 fw_ver1, fw_ver2;
6894
6895         bnx2x_cl45_read(bp, phy, MDIO_PMA_DEVAD,
6896                         MDIO_PMA_REG_ROM_VER1, &fw_ver1);
6897         bnx2x_cl45_read(bp, phy, MDIO_PMA_DEVAD,
6898                         MDIO_PMA_REG_ROM_VER2, &fw_ver2);
6899         bnx2x_save_spirom_version(bp, port, (u32)(fw_ver1<<16 | fw_ver2),
6900                                   phy->ver_addr);
6901 }
6902
6903 static void bnx2x_ext_phy_10G_an_resolve(struct bnx2x *bp,
6904                                        struct bnx2x_phy *phy,
6905                                        struct link_vars *vars)
6906 {
6907         u16 val;
6908         bnx2x_cl45_read(bp, phy,
6909                         MDIO_AN_DEVAD,
6910                         MDIO_AN_REG_STATUS, &val);
6911         bnx2x_cl45_read(bp, phy,
6912                         MDIO_AN_DEVAD,
6913                         MDIO_AN_REG_STATUS, &val);
6914         if (val & (1<<5))
6915                 vars->link_status |= LINK_STATUS_AUTO_NEGOTIATE_COMPLETE;
6916         if ((val & (1<<0)) == 0)
6917                 vars->link_status |= LINK_STATUS_PARALLEL_DETECTION_USED;
6918 }
6919
6920 /******************************************************************/
6921 /*              common BCM8073/BCM8727 PHY SECTION                */
6922 /******************************************************************/
6923 static void bnx2x_8073_resolve_fc(struct bnx2x_phy *phy,
6924                                   struct link_params *params,
6925                                   struct link_vars *vars)
6926 {
6927         struct bnx2x *bp = params->bp;
6928         if (phy->req_line_speed == SPEED_10 ||
6929             phy->req_line_speed == SPEED_100) {
6930                 vars->flow_ctrl = phy->req_flow_ctrl;
6931                 return;
6932         }
6933
6934         if (bnx2x_ext_phy_resolve_fc(phy, params, vars) &&
6935             (vars->flow_ctrl == BNX2X_FLOW_CTRL_NONE)) {
6936                 u16 pause_result;
6937                 u16 ld_pause;           /* local */
6938                 u16 lp_pause;           /* link partner */
6939                 bnx2x_cl45_read(bp, phy,
6940                                 MDIO_AN_DEVAD,
6941                                 MDIO_AN_REG_CL37_FC_LD, &ld_pause);
6942
6943                 bnx2x_cl45_read(bp, phy,
6944                                 MDIO_AN_DEVAD,
6945                                 MDIO_AN_REG_CL37_FC_LP, &lp_pause);
6946                 pause_result = (ld_pause &
6947                                 MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_BOTH) >> 5;
6948                 pause_result |= (lp_pause &
6949                                  MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_BOTH) >> 7;
6950
6951                 bnx2x_pause_resolve(vars, pause_result);
6952                 DP(NETIF_MSG_LINK, "Ext PHY CL37 pause result 0x%x\n",
6953                            pause_result);
6954         }
6955 }
6956 static int bnx2x_8073_8727_external_rom_boot(struct bnx2x *bp,
6957                                              struct bnx2x_phy *phy,
6958                                              u8 port)
6959 {
6960         u32 count = 0;
6961         u16 fw_ver1, fw_msgout;
6962         int rc = 0;
6963
6964         /* Boot port from external ROM  */
6965         /* EDC grst */
6966         bnx2x_cl45_write(bp, phy,
6967                          MDIO_PMA_DEVAD,
6968                          MDIO_PMA_REG_GEN_CTRL,
6969                          0x0001);
6970
6971         /* ucode reboot and rst */
6972         bnx2x_cl45_write(bp, phy,
6973                          MDIO_PMA_DEVAD,
6974                          MDIO_PMA_REG_GEN_CTRL,
6975                          0x008c);
6976
6977         bnx2x_cl45_write(bp, phy,
6978                          MDIO_PMA_DEVAD,
6979                          MDIO_PMA_REG_MISC_CTRL1, 0x0001);
6980
6981         /* Reset internal microprocessor */
6982         bnx2x_cl45_write(bp, phy,
6983                          MDIO_PMA_DEVAD,
6984                          MDIO_PMA_REG_GEN_CTRL,
6985                          MDIO_PMA_REG_GEN_CTRL_ROM_MICRO_RESET);
6986
6987         /* Release srst bit */
6988         bnx2x_cl45_write(bp, phy,
6989                          MDIO_PMA_DEVAD,
6990                          MDIO_PMA_REG_GEN_CTRL,
6991                          MDIO_PMA_REG_GEN_CTRL_ROM_RESET_INTERNAL_MP);
6992
6993         /* Delay 100ms per the PHY specifications */
6994         msleep(100);
6995
6996         /* 8073 sometimes taking longer to download */
6997         do {
6998                 count++;
6999                 if (count > 300) {
7000                         DP(NETIF_MSG_LINK,
7001                                  "bnx2x_8073_8727_external_rom_boot port %x:"
7002                                  "Download failed. fw version = 0x%x\n",
7003                                  port, fw_ver1);
7004                         rc = -EINVAL;
7005                         break;
7006                 }
7007
7008                 bnx2x_cl45_read(bp, phy,
7009                                 MDIO_PMA_DEVAD,
7010                                 MDIO_PMA_REG_ROM_VER1, &fw_ver1);
7011                 bnx2x_cl45_read(bp, phy,
7012                                 MDIO_PMA_DEVAD,
7013                                 MDIO_PMA_REG_M8051_MSGOUT_REG, &fw_msgout);
7014
7015                 msleep(1);
7016         } while (fw_ver1 == 0 || fw_ver1 == 0x4321 ||
7017                         ((fw_msgout & 0xff) != 0x03 && (phy->type ==
7018                         PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8073)));
7019
7020         /* Clear ser_boot_ctl bit */
7021         bnx2x_cl45_write(bp, phy,
7022                          MDIO_PMA_DEVAD,
7023                          MDIO_PMA_REG_MISC_CTRL1, 0x0000);
7024         bnx2x_save_bcm_spirom_ver(bp, phy, port);
7025
7026         DP(NETIF_MSG_LINK,
7027                  "bnx2x_8073_8727_external_rom_boot port %x:"
7028                  "Download complete. fw version = 0x%x\n",
7029                  port, fw_ver1);
7030
7031         return rc;
7032 }
7033
7034 /******************************************************************/
7035 /*                      BCM8073 PHY SECTION                       */
7036 /******************************************************************/
7037 static int bnx2x_8073_is_snr_needed(struct bnx2x *bp, struct bnx2x_phy *phy)
7038 {
7039         /* This is only required for 8073A1, version 102 only */
7040         u16 val;
7041
7042         /* Read 8073 HW revision*/
7043         bnx2x_cl45_read(bp, phy,
7044                         MDIO_PMA_DEVAD,
7045                         MDIO_PMA_REG_8073_CHIP_REV, &val);
7046
7047         if (val != 1) {
7048                 /* No need to workaround in 8073 A1 */
7049                 return 0;
7050         }
7051
7052         bnx2x_cl45_read(bp, phy,
7053                         MDIO_PMA_DEVAD,
7054                         MDIO_PMA_REG_ROM_VER2, &val);
7055
7056         /* SNR should be applied only for version 0x102 */
7057         if (val != 0x102)
7058                 return 0;
7059
7060         return 1;
7061 }
7062
7063 static int bnx2x_8073_xaui_wa(struct bnx2x *bp, struct bnx2x_phy *phy)
7064 {
7065         u16 val, cnt, cnt1 ;
7066
7067         bnx2x_cl45_read(bp, phy,
7068                         MDIO_PMA_DEVAD,
7069                         MDIO_PMA_REG_8073_CHIP_REV, &val);
7070
7071         if (val > 0) {
7072                 /* No need to workaround in 8073 A1 */
7073                 return 0;
7074         }
7075         /* XAUI workaround in 8073 A0: */
7076
7077         /*
7078          * After loading the boot ROM and restarting Autoneg, poll
7079          * Dev1, Reg $C820:
7080          */
7081
7082         for (cnt = 0; cnt < 1000; cnt++) {
7083                 bnx2x_cl45_read(bp, phy,
7084                                 MDIO_PMA_DEVAD,
7085                                 MDIO_PMA_REG_8073_SPEED_LINK_STATUS,
7086                                 &val);
7087                   /*
7088                    * If bit [14] = 0 or bit [13] = 0, continue on with
7089                    * system initialization (XAUI work-around not required, as
7090                    * these bits indicate 2.5G or 1G link up).
7091                    */
7092                 if (!(val & (1<<14)) || !(val & (1<<13))) {
7093                         DP(NETIF_MSG_LINK, "XAUI work-around not required\n");
7094                         return 0;
7095                 } else if (!(val & (1<<15))) {
7096                         DP(NETIF_MSG_LINK, "bit 15 went off\n");
7097                         /*
7098                          * If bit 15 is 0, then poll Dev1, Reg $C841 until it's
7099                          * MSB (bit15) goes to 1 (indicating that the XAUI
7100                          * workaround has completed), then continue on with
7101                          * system initialization.
7102                          */
7103                         for (cnt1 = 0; cnt1 < 1000; cnt1++) {
7104                                 bnx2x_cl45_read(bp, phy,
7105                                         MDIO_PMA_DEVAD,
7106                                         MDIO_PMA_REG_8073_XAUI_WA, &val);
7107                                 if (val & (1<<15)) {
7108                                         DP(NETIF_MSG_LINK,
7109                                           "XAUI workaround has completed\n");
7110                                         return 0;
7111                                  }
7112                                  msleep(3);
7113                         }
7114                         break;
7115                 }
7116                 msleep(3);
7117         }
7118         DP(NETIF_MSG_LINK, "Warning: XAUI work-around timeout !!!\n");
7119         return -EINVAL;
7120 }
7121
7122 static void bnx2x_807x_force_10G(struct bnx2x *bp, struct bnx2x_phy *phy)
7123 {
7124         /* Force KR or KX */
7125         bnx2x_cl45_write(bp, phy,
7126                          MDIO_PMA_DEVAD, MDIO_PMA_REG_CTRL, 0x2040);
7127         bnx2x_cl45_write(bp, phy,
7128                          MDIO_PMA_DEVAD, MDIO_PMA_REG_10G_CTRL2, 0x000b);
7129         bnx2x_cl45_write(bp, phy,
7130                          MDIO_PMA_DEVAD, MDIO_PMA_REG_BCM_CTRL, 0x0000);
7131         bnx2x_cl45_write(bp, phy,
7132                          MDIO_AN_DEVAD, MDIO_AN_REG_CTRL, 0x0000);
7133 }
7134
7135 static void bnx2x_8073_set_pause_cl37(struct link_params *params,
7136                                       struct bnx2x_phy *phy,
7137                                       struct link_vars *vars)
7138 {
7139         u16 cl37_val;
7140         struct bnx2x *bp = params->bp;
7141         bnx2x_cl45_read(bp, phy,
7142                         MDIO_AN_DEVAD, MDIO_AN_REG_CL37_FC_LD, &cl37_val);
7143
7144         cl37_val &= ~MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_BOTH;
7145         /* Please refer to Table 28B-3 of 802.3ab-1999 spec. */
7146         bnx2x_calc_ieee_aneg_adv(phy, params, &vars->ieee_fc);
7147         if ((vars->ieee_fc &
7148             MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_SYMMETRIC) ==
7149             MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_SYMMETRIC) {
7150                 cl37_val |=  MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_SYMMETRIC;
7151         }
7152         if ((vars->ieee_fc &
7153             MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_ASYMMETRIC) ==
7154             MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_ASYMMETRIC) {
7155                 cl37_val |=  MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_ASYMMETRIC;
7156         }
7157         if ((vars->ieee_fc &
7158             MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_BOTH) ==
7159             MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_BOTH) {
7160                 cl37_val |= MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_BOTH;
7161         }
7162         DP(NETIF_MSG_LINK,
7163                  "Ext phy AN advertize cl37 0x%x\n", cl37_val);
7164
7165         bnx2x_cl45_write(bp, phy,
7166                          MDIO_AN_DEVAD, MDIO_AN_REG_CL37_FC_LD, cl37_val);
7167         msleep(500);
7168 }
7169
7170 static int bnx2x_8073_config_init(struct bnx2x_phy *phy,
7171                                   struct link_params *params,
7172                                   struct link_vars *vars)
7173 {
7174         struct bnx2x *bp = params->bp;
7175         u16 val = 0, tmp1;
7176         u8 gpio_port;
7177         DP(NETIF_MSG_LINK, "Init 8073\n");
7178
7179         if (CHIP_IS_E2(bp))
7180                 gpio_port = BP_PATH(bp);
7181         else
7182                 gpio_port = params->port;
7183         /* Restore normal power mode*/
7184         bnx2x_set_gpio(bp, MISC_REGISTERS_GPIO_2,
7185                        MISC_REGISTERS_GPIO_OUTPUT_HIGH, gpio_port);
7186
7187         bnx2x_set_gpio(bp, MISC_REGISTERS_GPIO_1,
7188                        MISC_REGISTERS_GPIO_OUTPUT_HIGH, gpio_port);
7189
7190         /* enable LASI */
7191         bnx2x_cl45_write(bp, phy,
7192                          MDIO_PMA_DEVAD, MDIO_PMA_LASI_RXCTRL, (1<<2));
7193         bnx2x_cl45_write(bp, phy,
7194                          MDIO_PMA_DEVAD, MDIO_PMA_LASI_CTRL,  0x0004);
7195
7196         bnx2x_8073_set_pause_cl37(params, phy, vars);
7197
7198         bnx2x_cl45_read(bp, phy,
7199                         MDIO_PMA_DEVAD, MDIO_PMA_REG_M8051_MSGOUT_REG, &tmp1);
7200
7201         bnx2x_cl45_read(bp, phy,
7202                         MDIO_PMA_DEVAD, MDIO_PMA_LASI_RXSTAT, &tmp1);
7203
7204         DP(NETIF_MSG_LINK, "Before rom RX_ALARM(port1): 0x%x\n", tmp1);
7205
7206         /* Swap polarity if required - Must be done only in non-1G mode */
7207         if (params->lane_config & PORT_HW_CFG_SWAP_PHY_POLARITY_ENABLED) {
7208                 /* Configure the 8073 to swap _P and _N of the KR lines */
7209                 DP(NETIF_MSG_LINK, "Swapping polarity for the 8073\n");
7210                 /* 10G Rx/Tx and 1G Tx signal polarity swap */
7211                 bnx2x_cl45_read(bp, phy,
7212                                 MDIO_PMA_DEVAD,
7213                                 MDIO_PMA_REG_8073_OPT_DIGITAL_CTRL, &val);
7214                 bnx2x_cl45_write(bp, phy,
7215                                  MDIO_PMA_DEVAD,
7216                                  MDIO_PMA_REG_8073_OPT_DIGITAL_CTRL,
7217                                  (val | (3<<9)));
7218         }
7219
7220
7221         /* Enable CL37 BAM */
7222         if (REG_RD(bp, params->shmem_base +
7223                          offsetof(struct shmem_region, dev_info.
7224                                   port_hw_config[params->port].default_cfg)) &
7225             PORT_HW_CFG_ENABLE_BAM_ON_KR_ENABLED) {
7226
7227                 bnx2x_cl45_read(bp, phy,
7228                                 MDIO_AN_DEVAD,
7229                                 MDIO_AN_REG_8073_BAM, &val);
7230                 bnx2x_cl45_write(bp, phy,
7231                                  MDIO_AN_DEVAD,
7232                                  MDIO_AN_REG_8073_BAM, val | 1);
7233                 DP(NETIF_MSG_LINK, "Enable CL37 BAM on KR\n");
7234         }
7235         if (params->loopback_mode == LOOPBACK_EXT) {
7236                 bnx2x_807x_force_10G(bp, phy);
7237                 DP(NETIF_MSG_LINK, "Forced speed 10G on 807X\n");
7238                 return 0;
7239         } else {
7240                 bnx2x_cl45_write(bp, phy,
7241                                  MDIO_PMA_DEVAD, MDIO_PMA_REG_BCM_CTRL, 0x0002);
7242         }
7243         if (phy->req_line_speed != SPEED_AUTO_NEG) {
7244                 if (phy->req_line_speed == SPEED_10000) {
7245                         val = (1<<7);
7246                 } else if (phy->req_line_speed ==  SPEED_2500) {
7247                         val = (1<<5);
7248                         /*
7249                          * Note that 2.5G works only when used with 1G
7250                          * advertisement
7251                          */
7252                 } else
7253                         val = (1<<5);
7254         } else {
7255                 val = 0;
7256                 if (phy->speed_cap_mask &
7257                         PORT_HW_CFG_SPEED_CAPABILITY_D0_10G)
7258                         val |= (1<<7);
7259
7260                 /* Note that 2.5G works only when used with 1G advertisement */
7261                 if (phy->speed_cap_mask &
7262                         (PORT_HW_CFG_SPEED_CAPABILITY_D0_1G |
7263                          PORT_HW_CFG_SPEED_CAPABILITY_D0_2_5G))
7264                         val |= (1<<5);
7265                 DP(NETIF_MSG_LINK, "807x autoneg val = 0x%x\n", val);
7266         }
7267
7268         bnx2x_cl45_write(bp, phy, MDIO_AN_DEVAD, MDIO_AN_REG_ADV, val);
7269         bnx2x_cl45_read(bp, phy, MDIO_AN_DEVAD, MDIO_AN_REG_8073_2_5G, &tmp1);
7270
7271         if (((phy->speed_cap_mask & PORT_HW_CFG_SPEED_CAPABILITY_D0_2_5G) &&
7272              (phy->req_line_speed == SPEED_AUTO_NEG)) ||
7273             (phy->req_line_speed == SPEED_2500)) {
7274                 u16 phy_ver;
7275                 /* Allow 2.5G for A1 and above */
7276                 bnx2x_cl45_read(bp, phy,
7277                                 MDIO_PMA_DEVAD, MDIO_PMA_REG_8073_CHIP_REV,
7278                                 &phy_ver);
7279                 DP(NETIF_MSG_LINK, "Add 2.5G\n");
7280                 if (phy_ver > 0)
7281                         tmp1 |= 1;
7282                 else
7283                         tmp1 &= 0xfffe;
7284         } else {
7285                 DP(NETIF_MSG_LINK, "Disable 2.5G\n");
7286                 tmp1 &= 0xfffe;
7287         }
7288
7289         bnx2x_cl45_write(bp, phy, MDIO_AN_DEVAD, MDIO_AN_REG_8073_2_5G, tmp1);
7290         /* Add support for CL37 (passive mode) II */
7291
7292         bnx2x_cl45_read(bp, phy, MDIO_AN_DEVAD, MDIO_AN_REG_CL37_FC_LD, &tmp1);
7293         bnx2x_cl45_write(bp, phy, MDIO_AN_DEVAD, MDIO_AN_REG_CL37_FC_LD,
7294                          (tmp1 | ((phy->req_duplex == DUPLEX_FULL) ?
7295                                   0x20 : 0x40)));
7296
7297         /* Add support for CL37 (passive mode) III */
7298         bnx2x_cl45_write(bp, phy, MDIO_AN_DEVAD, MDIO_AN_REG_CL37_AN, 0x1000);
7299
7300         /*
7301          * The SNR will improve about 2db by changing BW and FEE main
7302          * tap. Rest commands are executed after link is up
7303          * Change FFE main cursor to 5 in EDC register
7304          */
7305         if (bnx2x_8073_is_snr_needed(bp, phy))
7306                 bnx2x_cl45_write(bp, phy,
7307                                  MDIO_PMA_DEVAD, MDIO_PMA_REG_EDC_FFE_MAIN,
7308                                  0xFB0C);
7309
7310         /* Enable FEC (Forware Error Correction) Request in the AN */
7311         bnx2x_cl45_read(bp, phy, MDIO_AN_DEVAD, MDIO_AN_REG_ADV2, &tmp1);
7312         tmp1 |= (1<<15);
7313         bnx2x_cl45_write(bp, phy, MDIO_AN_DEVAD, MDIO_AN_REG_ADV2, tmp1);
7314
7315         bnx2x_ext_phy_set_pause(params, phy, vars);
7316
7317         /* Restart autoneg */
7318         msleep(500);
7319         bnx2x_cl45_write(bp, phy, MDIO_AN_DEVAD, MDIO_AN_REG_CTRL, 0x1200);
7320         DP(NETIF_MSG_LINK, "807x Autoneg Restart: Advertise 1G=%x, 10G=%x\n",
7321                    ((val & (1<<5)) > 0), ((val & (1<<7)) > 0));
7322         return 0;
7323 }
7324
7325 static u8 bnx2x_8073_read_status(struct bnx2x_phy *phy,
7326                                  struct link_params *params,
7327                                  struct link_vars *vars)
7328 {
7329         struct bnx2x *bp = params->bp;
7330         u8 link_up = 0;
7331         u16 val1, val2;
7332         u16 link_status = 0;
7333         u16 an1000_status = 0;
7334
7335         bnx2x_cl45_read(bp, phy,
7336                         MDIO_PMA_DEVAD, MDIO_PMA_LASI_STAT, &val1);
7337
7338         DP(NETIF_MSG_LINK, "8703 LASI status 0x%x\n", val1);
7339
7340         /* clear the interrupt LASI status register */
7341         bnx2x_cl45_read(bp, phy,
7342                         MDIO_PCS_DEVAD, MDIO_PCS_REG_STATUS, &val2);
7343         bnx2x_cl45_read(bp, phy,
7344                         MDIO_PCS_DEVAD, MDIO_PCS_REG_STATUS, &val1);
7345         DP(NETIF_MSG_LINK, "807x PCS status 0x%x->0x%x\n", val2, val1);
7346         /* Clear MSG-OUT */
7347         bnx2x_cl45_read(bp, phy,
7348                         MDIO_PMA_DEVAD, MDIO_PMA_REG_M8051_MSGOUT_REG, &val1);
7349
7350         /* Check the LASI */
7351         bnx2x_cl45_read(bp, phy,
7352                         MDIO_PMA_DEVAD, MDIO_PMA_LASI_RXSTAT, &val2);
7353
7354         DP(NETIF_MSG_LINK, "KR 0x9003 0x%x\n", val2);
7355
7356         /* Check the link status */
7357         bnx2x_cl45_read(bp, phy,
7358                         MDIO_PCS_DEVAD, MDIO_PCS_REG_STATUS, &val2);
7359         DP(NETIF_MSG_LINK, "KR PCS status 0x%x\n", val2);
7360
7361         bnx2x_cl45_read(bp, phy,
7362                         MDIO_PMA_DEVAD, MDIO_PMA_REG_STATUS, &val2);
7363         bnx2x_cl45_read(bp, phy,
7364                         MDIO_PMA_DEVAD, MDIO_PMA_REG_STATUS, &val1);
7365         link_up = ((val1 & 4) == 4);
7366         DP(NETIF_MSG_LINK, "PMA_REG_STATUS=0x%x\n", val1);
7367
7368         if (link_up &&
7369              ((phy->req_line_speed != SPEED_10000))) {
7370                 if (bnx2x_8073_xaui_wa(bp, phy) != 0)
7371                         return 0;
7372         }
7373         bnx2x_cl45_read(bp, phy,
7374                         MDIO_AN_DEVAD, MDIO_AN_REG_LINK_STATUS, &an1000_status);
7375         bnx2x_cl45_read(bp, phy,
7376                         MDIO_AN_DEVAD, MDIO_AN_REG_LINK_STATUS, &an1000_status);
7377
7378         /* Check the link status on 1.1.2 */
7379         bnx2x_cl45_read(bp, phy,
7380                         MDIO_PMA_DEVAD, MDIO_PMA_REG_STATUS, &val2);
7381         bnx2x_cl45_read(bp, phy,
7382                         MDIO_PMA_DEVAD, MDIO_PMA_REG_STATUS, &val1);
7383         DP(NETIF_MSG_LINK, "KR PMA status 0x%x->0x%x,"
7384                    "an_link_status=0x%x\n", val2, val1, an1000_status);
7385
7386         link_up = (((val1 & 4) == 4) || (an1000_status & (1<<1)));
7387         if (link_up && bnx2x_8073_is_snr_needed(bp, phy)) {
7388                 /*
7389                  * The SNR will improve about 2dbby changing the BW and FEE main
7390                  * tap. The 1st write to change FFE main tap is set before
7391                  * restart AN. Change PLL Bandwidth in EDC register
7392                  */
7393                 bnx2x_cl45_write(bp, phy,
7394                                  MDIO_PMA_DEVAD, MDIO_PMA_REG_PLL_BANDWIDTH,
7395                                  0x26BC);
7396
7397                 /* Change CDR Bandwidth in EDC register */
7398                 bnx2x_cl45_write(bp, phy,
7399                                  MDIO_PMA_DEVAD, MDIO_PMA_REG_CDR_BANDWIDTH,
7400                                  0x0333);
7401         }
7402         bnx2x_cl45_read(bp, phy,
7403                         MDIO_PMA_DEVAD, MDIO_PMA_REG_8073_SPEED_LINK_STATUS,
7404                         &link_status);
7405
7406         /* Bits 0..2 --> speed detected, bits 13..15--> link is down */
7407         if ((link_status & (1<<2)) && (!(link_status & (1<<15)))) {
7408                 link_up = 1;
7409                 vars->line_speed = SPEED_10000;
7410                 DP(NETIF_MSG_LINK, "port %x: External link up in 10G\n",
7411                            params->port);
7412         } else if ((link_status & (1<<1)) && (!(link_status & (1<<14)))) {
7413                 link_up = 1;
7414                 vars->line_speed = SPEED_2500;
7415                 DP(NETIF_MSG_LINK, "port %x: External link up in 2.5G\n",
7416                            params->port);
7417         } else if ((link_status & (1<<0)) && (!(link_status & (1<<13)))) {
7418                 link_up = 1;
7419                 vars->line_speed = SPEED_1000;
7420                 DP(NETIF_MSG_LINK, "port %x: External link up in 1G\n",
7421                            params->port);
7422         } else {
7423                 link_up = 0;
7424                 DP(NETIF_MSG_LINK, "port %x: External link is down\n",
7425                            params->port);
7426         }
7427
7428         if (link_up) {
7429                 /* Swap polarity if required */
7430                 if (params->lane_config &
7431                     PORT_HW_CFG_SWAP_PHY_POLARITY_ENABLED) {
7432                         /* Configure the 8073 to swap P and N of the KR lines */
7433                         bnx2x_cl45_read(bp, phy,
7434                                         MDIO_XS_DEVAD,
7435                                         MDIO_XS_REG_8073_RX_CTRL_PCIE, &val1);
7436                         /*
7437                          * Set bit 3 to invert Rx in 1G mode and clear this bit
7438                          * when it`s in 10G mode.
7439                          */
7440                         if (vars->line_speed == SPEED_1000) {
7441                                 DP(NETIF_MSG_LINK, "Swapping 1G polarity for"
7442                                               "the 8073\n");
7443                                 val1 |= (1<<3);
7444                         } else
7445                                 val1 &= ~(1<<3);
7446
7447                         bnx2x_cl45_write(bp, phy,
7448                                          MDIO_XS_DEVAD,
7449                                          MDIO_XS_REG_8073_RX_CTRL_PCIE,
7450                                          val1);
7451                 }
7452                 bnx2x_ext_phy_10G_an_resolve(bp, phy, vars);
7453                 bnx2x_8073_resolve_fc(phy, params, vars);
7454                 vars->duplex = DUPLEX_FULL;
7455         }
7456
7457         if (vars->link_status & LINK_STATUS_AUTO_NEGOTIATE_COMPLETE) {
7458                 bnx2x_cl45_read(bp, phy, MDIO_AN_DEVAD,
7459                                 MDIO_AN_REG_LP_AUTO_NEG2, &val1);
7460
7461                 if (val1 & (1<<5))
7462                         vars->link_status |=
7463                                 LINK_STATUS_LINK_PARTNER_1000TFD_CAPABLE;
7464                 if (val1 & (1<<7))
7465                         vars->link_status |=
7466                                 LINK_STATUS_LINK_PARTNER_10GXFD_CAPABLE;
7467         }
7468
7469         return link_up;
7470 }
7471
7472 static void bnx2x_8073_link_reset(struct bnx2x_phy *phy,
7473                                   struct link_params *params)
7474 {
7475         struct bnx2x *bp = params->bp;
7476         u8 gpio_port;
7477         if (CHIP_IS_E2(bp))
7478                 gpio_port = BP_PATH(bp);
7479         else
7480                 gpio_port = params->port;
7481         DP(NETIF_MSG_LINK, "Setting 8073 port %d into low power mode\n",
7482            gpio_port);
7483         bnx2x_set_gpio(bp, MISC_REGISTERS_GPIO_2,
7484                        MISC_REGISTERS_GPIO_OUTPUT_LOW,
7485                        gpio_port);
7486 }
7487
7488 /******************************************************************/
7489 /*                      BCM8705 PHY SECTION                       */
7490 /******************************************************************/
7491 static int bnx2x_8705_config_init(struct bnx2x_phy *phy,
7492                                   struct link_params *params,
7493                                   struct link_vars *vars)
7494 {
7495         struct bnx2x *bp = params->bp;
7496         DP(NETIF_MSG_LINK, "init 8705\n");
7497         /* Restore normal power mode*/
7498         bnx2x_set_gpio(bp, MISC_REGISTERS_GPIO_2,
7499                        MISC_REGISTERS_GPIO_OUTPUT_HIGH, params->port);
7500         /* HW reset */
7501         bnx2x_ext_phy_hw_reset(bp, params->port);
7502         bnx2x_cl45_write(bp, phy, MDIO_PMA_DEVAD, MDIO_PMA_REG_CTRL, 0xa040);
7503         bnx2x_wait_reset_complete(bp, phy, params);
7504
7505         bnx2x_cl45_write(bp, phy,
7506                          MDIO_PMA_DEVAD, MDIO_PMA_REG_MISC_CTRL, 0x8288);
7507         bnx2x_cl45_write(bp, phy,
7508                          MDIO_PMA_DEVAD, MDIO_PMA_REG_PHY_IDENTIFIER, 0x7fbf);
7509         bnx2x_cl45_write(bp, phy,
7510                          MDIO_PMA_DEVAD, MDIO_PMA_REG_CMU_PLL_BYPASS, 0x0100);
7511         bnx2x_cl45_write(bp, phy,
7512                          MDIO_WIS_DEVAD, MDIO_WIS_REG_LASI_CNTL, 0x1);
7513         /* BCM8705 doesn't have microcode, hence the 0 */
7514         bnx2x_save_spirom_version(bp, params->port, params->shmem_base, 0);
7515         return 0;
7516 }
7517
7518 static u8 bnx2x_8705_read_status(struct bnx2x_phy *phy,
7519                                  struct link_params *params,
7520                                  struct link_vars *vars)
7521 {
7522         u8 link_up = 0;
7523         u16 val1, rx_sd;
7524         struct bnx2x *bp = params->bp;
7525         DP(NETIF_MSG_LINK, "read status 8705\n");
7526         bnx2x_cl45_read(bp, phy,
7527                       MDIO_WIS_DEVAD, MDIO_WIS_REG_LASI_STATUS, &val1);
7528         DP(NETIF_MSG_LINK, "8705 LASI status 0x%x\n", val1);
7529
7530         bnx2x_cl45_read(bp, phy,
7531                       MDIO_WIS_DEVAD, MDIO_WIS_REG_LASI_STATUS, &val1);
7532         DP(NETIF_MSG_LINK, "8705 LASI status 0x%x\n", val1);
7533
7534         bnx2x_cl45_read(bp, phy,
7535                       MDIO_PMA_DEVAD, MDIO_PMA_REG_RX_SD, &rx_sd);
7536
7537         bnx2x_cl45_read(bp, phy,
7538                       MDIO_PMA_DEVAD, 0xc809, &val1);
7539         bnx2x_cl45_read(bp, phy,
7540                       MDIO_PMA_DEVAD, 0xc809, &val1);
7541
7542         DP(NETIF_MSG_LINK, "8705 1.c809 val=0x%x\n", val1);
7543         link_up = ((rx_sd & 0x1) && (val1 & (1<<9)) && ((val1 & (1<<8)) == 0));
7544         if (link_up) {
7545                 vars->line_speed = SPEED_10000;
7546                 bnx2x_ext_phy_resolve_fc(phy, params, vars);
7547         }
7548         return link_up;
7549 }
7550
7551 /******************************************************************/
7552 /*                      SFP+ module Section                       */
7553 /******************************************************************/
7554 static void bnx2x_set_disable_pmd_transmit(struct link_params *params,
7555                                            struct bnx2x_phy *phy,
7556                                            u8 pmd_dis)
7557 {
7558         struct bnx2x *bp = params->bp;
7559         /*
7560          * Disable transmitter only for bootcodes which can enable it afterwards
7561          * (for D3 link)
7562          */
7563         if (pmd_dis) {
7564                 if (params->feature_config_flags &
7565                      FEATURE_CONFIG_BC_SUPPORTS_SFP_TX_DISABLED)
7566                         DP(NETIF_MSG_LINK, "Disabling PMD transmitter\n");
7567                 else {
7568                         DP(NETIF_MSG_LINK, "NOT disabling PMD transmitter\n");
7569                         return;
7570                 }
7571         } else
7572                 DP(NETIF_MSG_LINK, "Enabling PMD transmitter\n");
7573         bnx2x_cl45_write(bp, phy,
7574                          MDIO_PMA_DEVAD,
7575                          MDIO_PMA_REG_TX_DISABLE, pmd_dis);
7576 }
7577
7578 static u8 bnx2x_get_gpio_port(struct link_params *params)
7579 {
7580         u8 gpio_port;
7581         u32 swap_val, swap_override;
7582         struct bnx2x *bp = params->bp;
7583         if (CHIP_IS_E2(bp))
7584                 gpio_port = BP_PATH(bp);
7585         else
7586                 gpio_port = params->port;
7587         swap_val = REG_RD(bp, NIG_REG_PORT_SWAP);
7588         swap_override = REG_RD(bp, NIG_REG_STRAP_OVERRIDE);
7589         return gpio_port ^ (swap_val && swap_override);
7590 }
7591
7592 static void bnx2x_sfp_e1e2_set_transmitter(struct link_params *params,
7593                                            struct bnx2x_phy *phy,
7594                                            u8 tx_en)
7595 {
7596         u16 val;
7597         u8 port = params->port;
7598         struct bnx2x *bp = params->bp;
7599         u32 tx_en_mode;
7600
7601         /* Disable/Enable transmitter ( TX laser of the SFP+ module.)*/
7602         tx_en_mode = REG_RD(bp, params->shmem_base +
7603                             offsetof(struct shmem_region,
7604                                      dev_info.port_hw_config[port].sfp_ctrl)) &
7605                 PORT_HW_CFG_TX_LASER_MASK;
7606         DP(NETIF_MSG_LINK, "Setting transmitter tx_en=%x for port %x "
7607                            "mode = %x\n", tx_en, port, tx_en_mode);
7608         switch (tx_en_mode) {
7609         case PORT_HW_CFG_TX_LASER_MDIO:
7610
7611                 bnx2x_cl45_read(bp, phy,
7612                                 MDIO_PMA_DEVAD,
7613                                 MDIO_PMA_REG_PHY_IDENTIFIER,
7614                                 &val);
7615
7616                 if (tx_en)
7617                         val &= ~(1<<15);
7618                 else
7619                         val |= (1<<15);
7620
7621                 bnx2x_cl45_write(bp, phy,
7622                                  MDIO_PMA_DEVAD,
7623                                  MDIO_PMA_REG_PHY_IDENTIFIER,
7624                                  val);
7625         break;
7626         case PORT_HW_CFG_TX_LASER_GPIO0:
7627         case PORT_HW_CFG_TX_LASER_GPIO1:
7628         case PORT_HW_CFG_TX_LASER_GPIO2:
7629         case PORT_HW_CFG_TX_LASER_GPIO3:
7630         {
7631                 u16 gpio_pin;
7632                 u8 gpio_port, gpio_mode;
7633                 if (tx_en)
7634                         gpio_mode = MISC_REGISTERS_GPIO_OUTPUT_HIGH;
7635                 else
7636                         gpio_mode = MISC_REGISTERS_GPIO_OUTPUT_LOW;
7637
7638                 gpio_pin = tx_en_mode - PORT_HW_CFG_TX_LASER_GPIO0;
7639                 gpio_port = bnx2x_get_gpio_port(params);
7640                 bnx2x_set_gpio(bp, gpio_pin, gpio_mode, gpio_port);
7641                 break;
7642         }
7643         default:
7644                 DP(NETIF_MSG_LINK, "Invalid TX_LASER_MDIO 0x%x\n", tx_en_mode);
7645                 break;
7646         }
7647 }
7648
7649 static void bnx2x_sfp_set_transmitter(struct link_params *params,
7650                                       struct bnx2x_phy *phy,
7651                                       u8 tx_en)
7652 {
7653         struct bnx2x *bp = params->bp;
7654         DP(NETIF_MSG_LINK, "Setting SFP+ transmitter to %d\n", tx_en);
7655         if (CHIP_IS_E3(bp))
7656                 bnx2x_sfp_e3_set_transmitter(params, phy, tx_en);
7657         else
7658                 bnx2x_sfp_e1e2_set_transmitter(params, phy, tx_en);
7659 }
7660
7661 static int bnx2x_8726_read_sfp_module_eeprom(struct bnx2x_phy *phy,
7662                                              struct link_params *params,
7663                                              u16 addr, u8 byte_cnt, u8 *o_buf)
7664 {
7665         struct bnx2x *bp = params->bp;
7666         u16 val = 0;
7667         u16 i;
7668         if (byte_cnt > 16) {
7669                 DP(NETIF_MSG_LINK,
7670                    "Reading from eeprom is limited to 0xf\n");
7671                 return -EINVAL;
7672         }
7673         /* Set the read command byte count */
7674         bnx2x_cl45_write(bp, phy,
7675                          MDIO_PMA_DEVAD, MDIO_PMA_REG_SFP_TWO_WIRE_BYTE_CNT,
7676                          (byte_cnt | 0xa000));
7677
7678         /* Set the read command address */
7679         bnx2x_cl45_write(bp, phy,
7680                          MDIO_PMA_DEVAD, MDIO_PMA_REG_SFP_TWO_WIRE_MEM_ADDR,
7681                          addr);
7682
7683         /* Activate read command */
7684         bnx2x_cl45_write(bp, phy,
7685                          MDIO_PMA_DEVAD, MDIO_PMA_REG_SFP_TWO_WIRE_CTRL,
7686                          0x2c0f);
7687
7688         /* Wait up to 500us for command complete status */
7689         for (i = 0; i < 100; i++) {
7690                 bnx2x_cl45_read(bp, phy,
7691                                 MDIO_PMA_DEVAD,
7692                                 MDIO_PMA_REG_SFP_TWO_WIRE_CTRL, &val);
7693                 if ((val & MDIO_PMA_REG_SFP_TWO_WIRE_CTRL_STATUS_MASK) ==
7694                     MDIO_PMA_REG_SFP_TWO_WIRE_STATUS_COMPLETE)
7695                         break;
7696                 udelay(5);
7697         }
7698
7699         if ((val & MDIO_PMA_REG_SFP_TWO_WIRE_CTRL_STATUS_MASK) !=
7700                     MDIO_PMA_REG_SFP_TWO_WIRE_STATUS_COMPLETE) {
7701                 DP(NETIF_MSG_LINK,
7702                          "Got bad status 0x%x when reading from SFP+ EEPROM\n",
7703                          (val & MDIO_PMA_REG_SFP_TWO_WIRE_CTRL_STATUS_MASK));
7704                 return -EINVAL;
7705         }
7706
7707         /* Read the buffer */
7708         for (i = 0; i < byte_cnt; i++) {
7709                 bnx2x_cl45_read(bp, phy,
7710                                 MDIO_PMA_DEVAD,
7711                                 MDIO_PMA_REG_8726_TWO_WIRE_DATA_BUF + i, &val);
7712                 o_buf[i] = (u8)(val & MDIO_PMA_REG_8726_TWO_WIRE_DATA_MASK);
7713         }
7714
7715         for (i = 0; i < 100; i++) {
7716                 bnx2x_cl45_read(bp, phy,
7717                                 MDIO_PMA_DEVAD,
7718                                 MDIO_PMA_REG_SFP_TWO_WIRE_CTRL, &val);
7719                 if ((val & MDIO_PMA_REG_SFP_TWO_WIRE_CTRL_STATUS_MASK) ==
7720                     MDIO_PMA_REG_SFP_TWO_WIRE_STATUS_IDLE)
7721                         return 0;
7722                 msleep(1);
7723         }
7724         return -EINVAL;
7725 }
7726
7727 static int bnx2x_warpcore_read_sfp_module_eeprom(struct bnx2x_phy *phy,
7728                                                  struct link_params *params,
7729                                                  u16 addr, u8 byte_cnt,
7730                                                  u8 *o_buf)
7731 {
7732         int rc = 0;
7733         u8 i, j = 0, cnt = 0;
7734         u32 data_array[4];
7735         u16 addr32;
7736         struct bnx2x *bp = params->bp;
7737         /*DP(NETIF_MSG_LINK, "bnx2x_direct_read_sfp_module_eeprom:"
7738                                         " addr %d, cnt %d\n",
7739                                         addr, byte_cnt);*/
7740         if (byte_cnt > 16) {
7741                 DP(NETIF_MSG_LINK,
7742                    "Reading from eeprom is limited to 16 bytes\n");
7743                 return -EINVAL;
7744         }
7745
7746         /* 4 byte aligned address */
7747         addr32 = addr & (~0x3);
7748         do {
7749                 rc = bnx2x_bsc_read(params, phy, 0xa0, addr32, 0, byte_cnt,
7750                                     data_array);
7751         } while ((rc != 0) && (++cnt < I2C_WA_RETRY_CNT));
7752
7753         if (rc == 0) {
7754                 for (i = (addr - addr32); i < byte_cnt + (addr - addr32); i++) {
7755                         o_buf[j] = *((u8 *)data_array + i);
7756                         j++;
7757                 }
7758         }
7759
7760         return rc;
7761 }
7762
7763 static int bnx2x_8727_read_sfp_module_eeprom(struct bnx2x_phy *phy,
7764                                              struct link_params *params,
7765                                              u16 addr, u8 byte_cnt, u8 *o_buf)
7766 {
7767         struct bnx2x *bp = params->bp;
7768         u16 val, i;
7769
7770         if (byte_cnt > 16) {
7771                 DP(NETIF_MSG_LINK,
7772                    "Reading from eeprom is limited to 0xf\n");
7773                 return -EINVAL;
7774         }
7775
7776         /* Need to read from 1.8000 to clear it */
7777         bnx2x_cl45_read(bp, phy,
7778                         MDIO_PMA_DEVAD,
7779                         MDIO_PMA_REG_SFP_TWO_WIRE_CTRL,
7780                         &val);
7781
7782         /* Set the read command byte count */
7783         bnx2x_cl45_write(bp, phy,
7784                          MDIO_PMA_DEVAD,
7785                          MDIO_PMA_REG_SFP_TWO_WIRE_BYTE_CNT,
7786                          ((byte_cnt < 2) ? 2 : byte_cnt));
7787
7788         /* Set the read command address */
7789         bnx2x_cl45_write(bp, phy,
7790                          MDIO_PMA_DEVAD,
7791                          MDIO_PMA_REG_SFP_TWO_WIRE_MEM_ADDR,
7792                          addr);
7793         /* Set the destination address */
7794         bnx2x_cl45_write(bp, phy,
7795                          MDIO_PMA_DEVAD,
7796                          0x8004,
7797                          MDIO_PMA_REG_8727_TWO_WIRE_DATA_BUF);
7798
7799         /* Activate read command */
7800         bnx2x_cl45_write(bp, phy,
7801                          MDIO_PMA_DEVAD,
7802                          MDIO_PMA_REG_SFP_TWO_WIRE_CTRL,
7803                          0x8002);
7804         /*
7805          * Wait appropriate time for two-wire command to finish before
7806          * polling the status register
7807          */
7808         msleep(1);
7809
7810         /* Wait up to 500us for command complete status */
7811         for (i = 0; i < 100; i++) {
7812                 bnx2x_cl45_read(bp, phy,
7813                                 MDIO_PMA_DEVAD,
7814                                 MDIO_PMA_REG_SFP_TWO_WIRE_CTRL, &val);
7815                 if ((val & MDIO_PMA_REG_SFP_TWO_WIRE_CTRL_STATUS_MASK) ==
7816                     MDIO_PMA_REG_SFP_TWO_WIRE_STATUS_COMPLETE)
7817                         break;
7818                 udelay(5);
7819         }
7820
7821         if ((val & MDIO_PMA_REG_SFP_TWO_WIRE_CTRL_STATUS_MASK) !=
7822                     MDIO_PMA_REG_SFP_TWO_WIRE_STATUS_COMPLETE) {
7823                 DP(NETIF_MSG_LINK,
7824                          "Got bad status 0x%x when reading from SFP+ EEPROM\n",
7825                          (val & MDIO_PMA_REG_SFP_TWO_WIRE_CTRL_STATUS_MASK));
7826                 return -EFAULT;
7827         }
7828
7829         /* Read the buffer */
7830         for (i = 0; i < byte_cnt; i++) {
7831                 bnx2x_cl45_read(bp, phy,
7832                                 MDIO_PMA_DEVAD,
7833                                 MDIO_PMA_REG_8727_TWO_WIRE_DATA_BUF + i, &val);
7834                 o_buf[i] = (u8)(val & MDIO_PMA_REG_8727_TWO_WIRE_DATA_MASK);
7835         }
7836
7837         for (i = 0; i < 100; i++) {
7838                 bnx2x_cl45_read(bp, phy,
7839                                 MDIO_PMA_DEVAD,
7840                                 MDIO_PMA_REG_SFP_TWO_WIRE_CTRL, &val);
7841                 if ((val & MDIO_PMA_REG_SFP_TWO_WIRE_CTRL_STATUS_MASK) ==
7842                     MDIO_PMA_REG_SFP_TWO_WIRE_STATUS_IDLE)
7843                         return 0;
7844                 msleep(1);
7845         }
7846
7847         return -EINVAL;
7848 }
7849
7850 int bnx2x_read_sfp_module_eeprom(struct bnx2x_phy *phy,
7851                                  struct link_params *params, u16 addr,
7852                                  u8 byte_cnt, u8 *o_buf)
7853 {
7854         int rc = -EINVAL;
7855         switch (phy->type) {
7856         case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8726:
7857                 rc = bnx2x_8726_read_sfp_module_eeprom(phy, params, addr,
7858                                                        byte_cnt, o_buf);
7859         break;
7860         case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8727:
7861         case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8722:
7862                 rc = bnx2x_8727_read_sfp_module_eeprom(phy, params, addr,
7863                                                        byte_cnt, o_buf);
7864         break;
7865         case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_DIRECT:
7866                 rc = bnx2x_warpcore_read_sfp_module_eeprom(phy, params, addr,
7867                                                            byte_cnt, o_buf);
7868         break;
7869         }
7870         return rc;
7871 }
7872
7873 static int bnx2x_get_edc_mode(struct bnx2x_phy *phy,
7874                               struct link_params *params,
7875                               u16 *edc_mode)
7876 {
7877         struct bnx2x *bp = params->bp;
7878         u32 sync_offset = 0, phy_idx, media_types;
7879         u8 val, check_limiting_mode = 0;
7880         *edc_mode = EDC_MODE_LIMITING;
7881
7882         phy->media_type = ETH_PHY_UNSPECIFIED;
7883         /* First check for copper cable */
7884         if (bnx2x_read_sfp_module_eeprom(phy,
7885                                          params,
7886                                          SFP_EEPROM_CON_TYPE_ADDR,
7887                                          1,
7888                                          &val) != 0) {
7889                 DP(NETIF_MSG_LINK, "Failed to read from SFP+ module EEPROM\n");
7890                 return -EINVAL;
7891         }
7892
7893         switch (val) {
7894         case SFP_EEPROM_CON_TYPE_VAL_COPPER:
7895         {
7896                 u8 copper_module_type;
7897                 phy->media_type = ETH_PHY_DA_TWINAX;
7898                 /*
7899                  * Check if its active cable (includes SFP+ module)
7900                  * of passive cable
7901                  */
7902                 if (bnx2x_read_sfp_module_eeprom(phy,
7903                                                params,
7904                                                SFP_EEPROM_FC_TX_TECH_ADDR,
7905                                                1,
7906                                                &copper_module_type) != 0) {
7907                         DP(NETIF_MSG_LINK,
7908                                 "Failed to read copper-cable-type"
7909                                 " from SFP+ EEPROM\n");
7910                         return -EINVAL;
7911                 }
7912
7913                 if (copper_module_type &
7914                     SFP_EEPROM_FC_TX_TECH_BITMASK_COPPER_ACTIVE) {
7915                         DP(NETIF_MSG_LINK, "Active Copper cable detected\n");
7916                         check_limiting_mode = 1;
7917                 } else if (copper_module_type &
7918                         SFP_EEPROM_FC_TX_TECH_BITMASK_COPPER_PASSIVE) {
7919                                 DP(NETIF_MSG_LINK,
7920                                    "Passive Copper cable detected\n");
7921                                 *edc_mode =
7922                                       EDC_MODE_PASSIVE_DAC;
7923                 } else {
7924                         DP(NETIF_MSG_LINK,
7925                            "Unknown copper-cable-type 0x%x !!!\n",
7926                            copper_module_type);
7927                         return -EINVAL;
7928                 }
7929                 break;
7930         }
7931         case SFP_EEPROM_CON_TYPE_VAL_LC:
7932                 phy->media_type = ETH_PHY_SFP_FIBER;
7933                 DP(NETIF_MSG_LINK, "Optic module detected\n");
7934                 check_limiting_mode = 1;
7935                 break;
7936         default:
7937                 DP(NETIF_MSG_LINK, "Unable to determine module type 0x%x !!!\n",
7938                          val);
7939                 return -EINVAL;
7940         }
7941         sync_offset = params->shmem_base +
7942                 offsetof(struct shmem_region,
7943                          dev_info.port_hw_config[params->port].media_type);
7944         media_types = REG_RD(bp, sync_offset);
7945         /* Update media type for non-PMF sync */
7946         for (phy_idx = INT_PHY; phy_idx < MAX_PHYS; phy_idx++) {
7947                 if (&(params->phy[phy_idx]) == phy) {
7948                         media_types &= ~(PORT_HW_CFG_MEDIA_TYPE_PHY0_MASK <<
7949                                 (PORT_HW_CFG_MEDIA_TYPE_PHY1_SHIFT * phy_idx));
7950                         media_types |= ((phy->media_type &
7951                                         PORT_HW_CFG_MEDIA_TYPE_PHY0_MASK) <<
7952                                 (PORT_HW_CFG_MEDIA_TYPE_PHY1_SHIFT * phy_idx));
7953                         break;
7954                 }
7955         }
7956         REG_WR(bp, sync_offset, media_types);
7957         if (check_limiting_mode) {
7958                 u8 options[SFP_EEPROM_OPTIONS_SIZE];
7959                 if (bnx2x_read_sfp_module_eeprom(phy,
7960                                                  params,
7961                                                  SFP_EEPROM_OPTIONS_ADDR,
7962                                                  SFP_EEPROM_OPTIONS_SIZE,
7963                                                  options) != 0) {
7964                         DP(NETIF_MSG_LINK,
7965                            "Failed to read Option field from module EEPROM\n");
7966                         return -EINVAL;
7967                 }
7968                 if ((options[0] & SFP_EEPROM_OPTIONS_LINEAR_RX_OUT_MASK))
7969                         *edc_mode = EDC_MODE_LINEAR;
7970                 else
7971                         *edc_mode = EDC_MODE_LIMITING;
7972         }
7973         DP(NETIF_MSG_LINK, "EDC mode is set to 0x%x\n", *edc_mode);
7974         return 0;
7975 }
7976 /*
7977  * This function read the relevant field from the module (SFP+), and verify it
7978  * is compliant with this board
7979  */
7980 static int bnx2x_verify_sfp_module(struct bnx2x_phy *phy,
7981                                    struct link_params *params)
7982 {
7983         struct bnx2x *bp = params->bp;
7984         u32 val, cmd;
7985         u32 fw_resp, fw_cmd_param;
7986         char vendor_name[SFP_EEPROM_VENDOR_NAME_SIZE+1];
7987         char vendor_pn[SFP_EEPROM_PART_NO_SIZE+1];
7988         phy->flags &= ~FLAGS_SFP_NOT_APPROVED;
7989         val = REG_RD(bp, params->shmem_base +
7990                          offsetof(struct shmem_region, dev_info.
7991                                   port_feature_config[params->port].config));
7992         if ((val & PORT_FEAT_CFG_OPT_MDL_ENFRCMNT_MASK) ==
7993             PORT_FEAT_CFG_OPT_MDL_ENFRCMNT_NO_ENFORCEMENT) {
7994                 DP(NETIF_MSG_LINK, "NOT enforcing module verification\n");
7995                 return 0;
7996         }
7997
7998         if (params->feature_config_flags &
7999             FEATURE_CONFIG_BC_SUPPORTS_DUAL_PHY_OPT_MDL_VRFY) {
8000                 /* Use specific phy request */
8001                 cmd = DRV_MSG_CODE_VRFY_SPECIFIC_PHY_OPT_MDL;
8002         } else if (params->feature_config_flags &
8003                    FEATURE_CONFIG_BC_SUPPORTS_OPT_MDL_VRFY) {
8004                 /* Use first phy request only in case of non-dual media*/
8005                 if (DUAL_MEDIA(params)) {
8006                         DP(NETIF_MSG_LINK,
8007                            "FW does not support OPT MDL verification\n");
8008                         return -EINVAL;
8009                 }
8010                 cmd = DRV_MSG_CODE_VRFY_FIRST_PHY_OPT_MDL;
8011         } else {
8012                 /* No support in OPT MDL detection */
8013                 DP(NETIF_MSG_LINK,
8014                    "FW does not support OPT MDL verification\n");
8015                 return -EINVAL;
8016         }
8017
8018         fw_cmd_param = FW_PARAM_SET(phy->addr, phy->type, phy->mdio_ctrl);
8019         fw_resp = bnx2x_fw_command(bp, cmd, fw_cmd_param);
8020         if (fw_resp == FW_MSG_CODE_VRFY_OPT_MDL_SUCCESS) {
8021                 DP(NETIF_MSG_LINK, "Approved module\n");
8022                 return 0;
8023         }
8024
8025         /* format the warning message */
8026         if (bnx2x_read_sfp_module_eeprom(phy,
8027                                          params,
8028                                          SFP_EEPROM_VENDOR_NAME_ADDR,
8029                                          SFP_EEPROM_VENDOR_NAME_SIZE,
8030                                          (u8 *)vendor_name))
8031                 vendor_name[0] = '\0';
8032         else
8033                 vendor_name[SFP_EEPROM_VENDOR_NAME_SIZE] = '\0';
8034         if (bnx2x_read_sfp_module_eeprom(phy,
8035                                          params,
8036                                          SFP_EEPROM_PART_NO_ADDR,
8037                                          SFP_EEPROM_PART_NO_SIZE,
8038                                          (u8 *)vendor_pn))
8039                 vendor_pn[0] = '\0';
8040         else
8041                 vendor_pn[SFP_EEPROM_PART_NO_SIZE] = '\0';
8042
8043         netdev_err(bp->dev,  "Warning: Unqualified SFP+ module detected,"
8044                               " Port %d from %s part number %s\n",
8045                          params->port, vendor_name, vendor_pn);
8046         phy->flags |= FLAGS_SFP_NOT_APPROVED;
8047         return -EINVAL;
8048 }
8049
8050 static int bnx2x_wait_for_sfp_module_initialized(struct bnx2x_phy *phy,
8051                                                  struct link_params *params)
8052
8053 {
8054         u8 val;
8055         struct bnx2x *bp = params->bp;
8056         u16 timeout;
8057         /*
8058          * Initialization time after hot-plug may take up to 300ms for
8059          * some phys type ( e.g. JDSU )
8060          */
8061
8062         for (timeout = 0; timeout < 60; timeout++) {
8063                 if (bnx2x_read_sfp_module_eeprom(phy, params, 1, 1, &val)
8064                     == 0) {
8065                         DP(NETIF_MSG_LINK,
8066                            "SFP+ module initialization took %d ms\n",
8067                            timeout * 5);
8068                         return 0;
8069                 }
8070                 msleep(5);
8071         }
8072         return -EINVAL;
8073 }
8074
8075 static void bnx2x_8727_power_module(struct bnx2x *bp,
8076                                     struct bnx2x_phy *phy,
8077                                     u8 is_power_up) {
8078         /* Make sure GPIOs are not using for LED mode */
8079         u16 val;
8080         /*
8081          * In the GPIO register, bit 4 is use to determine if the GPIOs are
8082          * operating as INPUT or as OUTPUT. Bit 1 is for input, and 0 for
8083          * output
8084          * Bits 0-1 determine the GPIOs value for OUTPUT in case bit 4 val is 0
8085          * Bits 8-9 determine the GPIOs value for INPUT in case bit 4 val is 1
8086          * where the 1st bit is the over-current(only input), and 2nd bit is
8087          * for power( only output )
8088          *
8089          * In case of NOC feature is disabled and power is up, set GPIO control
8090          *  as input to enable listening of over-current indication
8091          */
8092         if (phy->flags & FLAGS_NOC)
8093                 return;
8094         if (is_power_up)
8095                 val = (1<<4);
8096         else
8097                 /*
8098                  * Set GPIO control to OUTPUT, and set the power bit
8099                  * to according to the is_power_up
8100                  */
8101                 val = (1<<1);
8102
8103         bnx2x_cl45_write(bp, phy,
8104                          MDIO_PMA_DEVAD,
8105                          MDIO_PMA_REG_8727_GPIO_CTRL,
8106                          val);
8107 }
8108
8109 static int bnx2x_8726_set_limiting_mode(struct bnx2x *bp,
8110                                         struct bnx2x_phy *phy,
8111                                         u16 edc_mode)
8112 {
8113         u16 cur_limiting_mode;
8114
8115         bnx2x_cl45_read(bp, phy,
8116                         MDIO_PMA_DEVAD,
8117                         MDIO_PMA_REG_ROM_VER2,
8118                         &cur_limiting_mode);
8119         DP(NETIF_MSG_LINK, "Current Limiting mode is 0x%x\n",
8120                  cur_limiting_mode);
8121
8122         if (edc_mode == EDC_MODE_LIMITING) {
8123                 DP(NETIF_MSG_LINK, "Setting LIMITING MODE\n");
8124                 bnx2x_cl45_write(bp, phy,
8125                                  MDIO_PMA_DEVAD,
8126                                  MDIO_PMA_REG_ROM_VER2,
8127                                  EDC_MODE_LIMITING);
8128         } else { /* LRM mode ( default )*/
8129
8130                 DP(NETIF_MSG_LINK, "Setting LRM MODE\n");
8131
8132                 /*
8133                  * Changing to LRM mode takes quite few seconds. So do it only
8134                  * if current mode is limiting (default is LRM)
8135                  */
8136                 if (cur_limiting_mode != EDC_MODE_LIMITING)
8137                         return 0;
8138
8139                 bnx2x_cl45_write(bp, phy,
8140                                  MDIO_PMA_DEVAD,
8141                                  MDIO_PMA_REG_LRM_MODE,
8142                                  0);
8143                 bnx2x_cl45_write(bp, phy,
8144                                  MDIO_PMA_DEVAD,
8145                                  MDIO_PMA_REG_ROM_VER2,
8146                                  0x128);
8147                 bnx2x_cl45_write(bp, phy,
8148                                  MDIO_PMA_DEVAD,
8149                                  MDIO_PMA_REG_MISC_CTRL0,
8150                                  0x4008);
8151                 bnx2x_cl45_write(bp, phy,
8152                                  MDIO_PMA_DEVAD,
8153                                  MDIO_PMA_REG_LRM_MODE,
8154                                  0xaaaa);
8155         }
8156         return 0;
8157 }
8158
8159 static int bnx2x_8727_set_limiting_mode(struct bnx2x *bp,
8160                                         struct bnx2x_phy *phy,
8161                                         u16 edc_mode)
8162 {
8163         u16 phy_identifier;
8164         u16 rom_ver2_val;
8165         bnx2x_cl45_read(bp, phy,
8166                         MDIO_PMA_DEVAD,
8167                         MDIO_PMA_REG_PHY_IDENTIFIER,
8168                         &phy_identifier);
8169
8170         bnx2x_cl45_write(bp, phy,
8171                          MDIO_PMA_DEVAD,
8172                          MDIO_PMA_REG_PHY_IDENTIFIER,
8173                          (phy_identifier & ~(1<<9)));
8174
8175         bnx2x_cl45_read(bp, phy,
8176                         MDIO_PMA_DEVAD,
8177                         MDIO_PMA_REG_ROM_VER2,
8178                         &rom_ver2_val);
8179         /* Keep the MSB 8-bits, and set the LSB 8-bits with the edc_mode */
8180         bnx2x_cl45_write(bp, phy,
8181                          MDIO_PMA_DEVAD,
8182                          MDIO_PMA_REG_ROM_VER2,
8183                          (rom_ver2_val & 0xff00) | (edc_mode & 0x00ff));
8184
8185         bnx2x_cl45_write(bp, phy,
8186                          MDIO_PMA_DEVAD,
8187                          MDIO_PMA_REG_PHY_IDENTIFIER,
8188                          (phy_identifier | (1<<9)));
8189
8190         return 0;
8191 }
8192
8193 static void bnx2x_8727_specific_func(struct bnx2x_phy *phy,
8194                                      struct link_params *params,
8195                                      u32 action)
8196 {
8197         struct bnx2x *bp = params->bp;
8198
8199         switch (action) {
8200         case DISABLE_TX:
8201                 bnx2x_sfp_set_transmitter(params, phy, 0);
8202                 break;
8203         case ENABLE_TX:
8204                 if (!(phy->flags & FLAGS_SFP_NOT_APPROVED))
8205                         bnx2x_sfp_set_transmitter(params, phy, 1);
8206                 break;
8207         default:
8208                 DP(NETIF_MSG_LINK, "Function 0x%x not supported by 8727\n",
8209                    action);
8210                 return;
8211         }
8212 }
8213
8214 static void bnx2x_set_e1e2_module_fault_led(struct link_params *params,
8215                                            u8 gpio_mode)
8216 {
8217         struct bnx2x *bp = params->bp;
8218
8219         u32 fault_led_gpio = REG_RD(bp, params->shmem_base +
8220                             offsetof(struct shmem_region,
8221                         dev_info.port_hw_config[params->port].sfp_ctrl)) &
8222                 PORT_HW_CFG_FAULT_MODULE_LED_MASK;
8223         switch (fault_led_gpio) {
8224         case PORT_HW_CFG_FAULT_MODULE_LED_DISABLED:
8225                 return;
8226         case PORT_HW_CFG_FAULT_MODULE_LED_GPIO0:
8227         case PORT_HW_CFG_FAULT_MODULE_LED_GPIO1:
8228         case PORT_HW_CFG_FAULT_MODULE_LED_GPIO2:
8229         case PORT_HW_CFG_FAULT_MODULE_LED_GPIO3:
8230         {
8231                 u8 gpio_port = bnx2x_get_gpio_port(params);
8232                 u16 gpio_pin = fault_led_gpio -
8233                         PORT_HW_CFG_FAULT_MODULE_LED_GPIO0;
8234                 DP(NETIF_MSG_LINK, "Set fault module-detected led "
8235                                    "pin %x port %x mode %x\n",
8236                                gpio_pin, gpio_port, gpio_mode);
8237                 bnx2x_set_gpio(bp, gpio_pin, gpio_mode, gpio_port);
8238         }
8239         break;
8240         default:
8241                 DP(NETIF_MSG_LINK, "Error: Invalid fault led mode 0x%x\n",
8242                                fault_led_gpio);
8243         }
8244 }
8245
8246 static void bnx2x_set_e3_module_fault_led(struct link_params *params,
8247                                           u8 gpio_mode)
8248 {
8249         u32 pin_cfg;
8250         u8 port = params->port;
8251         struct bnx2x *bp = params->bp;
8252         pin_cfg = (REG_RD(bp, params->shmem_base +
8253                          offsetof(struct shmem_region,
8254                                   dev_info.port_hw_config[port].e3_sfp_ctrl)) &
8255                 PORT_HW_CFG_E3_FAULT_MDL_LED_MASK) >>
8256                 PORT_HW_CFG_E3_FAULT_MDL_LED_SHIFT;
8257         DP(NETIF_MSG_LINK, "Setting Fault LED to %d using pin cfg %d\n",
8258                        gpio_mode, pin_cfg);
8259         bnx2x_set_cfg_pin(bp, pin_cfg, gpio_mode);
8260 }
8261
8262 static void bnx2x_set_sfp_module_fault_led(struct link_params *params,
8263                                            u8 gpio_mode)
8264 {
8265         struct bnx2x *bp = params->bp;
8266         DP(NETIF_MSG_LINK, "Setting SFP+ module fault LED to %d\n", gpio_mode);
8267         if (CHIP_IS_E3(bp)) {
8268                 /*
8269                  * Low ==> if SFP+ module is supported otherwise
8270                  * High ==> if SFP+ module is not on the approved vendor list
8271                  */
8272                 bnx2x_set_e3_module_fault_led(params, gpio_mode);
8273         } else
8274                 bnx2x_set_e1e2_module_fault_led(params, gpio_mode);
8275 }
8276
8277 static void bnx2x_warpcore_power_module(struct link_params *params,
8278                                         struct bnx2x_phy *phy,
8279                                         u8 power)
8280 {
8281         u32 pin_cfg;
8282         struct bnx2x *bp = params->bp;
8283
8284         pin_cfg = (REG_RD(bp, params->shmem_base +
8285                           offsetof(struct shmem_region,
8286                         dev_info.port_hw_config[params->port].e3_sfp_ctrl)) &
8287                         PORT_HW_CFG_E3_PWR_DIS_MASK) >>
8288                         PORT_HW_CFG_E3_PWR_DIS_SHIFT;
8289
8290         if (pin_cfg == PIN_CFG_NA)
8291                 return;
8292         DP(NETIF_MSG_LINK, "Setting SFP+ module power to %d using pin cfg %d\n",
8293                        power, pin_cfg);
8294         /*
8295          * Low ==> corresponding SFP+ module is powered
8296          * high ==> the SFP+ module is powered down
8297          */
8298         bnx2x_set_cfg_pin(bp, pin_cfg, power ^ 1);
8299 }
8300
8301 static void bnx2x_warpcore_hw_reset(struct bnx2x_phy *phy,
8302                                     struct link_params *params)
8303 {
8304         struct bnx2x *bp = params->bp;
8305         bnx2x_warpcore_power_module(params, phy, 0);
8306         /* Put Warpcore in low power mode */
8307         REG_WR(bp, MISC_REG_WC0_RESET, 0x0c0e);
8308
8309         /* Put LCPLL in low power mode */
8310         REG_WR(bp, MISC_REG_LCPLL_E40_PWRDWN, 1);
8311         REG_WR(bp, MISC_REG_LCPLL_E40_RESETB_ANA, 0);
8312         REG_WR(bp, MISC_REG_LCPLL_E40_RESETB_DIG, 0);
8313 }
8314
8315 static void bnx2x_power_sfp_module(struct link_params *params,
8316                                    struct bnx2x_phy *phy,
8317                                    u8 power)
8318 {
8319         struct bnx2x *bp = params->bp;
8320         DP(NETIF_MSG_LINK, "Setting SFP+ power to %x\n", power);
8321
8322         switch (phy->type) {
8323         case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8727:
8324         case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8722:
8325                 bnx2x_8727_power_module(params->bp, phy, power);
8326                 break;
8327         case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_DIRECT:
8328                 bnx2x_warpcore_power_module(params, phy, power);
8329                 break;
8330         default:
8331                 break;
8332         }
8333 }
8334 static void bnx2x_warpcore_set_limiting_mode(struct link_params *params,
8335                                              struct bnx2x_phy *phy,
8336                                              u16 edc_mode)
8337 {
8338         u16 val = 0;
8339         u16 mode = MDIO_WC_REG_UC_INFO_B1_FIRMWARE_MODE_DEFAULT;
8340         struct bnx2x *bp = params->bp;
8341
8342         u8 lane = bnx2x_get_warpcore_lane(phy, params);
8343         /* This is a global register which controls all lanes */
8344         bnx2x_cl45_read(bp, phy, MDIO_WC_DEVAD,
8345                         MDIO_WC_REG_UC_INFO_B1_FIRMWARE_MODE, &val);
8346         val &= ~(0xf << (lane << 2));
8347
8348         switch (edc_mode) {
8349         case EDC_MODE_LINEAR:
8350         case EDC_MODE_LIMITING:
8351                 mode = MDIO_WC_REG_UC_INFO_B1_FIRMWARE_MODE_DEFAULT;
8352                 break;
8353         case EDC_MODE_PASSIVE_DAC:
8354                 mode = MDIO_WC_REG_UC_INFO_B1_FIRMWARE_MODE_SFP_DAC;
8355                 break;
8356         default:
8357                 break;
8358         }
8359
8360         val |= (mode << (lane << 2));
8361         bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,
8362                          MDIO_WC_REG_UC_INFO_B1_FIRMWARE_MODE, val);
8363         /* A must read */
8364         bnx2x_cl45_read(bp, phy, MDIO_WC_DEVAD,
8365                         MDIO_WC_REG_UC_INFO_B1_FIRMWARE_MODE, &val);
8366
8367         /* Restart microcode to re-read the new mode */
8368         bnx2x_warpcore_reset_lane(bp, phy, 1);
8369         bnx2x_warpcore_reset_lane(bp, phy, 0);
8370
8371 }
8372
8373 static void bnx2x_set_limiting_mode(struct link_params *params,
8374                                     struct bnx2x_phy *phy,
8375                                     u16 edc_mode)
8376 {
8377         switch (phy->type) {
8378         case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8726:
8379                 bnx2x_8726_set_limiting_mode(params->bp, phy, edc_mode);
8380                 break;
8381         case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8727:
8382         case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8722:
8383                 bnx2x_8727_set_limiting_mode(params->bp, phy, edc_mode);
8384                 break;
8385         case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_DIRECT:
8386                 bnx2x_warpcore_set_limiting_mode(params, phy, edc_mode);
8387                 break;
8388         }
8389 }
8390
8391 int bnx2x_sfp_module_detection(struct bnx2x_phy *phy,
8392                                struct link_params *params)
8393 {
8394         struct bnx2x *bp = params->bp;
8395         u16 edc_mode;
8396         int rc = 0;
8397
8398         u32 val = REG_RD(bp, params->shmem_base +
8399                              offsetof(struct shmem_region, dev_info.
8400                                      port_feature_config[params->port].config));
8401
8402         DP(NETIF_MSG_LINK, "SFP+ module plugged in/out detected on port %d\n",
8403                  params->port);
8404         /* Power up module */
8405         bnx2x_power_sfp_module(params, phy, 1);
8406         if (bnx2x_get_edc_mode(phy, params, &edc_mode) != 0) {
8407                 DP(NETIF_MSG_LINK, "Failed to get valid module type\n");
8408                 return -EINVAL;
8409         } else if (bnx2x_verify_sfp_module(phy, params) != 0) {
8410                 /* check SFP+ module compatibility */
8411                 DP(NETIF_MSG_LINK, "Module verification failed!!\n");
8412                 rc = -EINVAL;
8413                 /* Turn on fault module-detected led */
8414                 bnx2x_set_sfp_module_fault_led(params,
8415                                                MISC_REGISTERS_GPIO_HIGH);
8416
8417                 /* Check if need to power down the SFP+ module */
8418                 if ((val & PORT_FEAT_CFG_OPT_MDL_ENFRCMNT_MASK) ==
8419                      PORT_FEAT_CFG_OPT_MDL_ENFRCMNT_POWER_DOWN) {
8420                         DP(NETIF_MSG_LINK, "Shutdown SFP+ module!!\n");
8421                         bnx2x_power_sfp_module(params, phy, 0);
8422                         return rc;
8423                 }
8424         } else {
8425                 /* Turn off fault module-detected led */
8426                 bnx2x_set_sfp_module_fault_led(params, MISC_REGISTERS_GPIO_LOW);
8427         }
8428
8429         /*
8430          * Check and set limiting mode / LRM mode on 8726. On 8727 it
8431          * is done automatically
8432          */
8433         bnx2x_set_limiting_mode(params, phy, edc_mode);
8434
8435         /*
8436          * Enable transmit for this module if the module is approved, or
8437          * if unapproved modules should also enable the Tx laser
8438          */
8439         if (rc == 0 ||
8440             (val & PORT_FEAT_CFG_OPT_MDL_ENFRCMNT_MASK) !=
8441             PORT_FEAT_CFG_OPT_MDL_ENFRCMNT_DISABLE_TX_LASER)
8442                 bnx2x_sfp_set_transmitter(params, phy, 1);
8443         else
8444                 bnx2x_sfp_set_transmitter(params, phy, 0);
8445
8446         return rc;
8447 }
8448
8449 void bnx2x_handle_module_detect_int(struct link_params *params)
8450 {
8451         struct bnx2x *bp = params->bp;
8452         struct bnx2x_phy *phy;
8453         u32 gpio_val;
8454         u8 gpio_num, gpio_port;
8455         if (CHIP_IS_E3(bp))
8456                 phy = &params->phy[INT_PHY];
8457         else
8458                 phy = &params->phy[EXT_PHY1];
8459
8460         if (bnx2x_get_mod_abs_int_cfg(bp, params->chip_id, params->shmem_base,
8461                                       params->port, &gpio_num, &gpio_port) ==
8462             -EINVAL) {
8463                 DP(NETIF_MSG_LINK, "Failed to get MOD_ABS interrupt config\n");
8464                 return;
8465         }
8466
8467         /* Set valid module led off */
8468         bnx2x_set_sfp_module_fault_led(params, MISC_REGISTERS_GPIO_HIGH);
8469
8470         /* Get current gpio val reflecting module plugged in / out*/
8471         gpio_val = bnx2x_get_gpio(bp, gpio_num, gpio_port);
8472
8473         /* Call the handling function in case module is detected */
8474         if (gpio_val == 0) {
8475                 bnx2x_power_sfp_module(params, phy, 1);
8476                 bnx2x_set_gpio_int(bp, gpio_num,
8477                                    MISC_REGISTERS_GPIO_INT_OUTPUT_CLR,
8478                                    gpio_port);
8479                 if (bnx2x_wait_for_sfp_module_initialized(phy, params) == 0)
8480                         bnx2x_sfp_module_detection(phy, params);
8481                 else
8482                         DP(NETIF_MSG_LINK, "SFP+ module is not initialized\n");
8483         } else {
8484                 u32 val = REG_RD(bp, params->shmem_base +
8485                                  offsetof(struct shmem_region, dev_info.
8486                                           port_feature_config[params->port].
8487                                           config));
8488                 bnx2x_set_gpio_int(bp, gpio_num,
8489                                    MISC_REGISTERS_GPIO_INT_OUTPUT_SET,
8490                                    gpio_port);
8491                 /*
8492                  * Module was plugged out.
8493                  * Disable transmit for this module
8494                  */
8495                 phy->media_type = ETH_PHY_NOT_PRESENT;
8496                 if (((val & PORT_FEAT_CFG_OPT_MDL_ENFRCMNT_MASK) ==
8497                      PORT_FEAT_CFG_OPT_MDL_ENFRCMNT_DISABLE_TX_LASER) ||
8498                     CHIP_IS_E3(bp))
8499                         bnx2x_sfp_set_transmitter(params, phy, 0);
8500         }
8501 }
8502
8503 /******************************************************************/
8504 /*              Used by 8706 and 8727                             */
8505 /******************************************************************/
8506 static void bnx2x_sfp_mask_fault(struct bnx2x *bp,
8507                                  struct bnx2x_phy *phy,
8508                                  u16 alarm_status_offset,
8509                                  u16 alarm_ctrl_offset)
8510 {
8511         u16 alarm_status, val;
8512         bnx2x_cl45_read(bp, phy,
8513                         MDIO_PMA_DEVAD, alarm_status_offset,
8514                         &alarm_status);
8515         bnx2x_cl45_read(bp, phy,
8516                         MDIO_PMA_DEVAD, alarm_status_offset,
8517                         &alarm_status);
8518         /* Mask or enable the fault event. */
8519         bnx2x_cl45_read(bp, phy, MDIO_PMA_DEVAD, alarm_ctrl_offset, &val);
8520         if (alarm_status & (1<<0))
8521                 val &= ~(1<<0);
8522         else
8523                 val |= (1<<0);
8524         bnx2x_cl45_write(bp, phy, MDIO_PMA_DEVAD, alarm_ctrl_offset, val);
8525 }
8526 /******************************************************************/
8527 /*              common BCM8706/BCM8726 PHY SECTION                */
8528 /******************************************************************/
8529 static u8 bnx2x_8706_8726_read_status(struct bnx2x_phy *phy,
8530                                       struct link_params *params,
8531                                       struct link_vars *vars)
8532 {
8533         u8 link_up = 0;
8534         u16 val1, val2, rx_sd, pcs_status;
8535         struct bnx2x *bp = params->bp;
8536         DP(NETIF_MSG_LINK, "XGXS 8706/8726\n");
8537         /* Clear RX Alarm*/
8538         bnx2x_cl45_read(bp, phy,
8539                         MDIO_PMA_DEVAD, MDIO_PMA_LASI_RXSTAT, &val2);
8540
8541         bnx2x_sfp_mask_fault(bp, phy, MDIO_PMA_LASI_TXSTAT,
8542                              MDIO_PMA_LASI_TXCTRL);
8543
8544         /* clear LASI indication*/
8545         bnx2x_cl45_read(bp, phy,
8546                         MDIO_PMA_DEVAD, MDIO_PMA_LASI_STAT, &val1);
8547         bnx2x_cl45_read(bp, phy,
8548                         MDIO_PMA_DEVAD, MDIO_PMA_LASI_STAT, &val2);
8549         DP(NETIF_MSG_LINK, "8706/8726 LASI status 0x%x--> 0x%x\n", val1, val2);
8550
8551         bnx2x_cl45_read(bp, phy,
8552                         MDIO_PMA_DEVAD, MDIO_PMA_REG_RX_SD, &rx_sd);
8553         bnx2x_cl45_read(bp, phy,
8554                         MDIO_PCS_DEVAD, MDIO_PCS_REG_STATUS, &pcs_status);
8555         bnx2x_cl45_read(bp, phy,
8556                         MDIO_AN_DEVAD, MDIO_AN_REG_LINK_STATUS, &val2);
8557         bnx2x_cl45_read(bp, phy,
8558                         MDIO_AN_DEVAD, MDIO_AN_REG_LINK_STATUS, &val2);
8559
8560         DP(NETIF_MSG_LINK, "8706/8726 rx_sd 0x%x pcs_status 0x%x 1Gbps"
8561                         " link_status 0x%x\n", rx_sd, pcs_status, val2);
8562         /*
8563          * link is up if both bit 0 of pmd_rx_sd and bit 0 of pcs_status
8564          * are set, or if the autoneg bit 1 is set
8565          */
8566         link_up = ((rx_sd & pcs_status & 0x1) || (val2 & (1<<1)));
8567         if (link_up) {
8568                 if (val2 & (1<<1))
8569                         vars->line_speed = SPEED_1000;
8570                 else
8571                         vars->line_speed = SPEED_10000;
8572                 bnx2x_ext_phy_resolve_fc(phy, params, vars);
8573                 vars->duplex = DUPLEX_FULL;
8574         }
8575
8576         /* Capture 10G link fault. Read twice to clear stale value. */
8577         if (vars->line_speed == SPEED_10000) {
8578                 bnx2x_cl45_read(bp, phy, MDIO_PMA_DEVAD,
8579                             MDIO_PMA_LASI_TXSTAT, &val1);
8580                 bnx2x_cl45_read(bp, phy, MDIO_PMA_DEVAD,
8581                             MDIO_PMA_LASI_TXSTAT, &val1);
8582                 if (val1 & (1<<0))
8583                         vars->fault_detected = 1;
8584         }
8585
8586         return link_up;
8587 }
8588
8589 /******************************************************************/
8590 /*                      BCM8706 PHY SECTION                       */
8591 /******************************************************************/
8592 static u8 bnx2x_8706_config_init(struct bnx2x_phy *phy,
8593                                  struct link_params *params,
8594                                  struct link_vars *vars)
8595 {
8596         u32 tx_en_mode;
8597         u16 cnt, val, tmp1;
8598         struct bnx2x *bp = params->bp;
8599
8600         bnx2x_set_gpio(bp, MISC_REGISTERS_GPIO_2,
8601                        MISC_REGISTERS_GPIO_OUTPUT_HIGH, params->port);
8602         /* HW reset */
8603         bnx2x_ext_phy_hw_reset(bp, params->port);
8604         bnx2x_cl45_write(bp, phy, MDIO_PMA_DEVAD, MDIO_PMA_REG_CTRL, 0xa040);
8605         bnx2x_wait_reset_complete(bp, phy, params);
8606
8607         /* Wait until fw is loaded */
8608         for (cnt = 0; cnt < 100; cnt++) {
8609                 bnx2x_cl45_read(bp, phy,
8610                                 MDIO_PMA_DEVAD, MDIO_PMA_REG_ROM_VER1, &val);
8611                 if (val)
8612                         break;
8613                 msleep(10);
8614         }
8615         DP(NETIF_MSG_LINK, "XGXS 8706 is initialized after %d ms\n", cnt);
8616         if ((params->feature_config_flags &
8617              FEATURE_CONFIG_OVERRIDE_PREEMPHASIS_ENABLED)) {
8618                 u8 i;
8619                 u16 reg;
8620                 for (i = 0; i < 4; i++) {
8621                         reg = MDIO_XS_8706_REG_BANK_RX0 +
8622                                 i*(MDIO_XS_8706_REG_BANK_RX1 -
8623                                    MDIO_XS_8706_REG_BANK_RX0);
8624                         bnx2x_cl45_read(bp, phy, MDIO_XS_DEVAD, reg, &val);
8625                         /* Clear first 3 bits of the control */
8626                         val &= ~0x7;
8627                         /* Set control bits according to configuration */
8628                         val |= (phy->rx_preemphasis[i] & 0x7);
8629                         DP(NETIF_MSG_LINK, "Setting RX Equalizer to BCM8706"
8630                                    " reg 0x%x <-- val 0x%x\n", reg, val);
8631                         bnx2x_cl45_write(bp, phy, MDIO_XS_DEVAD, reg, val);
8632                 }
8633         }
8634         /* Force speed */
8635         if (phy->req_line_speed == SPEED_10000) {
8636                 DP(NETIF_MSG_LINK, "XGXS 8706 force 10Gbps\n");
8637
8638                 bnx2x_cl45_write(bp, phy,
8639                                  MDIO_PMA_DEVAD,
8640                                  MDIO_PMA_REG_DIGITAL_CTRL, 0x400);
8641                 bnx2x_cl45_write(bp, phy,
8642                                  MDIO_PMA_DEVAD, MDIO_PMA_LASI_TXCTRL,
8643                                  0);
8644                 /* Arm LASI for link and Tx fault. */
8645                 bnx2x_cl45_write(bp, phy,
8646                                  MDIO_PMA_DEVAD, MDIO_PMA_LASI_CTRL, 3);
8647         } else {
8648                 /* Force 1Gbps using autoneg with 1G advertisement */
8649
8650                 /* Allow CL37 through CL73 */
8651                 DP(NETIF_MSG_LINK, "XGXS 8706 AutoNeg\n");
8652                 bnx2x_cl45_write(bp, phy,
8653                                  MDIO_AN_DEVAD, MDIO_AN_REG_CL37_CL73, 0x040c);
8654
8655                 /* Enable Full-Duplex advertisement on CL37 */
8656                 bnx2x_cl45_write(bp, phy,
8657                                  MDIO_AN_DEVAD, MDIO_AN_REG_CL37_FC_LP, 0x0020);
8658                 /* Enable CL37 AN */
8659                 bnx2x_cl45_write(bp, phy,
8660                                  MDIO_AN_DEVAD, MDIO_AN_REG_CL37_AN, 0x1000);
8661                 /* 1G support */
8662                 bnx2x_cl45_write(bp, phy,
8663                                  MDIO_AN_DEVAD, MDIO_AN_REG_ADV, (1<<5));
8664
8665                 /* Enable clause 73 AN */
8666                 bnx2x_cl45_write(bp, phy,
8667                                  MDIO_AN_DEVAD, MDIO_AN_REG_CTRL, 0x1200);
8668                 bnx2x_cl45_write(bp, phy,
8669                                  MDIO_PMA_DEVAD, MDIO_PMA_LASI_RXCTRL,
8670                                  0x0400);
8671                 bnx2x_cl45_write(bp, phy,
8672                                  MDIO_PMA_DEVAD, MDIO_PMA_LASI_CTRL,
8673                                  0x0004);
8674         }
8675         bnx2x_save_bcm_spirom_ver(bp, phy, params->port);
8676
8677         /*
8678          * If TX Laser is controlled by GPIO_0, do not let PHY go into low
8679          * power mode, if TX Laser is disabled
8680          */
8681
8682         tx_en_mode = REG_RD(bp, params->shmem_base +
8683                             offsetof(struct shmem_region,
8684                                 dev_info.port_hw_config[params->port].sfp_ctrl))
8685                         & PORT_HW_CFG_TX_LASER_MASK;
8686
8687         if (tx_en_mode == PORT_HW_CFG_TX_LASER_GPIO0) {
8688                 DP(NETIF_MSG_LINK, "Enabling TXONOFF_PWRDN_DIS\n");
8689                 bnx2x_cl45_read(bp, phy,
8690                         MDIO_PMA_DEVAD, MDIO_PMA_REG_DIGITAL_CTRL, &tmp1);
8691                 tmp1 |= 0x1;
8692                 bnx2x_cl45_write(bp, phy,
8693                         MDIO_PMA_DEVAD, MDIO_PMA_REG_DIGITAL_CTRL, tmp1);
8694         }
8695
8696         return 0;
8697 }
8698
8699 static int bnx2x_8706_read_status(struct bnx2x_phy *phy,
8700                                   struct link_params *params,
8701                                   struct link_vars *vars)
8702 {
8703         return bnx2x_8706_8726_read_status(phy, params, vars);
8704 }
8705
8706 /******************************************************************/
8707 /*                      BCM8726 PHY SECTION                       */
8708 /******************************************************************/
8709 static void bnx2x_8726_config_loopback(struct bnx2x_phy *phy,
8710                                        struct link_params *params)
8711 {
8712         struct bnx2x *bp = params->bp;
8713         DP(NETIF_MSG_LINK, "PMA/PMD ext_phy_loopback: 8726\n");
8714         bnx2x_cl45_write(bp, phy, MDIO_PMA_DEVAD, MDIO_PMA_REG_CTRL, 0x0001);
8715 }
8716
8717 static void bnx2x_8726_external_rom_boot(struct bnx2x_phy *phy,
8718                                          struct link_params *params)
8719 {
8720         struct bnx2x *bp = params->bp;
8721         /* Need to wait 100ms after reset */
8722         msleep(100);
8723
8724         /* Micro controller re-boot */
8725         bnx2x_cl45_write(bp, phy,
8726                          MDIO_PMA_DEVAD, MDIO_PMA_REG_GEN_CTRL, 0x018B);
8727
8728         /* Set soft reset */
8729         bnx2x_cl45_write(bp, phy,
8730                          MDIO_PMA_DEVAD,
8731                          MDIO_PMA_REG_GEN_CTRL,
8732                          MDIO_PMA_REG_GEN_CTRL_ROM_MICRO_RESET);
8733
8734         bnx2x_cl45_write(bp, phy,
8735                          MDIO_PMA_DEVAD,
8736                          MDIO_PMA_REG_MISC_CTRL1, 0x0001);
8737
8738         bnx2x_cl45_write(bp, phy,
8739                          MDIO_PMA_DEVAD,
8740                          MDIO_PMA_REG_GEN_CTRL,
8741                          MDIO_PMA_REG_GEN_CTRL_ROM_RESET_INTERNAL_MP);
8742
8743         /* wait for 150ms for microcode load */
8744         msleep(150);
8745
8746         /* Disable serial boot control, tristates pins SS_N, SCK, MOSI, MISO */
8747         bnx2x_cl45_write(bp, phy,
8748                          MDIO_PMA_DEVAD,
8749                          MDIO_PMA_REG_MISC_CTRL1, 0x0000);
8750
8751         msleep(200);
8752         bnx2x_save_bcm_spirom_ver(bp, phy, params->port);
8753 }
8754
8755 static u8 bnx2x_8726_read_status(struct bnx2x_phy *phy,
8756                                  struct link_params *params,
8757                                  struct link_vars *vars)
8758 {
8759         struct bnx2x *bp = params->bp;
8760         u16 val1;
8761         u8 link_up = bnx2x_8706_8726_read_status(phy, params, vars);
8762         if (link_up) {
8763                 bnx2x_cl45_read(bp, phy,
8764                                 MDIO_PMA_DEVAD, MDIO_PMA_REG_PHY_IDENTIFIER,
8765                                 &val1);
8766                 if (val1 & (1<<15)) {
8767                         DP(NETIF_MSG_LINK, "Tx is disabled\n");
8768                         link_up = 0;
8769                         vars->line_speed = 0;
8770                 }
8771         }
8772         return link_up;
8773 }
8774
8775
8776 static int bnx2x_8726_config_init(struct bnx2x_phy *phy,
8777                                   struct link_params *params,
8778                                   struct link_vars *vars)
8779 {
8780         struct bnx2x *bp = params->bp;
8781         DP(NETIF_MSG_LINK, "Initializing BCM8726\n");
8782
8783         bnx2x_cl45_write(bp, phy, MDIO_PMA_DEVAD, MDIO_PMA_REG_CTRL, 1<<15);
8784         bnx2x_wait_reset_complete(bp, phy, params);
8785
8786         bnx2x_8726_external_rom_boot(phy, params);
8787
8788         /*
8789          * Need to call module detected on initialization since the module
8790          * detection triggered by actual module insertion might occur before
8791          * driver is loaded, and when driver is loaded, it reset all
8792          * registers, including the transmitter
8793          */
8794         bnx2x_sfp_module_detection(phy, params);
8795
8796         if (phy->req_line_speed == SPEED_1000) {
8797                 DP(NETIF_MSG_LINK, "Setting 1G force\n");
8798                 bnx2x_cl45_write(bp, phy,
8799                                  MDIO_PMA_DEVAD, MDIO_PMA_REG_CTRL, 0x40);
8800                 bnx2x_cl45_write(bp, phy,
8801                                  MDIO_PMA_DEVAD, MDIO_PMA_REG_10G_CTRL2, 0xD);
8802                 bnx2x_cl45_write(bp, phy,
8803                                  MDIO_PMA_DEVAD, MDIO_PMA_LASI_CTRL, 0x5);
8804                 bnx2x_cl45_write(bp, phy,
8805                                  MDIO_PMA_DEVAD, MDIO_PMA_LASI_RXCTRL,
8806                                  0x400);
8807         } else if ((phy->req_line_speed == SPEED_AUTO_NEG) &&
8808                    (phy->speed_cap_mask &
8809                       PORT_HW_CFG_SPEED_CAPABILITY_D0_1G) &&
8810                    ((phy->speed_cap_mask &
8811                       PORT_HW_CFG_SPEED_CAPABILITY_D0_10G) !=
8812                     PORT_HW_CFG_SPEED_CAPABILITY_D0_10G)) {
8813                 DP(NETIF_MSG_LINK, "Setting 1G clause37\n");
8814                 /* Set Flow control */
8815                 bnx2x_ext_phy_set_pause(params, phy, vars);
8816                 bnx2x_cl45_write(bp, phy,
8817                                  MDIO_AN_DEVAD, MDIO_AN_REG_ADV, 0x20);
8818                 bnx2x_cl45_write(bp, phy,
8819                                  MDIO_AN_DEVAD, MDIO_AN_REG_CL37_CL73, 0x040c);
8820                 bnx2x_cl45_write(bp, phy,
8821                                  MDIO_AN_DEVAD, MDIO_AN_REG_CL37_FC_LD, 0x0020);
8822                 bnx2x_cl45_write(bp, phy,
8823                                  MDIO_AN_DEVAD, MDIO_AN_REG_CL37_AN, 0x1000);
8824                 bnx2x_cl45_write(bp, phy,
8825                                 MDIO_AN_DEVAD, MDIO_AN_REG_CTRL, 0x1200);
8826                 /*
8827                  * Enable RX-ALARM control to receive interrupt for 1G speed
8828                  * change
8829                  */
8830                 bnx2x_cl45_write(bp, phy,
8831                                  MDIO_PMA_DEVAD, MDIO_PMA_LASI_CTRL, 0x4);
8832                 bnx2x_cl45_write(bp, phy,
8833                                  MDIO_PMA_DEVAD, MDIO_PMA_LASI_RXCTRL,
8834                                  0x400);
8835
8836         } else { /* Default 10G. Set only LASI control */
8837                 bnx2x_cl45_write(bp, phy,
8838                                  MDIO_PMA_DEVAD, MDIO_PMA_LASI_CTRL, 1);
8839         }
8840
8841         /* Set TX PreEmphasis if needed */
8842         if ((params->feature_config_flags &
8843              FEATURE_CONFIG_OVERRIDE_PREEMPHASIS_ENABLED)) {
8844                 DP(NETIF_MSG_LINK,
8845                    "Setting TX_CTRL1 0x%x, TX_CTRL2 0x%x\n",
8846                          phy->tx_preemphasis[0],
8847                          phy->tx_preemphasis[1]);
8848                 bnx2x_cl45_write(bp, phy,
8849                                  MDIO_PMA_DEVAD,
8850                                  MDIO_PMA_REG_8726_TX_CTRL1,
8851                                  phy->tx_preemphasis[0]);
8852
8853                 bnx2x_cl45_write(bp, phy,
8854                                  MDIO_PMA_DEVAD,
8855                                  MDIO_PMA_REG_8726_TX_CTRL2,
8856                                  phy->tx_preemphasis[1]);
8857         }
8858
8859         return 0;
8860
8861 }
8862
8863 static void bnx2x_8726_link_reset(struct bnx2x_phy *phy,
8864                                   struct link_params *params)
8865 {
8866         struct bnx2x *bp = params->bp;
8867         DP(NETIF_MSG_LINK, "bnx2x_8726_link_reset port %d\n", params->port);
8868         /* Set serial boot control for external load */
8869         bnx2x_cl45_write(bp, phy,
8870                          MDIO_PMA_DEVAD,
8871                          MDIO_PMA_REG_GEN_CTRL, 0x0001);
8872 }
8873
8874 /******************************************************************/
8875 /*                      BCM8727 PHY SECTION                       */
8876 /******************************************************************/
8877
8878 static void bnx2x_8727_set_link_led(struct bnx2x_phy *phy,
8879                                     struct link_params *params, u8 mode)
8880 {
8881         struct bnx2x *bp = params->bp;
8882         u16 led_mode_bitmask = 0;
8883         u16 gpio_pins_bitmask = 0;
8884         u16 val;
8885         /* Only NOC flavor requires to set the LED specifically */
8886         if (!(phy->flags & FLAGS_NOC))
8887                 return;
8888         switch (mode) {
8889         case LED_MODE_FRONT_PANEL_OFF:
8890         case LED_MODE_OFF:
8891                 led_mode_bitmask = 0;
8892                 gpio_pins_bitmask = 0x03;
8893                 break;
8894         case LED_MODE_ON:
8895                 led_mode_bitmask = 0;
8896                 gpio_pins_bitmask = 0x02;
8897                 break;
8898         case LED_MODE_OPER:
8899                 led_mode_bitmask = 0x60;
8900                 gpio_pins_bitmask = 0x11;
8901                 break;
8902         }
8903         bnx2x_cl45_read(bp, phy,
8904                         MDIO_PMA_DEVAD,
8905                         MDIO_PMA_REG_8727_PCS_OPT_CTRL,
8906                         &val);
8907         val &= 0xff8f;
8908         val |= led_mode_bitmask;
8909         bnx2x_cl45_write(bp, phy,
8910                          MDIO_PMA_DEVAD,
8911                          MDIO_PMA_REG_8727_PCS_OPT_CTRL,
8912                          val);
8913         bnx2x_cl45_read(bp, phy,
8914                         MDIO_PMA_DEVAD,
8915                         MDIO_PMA_REG_8727_GPIO_CTRL,
8916                         &val);
8917         val &= 0xffe0;
8918         val |= gpio_pins_bitmask;
8919         bnx2x_cl45_write(bp, phy,
8920                          MDIO_PMA_DEVAD,
8921                          MDIO_PMA_REG_8727_GPIO_CTRL,
8922                          val);
8923 }
8924 static void bnx2x_8727_hw_reset(struct bnx2x_phy *phy,
8925                                 struct link_params *params) {
8926         u32 swap_val, swap_override;
8927         u8 port;
8928         /*
8929          * The PHY reset is controlled by GPIO 1. Fake the port number
8930          * to cancel the swap done in set_gpio()
8931          */
8932         struct bnx2x *bp = params->bp;
8933         swap_val = REG_RD(bp, NIG_REG_PORT_SWAP);
8934         swap_override = REG_RD(bp, NIG_REG_STRAP_OVERRIDE);
8935         port = (swap_val && swap_override) ^ 1;
8936         bnx2x_set_gpio(bp, MISC_REGISTERS_GPIO_1,
8937                        MISC_REGISTERS_GPIO_OUTPUT_LOW, port);
8938 }
8939
8940 static int bnx2x_8727_config_init(struct bnx2x_phy *phy,
8941                                   struct link_params *params,
8942                                   struct link_vars *vars)
8943 {
8944         u32 tx_en_mode;
8945         u16 tmp1, val, mod_abs, tmp2;
8946         u16 rx_alarm_ctrl_val;
8947         u16 lasi_ctrl_val;
8948         struct bnx2x *bp = params->bp;
8949         /* Enable PMD link, MOD_ABS_FLT, and 1G link alarm */
8950
8951         bnx2x_wait_reset_complete(bp, phy, params);
8952         rx_alarm_ctrl_val = (1<<2) | (1<<5) ;
8953         /* Should be 0x6 to enable XS on Tx side. */
8954         lasi_ctrl_val = 0x0006;
8955
8956         DP(NETIF_MSG_LINK, "Initializing BCM8727\n");
8957         /* enable LASI */
8958         bnx2x_cl45_write(bp, phy,
8959                          MDIO_PMA_DEVAD, MDIO_PMA_LASI_RXCTRL,
8960                          rx_alarm_ctrl_val);
8961         bnx2x_cl45_write(bp, phy,
8962                          MDIO_PMA_DEVAD, MDIO_PMA_LASI_TXCTRL,
8963                          0);
8964         bnx2x_cl45_write(bp, phy,
8965                          MDIO_PMA_DEVAD, MDIO_PMA_LASI_CTRL, lasi_ctrl_val);
8966
8967         /*
8968          * Initially configure MOD_ABS to interrupt when module is
8969          * presence( bit 8)
8970          */
8971         bnx2x_cl45_read(bp, phy,
8972                         MDIO_PMA_DEVAD, MDIO_PMA_REG_PHY_IDENTIFIER, &mod_abs);
8973         /*
8974          * Set EDC off by setting OPTXLOS signal input to low (bit 9).
8975          * When the EDC is off it locks onto a reference clock and avoids
8976          * becoming 'lost'
8977          */
8978         mod_abs &= ~(1<<8);
8979         if (!(phy->flags & FLAGS_NOC))
8980                 mod_abs &= ~(1<<9);
8981         bnx2x_cl45_write(bp, phy,
8982                          MDIO_PMA_DEVAD, MDIO_PMA_REG_PHY_IDENTIFIER, mod_abs);
8983
8984
8985         /* Enable/Disable PHY transmitter output */
8986         bnx2x_set_disable_pmd_transmit(params, phy, 0);
8987
8988         /* Make MOD_ABS give interrupt on change */
8989         bnx2x_cl45_read(bp, phy, MDIO_PMA_DEVAD, MDIO_PMA_REG_8727_PCS_OPT_CTRL,
8990                         &val);
8991         val |= (1<<12);
8992         if (phy->flags & FLAGS_NOC)
8993                 val |= (3<<5);
8994
8995         /*
8996          * Set 8727 GPIOs to input to allow reading from the 8727 GPIO0
8997          * status which reflect SFP+ module over-current
8998          */
8999         if (!(phy->flags & FLAGS_NOC))
9000                 val &= 0xff8f; /* Reset bits 4-6 */
9001         bnx2x_cl45_write(bp, phy,
9002                          MDIO_PMA_DEVAD, MDIO_PMA_REG_8727_PCS_OPT_CTRL, val);
9003
9004         bnx2x_8727_power_module(bp, phy, 1);
9005
9006         bnx2x_cl45_read(bp, phy,
9007                         MDIO_PMA_DEVAD, MDIO_PMA_REG_M8051_MSGOUT_REG, &tmp1);
9008
9009         bnx2x_cl45_read(bp, phy,
9010                         MDIO_PMA_DEVAD, MDIO_PMA_LASI_RXSTAT, &tmp1);
9011
9012         /* Set option 1G speed */
9013         if (phy->req_line_speed == SPEED_1000) {
9014                 DP(NETIF_MSG_LINK, "Setting 1G force\n");
9015                 bnx2x_cl45_write(bp, phy,
9016                                  MDIO_PMA_DEVAD, MDIO_PMA_REG_CTRL, 0x40);
9017                 bnx2x_cl45_write(bp, phy,
9018                                  MDIO_PMA_DEVAD, MDIO_PMA_REG_10G_CTRL2, 0xD);
9019                 bnx2x_cl45_read(bp, phy,
9020                                 MDIO_PMA_DEVAD, MDIO_PMA_REG_10G_CTRL2, &tmp1);
9021                 DP(NETIF_MSG_LINK, "1.7 = 0x%x\n", tmp1);
9022                 /*
9023                  * Power down the XAUI until link is up in case of dual-media
9024                  * and 1G
9025                  */
9026                 if (DUAL_MEDIA(params)) {
9027                         bnx2x_cl45_read(bp, phy,
9028                                         MDIO_PMA_DEVAD,
9029                                         MDIO_PMA_REG_8727_PCS_GP, &val);
9030                         val |= (3<<10);
9031                         bnx2x_cl45_write(bp, phy,
9032                                          MDIO_PMA_DEVAD,
9033                                          MDIO_PMA_REG_8727_PCS_GP, val);
9034                 }
9035         } else if ((phy->req_line_speed == SPEED_AUTO_NEG) &&
9036                    ((phy->speed_cap_mask &
9037                      PORT_HW_CFG_SPEED_CAPABILITY_D0_1G)) &&
9038                    ((phy->speed_cap_mask &
9039                       PORT_HW_CFG_SPEED_CAPABILITY_D0_10G) !=
9040                    PORT_HW_CFG_SPEED_CAPABILITY_D0_10G)) {
9041
9042                 DP(NETIF_MSG_LINK, "Setting 1G clause37\n");
9043                 bnx2x_cl45_write(bp, phy,
9044                                  MDIO_AN_DEVAD, MDIO_AN_REG_8727_MISC_CTRL, 0);
9045                 bnx2x_cl45_write(bp, phy,
9046                                  MDIO_AN_DEVAD, MDIO_AN_REG_CL37_AN, 0x1300);
9047         } else {
9048                 /*
9049                  * Since the 8727 has only single reset pin, need to set the 10G
9050                  * registers although it is default
9051                  */
9052                 bnx2x_cl45_write(bp, phy,
9053                                  MDIO_AN_DEVAD, MDIO_AN_REG_8727_MISC_CTRL,
9054                                  0x0020);
9055                 bnx2x_cl45_write(bp, phy,
9056                                  MDIO_AN_DEVAD, MDIO_AN_REG_CL37_AN, 0x0100);
9057                 bnx2x_cl45_write(bp, phy,
9058                                  MDIO_PMA_DEVAD, MDIO_PMA_REG_CTRL, 0x2040);
9059                 bnx2x_cl45_write(bp, phy,
9060                                  MDIO_PMA_DEVAD, MDIO_PMA_REG_10G_CTRL2,
9061                                  0x0008);
9062         }
9063
9064         /*
9065          * Set 2-wire transfer rate of SFP+ module EEPROM
9066          * to 100Khz since some DACs(direct attached cables) do
9067          * not work at 400Khz.
9068          */
9069         bnx2x_cl45_write(bp, phy,
9070                          MDIO_PMA_DEVAD, MDIO_PMA_REG_8727_TWO_WIRE_SLAVE_ADDR,
9071                          0xa001);
9072
9073         /* Set TX PreEmphasis if needed */
9074         if ((params->feature_config_flags &
9075              FEATURE_CONFIG_OVERRIDE_PREEMPHASIS_ENABLED)) {
9076                 DP(NETIF_MSG_LINK, "Setting TX_CTRL1 0x%x, TX_CTRL2 0x%x\n",
9077                            phy->tx_preemphasis[0],
9078                            phy->tx_preemphasis[1]);
9079                 bnx2x_cl45_write(bp, phy,
9080                                  MDIO_PMA_DEVAD, MDIO_PMA_REG_8727_TX_CTRL1,
9081                                  phy->tx_preemphasis[0]);
9082
9083                 bnx2x_cl45_write(bp, phy,
9084                                  MDIO_PMA_DEVAD, MDIO_PMA_REG_8727_TX_CTRL2,
9085                                  phy->tx_preemphasis[1]);
9086         }
9087
9088         /*
9089          * If TX Laser is controlled by GPIO_0, do not let PHY go into low
9090          * power mode, if TX Laser is disabled
9091          */
9092         tx_en_mode = REG_RD(bp, params->shmem_base +
9093                             offsetof(struct shmem_region,
9094                                 dev_info.port_hw_config[params->port].sfp_ctrl))
9095                         & PORT_HW_CFG_TX_LASER_MASK;
9096
9097         if (tx_en_mode == PORT_HW_CFG_TX_LASER_GPIO0) {
9098
9099                 DP(NETIF_MSG_LINK, "Enabling TXONOFF_PWRDN_DIS\n");
9100                 bnx2x_cl45_read(bp, phy,
9101                         MDIO_PMA_DEVAD, MDIO_PMA_REG_8727_OPT_CFG_REG, &tmp2);
9102                 tmp2 |= 0x1000;
9103                 tmp2 &= 0xFFEF;
9104                 bnx2x_cl45_write(bp, phy,
9105                         MDIO_PMA_DEVAD, MDIO_PMA_REG_8727_OPT_CFG_REG, tmp2);
9106         }
9107
9108         return 0;
9109 }
9110
9111 static void bnx2x_8727_handle_mod_abs(struct bnx2x_phy *phy,
9112                                       struct link_params *params)
9113 {
9114         struct bnx2x *bp = params->bp;
9115         u16 mod_abs, rx_alarm_status;
9116         u32 val = REG_RD(bp, params->shmem_base +
9117                              offsetof(struct shmem_region, dev_info.
9118                                       port_feature_config[params->port].
9119                                       config));
9120         bnx2x_cl45_read(bp, phy,
9121                         MDIO_PMA_DEVAD,
9122                         MDIO_PMA_REG_PHY_IDENTIFIER, &mod_abs);
9123         if (mod_abs & (1<<8)) {
9124
9125                 /* Module is absent */
9126                 DP(NETIF_MSG_LINK,
9127                    "MOD_ABS indication show module is absent\n");
9128                 phy->media_type = ETH_PHY_NOT_PRESENT;
9129                 /*
9130                  * 1. Set mod_abs to detect next module
9131                  *    presence event
9132                  * 2. Set EDC off by setting OPTXLOS signal input to low
9133                  *    (bit 9).
9134                  *    When the EDC is off it locks onto a reference clock and
9135                  *    avoids becoming 'lost'.
9136                  */
9137                 mod_abs &= ~(1<<8);
9138                 if (!(phy->flags & FLAGS_NOC))
9139                         mod_abs &= ~(1<<9);
9140                 bnx2x_cl45_write(bp, phy,
9141                                  MDIO_PMA_DEVAD,
9142                                  MDIO_PMA_REG_PHY_IDENTIFIER, mod_abs);
9143
9144                 /*
9145                  * Clear RX alarm since it stays up as long as
9146                  * the mod_abs wasn't changed
9147                  */
9148                 bnx2x_cl45_read(bp, phy,
9149                                 MDIO_PMA_DEVAD,
9150                                 MDIO_PMA_LASI_RXSTAT, &rx_alarm_status);
9151
9152         } else {
9153                 /* Module is present */
9154                 DP(NETIF_MSG_LINK,
9155                    "MOD_ABS indication show module is present\n");
9156                 /*
9157                  * First disable transmitter, and if the module is ok, the
9158                  * module_detection will enable it
9159                  * 1. Set mod_abs to detect next module absent event ( bit 8)
9160                  * 2. Restore the default polarity of the OPRXLOS signal and
9161                  * this signal will then correctly indicate the presence or
9162                  * absence of the Rx signal. (bit 9)
9163                  */
9164                 mod_abs |= (1<<8);
9165                 if (!(phy->flags & FLAGS_NOC))
9166                         mod_abs |= (1<<9);
9167                 bnx2x_cl45_write(bp, phy,
9168                                  MDIO_PMA_DEVAD,
9169                                  MDIO_PMA_REG_PHY_IDENTIFIER, mod_abs);
9170
9171                 /*
9172                  * Clear RX alarm since it stays up as long as the mod_abs
9173                  * wasn't changed. This is need to be done before calling the
9174                  * module detection, otherwise it will clear* the link update
9175                  * alarm
9176                  */
9177                 bnx2x_cl45_read(bp, phy,
9178                                 MDIO_PMA_DEVAD,
9179                                 MDIO_PMA_LASI_RXSTAT, &rx_alarm_status);
9180
9181
9182                 if ((val & PORT_FEAT_CFG_OPT_MDL_ENFRCMNT_MASK) ==
9183                     PORT_FEAT_CFG_OPT_MDL_ENFRCMNT_DISABLE_TX_LASER)
9184                         bnx2x_sfp_set_transmitter(params, phy, 0);
9185
9186                 if (bnx2x_wait_for_sfp_module_initialized(phy, params) == 0)
9187                         bnx2x_sfp_module_detection(phy, params);
9188                 else
9189                         DP(NETIF_MSG_LINK, "SFP+ module is not initialized\n");
9190         }
9191
9192         DP(NETIF_MSG_LINK, "8727 RX_ALARM_STATUS 0x%x\n",
9193                    rx_alarm_status);
9194         /* No need to check link status in case of module plugged in/out */
9195 }
9196
9197 static u8 bnx2x_8727_read_status(struct bnx2x_phy *phy,
9198                                  struct link_params *params,
9199                                  struct link_vars *vars)
9200
9201 {
9202         struct bnx2x *bp = params->bp;
9203         u8 link_up = 0, oc_port = params->port;
9204         u16 link_status = 0;
9205         u16 rx_alarm_status, lasi_ctrl, val1;
9206
9207         /* If PHY is not initialized, do not check link status */
9208         bnx2x_cl45_read(bp, phy,
9209                         MDIO_PMA_DEVAD, MDIO_PMA_LASI_CTRL,
9210                         &lasi_ctrl);
9211         if (!lasi_ctrl)
9212                 return 0;
9213
9214         /* Check the LASI on Rx */
9215         bnx2x_cl45_read(bp, phy,
9216                         MDIO_PMA_DEVAD, MDIO_PMA_LASI_RXSTAT,
9217                         &rx_alarm_status);
9218         vars->line_speed = 0;
9219         DP(NETIF_MSG_LINK, "8727 RX_ALARM_STATUS  0x%x\n", rx_alarm_status);
9220
9221         bnx2x_sfp_mask_fault(bp, phy, MDIO_PMA_LASI_TXSTAT,
9222                              MDIO_PMA_LASI_TXCTRL);
9223
9224         bnx2x_cl45_read(bp, phy,
9225                         MDIO_PMA_DEVAD, MDIO_PMA_LASI_STAT, &val1);
9226
9227         DP(NETIF_MSG_LINK, "8727 LASI status 0x%x\n", val1);
9228
9229         /* Clear MSG-OUT */
9230         bnx2x_cl45_read(bp, phy,
9231                         MDIO_PMA_DEVAD, MDIO_PMA_REG_M8051_MSGOUT_REG, &val1);
9232
9233         /*
9234          * If a module is present and there is need to check
9235          * for over current
9236          */
9237         if (!(phy->flags & FLAGS_NOC) && !(rx_alarm_status & (1<<5))) {
9238                 /* Check over-current using 8727 GPIO0 input*/
9239                 bnx2x_cl45_read(bp, phy,
9240                                 MDIO_PMA_DEVAD, MDIO_PMA_REG_8727_GPIO_CTRL,
9241                                 &val1);
9242
9243                 if ((val1 & (1<<8)) == 0) {
9244                         if (!CHIP_IS_E1x(bp))
9245                                 oc_port = BP_PATH(bp) + (params->port << 1);
9246                         DP(NETIF_MSG_LINK,
9247                            "8727 Power fault has been detected on port %d\n",
9248                            oc_port);
9249                         netdev_err(bp->dev, "Error: Power fault on Port %d has "
9250                                             "been detected and the power to "
9251                                             "that SFP+ module has been removed "
9252                                             "to prevent failure of the card. "
9253                                             "Please remove the SFP+ module and "
9254                                             "restart the system to clear this "
9255                                             "error.\n",
9256                          oc_port);
9257                         /* Disable all RX_ALARMs except for mod_abs */
9258                         bnx2x_cl45_write(bp, phy,
9259                                          MDIO_PMA_DEVAD,
9260                                          MDIO_PMA_LASI_RXCTRL, (1<<5));
9261
9262                         bnx2x_cl45_read(bp, phy,
9263                                         MDIO_PMA_DEVAD,
9264                                         MDIO_PMA_REG_PHY_IDENTIFIER, &val1);
9265                         /* Wait for module_absent_event */
9266                         val1 |= (1<<8);
9267                         bnx2x_cl45_write(bp, phy,
9268                                          MDIO_PMA_DEVAD,
9269                                          MDIO_PMA_REG_PHY_IDENTIFIER, val1);
9270                         /* Clear RX alarm */
9271                         bnx2x_cl45_read(bp, phy,
9272                                 MDIO_PMA_DEVAD,
9273                                 MDIO_PMA_LASI_RXSTAT, &rx_alarm_status);
9274                         return 0;
9275                 }
9276         } /* Over current check */
9277
9278         /* When module absent bit is set, check module */
9279         if (rx_alarm_status & (1<<5)) {
9280                 bnx2x_8727_handle_mod_abs(phy, params);
9281                 /* Enable all mod_abs and link detection bits */
9282                 bnx2x_cl45_write(bp, phy,
9283                                  MDIO_PMA_DEVAD, MDIO_PMA_LASI_RXCTRL,
9284                                  ((1<<5) | (1<<2)));
9285         }
9286         DP(NETIF_MSG_LINK, "Enabling 8727 TX laser if SFP is approved\n");
9287         bnx2x_8727_specific_func(phy, params, ENABLE_TX);
9288         /* If transmitter is disabled, ignore false link up indication */
9289         bnx2x_cl45_read(bp, phy,
9290                         MDIO_PMA_DEVAD, MDIO_PMA_REG_PHY_IDENTIFIER, &val1);
9291         if (val1 & (1<<15)) {
9292                 DP(NETIF_MSG_LINK, "Tx is disabled\n");
9293                 return 0;
9294         }
9295
9296         bnx2x_cl45_read(bp, phy,
9297                         MDIO_PMA_DEVAD,
9298                         MDIO_PMA_REG_8073_SPEED_LINK_STATUS, &link_status);
9299
9300         /*
9301          * Bits 0..2 --> speed detected,
9302          * Bits 13..15--> link is down
9303          */
9304         if ((link_status & (1<<2)) && (!(link_status & (1<<15)))) {
9305                 link_up = 1;
9306                 vars->line_speed = SPEED_10000;
9307                 DP(NETIF_MSG_LINK, "port %x: External link up in 10G\n",
9308                            params->port);
9309         } else if ((link_status & (1<<0)) && (!(link_status & (1<<13)))) {
9310                 link_up = 1;
9311                 vars->line_speed = SPEED_1000;
9312                 DP(NETIF_MSG_LINK, "port %x: External link up in 1G\n",
9313                            params->port);
9314         } else {
9315                 link_up = 0;
9316                 DP(NETIF_MSG_LINK, "port %x: External link is down\n",
9317                            params->port);
9318         }
9319
9320         /* Capture 10G link fault. */
9321         if (vars->line_speed == SPEED_10000) {
9322                 bnx2x_cl45_read(bp, phy, MDIO_PMA_DEVAD,
9323                             MDIO_PMA_LASI_TXSTAT, &val1);
9324
9325                 bnx2x_cl45_read(bp, phy, MDIO_PMA_DEVAD,
9326                             MDIO_PMA_LASI_TXSTAT, &val1);
9327
9328                 if (val1 & (1<<0)) {
9329                         vars->fault_detected = 1;
9330                 }
9331         }
9332
9333         if (link_up) {
9334                 bnx2x_ext_phy_resolve_fc(phy, params, vars);
9335                 vars->duplex = DUPLEX_FULL;
9336                 DP(NETIF_MSG_LINK, "duplex = 0x%x\n", vars->duplex);
9337         }
9338
9339         if ((DUAL_MEDIA(params)) &&
9340             (phy->req_line_speed == SPEED_1000)) {
9341                 bnx2x_cl45_read(bp, phy,
9342                                 MDIO_PMA_DEVAD,
9343                                 MDIO_PMA_REG_8727_PCS_GP, &val1);
9344                 /*
9345                  * In case of dual-media board and 1G, power up the XAUI side,
9346                  * otherwise power it down. For 10G it is done automatically
9347                  */
9348                 if (link_up)
9349                         val1 &= ~(3<<10);
9350                 else
9351                         val1 |= (3<<10);
9352                 bnx2x_cl45_write(bp, phy,
9353                                  MDIO_PMA_DEVAD,
9354                                  MDIO_PMA_REG_8727_PCS_GP, val1);
9355         }
9356         return link_up;
9357 }
9358
9359 static void bnx2x_8727_link_reset(struct bnx2x_phy *phy,
9360                                   struct link_params *params)
9361 {
9362         struct bnx2x *bp = params->bp;
9363
9364         /* Enable/Disable PHY transmitter output */
9365         bnx2x_set_disable_pmd_transmit(params, phy, 1);
9366
9367         /* Disable Transmitter */
9368         bnx2x_sfp_set_transmitter(params, phy, 0);
9369         /* Clear LASI */
9370         bnx2x_cl45_write(bp, phy, MDIO_PMA_DEVAD, MDIO_PMA_LASI_CTRL, 0);
9371
9372 }
9373
9374 /******************************************************************/
9375 /*              BCM8481/BCM84823/BCM84833 PHY SECTION             */
9376 /******************************************************************/
9377 static void bnx2x_save_848xx_spirom_version(struct bnx2x_phy *phy,
9378                                             struct bnx2x *bp,
9379                                             u8 port)
9380 {
9381         u16 val, fw_ver1, fw_ver2, cnt;
9382
9383         if (phy->type == PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM84833) {
9384                 bnx2x_cl45_read(bp, phy, MDIO_CTL_DEVAD, 0x400f, &fw_ver1);
9385                 bnx2x_save_spirom_version(bp, port,
9386                                 ((fw_ver1 & 0xf000)>>5) | (fw_ver1 & 0x7f),
9387                                 phy->ver_addr);
9388         } else {
9389                 /* For 32-bit registers in 848xx, access via MDIO2ARM i/f. */
9390                 /* (1) set reg 0xc200_0014(SPI_BRIDGE_CTRL_2) to 0x03000000 */
9391                 bnx2x_cl45_write(bp, phy, MDIO_PMA_DEVAD, 0xA819, 0x0014);
9392                 bnx2x_cl45_write(bp, phy, MDIO_PMA_DEVAD, 0xA81A, 0xc200);
9393                 bnx2x_cl45_write(bp, phy, MDIO_PMA_DEVAD, 0xA81B, 0x0000);
9394                 bnx2x_cl45_write(bp, phy, MDIO_PMA_DEVAD, 0xA81C, 0x0300);
9395                 bnx2x_cl45_write(bp, phy, MDIO_PMA_DEVAD, 0xA817, 0x0009);
9396
9397                 for (cnt = 0; cnt < 100; cnt++) {
9398                         bnx2x_cl45_read(bp, phy, MDIO_PMA_DEVAD, 0xA818, &val);
9399                         if (val & 1)
9400                                 break;
9401                         udelay(5);
9402                 }
9403                 if (cnt == 100) {
9404                         DP(NETIF_MSG_LINK, "Unable to read 848xx "
9405                                         "phy fw version(1)\n");
9406                         bnx2x_save_spirom_version(bp, port, 0,
9407                                                   phy->ver_addr);
9408                         return;
9409                 }
9410
9411
9412                 /* 2) read register 0xc200_0000 (SPI_FW_STATUS) */
9413                 bnx2x_cl45_write(bp, phy, MDIO_PMA_DEVAD, 0xA819, 0x0000);
9414                 bnx2x_cl45_write(bp, phy, MDIO_PMA_DEVAD, 0xA81A, 0xc200);
9415                 bnx2x_cl45_write(bp, phy, MDIO_PMA_DEVAD, 0xA817, 0x000A);
9416                 for (cnt = 0; cnt < 100; cnt++) {
9417                         bnx2x_cl45_read(bp, phy, MDIO_PMA_DEVAD, 0xA818, &val);
9418                         if (val & 1)
9419                                 break;
9420                         udelay(5);
9421                 }
9422                 if (cnt == 100) {
9423                         DP(NETIF_MSG_LINK, "Unable to read 848xx phy fw "
9424                                         "version(2)\n");
9425                         bnx2x_save_spirom_version(bp, port, 0,
9426                                                   phy->ver_addr);
9427                         return;
9428                 }
9429
9430                 /* lower 16 bits of the register SPI_FW_STATUS */
9431                 bnx2x_cl45_read(bp, phy, MDIO_PMA_DEVAD, 0xA81B, &fw_ver1);
9432                 /* upper 16 bits of register SPI_FW_STATUS */
9433                 bnx2x_cl45_read(bp, phy, MDIO_PMA_DEVAD, 0xA81C, &fw_ver2);
9434
9435                 bnx2x_save_spirom_version(bp, port, (fw_ver2<<16) | fw_ver1,
9436                                           phy->ver_addr);
9437         }
9438
9439 }
9440 static void bnx2x_848xx_set_led(struct bnx2x *bp,
9441                                 struct bnx2x_phy *phy)
9442 {
9443         u16 val, offset;
9444
9445         /* PHYC_CTL_LED_CTL */
9446         bnx2x_cl45_read(bp, phy,
9447                         MDIO_PMA_DEVAD,
9448                         MDIO_PMA_REG_8481_LINK_SIGNAL, &val);
9449         val &= 0xFE00;
9450         val |= 0x0092;
9451
9452         bnx2x_cl45_write(bp, phy,
9453                          MDIO_PMA_DEVAD,
9454                          MDIO_PMA_REG_8481_LINK_SIGNAL, val);
9455
9456         bnx2x_cl45_write(bp, phy,
9457                          MDIO_PMA_DEVAD,
9458                          MDIO_PMA_REG_8481_LED1_MASK,
9459                          0x80);
9460
9461         bnx2x_cl45_write(bp, phy,
9462                          MDIO_PMA_DEVAD,
9463                          MDIO_PMA_REG_8481_LED2_MASK,
9464                          0x18);
9465
9466         /* Select activity source by Tx and Rx, as suggested by PHY AE */
9467         bnx2x_cl45_write(bp, phy,
9468                          MDIO_PMA_DEVAD,
9469                          MDIO_PMA_REG_8481_LED3_MASK,
9470                          0x0006);
9471
9472         /* Select the closest activity blink rate to that in 10/100/1000 */
9473         bnx2x_cl45_write(bp, phy,
9474                         MDIO_PMA_DEVAD,
9475                         MDIO_PMA_REG_8481_LED3_BLINK,
9476                         0);
9477
9478         /* Configure the blink rate to ~15.9 Hz */
9479         bnx2x_cl45_write(bp, phy,
9480                         MDIO_PMA_DEVAD,
9481                         MDIO_PMA_REG_84823_CTL_SLOW_CLK_CNT_HIGH,
9482                         MDIO_PMA_REG_84823_BLINK_RATE_VAL_15P9HZ);
9483
9484         if (phy->type == PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM84833)
9485                 offset = MDIO_PMA_REG_84833_CTL_LED_CTL_1;
9486         else
9487                 offset = MDIO_PMA_REG_84823_CTL_LED_CTL_1;
9488
9489         bnx2x_cl45_read(bp, phy,
9490                         MDIO_PMA_DEVAD, offset, &val);
9491         val |= MDIO_PMA_REG_84823_LED3_STRETCH_EN; /* stretch_en for LED3*/
9492         bnx2x_cl45_write(bp, phy,
9493                          MDIO_PMA_DEVAD, offset, val);
9494
9495         /* 'Interrupt Mask' */
9496         bnx2x_cl45_write(bp, phy,
9497                          MDIO_AN_DEVAD,
9498                          0xFFFB, 0xFFFD);
9499 }
9500
9501 static int bnx2x_848xx_cmn_config_init(struct bnx2x_phy *phy,
9502                                        struct link_params *params,
9503                                        struct link_vars *vars)
9504 {
9505         struct bnx2x *bp = params->bp;
9506         u16 autoneg_val, an_1000_val, an_10_100_val, an_10g_val;
9507
9508         if (phy->type != PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM84833) {
9509                 /* Save spirom version */
9510                 bnx2x_save_848xx_spirom_version(phy, bp, params->port);
9511         }
9512         /*
9513          * This phy uses the NIG latch mechanism since link indication
9514          * arrives through its LED4 and not via its LASI signal, so we
9515          * get steady signal instead of clear on read
9516          */
9517         bnx2x_bits_en(bp, NIG_REG_LATCH_BC_0 + params->port*4,
9518                       1 << NIG_LATCH_BC_ENABLE_MI_INT);
9519
9520         bnx2x_cl45_write(bp, phy,
9521                          MDIO_PMA_DEVAD, MDIO_PMA_REG_CTRL, 0x0000);
9522
9523         bnx2x_848xx_set_led(bp, phy);
9524
9525         /* set 1000 speed advertisement */
9526         bnx2x_cl45_read(bp, phy,
9527                         MDIO_AN_DEVAD, MDIO_AN_REG_8481_1000T_CTRL,
9528                         &an_1000_val);
9529
9530         bnx2x_ext_phy_set_pause(params, phy, vars);
9531         bnx2x_cl45_read(bp, phy,
9532                         MDIO_AN_DEVAD,
9533                         MDIO_AN_REG_8481_LEGACY_AN_ADV,
9534                         &an_10_100_val);
9535         bnx2x_cl45_read(bp, phy,
9536                         MDIO_AN_DEVAD, MDIO_AN_REG_8481_LEGACY_MII_CTRL,
9537                         &autoneg_val);
9538         /* Disable forced speed */
9539         autoneg_val &= ~((1<<6) | (1<<8) | (1<<9) | (1<<12) | (1<<13));
9540         an_10_100_val &= ~((1<<5) | (1<<6) | (1<<7) | (1<<8));
9541
9542         if (((phy->req_line_speed == SPEED_AUTO_NEG) &&
9543              (phy->speed_cap_mask &
9544              PORT_HW_CFG_SPEED_CAPABILITY_D0_1G)) ||
9545             (phy->req_line_speed == SPEED_1000)) {
9546                 an_1000_val |= (1<<8);
9547                 autoneg_val |= (1<<9 | 1<<12);
9548                 if (phy->req_duplex == DUPLEX_FULL)
9549                         an_1000_val |= (1<<9);
9550                 DP(NETIF_MSG_LINK, "Advertising 1G\n");
9551         } else
9552                 an_1000_val &= ~((1<<8) | (1<<9));
9553
9554         bnx2x_cl45_write(bp, phy,
9555                          MDIO_AN_DEVAD, MDIO_AN_REG_8481_1000T_CTRL,
9556                          an_1000_val);
9557
9558         /* set 100 speed advertisement */
9559         if ((phy->req_line_speed == SPEED_AUTO_NEG) &&
9560              (phy->speed_cap_mask &
9561               (PORT_HW_CFG_SPEED_CAPABILITY_D0_100M_FULL |
9562                PORT_HW_CFG_SPEED_CAPABILITY_D0_100M_HALF))) {
9563                 an_10_100_val |= (1<<7);
9564                 /* Enable autoneg and restart autoneg for legacy speeds */
9565                 autoneg_val |= (1<<9 | 1<<12);
9566
9567                 if (phy->req_duplex == DUPLEX_FULL)
9568                         an_10_100_val |= (1<<8);
9569                 DP(NETIF_MSG_LINK, "Advertising 100M\n");
9570         }
9571         /* set 10 speed advertisement */
9572         if (((phy->req_line_speed == SPEED_AUTO_NEG) &&
9573              (phy->speed_cap_mask &
9574               (PORT_HW_CFG_SPEED_CAPABILITY_D0_10M_FULL |
9575                PORT_HW_CFG_SPEED_CAPABILITY_D0_10M_HALF)) &&
9576              (phy->supported &
9577               (SUPPORTED_10baseT_Half |
9578                SUPPORTED_10baseT_Full)))) {
9579                 an_10_100_val |= (1<<5);
9580                 autoneg_val |= (1<<9 | 1<<12);
9581                 if (phy->req_duplex == DUPLEX_FULL)
9582                         an_10_100_val |= (1<<6);
9583                 DP(NETIF_MSG_LINK, "Advertising 10M\n");
9584         }
9585
9586         /* Only 10/100 are allowed to work in FORCE mode */
9587         if ((phy->req_line_speed == SPEED_100) &&
9588             (phy->supported &
9589              (SUPPORTED_100baseT_Half |
9590               SUPPORTED_100baseT_Full))) {
9591                 autoneg_val |= (1<<13);
9592                 /* Enabled AUTO-MDIX when autoneg is disabled */
9593                 bnx2x_cl45_write(bp, phy,
9594                                  MDIO_AN_DEVAD, MDIO_AN_REG_8481_AUX_CTRL,
9595                                  (1<<15 | 1<<9 | 7<<0));
9596                 /* The PHY needs this set even for forced link. */
9597                 an_10_100_val |= (1<<8) | (1<<7);
9598                 DP(NETIF_MSG_LINK, "Setting 100M force\n");
9599         }
9600         if ((phy->req_line_speed == SPEED_10) &&
9601             (phy->supported &
9602              (SUPPORTED_10baseT_Half |
9603               SUPPORTED_10baseT_Full))) {
9604                 /* Enabled AUTO-MDIX when autoneg is disabled */
9605                 bnx2x_cl45_write(bp, phy,
9606                                  MDIO_AN_DEVAD, MDIO_AN_REG_8481_AUX_CTRL,
9607                                  (1<<15 | 1<<9 | 7<<0));
9608                 DP(NETIF_MSG_LINK, "Setting 10M force\n");
9609         }
9610
9611         bnx2x_cl45_write(bp, phy,
9612                          MDIO_AN_DEVAD, MDIO_AN_REG_8481_LEGACY_AN_ADV,
9613                          an_10_100_val);
9614
9615         if (phy->req_duplex == DUPLEX_FULL)
9616                 autoneg_val |= (1<<8);
9617
9618         /*
9619          * Always write this if this is not 84833.
9620          * For 84833, write it only when it's a forced speed.
9621          */
9622         if ((phy->type != PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM84833) ||
9623                 ((autoneg_val & (1<<12)) == 0))
9624                 bnx2x_cl45_write(bp, phy,
9625                          MDIO_AN_DEVAD,
9626                          MDIO_AN_REG_8481_LEGACY_MII_CTRL, autoneg_val);
9627
9628         if (((phy->req_line_speed == SPEED_AUTO_NEG) &&
9629             (phy->speed_cap_mask &
9630              PORT_HW_CFG_SPEED_CAPABILITY_D0_10G)) ||
9631                 (phy->req_line_speed == SPEED_10000)) {
9632                         DP(NETIF_MSG_LINK, "Advertising 10G\n");
9633                         /* Restart autoneg for 10G*/
9634
9635                         bnx2x_cl45_read(bp, phy,
9636                                         MDIO_AN_DEVAD,
9637                                         MDIO_AN_REG_8481_10GBASE_T_AN_CTRL,
9638                                         &an_10g_val);
9639                         bnx2x_cl45_write(bp, phy,
9640                                          MDIO_AN_DEVAD,
9641                                          MDIO_AN_REG_8481_10GBASE_T_AN_CTRL,
9642                                          an_10g_val | 0x1000);
9643                         bnx2x_cl45_write(bp, phy,
9644                                          MDIO_AN_DEVAD, MDIO_AN_REG_CTRL,
9645                                          0x3200);
9646         } else
9647                 bnx2x_cl45_write(bp, phy,
9648                                  MDIO_AN_DEVAD,
9649                                  MDIO_AN_REG_8481_10GBASE_T_AN_CTRL,
9650                                  1);
9651
9652         return 0;
9653 }
9654
9655 static int bnx2x_8481_config_init(struct bnx2x_phy *phy,
9656                                   struct link_params *params,
9657                                   struct link_vars *vars)
9658 {
9659         struct bnx2x *bp = params->bp;
9660         /* Restore normal power mode*/
9661         bnx2x_set_gpio(bp, MISC_REGISTERS_GPIO_2,
9662                        MISC_REGISTERS_GPIO_OUTPUT_HIGH, params->port);
9663
9664         /* HW reset */
9665         bnx2x_ext_phy_hw_reset(bp, params->port);
9666         bnx2x_wait_reset_complete(bp, phy, params);
9667
9668         bnx2x_cl45_write(bp, phy, MDIO_PMA_DEVAD, MDIO_PMA_REG_CTRL, 1<<15);
9669         return bnx2x_848xx_cmn_config_init(phy, params, vars);
9670 }
9671
9672 #define PHY84833_CMDHDLR_WAIT 300
9673 #define PHY84833_CMDHDLR_MAX_ARGS 5
9674 static int bnx2x_84833_cmd_hdlr(struct bnx2x_phy *phy,
9675                                    struct link_params *params,
9676                    u16 fw_cmd,
9677                    u16 cmd_args[])
9678 {
9679         u32 idx;
9680         u16 val;
9681         struct bnx2x *bp = params->bp;
9682         /* Write CMD_OPEN_OVERRIDE to STATUS reg */
9683         bnx2x_cl45_write(bp, phy, MDIO_CTL_DEVAD,
9684                         MDIO_84833_CMD_HDLR_STATUS,
9685                         PHY84833_STATUS_CMD_OPEN_OVERRIDE);
9686         for (idx = 0; idx < PHY84833_CMDHDLR_WAIT; idx++) {
9687                 bnx2x_cl45_read(bp, phy, MDIO_CTL_DEVAD,
9688                                 MDIO_84833_CMD_HDLR_STATUS, &val);
9689                 if (val == PHY84833_STATUS_CMD_OPEN_FOR_CMDS)
9690                         break;
9691                 msleep(1);
9692         }
9693         if (idx >= PHY84833_CMDHDLR_WAIT) {
9694                 DP(NETIF_MSG_LINK, "FW cmd: FW not ready.\n");
9695                 return -EINVAL;
9696         }
9697
9698         /* Prepare argument(s) and issue command */
9699         for (idx = 0; idx < PHY84833_CMDHDLR_MAX_ARGS; idx++) {
9700                 bnx2x_cl45_write(bp, phy, MDIO_CTL_DEVAD,
9701                                 MDIO_84833_CMD_HDLR_DATA1 + idx,
9702                                 cmd_args[idx]);
9703         }
9704         bnx2x_cl45_write(bp, phy, MDIO_CTL_DEVAD,
9705                         MDIO_84833_CMD_HDLR_COMMAND, fw_cmd);
9706         for (idx = 0; idx < PHY84833_CMDHDLR_WAIT; idx++) {
9707                 bnx2x_cl45_read(bp, phy, MDIO_CTL_DEVAD,
9708                                 MDIO_84833_CMD_HDLR_STATUS, &val);
9709                 if ((val == PHY84833_STATUS_CMD_COMPLETE_PASS) ||
9710                         (val == PHY84833_STATUS_CMD_COMPLETE_ERROR))
9711                         break;
9712                 msleep(1);
9713         }
9714         if ((idx >= PHY84833_CMDHDLR_WAIT) ||
9715                 (val == PHY84833_STATUS_CMD_COMPLETE_ERROR)) {
9716                 DP(NETIF_MSG_LINK, "FW cmd failed.\n");
9717                 return -EINVAL;
9718         }
9719         /* Gather returning data */
9720         for (idx = 0; idx < PHY84833_CMDHDLR_MAX_ARGS; idx++) {
9721                 bnx2x_cl45_read(bp, phy, MDIO_CTL_DEVAD,
9722                                 MDIO_84833_CMD_HDLR_DATA1 + idx,
9723                                 &cmd_args[idx]);
9724         }
9725         bnx2x_cl45_write(bp, phy, MDIO_CTL_DEVAD,
9726                         MDIO_84833_CMD_HDLR_STATUS,
9727                         PHY84833_STATUS_CMD_CLEAR_COMPLETE);
9728         return 0;
9729 }
9730
9731
9732 static int bnx2x_84833_pair_swap_cfg(struct bnx2x_phy *phy,
9733                                    struct link_params *params,
9734                                    struct link_vars *vars)
9735 {
9736         u32 pair_swap;
9737         u16 data[PHY84833_CMDHDLR_MAX_ARGS];
9738         int status;
9739         struct bnx2x *bp = params->bp;
9740
9741         /* Check for configuration. */
9742         pair_swap = REG_RD(bp, params->shmem_base +
9743                            offsetof(struct shmem_region,
9744                         dev_info.port_hw_config[params->port].xgbt_phy_cfg)) &
9745                 PORT_HW_CFG_RJ45_PAIR_SWAP_MASK;
9746
9747         if (pair_swap == 0)
9748                 return 0;
9749
9750         /* Only the second argument is used for this command */
9751         data[1] = (u16)pair_swap;
9752
9753         status = bnx2x_84833_cmd_hdlr(phy, params,
9754                 PHY84833_CMD_SET_PAIR_SWAP, data);
9755         if (status == 0)
9756                 DP(NETIF_MSG_LINK, "Pairswap OK, val=0x%x\n", data[1]);
9757
9758         return status;
9759 }
9760
9761 static u8 bnx2x_84833_get_reset_gpios(struct bnx2x *bp,
9762                                       u32 shmem_base_path[],
9763                                       u32 chip_id)
9764 {
9765         u32 reset_pin[2];
9766         u32 idx;
9767         u8 reset_gpios;
9768         if (CHIP_IS_E3(bp)) {
9769                 /* Assume that these will be GPIOs, not EPIOs. */
9770                 for (idx = 0; idx < 2; idx++) {
9771                         /* Map config param to register bit. */
9772                         reset_pin[idx] = REG_RD(bp, shmem_base_path[idx] +
9773                                 offsetof(struct shmem_region,
9774                                 dev_info.port_hw_config[0].e3_cmn_pin_cfg));
9775                         reset_pin[idx] = (reset_pin[idx] &
9776                                 PORT_HW_CFG_E3_PHY_RESET_MASK) >>
9777                                 PORT_HW_CFG_E3_PHY_RESET_SHIFT;
9778                         reset_pin[idx] -= PIN_CFG_GPIO0_P0;
9779                         reset_pin[idx] = (1 << reset_pin[idx]);
9780                 }
9781                 reset_gpios = (u8)(reset_pin[0] | reset_pin[1]);
9782         } else {
9783                 /* E2, look from diff place of shmem. */
9784                 for (idx = 0; idx < 2; idx++) {
9785                         reset_pin[idx] = REG_RD(bp, shmem_base_path[idx] +
9786                                 offsetof(struct shmem_region,
9787                                 dev_info.port_hw_config[0].default_cfg));
9788                         reset_pin[idx] &= PORT_HW_CFG_EXT_PHY_GPIO_RST_MASK;
9789                         reset_pin[idx] -= PORT_HW_CFG_EXT_PHY_GPIO_RST_GPIO0_P0;
9790                         reset_pin[idx] >>= PORT_HW_CFG_EXT_PHY_GPIO_RST_SHIFT;
9791                         reset_pin[idx] = (1 << reset_pin[idx]);
9792                 }
9793                 reset_gpios = (u8)(reset_pin[0] | reset_pin[1]);
9794         }
9795
9796         return reset_gpios;
9797 }
9798
9799 static int bnx2x_84833_hw_reset_phy(struct bnx2x_phy *phy,
9800                                 struct link_params *params)
9801 {
9802         struct bnx2x *bp = params->bp;
9803         u8 reset_gpios;
9804         u32 other_shmem_base_addr = REG_RD(bp, params->shmem2_base +
9805                                 offsetof(struct shmem2_region,
9806                                 other_shmem_base_addr));
9807
9808         u32 shmem_base_path[2];
9809         shmem_base_path[0] = params->shmem_base;
9810         shmem_base_path[1] = other_shmem_base_addr;
9811
9812         reset_gpios = bnx2x_84833_get_reset_gpios(bp, shmem_base_path,
9813                                                   params->chip_id);
9814
9815         bnx2x_set_mult_gpio(bp, reset_gpios, MISC_REGISTERS_GPIO_OUTPUT_LOW);
9816         udelay(10);
9817         DP(NETIF_MSG_LINK, "84833 hw reset on pin values 0x%x\n",
9818                 reset_gpios);
9819
9820         return 0;
9821 }
9822
9823 #define PHY84833_CONSTANT_LATENCY 1193
9824 static int bnx2x_848x3_config_init(struct bnx2x_phy *phy,
9825                                    struct link_params *params,
9826                                    struct link_vars *vars)
9827 {
9828         struct bnx2x *bp = params->bp;
9829         u8 port, initialize = 1;
9830         u16 val;
9831         u32 actual_phy_selection, cms_enable;
9832         u16 cmd_args[PHY84833_CMDHDLR_MAX_ARGS];
9833         int rc = 0;
9834
9835         msleep(1);
9836
9837         if (!(CHIP_IS_E1(bp)))
9838                 port = BP_PATH(bp);
9839         else
9840                 port = params->port;
9841
9842         if (phy->type == PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM84823) {
9843                 bnx2x_set_gpio(bp, MISC_REGISTERS_GPIO_3,
9844                                MISC_REGISTERS_GPIO_OUTPUT_HIGH,
9845                                port);
9846         } else {
9847                 /* MDIO reset */
9848                 bnx2x_cl45_write(bp, phy,
9849                                 MDIO_PMA_DEVAD,
9850                                 MDIO_PMA_REG_CTRL, 0x8000);
9851         }
9852
9853         bnx2x_wait_reset_complete(bp, phy, params);
9854
9855         /* Wait for GPHY to come out of reset */
9856         msleep(50);
9857         if (phy->type != PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM84833) {
9858                 /*
9859                  * BCM84823 requires that XGXS links up first @ 10G for normal
9860                  * behavior.
9861                  */
9862                 u16 temp;
9863                 temp = vars->line_speed;
9864                 vars->line_speed = SPEED_10000;
9865                 bnx2x_set_autoneg(&params->phy[INT_PHY], params, vars, 0);
9866                 bnx2x_program_serdes(&params->phy[INT_PHY], params, vars);
9867                 vars->line_speed = temp;
9868         }
9869
9870         bnx2x_cl45_read(bp, phy, MDIO_CTL_DEVAD,
9871                         MDIO_CTL_REG_84823_MEDIA, &val);
9872         val &= ~(MDIO_CTL_REG_84823_MEDIA_MAC_MASK |
9873                  MDIO_CTL_REG_84823_MEDIA_LINE_MASK |
9874                  MDIO_CTL_REG_84823_MEDIA_COPPER_CORE_DOWN |
9875                  MDIO_CTL_REG_84823_MEDIA_PRIORITY_MASK |
9876                  MDIO_CTL_REG_84823_MEDIA_FIBER_1G);
9877
9878         if (CHIP_IS_E3(bp)) {
9879                 val &= ~(MDIO_CTL_REG_84823_MEDIA_MAC_MASK |
9880                          MDIO_CTL_REG_84823_MEDIA_LINE_MASK);
9881         } else {
9882                 val |= (MDIO_CTL_REG_84823_CTRL_MAC_XFI |
9883                         MDIO_CTL_REG_84823_MEDIA_LINE_XAUI_L);
9884         }
9885
9886         actual_phy_selection = bnx2x_phy_selection(params);
9887
9888         switch (actual_phy_selection) {
9889         case PORT_HW_CFG_PHY_SELECTION_HARDWARE_DEFAULT:
9890                 /* Do nothing. Essentially this is like the priority copper */
9891                 break;
9892         case PORT_HW_CFG_PHY_SELECTION_FIRST_PHY_PRIORITY:
9893                 val |= MDIO_CTL_REG_84823_MEDIA_PRIORITY_COPPER;
9894                 break;
9895         case PORT_HW_CFG_PHY_SELECTION_SECOND_PHY_PRIORITY:
9896                 val |= MDIO_CTL_REG_84823_MEDIA_PRIORITY_FIBER;
9897                 break;
9898         case PORT_HW_CFG_PHY_SELECTION_FIRST_PHY:
9899                 /* Do nothing here. The first PHY won't be initialized at all */
9900                 break;
9901         case PORT_HW_CFG_PHY_SELECTION_SECOND_PHY:
9902                 val |= MDIO_CTL_REG_84823_MEDIA_COPPER_CORE_DOWN;
9903                 initialize = 0;
9904                 break;
9905         }
9906         if (params->phy[EXT_PHY2].req_line_speed == SPEED_1000)
9907                 val |= MDIO_CTL_REG_84823_MEDIA_FIBER_1G;
9908
9909         bnx2x_cl45_write(bp, phy, MDIO_CTL_DEVAD,
9910                          MDIO_CTL_REG_84823_MEDIA, val);
9911         DP(NETIF_MSG_LINK, "Multi_phy config = 0x%x, Media control = 0x%x\n",
9912                    params->multi_phy_config, val);
9913
9914         if (phy->type == PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM84833) {
9915                 bnx2x_84833_pair_swap_cfg(phy, params, vars);
9916
9917                 /* Keep AutogrEEEn disabled. */
9918                 cmd_args[0] = 0x0;
9919                 cmd_args[1] = 0x0;
9920                 cmd_args[2] = PHY84833_CONSTANT_LATENCY + 1;
9921                 cmd_args[3] = PHY84833_CONSTANT_LATENCY;
9922                 rc = bnx2x_84833_cmd_hdlr(phy, params,
9923                         PHY84833_CMD_SET_EEE_MODE, cmd_args);
9924                 if (rc != 0)
9925                         DP(NETIF_MSG_LINK, "Cfg AutogrEEEn failed.\n");
9926         }
9927         if (initialize)
9928                 rc = bnx2x_848xx_cmn_config_init(phy, params, vars);
9929         else
9930                 bnx2x_save_848xx_spirom_version(phy, bp, params->port);
9931         /* 84833 PHY has a better feature and doesn't need to support this. */
9932         if (phy->type == PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM84823) {
9933                 cms_enable = REG_RD(bp, params->shmem_base +
9934                         offsetof(struct shmem_region,
9935                         dev_info.port_hw_config[params->port].default_cfg)) &
9936                         PORT_HW_CFG_ENABLE_CMS_MASK;
9937
9938                 bnx2x_cl45_read(bp, phy, MDIO_CTL_DEVAD,
9939                                 MDIO_CTL_REG_84823_USER_CTRL_REG, &val);
9940                 if (cms_enable)
9941                         val |= MDIO_CTL_REG_84823_USER_CTRL_CMS;
9942                 else
9943                         val &= ~MDIO_CTL_REG_84823_USER_CTRL_CMS;
9944                 bnx2x_cl45_write(bp, phy, MDIO_CTL_DEVAD,
9945                                  MDIO_CTL_REG_84823_USER_CTRL_REG, val);
9946         }
9947
9948         if (phy->type == PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM84833) {
9949                 /* Bring PHY out of super isolate mode as the final step. */
9950                 bnx2x_cl45_read(bp, phy,
9951                                 MDIO_CTL_DEVAD,
9952                                 MDIO_84833_TOP_CFG_XGPHY_STRAP1, &val);
9953                 val &= ~MDIO_84833_SUPER_ISOLATE;
9954                 bnx2x_cl45_write(bp, phy,
9955                                 MDIO_CTL_DEVAD,
9956                                 MDIO_84833_TOP_CFG_XGPHY_STRAP1, val);
9957         }
9958         return rc;
9959 }
9960
9961 static u8 bnx2x_848xx_read_status(struct bnx2x_phy *phy,
9962                                   struct link_params *params,
9963                                   struct link_vars *vars)
9964 {
9965         struct bnx2x *bp = params->bp;
9966         u16 val, val1, val2;
9967         u8 link_up = 0;
9968
9969
9970         /* Check 10G-BaseT link status */
9971         /* Check PMD signal ok */
9972         bnx2x_cl45_read(bp, phy,
9973                         MDIO_AN_DEVAD, 0xFFFA, &val1);
9974         bnx2x_cl45_read(bp, phy,
9975                         MDIO_PMA_DEVAD, MDIO_PMA_REG_8481_PMD_SIGNAL,
9976                         &val2);
9977         DP(NETIF_MSG_LINK, "BCM848xx: PMD_SIGNAL 1.a811 = 0x%x\n", val2);
9978
9979         /* Check link 10G */
9980         if (val2 & (1<<11)) {
9981                 vars->line_speed = SPEED_10000;
9982                 vars->duplex = DUPLEX_FULL;
9983                 link_up = 1;
9984                 bnx2x_ext_phy_10G_an_resolve(bp, phy, vars);
9985         } else { /* Check Legacy speed link */
9986                 u16 legacy_status, legacy_speed;
9987
9988                 /* Enable expansion register 0x42 (Operation mode status) */
9989                 bnx2x_cl45_write(bp, phy,
9990                                  MDIO_AN_DEVAD,
9991                                  MDIO_AN_REG_8481_EXPANSION_REG_ACCESS, 0xf42);
9992
9993                 /* Get legacy speed operation status */
9994                 bnx2x_cl45_read(bp, phy,
9995                                 MDIO_AN_DEVAD,
9996                                 MDIO_AN_REG_8481_EXPANSION_REG_RD_RW,
9997                                 &legacy_status);
9998
9999                 DP(NETIF_MSG_LINK, "Legacy speed status = 0x%x\n",
10000                    legacy_status);
10001                 link_up = ((legacy_status & (1<<11)) == (1<<11));
10002                 if (link_up) {
10003                         legacy_speed = (legacy_status & (3<<9));
10004                         if (legacy_speed == (0<<9))
10005                                 vars->line_speed = SPEED_10;
10006                         else if (legacy_speed == (1<<9))
10007                                 vars->line_speed = SPEED_100;
10008                         else if (legacy_speed == (2<<9))
10009                                 vars->line_speed = SPEED_1000;
10010                         else /* Should not happen */
10011                                 vars->line_speed = 0;
10012
10013                         if (legacy_status & (1<<8))
10014                                 vars->duplex = DUPLEX_FULL;
10015                         else
10016                                 vars->duplex = DUPLEX_HALF;
10017
10018                         DP(NETIF_MSG_LINK,
10019                            "Link is up in %dMbps, is_duplex_full= %d\n",
10020                            vars->line_speed,
10021                            (vars->duplex == DUPLEX_FULL));
10022                         /* Check legacy speed AN resolution */
10023                         bnx2x_cl45_read(bp, phy,
10024                                         MDIO_AN_DEVAD,
10025                                         MDIO_AN_REG_8481_LEGACY_MII_STATUS,
10026                                         &val);
10027                         if (val & (1<<5))
10028                                 vars->link_status |=
10029                                         LINK_STATUS_AUTO_NEGOTIATE_COMPLETE;
10030                         bnx2x_cl45_read(bp, phy,
10031                                         MDIO_AN_DEVAD,
10032                                         MDIO_AN_REG_8481_LEGACY_AN_EXPANSION,
10033                                         &val);
10034                         if ((val & (1<<0)) == 0)
10035                                 vars->link_status |=
10036                                         LINK_STATUS_PARALLEL_DETECTION_USED;
10037                 }
10038         }
10039         if (link_up) {
10040                 DP(NETIF_MSG_LINK, "BCM84823: link speed is %d\n",
10041                            vars->line_speed);
10042                 bnx2x_ext_phy_resolve_fc(phy, params, vars);
10043
10044                 /* Read LP advertised speeds */
10045                 bnx2x_cl45_read(bp, phy, MDIO_AN_DEVAD,
10046                                 MDIO_AN_REG_CL37_FC_LP, &val);
10047                 if (val & (1<<5))
10048                         vars->link_status |=
10049                                 LINK_STATUS_LINK_PARTNER_10THD_CAPABLE;
10050                 if (val & (1<<6))
10051                         vars->link_status |=
10052                                 LINK_STATUS_LINK_PARTNER_10TFD_CAPABLE;
10053                 if (val & (1<<7))
10054                         vars->link_status |=
10055                                 LINK_STATUS_LINK_PARTNER_100TXHD_CAPABLE;
10056                 if (val & (1<<8))
10057                         vars->link_status |=
10058                                 LINK_STATUS_LINK_PARTNER_100TXFD_CAPABLE;
10059                 if (val & (1<<9))
10060                         vars->link_status |=
10061                                 LINK_STATUS_LINK_PARTNER_100T4_CAPABLE;
10062
10063                 bnx2x_cl45_read(bp, phy, MDIO_AN_DEVAD,
10064                                 MDIO_AN_REG_1000T_STATUS, &val);
10065
10066                 if (val & (1<<10))
10067                         vars->link_status |=
10068                                 LINK_STATUS_LINK_PARTNER_1000THD_CAPABLE;
10069                 if (val & (1<<11))
10070                         vars->link_status |=
10071                                 LINK_STATUS_LINK_PARTNER_1000TFD_CAPABLE;
10072
10073                 bnx2x_cl45_read(bp, phy, MDIO_AN_DEVAD,
10074                                 MDIO_AN_REG_MASTER_STATUS, &val);
10075
10076                 if (val & (1<<11))
10077                         vars->link_status |=
10078                                 LINK_STATUS_LINK_PARTNER_10GXFD_CAPABLE;
10079         }
10080
10081         return link_up;
10082 }
10083
10084
10085 static int bnx2x_848xx_format_ver(u32 raw_ver, u8 *str, u16 *len)
10086 {
10087         int status = 0;
10088         u32 spirom_ver;
10089         spirom_ver = ((raw_ver & 0xF80) >> 7) << 16 | (raw_ver & 0x7F);
10090         status = bnx2x_format_ver(spirom_ver, str, len);
10091         return status;
10092 }
10093
10094 static void bnx2x_8481_hw_reset(struct bnx2x_phy *phy,
10095                                 struct link_params *params)
10096 {
10097         bnx2x_set_gpio(params->bp, MISC_REGISTERS_GPIO_1,
10098                        MISC_REGISTERS_GPIO_OUTPUT_LOW, 0);
10099         bnx2x_set_gpio(params->bp, MISC_REGISTERS_GPIO_1,
10100                        MISC_REGISTERS_GPIO_OUTPUT_LOW, 1);
10101 }
10102
10103 static void bnx2x_8481_link_reset(struct bnx2x_phy *phy,
10104                                         struct link_params *params)
10105 {
10106         bnx2x_cl45_write(params->bp, phy,
10107                          MDIO_AN_DEVAD, MDIO_AN_REG_CTRL, 0x0000);
10108         bnx2x_cl45_write(params->bp, phy,
10109                          MDIO_PMA_DEVAD, MDIO_PMA_REG_CTRL, 1);
10110 }
10111
10112 static void bnx2x_848x3_link_reset(struct bnx2x_phy *phy,
10113                                    struct link_params *params)
10114 {
10115         struct bnx2x *bp = params->bp;
10116         u8 port;
10117         u16 val16;
10118
10119         if (!(CHIP_IS_E1(bp)))
10120                 port = BP_PATH(bp);
10121         else
10122                 port = params->port;
10123
10124         if (phy->type == PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM84823) {
10125                 bnx2x_set_gpio(bp, MISC_REGISTERS_GPIO_3,
10126                                MISC_REGISTERS_GPIO_OUTPUT_LOW,
10127                                port);
10128         } else {
10129                 bnx2x_cl45_read(bp, phy,
10130                                 MDIO_CTL_DEVAD,
10131                                 MDIO_84833_TOP_CFG_XGPHY_STRAP1, &val16);
10132                 val16 |= MDIO_84833_SUPER_ISOLATE;
10133                 bnx2x_cl45_write(bp, phy,
10134                                  MDIO_CTL_DEVAD,
10135                                  MDIO_84833_TOP_CFG_XGPHY_STRAP1, val16);
10136         }
10137 }
10138
10139 static void bnx2x_848xx_set_link_led(struct bnx2x_phy *phy,
10140                                      struct link_params *params, u8 mode)
10141 {
10142         struct bnx2x *bp = params->bp;
10143         u16 val;
10144         u8 port;
10145
10146         if (!(CHIP_IS_E1(bp)))
10147                 port = BP_PATH(bp);
10148         else
10149                 port = params->port;
10150
10151         switch (mode) {
10152         case LED_MODE_OFF:
10153
10154                 DP(NETIF_MSG_LINK, "Port 0x%x: LED MODE OFF\n", port);
10155
10156                 if ((params->hw_led_mode << SHARED_HW_CFG_LED_MODE_SHIFT) ==
10157                     SHARED_HW_CFG_LED_EXTPHY1) {
10158
10159                         /* Set LED masks */
10160                         bnx2x_cl45_write(bp, phy,
10161                                         MDIO_PMA_DEVAD,
10162                                         MDIO_PMA_REG_8481_LED1_MASK,
10163                                         0x0);
10164
10165                         bnx2x_cl45_write(bp, phy,
10166                                         MDIO_PMA_DEVAD,
10167                                         MDIO_PMA_REG_8481_LED2_MASK,
10168                                         0x0);
10169
10170                         bnx2x_cl45_write(bp, phy,
10171                                         MDIO_PMA_DEVAD,
10172                                         MDIO_PMA_REG_8481_LED3_MASK,
10173                                         0x0);
10174
10175                         bnx2x_cl45_write(bp, phy,
10176                                         MDIO_PMA_DEVAD,
10177                                         MDIO_PMA_REG_8481_LED5_MASK,
10178                                         0x0);
10179
10180                 } else {
10181                         bnx2x_cl45_write(bp, phy,
10182                                          MDIO_PMA_DEVAD,
10183                                          MDIO_PMA_REG_8481_LED1_MASK,
10184                                          0x0);
10185                 }
10186                 break;
10187         case LED_MODE_FRONT_PANEL_OFF:
10188
10189                 DP(NETIF_MSG_LINK, "Port 0x%x: LED MODE FRONT PANEL OFF\n",
10190                    port);
10191
10192                 if ((params->hw_led_mode << SHARED_HW_CFG_LED_MODE_SHIFT) ==
10193                     SHARED_HW_CFG_LED_EXTPHY1) {
10194
10195                         /* Set LED masks */
10196                         bnx2x_cl45_write(bp, phy,
10197                                          MDIO_PMA_DEVAD,
10198                                          MDIO_PMA_REG_8481_LED1_MASK,
10199                                          0x0);
10200
10201                         bnx2x_cl45_write(bp, phy,
10202                                          MDIO_PMA_DEVAD,
10203                                          MDIO_PMA_REG_8481_LED2_MASK,
10204                                          0x0);
10205
10206                         bnx2x_cl45_write(bp, phy,
10207                                          MDIO_PMA_DEVAD,
10208                                          MDIO_PMA_REG_8481_LED3_MASK,
10209                                          0x0);
10210
10211                         bnx2x_cl45_write(bp, phy,
10212                                          MDIO_PMA_DEVAD,
10213                                          MDIO_PMA_REG_8481_LED5_MASK,
10214                                          0x20);
10215
10216                 } else {
10217                         bnx2x_cl45_write(bp, phy,
10218                                          MDIO_PMA_DEVAD,
10219                                          MDIO_PMA_REG_8481_LED1_MASK,
10220                                          0x0);
10221                 }
10222                 break;
10223         case LED_MODE_ON:
10224
10225                 DP(NETIF_MSG_LINK, "Port 0x%x: LED MODE ON\n", port);
10226
10227                 if ((params->hw_led_mode << SHARED_HW_CFG_LED_MODE_SHIFT) ==
10228                     SHARED_HW_CFG_LED_EXTPHY1) {
10229                         /* Set control reg */
10230                         bnx2x_cl45_read(bp, phy,
10231                                         MDIO_PMA_DEVAD,
10232                                         MDIO_PMA_REG_8481_LINK_SIGNAL,
10233                                         &val);
10234                         val &= 0x8000;
10235                         val |= 0x2492;
10236
10237                         bnx2x_cl45_write(bp, phy,
10238                                          MDIO_PMA_DEVAD,
10239                                          MDIO_PMA_REG_8481_LINK_SIGNAL,
10240                                          val);
10241
10242                         /* Set LED masks */
10243                         bnx2x_cl45_write(bp, phy,
10244                                          MDIO_PMA_DEVAD,
10245                                          MDIO_PMA_REG_8481_LED1_MASK,
10246                                          0x0);
10247
10248                         bnx2x_cl45_write(bp, phy,
10249                                          MDIO_PMA_DEVAD,
10250                                          MDIO_PMA_REG_8481_LED2_MASK,
10251                                          0x20);
10252
10253                         bnx2x_cl45_write(bp, phy,
10254                                          MDIO_PMA_DEVAD,
10255                                          MDIO_PMA_REG_8481_LED3_MASK,
10256                                          0x20);
10257
10258                         bnx2x_cl45_write(bp, phy,
10259                                          MDIO_PMA_DEVAD,
10260                                          MDIO_PMA_REG_8481_LED5_MASK,
10261                                          0x0);
10262                 } else {
10263                         bnx2x_cl45_write(bp, phy,
10264                                          MDIO_PMA_DEVAD,
10265                                          MDIO_PMA_REG_8481_LED1_MASK,
10266                                          0x20);
10267                 }
10268                 break;
10269
10270         case LED_MODE_OPER:
10271
10272                 DP(NETIF_MSG_LINK, "Port 0x%x: LED MODE OPER\n", port);
10273
10274                 if ((params->hw_led_mode << SHARED_HW_CFG_LED_MODE_SHIFT) ==
10275                     SHARED_HW_CFG_LED_EXTPHY1) {
10276
10277                         /* Set control reg */
10278                         bnx2x_cl45_read(bp, phy,
10279                                         MDIO_PMA_DEVAD,
10280                                         MDIO_PMA_REG_8481_LINK_SIGNAL,
10281                                         &val);
10282
10283                         if (!((val &
10284                                MDIO_PMA_REG_8481_LINK_SIGNAL_LED4_ENABLE_MASK)
10285                           >> MDIO_PMA_REG_8481_LINK_SIGNAL_LED4_ENABLE_SHIFT)) {
10286                                 DP(NETIF_MSG_LINK, "Setting LINK_SIGNAL\n");
10287                                 bnx2x_cl45_write(bp, phy,
10288                                                  MDIO_PMA_DEVAD,
10289                                                  MDIO_PMA_REG_8481_LINK_SIGNAL,
10290                                                  0xa492);
10291                         }
10292
10293                         /* Set LED masks */
10294                         bnx2x_cl45_write(bp, phy,
10295                                          MDIO_PMA_DEVAD,
10296                                          MDIO_PMA_REG_8481_LED1_MASK,
10297                                          0x10);
10298
10299                         bnx2x_cl45_write(bp, phy,
10300                                          MDIO_PMA_DEVAD,
10301                                          MDIO_PMA_REG_8481_LED2_MASK,
10302                                          0x80);
10303
10304                         bnx2x_cl45_write(bp, phy,
10305                                          MDIO_PMA_DEVAD,
10306                                          MDIO_PMA_REG_8481_LED3_MASK,
10307                                          0x98);
10308
10309                         bnx2x_cl45_write(bp, phy,
10310                                          MDIO_PMA_DEVAD,
10311                                          MDIO_PMA_REG_8481_LED5_MASK,
10312                                          0x40);
10313
10314                 } else {
10315                         bnx2x_cl45_write(bp, phy,
10316                                          MDIO_PMA_DEVAD,
10317                                          MDIO_PMA_REG_8481_LED1_MASK,
10318                                          0x80);
10319
10320                         /* Tell LED3 to blink on source */
10321                         bnx2x_cl45_read(bp, phy,
10322                                         MDIO_PMA_DEVAD,
10323                                         MDIO_PMA_REG_8481_LINK_SIGNAL,
10324                                         &val);
10325                         val &= ~(7<<6);
10326                         val |= (1<<6); /* A83B[8:6]= 1 */
10327                         bnx2x_cl45_write(bp, phy,
10328                                          MDIO_PMA_DEVAD,
10329                                          MDIO_PMA_REG_8481_LINK_SIGNAL,
10330                                          val);
10331                 }
10332                 break;
10333         }
10334
10335         /*
10336          * This is a workaround for E3+84833 until autoneg
10337          * restart is fixed in f/w
10338          */
10339         if (CHIP_IS_E3(bp)) {
10340                 bnx2x_cl45_read(bp, phy, MDIO_WC_DEVAD,
10341                                 MDIO_WC_REG_GP2_STATUS_GP_2_1, &val);
10342         }
10343 }
10344
10345 /******************************************************************/
10346 /*                      54618SE PHY SECTION                       */
10347 /******************************************************************/
10348 static int bnx2x_54618se_config_init(struct bnx2x_phy *phy,
10349                                                struct link_params *params,
10350                                                struct link_vars *vars)
10351 {
10352         struct bnx2x *bp = params->bp;
10353         u8 port;
10354         u16 autoneg_val, an_1000_val, an_10_100_val, fc_val, temp;
10355         u32 cfg_pin;
10356
10357         DP(NETIF_MSG_LINK, "54618SE cfg init\n");
10358         usleep_range(1000, 1000);
10359
10360         /*
10361          * This works with E3 only, no need to check the chip
10362          * before determining the port.
10363          */
10364         port = params->port;
10365
10366         cfg_pin = (REG_RD(bp, params->shmem_base +
10367                         offsetof(struct shmem_region,
10368                         dev_info.port_hw_config[port].e3_cmn_pin_cfg)) &
10369                         PORT_HW_CFG_E3_PHY_RESET_MASK) >>
10370                         PORT_HW_CFG_E3_PHY_RESET_SHIFT;
10371
10372         /* Drive pin high to bring the GPHY out of reset. */
10373         bnx2x_set_cfg_pin(bp, cfg_pin, 1);
10374
10375         /* wait for GPHY to reset */
10376         msleep(50);
10377
10378         /* reset phy */
10379         bnx2x_cl22_write(bp, phy,
10380                          MDIO_PMA_REG_CTRL, 0x8000);
10381         bnx2x_wait_reset_complete(bp, phy, params);
10382
10383         /*wait for GPHY to reset */
10384         msleep(50);
10385
10386         /* Configure LED4: set to INTR (0x6). */
10387         /* Accessing shadow register 0xe. */
10388         bnx2x_cl22_write(bp, phy,
10389                         MDIO_REG_GPHY_SHADOW,
10390                         MDIO_REG_GPHY_SHADOW_LED_SEL2);
10391         bnx2x_cl22_read(bp, phy,
10392                         MDIO_REG_GPHY_SHADOW,
10393                         &temp);
10394         temp &= ~(0xf << 4);
10395         temp |= (0x6 << 4);
10396         bnx2x_cl22_write(bp, phy,
10397                         MDIO_REG_GPHY_SHADOW,
10398                         MDIO_REG_GPHY_SHADOW_WR_ENA | temp);
10399         /* Configure INTR based on link status change. */
10400         bnx2x_cl22_write(bp, phy,
10401                         MDIO_REG_INTR_MASK,
10402                         ~MDIO_REG_INTR_MASK_LINK_STATUS);
10403
10404         /* Flip the signal detect polarity (set 0x1c.0x1e[8]). */
10405         bnx2x_cl22_write(bp, phy,
10406                         MDIO_REG_GPHY_SHADOW,
10407                         MDIO_REG_GPHY_SHADOW_AUTO_DET_MED);
10408         bnx2x_cl22_read(bp, phy,
10409                         MDIO_REG_GPHY_SHADOW,
10410                         &temp);
10411         temp |= MDIO_REG_GPHY_SHADOW_INVERT_FIB_SD;
10412         bnx2x_cl22_write(bp, phy,
10413                         MDIO_REG_GPHY_SHADOW,
10414                         MDIO_REG_GPHY_SHADOW_WR_ENA | temp);
10415
10416         /* Set up fc */
10417         /* Please refer to Table 28B-3 of 802.3ab-1999 spec. */
10418         bnx2x_calc_ieee_aneg_adv(phy, params, &vars->ieee_fc);
10419         fc_val = 0;
10420         if ((vars->ieee_fc & MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_ASYMMETRIC) ==
10421                         MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_ASYMMETRIC)
10422                 fc_val |= MDIO_AN_REG_ADV_PAUSE_ASYMMETRIC;
10423
10424         if ((vars->ieee_fc & MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_BOTH) ==
10425                         MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_BOTH)
10426                 fc_val |= MDIO_AN_REG_ADV_PAUSE_PAUSE;
10427
10428         /* read all advertisement */
10429         bnx2x_cl22_read(bp, phy,
10430                         0x09,
10431                         &an_1000_val);
10432
10433         bnx2x_cl22_read(bp, phy,
10434                         0x04,
10435                         &an_10_100_val);
10436
10437         bnx2x_cl22_read(bp, phy,
10438                         MDIO_PMA_REG_CTRL,
10439                         &autoneg_val);
10440
10441         /* Disable forced speed */
10442         autoneg_val &= ~((1<<6) | (1<<8) | (1<<9) | (1<<12) | (1<<13));
10443         an_10_100_val &= ~((1<<5) | (1<<6) | (1<<7) | (1<<8) | (1<<10) |
10444                            (1<<11));
10445
10446         if (((phy->req_line_speed == SPEED_AUTO_NEG) &&
10447                         (phy->speed_cap_mask &
10448                         PORT_HW_CFG_SPEED_CAPABILITY_D0_1G)) ||
10449                         (phy->req_line_speed == SPEED_1000)) {
10450                 an_1000_val |= (1<<8);
10451                 autoneg_val |= (1<<9 | 1<<12);
10452                 if (phy->req_duplex == DUPLEX_FULL)
10453                         an_1000_val |= (1<<9);
10454                 DP(NETIF_MSG_LINK, "Advertising 1G\n");
10455         } else
10456                 an_1000_val &= ~((1<<8) | (1<<9));
10457
10458         bnx2x_cl22_write(bp, phy,
10459                         0x09,
10460                         an_1000_val);
10461         bnx2x_cl22_read(bp, phy,
10462                         0x09,
10463                         &an_1000_val);
10464
10465         /* set 100 speed advertisement */
10466         if (((phy->req_line_speed == SPEED_AUTO_NEG) &&
10467                         (phy->speed_cap_mask &
10468                         (PORT_HW_CFG_SPEED_CAPABILITY_D0_100M_FULL |
10469                         PORT_HW_CFG_SPEED_CAPABILITY_D0_100M_HALF)))) {
10470                 an_10_100_val |= (1<<7);
10471                 /* Enable autoneg and restart autoneg for legacy speeds */
10472                 autoneg_val |= (1<<9 | 1<<12);
10473
10474                 if (phy->req_duplex == DUPLEX_FULL)
10475                         an_10_100_val |= (1<<8);
10476                 DP(NETIF_MSG_LINK, "Advertising 100M\n");
10477         }
10478
10479         /* set 10 speed advertisement */
10480         if (((phy->req_line_speed == SPEED_AUTO_NEG) &&
10481                         (phy->speed_cap_mask &
10482                         (PORT_HW_CFG_SPEED_CAPABILITY_D0_10M_FULL |
10483                         PORT_HW_CFG_SPEED_CAPABILITY_D0_10M_HALF)))) {
10484                 an_10_100_val |= (1<<5);
10485                 autoneg_val |= (1<<9 | 1<<12);
10486                 if (phy->req_duplex == DUPLEX_FULL)
10487                         an_10_100_val |= (1<<6);
10488                 DP(NETIF_MSG_LINK, "Advertising 10M\n");
10489         }
10490
10491         /* Only 10/100 are allowed to work in FORCE mode */
10492         if (phy->req_line_speed == SPEED_100) {
10493                 autoneg_val |= (1<<13);
10494                 /* Enabled AUTO-MDIX when autoneg is disabled */
10495                 bnx2x_cl22_write(bp, phy,
10496                                 0x18,
10497                                 (1<<15 | 1<<9 | 7<<0));
10498                 DP(NETIF_MSG_LINK, "Setting 100M force\n");
10499         }
10500         if (phy->req_line_speed == SPEED_10) {
10501                 /* Enabled AUTO-MDIX when autoneg is disabled */
10502                 bnx2x_cl22_write(bp, phy,
10503                                 0x18,
10504                                 (1<<15 | 1<<9 | 7<<0));
10505                 DP(NETIF_MSG_LINK, "Setting 10M force\n");
10506         }
10507
10508         /* Check if we should turn on Auto-GrEEEn */
10509         bnx2x_cl22_read(bp, phy, MDIO_REG_GPHY_PHYID_LSB, &temp);
10510         if (temp == MDIO_REG_GPHY_ID_54618SE) {
10511                 if (params->feature_config_flags &
10512                     FEATURE_CONFIG_AUTOGREEEN_ENABLED) {
10513                         temp = 6;
10514                         DP(NETIF_MSG_LINK, "Enabling Auto-GrEEEn\n");
10515                 } else {
10516                         temp = 0;
10517                         DP(NETIF_MSG_LINK, "Disabling Auto-GrEEEn\n");
10518                 }
10519                 bnx2x_cl22_write(bp, phy,
10520                                  MDIO_REG_GPHY_CL45_ADDR_REG, MDIO_AN_DEVAD);
10521                 bnx2x_cl22_write(bp, phy,
10522                                  MDIO_REG_GPHY_CL45_DATA_REG,
10523                                  MDIO_REG_GPHY_EEE_ADV);
10524                 bnx2x_cl22_write(bp, phy,
10525                                  MDIO_REG_GPHY_CL45_ADDR_REG,
10526                                  (0x1 << 14) | MDIO_AN_DEVAD);
10527                 bnx2x_cl22_write(bp, phy,
10528                                  MDIO_REG_GPHY_CL45_DATA_REG,
10529                                  temp);
10530         }
10531
10532         bnx2x_cl22_write(bp, phy,
10533                         0x04,
10534                         an_10_100_val | fc_val);
10535
10536         if (phy->req_duplex == DUPLEX_FULL)
10537                 autoneg_val |= (1<<8);
10538
10539         bnx2x_cl22_write(bp, phy,
10540                         MDIO_PMA_REG_CTRL, autoneg_val);
10541
10542         return 0;
10543 }
10544
10545
10546 static void bnx2x_5461x_set_link_led(struct bnx2x_phy *phy,
10547                                        struct link_params *params, u8 mode)
10548 {
10549         struct bnx2x *bp = params->bp;
10550         u16 temp;
10551
10552         bnx2x_cl22_write(bp, phy,
10553                 MDIO_REG_GPHY_SHADOW,
10554                 MDIO_REG_GPHY_SHADOW_LED_SEL1);
10555         bnx2x_cl22_read(bp, phy,
10556                 MDIO_REG_GPHY_SHADOW,
10557                 &temp);
10558         temp &= 0xff00;
10559
10560         DP(NETIF_MSG_LINK, "54618x set link led (mode=%x)\n", mode);
10561         switch (mode) {
10562         case LED_MODE_FRONT_PANEL_OFF:
10563         case LED_MODE_OFF:
10564                 temp |= 0x00ee;
10565                 break;
10566         case LED_MODE_OPER:
10567                 temp |= 0x0001;
10568                 break;
10569         case LED_MODE_ON:
10570                 temp |= 0x00ff;
10571                 break;
10572         default:
10573                 break;
10574         }
10575         bnx2x_cl22_write(bp, phy,
10576                 MDIO_REG_GPHY_SHADOW,
10577                 MDIO_REG_GPHY_SHADOW_WR_ENA | temp);
10578         return;
10579 }
10580
10581
10582 static void bnx2x_54618se_link_reset(struct bnx2x_phy *phy,
10583                                      struct link_params *params)
10584 {
10585         struct bnx2x *bp = params->bp;
10586         u32 cfg_pin;
10587         u8 port;
10588
10589         /*
10590          * In case of no EPIO routed to reset the GPHY, put it
10591          * in low power mode.
10592          */
10593         bnx2x_cl22_write(bp, phy, MDIO_PMA_REG_CTRL, 0x800);
10594         /*
10595          * This works with E3 only, no need to check the chip
10596          * before determining the port.
10597          */
10598         port = params->port;
10599         cfg_pin = (REG_RD(bp, params->shmem_base +
10600                         offsetof(struct shmem_region,
10601                         dev_info.port_hw_config[port].e3_cmn_pin_cfg)) &
10602                         PORT_HW_CFG_E3_PHY_RESET_MASK) >>
10603                         PORT_HW_CFG_E3_PHY_RESET_SHIFT;
10604
10605         /* Drive pin low to put GPHY in reset. */
10606         bnx2x_set_cfg_pin(bp, cfg_pin, 0);
10607 }
10608
10609 static u8 bnx2x_54618se_read_status(struct bnx2x_phy *phy,
10610                                     struct link_params *params,
10611                                     struct link_vars *vars)
10612 {
10613         struct bnx2x *bp = params->bp;
10614         u16 val;
10615         u8 link_up = 0;
10616         u16 legacy_status, legacy_speed;
10617
10618         /* Get speed operation status */
10619         bnx2x_cl22_read(bp, phy,
10620                         0x19,
10621                         &legacy_status);
10622         DP(NETIF_MSG_LINK, "54618SE read_status: 0x%x\n", legacy_status);
10623
10624         /* Read status to clear the PHY interrupt. */
10625         bnx2x_cl22_read(bp, phy,
10626                         MDIO_REG_INTR_STATUS,
10627                         &val);
10628
10629         link_up = ((legacy_status & (1<<2)) == (1<<2));
10630
10631         if (link_up) {
10632                 legacy_speed = (legacy_status & (7<<8));
10633                 if (legacy_speed == (7<<8)) {
10634                         vars->line_speed = SPEED_1000;
10635                         vars->duplex = DUPLEX_FULL;
10636                 } else if (legacy_speed == (6<<8)) {
10637                         vars->line_speed = SPEED_1000;
10638                         vars->duplex = DUPLEX_HALF;
10639                 } else if (legacy_speed == (5<<8)) {
10640                         vars->line_speed = SPEED_100;
10641                         vars->duplex = DUPLEX_FULL;
10642                 }
10643                 /* Omitting 100Base-T4 for now */
10644                 else if (legacy_speed == (3<<8)) {
10645                         vars->line_speed = SPEED_100;
10646                         vars->duplex = DUPLEX_HALF;
10647                 } else if (legacy_speed == (2<<8)) {
10648                         vars->line_speed = SPEED_10;
10649                         vars->duplex = DUPLEX_FULL;
10650                 } else if (legacy_speed == (1<<8)) {
10651                         vars->line_speed = SPEED_10;
10652                         vars->duplex = DUPLEX_HALF;
10653                 } else /* Should not happen */
10654                         vars->line_speed = 0;
10655
10656                 DP(NETIF_MSG_LINK,
10657                    "Link is up in %dMbps, is_duplex_full= %d\n",
10658                    vars->line_speed,
10659                    (vars->duplex == DUPLEX_FULL));
10660
10661                 /* Check legacy speed AN resolution */
10662                 bnx2x_cl22_read(bp, phy,
10663                                 0x01,
10664                                 &val);
10665                 if (val & (1<<5))
10666                         vars->link_status |=
10667                                 LINK_STATUS_AUTO_NEGOTIATE_COMPLETE;
10668                 bnx2x_cl22_read(bp, phy,
10669                                 0x06,
10670                                 &val);
10671                 if ((val & (1<<0)) == 0)
10672                         vars->link_status |=
10673                                 LINK_STATUS_PARALLEL_DETECTION_USED;
10674
10675                 DP(NETIF_MSG_LINK, "BCM54618SE: link speed is %d\n",
10676                            vars->line_speed);
10677
10678                 /* Report whether EEE is resolved. */
10679                 bnx2x_cl22_read(bp, phy, MDIO_REG_GPHY_PHYID_LSB, &val);
10680                 if (val == MDIO_REG_GPHY_ID_54618SE) {
10681                         if (vars->link_status &
10682                             LINK_STATUS_AUTO_NEGOTIATE_COMPLETE)
10683                                 val = 0;
10684                         else {
10685                                 bnx2x_cl22_write(bp, phy,
10686                                         MDIO_REG_GPHY_CL45_ADDR_REG,
10687                                         MDIO_AN_DEVAD);
10688                                 bnx2x_cl22_write(bp, phy,
10689                                         MDIO_REG_GPHY_CL45_DATA_REG,
10690                                         MDIO_REG_GPHY_EEE_RESOLVED);
10691                                 bnx2x_cl22_write(bp, phy,
10692                                         MDIO_REG_GPHY_CL45_ADDR_REG,
10693                                         (0x1 << 14) | MDIO_AN_DEVAD);
10694                                 bnx2x_cl22_read(bp, phy,
10695                                         MDIO_REG_GPHY_CL45_DATA_REG,
10696                                         &val);
10697                         }
10698                         DP(NETIF_MSG_LINK, "EEE resolution: 0x%x\n", val);
10699                 }
10700
10701                 bnx2x_ext_phy_resolve_fc(phy, params, vars);
10702
10703                 if (vars->link_status & LINK_STATUS_AUTO_NEGOTIATE_COMPLETE) {
10704                         /* report LP advertised speeds */
10705                         bnx2x_cl22_read(bp, phy, 0x5, &val);
10706
10707                         if (val & (1<<5))
10708                                 vars->link_status |=
10709                                   LINK_STATUS_LINK_PARTNER_10THD_CAPABLE;
10710                         if (val & (1<<6))
10711                                 vars->link_status |=
10712                                   LINK_STATUS_LINK_PARTNER_10TFD_CAPABLE;
10713                         if (val & (1<<7))
10714                                 vars->link_status |=
10715                                   LINK_STATUS_LINK_PARTNER_100TXHD_CAPABLE;
10716                         if (val & (1<<8))
10717                                 vars->link_status |=
10718                                   LINK_STATUS_LINK_PARTNER_100TXFD_CAPABLE;
10719                         if (val & (1<<9))
10720                                 vars->link_status |=
10721                                   LINK_STATUS_LINK_PARTNER_100T4_CAPABLE;
10722
10723                         bnx2x_cl22_read(bp, phy, 0xa, &val);
10724                         if (val & (1<<10))
10725                                 vars->link_status |=
10726                                   LINK_STATUS_LINK_PARTNER_1000THD_CAPABLE;
10727                         if (val & (1<<11))
10728                                 vars->link_status |=
10729                                   LINK_STATUS_LINK_PARTNER_1000TFD_CAPABLE;
10730                 }
10731         }
10732         return link_up;
10733 }
10734
10735 static void bnx2x_54618se_config_loopback(struct bnx2x_phy *phy,
10736                                           struct link_params *params)
10737 {
10738         struct bnx2x *bp = params->bp;
10739         u16 val;
10740         u32 umac_base = params->port ? GRCBASE_UMAC1 : GRCBASE_UMAC0;
10741
10742         DP(NETIF_MSG_LINK, "2PMA/PMD ext_phy_loopback: 54618se\n");
10743
10744         /* Enable master/slave manual mmode and set to master */
10745         /* mii write 9 [bits set 11 12] */
10746         bnx2x_cl22_write(bp, phy, 0x09, 3<<11);
10747
10748         /* forced 1G and disable autoneg */
10749         /* set val [mii read 0] */
10750         /* set val [expr $val & [bits clear 6 12 13]] */
10751         /* set val [expr $val | [bits set 6 8]] */
10752         /* mii write 0 $val */
10753         bnx2x_cl22_read(bp, phy, 0x00, &val);
10754         val &= ~((1<<6) | (1<<12) | (1<<13));
10755         val |= (1<<6) | (1<<8);
10756         bnx2x_cl22_write(bp, phy, 0x00, val);
10757
10758         /* Set external loopback and Tx using 6dB coding */
10759         /* mii write 0x18 7 */
10760         /* set val [mii read 0x18] */
10761         /* mii write 0x18 [expr $val | [bits set 10 15]] */
10762         bnx2x_cl22_write(bp, phy, 0x18, 7);
10763         bnx2x_cl22_read(bp, phy, 0x18, &val);
10764         bnx2x_cl22_write(bp, phy, 0x18, val | (1<<10) | (1<<15));
10765
10766         /* This register opens the gate for the UMAC despite its name */
10767         REG_WR(bp, NIG_REG_EGRESS_EMAC0_PORT + params->port*4, 1);
10768
10769         /*
10770          * Maximum Frame Length (RW). Defines a 14-Bit maximum frame
10771          * length used by the MAC receive logic to check frames.
10772          */
10773         REG_WR(bp, umac_base + UMAC_REG_MAXFR, 0x2710);
10774 }
10775
10776 /******************************************************************/
10777 /*                      SFX7101 PHY SECTION                       */
10778 /******************************************************************/
10779 static void bnx2x_7101_config_loopback(struct bnx2x_phy *phy,
10780                                        struct link_params *params)
10781 {
10782         struct bnx2x *bp = params->bp;
10783         /* SFX7101_XGXS_TEST1 */
10784         bnx2x_cl45_write(bp, phy,
10785                          MDIO_XS_DEVAD, MDIO_XS_SFX7101_XGXS_TEST1, 0x100);
10786 }
10787
10788 static int bnx2x_7101_config_init(struct bnx2x_phy *phy,
10789                                   struct link_params *params,
10790                                   struct link_vars *vars)
10791 {
10792         u16 fw_ver1, fw_ver2, val;
10793         struct bnx2x *bp = params->bp;
10794         DP(NETIF_MSG_LINK, "Setting the SFX7101 LASI indication\n");
10795
10796         /* Restore normal power mode*/
10797         bnx2x_set_gpio(bp, MISC_REGISTERS_GPIO_2,
10798                        MISC_REGISTERS_GPIO_OUTPUT_HIGH, params->port);
10799         /* HW reset */
10800         bnx2x_ext_phy_hw_reset(bp, params->port);
10801         bnx2x_wait_reset_complete(bp, phy, params);
10802
10803         bnx2x_cl45_write(bp, phy,
10804                          MDIO_PMA_DEVAD, MDIO_PMA_LASI_CTRL, 0x1);
10805         DP(NETIF_MSG_LINK, "Setting the SFX7101 LED to blink on traffic\n");
10806         bnx2x_cl45_write(bp, phy,
10807                          MDIO_PMA_DEVAD, MDIO_PMA_REG_7107_LED_CNTL, (1<<3));
10808
10809         bnx2x_ext_phy_set_pause(params, phy, vars);
10810         /* Restart autoneg */
10811         bnx2x_cl45_read(bp, phy,
10812                         MDIO_AN_DEVAD, MDIO_AN_REG_CTRL, &val);
10813         val |= 0x200;
10814         bnx2x_cl45_write(bp, phy,
10815                          MDIO_AN_DEVAD, MDIO_AN_REG_CTRL, val);
10816
10817         /* Save spirom version */
10818         bnx2x_cl45_read(bp, phy,
10819                         MDIO_PMA_DEVAD, MDIO_PMA_REG_7101_VER1, &fw_ver1);
10820
10821         bnx2x_cl45_read(bp, phy,
10822                         MDIO_PMA_DEVAD, MDIO_PMA_REG_7101_VER2, &fw_ver2);
10823         bnx2x_save_spirom_version(bp, params->port,
10824                                   (u32)(fw_ver1<<16 | fw_ver2), phy->ver_addr);
10825         return 0;
10826 }
10827
10828 static u8 bnx2x_7101_read_status(struct bnx2x_phy *phy,
10829                                  struct link_params *params,
10830                                  struct link_vars *vars)
10831 {
10832         struct bnx2x *bp = params->bp;
10833         u8 link_up;
10834         u16 val1, val2;
10835         bnx2x_cl45_read(bp, phy,
10836                         MDIO_PMA_DEVAD, MDIO_PMA_LASI_STAT, &val2);
10837         bnx2x_cl45_read(bp, phy,
10838                         MDIO_PMA_DEVAD, MDIO_PMA_LASI_STAT, &val1);
10839         DP(NETIF_MSG_LINK, "10G-base-T LASI status 0x%x->0x%x\n",
10840                    val2, val1);
10841         bnx2x_cl45_read(bp, phy,
10842                         MDIO_PMA_DEVAD, MDIO_PMA_REG_STATUS, &val2);
10843         bnx2x_cl45_read(bp, phy,
10844                         MDIO_PMA_DEVAD, MDIO_PMA_REG_STATUS, &val1);
10845         DP(NETIF_MSG_LINK, "10G-base-T PMA status 0x%x->0x%x\n",
10846                    val2, val1);
10847         link_up = ((val1 & 4) == 4);
10848         /* if link is up print the AN outcome of the SFX7101 PHY */
10849         if (link_up) {
10850                 bnx2x_cl45_read(bp, phy,
10851                                 MDIO_AN_DEVAD, MDIO_AN_REG_MASTER_STATUS,
10852                                 &val2);
10853                 vars->line_speed = SPEED_10000;
10854                 vars->duplex = DUPLEX_FULL;
10855                 DP(NETIF_MSG_LINK, "SFX7101 AN status 0x%x->Master=%x\n",
10856                            val2, (val2 & (1<<14)));
10857                 bnx2x_ext_phy_10G_an_resolve(bp, phy, vars);
10858                 bnx2x_ext_phy_resolve_fc(phy, params, vars);
10859
10860                 /* read LP advertised speeds */
10861                 if (val2 & (1<<11))
10862                         vars->link_status |=
10863                                 LINK_STATUS_LINK_PARTNER_10GXFD_CAPABLE;
10864         }
10865         return link_up;
10866 }
10867
10868 static int bnx2x_7101_format_ver(u32 spirom_ver, u8 *str, u16 *len)
10869 {
10870         if (*len < 5)
10871                 return -EINVAL;
10872         str[0] = (spirom_ver & 0xFF);
10873         str[1] = (spirom_ver & 0xFF00) >> 8;
10874         str[2] = (spirom_ver & 0xFF0000) >> 16;
10875         str[3] = (spirom_ver & 0xFF000000) >> 24;
10876         str[4] = '\0';
10877         *len -= 5;
10878         return 0;
10879 }
10880
10881 void bnx2x_sfx7101_sp_sw_reset(struct bnx2x *bp, struct bnx2x_phy *phy)
10882 {
10883         u16 val, cnt;
10884
10885         bnx2x_cl45_read(bp, phy,
10886                         MDIO_PMA_DEVAD,
10887                         MDIO_PMA_REG_7101_RESET, &val);
10888
10889         for (cnt = 0; cnt < 10; cnt++) {
10890                 msleep(50);
10891                 /* Writes a self-clearing reset */
10892                 bnx2x_cl45_write(bp, phy,
10893                                  MDIO_PMA_DEVAD,
10894                                  MDIO_PMA_REG_7101_RESET,
10895                                  (val | (1<<15)));
10896                 /* Wait for clear */
10897                 bnx2x_cl45_read(bp, phy,
10898                                 MDIO_PMA_DEVAD,
10899                                 MDIO_PMA_REG_7101_RESET, &val);
10900
10901                 if ((val & (1<<15)) == 0)
10902                         break;
10903         }
10904 }
10905
10906 static void bnx2x_7101_hw_reset(struct bnx2x_phy *phy,
10907                                 struct link_params *params) {
10908         /* Low power mode is controlled by GPIO 2 */
10909         bnx2x_set_gpio(params->bp, MISC_REGISTERS_GPIO_2,
10910                        MISC_REGISTERS_GPIO_OUTPUT_LOW, params->port);
10911         /* The PHY reset is controlled by GPIO 1 */
10912         bnx2x_set_gpio(params->bp, MISC_REGISTERS_GPIO_1,
10913                        MISC_REGISTERS_GPIO_OUTPUT_LOW, params->port);
10914 }
10915
10916 static void bnx2x_7101_set_link_led(struct bnx2x_phy *phy,
10917                                     struct link_params *params, u8 mode)
10918 {
10919         u16 val = 0;
10920         struct bnx2x *bp = params->bp;
10921         switch (mode) {
10922         case LED_MODE_FRONT_PANEL_OFF:
10923         case LED_MODE_OFF:
10924                 val = 2;
10925                 break;
10926         case LED_MODE_ON:
10927                 val = 1;
10928                 break;
10929         case LED_MODE_OPER:
10930                 val = 0;
10931                 break;
10932         }
10933         bnx2x_cl45_write(bp, phy,
10934                          MDIO_PMA_DEVAD,
10935                          MDIO_PMA_REG_7107_LINK_LED_CNTL,
10936                          val);
10937 }
10938
10939 /******************************************************************/
10940 /*                      STATIC PHY DECLARATION                    */
10941 /******************************************************************/
10942
10943 static struct bnx2x_phy phy_null = {
10944         .type           = PORT_HW_CFG_XGXS_EXT_PHY_TYPE_NOT_CONN,
10945         .addr           = 0,
10946         .def_md_devad   = 0,
10947         .flags          = FLAGS_INIT_XGXS_FIRST,
10948         .rx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff},
10949         .tx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff},
10950         .mdio_ctrl      = 0,
10951         .supported      = 0,
10952         .media_type     = ETH_PHY_NOT_PRESENT,
10953         .ver_addr       = 0,
10954         .req_flow_ctrl  = 0,
10955         .req_line_speed = 0,
10956         .speed_cap_mask = 0,
10957         .req_duplex     = 0,
10958         .rsrv           = 0,
10959         .config_init    = (config_init_t)NULL,
10960         .read_status    = (read_status_t)NULL,
10961         .link_reset     = (link_reset_t)NULL,
10962         .config_loopback = (config_loopback_t)NULL,
10963         .format_fw_ver  = (format_fw_ver_t)NULL,
10964         .hw_reset       = (hw_reset_t)NULL,
10965         .set_link_led   = (set_link_led_t)NULL,
10966         .phy_specific_func = (phy_specific_func_t)NULL
10967 };
10968
10969 static struct bnx2x_phy phy_serdes = {
10970         .type           = PORT_HW_CFG_SERDES_EXT_PHY_TYPE_DIRECT,
10971         .addr           = 0xff,
10972         .def_md_devad   = 0,
10973         .flags          = 0,
10974         .rx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff},
10975         .tx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff},
10976         .mdio_ctrl      = 0,
10977         .supported      = (SUPPORTED_10baseT_Half |
10978                            SUPPORTED_10baseT_Full |
10979                            SUPPORTED_100baseT_Half |
10980                            SUPPORTED_100baseT_Full |
10981                            SUPPORTED_1000baseT_Full |
10982                            SUPPORTED_2500baseX_Full |
10983                            SUPPORTED_TP |
10984                            SUPPORTED_Autoneg |
10985                            SUPPORTED_Pause |
10986                            SUPPORTED_Asym_Pause),
10987         .media_type     = ETH_PHY_BASE_T,
10988         .ver_addr       = 0,
10989         .req_flow_ctrl  = 0,
10990         .req_line_speed = 0,
10991         .speed_cap_mask = 0,
10992         .req_duplex     = 0,
10993         .rsrv           = 0,
10994         .config_init    = (config_init_t)bnx2x_xgxs_config_init,
10995         .read_status    = (read_status_t)bnx2x_link_settings_status,
10996         .link_reset     = (link_reset_t)bnx2x_int_link_reset,
10997         .config_loopback = (config_loopback_t)NULL,
10998         .format_fw_ver  = (format_fw_ver_t)NULL,
10999         .hw_reset       = (hw_reset_t)NULL,
11000         .set_link_led   = (set_link_led_t)NULL,
11001         .phy_specific_func = (phy_specific_func_t)NULL
11002 };
11003
11004 static struct bnx2x_phy phy_xgxs = {
11005         .type           = PORT_HW_CFG_XGXS_EXT_PHY_TYPE_DIRECT,
11006         .addr           = 0xff,
11007         .def_md_devad   = 0,
11008         .flags          = 0,
11009         .rx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff},
11010         .tx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff},
11011         .mdio_ctrl      = 0,
11012         .supported      = (SUPPORTED_10baseT_Half |
11013                            SUPPORTED_10baseT_Full |
11014                            SUPPORTED_100baseT_Half |
11015                            SUPPORTED_100baseT_Full |
11016                            SUPPORTED_1000baseT_Full |
11017                            SUPPORTED_2500baseX_Full |
11018                            SUPPORTED_10000baseT_Full |
11019                            SUPPORTED_FIBRE |
11020                            SUPPORTED_Autoneg |
11021                            SUPPORTED_Pause |
11022                            SUPPORTED_Asym_Pause),
11023         .media_type     = ETH_PHY_CX4,
11024         .ver_addr       = 0,
11025         .req_flow_ctrl  = 0,
11026         .req_line_speed = 0,
11027         .speed_cap_mask = 0,
11028         .req_duplex     = 0,
11029         .rsrv           = 0,
11030         .config_init    = (config_init_t)bnx2x_xgxs_config_init,
11031         .read_status    = (read_status_t)bnx2x_link_settings_status,
11032         .link_reset     = (link_reset_t)bnx2x_int_link_reset,
11033         .config_loopback = (config_loopback_t)bnx2x_set_xgxs_loopback,
11034         .format_fw_ver  = (format_fw_ver_t)NULL,
11035         .hw_reset       = (hw_reset_t)NULL,
11036         .set_link_led   = (set_link_led_t)NULL,
11037         .phy_specific_func = (phy_specific_func_t)NULL
11038 };
11039 static struct bnx2x_phy phy_warpcore = {
11040         .type           = PORT_HW_CFG_XGXS_EXT_PHY_TYPE_DIRECT,
11041         .addr           = 0xff,
11042         .def_md_devad   = 0,
11043         .flags          = FLAGS_HW_LOCK_REQUIRED,
11044         .rx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff},
11045         .tx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff},
11046         .mdio_ctrl      = 0,
11047         .supported      = (SUPPORTED_10baseT_Half |
11048                              SUPPORTED_10baseT_Full |
11049                              SUPPORTED_100baseT_Half |
11050                              SUPPORTED_100baseT_Full |
11051                              SUPPORTED_1000baseT_Full |
11052                              SUPPORTED_10000baseT_Full |
11053                              SUPPORTED_20000baseKR2_Full |
11054                              SUPPORTED_20000baseMLD2_Full |
11055                              SUPPORTED_FIBRE |
11056                              SUPPORTED_Autoneg |
11057                              SUPPORTED_Pause |
11058                              SUPPORTED_Asym_Pause),
11059         .media_type     = ETH_PHY_UNSPECIFIED,
11060         .ver_addr       = 0,
11061         .req_flow_ctrl  = 0,
11062         .req_line_speed = 0,
11063         .speed_cap_mask = 0,
11064         /* req_duplex = */0,
11065         /* rsrv = */0,
11066         .config_init    = (config_init_t)bnx2x_warpcore_config_init,
11067         .read_status    = (read_status_t)bnx2x_warpcore_read_status,
11068         .link_reset     = (link_reset_t)bnx2x_warpcore_link_reset,
11069         .config_loopback = (config_loopback_t)bnx2x_set_warpcore_loopback,
11070         .format_fw_ver  = (format_fw_ver_t)NULL,
11071         .hw_reset       = (hw_reset_t)bnx2x_warpcore_hw_reset,
11072         .set_link_led   = (set_link_led_t)NULL,
11073         .phy_specific_func = (phy_specific_func_t)NULL
11074 };
11075
11076
11077 static struct bnx2x_phy phy_7101 = {
11078         .type           = PORT_HW_CFG_XGXS_EXT_PHY_TYPE_SFX7101,
11079         .addr           = 0xff,
11080         .def_md_devad   = 0,
11081         .flags          = FLAGS_FAN_FAILURE_DET_REQ,
11082         .rx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff},
11083         .tx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff},
11084         .mdio_ctrl      = 0,
11085         .supported      = (SUPPORTED_10000baseT_Full |
11086                            SUPPORTED_TP |
11087                            SUPPORTED_Autoneg |
11088                            SUPPORTED_Pause |
11089                            SUPPORTED_Asym_Pause),
11090         .media_type     = ETH_PHY_BASE_T,
11091         .ver_addr       = 0,
11092         .req_flow_ctrl  = 0,
11093         .req_line_speed = 0,
11094         .speed_cap_mask = 0,
11095         .req_duplex     = 0,
11096         .rsrv           = 0,
11097         .config_init    = (config_init_t)bnx2x_7101_config_init,
11098         .read_status    = (read_status_t)bnx2x_7101_read_status,
11099         .link_reset     = (link_reset_t)bnx2x_common_ext_link_reset,
11100         .config_loopback = (config_loopback_t)bnx2x_7101_config_loopback,
11101         .format_fw_ver  = (format_fw_ver_t)bnx2x_7101_format_ver,
11102         .hw_reset       = (hw_reset_t)bnx2x_7101_hw_reset,
11103         .set_link_led   = (set_link_led_t)bnx2x_7101_set_link_led,
11104         .phy_specific_func = (phy_specific_func_t)NULL
11105 };
11106 static struct bnx2x_phy phy_8073 = {
11107         .type           = PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8073,
11108         .addr           = 0xff,
11109         .def_md_devad   = 0,
11110         .flags          = FLAGS_HW_LOCK_REQUIRED,
11111         .rx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff},
11112         .tx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff},
11113         .mdio_ctrl      = 0,
11114         .supported      = (SUPPORTED_10000baseT_Full |
11115                            SUPPORTED_2500baseX_Full |
11116                            SUPPORTED_1000baseT_Full |
11117                            SUPPORTED_FIBRE |
11118                            SUPPORTED_Autoneg |
11119                            SUPPORTED_Pause |
11120                            SUPPORTED_Asym_Pause),
11121         .media_type     = ETH_PHY_KR,
11122         .ver_addr       = 0,
11123         .req_flow_ctrl  = 0,
11124         .req_line_speed = 0,
11125         .speed_cap_mask = 0,
11126         .req_duplex     = 0,
11127         .rsrv           = 0,
11128         .config_init    = (config_init_t)bnx2x_8073_config_init,
11129         .read_status    = (read_status_t)bnx2x_8073_read_status,
11130         .link_reset     = (link_reset_t)bnx2x_8073_link_reset,
11131         .config_loopback = (config_loopback_t)NULL,
11132         .format_fw_ver  = (format_fw_ver_t)bnx2x_format_ver,
11133         .hw_reset       = (hw_reset_t)NULL,
11134         .set_link_led   = (set_link_led_t)NULL,
11135         .phy_specific_func = (phy_specific_func_t)NULL
11136 };
11137 static struct bnx2x_phy phy_8705 = {
11138         .type           = PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8705,
11139         .addr           = 0xff,
11140         .def_md_devad   = 0,
11141         .flags          = FLAGS_INIT_XGXS_FIRST,
11142         .rx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff},
11143         .tx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff},
11144         .mdio_ctrl      = 0,
11145         .supported      = (SUPPORTED_10000baseT_Full |
11146                            SUPPORTED_FIBRE |
11147                            SUPPORTED_Pause |
11148                            SUPPORTED_Asym_Pause),
11149         .media_type     = ETH_PHY_XFP_FIBER,
11150         .ver_addr       = 0,
11151         .req_flow_ctrl  = 0,
11152         .req_line_speed = 0,
11153         .speed_cap_mask = 0,
11154         .req_duplex     = 0,
11155         .rsrv           = 0,
11156         .config_init    = (config_init_t)bnx2x_8705_config_init,
11157         .read_status    = (read_status_t)bnx2x_8705_read_status,
11158         .link_reset     = (link_reset_t)bnx2x_common_ext_link_reset,
11159         .config_loopback = (config_loopback_t)NULL,
11160         .format_fw_ver  = (format_fw_ver_t)bnx2x_null_format_ver,
11161         .hw_reset       = (hw_reset_t)NULL,
11162         .set_link_led   = (set_link_led_t)NULL,
11163         .phy_specific_func = (phy_specific_func_t)NULL
11164 };
11165 static struct bnx2x_phy phy_8706 = {
11166         .type           = PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8706,
11167         .addr           = 0xff,
11168         .def_md_devad   = 0,
11169         .flags          = FLAGS_INIT_XGXS_FIRST,
11170         .rx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff},
11171         .tx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff},
11172         .mdio_ctrl      = 0,
11173         .supported      = (SUPPORTED_10000baseT_Full |
11174                            SUPPORTED_1000baseT_Full |
11175                            SUPPORTED_FIBRE |
11176                            SUPPORTED_Pause |
11177                            SUPPORTED_Asym_Pause),
11178         .media_type     = ETH_PHY_SFP_FIBER,
11179         .ver_addr       = 0,
11180         .req_flow_ctrl  = 0,
11181         .req_line_speed = 0,
11182         .speed_cap_mask = 0,
11183         .req_duplex     = 0,
11184         .rsrv           = 0,
11185         .config_init    = (config_init_t)bnx2x_8706_config_init,
11186         .read_status    = (read_status_t)bnx2x_8706_read_status,
11187         .link_reset     = (link_reset_t)bnx2x_common_ext_link_reset,
11188         .config_loopback = (config_loopback_t)NULL,
11189         .format_fw_ver  = (format_fw_ver_t)bnx2x_format_ver,
11190         .hw_reset       = (hw_reset_t)NULL,
11191         .set_link_led   = (set_link_led_t)NULL,
11192         .phy_specific_func = (phy_specific_func_t)NULL
11193 };
11194
11195 static struct bnx2x_phy phy_8726 = {
11196         .type           = PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8726,
11197         .addr           = 0xff,
11198         .def_md_devad   = 0,
11199         .flags          = (FLAGS_HW_LOCK_REQUIRED |
11200                            FLAGS_INIT_XGXS_FIRST),
11201         .rx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff},
11202         .tx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff},
11203         .mdio_ctrl      = 0,
11204         .supported      = (SUPPORTED_10000baseT_Full |
11205                            SUPPORTED_1000baseT_Full |
11206                            SUPPORTED_Autoneg |
11207                            SUPPORTED_FIBRE |
11208                            SUPPORTED_Pause |
11209                            SUPPORTED_Asym_Pause),
11210         .media_type     = ETH_PHY_NOT_PRESENT,
11211         .ver_addr       = 0,
11212         .req_flow_ctrl  = 0,
11213         .req_line_speed = 0,
11214         .speed_cap_mask = 0,
11215         .req_duplex     = 0,
11216         .rsrv           = 0,
11217         .config_init    = (config_init_t)bnx2x_8726_config_init,
11218         .read_status    = (read_status_t)bnx2x_8726_read_status,
11219         .link_reset     = (link_reset_t)bnx2x_8726_link_reset,
11220         .config_loopback = (config_loopback_t)bnx2x_8726_config_loopback,
11221         .format_fw_ver  = (format_fw_ver_t)bnx2x_format_ver,
11222         .hw_reset       = (hw_reset_t)NULL,
11223         .set_link_led   = (set_link_led_t)NULL,
11224         .phy_specific_func = (phy_specific_func_t)NULL
11225 };
11226
11227 static struct bnx2x_phy phy_8727 = {
11228         .type           = PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8727,
11229         .addr           = 0xff,
11230         .def_md_devad   = 0,
11231         .flags          = FLAGS_FAN_FAILURE_DET_REQ,
11232         .rx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff},
11233         .tx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff},
11234         .mdio_ctrl      = 0,
11235         .supported      = (SUPPORTED_10000baseT_Full |
11236                            SUPPORTED_1000baseT_Full |
11237                            SUPPORTED_FIBRE |
11238                            SUPPORTED_Pause |
11239                            SUPPORTED_Asym_Pause),
11240         .media_type     = ETH_PHY_NOT_PRESENT,
11241         .ver_addr       = 0,
11242         .req_flow_ctrl  = 0,
11243         .req_line_speed = 0,
11244         .speed_cap_mask = 0,
11245         .req_duplex     = 0,
11246         .rsrv           = 0,
11247         .config_init    = (config_init_t)bnx2x_8727_config_init,
11248         .read_status    = (read_status_t)bnx2x_8727_read_status,
11249         .link_reset     = (link_reset_t)bnx2x_8727_link_reset,
11250         .config_loopback = (config_loopback_t)NULL,
11251         .format_fw_ver  = (format_fw_ver_t)bnx2x_format_ver,
11252         .hw_reset       = (hw_reset_t)bnx2x_8727_hw_reset,
11253         .set_link_led   = (set_link_led_t)bnx2x_8727_set_link_led,
11254         .phy_specific_func = (phy_specific_func_t)bnx2x_8727_specific_func
11255 };
11256 static struct bnx2x_phy phy_8481 = {
11257         .type           = PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8481,
11258         .addr           = 0xff,
11259         .def_md_devad   = 0,
11260         .flags          = FLAGS_FAN_FAILURE_DET_REQ |
11261                           FLAGS_REARM_LATCH_SIGNAL,
11262         .rx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff},
11263         .tx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff},
11264         .mdio_ctrl      = 0,
11265         .supported      = (SUPPORTED_10baseT_Half |
11266                            SUPPORTED_10baseT_Full |
11267                            SUPPORTED_100baseT_Half |
11268                            SUPPORTED_100baseT_Full |
11269                            SUPPORTED_1000baseT_Full |
11270                            SUPPORTED_10000baseT_Full |
11271                            SUPPORTED_TP |
11272                            SUPPORTED_Autoneg |
11273                            SUPPORTED_Pause |
11274                            SUPPORTED_Asym_Pause),
11275         .media_type     = ETH_PHY_BASE_T,
11276         .ver_addr       = 0,
11277         .req_flow_ctrl  = 0,
11278         .req_line_speed = 0,
11279         .speed_cap_mask = 0,
11280         .req_duplex     = 0,
11281         .rsrv           = 0,
11282         .config_init    = (config_init_t)bnx2x_8481_config_init,
11283         .read_status    = (read_status_t)bnx2x_848xx_read_status,
11284         .link_reset     = (link_reset_t)bnx2x_8481_link_reset,
11285         .config_loopback = (config_loopback_t)NULL,
11286         .format_fw_ver  = (format_fw_ver_t)bnx2x_848xx_format_ver,
11287         .hw_reset       = (hw_reset_t)bnx2x_8481_hw_reset,
11288         .set_link_led   = (set_link_led_t)bnx2x_848xx_set_link_led,
11289         .phy_specific_func = (phy_specific_func_t)NULL
11290 };
11291
11292 static struct bnx2x_phy phy_84823 = {
11293         .type           = PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM84823,
11294         .addr           = 0xff,
11295         .def_md_devad   = 0,
11296         .flags          = FLAGS_FAN_FAILURE_DET_REQ |
11297                           FLAGS_REARM_LATCH_SIGNAL,
11298         .rx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff},
11299         .tx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff},
11300         .mdio_ctrl      = 0,
11301         .supported      = (SUPPORTED_10baseT_Half |
11302                            SUPPORTED_10baseT_Full |
11303                            SUPPORTED_100baseT_Half |
11304                            SUPPORTED_100baseT_Full |
11305                            SUPPORTED_1000baseT_Full |
11306                            SUPPORTED_10000baseT_Full |
11307                            SUPPORTED_TP |
11308                            SUPPORTED_Autoneg |
11309                            SUPPORTED_Pause |
11310                            SUPPORTED_Asym_Pause),
11311         .media_type     = ETH_PHY_BASE_T,
11312         .ver_addr       = 0,
11313         .req_flow_ctrl  = 0,
11314         .req_line_speed = 0,
11315         .speed_cap_mask = 0,
11316         .req_duplex     = 0,
11317         .rsrv           = 0,
11318         .config_init    = (config_init_t)bnx2x_848x3_config_init,
11319         .read_status    = (read_status_t)bnx2x_848xx_read_status,
11320         .link_reset     = (link_reset_t)bnx2x_848x3_link_reset,
11321         .config_loopback = (config_loopback_t)NULL,
11322         .format_fw_ver  = (format_fw_ver_t)bnx2x_848xx_format_ver,
11323         .hw_reset       = (hw_reset_t)NULL,
11324         .set_link_led   = (set_link_led_t)bnx2x_848xx_set_link_led,
11325         .phy_specific_func = (phy_specific_func_t)NULL
11326 };
11327
11328 static struct bnx2x_phy phy_84833 = {
11329         .type           = PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM84833,
11330         .addr           = 0xff,
11331         .def_md_devad   = 0,
11332         .flags          = FLAGS_FAN_FAILURE_DET_REQ |
11333                             FLAGS_REARM_LATCH_SIGNAL,
11334         .rx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff},
11335         .tx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff},
11336         .mdio_ctrl      = 0,
11337         .supported      = (SUPPORTED_100baseT_Half |
11338                            SUPPORTED_100baseT_Full |
11339                            SUPPORTED_1000baseT_Full |
11340                            SUPPORTED_10000baseT_Full |
11341                            SUPPORTED_TP |
11342                            SUPPORTED_Autoneg |
11343                            SUPPORTED_Pause |
11344                            SUPPORTED_Asym_Pause),
11345         .media_type     = ETH_PHY_BASE_T,
11346         .ver_addr       = 0,
11347         .req_flow_ctrl  = 0,
11348         .req_line_speed = 0,
11349         .speed_cap_mask = 0,
11350         .req_duplex     = 0,
11351         .rsrv           = 0,
11352         .config_init    = (config_init_t)bnx2x_848x3_config_init,
11353         .read_status    = (read_status_t)bnx2x_848xx_read_status,
11354         .link_reset     = (link_reset_t)bnx2x_848x3_link_reset,
11355         .config_loopback = (config_loopback_t)NULL,
11356         .format_fw_ver  = (format_fw_ver_t)bnx2x_848xx_format_ver,
11357         .hw_reset       = (hw_reset_t)bnx2x_84833_hw_reset_phy,
11358         .set_link_led   = (set_link_led_t)bnx2x_848xx_set_link_led,
11359         .phy_specific_func = (phy_specific_func_t)NULL
11360 };
11361
11362 static struct bnx2x_phy phy_54618se = {
11363         .type           = PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM54618SE,
11364         .addr           = 0xff,
11365         .def_md_devad   = 0,
11366         .flags          = FLAGS_INIT_XGXS_FIRST,
11367         .rx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff},
11368         .tx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff},
11369         .mdio_ctrl      = 0,
11370         .supported      = (SUPPORTED_10baseT_Half |
11371                            SUPPORTED_10baseT_Full |
11372                            SUPPORTED_100baseT_Half |
11373                            SUPPORTED_100baseT_Full |
11374                            SUPPORTED_1000baseT_Full |
11375                            SUPPORTED_TP |
11376                            SUPPORTED_Autoneg |
11377                            SUPPORTED_Pause |
11378                            SUPPORTED_Asym_Pause),
11379         .media_type     = ETH_PHY_BASE_T,
11380         .ver_addr       = 0,
11381         .req_flow_ctrl  = 0,
11382         .req_line_speed = 0,
11383         .speed_cap_mask = 0,
11384         /* req_duplex = */0,
11385         /* rsrv = */0,
11386         .config_init    = (config_init_t)bnx2x_54618se_config_init,
11387         .read_status    = (read_status_t)bnx2x_54618se_read_status,
11388         .link_reset     = (link_reset_t)bnx2x_54618se_link_reset,
11389         .config_loopback = (config_loopback_t)bnx2x_54618se_config_loopback,
11390         .format_fw_ver  = (format_fw_ver_t)NULL,
11391         .hw_reset       = (hw_reset_t)NULL,
11392         .set_link_led   = (set_link_led_t)bnx2x_5461x_set_link_led,
11393         .phy_specific_func = (phy_specific_func_t)NULL
11394 };
11395 /*****************************************************************/
11396 /*                                                               */
11397 /* Populate the phy according. Main function: bnx2x_populate_phy   */
11398 /*                                                               */
11399 /*****************************************************************/
11400
11401 static void bnx2x_populate_preemphasis(struct bnx2x *bp, u32 shmem_base,
11402                                      struct bnx2x_phy *phy, u8 port,
11403                                      u8 phy_index)
11404 {
11405         /* Get the 4 lanes xgxs config rx and tx */
11406         u32 rx = 0, tx = 0, i;
11407         for (i = 0; i < 2; i++) {
11408                 /*
11409                  * INT_PHY and EXT_PHY1 share the same value location in the
11410                  * shmem. When num_phys is greater than 1, than this value
11411                  * applies only to EXT_PHY1
11412                  */
11413                 if (phy_index == INT_PHY || phy_index == EXT_PHY1) {
11414                         rx = REG_RD(bp, shmem_base +
11415                                     offsetof(struct shmem_region,
11416                           dev_info.port_hw_config[port].xgxs_config_rx[i<<1]));
11417
11418                         tx = REG_RD(bp, shmem_base +
11419                                     offsetof(struct shmem_region,
11420                           dev_info.port_hw_config[port].xgxs_config_tx[i<<1]));
11421                 } else {
11422                         rx = REG_RD(bp, shmem_base +
11423                                     offsetof(struct shmem_region,
11424                          dev_info.port_hw_config[port].xgxs_config2_rx[i<<1]));
11425
11426                         tx = REG_RD(bp, shmem_base +
11427                                     offsetof(struct shmem_region,
11428                          dev_info.port_hw_config[port].xgxs_config2_rx[i<<1]));
11429                 }
11430
11431                 phy->rx_preemphasis[i << 1] = ((rx>>16) & 0xffff);
11432                 phy->rx_preemphasis[(i << 1) + 1] = (rx & 0xffff);
11433
11434                 phy->tx_preemphasis[i << 1] = ((tx>>16) & 0xffff);
11435                 phy->tx_preemphasis[(i << 1) + 1] = (tx & 0xffff);
11436         }
11437 }
11438
11439 static u32 bnx2x_get_ext_phy_config(struct bnx2x *bp, u32 shmem_base,
11440                                     u8 phy_index, u8 port)
11441 {
11442         u32 ext_phy_config = 0;
11443         switch (phy_index) {
11444         case EXT_PHY1:
11445                 ext_phy_config = REG_RD(bp, shmem_base +
11446                                               offsetof(struct shmem_region,
11447                         dev_info.port_hw_config[port].external_phy_config));
11448                 break;
11449         case EXT_PHY2:
11450                 ext_phy_config = REG_RD(bp, shmem_base +
11451                                               offsetof(struct shmem_region,
11452                         dev_info.port_hw_config[port].external_phy_config2));
11453                 break;
11454         default:
11455                 DP(NETIF_MSG_LINK, "Invalid phy_index %d\n", phy_index);
11456                 return -EINVAL;
11457         }
11458
11459         return ext_phy_config;
11460 }
11461 static int bnx2x_populate_int_phy(struct bnx2x *bp, u32 shmem_base, u8 port,
11462                                   struct bnx2x_phy *phy)
11463 {
11464         u32 phy_addr;
11465         u32 chip_id;
11466         u32 switch_cfg = (REG_RD(bp, shmem_base +
11467                                        offsetof(struct shmem_region,
11468                         dev_info.port_feature_config[port].link_config)) &
11469                           PORT_FEATURE_CONNECTED_SWITCH_MASK);
11470         chip_id = (REG_RD(bp, MISC_REG_CHIP_NUM) << 16) |
11471                 ((REG_RD(bp, MISC_REG_CHIP_REV) & 0xf) << 12);
11472
11473         DP(NETIF_MSG_LINK, ":chip_id = 0x%x\n", chip_id);
11474         if (USES_WARPCORE(bp)) {
11475                 u32 serdes_net_if;
11476                 phy_addr = REG_RD(bp,
11477                                   MISC_REG_WC0_CTRL_PHY_ADDR);
11478                 *phy = phy_warpcore;
11479                 if (REG_RD(bp, MISC_REG_PORT4MODE_EN_OVWR) == 0x3)
11480                         phy->flags |= FLAGS_4_PORT_MODE;
11481                 else
11482                         phy->flags &= ~FLAGS_4_PORT_MODE;
11483                         /* Check Dual mode */
11484                 serdes_net_if = (REG_RD(bp, shmem_base +
11485                                         offsetof(struct shmem_region, dev_info.
11486                                         port_hw_config[port].default_cfg)) &
11487                                  PORT_HW_CFG_NET_SERDES_IF_MASK);
11488                 /*
11489                  * Set the appropriate supported and flags indications per
11490                  * interface type of the chip
11491                  */
11492                 switch (serdes_net_if) {
11493                 case PORT_HW_CFG_NET_SERDES_IF_SGMII:
11494                         phy->supported &= (SUPPORTED_10baseT_Half |
11495                                            SUPPORTED_10baseT_Full |
11496                                            SUPPORTED_100baseT_Half |
11497                                            SUPPORTED_100baseT_Full |
11498                                            SUPPORTED_1000baseT_Full |
11499                                            SUPPORTED_FIBRE |
11500                                            SUPPORTED_Autoneg |
11501                                            SUPPORTED_Pause |
11502                                            SUPPORTED_Asym_Pause);
11503                         phy->media_type = ETH_PHY_BASE_T;
11504                         break;
11505                 case PORT_HW_CFG_NET_SERDES_IF_XFI:
11506                         phy->media_type = ETH_PHY_XFP_FIBER;
11507                         break;
11508                 case PORT_HW_CFG_NET_SERDES_IF_SFI:
11509                         phy->supported &= (SUPPORTED_1000baseT_Full |
11510                                            SUPPORTED_10000baseT_Full |
11511                                            SUPPORTED_FIBRE |
11512                                            SUPPORTED_Pause |
11513                                            SUPPORTED_Asym_Pause);
11514                         phy->media_type = ETH_PHY_SFP_FIBER;
11515                         break;
11516                 case PORT_HW_CFG_NET_SERDES_IF_KR:
11517                         phy->media_type = ETH_PHY_KR;
11518                         phy->supported &= (SUPPORTED_1000baseT_Full |
11519                                            SUPPORTED_10000baseT_Full |
11520                                            SUPPORTED_FIBRE |
11521                                            SUPPORTED_Autoneg |
11522                                            SUPPORTED_Pause |
11523                                            SUPPORTED_Asym_Pause);
11524                         break;
11525                 case PORT_HW_CFG_NET_SERDES_IF_DXGXS:
11526                         phy->media_type = ETH_PHY_KR;
11527                         phy->flags |= FLAGS_WC_DUAL_MODE;
11528                         phy->supported &= (SUPPORTED_20000baseMLD2_Full |
11529                                            SUPPORTED_FIBRE |
11530                                            SUPPORTED_Pause |
11531                                            SUPPORTED_Asym_Pause);
11532                         break;
11533                 case PORT_HW_CFG_NET_SERDES_IF_KR2:
11534                         phy->media_type = ETH_PHY_KR;
11535                         phy->flags |= FLAGS_WC_DUAL_MODE;
11536                         phy->supported &= (SUPPORTED_20000baseKR2_Full |
11537                                            SUPPORTED_FIBRE |
11538                                            SUPPORTED_Pause |
11539                                            SUPPORTED_Asym_Pause);
11540                         break;
11541                 default:
11542                         DP(NETIF_MSG_LINK, "Unknown WC interface type 0x%x\n",
11543                                        serdes_net_if);
11544                         break;
11545                 }
11546
11547                 /*
11548                  * Enable MDC/MDIO work-around for E3 A0 since free running MDC
11549                  * was not set as expected. For B0, ECO will be enabled so there
11550                  * won't be an issue there
11551                  */
11552                 if (CHIP_REV(bp) == CHIP_REV_Ax)
11553                         phy->flags |= FLAGS_MDC_MDIO_WA;
11554                 else
11555                         phy->flags |= FLAGS_MDC_MDIO_WA_B0;
11556         } else {
11557                 switch (switch_cfg) {
11558                 case SWITCH_CFG_1G:
11559                         phy_addr = REG_RD(bp,
11560                                           NIG_REG_SERDES0_CTRL_PHY_ADDR +
11561                                           port * 0x10);
11562                         *phy = phy_serdes;
11563                         break;
11564                 case SWITCH_CFG_10G:
11565                         phy_addr = REG_RD(bp,
11566                                           NIG_REG_XGXS0_CTRL_PHY_ADDR +
11567                                           port * 0x18);
11568                         *phy = phy_xgxs;
11569                         break;
11570                 default:
11571                         DP(NETIF_MSG_LINK, "Invalid switch_cfg\n");
11572                         return -EINVAL;
11573                 }
11574         }
11575         phy->addr = (u8)phy_addr;
11576         phy->mdio_ctrl = bnx2x_get_emac_base(bp,
11577                                             SHARED_HW_CFG_MDC_MDIO_ACCESS1_BOTH,
11578                                             port);
11579         if (CHIP_IS_E2(bp))
11580                 phy->def_md_devad = E2_DEFAULT_PHY_DEV_ADDR;
11581         else
11582                 phy->def_md_devad = DEFAULT_PHY_DEV_ADDR;
11583
11584         DP(NETIF_MSG_LINK, "Internal phy port=%d, addr=0x%x, mdio_ctl=0x%x\n",
11585                    port, phy->addr, phy->mdio_ctrl);
11586
11587         bnx2x_populate_preemphasis(bp, shmem_base, phy, port, INT_PHY);
11588         return 0;
11589 }
11590
11591 static int bnx2x_populate_ext_phy(struct bnx2x *bp,
11592                                   u8 phy_index,
11593                                   u32 shmem_base,
11594                                   u32 shmem2_base,
11595                                   u8 port,
11596                                   struct bnx2x_phy *phy)
11597 {
11598         u32 ext_phy_config, phy_type, config2;
11599         u32 mdc_mdio_access = SHARED_HW_CFG_MDC_MDIO_ACCESS1_BOTH;
11600         ext_phy_config = bnx2x_get_ext_phy_config(bp, shmem_base,
11601                                                   phy_index, port);
11602         phy_type = XGXS_EXT_PHY_TYPE(ext_phy_config);
11603         /* Select the phy type */
11604         switch (phy_type) {
11605         case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8073:
11606                 mdc_mdio_access = SHARED_HW_CFG_MDC_MDIO_ACCESS1_SWAPPED;
11607                 *phy = phy_8073;
11608                 break;
11609         case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8705:
11610                 *phy = phy_8705;
11611                 break;
11612         case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8706:
11613                 *phy = phy_8706;
11614                 break;
11615         case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8726:
11616                 mdc_mdio_access = SHARED_HW_CFG_MDC_MDIO_ACCESS1_EMAC1;
11617                 *phy = phy_8726;
11618                 break;
11619         case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8727_NOC:
11620                 /* BCM8727_NOC => BCM8727 no over current */
11621                 mdc_mdio_access = SHARED_HW_CFG_MDC_MDIO_ACCESS1_EMAC1;
11622                 *phy = phy_8727;
11623                 phy->flags |= FLAGS_NOC;
11624                 break;
11625         case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8722:
11626         case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8727:
11627                 mdc_mdio_access = SHARED_HW_CFG_MDC_MDIO_ACCESS1_EMAC1;
11628                 *phy = phy_8727;
11629                 break;
11630         case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8481:
11631                 *phy = phy_8481;
11632                 break;
11633         case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM84823:
11634                 *phy = phy_84823;
11635                 break;
11636         case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM84833:
11637                 *phy = phy_84833;
11638                 break;
11639         case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM54616:
11640         case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM54618SE:
11641                 *phy = phy_54618se;
11642                 break;
11643         case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_SFX7101:
11644                 *phy = phy_7101;
11645                 break;
11646         case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_FAILURE:
11647                 *phy = phy_null;
11648                 return -EINVAL;
11649         default:
11650                 *phy = phy_null;
11651                 /* In case external PHY wasn't found */
11652                 if ((phy_type != PORT_HW_CFG_XGXS_EXT_PHY_TYPE_DIRECT) &&
11653                     (phy_type != PORT_HW_CFG_XGXS_EXT_PHY_TYPE_NOT_CONN))
11654                         return -EINVAL;
11655                 return 0;
11656         }
11657
11658         phy->addr = XGXS_EXT_PHY_ADDR(ext_phy_config);
11659         bnx2x_populate_preemphasis(bp, shmem_base, phy, port, phy_index);
11660
11661         /*
11662          * The shmem address of the phy version is located on different
11663          * structures. In case this structure is too old, do not set
11664          * the address
11665          */
11666         config2 = REG_RD(bp, shmem_base + offsetof(struct shmem_region,
11667                                         dev_info.shared_hw_config.config2));
11668         if (phy_index == EXT_PHY1) {
11669                 phy->ver_addr = shmem_base + offsetof(struct shmem_region,
11670                                 port_mb[port].ext_phy_fw_version);
11671
11672                 /* Check specific mdc mdio settings */
11673                 if (config2 & SHARED_HW_CFG_MDC_MDIO_ACCESS1_MASK)
11674                         mdc_mdio_access = config2 &
11675                         SHARED_HW_CFG_MDC_MDIO_ACCESS1_MASK;
11676         } else {
11677                 u32 size = REG_RD(bp, shmem2_base);
11678
11679                 if (size >
11680                     offsetof(struct shmem2_region, ext_phy_fw_version2)) {
11681                         phy->ver_addr = shmem2_base +
11682                             offsetof(struct shmem2_region,
11683                                      ext_phy_fw_version2[port]);
11684                 }
11685                 /* Check specific mdc mdio settings */
11686                 if (config2 & SHARED_HW_CFG_MDC_MDIO_ACCESS2_MASK)
11687                         mdc_mdio_access = (config2 &
11688                         SHARED_HW_CFG_MDC_MDIO_ACCESS2_MASK) >>
11689                         (SHARED_HW_CFG_MDC_MDIO_ACCESS2_SHIFT -
11690                          SHARED_HW_CFG_MDC_MDIO_ACCESS1_SHIFT);
11691         }
11692         phy->mdio_ctrl = bnx2x_get_emac_base(bp, mdc_mdio_access, port);
11693
11694         if ((phy->type == PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM84833) &&
11695             (phy->ver_addr)) {
11696                 /*
11697                  * Remove 100Mb link supported for BCM84833 when phy fw
11698                  * version lower than or equal to 1.39
11699                  */
11700                 u32 raw_ver = REG_RD(bp, phy->ver_addr);
11701                 if (((raw_ver & 0x7F) <= 39) &&
11702                     (((raw_ver & 0xF80) >> 7) <= 1))
11703                         phy->supported &= ~(SUPPORTED_100baseT_Half |
11704                                             SUPPORTED_100baseT_Full);
11705         }
11706
11707         /*
11708          * In case mdc/mdio_access of the external phy is different than the
11709          * mdc/mdio access of the XGXS, a HW lock must be taken in each access
11710          * to prevent one port interfere with another port's CL45 operations.
11711          */
11712         if (mdc_mdio_access != SHARED_HW_CFG_MDC_MDIO_ACCESS1_BOTH)
11713                 phy->flags |= FLAGS_HW_LOCK_REQUIRED;
11714         DP(NETIF_MSG_LINK, "phy_type 0x%x port %d found in index %d\n",
11715                    phy_type, port, phy_index);
11716         DP(NETIF_MSG_LINK, "             addr=0x%x, mdio_ctl=0x%x\n",
11717                    phy->addr, phy->mdio_ctrl);
11718         return 0;
11719 }
11720
11721 static int bnx2x_populate_phy(struct bnx2x *bp, u8 phy_index, u32 shmem_base,
11722                               u32 shmem2_base, u8 port, struct bnx2x_phy *phy)
11723 {
11724         int status = 0;
11725         phy->type = PORT_HW_CFG_XGXS_EXT_PHY_TYPE_NOT_CONN;
11726         if (phy_index == INT_PHY)
11727                 return bnx2x_populate_int_phy(bp, shmem_base, port, phy);
11728         status = bnx2x_populate_ext_phy(bp, phy_index, shmem_base, shmem2_base,
11729                                         port, phy);
11730         return status;
11731 }
11732
11733 static void bnx2x_phy_def_cfg(struct link_params *params,
11734                               struct bnx2x_phy *phy,
11735                               u8 phy_index)
11736 {
11737         struct bnx2x *bp = params->bp;
11738         u32 link_config;
11739         /* Populate the default phy configuration for MF mode */
11740         if (phy_index == EXT_PHY2) {
11741                 link_config = REG_RD(bp, params->shmem_base +
11742                                      offsetof(struct shmem_region, dev_info.
11743                         port_feature_config[params->port].link_config2));
11744                 phy->speed_cap_mask = REG_RD(bp, params->shmem_base +
11745                                              offsetof(struct shmem_region,
11746                                                       dev_info.
11747                         port_hw_config[params->port].speed_capability_mask2));
11748         } else {
11749                 link_config = REG_RD(bp, params->shmem_base +
11750                                      offsetof(struct shmem_region, dev_info.
11751                                 port_feature_config[params->port].link_config));
11752                 phy->speed_cap_mask = REG_RD(bp, params->shmem_base +
11753                                              offsetof(struct shmem_region,
11754                                                       dev_info.
11755                         port_hw_config[params->port].speed_capability_mask));
11756         }
11757         DP(NETIF_MSG_LINK,
11758            "Default config phy idx %x cfg 0x%x speed_cap_mask 0x%x\n",
11759            phy_index, link_config, phy->speed_cap_mask);
11760
11761         phy->req_duplex = DUPLEX_FULL;
11762         switch (link_config  & PORT_FEATURE_LINK_SPEED_MASK) {
11763         case PORT_FEATURE_LINK_SPEED_10M_HALF:
11764                 phy->req_duplex = DUPLEX_HALF;
11765         case PORT_FEATURE_LINK_SPEED_10M_FULL:
11766                 phy->req_line_speed = SPEED_10;
11767                 break;
11768         case PORT_FEATURE_LINK_SPEED_100M_HALF:
11769                 phy->req_duplex = DUPLEX_HALF;
11770         case PORT_FEATURE_LINK_SPEED_100M_FULL:
11771                 phy->req_line_speed = SPEED_100;
11772                 break;
11773         case PORT_FEATURE_LINK_SPEED_1G:
11774                 phy->req_line_speed = SPEED_1000;
11775                 break;
11776         case PORT_FEATURE_LINK_SPEED_2_5G:
11777                 phy->req_line_speed = SPEED_2500;
11778                 break;
11779         case PORT_FEATURE_LINK_SPEED_10G_CX4:
11780                 phy->req_line_speed = SPEED_10000;
11781                 break;
11782         default:
11783                 phy->req_line_speed = SPEED_AUTO_NEG;
11784                 break;
11785         }
11786
11787         switch (link_config  & PORT_FEATURE_FLOW_CONTROL_MASK) {
11788         case PORT_FEATURE_FLOW_CONTROL_AUTO:
11789                 phy->req_flow_ctrl = BNX2X_FLOW_CTRL_AUTO;
11790                 break;
11791         case PORT_FEATURE_FLOW_CONTROL_TX:
11792                 phy->req_flow_ctrl = BNX2X_FLOW_CTRL_TX;
11793                 break;
11794         case PORT_FEATURE_FLOW_CONTROL_RX:
11795                 phy->req_flow_ctrl = BNX2X_FLOW_CTRL_RX;
11796                 break;
11797         case PORT_FEATURE_FLOW_CONTROL_BOTH:
11798                 phy->req_flow_ctrl = BNX2X_FLOW_CTRL_BOTH;
11799                 break;
11800         default:
11801                 phy->req_flow_ctrl = BNX2X_FLOW_CTRL_NONE;
11802                 break;
11803         }
11804 }
11805
11806 u32 bnx2x_phy_selection(struct link_params *params)
11807 {
11808         u32 phy_config_swapped, prio_cfg;
11809         u32 return_cfg = PORT_HW_CFG_PHY_SELECTION_HARDWARE_DEFAULT;
11810
11811         phy_config_swapped = params->multi_phy_config &
11812                 PORT_HW_CFG_PHY_SWAPPED_ENABLED;
11813
11814         prio_cfg = params->multi_phy_config &
11815                         PORT_HW_CFG_PHY_SELECTION_MASK;
11816
11817         if (phy_config_swapped) {
11818                 switch (prio_cfg) {
11819                 case PORT_HW_CFG_PHY_SELECTION_FIRST_PHY_PRIORITY:
11820                      return_cfg = PORT_HW_CFG_PHY_SELECTION_SECOND_PHY_PRIORITY;
11821                      break;
11822                 case PORT_HW_CFG_PHY_SELECTION_SECOND_PHY_PRIORITY:
11823                      return_cfg = PORT_HW_CFG_PHY_SELECTION_FIRST_PHY_PRIORITY;
11824                      break;
11825                 case PORT_HW_CFG_PHY_SELECTION_SECOND_PHY:
11826                      return_cfg = PORT_HW_CFG_PHY_SELECTION_FIRST_PHY;
11827                      break;
11828                 case PORT_HW_CFG_PHY_SELECTION_FIRST_PHY:
11829                      return_cfg = PORT_HW_CFG_PHY_SELECTION_SECOND_PHY;
11830                      break;
11831                 }
11832         } else
11833                 return_cfg = prio_cfg;
11834
11835         return return_cfg;
11836 }
11837
11838
11839 int bnx2x_phy_probe(struct link_params *params)
11840 {
11841         u8 phy_index, actual_phy_idx;
11842         u32 phy_config_swapped, sync_offset, media_types;
11843         struct bnx2x *bp = params->bp;
11844         struct bnx2x_phy *phy;
11845         params->num_phys = 0;
11846         DP(NETIF_MSG_LINK, "Begin phy probe\n");
11847         phy_config_swapped = params->multi_phy_config &
11848                 PORT_HW_CFG_PHY_SWAPPED_ENABLED;
11849
11850         for (phy_index = INT_PHY; phy_index < MAX_PHYS;
11851               phy_index++) {
11852                 actual_phy_idx = phy_index;
11853                 if (phy_config_swapped) {
11854                         if (phy_index == EXT_PHY1)
11855                                 actual_phy_idx = EXT_PHY2;
11856                         else if (phy_index == EXT_PHY2)
11857                                 actual_phy_idx = EXT_PHY1;
11858                 }
11859                 DP(NETIF_MSG_LINK, "phy_config_swapped %x, phy_index %x,"
11860                                " actual_phy_idx %x\n", phy_config_swapped,
11861                            phy_index, actual_phy_idx);
11862                 phy = &params->phy[actual_phy_idx];
11863                 if (bnx2x_populate_phy(bp, phy_index, params->shmem_base,
11864                                        params->shmem2_base, params->port,
11865                                        phy) != 0) {
11866                         params->num_phys = 0;
11867                         DP(NETIF_MSG_LINK, "phy probe failed in phy index %d\n",
11868                                    phy_index);
11869                         for (phy_index = INT_PHY;
11870                               phy_index < MAX_PHYS;
11871                               phy_index++)
11872                                 *phy = phy_null;
11873                         return -EINVAL;
11874                 }
11875                 if (phy->type == PORT_HW_CFG_XGXS_EXT_PHY_TYPE_NOT_CONN)
11876                         break;
11877
11878                 sync_offset = params->shmem_base +
11879                         offsetof(struct shmem_region,
11880                         dev_info.port_hw_config[params->port].media_type);
11881                 media_types = REG_RD(bp, sync_offset);
11882
11883                 /*
11884                  * Update media type for non-PMF sync only for the first time
11885                  * In case the media type changes afterwards, it will be updated
11886                  * using the update_status function
11887                  */
11888                 if ((media_types & (PORT_HW_CFG_MEDIA_TYPE_PHY0_MASK <<
11889                                     (PORT_HW_CFG_MEDIA_TYPE_PHY1_SHIFT *
11890                                      actual_phy_idx))) == 0) {
11891                         media_types |= ((phy->media_type &
11892                                         PORT_HW_CFG_MEDIA_TYPE_PHY0_MASK) <<
11893                                 (PORT_HW_CFG_MEDIA_TYPE_PHY1_SHIFT *
11894                                  actual_phy_idx));
11895                 }
11896                 REG_WR(bp, sync_offset, media_types);
11897
11898                 bnx2x_phy_def_cfg(params, phy, phy_index);
11899                 params->num_phys++;
11900         }
11901
11902         DP(NETIF_MSG_LINK, "End phy probe. #phys found %x\n", params->num_phys);
11903         return 0;
11904 }
11905
11906 void bnx2x_init_bmac_loopback(struct link_params *params,
11907                               struct link_vars *vars)
11908 {
11909         struct bnx2x *bp = params->bp;
11910                 vars->link_up = 1;
11911                 vars->line_speed = SPEED_10000;
11912                 vars->duplex = DUPLEX_FULL;
11913                 vars->flow_ctrl = BNX2X_FLOW_CTRL_NONE;
11914                 vars->mac_type = MAC_TYPE_BMAC;
11915
11916                 vars->phy_flags = PHY_XGXS_FLAG;
11917
11918                 bnx2x_xgxs_deassert(params);
11919
11920                 /* set bmac loopback */
11921                 bnx2x_bmac_enable(params, vars, 1);
11922
11923                 REG_WR(bp, NIG_REG_EGRESS_DRAIN0_MODE + params->port*4, 0);
11924 }
11925
11926 void bnx2x_init_emac_loopback(struct link_params *params,
11927                               struct link_vars *vars)
11928 {
11929         struct bnx2x *bp = params->bp;
11930                 vars->link_up = 1;
11931                 vars->line_speed = SPEED_1000;
11932                 vars->duplex = DUPLEX_FULL;
11933                 vars->flow_ctrl = BNX2X_FLOW_CTRL_NONE;
11934                 vars->mac_type = MAC_TYPE_EMAC;
11935
11936                 vars->phy_flags = PHY_XGXS_FLAG;
11937
11938                 bnx2x_xgxs_deassert(params);
11939                 /* set bmac loopback */
11940                 bnx2x_emac_enable(params, vars, 1);
11941                 bnx2x_emac_program(params, vars);
11942                 REG_WR(bp, NIG_REG_EGRESS_DRAIN0_MODE + params->port*4, 0);
11943 }
11944
11945 void bnx2x_init_xmac_loopback(struct link_params *params,
11946                               struct link_vars *vars)
11947 {
11948         struct bnx2x *bp = params->bp;
11949         vars->link_up = 1;
11950         if (!params->req_line_speed[0])
11951                 vars->line_speed = SPEED_10000;
11952         else
11953                 vars->line_speed = params->req_line_speed[0];
11954         vars->duplex = DUPLEX_FULL;
11955         vars->flow_ctrl = BNX2X_FLOW_CTRL_NONE;
11956         vars->mac_type = MAC_TYPE_XMAC;
11957         vars->phy_flags = PHY_XGXS_FLAG;
11958         /*
11959          * Set WC to loopback mode since link is required to provide clock
11960          * to the XMAC in 20G mode
11961          */
11962         bnx2x_set_aer_mmd(params, &params->phy[0]);
11963         bnx2x_warpcore_reset_lane(bp, &params->phy[0], 0);
11964         params->phy[INT_PHY].config_loopback(
11965                         &params->phy[INT_PHY],
11966                         params);
11967
11968         bnx2x_xmac_enable(params, vars, 1);
11969         REG_WR(bp, NIG_REG_EGRESS_DRAIN0_MODE + params->port*4, 0);
11970 }
11971
11972 void bnx2x_init_umac_loopback(struct link_params *params,
11973                               struct link_vars *vars)
11974 {
11975         struct bnx2x *bp = params->bp;
11976         vars->link_up = 1;
11977         vars->line_speed = SPEED_1000;
11978         vars->duplex = DUPLEX_FULL;
11979         vars->flow_ctrl = BNX2X_FLOW_CTRL_NONE;
11980         vars->mac_type = MAC_TYPE_UMAC;
11981         vars->phy_flags = PHY_XGXS_FLAG;
11982         bnx2x_umac_enable(params, vars, 1);
11983
11984         REG_WR(bp, NIG_REG_EGRESS_DRAIN0_MODE + params->port*4, 0);
11985 }
11986
11987 void bnx2x_init_xgxs_loopback(struct link_params *params,
11988                               struct link_vars *vars)
11989 {
11990         struct bnx2x *bp = params->bp;
11991                 vars->link_up = 1;
11992                 vars->flow_ctrl = BNX2X_FLOW_CTRL_NONE;
11993                 vars->duplex = DUPLEX_FULL;
11994         if (params->req_line_speed[0] == SPEED_1000)
11995                         vars->line_speed = SPEED_1000;
11996         else
11997                         vars->line_speed = SPEED_10000;
11998
11999         if (!USES_WARPCORE(bp))
12000                 bnx2x_xgxs_deassert(params);
12001         bnx2x_link_initialize(params, vars);
12002
12003         if (params->req_line_speed[0] == SPEED_1000) {
12004                 if (USES_WARPCORE(bp))
12005                         bnx2x_umac_enable(params, vars, 0);
12006                 else {
12007                         bnx2x_emac_program(params, vars);
12008                         bnx2x_emac_enable(params, vars, 0);
12009                 }
12010         } else {
12011                 if (USES_WARPCORE(bp))
12012                         bnx2x_xmac_enable(params, vars, 0);
12013                 else
12014                         bnx2x_bmac_enable(params, vars, 0);
12015         }
12016
12017                 if (params->loopback_mode == LOOPBACK_XGXS) {
12018                         /* set 10G XGXS loopback */
12019                         params->phy[INT_PHY].config_loopback(
12020                                 &params->phy[INT_PHY],
12021                                 params);
12022
12023                 } else {
12024                         /* set external phy loopback */
12025                         u8 phy_index;
12026                         for (phy_index = EXT_PHY1;
12027                               phy_index < params->num_phys; phy_index++) {
12028                                 if (params->phy[phy_index].config_loopback)
12029                                         params->phy[phy_index].config_loopback(
12030                                                 &params->phy[phy_index],
12031                                                 params);
12032                         }
12033                 }
12034                 REG_WR(bp, NIG_REG_EGRESS_DRAIN0_MODE + params->port*4, 0);
12035
12036         bnx2x_set_led(params, vars, LED_MODE_OPER, vars->line_speed);
12037 }
12038
12039 int bnx2x_phy_init(struct link_params *params, struct link_vars *vars)
12040 {
12041         struct bnx2x *bp = params->bp;
12042         DP(NETIF_MSG_LINK, "Phy Initialization started\n");
12043         DP(NETIF_MSG_LINK, "(1) req_speed %d, req_flowctrl %d\n",
12044                    params->req_line_speed[0], params->req_flow_ctrl[0]);
12045         DP(NETIF_MSG_LINK, "(2) req_speed %d, req_flowctrl %d\n",
12046                    params->req_line_speed[1], params->req_flow_ctrl[1]);
12047         vars->link_status = 0;
12048         vars->phy_link_up = 0;
12049         vars->link_up = 0;
12050         vars->line_speed = 0;
12051         vars->duplex = DUPLEX_FULL;
12052         vars->flow_ctrl = BNX2X_FLOW_CTRL_NONE;
12053         vars->mac_type = MAC_TYPE_NONE;
12054         vars->phy_flags = 0;
12055
12056         /* disable attentions */
12057         bnx2x_bits_dis(bp, NIG_REG_MASK_INTERRUPT_PORT0 + params->port*4,
12058                        (NIG_MASK_XGXS0_LINK_STATUS |
12059                         NIG_MASK_XGXS0_LINK10G |
12060                         NIG_MASK_SERDES0_LINK_STATUS |
12061                         NIG_MASK_MI_INT));
12062
12063         bnx2x_emac_init(params, vars);
12064
12065         if (params->feature_config_flags & FEATURE_CONFIG_PFC_ENABLED)
12066                 vars->link_status |= LINK_STATUS_PFC_ENABLED;
12067
12068         if (params->num_phys == 0) {
12069                 DP(NETIF_MSG_LINK, "No phy found for initialization !!\n");
12070                 return -EINVAL;
12071         }
12072         set_phy_vars(params, vars);
12073
12074         DP(NETIF_MSG_LINK, "Num of phys on board: %d\n", params->num_phys);
12075         switch (params->loopback_mode) {
12076         case LOOPBACK_BMAC:
12077                 bnx2x_init_bmac_loopback(params, vars);
12078                 break;
12079         case LOOPBACK_EMAC:
12080                 bnx2x_init_emac_loopback(params, vars);
12081                 break;
12082         case LOOPBACK_XMAC:
12083                 bnx2x_init_xmac_loopback(params, vars);
12084                 break;
12085         case LOOPBACK_UMAC:
12086                 bnx2x_init_umac_loopback(params, vars);
12087                 break;
12088         case LOOPBACK_XGXS:
12089         case LOOPBACK_EXT_PHY:
12090                 bnx2x_init_xgxs_loopback(params, vars);
12091                 break;
12092         default:
12093                 if (!CHIP_IS_E3(bp)) {
12094                         if (params->switch_cfg == SWITCH_CFG_10G)
12095                                 bnx2x_xgxs_deassert(params);
12096                         else
12097                                 bnx2x_serdes_deassert(bp, params->port);
12098                 }
12099                 bnx2x_link_initialize(params, vars);
12100                 msleep(30);
12101                 bnx2x_link_int_enable(params);
12102                 break;
12103         }
12104         return 0;
12105 }
12106
12107 int bnx2x_link_reset(struct link_params *params, struct link_vars *vars,
12108                      u8 reset_ext_phy)
12109 {
12110         struct bnx2x *bp = params->bp;
12111         u8 phy_index, port = params->port, clear_latch_ind = 0;
12112         DP(NETIF_MSG_LINK, "Resetting the link of port %d\n", port);
12113         /* disable attentions */
12114         vars->link_status = 0;
12115         bnx2x_update_mng(params, vars->link_status);
12116         bnx2x_bits_dis(bp, NIG_REG_MASK_INTERRUPT_PORT0 + port*4,
12117                        (NIG_MASK_XGXS0_LINK_STATUS |
12118                         NIG_MASK_XGXS0_LINK10G |
12119                         NIG_MASK_SERDES0_LINK_STATUS |
12120                         NIG_MASK_MI_INT));
12121
12122         /* activate nig drain */
12123         REG_WR(bp, NIG_REG_EGRESS_DRAIN0_MODE + port*4, 1);
12124
12125         /* disable nig egress interface */
12126         if (!CHIP_IS_E3(bp)) {
12127                 REG_WR(bp, NIG_REG_BMAC0_OUT_EN + port*4, 0);
12128                 REG_WR(bp, NIG_REG_EGRESS_EMAC0_OUT_EN + port*4, 0);
12129         }
12130
12131         /* Stop BigMac rx */
12132         if (!CHIP_IS_E3(bp))
12133                 bnx2x_bmac_rx_disable(bp, port);
12134         else {
12135                 bnx2x_xmac_disable(params);
12136                 bnx2x_umac_disable(params);
12137         }
12138         /* disable emac */
12139         if (!CHIP_IS_E3(bp))
12140                 REG_WR(bp, NIG_REG_NIG_EMAC0_EN + port*4, 0);
12141
12142         msleep(10);
12143         /* The PHY reset is controlled by GPIO 1
12144          * Hold it as vars low
12145          */
12146          /* clear link led */
12147         bnx2x_set_led(params, vars, LED_MODE_OFF, 0);
12148
12149         if (reset_ext_phy) {
12150                 bnx2x_set_mdio_clk(bp, params->chip_id, port);
12151                 for (phy_index = EXT_PHY1; phy_index < params->num_phys;
12152                       phy_index++) {
12153                         if (params->phy[phy_index].link_reset) {
12154                                 bnx2x_set_aer_mmd(params,
12155                                                   &params->phy[phy_index]);
12156                                 params->phy[phy_index].link_reset(
12157                                         &params->phy[phy_index],
12158                                         params);
12159                         }
12160                         if (params->phy[phy_index].flags &
12161                             FLAGS_REARM_LATCH_SIGNAL)
12162                                 clear_latch_ind = 1;
12163                 }
12164         }
12165
12166         if (clear_latch_ind) {
12167                 /* Clear latching indication */
12168                 bnx2x_rearm_latch_signal(bp, port, 0);
12169                 bnx2x_bits_dis(bp, NIG_REG_LATCH_BC_0 + port*4,
12170                                1 << NIG_LATCH_BC_ENABLE_MI_INT);
12171         }
12172         if (params->phy[INT_PHY].link_reset)
12173                 params->phy[INT_PHY].link_reset(
12174                         &params->phy[INT_PHY], params);
12175
12176         /* disable nig ingress interface */
12177         if (!CHIP_IS_E3(bp)) {
12178                 /* reset BigMac */
12179                 REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_2_CLEAR,
12180                        (MISC_REGISTERS_RESET_REG_2_RST_BMAC0 << port));
12181                 REG_WR(bp, NIG_REG_BMAC0_IN_EN + port*4, 0);
12182                 REG_WR(bp, NIG_REG_EMAC0_IN_EN + port*4, 0);
12183         } else {
12184                 u32 xmac_base = (params->port) ? GRCBASE_XMAC1 : GRCBASE_XMAC0;
12185                 bnx2x_set_xumac_nig(params, 0, 0);
12186                 if (REG_RD(bp, MISC_REG_RESET_REG_2) &
12187                     MISC_REGISTERS_RESET_REG_2_XMAC)
12188                         REG_WR(bp, xmac_base + XMAC_REG_CTRL,
12189                                XMAC_CTRL_REG_SOFT_RESET);
12190         }
12191         vars->link_up = 0;
12192         vars->phy_flags = 0;
12193         return 0;
12194 }
12195
12196 /****************************************************************************/
12197 /*                              Common function                             */
12198 /****************************************************************************/
12199 static int bnx2x_8073_common_init_phy(struct bnx2x *bp,
12200                                       u32 shmem_base_path[],
12201                                       u32 shmem2_base_path[], u8 phy_index,
12202                                       u32 chip_id)
12203 {
12204         struct bnx2x_phy phy[PORT_MAX];
12205         struct bnx2x_phy *phy_blk[PORT_MAX];
12206         u16 val;
12207         s8 port = 0;
12208         s8 port_of_path = 0;
12209         u32 swap_val, swap_override;
12210         swap_val = REG_RD(bp,  NIG_REG_PORT_SWAP);
12211         swap_override = REG_RD(bp,  NIG_REG_STRAP_OVERRIDE);
12212         port ^= (swap_val && swap_override);
12213         bnx2x_ext_phy_hw_reset(bp, port);
12214         /* PART1 - Reset both phys */
12215         for (port = PORT_MAX - 1; port >= PORT_0; port--) {
12216                 u32 shmem_base, shmem2_base;
12217                 /* In E2, same phy is using for port0 of the two paths */
12218                 if (CHIP_IS_E1x(bp)) {
12219                         shmem_base = shmem_base_path[0];
12220                         shmem2_base = shmem2_base_path[0];
12221                         port_of_path = port;
12222                 } else {
12223                         shmem_base = shmem_base_path[port];
12224                         shmem2_base = shmem2_base_path[port];
12225                         port_of_path = 0;
12226                 }
12227
12228                 /* Extract the ext phy address for the port */
12229                 if (bnx2x_populate_phy(bp, phy_index, shmem_base, shmem2_base,
12230                                        port_of_path, &phy[port]) !=
12231                     0) {
12232                         DP(NETIF_MSG_LINK, "populate_phy failed\n");
12233                         return -EINVAL;
12234                 }
12235                 /* disable attentions */
12236                 bnx2x_bits_dis(bp, NIG_REG_MASK_INTERRUPT_PORT0 +
12237                                port_of_path*4,
12238                                (NIG_MASK_XGXS0_LINK_STATUS |
12239                                 NIG_MASK_XGXS0_LINK10G |
12240                                 NIG_MASK_SERDES0_LINK_STATUS |
12241                                 NIG_MASK_MI_INT));
12242
12243                 /* Need to take the phy out of low power mode in order
12244                         to write to access its registers */
12245                 bnx2x_set_gpio(bp, MISC_REGISTERS_GPIO_2,
12246                                MISC_REGISTERS_GPIO_OUTPUT_HIGH,
12247                                port);
12248
12249                 /* Reset the phy */
12250                 bnx2x_cl45_write(bp, &phy[port],
12251                                  MDIO_PMA_DEVAD,
12252                                  MDIO_PMA_REG_CTRL,
12253                                  1<<15);
12254         }
12255
12256         /* Add delay of 150ms after reset */
12257         msleep(150);
12258
12259         if (phy[PORT_0].addr & 0x1) {
12260                 phy_blk[PORT_0] = &(phy[PORT_1]);
12261                 phy_blk[PORT_1] = &(phy[PORT_0]);
12262         } else {
12263                 phy_blk[PORT_0] = &(phy[PORT_0]);
12264                 phy_blk[PORT_1] = &(phy[PORT_1]);
12265         }
12266
12267         /* PART2 - Download firmware to both phys */
12268         for (port = PORT_MAX - 1; port >= PORT_0; port--) {
12269                 if (CHIP_IS_E1x(bp))
12270                         port_of_path = port;
12271                 else
12272                         port_of_path = 0;
12273
12274                 DP(NETIF_MSG_LINK, "Loading spirom for phy address 0x%x\n",
12275                            phy_blk[port]->addr);
12276                 if (bnx2x_8073_8727_external_rom_boot(bp, phy_blk[port],
12277                                                       port_of_path))
12278                         return -EINVAL;
12279
12280                 /* Only set bit 10 = 1 (Tx power down) */
12281                 bnx2x_cl45_read(bp, phy_blk[port],
12282                                 MDIO_PMA_DEVAD,
12283                                 MDIO_PMA_REG_TX_POWER_DOWN, &val);
12284
12285                 /* Phase1 of TX_POWER_DOWN reset */
12286                 bnx2x_cl45_write(bp, phy_blk[port],
12287                                  MDIO_PMA_DEVAD,
12288                                  MDIO_PMA_REG_TX_POWER_DOWN,
12289                                  (val | 1<<10));
12290         }
12291
12292         /*
12293          * Toggle Transmitter: Power down and then up with 600ms delay
12294          * between
12295          */
12296         msleep(600);
12297
12298         /* PART3 - complete TX_POWER_DOWN process, and set GPIO2 back to low */
12299         for (port = PORT_MAX - 1; port >= PORT_0; port--) {
12300                 /* Phase2 of POWER_DOWN_RESET */
12301                 /* Release bit 10 (Release Tx power down) */
12302                 bnx2x_cl45_read(bp, phy_blk[port],
12303                                 MDIO_PMA_DEVAD,
12304                                 MDIO_PMA_REG_TX_POWER_DOWN, &val);
12305
12306                 bnx2x_cl45_write(bp, phy_blk[port],
12307                                 MDIO_PMA_DEVAD,
12308                                 MDIO_PMA_REG_TX_POWER_DOWN, (val & (~(1<<10))));
12309                 msleep(15);
12310
12311                 /* Read modify write the SPI-ROM version select register */
12312                 bnx2x_cl45_read(bp, phy_blk[port],
12313                                 MDIO_PMA_DEVAD,
12314                                 MDIO_PMA_REG_EDC_FFE_MAIN, &val);
12315                 bnx2x_cl45_write(bp, phy_blk[port],
12316                                  MDIO_PMA_DEVAD,
12317                                  MDIO_PMA_REG_EDC_FFE_MAIN, (val | (1<<12)));
12318
12319                 /* set GPIO2 back to LOW */
12320                 bnx2x_set_gpio(bp, MISC_REGISTERS_GPIO_2,
12321                                MISC_REGISTERS_GPIO_OUTPUT_LOW, port);
12322         }
12323         return 0;
12324 }
12325 static int bnx2x_8726_common_init_phy(struct bnx2x *bp,
12326                                       u32 shmem_base_path[],
12327                                       u32 shmem2_base_path[], u8 phy_index,
12328                                       u32 chip_id)
12329 {
12330         u32 val;
12331         s8 port;
12332         struct bnx2x_phy phy;
12333         /* Use port1 because of the static port-swap */
12334         /* Enable the module detection interrupt */
12335         val = REG_RD(bp, MISC_REG_GPIO_EVENT_EN);
12336         val |= ((1<<MISC_REGISTERS_GPIO_3)|
12337                 (1<<(MISC_REGISTERS_GPIO_3 + MISC_REGISTERS_GPIO_PORT_SHIFT)));
12338         REG_WR(bp, MISC_REG_GPIO_EVENT_EN, val);
12339
12340         bnx2x_ext_phy_hw_reset(bp, 0);
12341         msleep(5);
12342         for (port = 0; port < PORT_MAX; port++) {
12343                 u32 shmem_base, shmem2_base;
12344
12345                 /* In E2, same phy is using for port0 of the two paths */
12346                 if (CHIP_IS_E1x(bp)) {
12347                         shmem_base = shmem_base_path[0];
12348                         shmem2_base = shmem2_base_path[0];
12349                 } else {
12350                         shmem_base = shmem_base_path[port];
12351                         shmem2_base = shmem2_base_path[port];
12352                 }
12353                 /* Extract the ext phy address for the port */
12354                 if (bnx2x_populate_phy(bp, phy_index, shmem_base, shmem2_base,
12355                                        port, &phy) !=
12356                     0) {
12357                         DP(NETIF_MSG_LINK, "populate phy failed\n");
12358                         return -EINVAL;
12359                 }
12360
12361                 /* Reset phy*/
12362                 bnx2x_cl45_write(bp, &phy,
12363                                  MDIO_PMA_DEVAD, MDIO_PMA_REG_GEN_CTRL, 0x0001);
12364
12365
12366                 /* Set fault module detected LED on */
12367                 bnx2x_set_gpio(bp, MISC_REGISTERS_GPIO_0,
12368                                MISC_REGISTERS_GPIO_HIGH,
12369                                port);
12370         }
12371
12372         return 0;
12373 }
12374 static void bnx2x_get_ext_phy_reset_gpio(struct bnx2x *bp, u32 shmem_base,
12375                                          u8 *io_gpio, u8 *io_port)
12376 {
12377
12378         u32 phy_gpio_reset = REG_RD(bp, shmem_base +
12379                                           offsetof(struct shmem_region,
12380                                 dev_info.port_hw_config[PORT_0].default_cfg));
12381         switch (phy_gpio_reset) {
12382         case PORT_HW_CFG_EXT_PHY_GPIO_RST_GPIO0_P0:
12383                 *io_gpio = 0;
12384                 *io_port = 0;
12385                 break;
12386         case PORT_HW_CFG_EXT_PHY_GPIO_RST_GPIO1_P0:
12387                 *io_gpio = 1;
12388                 *io_port = 0;
12389                 break;
12390         case PORT_HW_CFG_EXT_PHY_GPIO_RST_GPIO2_P0:
12391                 *io_gpio = 2;
12392                 *io_port = 0;
12393                 break;
12394         case PORT_HW_CFG_EXT_PHY_GPIO_RST_GPIO3_P0:
12395                 *io_gpio = 3;
12396                 *io_port = 0;
12397                 break;
12398         case PORT_HW_CFG_EXT_PHY_GPIO_RST_GPIO0_P1:
12399                 *io_gpio = 0;
12400                 *io_port = 1;
12401                 break;
12402         case PORT_HW_CFG_EXT_PHY_GPIO_RST_GPIO1_P1:
12403                 *io_gpio = 1;
12404                 *io_port = 1;
12405                 break;
12406         case PORT_HW_CFG_EXT_PHY_GPIO_RST_GPIO2_P1:
12407                 *io_gpio = 2;
12408                 *io_port = 1;
12409                 break;
12410         case PORT_HW_CFG_EXT_PHY_GPIO_RST_GPIO3_P1:
12411                 *io_gpio = 3;
12412                 *io_port = 1;
12413                 break;
12414         default:
12415                 /* Don't override the io_gpio and io_port */
12416                 break;
12417         }
12418 }
12419
12420 static int bnx2x_8727_common_init_phy(struct bnx2x *bp,
12421                                       u32 shmem_base_path[],
12422                                       u32 shmem2_base_path[], u8 phy_index,
12423                                       u32 chip_id)
12424 {
12425         s8 port, reset_gpio;
12426         u32 swap_val, swap_override;
12427         struct bnx2x_phy phy[PORT_MAX];
12428         struct bnx2x_phy *phy_blk[PORT_MAX];
12429         s8 port_of_path;
12430         swap_val = REG_RD(bp, NIG_REG_PORT_SWAP);
12431         swap_override = REG_RD(bp, NIG_REG_STRAP_OVERRIDE);
12432
12433         reset_gpio = MISC_REGISTERS_GPIO_1;
12434         port = 1;
12435
12436         /*
12437          * Retrieve the reset gpio/port which control the reset.
12438          * Default is GPIO1, PORT1
12439          */
12440         bnx2x_get_ext_phy_reset_gpio(bp, shmem_base_path[0],
12441                                      (u8 *)&reset_gpio, (u8 *)&port);
12442
12443         /* Calculate the port based on port swap */
12444         port ^= (swap_val && swap_override);
12445
12446         /* Initiate PHY reset*/
12447         bnx2x_set_gpio(bp, reset_gpio, MISC_REGISTERS_GPIO_OUTPUT_LOW,
12448                        port);
12449         msleep(1);
12450         bnx2x_set_gpio(bp, reset_gpio, MISC_REGISTERS_GPIO_OUTPUT_HIGH,
12451                        port);
12452
12453         msleep(5);
12454
12455         /* PART1 - Reset both phys */
12456         for (port = PORT_MAX - 1; port >= PORT_0; port--) {
12457                 u32 shmem_base, shmem2_base;
12458
12459                 /* In E2, same phy is using for port0 of the two paths */
12460                 if (CHIP_IS_E1x(bp)) {
12461                         shmem_base = shmem_base_path[0];
12462                         shmem2_base = shmem2_base_path[0];
12463                         port_of_path = port;
12464                 } else {
12465                         shmem_base = shmem_base_path[port];
12466                         shmem2_base = shmem2_base_path[port];
12467                         port_of_path = 0;
12468                 }
12469
12470                 /* Extract the ext phy address for the port */
12471                 if (bnx2x_populate_phy(bp, phy_index, shmem_base, shmem2_base,
12472                                        port_of_path, &phy[port]) !=
12473                                        0) {
12474                         DP(NETIF_MSG_LINK, "populate phy failed\n");
12475                         return -EINVAL;
12476                 }
12477                 /* disable attentions */
12478                 bnx2x_bits_dis(bp, NIG_REG_MASK_INTERRUPT_PORT0 +
12479                                port_of_path*4,
12480                                (NIG_MASK_XGXS0_LINK_STATUS |
12481                                 NIG_MASK_XGXS0_LINK10G |
12482                                 NIG_MASK_SERDES0_LINK_STATUS |
12483                                 NIG_MASK_MI_INT));
12484
12485
12486                 /* Reset the phy */
12487                 bnx2x_cl45_write(bp, &phy[port],
12488                                  MDIO_PMA_DEVAD, MDIO_PMA_REG_CTRL, 1<<15);
12489         }
12490
12491         /* Add delay of 150ms after reset */
12492         msleep(150);
12493         if (phy[PORT_0].addr & 0x1) {
12494                 phy_blk[PORT_0] = &(phy[PORT_1]);
12495                 phy_blk[PORT_1] = &(phy[PORT_0]);
12496         } else {
12497                 phy_blk[PORT_0] = &(phy[PORT_0]);
12498                 phy_blk[PORT_1] = &(phy[PORT_1]);
12499         }
12500         /* PART2 - Download firmware to both phys */
12501         for (port = PORT_MAX - 1; port >= PORT_0; port--) {
12502                 if (CHIP_IS_E1x(bp))
12503                         port_of_path = port;
12504                 else
12505                         port_of_path = 0;
12506                 DP(NETIF_MSG_LINK, "Loading spirom for phy address 0x%x\n",
12507                            phy_blk[port]->addr);
12508                 if (bnx2x_8073_8727_external_rom_boot(bp, phy_blk[port],
12509                                                       port_of_path))
12510                         return -EINVAL;
12511                 /* Disable PHY transmitter output */
12512                 bnx2x_cl45_write(bp, phy_blk[port],
12513                                  MDIO_PMA_DEVAD,
12514                                  MDIO_PMA_REG_TX_DISABLE, 1);
12515
12516         }
12517         return 0;
12518 }
12519
12520 static int bnx2x_84833_common_init_phy(struct bnx2x *bp,
12521                                                 u32 shmem_base_path[],
12522                                                 u32 shmem2_base_path[],
12523                                                 u8 phy_index,
12524                                                 u32 chip_id)
12525 {
12526         u8 reset_gpios;
12527         reset_gpios = bnx2x_84833_get_reset_gpios(bp, shmem_base_path, chip_id);
12528         bnx2x_set_mult_gpio(bp, reset_gpios, MISC_REGISTERS_GPIO_OUTPUT_LOW);
12529         udelay(10);
12530         bnx2x_set_mult_gpio(bp, reset_gpios, MISC_REGISTERS_GPIO_OUTPUT_HIGH);
12531         DP(NETIF_MSG_LINK, "84833 reset pulse on pin values 0x%x\n",
12532                 reset_gpios);
12533         return 0;
12534 }
12535
12536 static int bnx2x_84833_pre_init_phy(struct bnx2x *bp,
12537                                                struct bnx2x_phy *phy)
12538 {
12539         u16 val, cnt;
12540         /* Wait for FW completing its initialization. */
12541         for (cnt = 0; cnt < 1500; cnt++) {
12542                 bnx2x_cl45_read(bp, phy,
12543                                 MDIO_PMA_DEVAD,
12544                                 MDIO_PMA_REG_CTRL, &val);
12545                 if (!(val & (1<<15)))
12546                         break;
12547                 msleep(1);
12548         }
12549         if (cnt >= 1500) {
12550                 DP(NETIF_MSG_LINK, "84833 reset timeout\n");
12551                 return -EINVAL;
12552         }
12553
12554         /* Put the port in super isolate mode. */
12555         bnx2x_cl45_read(bp, phy,
12556                         MDIO_CTL_DEVAD,
12557                         MDIO_84833_TOP_CFG_XGPHY_STRAP1, &val);
12558         val |= MDIO_84833_SUPER_ISOLATE;
12559         bnx2x_cl45_write(bp, phy,
12560                          MDIO_CTL_DEVAD,
12561                          MDIO_84833_TOP_CFG_XGPHY_STRAP1, val);
12562
12563         /* Save spirom version */
12564         bnx2x_save_848xx_spirom_version(phy, bp, PORT_0);
12565         return 0;
12566 }
12567
12568 int bnx2x_pre_init_phy(struct bnx2x *bp,
12569                                   u32 shmem_base,
12570                                   u32 shmem2_base,
12571                                   u32 chip_id)
12572 {
12573         int rc = 0;
12574         struct bnx2x_phy phy;
12575         bnx2x_set_mdio_clk(bp, chip_id, PORT_0);
12576         if (bnx2x_populate_phy(bp, EXT_PHY1, shmem_base, shmem2_base,
12577                                PORT_0, &phy)) {
12578                 DP(NETIF_MSG_LINK, "populate_phy failed\n");
12579                 return -EINVAL;
12580         }
12581         switch (phy.type) {
12582         case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM84833:
12583                 rc = bnx2x_84833_pre_init_phy(bp, &phy);
12584                 break;
12585         default:
12586                 break;
12587         }
12588         return rc;
12589 }
12590
12591 static int bnx2x_ext_phy_common_init(struct bnx2x *bp, u32 shmem_base_path[],
12592                                      u32 shmem2_base_path[], u8 phy_index,
12593                                      u32 ext_phy_type, u32 chip_id)
12594 {
12595         int rc = 0;
12596
12597         switch (ext_phy_type) {
12598         case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8073:
12599                 rc = bnx2x_8073_common_init_phy(bp, shmem_base_path,
12600                                                 shmem2_base_path,
12601                                                 phy_index, chip_id);
12602                 break;
12603         case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8722:
12604         case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8727:
12605         case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8727_NOC:
12606                 rc = bnx2x_8727_common_init_phy(bp, shmem_base_path,
12607                                                 shmem2_base_path,
12608                                                 phy_index, chip_id);
12609                 break;
12610
12611         case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8726:
12612                 /*
12613                  * GPIO1 affects both ports, so there's need to pull
12614                  * it for single port alone
12615                  */
12616                 rc = bnx2x_8726_common_init_phy(bp, shmem_base_path,
12617                                                 shmem2_base_path,
12618                                                 phy_index, chip_id);
12619                 break;
12620         case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM84833:
12621                 /*
12622                  * GPIO3's are linked, and so both need to be toggled
12623                  * to obtain required 2us pulse.
12624                  */
12625                 rc = bnx2x_84833_common_init_phy(bp, shmem_base_path,
12626                                                 shmem2_base_path,
12627                                                 phy_index, chip_id);
12628                 break;
12629         case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_FAILURE:
12630                 rc = -EINVAL;
12631                 break;
12632         default:
12633                 DP(NETIF_MSG_LINK,
12634                            "ext_phy 0x%x common init not required\n",
12635                            ext_phy_type);
12636                 break;
12637         }
12638
12639         if (rc != 0)
12640                 netdev_err(bp->dev,  "Warning: PHY was not initialized,"
12641                                       " Port %d\n",
12642                          0);
12643         return rc;
12644 }
12645
12646 int bnx2x_common_init_phy(struct bnx2x *bp, u32 shmem_base_path[],
12647                           u32 shmem2_base_path[], u32 chip_id)
12648 {
12649         int rc = 0;
12650         u32 phy_ver, val;
12651         u8 phy_index = 0;
12652         u32 ext_phy_type, ext_phy_config;
12653         bnx2x_set_mdio_clk(bp, chip_id, PORT_0);
12654         bnx2x_set_mdio_clk(bp, chip_id, PORT_1);
12655         DP(NETIF_MSG_LINK, "Begin common phy init\n");
12656         if (CHIP_IS_E3(bp)) {
12657                 /* Enable EPIO */
12658                 val = REG_RD(bp, MISC_REG_GEN_PURP_HWG);
12659                 REG_WR(bp, MISC_REG_GEN_PURP_HWG, val | 1);
12660         }
12661         /* Check if common init was already done */
12662         phy_ver = REG_RD(bp, shmem_base_path[0] +
12663                          offsetof(struct shmem_region,
12664                                   port_mb[PORT_0].ext_phy_fw_version));
12665         if (phy_ver) {
12666                 DP(NETIF_MSG_LINK, "Not doing common init; phy ver is 0x%x\n",
12667                                phy_ver);
12668                 return 0;
12669         }
12670
12671         /* Read the ext_phy_type for arbitrary port(0) */
12672         for (phy_index = EXT_PHY1; phy_index < MAX_PHYS;
12673               phy_index++) {
12674                 ext_phy_config = bnx2x_get_ext_phy_config(bp,
12675                                                           shmem_base_path[0],
12676                                                           phy_index, 0);
12677                 ext_phy_type = XGXS_EXT_PHY_TYPE(ext_phy_config);
12678                 rc |= bnx2x_ext_phy_common_init(bp, shmem_base_path,
12679                                                 shmem2_base_path,
12680                                                 phy_index, ext_phy_type,
12681                                                 chip_id);
12682         }
12683         return rc;
12684 }
12685
12686 static void bnx2x_check_over_curr(struct link_params *params,
12687                                   struct link_vars *vars)
12688 {
12689         struct bnx2x *bp = params->bp;
12690         u32 cfg_pin;
12691         u8 port = params->port;
12692         u32 pin_val;
12693
12694         cfg_pin = (REG_RD(bp, params->shmem_base +
12695                           offsetof(struct shmem_region,
12696                                dev_info.port_hw_config[port].e3_cmn_pin_cfg1)) &
12697                    PORT_HW_CFG_E3_OVER_CURRENT_MASK) >>
12698                 PORT_HW_CFG_E3_OVER_CURRENT_SHIFT;
12699
12700         /* Ignore check if no external input PIN available */
12701         if (bnx2x_get_cfg_pin(bp, cfg_pin, &pin_val) != 0)
12702                 return;
12703
12704         if (!pin_val) {
12705                 if ((vars->phy_flags & PHY_OVER_CURRENT_FLAG) == 0) {
12706                         netdev_err(bp->dev, "Error:  Power fault on Port %d has"
12707                                             " been detected and the power to "
12708                                             "that SFP+ module has been removed"
12709                                             " to prevent failure of the card."
12710                                             " Please remove the SFP+ module and"
12711                                             " restart the system to clear this"
12712                                             " error.\n",
12713                          params->port);
12714                         vars->phy_flags |= PHY_OVER_CURRENT_FLAG;
12715                 }
12716         } else
12717                 vars->phy_flags &= ~PHY_OVER_CURRENT_FLAG;
12718 }
12719
12720 static void bnx2x_analyze_link_error(struct link_params *params,
12721                                      struct link_vars *vars, u32 lss_status)
12722 {
12723         struct bnx2x *bp = params->bp;
12724         /* Compare new value with previous value */
12725         u8 led_mode;
12726         u32 half_open_conn = (vars->phy_flags & PHY_HALF_OPEN_CONN_FLAG) > 0;
12727
12728         if ((lss_status ^ half_open_conn) == 0)
12729                 return;
12730
12731         /* If values differ */
12732         DP(NETIF_MSG_LINK, "Link changed:%x %x->%x\n", vars->link_up,
12733                        half_open_conn, lss_status);
12734
12735         /*
12736          * a. Update shmem->link_status accordingly
12737          * b. Update link_vars->link_up
12738          */
12739         if (lss_status) {
12740                 DP(NETIF_MSG_LINK, "Remote Fault detected !!!\n");
12741                 vars->link_status &= ~LINK_STATUS_LINK_UP;
12742                 vars->link_up = 0;
12743                 vars->phy_flags |= PHY_HALF_OPEN_CONN_FLAG;
12744                 /*
12745                  * Set LED mode to off since the PHY doesn't know about these
12746                  * errors
12747                  */
12748                 led_mode = LED_MODE_OFF;
12749         } else {
12750                 DP(NETIF_MSG_LINK, "Remote Fault cleared\n");
12751                 vars->link_status |= LINK_STATUS_LINK_UP;
12752                 vars->link_up = 1;
12753                 vars->phy_flags &= ~PHY_HALF_OPEN_CONN_FLAG;
12754                 led_mode = LED_MODE_OPER;
12755         }
12756         /* Update the LED according to the link state */
12757         bnx2x_set_led(params, vars, led_mode, SPEED_10000);
12758
12759         /* Update link status in the shared memory */
12760         bnx2x_update_mng(params, vars->link_status);
12761
12762         /* C. Trigger General Attention */
12763         vars->periodic_flags |= PERIODIC_FLAGS_LINK_EVENT;
12764         bnx2x_notify_link_changed(bp);
12765 }
12766
12767 /******************************************************************************
12768 * Description:
12769 *       This function checks for half opened connection change indication.
12770 *       When such change occurs, it calls the bnx2x_analyze_link_error
12771 *       to check if Remote Fault is set or cleared. Reception of remote fault
12772 *       status message in the MAC indicates that the peer's MAC has detected
12773 *       a fault, for example, due to break in the TX side of fiber.
12774 *
12775 ******************************************************************************/
12776 static void bnx2x_check_half_open_conn(struct link_params *params,
12777                                        struct link_vars *vars)
12778 {
12779         struct bnx2x *bp = params->bp;
12780         u32 lss_status = 0;
12781         u32 mac_base;
12782         /* In case link status is physically up @ 10G do */
12783         if ((vars->phy_flags & PHY_PHYSICAL_LINK_FLAG) == 0)
12784                 return;
12785
12786         if (CHIP_IS_E3(bp) &&
12787             (REG_RD(bp, MISC_REG_RESET_REG_2) &
12788               (MISC_REGISTERS_RESET_REG_2_XMAC))) {
12789                 /* Check E3 XMAC */
12790                 /*
12791                  * Note that link speed cannot be queried here, since it may be
12792                  * zero while link is down. In case UMAC is active, LSS will
12793                  * simply not be set
12794                  */
12795                 mac_base = (params->port) ? GRCBASE_XMAC1 : GRCBASE_XMAC0;
12796
12797                 /* Clear stick bits (Requires rising edge) */
12798                 REG_WR(bp, mac_base + XMAC_REG_CLEAR_RX_LSS_STATUS, 0);
12799                 REG_WR(bp, mac_base + XMAC_REG_CLEAR_RX_LSS_STATUS,
12800                        XMAC_CLEAR_RX_LSS_STATUS_REG_CLEAR_LOCAL_FAULT_STATUS |
12801                        XMAC_CLEAR_RX_LSS_STATUS_REG_CLEAR_REMOTE_FAULT_STATUS);
12802                 if (REG_RD(bp, mac_base + XMAC_REG_RX_LSS_STATUS))
12803                         lss_status = 1;
12804
12805                 bnx2x_analyze_link_error(params, vars, lss_status);
12806         } else if (REG_RD(bp, MISC_REG_RESET_REG_2) &
12807                    (MISC_REGISTERS_RESET_REG_2_RST_BMAC0 << params->port)) {
12808                 /* Check E1X / E2 BMAC */
12809                 u32 lss_status_reg;
12810                 u32 wb_data[2];
12811                 mac_base = params->port ? NIG_REG_INGRESS_BMAC1_MEM :
12812                         NIG_REG_INGRESS_BMAC0_MEM;
12813                 /*  Read BIGMAC_REGISTER_RX_LSS_STATUS */
12814                 if (CHIP_IS_E2(bp))
12815                         lss_status_reg = BIGMAC2_REGISTER_RX_LSS_STAT;
12816                 else
12817                         lss_status_reg = BIGMAC_REGISTER_RX_LSS_STATUS;
12818
12819                 REG_RD_DMAE(bp, mac_base + lss_status_reg, wb_data, 2);
12820                 lss_status = (wb_data[0] > 0);
12821
12822                 bnx2x_analyze_link_error(params, vars, lss_status);
12823         }
12824 }
12825
12826 void bnx2x_period_func(struct link_params *params, struct link_vars *vars)
12827 {
12828         struct bnx2x *bp = params->bp;
12829         u16 phy_idx;
12830         for (phy_idx = INT_PHY; phy_idx < MAX_PHYS; phy_idx++) {
12831                 if (params->phy[phy_idx].flags & FLAGS_TX_ERROR_CHECK) {
12832                         bnx2x_set_aer_mmd(params, &params->phy[phy_idx]);
12833                         bnx2x_check_half_open_conn(params, vars);
12834                         break;
12835                 }
12836         }
12837
12838         if (CHIP_IS_E3(bp)) {
12839                 struct bnx2x_phy *phy = &params->phy[INT_PHY];
12840                 bnx2x_set_aer_mmd(params, phy);
12841                 bnx2x_check_over_curr(params, vars);
12842                 bnx2x_warpcore_config_runtime(phy, params, vars);
12843         }
12844
12845 }
12846
12847 u8 bnx2x_hw_lock_required(struct bnx2x *bp, u32 shmem_base, u32 shmem2_base)
12848 {
12849         u8 phy_index;
12850         struct bnx2x_phy phy;
12851         for (phy_index = INT_PHY; phy_index < MAX_PHYS;
12852               phy_index++) {
12853                 if (bnx2x_populate_phy(bp, phy_index, shmem_base, shmem2_base,
12854                                        0, &phy) != 0) {
12855                         DP(NETIF_MSG_LINK, "populate phy failed\n");
12856                         return 0;
12857                 }
12858
12859                 if (phy.flags & FLAGS_HW_LOCK_REQUIRED)
12860                         return 1;
12861         }
12862         return 0;
12863 }
12864
12865 u8 bnx2x_fan_failure_det_req(struct bnx2x *bp,
12866                              u32 shmem_base,
12867                              u32 shmem2_base,
12868                              u8 port)
12869 {
12870         u8 phy_index, fan_failure_det_req = 0;
12871         struct bnx2x_phy phy;
12872         for (phy_index = EXT_PHY1; phy_index < MAX_PHYS;
12873               phy_index++) {
12874                 if (bnx2x_populate_phy(bp, phy_index, shmem_base, shmem2_base,
12875                                        port, &phy)
12876                     != 0) {
12877                         DP(NETIF_MSG_LINK, "populate phy failed\n");
12878                         return 0;
12879                 }
12880                 fan_failure_det_req |= (phy.flags &
12881                                         FLAGS_FAN_FAILURE_DET_REQ);
12882         }
12883         return fan_failure_det_req;
12884 }
12885
12886 void bnx2x_hw_reset_phy(struct link_params *params)
12887 {
12888         u8 phy_index;
12889         struct bnx2x *bp = params->bp;
12890         bnx2x_update_mng(params, 0);
12891         bnx2x_bits_dis(bp, NIG_REG_MASK_INTERRUPT_PORT0 + params->port*4,
12892                        (NIG_MASK_XGXS0_LINK_STATUS |
12893                         NIG_MASK_XGXS0_LINK10G |
12894                         NIG_MASK_SERDES0_LINK_STATUS |
12895                         NIG_MASK_MI_INT));
12896
12897         for (phy_index = INT_PHY; phy_index < MAX_PHYS;
12898               phy_index++) {
12899                 if (params->phy[phy_index].hw_reset) {
12900                         params->phy[phy_index].hw_reset(
12901                                 &params->phy[phy_index],
12902                                 params);
12903                         params->phy[phy_index] = phy_null;
12904                 }
12905         }
12906 }
12907
12908 void bnx2x_init_mod_abs_int(struct bnx2x *bp, struct link_vars *vars,
12909                             u32 chip_id, u32 shmem_base, u32 shmem2_base,
12910                             u8 port)
12911 {
12912         u8 gpio_num = 0xff, gpio_port = 0xff, phy_index;
12913         u32 val;
12914         u32 offset, aeu_mask, swap_val, swap_override, sync_offset;
12915         if (CHIP_IS_E3(bp)) {
12916                 if (bnx2x_get_mod_abs_int_cfg(bp, chip_id,
12917                                               shmem_base,
12918                                               port,
12919                                               &gpio_num,
12920                                               &gpio_port) != 0)
12921                         return;
12922         } else {
12923                 struct bnx2x_phy phy;
12924                 for (phy_index = EXT_PHY1; phy_index < MAX_PHYS;
12925                       phy_index++) {
12926                         if (bnx2x_populate_phy(bp, phy_index, shmem_base,
12927                                                shmem2_base, port, &phy)
12928                             != 0) {
12929                                 DP(NETIF_MSG_LINK, "populate phy failed\n");
12930                                 return;
12931                         }
12932                         if (phy.type == PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8726) {
12933                                 gpio_num = MISC_REGISTERS_GPIO_3;
12934                                 gpio_port = port;
12935                                 break;
12936                         }
12937                 }
12938         }
12939
12940         if (gpio_num == 0xff)
12941                 return;
12942
12943         /* Set GPIO3 to trigger SFP+ module insertion/removal */
12944         bnx2x_set_gpio(bp, gpio_num, MISC_REGISTERS_GPIO_INPUT_HI_Z, gpio_port);
12945
12946         swap_val = REG_RD(bp, NIG_REG_PORT_SWAP);
12947         swap_override = REG_RD(bp, NIG_REG_STRAP_OVERRIDE);
12948         gpio_port ^= (swap_val && swap_override);
12949
12950         vars->aeu_int_mask = AEU_INPUTS_ATTN_BITS_GPIO0_FUNCTION_0 <<
12951                 (gpio_num + (gpio_port << 2));
12952
12953         sync_offset = shmem_base +
12954                 offsetof(struct shmem_region,
12955                          dev_info.port_hw_config[port].aeu_int_mask);
12956         REG_WR(bp, sync_offset, vars->aeu_int_mask);
12957
12958         DP(NETIF_MSG_LINK, "Setting MOD_ABS (GPIO%d_P%d) AEU to 0x%x\n",
12959                        gpio_num, gpio_port, vars->aeu_int_mask);
12960
12961         if (port == 0)
12962                 offset = MISC_REG_AEU_ENABLE1_FUNC_0_OUT_0;
12963         else
12964                 offset = MISC_REG_AEU_ENABLE1_FUNC_1_OUT_0;
12965
12966         /* Open appropriate AEU for interrupts */
12967         aeu_mask = REG_RD(bp, offset);
12968         aeu_mask |= vars->aeu_int_mask;
12969         REG_WR(bp, offset, aeu_mask);
12970
12971         /* Enable the GPIO to trigger interrupt */
12972         val = REG_RD(bp, MISC_REG_GPIO_EVENT_EN);
12973         val |= 1 << (gpio_num + (gpio_port << 2));
12974         REG_WR(bp, MISC_REG_GPIO_EVENT_EN, val);
12975 }