drivers/net/ethernet/broadcom/bnxt/bnxt.c

   1 /* Broadcom NetXtreme-C/E network driver.
   2  *
   3  * Copyright (c) 2014-2016 Broadcom Corporation
   4  * Copyright (c) 2016-2017 Broadcom Limited
   5  *
   6  * This program is free software; you can redistribute it and/or modify
   7  * it under the terms of the GNU General Public License as published by
   8  * the Free Software Foundation.
   9  */
  10
  11 #include <linux/module.h>
  12
  13 #include <linux/stringify.h>
  14 #include <linux/kernel.h>
  15 #include <linux/timer.h>
  16 #include <linux/errno.h>
  17 #include <linux/ioport.h>
  18 #include <linux/slab.h>
  19 #include <linux/vmalloc.h>
  20 #include <linux/interrupt.h>
  21 #include <linux/pci.h>
  22 #include <linux/netdevice.h>
  23 #include <linux/etherdevice.h>
  24 #include <linux/skbuff.h>
  25 #include <linux/dma-mapping.h>
  26 #include <linux/bitops.h>
  27 #include <linux/io.h>
  28 #include <linux/irq.h>
  29 #include <linux/delay.h>
  30 #include <asm/byteorder.h>
  31 #include <asm/page.h>
  32 #include <linux/time.h>
  33 #include <linux/mii.h>
  34 #include <linux/if.h>
  35 #include <linux/if_vlan.h>
  36 #include <linux/rtc.h>
  37 #include <linux/bpf.h>
  38 #include <net/ip.h>
  39 #include <net/tcp.h>
  40 #include <net/udp.h>
  41 #include <net/checksum.h>
  42 #include <net/ip6_checksum.h>
  43 #include <net/udp_tunnel.h>
  44 #include <linux/workqueue.h>
  45 #include <linux/prefetch.h>
  46 #include <linux/cache.h>
  47 #include <linux/log2.h>
  48 #include <linux/aer.h>
  49 #include <linux/bitmap.h>
  50 #include <linux/cpu_rmap.h>
  51
  52 #include "bnxt_hsi.h"
  53 #include "bnxt.h"
  54 #include "bnxt_ulp.h"
  55 #include "bnxt_sriov.h"
  56 #include "bnxt_ethtool.h"
  57 #include "bnxt_dcb.h"
  58 #include "bnxt_xdp.h"
  59
  60 #define BNXT_TX_TIMEOUT         (5 * HZ)
  61
  62 static const char version[] =
  63         "Broadcom NetXtreme-C/E driver " DRV_MODULE_NAME " v" DRV_MODULE_VERSION "\n";
  64
  65 MODULE_LICENSE("GPL");
  66 MODULE_DESCRIPTION("Broadcom BCM573xx network driver");
  67 MODULE_VERSION(DRV_MODULE_VERSION);
  68
  69 #define BNXT_RX_OFFSET (NET_SKB_PAD + NET_IP_ALIGN)
  70 #define BNXT_RX_DMA_OFFSET NET_SKB_PAD
  71 #define BNXT_RX_COPY_THRESH 256
  72
  73 #define BNXT_TX_PUSH_THRESH 164
  74
  75 enum board_idx {
  76         BCM57301,
  77         BCM57302,
  78         BCM57304,
  79         BCM57417_NPAR,
  80         BCM58700,
  81         BCM57311,
  82         BCM57312,
  83         BCM57402,
  84         BCM57404,
  85         BCM57406,
  86         BCM57402_NPAR,
  87         BCM57407,
  88         BCM57412,
  89         BCM57414,
  90         BCM57416,
  91         BCM57417,
  92         BCM57412_NPAR,
  93         BCM57314,
  94         BCM57417_SFP,
  95         BCM57416_SFP,
  96         BCM57404_NPAR,
  97         BCM57406_NPAR,
  98         BCM57407_SFP,
  99         BCM57407_NPAR,
 100         BCM57414_NPAR,
 101         BCM57416_NPAR,
 102         BCM57452,
 103         BCM57454,
 104         NETXTREME_E_VF,
 105         NETXTREME_C_VF,
 106 };
 107
 108 /* indexed by enum above */
 109 static const struct {
 110         char *name;
 111 } board_info[] = {
 112         { "Broadcom BCM57301 NetXtreme-C 10Gb Ethernet" },
 113         { "Broadcom BCM57302 NetXtreme-C 10Gb/25Gb Ethernet" },
 114         { "Broadcom BCM57304 NetXtreme-C 10Gb/25Gb/40Gb/50Gb Ethernet" },
 115         { "Broadcom BCM57417 NetXtreme-E Ethernet Partition" },
 116         { "Broadcom BCM58700 Nitro 1Gb/2.5Gb/10Gb Ethernet" },
 117         { "Broadcom BCM57311 NetXtreme-C 10Gb Ethernet" },
 118         { "Broadcom BCM57312 NetXtreme-C 10Gb/25Gb Ethernet" },
 119         { "Broadcom BCM57402 NetXtreme-E 10Gb Ethernet" },
 120         { "Broadcom BCM57404 NetXtreme-E 10Gb/25Gb Ethernet" },
 121         { "Broadcom BCM57406 NetXtreme-E 10GBase-T Ethernet" },
 122         { "Broadcom BCM57402 NetXtreme-E Ethernet Partition" },
 123         { "Broadcom BCM57407 NetXtreme-E 10GBase-T Ethernet" },
 124         { "Broadcom BCM57412 NetXtreme-E 10Gb Ethernet" },
 125         { "Broadcom BCM57414 NetXtreme-E 10Gb/25Gb Ethernet" },
 126         { "Broadcom BCM57416 NetXtreme-E 10GBase-T Ethernet" },
 127         { "Broadcom BCM57417 NetXtreme-E 10GBase-T Ethernet" },
 128         { "Broadcom BCM57412 NetXtreme-E Ethernet Partition" },
 129         { "Broadcom BCM57314 NetXtreme-C 10Gb/25Gb/40Gb/50Gb Ethernet" },
 130         { "Broadcom BCM57417 NetXtreme-E 10Gb/25Gb Ethernet" },
 131         { "Broadcom BCM57416 NetXtreme-E 10Gb Ethernet" },
 132         { "Broadcom BCM57404 NetXtreme-E Ethernet Partition" },
 133         { "Broadcom BCM57406 NetXtreme-E Ethernet Partition" },
 134         { "Broadcom BCM57407 NetXtreme-E 25Gb Ethernet" },
 135         { "Broadcom BCM57407 NetXtreme-E Ethernet Partition" },
 136         { "Broadcom BCM57414 NetXtreme-E Ethernet Partition" },
 137         { "Broadcom BCM57416 NetXtreme-E Ethernet Partition" },
 138         { "Broadcom BCM57452 NetXtreme-E 10Gb/25Gb/40Gb/50Gb Ethernet" },
 139         { "Broadcom BCM57454 NetXtreme-E 10Gb/25Gb/40Gb/50Gb/100Gb Ethernet" },
 140         { "Broadcom NetXtreme-E Ethernet Virtual Function" },
 141         { "Broadcom NetXtreme-C Ethernet Virtual Function" },
 142 };
 143
 144 static const struct pci_device_id bnxt_pci_tbl[] = {
 145         { PCI_VDEVICE(BROADCOM, 0x16c0), .driver_data = BCM57417_NPAR },
 146         { PCI_VDEVICE(BROADCOM, 0x16c8), .driver_data = BCM57301 },
 147         { PCI_VDEVICE(BROADCOM, 0x16c9), .driver_data = BCM57302 },
 148         { PCI_VDEVICE(BROADCOM, 0x16ca), .driver_data = BCM57304 },
 149         { PCI_VDEVICE(BROADCOM, 0x16cc), .driver_data = BCM57417_NPAR },
 150         { PCI_VDEVICE(BROADCOM, 0x16cd), .driver_data = BCM58700 },
 151         { PCI_VDEVICE(BROADCOM, 0x16ce), .driver_data = BCM57311 },
 152         { PCI_VDEVICE(BROADCOM, 0x16cf), .driver_data = BCM57312 },
 153         { PCI_VDEVICE(BROADCOM, 0x16d0), .driver_data = BCM57402 },
 154         { PCI_VDEVICE(BROADCOM, 0x16d1), .driver_data = BCM57404 },
 155         { PCI_VDEVICE(BROADCOM, 0x16d2), .driver_data = BCM57406 },
 156         { PCI_VDEVICE(BROADCOM, 0x16d4), .driver_data = BCM57402_NPAR },
 157         { PCI_VDEVICE(BROADCOM, 0x16d5), .driver_data = BCM57407 },
 158         { PCI_VDEVICE(BROADCOM, 0x16d6), .driver_data = BCM57412 },
 159         { PCI_VDEVICE(BROADCOM, 0x16d7), .driver_data = BCM57414 },
 160         { PCI_VDEVICE(BROADCOM, 0x16d8), .driver_data = BCM57416 },
 161         { PCI_VDEVICE(BROADCOM, 0x16d9), .driver_data = BCM57417 },
 162         { PCI_VDEVICE(BROADCOM, 0x16de), .driver_data = BCM57412_NPAR },
 163         { PCI_VDEVICE(BROADCOM, 0x16df), .driver_data = BCM57314 },
 164         { PCI_VDEVICE(BROADCOM, 0x16e2), .driver_data = BCM57417_SFP },
 165         { PCI_VDEVICE(BROADCOM, 0x16e3), .driver_data = BCM57416_SFP },
 166         { PCI_VDEVICE(BROADCOM, 0x16e7), .driver_data = BCM57404_NPAR },
 167         { PCI_VDEVICE(BROADCOM, 0x16e8), .driver_data = BCM57406_NPAR },
 168         { PCI_VDEVICE(BROADCOM, 0x16e9), .driver_data = BCM57407_SFP },
 169         { PCI_VDEVICE(BROADCOM, 0x16ea), .driver_data = BCM57407_NPAR },
 170         { PCI_VDEVICE(BROADCOM, 0x16eb), .driver_data = BCM57412_NPAR },
 171         { PCI_VDEVICE(BROADCOM, 0x16ec), .driver_data = BCM57414_NPAR },
 172         { PCI_VDEVICE(BROADCOM, 0x16ed), .driver_data = BCM57414_NPAR },
 173         { PCI_VDEVICE(BROADCOM, 0x16ee), .driver_data = BCM57416_NPAR },
 174         { PCI_VDEVICE(BROADCOM, 0x16ef), .driver_data = BCM57416_NPAR },
 175         { PCI_VDEVICE(BROADCOM, 0x16f1), .driver_data = BCM57452 },
 176         { PCI_VDEVICE(BROADCOM, 0x1614), .driver_data = BCM57454 },
 177 #ifdef CONFIG_BNXT_SRIOV
 178         { PCI_VDEVICE(BROADCOM, 0x16c1), .driver_data = NETXTREME_E_VF },
 179         { PCI_VDEVICE(BROADCOM, 0x16cb), .driver_data = NETXTREME_C_VF },
 180         { PCI_VDEVICE(BROADCOM, 0x16d3), .driver_data = NETXTREME_E_VF },
 181         { PCI_VDEVICE(BROADCOM, 0x16dc), .driver_data = NETXTREME_E_VF },
 182         { PCI_VDEVICE(BROADCOM, 0x16e1), .driver_data = NETXTREME_C_VF },
 183         { PCI_VDEVICE(BROADCOM, 0x16e5), .driver_data = NETXTREME_C_VF },
 184 #endif
 185         { 0 }
 186 };
 187
 188 MODULE_DEVICE_TABLE(pci, bnxt_pci_tbl);
 189
 190 static const u16 bnxt_vf_req_snif[] = {
 191         HWRM_FUNC_CFG,
 192         HWRM_PORT_PHY_QCFG,
 193         HWRM_CFA_L2_FILTER_ALLOC,
 194 };
 195
 196 static const u16 bnxt_async_events_arr[] = {
 197         ASYNC_EVENT_CMPL_EVENT_ID_LINK_STATUS_CHANGE,
 198         ASYNC_EVENT_CMPL_EVENT_ID_PF_DRVR_UNLOAD,
 199         ASYNC_EVENT_CMPL_EVENT_ID_PORT_CONN_NOT_ALLOWED,
 200         ASYNC_EVENT_CMPL_EVENT_ID_VF_CFG_CHANGE,
 201         ASYNC_EVENT_CMPL_EVENT_ID_LINK_SPEED_CFG_CHANGE,
 202 };
 203
 204 static bool bnxt_vf_pciid(enum board_idx idx)
 205 {
 206         return (idx == NETXTREME_C_VF || idx == NETXTREME_E_VF);
 207 }
 208
 209 #define DB_CP_REARM_FLAGS       (DB_KEY_CP | DB_IDX_VALID)
 210 #define DB_CP_FLAGS             (DB_KEY_CP | DB_IDX_VALID | DB_IRQ_DIS)
 211 #define DB_CP_IRQ_DIS_FLAGS     (DB_KEY_CP | DB_IRQ_DIS)
 212
 213 #define BNXT_CP_DB_REARM(db, raw_cons)                                  \
 214                 writel(DB_CP_REARM_FLAGS | RING_CMP(raw_cons), db)
 215
 216 #define BNXT_CP_DB(db, raw_cons)                                        \
 217                 writel(DB_CP_FLAGS | RING_CMP(raw_cons), db)
 218
 219 #define BNXT_CP_DB_IRQ_DIS(db)                                          \
 220                 writel(DB_CP_IRQ_DIS_FLAGS, db)
 221
 222 const u16 bnxt_lhint_arr[] = {
 223         TX_BD_FLAGS_LHINT_512_AND_SMALLER,
 224         TX_BD_FLAGS_LHINT_512_TO_1023,
 225         TX_BD_FLAGS_LHINT_1024_TO_2047,
 226         TX_BD_FLAGS_LHINT_1024_TO_2047,
 227         TX_BD_FLAGS_LHINT_2048_AND_LARGER,
 228         TX_BD_FLAGS_LHINT_2048_AND_LARGER,
 229         TX_BD_FLAGS_LHINT_2048_AND_LARGER,
 230         TX_BD_FLAGS_LHINT_2048_AND_LARGER,
 231         TX_BD_FLAGS_LHINT_2048_AND_LARGER,
 232         TX_BD_FLAGS_LHINT_2048_AND_LARGER,
 233         TX_BD_FLAGS_LHINT_2048_AND_LARGER,
 234         TX_BD_FLAGS_LHINT_2048_AND_LARGER,
 235         TX_BD_FLAGS_LHINT_2048_AND_LARGER,
 236         TX_BD_FLAGS_LHINT_2048_AND_LARGER,
 237         TX_BD_FLAGS_LHINT_2048_AND_LARGER,
 238         TX_BD_FLAGS_LHINT_2048_AND_LARGER,
 239         TX_BD_FLAGS_LHINT_2048_AND_LARGER,
 240         TX_BD_FLAGS_LHINT_2048_AND_LARGER,
 241         TX_BD_FLAGS_LHINT_2048_AND_LARGER,
 242 };
 243
 244 static netdev_tx_t bnxt_start_xmit(struct sk_buff *skb, struct net_device *dev)
 245 {
 246         struct bnxt *bp = netdev_priv(dev);
 247         struct tx_bd *txbd;
 248         struct tx_bd_ext *txbd1;
 249         struct netdev_queue *txq;
 250         int i;
 251         dma_addr_t mapping;
 252         unsigned int length, pad = 0;
 253         u32 len, free_size, vlan_tag_flags, cfa_action, flags;
 254         u16 prod, last_frag;
 255         struct pci_dev *pdev = bp->pdev;
 256         struct bnxt_tx_ring_info *txr;
 257         struct bnxt_sw_tx_bd *tx_buf;
 258
 259         i = skb_get_queue_mapping(skb);
 260         if (unlikely(i >= bp->tx_nr_rings)) {
 261                 dev_kfree_skb_any(skb);
 262                 return NETDEV_TX_OK;
 263         }
 264
 265         txq = netdev_get_tx_queue(dev, i);
 266         txr = &bp->tx_ring[bp->tx_ring_map[i]];
 267         prod = txr->tx_prod;
 268
 269         free_size = bnxt_tx_avail(bp, txr);
 270         if (unlikely(free_size < skb_shinfo(skb)->nr_frags + 2)) {
 271                 netif_tx_stop_queue(txq);
 272                 return NETDEV_TX_BUSY;
 273         }
 274
 275         length = skb->len;
 276         len = skb_headlen(skb);
 277         last_frag = skb_shinfo(skb)->nr_frags;
 278
 279         txbd = &txr->tx_desc_ring[TX_RING(prod)][TX_IDX(prod)];
 280
 281         txbd->tx_bd_opaque = prod;
 282
 283         tx_buf = &txr->tx_buf_ring[prod];
 284         tx_buf->skb = skb;
 285         tx_buf->nr_frags = last_frag;
 286
 287         vlan_tag_flags = 0;
 288         cfa_action = 0;
 289         if (skb_vlan_tag_present(skb)) {
 290                 vlan_tag_flags = TX_BD_CFA_META_KEY_VLAN |
 291                                  skb_vlan_tag_get(skb);
 292                 /* Currently supports 8021Q, 8021AD vlan offloads
 293                  * QINQ1, QINQ2, QINQ3 vlan headers are deprecated
 294                  */
 295                 if (skb->vlan_proto == htons(ETH_P_8021Q))
 296                         vlan_tag_flags |= 1 << TX_BD_CFA_META_TPID_SHIFT;
 297         }
 298
 299         if (free_size == bp->tx_ring_size && length <= bp->tx_push_thresh) {
 300                 struct tx_push_buffer *tx_push_buf = txr->tx_push;
 301                 struct tx_push_bd *tx_push = &tx_push_buf->push_bd;
 302                 struct tx_bd_ext *tx_push1 = &tx_push->txbd2;
 303                 void *pdata = tx_push_buf->data;
 304                 u64 *end;
 305                 int j, push_len;
 306
 307                 /* Set COAL_NOW to be ready quickly for the next push */
 308                 tx_push->tx_bd_len_flags_type =
 309                         cpu_to_le32((length << TX_BD_LEN_SHIFT) |
 310                                         TX_BD_TYPE_LONG_TX_BD |
 311                                         TX_BD_FLAGS_LHINT_512_AND_SMALLER |
 312                                         TX_BD_FLAGS_COAL_NOW |
 313                                         TX_BD_FLAGS_PACKET_END |
 314                                         (2 << TX_BD_FLAGS_BD_CNT_SHIFT));
 315
 316                 if (skb->ip_summed == CHECKSUM_PARTIAL)
 317                         tx_push1->tx_bd_hsize_lflags =
 318                                         cpu_to_le32(TX_BD_FLAGS_TCP_UDP_CHKSUM);
 319                 else
 320                         tx_push1->tx_bd_hsize_lflags = 0;
 321
 322                 tx_push1->tx_bd_cfa_meta = cpu_to_le32(vlan_tag_flags);
 323                 tx_push1->tx_bd_cfa_action = cpu_to_le32(cfa_action);
 324
 325                 end = pdata + length;
 326                 end = PTR_ALIGN(end, 8) - 1;
 327                 *end = 0;
 328
 329                 skb_copy_from_linear_data(skb, pdata, len);
 330                 pdata += len;
 331                 for (j = 0; j < last_frag; j++) {
 332                         skb_frag_t *frag = &skb_shinfo(skb)->frags[j];
 333                         void *fptr;
 334
 335                         fptr = skb_frag_address_safe(frag);
 336                         if (!fptr)
 337                                 goto normal_tx;
 338
 339                         memcpy(pdata, fptr, skb_frag_size(frag));
 340                         pdata += skb_frag_size(frag);
 341                 }
 342
 343                 txbd->tx_bd_len_flags_type = tx_push->tx_bd_len_flags_type;
 344                 txbd->tx_bd_haddr = txr->data_mapping;
 345                 prod = NEXT_TX(prod);
 346                 txbd = &txr->tx_desc_ring[TX_RING(prod)][TX_IDX(prod)];
 347                 memcpy(txbd, tx_push1, sizeof(*txbd));
 348                 prod = NEXT_TX(prod);
 349                 tx_push->doorbell =
 350                         cpu_to_le32(DB_KEY_TX_PUSH | DB_LONG_TX_PUSH | prod);
 351                 txr->tx_prod = prod;
 352
 353                 tx_buf->is_push = 1;
 354                 netdev_tx_sent_queue(txq, skb->len);
 355                 wmb();  /* Sync is_push and byte queue before pushing data */
 356
 357                 push_len = (length + sizeof(*tx_push) + 7) / 8;
 358                 if (push_len > 16) {
 359                         __iowrite64_copy(txr->tx_doorbell, tx_push_buf, 16);
 360                         __iowrite32_copy(txr->tx_doorbell + 4, tx_push_buf + 1,
 361                                          (push_len - 16) << 1);
 362                 } else {
 363                         __iowrite64_copy(txr->tx_doorbell, tx_push_buf,
 364                                          push_len);
 365                 }
 366
 367                 goto tx_done;
 368         }
 369
 370 normal_tx:
 371         if (length < BNXT_MIN_PKT_SIZE) {
 372                 pad = BNXT_MIN_PKT_SIZE - length;
 373                 if (skb_pad(skb, pad)) {
 374                         /* SKB already freed. */
 375                         tx_buf->skb = NULL;
 376                         return NETDEV_TX_OK;
 377                 }
 378                 length = BNXT_MIN_PKT_SIZE;
 379         }
 380
 381         mapping = dma_map_single(&pdev->dev, skb->data, len, DMA_TO_DEVICE);
 382
 383         if (unlikely(dma_mapping_error(&pdev->dev, mapping))) {
 384                 dev_kfree_skb_any(skb);
 385                 tx_buf->skb = NULL;
 386                 return NETDEV_TX_OK;
 387         }
 388
 389         dma_unmap_addr_set(tx_buf, mapping, mapping);
 390         flags = (len << TX_BD_LEN_SHIFT) | TX_BD_TYPE_LONG_TX_BD |
 391                 ((last_frag + 2) << TX_BD_FLAGS_BD_CNT_SHIFT);
 392
 393         txbd->tx_bd_haddr = cpu_to_le64(mapping);
 394
 395         prod = NEXT_TX(prod);
 396         txbd1 = (struct tx_bd_ext *)
 397                 &txr->tx_desc_ring[TX_RING(prod)][TX_IDX(prod)];
 398
 399         txbd1->tx_bd_hsize_lflags = 0;
 400         if (skb_is_gso(skb)) {
 401                 u32 hdr_len;
 402
 403                 if (skb->encapsulation)
 404                         hdr_len = skb_inner_network_offset(skb) +
 405                                 skb_inner_network_header_len(skb) +
 406                                 inner_tcp_hdrlen(skb);
 407                 else
 408                         hdr_len = skb_transport_offset(skb) +
 409                                 tcp_hdrlen(skb);
 410
 411                 txbd1->tx_bd_hsize_lflags = cpu_to_le32(TX_BD_FLAGS_LSO |
 412                                         TX_BD_FLAGS_T_IPID |
 413                                         (hdr_len << (TX_BD_HSIZE_SHIFT - 1)));
 414                 length = skb_shinfo(skb)->gso_size;
 415                 txbd1->tx_bd_mss = cpu_to_le32(length);
 416                 length += hdr_len;
 417         } else if (skb->ip_summed == CHECKSUM_PARTIAL) {
 418                 txbd1->tx_bd_hsize_lflags =
 419                         cpu_to_le32(TX_BD_FLAGS_TCP_UDP_CHKSUM);
 420                 txbd1->tx_bd_mss = 0;
 421         }
 422
 423         length >>= 9;
 424         flags |= bnxt_lhint_arr[length];
 425         txbd->tx_bd_len_flags_type = cpu_to_le32(flags);
 426
 427         txbd1->tx_bd_cfa_meta = cpu_to_le32(vlan_tag_flags);
 428         txbd1->tx_bd_cfa_action = cpu_to_le32(cfa_action);
 429         for (i = 0; i < last_frag; i++) {
 430                 skb_frag_t *frag = &skb_shinfo(skb)->frags[i];
 431
 432                 prod = NEXT_TX(prod);
 433                 txbd = &txr->tx_desc_ring[TX_RING(prod)][TX_IDX(prod)];
 434
 435                 len = skb_frag_size(frag);
 436                 mapping = skb_frag_dma_map(&pdev->dev, frag, 0, len,
 437                                            DMA_TO_DEVICE);
 438
 439                 if (unlikely(dma_mapping_error(&pdev->dev, mapping)))
 440                         goto tx_dma_error;
 441
 442                 tx_buf = &txr->tx_buf_ring[prod];
 443                 dma_unmap_addr_set(tx_buf, mapping, mapping);
 444
 445                 txbd->tx_bd_haddr = cpu_to_le64(mapping);
 446
 447                 flags = len << TX_BD_LEN_SHIFT;
 448                 txbd->tx_bd_len_flags_type = cpu_to_le32(flags);
 449         }
 450
 451         flags &= ~TX_BD_LEN;
 452         txbd->tx_bd_len_flags_type =
 453                 cpu_to_le32(((len + pad) << TX_BD_LEN_SHIFT) | flags |
 454                             TX_BD_FLAGS_PACKET_END);
 455
 456         netdev_tx_sent_queue(txq, skb->len);
 457
 458         /* Sync BD data before updating doorbell */
 459         wmb();
 460
 461         prod = NEXT_TX(prod);
 462         txr->tx_prod = prod;
 463
 464         writel(DB_KEY_TX | prod, txr->tx_doorbell);
 465         writel(DB_KEY_TX | prod, txr->tx_doorbell);
 466
 467 tx_done:
 468
 469         mmiowb();
 470
 471         if (unlikely(bnxt_tx_avail(bp, txr) <= MAX_SKB_FRAGS + 1)) {
 472                 netif_tx_stop_queue(txq);
 473
 474                 /* netif_tx_stop_queue() must be done before checking
 475                  * tx index in bnxt_tx_avail() below, because in
 476                  * bnxt_tx_int(), we update tx index before checking for
 477                  * netif_tx_queue_stopped().
 478                  */
 479                 smp_mb();
 480                 if (bnxt_tx_avail(bp, txr) > bp->tx_wake_thresh)
 481                         netif_tx_wake_queue(txq);
 482         }
 483         return NETDEV_TX_OK;
 484
 485 tx_dma_error:
 486         last_frag = i;
 487
 488         /* start back at beginning and unmap skb */
 489         prod = txr->tx_prod;
 490         tx_buf = &txr->tx_buf_ring[prod];
 491         tx_buf->skb = NULL;
 492         dma_unmap_single(&pdev->dev, dma_unmap_addr(tx_buf, mapping),
 493                          skb_headlen(skb), PCI_DMA_TODEVICE);
 494         prod = NEXT_TX(prod);
 495
 496         /* unmap remaining mapped pages */
 497         for (i = 0; i < last_frag; i++) {
 498                 prod = NEXT_TX(prod);
 499                 tx_buf = &txr->tx_buf_ring[prod];
 500                 dma_unmap_page(&pdev->dev, dma_unmap_addr(tx_buf, mapping),
 501                                skb_frag_size(&skb_shinfo(skb)->frags[i]),
 502                                PCI_DMA_TODEVICE);
 503         }
 504
 505         dev_kfree_skb_any(skb);
 506         return NETDEV_TX_OK;
 507 }
 508
 509 static void bnxt_tx_int(struct bnxt *bp, struct bnxt_napi *bnapi, int nr_pkts)
 510 {
 511         struct bnxt_tx_ring_info *txr = bnapi->tx_ring;
 512         struct netdev_queue *txq = netdev_get_tx_queue(bp->dev, txr->txq_index);
 513         u16 cons = txr->tx_cons;
 514         struct pci_dev *pdev = bp->pdev;
 515         int i;
 516         unsigned int tx_bytes = 0;
 517
 518         for (i = 0; i < nr_pkts; i++) {
 519                 struct bnxt_sw_tx_bd *tx_buf;
 520                 struct sk_buff *skb;
 521                 int j, last;
 522
 523                 tx_buf = &txr->tx_buf_ring[cons];
 524                 cons = NEXT_TX(cons);
 525                 skb = tx_buf->skb;
 526                 tx_buf->skb = NULL;
 527
 528                 if (tx_buf->is_push) {
 529                         tx_buf->is_push = 0;
 530                         goto next_tx_int;
 531                 }
 532
 533                 dma_unmap_single(&pdev->dev, dma_unmap_addr(tx_buf, mapping),
 534                                  skb_headlen(skb), PCI_DMA_TODEVICE);
 535                 last = tx_buf->nr_frags;
 536
 537                 for (j = 0; j < last; j++) {
 538                         cons = NEXT_TX(cons);
 539                         tx_buf = &txr->tx_buf_ring[cons];
 540                         dma_unmap_page(
 541                                 &pdev->dev,
 542                                 dma_unmap_addr(tx_buf, mapping),
 543                                 skb_frag_size(&skb_shinfo(skb)->frags[j]),
 544                                 PCI_DMA_TODEVICE);
 545                 }
 546
 547 next_tx_int:
 548                 cons = NEXT_TX(cons);
 549
 550                 tx_bytes += skb->len;
 551                 dev_kfree_skb_any(skb);
 552         }
 553
 554         netdev_tx_completed_queue(txq, nr_pkts, tx_bytes);
 555         txr->tx_cons = cons;
 556
 557         /* Need to make the tx_cons update visible to bnxt_start_xmit()
 558          * before checking for netif_tx_queue_stopped().  Without the
 559          * memory barrier, there is a small possibility that bnxt_start_xmit()
 560          * will miss it and cause the queue to be stopped forever.
 561          */
 562         smp_mb();
 563
 564         if (unlikely(netif_tx_queue_stopped(txq)) &&
 565             (bnxt_tx_avail(bp, txr) > bp->tx_wake_thresh)) {
 566                 __netif_tx_lock(txq, smp_processor_id());
 567                 if (netif_tx_queue_stopped(txq) &&
 568                     bnxt_tx_avail(bp, txr) > bp->tx_wake_thresh &&
 569                     txr->dev_state != BNXT_DEV_STATE_CLOSING)
 570                         netif_tx_wake_queue(txq);
 571                 __netif_tx_unlock(txq);
 572         }
 573 }
 574
 575 static struct page *__bnxt_alloc_rx_page(struct bnxt *bp, dma_addr_t *mapping,
 576                                          gfp_t gfp)
 577 {
 578         struct device *dev = &bp->pdev->dev;
 579         struct page *page;
 580
 581         page = alloc_page(gfp);
 582         if (!page)
 583                 return NULL;
 584
 585         *mapping = dma_map_page(dev, page, 0, PAGE_SIZE, bp->rx_dir);
 586         if (dma_mapping_error(dev, *mapping)) {
 587                 __free_page(page);
 588                 return NULL;
 589         }
 590         *mapping += bp->rx_dma_offset;
 591         return page;
 592 }
 593
 594 static inline u8 *__bnxt_alloc_rx_data(struct bnxt *bp, dma_addr_t *mapping,
 595                                        gfp_t gfp)
 596 {
 597         u8 *data;
 598         struct pci_dev *pdev = bp->pdev;
 599
 600         data = kmalloc(bp->rx_buf_size, gfp);
 601         if (!data)
 602                 return NULL;
 603
 604         *mapping = dma_map_single(&pdev->dev, data + bp->rx_dma_offset,
 605                                   bp->rx_buf_use_size, bp->rx_dir);
 606
 607         if (dma_mapping_error(&pdev->dev, *mapping)) {
 608                 kfree(data);
 609                 data = NULL;
 610         }
 611         return data;
 612 }
 613
 614 int bnxt_alloc_rx_data(struct bnxt *bp, struct bnxt_rx_ring_info *rxr,
 615                        u16 prod, gfp_t gfp)
 616 {
 617         struct rx_bd *rxbd = &rxr->rx_desc_ring[RX_RING(prod)][RX_IDX(prod)];
 618         struct bnxt_sw_rx_bd *rx_buf = &rxr->rx_buf_ring[prod];
 619         dma_addr_t mapping;
 620
 621         if (BNXT_RX_PAGE_MODE(bp)) {
 622                 struct page *page = __bnxt_alloc_rx_page(bp, &mapping, gfp);
 623
 624                 if (!page)
 625                         return -ENOMEM;
 626
 627                 rx_buf->data = page;
 628                 rx_buf->data_ptr = page_address(page) + bp->rx_offset;
 629         } else {
 630                 u8 *data = __bnxt_alloc_rx_data(bp, &mapping, gfp);
 631
 632                 if (!data)
 633                         return -ENOMEM;
 634
 635                 rx_buf->data = data;
 636                 rx_buf->data_ptr = data + bp->rx_offset;
 637         }
 638         rx_buf->mapping = mapping;
 639
 640         rxbd->rx_bd_haddr = cpu_to_le64(mapping);
 641         return 0;
 642 }
 643
 644 void bnxt_reuse_rx_data(struct bnxt_rx_ring_info *rxr, u16 cons, void *data)
 645 {
 646         u16 prod = rxr->rx_prod;
 647         struct bnxt_sw_rx_bd *cons_rx_buf, *prod_rx_buf;
 648         struct rx_bd *cons_bd, *prod_bd;
 649
 650         prod_rx_buf = &rxr->rx_buf_ring[prod];
 651         cons_rx_buf = &rxr->rx_buf_ring[cons];
 652
 653         prod_rx_buf->data = data;
 654         prod_rx_buf->data_ptr = cons_rx_buf->data_ptr;
 655
 656         prod_rx_buf->mapping = cons_rx_buf->mapping;
 657
 658         prod_bd = &rxr->rx_desc_ring[RX_RING(prod)][RX_IDX(prod)];
 659         cons_bd = &rxr->rx_desc_ring[RX_RING(cons)][RX_IDX(cons)];
 660
 661         prod_bd->rx_bd_haddr = cons_bd->rx_bd_haddr;
 662 }
 663
 664 static inline u16 bnxt_find_next_agg_idx(struct bnxt_rx_ring_info *rxr, u16 idx)
 665 {
 666         u16 next, max = rxr->rx_agg_bmap_size;
 667
 668         next = find_next_zero_bit(rxr->rx_agg_bmap, max, idx);
 669         if (next >= max)
 670                 next = find_first_zero_bit(rxr->rx_agg_bmap, max);
 671         return next;
 672 }
 673
 674 static inline int bnxt_alloc_rx_page(struct bnxt *bp,
 675                                      struct bnxt_rx_ring_info *rxr,
 676                                      u16 prod, gfp_t gfp)
 677 {
 678         struct rx_bd *rxbd =
 679                 &rxr->rx_agg_desc_ring[RX_RING(prod)][RX_IDX(prod)];
 680         struct bnxt_sw_rx_agg_bd *rx_agg_buf;
 681         struct pci_dev *pdev = bp->pdev;
 682         struct page *page;
 683         dma_addr_t mapping;
 684         u16 sw_prod = rxr->rx_sw_agg_prod;
 685         unsigned int offset = 0;
 686
 687         if (PAGE_SIZE > BNXT_RX_PAGE_SIZE) {
 688                 page = rxr->rx_page;
 689                 if (!page) {
 690                         page = alloc_page(gfp);
 691                         if (!page)
 692                                 return -ENOMEM;
 693                         rxr->rx_page = page;
 694                         rxr->rx_page_offset = 0;
 695                 }
 696                 offset = rxr->rx_page_offset;
 697                 rxr->rx_page_offset += BNXT_RX_PAGE_SIZE;
 698                 if (rxr->rx_page_offset == PAGE_SIZE)
 699                         rxr->rx_page = NULL;
 700                 else
 701                         get_page(page);
 702         } else {
 703                 page = alloc_page(gfp);
 704                 if (!page)
 705                         return -ENOMEM;
 706         }
 707
 708         mapping = dma_map_page(&pdev->dev, page, offset, BNXT_RX_PAGE_SIZE,
 709                                PCI_DMA_FROMDEVICE);
 710         if (dma_mapping_error(&pdev->dev, mapping)) {
 711                 __free_page(page);
 712                 return -EIO;
 713         }
 714
 715         if (unlikely(test_bit(sw_prod, rxr->rx_agg_bmap)))
 716                 sw_prod = bnxt_find_next_agg_idx(rxr, sw_prod);
 717
 718         __set_bit(sw_prod, rxr->rx_agg_bmap);
 719         rx_agg_buf = &rxr->rx_agg_ring[sw_prod];
 720         rxr->rx_sw_agg_prod = NEXT_RX_AGG(sw_prod);
 721
 722         rx_agg_buf->page = page;
 723         rx_agg_buf->offset = offset;
 724         rx_agg_buf->mapping = mapping;
 725         rxbd->rx_bd_haddr = cpu_to_le64(mapping);
 726         rxbd->rx_bd_opaque = sw_prod;
 727         return 0;
 728 }
 729
 730 static void bnxt_reuse_rx_agg_bufs(struct bnxt_napi *bnapi, u16 cp_cons,
 731                                    u32 agg_bufs)
 732 {
 733         struct bnxt *bp = bnapi->bp;
 734         struct bnxt_cp_ring_info *cpr = &bnapi->cp_ring;
 735         struct bnxt_rx_ring_info *rxr = bnapi->rx_ring;
 736         u16 prod = rxr->rx_agg_prod;
 737         u16 sw_prod = rxr->rx_sw_agg_prod;
 738         u32 i;
 739
 740         for (i = 0; i < agg_bufs; i++) {
 741                 u16 cons;
 742                 struct rx_agg_cmp *agg;
 743                 struct bnxt_sw_rx_agg_bd *cons_rx_buf, *prod_rx_buf;
 744                 struct rx_bd *prod_bd;
 745                 struct page *page;
 746
 747                 agg = (struct rx_agg_cmp *)
 748                         &cpr->cp_desc_ring[CP_RING(cp_cons)][CP_IDX(cp_cons)];
 749                 cons = agg->rx_agg_cmp_opaque;
 750                 __clear_bit(cons, rxr->rx_agg_bmap);
 751
 752                 if (unlikely(test_bit(sw_prod, rxr->rx_agg_bmap)))
 753                         sw_prod = bnxt_find_next_agg_idx(rxr, sw_prod);
 754
 755                 __set_bit(sw_prod, rxr->rx_agg_bmap);
 756                 prod_rx_buf = &rxr->rx_agg_ring[sw_prod];
 757                 cons_rx_buf = &rxr->rx_agg_ring[cons];
 758
 759                 /* It is possible for sw_prod to be equal to cons, so
 760                  * set cons_rx_buf->page to NULL first.
 761                  */
 762                 page = cons_rx_buf->page;
 763                 cons_rx_buf->page = NULL;
 764                 prod_rx_buf->page = page;
 765                 prod_rx_buf->offset = cons_rx_buf->offset;
 766
 767                 prod_rx_buf->mapping = cons_rx_buf->mapping;
 768
 769                 prod_bd = &rxr->rx_agg_desc_ring[RX_RING(prod)][RX_IDX(prod)];
 770
 771                 prod_bd->rx_bd_haddr = cpu_to_le64(cons_rx_buf->mapping);
 772                 prod_bd->rx_bd_opaque = sw_prod;
 773
 774                 prod = NEXT_RX_AGG(prod);
 775                 sw_prod = NEXT_RX_AGG(sw_prod);
 776                 cp_cons = NEXT_CMP(cp_cons);
 777         }
 778         rxr->rx_agg_prod = prod;
 779         rxr->rx_sw_agg_prod = sw_prod;
 780 }
 781
 782 static struct sk_buff *bnxt_rx_page_skb(struct bnxt *bp,
 783                                         struct bnxt_rx_ring_info *rxr,
 784                                         u16 cons, void *data, u8 *data_ptr,
 785                                         dma_addr_t dma_addr,
 786                                         unsigned int offset_and_len)
 787 {
 788         unsigned int payload = offset_and_len >> 16;
 789         unsigned int len = offset_and_len & 0xffff;
 790         struct skb_frag_struct *frag;
 791         struct page *page = data;
 792         u16 prod = rxr->rx_prod;
 793         struct sk_buff *skb;
 794         int off, err;
 795
 796         err = bnxt_alloc_rx_data(bp, rxr, prod, GFP_ATOMIC);
 797         if (unlikely(err)) {
 798                 bnxt_reuse_rx_data(rxr, cons, data);
 799                 return NULL;
 800         }
 801         dma_addr -= bp->rx_dma_offset;
 802         dma_unmap_page(&bp->pdev->dev, dma_addr, PAGE_SIZE, bp->rx_dir);
 803
 804         if (unlikely(!payload))
 805                 payload = eth_get_headlen(data_ptr, len);
 806
 807         skb = napi_alloc_skb(&rxr->bnapi->napi, payload);
 808         if (!skb) {
 809                 __free_page(page);
 810                 return NULL;
 811         }
 812
 813         off = (void *)data_ptr - page_address(page);
 814         skb_add_rx_frag(skb, 0, page, off, len, PAGE_SIZE);
 815         memcpy(skb->data - NET_IP_ALIGN, data_ptr - NET_IP_ALIGN,
 816                payload + NET_IP_ALIGN);
 817
 818         frag = &skb_shinfo(skb)->frags[0];
 819         skb_frag_size_sub(frag, payload);
 820         frag->page_offset += payload;
 821         skb->data_len -= payload;
 822         skb->tail += payload;
 823
 824         return skb;
 825 }
 826
 827 static struct sk_buff *bnxt_rx_skb(struct bnxt *bp,
 828                                    struct bnxt_rx_ring_info *rxr, u16 cons,
 829                                    void *data, u8 *data_ptr,
 830                                    dma_addr_t dma_addr,
 831                                    unsigned int offset_and_len)
 832 {
 833         u16 prod = rxr->rx_prod;
 834         struct sk_buff *skb;
 835         int err;
 836
 837         err = bnxt_alloc_rx_data(bp, rxr, prod, GFP_ATOMIC);
 838         if (unlikely(err)) {
 839                 bnxt_reuse_rx_data(rxr, cons, data);
 840                 return NULL;
 841         }
 842
 843         skb = build_skb(data, 0);
 844         dma_unmap_single(&bp->pdev->dev, dma_addr, bp->rx_buf_use_size,
 845                          bp->rx_dir);
 846         if (!skb) {
 847                 kfree(data);
 848                 return NULL;
 849         }
 850
 851         skb_reserve(skb, bp->rx_offset);
 852         skb_put(skb, offset_and_len & 0xffff);
 853         return skb;
 854 }
 855
 856 static struct sk_buff *bnxt_rx_pages(struct bnxt *bp, struct bnxt_napi *bnapi,
 857                                      struct sk_buff *skb, u16 cp_cons,
 858                                      u32 agg_bufs)
 859 {
 860         struct pci_dev *pdev = bp->pdev;
 861         struct bnxt_cp_ring_info *cpr = &bnapi->cp_ring;
 862         struct bnxt_rx_ring_info *rxr = bnapi->rx_ring;
 863         u16 prod = rxr->rx_agg_prod;
 864         u32 i;
 865
 866         for (i = 0; i < agg_bufs; i++) {
 867                 u16 cons, frag_len;
 868                 struct rx_agg_cmp *agg;
 869                 struct bnxt_sw_rx_agg_bd *cons_rx_buf;
 870                 struct page *page;
 871                 dma_addr_t mapping;
 872
 873                 agg = (struct rx_agg_cmp *)
 874                         &cpr->cp_desc_ring[CP_RING(cp_cons)][CP_IDX(cp_cons)];
 875                 cons = agg->rx_agg_cmp_opaque;
 876                 frag_len = (le32_to_cpu(agg->rx_agg_cmp_len_flags_type) &
 877                             RX_AGG_CMP_LEN) >> RX_AGG_CMP_LEN_SHIFT;
 878
 879                 cons_rx_buf = &rxr->rx_agg_ring[cons];
 880                 skb_fill_page_desc(skb, i, cons_rx_buf->page,
 881                                    cons_rx_buf->offset, frag_len);
 882                 __clear_bit(cons, rxr->rx_agg_bmap);
 883
 884                 /* It is possible for bnxt_alloc_rx_page() to allocate
 885                  * a sw_prod index that equals the cons index, so we
 886                  * need to clear the cons entry now.
 887                  */
 888                 mapping = cons_rx_buf->mapping;
 889                 page = cons_rx_buf->page;
 890                 cons_rx_buf->page = NULL;
 891
 892                 if (bnxt_alloc_rx_page(bp, rxr, prod, GFP_ATOMIC) != 0) {
 893                         struct skb_shared_info *shinfo;
 894                         unsigned int nr_frags;
 895
 896                         shinfo = skb_shinfo(skb);
 897                         nr_frags = --shinfo->nr_frags;
 898                         __skb_frag_set_page(&shinfo->frags[nr_frags], NULL);
 899
 900                         dev_kfree_skb(skb);
 901
 902                         cons_rx_buf->page = page;
 903
 904                         /* Update prod since possibly some pages have been
 905                          * allocated already.
 906                          */
 907                         rxr->rx_agg_prod = prod;
 908                         bnxt_reuse_rx_agg_bufs(bnapi, cp_cons, agg_bufs - i);
 909                         return NULL;
 910                 }
 911
 912                 dma_unmap_page(&pdev->dev, mapping, BNXT_RX_PAGE_SIZE,
 913                                PCI_DMA_FROMDEVICE);
 914
 915                 skb->data_len += frag_len;
 916                 skb->len += frag_len;
 917                 skb->truesize += PAGE_SIZE;
 918
 919                 prod = NEXT_RX_AGG(prod);
 920                 cp_cons = NEXT_CMP(cp_cons);
 921         }
 922         rxr->rx_agg_prod = prod;
 923         return skb;
 924 }
 925
 926 static int bnxt_agg_bufs_valid(struct bnxt *bp, struct bnxt_cp_ring_info *cpr,
 927                                u8 agg_bufs, u32 *raw_cons)
 928 {
 929         u16 last;
 930         struct rx_agg_cmp *agg;
 931
 932         *raw_cons = ADV_RAW_CMP(*raw_cons, agg_bufs);
 933         last = RING_CMP(*raw_cons);
 934         agg = (struct rx_agg_cmp *)
 935                 &cpr->cp_desc_ring[CP_RING(last)][CP_IDX(last)];
 936         return RX_AGG_CMP_VALID(agg, *raw_cons);
 937 }
 938
 939 static inline struct sk_buff *bnxt_copy_skb(struct bnxt_napi *bnapi, u8 *data,
 940                                             unsigned int len,
 941                                             dma_addr_t mapping)
 942 {
 943         struct bnxt *bp = bnapi->bp;
 944         struct pci_dev *pdev = bp->pdev;
 945         struct sk_buff *skb;
 946
 947         skb = napi_alloc_skb(&bnapi->napi, len);
 948         if (!skb)
 949                 return NULL;
 950
 951         dma_sync_single_for_cpu(&pdev->dev, mapping, bp->rx_copy_thresh,
 952                                 bp->rx_dir);
 953
 954         memcpy(skb->data - NET_IP_ALIGN, data - NET_IP_ALIGN,
 955                len + NET_IP_ALIGN);
 956
 957         dma_sync_single_for_device(&pdev->dev, mapping, bp->rx_copy_thresh,
 958                                    bp->rx_dir);
 959
 960         skb_put(skb, len);
 961         return skb;
 962 }
 963
 964 static int bnxt_discard_rx(struct bnxt *bp, struct bnxt_napi *bnapi,
 965                            u32 *raw_cons, void *cmp)
 966 {
 967         struct bnxt_cp_ring_info *cpr = &bnapi->cp_ring;
 968         struct rx_cmp *rxcmp = cmp;
 969         u32 tmp_raw_cons = *raw_cons;
 970         u8 cmp_type, agg_bufs = 0;
 971
 972         cmp_type = RX_CMP_TYPE(rxcmp);
 973
 974         if (cmp_type == CMP_TYPE_RX_L2_CMP) {
 975                 agg_bufs = (le32_to_cpu(rxcmp->rx_cmp_misc_v1) &
 976                             RX_CMP_AGG_BUFS) >>
 977                            RX_CMP_AGG_BUFS_SHIFT;
 978         } else if (cmp_type == CMP_TYPE_RX_L2_TPA_END_CMP) {
 979                 struct rx_tpa_end_cmp *tpa_end = cmp;
 980
 981                 agg_bufs = (le32_to_cpu(tpa_end->rx_tpa_end_cmp_misc_v1) &
 982                             RX_TPA_END_CMP_AGG_BUFS) >>
 983                            RX_TPA_END_CMP_AGG_BUFS_SHIFT;
 984         }
 985
 986         if (agg_bufs) {
 987                 if (!bnxt_agg_bufs_valid(bp, cpr, agg_bufs, &tmp_raw_cons))
 988                         return -EBUSY;
 989         }
 990         *raw_cons = tmp_raw_cons;
 991         return 0;
 992 }
 993
 994 static void bnxt_sched_reset(struct bnxt *bp, struct bnxt_rx_ring_info *rxr)
 995 {
 996         if (!rxr->bnapi->in_reset) {
 997                 rxr->bnapi->in_reset = true;
 998                 set_bit(BNXT_RESET_TASK_SP_EVENT, &bp->sp_event);
 999                 schedule_work(&bp->sp_task);
1000         }
1001         rxr->rx_next_cons = 0xffff;
1002 }
1003
1004 static void bnxt_tpa_start(struct bnxt *bp, struct bnxt_rx_ring_info *rxr,
1005                            struct rx_tpa_start_cmp *tpa_start,
1006                            struct rx_tpa_start_cmp_ext *tpa_start1)
1007 {
1008         u8 agg_id = TPA_START_AGG_ID(tpa_start);
1009         u16 cons, prod;
1010         struct bnxt_tpa_info *tpa_info;
1011         struct bnxt_sw_rx_bd *cons_rx_buf, *prod_rx_buf;
1012         struct rx_bd *prod_bd;
1013         dma_addr_t mapping;
1014
1015         cons = tpa_start->rx_tpa_start_cmp_opaque;
1016         prod = rxr->rx_prod;
1017         cons_rx_buf = &rxr->rx_buf_ring[cons];
1018         prod_rx_buf = &rxr->rx_buf_ring[prod];
1019         tpa_info = &rxr->rx_tpa[agg_id];
1020
1021         if (unlikely(cons != rxr->rx_next_cons)) {
1022                 bnxt_sched_reset(bp, rxr);
1023                 return;
1024         }
1025
1026         prod_rx_buf->data = tpa_info->data;
1027         prod_rx_buf->data_ptr = tpa_info->data_ptr;
1028
1029         mapping = tpa_info->mapping;
1030         prod_rx_buf->mapping = mapping;
1031
1032         prod_bd = &rxr->rx_desc_ring[RX_RING(prod)][RX_IDX(prod)];
1033
1034         prod_bd->rx_bd_haddr = cpu_to_le64(mapping);
1035
1036         tpa_info->data = cons_rx_buf->data;
1037         tpa_info->data_ptr = cons_rx_buf->data_ptr;
1038         cons_rx_buf->data = NULL;
1039         tpa_info->mapping = cons_rx_buf->mapping;
1040
1041         tpa_info->len =
1042                 le32_to_cpu(tpa_start->rx_tpa_start_cmp_len_flags_type) >>
1043                                 RX_TPA_START_CMP_LEN_SHIFT;
1044         if (likely(TPA_START_HASH_VALID(tpa_start))) {
1045                 u32 hash_type = TPA_START_HASH_TYPE(tpa_start);
1046
1047                 tpa_info->hash_type = PKT_HASH_TYPE_L4;
1048                 tpa_info->gso_type = SKB_GSO_TCPV4;
1049                 /* RSS profiles 1 and 3 with extract code 0 for inner 4-tuple */
1050                 if (hash_type == 3)
1051                         tpa_info->gso_type = SKB_GSO_TCPV6;
1052                 tpa_info->rss_hash =
1053                         le32_to_cpu(tpa_start->rx_tpa_start_cmp_rss_hash);
1054         } else {
1055                 tpa_info->hash_type = PKT_HASH_TYPE_NONE;
1056                 tpa_info->gso_type = 0;
1057                 if (netif_msg_rx_err(bp))
1058                         netdev_warn(bp->dev, "TPA packet without valid hash\n");
1059         }
1060         tpa_info->flags2 = le32_to_cpu(tpa_start1->rx_tpa_start_cmp_flags2);
1061         tpa_info->metadata = le32_to_cpu(tpa_start1->rx_tpa_start_cmp_metadata);
1062         tpa_info->hdr_info = le32_to_cpu(tpa_start1->rx_tpa_start_cmp_hdr_info);
1063
1064         rxr->rx_prod = NEXT_RX(prod);
1065         cons = NEXT_RX(cons);
1066         rxr->rx_next_cons = NEXT_RX(cons);
1067         cons_rx_buf = &rxr->rx_buf_ring[cons];
1068
1069         bnxt_reuse_rx_data(rxr, cons, cons_rx_buf->data);
1070         rxr->rx_prod = NEXT_RX(rxr->rx_prod);
1071         cons_rx_buf->data = NULL;
1072 }
1073
1074 static void bnxt_abort_tpa(struct bnxt *bp, struct bnxt_napi *bnapi,
1075                            u16 cp_cons, u32 agg_bufs)
1076 {
1077         if (agg_bufs)
1078                 bnxt_reuse_rx_agg_bufs(bnapi, cp_cons, agg_bufs);
1079 }
1080
1081 static struct sk_buff *bnxt_gro_func_5731x(struct bnxt_tpa_info *tpa_info,
1082                                            int payload_off, int tcp_ts,
1083                                            struct sk_buff *skb)
1084 {
1085 #ifdef CONFIG_INET
1086         struct tcphdr *th;
1087         int len, nw_off;
1088         u16 outer_ip_off, inner_ip_off, inner_mac_off;
1089         u32 hdr_info = tpa_info->hdr_info;
1090         bool loopback = false;
1091
1092         inner_ip_off = BNXT_TPA_INNER_L3_OFF(hdr_info);
1093         inner_mac_off = BNXT_TPA_INNER_L2_OFF(hdr_info);
1094         outer_ip_off = BNXT_TPA_OUTER_L3_OFF(hdr_info);
1095
1096         /* If the packet is an internal loopback packet, the offsets will
1097          * have an extra 4 bytes.
1098          */
1099         if (inner_mac_off == 4) {
1100                 loopback = true;
1101         } else if (inner_mac_off > 4) {
1102                 __be16 proto = *((__be16 *)(skb->data + inner_ip_off -
1103                                             ETH_HLEN - 2));
1104
1105                 /* We only support inner iPv4/ipv6.  If we don't see the
1106                  * correct protocol ID, it must be a loopback packet where
1107                  * the offsets are off by 4.
1108                  */
1109                 if (proto != htons(ETH_P_IP) && proto != htons(ETH_P_IPV6))
1110                         loopback = true;
1111         }
1112         if (loopback) {
1113                 /* internal loopback packet, subtract all offsets by 4 */
1114                 inner_ip_off -= 4;
1115                 inner_mac_off -= 4;
1116                 outer_ip_off -= 4;
1117         }
1118
1119         nw_off = inner_ip_off - ETH_HLEN;
1120         skb_set_network_header(skb, nw_off);
1121         if (tpa_info->flags2 & RX_TPA_START_CMP_FLAGS2_IP_TYPE) {
1122                 struct ipv6hdr *iph = ipv6_hdr(skb);
1123
1124                 skb_set_transport_header(skb, nw_off + sizeof(struct ipv6hdr));
1125                 len = skb->len - skb_transport_offset(skb);
1126                 th = tcp_hdr(skb);
1127                 th->check = ~tcp_v6_check(len, &iph->saddr, &iph->daddr, 0);
1128         } else {
1129                 struct iphdr *iph = ip_hdr(skb);
1130
1131                 skb_set_transport_header(skb, nw_off + sizeof(struct iphdr));
1132                 len = skb->len - skb_transport_offset(skb);
1133                 th = tcp_hdr(skb);
1134                 th->check = ~tcp_v4_check(len, iph->saddr, iph->daddr, 0);
1135         }
1136
1137         if (inner_mac_off) { /* tunnel */
1138                 struct udphdr *uh = NULL;
1139                 __be16 proto = *((__be16 *)(skb->data + outer_ip_off -
1140                                             ETH_HLEN - 2));
1141
1142                 if (proto == htons(ETH_P_IP)) {
1143                         struct iphdr *iph = (struct iphdr *)skb->data;
1144
1145                         if (iph->protocol == IPPROTO_UDP)
1146                                 uh = (struct udphdr *)(iph + 1);
1147                 } else {
1148                         struct ipv6hdr *iph = (struct ipv6hdr *)skb->data;
1149
1150                         if (iph->nexthdr == IPPROTO_UDP)
1151                                 uh = (struct udphdr *)(iph + 1);
1152                 }
1153                 if (uh) {
1154                         if (uh->check)
1155                                 skb_shinfo(skb)->gso_type |=
1156                                         SKB_GSO_UDP_TUNNEL_CSUM;
1157                         else
1158                                 skb_shinfo(skb)->gso_type |= SKB_GSO_UDP_TUNNEL;
1159                 }
1160         }
1161 #endif
1162         return skb;
1163 }
1164
1165 #define BNXT_IPV4_HDR_SIZE      (sizeof(struct iphdr) + sizeof(struct tcphdr))
1166 #define BNXT_IPV6_HDR_SIZE      (sizeof(struct ipv6hdr) + sizeof(struct tcphdr))
1167
1168 static struct sk_buff *bnxt_gro_func_5730x(struct bnxt_tpa_info *tpa_info,
1169                                            int payload_off, int tcp_ts,
1170                                            struct sk_buff *skb)
1171 {
1172 #ifdef CONFIG_INET
1173         struct tcphdr *th;
1174         int len, nw_off, tcp_opt_len = 0;
1175
1176         if (tcp_ts)
1177                 tcp_opt_len = 12;
1178
1179         if (tpa_info->gso_type == SKB_GSO_TCPV4) {
1180                 struct iphdr *iph;
1181
1182                 nw_off = payload_off - BNXT_IPV4_HDR_SIZE - tcp_opt_len -
1183                          ETH_HLEN;
1184                 skb_set_network_header(skb, nw_off);
1185                 iph = ip_hdr(skb);
1186                 skb_set_transport_header(skb, nw_off + sizeof(struct iphdr));
1187                 len = skb->len - skb_transport_offset(skb);
1188                 th = tcp_hdr(skb);
1189                 th->check = ~tcp_v4_check(len, iph->saddr, iph->daddr, 0);
1190         } else if (tpa_info->gso_type == SKB_GSO_TCPV6) {
1191                 struct ipv6hdr *iph;
1192
1193                 nw_off = payload_off - BNXT_IPV6_HDR_SIZE - tcp_opt_len -
1194                          ETH_HLEN;
1195                 skb_set_network_header(skb, nw_off);
1196                 iph = ipv6_hdr(skb);
1197                 skb_set_transport_header(skb, nw_off + sizeof(struct ipv6hdr));
1198                 len = skb->len - skb_transport_offset(skb);
1199                 th = tcp_hdr(skb);
1200                 th->check = ~tcp_v6_check(len, &iph->saddr, &iph->daddr, 0);
1201         } else {
1202                 dev_kfree_skb_any(skb);
1203                 return NULL;
1204         }
1205
1206         if (nw_off) { /* tunnel */
1207                 struct udphdr *uh = NULL;
1208
1209                 if (skb->protocol == htons(ETH_P_IP)) {
1210                         struct iphdr *iph = (struct iphdr *)skb->data;
1211
1212                         if (iph->protocol == IPPROTO_UDP)
1213                                 uh = (struct udphdr *)(iph + 1);
1214                 } else {
1215                         struct ipv6hdr *iph = (struct ipv6hdr *)skb->data;
1216
1217                         if (iph->nexthdr == IPPROTO_UDP)
1218                                 uh = (struct udphdr *)(iph + 1);
1219                 }
1220                 if (uh) {
1221                         if (uh->check)
1222                                 skb_shinfo(skb)->gso_type |=
1223                                         SKB_GSO_UDP_TUNNEL_CSUM;
1224                         else
1225                                 skb_shinfo(skb)->gso_type |= SKB_GSO_UDP_TUNNEL;
1226                 }
1227         }
1228 #endif
1229         return skb;
1230 }
1231
1232 static inline struct sk_buff *bnxt_gro_skb(struct bnxt *bp,
1233                                            struct bnxt_tpa_info *tpa_info,
1234                                            struct rx_tpa_end_cmp *tpa_end,
1235                                            struct rx_tpa_end_cmp_ext *tpa_end1,
1236                                            struct sk_buff *skb)
1237 {
1238 #ifdef CONFIG_INET
1239         int payload_off;
1240         u16 segs;
1241
1242         segs = TPA_END_TPA_SEGS(tpa_end);
1243         if (segs == 1)
1244                 return skb;
1245
1246         NAPI_GRO_CB(skb)->count = segs;
1247         skb_shinfo(skb)->gso_size =
1248                 le32_to_cpu(tpa_end1->rx_tpa_end_cmp_seg_len);
1249         skb_shinfo(skb)->gso_type = tpa_info->gso_type;
1250         payload_off = (le32_to_cpu(tpa_end->rx_tpa_end_cmp_misc_v1) &
1251                        RX_TPA_END_CMP_PAYLOAD_OFFSET) >>
1252                       RX_TPA_END_CMP_PAYLOAD_OFFSET_SHIFT;
1253         skb = bp->gro_func(tpa_info, payload_off, TPA_END_GRO_TS(tpa_end), skb);
1254         if (likely(skb))
1255                 tcp_gro_complete(skb);
1256 #endif
1257         return skb;
1258 }
1259
1260 static inline struct sk_buff *bnxt_tpa_end(struct bnxt *bp,
1261                                            struct bnxt_napi *bnapi,
1262                                            u32 *raw_cons,
1263                                            struct rx_tpa_end_cmp *tpa_end,
1264                                            struct rx_tpa_end_cmp_ext *tpa_end1,
1265                                            u8 *event)
1266 {
1267         struct bnxt_cp_ring_info *cpr = &bnapi->cp_ring;
1268         struct bnxt_rx_ring_info *rxr = bnapi->rx_ring;
1269         u8 agg_id = TPA_END_AGG_ID(tpa_end);
1270         u8 *data_ptr, agg_bufs;
1271         u16 cp_cons = RING_CMP(*raw_cons);
1272         unsigned int len;
1273         struct bnxt_tpa_info *tpa_info;
1274         dma_addr_t mapping;
1275         struct sk_buff *skb;
1276         void *data;
1277
1278         if (unlikely(bnapi->in_reset)) {
1279                 int rc = bnxt_discard_rx(bp, bnapi, raw_cons, tpa_end);
1280
1281                 if (rc < 0)
1282                         return ERR_PTR(-EBUSY);
1283                 return NULL;
1284         }
1285
1286         tpa_info = &rxr->rx_tpa[agg_id];
1287         data = tpa_info->data;
1288         data_ptr = tpa_info->data_ptr;
1289         prefetch(data_ptr);
1290         len = tpa_info->len;
1291         mapping = tpa_info->mapping;
1292
1293         agg_bufs = (le32_to_cpu(tpa_end->rx_tpa_end_cmp_misc_v1) &
1294                     RX_TPA_END_CMP_AGG_BUFS) >> RX_TPA_END_CMP_AGG_BUFS_SHIFT;
1295
1296         if (agg_bufs) {
1297                 if (!bnxt_agg_bufs_valid(bp, cpr, agg_bufs, raw_cons))
1298                         return ERR_PTR(-EBUSY);
1299
1300                 *event |= BNXT_AGG_EVENT;
1301                 cp_cons = NEXT_CMP(cp_cons);
1302         }
1303
1304         if (unlikely(agg_bufs > MAX_SKB_FRAGS)) {
1305                 bnxt_abort_tpa(bp, bnapi, cp_cons, agg_bufs);
1306                 netdev_warn(bp->dev, "TPA frags %d exceeded MAX_SKB_FRAGS %d\n",
1307                             agg_bufs, (int)MAX_SKB_FRAGS);
1308                 return NULL;
1309         }
1310
1311         if (len <= bp->rx_copy_thresh) {
1312                 skb = bnxt_copy_skb(bnapi, data_ptr, len, mapping);
1313                 if (!skb) {
1314                         bnxt_abort_tpa(bp, bnapi, cp_cons, agg_bufs);
1315                         return NULL;
1316                 }
1317         } else {
1318                 u8 *new_data;
1319                 dma_addr_t new_mapping;
1320
1321                 new_data = __bnxt_alloc_rx_data(bp, &new_mapping, GFP_ATOMIC);
1322                 if (!new_data) {
1323                         bnxt_abort_tpa(bp, bnapi, cp_cons, agg_bufs);
1324                         return NULL;
1325                 }
1326
1327                 tpa_info->data = new_data;
1328                 tpa_info->data_ptr = new_data + bp->rx_offset;
1329                 tpa_info->mapping = new_mapping;
1330
1331                 skb = build_skb(data, 0);
1332                 dma_unmap_single(&bp->pdev->dev, mapping, bp->rx_buf_use_size,
1333                                  bp->rx_dir);
1334
1335                 if (!skb) {
1336                         kfree(data);
1337                         bnxt_abort_tpa(bp, bnapi, cp_cons, agg_bufs);
1338                         return NULL;
1339                 }
1340                 skb_reserve(skb, bp->rx_offset);
1341                 skb_put(skb, len);
1342         }
1343
1344         if (agg_bufs) {
1345                 skb = bnxt_rx_pages(bp, bnapi, skb, cp_cons, agg_bufs);
1346                 if (!skb) {
1347                         /* Page reuse already handled by bnxt_rx_pages(). */
1348                         return NULL;
1349                 }
1350         }
1351         skb->protocol = eth_type_trans(skb, bp->dev);
1352
1353         if (tpa_info->hash_type != PKT_HASH_TYPE_NONE)
1354                 skb_set_hash(skb, tpa_info->rss_hash, tpa_info->hash_type);
1355
1356         if ((tpa_info->flags2 & RX_CMP_FLAGS2_META_FORMAT_VLAN) &&
1357             (skb->dev->features & NETIF_F_HW_VLAN_CTAG_RX)) {
1358                 u16 vlan_proto = tpa_info->metadata >>
1359                         RX_CMP_FLAGS2_METADATA_TPID_SFT;
1360                 u16 vtag = tpa_info->metadata & RX_CMP_FLAGS2_METADATA_VID_MASK;
1361
1362                 __vlan_hwaccel_put_tag(skb, htons(vlan_proto), vtag);
1363         }
1364
1365         skb_checksum_none_assert(skb);
1366         if (likely(tpa_info->flags2 & RX_TPA_START_CMP_FLAGS2_L4_CS_CALC)) {
1367                 skb->ip_summed = CHECKSUM_UNNECESSARY;
1368                 skb->csum_level =
1369                         (tpa_info->flags2 & RX_CMP_FLAGS2_T_L4_CS_CALC) >> 3;
1370         }
1371
1372         if (TPA_END_GRO(tpa_end))
1373                 skb = bnxt_gro_skb(bp, tpa_info, tpa_end, tpa_end1, skb);
1374
1375         return skb;
1376 }
1377
1378 /* returns the following:
1379  * 1       - 1 packet successfully received
1380  * 0       - successful TPA_START, packet not completed yet
1381  * -EBUSY  - completion ring does not have all the agg buffers yet
1382  * -ENOMEM - packet aborted due to out of memory
1383  * -EIO    - packet aborted due to hw error indicated in BD
1384  */
1385 static int bnxt_rx_pkt(struct bnxt *bp, struct bnxt_napi *bnapi, u32 *raw_cons,
1386                        u8 *event)
1387 {
1388         struct bnxt_cp_ring_info *cpr = &bnapi->cp_ring;
1389         struct bnxt_rx_ring_info *rxr = bnapi->rx_ring;
1390         struct net_device *dev = bp->dev;
1391         struct rx_cmp *rxcmp;
1392         struct rx_cmp_ext *rxcmp1;
1393         u32 tmp_raw_cons = *raw_cons;
1394         u16 cons, prod, cp_cons = RING_CMP(tmp_raw_cons);
1395         struct bnxt_sw_rx_bd *rx_buf;
1396         unsigned int len;
1397         u8 *data_ptr, agg_bufs, cmp_type;
1398         dma_addr_t dma_addr;
1399         struct sk_buff *skb;
1400         void *data;
1401         int rc = 0;
1402         u32 misc;
1403
1404         rxcmp = (struct rx_cmp *)
1405                         &cpr->cp_desc_ring[CP_RING(cp_cons)][CP_IDX(cp_cons)];
1406
1407         tmp_raw_cons = NEXT_RAW_CMP(tmp_raw_cons);
1408         cp_cons = RING_CMP(tmp_raw_cons);
1409         rxcmp1 = (struct rx_cmp_ext *)
1410                         &cpr->cp_desc_ring[CP_RING(cp_cons)][CP_IDX(cp_cons)];
1411
1412         if (!RX_CMP_VALID(rxcmp1, tmp_raw_cons))
1413                 return -EBUSY;
1414
1415         cmp_type = RX_CMP_TYPE(rxcmp);
1416
1417         prod = rxr->rx_prod;
1418
1419         if (cmp_type == CMP_TYPE_RX_L2_TPA_START_CMP) {
1420                 bnxt_tpa_start(bp, rxr, (struct rx_tpa_start_cmp *)rxcmp,
1421                                (struct rx_tpa_start_cmp_ext *)rxcmp1);
1422
1423                 *event |= BNXT_RX_EVENT;
1424                 goto next_rx_no_prod;
1425
1426         } else if (cmp_type == CMP_TYPE_RX_L2_TPA_END_CMP) {
1427                 skb = bnxt_tpa_end(bp, bnapi, &tmp_raw_cons,
1428                                    (struct rx_tpa_end_cmp *)rxcmp,
1429                                    (struct rx_tpa_end_cmp_ext *)rxcmp1, event);
1430
1431                 if (unlikely(IS_ERR(skb)))
1432                         return -EBUSY;
1433
1434                 rc = -ENOMEM;
1435                 if (likely(skb)) {
1436                         skb_record_rx_queue(skb, bnapi->index);
1437                         napi_gro_receive(&bnapi->napi, skb);
1438                         rc = 1;
1439                 }
1440                 *event |= BNXT_RX_EVENT;
1441                 goto next_rx_no_prod;
1442         }
1443
1444         cons = rxcmp->rx_cmp_opaque;
1445         rx_buf = &rxr->rx_buf_ring[cons];
1446         data = rx_buf->data;
1447         data_ptr = rx_buf->data_ptr;
1448         if (unlikely(cons != rxr->rx_next_cons)) {
1449                 int rc1 = bnxt_discard_rx(bp, bnapi, raw_cons, rxcmp);
1450
1451                 bnxt_sched_reset(bp, rxr);
1452                 return rc1;
1453         }
1454         prefetch(data_ptr);
1455
1456         misc = le32_to_cpu(rxcmp->rx_cmp_misc_v1);
1457         agg_bufs = (misc & RX_CMP_AGG_BUFS) >> RX_CMP_AGG_BUFS_SHIFT;
1458
1459         if (agg_bufs) {
1460                 if (!bnxt_agg_bufs_valid(bp, cpr, agg_bufs, &tmp_raw_cons))
1461                         return -EBUSY;
1462
1463                 cp_cons = NEXT_CMP(cp_cons);
1464                 *event |= BNXT_AGG_EVENT;
1465         }
1466         *event |= BNXT_RX_EVENT;
1467
1468         rx_buf->data = NULL;
1469         if (rxcmp1->rx_cmp_cfa_code_errors_v2 & RX_CMP_L2_ERRORS) {
1470                 bnxt_reuse_rx_data(rxr, cons, data);
1471                 if (agg_bufs)
1472                         bnxt_reuse_rx_agg_bufs(bnapi, cp_cons, agg_bufs);
1473
1474                 rc = -EIO;
1475                 goto next_rx;
1476         }
1477
1478         len = le32_to_cpu(rxcmp->rx_cmp_len_flags_type) >> RX_CMP_LEN_SHIFT;
1479         dma_addr = rx_buf->mapping;
1480
1481         if (bnxt_rx_xdp(bp, rxr, cons, data, &data_ptr, &len, event)) {
1482                 rc = 1;
1483                 goto next_rx;
1484         }
1485
1486         if (len <= bp->rx_copy_thresh) {
1487                 skb = bnxt_copy_skb(bnapi, data_ptr, len, dma_addr);
1488                 bnxt_reuse_rx_data(rxr, cons, data);
1489                 if (!skb) {
1490                         rc = -ENOMEM;
1491                         goto next_rx;
1492                 }
1493         } else {
1494                 u32 payload;
1495
1496                 if (rx_buf->data_ptr == data_ptr)
1497                         payload = misc & RX_CMP_PAYLOAD_OFFSET;
1498                 else
1499                         payload = 0;
1500                 skb = bp->rx_skb_func(bp, rxr, cons, data, data_ptr, dma_addr,
1501                                       payload | len);
1502                 if (!skb) {
1503                         rc = -ENOMEM;
1504                         goto next_rx;
1505                 }
1506         }
1507
1508         if (agg_bufs) {
1509                 skb = bnxt_rx_pages(bp, bnapi, skb, cp_cons, agg_bufs);
1510                 if (!skb) {
1511                         rc = -ENOMEM;
1512                         goto next_rx;
1513                 }
1514         }
1515
1516         if (RX_CMP_HASH_VALID(rxcmp)) {
1517                 u32 hash_type = RX_CMP_HASH_TYPE(rxcmp);
1518                 enum pkt_hash_types type = PKT_HASH_TYPE_L4;
1519
1520                 /* RSS profiles 1 and 3 with extract code 0 for inner 4-tuple */
1521                 if (hash_type != 1 && hash_type != 3)
1522                         type = PKT_HASH_TYPE_L3;
1523                 skb_set_hash(skb, le32_to_cpu(rxcmp->rx_cmp_rss_hash), type);
1524         }
1525
1526         skb->protocol = eth_type_trans(skb, dev);
1527
1528         if ((rxcmp1->rx_cmp_flags2 &
1529              cpu_to_le32(RX_CMP_FLAGS2_META_FORMAT_VLAN)) &&
1530             (skb->dev->features & NETIF_F_HW_VLAN_CTAG_RX)) {
1531                 u32 meta_data = le32_to_cpu(rxcmp1->rx_cmp_meta_data);
1532                 u16 vtag = meta_data & RX_CMP_FLAGS2_METADATA_VID_MASK;
1533                 u16 vlan_proto = meta_data >> RX_CMP_FLAGS2_METADATA_TPID_SFT;
1534
1535                 __vlan_hwaccel_put_tag(skb, htons(vlan_proto), vtag);
1536         }
1537
1538         skb_checksum_none_assert(skb);
1539         if (RX_CMP_L4_CS_OK(rxcmp1)) {
1540                 if (dev->features & NETIF_F_RXCSUM) {
1541                         skb->ip_summed = CHECKSUM_UNNECESSARY;
1542                         skb->csum_level = RX_CMP_ENCAP(rxcmp1);
1543                 }
1544         } else {
1545                 if (rxcmp1->rx_cmp_cfa_code_errors_v2 & RX_CMP_L4_CS_ERR_BITS) {
1546                         if (dev->features & NETIF_F_RXCSUM)
1547                                 cpr->rx_l4_csum_errors++;
1548                 }
1549         }
1550
1551         skb_record_rx_queue(skb, bnapi->index);
1552         napi_gro_receive(&bnapi->napi, skb);
1553         rc = 1;
1554
1555 next_rx:
1556         rxr->rx_prod = NEXT_RX(prod);
1557         rxr->rx_next_cons = NEXT_RX(cons);
1558
1559 next_rx_no_prod:
1560         *raw_cons = tmp_raw_cons;
1561
1562         return rc;
1563 }
1564
1565 #define BNXT_GET_EVENT_PORT(data)       \
1566         ((data) &                       \
1567          ASYNC_EVENT_CMPL_PORT_CONN_NOT_ALLOWED_EVENT_DATA1_PORT_ID_MASK)
1568
1569 static int bnxt_async_event_process(struct bnxt *bp,
1570                                     struct hwrm_async_event_cmpl *cmpl)
1571 {
1572         u16 event_id = le16_to_cpu(cmpl->event_id);
1573
1574         /* TODO CHIMP_FW: Define event id's for link change, error etc */
1575         switch (event_id) {
1576         case ASYNC_EVENT_CMPL_EVENT_ID_LINK_SPEED_CFG_CHANGE: {
1577                 u32 data1 = le32_to_cpu(cmpl->event_data1);
1578                 struct bnxt_link_info *link_info = &bp->link_info;
1579
1580                 if (BNXT_VF(bp))
1581                         goto async_event_process_exit;
1582                 if (data1 & 0x20000) {
1583                         u16 fw_speed = link_info->force_link_speed;
1584                         u32 speed = bnxt_fw_to_ethtool_speed(fw_speed);
1585
1586                         netdev_warn(bp->dev, "Link speed %d no longer supported\n",
1587                                     speed);
1588                 }
1589                 set_bit(BNXT_LINK_SPEED_CHNG_SP_EVENT, &bp->sp_event);
1590                 /* fall thru */
1591         }
1592         case ASYNC_EVENT_CMPL_EVENT_ID_LINK_STATUS_CHANGE:
1593                 set_bit(BNXT_LINK_CHNG_SP_EVENT, &bp->sp_event);
1594                 break;
1595         case ASYNC_EVENT_CMPL_EVENT_ID_PF_DRVR_UNLOAD:
1596                 set_bit(BNXT_HWRM_PF_UNLOAD_SP_EVENT, &bp->sp_event);
1597                 break;
1598         case ASYNC_EVENT_CMPL_EVENT_ID_PORT_CONN_NOT_ALLOWED: {
1599                 u32 data1 = le32_to_cpu(cmpl->event_data1);
1600                 u16 port_id = BNXT_GET_EVENT_PORT(data1);
1601
1602                 if (BNXT_VF(bp))
1603                         break;
1604
1605                 if (bp->pf.port_id != port_id)
1606                         break;
1607
1608                 set_bit(BNXT_HWRM_PORT_MODULE_SP_EVENT, &bp->sp_event);
1609                 break;
1610         }
1611         case ASYNC_EVENT_CMPL_EVENT_ID_VF_CFG_CHANGE:
1612                 if (BNXT_PF(bp))
1613                         goto async_event_process_exit;
1614                 set_bit(BNXT_RESET_TASK_SILENT_SP_EVENT, &bp->sp_event);
1615                 break;
1616         default:
1617                 goto async_event_process_exit;
1618         }
1619         schedule_work(&bp->sp_task);
1620 async_event_process_exit:
1621         bnxt_ulp_async_events(bp, cmpl);
1622         return 0;
1623 }
1624
1625 static int bnxt_hwrm_handler(struct bnxt *bp, struct tx_cmp *txcmp)
1626 {
1627         u16 cmpl_type = TX_CMP_TYPE(txcmp), vf_id, seq_id;
1628         struct hwrm_cmpl *h_cmpl = (struct hwrm_cmpl *)txcmp;
1629         struct hwrm_fwd_req_cmpl *fwd_req_cmpl =
1630                                 (struct hwrm_fwd_req_cmpl *)txcmp;
1631
1632         switch (cmpl_type) {
1633         case CMPL_BASE_TYPE_HWRM_DONE:
1634                 seq_id = le16_to_cpu(h_cmpl->sequence_id);
1635                 if (seq_id == bp->hwrm_intr_seq_id)
1636                         bp->hwrm_intr_seq_id = HWRM_SEQ_ID_INVALID;
1637                 else
1638                         netdev_err(bp->dev, "Invalid hwrm seq id %d\n", seq_id);
1639                 break;
1640
1641         case CMPL_BASE_TYPE_HWRM_FWD_REQ:
1642                 vf_id = le16_to_cpu(fwd_req_cmpl->source_id);
1643
1644                 if ((vf_id < bp->pf.first_vf_id) ||
1645                     (vf_id >= bp->pf.first_vf_id + bp->pf.active_vfs)) {
1646                         netdev_err(bp->dev, "Msg contains invalid VF id %x\n",
1647                                    vf_id);
1648                         return -EINVAL;
1649                 }
1650
1651                 set_bit(vf_id - bp->pf.first_vf_id, bp->pf.vf_event_bmap);
1652                 set_bit(BNXT_HWRM_EXEC_FWD_REQ_SP_EVENT, &bp->sp_event);
1653                 schedule_work(&bp->sp_task);
1654                 break;
1655
1656         case CMPL_BASE_TYPE_HWRM_ASYNC_EVENT:
1657                 bnxt_async_event_process(bp,
1658                                          (struct hwrm_async_event_cmpl *)txcmp);
1659
1660         default:
1661                 break;
1662         }
1663
1664         return 0;
1665 }
1666
1667 static irqreturn_t bnxt_msix(int irq, void *dev_instance)
1668 {
1669         struct bnxt_napi *bnapi = dev_instance;
1670         struct bnxt *bp = bnapi->bp;
1671         struct bnxt_cp_ring_info *cpr = &bnapi->cp_ring;
1672         u32 cons = RING_CMP(cpr->cp_raw_cons);
1673
1674         prefetch(&cpr->cp_desc_ring[CP_RING(cons)][CP_IDX(cons)]);
1675         napi_schedule(&bnapi->napi);
1676         return IRQ_HANDLED;
1677 }
1678
1679 static inline int bnxt_has_work(struct bnxt *bp, struct bnxt_cp_ring_info *cpr)
1680 {
1681         u32 raw_cons = cpr->cp_raw_cons;
1682         u16 cons = RING_CMP(raw_cons);
1683         struct tx_cmp *txcmp;
1684
1685         txcmp = &cpr->cp_desc_ring[CP_RING(cons)][CP_IDX(cons)];
1686
1687         return TX_CMP_VALID(txcmp, raw_cons);
1688 }
1689
1690 static irqreturn_t bnxt_inta(int irq, void *dev_instance)
1691 {
1692         struct bnxt_napi *bnapi = dev_instance;
1693         struct bnxt *bp = bnapi->bp;
1694         struct bnxt_cp_ring_info *cpr = &bnapi->cp_ring;
1695         u32 cons = RING_CMP(cpr->cp_raw_cons);
1696         u32 int_status;
1697
1698         prefetch(&cpr->cp_desc_ring[CP_RING(cons)][CP_IDX(cons)]);
1699
1700         if (!bnxt_has_work(bp, cpr)) {
1701                 int_status = readl(bp->bar0 + BNXT_CAG_REG_LEGACY_INT_STATUS);
1702                 /* return if erroneous interrupt */
1703                 if (!(int_status & (0x10000 << cpr->cp_ring_struct.fw_ring_id)))
1704                         return IRQ_NONE;
1705         }
1706
1707         /* disable ring IRQ */
1708         BNXT_CP_DB_IRQ_DIS(cpr->cp_doorbell);
1709
1710         /* Return here if interrupt is shared and is disabled. */
1711         if (unlikely(atomic_read(&bp->intr_sem) != 0))
1712                 return IRQ_HANDLED;
1713
1714         napi_schedule(&bnapi->napi);
1715         return IRQ_HANDLED;
1716 }
1717
1718 static int bnxt_poll_work(struct bnxt *bp, struct bnxt_napi *bnapi, int budget)
1719 {
1720         struct bnxt_cp_ring_info *cpr = &bnapi->cp_ring;
1721         u32 raw_cons = cpr->cp_raw_cons;
1722         u32 cons;
1723         int tx_pkts = 0;
1724         int rx_pkts = 0;
1725         u8 event = 0;
1726         struct tx_cmp *txcmp;
1727
1728         while (1) {
1729                 int rc;
1730
1731                 cons = RING_CMP(raw_cons);
1732                 txcmp = &cpr->cp_desc_ring[CP_RING(cons)][CP_IDX(cons)];
1733
1734                 if (!TX_CMP_VALID(txcmp, raw_cons))
1735                         break;
1736
1737                 /* The valid test of the entry must be done first before
1738                  * reading any further.
1739                  */
1740                 dma_rmb();
1741                 if (TX_CMP_TYPE(txcmp) == CMP_TYPE_TX_L2_CMP) {
1742                         tx_pkts++;
1743                         /* return full budget so NAPI will complete. */
1744                         if (unlikely(tx_pkts > bp->tx_wake_thresh))
1745                                 rx_pkts = budget;
1746                 } else if ((TX_CMP_TYPE(txcmp) & 0x30) == 0x10) {
1747                         rc = bnxt_rx_pkt(bp, bnapi, &raw_cons, &event);
1748                         if (likely(rc >= 0))
1749                                 rx_pkts += rc;
1750                         else if (rc == -EBUSY)  /* partial completion */
1751                                 break;
1752                 } else if (unlikely((TX_CMP_TYPE(txcmp) ==
1753                                      CMPL_BASE_TYPE_HWRM_DONE) ||
1754                                     (TX_CMP_TYPE(txcmp) ==
1755                                      CMPL_BASE_TYPE_HWRM_FWD_REQ) ||
1756                                     (TX_CMP_TYPE(txcmp) ==
1757                                      CMPL_BASE_TYPE_HWRM_ASYNC_EVENT))) {
1758                         bnxt_hwrm_handler(bp, txcmp);
1759                 }
1760                 raw_cons = NEXT_RAW_CMP(raw_cons);
1761
1762                 if (rx_pkts == budget)
1763                         break;
1764         }
1765
1766         if (event & BNXT_TX_EVENT) {
1767                 struct bnxt_tx_ring_info *txr = bnapi->tx_ring;
1768                 void __iomem *db = txr->tx_doorbell;
1769                 u16 prod = txr->tx_prod;
1770
1771                 /* Sync BD data before updating doorbell */
1772                 wmb();
1773
1774                 writel(DB_KEY_TX | prod, db);
1775                 writel(DB_KEY_TX | prod, db);
1776         }
1777
1778         cpr->cp_raw_cons = raw_cons;
1779         /* ACK completion ring before freeing tx ring and producing new
1780          * buffers in rx/agg rings to prevent overflowing the completion
1781          * ring.
1782          */
1783         BNXT_CP_DB(cpr->cp_doorbell, cpr->cp_raw_cons);
1784
1785         if (tx_pkts)
1786                 bnapi->tx_int(bp, bnapi, tx_pkts);
1787
1788         if (event & BNXT_RX_EVENT) {
1789                 struct bnxt_rx_ring_info *rxr = bnapi->rx_ring;
1790
1791                 writel(DB_KEY_RX | rxr->rx_prod, rxr->rx_doorbell);
1792                 writel(DB_KEY_RX | rxr->rx_prod, rxr->rx_doorbell);
1793                 if (event & BNXT_AGG_EVENT) {
1794                         writel(DB_KEY_RX | rxr->rx_agg_prod,
1795                                rxr->rx_agg_doorbell);
1796                         writel(DB_KEY_RX | rxr->rx_agg_prod,
1797                                rxr->rx_agg_doorbell);
1798                 }
1799         }
1800         return rx_pkts;
1801 }
1802
1803 static int bnxt_poll_nitroa0(struct napi_struct *napi, int budget)
1804 {
1805         struct bnxt_napi *bnapi = container_of(napi, struct bnxt_napi, napi);
1806         struct bnxt *bp = bnapi->bp;
1807         struct bnxt_cp_ring_info *cpr = &bnapi->cp_ring;
1808         struct bnxt_rx_ring_info *rxr = bnapi->rx_ring;
1809         struct tx_cmp *txcmp;
1810         struct rx_cmp_ext *rxcmp1;
1811         u32 cp_cons, tmp_raw_cons;
1812         u32 raw_cons = cpr->cp_raw_cons;
1813         u32 rx_pkts = 0;
1814         u8 event = 0;
1815
1816         while (1) {
1817                 int rc;
1818
1819                 cp_cons = RING_CMP(raw_cons);
1820                 txcmp = &cpr->cp_desc_ring[CP_RING(cp_cons)][CP_IDX(cp_cons)];
1821
1822                 if (!TX_CMP_VALID(txcmp, raw_cons))
1823                         break;
1824
1825                 if ((TX_CMP_TYPE(txcmp) & 0x30) == 0x10) {
1826                         tmp_raw_cons = NEXT_RAW_CMP(raw_cons);
1827                         cp_cons = RING_CMP(tmp_raw_cons);
1828                         rxcmp1 = (struct rx_cmp_ext *)
1829                           &cpr->cp_desc_ring[CP_RING(cp_cons)][CP_IDX(cp_cons)];
1830
1831                         if (!RX_CMP_VALID(rxcmp1, tmp_raw_cons))
1832                                 break;
1833
1834                         /* force an error to recycle the buffer */
1835                         rxcmp1->rx_cmp_cfa_code_errors_v2 |=
1836                                 cpu_to_le32(RX_CMPL_ERRORS_CRC_ERROR);
1837
1838                         rc = bnxt_rx_pkt(bp, bnapi, &raw_cons, &event);
1839                         if (likely(rc == -EIO))
1840                                 rx_pkts++;
1841                         else if (rc == -EBUSY)  /* partial completion */
1842                                 break;
1843                 } else if (unlikely(TX_CMP_TYPE(txcmp) ==
1844                                     CMPL_BASE_TYPE_HWRM_DONE)) {
1845                         bnxt_hwrm_handler(bp, txcmp);
1846                 } else {
1847                         netdev_err(bp->dev,
1848                                    "Invalid completion received on special ring\n");
1849                 }
1850                 raw_cons = NEXT_RAW_CMP(raw_cons);
1851
1852                 if (rx_pkts == budget)
1853                         break;
1854         }
1855
1856         cpr->cp_raw_cons = raw_cons;
1857         BNXT_CP_DB(cpr->cp_doorbell, cpr->cp_raw_cons);
1858         writel(DB_KEY_RX | rxr->rx_prod, rxr->rx_doorbell);
1859         writel(DB_KEY_RX | rxr->rx_prod, rxr->rx_doorbell);
1860
1861         if (event & BNXT_AGG_EVENT) {
1862                 writel(DB_KEY_RX | rxr->rx_agg_prod, rxr->rx_agg_doorbell);
1863                 writel(DB_KEY_RX | rxr->rx_agg_prod, rxr->rx_agg_doorbell);
1864         }
1865
1866         if (!bnxt_has_work(bp, cpr) && rx_pkts < budget) {
1867                 napi_complete_done(napi, rx_pkts);
1868                 BNXT_CP_DB_REARM(cpr->cp_doorbell, cpr->cp_raw_cons);
1869         }
1870         return rx_pkts;
1871 }
1872
1873 static int bnxt_poll(struct napi_struct *napi, int budget)
1874 {
1875         struct bnxt_napi *bnapi = container_of(napi, struct bnxt_napi, napi);
1876         struct bnxt *bp = bnapi->bp;
1877         struct bnxt_cp_ring_info *cpr = &bnapi->cp_ring;
1878         int work_done = 0;
1879
1880         while (1) {
1881                 work_done += bnxt_poll_work(bp, bnapi, budget - work_done);
1882
1883                 if (work_done >= budget)
1884                         break;
1885
1886                 if (!bnxt_has_work(bp, cpr)) {
1887                         if (napi_complete_done(napi, work_done))
1888                                 BNXT_CP_DB_REARM(cpr->cp_doorbell,
1889                                                  cpr->cp_raw_cons);
1890                         break;
1891                 }
1892         }
1893         mmiowb();
1894         return work_done;
1895 }
1896
1897 static void bnxt_free_tx_skbs(struct bnxt *bp)
1898 {
1899         int i, max_idx;
1900         struct pci_dev *pdev = bp->pdev;
1901
1902         if (!bp->tx_ring)
1903                 return;
1904
1905         max_idx = bp->tx_nr_pages * TX_DESC_CNT;
1906         for (i = 0; i < bp->tx_nr_rings; i++) {
1907                 struct bnxt_tx_ring_info *txr = &bp->tx_ring[i];
1908                 int j;
1909
1910                 for (j = 0; j < max_idx;) {
1911                         struct bnxt_sw_tx_bd *tx_buf = &txr->tx_buf_ring[j];
1912                         struct sk_buff *skb = tx_buf->skb;
1913                         int k, last;
1914
1915                         if (!skb) {
1916                                 j++;
1917                                 continue;
1918                         }
1919
1920                         tx_buf->skb = NULL;
1921
1922                         if (tx_buf->is_push) {
1923                                 dev_kfree_skb(skb);
1924                                 j += 2;
1925                                 continue;
1926                         }
1927
1928                         dma_unmap_single(&pdev->dev,
1929                                          dma_unmap_addr(tx_buf, mapping),
1930                                          skb_headlen(skb),
1931                                          PCI_DMA_TODEVICE);
1932
1933                         last = tx_buf->nr_frags;
1934                         j += 2;
1935                         for (k = 0; k < last; k++, j++) {
1936                                 int ring_idx = j & bp->tx_ring_mask;
1937                                 skb_frag_t *frag = &skb_shinfo(skb)->frags[k];
1938
1939                                 tx_buf = &txr->tx_buf_ring[ring_idx];
1940                                 dma_unmap_page(
1941                                         &pdev->dev,
1942                                         dma_unmap_addr(tx_buf, mapping),
1943                                         skb_frag_size(frag), PCI_DMA_TODEVICE);
1944                         }
1945                         dev_kfree_skb(skb);
1946                 }
1947                 netdev_tx_reset_queue(netdev_get_tx_queue(bp->dev, i));
1948         }
1949 }
1950
1951 static void bnxt_free_rx_skbs(struct bnxt *bp)
1952 {
1953         int i, max_idx, max_agg_idx;
1954         struct pci_dev *pdev = bp->pdev;
1955
1956         if (!bp->rx_ring)
1957                 return;
1958
1959         max_idx = bp->rx_nr_pages * RX_DESC_CNT;
1960         max_agg_idx = bp->rx_agg_nr_pages * RX_DESC_CNT;
1961         for (i = 0; i < bp->rx_nr_rings; i++) {
1962                 struct bnxt_rx_ring_info *rxr = &bp->rx_ring[i];
1963                 int j;
1964
1965                 if (rxr->rx_tpa) {
1966                         for (j = 0; j < MAX_TPA; j++) {
1967                                 struct bnxt_tpa_info *tpa_info =
1968                                                         &rxr->rx_tpa[j];
1969                                 u8 *data = tpa_info->data;
1970
1971                                 if (!data)
1972                                         continue;
1973
1974                                 dma_unmap_single(&pdev->dev, tpa_info->mapping,
1975                                                  bp->rx_buf_use_size,
1976                                                  bp->rx_dir);
1977
1978                                 tpa_info->data = NULL;
1979
1980                                 kfree(data);
1981                         }
1982                 }
1983
1984                 for (j = 0; j < max_idx; j++) {
1985                         struct bnxt_sw_rx_bd *rx_buf = &rxr->rx_buf_ring[j];
1986                         void *data = rx_buf->data;
1987
1988                         if (!data)
1989                                 continue;
1990
1991                         dma_unmap_single(&pdev->dev, rx_buf->mapping,
1992                                          bp->rx_buf_use_size, bp->rx_dir);
1993
1994                         rx_buf->data = NULL;
1995
1996                         if (BNXT_RX_PAGE_MODE(bp))
1997                                 __free_page(data);
1998                         else
1999                                 kfree(data);
2000                 }
2001
2002                 for (j = 0; j < max_agg_idx; j++) {
2003                         struct bnxt_sw_rx_agg_bd *rx_agg_buf =
2004                                 &rxr->rx_agg_ring[j];
2005                         struct page *page = rx_agg_buf->page;
2006
2007                         if (!page)
2008                                 continue;
2009
2010                         dma_unmap_page(&pdev->dev, rx_agg_buf->mapping,
2011                                        BNXT_RX_PAGE_SIZE, PCI_DMA_FROMDEVICE);
2012
2013                         rx_agg_buf->page = NULL;
2014                         __clear_bit(j, rxr->rx_agg_bmap);
2015
2016                         __free_page(page);
2017                 }
2018                 if (rxr->rx_page) {
2019                         __free_page(rxr->rx_page);
2020                         rxr->rx_page = NULL;
2021                 }
2022         }
2023 }
2024
2025 static void bnxt_free_skbs(struct bnxt *bp)
2026 {
2027         bnxt_free_tx_skbs(bp);
2028         bnxt_free_rx_skbs(bp);
2029 }
2030
2031 static void bnxt_free_ring(struct bnxt *bp, struct bnxt_ring_struct *ring)
2032 {
2033         struct pci_dev *pdev = bp->pdev;
2034         int i;
2035
2036         for (i = 0; i < ring->nr_pages; i++) {
2037                 if (!ring->pg_arr[i])
2038                         continue;
2039
2040                 dma_free_coherent(&pdev->dev, ring->page_size,
2041                                   ring->pg_arr[i], ring->dma_arr[i]);
2042
2043                 ring->pg_arr[i] = NULL;
2044         }
2045         if (ring->pg_tbl) {
2046                 dma_free_coherent(&pdev->dev, ring->nr_pages * 8,
2047                                   ring->pg_tbl, ring->pg_tbl_map);
2048                 ring->pg_tbl = NULL;
2049         }
2050         if (ring->vmem_size && *ring->vmem) {
2051                 vfree(*ring->vmem);
2052                 *ring->vmem = NULL;
2053         }
2054 }
2055
2056 static int bnxt_alloc_ring(struct bnxt *bp, struct bnxt_ring_struct *ring)
2057 {
2058         int i;
2059         struct pci_dev *pdev = bp->pdev;
2060
2061         if (ring->nr_pages > 1) {
2062                 ring->pg_tbl = dma_alloc_coherent(&pdev->dev,
2063                                                   ring->nr_pages * 8,
2064                                                   &ring->pg_tbl_map,
2065                                                   GFP_KERNEL);
2066                 if (!ring->pg_tbl)
2067                         return -ENOMEM;
2068         }
2069
2070         for (i = 0; i < ring->nr_pages; i++) {
2071                 ring->pg_arr[i] = dma_alloc_coherent(&pdev->dev,
2072                                                      ring->page_size,
2073                                                      &ring->dma_arr[i],
2074                                                      GFP_KERNEL);
2075                 if (!ring->pg_arr[i])
2076                         return -ENOMEM;
2077
2078                 if (ring->nr_pages > 1)
2079                         ring->pg_tbl[i] = cpu_to_le64(ring->dma_arr[i]);
2080         }
2081
2082         if (ring->vmem_size) {
2083                 *ring->vmem = vzalloc(ring->vmem_size);
2084                 if (!(*ring->vmem))
2085                         return -ENOMEM;
2086         }
2087         return 0;
2088 }
2089
2090 static void bnxt_free_rx_rings(struct bnxt *bp)
2091 {
2092         int i;
2093
2094         if (!bp->rx_ring)
2095                 return;
2096
2097         for (i = 0; i < bp->rx_nr_rings; i++) {
2098                 struct bnxt_rx_ring_info *rxr = &bp->rx_ring[i];
2099                 struct bnxt_ring_struct *ring;
2100
2101                 if (rxr->xdp_prog)
2102                         bpf_prog_put(rxr->xdp_prog);
2103
2104                 kfree(rxr->rx_tpa);
2105                 rxr->rx_tpa = NULL;
2106
2107                 kfree(rxr->rx_agg_bmap);
2108                 rxr->rx_agg_bmap = NULL;
2109
2110                 ring = &rxr->rx_ring_struct;
2111                 bnxt_free_ring(bp, ring);
2112
2113                 ring = &rxr->rx_agg_ring_struct;
2114                 bnxt_free_ring(bp, ring);
2115         }
2116 }
2117
2118 static int bnxt_alloc_rx_rings(struct bnxt *bp)
2119 {
2120         int i, rc, agg_rings = 0, tpa_rings = 0;
2121
2122         if (!bp->rx_ring)
2123                 return -ENOMEM;
2124
2125         if (bp->flags & BNXT_FLAG_AGG_RINGS)
2126                 agg_rings = 1;
2127
2128         if (bp->flags & BNXT_FLAG_TPA)
2129                 tpa_rings = 1;
2130
2131         for (i = 0; i < bp->rx_nr_rings; i++) {
2132                 struct bnxt_rx_ring_info *rxr = &bp->rx_ring[i];
2133                 struct bnxt_ring_struct *ring;
2134
2135                 ring = &rxr->rx_ring_struct;
2136
2137                 rc = bnxt_alloc_ring(bp, ring);
2138                 if (rc)
2139                         return rc;
2140
2141                 if (agg_rings) {
2142                         u16 mem_size;
2143
2144                         ring = &rxr->rx_agg_ring_struct;
2145                         rc = bnxt_alloc_ring(bp, ring);
2146                         if (rc)
2147                                 return rc;
2148
2149                         rxr->rx_agg_bmap_size = bp->rx_agg_ring_mask + 1;
2150                         mem_size = rxr->rx_agg_bmap_size / 8;
2151                         rxr->rx_agg_bmap = kzalloc(mem_size, GFP_KERNEL);
2152                         if (!rxr->rx_agg_bmap)
2153                                 return -ENOMEM;
2154
2155                         if (tpa_rings) {
2156                                 rxr->rx_tpa = kcalloc(MAX_TPA,
2157                                                 sizeof(struct bnxt_tpa_info),
2158                                                 GFP_KERNEL);
2159                                 if (!rxr->rx_tpa)
2160                                         return -ENOMEM;
2161                         }
2162                 }
2163         }
2164         return 0;
2165 }
2166
2167 static void bnxt_free_tx_rings(struct bnxt *bp)
2168 {
2169         int i;
2170         struct pci_dev *pdev = bp->pdev;
2171
2172         if (!bp->tx_ring)
2173                 return;
2174
2175         for (i = 0; i < bp->tx_nr_rings; i++) {
2176                 struct bnxt_tx_ring_info *txr = &bp->tx_ring[i];
2177                 struct bnxt_ring_struct *ring;
2178
2179                 if (txr->tx_push) {
2180                         dma_free_coherent(&pdev->dev, bp->tx_push_size,
2181                                           txr->tx_push, txr->tx_push_mapping);
2182                         txr->tx_push = NULL;
2183                 }
2184
2185                 ring = &txr->tx_ring_struct;
2186
2187                 bnxt_free_ring(bp, ring);
2188         }
2189 }
2190
2191 static int bnxt_alloc_tx_rings(struct bnxt *bp)
2192 {
2193         int i, j, rc;
2194         struct pci_dev *pdev = bp->pdev;
2195
2196         bp->tx_push_size = 0;
2197         if (bp->tx_push_thresh) {
2198                 int push_size;
2199
2200                 push_size  = L1_CACHE_ALIGN(sizeof(struct tx_push_bd) +
2201                                         bp->tx_push_thresh);
2202
2203                 if (push_size > 256) {
2204                         push_size = 0;
2205                         bp->tx_push_thresh = 0;
2206                 }
2207
2208                 bp->tx_push_size = push_size;
2209         }
2210
2211         for (i = 0, j = 0; i < bp->tx_nr_rings; i++) {
2212                 struct bnxt_tx_ring_info *txr = &bp->tx_ring[i];
2213                 struct bnxt_ring_struct *ring;
2214
2215                 ring = &txr->tx_ring_struct;
2216
2217                 rc = bnxt_alloc_ring(bp, ring);
2218                 if (rc)
2219                         return rc;
2220
2221                 if (bp->tx_push_size) {
2222                         dma_addr_t mapping;
2223
2224                         /* One pre-allocated DMA buffer to backup
2225                          * TX push operation
2226                          */
2227                         txr->tx_push = dma_alloc_coherent(&pdev->dev,
2228                                                 bp->tx_push_size,
2229                                                 &txr->tx_push_mapping,
2230                                                 GFP_KERNEL);
2231
2232                         if (!txr->tx_push)
2233                                 return -ENOMEM;
2234
2235                         mapping = txr->tx_push_mapping +
2236                                 sizeof(struct tx_push_bd);
2237                         txr->data_mapping = cpu_to_le64(mapping);
2238
2239                         memset(txr->tx_push, 0, sizeof(struct tx_push_bd));
2240                 }
2241                 ring->queue_id = bp->q_info[j].queue_id;
2242                 if (i < bp->tx_nr_rings_xdp)
2243                         continue;
2244                 if (i % bp->tx_nr_rings_per_tc == (bp->tx_nr_rings_per_tc - 1))
2245                         j++;
2246         }
2247         return 0;
2248 }
2249
2250 static void bnxt_free_cp_rings(struct bnxt *bp)
2251 {
2252         int i;
2253
2254         if (!bp->bnapi)
2255                 return;
2256
2257         for (i = 0; i < bp->cp_nr_rings; i++) {
2258                 struct bnxt_napi *bnapi = bp->bnapi[i];
2259                 struct bnxt_cp_ring_info *cpr;
2260                 struct bnxt_ring_struct *ring;
2261
2262                 if (!bnapi)
2263                         continue;
2264
2265                 cpr = &bnapi->cp_ring;
2266                 ring = &cpr->cp_ring_struct;
2267
2268                 bnxt_free_ring(bp, ring);
2269         }
2270 }
2271
2272 static int bnxt_alloc_cp_rings(struct bnxt *bp)
2273 {
2274         int i, rc;
2275
2276         for (i = 0; i < bp->cp_nr_rings; i++) {
2277                 struct bnxt_napi *bnapi = bp->bnapi[i];
2278                 struct bnxt_cp_ring_info *cpr;
2279                 struct bnxt_ring_struct *ring;
2280
2281                 if (!bnapi)
2282                         continue;
2283
2284                 cpr = &bnapi->cp_ring;
2285                 ring = &cpr->cp_ring_struct;
2286
2287                 rc = bnxt_alloc_ring(bp, ring);
2288                 if (rc)
2289                         return rc;
2290         }
2291         return 0;
2292 }
2293
2294 static void bnxt_init_ring_struct(struct bnxt *bp)
2295 {
2296         int i;
2297
2298         for (i = 0; i < bp->cp_nr_rings; i++) {
2299                 struct bnxt_napi *bnapi = bp->bnapi[i];
2300                 struct bnxt_cp_ring_info *cpr;
2301                 struct bnxt_rx_ring_info *rxr;
2302                 struct bnxt_tx_ring_info *txr;
2303                 struct bnxt_ring_struct *ring;
2304
2305                 if (!bnapi)
2306                         continue;
2307
2308                 cpr = &bnapi->cp_ring;
2309                 ring = &cpr->cp_ring_struct;
2310                 ring->nr_pages = bp->cp_nr_pages;
2311                 ring->page_size = HW_CMPD_RING_SIZE;
2312                 ring->pg_arr = (void **)cpr->cp_desc_ring;
2313                 ring->dma_arr = cpr->cp_desc_mapping;
2314                 ring->vmem_size = 0;
2315
2316                 rxr = bnapi->rx_ring;
2317                 if (!rxr)
2318                         goto skip_rx;
2319
2320                 ring = &rxr->rx_ring_struct;
2321                 ring->nr_pages = bp->rx_nr_pages;
2322                 ring->page_size = HW_RXBD_RING_SIZE;
2323                 ring->pg_arr = (void **)rxr->rx_desc_ring;
2324                 ring->dma_arr = rxr->rx_desc_mapping;
2325                 ring->vmem_size = SW_RXBD_RING_SIZE * bp->rx_nr_pages;
2326                 ring->vmem = (void **)&rxr->rx_buf_ring;
2327
2328                 ring = &rxr->rx_agg_ring_struct;
2329                 ring->nr_pages = bp->rx_agg_nr_pages;
2330                 ring->page_size = HW_RXBD_RING_SIZE;
2331                 ring->pg_arr = (void **)rxr->rx_agg_desc_ring;
2332                 ring->dma_arr = rxr->rx_agg_desc_mapping;
2333                 ring->vmem_size = SW_RXBD_AGG_RING_SIZE * bp->rx_agg_nr_pages;
2334                 ring->vmem = (void **)&rxr->rx_agg_ring;
2335
2336 skip_rx:
2337                 txr = bnapi->tx_ring;
2338                 if (!txr)
2339                         continue;
2340
2341                 ring = &txr->tx_ring_struct;
2342                 ring->nr_pages = bp->tx_nr_pages;
2343                 ring->page_size = HW_RXBD_RING_SIZE;
2344                 ring->pg_arr = (void **)txr->tx_desc_ring;
2345                 ring->dma_arr = txr->tx_desc_mapping;
2346                 ring->vmem_size = SW_TXBD_RING_SIZE * bp->tx_nr_pages;
2347                 ring->vmem = (void **)&txr->tx_buf_ring;
2348         }
2349 }
2350
2351 static void bnxt_init_rxbd_pages(struct bnxt_ring_struct *ring, u32 type)
2352 {
2353         int i;
2354         u32 prod;
2355         struct rx_bd **rx_buf_ring;
2356
2357         rx_buf_ring = (struct rx_bd **)ring->pg_arr;
2358         for (i = 0, prod = 0; i < ring->nr_pages; i++) {
2359                 int j;
2360                 struct rx_bd *rxbd;
2361
2362                 rxbd = rx_buf_ring[i];
2363                 if (!rxbd)
2364                         continue;
2365
2366                 for (j = 0; j < RX_DESC_CNT; j++, rxbd++, prod++) {
2367                         rxbd->rx_bd_len_flags_type = cpu_to_le32(type);
2368                         rxbd->rx_bd_opaque = prod;
2369                 }
2370         }
2371 }
2372
2373 static int bnxt_init_one_rx_ring(struct bnxt *bp, int ring_nr)
2374 {
2375         struct net_device *dev = bp->dev;
2376         struct bnxt_rx_ring_info *rxr;
2377         struct bnxt_ring_struct *ring;
2378         u32 prod, type;
2379         int i;
2380
2381         type = (bp->rx_buf_use_size << RX_BD_LEN_SHIFT) |
2382                 RX_BD_TYPE_RX_PACKET_BD | RX_BD_FLAGS_EOP;
2383
2384         if (NET_IP_ALIGN == 2)
2385                 type |= RX_BD_FLAGS_SOP;
2386
2387         rxr = &bp->rx_ring[ring_nr];
2388         ring = &rxr->rx_ring_struct;
2389         bnxt_init_rxbd_pages(ring, type);
2390
2391         if (BNXT_RX_PAGE_MODE(bp) && bp->xdp_prog) {
2392                 rxr->xdp_prog = bpf_prog_add(bp->xdp_prog, 1);
2393                 if (IS_ERR(rxr->xdp_prog)) {
2394                         int rc = PTR_ERR(rxr->xdp_prog);
2395
2396                         rxr->xdp_prog = NULL;
2397                         return rc;
2398                 }
2399         }
2400         prod = rxr->rx_prod;
2401         for (i = 0; i < bp->rx_ring_size; i++) {
2402                 if (bnxt_alloc_rx_data(bp, rxr, prod, GFP_KERNEL) != 0) {
2403                         netdev_warn(dev, "init'ed rx ring %d with %d/%d skbs only\n",
2404                                     ring_nr, i, bp->rx_ring_size);
2405                         break;
2406                 }
2407                 prod = NEXT_RX(prod);
2408         }
2409         rxr->rx_prod = prod;
2410         ring->fw_ring_id = INVALID_HW_RING_ID;
2411
2412         ring = &rxr->rx_agg_ring_struct;
2413         ring->fw_ring_id = INVALID_HW_RING_ID;
2414
2415         if (!(bp->flags & BNXT_FLAG_AGG_RINGS))
2416                 return 0;
2417
2418         type = ((u32)BNXT_RX_PAGE_SIZE << RX_BD_LEN_SHIFT) |
2419                 RX_BD_TYPE_RX_AGG_BD | RX_BD_FLAGS_SOP;
2420
2421         bnxt_init_rxbd_pages(ring, type);
2422
2423         prod = rxr->rx_agg_prod;
2424         for (i = 0; i < bp->rx_agg_ring_size; i++) {
2425                 if (bnxt_alloc_rx_page(bp, rxr, prod, GFP_KERNEL) != 0) {
2426                         netdev_warn(dev, "init'ed rx ring %d with %d/%d pages only\n",
2427                                     ring_nr, i, bp->rx_ring_size);
2428                         break;
2429                 }
2430                 prod = NEXT_RX_AGG(prod);
2431         }
2432         rxr->rx_agg_prod = prod;
2433
2434         if (bp->flags & BNXT_FLAG_TPA) {
2435                 if (rxr->rx_tpa) {
2436                         u8 *data;
2437                         dma_addr_t mapping;
2438
2439                         for (i = 0; i < MAX_TPA; i++) {
2440                                 data = __bnxt_alloc_rx_data(bp, &mapping,
2441                                                             GFP_KERNEL);
2442                                 if (!data)
2443                                         return -ENOMEM;
2444
2445                                 rxr->rx_tpa[i].data = data;
2446                                 rxr->rx_tpa[i].data_ptr = data + bp->rx_offset;
2447                                 rxr->rx_tpa[i].mapping = mapping;
2448                         }
2449                 } else {
2450                         netdev_err(bp->dev, "No resource allocated for LRO/GRO\n");
2451                         return -ENOMEM;
2452                 }
2453         }
2454
2455         return 0;
2456 }
2457
2458 static int bnxt_init_rx_rings(struct bnxt *bp)
2459 {
2460         int i, rc = 0;
2461
2462         if (BNXT_RX_PAGE_MODE(bp)) {
2463                 bp->rx_offset = NET_IP_ALIGN + XDP_PACKET_HEADROOM;
2464                 bp->rx_dma_offset = XDP_PACKET_HEADROOM;
2465         } else {
2466                 bp->rx_offset = BNXT_RX_OFFSET;
2467                 bp->rx_dma_offset = BNXT_RX_DMA_OFFSET;
2468         }
2469
2470         for (i = 0; i < bp->rx_nr_rings; i++) {
2471                 rc = bnxt_init_one_rx_ring(bp, i);
2472                 if (rc)
2473                         break;
2474         }
2475
2476         return rc;
2477 }
2478
2479 static int bnxt_init_tx_rings(struct bnxt *bp)
2480 {
2481         u16 i;
2482
2483         bp->tx_wake_thresh = max_t(int, bp->tx_ring_size / 2,
2484                                    MAX_SKB_FRAGS + 1);
2485
2486         for (i = 0; i < bp->tx_nr_rings; i++) {
2487                 struct bnxt_tx_ring_info *txr = &bp->tx_ring[i];
2488                 struct bnxt_ring_struct *ring = &txr->tx_ring_struct;
2489
2490                 ring->fw_ring_id = INVALID_HW_RING_ID;
2491         }
2492
2493         return 0;
2494 }
2495
2496 static void bnxt_free_ring_grps(struct bnxt *bp)
2497 {
2498         kfree(bp->grp_info);
2499         bp->grp_info = NULL;
2500 }
2501
2502 static int bnxt_init_ring_grps(struct bnxt *bp, bool irq_re_init)
2503 {
2504         int i;
2505
2506         if (irq_re_init) {
2507                 bp->grp_info = kcalloc(bp->cp_nr_rings,
2508                                        sizeof(struct bnxt_ring_grp_info),
2509                                        GFP_KERNEL);
2510                 if (!bp->grp_info)
2511                         return -ENOMEM;
2512         }
2513         for (i = 0; i < bp->cp_nr_rings; i++) {
2514                 if (irq_re_init)
2515                         bp->grp_info[i].fw_stats_ctx = INVALID_HW_RING_ID;
2516                 bp->grp_info[i].fw_grp_id = INVALID_HW_RING_ID;
2517                 bp->grp_info[i].rx_fw_ring_id = INVALID_HW_RING_ID;
2518                 bp->grp_info[i].agg_fw_ring_id = INVALID_HW_RING_ID;
2519                 bp->grp_info[i].cp_fw_ring_id = INVALID_HW_RING_ID;
2520         }
2521         return 0;
2522 }
2523
2524 static void bnxt_free_vnics(struct bnxt *bp)
2525 {
2526         kfree(bp->vnic_info);
2527         bp->vnic_info = NULL;
2528         bp->nr_vnics = 0;
2529 }
2530
2531 static int bnxt_alloc_vnics(struct bnxt *bp)
2532 {
2533         int num_vnics = 1;
2534
2535 #ifdef CONFIG_RFS_ACCEL
2536         if (bp->flags & BNXT_FLAG_RFS)
2537                 num_vnics += bp->rx_nr_rings;
2538 #endif
2539
2540         if (BNXT_CHIP_TYPE_NITRO_A0(bp))
2541                 num_vnics++;
2542
2543         bp->vnic_info = kcalloc(num_vnics, sizeof(struct bnxt_vnic_info),
2544                                 GFP_KERNEL);
2545         if (!bp->vnic_info)
2546                 return -ENOMEM;
2547
2548         bp->nr_vnics = num_vnics;
2549         return 0;
2550 }
2551
2552 static void bnxt_init_vnics(struct bnxt *bp)
2553 {
2554         int i;
2555
2556         for (i = 0; i < bp->nr_vnics; i++) {
2557                 struct bnxt_vnic_info *vnic = &bp->vnic_info[i];
2558
2559                 vnic->fw_vnic_id = INVALID_HW_RING_ID;
2560                 vnic->fw_rss_cos_lb_ctx[0] = INVALID_HW_RING_ID;
2561                 vnic->fw_rss_cos_lb_ctx[1] = INVALID_HW_RING_ID;
2562                 vnic->fw_l2_ctx_id = INVALID_HW_RING_ID;
2563
2564                 if (bp->vnic_info[i].rss_hash_key) {
2565                         if (i == 0)
2566                                 prandom_bytes(vnic->rss_hash_key,
2567                                               HW_HASH_KEY_SIZE);
2568                         else
2569                                 memcpy(vnic->rss_hash_key,
2570                                        bp->vnic_info[0].rss_hash_key,
2571                                        HW_HASH_KEY_SIZE);
2572                 }
2573         }
2574 }
2575
2576 static int bnxt_calc_nr_ring_pages(u32 ring_size, int desc_per_pg)
2577 {
2578         int pages;
2579
2580         pages = ring_size / desc_per_pg;
2581
2582         if (!pages)
2583                 return 1;
2584
2585         pages++;
2586
2587         while (pages & (pages - 1))
2588                 pages++;
2589
2590         return pages;
2591 }
2592
2593 void bnxt_set_tpa_flags(struct bnxt *bp)
2594 {
2595         bp->flags &= ~BNXT_FLAG_TPA;
2596         if (bp->flags & BNXT_FLAG_NO_AGG_RINGS)
2597                 return;
2598         if (bp->dev->features & NETIF_F_LRO)
2599                 bp->flags |= BNXT_FLAG_LRO;
2600         if (bp->dev->features & NETIF_F_GRO)
2601                 bp->flags |= BNXT_FLAG_GRO;
2602 }
2603
2604 /* bp->rx_ring_size, bp->tx_ring_size, dev->mtu, BNXT_FLAG_{G|L}RO flags must
2605  * be set on entry.
2606  */
2607 void bnxt_set_ring_params(struct bnxt *bp)
2608 {
2609         u32 ring_size, rx_size, rx_space;
2610         u32 agg_factor = 0, agg_ring_size = 0;
2611
2612         /* 8 for CRC and VLAN */
2613         rx_size = SKB_DATA_ALIGN(bp->dev->mtu + ETH_HLEN + NET_IP_ALIGN + 8);
2614
2615         rx_space = rx_size + NET_SKB_PAD +
2616                 SKB_DATA_ALIGN(sizeof(struct skb_shared_info));
2617
2618         bp->rx_copy_thresh = BNXT_RX_COPY_THRESH;
2619         ring_size = bp->rx_ring_size;
2620         bp->rx_agg_ring_size = 0;
2621         bp->rx_agg_nr_pages = 0;
2622
2623         if (bp->flags & BNXT_FLAG_TPA)
2624                 agg_factor = min_t(u32, 4, 65536 / BNXT_RX_PAGE_SIZE);
2625
2626         bp->flags &= ~BNXT_FLAG_JUMBO;
2627         if (rx_space > PAGE_SIZE && !(bp->flags & BNXT_FLAG_NO_AGG_RINGS)) {
2628                 u32 jumbo_factor;
2629
2630                 bp->flags |= BNXT_FLAG_JUMBO;
2631                 jumbo_factor = PAGE_ALIGN(bp->dev->mtu - 40) >> PAGE_SHIFT;
2632                 if (jumbo_factor > agg_factor)
2633                         agg_factor = jumbo_factor;
2634         }
2635         agg_ring_size = ring_size * agg_factor;
2636
2637         if (agg_ring_size) {
2638                 bp->rx_agg_nr_pages = bnxt_calc_nr_ring_pages(agg_ring_size,
2639                                                         RX_DESC_CNT);
2640                 if (bp->rx_agg_nr_pages > MAX_RX_AGG_PAGES) {
2641                         u32 tmp = agg_ring_size;
2642
2643                         bp->rx_agg_nr_pages = MAX_RX_AGG_PAGES;
2644                         agg_ring_size = MAX_RX_AGG_PAGES * RX_DESC_CNT - 1;
2645                         netdev_warn(bp->dev, "rx agg ring size %d reduced to %d.\n",
2646                                     tmp, agg_ring_size);
2647                 }
2648                 bp->rx_agg_ring_size = agg_ring_size;
2649                 bp->rx_agg_ring_mask = (bp->rx_agg_nr_pages * RX_DESC_CNT) - 1;
2650                 rx_size = SKB_DATA_ALIGN(BNXT_RX_COPY_THRESH + NET_IP_ALIGN);
2651                 rx_space = rx_size + NET_SKB_PAD +
2652                         SKB_DATA_ALIGN(sizeof(struct skb_shared_info));
2653         }
2654
2655         bp->rx_buf_use_size = rx_size;
2656         bp->rx_buf_size = rx_space;
2657
2658         bp->rx_nr_pages = bnxt_calc_nr_ring_pages(ring_size, RX_DESC_CNT);
2659         bp->rx_ring_mask = (bp->rx_nr_pages * RX_DESC_CNT) - 1;
2660
2661         ring_size = bp->tx_ring_size;
2662         bp->tx_nr_pages = bnxt_calc_nr_ring_pages(ring_size, TX_DESC_CNT);
2663         bp->tx_ring_mask = (bp->tx_nr_pages * TX_DESC_CNT) - 1;
2664
2665         ring_size = bp->rx_ring_size * (2 + agg_factor) + bp->tx_ring_size;
2666         bp->cp_ring_size = ring_size;
2667
2668         bp->cp_nr_pages = bnxt_calc_nr_ring_pages(ring_size, CP_DESC_CNT);
2669         if (bp->cp_nr_pages > MAX_CP_PAGES) {
2670                 bp->cp_nr_pages = MAX_CP_PAGES;
2671                 bp->cp_ring_size = MAX_CP_PAGES * CP_DESC_CNT - 1;
2672                 netdev_warn(bp->dev, "completion ring size %d reduced to %d.\n",
2673                             ring_size, bp->cp_ring_size);
2674         }
2675         bp->cp_bit = bp->cp_nr_pages * CP_DESC_CNT;
2676         bp->cp_ring_mask = bp->cp_bit - 1;
2677 }
2678
2679 int bnxt_set_rx_skb_mode(struct bnxt *bp, bool page_mode)
2680 {
2681         if (page_mode) {
2682                 if (bp->dev->mtu > BNXT_MAX_PAGE_MODE_MTU)
2683                         return -EOPNOTSUPP;
2684                 bp->dev->max_mtu = BNXT_MAX_PAGE_MODE_MTU;
2685                 bp->flags &= ~BNXT_FLAG_AGG_RINGS;
2686                 bp->flags |= BNXT_FLAG_NO_AGG_RINGS | BNXT_FLAG_RX_PAGE_MODE;
2687                 bp->dev->hw_features &= ~NETIF_F_LRO;
2688                 bp->dev->features &= ~NETIF_F_LRO;
2689                 bp->rx_dir = DMA_BIDIRECTIONAL;
2690                 bp->rx_skb_func = bnxt_rx_page_skb;
2691         } else {
2692                 bp->dev->max_mtu = BNXT_MAX_MTU;
2693                 bp->flags &= ~BNXT_FLAG_RX_PAGE_MODE;
2694                 bp->rx_dir = DMA_FROM_DEVICE;
2695                 bp->rx_skb_func = bnxt_rx_skb;
2696         }
2697         return 0;
2698 }
2699
2700 static void bnxt_free_vnic_attributes(struct bnxt *bp)
2701 {
2702         int i;
2703         struct bnxt_vnic_info *vnic;
2704         struct pci_dev *pdev = bp->pdev;
2705
2706         if (!bp->vnic_info)
2707                 return;
2708
2709         for (i = 0; i < bp->nr_vnics; i++) {
2710                 vnic = &bp->vnic_info[i];
2711
2712                 kfree(vnic->fw_grp_ids);
2713                 vnic->fw_grp_ids = NULL;
2714
2715                 kfree(vnic->uc_list);
2716                 vnic->uc_list = NULL;
2717
2718                 if (vnic->mc_list) {
2719                         dma_free_coherent(&pdev->dev, vnic->mc_list_size,
2720                                           vnic->mc_list, vnic->mc_list_mapping);
2721                         vnic->mc_list = NULL;
2722                 }
2723
2724                 if (vnic->rss_table) {
2725                         dma_free_coherent(&pdev->dev, PAGE_SIZE,
2726                                           vnic->rss_table,
2727                                           vnic->rss_table_dma_addr);
2728                         vnic->rss_table = NULL;
2729                 }
2730
2731                 vnic->rss_hash_key = NULL;
2732                 vnic->flags = 0;
2733         }
2734 }
2735
2736 static int bnxt_alloc_vnic_attributes(struct bnxt *bp)
2737 {
2738         int i, rc = 0, size;
2739         struct bnxt_vnic_info *vnic;
2740         struct pci_dev *pdev = bp->pdev;
2741         int max_rings;
2742
2743         for (i = 0; i < bp->nr_vnics; i++) {
2744                 vnic = &bp->vnic_info[i];
2745
2746                 if (vnic->flags & BNXT_VNIC_UCAST_FLAG) {
2747                         int mem_size = (BNXT_MAX_UC_ADDRS - 1) * ETH_ALEN;
2748
2749                         if (mem_size > 0) {
2750                                 vnic->uc_list = kmalloc(mem_size, GFP_KERNEL);
2751                                 if (!vnic->uc_list) {
2752                                         rc = -ENOMEM;
2753                                         goto out;
2754                                 }
2755                         }
2756                 }
2757
2758                 if (vnic->flags & BNXT_VNIC_MCAST_FLAG) {
2759                         vnic->mc_list_size = BNXT_MAX_MC_ADDRS * ETH_ALEN;
2760                         vnic->mc_list =
2761                                 dma_alloc_coherent(&pdev->dev,
2762                                                    vnic->mc_list_size,
2763                                                    &vnic->mc_list_mapping,
2764                                                    GFP_KERNEL);
2765                         if (!vnic->mc_list) {
2766                                 rc = -ENOMEM;
2767                                 goto out;
2768                         }
2769                 }
2770
2771                 if (vnic->flags & BNXT_VNIC_RSS_FLAG)
2772                         max_rings = bp->rx_nr_rings;
2773                 else
2774                         max_rings = 1;
2775
2776                 vnic->fw_grp_ids = kcalloc(max_rings, sizeof(u16), GFP_KERNEL);
2777                 if (!vnic->fw_grp_ids) {
2778                         rc = -ENOMEM;
2779                         goto out;
2780                 }
2781
2782                 if ((bp->flags & BNXT_FLAG_NEW_RSS_CAP) &&
2783                     !(vnic->flags & BNXT_VNIC_RSS_FLAG))
2784                         continue;
2785
2786                 /* Allocate rss table and hash key */
2787                 vnic->rss_table = dma_alloc_coherent(&pdev->dev, PAGE_SIZE,
2788                                                      &vnic->rss_table_dma_addr,
2789                                                      GFP_KERNEL);
2790                 if (!vnic->rss_table) {
2791                         rc = -ENOMEM;
2792                         goto out;
2793                 }
2794
2795                 size = L1_CACHE_ALIGN(HW_HASH_INDEX_SIZE * sizeof(u16));
2796
2797                 vnic->rss_hash_key = ((void *)vnic->rss_table) + size;
2798                 vnic->rss_hash_key_dma_addr = vnic->rss_table_dma_addr + size;
2799         }
2800         return 0;
2801
2802 out:
2803         return rc;
2804 }
2805
2806 static void bnxt_free_hwrm_resources(struct bnxt *bp)
2807 {
2808         struct pci_dev *pdev = bp->pdev;
2809
2810         dma_free_coherent(&pdev->dev, PAGE_SIZE, bp->hwrm_cmd_resp_addr,
2811                           bp->hwrm_cmd_resp_dma_addr);
2812
2813         bp->hwrm_cmd_resp_addr = NULL;
2814         if (bp->hwrm_dbg_resp_addr) {
2815                 dma_free_coherent(&pdev->dev, HWRM_DBG_REG_BUF_SIZE,
2816                                   bp->hwrm_dbg_resp_addr,
2817                                   bp->hwrm_dbg_resp_dma_addr);
2818
2819                 bp->hwrm_dbg_resp_addr = NULL;
2820         }
2821 }
2822
2823 static int bnxt_alloc_hwrm_resources(struct bnxt *bp)
2824 {
2825         struct pci_dev *pdev = bp->pdev;
2826
2827         bp->hwrm_cmd_resp_addr = dma_alloc_coherent(&pdev->dev, PAGE_SIZE,
2828                                                    &bp->hwrm_cmd_resp_dma_addr,
2829                                                    GFP_KERNEL);
2830         if (!bp->hwrm_cmd_resp_addr)
2831                 return -ENOMEM;
2832         bp->hwrm_dbg_resp_addr = dma_alloc_coherent(&pdev->dev,
2833                                                     HWRM_DBG_REG_BUF_SIZE,
2834                                                     &bp->hwrm_dbg_resp_dma_addr,
2835                                                     GFP_KERNEL);
2836         if (!bp->hwrm_dbg_resp_addr)
2837                 netdev_warn(bp->dev, "fail to alloc debug register dma mem\n");
2838
2839         return 0;
2840 }
2841
2842 static void bnxt_free_stats(struct bnxt *bp)
2843 {
2844         u32 size, i;
2845         struct pci_dev *pdev = bp->pdev;
2846
2847         if (bp->hw_rx_port_stats) {
2848                 dma_free_coherent(&pdev->dev, bp->hw_port_stats_size,
2849                                   bp->hw_rx_port_stats,
2850                                   bp->hw_rx_port_stats_map);
2851                 bp->hw_rx_port_stats = NULL;
2852                 bp->flags &= ~BNXT_FLAG_PORT_STATS;
2853         }
2854
2855         if (!bp->bnapi)
2856                 return;
2857
2858         size = sizeof(struct ctx_hw_stats);
2859
2860         for (i = 0; i < bp->cp_nr_rings; i++) {
2861                 struct bnxt_napi *bnapi = bp->bnapi[i];
2862                 struct bnxt_cp_ring_info *cpr = &bnapi->cp_ring;
2863
2864                 if (cpr->hw_stats) {
2865                         dma_free_coherent(&pdev->dev, size, cpr->hw_stats,
2866                                           cpr->hw_stats_map);
2867                         cpr->hw_stats = NULL;
2868                 }
2869         }
2870 }
2871
2872 static int bnxt_alloc_stats(struct bnxt *bp)
2873 {
2874         u32 size, i;
2875         struct pci_dev *pdev = bp->pdev;
2876
2877         size = sizeof(struct ctx_hw_stats);
2878
2879         for (i = 0; i < bp->cp_nr_rings; i++) {
2880                 struct bnxt_napi *bnapi = bp->bnapi[i];
2881                 struct bnxt_cp_ring_info *cpr = &bnapi->cp_ring;
2882
2883                 cpr->hw_stats = dma_alloc_coherent(&pdev->dev, size,
2884                                                    &cpr->hw_stats_map,
2885                                                    GFP_KERNEL);
2886                 if (!cpr->hw_stats)
2887                         return -ENOMEM;
2888
2889                 cpr->hw_stats_ctx_id = INVALID_STATS_CTX_ID;
2890         }
2891
2892         if (BNXT_PF(bp) && bp->chip_num != CHIP_NUM_58700) {
2893                 bp->hw_port_stats_size = sizeof(struct rx_port_stats) +
2894                                          sizeof(struct tx_port_stats) + 1024;
2895
2896                 bp->hw_rx_port_stats =
2897                         dma_alloc_coherent(&pdev->dev, bp->hw_port_stats_size,
2898                                            &bp->hw_rx_port_stats_map,
2899                                            GFP_KERNEL);
2900                 if (!bp->hw_rx_port_stats)
2901                         return -ENOMEM;
2902
2903                 bp->hw_tx_port_stats = (void *)(bp->hw_rx_port_stats + 1) +
2904                                        512;
2905                 bp->hw_tx_port_stats_map = bp->hw_rx_port_stats_map +
2906                                            sizeof(struct rx_port_stats) + 512;
2907                 bp->flags |= BNXT_FLAG_PORT_STATS;
2908         }
2909         return 0;
2910 }
2911
2912 static void bnxt_clear_ring_indices(struct bnxt *bp)
2913 {
2914         int i;
2915
2916         if (!bp->bnapi)
2917                 return;
2918
2919         for (i = 0; i < bp->cp_nr_rings; i++) {
2920                 struct bnxt_napi *bnapi = bp->bnapi[i];
2921                 struct bnxt_cp_ring_info *cpr;
2922                 struct bnxt_rx_ring_info *rxr;
2923                 struct bnxt_tx_ring_info *txr;
2924
2925                 if (!bnapi)
2926                         continue;
2927
2928                 cpr = &bnapi->cp_ring;
2929                 cpr->cp_raw_cons = 0;
2930
2931                 txr = bnapi->tx_ring;
2932                 if (txr) {
2933                         txr->tx_prod = 0;
2934                         txr->tx_cons = 0;
2935                 }
2936
2937                 rxr = bnapi->rx_ring;
2938                 if (rxr) {
2939                         rxr->rx_prod = 0;
2940                         rxr->rx_agg_prod = 0;
2941                         rxr->rx_sw_agg_prod = 0;
2942                         rxr->rx_next_cons = 0;
2943                 }
2944         }
2945 }
2946
2947 static void bnxt_free_ntp_fltrs(struct bnxt *bp, bool irq_reinit)
2948 {
2949 #ifdef CONFIG_RFS_ACCEL
2950         int i;
2951
2952         /* Under rtnl_lock and all our NAPIs have been disabled.  It's
2953          * safe to delete the hash table.
2954          */
2955         for (i = 0; i < BNXT_NTP_FLTR_HASH_SIZE; i++) {
2956                 struct hlist_head *head;
2957                 struct hlist_node *tmp;
2958                 struct bnxt_ntuple_filter *fltr;
2959
2960                 head = &bp->ntp_fltr_hash_tbl[i];
2961                 hlist_for_each_entry_safe(fltr, tmp, head, hash) {
2962                         hlist_del(&fltr->hash);
2963                         kfree(fltr);
2964                 }
2965         }
2966         if (irq_reinit) {
2967                 kfree(bp->ntp_fltr_bmap);
2968                 bp->ntp_fltr_bmap = NULL;
2969         }
2970         bp->ntp_fltr_count = 0;
2971 #endif
2972 }
2973
2974 static int bnxt_alloc_ntp_fltrs(struct bnxt *bp)
2975 {
2976 #ifdef CONFIG_RFS_ACCEL
2977         int i, rc = 0;
2978
2979         if (!(bp->flags & BNXT_FLAG_RFS))
2980                 return 0;
2981
2982         for (i = 0; i < BNXT_NTP_FLTR_HASH_SIZE; i++)
2983                 INIT_HLIST_HEAD(&bp->ntp_fltr_hash_tbl[i]);
2984
2985         bp->ntp_fltr_count = 0;
2986         bp->ntp_fltr_bmap = kzalloc(BITS_TO_LONGS(BNXT_NTP_FLTR_MAX_FLTR),
2987                                     GFP_KERNEL);
2988
2989         if (!bp->ntp_fltr_bmap)
2990                 rc = -ENOMEM;
2991
2992         return rc;
2993 #else
2994         return 0;
2995 #endif
2996 }
2997
2998 static void bnxt_free_mem(struct bnxt *bp, bool irq_re_init)
2999 {
3000         bnxt_free_vnic_attributes(bp);
3001         bnxt_free_tx_rings(bp);
3002         bnxt_free_rx_rings(bp);
3003         bnxt_free_cp_rings(bp);
3004         bnxt_free_ntp_fltrs(bp, irq_re_init);
3005         if (irq_re_init) {
3006                 bnxt_free_stats(bp);
3007                 bnxt_free_ring_grps(bp);
3008                 bnxt_free_vnics(bp);
3009                 kfree(bp->tx_ring_map);
3010                 bp->tx_ring_map = NULL;
3011                 kfree(bp->tx_ring);
3012                 bp->tx_ring = NULL;
3013                 kfree(bp->rx_ring);
3014                 bp->rx_ring = NULL;
3015                 kfree(bp->bnapi);
3016                 bp->bnapi = NULL;
3017         } else {
3018                 bnxt_clear_ring_indices(bp);
3019         }
3020 }
3021
3022 static int bnxt_alloc_mem(struct bnxt *bp, bool irq_re_init)
3023 {
3024         int i, j, rc, size, arr_size;
3025         void *bnapi;
3026
3027         if (irq_re_init) {
3028                 /* Allocate bnapi mem pointer array and mem block for
3029                  * all queues
3030                  */
3031                 arr_size = L1_CACHE_ALIGN(sizeof(struct bnxt_napi *) *
3032                                 bp->cp_nr_rings);
3033                 size = L1_CACHE_ALIGN(sizeof(struct bnxt_napi));
3034                 bnapi = kzalloc(arr_size + size * bp->cp_nr_rings, GFP_KERNEL);
3035                 if (!bnapi)
3036                         return -ENOMEM;
3037
3038                 bp->bnapi = bnapi;
3039                 bnapi += arr_size;
3040                 for (i = 0; i < bp->cp_nr_rings; i++, bnapi += size) {
3041                         bp->bnapi[i] = bnapi;
3042                         bp->bnapi[i]->index = i;
3043                         bp->bnapi[i]->bp = bp;
3044                 }
3045
3046                 bp->rx_ring = kcalloc(bp->rx_nr_rings,
3047                                       sizeof(struct bnxt_rx_ring_info),
3048                                       GFP_KERNEL);
3049                 if (!bp->rx_ring)
3050                         return -ENOMEM;
3051
3052                 for (i = 0; i < bp->rx_nr_rings; i++) {
3053                         bp->rx_ring[i].bnapi = bp->bnapi[i];
3054                         bp->bnapi[i]->rx_ring = &bp->rx_ring[i];
3055                 }
3056
3057                 bp->tx_ring = kcalloc(bp->tx_nr_rings,
3058                                       sizeof(struct bnxt_tx_ring_info),
3059                                       GFP_KERNEL);
3060                 if (!bp->tx_ring)
3061                         return -ENOMEM;
3062
3063                 bp->tx_ring_map = kcalloc(bp->tx_nr_rings, sizeof(u16),
3064                                           GFP_KERNEL);
3065
3066                 if (!bp->tx_ring_map)
3067                         return -ENOMEM;
3068
3069                 if (bp->flags & BNXT_FLAG_SHARED_RINGS)
3070                         j = 0;
3071                 else
3072                         j = bp->rx_nr_rings;
3073
3074                 for (i = 0; i < bp->tx_nr_rings; i++, j++) {
3075                         bp->tx_ring[i].bnapi = bp->bnapi[j];
3076                         bp->bnapi[j]->tx_ring = &bp->tx_ring[i];
3077                         bp->tx_ring_map[i] = bp->tx_nr_rings_xdp + i;
3078                         if (i >= bp->tx_nr_rings_xdp) {
3079                                 bp->tx_ring[i].txq_index = i -
3080                                         bp->tx_nr_rings_xdp;
3081                                 bp->bnapi[j]->tx_int = bnxt_tx_int;
3082                         } else {
3083                                 bp->bnapi[j]->flags |= BNXT_NAPI_FLAG_XDP;
3084                                 bp->bnapi[j]->tx_int = bnxt_tx_int_xdp;
3085                         }
3086                 }
3087
3088                 rc = bnxt_alloc_stats(bp);
3089                 if (rc)
3090                         goto alloc_mem_err;
3091
3092                 rc = bnxt_alloc_ntp_fltrs(bp);
3093                 if (rc)
3094                         goto alloc_mem_err;
3095
3096                 rc = bnxt_alloc_vnics(bp);
3097                 if (rc)
3098                         goto alloc_mem_err;
3099         }
3100
3101         bnxt_init_ring_struct(bp);
3102
3103         rc = bnxt_alloc_rx_rings(bp);
3104         if (rc)
3105                 goto alloc_mem_err;
3106
3107         rc = bnxt_alloc_tx_rings(bp);
3108         if (rc)
3109                 goto alloc_mem_err;
3110
3111         rc = bnxt_alloc_cp_rings(bp);
3112         if (rc)
3113                 goto alloc_mem_err;
3114
3115         bp->vnic_info[0].flags |= BNXT_VNIC_RSS_FLAG | BNXT_VNIC_MCAST_FLAG |
3116                                   BNXT_VNIC_UCAST_FLAG;
3117         rc = bnxt_alloc_vnic_attributes(bp);
3118         if (rc)
3119                 goto alloc_mem_err;
3120         return 0;
3121
3122 alloc_mem_err:
3123         bnxt_free_mem(bp, true);
3124         return rc;
3125 }
3126
3127 static void bnxt_disable_int(struct bnxt *bp)
3128 {
3129         int i;
3130
3131         if (!bp->bnapi)
3132                 return;
3133
3134         for (i = 0; i < bp->cp_nr_rings; i++) {
3135                 struct bnxt_napi *bnapi = bp->bnapi[i];
3136                 struct bnxt_cp_ring_info *cpr = &bnapi->cp_ring;
3137                 struct bnxt_ring_struct *ring = &cpr->cp_ring_struct;
3138
3139                 if (ring->fw_ring_id != INVALID_HW_RING_ID)
3140                         BNXT_CP_DB(cpr->cp_doorbell, cpr->cp_raw_cons);
3141         }
3142 }
3143
3144 static void bnxt_disable_int_sync(struct bnxt *bp)
3145 {
3146         int i;
3147
3148         atomic_inc(&bp->intr_sem);
3149
3150         bnxt_disable_int(bp);
3151         for (i = 0; i < bp->cp_nr_rings; i++)
3152                 synchronize_irq(bp->irq_tbl[i].vector);
3153 }
3154
3155 static void bnxt_enable_int(struct bnxt *bp)
3156 {
3157         int i;
3158
3159         atomic_set(&bp->intr_sem, 0);
3160         for (i = 0; i < bp->cp_nr_rings; i++) {
3161                 struct bnxt_napi *bnapi = bp->bnapi[i];
3162                 struct bnxt_cp_ring_info *cpr = &bnapi->cp_ring;
3163
3164                 BNXT_CP_DB_REARM(cpr->cp_doorbell, cpr->cp_raw_cons);
3165         }
3166 }
3167
3168 void bnxt_hwrm_cmd_hdr_init(struct bnxt *bp, void *request, u16 req_type,
3169                             u16 cmpl_ring, u16 target_id)
3170 {
3171         struct input *req = request;
3172
3173         req->req_type = cpu_to_le16(req_type);
3174         req->cmpl_ring = cpu_to_le16(cmpl_ring);
3175         req->target_id = cpu_to_le16(target_id);
3176         req->resp_addr = cpu_to_le64(bp->hwrm_cmd_resp_dma_addr);
3177 }
3178
3179 static int bnxt_hwrm_do_send_msg(struct bnxt *bp, void *msg, u32 msg_len,
3180                                  int timeout, bool silent)
3181 {
3182         int i, intr_process, rc, tmo_count;
3183         struct input *req = msg;
3184         u32 *data = msg;
3185         __le32 *resp_len, *valid;
3186         u16 cp_ring_id, len = 0;
3187         struct hwrm_err_output *resp = bp->hwrm_cmd_resp_addr;
3188
3189         req->seq_id = cpu_to_le16(bp->hwrm_cmd_seq++);
3190         memset(resp, 0, PAGE_SIZE);
3191         cp_ring_id = le16_to_cpu(req->cmpl_ring);
3192         intr_process = (cp_ring_id == INVALID_HW_RING_ID) ? 0 : 1;
3193
3194         /* Write request msg to hwrm channel */
3195         __iowrite32_copy(bp->bar0, data, msg_len / 4);
3196
3197         for (i = msg_len; i < BNXT_HWRM_MAX_REQ_LEN; i += 4)
3198                 writel(0, bp->bar0 + i);
3199
3200         /* currently supports only one outstanding message */
3201         if (intr_process)
3202                 bp->hwrm_intr_seq_id = le16_to_cpu(req->seq_id);
3203
3204         /* Ring channel doorbell */
3205         writel(1, bp->bar0 + 0x100);
3206
3207         if (!timeout)
3208                 timeout = DFLT_HWRM_CMD_TIMEOUT;
3209
3210         i = 0;
3211         tmo_count = timeout * 40;
3212         if (intr_process) {
3213                 /* Wait until hwrm response cmpl interrupt is processed */
3214                 while (bp->hwrm_intr_seq_id != HWRM_SEQ_ID_INVALID &&
3215                        i++ < tmo_count) {
3216                         usleep_range(25, 40);
3217                 }
3218
3219                 if (bp->hwrm_intr_seq_id != HWRM_SEQ_ID_INVALID) {
3220                         netdev_err(bp->dev, "Resp cmpl intr err msg: 0x%x\n",
3221                                    le16_to_cpu(req->req_type));
3222                         return -1;
3223                 }
3224         } else {
3225                 /* Check if response len is updated */
3226                 resp_len = bp->hwrm_cmd_resp_addr + HWRM_RESP_LEN_OFFSET;
3227                 for (i = 0; i < tmo_count; i++) {
3228                         len = (le32_to_cpu(*resp_len) & HWRM_RESP_LEN_MASK) >>
3229                               HWRM_RESP_LEN_SFT;
3230                         if (len)
3231                                 break;
3232                         usleep_range(25, 40);
3233                 }
3234
3235                 if (i >= tmo_count) {
3236                         netdev_err(bp->dev, "Error (timeout: %d) msg {0x%x 0x%x} len:%d\n",
3237                                    timeout, le16_to_cpu(req->req_type),
3238                                    le16_to_cpu(req->seq_id), len);
3239                         return -1;
3240                 }
3241
3242                 /* Last word of resp contains valid bit */
3243                 valid = bp->hwrm_cmd_resp_addr + len - 4;
3244                 for (i = 0; i < 5; i++) {
3245                         if (le32_to_cpu(*valid) & HWRM_RESP_VALID_MASK)
3246                                 break;
3247                         udelay(1);
3248                 }
3249
3250                 if (i >= 5) {
3251                         netdev_err(bp->dev, "Error (timeout: %d) msg {0x%x 0x%x} len:%d v:%d\n",
3252                                    timeout, le16_to_cpu(req->req_type),
3253                                    le16_to_cpu(req->seq_id), len, *valid);
3254                         return -1;
3255                 }
3256         }
3257
3258         rc = le16_to_cpu(resp->error_code);
3259         if (rc && !silent)
3260                 netdev_err(bp->dev, "hwrm req_type 0x%x seq id 0x%x error 0x%x\n",
3261                            le16_to_cpu(resp->req_type),
3262                            le16_to_cpu(resp->seq_id), rc);
3263         return rc;
3264 }
3265
3266 int _hwrm_send_message(struct bnxt *bp, void *msg, u32 msg_len, int timeout)
3267 {
3268         return bnxt_hwrm_do_send_msg(bp, msg, msg_len, timeout, false);
3269 }
3270
3271 int hwrm_send_message(struct bnxt *bp, void *msg, u32 msg_len, int timeout)
3272 {
3273         int rc;
3274
3275         mutex_lock(&bp->hwrm_cmd_lock);
3276         rc = _hwrm_send_message(bp, msg, msg_len, timeout);
3277         mutex_unlock(&bp->hwrm_cmd_lock);
3278         return rc;
3279 }
3280
3281 int hwrm_send_message_silent(struct bnxt *bp, void *msg, u32 msg_len,
3282                              int timeout)
3283 {
3284         int rc;
3285
3286         mutex_lock(&bp->hwrm_cmd_lock);
3287         rc = bnxt_hwrm_do_send_msg(bp, msg, msg_len, timeout, true);
3288         mutex_unlock(&bp->hwrm_cmd_lock);
3289         return rc;
3290 }
3291
3292 int bnxt_hwrm_func_rgtr_async_events(struct bnxt *bp, unsigned long *bmap,
3293                                      int bmap_size)
3294 {
3295         struct hwrm_func_drv_rgtr_input req = {0};
3296         DECLARE_BITMAP(async_events_bmap, 256);
3297         u32 *events = (u32 *)async_events_bmap;
3298         int i;
3299
3300         bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_FUNC_DRV_RGTR, -1, -1);
3301
3302         req.enables =
3303                 cpu_to_le32(FUNC_DRV_RGTR_REQ_ENABLES_ASYNC_EVENT_FWD);
3304
3305         memset(async_events_bmap, 0, sizeof(async_events_bmap));
3306         for (i = 0; i < ARRAY_SIZE(bnxt_async_events_arr); i++)
3307                 __set_bit(bnxt_async_events_arr[i], async_events_bmap);
3308
3309         if (bmap && bmap_size) {
3310                 for (i = 0; i < bmap_size; i++) {
3311                         if (test_bit(i, bmap))
3312                                 __set_bit(i, async_events_bmap);
3313                 }
3314         }
3315
3316         for (i = 0; i < 8; i++)
3317                 req.async_event_fwd[i] |= cpu_to_le32(events[i]);
3318
3319         return hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT);
3320 }
3321
3322 static int bnxt_hwrm_func_drv_rgtr(struct bnxt *bp)
3323 {
3324         struct hwrm_func_drv_rgtr_input req = {0};
3325
3326         bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_FUNC_DRV_RGTR, -1, -1);
3327
3328         req.enables =
3329                 cpu_to_le32(FUNC_DRV_RGTR_REQ_ENABLES_OS_TYPE |
3330                             FUNC_DRV_RGTR_REQ_ENABLES_VER);
3331
3332         req.os_type = cpu_to_le16(FUNC_DRV_RGTR_REQ_OS_TYPE_LINUX);
3333         req.ver_maj = DRV_VER_MAJ;
3334         req.ver_min = DRV_VER_MIN;
3335         req.ver_upd = DRV_VER_UPD;
3336
3337         if (BNXT_PF(bp)) {
3338                 DECLARE_BITMAP(vf_req_snif_bmap, 256);
3339                 u32 *data = (u32 *)vf_req_snif_bmap;
3340                 int i;
3341
3342                 memset(vf_req_snif_bmap, 0, sizeof(vf_req_snif_bmap));
3343                 for (i = 0; i < ARRAY_SIZE(bnxt_vf_req_snif); i++)
3344                         __set_bit(bnxt_vf_req_snif[i], vf_req_snif_bmap);
3345
3346                 for (i = 0; i < 8; i++)
3347                         req.vf_req_fwd[i] = cpu_to_le32(data[i]);
3348
3349                 req.enables |=
3350                         cpu_to_le32(FUNC_DRV_RGTR_REQ_ENABLES_VF_REQ_FWD);
3351         }
3352
3353         return hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT);
3354 }
3355
3356 static int bnxt_hwrm_func_drv_unrgtr(struct bnxt *bp)
3357 {
3358         struct hwrm_func_drv_unrgtr_input req = {0};
3359
3360         bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_FUNC_DRV_UNRGTR, -1, -1);
3361         return hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT);
3362 }
3363
3364 static int bnxt_hwrm_tunnel_dst_port_free(struct bnxt *bp, u8 tunnel_type)
3365 {
3366         u32 rc = 0;
3367         struct hwrm_tunnel_dst_port_free_input req = {0};
3368
3369         bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_TUNNEL_DST_PORT_FREE, -1, -1);
3370         req.tunnel_type = tunnel_type;
3371
3372         switch (tunnel_type) {
3373         case TUNNEL_DST_PORT_FREE_REQ_TUNNEL_TYPE_VXLAN:
3374                 req.tunnel_dst_port_id = bp->vxlan_fw_dst_port_id;
3375                 break;
3376         case TUNNEL_DST_PORT_FREE_REQ_TUNNEL_TYPE_GENEVE:
3377                 req.tunnel_dst_port_id = bp->nge_fw_dst_port_id;
3378                 break;
3379         default:
3380                 break;
3381         }
3382
3383         rc = hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT);
3384         if (rc)
3385                 netdev_err(bp->dev, "hwrm_tunnel_dst_port_free failed. rc:%d\n",
3386                            rc);
3387         return rc;
3388 }
3389
3390 static int bnxt_hwrm_tunnel_dst_port_alloc(struct bnxt *bp, __be16 port,
3391                                            u8 tunnel_type)
3392 {
3393         u32 rc = 0;
3394         struct hwrm_tunnel_dst_port_alloc_input req = {0};
3395         struct hwrm_tunnel_dst_port_alloc_output *resp = bp->hwrm_cmd_resp_addr;
3396
3397         bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_TUNNEL_DST_PORT_ALLOC, -1, -1);
3398
3399         req.tunnel_type = tunnel_type;
3400         req.tunnel_dst_port_val = port;
3401
3402         mutex_lock(&bp->hwrm_cmd_lock);
3403         rc = _hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT);
3404         if (rc) {
3405                 netdev_err(bp->dev, "hwrm_tunnel_dst_port_alloc failed. rc:%d\n",
3406                            rc);
3407                 goto err_out;
3408         }
3409
3410         switch (tunnel_type) {
3411         case TUNNEL_DST_PORT_ALLOC_REQ_TUNNEL_TYPE_VXLAN:
3412                 bp->vxlan_fw_dst_port_id = resp->tunnel_dst_port_id;
3413                 break;
3414         case TUNNEL_DST_PORT_ALLOC_REQ_TUNNEL_TYPE_GENEVE:
3415                 bp->nge_fw_dst_port_id = resp->tunnel_dst_port_id;
3416                 break;
3417         default:
3418                 break;
3419         }
3420
3421 err_out:
3422         mutex_unlock(&bp->hwrm_cmd_lock);
3423         return rc;
3424 }
3425
3426 static int bnxt_hwrm_cfa_l2_set_rx_mask(struct bnxt *bp, u16 vnic_id)
3427 {
3428         struct hwrm_cfa_l2_set_rx_mask_input req = {0};
3429         struct bnxt_vnic_info *vnic = &bp->vnic_info[vnic_id];
3430
3431         bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_CFA_L2_SET_RX_MASK, -1, -1);
3432         req.vnic_id = cpu_to_le32(vnic->fw_vnic_id);
3433
3434         req.num_mc_entries = cpu_to_le32(vnic->mc_list_count);
3435         req.mc_tbl_addr = cpu_to_le64(vnic->mc_list_mapping);
3436         req.mask = cpu_to_le32(vnic->rx_mask);
3437         return hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT);
3438 }
3439
3440 #ifdef CONFIG_RFS_ACCEL
3441 static int bnxt_hwrm_cfa_ntuple_filter_free(struct bnxt *bp,
3442                                             struct bnxt_ntuple_filter *fltr)
3443 {
3444         struct hwrm_cfa_ntuple_filter_free_input req = {0};
3445
3446         bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_CFA_NTUPLE_FILTER_FREE, -1, -1);
3447         req.ntuple_filter_id = fltr->filter_id;
3448         return hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT);
3449 }
3450
3451 #define BNXT_NTP_FLTR_FLAGS                                     \
3452         (CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_L2_FILTER_ID |     \
3453          CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_ETHERTYPE |        \
3454          CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_SRC_MACADDR |      \
3455          CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_IPADDR_TYPE |      \
3456          CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_SRC_IPADDR |       \
3457          CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_SRC_IPADDR_MASK |  \
3458          CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_DST_IPADDR |       \
3459          CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_DST_IPADDR_MASK |  \
3460          CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_IP_PROTOCOL |      \
3461          CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_SRC_PORT |         \
3462          CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_SRC_PORT_MASK |    \
3463          CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_DST_PORT |         \
3464          CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_DST_PORT_MASK |    \
3465          CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_DST_ID)
3466
3467 #define BNXT_NTP_TUNNEL_FLTR_FLAG                               \
3468                 CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_TUNNEL_TYPE
3469
3470 static int bnxt_hwrm_cfa_ntuple_filter_alloc(struct bnxt *bp,
3471                                              struct bnxt_ntuple_filter *fltr)
3472 {
3473         int rc = 0;
3474         struct hwrm_cfa_ntuple_filter_alloc_input req = {0};
3475         struct hwrm_cfa_ntuple_filter_alloc_output *resp =
3476                 bp->hwrm_cmd_resp_addr;
3477         struct flow_keys *keys = &fltr->fkeys;
3478         struct bnxt_vnic_info *vnic = &bp->vnic_info[fltr->rxq + 1];
3479
3480         bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_CFA_NTUPLE_FILTER_ALLOC, -1, -1);
3481         req.l2_filter_id = bp->vnic_info[0].fw_l2_filter_id[fltr->l2_fltr_idx];
3482
3483         req.enables = cpu_to_le32(BNXT_NTP_FLTR_FLAGS);
3484
3485         req.ethertype = htons(ETH_P_IP);
3486         memcpy(req.src_macaddr, fltr->src_mac_addr, ETH_ALEN);
3487         req.ip_addr_type = CFA_NTUPLE_FILTER_ALLOC_REQ_IP_ADDR_TYPE_IPV4;
3488         req.ip_protocol = keys->basic.ip_proto;
3489
3490         if (keys->basic.n_proto == htons(ETH_P_IPV6)) {
3491                 int i;
3492
3493                 req.ethertype = htons(ETH_P_IPV6);
3494                 req.ip_addr_type =
3495                         CFA_NTUPLE_FILTER_ALLOC_REQ_IP_ADDR_TYPE_IPV6;
3496                 *(struct in6_addr *)&req.src_ipaddr[0] =
3497                         keys->addrs.v6addrs.src;
3498                 *(struct in6_addr *)&req.dst_ipaddr[0] =
3499                         keys->addrs.v6addrs.dst;
3500                 for (i = 0; i < 4; i++) {
3501                         req.src_ipaddr_mask[i] = cpu_to_be32(0xffffffff);
3502                         req.dst_ipaddr_mask[i] = cpu_to_be32(0xffffffff);
3503                 }
3504         } else {
3505                 req.src_ipaddr[0] = keys->addrs.v4addrs.src;
3506                 req.src_ipaddr_mask[0] = cpu_to_be32(0xffffffff);
3507                 req.dst_ipaddr[0] = keys->addrs.v4addrs.dst;
3508                 req.dst_ipaddr_mask[0] = cpu_to_be32(0xffffffff);
3509         }
3510         if (keys->control.flags & FLOW_DIS_ENCAPSULATION) {
3511                 req.enables |= cpu_to_le32(BNXT_NTP_TUNNEL_FLTR_FLAG);
3512                 req.tunnel_type =
3513                         CFA_NTUPLE_FILTER_ALLOC_REQ_TUNNEL_TYPE_ANYTUNNEL;
3514         }
3515
3516         req.src_port = keys->ports.src;
3517         req.src_port_mask = cpu_to_be16(0xffff);
3518         req.dst_port = keys->ports.dst;
3519         req.dst_port_mask = cpu_to_be16(0xffff);
3520
3521         req.dst_id = cpu_to_le16(vnic->fw_vnic_id);
3522         mutex_lock(&bp->hwrm_cmd_lock);
3523         rc = _hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT);
3524         if (!rc)
3525                 fltr->filter_id = resp->ntuple_filter_id;
3526         mutex_unlock(&bp->hwrm_cmd_lock);
3527         return rc;
3528 }
3529 #endif
3530
3531 static int bnxt_hwrm_set_vnic_filter(struct bnxt *bp, u16 vnic_id, u16 idx,
3532                                      u8 *mac_addr)
3533 {
3534         u32 rc = 0;
3535         struct hwrm_cfa_l2_filter_alloc_input req = {0};
3536         struct hwrm_cfa_l2_filter_alloc_output *resp = bp->hwrm_cmd_resp_addr;
3537
3538         bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_CFA_L2_FILTER_ALLOC, -1, -1);
3539         req.flags = cpu_to_le32(CFA_L2_FILTER_ALLOC_REQ_FLAGS_PATH_RX);
3540         if (!BNXT_CHIP_TYPE_NITRO_A0(bp))
3541                 req.flags |=
3542                         cpu_to_le32(CFA_L2_FILTER_ALLOC_REQ_FLAGS_OUTERMOST);
3543         req.dst_id = cpu_to_le16(bp->vnic_info[vnic_id].fw_vnic_id);
3544         req.enables =
3545                 cpu_to_le32(CFA_L2_FILTER_ALLOC_REQ_ENABLES_L2_ADDR |
3546                             CFA_L2_FILTER_ALLOC_REQ_ENABLES_DST_ID |
3547                             CFA_L2_FILTER_ALLOC_REQ_ENABLES_L2_ADDR_MASK);
3548         memcpy(req.l2_addr, mac_addr, ETH_ALEN);
3549         req.l2_addr_mask[0] = 0xff;
3550         req.l2_addr_mask[1] = 0xff;
3551         req.l2_addr_mask[2] = 0xff;
3552         req.l2_addr_mask[3] = 0xff;
3553         req.l2_addr_mask[4] = 0xff;
3554         req.l2_addr_mask[5] = 0xff;
3555
3556         mutex_lock(&bp->hwrm_cmd_lock);
3557         rc = _hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT);
3558         if (!rc)
3559                 bp->vnic_info[vnic_id].fw_l2_filter_id[idx] =
3560                                                         resp->l2_filter_id;
3561         mutex_unlock(&bp->hwrm_cmd_lock);
3562         return rc;
3563 }
3564
3565 static int bnxt_hwrm_clear_vnic_filter(struct bnxt *bp)
3566 {
3567         u16 i, j, num_of_vnics = 1; /* only vnic 0 supported */
3568         int rc = 0;
3569
3570         /* Any associated ntuple filters will also be cleared by firmware. */
3571         mutex_lock(&bp->hwrm_cmd_lock);
3572         for (i = 0; i < num_of_vnics; i++) {
3573                 struct bnxt_vnic_info *vnic = &bp->vnic_info[i];
3574
3575                 for (j = 0; j < vnic->uc_filter_count; j++) {
3576                         struct hwrm_cfa_l2_filter_free_input req = {0};
3577
3578                         bnxt_hwrm_cmd_hdr_init(bp, &req,
3579                                                HWRM_CFA_L2_FILTER_FREE, -1, -1);
3580
3581                         req.l2_filter_id = vnic->fw_l2_filter_id[j];
3582
3583                         rc = _hwrm_send_message(bp, &req, sizeof(req),
3584                                                 HWRM_CMD_TIMEOUT);
3585                 }
3586                 vnic->uc_filter_count = 0;
3587         }
3588         mutex_unlock(&bp->hwrm_cmd_lock);
3589
3590         return rc;
3591 }
3592
3593 static int bnxt_hwrm_vnic_set_tpa(struct bnxt *bp, u16 vnic_id, u32 tpa_flags)
3594 {
3595         struct bnxt_vnic_info *vnic = &bp->vnic_info[vnic_id];
3596         struct hwrm_vnic_tpa_cfg_input req = {0};
3597
3598         bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_VNIC_TPA_CFG, -1, -1);
3599
3600         if (tpa_flags) {
3601                 u16 mss = bp->dev->mtu - 40;
3602                 u32 nsegs, n, segs = 0, flags;
3603
3604                 flags = VNIC_TPA_CFG_REQ_FLAGS_TPA |
3605                         VNIC_TPA_CFG_REQ_FLAGS_ENCAP_TPA |
3606                         VNIC_TPA_CFG_REQ_FLAGS_RSC_WND_UPDATE |
3607                         VNIC_TPA_CFG_REQ_FLAGS_AGG_WITH_ECN |
3608                         VNIC_TPA_CFG_REQ_FLAGS_AGG_WITH_SAME_GRE_SEQ;
3609                 if (tpa_flags & BNXT_FLAG_GRO)
3610                         flags |= VNIC_TPA_CFG_REQ_FLAGS_GRO;
3611
3612                 req.flags = cpu_to_le32(flags);
3613
3614                 req.enables =
3615                         cpu_to_le32(VNIC_TPA_CFG_REQ_ENABLES_MAX_AGG_SEGS |
3616                                     VNIC_TPA_CFG_REQ_ENABLES_MAX_AGGS |
3617                                     VNIC_TPA_CFG_REQ_ENABLES_MIN_AGG_LEN);
3618
3619                 /* Number of segs are log2 units, and first packet is not
3620                  * included as part of this units.
3621                  */
3622                 if (mss <= BNXT_RX_PAGE_SIZE) {
3623                         n = BNXT_RX_PAGE_SIZE / mss;
3624                         nsegs = (MAX_SKB_FRAGS - 1) * n;
3625                 } else {
3626                         n = mss / BNXT_RX_PAGE_SIZE;
3627                         if (mss & (BNXT_RX_PAGE_SIZE - 1))
3628                                 n++;
3629                         nsegs = (MAX_SKB_FRAGS - n) / n;
3630                 }
3631
3632                 segs = ilog2(nsegs);
3633                 req.max_agg_segs = cpu_to_le16(segs);
3634                 req.max_aggs = cpu_to_le16(VNIC_TPA_CFG_REQ_MAX_AGGS_MAX);
3635
3636                 req.min_agg_len = cpu_to_le32(512);
3637         }
3638         req.vnic_id = cpu_to_le16(vnic->fw_vnic_id);
3639
3640         return hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT);
3641 }
3642
3643 static int bnxt_hwrm_vnic_set_rss(struct bnxt *bp, u16 vnic_id, bool set_rss)
3644 {
3645         u32 i, j, max_rings;
3646         struct bnxt_vnic_info *vnic = &bp->vnic_info[vnic_id];
3647         struct hwrm_vnic_rss_cfg_input req = {0};
3648
3649         if (vnic->fw_rss_cos_lb_ctx[0] == INVALID_HW_RING_ID)
3650                 return 0;
3651
3652         bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_VNIC_RSS_CFG, -1, -1);
3653         if (set_rss) {
3654                 req.hash_type = cpu_to_le32(bp->rss_hash_cfg);
3655                 if (vnic->flags & BNXT_VNIC_RSS_FLAG) {
3656                         if (BNXT_CHIP_TYPE_NITRO_A0(bp))
3657                                 max_rings = bp->rx_nr_rings - 1;
3658                         else
3659                                 max_rings = bp->rx_nr_rings;
3660                 } else {
3661                         max_rings = 1;
3662                 }
3663
3664                 /* Fill the RSS indirection table with ring group ids */
3665                 for (i = 0, j = 0; i < HW_HASH_INDEX_SIZE; i++, j++) {
3666                         if (j == max_rings)
3667                                 j = 0;
3668                         vnic->rss_table[i] = cpu_to_le16(vnic->fw_grp_ids[j]);
3669                 }
3670
3671                 req.ring_grp_tbl_addr = cpu_to_le64(vnic->rss_table_dma_addr);
3672                 req.hash_key_tbl_addr =
3673                         cpu_to_le64(vnic->rss_hash_key_dma_addr);
3674         }
3675         req.rss_ctx_idx = cpu_to_le16(vnic->fw_rss_cos_lb_ctx[0]);
3676         return hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT);
3677 }
3678
3679 static int bnxt_hwrm_vnic_set_hds(struct bnxt *bp, u16 vnic_id)
3680 {
3681         struct bnxt_vnic_info *vnic = &bp->vnic_info[vnic_id];
3682         struct hwrm_vnic_plcmodes_cfg_input req = {0};
3683
3684         bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_VNIC_PLCMODES_CFG, -1, -1);
3685         req.flags = cpu_to_le32(VNIC_PLCMODES_CFG_REQ_FLAGS_JUMBO_PLACEMENT |
3686                                 VNIC_PLCMODES_CFG_REQ_FLAGS_HDS_IPV4 |
3687                                 VNIC_PLCMODES_CFG_REQ_FLAGS_HDS_IPV6);
3688         req.enables =
3689                 cpu_to_le32(VNIC_PLCMODES_CFG_REQ_ENABLES_JUMBO_THRESH_VALID |
3690                             VNIC_PLCMODES_CFG_REQ_ENABLES_HDS_THRESHOLD_VALID);
3691         /* thresholds not implemented in firmware yet */
3692         req.jumbo_thresh = cpu_to_le16(bp->rx_copy_thresh);
3693         req.hds_threshold = cpu_to_le16(bp->rx_copy_thresh);
3694         req.vnic_id = cpu_to_le32(vnic->fw_vnic_id);
3695         return hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT);
3696 }
3697
3698 static void bnxt_hwrm_vnic_ctx_free_one(struct bnxt *bp, u16 vnic_id,
3699                                         u16 ctx_idx)
3700 {
3701         struct hwrm_vnic_rss_cos_lb_ctx_free_input req = {0};
3702
3703         bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_VNIC_RSS_COS_LB_CTX_FREE, -1, -1);
3704         req.rss_cos_lb_ctx_id =
3705                 cpu_to_le16(bp->vnic_info[vnic_id].fw_rss_cos_lb_ctx[ctx_idx]);
3706
3707         hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT);
3708         bp->vnic_info[vnic_id].fw_rss_cos_lb_ctx[ctx_idx] = INVALID_HW_RING_ID;
3709 }
3710
3711 static void bnxt_hwrm_vnic_ctx_free(struct bnxt *bp)
3712 {
3713         int i, j;
3714
3715         for (i = 0; i < bp->nr_vnics; i++) {
3716                 struct bnxt_vnic_info *vnic = &bp->vnic_info[i];
3717
3718                 for (j = 0; j < BNXT_MAX_CTX_PER_VNIC; j++) {
3719                         if (vnic->fw_rss_cos_lb_ctx[j] != INVALID_HW_RING_ID)
3720                                 bnxt_hwrm_vnic_ctx_free_one(bp, i, j);
3721                 }
3722         }
3723         bp->rsscos_nr_ctxs = 0;
3724 }
3725
3726 static int bnxt_hwrm_vnic_ctx_alloc(struct bnxt *bp, u16 vnic_id, u16 ctx_idx)
3727 {
3728         int rc;
3729         struct hwrm_vnic_rss_cos_lb_ctx_alloc_input req = {0};
3730         struct hwrm_vnic_rss_cos_lb_ctx_alloc_output *resp =
3731                                                 bp->hwrm_cmd_resp_addr;
3732
3733         bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_VNIC_RSS_COS_LB_CTX_ALLOC, -1,
3734                                -1);
3735
3736         mutex_lock(&bp->hwrm_cmd_lock);
3737         rc = _hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT);
3738         if (!rc)
3739                 bp->vnic_info[vnic_id].fw_rss_cos_lb_ctx[ctx_idx] =
3740                         le16_to_cpu(resp->rss_cos_lb_ctx_id);
3741         mutex_unlock(&bp->hwrm_cmd_lock);
3742
3743         return rc;
3744 }
3745
3746 int bnxt_hwrm_vnic_cfg(struct bnxt *bp, u16 vnic_id)
3747 {
3748         unsigned int ring = 0, grp_idx;
3749         struct bnxt_vnic_info *vnic = &bp->vnic_info[vnic_id];
3750         struct hwrm_vnic_cfg_input req = {0};
3751         u16 def_vlan = 0;
3752
3753         bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_VNIC_CFG, -1, -1);
3754
3755         req.enables = cpu_to_le32(VNIC_CFG_REQ_ENABLES_DFLT_RING_GRP);
3756         /* Only RSS support for now TBD: COS & LB */
3757         if (vnic->fw_rss_cos_lb_ctx[0] != INVALID_HW_RING_ID) {
3758                 req.rss_rule = cpu_to_le16(vnic->fw_rss_cos_lb_ctx[0]);
3759                 req.enables |= cpu_to_le32(VNIC_CFG_REQ_ENABLES_RSS_RULE |
3760                                            VNIC_CFG_REQ_ENABLES_MRU);
3761         } else if (vnic->flags & BNXT_VNIC_RFS_NEW_RSS_FLAG) {
3762                 req.rss_rule =
3763                         cpu_to_le16(bp->vnic_info[0].fw_rss_cos_lb_ctx[0]);
3764                 req.enables |= cpu_to_le32(VNIC_CFG_REQ_ENABLES_RSS_RULE |
3765                                            VNIC_CFG_REQ_ENABLES_MRU);
3766                 req.flags |= cpu_to_le32(VNIC_CFG_REQ_FLAGS_RSS_DFLT_CR_MODE);
3767         } else {
3768                 req.rss_rule = cpu_to_le16(0xffff);
3769         }
3770
3771         if (BNXT_CHIP_TYPE_NITRO_A0(bp) &&
3772             (vnic->fw_rss_cos_lb_ctx[0] != INVALID_HW_RING_ID)) {
3773                 req.cos_rule = cpu_to_le16(vnic->fw_rss_cos_lb_ctx[1]);
3774                 req.enables |= cpu_to_le32(VNIC_CFG_REQ_ENABLES_COS_RULE);
3775         } else {
3776                 req.cos_rule = cpu_to_le16(0xffff);
3777         }
3778
3779         if (vnic->flags & BNXT_VNIC_RSS_FLAG)
3780                 ring = 0;
3781         else if (vnic->flags & BNXT_VNIC_RFS_FLAG)
3782                 ring = vnic_id - 1;
3783         else if ((vnic_id == 1) && BNXT_CHIP_TYPE_NITRO_A0(bp))
3784                 ring = bp->rx_nr_rings - 1;
3785
3786         grp_idx = bp->rx_ring[ring].bnapi->index;
3787         req.vnic_id = cpu_to_le16(vnic->fw_vnic_id);
3788         req.dflt_ring_grp = cpu_to_le16(bp->grp_info[grp_idx].fw_grp_id);
3789
3790         req.lb_rule = cpu_to_le16(0xffff);
3791         req.mru = cpu_to_le16(bp->dev->mtu + ETH_HLEN + ETH_FCS_LEN +
3792                               VLAN_HLEN);
3793
3794 #ifdef CONFIG_BNXT_SRIOV
3795         if (BNXT_VF(bp))
3796                 def_vlan = bp->vf.vlan;
3797 #endif
3798         if ((bp->flags & BNXT_FLAG_STRIP_VLAN) || def_vlan)
3799                 req.flags |= cpu_to_le32(VNIC_CFG_REQ_FLAGS_VLAN_STRIP_MODE);
3800         if (!vnic_id && bnxt_ulp_registered(bp->edev, BNXT_ROCE_ULP))
3801                 req.flags |=
3802                         cpu_to_le32(VNIC_CFG_REQ_FLAGS_ROCE_DUAL_VNIC_MODE);
3803
3804         return hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT);
3805 }
3806
3807 static int bnxt_hwrm_vnic_free_one(struct bnxt *bp, u16 vnic_id)
3808 {
3809         u32 rc = 0;
3810
3811         if (bp->vnic_info[vnic_id].fw_vnic_id != INVALID_HW_RING_ID) {
3812                 struct hwrm_vnic_free_input req = {0};
3813
3814                 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_VNIC_FREE, -1, -1);
3815                 req.vnic_id =
3816                         cpu_to_le32(bp->vnic_info[vnic_id].fw_vnic_id);
3817
3818                 rc = hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT);
3819                 if (rc)
3820                         return rc;
3821                 bp->vnic_info[vnic_id].fw_vnic_id = INVALID_HW_RING_ID;
3822         }
3823         return rc;
3824 }
3825
3826 static void bnxt_hwrm_vnic_free(struct bnxt *bp)
3827 {
3828         u16 i;
3829
3830         for (i = 0; i < bp->nr_vnics; i++)
3831                 bnxt_hwrm_vnic_free_one(bp, i);
3832 }
3833
3834 static int bnxt_hwrm_vnic_alloc(struct bnxt *bp, u16 vnic_id,
3835                                 unsigned int start_rx_ring_idx,
3836                                 unsigned int nr_rings)
3837 {
3838         int rc = 0;
3839         unsigned int i, j, grp_idx, end_idx = start_rx_ring_idx + nr_rings;
3840         struct hwrm_vnic_alloc_input req = {0};
3841         struct hwrm_vnic_alloc_output *resp = bp->hwrm_cmd_resp_addr;
3842
3843         /* map ring groups to this vnic */
3844         for (i = start_rx_ring_idx, j = 0; i < end_idx; i++, j++) {
3845                 grp_idx = bp->rx_ring[i].bnapi->index;
3846                 if (bp->grp_info[grp_idx].fw_grp_id == INVALID_HW_RING_ID) {
3847                         netdev_err(bp->dev, "Not enough ring groups avail:%x req:%x\n",
3848                                    j, nr_rings);
3849                         break;
3850                 }
3851                 bp->vnic_info[vnic_id].fw_grp_ids[j] =
3852                                         bp->grp_info[grp_idx].fw_grp_id;
3853         }
3854
3855         bp->vnic_info[vnic_id].fw_rss_cos_lb_ctx[0] = INVALID_HW_RING_ID;
3856         bp->vnic_info[vnic_id].fw_rss_cos_lb_ctx[1] = INVALID_HW_RING_ID;
3857         if (vnic_id == 0)
3858                 req.flags = cpu_to_le32(VNIC_ALLOC_REQ_FLAGS_DEFAULT);
3859
3860         bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_VNIC_ALLOC, -1, -1);
3861
3862         mutex_lock(&bp->hwrm_cmd_lock);
3863         rc = _hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT);
3864         if (!rc)
3865                 bp->vnic_info[vnic_id].fw_vnic_id = le32_to_cpu(resp->vnic_id);
3866         mutex_unlock(&bp->hwrm_cmd_lock);
3867         return rc;
3868 }
3869
3870 static int bnxt_hwrm_vnic_qcaps(struct bnxt *bp)
3871 {
3872         struct hwrm_vnic_qcaps_output *resp = bp->hwrm_cmd_resp_addr;
3873         struct hwrm_vnic_qcaps_input req = {0};
3874         int rc;
3875
3876         if (bp->hwrm_spec_code < 0x10600)
3877                 return 0;
3878
3879         bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_VNIC_QCAPS, -1, -1);
3880         mutex_lock(&bp->hwrm_cmd_lock);
3881         rc = _hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT);
3882         if (!rc) {
3883                 if (resp->flags &
3884                     cpu_to_le32(VNIC_QCAPS_RESP_FLAGS_RSS_DFLT_CR_CAP))
3885                         bp->flags |= BNXT_FLAG_NEW_RSS_CAP;
3886         }
3887         mutex_unlock(&bp->hwrm_cmd_lock);
3888         return rc;
3889 }
3890
3891 static int bnxt_hwrm_ring_grp_alloc(struct bnxt *bp)
3892 {
3893         u16 i;
3894         u32 rc = 0;
3895
3896         mutex_lock(&bp->hwrm_cmd_lock);
3897         for (i = 0; i < bp->rx_nr_rings; i++) {
3898                 struct hwrm_ring_grp_alloc_input req = {0};
3899                 struct hwrm_ring_grp_alloc_output *resp =
3900                                         bp->hwrm_cmd_resp_addr;
3901                 unsigned int grp_idx = bp->rx_ring[i].bnapi->index;
3902
3903                 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_RING_GRP_ALLOC, -1, -1);
3904
3905                 req.cr = cpu_to_le16(bp->grp_info[grp_idx].cp_fw_ring_id);
3906                 req.rr = cpu_to_le16(bp->grp_info[grp_idx].rx_fw_ring_id);
3907                 req.ar = cpu_to_le16(bp->grp_info[grp_idx].agg_fw_ring_id);
3908                 req.sc = cpu_to_le16(bp->grp_info[grp_idx].fw_stats_ctx);
3909
3910                 rc = _hwrm_send_message(bp, &req, sizeof(req),
3911                                         HWRM_CMD_TIMEOUT);
3912                 if (rc)
3913                         break;
3914
3915                 bp->grp_info[grp_idx].fw_grp_id =
3916                         le32_to_cpu(resp->ring_group_id);
3917         }
3918         mutex_unlock(&bp->hwrm_cmd_lock);
3919         return rc;
3920 }
3921
3922 static int bnxt_hwrm_ring_grp_free(struct bnxt *bp)
3923 {
3924         u16 i;
3925         u32 rc = 0;
3926         struct hwrm_ring_grp_free_input req = {0};
3927
3928         if (!bp->grp_info)
3929                 return 0;
3930
3931         bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_RING_GRP_FREE, -1, -1);
3932
3933         mutex_lock(&bp->hwrm_cmd_lock);
3934         for (i = 0; i < bp->cp_nr_rings; i++) {
3935                 if (bp->grp_info[i].fw_grp_id == INVALID_HW_RING_ID)
3936                         continue;
3937                 req.ring_group_id =
3938                         cpu_to_le32(bp->grp_info[i].fw_grp_id);
3939
3940                 rc = _hwrm_send_message(bp, &req, sizeof(req),
3941                                         HWRM_CMD_TIMEOUT);
3942                 if (rc)
3943                         break;
3944                 bp->grp_info[i].fw_grp_id = INVALID_HW_RING_ID;
3945         }
3946         mutex_unlock(&bp->hwrm_cmd_lock);
3947         return rc;
3948 }
3949
3950 static int hwrm_ring_alloc_send_msg(struct bnxt *bp,
3951                                     struct bnxt_ring_struct *ring,
3952                                     u32 ring_type, u32 map_index,
3953                                     u32 stats_ctx_id)
3954 {
3955         int rc = 0, err = 0;
3956         struct hwrm_ring_alloc_input req = {0};
3957         struct hwrm_ring_alloc_output *resp = bp->hwrm_cmd_resp_addr;
3958         u16 ring_id;
3959
3960         bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_RING_ALLOC, -1, -1);
3961
3962         req.enables = 0;
3963         if (ring->nr_pages > 1) {
3964                 req.page_tbl_addr = cpu_to_le64(ring->pg_tbl_map);
3965                 /* Page size is in log2 units */
3966                 req.page_size = BNXT_PAGE_SHIFT;
3967                 req.page_tbl_depth = 1;
3968         } else {
3969                 req.page_tbl_addr =  cpu_to_le64(ring->dma_arr[0]);
3970         }
3971         req.fbo = 0;
3972         /* Association of ring index with doorbell index and MSIX number */
3973         req.logical_id = cpu_to_le16(map_index);
3974
3975         switch (ring_type) {
3976         case HWRM_RING_ALLOC_TX:
3977                 req.ring_type = RING_ALLOC_REQ_RING_TYPE_TX;
3978                 /* Association of transmit ring with completion ring */
3979                 req.cmpl_ring_id =
3980                         cpu_to_le16(bp->grp_info[map_index].cp_fw_ring_id);
3981                 req.length = cpu_to_le32(bp->tx_ring_mask + 1);
3982                 req.stat_ctx_id = cpu_to_le32(stats_ctx_id);
3983                 req.queue_id = cpu_to_le16(ring->queue_id);
3984                 break;
3985         case HWRM_RING_ALLOC_RX:
3986                 req.ring_type = RING_ALLOC_REQ_RING_TYPE_RX;
3987                 req.length = cpu_to_le32(bp->rx_ring_mask + 1);
3988                 break;
3989         case HWRM_RING_ALLOC_AGG:
3990                 req.ring_type = RING_ALLOC_REQ_RING_TYPE_RX;
3991                 req.length = cpu_to_le32(bp->rx_agg_ring_mask + 1);
3992                 break;
3993         case HWRM_RING_ALLOC_CMPL:
3994                 req.ring_type = RING_ALLOC_REQ_RING_TYPE_L2_CMPL;
3995                 req.length = cpu_to_le32(bp->cp_ring_mask + 1);
3996                 if (bp->flags & BNXT_FLAG_USING_MSIX)
3997                         req.int_mode = RING_ALLOC_REQ_INT_MODE_MSIX;
3998                 break;
3999         default:
4000                 netdev_err(bp->dev, "hwrm alloc invalid ring type %d\n",
4001                            ring_type);
4002                 return -1;
4003         }
4004
4005         mutex_lock(&bp->hwrm_cmd_lock);
4006         rc = _hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT);
4007         err = le16_to_cpu(resp->error_code);
4008         ring_id = le16_to_cpu(resp->ring_id);
4009         mutex_unlock(&bp->hwrm_cmd_lock);
4010
4011         if (rc || err) {
4012                 switch (ring_type) {
4013                 case RING_FREE_REQ_RING_TYPE_L2_CMPL:
4014                         netdev_err(bp->dev, "hwrm_ring_alloc cp failed. rc:%x err:%x\n",
4015                                    rc, err);
4016                         return -1;
4017
4018                 case RING_FREE_REQ_RING_TYPE_RX:
4019                         netdev_err(bp->dev, "hwrm_ring_alloc rx failed. rc:%x err:%x\n",
4020                                    rc, err);
4021                         return -1;
4022
4023                 case RING_FREE_REQ_RING_TYPE_TX:
4024                         netdev_err(bp->dev, "hwrm_ring_alloc tx failed. rc:%x err:%x\n",
4025                                    rc, err);
4026                         return -1;
4027
4028                 default:
4029                         netdev_err(bp->dev, "Invalid ring\n");
4030                         return -1;
4031                 }
4032         }
4033         ring->fw_ring_id = ring_id;
4034         return rc;
4035 }
4036
4037 static int bnxt_hwrm_set_async_event_cr(struct bnxt *bp, int idx)
4038 {
4039         int rc;
4040
4041         if (BNXT_PF(bp)) {
4042                 struct hwrm_func_cfg_input req = {0};
4043
4044                 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_FUNC_CFG, -1, -1);
4045                 req.fid = cpu_to_le16(0xffff);
4046                 req.enables = cpu_to_le32(FUNC_CFG_REQ_ENABLES_ASYNC_EVENT_CR);
4047                 req.async_event_cr = cpu_to_le16(idx);
4048                 rc = hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT);
4049         } else {
4050                 struct hwrm_func_vf_cfg_input req = {0};
4051
4052                 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_FUNC_VF_CFG, -1, -1);
4053                 req.enables =
4054                         cpu_to_le32(FUNC_VF_CFG_REQ_ENABLES_ASYNC_EVENT_CR);
4055                 req.async_event_cr = cpu_to_le16(idx);
4056                 rc = hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT);
4057         }
4058         return rc;
4059 }
4060
4061 static int bnxt_hwrm_ring_alloc(struct bnxt *bp)
4062 {
4063         int i, rc = 0;
4064
4065         for (i = 0; i < bp->cp_nr_rings; i++) {
4066                 struct bnxt_napi *bnapi = bp->bnapi[i];
4067                 struct bnxt_cp_ring_info *cpr = &bnapi->cp_ring;
4068                 struct bnxt_ring_struct *ring = &cpr->cp_ring_struct;
4069
4070                 cpr->cp_doorbell = bp->bar1 + i * 0x80;
4071                 rc = hwrm_ring_alloc_send_msg(bp, ring, HWRM_RING_ALLOC_CMPL, i,
4072                                               INVALID_STATS_CTX_ID);
4073                 if (rc)
4074                         goto err_out;
4075                 BNXT_CP_DB(cpr->cp_doorbell, cpr->cp_raw_cons);
4076                 bp->grp_info[i].cp_fw_ring_id = ring->fw_ring_id;
4077
4078                 if (!i) {
4079                         rc = bnxt_hwrm_set_async_event_cr(bp, ring->fw_ring_id);
4080                         if (rc)
4081                                 netdev_warn(bp->dev, "Failed to set async event completion ring.\n");
4082                 }
4083         }
4084
4085         for (i = 0; i < bp->tx_nr_rings; i++) {
4086                 struct bnxt_tx_ring_info *txr = &bp->tx_ring[i];
4087                 struct bnxt_ring_struct *ring = &txr->tx_ring_struct;
4088                 u32 map_idx = txr->bnapi->index;
4089                 u16 fw_stats_ctx = bp->grp_info[map_idx].fw_stats_ctx;
4090
4091                 rc = hwrm_ring_alloc_send_msg(bp, ring, HWRM_RING_ALLOC_TX,
4092                                               map_idx, fw_stats_ctx);
4093                 if (rc)
4094                         goto err_out;
4095                 txr->tx_doorbell = bp->bar1 + map_idx * 0x80;
4096         }
4097
4098         for (i = 0; i < bp->rx_nr_rings; i++) {
4099                 struct bnxt_rx_ring_info *rxr = &bp->rx_ring[i];
4100                 struct bnxt_ring_struct *ring = &rxr->rx_ring_struct;
4101                 u32 map_idx = rxr->bnapi->index;
4102
4103                 rc = hwrm_ring_alloc_send_msg(bp, ring, HWRM_RING_ALLOC_RX,
4104                                               map_idx, INVALID_STATS_CTX_ID);
4105                 if (rc)
4106                         goto err_out;
4107                 rxr->rx_doorbell = bp->bar1 + map_idx * 0x80;
4108                 writel(DB_KEY_RX | rxr->rx_prod, rxr->rx_doorbell);
4109                 bp->grp_info[map_idx].rx_fw_ring_id = ring->fw_ring_id;
4110         }
4111
4112         if (bp->flags & BNXT_FLAG_AGG_RINGS) {
4113                 for (i = 0; i < bp->rx_nr_rings; i++) {
4114                         struct bnxt_rx_ring_info *rxr = &bp->rx_ring[i];
4115                         struct bnxt_ring_struct *ring =
4116                                                 &rxr->rx_agg_ring_struct;
4117                         u32 grp_idx = rxr->bnapi->index;
4118                         u32 map_idx = grp_idx + bp->rx_nr_rings;
4119
4120                         rc = hwrm_ring_alloc_send_msg(bp, ring,
4121                                                       HWRM_RING_ALLOC_AGG,
4122                                                       map_idx,
4123                                                       INVALID_STATS_CTX_ID);
4124                         if (rc)
4125                                 goto err_out;
4126
4127                         rxr->rx_agg_doorbell = bp->bar1 + map_idx * 0x80;
4128                         writel(DB_KEY_RX | rxr->rx_agg_prod,
4129                                rxr->rx_agg_doorbell);
4130                         bp->grp_info[grp_idx].agg_fw_ring_id = ring->fw_ring_id;
4131                 }
4132         }
4133 err_out:
4134         return rc;
4135 }
4136
4137 static int hwrm_ring_free_send_msg(struct bnxt *bp,
4138                                    struct bnxt_ring_struct *ring,
4139                                    u32 ring_type, int cmpl_ring_id)
4140 {
4141         int rc;
4142         struct hwrm_ring_free_input req = {0};
4143         struct hwrm_ring_free_output *resp = bp->hwrm_cmd_resp_addr;
4144         u16 error_code;
4145
4146         bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_RING_FREE, cmpl_ring_id, -1);
4147         req.ring_type = ring_type;
4148         req.ring_id = cpu_to_le16(ring->fw_ring_id);
4149
4150         mutex_lock(&bp->hwrm_cmd_lock);
4151         rc = _hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT);
4152         error_code = le16_to_cpu(resp->error_code);
4153         mutex_unlock(&bp->hwrm_cmd_lock);
4154
4155         if (rc || error_code) {
4156                 switch (ring_type) {
4157                 case RING_FREE_REQ_RING_TYPE_L2_CMPL:
4158                         netdev_err(bp->dev, "hwrm_ring_free cp failed. rc:%d\n",
4159                                    rc);
4160                         return rc;
4161                 case RING_FREE_REQ_RING_TYPE_RX:
4162                         netdev_err(bp->dev, "hwrm_ring_free rx failed. rc:%d\n",
4163                                    rc);
4164                         return rc;
4165                 case RING_FREE_REQ_RING_TYPE_TX:
4166                         netdev_err(bp->dev, "hwrm_ring_free tx failed. rc:%d\n",
4167                                    rc);
4168                         return rc;
4169                 default:
4170                         netdev_err(bp->dev, "Invalid ring\n");
4171                         return -1;
4172                 }
4173         }
4174         return 0;
4175 }
4176
4177 static void bnxt_hwrm_ring_free(struct bnxt *bp, bool close_path)
4178 {
4179         int i;
4180
4181         if (!bp->bnapi)
4182                 return;
4183
4184         for (i = 0; i < bp->tx_nr_rings; i++) {
4185                 struct bnxt_tx_ring_info *txr = &bp->tx_ring[i];
4186                 struct bnxt_ring_struct *ring = &txr->tx_ring_struct;
4187                 u32 grp_idx = txr->bnapi->index;
4188                 u32 cmpl_ring_id = bp->grp_info[grp_idx].cp_fw_ring_id;
4189
4190                 if (ring->fw_ring_id != INVALID_HW_RING_ID) {
4191                         hwrm_ring_free_send_msg(bp, ring,
4192                                                 RING_FREE_REQ_RING_TYPE_TX,
4193                                                 close_path ? cmpl_ring_id :
4194                                                 INVALID_HW_RING_ID);
4195                         ring->fw_ring_id = INVALID_HW_RING_ID;
4196                 }
4197         }
4198
4199         for (i = 0; i < bp->rx_nr_rings; i++) {
4200                 struct bnxt_rx_ring_info *rxr = &bp->rx_ring[i];
4201                 struct bnxt_ring_struct *ring = &rxr->rx_ring_struct;
4202                 u32 grp_idx = rxr->bnapi->index;
4203                 u32 cmpl_ring_id = bp->grp_info[grp_idx].cp_fw_ring_id;
4204
4205                 if (ring->fw_ring_id != INVALID_HW_RING_ID) {
4206                         hwrm_ring_free_send_msg(bp, ring,
4207                                                 RING_FREE_REQ_RING_TYPE_RX,
4208                                                 close_path ? cmpl_ring_id :
4209                                                 INVALID_HW_RING_ID);
4210                         ring->fw_ring_id = INVALID_HW_RING_ID;
4211                         bp->grp_info[grp_idx].rx_fw_ring_id =
4212                                 INVALID_HW_RING_ID;
4213                 }
4214         }
4215
4216         for (i = 0; i < bp->rx_nr_rings; i++) {
4217                 struct bnxt_rx_ring_info *rxr = &bp->rx_ring[i];
4218                 struct bnxt_ring_struct *ring = &rxr->rx_agg_ring_struct;
4219                 u32 grp_idx = rxr->bnapi->index;
4220                 u32 cmpl_ring_id = bp->grp_info[grp_idx].cp_fw_ring_id;
4221
4222                 if (ring->fw_ring_id != INVALID_HW_RING_ID) {
4223                         hwrm_ring_free_send_msg(bp, ring,
4224                                                 RING_FREE_REQ_RING_TYPE_RX,
4225                                                 close_path ? cmpl_ring_id :
4226                                                 INVALID_HW_RING_ID);
4227                         ring->fw_ring_id = INVALID_HW_RING_ID;
4228                         bp->grp_info[grp_idx].agg_fw_ring_id =
4229                                 INVALID_HW_RING_ID;
4230                 }
4231         }
4232
4233         /* The completion rings are about to be freed.  After that the
4234          * IRQ doorbell will not work anymore.  So we need to disable
4235          * IRQ here.
4236          */
4237         bnxt_disable_int_sync(bp);
4238
4239         for (i = 0; i < bp->cp_nr_rings; i++) {
4240                 struct bnxt_napi *bnapi = bp->bnapi[i];
4241                 struct bnxt_cp_ring_info *cpr = &bnapi->cp_ring;
4242                 struct bnxt_ring_struct *ring = &cpr->cp_ring_struct;
4243
4244                 if (ring->fw_ring_id != INVALID_HW_RING_ID) {
4245                         hwrm_ring_free_send_msg(bp, ring,
4246                                                 RING_FREE_REQ_RING_TYPE_L2_CMPL,
4247                                                 INVALID_HW_RING_ID);
4248                         ring->fw_ring_id = INVALID_HW_RING_ID;
4249                         bp->grp_info[i].cp_fw_ring_id = INVALID_HW_RING_ID;
4250                 }
4251         }
4252 }
4253
4254 /* Caller must hold bp->hwrm_cmd_lock */
4255 int __bnxt_hwrm_get_tx_rings(struct bnxt *bp, u16 fid, int *tx_rings)
4256 {
4257         struct hwrm_func_qcfg_output *resp = bp->hwrm_cmd_resp_addr;
4258         struct hwrm_func_qcfg_input req = {0};
4259         int rc;
4260
4261         if (bp->hwrm_spec_code < 0x10601)
4262                 return 0;
4263
4264         bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_FUNC_QCFG, -1, -1);
4265         req.fid = cpu_to_le16(fid);
4266         rc = _hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT);
4267         if (!rc)
4268                 *tx_rings = le16_to_cpu(resp->alloc_tx_rings);
4269
4270         return rc;
4271 }
4272
4273 static int bnxt_hwrm_reserve_tx_rings(struct bnxt *bp, int *tx_rings)
4274 {
4275         struct hwrm_func_cfg_input req = {0};
4276         int rc;
4277
4278         if (bp->hwrm_spec_code < 0x10601)
4279                 return 0;
4280
4281         if (BNXT_VF(bp))
4282                 return 0;
4283
4284         bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_FUNC_CFG, -1, -1);
4285         req.fid = cpu_to_le16(0xffff);
4286         req.enables = cpu_to_le32(FUNC_CFG_REQ_ENABLES_NUM_TX_RINGS);
4287         req.num_tx_rings = cpu_to_le16(*tx_rings);
4288         rc = hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT);
4289         if (rc)
4290                 return rc;
4291
4292         mutex_lock(&bp->hwrm_cmd_lock);
4293         rc = __bnxt_hwrm_get_tx_rings(bp, 0xffff, tx_rings);
4294         mutex_unlock(&bp->hwrm_cmd_lock);
4295         return rc;
4296 }
4297
4298 static void bnxt_hwrm_set_coal_params(struct bnxt *bp, u32 max_bufs,
4299         u32 buf_tmrs, u16 flags,
4300         struct hwrm_ring_cmpl_ring_cfg_aggint_params_input *req)
4301 {
4302         req->flags = cpu_to_le16(flags);
4303         req->num_cmpl_dma_aggr = cpu_to_le16((u16)max_bufs);
4304         req->num_cmpl_dma_aggr_during_int = cpu_to_le16(max_bufs >> 16);
4305         req->cmpl_aggr_dma_tmr = cpu_to_le16((u16)buf_tmrs);
4306         req->cmpl_aggr_dma_tmr_during_int = cpu_to_le16(buf_tmrs >> 16);
4307         /* Minimum time between 2 interrupts set to buf_tmr x 2 */
4308         req->int_lat_tmr_min = cpu_to_le16((u16)buf_tmrs * 2);
4309         req->int_lat_tmr_max = cpu_to_le16((u16)buf_tmrs * 4);
4310         req->num_cmpl_aggr_int = cpu_to_le16((u16)max_bufs * 4);
4311 }
4312
4313 int bnxt_hwrm_set_coal(struct bnxt *bp)
4314 {
4315         int i, rc = 0;
4316         struct hwrm_ring_cmpl_ring_cfg_aggint_params_input req_rx = {0},
4317                                                            req_tx = {0}, *req;
4318         u16 max_buf, max_buf_irq;
4319         u16 buf_tmr, buf_tmr_irq;
4320         u32 flags;
4321
4322         bnxt_hwrm_cmd_hdr_init(bp, &req_rx,
4323                                HWRM_RING_CMPL_RING_CFG_AGGINT_PARAMS, -1, -1);
4324         bnxt_hwrm_cmd_hdr_init(bp, &req_tx,
4325                                HWRM_RING_CMPL_RING_CFG_AGGINT_PARAMS, -1, -1);
4326
4327         /* Each rx completion (2 records) should be DMAed immediately.
4328          * DMA 1/4 of the completion buffers at a time.
4329          */
4330         max_buf = min_t(u16, bp->rx_coal_bufs / 4, 2);
4331         /* max_buf must not be zero */
4332         max_buf = clamp_t(u16, max_buf, 1, 63);
4333         max_buf_irq = clamp_t(u16, bp->rx_coal_bufs_irq, 1, 63);
4334         buf_tmr = BNXT_USEC_TO_COAL_TIMER(bp->rx_coal_ticks);
4335         /* buf timer set to 1/4 of interrupt timer */
4336         buf_tmr = max_t(u16, buf_tmr / 4, 1);
4337         buf_tmr_irq = BNXT_USEC_TO_COAL_TIMER(bp->rx_coal_ticks_irq);
4338         buf_tmr_irq = max_t(u16, buf_tmr_irq, 1);
4339
4340         flags = RING_CMPL_RING_CFG_AGGINT_PARAMS_REQ_FLAGS_TIMER_RESET;
4341
4342         /* RING_IDLE generates more IRQs for lower latency.  Enable it only
4343          * if coal_ticks is less than 25 us.
4344          */
4345         if (bp->rx_coal_ticks < 25)
4346                 flags |= RING_CMPL_RING_CFG_AGGINT_PARAMS_REQ_FLAGS_RING_IDLE;
4347
4348         bnxt_hwrm_set_coal_params(bp, max_buf_irq << 16 | max_buf,
4349                                   buf_tmr_irq << 16 | buf_tmr, flags, &req_rx);
4350
4351         /* max_buf must not be zero */
4352         max_buf = clamp_t(u16, bp->tx_coal_bufs, 1, 63);
4353         max_buf_irq = clamp_t(u16, bp->tx_coal_bufs_irq, 1, 63);
4354         buf_tmr = BNXT_USEC_TO_COAL_TIMER(bp->tx_coal_ticks);
4355         /* buf timer set to 1/4 of interrupt timer */
4356         buf_tmr = max_t(u16, buf_tmr / 4, 1);
4357         buf_tmr_irq = BNXT_USEC_TO_COAL_TIMER(bp->tx_coal_ticks_irq);
4358         buf_tmr_irq = max_t(u16, buf_tmr_irq, 1);
4359
4360         flags = RING_CMPL_RING_CFG_AGGINT_PARAMS_REQ_FLAGS_TIMER_RESET;
4361         bnxt_hwrm_set_coal_params(bp, max_buf_irq << 16 | max_buf,
4362                                   buf_tmr_irq << 16 | buf_tmr, flags, &req_tx);
4363
4364         mutex_lock(&bp->hwrm_cmd_lock);
4365         for (i = 0; i < bp->cp_nr_rings; i++) {
4366                 struct bnxt_napi *bnapi = bp->bnapi[i];
4367
4368                 req = &req_rx;
4369                 if (!bnapi->rx_ring)
4370                         req = &req_tx;
4371                 req->ring_id = cpu_to_le16(bp->grp_info[i].cp_fw_ring_id);
4372
4373                 rc = _hwrm_send_message(bp, req, sizeof(*req),
4374                                         HWRM_CMD_TIMEOUT);
4375                 if (rc)
4376                         break;
4377         }
4378         mutex_unlock(&bp->hwrm_cmd_lock);
4379         return rc;
4380 }
4381
4382 static int bnxt_hwrm_stat_ctx_free(struct bnxt *bp)
4383 {
4384         int rc = 0, i;
4385         struct hwrm_stat_ctx_free_input req = {0};
4386
4387         if (!bp->bnapi)
4388                 return 0;
4389
4390         if (BNXT_CHIP_TYPE_NITRO_A0(bp))
4391                 return 0;
4392
4393         bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_STAT_CTX_FREE, -1, -1);
4394
4395         mutex_lock(&bp->hwrm_cmd_lock);
4396         for (i = 0; i < bp->cp_nr_rings; i++) {
4397                 struct bnxt_napi *bnapi = bp->bnapi[i];
4398                 struct bnxt_cp_ring_info *cpr = &bnapi->cp_ring;
4399
4400                 if (cpr->hw_stats_ctx_id != INVALID_STATS_CTX_ID) {
4401                         req.stat_ctx_id = cpu_to_le32(cpr->hw_stats_ctx_id);
4402
4403                         rc = _hwrm_send_message(bp, &req, sizeof(req),
4404                                                 HWRM_CMD_TIMEOUT);
4405                         if (rc)
4406                                 break;
4407
4408                         cpr->hw_stats_ctx_id = INVALID_STATS_CTX_ID;
4409                 }
4410         }
4411         mutex_unlock(&bp->hwrm_cmd_lock);
4412         return rc;
4413 }
4414
4415 static int bnxt_hwrm_stat_ctx_alloc(struct bnxt *bp)
4416 {
4417         int rc = 0, i;
4418         struct hwrm_stat_ctx_alloc_input req = {0};
4419         struct hwrm_stat_ctx_alloc_output *resp = bp->hwrm_cmd_resp_addr;
4420
4421         if (BNXT_CHIP_TYPE_NITRO_A0(bp))
4422                 return 0;
4423
4424         bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_STAT_CTX_ALLOC, -1, -1);
4425
4426         req.update_period_ms = cpu_to_le32(bp->stats_coal_ticks / 1000);
4427
4428         mutex_lock(&bp->hwrm_cmd_lock);
4429         for (i = 0; i < bp->cp_nr_rings; i++) {
4430                 struct bnxt_napi *bnapi = bp->bnapi[i];
4431                 struct bnxt_cp_ring_info *cpr = &bnapi->cp_ring;
4432
4433                 req.stats_dma_addr = cpu_to_le64(cpr->hw_stats_map);
4434
4435                 rc = _hwrm_send_message(bp, &req, sizeof(req),
4436                                         HWRM_CMD_TIMEOUT);
4437                 if (rc)
4438                         break;
4439
4440                 cpr->hw_stats_ctx_id = le32_to_cpu(resp->stat_ctx_id);
4441
4442                 bp->grp_info[i].fw_stats_ctx = cpr->hw_stats_ctx_id;
4443         }
4444         mutex_unlock(&bp->hwrm_cmd_lock);
4445         return rc;
4446 }
4447
4448 static int bnxt_hwrm_func_qcfg(struct bnxt *bp)
4449 {
4450         struct hwrm_func_qcfg_input req = {0};
4451         struct hwrm_func_qcfg_output *resp = bp->hwrm_cmd_resp_addr;
4452         int rc;
4453
4454         bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_FUNC_QCFG, -1, -1);
4455         req.fid = cpu_to_le16(0xffff);
4456         mutex_lock(&bp->hwrm_cmd_lock);
4457         rc = _hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT);
4458         if (rc)
4459                 goto func_qcfg_exit;
4460
4461 #ifdef CONFIG_BNXT_SRIOV
4462         if (BNXT_VF(bp)) {
4463                 struct bnxt_vf_info *vf = &bp->vf;
4464
4465                 vf->vlan = le16_to_cpu(resp->vlan) & VLAN_VID_MASK;
4466         }
4467 #endif
4468         switch (resp->port_partition_type) {
4469         case FUNC_QCFG_RESP_PORT_PARTITION_TYPE_NPAR1_0:
4470         case FUNC_QCFG_RESP_PORT_PARTITION_TYPE_NPAR1_5:
4471         case FUNC_QCFG_RESP_PORT_PARTITION_TYPE_NPAR2_0:
4472                 bp->port_partition_type = resp->port_partition_type;
4473                 break;
4474         }
4475
4476 func_qcfg_exit:
4477         mutex_unlock(&bp->hwrm_cmd_lock);
4478         return rc;
4479 }
4480
4481 static int bnxt_hwrm_func_qcaps(struct bnxt *bp)
4482 {
4483         int rc = 0;
4484         struct hwrm_func_qcaps_input req = {0};
4485         struct hwrm_func_qcaps_output *resp = bp->hwrm_cmd_resp_addr;
4486
4487         bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_FUNC_QCAPS, -1, -1);
4488         req.fid = cpu_to_le16(0xffff);
4489
4490         mutex_lock(&bp->hwrm_cmd_lock);
4491         rc = _hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT);
4492         if (rc)
4493                 goto hwrm_func_qcaps_exit;
4494
4495         if (resp->flags & cpu_to_le32(FUNC_QCAPS_RESP_FLAGS_ROCE_V1_SUPPORTED))
4496                 bp->flags |= BNXT_FLAG_ROCEV1_CAP;
4497         if (resp->flags & cpu_to_le32(FUNC_QCAPS_RESP_FLAGS_ROCE_V2_SUPPORTED))
4498                 bp->flags |= BNXT_FLAG_ROCEV2_CAP;
4499
4500         bp->tx_push_thresh = 0;
4501         if (resp->flags &
4502             cpu_to_le32(FUNC_QCAPS_RESP_FLAGS_PUSH_MODE_SUPPORTED))
4503                 bp->tx_push_thresh = BNXT_TX_PUSH_THRESH;
4504
4505         if (BNXT_PF(bp)) {
4506                 struct bnxt_pf_info *pf = &bp->pf;
4507
4508                 pf->fw_fid = le16_to_cpu(resp->fid);
4509                 pf->port_id = le16_to_cpu(resp->port_id);
4510                 bp->dev->dev_port = pf->port_id;
4511                 memcpy(pf->mac_addr, resp->mac_address, ETH_ALEN);
4512                 memcpy(bp->dev->dev_addr, pf->mac_addr, ETH_ALEN);
4513                 pf->max_rsscos_ctxs = le16_to_cpu(resp->max_rsscos_ctx);
4514                 pf->max_cp_rings = le16_to_cpu(resp->max_cmpl_rings);
4515                 pf->max_tx_rings = le16_to_cpu(resp->max_tx_rings);
4516                 pf->max_rx_rings = le16_to_cpu(resp->max_rx_rings);
4517                 pf->max_hw_ring_grps = le32_to_cpu(resp->max_hw_ring_grps);
4518                 if (!pf->max_hw_ring_grps)
4519                         pf->max_hw_ring_grps = pf->max_tx_rings;
4520                 pf->max_l2_ctxs = le16_to_cpu(resp->max_l2_ctxs);
4521                 pf->max_vnics = le16_to_cpu(resp->max_vnics);
4522                 pf->max_stat_ctxs = le16_to_cpu(resp->max_stat_ctx);
4523                 pf->first_vf_id = le16_to_cpu(resp->first_vf_id);
4524                 pf->max_vfs = le16_to_cpu(resp->max_vfs);
4525                 pf->max_encap_records = le32_to_cpu(resp->max_encap_records);
4526                 pf->max_decap_records = le32_to_cpu(resp->max_decap_records);
4527                 pf->max_tx_em_flows = le32_to_cpu(resp->max_tx_em_flows);
4528                 pf->max_tx_wm_flows = le32_to_cpu(resp->max_tx_wm_flows);
4529                 pf->max_rx_em_flows = le32_to_cpu(resp->max_rx_em_flows);
4530                 pf->max_rx_wm_flows = le32_to_cpu(resp->max_rx_wm_flows);
4531         } else {
4532 #ifdef CONFIG_BNXT_SRIOV
4533                 struct bnxt_vf_info *vf = &bp->vf;
4534
4535                 vf->fw_fid = le16_to_cpu(resp->fid);
4536
4537                 vf->max_rsscos_ctxs = le16_to_cpu(resp->max_rsscos_ctx);
4538                 vf->max_cp_rings = le16_to_cpu(resp->max_cmpl_rings);
4539                 vf->max_tx_rings = le16_to_cpu(resp->max_tx_rings);
4540                 vf->max_rx_rings = le16_to_cpu(resp->max_rx_rings);
4541                 vf->max_hw_ring_grps = le32_to_cpu(resp->max_hw_ring_grps);
4542                 if (!vf->max_hw_ring_grps)
4543                         vf->max_hw_ring_grps = vf->max_tx_rings;
4544                 vf->max_l2_ctxs = le16_to_cpu(resp->max_l2_ctxs);
4545                 vf->max_vnics = le16_to_cpu(resp->max_vnics);
4546                 vf->max_stat_ctxs = le16_to_cpu(resp->max_stat_ctx);
4547
4548                 memcpy(vf->mac_addr, resp->mac_address, ETH_ALEN);
4549                 mutex_unlock(&bp->hwrm_cmd_lock);
4550
4551                 if (is_valid_ether_addr(vf->mac_addr)) {
4552                         /* overwrite netdev dev_adr with admin VF MAC */
4553                         memcpy(bp->dev->dev_addr, vf->mac_addr, ETH_ALEN);
4554                 } else {
4555                         eth_hw_addr_random(bp->dev);
4556                         rc = bnxt_approve_mac(bp, bp->dev->dev_addr);
4557                 }
4558                 return rc;
4559 #endif
4560         }
4561
4562 hwrm_func_qcaps_exit:
4563         mutex_unlock(&bp->hwrm_cmd_lock);
4564         return rc;
4565 }
4566
4567 static int bnxt_hwrm_func_reset(struct bnxt *bp)
4568 {
4569         struct hwrm_func_reset_input req = {0};
4570
4571         bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_FUNC_RESET, -1, -1);
4572         req.enables = 0;
4573
4574         return hwrm_send_message(bp, &req, sizeof(req), HWRM_RESET_TIMEOUT);
4575 }
4576
4577 static int bnxt_hwrm_queue_qportcfg(struct bnxt *bp)
4578 {
4579         int rc = 0;
4580         struct hwrm_queue_qportcfg_input req = {0};
4581         struct hwrm_queue_qportcfg_output *resp = bp->hwrm_cmd_resp_addr;
4582         u8 i, *qptr;
4583
4584         bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_QUEUE_QPORTCFG, -1, -1);
4585
4586         mutex_lock(&bp->hwrm_cmd_lock);
4587         rc = _hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT);
4588         if (rc)
4589                 goto qportcfg_exit;
4590
4591         if (!resp->max_configurable_queues) {
4592                 rc = -EINVAL;
4593                 goto qportcfg_exit;
4594         }
4595         bp->max_tc = resp->max_configurable_queues;
4596         bp->max_lltc = resp->max_configurable_lossless_queues;
4597         if (bp->max_tc > BNXT_MAX_QUEUE)
4598                 bp->max_tc = BNXT_MAX_QUEUE;
4599
4600         if (resp->queue_cfg_info & QUEUE_QPORTCFG_RESP_QUEUE_CFG_INFO_ASYM_CFG)
4601                 bp->max_tc = 1;
4602
4603         if (bp->max_lltc > bp->max_tc)
4604                 bp->max_lltc = bp->max_tc;
4605
4606         qptr = &resp->queue_id0;
4607         for (i = 0; i < bp->max_tc; i++) {
4608                 bp->q_info[i].queue_id = *qptr++;
4609                 bp->q_info[i].queue_profile = *qptr++;
4610         }
4611
4612 qportcfg_exit:
4613         mutex_unlock(&bp->hwrm_cmd_lock);
4614         return rc;
4615 }
4616
4617 static int bnxt_hwrm_ver_get(struct bnxt *bp)
4618 {
4619         int rc;
4620         struct hwrm_ver_get_input req = {0};
4621         struct hwrm_ver_get_output *resp = bp->hwrm_cmd_resp_addr;
4622
4623         bp->hwrm_max_req_len = HWRM_MAX_REQ_LEN;
4624         bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_VER_GET, -1, -1);
4625         req.hwrm_intf_maj = HWRM_VERSION_MAJOR;
4626         req.hwrm_intf_min = HWRM_VERSION_MINOR;
4627         req.hwrm_intf_upd = HWRM_VERSION_UPDATE;
4628         mutex_lock(&bp->hwrm_cmd_lock);
4629         rc = _hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT);
4630         if (rc)
4631                 goto hwrm_ver_get_exit;
4632
4633         memcpy(&bp->ver_resp, resp, sizeof(struct hwrm_ver_get_output));
4634
4635         bp->hwrm_spec_code = resp->hwrm_intf_maj << 16 |
4636                              resp->hwrm_intf_min << 8 | resp->hwrm_intf_upd;
4637         if (resp->hwrm_intf_maj < 1) {
4638                 netdev_warn(bp->dev, "HWRM interface %d.%d.%d is older than 1.0.0.\n",
4639                             resp->hwrm_intf_maj, resp->hwrm_intf_min,
4640                             resp->hwrm_intf_upd);
4641                 netdev_warn(bp->dev, "Please update firmware with HWRM interface 1.0.0 or newer.\n");
4642         }
4643         snprintf(bp->fw_ver_str, BC_HWRM_STR_LEN, "%d.%d.%d/%d.%d.%d",
4644                  resp->hwrm_fw_maj, resp->hwrm_fw_min, resp->hwrm_fw_bld,
4645                  resp->hwrm_intf_maj, resp->hwrm_intf_min, resp->hwrm_intf_upd);
4646
4647         bp->hwrm_cmd_timeout = le16_to_cpu(resp->def_req_timeout);
4648         if (!bp->hwrm_cmd_timeout)
4649                 bp->hwrm_cmd_timeout = DFLT_HWRM_CMD_TIMEOUT;
4650
4651         if (resp->hwrm_intf_maj >= 1)
4652                 bp->hwrm_max_req_len = le16_to_cpu(resp->max_req_win_len);
4653
4654         bp->chip_num = le16_to_cpu(resp->chip_num);
4655         if (bp->chip_num == CHIP_NUM_58700 && !resp->chip_rev &&
4656             !resp->chip_metal)
4657                 bp->flags |= BNXT_FLAG_CHIP_NITRO_A0;
4658
4659 hwrm_ver_get_exit:
4660         mutex_unlock(&bp->hwrm_cmd_lock);
4661         return rc;
4662 }
4663
4664 int bnxt_hwrm_fw_set_time(struct bnxt *bp)
4665 {
4666 #if IS_ENABLED(CONFIG_RTC_LIB)
4667         struct hwrm_fw_set_time_input req = {0};
4668         struct rtc_time tm;
4669         struct timeval tv;
4670
4671         if (bp->hwrm_spec_code < 0x10400)
4672                 return -EOPNOTSUPP;
4673
4674         do_gettimeofday(&tv);
4675         rtc_time_to_tm(tv.tv_sec, &tm);
4676         bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_FW_SET_TIME, -1, -1);
4677         req.year = cpu_to_le16(1900 + tm.tm_year);
4678         req.month = 1 + tm.tm_mon;
4679         req.day = tm.tm_mday;
4680         req.hour = tm.tm_hour;
4681         req.minute = tm.tm_min;
4682         req.second = tm.tm_sec;
4683         return hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT);
4684 #else
4685         return -EOPNOTSUPP;
4686 #endif
4687 }
4688
4689 static int bnxt_hwrm_port_qstats(struct bnxt *bp)
4690 {
4691         int rc;
4692         struct bnxt_pf_info *pf = &bp->pf;
4693         struct hwrm_port_qstats_input req = {0};
4694
4695         if (!(bp->flags & BNXT_FLAG_PORT_STATS))
4696                 return 0;
4697
4698         bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_PORT_QSTATS, -1, -1);
4699         req.port_id = cpu_to_le16(pf->port_id);
4700         req.tx_stat_host_addr = cpu_to_le64(bp->hw_tx_port_stats_map);
4701         req.rx_stat_host_addr = cpu_to_le64(bp->hw_rx_port_stats_map);
4702         rc = hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT);
4703         return rc;
4704 }
4705
4706 static void bnxt_hwrm_free_tunnel_ports(struct bnxt *bp)
4707 {
4708         if (bp->vxlan_port_cnt) {
4709                 bnxt_hwrm_tunnel_dst_port_free(
4710                         bp, TUNNEL_DST_PORT_FREE_REQ_TUNNEL_TYPE_VXLAN);
4711         }
4712         bp->vxlan_port_cnt = 0;
4713         if (bp->nge_port_cnt) {
4714                 bnxt_hwrm_tunnel_dst_port_free(
4715                         bp, TUNNEL_DST_PORT_FREE_REQ_TUNNEL_TYPE_GENEVE);
4716         }
4717         bp->nge_port_cnt = 0;
4718 }
4719
4720 static int bnxt_set_tpa(struct bnxt *bp, bool set_tpa)
4721 {
4722         int rc, i;
4723         u32 tpa_flags = 0;
4724
4725         if (set_tpa)
4726                 tpa_flags = bp->flags & BNXT_FLAG_TPA;
4727         for (i = 0; i < bp->nr_vnics; i++) {
4728                 rc = bnxt_hwrm_vnic_set_tpa(bp, i, tpa_flags);
4729                 if (rc) {
4730                         netdev_err(bp->dev, "hwrm vnic set tpa failure rc for vnic %d: %x\n",
4731                                    rc, i);
4732                         return rc;
4733                 }
4734         }
4735         return 0;
4736 }
4737
4738 static void bnxt_hwrm_clear_vnic_rss(struct bnxt *bp)
4739 {
4740         int i;
4741
4742         for (i = 0; i < bp->nr_vnics; i++)
4743                 bnxt_hwrm_vnic_set_rss(bp, i, false);
4744 }
4745
4746 static void bnxt_hwrm_resource_free(struct bnxt *bp, bool close_path,
4747                                     bool irq_re_init)
4748 {
4749         if (bp->vnic_info) {
4750                 bnxt_hwrm_clear_vnic_filter(bp);
4751                 /* clear all RSS setting before free vnic ctx */
4752                 bnxt_hwrm_clear_vnic_rss(bp);
4753                 bnxt_hwrm_vnic_ctx_free(bp);
4754                 /* before free the vnic, undo the vnic tpa settings */
4755                 if (bp->flags & BNXT_FLAG_TPA)
4756                         bnxt_set_tpa(bp, false);
4757                 bnxt_hwrm_vnic_free(bp);
4758         }
4759         bnxt_hwrm_ring_free(bp, close_path);
4760         bnxt_hwrm_ring_grp_free(bp);
4761         if (irq_re_init) {
4762                 bnxt_hwrm_stat_ctx_free(bp);
4763                 bnxt_hwrm_free_tunnel_ports(bp);
4764         }
4765 }
4766
4767 static int bnxt_setup_vnic(struct bnxt *bp, u16 vnic_id)
4768 {
4769         struct bnxt_vnic_info *vnic = &bp->vnic_info[vnic_id];
4770         int rc;
4771
4772         if (vnic->flags & BNXT_VNIC_RFS_NEW_RSS_FLAG)
4773                 goto skip_rss_ctx;
4774
4775         /* allocate context for vnic */
4776         rc = bnxt_hwrm_vnic_ctx_alloc(bp, vnic_id, 0);
4777         if (rc) {
4778                 netdev_err(bp->dev, "hwrm vnic %d alloc failure rc: %x\n",
4779                            vnic_id, rc);
4780                 goto vnic_setup_err;
4781         }
4782         bp->rsscos_nr_ctxs++;
4783
4784         if (BNXT_CHIP_TYPE_NITRO_A0(bp)) {
4785                 rc = bnxt_hwrm_vnic_ctx_alloc(bp, vnic_id, 1);
4786                 if (rc) {
4787                         netdev_err(bp->dev, "hwrm vnic %d cos ctx alloc failure rc: %x\n",
4788                                    vnic_id, rc);
4789                         goto vnic_setup_err;
4790                 }
4791                 bp->rsscos_nr_ctxs++;
4792         }
4793
4794 skip_rss_ctx:
4795         /* configure default vnic, ring grp */
4796         rc = bnxt_hwrm_vnic_cfg(bp, vnic_id);
4797         if (rc) {
4798                 netdev_err(bp->dev, "hwrm vnic %d cfg failure rc: %x\n",
4799                            vnic_id, rc);
4800                 goto vnic_setup_err;
4801         }
4802
4803         /* Enable RSS hashing on vnic */
4804         rc = bnxt_hwrm_vnic_set_rss(bp, vnic_id, true);
4805         if (rc) {
4806                 netdev_err(bp->dev, "hwrm vnic %d set rss failure rc: %x\n",
4807                            vnic_id, rc);
4808                 goto vnic_setup_err;
4809         }
4810
4811         if (bp->flags & BNXT_FLAG_AGG_RINGS) {
4812                 rc = bnxt_hwrm_vnic_set_hds(bp, vnic_id);
4813                 if (rc) {
4814                         netdev_err(bp->dev, "hwrm vnic %d set hds failure rc: %x\n",
4815                                    vnic_id, rc);
4816                 }
4817         }
4818
4819 vnic_setup_err:
4820         return rc;
4821 }
4822
4823 static int bnxt_alloc_rfs_vnics(struct bnxt *bp)
4824 {
4825 #ifdef CONFIG_RFS_ACCEL
4826         int i, rc = 0;
4827
4828         for (i = 0; i < bp->rx_nr_rings; i++) {
4829                 struct bnxt_vnic_info *vnic;
4830                 u16 vnic_id = i + 1;
4831                 u16 ring_id = i;
4832
4833                 if (vnic_id >= bp->nr_vnics)
4834                         break;
4835
4836                 vnic = &bp->vnic_info[vnic_id];
4837                 vnic->flags |= BNXT_VNIC_RFS_FLAG;
4838                 if (bp->flags & BNXT_FLAG_NEW_RSS_CAP)
4839                         vnic->flags |= BNXT_VNIC_RFS_NEW_RSS_FLAG;
4840                 rc = bnxt_hwrm_vnic_alloc(bp, vnic_id, ring_id, 1);
4841                 if (rc) {
4842                         netdev_err(bp->dev, "hwrm vnic %d alloc failure rc: %x\n",
4843                                    vnic_id, rc);
4844                         break;
4845                 }
4846                 rc = bnxt_setup_vnic(bp, vnic_id);
4847                 if (rc)
4848                         break;
4849         }
4850         return rc;
4851 #else
4852         return 0;
4853 #endif
4854 }
4855
4856 /* Allow PF and VF with default VLAN to be in promiscuous mode */
4857 static bool bnxt_promisc_ok(struct bnxt *bp)
4858 {
4859 #ifdef CONFIG_BNXT_SRIOV
4860         if (BNXT_VF(bp) && !bp->vf.vlan)
4861                 return false;
4862 #endif
4863         return true;
4864 }
4865
4866 static int bnxt_setup_nitroa0_vnic(struct bnxt *bp)
4867 {
4868         unsigned int rc = 0;
4869
4870         rc = bnxt_hwrm_vnic_alloc(bp, 1, bp->rx_nr_rings - 1, 1);
4871         if (rc) {
4872                 netdev_err(bp->dev, "Cannot allocate special vnic for NS2 A0: %x\n",
4873                            rc);
4874                 return rc;
4875         }
4876
4877         rc = bnxt_hwrm_vnic_cfg(bp, 1);
4878         if (rc) {
4879                 netdev_err(bp->dev, "Cannot allocate special vnic for NS2 A0: %x\n",
4880                            rc);
4881                 return rc;
4882         }
4883         return rc;
4884 }
4885
4886 static int bnxt_cfg_rx_mode(struct bnxt *);
4887 static bool bnxt_mc_list_updated(struct bnxt *, u32 *);
4888
4889 static int bnxt_init_chip(struct bnxt *bp, bool irq_re_init)
4890 {
4891         struct bnxt_vnic_info *vnic = &bp->vnic_info[0];
4892         int rc = 0;
4893         unsigned int rx_nr_rings = bp->rx_nr_rings;
4894
4895         if (irq_re_init) {
4896                 rc = bnxt_hwrm_stat_ctx_alloc(bp);
4897                 if (rc) {
4898                         netdev_err(bp->dev, "hwrm stat ctx alloc failure rc: %x\n",
4899                                    rc);
4900                         goto err_out;
4901                 }
4902         }
4903
4904         rc = bnxt_hwrm_ring_alloc(bp);
4905         if (rc) {
4906                 netdev_err(bp->dev, "hwrm ring alloc failure rc: %x\n", rc);
4907                 goto err_out;
4908         }
4909
4910         rc = bnxt_hwrm_ring_grp_alloc(bp);
4911         if (rc) {
4912                 netdev_err(bp->dev, "hwrm_ring_grp alloc failure: %x\n", rc);
4913                 goto err_out;
4914         }
4915
4916         if (BNXT_CHIP_TYPE_NITRO_A0(bp))
4917                 rx_nr_rings--;
4918
4919         /* default vnic 0 */
4920         rc = bnxt_hwrm_vnic_alloc(bp, 0, 0, rx_nr_rings);
4921         if (rc) {
4922                 netdev_err(bp->dev, "hwrm vnic alloc failure rc: %x\n", rc);
4923                 goto err_out;
4924         }
4925
4926         rc = bnxt_setup_vnic(bp, 0);
4927         if (rc)
4928                 goto err_out;
4929
4930         if (bp->flags & BNXT_FLAG_RFS) {
4931                 rc = bnxt_alloc_rfs_vnics(bp);
4932                 if (rc)
4933                         goto err_out;
4934         }
4935
4936         if (bp->flags & BNXT_FLAG_TPA) {
4937                 rc = bnxt_set_tpa(bp, true);
4938                 if (rc)
4939                         goto err_out;
4940         }
4941
4942         if (BNXT_VF(bp))
4943                 bnxt_update_vf_mac(bp);
4944
4945         /* Filter for default vnic 0 */
4946         rc = bnxt_hwrm_set_vnic_filter(bp, 0, 0, bp->dev->dev_addr);
4947         if (rc) {
4948                 netdev_err(bp->dev, "HWRM vnic filter failure rc: %x\n", rc);
4949                 goto err_out;
4950         }
4951         vnic->uc_filter_count = 1;
4952
4953         vnic->rx_mask = CFA_L2_SET_RX_MASK_REQ_MASK_BCAST;
4954
4955         if ((bp->dev->flags & IFF_PROMISC) && bnxt_promisc_ok(bp))
4956                 vnic->rx_mask |= CFA_L2_SET_RX_MASK_REQ_MASK_PROMISCUOUS;
4957
4958         if (bp->dev->flags & IFF_ALLMULTI) {
4959                 vnic->rx_mask |= CFA_L2_SET_RX_MASK_REQ_MASK_ALL_MCAST;
4960                 vnic->mc_list_count = 0;
4961         } else {
4962                 u32 mask = 0;
4963
4964                 bnxt_mc_list_updated(bp, &mask);
4965                 vnic->rx_mask |= mask;
4966         }
4967
4968         rc = bnxt_cfg_rx_mode(bp);
4969         if (rc)
4970                 goto err_out;
4971
4972         rc = bnxt_hwrm_set_coal(bp);
4973         if (rc)
4974                 netdev_warn(bp->dev, "HWRM set coalescing failure rc: %x\n",
4975                                 rc);
4976
4977         if (BNXT_CHIP_TYPE_NITRO_A0(bp)) {
4978                 rc = bnxt_setup_nitroa0_vnic(bp);
4979                 if (rc)
4980                         netdev_err(bp->dev, "Special vnic setup failure for NS2 A0 rc: %x\n",
4981                                    rc);
4982         }
4983
4984         if (BNXT_VF(bp)) {
4985                 bnxt_hwrm_func_qcfg(bp);
4986                 netdev_update_features(bp->dev);
4987         }
4988
4989         return 0;
4990
4991 err_out:
4992         bnxt_hwrm_resource_free(bp, 0, true);
4993
4994         return rc;
4995 }
4996
4997 static int bnxt_shutdown_nic(struct bnxt *bp, bool irq_re_init)
4998 {
4999         bnxt_hwrm_resource_free(bp, 1, irq_re_init);
5000         return 0;
5001 }
5002
5003 static int bnxt_init_nic(struct bnxt *bp, bool irq_re_init)
5004 {
5005         bnxt_init_rx_rings(bp);
5006         bnxt_init_tx_rings(bp);
5007         bnxt_init_ring_grps(bp, irq_re_init);
5008         bnxt_init_vnics(bp);
5009
5010         return bnxt_init_chip(bp, irq_re_init);
5011 }
5012
5013 static int bnxt_set_real_num_queues(struct bnxt *bp)
5014 {
5015         int rc;
5016         struct net_device *dev = bp->dev;
5017
5018         rc = netif_set_real_num_tx_queues(dev, bp->tx_nr_rings -
5019                                           bp->tx_nr_rings_xdp);
5020         if (rc)
5021                 return rc;
5022
5023         rc = netif_set_real_num_rx_queues(dev, bp->rx_nr_rings);
5024         if (rc)
5025                 return rc;
5026
5027 #ifdef CONFIG_RFS_ACCEL
5028         if (bp->flags & BNXT_FLAG_RFS)
5029                 dev->rx_cpu_rmap = alloc_irq_cpu_rmap(bp->rx_nr_rings);
5030 #endif
5031
5032         return rc;
5033 }
5034
5035 static int bnxt_trim_rings(struct bnxt *bp, int *rx, int *tx, int max,
5036                            bool shared)
5037 {
5038         int _rx = *rx, _tx = *tx;
5039
5040         if (shared) {
5041                 *rx = min_t(int, _rx, max);
5042                 *tx = min_t(int, _tx, max);
5043         } else {
5044                 if (max < 2)
5045                         return -ENOMEM;
5046
5047                 while (_rx + _tx > max) {
5048                         if (_rx > _tx && _rx > 1)
5049                                 _rx--;
5050                         else if (_tx > 1)
5051                                 _tx--;
5052                 }
5053                 *rx = _rx;
5054                 *tx = _tx;
5055         }
5056         return 0;
5057 }
5058
5059 static void bnxt_setup_msix(struct bnxt *bp)
5060 {
5061         const int len = sizeof(bp->irq_tbl[0].name);
5062         struct net_device *dev = bp->dev;
5063         int tcs, i;
5064
5065         tcs = netdev_get_num_tc(dev);
5066         if (tcs > 1) {
5067                 int i, off, count;
5068
5069                 for (i = 0; i < tcs; i++) {
5070                         count = bp->tx_nr_rings_per_tc;
5071                         off = i * count;
5072                         netdev_set_tc_queue(dev, i, count, off);
5073                 }
5074         }
5075
5076         for (i = 0; i < bp->cp_nr_rings; i++) {
5077                 char *attr;
5078
5079                 if (bp->flags & BNXT_FLAG_SHARED_RINGS)
5080                         attr = "TxRx";
5081                 else if (i < bp->rx_nr_rings)
5082                         attr = "rx";
5083                 else
5084                         attr = "tx";
5085
5086                 snprintf(bp->irq_tbl[i].name, len, "%s-%s-%d", dev->name, attr,
5087                          i);
5088                 bp->irq_tbl[i].handler = bnxt_msix;
5089         }
5090 }
5091
5092 static void bnxt_setup_inta(struct bnxt *bp)
5093 {
5094         const int len = sizeof(bp->irq_tbl[0].name);
5095
5096         if (netdev_get_num_tc(bp->dev))
5097                 netdev_reset_tc(bp->dev);
5098
5099         snprintf(bp->irq_tbl[0].name, len, "%s-%s-%d", bp->dev->name, "TxRx",
5100                  0);
5101         bp->irq_tbl[0].handler = bnxt_inta;
5102 }
5103
5104 static int bnxt_setup_int_mode(struct bnxt *bp)
5105 {
5106         int rc;
5107
5108         if (bp->flags & BNXT_FLAG_USING_MSIX)
5109                 bnxt_setup_msix(bp);
5110         else
5111                 bnxt_setup_inta(bp);
5112
5113         rc = bnxt_set_real_num_queues(bp);
5114         return rc;
5115 }
5116
5117 #ifdef CONFIG_RFS_ACCEL
5118 static unsigned int bnxt_get_max_func_rss_ctxs(struct bnxt *bp)
5119 {
5120 #if defined(CONFIG_BNXT_SRIOV)
5121         if (BNXT_VF(bp))
5122                 return bp->vf.max_rsscos_ctxs;
5123 #endif
5124         return bp->pf.max_rsscos_ctxs;
5125 }
5126
5127 static unsigned int bnxt_get_max_func_vnics(struct bnxt *bp)
5128 {
5129 #if defined(CONFIG_BNXT_SRIOV)
5130         if (BNXT_VF(bp))
5131                 return bp->vf.max_vnics;
5132 #endif
5133         return bp->pf.max_vnics;
5134 }
5135 #endif
5136
5137 unsigned int bnxt_get_max_func_stat_ctxs(struct bnxt *bp)
5138 {
5139 #if defined(CONFIG_BNXT_SRIOV)
5140         if (BNXT_VF(bp))
5141                 return bp->vf.max_stat_ctxs;
5142 #endif
5143         return bp->pf.max_stat_ctxs;
5144 }
5145
5146 void bnxt_set_max_func_stat_ctxs(struct bnxt *bp, unsigned int max)
5147 {
5148 #if defined(CONFIG_BNXT_SRIOV)
5149         if (BNXT_VF(bp))
5150                 bp->vf.max_stat_ctxs = max;
5151         else
5152 #endif
5153                 bp->pf.max_stat_ctxs = max;
5154 }
5155
5156 unsigned int bnxt_get_max_func_cp_rings(struct bnxt *bp)
5157 {
5158 #if defined(CONFIG_BNXT_SRIOV)
5159         if (BNXT_VF(bp))
5160                 return bp->vf.max_cp_rings;
5161 #endif
5162         return bp->pf.max_cp_rings;
5163 }
5164
5165 void bnxt_set_max_func_cp_rings(struct bnxt *bp, unsigned int max)
5166 {
5167 #if defined(CONFIG_BNXT_SRIOV)
5168         if (BNXT_VF(bp))
5169                 bp->vf.max_cp_rings = max;
5170         else
5171 #endif
5172                 bp->pf.max_cp_rings = max;
5173 }
5174
5175 static unsigned int bnxt_get_max_func_irqs(struct bnxt *bp)
5176 {
5177 #if defined(CONFIG_BNXT_SRIOV)
5178         if (BNXT_VF(bp))
5179                 return bp->vf.max_irqs;
5180 #endif
5181         return bp->pf.max_irqs;
5182 }
5183
5184 void bnxt_set_max_func_irqs(struct bnxt *bp, unsigned int max_irqs)
5185 {
5186 #if defined(CONFIG_BNXT_SRIOV)
5187         if (BNXT_VF(bp))
5188                 bp->vf.max_irqs = max_irqs;
5189         else
5190 #endif
5191                 bp->pf.max_irqs = max_irqs;
5192 }
5193
5194 static int bnxt_init_msix(struct bnxt *bp)
5195 {
5196         int i, total_vecs, rc = 0, min = 1;
5197         struct msix_entry *msix_ent;
5198
5199         total_vecs = bnxt_get_max_func_irqs(bp);
5200         msix_ent = kcalloc(total_vecs, sizeof(struct msix_entry), GFP_KERNEL);
5201         if (!msix_ent)
5202                 return -ENOMEM;
5203
5204         for (i = 0; i < total_vecs; i++) {
5205                 msix_ent[i].entry = i;
5206                 msix_ent[i].vector = 0;
5207         }
5208
5209         if (!(bp->flags & BNXT_FLAG_SHARED_RINGS))
5210                 min = 2;
5211
5212         total_vecs = pci_enable_msix_range(bp->pdev, msix_ent, min, total_vecs);
5213         if (total_vecs < 0) {
5214                 rc = -ENODEV;
5215                 goto msix_setup_exit;
5216         }
5217
5218         bp->irq_tbl = kcalloc(total_vecs, sizeof(struct bnxt_irq), GFP_KERNEL);
5219         if (bp->irq_tbl) {
5220                 for (i = 0; i < total_vecs; i++)
5221                         bp->irq_tbl[i].vector = msix_ent[i].vector;
5222
5223                 bp->total_irqs = total_vecs;
5224                 /* Trim rings based upon num of vectors allocated */
5225                 rc = bnxt_trim_rings(bp, &bp->rx_nr_rings, &bp->tx_nr_rings,
5226                                      total_vecs, min == 1);
5227                 if (rc)
5228                         goto msix_setup_exit;
5229
5230                 bp->tx_nr_rings_per_tc = bp->tx_nr_rings;
5231                 bp->cp_nr_rings = (min == 1) ?
5232                                   max_t(int, bp->tx_nr_rings, bp->rx_nr_rings) :
5233                                   bp->tx_nr_rings + bp->rx_nr_rings;
5234
5235         } else {
5236                 rc = -ENOMEM;
5237                 goto msix_setup_exit;
5238         }
5239         bp->flags |= BNXT_FLAG_USING_MSIX;
5240         kfree(msix_ent);
5241         return 0;
5242
5243 msix_setup_exit:
5244         netdev_err(bp->dev, "bnxt_init_msix err: %x\n", rc);
5245         kfree(bp->irq_tbl);
5246         bp->irq_tbl = NULL;
5247         pci_disable_msix(bp->pdev);
5248         kfree(msix_ent);
5249         return rc;
5250 }
5251
5252 static int bnxt_init_inta(struct bnxt *bp)
5253 {
5254         bp->irq_tbl = kcalloc(1, sizeof(struct bnxt_irq), GFP_KERNEL);
5255         if (!bp->irq_tbl)
5256                 return -ENOMEM;
5257
5258         bp->total_irqs = 1;
5259         bp->rx_nr_rings = 1;
5260         bp->tx_nr_rings = 1;
5261         bp->cp_nr_rings = 1;
5262         bp->tx_nr_rings_per_tc = bp->tx_nr_rings;
5263         bp->flags |= BNXT_FLAG_SHARED_RINGS;
5264         bp->irq_tbl[0].vector = bp->pdev->irq;
5265         return 0;
5266 }
5267
5268 static int bnxt_init_int_mode(struct bnxt *bp)
5269 {
5270         int rc = 0;
5271
5272         if (bp->flags & BNXT_FLAG_MSIX_CAP)
5273                 rc = bnxt_init_msix(bp);
5274
5275         if (!(bp->flags & BNXT_FLAG_USING_MSIX) && BNXT_PF(bp)) {
5276                 /* fallback to INTA */
5277                 rc = bnxt_init_inta(bp);
5278         }
5279         return rc;
5280 }
5281
5282 static void bnxt_clear_int_mode(struct bnxt *bp)
5283 {
5284         if (bp->flags & BNXT_FLAG_USING_MSIX)
5285                 pci_disable_msix(bp->pdev);
5286
5287         kfree(bp->irq_tbl);
5288         bp->irq_tbl = NULL;
5289         bp->flags &= ~BNXT_FLAG_USING_MSIX;
5290 }
5291
5292 static void bnxt_free_irq(struct bnxt *bp)
5293 {
5294         struct bnxt_irq *irq;
5295         int i;
5296
5297 #ifdef CONFIG_RFS_ACCEL
5298         free_irq_cpu_rmap(bp->dev->rx_cpu_rmap);
5299         bp->dev->rx_cpu_rmap = NULL;
5300 #endif
5301         if (!bp->irq_tbl)
5302                 return;
5303
5304         for (i = 0; i < bp->cp_nr_rings; i++) {
5305                 irq = &bp->irq_tbl[i];
5306                 if (irq->requested)
5307                         free_irq(irq->vector, bp->bnapi[i]);
5308                 irq->requested = 0;
5309         }
5310 }
5311
5312 static int bnxt_request_irq(struct bnxt *bp)
5313 {
5314         int i, j, rc = 0;
5315         unsigned long flags = 0;
5316 #ifdef CONFIG_RFS_ACCEL
5317         struct cpu_rmap *rmap = bp->dev->rx_cpu_rmap;
5318 #endif
5319
5320         if (!(bp->flags & BNXT_FLAG_USING_MSIX))
5321                 flags = IRQF_SHARED;
5322
5323         for (i = 0, j = 0; i < bp->cp_nr_rings; i++) {
5324                 struct bnxt_irq *irq = &bp->irq_tbl[i];
5325 #ifdef CONFIG_RFS_ACCEL
5326                 if (rmap && bp->bnapi[i]->rx_ring) {
5327                         rc = irq_cpu_rmap_add(rmap, irq->vector);
5328                         if (rc)
5329                                 netdev_warn(bp->dev, "failed adding irq rmap for ring %d\n",
5330                                             j);
5331                         j++;
5332                 }
5333 #endif
5334                 rc = request_irq(irq->vector, irq->handler, flags, irq->name,
5335                                  bp->bnapi[i]);
5336                 if (rc)
5337                         break;
5338
5339                 irq->requested = 1;
5340         }
5341         return rc;
5342 }
5343
5344 static void bnxt_del_napi(struct bnxt *bp)
5345 {
5346         int i;
5347
5348         if (!bp->bnapi)
5349                 return;
5350
5351         for (i = 0; i < bp->cp_nr_rings; i++) {
5352                 struct bnxt_napi *bnapi = bp->bnapi[i];
5353
5354                 napi_hash_del(&bnapi->napi);
5355                 netif_napi_del(&bnapi->napi);
5356         }
5357         /* We called napi_hash_del() before netif_napi_del(), we need
5358          * to respect an RCU grace period before freeing napi structures.
5359          */
5360         synchronize_net();
5361 }
5362
5363 static void bnxt_init_napi(struct bnxt *bp)
5364 {
5365         int i;
5366         unsigned int cp_nr_rings = bp->cp_nr_rings;
5367         struct bnxt_napi *bnapi;
5368
5369         if (bp->flags & BNXT_FLAG_USING_MSIX) {
5370                 if (BNXT_CHIP_TYPE_NITRO_A0(bp))
5371                         cp_nr_rings--;
5372                 for (i = 0; i < cp_nr_rings; i++) {
5373                         bnapi = bp->bnapi[i];
5374                         netif_napi_add(bp->dev, &bnapi->napi,
5375                                        bnxt_poll, 64);
5376                 }
5377                 if (BNXT_CHIP_TYPE_NITRO_A0(bp)) {
5378                         bnapi = bp->bnapi[cp_nr_rings];
5379                         netif_napi_add(bp->dev, &bnapi->napi,
5380                                        bnxt_poll_nitroa0, 64);
5381                 }
5382         } else {
5383                 bnapi = bp->bnapi[0];
5384                 netif_napi_add(bp->dev, &bnapi->napi, bnxt_poll, 64);
5385         }
5386 }
5387
5388 static void bnxt_disable_napi(struct bnxt *bp)
5389 {
5390         int i;
5391
5392         if (!bp->bnapi)
5393                 return;
5394
5395         for (i = 0; i < bp->cp_nr_rings; i++)
5396                 napi_disable(&bp->bnapi[i]->napi);
5397 }
5398
5399 static void bnxt_enable_napi(struct bnxt *bp)
5400 {
5401         int i;
5402
5403         for (i = 0; i < bp->cp_nr_rings; i++) {
5404                 bp->bnapi[i]->in_reset = false;
5405                 napi_enable(&bp->bnapi[i]->napi);
5406         }
5407 }
5408
5409 void bnxt_tx_disable(struct bnxt *bp)
5410 {
5411         int i;
5412         struct bnxt_tx_ring_info *txr;
5413         struct netdev_queue *txq;
5414
5415         if (bp->tx_ring) {
5416                 for (i = 0; i < bp->tx_nr_rings; i++) {
5417                         txr = &bp->tx_ring[i];
5418                         txq = netdev_get_tx_queue(bp->dev, i);
5419                         txr->dev_state = BNXT_DEV_STATE_CLOSING;
5420                 }
5421         }
5422         /* Stop all TX queues */
5423         netif_tx_disable(bp->dev);
5424         netif_carrier_off(bp->dev);
5425 }
5426
5427 void bnxt_tx_enable(struct bnxt *bp)
5428 {
5429         int i;
5430         struct bnxt_tx_ring_info *txr;
5431         struct netdev_queue *txq;
5432
5433         for (i = 0; i < bp->tx_nr_rings; i++) {
5434                 txr = &bp->tx_ring[i];
5435                 txq = netdev_get_tx_queue(bp->dev, i);
5436                 txr->dev_state = 0;
5437         }
5438         netif_tx_wake_all_queues(bp->dev);
5439         if (bp->link_info.link_up)
5440                 netif_carrier_on(bp->dev);
5441 }
5442
5443 static void bnxt_report_link(struct bnxt *bp)
5444 {
5445         if (bp->link_info.link_up) {
5446                 const char *duplex;
5447                 const char *flow_ctrl;
5448                 u16 speed, fec;
5449
5450                 netif_carrier_on(bp->dev);
5451                 if (bp->link_info.duplex == BNXT_LINK_DUPLEX_FULL)
5452                         duplex = "full";
5453                 else
5454                         duplex = "half";
5455                 if (bp->link_info.pause == BNXT_LINK_PAUSE_BOTH)
5456                         flow_ctrl = "ON - receive & transmit";
5457                 else if (bp->link_info.pause == BNXT_LINK_PAUSE_TX)
5458                         flow_ctrl = "ON - transmit";
5459                 else if (bp->link_info.pause == BNXT_LINK_PAUSE_RX)
5460                         flow_ctrl = "ON - receive";
5461                 else
5462                         flow_ctrl = "none";
5463                 speed = bnxt_fw_to_ethtool_speed(bp->link_info.link_speed);
5464                 netdev_info(bp->dev, "NIC Link is Up, %d Mbps %s duplex, Flow control: %s\n",
5465                             speed, duplex, flow_ctrl);
5466                 if (bp->flags & BNXT_FLAG_EEE_CAP)
5467                         netdev_info(bp->dev, "EEE is %s\n",
5468                                     bp->eee.eee_active ? "active" :
5469                                                          "not active");
5470                 fec = bp->link_info.fec_cfg;
5471                 if (!(fec & PORT_PHY_QCFG_RESP_FEC_CFG_FEC_NONE_SUPPORTED))
5472                         netdev_info(bp->dev, "FEC autoneg %s encodings: %s\n",
5473                                     (fec & BNXT_FEC_AUTONEG) ? "on" : "off",
5474                                     (fec & BNXT_FEC_ENC_BASE_R) ? "BaseR" :
5475                                      (fec & BNXT_FEC_ENC_RS) ? "RS" : "None");
5476         } else {
5477                 netif_carrier_off(bp->dev);
5478                 netdev_err(bp->dev, "NIC Link is Down\n");
5479         }
5480 }
5481
5482 static int bnxt_hwrm_phy_qcaps(struct bnxt *bp)
5483 {
5484         int rc = 0;
5485         struct hwrm_port_phy_qcaps_input req = {0};
5486         struct hwrm_port_phy_qcaps_output *resp = bp->hwrm_cmd_resp_addr;
5487         struct bnxt_link_info *link_info = &bp->link_info;
5488
5489         if (bp->hwrm_spec_code < 0x10201)
5490                 return 0;
5491
5492         bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_PORT_PHY_QCAPS, -1, -1);
5493
5494         mutex_lock(&bp->hwrm_cmd_lock);
5495         rc = _hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT);
5496         if (rc)
5497                 goto hwrm_phy_qcaps_exit;
5498
5499         if (resp->eee_supported & PORT_PHY_QCAPS_RESP_EEE_SUPPORTED) {
5500                 struct ethtool_eee *eee = &bp->eee;
5501                 u16 fw_speeds = le16_to_cpu(resp->supported_speeds_eee_mode);
5502
5503                 bp->flags |= BNXT_FLAG_EEE_CAP;
5504                 eee->supported = _bnxt_fw_to_ethtool_adv_spds(fw_speeds, 0);
5505                 bp->lpi_tmr_lo = le32_to_cpu(resp->tx_lpi_timer_low) &
5506                                  PORT_PHY_QCAPS_RESP_TX_LPI_TIMER_LOW_MASK;
5507                 bp->lpi_tmr_hi = le32_to_cpu(resp->valid_tx_lpi_timer_high) &
5508                                  PORT_PHY_QCAPS_RESP_TX_LPI_TIMER_HIGH_MASK;
5509         }
5510         link_info->support_auto_speeds =
5511                 le16_to_cpu(resp->supported_speeds_auto_mode);
5512
5513 hwrm_phy_qcaps_exit:
5514         mutex_unlock(&bp->hwrm_cmd_lock);
5515         return rc;
5516 }
5517
5518 static int bnxt_update_link(struct bnxt *bp, bool chng_link_state)
5519 {
5520         int rc = 0;
5521         struct bnxt_link_info *link_info = &bp->link_info;
5522         struct hwrm_port_phy_qcfg_input req = {0};
5523         struct hwrm_port_phy_qcfg_output *resp = bp->hwrm_cmd_resp_addr;
5524         u8 link_up = link_info->link_up;
5525         u16 diff;
5526
5527         bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_PORT_PHY_QCFG, -1, -1);
5528
5529         mutex_lock(&bp->hwrm_cmd_lock);
5530         rc = _hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT);
5531         if (rc) {
5532                 mutex_unlock(&bp->hwrm_cmd_lock);
5533                 return rc;
5534         }
5535
5536         memcpy(&link_info->phy_qcfg_resp, resp, sizeof(*resp));
5537         link_info->phy_link_status = resp->link;
5538         link_info->duplex =  resp->duplex;
5539         link_info->pause = resp->pause;
5540         link_info->auto_mode = resp->auto_mode;
5541         link_info->auto_pause_setting = resp->auto_pause;
5542         link_info->lp_pause = resp->link_partner_adv_pause;
5543         link_info->force_pause_setting = resp->force_pause;
5544         link_info->duplex_setting = resp->duplex;
5545         if (link_info->phy_link_status == BNXT_LINK_LINK)
5546                 link_info->link_speed = le16_to_cpu(resp->link_speed);
5547         else
5548                 link_info->link_speed = 0;
5549         link_info->force_link_speed = le16_to_cpu(resp->force_link_speed);
5550         link_info->support_speeds = le16_to_cpu(resp->support_speeds);
5551         link_info->auto_link_speeds = le16_to_cpu(resp->auto_link_speed_mask);
5552         link_info->lp_auto_link_speeds =
5553                 le16_to_cpu(resp->link_partner_adv_speeds);
5554         link_info->preemphasis = le32_to_cpu(resp->preemphasis);
5555         link_info->phy_ver[0] = resp->phy_maj;
5556         link_info->phy_ver[1] = resp->phy_min;
5557         link_info->phy_ver[2] = resp->phy_bld;
5558         link_info->media_type = resp->media_type;
5559         link_info->phy_type = resp->phy_type;
5560         link_info->transceiver = resp->xcvr_pkg_type;
5561         link_info->phy_addr = resp->eee_config_phy_addr &
5562                               PORT_PHY_QCFG_RESP_PHY_ADDR_MASK;
5563         link_info->module_status = resp->module_status;
5564
5565         if (bp->flags & BNXT_FLAG_EEE_CAP) {
5566                 struct ethtool_eee *eee = &bp->eee;
5567                 u16 fw_speeds;
5568
5569                 eee->eee_active = 0;
5570                 if (resp->eee_config_phy_addr &
5571                     PORT_PHY_QCFG_RESP_EEE_CONFIG_EEE_ACTIVE) {
5572                         eee->eee_active = 1;
5573                         fw_speeds = le16_to_cpu(
5574                                 resp->link_partner_adv_eee_link_speed_mask);
5575                         eee->lp_advertised =
5576                                 _bnxt_fw_to_ethtool_adv_spds(fw_speeds, 0);
5577                 }
5578
5579                 /* Pull initial EEE config */
5580                 if (!chng_link_state) {
5581                         if (resp->eee_config_phy_addr &
5582                             PORT_PHY_QCFG_RESP_EEE_CONFIG_EEE_ENABLED)
5583                                 eee->eee_enabled = 1;
5584
5585                         fw_speeds = le16_to_cpu(resp->adv_eee_link_speed_mask);
5586                         eee->advertised =
5587                                 _bnxt_fw_to_ethtool_adv_spds(fw_speeds, 0);
5588
5589                         if (resp->eee_config_phy_addr &
5590                             PORT_PHY_QCFG_RESP_EEE_CONFIG_EEE_TX_LPI) {
5591                                 __le32 tmr;
5592
5593                                 eee->tx_lpi_enabled = 1;
5594                                 tmr = resp->xcvr_identifier_type_tx_lpi_timer;
5595                                 eee->tx_lpi_timer = le32_to_cpu(tmr) &
5596                                         PORT_PHY_QCFG_RESP_TX_LPI_TIMER_MASK;
5597                         }
5598                 }
5599         }
5600
5601         link_info->fec_cfg = PORT_PHY_QCFG_RESP_FEC_CFG_FEC_NONE_SUPPORTED;
5602         if (bp->hwrm_spec_code >= 0x10504)
5603                 link_info->fec_cfg = le16_to_cpu(resp->fec_cfg);
5604
5605         /* TODO: need to add more logic to report VF link */
5606         if (chng_link_state) {
5607                 if (link_info->phy_link_status == BNXT_LINK_LINK)
5608                         link_info->link_up = 1;
5609                 else
5610                         link_info->link_up = 0;
5611                 if (link_up != link_info->link_up)
5612                         bnxt_report_link(bp);
5613         } else {
5614                 /* alwasy link down if not require to update link state */
5615                 link_info->link_up = 0;
5616         }
5617         mutex_unlock(&bp->hwrm_cmd_lock);
5618
5619         diff = link_info->support_auto_speeds ^ link_info->advertising;
5620         if ((link_info->support_auto_speeds | diff) !=
5621             link_info->support_auto_speeds) {
5622                 /* An advertised speed is no longer supported, so we need to
5623                  * update the advertisement settings.  Caller holds RTNL
5624                  * so we can modify link settings.
5625                  */
5626                 link_info->advertising = link_info->support_auto_speeds;
5627                 if (link_info->autoneg & BNXT_AUTONEG_SPEED)
5628                         bnxt_hwrm_set_link_setting(bp, true, false);
5629         }
5630         return 0;
5631 }
5632
5633 static void bnxt_get_port_module_status(struct bnxt *bp)
5634 {
5635         struct bnxt_link_info *link_info = &bp->link_info;
5636         struct hwrm_port_phy_qcfg_output *resp = &link_info->phy_qcfg_resp;
5637         u8 module_status;
5638
5639         if (bnxt_update_link(bp, true))
5640                 return;
5641
5642         module_status = link_info->module_status;
5643         switch (module_status) {
5644         case PORT_PHY_QCFG_RESP_MODULE_STATUS_DISABLETX:
5645         case PORT_PHY_QCFG_RESP_MODULE_STATUS_PWRDOWN:
5646         case PORT_PHY_QCFG_RESP_MODULE_STATUS_WARNINGMSG:
5647                 netdev_warn(bp->dev, "Unqualified SFP+ module detected on port %d\n",
5648                             bp->pf.port_id);
5649                 if (bp->hwrm_spec_code >= 0x10201) {
5650                         netdev_warn(bp->dev, "Module part number %s\n",
5651                                     resp->phy_vendor_partnumber);
5652                 }
5653                 if (module_status == PORT_PHY_QCFG_RESP_MODULE_STATUS_DISABLETX)
5654                         netdev_warn(bp->dev, "TX is disabled\n");
5655                 if (module_status == PORT_PHY_QCFG_RESP_MODULE_STATUS_PWRDOWN)
5656                         netdev_warn(bp->dev, "SFP+ module is shutdown\n");
5657         }
5658 }
5659
5660 static void
5661 bnxt_hwrm_set_pause_common(struct bnxt *bp, struct hwrm_port_phy_cfg_input *req)
5662 {
5663         if (bp->link_info.autoneg & BNXT_AUTONEG_FLOW_CTRL) {
5664                 if (bp->hwrm_spec_code >= 0x10201)
5665                         req->auto_pause =
5666                                 PORT_PHY_CFG_REQ_AUTO_PAUSE_AUTONEG_PAUSE;
5667                 if (bp->link_info.req_flow_ctrl & BNXT_LINK_PAUSE_RX)
5668                         req->auto_pause |= PORT_PHY_CFG_REQ_AUTO_PAUSE_RX;
5669                 if (bp->link_info.req_flow_ctrl & BNXT_LINK_PAUSE_TX)
5670                         req->auto_pause |= PORT_PHY_CFG_REQ_AUTO_PAUSE_TX;
5671                 req->enables |=
5672                         cpu_to_le32(PORT_PHY_CFG_REQ_ENABLES_AUTO_PAUSE);
5673         } else {
5674                 if (bp->link_info.req_flow_ctrl & BNXT_LINK_PAUSE_RX)
5675                         req->force_pause |= PORT_PHY_CFG_REQ_FORCE_PAUSE_RX;
5676                 if (bp->link_info.req_flow_ctrl & BNXT_LINK_PAUSE_TX)
5677                         req->force_pause |= PORT_PHY_CFG_REQ_FORCE_PAUSE_TX;
5678                 req->enables |=
5679                         cpu_to_le32(PORT_PHY_CFG_REQ_ENABLES_FORCE_PAUSE);
5680                 if (bp->hwrm_spec_code >= 0x10201) {
5681                         req->auto_pause = req->force_pause;
5682                         req->enables |= cpu_to_le32(
5683                                 PORT_PHY_CFG_REQ_ENABLES_AUTO_PAUSE);
5684                 }
5685         }
5686 }
5687
5688 static void bnxt_hwrm_set_link_common(struct bnxt *bp,
5689                                       struct hwrm_port_phy_cfg_input *req)
5690 {
5691         u8 autoneg = bp->link_info.autoneg;
5692         u16 fw_link_speed = bp->link_info.req_link_speed;
5693         u16 advertising = bp->link_info.advertising;
5694
5695         if (autoneg & BNXT_AUTONEG_SPEED) {
5696                 req->auto_mode |=
5697                         PORT_PHY_CFG_REQ_AUTO_MODE_SPEED_MASK;
5698
5699                 req->enables |= cpu_to_le32(
5700                         PORT_PHY_CFG_REQ_ENABLES_AUTO_LINK_SPEED_MASK);
5701                 req->auto_link_speed_mask = cpu_to_le16(advertising);
5702
5703                 req->enables |= cpu_to_le32(PORT_PHY_CFG_REQ_ENABLES_AUTO_MODE);
5704                 req->flags |=
5705                         cpu_to_le32(PORT_PHY_CFG_REQ_FLAGS_RESTART_AUTONEG);
5706         } else {
5707                 req->force_link_speed = cpu_to_le16(fw_link_speed);
5708                 req->flags |= cpu_to_le32(PORT_PHY_CFG_REQ_FLAGS_FORCE);
5709         }
5710
5711         /* tell chimp that the setting takes effect immediately */
5712         req->flags |= cpu_to_le32(PORT_PHY_CFG_REQ_FLAGS_RESET_PHY);
5713 }
5714
5715 int bnxt_hwrm_set_pause(struct bnxt *bp)
5716 {
5717         struct hwrm_port_phy_cfg_input req = {0};
5718         int rc;
5719
5720         bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_PORT_PHY_CFG, -1, -1);
5721         bnxt_hwrm_set_pause_common(bp, &req);
5722
5723         if ((bp->link_info.autoneg & BNXT_AUTONEG_FLOW_CTRL) ||
5724             bp->link_info.force_link_chng)
5725                 bnxt_hwrm_set_link_common(bp, &req);
5726
5727         mutex_lock(&bp->hwrm_cmd_lock);
5728         rc = _hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT);
5729         if (!rc && !(bp->link_info.autoneg & BNXT_AUTONEG_FLOW_CTRL)) {
5730                 /* since changing of pause setting doesn't trigger any link
5731                  * change event, the driver needs to update the current pause
5732                  * result upon successfully return of the phy_cfg command
5733                  */
5734                 bp->link_info.pause =
5735                 bp->link_info.force_pause_setting = bp->link_info.req_flow_ctrl;
5736                 bp->link_info.auto_pause_setting = 0;
5737                 if (!bp->link_info.force_link_chng)
5738                         bnxt_report_link(bp);
5739         }
5740         bp->link_info.force_link_chng = false;
5741         mutex_unlock(&bp->hwrm_cmd_lock);
5742         return rc;
5743 }
5744
5745 static void bnxt_hwrm_set_eee(struct bnxt *bp,
5746                               struct hwrm_port_phy_cfg_input *req)
5747 {
5748         struct ethtool_eee *eee = &bp->eee;
5749
5750         if (eee->eee_enabled) {
5751                 u16 eee_speeds;
5752                 u32 flags = PORT_PHY_CFG_REQ_FLAGS_EEE_ENABLE;
5753
5754                 if (eee->tx_lpi_enabled)
5755                         flags |= PORT_PHY_CFG_REQ_FLAGS_EEE_TX_LPI_ENABLE;
5756                 else
5757                         flags |= PORT_PHY_CFG_REQ_FLAGS_EEE_TX_LPI_DISABLE;
5758
5759                 req->flags |= cpu_to_le32(flags);
5760                 eee_speeds = bnxt_get_fw_auto_link_speeds(eee->advertised);
5761                 req->eee_link_speed_mask = cpu_to_le16(eee_speeds);
5762                 req->tx_lpi_timer = cpu_to_le32(eee->tx_lpi_timer);
5763         } else {
5764                 req->flags |= cpu_to_le32(PORT_PHY_CFG_REQ_FLAGS_EEE_DISABLE);
5765         }
5766 }
5767
5768 int bnxt_hwrm_set_link_setting(struct bnxt *bp, bool set_pause, bool set_eee)
5769 {
5770         struct hwrm_port_phy_cfg_input req = {0};
5771
5772         bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_PORT_PHY_CFG, -1, -1);
5773         if (set_pause)
5774                 bnxt_hwrm_set_pause_common(bp, &req);
5775
5776         bnxt_hwrm_set_link_common(bp, &req);
5777
5778         if (set_eee)
5779                 bnxt_hwrm_set_eee(bp, &req);
5780         return hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT);
5781 }
5782
5783 static int bnxt_hwrm_shutdown_link(struct bnxt *bp)
5784 {
5785         struct hwrm_port_phy_cfg_input req = {0};
5786
5787         if (!BNXT_SINGLE_PF(bp))
5788                 return 0;
5789
5790         if (pci_num_vf(bp->pdev))
5791                 return 0;
5792
5793         bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_PORT_PHY_CFG, -1, -1);
5794         req.flags = cpu_to_le32(PORT_PHY_CFG_REQ_FLAGS_FORCE_LINK_DWN);
5795         return hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT);
5796 }
5797
5798 static int bnxt_hwrm_port_led_qcaps(struct bnxt *bp)
5799 {
5800         struct hwrm_port_led_qcaps_output *resp = bp->hwrm_cmd_resp_addr;
5801         struct hwrm_port_led_qcaps_input req = {0};
5802         struct bnxt_pf_info *pf = &bp->pf;
5803         int rc;
5804
5805         if (BNXT_VF(bp) || bp->hwrm_spec_code < 0x10601)
5806                 return 0;
5807
5808         bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_PORT_LED_QCAPS, -1, -1);
5809         req.port_id = cpu_to_le16(pf->port_id);
5810         mutex_lock(&bp->hwrm_cmd_lock);
5811         rc = _hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT);
5812         if (rc) {
5813                 mutex_unlock(&bp->hwrm_cmd_lock);
5814                 return rc;
5815         }
5816         if (resp->num_leds > 0 && resp->num_leds < BNXT_MAX_LED) {
5817                 int i;
5818
5819                 bp->num_leds = resp->num_leds;
5820                 memcpy(bp->leds, &resp->led0_id, sizeof(bp->leds[0]) *
5821                                                  bp->num_leds);
5822                 for (i = 0; i < bp->num_leds; i++) {
5823                         struct bnxt_led_info *led = &bp->leds[i];
5824                         __le16 caps = led->led_state_caps;
5825
5826                         if (!led->led_group_id ||
5827                             !BNXT_LED_ALT_BLINK_CAP(caps)) {
5828                                 bp->num_leds = 0;
5829                                 break;
5830                         }
5831                 }
5832         }
5833         mutex_unlock(&bp->hwrm_cmd_lock);
5834         return 0;
5835 }
5836
5837 static bool bnxt_eee_config_ok(struct bnxt *bp)
5838 {
5839         struct ethtool_eee *eee = &bp->eee;
5840         struct bnxt_link_info *link_info = &bp->link_info;
5841
5842         if (!(bp->flags & BNXT_FLAG_EEE_CAP))
5843                 return true;
5844
5845         if (eee->eee_enabled) {
5846                 u32 advertising =
5847                         _bnxt_fw_to_ethtool_adv_spds(link_info->advertising, 0);
5848
5849                 if (!(link_info->autoneg & BNXT_AUTONEG_SPEED)) {
5850                         eee->eee_enabled = 0;
5851                         return false;
5852                 }
5853                 if (eee->advertised & ~advertising) {
5854                         eee->advertised = advertising & eee->supported;
5855                         return false;
5856                 }
5857         }
5858         return true;
5859 }
5860
5861 static int bnxt_update_phy_setting(struct bnxt *bp)
5862 {
5863         int rc;
5864         bool update_link = false;
5865         bool update_pause = false;
5866         bool update_eee = false;
5867         struct bnxt_link_info *link_info = &bp->link_info;
5868
5869         rc = bnxt_update_link(bp, true);
5870         if (rc) {
5871                 netdev_err(bp->dev, "failed to update link (rc: %x)\n",
5872                            rc);
5873                 return rc;
5874         }
5875         if (!BNXT_SINGLE_PF(bp))
5876                 return 0;
5877
5878         if ((link_info->autoneg & BNXT_AUTONEG_FLOW_CTRL) &&
5879             (link_info->auto_pause_setting & BNXT_LINK_PAUSE_BOTH) !=
5880             link_info->req_flow_ctrl)
5881                 update_pause = true;
5882         if (!(link_info->autoneg & BNXT_AUTONEG_FLOW_CTRL) &&
5883             link_info->force_pause_setting != link_info->req_flow_ctrl)
5884                 update_pause = true;
5885         if (!(link_info->autoneg & BNXT_AUTONEG_SPEED)) {
5886                 if (BNXT_AUTO_MODE(link_info->auto_mode))
5887                         update_link = true;
5888                 if (link_info->req_link_speed != link_info->force_link_speed)
5889                         update_link = true;
5890                 if (link_info->req_duplex != link_info->duplex_setting)
5891                         update_link = true;
5892         } else {
5893                 if (link_info->auto_mode == BNXT_LINK_AUTO_NONE)
5894                         update_link = true;
5895                 if (link_info->advertising != link_info->auto_link_speeds)
5896                         update_link = true;
5897         }
5898
5899         /* The last close may have shutdown the link, so need to call
5900          * PHY_CFG to bring it back up.
5901          */
5902         if (!netif_carrier_ok(bp->dev))
5903                 update_link = true;
5904
5905         if (!bnxt_eee_config_ok(bp))
5906                 update_eee = true;
5907
5908         if (update_link)
5909                 rc = bnxt_hwrm_set_link_setting(bp, update_pause, update_eee);
5910         else if (update_pause)
5911                 rc = bnxt_hwrm_set_pause(bp);
5912         if (rc) {
5913                 netdev_err(bp->dev, "failed to update phy setting (rc: %x)\n",
5914                            rc);
5915                 return rc;
5916         }
5917
5918         return rc;
5919 }
5920
5921 /* Common routine to pre-map certain register block to different GRC window.
5922  * A PF has 16 4K windows and a VF has 4 4K windows. However, only 15 windows
5923  * in PF and 3 windows in VF that can be customized to map in different
5924  * register blocks.
5925  */
5926 static void bnxt_preset_reg_win(struct bnxt *bp)
5927 {
5928         if (BNXT_PF(bp)) {
5929                 /* CAG registers map to GRC window #4 */
5930                 writel(BNXT_CAG_REG_BASE,
5931                        bp->bar0 + BNXT_GRCPF_REG_WINDOW_BASE_OUT + 12);
5932         }
5933 }
5934
5935 static int __bnxt_open_nic(struct bnxt *bp, bool irq_re_init, bool link_re_init)
5936 {
5937         int rc = 0;
5938
5939         bnxt_preset_reg_win(bp);
5940         netif_carrier_off(bp->dev);
5941         if (irq_re_init) {
5942                 rc = bnxt_setup_int_mode(bp);
5943                 if (rc) {
5944                         netdev_err(bp->dev, "bnxt_setup_int_mode err: %x\n",
5945                                    rc);
5946                         return rc;
5947                 }
5948         }
5949         if ((bp->flags & BNXT_FLAG_RFS) &&
5950             !(bp->flags & BNXT_FLAG_USING_MSIX)) {
5951                 /* disable RFS if falling back to INTA */
5952                 bp->dev->hw_features &= ~NETIF_F_NTUPLE;
5953                 bp->flags &= ~BNXT_FLAG_RFS;
5954         }
5955
5956         rc = bnxt_alloc_mem(bp, irq_re_init);
5957         if (rc) {
5958                 netdev_err(bp->dev, "bnxt_alloc_mem err: %x\n", rc);
5959                 goto open_err_free_mem;
5960         }
5961
5962         if (irq_re_init) {
5963                 bnxt_init_napi(bp);
5964                 rc = bnxt_request_irq(bp);
5965                 if (rc) {
5966                         netdev_err(bp->dev, "bnxt_request_irq err: %x\n", rc);
5967                         goto open_err;
5968                 }
5969         }
5970
5971         bnxt_enable_napi(bp);
5972
5973         rc = bnxt_init_nic(bp, irq_re_init);
5974         if (rc) {
5975                 netdev_err(bp->dev, "bnxt_init_nic err: %x\n", rc);
5976                 goto open_err;
5977         }
5978
5979         if (link_re_init) {
5980                 rc = bnxt_update_phy_setting(bp);
5981                 if (rc)
5982                         netdev_warn(bp->dev, "failed to update phy settings\n");
5983         }
5984
5985         if (irq_re_init)
5986                 udp_tunnel_get_rx_info(bp->dev);
5987
5988         set_bit(BNXT_STATE_OPEN, &bp->state);
5989         bnxt_enable_int(bp);
5990         /* Enable TX queues */
5991         bnxt_tx_enable(bp);
5992         mod_timer(&bp->timer, jiffies + bp->current_interval);
5993         /* Poll link status and check for SFP+ module status */
5994         bnxt_get_port_module_status(bp);
5995
5996         return 0;
5997
5998 open_err:
5999         bnxt_disable_napi(bp);
6000         bnxt_del_napi(bp);
6001
6002 open_err_free_mem:
6003         bnxt_free_skbs(bp);
6004         bnxt_free_irq(bp);
6005         bnxt_free_mem(bp, true);
6006         return rc;
6007 }
6008
6009 /* rtnl_lock held */
6010 int bnxt_open_nic(struct bnxt *bp, bool irq_re_init, bool link_re_init)
6011 {
6012         int rc = 0;
6013
6014         rc = __bnxt_open_nic(bp, irq_re_init, link_re_init);
6015         if (rc) {
6016                 netdev_err(bp->dev, "nic open fail (rc: %x)\n", rc);
6017                 dev_close(bp->dev);
6018         }
6019         return rc;
6020 }
6021
6022 static int bnxt_open(struct net_device *dev)
6023 {
6024         struct bnxt *bp = netdev_priv(dev);
6025
6026         return __bnxt_open_nic(bp, true, true);
6027 }
6028
6029 int bnxt_close_nic(struct bnxt *bp, bool irq_re_init, bool link_re_init)
6030 {
6031         int rc = 0;
6032
6033 #ifdef CONFIG_BNXT_SRIOV
6034         if (bp->sriov_cfg) {
6035                 rc = wait_event_interruptible_timeout(bp->sriov_cfg_wait,
6036                                                       !bp->sriov_cfg,
6037                                                       BNXT_SRIOV_CFG_WAIT_TMO);
6038                 if (rc)
6039                         netdev_warn(bp->dev, "timeout waiting for SRIOV config operation to complete!\n");
6040         }
6041 #endif
6042         /* Change device state to avoid TX queue wake up's */
6043         bnxt_tx_disable(bp);
6044
6045         clear_bit(BNXT_STATE_OPEN, &bp->state);
6046         smp_mb__after_atomic();
6047         while (test_bit(BNXT_STATE_IN_SP_TASK, &bp->state))
6048                 msleep(20);
6049
6050         /* Flush rings and and disable interrupts */
6051         bnxt_shutdown_nic(bp, irq_re_init);
6052
6053         /* TODO CHIMP_FW: Link/PHY related cleanup if (link_re_init) */
6054
6055         bnxt_disable_napi(bp);
6056         del_timer_sync(&bp->timer);
6057         bnxt_free_skbs(bp);
6058
6059         if (irq_re_init) {
6060                 bnxt_free_irq(bp);
6061                 bnxt_del_napi(bp);
6062         }
6063         bnxt_free_mem(bp, irq_re_init);
6064         return rc;
6065 }
6066
6067 static int bnxt_close(struct net_device *dev)
6068 {
6069         struct bnxt *bp = netdev_priv(dev);
6070
6071         bnxt_close_nic(bp, true, true);
6072         bnxt_hwrm_shutdown_link(bp);
6073         return 0;
6074 }
6075
6076 /* rtnl_lock held */
6077 static int bnxt_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd)
6078 {
6079         switch (cmd) {
6080         case SIOCGMIIPHY:
6081                 /* fallthru */
6082         case SIOCGMIIREG: {
6083                 if (!netif_running(dev))
6084                         return -EAGAIN;
6085
6086                 return 0;
6087         }
6088
6089         case SIOCSMIIREG:
6090                 if (!netif_running(dev))
6091                         return -EAGAIN;
6092
6093                 return 0;
6094
6095         default:
6096                 /* do nothing */
6097                 break;
6098         }
6099         return -EOPNOTSUPP;
6100 }
6101
6102 static void
6103 bnxt_get_stats64(struct net_device *dev, struct rtnl_link_stats64 *stats)
6104 {
6105         u32 i;
6106         struct bnxt *bp = netdev_priv(dev);
6107
6108         if (!bp->bnapi)
6109                 return;
6110
6111         /* TODO check if we need to synchronize with bnxt_close path */
6112         for (i = 0; i < bp->cp_nr_rings; i++) {
6113                 struct bnxt_napi *bnapi = bp->bnapi[i];
6114                 struct bnxt_cp_ring_info *cpr = &bnapi->cp_ring;
6115                 struct ctx_hw_stats *hw_stats = cpr->hw_stats;
6116
6117                 stats->rx_packets += le64_to_cpu(hw_stats->rx_ucast_pkts);
6118                 stats->rx_packets += le64_to_cpu(hw_stats->rx_mcast_pkts);
6119                 stats->rx_packets += le64_to_cpu(hw_stats->rx_bcast_pkts);
6120
6121                 stats->tx_packets += le64_to_cpu(hw_stats->tx_ucast_pkts);
6122                 stats->tx_packets += le64_to_cpu(hw_stats->tx_mcast_pkts);
6123                 stats->tx_packets += le64_to_cpu(hw_stats->tx_bcast_pkts);
6124
6125                 stats->rx_bytes += le64_to_cpu(hw_stats->rx_ucast_bytes);
6126                 stats->rx_bytes += le64_to_cpu(hw_stats->rx_mcast_bytes);
6127                 stats->rx_bytes += le64_to_cpu(hw_stats->rx_bcast_bytes);
6128
6129                 stats->tx_bytes += le64_to_cpu(hw_stats->tx_ucast_bytes);
6130                 stats->tx_bytes += le64_to_cpu(hw_stats->tx_mcast_bytes);
6131                 stats->tx_bytes += le64_to_cpu(hw_stats->tx_bcast_bytes);
6132
6133                 stats->rx_missed_errors +=
6134                         le64_to_cpu(hw_stats->rx_discard_pkts);
6135
6136                 stats->multicast += le64_to_cpu(hw_stats->rx_mcast_pkts);
6137
6138                 stats->tx_dropped += le64_to_cpu(hw_stats->tx_drop_pkts);
6139         }
6140
6141         if (bp->flags & BNXT_FLAG_PORT_STATS) {
6142                 struct rx_port_stats *rx = bp->hw_rx_port_stats;
6143                 struct tx_port_stats *tx = bp->hw_tx_port_stats;
6144
6145                 stats->rx_crc_errors = le64_to_cpu(rx->rx_fcs_err_frames);
6146                 stats->rx_frame_errors = le64_to_cpu(rx->rx_align_err_frames);
6147                 stats->rx_length_errors = le64_to_cpu(rx->rx_undrsz_frames) +
6148                                           le64_to_cpu(rx->rx_ovrsz_frames) +
6149                                           le64_to_cpu(rx->rx_runt_frames);
6150                 stats->rx_errors = le64_to_cpu(rx->rx_false_carrier_frames) +
6151                                    le64_to_cpu(rx->rx_jbr_frames);
6152                 stats->collisions = le64_to_cpu(tx->tx_total_collisions);
6153                 stats->tx_fifo_errors = le64_to_cpu(tx->tx_fifo_underruns);
6154                 stats->tx_errors = le64_to_cpu(tx->tx_err);
6155         }
6156 }
6157
6158 static bool bnxt_mc_list_updated(struct bnxt *bp, u32 *rx_mask)
6159 {
6160         struct net_device *dev = bp->dev;
6161         struct bnxt_vnic_info *vnic = &bp->vnic_info[0];
6162         struct netdev_hw_addr *ha;
6163         u8 *haddr;
6164         int mc_count = 0;
6165         bool update = false;
6166         int off = 0;
6167
6168         netdev_for_each_mc_addr(ha, dev) {
6169                 if (mc_count >= BNXT_MAX_MC_ADDRS) {
6170                         *rx_mask |= CFA_L2_SET_RX_MASK_REQ_MASK_ALL_MCAST;
6171                         vnic->mc_list_count = 0;
6172                         return false;
6173                 }
6174                 haddr = ha->addr;
6175                 if (!ether_addr_equal(haddr, vnic->mc_list + off)) {
6176                         memcpy(vnic->mc_list + off, haddr, ETH_ALEN);
6177                         update = true;
6178                 }
6179                 off += ETH_ALEN;
6180                 mc_count++;
6181         }
6182         if (mc_count)
6183                 *rx_mask |= CFA_L2_SET_RX_MASK_REQ_MASK_MCAST;
6184
6185         if (mc_count != vnic->mc_list_count) {
6186                 vnic->mc_list_count = mc_count;
6187                 update = true;
6188         }
6189         return update;
6190 }
6191
6192 static bool bnxt_uc_list_updated(struct bnxt *bp)
6193 {
6194         struct net_device *dev = bp->dev;
6195         struct bnxt_vnic_info *vnic = &bp->vnic_info[0];
6196         struct netdev_hw_addr *ha;
6197         int off = 0;
6198
6199         if (netdev_uc_count(dev) != (vnic->uc_filter_count - 1))
6200                 return true;
6201
6202         netdev_for_each_uc_addr(ha, dev) {
6203                 if (!ether_addr_equal(ha->addr, vnic->uc_list + off))
6204                         return true;
6205
6206                 off += ETH_ALEN;
6207         }
6208         return false;
6209 }
6210
6211 static void bnxt_set_rx_mode(struct net_device *dev)
6212 {
6213         struct bnxt *bp = netdev_priv(dev);
6214         struct bnxt_vnic_info *vnic = &bp->vnic_info[0];
6215         u32 mask = vnic->rx_mask;
6216         bool mc_update = false;
6217         bool uc_update;
6218
6219         if (!netif_running(dev))
6220                 return;
6221
6222         mask &= ~(CFA_L2_SET_RX_MASK_REQ_MASK_PROMISCUOUS |
6223                   CFA_L2_SET_RX_MASK_REQ_MASK_MCAST |
6224                   CFA_L2_SET_RX_MASK_REQ_MASK_ALL_MCAST);
6225
6226         if ((dev->flags & IFF_PROMISC) && bnxt_promisc_ok(bp))
6227                 mask |= CFA_L2_SET_RX_MASK_REQ_MASK_PROMISCUOUS;
6228
6229         uc_update = bnxt_uc_list_updated(bp);
6230
6231         if (dev->flags & IFF_ALLMULTI) {
6232                 mask |= CFA_L2_SET_RX_MASK_REQ_MASK_ALL_MCAST;
6233                 vnic->mc_list_count = 0;
6234         } else {
6235                 mc_update = bnxt_mc_list_updated(bp, &mask);
6236         }
6237
6238         if (mask != vnic->rx_mask || uc_update || mc_update) {
6239                 vnic->rx_mask = mask;
6240
6241                 set_bit(BNXT_RX_MASK_SP_EVENT, &bp->sp_event);
6242                 schedule_work(&bp->sp_task);
6243         }
6244 }
6245
6246 static int bnxt_cfg_rx_mode(struct bnxt *bp)
6247 {
6248         struct net_device *dev = bp->dev;
6249         struct bnxt_vnic_info *vnic = &bp->vnic_info[0];
6250         struct netdev_hw_addr *ha;
6251         int i, off = 0, rc;
6252         bool uc_update;
6253
6254         netif_addr_lock_bh(dev);
6255         uc_update = bnxt_uc_list_updated(bp);
6256         netif_addr_unlock_bh(dev);
6257
6258         if (!uc_update)
6259                 goto skip_uc;
6260
6261         mutex_lock(&bp->hwrm_cmd_lock);
6262         for (i = 1; i < vnic->uc_filter_count; i++) {
6263                 struct hwrm_cfa_l2_filter_free_input req = {0};
6264
6265                 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_CFA_L2_FILTER_FREE, -1,
6266                                        -1);
6267
6268                 req.l2_filter_id = vnic->fw_l2_filter_id[i];
6269
6270                 rc = _hwrm_send_message(bp, &req, sizeof(req),
6271                                         HWRM_CMD_TIMEOUT);
6272         }
6273         mutex_unlock(&bp->hwrm_cmd_lock);
6274
6275         vnic->uc_filter_count = 1;
6276
6277         netif_addr_lock_bh(dev);
6278         if (netdev_uc_count(dev) > (BNXT_MAX_UC_ADDRS - 1)) {
6279                 vnic->rx_mask |= CFA_L2_SET_RX_MASK_REQ_MASK_PROMISCUOUS;
6280         } else {
6281                 netdev_for_each_uc_addr(ha, dev) {
6282                         memcpy(vnic->uc_list + off, ha->addr, ETH_ALEN);
6283                         off += ETH_ALEN;
6284                         vnic->uc_filter_count++;
6285                 }
6286         }
6287         netif_addr_unlock_bh(dev);
6288
6289         for (i = 1, off = 0; i < vnic->uc_filter_count; i++, off += ETH_ALEN) {
6290                 rc = bnxt_hwrm_set_vnic_filter(bp, 0, i, vnic->uc_list + off);
6291                 if (rc) {
6292                         netdev_err(bp->dev, "HWRM vnic filter failure rc: %x\n",
6293                                    rc);
6294                         vnic->uc_filter_count = i;
6295                         return rc;
6296                 }
6297         }
6298
6299 skip_uc:
6300         rc = bnxt_hwrm_cfa_l2_set_rx_mask(bp, 0);
6301         if (rc)
6302                 netdev_err(bp->dev, "HWRM cfa l2 rx mask failure rc: %x\n",
6303                            rc);
6304
6305         return rc;
6306 }
6307
6308 /* If the chip and firmware supports RFS */
6309 static bool bnxt_rfs_supported(struct bnxt *bp)
6310 {
6311         if (BNXT_PF(bp) && !BNXT_CHIP_TYPE_NITRO_A0(bp))
6312                 return true;
6313         if (bp->flags & BNXT_FLAG_NEW_RSS_CAP)
6314                 return true;
6315         return false;
6316 }
6317
6318 /* If runtime conditions support RFS */
6319 static bool bnxt_rfs_capable(struct bnxt *bp)
6320 {
6321 #ifdef CONFIG_RFS_ACCEL
6322         int vnics, max_vnics, max_rss_ctxs;
6323
6324         if (!(bp->flags & BNXT_FLAG_MSIX_CAP))
6325                 return false;
6326
6327         vnics = 1 + bp->rx_nr_rings;
6328         max_vnics = bnxt_get_max_func_vnics(bp);
6329         max_rss_ctxs = bnxt_get_max_func_rss_ctxs(bp);
6330
6331         /* RSS contexts not a limiting factor */
6332         if (bp->flags & BNXT_FLAG_NEW_RSS_CAP)
6333                 max_rss_ctxs = max_vnics;
6334         if (vnics > max_vnics || vnics > max_rss_ctxs) {
6335                 netdev_warn(bp->dev,
6336                             "Not enough resources to support NTUPLE filters, enough resources for up to %d rx rings\n",
6337                             min(max_rss_ctxs - 1, max_vnics - 1));
6338                 return false;
6339         }
6340
6341         return true;
6342 #else
6343         return false;
6344 #endif
6345 }
6346
6347 static netdev_features_t bnxt_fix_features(struct net_device *dev,
6348                                            netdev_features_t features)
6349 {
6350         struct bnxt *bp = netdev_priv(dev);
6351
6352         if ((features & NETIF_F_NTUPLE) && !bnxt_rfs_capable(bp))
6353                 features &= ~NETIF_F_NTUPLE;
6354
6355         /* Both CTAG and STAG VLAN accelaration on the RX side have to be
6356          * turned on or off together.
6357          */
6358         if ((features & (NETIF_F_HW_VLAN_CTAG_RX | NETIF_F_HW_VLAN_STAG_RX)) !=
6359             (NETIF_F_HW_VLAN_CTAG_RX | NETIF_F_HW_VLAN_STAG_RX)) {
6360                 if (dev->features & NETIF_F_HW_VLAN_CTAG_RX)
6361                         features &= ~(NETIF_F_HW_VLAN_CTAG_RX |
6362                                       NETIF_F_HW_VLAN_STAG_RX);
6363                 else
6364                         features |= NETIF_F_HW_VLAN_CTAG_RX |
6365                                     NETIF_F_HW_VLAN_STAG_RX;
6366         }
6367 #ifdef CONFIG_BNXT_SRIOV
6368         if (BNXT_VF(bp)) {
6369                 if (bp->vf.vlan) {
6370                         features &= ~(NETIF_F_HW_VLAN_CTAG_RX |
6371                                       NETIF_F_HW_VLAN_STAG_RX);
6372                 }
6373         }
6374 #endif
6375         return features;
6376 }
6377
6378 static int bnxt_set_features(struct net_device *dev, netdev_features_t features)
6379 {
6380         struct bnxt *bp = netdev_priv(dev);
6381         u32 flags = bp->flags;
6382         u32 changes;
6383         int rc = 0;
6384         bool re_init = false;
6385         bool update_tpa = false;
6386
6387         flags &= ~BNXT_FLAG_ALL_CONFIG_FEATS;
6388         if ((features & NETIF_F_GRO) && !BNXT_CHIP_TYPE_NITRO_A0(bp))
6389                 flags |= BNXT_FLAG_GRO;
6390         if (features & NETIF_F_LRO)
6391                 flags |= BNXT_FLAG_LRO;
6392
6393         if (bp->flags & BNXT_FLAG_NO_AGG_RINGS)
6394                 flags &= ~BNXT_FLAG_TPA;
6395
6396         if (features & NETIF_F_HW_VLAN_CTAG_RX)
6397                 flags |= BNXT_FLAG_STRIP_VLAN;
6398
6399         if (features & NETIF_F_NTUPLE)
6400                 flags |= BNXT_FLAG_RFS;
6401
6402         changes = flags ^ bp->flags;
6403         if (changes & BNXT_FLAG_TPA) {
6404                 update_tpa = true;
6405                 if ((bp->flags & BNXT_FLAG_TPA) == 0 ||
6406                     (flags & BNXT_FLAG_TPA) == 0)
6407                         re_init = true;
6408         }
6409
6410         if (changes & ~BNXT_FLAG_TPA)
6411                 re_init = true;
6412
6413         if (flags != bp->flags) {
6414                 u32 old_flags = bp->flags;
6415
6416                 bp->flags = flags;
6417
6418                 if (!test_bit(BNXT_STATE_OPEN, &bp->state)) {
6419                         if (update_tpa)
6420                                 bnxt_set_ring_params(bp);
6421                         return rc;
6422                 }
6423
6424                 if (re_init) {
6425                         bnxt_close_nic(bp, false, false);
6426                         if (update_tpa)
6427                                 bnxt_set_ring_params(bp);
6428
6429                         return bnxt_open_nic(bp, false, false);
6430                 }
6431                 if (update_tpa) {
6432                         rc = bnxt_set_tpa(bp,
6433                                           (flags & BNXT_FLAG_TPA) ?
6434                                           true : false);
6435                         if (rc)
6436                                 bp->flags = old_flags;
6437                 }
6438         }
6439         return rc;
6440 }
6441
6442 static void bnxt_dump_tx_sw_state(struct bnxt_napi *bnapi)
6443 {
6444         struct bnxt_tx_ring_info *txr = bnapi->tx_ring;
6445         int i = bnapi->index;
6446
6447         if (!txr)
6448                 return;
6449
6450         netdev_info(bnapi->bp->dev, "[%d]: tx{fw_ring: %d prod: %x cons: %x}\n",
6451                     i, txr->tx_ring_struct.fw_ring_id, txr->tx_prod,
6452                     txr->tx_cons);
6453 }
6454
6455 static void bnxt_dump_rx_sw_state(struct bnxt_napi *bnapi)
6456 {
6457         struct bnxt_rx_ring_info *rxr = bnapi->rx_ring;
6458         int i = bnapi->index;
6459
6460         if (!rxr)
6461                 return;
6462
6463         netdev_info(bnapi->bp->dev, "[%d]: rx{fw_ring: %d prod: %x} rx_agg{fw_ring: %d agg_prod: %x sw_agg_prod: %x}\n",
6464                     i, rxr->rx_ring_struct.fw_ring_id, rxr->rx_prod,
6465                     rxr->rx_agg_ring_struct.fw_ring_id, rxr->rx_agg_prod,
6466                     rxr->rx_sw_agg_prod);
6467 }
6468
6469 static void bnxt_dump_cp_sw_state(struct bnxt_napi *bnapi)
6470 {
6471         struct bnxt_cp_ring_info *cpr = &bnapi->cp_ring;
6472         int i = bnapi->index;
6473
6474         netdev_info(bnapi->bp->dev, "[%d]: cp{fw_ring: %d raw_cons: %x}\n",
6475                     i, cpr->cp_ring_struct.fw_ring_id, cpr->cp_raw_cons);
6476 }
6477
6478 static void bnxt_dbg_dump_states(struct bnxt *bp)
6479 {
6480         int i;
6481         struct bnxt_napi *bnapi;
6482
6483         for (i = 0; i < bp->cp_nr_rings; i++) {
6484                 bnapi = bp->bnapi[i];
6485                 if (netif_msg_drv(bp)) {
6486                         bnxt_dump_tx_sw_state(bnapi);
6487                         bnxt_dump_rx_sw_state(bnapi);
6488                         bnxt_dump_cp_sw_state(bnapi);
6489                 }
6490         }
6491 }
6492
6493 static void bnxt_reset_task(struct bnxt *bp, bool silent)
6494 {
6495         if (!silent)
6496                 bnxt_dbg_dump_states(bp);
6497         if (netif_running(bp->dev)) {
6498                 bnxt_close_nic(bp, false, false);
6499                 bnxt_open_nic(bp, false, false);
6500         }
6501 }
6502
6503 static void bnxt_tx_timeout(struct net_device *dev)
6504 {
6505         struct bnxt *bp = netdev_priv(dev);
6506
6507         netdev_err(bp->dev,  "TX timeout detected, starting reset task!\n");
6508         set_bit(BNXT_RESET_TASK_SP_EVENT, &bp->sp_event);
6509         schedule_work(&bp->sp_task);
6510 }
6511
6512 #ifdef CONFIG_NET_POLL_CONTROLLER
6513 static void bnxt_poll_controller(struct net_device *dev)
6514 {
6515         struct bnxt *bp = netdev_priv(dev);
6516         int i;
6517
6518         for (i = 0; i < bp->cp_nr_rings; i++) {
6519                 struct bnxt_irq *irq = &bp->irq_tbl[i];
6520
6521                 disable_irq(irq->vector);
6522                 irq->handler(irq->vector, bp->bnapi[i]);
6523                 enable_irq(irq->vector);
6524         }
6525 }
6526 #endif
6527
6528 static void bnxt_timer(unsigned long data)
6529 {
6530         struct bnxt *bp = (struct bnxt *)data;
6531         struct net_device *dev = bp->dev;
6532
6533         if (!netif_running(dev))
6534                 return;
6535
6536         if (atomic_read(&bp->intr_sem) != 0)
6537                 goto bnxt_restart_timer;
6538
6539         if (bp->link_info.link_up && (bp->flags & BNXT_FLAG_PORT_STATS)) {
6540                 set_bit(BNXT_PERIODIC_STATS_SP_EVENT, &bp->sp_event);
6541                 schedule_work(&bp->sp_task);
6542         }
6543 bnxt_restart_timer:
6544         mod_timer(&bp->timer, jiffies + bp->current_interval);
6545 }
6546
6547 static void bnxt_rtnl_lock_sp(struct bnxt *bp)
6548 {
6549         /* We are called from bnxt_sp_task which has BNXT_STATE_IN_SP_TASK
6550          * set.  If the device is being closed, bnxt_close() may be holding
6551          * rtnl() and waiting for BNXT_STATE_IN_SP_TASK to clear.  So we
6552          * must clear BNXT_STATE_IN_SP_TASK before holding rtnl().
6553          */
6554         clear_bit(BNXT_STATE_IN_SP_TASK, &bp->state);
6555         rtnl_lock();
6556 }
6557
6558 static void bnxt_rtnl_unlock_sp(struct bnxt *bp)
6559 {
6560         set_bit(BNXT_STATE_IN_SP_TASK, &bp->state);
6561         rtnl_unlock();
6562 }
6563
6564 /* Only called from bnxt_sp_task() */
6565 static void bnxt_reset(struct bnxt *bp, bool silent)
6566 {
6567         bnxt_rtnl_lock_sp(bp);
6568         if (test_bit(BNXT_STATE_OPEN, &bp->state))
6569                 bnxt_reset_task(bp, silent);
6570         bnxt_rtnl_unlock_sp(bp);
6571 }
6572
6573 static void bnxt_cfg_ntp_filters(struct bnxt *);
6574
6575 static void bnxt_sp_task(struct work_struct *work)
6576 {
6577         struct bnxt *bp = container_of(work, struct bnxt, sp_task);
6578
6579         set_bit(BNXT_STATE_IN_SP_TASK, &bp->state);
6580         smp_mb__after_atomic();
6581         if (!test_bit(BNXT_STATE_OPEN, &bp->state)) {
6582                 clear_bit(BNXT_STATE_IN_SP_TASK, &bp->state);
6583                 return;
6584         }
6585
6586         if (test_and_clear_bit(BNXT_RX_MASK_SP_EVENT, &bp->sp_event))
6587                 bnxt_cfg_rx_mode(bp);
6588
6589         if (test_and_clear_bit(BNXT_RX_NTP_FLTR_SP_EVENT, &bp->sp_event))
6590                 bnxt_cfg_ntp_filters(bp);
6591         if (test_and_clear_bit(BNXT_HWRM_EXEC_FWD_REQ_SP_EVENT, &bp->sp_event))
6592                 bnxt_hwrm_exec_fwd_req(bp);
6593         if (test_and_clear_bit(BNXT_VXLAN_ADD_PORT_SP_EVENT, &bp->sp_event)) {
6594                 bnxt_hwrm_tunnel_dst_port_alloc(
6595                         bp, bp->vxlan_port,
6596                         TUNNEL_DST_PORT_FREE_REQ_TUNNEL_TYPE_VXLAN);
6597         }
6598         if (test_and_clear_bit(BNXT_VXLAN_DEL_PORT_SP_EVENT, &bp->sp_event)) {
6599                 bnxt_hwrm_tunnel_dst_port_free(
6600                         bp, TUNNEL_DST_PORT_FREE_REQ_TUNNEL_TYPE_VXLAN);
6601         }
6602         if (test_and_clear_bit(BNXT_GENEVE_ADD_PORT_SP_EVENT, &bp->sp_event)) {
6603                 bnxt_hwrm_tunnel_dst_port_alloc(
6604                         bp, bp->nge_port,
6605                         TUNNEL_DST_PORT_FREE_REQ_TUNNEL_TYPE_GENEVE);
6606         }
6607         if (test_and_clear_bit(BNXT_GENEVE_DEL_PORT_SP_EVENT, &bp->sp_event)) {
6608                 bnxt_hwrm_tunnel_dst_port_free(
6609                         bp, TUNNEL_DST_PORT_FREE_REQ_TUNNEL_TYPE_GENEVE);
6610         }
6611         if (test_and_clear_bit(BNXT_PERIODIC_STATS_SP_EVENT, &bp->sp_event))
6612                 bnxt_hwrm_port_qstats(bp);
6613
6614         /* These functions below will clear BNXT_STATE_IN_SP_TASK.  They
6615          * must be the last functions to be called before exiting.
6616          */
6617         if (test_and_clear_bit(BNXT_LINK_CHNG_SP_EVENT, &bp->sp_event)) {
6618                 int rc = 0;
6619
6620                 if (test_and_clear_bit(BNXT_LINK_SPEED_CHNG_SP_EVENT,
6621                                        &bp->sp_event))
6622                         bnxt_hwrm_phy_qcaps(bp);
6623
6624                 bnxt_rtnl_lock_sp(bp);
6625                 if (test_bit(BNXT_STATE_OPEN, &bp->state))
6626                         rc = bnxt_update_link(bp, true);
6627                 bnxt_rtnl_unlock_sp(bp);
6628                 if (rc)
6629                         netdev_err(bp->dev, "SP task can't update link (rc: %x)\n",
6630                                    rc);
6631         }
6632         if (test_and_clear_bit(BNXT_HWRM_PORT_MODULE_SP_EVENT, &bp->sp_event)) {
6633                 bnxt_rtnl_lock_sp(bp);
6634                 if (test_bit(BNXT_STATE_OPEN, &bp->state))
6635                         bnxt_get_port_module_status(bp);
6636                 bnxt_rtnl_unlock_sp(bp);
6637         }
6638         if (test_and_clear_bit(BNXT_RESET_TASK_SP_EVENT, &bp->sp_event))
6639                 bnxt_reset(bp, false);
6640
6641         if (test_and_clear_bit(BNXT_RESET_TASK_SILENT_SP_EVENT, &bp->sp_event))
6642                 bnxt_reset(bp, true);
6643
6644         smp_mb__before_atomic();
6645         clear_bit(BNXT_STATE_IN_SP_TASK, &bp->state);
6646 }
6647
6648 /* Under rtnl_lock */
6649 int bnxt_reserve_rings(struct bnxt *bp, int tx, int rx, int tcs, int tx_xdp)
6650 {
6651         int max_rx, max_tx, tx_sets = 1;
6652         int tx_rings_needed;
6653         bool sh = true;
6654         int rc;
6655
6656         if (!(bp->flags & BNXT_FLAG_SHARED_RINGS))
6657                 sh = false;
6658
6659         if (tcs)
6660                 tx_sets = tcs;
6661
6662         rc = bnxt_get_max_rings(bp, &max_rx, &max_tx, sh);
6663         if (rc)
6664                 return rc;
6665
6666         if (max_rx < rx)
6667                 return -ENOMEM;
6668
6669         tx_rings_needed = tx * tx_sets + tx_xdp;
6670         if (max_tx < tx_rings_needed)
6671                 return -ENOMEM;
6672
6673         if (bnxt_hwrm_reserve_tx_rings(bp, &tx_rings_needed) ||
6674             tx_rings_needed < (tx * tx_sets + tx_xdp))
6675                 return -ENOMEM;
6676         return 0;
6677 }
6678
6679 static void bnxt_unmap_bars(struct bnxt *bp, struct pci_dev *pdev)
6680 {
6681         if (bp->bar2) {
6682                 pci_iounmap(pdev, bp->bar2);
6683                 bp->bar2 = NULL;
6684         }
6685
6686         if (bp->bar1) {
6687                 pci_iounmap(pdev, bp->bar1);
6688                 bp->bar1 = NULL;
6689         }
6690
6691         if (bp->bar0) {
6692                 pci_iounmap(pdev, bp->bar0);
6693                 bp->bar0 = NULL;
6694         }
6695 }
6696
6697 static void bnxt_cleanup_pci(struct bnxt *bp)
6698 {
6699         bnxt_unmap_bars(bp, bp->pdev);
6700         pci_release_regions(bp->pdev);
6701         pci_disable_device(bp->pdev);
6702 }
6703
6704 static int bnxt_init_board(struct pci_dev *pdev, struct net_device *dev)
6705 {
6706         int rc;
6707         struct bnxt *bp = netdev_priv(dev);
6708
6709         SET_NETDEV_DEV(dev, &pdev->dev);
6710
6711         /* enable device (incl. PCI PM wakeup), and bus-mastering */
6712         rc = pci_enable_device(pdev);
6713         if (rc) {
6714                 dev_err(&pdev->dev, "Cannot enable PCI device, aborting\n");
6715                 goto init_err;
6716         }
6717
6718         if (!(pci_resource_flags(pdev, 0) & IORESOURCE_MEM)) {
6719                 dev_err(&pdev->dev,
6720                         "Cannot find PCI device base address, aborting\n");
6721                 rc = -ENODEV;
6722                 goto init_err_disable;
6723         }
6724
6725         rc = pci_request_regions(pdev, DRV_MODULE_NAME);
6726         if (rc) {
6727                 dev_err(&pdev->dev, "Cannot obtain PCI resources, aborting\n");
6728                 goto init_err_disable;
6729         }
6730
6731         if (dma_set_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(64)) != 0 &&
6732             dma_set_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(32)) != 0) {
6733                 dev_err(&pdev->dev, "System does not support DMA, aborting\n");
6734                 goto init_err_disable;
6735         }
6736
6737         pci_set_master(pdev);
6738
6739         bp->dev = dev;
6740         bp->pdev = pdev;
6741
6742         bp->bar0 = pci_ioremap_bar(pdev, 0);
6743         if (!bp->bar0) {
6744                 dev_err(&pdev->dev, "Cannot map device registers, aborting\n");
6745                 rc = -ENOMEM;
6746                 goto init_err_release;
6747         }
6748
6749         bp->bar1 = pci_ioremap_bar(pdev, 2);
6750         if (!bp->bar1) {
6751                 dev_err(&pdev->dev, "Cannot map doorbell registers, aborting\n");
6752                 rc = -ENOMEM;
6753                 goto init_err_release;
6754         }
6755
6756         bp->bar2 = pci_ioremap_bar(pdev, 4);
6757         if (!bp->bar2) {
6758                 dev_err(&pdev->dev, "Cannot map bar4 registers, aborting\n");
6759                 rc = -ENOMEM;
6760                 goto init_err_release;
6761         }
6762
6763         pci_enable_pcie_error_reporting(pdev);
6764
6765         INIT_WORK(&bp->sp_task, bnxt_sp_task);
6766
6767         spin_lock_init(&bp->ntp_fltr_lock);
6768
6769         bp->rx_ring_size = BNXT_DEFAULT_RX_RING_SIZE;
6770         bp->tx_ring_size = BNXT_DEFAULT_TX_RING_SIZE;
6771
6772         /* tick values in micro seconds */
6773         bp->rx_coal_ticks = 12;
6774         bp->rx_coal_bufs = 30;
6775         bp->rx_coal_ticks_irq = 1;
6776         bp->rx_coal_bufs_irq = 2;
6777
6778         bp->tx_coal_ticks = 25;
6779         bp->tx_coal_bufs = 30;
6780         bp->tx_coal_ticks_irq = 2;
6781         bp->tx_coal_bufs_irq = 2;
6782
6783         bp->stats_coal_ticks = BNXT_DEF_STATS_COAL_TICKS;
6784
6785         init_timer(&bp->timer);
6786         bp->timer.data = (unsigned long)bp;
6787         bp->timer.function = bnxt_timer;
6788         bp->current_interval = BNXT_TIMER_INTERVAL;
6789
6790         clear_bit(BNXT_STATE_OPEN, &bp->state);
6791         return 0;
6792
6793 init_err_release:
6794         bnxt_unmap_bars(bp, pdev);
6795         pci_release_regions(pdev);
6796
6797 init_err_disable:
6798         pci_disable_device(pdev);
6799
6800 init_err:
6801         return rc;
6802 }
6803
6804 /* rtnl_lock held */
6805 static int bnxt_change_mac_addr(struct net_device *dev, void *p)
6806 {
6807         struct sockaddr *addr = p;
6808         struct bnxt *bp = netdev_priv(dev);
6809         int rc = 0;
6810
6811         if (!is_valid_ether_addr(addr->sa_data))
6812                 return -EADDRNOTAVAIL;
6813
6814         rc = bnxt_approve_mac(bp, addr->sa_data);
6815         if (rc)
6816                 return rc;
6817
6818         if (ether_addr_equal(addr->sa_data, dev->dev_addr))
6819                 return 0;
6820
6821         memcpy(dev->dev_addr, addr->sa_data, dev->addr_len);
6822         if (netif_running(dev)) {
6823                 bnxt_close_nic(bp, false, false);
6824                 rc = bnxt_open_nic(bp, false, false);
6825         }
6826
6827         return rc;
6828 }
6829
6830 /* rtnl_lock held */
6831 static int bnxt_change_mtu(struct net_device *dev, int new_mtu)
6832 {
6833         struct bnxt *bp = netdev_priv(dev);
6834
6835         if (netif_running(dev))
6836                 bnxt_close_nic(bp, false, false);
6837
6838         dev->mtu = new_mtu;
6839         bnxt_set_ring_params(bp);
6840
6841         if (netif_running(dev))
6842                 return bnxt_open_nic(bp, false, false);
6843
6844         return 0;
6845 }
6846
6847 int bnxt_setup_mq_tc(struct net_device *dev, u8 tc)
6848 {
6849         struct bnxt *bp = netdev_priv(dev);
6850         bool sh = false;
6851         int rc;
6852
6853         if (tc > bp->max_tc) {
6854                 netdev_err(dev, "Too many traffic classes requested: %d. Max supported is %d.\n",
6855                            tc, bp->max_tc);
6856                 return -EINVAL;
6857         }
6858
6859         if (netdev_get_num_tc(dev) == tc)
6860                 return 0;
6861
6862         if (bp->flags & BNXT_FLAG_SHARED_RINGS)
6863                 sh = true;
6864
6865         rc = bnxt_reserve_rings(bp, bp->tx_nr_rings_per_tc, bp->rx_nr_rings,
6866                                 tc, bp->tx_nr_rings_xdp);
6867         if (rc)
6868                 return rc;
6869
6870         /* Needs to close the device and do hw resource re-allocations */
6871         if (netif_running(bp->dev))
6872                 bnxt_close_nic(bp, true, false);
6873
6874         if (tc) {
6875                 bp->tx_nr_rings = bp->tx_nr_rings_per_tc * tc;
6876                 netdev_set_num_tc(dev, tc);
6877         } else {
6878                 bp->tx_nr_rings = bp->tx_nr_rings_per_tc;
6879                 netdev_reset_tc(dev);
6880         }
6881         bp->cp_nr_rings = sh ? max_t(int, bp->tx_nr_rings, bp->rx_nr_rings) :
6882                                bp->tx_nr_rings + bp->rx_nr_rings;
6883         bp->num_stat_ctxs = bp->cp_nr_rings;
6884
6885         if (netif_running(bp->dev))
6886                 return bnxt_open_nic(bp, true, false);
6887
6888         return 0;
6889 }
6890
6891 static int bnxt_setup_tc(struct net_device *dev, u32 handle, __be16 proto,
6892                          struct tc_to_netdev *ntc)
6893 {
6894         if (ntc->type != TC_SETUP_MQPRIO)
6895                 return -EINVAL;
6896
6897         return bnxt_setup_mq_tc(dev, ntc->tc);
6898 }
6899
6900 #ifdef CONFIG_RFS_ACCEL
6901 static bool bnxt_fltr_match(struct bnxt_ntuple_filter *f1,
6902                             struct bnxt_ntuple_filter *f2)
6903 {
6904         struct flow_keys *keys1 = &f1->fkeys;
6905         struct flow_keys *keys2 = &f2->fkeys;
6906
6907         if (keys1->addrs.v4addrs.src == keys2->addrs.v4addrs.src &&
6908             keys1->addrs.v4addrs.dst == keys2->addrs.v4addrs.dst &&
6909             keys1->ports.ports == keys2->ports.ports &&
6910             keys1->basic.ip_proto == keys2->basic.ip_proto &&
6911             keys1->basic.n_proto == keys2->basic.n_proto &&
6912             keys1->control.flags == keys2->control.flags &&
6913             ether_addr_equal(f1->src_mac_addr, f2->src_mac_addr) &&
6914             ether_addr_equal(f1->dst_mac_addr, f2->dst_mac_addr))
6915                 return true;
6916
6917         return false;
6918 }
6919
6920 static int bnxt_rx_flow_steer(struct net_device *dev, const struct sk_buff *skb,
6921                               u16 rxq_index, u32 flow_id)
6922 {
6923         struct bnxt *bp = netdev_priv(dev);
6924         struct bnxt_ntuple_filter *fltr, *new_fltr;
6925         struct flow_keys *fkeys;
6926         struct ethhdr *eth = (struct ethhdr *)skb_mac_header(skb);
6927         int rc = 0, idx, bit_id, l2_idx = 0;
6928         struct hlist_head *head;
6929
6930         if (!ether_addr_equal(dev->dev_addr, eth->h_dest)) {
6931                 struct bnxt_vnic_info *vnic = &bp->vnic_info[0];
6932                 int off = 0, j;
6933
6934                 netif_addr_lock_bh(dev);
6935                 for (j = 0; j < vnic->uc_filter_count; j++, off += ETH_ALEN) {
6936                         if (ether_addr_equal(eth->h_dest,
6937                                              vnic->uc_list + off)) {
6938                                 l2_idx = j + 1;
6939                                 break;
6940                         }
6941                 }
6942                 netif_addr_unlock_bh(dev);
6943                 if (!l2_idx)
6944                         return -EINVAL;
6945         }
6946         new_fltr = kzalloc(sizeof(*new_fltr), GFP_ATOMIC);
6947         if (!new_fltr)
6948                 return -ENOMEM;
6949
6950         fkeys = &new_fltr->fkeys;
6951         if (!skb_flow_dissect_flow_keys(skb, fkeys, 0)) {
6952                 rc = -EPROTONOSUPPORT;
6953                 goto err_free;
6954         }
6955
6956         if ((fkeys->basic.n_proto != htons(ETH_P_IP) &&
6957              fkeys->basic.n_proto != htons(ETH_P_IPV6)) ||
6958             ((fkeys->basic.ip_proto != IPPROTO_TCP) &&
6959              (fkeys->basic.ip_proto != IPPROTO_UDP))) {
6960                 rc = -EPROTONOSUPPORT;
6961                 goto err_free;
6962         }
6963         if (fkeys->basic.n_proto == htons(ETH_P_IPV6) &&
6964             bp->hwrm_spec_code < 0x10601) {
6965                 rc = -EPROTONOSUPPORT;
6966                 goto err_free;
6967         }
6968         if ((fkeys->control.flags & FLOW_DIS_ENCAPSULATION) &&
6969             bp->hwrm_spec_code < 0x10601) {
6970                 rc = -EPROTONOSUPPORT;
6971                 goto err_free;
6972         }
6973
6974         memcpy(new_fltr->dst_mac_addr, eth->h_dest, ETH_ALEN);
6975         memcpy(new_fltr->src_mac_addr, eth->h_source, ETH_ALEN);
6976
6977         idx = skb_get_hash_raw(skb) & BNXT_NTP_FLTR_HASH_MASK;
6978         head = &bp->ntp_fltr_hash_tbl[idx];
6979         rcu_read_lock();
6980         hlist_for_each_entry_rcu(fltr, head, hash) {
6981                 if (bnxt_fltr_match(fltr, new_fltr)) {
6982                         rcu_read_unlock();
6983                         rc = 0;
6984                         goto err_free;
6985                 }
6986         }
6987         rcu_read_unlock();
6988
6989         spin_lock_bh(&bp->ntp_fltr_lock);
6990         bit_id = bitmap_find_free_region(bp->ntp_fltr_bmap,
6991                                          BNXT_NTP_FLTR_MAX_FLTR, 0);
6992         if (bit_id < 0) {
6993                 spin_unlock_bh(&bp->ntp_fltr_lock);
6994                 rc = -ENOMEM;
6995                 goto err_free;
6996         }
6997
6998         new_fltr->sw_id = (u16)bit_id;
6999         new_fltr->flow_id = flow_id;
7000         new_fltr->l2_fltr_idx = l2_idx;
7001         new_fltr->rxq = rxq_index;
7002         hlist_add_head_rcu(&new_fltr->hash, head);
7003         bp->ntp_fltr_count++;
7004         spin_unlock_bh(&bp->ntp_fltr_lock);
7005
7006         set_bit(BNXT_RX_NTP_FLTR_SP_EVENT, &bp->sp_event);
7007         schedule_work(&bp->sp_task);
7008
7009         return new_fltr->sw_id;
7010
7011 err_free:
7012         kfree(new_fltr);
7013         return rc;
7014 }
7015
7016 static void bnxt_cfg_ntp_filters(struct bnxt *bp)
7017 {
7018         int i;
7019
7020         for (i = 0; i < BNXT_NTP_FLTR_HASH_SIZE; i++) {
7021                 struct hlist_head *head;
7022                 struct hlist_node *tmp;
7023                 struct bnxt_ntuple_filter *fltr;
7024                 int rc;
7025
7026                 head = &bp->ntp_fltr_hash_tbl[i];
7027                 hlist_for_each_entry_safe(fltr, tmp, head, hash) {
7028                         bool del = false;
7029
7030                         if (test_bit(BNXT_FLTR_VALID, &fltr->state)) {
7031                                 if (rps_may_expire_flow(bp->dev, fltr->rxq,
7032                                                         fltr->flow_id,
7033                                                         fltr->sw_id)) {
7034                                         bnxt_hwrm_cfa_ntuple_filter_free(bp,
7035                                                                          fltr);
7036                                         del = true;
7037                                 }
7038                         } else {
7039                                 rc = bnxt_hwrm_cfa_ntuple_filter_alloc(bp,
7040                                                                        fltr);
7041                                 if (rc)
7042                                         del = true;
7043                                 else
7044                                         set_bit(BNXT_FLTR_VALID, &fltr->state);
7045                         }
7046
7047                         if (del) {
7048                                 spin_lock_bh(&bp->ntp_fltr_lock);
7049                                 hlist_del_rcu(&fltr->hash);
7050                                 bp->ntp_fltr_count--;
7051                                 spin_unlock_bh(&bp->ntp_fltr_lock);
7052                                 synchronize_rcu();
7053                                 clear_bit(fltr->sw_id, bp->ntp_fltr_bmap);
7054                                 kfree(fltr);
7055                         }
7056                 }
7057         }
7058         if (test_and_clear_bit(BNXT_HWRM_PF_UNLOAD_SP_EVENT, &bp->sp_event))
7059                 netdev_info(bp->dev, "Receive PF driver unload event!");
7060 }
7061
7062 #else
7063
7064 static void bnxt_cfg_ntp_filters(struct bnxt *bp)
7065 {
7066 }
7067
7068 #endif /* CONFIG_RFS_ACCEL */
7069
7070 static void bnxt_udp_tunnel_add(struct net_device *dev,
7071                                 struct udp_tunnel_info *ti)
7072 {
7073         struct bnxt *bp = netdev_priv(dev);
7074
7075         if (ti->sa_family != AF_INET6 && ti->sa_family != AF_INET)
7076                 return;
7077
7078         if (!netif_running(dev))
7079                 return;
7080
7081         switch (ti->type) {
7082         case UDP_TUNNEL_TYPE_VXLAN:
7083                 if (bp->vxlan_port_cnt && bp->vxlan_port != ti->port)
7084                         return;
7085
7086                 bp->vxlan_port_cnt++;
7087                 if (bp->vxlan_port_cnt == 1) {
7088                         bp->vxlan_port = ti->port;
7089                         set_bit(BNXT_VXLAN_ADD_PORT_SP_EVENT, &bp->sp_event);
7090                         schedule_work(&bp->sp_task);
7091                 }
7092                 break;
7093         case UDP_TUNNEL_TYPE_GENEVE:
7094                 if (bp->nge_port_cnt && bp->nge_port != ti->port)
7095                         return;
7096
7097                 bp->nge_port_cnt++;
7098                 if (bp->nge_port_cnt == 1) {
7099                         bp->nge_port = ti->port;
7100                         set_bit(BNXT_GENEVE_ADD_PORT_SP_EVENT, &bp->sp_event);
7101                 }
7102                 break;
7103         default:
7104                 return;
7105         }
7106
7107         schedule_work(&bp->sp_task);
7108 }
7109
7110 static void bnxt_udp_tunnel_del(struct net_device *dev,
7111                                 struct udp_tunnel_info *ti)
7112 {
7113         struct bnxt *bp = netdev_priv(dev);
7114
7115         if (ti->sa_family != AF_INET6 && ti->sa_family != AF_INET)
7116                 return;
7117
7118         if (!netif_running(dev))
7119                 return;
7120
7121         switch (ti->type) {
7122         case UDP_TUNNEL_TYPE_VXLAN:
7123                 if (!bp->vxlan_port_cnt || bp->vxlan_port != ti->port)
7124                         return;
7125                 bp->vxlan_port_cnt--;
7126
7127                 if (bp->vxlan_port_cnt != 0)
7128                         return;
7129
7130                 set_bit(BNXT_VXLAN_DEL_PORT_SP_EVENT, &bp->sp_event);
7131                 break;
7132         case UDP_TUNNEL_TYPE_GENEVE:
7133                 if (!bp->nge_port_cnt || bp->nge_port != ti->port)
7134                         return;
7135                 bp->nge_port_cnt--;
7136
7137                 if (bp->nge_port_cnt != 0)
7138                         return;
7139
7140                 set_bit(BNXT_GENEVE_DEL_PORT_SP_EVENT, &bp->sp_event);
7141                 break;
7142         default:
7143                 return;
7144         }
7145
7146         schedule_work(&bp->sp_task);
7147 }
7148
7149 static const struct net_device_ops bnxt_netdev_ops = {
7150         .ndo_open               = bnxt_open,
7151         .ndo_start_xmit         = bnxt_start_xmit,
7152         .ndo_stop               = bnxt_close,
7153         .ndo_get_stats64        = bnxt_get_stats64,
7154         .ndo_set_rx_mode        = bnxt_set_rx_mode,
7155         .ndo_do_ioctl           = bnxt_ioctl,
7156         .ndo_validate_addr      = eth_validate_addr,
7157         .ndo_set_mac_address    = bnxt_change_mac_addr,
7158         .ndo_change_mtu         = bnxt_change_mtu,
7159         .ndo_fix_features       = bnxt_fix_features,
7160         .ndo_set_features       = bnxt_set_features,
7161         .ndo_tx_timeout         = bnxt_tx_timeout,
7162 #ifdef CONFIG_BNXT_SRIOV
7163         .ndo_get_vf_config      = bnxt_get_vf_config,
7164         .ndo_set_vf_mac         = bnxt_set_vf_mac,
7165         .ndo_set_vf_vlan        = bnxt_set_vf_vlan,
7166         .ndo_set_vf_rate        = bnxt_set_vf_bw,
7167         .ndo_set_vf_link_state  = bnxt_set_vf_link_state,
7168         .ndo_set_vf_spoofchk    = bnxt_set_vf_spoofchk,
7169 #endif
7170 #ifdef CONFIG_NET_POLL_CONTROLLER
7171         .ndo_poll_controller    = bnxt_poll_controller,
7172 #endif
7173         .ndo_setup_tc           = bnxt_setup_tc,
7174 #ifdef CONFIG_RFS_ACCEL
7175         .ndo_rx_flow_steer      = bnxt_rx_flow_steer,
7176 #endif
7177         .ndo_udp_tunnel_add     = bnxt_udp_tunnel_add,
7178         .ndo_udp_tunnel_del     = bnxt_udp_tunnel_del,
7179         .ndo_xdp                = bnxt_xdp,
7180 };
7181
7182 static void bnxt_remove_one(struct pci_dev *pdev)
7183 {
7184         struct net_device *dev = pci_get_drvdata(pdev);
7185         struct bnxt *bp = netdev_priv(dev);
7186
7187         if (BNXT_PF(bp))
7188                 bnxt_sriov_disable(bp);
7189
7190         pci_disable_pcie_error_reporting(pdev);
7191         unregister_netdev(dev);
7192         cancel_work_sync(&bp->sp_task);
7193         bp->sp_event = 0;
7194
7195         bnxt_clear_int_mode(bp);
7196         bnxt_hwrm_func_drv_unrgtr(bp);
7197         bnxt_free_hwrm_resources(bp);
7198         bnxt_dcb_free(bp);
7199         kfree(bp->edev);
7200         bp->edev = NULL;
7201         if (bp->xdp_prog)
7202                 bpf_prog_put(bp->xdp_prog);
7203         bnxt_cleanup_pci(bp);
7204         free_netdev(dev);
7205 }
7206
7207 static int bnxt_probe_phy(struct bnxt *bp)
7208 {
7209         int rc = 0;
7210         struct bnxt_link_info *link_info = &bp->link_info;
7211
7212         rc = bnxt_hwrm_phy_qcaps(bp);
7213         if (rc) {
7214                 netdev_err(bp->dev, "Probe phy can't get phy capabilities (rc: %x)\n",
7215                            rc);
7216                 return rc;
7217         }
7218
7219         rc = bnxt_update_link(bp, false);
7220         if (rc) {
7221                 netdev_err(bp->dev, "Probe phy can't update link (rc: %x)\n",
7222                            rc);
7223                 return rc;
7224         }
7225
7226         /* Older firmware does not have supported_auto_speeds, so assume
7227          * that all supported speeds can be autonegotiated.
7228          */
7229         if (link_info->auto_link_speeds && !link_info->support_auto_speeds)
7230                 link_info->support_auto_speeds = link_info->support_speeds;
7231
7232         /*initialize the ethool setting copy with NVM settings */
7233         if (BNXT_AUTO_MODE(link_info->auto_mode)) {
7234                 link_info->autoneg = BNXT_AUTONEG_SPEED;
7235                 if (bp->hwrm_spec_code >= 0x10201) {
7236                         if (link_info->auto_pause_setting &
7237                             PORT_PHY_CFG_REQ_AUTO_PAUSE_AUTONEG_PAUSE)
7238                                 link_info->autoneg |= BNXT_AUTONEG_FLOW_CTRL;
7239                 } else {
7240                         link_info->autoneg |= BNXT_AUTONEG_FLOW_CTRL;
7241                 }
7242                 link_info->advertising = link_info->auto_link_speeds;
7243         } else {
7244                 link_info->req_link_speed = link_info->force_link_speed;
7245                 link_info->req_duplex = link_info->duplex_setting;
7246         }
7247         if (link_info->autoneg & BNXT_AUTONEG_FLOW_CTRL)
7248                 link_info->req_flow_ctrl =
7249                         link_info->auto_pause_setting & BNXT_LINK_PAUSE_BOTH;
7250         else
7251                 link_info->req_flow_ctrl = link_info->force_pause_setting;
7252         return rc;
7253 }
7254
7255 static int bnxt_get_max_irq(struct pci_dev *pdev)
7256 {
7257         u16 ctrl;
7258
7259         if (!pdev->msix_cap)
7260                 return 1;
7261
7262         pci_read_config_word(pdev, pdev->msix_cap + PCI_MSIX_FLAGS, &ctrl);
7263         return (ctrl & PCI_MSIX_FLAGS_QSIZE) + 1;
7264 }
7265
7266 static void _bnxt_get_max_rings(struct bnxt *bp, int *max_rx, int *max_tx,
7267                                 int *max_cp)
7268 {
7269         int max_ring_grps = 0;
7270
7271 #ifdef CONFIG_BNXT_SRIOV
7272         if (!BNXT_PF(bp)) {
7273                 *max_tx = bp->vf.max_tx_rings;
7274                 *max_rx = bp->vf.max_rx_rings;
7275                 *max_cp = min_t(int, bp->vf.max_irqs, bp->vf.max_cp_rings);
7276                 *max_cp = min_t(int, *max_cp, bp->vf.max_stat_ctxs);
7277                 max_ring_grps = bp->vf.max_hw_ring_grps;
7278         } else
7279 #endif
7280         {
7281                 *max_tx = bp->pf.max_tx_rings;
7282                 *max_rx = bp->pf.max_rx_rings;
7283                 *max_cp = min_t(int, bp->pf.max_irqs, bp->pf.max_cp_rings);
7284                 *max_cp = min_t(int, *max_cp, bp->pf.max_stat_ctxs);
7285                 max_ring_grps = bp->pf.max_hw_ring_grps;
7286         }
7287         if (BNXT_CHIP_TYPE_NITRO_A0(bp) && BNXT_PF(bp)) {
7288                 *max_cp -= 1;
7289                 *max_rx -= 2;
7290         }
7291         if (bp->flags & BNXT_FLAG_AGG_RINGS)
7292                 *max_rx >>= 1;
7293         *max_rx = min_t(int, *max_rx, max_ring_grps);
7294 }
7295
7296 int bnxt_get_max_rings(struct bnxt *bp, int *max_rx, int *max_tx, bool shared)
7297 {
7298         int rx, tx, cp;
7299
7300         _bnxt_get_max_rings(bp, &rx, &tx, &cp);
7301         if (!rx || !tx || !cp)
7302                 return -ENOMEM;
7303
7304         *max_rx = rx;
7305         *max_tx = tx;
7306         return bnxt_trim_rings(bp, max_rx, max_tx, cp, shared);
7307 }
7308
7309 static int bnxt_get_dflt_rings(struct bnxt *bp, int *max_rx, int *max_tx,
7310                                bool shared)
7311 {
7312         int rc;
7313
7314         rc = bnxt_get_max_rings(bp, max_rx, max_tx, shared);
7315         if (rc && (bp->flags & BNXT_FLAG_AGG_RINGS)) {
7316                 /* Not enough rings, try disabling agg rings. */
7317                 bp->flags &= ~BNXT_FLAG_AGG_RINGS;
7318                 rc = bnxt_get_max_rings(bp, max_rx, max_tx, shared);
7319                 if (rc)
7320                         return rc;
7321                 bp->flags |= BNXT_FLAG_NO_AGG_RINGS;
7322                 bp->dev->hw_features &= ~NETIF_F_LRO;
7323                 bp->dev->features &= ~NETIF_F_LRO;
7324                 bnxt_set_ring_params(bp);
7325         }
7326
7327         if (bp->flags & BNXT_FLAG_ROCE_CAP) {
7328                 int max_cp, max_stat, max_irq;
7329
7330                 /* Reserve minimum resources for RoCE */
7331                 max_cp = bnxt_get_max_func_cp_rings(bp);
7332                 max_stat = bnxt_get_max_func_stat_ctxs(bp);
7333                 max_irq = bnxt_get_max_func_irqs(bp);
7334                 if (max_cp <= BNXT_MIN_ROCE_CP_RINGS ||
7335                     max_irq <= BNXT_MIN_ROCE_CP_RINGS ||
7336                     max_stat <= BNXT_MIN_ROCE_STAT_CTXS)
7337                         return 0;
7338
7339                 max_cp -= BNXT_MIN_ROCE_CP_RINGS;
7340                 max_irq -= BNXT_MIN_ROCE_CP_RINGS;
7341                 max_stat -= BNXT_MIN_ROCE_STAT_CTXS;
7342                 max_cp = min_t(int, max_cp, max_irq);
7343                 max_cp = min_t(int, max_cp, max_stat);
7344                 rc = bnxt_trim_rings(bp, max_rx, max_tx, max_cp, shared);
7345                 if (rc)
7346                         rc = 0;
7347         }
7348         return rc;
7349 }
7350
7351 static int bnxt_set_dflt_rings(struct bnxt *bp)
7352 {
7353         int dflt_rings, max_rx_rings, max_tx_rings, rc;
7354         bool sh = true;
7355
7356         if (sh)
7357                 bp->flags |= BNXT_FLAG_SHARED_RINGS;
7358         dflt_rings = netif_get_num_default_rss_queues();
7359         rc = bnxt_get_dflt_rings(bp, &max_rx_rings, &max_tx_rings, sh);
7360         if (rc)
7361                 return rc;
7362         bp->rx_nr_rings = min_t(int, dflt_rings, max_rx_rings);
7363         bp->tx_nr_rings_per_tc = min_t(int, dflt_rings, max_tx_rings);
7364
7365         rc = bnxt_hwrm_reserve_tx_rings(bp, &bp->tx_nr_rings_per_tc);
7366         if (rc)
7367                 netdev_warn(bp->dev, "Unable to reserve tx rings\n");
7368
7369         bp->tx_nr_rings = bp->tx_nr_rings_per_tc;
7370         bp->cp_nr_rings = sh ? max_t(int, bp->tx_nr_rings, bp->rx_nr_rings) :
7371                                bp->tx_nr_rings + bp->rx_nr_rings;
7372         bp->num_stat_ctxs = bp->cp_nr_rings;
7373         if (BNXT_CHIP_TYPE_NITRO_A0(bp)) {
7374                 bp->rx_nr_rings++;
7375                 bp->cp_nr_rings++;
7376         }
7377         return rc;
7378 }
7379
7380 void bnxt_restore_pf_fw_resources(struct bnxt *bp)
7381 {
7382         ASSERT_RTNL();
7383         bnxt_hwrm_func_qcaps(bp);
7384         bnxt_subtract_ulp_resources(bp, BNXT_ROCE_ULP);
7385 }
7386
7387 static void bnxt_parse_log_pcie_link(struct bnxt *bp)
7388 {
7389         enum pcie_link_width width = PCIE_LNK_WIDTH_UNKNOWN;
7390         enum pci_bus_speed speed = PCI_SPEED_UNKNOWN;
7391
7392         if (pcie_get_minimum_link(bp->pdev, &speed, &width) ||
7393             speed == PCI_SPEED_UNKNOWN || width == PCIE_LNK_WIDTH_UNKNOWN)
7394                 netdev_info(bp->dev, "Failed to determine PCIe Link Info\n");
7395         else
7396                 netdev_info(bp->dev, "PCIe: Speed %s Width x%d\n",
7397                             speed == PCIE_SPEED_2_5GT ? "2.5GT/s" :
7398                             speed == PCIE_SPEED_5_0GT ? "5.0GT/s" :
7399                             speed == PCIE_SPEED_8_0GT ? "8.0GT/s" :
7400                             "Unknown", width);
7401 }
7402
7403 static int bnxt_init_one(struct pci_dev *pdev, const struct pci_device_id *ent)
7404 {
7405         static int version_printed;
7406         struct net_device *dev;
7407         struct bnxt *bp;
7408         int rc, max_irqs;
7409
7410         if (pci_is_bridge(pdev))
7411                 return -ENODEV;
7412
7413         if (version_printed++ == 0)
7414                 pr_info("%s", version);
7415
7416         max_irqs = bnxt_get_max_irq(pdev);
7417         dev = alloc_etherdev_mq(sizeof(*bp), max_irqs);
7418         if (!dev)
7419                 return -ENOMEM;
7420
7421         bp = netdev_priv(dev);
7422
7423         if (bnxt_vf_pciid(ent->driver_data))
7424                 bp->flags |= BNXT_FLAG_VF;
7425
7426         if (pdev->msix_cap)
7427                 bp->flags |= BNXT_FLAG_MSIX_CAP;
7428
7429         rc = bnxt_init_board(pdev, dev);
7430         if (rc < 0)
7431                 goto init_err_free;
7432
7433         dev->netdev_ops = &bnxt_netdev_ops;
7434         dev->watchdog_timeo = BNXT_TX_TIMEOUT;
7435         dev->ethtool_ops = &bnxt_ethtool_ops;
7436         pci_set_drvdata(pdev, dev);
7437
7438         rc = bnxt_alloc_hwrm_resources(bp);
7439         if (rc)
7440                 goto init_err_pci_clean;
7441
7442         mutex_init(&bp->hwrm_cmd_lock);
7443         rc = bnxt_hwrm_ver_get(bp);
7444         if (rc)
7445                 goto init_err_pci_clean;
7446
7447         rc = bnxt_hwrm_func_reset(bp);
7448         if (rc)
7449                 goto init_err_pci_clean;
7450
7451         bnxt_hwrm_fw_set_time(bp);
7452
7453         dev->hw_features = NETIF_F_IP_CSUM | NETIF_F_IPV6_CSUM | NETIF_F_SG |
7454                            NETIF_F_TSO | NETIF_F_TSO6 |
7455                            NETIF_F_GSO_UDP_TUNNEL | NETIF_F_GSO_GRE |
7456                            NETIF_F_GSO_IPXIP4 |
7457                            NETIF_F_GSO_UDP_TUNNEL_CSUM | NETIF_F_GSO_GRE_CSUM |
7458                            NETIF_F_GSO_PARTIAL | NETIF_F_RXHASH |
7459                            NETIF_F_RXCSUM | NETIF_F_GRO;
7460
7461         if (!BNXT_CHIP_TYPE_NITRO_A0(bp))
7462                 dev->hw_features |= NETIF_F_LRO;
7463
7464         dev->hw_enc_features =
7465                         NETIF_F_IP_CSUM | NETIF_F_IPV6_CSUM | NETIF_F_SG |
7466                         NETIF_F_TSO | NETIF_F_TSO6 |
7467                         NETIF_F_GSO_UDP_TUNNEL | NETIF_F_GSO_GRE |
7468                         NETIF_F_GSO_UDP_TUNNEL_CSUM | NETIF_F_GSO_GRE_CSUM |
7469                         NETIF_F_GSO_IPXIP4 | NETIF_F_GSO_PARTIAL;
7470         dev->gso_partial_features = NETIF_F_GSO_UDP_TUNNEL_CSUM |
7471                                     NETIF_F_GSO_GRE_CSUM;
7472         dev->vlan_features = dev->hw_features | NETIF_F_HIGHDMA;
7473         dev->hw_features |= NETIF_F_HW_VLAN_CTAG_RX | NETIF_F_HW_VLAN_CTAG_TX |
7474                             NETIF_F_HW_VLAN_STAG_RX | NETIF_F_HW_VLAN_STAG_TX;
7475         dev->features |= dev->hw_features | NETIF_F_HIGHDMA;
7476         dev->priv_flags |= IFF_UNICAST_FLT;
7477
7478         /* MTU range: 60 - 9500 */
7479         dev->min_mtu = ETH_ZLEN;
7480         dev->max_mtu = BNXT_MAX_MTU;
7481
7482         bnxt_dcb_init(bp);
7483
7484 #ifdef CONFIG_BNXT_SRIOV
7485         init_waitqueue_head(&bp->sriov_cfg_wait);
7486 #endif
7487         bp->gro_func = bnxt_gro_func_5730x;
7488         if (BNXT_CHIP_NUM_57X1X(bp->chip_num))
7489                 bp->gro_func = bnxt_gro_func_5731x;
7490
7491         rc = bnxt_hwrm_func_drv_rgtr(bp);
7492         if (rc)
7493                 goto init_err_pci_clean;
7494
7495         rc = bnxt_hwrm_func_rgtr_async_events(bp, NULL, 0);
7496         if (rc)
7497                 goto init_err_pci_clean;
7498
7499         bp->ulp_probe = bnxt_ulp_probe;
7500
7501         /* Get the MAX capabilities for this function */
7502         rc = bnxt_hwrm_func_qcaps(bp);
7503         if (rc) {
7504                 netdev_err(bp->dev, "hwrm query capability failure rc: %x\n",
7505                            rc);
7506                 rc = -1;
7507                 goto init_err_pci_clean;
7508         }
7509
7510         rc = bnxt_hwrm_queue_qportcfg(bp);
7511         if (rc) {
7512                 netdev_err(bp->dev, "hwrm query qportcfg failure rc: %x\n",
7513                            rc);
7514                 rc = -1;
7515                 goto init_err_pci_clean;
7516         }
7517
7518         bnxt_hwrm_func_qcfg(bp);
7519         bnxt_hwrm_port_led_qcaps(bp);
7520
7521         bnxt_set_rx_skb_mode(bp, false);
7522         bnxt_set_tpa_flags(bp);
7523         bnxt_set_ring_params(bp);
7524         bnxt_set_max_func_irqs(bp, max_irqs);
7525         rc = bnxt_set_dflt_rings(bp);
7526         if (rc) {
7527                 netdev_err(bp->dev, "Not enough rings available.\n");
7528                 rc = -ENOMEM;
7529                 goto init_err_pci_clean;
7530         }
7531
7532         /* Default RSS hash cfg. */
7533         bp->rss_hash_cfg = VNIC_RSS_CFG_REQ_HASH_TYPE_IPV4 |
7534                            VNIC_RSS_CFG_REQ_HASH_TYPE_TCP_IPV4 |
7535                            VNIC_RSS_CFG_REQ_HASH_TYPE_IPV6 |
7536                            VNIC_RSS_CFG_REQ_HASH_TYPE_TCP_IPV6;
7537         if (!BNXT_CHIP_NUM_57X0X(bp->chip_num) &&
7538             !BNXT_CHIP_TYPE_NITRO_A0(bp) &&
7539             bp->hwrm_spec_code >= 0x10501) {
7540                 bp->flags |= BNXT_FLAG_UDP_RSS_CAP;
7541                 bp->rss_hash_cfg |= VNIC_RSS_CFG_REQ_HASH_TYPE_UDP_IPV4 |
7542                                     VNIC_RSS_CFG_REQ_HASH_TYPE_UDP_IPV6;
7543         }
7544
7545         bnxt_hwrm_vnic_qcaps(bp);
7546         if (bnxt_rfs_supported(bp)) {
7547                 dev->hw_features |= NETIF_F_NTUPLE;
7548                 if (bnxt_rfs_capable(bp)) {
7549                         bp->flags |= BNXT_FLAG_RFS;
7550                         dev->features |= NETIF_F_NTUPLE;
7551                 }
7552         }
7553
7554         if (dev->hw_features & NETIF_F_HW_VLAN_CTAG_RX)
7555                 bp->flags |= BNXT_FLAG_STRIP_VLAN;
7556
7557         rc = bnxt_probe_phy(bp);
7558         if (rc)
7559                 goto init_err_pci_clean;
7560
7561         rc = bnxt_init_int_mode(bp);
7562         if (rc)
7563                 goto init_err_pci_clean;
7564
7565         rc = register_netdev(dev);
7566         if (rc)
7567                 goto init_err_clr_int;
7568
7569         netdev_info(dev, "%s found at mem %lx, node addr %pM\n",
7570                     board_info[ent->driver_data].name,
7571                     (long)pci_resource_start(pdev, 0), dev->dev_addr);
7572
7573         bnxt_parse_log_pcie_link(bp);
7574
7575         return 0;
7576
7577 init_err_clr_int:
7578         bnxt_clear_int_mode(bp);
7579
7580 init_err_pci_clean:
7581         bnxt_cleanup_pci(bp);
7582
7583 init_err_free:
7584         free_netdev(dev);
7585         return rc;
7586 }
7587
7588 /**
7589  * bnxt_io_error_detected - called when PCI error is detected
7590  * @pdev: Pointer to PCI device
7591  * @state: The current pci connection state
7592  *
7593  * This function is called after a PCI bus error affecting
7594  * this device has been detected.
7595  */
7596 static pci_ers_result_t bnxt_io_error_detected(struct pci_dev *pdev,
7597                                                pci_channel_state_t state)
7598 {
7599         struct net_device *netdev = pci_get_drvdata(pdev);
7600         struct bnxt *bp = netdev_priv(netdev);
7601
7602         netdev_info(netdev, "PCI I/O error detected\n");
7603
7604         rtnl_lock();
7605         netif_device_detach(netdev);
7606
7607         bnxt_ulp_stop(bp);
7608
7609         if (state == pci_channel_io_perm_failure) {
7610                 rtnl_unlock();
7611                 return PCI_ERS_RESULT_DISCONNECT;
7612         }
7613
7614         if (netif_running(netdev))
7615                 bnxt_close(netdev);
7616
7617         pci_disable_device(pdev);
7618         rtnl_unlock();
7619
7620         /* Request a slot slot reset. */
7621         return PCI_ERS_RESULT_NEED_RESET;
7622 }
7623
7624 /**
7625  * bnxt_io_slot_reset - called after the pci bus has been reset.
7626  * @pdev: Pointer to PCI device
7627  *
7628  * Restart the card from scratch, as if from a cold-boot.
7629  * At this point, the card has exprienced a hard reset,
7630  * followed by fixups by BIOS, and has its config space
7631  * set up identically to what it was at cold boot.
7632  */
7633 static pci_ers_result_t bnxt_io_slot_reset(struct pci_dev *pdev)
7634 {
7635         struct net_device *netdev = pci_get_drvdata(pdev);
7636         struct bnxt *bp = netdev_priv(netdev);
7637         int err = 0;
7638         pci_ers_result_t result = PCI_ERS_RESULT_DISCONNECT;
7639
7640         netdev_info(bp->dev, "PCI Slot Reset\n");
7641
7642         rtnl_lock();
7643
7644         if (pci_enable_device(pdev)) {
7645                 dev_err(&pdev->dev,
7646                         "Cannot re-enable PCI device after reset.\n");
7647         } else {
7648                 pci_set_master(pdev);
7649
7650                 err = bnxt_hwrm_func_reset(bp);
7651                 if (!err && netif_running(netdev))
7652                         err = bnxt_open(netdev);
7653
7654                 if (!err) {
7655                         result = PCI_ERS_RESULT_RECOVERED;
7656                         bnxt_ulp_start(bp);
7657                 }
7658         }
7659
7660         if (result != PCI_ERS_RESULT_RECOVERED && netif_running(netdev))
7661                 dev_close(netdev);
7662
7663         rtnl_unlock();
7664
7665         err = pci_cleanup_aer_uncorrect_error_status(pdev);
7666         if (err) {
7667                 dev_err(&pdev->dev,
7668                         "pci_cleanup_aer_uncorrect_error_status failed 0x%0x\n",
7669                          err); /* non-fatal, continue */
7670         }
7671
7672         return PCI_ERS_RESULT_RECOVERED;
7673 }
7674
7675 /**
7676  * bnxt_io_resume - called when traffic can start flowing again.
7677  * @pdev: Pointer to PCI device
7678  *
7679  * This callback is called when the error recovery driver tells
7680  * us that its OK to resume normal operation.
7681  */
7682 static void bnxt_io_resume(struct pci_dev *pdev)
7683 {
7684         struct net_device *netdev = pci_get_drvdata(pdev);
7685
7686         rtnl_lock();
7687
7688         netif_device_attach(netdev);
7689
7690         rtnl_unlock();
7691 }
7692
7693 static const struct pci_error_handlers bnxt_err_handler = {
7694         .error_detected = bnxt_io_error_detected,
7695         .slot_reset     = bnxt_io_slot_reset,
7696         .resume         = bnxt_io_resume
7697 };
7698
7699 static struct pci_driver bnxt_pci_driver = {
7700         .name           = DRV_MODULE_NAME,
7701         .id_table       = bnxt_pci_tbl,
7702         .probe          = bnxt_init_one,
7703         .remove         = bnxt_remove_one,
7704         .err_handler    = &bnxt_err_handler,
7705 #if defined(CONFIG_BNXT_SRIOV)
7706         .sriov_configure = bnxt_sriov_configure,
7707 #endif
7708 };
7709
7710 module_pci_driver(bnxt_pci_driver);