drivers/net/ethernet/broadcom/bnxt/bnxt.c

   1 /* Broadcom NetXtreme-C/E network driver.
   2  *
   3  * Copyright (c) 2014-2016 Broadcom Corporation
   4  *
   5  * This program is free software; you can redistribute it and/or modify
   6  * it under the terms of the GNU General Public License as published by
   7  * the Free Software Foundation.
   8  */
   9
  10 #include <linux/module.h>
  11
  12 #include <linux/stringify.h>
  13 #include <linux/kernel.h>
  14 #include <linux/timer.h>
  15 #include <linux/errno.h>
  16 #include <linux/ioport.h>
  17 #include <linux/slab.h>
  18 #include <linux/vmalloc.h>
  19 #include <linux/interrupt.h>
  20 #include <linux/pci.h>
  21 #include <linux/netdevice.h>
  22 #include <linux/etherdevice.h>
  23 #include <linux/skbuff.h>
  24 #include <linux/dma-mapping.h>
  25 #include <linux/bitops.h>
  26 #include <linux/io.h>
  27 #include <linux/irq.h>
  28 #include <linux/delay.h>
  29 #include <asm/byteorder.h>
  30 #include <asm/page.h>
  31 #include <linux/time.h>
  32 #include <linux/mii.h>
  33 #include <linux/if.h>
  34 #include <linux/if_vlan.h>
  35 #include <linux/rtc.h>
  36 #include <net/ip.h>
  37 #include <net/tcp.h>
  38 #include <net/udp.h>
  39 #include <net/checksum.h>
  40 #include <net/ip6_checksum.h>
  41 #include <net/udp_tunnel.h>
  42 #include <linux/workqueue.h>
  43 #include <linux/prefetch.h>
  44 #include <linux/cache.h>
  45 #include <linux/log2.h>
  46 #include <linux/aer.h>
  47 #include <linux/bitmap.h>
  48 #include <linux/cpu_rmap.h>
  49
  50 #include "bnxt_hsi.h"
  51 #include "bnxt.h"
  52 #include "bnxt_ulp.h"
  53 #include "bnxt_sriov.h"
  54 #include "bnxt_ethtool.h"
  55 #include "bnxt_dcb.h"
  56
  57 #define BNXT_TX_TIMEOUT         (5 * HZ)
  58
  59 static const char version[] =
  60         "Broadcom NetXtreme-C/E driver " DRV_MODULE_NAME " v" DRV_MODULE_VERSION "\n";
  61
  62 MODULE_LICENSE("GPL");
  63 MODULE_DESCRIPTION("Broadcom BCM573xx network driver");
  64 MODULE_VERSION(DRV_MODULE_VERSION);
  65
  66 #define BNXT_RX_OFFSET (NET_SKB_PAD + NET_IP_ALIGN)
  67 #define BNXT_RX_DMA_OFFSET NET_SKB_PAD
  68 #define BNXT_RX_COPY_THRESH 256
  69
  70 #define BNXT_TX_PUSH_THRESH 164
  71
  72 enum board_idx {
  73         BCM57301,
  74         BCM57302,
  75         BCM57304,
  76         BCM57417_NPAR,
  77         BCM58700,
  78         BCM57311,
  79         BCM57312,
  80         BCM57402,
  81         BCM57404,
  82         BCM57406,
  83         BCM57402_NPAR,
  84         BCM57407,
  85         BCM57412,
  86         BCM57414,
  87         BCM57416,
  88         BCM57417,
  89         BCM57412_NPAR,
  90         BCM57314,
  91         BCM57417_SFP,
  92         BCM57416_SFP,
  93         BCM57404_NPAR,
  94         BCM57406_NPAR,
  95         BCM57407_SFP,
  96         BCM57407_NPAR,
  97         BCM57414_NPAR,
  98         BCM57416_NPAR,
  99         NETXTREME_E_VF,
 100         NETXTREME_C_VF,
 101 };
 102
 103 /* indexed by enum above */
 104 static const struct {
 105         char *name;
 106 } board_info[] = {
 107         { "Broadcom BCM57301 NetXtreme-C 10Gb Ethernet" },
 108         { "Broadcom BCM57302 NetXtreme-C 10Gb/25Gb Ethernet" },
 109         { "Broadcom BCM57304 NetXtreme-C 10Gb/25Gb/40Gb/50Gb Ethernet" },
 110         { "Broadcom BCM57417 NetXtreme-E Ethernet Partition" },
 111         { "Broadcom BCM58700 Nitro 1Gb/2.5Gb/10Gb Ethernet" },
 112         { "Broadcom BCM57311 NetXtreme-C 10Gb Ethernet" },
 113         { "Broadcom BCM57312 NetXtreme-C 10Gb/25Gb Ethernet" },
 114         { "Broadcom BCM57402 NetXtreme-E 10Gb Ethernet" },
 115         { "Broadcom BCM57404 NetXtreme-E 10Gb/25Gb Ethernet" },
 116         { "Broadcom BCM57406 NetXtreme-E 10GBase-T Ethernet" },
 117         { "Broadcom BCM57402 NetXtreme-E Ethernet Partition" },
 118         { "Broadcom BCM57407 NetXtreme-E 10GBase-T Ethernet" },
 119         { "Broadcom BCM57412 NetXtreme-E 10Gb Ethernet" },
 120         { "Broadcom BCM57414 NetXtreme-E 10Gb/25Gb Ethernet" },
 121         { "Broadcom BCM57416 NetXtreme-E 10GBase-T Ethernet" },
 122         { "Broadcom BCM57417 NetXtreme-E 10GBase-T Ethernet" },
 123         { "Broadcom BCM57412 NetXtreme-E Ethernet Partition" },
 124         { "Broadcom BCM57314 NetXtreme-C 10Gb/25Gb/40Gb/50Gb Ethernet" },
 125         { "Broadcom BCM57417 NetXtreme-E 10Gb/25Gb Ethernet" },
 126         { "Broadcom BCM57416 NetXtreme-E 10Gb Ethernet" },
 127         { "Broadcom BCM57404 NetXtreme-E Ethernet Partition" },
 128         { "Broadcom BCM57406 NetXtreme-E Ethernet Partition" },
 129         { "Broadcom BCM57407 NetXtreme-E 25Gb Ethernet" },
 130         { "Broadcom BCM57407 NetXtreme-E Ethernet Partition" },
 131         { "Broadcom BCM57414 NetXtreme-E Ethernet Partition" },
 132         { "Broadcom BCM57416 NetXtreme-E Ethernet Partition" },
 133         { "Broadcom NetXtreme-E Ethernet Virtual Function" },
 134         { "Broadcom NetXtreme-C Ethernet Virtual Function" },
 135 };
 136
 137 static const struct pci_device_id bnxt_pci_tbl[] = {
 138         { PCI_VDEVICE(BROADCOM, 0x16c0), .driver_data = BCM57417_NPAR },
 139         { PCI_VDEVICE(BROADCOM, 0x16c8), .driver_data = BCM57301 },
 140         { PCI_VDEVICE(BROADCOM, 0x16c9), .driver_data = BCM57302 },
 141         { PCI_VDEVICE(BROADCOM, 0x16ca), .driver_data = BCM57304 },
 142         { PCI_VDEVICE(BROADCOM, 0x16cc), .driver_data = BCM57417_NPAR },
 143         { PCI_VDEVICE(BROADCOM, 0x16cd), .driver_data = BCM58700 },
 144         { PCI_VDEVICE(BROADCOM, 0x16ce), .driver_data = BCM57311 },
 145         { PCI_VDEVICE(BROADCOM, 0x16cf), .driver_data = BCM57312 },
 146         { PCI_VDEVICE(BROADCOM, 0x16d0), .driver_data = BCM57402 },
 147         { PCI_VDEVICE(BROADCOM, 0x16d1), .driver_data = BCM57404 },
 148         { PCI_VDEVICE(BROADCOM, 0x16d2), .driver_data = BCM57406 },
 149         { PCI_VDEVICE(BROADCOM, 0x16d4), .driver_data = BCM57402_NPAR },
 150         { PCI_VDEVICE(BROADCOM, 0x16d5), .driver_data = BCM57407 },
 151         { PCI_VDEVICE(BROADCOM, 0x16d6), .driver_data = BCM57412 },
 152         { PCI_VDEVICE(BROADCOM, 0x16d7), .driver_data = BCM57414 },
 153         { PCI_VDEVICE(BROADCOM, 0x16d8), .driver_data = BCM57416 },
 154         { PCI_VDEVICE(BROADCOM, 0x16d9), .driver_data = BCM57417 },
 155         { PCI_VDEVICE(BROADCOM, 0x16de), .driver_data = BCM57412_NPAR },
 156         { PCI_VDEVICE(BROADCOM, 0x16df), .driver_data = BCM57314 },
 157         { PCI_VDEVICE(BROADCOM, 0x16e2), .driver_data = BCM57417_SFP },
 158         { PCI_VDEVICE(BROADCOM, 0x16e3), .driver_data = BCM57416_SFP },
 159         { PCI_VDEVICE(BROADCOM, 0x16e7), .driver_data = BCM57404_NPAR },
 160         { PCI_VDEVICE(BROADCOM, 0x16e8), .driver_data = BCM57406_NPAR },
 161         { PCI_VDEVICE(BROADCOM, 0x16e9), .driver_data = BCM57407_SFP },
 162         { PCI_VDEVICE(BROADCOM, 0x16ea), .driver_data = BCM57407_NPAR },
 163         { PCI_VDEVICE(BROADCOM, 0x16eb), .driver_data = BCM57412_NPAR },
 164         { PCI_VDEVICE(BROADCOM, 0x16ec), .driver_data = BCM57414_NPAR },
 165         { PCI_VDEVICE(BROADCOM, 0x16ed), .driver_data = BCM57414_NPAR },
 166         { PCI_VDEVICE(BROADCOM, 0x16ee), .driver_data = BCM57416_NPAR },
 167         { PCI_VDEVICE(BROADCOM, 0x16ef), .driver_data = BCM57416_NPAR },
 168 #ifdef CONFIG_BNXT_SRIOV
 169         { PCI_VDEVICE(BROADCOM, 0x16c1), .driver_data = NETXTREME_E_VF },
 170         { PCI_VDEVICE(BROADCOM, 0x16cb), .driver_data = NETXTREME_C_VF },
 171         { PCI_VDEVICE(BROADCOM, 0x16d3), .driver_data = NETXTREME_E_VF },
 172         { PCI_VDEVICE(BROADCOM, 0x16dc), .driver_data = NETXTREME_E_VF },
 173         { PCI_VDEVICE(BROADCOM, 0x16e1), .driver_data = NETXTREME_C_VF },
 174         { PCI_VDEVICE(BROADCOM, 0x16e5), .driver_data = NETXTREME_C_VF },
 175 #endif
 176         { 0 }
 177 };
 178
 179 MODULE_DEVICE_TABLE(pci, bnxt_pci_tbl);
 180
 181 static const u16 bnxt_vf_req_snif[] = {
 182         HWRM_FUNC_CFG,
 183         HWRM_PORT_PHY_QCFG,
 184         HWRM_CFA_L2_FILTER_ALLOC,
 185 };
 186
 187 static const u16 bnxt_async_events_arr[] = {
 188         ASYNC_EVENT_CMPL_EVENT_ID_LINK_STATUS_CHANGE,
 189         ASYNC_EVENT_CMPL_EVENT_ID_PF_DRVR_UNLOAD,
 190         ASYNC_EVENT_CMPL_EVENT_ID_PORT_CONN_NOT_ALLOWED,
 191         ASYNC_EVENT_CMPL_EVENT_ID_VF_CFG_CHANGE,
 192         ASYNC_EVENT_CMPL_EVENT_ID_LINK_SPEED_CFG_CHANGE,
 193 };
 194
 195 static bool bnxt_vf_pciid(enum board_idx idx)
 196 {
 197         return (idx == NETXTREME_C_VF || idx == NETXTREME_E_VF);
 198 }
 199
 200 #define DB_CP_REARM_FLAGS       (DB_KEY_CP | DB_IDX_VALID)
 201 #define DB_CP_FLAGS             (DB_KEY_CP | DB_IDX_VALID | DB_IRQ_DIS)
 202 #define DB_CP_IRQ_DIS_FLAGS     (DB_KEY_CP | DB_IRQ_DIS)
 203
 204 #define BNXT_CP_DB_REARM(db, raw_cons)                                  \
 205                 writel(DB_CP_REARM_FLAGS | RING_CMP(raw_cons), db)
 206
 207 #define BNXT_CP_DB(db, raw_cons)                                        \
 208                 writel(DB_CP_FLAGS | RING_CMP(raw_cons), db)
 209
 210 #define BNXT_CP_DB_IRQ_DIS(db)                                          \
 211                 writel(DB_CP_IRQ_DIS_FLAGS, db)
 212
 213 static inline u32 bnxt_tx_avail(struct bnxt *bp, struct bnxt_tx_ring_info *txr)
 214 {
 215         /* Tell compiler to fetch tx indices from memory. */
 216         barrier();
 217
 218         return bp->tx_ring_size -
 219                 ((txr->tx_prod - txr->tx_cons) & bp->tx_ring_mask);
 220 }
 221
 222 static const u16 bnxt_lhint_arr[] = {
 223         TX_BD_FLAGS_LHINT_512_AND_SMALLER,
 224         TX_BD_FLAGS_LHINT_512_TO_1023,
 225         TX_BD_FLAGS_LHINT_1024_TO_2047,
 226         TX_BD_FLAGS_LHINT_1024_TO_2047,
 227         TX_BD_FLAGS_LHINT_2048_AND_LARGER,
 228         TX_BD_FLAGS_LHINT_2048_AND_LARGER,
 229         TX_BD_FLAGS_LHINT_2048_AND_LARGER,
 230         TX_BD_FLAGS_LHINT_2048_AND_LARGER,
 231         TX_BD_FLAGS_LHINT_2048_AND_LARGER,
 232         TX_BD_FLAGS_LHINT_2048_AND_LARGER,
 233         TX_BD_FLAGS_LHINT_2048_AND_LARGER,
 234         TX_BD_FLAGS_LHINT_2048_AND_LARGER,
 235         TX_BD_FLAGS_LHINT_2048_AND_LARGER,
 236         TX_BD_FLAGS_LHINT_2048_AND_LARGER,
 237         TX_BD_FLAGS_LHINT_2048_AND_LARGER,
 238         TX_BD_FLAGS_LHINT_2048_AND_LARGER,
 239         TX_BD_FLAGS_LHINT_2048_AND_LARGER,
 240         TX_BD_FLAGS_LHINT_2048_AND_LARGER,
 241         TX_BD_FLAGS_LHINT_2048_AND_LARGER,
 242 };
 243
 244 static netdev_tx_t bnxt_start_xmit(struct sk_buff *skb, struct net_device *dev)
 245 {
 246         struct bnxt *bp = netdev_priv(dev);
 247         struct tx_bd *txbd;
 248         struct tx_bd_ext *txbd1;
 249         struct netdev_queue *txq;
 250         int i;
 251         dma_addr_t mapping;
 252         unsigned int length, pad = 0;
 253         u32 len, free_size, vlan_tag_flags, cfa_action, flags;
 254         u16 prod, last_frag;
 255         struct pci_dev *pdev = bp->pdev;
 256         struct bnxt_tx_ring_info *txr;
 257         struct bnxt_sw_tx_bd *tx_buf;
 258
 259         i = skb_get_queue_mapping(skb);
 260         if (unlikely(i >= bp->tx_nr_rings)) {
 261                 dev_kfree_skb_any(skb);
 262                 return NETDEV_TX_OK;
 263         }
 264
 265         txq = netdev_get_tx_queue(dev, i);
 266         txr = &bp->tx_ring[bp->tx_ring_map[i]];
 267         prod = txr->tx_prod;
 268
 269         free_size = bnxt_tx_avail(bp, txr);
 270         if (unlikely(free_size < skb_shinfo(skb)->nr_frags + 2)) {
 271                 netif_tx_stop_queue(txq);
 272                 return NETDEV_TX_BUSY;
 273         }
 274
 275         length = skb->len;
 276         len = skb_headlen(skb);
 277         last_frag = skb_shinfo(skb)->nr_frags;
 278
 279         txbd = &txr->tx_desc_ring[TX_RING(prod)][TX_IDX(prod)];
 280
 281         txbd->tx_bd_opaque = prod;
 282
 283         tx_buf = &txr->tx_buf_ring[prod];
 284         tx_buf->skb = skb;
 285         tx_buf->nr_frags = last_frag;
 286
 287         vlan_tag_flags = 0;
 288         cfa_action = 0;
 289         if (skb_vlan_tag_present(skb)) {
 290                 vlan_tag_flags = TX_BD_CFA_META_KEY_VLAN |
 291                                  skb_vlan_tag_get(skb);
 292                 /* Currently supports 8021Q, 8021AD vlan offloads
 293                  * QINQ1, QINQ2, QINQ3 vlan headers are deprecated
 294                  */
 295                 if (skb->vlan_proto == htons(ETH_P_8021Q))
 296                         vlan_tag_flags |= 1 << TX_BD_CFA_META_TPID_SHIFT;
 297         }
 298
 299         if (free_size == bp->tx_ring_size && length <= bp->tx_push_thresh) {
 300                 struct tx_push_buffer *tx_push_buf = txr->tx_push;
 301                 struct tx_push_bd *tx_push = &tx_push_buf->push_bd;
 302                 struct tx_bd_ext *tx_push1 = &tx_push->txbd2;
 303                 void *pdata = tx_push_buf->data;
 304                 u64 *end;
 305                 int j, push_len;
 306
 307                 /* Set COAL_NOW to be ready quickly for the next push */
 308                 tx_push->tx_bd_len_flags_type =
 309                         cpu_to_le32((length << TX_BD_LEN_SHIFT) |
 310                                         TX_BD_TYPE_LONG_TX_BD |
 311                                         TX_BD_FLAGS_LHINT_512_AND_SMALLER |
 312                                         TX_BD_FLAGS_COAL_NOW |
 313                                         TX_BD_FLAGS_PACKET_END |
 314                                         (2 << TX_BD_FLAGS_BD_CNT_SHIFT));
 315
 316                 if (skb->ip_summed == CHECKSUM_PARTIAL)
 317                         tx_push1->tx_bd_hsize_lflags =
 318                                         cpu_to_le32(TX_BD_FLAGS_TCP_UDP_CHKSUM);
 319                 else
 320                         tx_push1->tx_bd_hsize_lflags = 0;
 321
 322                 tx_push1->tx_bd_cfa_meta = cpu_to_le32(vlan_tag_flags);
 323                 tx_push1->tx_bd_cfa_action = cpu_to_le32(cfa_action);
 324
 325                 end = pdata + length;
 326                 end = PTR_ALIGN(end, 8) - 1;
 327                 *end = 0;
 328
 329                 skb_copy_from_linear_data(skb, pdata, len);
 330                 pdata += len;
 331                 for (j = 0; j < last_frag; j++) {
 332                         skb_frag_t *frag = &skb_shinfo(skb)->frags[j];
 333                         void *fptr;
 334
 335                         fptr = skb_frag_address_safe(frag);
 336                         if (!fptr)
 337                                 goto normal_tx;
 338
 339                         memcpy(pdata, fptr, skb_frag_size(frag));
 340                         pdata += skb_frag_size(frag);
 341                 }
 342
 343                 txbd->tx_bd_len_flags_type = tx_push->tx_bd_len_flags_type;
 344                 txbd->tx_bd_haddr = txr->data_mapping;
 345                 prod = NEXT_TX(prod);
 346                 txbd = &txr->tx_desc_ring[TX_RING(prod)][TX_IDX(prod)];
 347                 memcpy(txbd, tx_push1, sizeof(*txbd));
 348                 prod = NEXT_TX(prod);
 349                 tx_push->doorbell =
 350                         cpu_to_le32(DB_KEY_TX_PUSH | DB_LONG_TX_PUSH | prod);
 351                 txr->tx_prod = prod;
 352
 353                 tx_buf->is_push = 1;
 354                 netdev_tx_sent_queue(txq, skb->len);
 355                 wmb();  /* Sync is_push and byte queue before pushing data */
 356
 357                 push_len = (length + sizeof(*tx_push) + 7) / 8;
 358                 if (push_len > 16) {
 359                         __iowrite64_copy(txr->tx_doorbell, tx_push_buf, 16);
 360                         __iowrite32_copy(txr->tx_doorbell + 4, tx_push_buf + 1,
 361                                          (push_len - 16) << 1);
 362                 } else {
 363                         __iowrite64_copy(txr->tx_doorbell, tx_push_buf,
 364                                          push_len);
 365                 }
 366
 367                 goto tx_done;
 368         }
 369
 370 normal_tx:
 371         if (length < BNXT_MIN_PKT_SIZE) {
 372                 pad = BNXT_MIN_PKT_SIZE - length;
 373                 if (skb_pad(skb, pad)) {
 374                         /* SKB already freed. */
 375                         tx_buf->skb = NULL;
 376                         return NETDEV_TX_OK;
 377                 }
 378                 length = BNXT_MIN_PKT_SIZE;
 379         }
 380
 381         mapping = dma_map_single(&pdev->dev, skb->data, len, DMA_TO_DEVICE);
 382
 383         if (unlikely(dma_mapping_error(&pdev->dev, mapping))) {
 384                 dev_kfree_skb_any(skb);
 385                 tx_buf->skb = NULL;
 386                 return NETDEV_TX_OK;
 387         }
 388
 389         dma_unmap_addr_set(tx_buf, mapping, mapping);
 390         flags = (len << TX_BD_LEN_SHIFT) | TX_BD_TYPE_LONG_TX_BD |
 391                 ((last_frag + 2) << TX_BD_FLAGS_BD_CNT_SHIFT);
 392
 393         txbd->tx_bd_haddr = cpu_to_le64(mapping);
 394
 395         prod = NEXT_TX(prod);
 396         txbd1 = (struct tx_bd_ext *)
 397                 &txr->tx_desc_ring[TX_RING(prod)][TX_IDX(prod)];
 398
 399         txbd1->tx_bd_hsize_lflags = 0;
 400         if (skb_is_gso(skb)) {
 401                 u32 hdr_len;
 402
 403                 if (skb->encapsulation)
 404                         hdr_len = skb_inner_network_offset(skb) +
 405                                 skb_inner_network_header_len(skb) +
 406                                 inner_tcp_hdrlen(skb);
 407                 else
 408                         hdr_len = skb_transport_offset(skb) +
 409                                 tcp_hdrlen(skb);
 410
 411                 txbd1->tx_bd_hsize_lflags = cpu_to_le32(TX_BD_FLAGS_LSO |
 412                                         TX_BD_FLAGS_T_IPID |
 413                                         (hdr_len << (TX_BD_HSIZE_SHIFT - 1)));
 414                 length = skb_shinfo(skb)->gso_size;
 415                 txbd1->tx_bd_mss = cpu_to_le32(length);
 416                 length += hdr_len;
 417         } else if (skb->ip_summed == CHECKSUM_PARTIAL) {
 418                 txbd1->tx_bd_hsize_lflags =
 419                         cpu_to_le32(TX_BD_FLAGS_TCP_UDP_CHKSUM);
 420                 txbd1->tx_bd_mss = 0;
 421         }
 422
 423         length >>= 9;
 424         flags |= bnxt_lhint_arr[length];
 425         txbd->tx_bd_len_flags_type = cpu_to_le32(flags);
 426
 427         txbd1->tx_bd_cfa_meta = cpu_to_le32(vlan_tag_flags);
 428         txbd1->tx_bd_cfa_action = cpu_to_le32(cfa_action);
 429         for (i = 0; i < last_frag; i++) {
 430                 skb_frag_t *frag = &skb_shinfo(skb)->frags[i];
 431
 432                 prod = NEXT_TX(prod);
 433                 txbd = &txr->tx_desc_ring[TX_RING(prod)][TX_IDX(prod)];
 434
 435                 len = skb_frag_size(frag);
 436                 mapping = skb_frag_dma_map(&pdev->dev, frag, 0, len,
 437                                            DMA_TO_DEVICE);
 438
 439                 if (unlikely(dma_mapping_error(&pdev->dev, mapping)))
 440                         goto tx_dma_error;
 441
 442                 tx_buf = &txr->tx_buf_ring[prod];
 443                 dma_unmap_addr_set(tx_buf, mapping, mapping);
 444
 445                 txbd->tx_bd_haddr = cpu_to_le64(mapping);
 446
 447                 flags = len << TX_BD_LEN_SHIFT;
 448                 txbd->tx_bd_len_flags_type = cpu_to_le32(flags);
 449         }
 450
 451         flags &= ~TX_BD_LEN;
 452         txbd->tx_bd_len_flags_type =
 453                 cpu_to_le32(((len + pad) << TX_BD_LEN_SHIFT) | flags |
 454                             TX_BD_FLAGS_PACKET_END);
 455
 456         netdev_tx_sent_queue(txq, skb->len);
 457
 458         /* Sync BD data before updating doorbell */
 459         wmb();
 460
 461         prod = NEXT_TX(prod);
 462         txr->tx_prod = prod;
 463
 464         writel(DB_KEY_TX | prod, txr->tx_doorbell);
 465         writel(DB_KEY_TX | prod, txr->tx_doorbell);
 466
 467 tx_done:
 468
 469         mmiowb();
 470
 471         if (unlikely(bnxt_tx_avail(bp, txr) <= MAX_SKB_FRAGS + 1)) {
 472                 netif_tx_stop_queue(txq);
 473
 474                 /* netif_tx_stop_queue() must be done before checking
 475                  * tx index in bnxt_tx_avail() below, because in
 476                  * bnxt_tx_int(), we update tx index before checking for
 477                  * netif_tx_queue_stopped().
 478                  */
 479                 smp_mb();
 480                 if (bnxt_tx_avail(bp, txr) > bp->tx_wake_thresh)
 481                         netif_tx_wake_queue(txq);
 482         }
 483         return NETDEV_TX_OK;
 484
 485 tx_dma_error:
 486         last_frag = i;
 487
 488         /* start back at beginning and unmap skb */
 489         prod = txr->tx_prod;
 490         tx_buf = &txr->tx_buf_ring[prod];
 491         tx_buf->skb = NULL;
 492         dma_unmap_single(&pdev->dev, dma_unmap_addr(tx_buf, mapping),
 493                          skb_headlen(skb), PCI_DMA_TODEVICE);
 494         prod = NEXT_TX(prod);
 495
 496         /* unmap remaining mapped pages */
 497         for (i = 0; i < last_frag; i++) {
 498                 prod = NEXT_TX(prod);
 499                 tx_buf = &txr->tx_buf_ring[prod];
 500                 dma_unmap_page(&pdev->dev, dma_unmap_addr(tx_buf, mapping),
 501                                skb_frag_size(&skb_shinfo(skb)->frags[i]),
 502                                PCI_DMA_TODEVICE);
 503         }
 504
 505         dev_kfree_skb_any(skb);
 506         return NETDEV_TX_OK;
 507 }
 508
 509 static void bnxt_tx_int(struct bnxt *bp, struct bnxt_napi *bnapi, int nr_pkts)
 510 {
 511         struct bnxt_tx_ring_info *txr = bnapi->tx_ring;
 512         struct netdev_queue *txq = netdev_get_tx_queue(bp->dev, txr->txq_index);
 513         u16 cons = txr->tx_cons;
 514         struct pci_dev *pdev = bp->pdev;
 515         int i;
 516         unsigned int tx_bytes = 0;
 517
 518         for (i = 0; i < nr_pkts; i++) {
 519                 struct bnxt_sw_tx_bd *tx_buf;
 520                 struct sk_buff *skb;
 521                 int j, last;
 522
 523                 tx_buf = &txr->tx_buf_ring[cons];
 524                 cons = NEXT_TX(cons);
 525                 skb = tx_buf->skb;
 526                 tx_buf->skb = NULL;
 527
 528                 if (tx_buf->is_push) {
 529                         tx_buf->is_push = 0;
 530                         goto next_tx_int;
 531                 }
 532
 533                 dma_unmap_single(&pdev->dev, dma_unmap_addr(tx_buf, mapping),
 534                                  skb_headlen(skb), PCI_DMA_TODEVICE);
 535                 last = tx_buf->nr_frags;
 536
 537                 for (j = 0; j < last; j++) {
 538                         cons = NEXT_TX(cons);
 539                         tx_buf = &txr->tx_buf_ring[cons];
 540                         dma_unmap_page(
 541                                 &pdev->dev,
 542                                 dma_unmap_addr(tx_buf, mapping),
 543                                 skb_frag_size(&skb_shinfo(skb)->frags[j]),
 544                                 PCI_DMA_TODEVICE);
 545                 }
 546
 547 next_tx_int:
 548                 cons = NEXT_TX(cons);
 549
 550                 tx_bytes += skb->len;
 551                 dev_kfree_skb_any(skb);
 552         }
 553
 554         netdev_tx_completed_queue(txq, nr_pkts, tx_bytes);
 555         txr->tx_cons = cons;
 556
 557         /* Need to make the tx_cons update visible to bnxt_start_xmit()
 558          * before checking for netif_tx_queue_stopped().  Without the
 559          * memory barrier, there is a small possibility that bnxt_start_xmit()
 560          * will miss it and cause the queue to be stopped forever.
 561          */
 562         smp_mb();
 563
 564         if (unlikely(netif_tx_queue_stopped(txq)) &&
 565             (bnxt_tx_avail(bp, txr) > bp->tx_wake_thresh)) {
 566                 __netif_tx_lock(txq, smp_processor_id());
 567                 if (netif_tx_queue_stopped(txq) &&
 568                     bnxt_tx_avail(bp, txr) > bp->tx_wake_thresh &&
 569                     txr->dev_state != BNXT_DEV_STATE_CLOSING)
 570                         netif_tx_wake_queue(txq);
 571                 __netif_tx_unlock(txq);
 572         }
 573 }
 574
 575 static struct page *__bnxt_alloc_rx_page(struct bnxt *bp, dma_addr_t *mapping,
 576                                          gfp_t gfp)
 577 {
 578         struct device *dev = &bp->pdev->dev;
 579         struct page *page;
 580
 581         page = alloc_page(gfp);
 582         if (!page)
 583                 return NULL;
 584
 585         *mapping = dma_map_page(dev, page, 0, PAGE_SIZE, bp->rx_dir);
 586         if (dma_mapping_error(dev, *mapping)) {
 587                 __free_page(page);
 588                 return NULL;
 589         }
 590         *mapping += bp->rx_dma_offset;
 591         return page;
 592 }
 593
 594 static inline u8 *__bnxt_alloc_rx_data(struct bnxt *bp, dma_addr_t *mapping,
 595                                        gfp_t gfp)
 596 {
 597         u8 *data;
 598         struct pci_dev *pdev = bp->pdev;
 599
 600         data = kmalloc(bp->rx_buf_size, gfp);
 601         if (!data)
 602                 return NULL;
 603
 604         *mapping = dma_map_single(&pdev->dev, data + bp->rx_dma_offset,
 605                                   bp->rx_buf_use_size, bp->rx_dir);
 606
 607         if (dma_mapping_error(&pdev->dev, *mapping)) {
 608                 kfree(data);
 609                 data = NULL;
 610         }
 611         return data;
 612 }
 613
 614 static inline int bnxt_alloc_rx_data(struct bnxt *bp,
 615                                      struct bnxt_rx_ring_info *rxr,
 616                                      u16 prod, gfp_t gfp)
 617 {
 618         struct rx_bd *rxbd = &rxr->rx_desc_ring[RX_RING(prod)][RX_IDX(prod)];
 619         struct bnxt_sw_rx_bd *rx_buf = &rxr->rx_buf_ring[prod];
 620         dma_addr_t mapping;
 621
 622         if (BNXT_RX_PAGE_MODE(bp)) {
 623                 struct page *page = __bnxt_alloc_rx_page(bp, &mapping, gfp);
 624
 625                 if (!page)
 626                         return -ENOMEM;
 627
 628                 rx_buf->data = page;
 629                 rx_buf->data_ptr = page_address(page) + bp->rx_offset;
 630         } else {
 631                 u8 *data = __bnxt_alloc_rx_data(bp, &mapping, gfp);
 632
 633                 if (!data)
 634                         return -ENOMEM;
 635
 636                 rx_buf->data = data;
 637                 rx_buf->data_ptr = data + bp->rx_offset;
 638         }
 639         rx_buf->mapping = mapping;
 640
 641         rxbd->rx_bd_haddr = cpu_to_le64(mapping);
 642         return 0;
 643 }
 644
 645 static void bnxt_reuse_rx_data(struct bnxt_rx_ring_info *rxr, u16 cons,
 646                                void *data)
 647 {
 648         u16 prod = rxr->rx_prod;
 649         struct bnxt_sw_rx_bd *cons_rx_buf, *prod_rx_buf;
 650         struct rx_bd *cons_bd, *prod_bd;
 651
 652         prod_rx_buf = &rxr->rx_buf_ring[prod];
 653         cons_rx_buf = &rxr->rx_buf_ring[cons];
 654
 655         prod_rx_buf->data = data;
 656         prod_rx_buf->data_ptr = cons_rx_buf->data_ptr;
 657
 658         prod_rx_buf->mapping = cons_rx_buf->mapping;
 659
 660         prod_bd = &rxr->rx_desc_ring[RX_RING(prod)][RX_IDX(prod)];
 661         cons_bd = &rxr->rx_desc_ring[RX_RING(cons)][RX_IDX(cons)];
 662
 663         prod_bd->rx_bd_haddr = cons_bd->rx_bd_haddr;
 664 }
 665
 666 static inline u16 bnxt_find_next_agg_idx(struct bnxt_rx_ring_info *rxr, u16 idx)
 667 {
 668         u16 next, max = rxr->rx_agg_bmap_size;
 669
 670         next = find_next_zero_bit(rxr->rx_agg_bmap, max, idx);
 671         if (next >= max)
 672                 next = find_first_zero_bit(rxr->rx_agg_bmap, max);
 673         return next;
 674 }
 675
 676 static inline int bnxt_alloc_rx_page(struct bnxt *bp,
 677                                      struct bnxt_rx_ring_info *rxr,
 678                                      u16 prod, gfp_t gfp)
 679 {
 680         struct rx_bd *rxbd =
 681                 &rxr->rx_agg_desc_ring[RX_RING(prod)][RX_IDX(prod)];
 682         struct bnxt_sw_rx_agg_bd *rx_agg_buf;
 683         struct pci_dev *pdev = bp->pdev;
 684         struct page *page;
 685         dma_addr_t mapping;
 686         u16 sw_prod = rxr->rx_sw_agg_prod;
 687         unsigned int offset = 0;
 688
 689         if (PAGE_SIZE > BNXT_RX_PAGE_SIZE) {
 690                 page = rxr->rx_page;
 691                 if (!page) {
 692                         page = alloc_page(gfp);
 693                         if (!page)
 694                                 return -ENOMEM;
 695                         rxr->rx_page = page;
 696                         rxr->rx_page_offset = 0;
 697                 }
 698                 offset = rxr->rx_page_offset;
 699                 rxr->rx_page_offset += BNXT_RX_PAGE_SIZE;
 700                 if (rxr->rx_page_offset == PAGE_SIZE)
 701                         rxr->rx_page = NULL;
 702                 else
 703                         get_page(page);
 704         } else {
 705                 page = alloc_page(gfp);
 706                 if (!page)
 707                         return -ENOMEM;
 708         }
 709
 710         mapping = dma_map_page(&pdev->dev, page, offset, BNXT_RX_PAGE_SIZE,
 711                                PCI_DMA_FROMDEVICE);
 712         if (dma_mapping_error(&pdev->dev, mapping)) {
 713                 __free_page(page);
 714                 return -EIO;
 715         }
 716
 717         if (unlikely(test_bit(sw_prod, rxr->rx_agg_bmap)))
 718                 sw_prod = bnxt_find_next_agg_idx(rxr, sw_prod);
 719
 720         __set_bit(sw_prod, rxr->rx_agg_bmap);
 721         rx_agg_buf = &rxr->rx_agg_ring[sw_prod];
 722         rxr->rx_sw_agg_prod = NEXT_RX_AGG(sw_prod);
 723
 724         rx_agg_buf->page = page;
 725         rx_agg_buf->offset = offset;
 726         rx_agg_buf->mapping = mapping;
 727         rxbd->rx_bd_haddr = cpu_to_le64(mapping);
 728         rxbd->rx_bd_opaque = sw_prod;
 729         return 0;
 730 }
 731
 732 static void bnxt_reuse_rx_agg_bufs(struct bnxt_napi *bnapi, u16 cp_cons,
 733                                    u32 agg_bufs)
 734 {
 735         struct bnxt *bp = bnapi->bp;
 736         struct bnxt_cp_ring_info *cpr = &bnapi->cp_ring;
 737         struct bnxt_rx_ring_info *rxr = bnapi->rx_ring;
 738         u16 prod = rxr->rx_agg_prod;
 739         u16 sw_prod = rxr->rx_sw_agg_prod;
 740         u32 i;
 741
 742         for (i = 0; i < agg_bufs; i++) {
 743                 u16 cons;
 744                 struct rx_agg_cmp *agg;
 745                 struct bnxt_sw_rx_agg_bd *cons_rx_buf, *prod_rx_buf;
 746                 struct rx_bd *prod_bd;
 747                 struct page *page;
 748
 749                 agg = (struct rx_agg_cmp *)
 750                         &cpr->cp_desc_ring[CP_RING(cp_cons)][CP_IDX(cp_cons)];
 751                 cons = agg->rx_agg_cmp_opaque;
 752                 __clear_bit(cons, rxr->rx_agg_bmap);
 753
 754                 if (unlikely(test_bit(sw_prod, rxr->rx_agg_bmap)))
 755                         sw_prod = bnxt_find_next_agg_idx(rxr, sw_prod);
 756
 757                 __set_bit(sw_prod, rxr->rx_agg_bmap);
 758                 prod_rx_buf = &rxr->rx_agg_ring[sw_prod];
 759                 cons_rx_buf = &rxr->rx_agg_ring[cons];
 760
 761                 /* It is possible for sw_prod to be equal to cons, so
 762                  * set cons_rx_buf->page to NULL first.
 763                  */
 764                 page = cons_rx_buf->page;
 765                 cons_rx_buf->page = NULL;
 766                 prod_rx_buf->page = page;
 767                 prod_rx_buf->offset = cons_rx_buf->offset;
 768
 769                 prod_rx_buf->mapping = cons_rx_buf->mapping;
 770
 771                 prod_bd = &rxr->rx_agg_desc_ring[RX_RING(prod)][RX_IDX(prod)];
 772
 773                 prod_bd->rx_bd_haddr = cpu_to_le64(cons_rx_buf->mapping);
 774                 prod_bd->rx_bd_opaque = sw_prod;
 775
 776                 prod = NEXT_RX_AGG(prod);
 777                 sw_prod = NEXT_RX_AGG(sw_prod);
 778                 cp_cons = NEXT_CMP(cp_cons);
 779         }
 780         rxr->rx_agg_prod = prod;
 781         rxr->rx_sw_agg_prod = sw_prod;
 782 }
 783
 784 static struct sk_buff *bnxt_rx_page_skb(struct bnxt *bp,
 785                                         struct bnxt_rx_ring_info *rxr,
 786                                         u16 cons, void *data, u8 *data_ptr,
 787                                         dma_addr_t dma_addr,
 788                                         unsigned int offset_and_len)
 789 {
 790         unsigned int payload = offset_and_len >> 16;
 791         unsigned int len = offset_and_len & 0xffff;
 792         struct skb_frag_struct *frag;
 793         struct page *page = data;
 794         u16 prod = rxr->rx_prod;
 795         struct sk_buff *skb;
 796         int off, err;
 797
 798         err = bnxt_alloc_rx_data(bp, rxr, prod, GFP_ATOMIC);
 799         if (unlikely(err)) {
 800                 bnxt_reuse_rx_data(rxr, cons, data);
 801                 return NULL;
 802         }
 803         dma_addr -= bp->rx_dma_offset;
 804         dma_unmap_page(&bp->pdev->dev, dma_addr, PAGE_SIZE, bp->rx_dir);
 805
 806         if (unlikely(!payload))
 807                 payload = eth_get_headlen(data_ptr, len);
 808
 809         skb = napi_alloc_skb(&rxr->bnapi->napi, payload);
 810         if (!skb) {
 811                 __free_page(page);
 812                 return NULL;
 813         }
 814
 815         off = (void *)data_ptr - page_address(page);
 816         skb_add_rx_frag(skb, 0, page, off, len, PAGE_SIZE);
 817         memcpy(skb->data - NET_IP_ALIGN, data_ptr - NET_IP_ALIGN,
 818                payload + NET_IP_ALIGN);
 819
 820         frag = &skb_shinfo(skb)->frags[0];
 821         skb_frag_size_sub(frag, payload);
 822         frag->page_offset += payload;
 823         skb->data_len -= payload;
 824         skb->tail += payload;
 825
 826         return skb;
 827 }
 828
 829 static struct sk_buff *bnxt_rx_skb(struct bnxt *bp,
 830                                    struct bnxt_rx_ring_info *rxr, u16 cons,
 831                                    void *data, u8 *data_ptr,
 832                                    dma_addr_t dma_addr,
 833                                    unsigned int offset_and_len)
 834 {
 835         u16 prod = rxr->rx_prod;
 836         struct sk_buff *skb;
 837         int err;
 838
 839         err = bnxt_alloc_rx_data(bp, rxr, prod, GFP_ATOMIC);
 840         if (unlikely(err)) {
 841                 bnxt_reuse_rx_data(rxr, cons, data);
 842                 return NULL;
 843         }
 844
 845         skb = build_skb(data, 0);
 846         dma_unmap_single(&bp->pdev->dev, dma_addr, bp->rx_buf_use_size,
 847                          bp->rx_dir);
 848         if (!skb) {
 849                 kfree(data);
 850                 return NULL;
 851         }
 852
 853         skb_reserve(skb, bp->rx_offset);
 854         skb_put(skb, offset_and_len & 0xffff);
 855         return skb;
 856 }
 857
 858 static struct sk_buff *bnxt_rx_pages(struct bnxt *bp, struct bnxt_napi *bnapi,
 859                                      struct sk_buff *skb, u16 cp_cons,
 860                                      u32 agg_bufs)
 861 {
 862         struct pci_dev *pdev = bp->pdev;
 863         struct bnxt_cp_ring_info *cpr = &bnapi->cp_ring;
 864         struct bnxt_rx_ring_info *rxr = bnapi->rx_ring;
 865         u16 prod = rxr->rx_agg_prod;
 866         u32 i;
 867
 868         for (i = 0; i < agg_bufs; i++) {
 869                 u16 cons, frag_len;
 870                 struct rx_agg_cmp *agg;
 871                 struct bnxt_sw_rx_agg_bd *cons_rx_buf;
 872                 struct page *page;
 873                 dma_addr_t mapping;
 874
 875                 agg = (struct rx_agg_cmp *)
 876                         &cpr->cp_desc_ring[CP_RING(cp_cons)][CP_IDX(cp_cons)];
 877                 cons = agg->rx_agg_cmp_opaque;
 878                 frag_len = (le32_to_cpu(agg->rx_agg_cmp_len_flags_type) &
 879                             RX_AGG_CMP_LEN) >> RX_AGG_CMP_LEN_SHIFT;
 880
 881                 cons_rx_buf = &rxr->rx_agg_ring[cons];
 882                 skb_fill_page_desc(skb, i, cons_rx_buf->page,
 883                                    cons_rx_buf->offset, frag_len);
 884                 __clear_bit(cons, rxr->rx_agg_bmap);
 885
 886                 /* It is possible for bnxt_alloc_rx_page() to allocate
 887                  * a sw_prod index that equals the cons index, so we
 888                  * need to clear the cons entry now.
 889                  */
 890                 mapping = cons_rx_buf->mapping;
 891                 page = cons_rx_buf->page;
 892                 cons_rx_buf->page = NULL;
 893
 894                 if (bnxt_alloc_rx_page(bp, rxr, prod, GFP_ATOMIC) != 0) {
 895                         struct skb_shared_info *shinfo;
 896                         unsigned int nr_frags;
 897
 898                         shinfo = skb_shinfo(skb);
 899                         nr_frags = --shinfo->nr_frags;
 900                         __skb_frag_set_page(&shinfo->frags[nr_frags], NULL);
 901
 902                         dev_kfree_skb(skb);
 903
 904                         cons_rx_buf->page = page;
 905
 906                         /* Update prod since possibly some pages have been
 907                          * allocated already.
 908                          */
 909                         rxr->rx_agg_prod = prod;
 910                         bnxt_reuse_rx_agg_bufs(bnapi, cp_cons, agg_bufs - i);
 911                         return NULL;
 912                 }
 913
 914                 dma_unmap_page(&pdev->dev, mapping, BNXT_RX_PAGE_SIZE,
 915                                PCI_DMA_FROMDEVICE);
 916
 917                 skb->data_len += frag_len;
 918                 skb->len += frag_len;
 919                 skb->truesize += PAGE_SIZE;
 920
 921                 prod = NEXT_RX_AGG(prod);
 922                 cp_cons = NEXT_CMP(cp_cons);
 923         }
 924         rxr->rx_agg_prod = prod;
 925         return skb;
 926 }
 927
 928 static int bnxt_agg_bufs_valid(struct bnxt *bp, struct bnxt_cp_ring_info *cpr,
 929                                u8 agg_bufs, u32 *raw_cons)
 930 {
 931         u16 last;
 932         struct rx_agg_cmp *agg;
 933
 934         *raw_cons = ADV_RAW_CMP(*raw_cons, agg_bufs);
 935         last = RING_CMP(*raw_cons);
 936         agg = (struct rx_agg_cmp *)
 937                 &cpr->cp_desc_ring[CP_RING(last)][CP_IDX(last)];
 938         return RX_AGG_CMP_VALID(agg, *raw_cons);
 939 }
 940
 941 static inline struct sk_buff *bnxt_copy_skb(struct bnxt_napi *bnapi, u8 *data,
 942                                             unsigned int len,
 943                                             dma_addr_t mapping)
 944 {
 945         struct bnxt *bp = bnapi->bp;
 946         struct pci_dev *pdev = bp->pdev;
 947         struct sk_buff *skb;
 948
 949         skb = napi_alloc_skb(&bnapi->napi, len);
 950         if (!skb)
 951                 return NULL;
 952
 953         dma_sync_single_for_cpu(&pdev->dev, mapping, bp->rx_copy_thresh,
 954                                 bp->rx_dir);
 955
 956         memcpy(skb->data - NET_IP_ALIGN, data - NET_IP_ALIGN,
 957                len + NET_IP_ALIGN);
 958
 959         dma_sync_single_for_device(&pdev->dev, mapping, bp->rx_copy_thresh,
 960                                    bp->rx_dir);
 961
 962         skb_put(skb, len);
 963         return skb;
 964 }
 965
 966 static int bnxt_discard_rx(struct bnxt *bp, struct bnxt_napi *bnapi,
 967                            u32 *raw_cons, void *cmp)
 968 {
 969         struct bnxt_cp_ring_info *cpr = &bnapi->cp_ring;
 970         struct rx_cmp *rxcmp = cmp;
 971         u32 tmp_raw_cons = *raw_cons;
 972         u8 cmp_type, agg_bufs = 0;
 973
 974         cmp_type = RX_CMP_TYPE(rxcmp);
 975
 976         if (cmp_type == CMP_TYPE_RX_L2_CMP) {
 977                 agg_bufs = (le32_to_cpu(rxcmp->rx_cmp_misc_v1) &
 978                             RX_CMP_AGG_BUFS) >>
 979                            RX_CMP_AGG_BUFS_SHIFT;
 980         } else if (cmp_type == CMP_TYPE_RX_L2_TPA_END_CMP) {
 981                 struct rx_tpa_end_cmp *tpa_end = cmp;
 982
 983                 agg_bufs = (le32_to_cpu(tpa_end->rx_tpa_end_cmp_misc_v1) &
 984                             RX_TPA_END_CMP_AGG_BUFS) >>
 985                            RX_TPA_END_CMP_AGG_BUFS_SHIFT;
 986         }
 987
 988         if (agg_bufs) {
 989                 if (!bnxt_agg_bufs_valid(bp, cpr, agg_bufs, &tmp_raw_cons))
 990                         return -EBUSY;
 991         }
 992         *raw_cons = tmp_raw_cons;
 993         return 0;
 994 }
 995
 996 static void bnxt_sched_reset(struct bnxt *bp, struct bnxt_rx_ring_info *rxr)
 997 {
 998         if (!rxr->bnapi->in_reset) {
 999                 rxr->bnapi->in_reset = true;
1000                 set_bit(BNXT_RESET_TASK_SP_EVENT, &bp->sp_event);
1001                 schedule_work(&bp->sp_task);
1002         }
1003         rxr->rx_next_cons = 0xffff;
1004 }
1005
1006 static void bnxt_tpa_start(struct bnxt *bp, struct bnxt_rx_ring_info *rxr,
1007                            struct rx_tpa_start_cmp *tpa_start,
1008                            struct rx_tpa_start_cmp_ext *tpa_start1)
1009 {
1010         u8 agg_id = TPA_START_AGG_ID(tpa_start);
1011         u16 cons, prod;
1012         struct bnxt_tpa_info *tpa_info;
1013         struct bnxt_sw_rx_bd *cons_rx_buf, *prod_rx_buf;
1014         struct rx_bd *prod_bd;
1015         dma_addr_t mapping;
1016
1017         cons = tpa_start->rx_tpa_start_cmp_opaque;
1018         prod = rxr->rx_prod;
1019         cons_rx_buf = &rxr->rx_buf_ring[cons];
1020         prod_rx_buf = &rxr->rx_buf_ring[prod];
1021         tpa_info = &rxr->rx_tpa[agg_id];
1022
1023         if (unlikely(cons != rxr->rx_next_cons)) {
1024                 bnxt_sched_reset(bp, rxr);
1025                 return;
1026         }
1027
1028         prod_rx_buf->data = tpa_info->data;
1029         prod_rx_buf->data_ptr = tpa_info->data_ptr;
1030
1031         mapping = tpa_info->mapping;
1032         prod_rx_buf->mapping = mapping;
1033
1034         prod_bd = &rxr->rx_desc_ring[RX_RING(prod)][RX_IDX(prod)];
1035
1036         prod_bd->rx_bd_haddr = cpu_to_le64(mapping);
1037
1038         tpa_info->data = cons_rx_buf->data;
1039         tpa_info->data_ptr = cons_rx_buf->data_ptr;
1040         cons_rx_buf->data = NULL;
1041         tpa_info->mapping = cons_rx_buf->mapping;
1042
1043         tpa_info->len =
1044                 le32_to_cpu(tpa_start->rx_tpa_start_cmp_len_flags_type) >>
1045                                 RX_TPA_START_CMP_LEN_SHIFT;
1046         if (likely(TPA_START_HASH_VALID(tpa_start))) {
1047                 u32 hash_type = TPA_START_HASH_TYPE(tpa_start);
1048
1049                 tpa_info->hash_type = PKT_HASH_TYPE_L4;
1050                 tpa_info->gso_type = SKB_GSO_TCPV4;
1051                 /* RSS profiles 1 and 3 with extract code 0 for inner 4-tuple */
1052                 if (hash_type == 3)
1053                         tpa_info->gso_type = SKB_GSO_TCPV6;
1054                 tpa_info->rss_hash =
1055                         le32_to_cpu(tpa_start->rx_tpa_start_cmp_rss_hash);
1056         } else {
1057                 tpa_info->hash_type = PKT_HASH_TYPE_NONE;
1058                 tpa_info->gso_type = 0;
1059                 if (netif_msg_rx_err(bp))
1060                         netdev_warn(bp->dev, "TPA packet without valid hash\n");
1061         }
1062         tpa_info->flags2 = le32_to_cpu(tpa_start1->rx_tpa_start_cmp_flags2);
1063         tpa_info->metadata = le32_to_cpu(tpa_start1->rx_tpa_start_cmp_metadata);
1064         tpa_info->hdr_info = le32_to_cpu(tpa_start1->rx_tpa_start_cmp_hdr_info);
1065
1066         rxr->rx_prod = NEXT_RX(prod);
1067         cons = NEXT_RX(cons);
1068         rxr->rx_next_cons = NEXT_RX(cons);
1069         cons_rx_buf = &rxr->rx_buf_ring[cons];
1070
1071         bnxt_reuse_rx_data(rxr, cons, cons_rx_buf->data);
1072         rxr->rx_prod = NEXT_RX(rxr->rx_prod);
1073         cons_rx_buf->data = NULL;
1074 }
1075
1076 static void bnxt_abort_tpa(struct bnxt *bp, struct bnxt_napi *bnapi,
1077                            u16 cp_cons, u32 agg_bufs)
1078 {
1079         if (agg_bufs)
1080                 bnxt_reuse_rx_agg_bufs(bnapi, cp_cons, agg_bufs);
1081 }
1082
1083 static struct sk_buff *bnxt_gro_func_5731x(struct bnxt_tpa_info *tpa_info,
1084                                            int payload_off, int tcp_ts,
1085                                            struct sk_buff *skb)
1086 {
1087 #ifdef CONFIG_INET
1088         struct tcphdr *th;
1089         int len, nw_off;
1090         u16 outer_ip_off, inner_ip_off, inner_mac_off;
1091         u32 hdr_info = tpa_info->hdr_info;
1092         bool loopback = false;
1093
1094         inner_ip_off = BNXT_TPA_INNER_L3_OFF(hdr_info);
1095         inner_mac_off = BNXT_TPA_INNER_L2_OFF(hdr_info);
1096         outer_ip_off = BNXT_TPA_OUTER_L3_OFF(hdr_info);
1097
1098         /* If the packet is an internal loopback packet, the offsets will
1099          * have an extra 4 bytes.
1100          */
1101         if (inner_mac_off == 4) {
1102                 loopback = true;
1103         } else if (inner_mac_off > 4) {
1104                 __be16 proto = *((__be16 *)(skb->data + inner_ip_off -
1105                                             ETH_HLEN - 2));
1106
1107                 /* We only support inner iPv4/ipv6.  If we don't see the
1108                  * correct protocol ID, it must be a loopback packet where
1109                  * the offsets are off by 4.
1110                  */
1111                 if (proto != htons(ETH_P_IP) && proto != htons(ETH_P_IPV6))
1112                         loopback = true;
1113         }
1114         if (loopback) {
1115                 /* internal loopback packet, subtract all offsets by 4 */
1116                 inner_ip_off -= 4;
1117                 inner_mac_off -= 4;
1118                 outer_ip_off -= 4;
1119         }
1120
1121         nw_off = inner_ip_off - ETH_HLEN;
1122         skb_set_network_header(skb, nw_off);
1123         if (tpa_info->flags2 & RX_TPA_START_CMP_FLAGS2_IP_TYPE) {
1124                 struct ipv6hdr *iph = ipv6_hdr(skb);
1125
1126                 skb_set_transport_header(skb, nw_off + sizeof(struct ipv6hdr));
1127                 len = skb->len - skb_transport_offset(skb);
1128                 th = tcp_hdr(skb);
1129                 th->check = ~tcp_v6_check(len, &iph->saddr, &iph->daddr, 0);
1130         } else {
1131                 struct iphdr *iph = ip_hdr(skb);
1132
1133                 skb_set_transport_header(skb, nw_off + sizeof(struct iphdr));
1134                 len = skb->len - skb_transport_offset(skb);
1135                 th = tcp_hdr(skb);
1136                 th->check = ~tcp_v4_check(len, iph->saddr, iph->daddr, 0);
1137         }
1138
1139         if (inner_mac_off) { /* tunnel */
1140                 struct udphdr *uh = NULL;
1141                 __be16 proto = *((__be16 *)(skb->data + outer_ip_off -
1142                                             ETH_HLEN - 2));
1143
1144                 if (proto == htons(ETH_P_IP)) {
1145                         struct iphdr *iph = (struct iphdr *)skb->data;
1146
1147                         if (iph->protocol == IPPROTO_UDP)
1148                                 uh = (struct udphdr *)(iph + 1);
1149                 } else {
1150                         struct ipv6hdr *iph = (struct ipv6hdr *)skb->data;
1151
1152                         if (iph->nexthdr == IPPROTO_UDP)
1153                                 uh = (struct udphdr *)(iph + 1);
1154                 }
1155                 if (uh) {
1156                         if (uh->check)
1157                                 skb_shinfo(skb)->gso_type |=
1158                                         SKB_GSO_UDP_TUNNEL_CSUM;
1159                         else
1160                                 skb_shinfo(skb)->gso_type |= SKB_GSO_UDP_TUNNEL;
1161                 }
1162         }
1163 #endif
1164         return skb;
1165 }
1166
1167 #define BNXT_IPV4_HDR_SIZE      (sizeof(struct iphdr) + sizeof(struct tcphdr))
1168 #define BNXT_IPV6_HDR_SIZE      (sizeof(struct ipv6hdr) + sizeof(struct tcphdr))
1169
1170 static struct sk_buff *bnxt_gro_func_5730x(struct bnxt_tpa_info *tpa_info,
1171                                            int payload_off, int tcp_ts,
1172                                            struct sk_buff *skb)
1173 {
1174 #ifdef CONFIG_INET
1175         struct tcphdr *th;
1176         int len, nw_off, tcp_opt_len = 0;
1177
1178         if (tcp_ts)
1179                 tcp_opt_len = 12;
1180
1181         if (tpa_info->gso_type == SKB_GSO_TCPV4) {
1182                 struct iphdr *iph;
1183
1184                 nw_off = payload_off - BNXT_IPV4_HDR_SIZE - tcp_opt_len -
1185                          ETH_HLEN;
1186                 skb_set_network_header(skb, nw_off);
1187                 iph = ip_hdr(skb);
1188                 skb_set_transport_header(skb, nw_off + sizeof(struct iphdr));
1189                 len = skb->len - skb_transport_offset(skb);
1190                 th = tcp_hdr(skb);
1191                 th->check = ~tcp_v4_check(len, iph->saddr, iph->daddr, 0);
1192         } else if (tpa_info->gso_type == SKB_GSO_TCPV6) {
1193                 struct ipv6hdr *iph;
1194
1195                 nw_off = payload_off - BNXT_IPV6_HDR_SIZE - tcp_opt_len -
1196                          ETH_HLEN;
1197                 skb_set_network_header(skb, nw_off);
1198                 iph = ipv6_hdr(skb);
1199                 skb_set_transport_header(skb, nw_off + sizeof(struct ipv6hdr));
1200                 len = skb->len - skb_transport_offset(skb);
1201                 th = tcp_hdr(skb);
1202                 th->check = ~tcp_v6_check(len, &iph->saddr, &iph->daddr, 0);
1203         } else {
1204                 dev_kfree_skb_any(skb);
1205                 return NULL;
1206         }
1207
1208         if (nw_off) { /* tunnel */
1209                 struct udphdr *uh = NULL;
1210
1211                 if (skb->protocol == htons(ETH_P_IP)) {
1212                         struct iphdr *iph = (struct iphdr *)skb->data;
1213
1214                         if (iph->protocol == IPPROTO_UDP)
1215                                 uh = (struct udphdr *)(iph + 1);
1216                 } else {
1217                         struct ipv6hdr *iph = (struct ipv6hdr *)skb->data;
1218
1219                         if (iph->nexthdr == IPPROTO_UDP)
1220                                 uh = (struct udphdr *)(iph + 1);
1221                 }
1222                 if (uh) {
1223                         if (uh->check)
1224                                 skb_shinfo(skb)->gso_type |=
1225                                         SKB_GSO_UDP_TUNNEL_CSUM;
1226                         else
1227                                 skb_shinfo(skb)->gso_type |= SKB_GSO_UDP_TUNNEL;
1228                 }
1229         }
1230 #endif
1231         return skb;
1232 }
1233
1234 static inline struct sk_buff *bnxt_gro_skb(struct bnxt *bp,
1235                                            struct bnxt_tpa_info *tpa_info,
1236                                            struct rx_tpa_end_cmp *tpa_end,
1237                                            struct rx_tpa_end_cmp_ext *tpa_end1,
1238                                            struct sk_buff *skb)
1239 {
1240 #ifdef CONFIG_INET
1241         int payload_off;
1242         u16 segs;
1243
1244         segs = TPA_END_TPA_SEGS(tpa_end);
1245         if (segs == 1)
1246                 return skb;
1247
1248         NAPI_GRO_CB(skb)->count = segs;
1249         skb_shinfo(skb)->gso_size =
1250                 le32_to_cpu(tpa_end1->rx_tpa_end_cmp_seg_len);
1251         skb_shinfo(skb)->gso_type = tpa_info->gso_type;
1252         payload_off = (le32_to_cpu(tpa_end->rx_tpa_end_cmp_misc_v1) &
1253                        RX_TPA_END_CMP_PAYLOAD_OFFSET) >>
1254                       RX_TPA_END_CMP_PAYLOAD_OFFSET_SHIFT;
1255         skb = bp->gro_func(tpa_info, payload_off, TPA_END_GRO_TS(tpa_end), skb);
1256         if (likely(skb))
1257                 tcp_gro_complete(skb);
1258 #endif
1259         return skb;
1260 }
1261
1262 static inline struct sk_buff *bnxt_tpa_end(struct bnxt *bp,
1263                                            struct bnxt_napi *bnapi,
1264                                            u32 *raw_cons,
1265                                            struct rx_tpa_end_cmp *tpa_end,
1266                                            struct rx_tpa_end_cmp_ext *tpa_end1,
1267                                            u8 *event)
1268 {
1269         struct bnxt_cp_ring_info *cpr = &bnapi->cp_ring;
1270         struct bnxt_rx_ring_info *rxr = bnapi->rx_ring;
1271         u8 agg_id = TPA_END_AGG_ID(tpa_end);
1272         u8 *data_ptr, agg_bufs;
1273         u16 cp_cons = RING_CMP(*raw_cons);
1274         unsigned int len;
1275         struct bnxt_tpa_info *tpa_info;
1276         dma_addr_t mapping;
1277         struct sk_buff *skb;
1278         void *data;
1279
1280         if (unlikely(bnapi->in_reset)) {
1281                 int rc = bnxt_discard_rx(bp, bnapi, raw_cons, tpa_end);
1282
1283                 if (rc < 0)
1284                         return ERR_PTR(-EBUSY);
1285                 return NULL;
1286         }
1287
1288         tpa_info = &rxr->rx_tpa[agg_id];
1289         data = tpa_info->data;
1290         data_ptr = tpa_info->data_ptr;
1291         prefetch(data_ptr);
1292         len = tpa_info->len;
1293         mapping = tpa_info->mapping;
1294
1295         agg_bufs = (le32_to_cpu(tpa_end->rx_tpa_end_cmp_misc_v1) &
1296                     RX_TPA_END_CMP_AGG_BUFS) >> RX_TPA_END_CMP_AGG_BUFS_SHIFT;
1297
1298         if (agg_bufs) {
1299                 if (!bnxt_agg_bufs_valid(bp, cpr, agg_bufs, raw_cons))
1300                         return ERR_PTR(-EBUSY);
1301
1302                 *event |= BNXT_AGG_EVENT;
1303                 cp_cons = NEXT_CMP(cp_cons);
1304         }
1305
1306         if (unlikely(agg_bufs > MAX_SKB_FRAGS)) {
1307                 bnxt_abort_tpa(bp, bnapi, cp_cons, agg_bufs);
1308                 netdev_warn(bp->dev, "TPA frags %d exceeded MAX_SKB_FRAGS %d\n",
1309                             agg_bufs, (int)MAX_SKB_FRAGS);
1310                 return NULL;
1311         }
1312
1313         if (len <= bp->rx_copy_thresh) {
1314                 skb = bnxt_copy_skb(bnapi, data_ptr, len, mapping);
1315                 if (!skb) {
1316                         bnxt_abort_tpa(bp, bnapi, cp_cons, agg_bufs);
1317                         return NULL;
1318                 }
1319         } else {
1320                 u8 *new_data;
1321                 dma_addr_t new_mapping;
1322
1323                 new_data = __bnxt_alloc_rx_data(bp, &new_mapping, GFP_ATOMIC);
1324                 if (!new_data) {
1325                         bnxt_abort_tpa(bp, bnapi, cp_cons, agg_bufs);
1326                         return NULL;
1327                 }
1328
1329                 tpa_info->data = new_data;
1330                 tpa_info->data_ptr = new_data + bp->rx_offset;
1331                 tpa_info->mapping = new_mapping;
1332
1333                 skb = build_skb(data, 0);
1334                 dma_unmap_single(&bp->pdev->dev, mapping, bp->rx_buf_use_size,
1335                                  bp->rx_dir);
1336
1337                 if (!skb) {
1338                         kfree(data);
1339                         bnxt_abort_tpa(bp, bnapi, cp_cons, agg_bufs);
1340                         return NULL;
1341                 }
1342                 skb_reserve(skb, bp->rx_offset);
1343                 skb_put(skb, len);
1344         }
1345
1346         if (agg_bufs) {
1347                 skb = bnxt_rx_pages(bp, bnapi, skb, cp_cons, agg_bufs);
1348                 if (!skb) {
1349                         /* Page reuse already handled by bnxt_rx_pages(). */
1350                         return NULL;
1351                 }
1352         }
1353         skb->protocol = eth_type_trans(skb, bp->dev);
1354
1355         if (tpa_info->hash_type != PKT_HASH_TYPE_NONE)
1356                 skb_set_hash(skb, tpa_info->rss_hash, tpa_info->hash_type);
1357
1358         if ((tpa_info->flags2 & RX_CMP_FLAGS2_META_FORMAT_VLAN) &&
1359             (skb->dev->features & NETIF_F_HW_VLAN_CTAG_RX)) {
1360                 u16 vlan_proto = tpa_info->metadata >>
1361                         RX_CMP_FLAGS2_METADATA_TPID_SFT;
1362                 u16 vtag = tpa_info->metadata & RX_CMP_FLAGS2_METADATA_VID_MASK;
1363
1364                 __vlan_hwaccel_put_tag(skb, htons(vlan_proto), vtag);
1365         }
1366
1367         skb_checksum_none_assert(skb);
1368         if (likely(tpa_info->flags2 & RX_TPA_START_CMP_FLAGS2_L4_CS_CALC)) {
1369                 skb->ip_summed = CHECKSUM_UNNECESSARY;
1370                 skb->csum_level =
1371                         (tpa_info->flags2 & RX_CMP_FLAGS2_T_L4_CS_CALC) >> 3;
1372         }
1373
1374         if (TPA_END_GRO(tpa_end))
1375                 skb = bnxt_gro_skb(bp, tpa_info, tpa_end, tpa_end1, skb);
1376
1377         return skb;
1378 }
1379
1380 /* returns the following:
1381  * 1       - 1 packet successfully received
1382  * 0       - successful TPA_START, packet not completed yet
1383  * -EBUSY  - completion ring does not have all the agg buffers yet
1384  * -ENOMEM - packet aborted due to out of memory
1385  * -EIO    - packet aborted due to hw error indicated in BD
1386  */
1387 static int bnxt_rx_pkt(struct bnxt *bp, struct bnxt_napi *bnapi, u32 *raw_cons,
1388                        u8 *event)
1389 {
1390         struct bnxt_cp_ring_info *cpr = &bnapi->cp_ring;
1391         struct bnxt_rx_ring_info *rxr = bnapi->rx_ring;
1392         struct net_device *dev = bp->dev;
1393         struct rx_cmp *rxcmp;
1394         struct rx_cmp_ext *rxcmp1;
1395         u32 tmp_raw_cons = *raw_cons;
1396         u16 cons, prod, cp_cons = RING_CMP(tmp_raw_cons);
1397         struct bnxt_sw_rx_bd *rx_buf;
1398         unsigned int len;
1399         u8 *data_ptr, agg_bufs, cmp_type;
1400         dma_addr_t dma_addr;
1401         struct sk_buff *skb;
1402         void *data;
1403         int rc = 0;
1404         u32 misc;
1405
1406         rxcmp = (struct rx_cmp *)
1407                         &cpr->cp_desc_ring[CP_RING(cp_cons)][CP_IDX(cp_cons)];
1408
1409         tmp_raw_cons = NEXT_RAW_CMP(tmp_raw_cons);
1410         cp_cons = RING_CMP(tmp_raw_cons);
1411         rxcmp1 = (struct rx_cmp_ext *)
1412                         &cpr->cp_desc_ring[CP_RING(cp_cons)][CP_IDX(cp_cons)];
1413
1414         if (!RX_CMP_VALID(rxcmp1, tmp_raw_cons))
1415                 return -EBUSY;
1416
1417         cmp_type = RX_CMP_TYPE(rxcmp);
1418
1419         prod = rxr->rx_prod;
1420
1421         if (cmp_type == CMP_TYPE_RX_L2_TPA_START_CMP) {
1422                 bnxt_tpa_start(bp, rxr, (struct rx_tpa_start_cmp *)rxcmp,
1423                                (struct rx_tpa_start_cmp_ext *)rxcmp1);
1424
1425                 *event |= BNXT_RX_EVENT;
1426                 goto next_rx_no_prod;
1427
1428         } else if (cmp_type == CMP_TYPE_RX_L2_TPA_END_CMP) {
1429                 skb = bnxt_tpa_end(bp, bnapi, &tmp_raw_cons,
1430                                    (struct rx_tpa_end_cmp *)rxcmp,
1431                                    (struct rx_tpa_end_cmp_ext *)rxcmp1, event);
1432
1433                 if (unlikely(IS_ERR(skb)))
1434                         return -EBUSY;
1435
1436                 rc = -ENOMEM;
1437                 if (likely(skb)) {
1438                         skb_record_rx_queue(skb, bnapi->index);
1439                         napi_gro_receive(&bnapi->napi, skb);
1440                         rc = 1;
1441                 }
1442                 *event |= BNXT_RX_EVENT;
1443                 goto next_rx_no_prod;
1444         }
1445
1446         cons = rxcmp->rx_cmp_opaque;
1447         rx_buf = &rxr->rx_buf_ring[cons];
1448         data = rx_buf->data;
1449         data_ptr = rx_buf->data_ptr;
1450         if (unlikely(cons != rxr->rx_next_cons)) {
1451                 int rc1 = bnxt_discard_rx(bp, bnapi, raw_cons, rxcmp);
1452
1453                 bnxt_sched_reset(bp, rxr);
1454                 return rc1;
1455         }
1456         prefetch(data_ptr);
1457
1458         misc = le32_to_cpu(rxcmp->rx_cmp_misc_v1);
1459         agg_bufs = (misc & RX_CMP_AGG_BUFS) >> RX_CMP_AGG_BUFS_SHIFT;
1460
1461         if (agg_bufs) {
1462                 if (!bnxt_agg_bufs_valid(bp, cpr, agg_bufs, &tmp_raw_cons))
1463                         return -EBUSY;
1464
1465                 cp_cons = NEXT_CMP(cp_cons);
1466                 *event |= BNXT_AGG_EVENT;
1467         }
1468         *event |= BNXT_RX_EVENT;
1469
1470         rx_buf->data = NULL;
1471         if (rxcmp1->rx_cmp_cfa_code_errors_v2 & RX_CMP_L2_ERRORS) {
1472                 bnxt_reuse_rx_data(rxr, cons, data);
1473                 if (agg_bufs)
1474                         bnxt_reuse_rx_agg_bufs(bnapi, cp_cons, agg_bufs);
1475
1476                 rc = -EIO;
1477                 goto next_rx;
1478         }
1479
1480         len = le32_to_cpu(rxcmp->rx_cmp_len_flags_type) >> RX_CMP_LEN_SHIFT;
1481         dma_addr = rx_buf->mapping;
1482
1483         if (len <= bp->rx_copy_thresh) {
1484                 skb = bnxt_copy_skb(bnapi, data_ptr, len, dma_addr);
1485                 bnxt_reuse_rx_data(rxr, cons, data);
1486                 if (!skb) {
1487                         rc = -ENOMEM;
1488                         goto next_rx;
1489                 }
1490         } else {
1491                 u32 payload;
1492
1493                 payload = misc & RX_CMP_PAYLOAD_OFFSET;
1494                 skb = bp->rx_skb_func(bp, rxr, cons, data, data_ptr, dma_addr,
1495                                       payload | len);
1496                 if (!skb) {
1497                         rc = -ENOMEM;
1498                         goto next_rx;
1499                 }
1500         }
1501
1502         if (agg_bufs) {
1503                 skb = bnxt_rx_pages(bp, bnapi, skb, cp_cons, agg_bufs);
1504                 if (!skb) {
1505                         rc = -ENOMEM;
1506                         goto next_rx;
1507                 }
1508         }
1509
1510         if (RX_CMP_HASH_VALID(rxcmp)) {
1511                 u32 hash_type = RX_CMP_HASH_TYPE(rxcmp);
1512                 enum pkt_hash_types type = PKT_HASH_TYPE_L4;
1513
1514                 /* RSS profiles 1 and 3 with extract code 0 for inner 4-tuple */
1515                 if (hash_type != 1 && hash_type != 3)
1516                         type = PKT_HASH_TYPE_L3;
1517                 skb_set_hash(skb, le32_to_cpu(rxcmp->rx_cmp_rss_hash), type);
1518         }
1519
1520         skb->protocol = eth_type_trans(skb, dev);
1521
1522         if ((rxcmp1->rx_cmp_flags2 &
1523              cpu_to_le32(RX_CMP_FLAGS2_META_FORMAT_VLAN)) &&
1524             (skb->dev->features & NETIF_F_HW_VLAN_CTAG_RX)) {
1525                 u32 meta_data = le32_to_cpu(rxcmp1->rx_cmp_meta_data);
1526                 u16 vtag = meta_data & RX_CMP_FLAGS2_METADATA_VID_MASK;
1527                 u16 vlan_proto = meta_data >> RX_CMP_FLAGS2_METADATA_TPID_SFT;
1528
1529                 __vlan_hwaccel_put_tag(skb, htons(vlan_proto), vtag);
1530         }
1531
1532         skb_checksum_none_assert(skb);
1533         if (RX_CMP_L4_CS_OK(rxcmp1)) {
1534                 if (dev->features & NETIF_F_RXCSUM) {
1535                         skb->ip_summed = CHECKSUM_UNNECESSARY;
1536                         skb->csum_level = RX_CMP_ENCAP(rxcmp1);
1537                 }
1538         } else {
1539                 if (rxcmp1->rx_cmp_cfa_code_errors_v2 & RX_CMP_L4_CS_ERR_BITS) {
1540                         if (dev->features & NETIF_F_RXCSUM)
1541                                 cpr->rx_l4_csum_errors++;
1542                 }
1543         }
1544
1545         skb_record_rx_queue(skb, bnapi->index);
1546         napi_gro_receive(&bnapi->napi, skb);
1547         rc = 1;
1548
1549 next_rx:
1550         rxr->rx_prod = NEXT_RX(prod);
1551         rxr->rx_next_cons = NEXT_RX(cons);
1552
1553 next_rx_no_prod:
1554         *raw_cons = tmp_raw_cons;
1555
1556         return rc;
1557 }
1558
1559 #define BNXT_GET_EVENT_PORT(data)       \
1560         ((data) &                       \
1561          ASYNC_EVENT_CMPL_PORT_CONN_NOT_ALLOWED_EVENT_DATA1_PORT_ID_MASK)
1562
1563 static int bnxt_async_event_process(struct bnxt *bp,
1564                                     struct hwrm_async_event_cmpl *cmpl)
1565 {
1566         u16 event_id = le16_to_cpu(cmpl->event_id);
1567
1568         /* TODO CHIMP_FW: Define event id's for link change, error etc */
1569         switch (event_id) {
1570         case ASYNC_EVENT_CMPL_EVENT_ID_LINK_SPEED_CFG_CHANGE: {
1571                 u32 data1 = le32_to_cpu(cmpl->event_data1);
1572                 struct bnxt_link_info *link_info = &bp->link_info;
1573
1574                 if (BNXT_VF(bp))
1575                         goto async_event_process_exit;
1576                 if (data1 & 0x20000) {
1577                         u16 fw_speed = link_info->force_link_speed;
1578                         u32 speed = bnxt_fw_to_ethtool_speed(fw_speed);
1579
1580                         netdev_warn(bp->dev, "Link speed %d no longer supported\n",
1581                                     speed);
1582                 }
1583                 set_bit(BNXT_LINK_SPEED_CHNG_SP_EVENT, &bp->sp_event);
1584                 /* fall thru */
1585         }
1586         case ASYNC_EVENT_CMPL_EVENT_ID_LINK_STATUS_CHANGE:
1587                 set_bit(BNXT_LINK_CHNG_SP_EVENT, &bp->sp_event);
1588                 break;
1589         case ASYNC_EVENT_CMPL_EVENT_ID_PF_DRVR_UNLOAD:
1590                 set_bit(BNXT_HWRM_PF_UNLOAD_SP_EVENT, &bp->sp_event);
1591                 break;
1592         case ASYNC_EVENT_CMPL_EVENT_ID_PORT_CONN_NOT_ALLOWED: {
1593                 u32 data1 = le32_to_cpu(cmpl->event_data1);
1594                 u16 port_id = BNXT_GET_EVENT_PORT(data1);
1595
1596                 if (BNXT_VF(bp))
1597                         break;
1598
1599                 if (bp->pf.port_id != port_id)
1600                         break;
1601
1602                 set_bit(BNXT_HWRM_PORT_MODULE_SP_EVENT, &bp->sp_event);
1603                 break;
1604         }
1605         case ASYNC_EVENT_CMPL_EVENT_ID_VF_CFG_CHANGE:
1606                 if (BNXT_PF(bp))
1607                         goto async_event_process_exit;
1608                 set_bit(BNXT_RESET_TASK_SILENT_SP_EVENT, &bp->sp_event);
1609                 break;
1610         default:
1611                 goto async_event_process_exit;
1612         }
1613         schedule_work(&bp->sp_task);
1614 async_event_process_exit:
1615         bnxt_ulp_async_events(bp, cmpl);
1616         return 0;
1617 }
1618
1619 static int bnxt_hwrm_handler(struct bnxt *bp, struct tx_cmp *txcmp)
1620 {
1621         u16 cmpl_type = TX_CMP_TYPE(txcmp), vf_id, seq_id;
1622         struct hwrm_cmpl *h_cmpl = (struct hwrm_cmpl *)txcmp;
1623         struct hwrm_fwd_req_cmpl *fwd_req_cmpl =
1624                                 (struct hwrm_fwd_req_cmpl *)txcmp;
1625
1626         switch (cmpl_type) {
1627         case CMPL_BASE_TYPE_HWRM_DONE:
1628                 seq_id = le16_to_cpu(h_cmpl->sequence_id);
1629                 if (seq_id == bp->hwrm_intr_seq_id)
1630                         bp->hwrm_intr_seq_id = HWRM_SEQ_ID_INVALID;
1631                 else
1632                         netdev_err(bp->dev, "Invalid hwrm seq id %d\n", seq_id);
1633                 break;
1634
1635         case CMPL_BASE_TYPE_HWRM_FWD_REQ:
1636                 vf_id = le16_to_cpu(fwd_req_cmpl->source_id);
1637
1638                 if ((vf_id < bp->pf.first_vf_id) ||
1639                     (vf_id >= bp->pf.first_vf_id + bp->pf.active_vfs)) {
1640                         netdev_err(bp->dev, "Msg contains invalid VF id %x\n",
1641                                    vf_id);
1642                         return -EINVAL;
1643                 }
1644
1645                 set_bit(vf_id - bp->pf.first_vf_id, bp->pf.vf_event_bmap);
1646                 set_bit(BNXT_HWRM_EXEC_FWD_REQ_SP_EVENT, &bp->sp_event);
1647                 schedule_work(&bp->sp_task);
1648                 break;
1649
1650         case CMPL_BASE_TYPE_HWRM_ASYNC_EVENT:
1651                 bnxt_async_event_process(bp,
1652                                          (struct hwrm_async_event_cmpl *)txcmp);
1653
1654         default:
1655                 break;
1656         }
1657
1658         return 0;
1659 }
1660
1661 static irqreturn_t bnxt_msix(int irq, void *dev_instance)
1662 {
1663         struct bnxt_napi *bnapi = dev_instance;
1664         struct bnxt *bp = bnapi->bp;
1665         struct bnxt_cp_ring_info *cpr = &bnapi->cp_ring;
1666         u32 cons = RING_CMP(cpr->cp_raw_cons);
1667
1668         prefetch(&cpr->cp_desc_ring[CP_RING(cons)][CP_IDX(cons)]);
1669         napi_schedule(&bnapi->napi);
1670         return IRQ_HANDLED;
1671 }
1672
1673 static inline int bnxt_has_work(struct bnxt *bp, struct bnxt_cp_ring_info *cpr)
1674 {
1675         u32 raw_cons = cpr->cp_raw_cons;
1676         u16 cons = RING_CMP(raw_cons);
1677         struct tx_cmp *txcmp;
1678
1679         txcmp = &cpr->cp_desc_ring[CP_RING(cons)][CP_IDX(cons)];
1680
1681         return TX_CMP_VALID(txcmp, raw_cons);
1682 }
1683
1684 static irqreturn_t bnxt_inta(int irq, void *dev_instance)
1685 {
1686         struct bnxt_napi *bnapi = dev_instance;
1687         struct bnxt *bp = bnapi->bp;
1688         struct bnxt_cp_ring_info *cpr = &bnapi->cp_ring;
1689         u32 cons = RING_CMP(cpr->cp_raw_cons);
1690         u32 int_status;
1691
1692         prefetch(&cpr->cp_desc_ring[CP_RING(cons)][CP_IDX(cons)]);
1693
1694         if (!bnxt_has_work(bp, cpr)) {
1695                 int_status = readl(bp->bar0 + BNXT_CAG_REG_LEGACY_INT_STATUS);
1696                 /* return if erroneous interrupt */
1697                 if (!(int_status & (0x10000 << cpr->cp_ring_struct.fw_ring_id)))
1698                         return IRQ_NONE;
1699         }
1700
1701         /* disable ring IRQ */
1702         BNXT_CP_DB_IRQ_DIS(cpr->cp_doorbell);
1703
1704         /* Return here if interrupt is shared and is disabled. */
1705         if (unlikely(atomic_read(&bp->intr_sem) != 0))
1706                 return IRQ_HANDLED;
1707
1708         napi_schedule(&bnapi->napi);
1709         return IRQ_HANDLED;
1710 }
1711
1712 static int bnxt_poll_work(struct bnxt *bp, struct bnxt_napi *bnapi, int budget)
1713 {
1714         struct bnxt_cp_ring_info *cpr = &bnapi->cp_ring;
1715         u32 raw_cons = cpr->cp_raw_cons;
1716         u32 cons;
1717         int tx_pkts = 0;
1718         int rx_pkts = 0;
1719         u8 event = 0;
1720         struct tx_cmp *txcmp;
1721
1722         while (1) {
1723                 int rc;
1724
1725                 cons = RING_CMP(raw_cons);
1726                 txcmp = &cpr->cp_desc_ring[CP_RING(cons)][CP_IDX(cons)];
1727
1728                 if (!TX_CMP_VALID(txcmp, raw_cons))
1729                         break;
1730
1731                 /* The valid test of the entry must be done first before
1732                  * reading any further.
1733                  */
1734                 dma_rmb();
1735                 if (TX_CMP_TYPE(txcmp) == CMP_TYPE_TX_L2_CMP) {
1736                         tx_pkts++;
1737                         /* return full budget so NAPI will complete. */
1738                         if (unlikely(tx_pkts > bp->tx_wake_thresh))
1739                                 rx_pkts = budget;
1740                 } else if ((TX_CMP_TYPE(txcmp) & 0x30) == 0x10) {
1741                         rc = bnxt_rx_pkt(bp, bnapi, &raw_cons, &event);
1742                         if (likely(rc >= 0))
1743                                 rx_pkts += rc;
1744                         else if (rc == -EBUSY)  /* partial completion */
1745                                 break;
1746                 } else if (unlikely((TX_CMP_TYPE(txcmp) ==
1747                                      CMPL_BASE_TYPE_HWRM_DONE) ||
1748                                     (TX_CMP_TYPE(txcmp) ==
1749                                      CMPL_BASE_TYPE_HWRM_FWD_REQ) ||
1750                                     (TX_CMP_TYPE(txcmp) ==
1751                                      CMPL_BASE_TYPE_HWRM_ASYNC_EVENT))) {
1752                         bnxt_hwrm_handler(bp, txcmp);
1753                 }
1754                 raw_cons = NEXT_RAW_CMP(raw_cons);
1755
1756                 if (rx_pkts == budget)
1757                         break;
1758         }
1759
1760         cpr->cp_raw_cons = raw_cons;
1761         /* ACK completion ring before freeing tx ring and producing new
1762          * buffers in rx/agg rings to prevent overflowing the completion
1763          * ring.
1764          */
1765         BNXT_CP_DB(cpr->cp_doorbell, cpr->cp_raw_cons);
1766
1767         if (tx_pkts)
1768                 bnxt_tx_int(bp, bnapi, tx_pkts);
1769
1770         if (event & BNXT_RX_EVENT) {
1771                 struct bnxt_rx_ring_info *rxr = bnapi->rx_ring;
1772
1773                 writel(DB_KEY_RX | rxr->rx_prod, rxr->rx_doorbell);
1774                 writel(DB_KEY_RX | rxr->rx_prod, rxr->rx_doorbell);
1775                 if (event & BNXT_AGG_EVENT) {
1776                         writel(DB_KEY_RX | rxr->rx_agg_prod,
1777                                rxr->rx_agg_doorbell);
1778                         writel(DB_KEY_RX | rxr->rx_agg_prod,
1779                                rxr->rx_agg_doorbell);
1780                 }
1781         }
1782         return rx_pkts;
1783 }
1784
1785 static int bnxt_poll_nitroa0(struct napi_struct *napi, int budget)
1786 {
1787         struct bnxt_napi *bnapi = container_of(napi, struct bnxt_napi, napi);
1788         struct bnxt *bp = bnapi->bp;
1789         struct bnxt_cp_ring_info *cpr = &bnapi->cp_ring;
1790         struct bnxt_rx_ring_info *rxr = bnapi->rx_ring;
1791         struct tx_cmp *txcmp;
1792         struct rx_cmp_ext *rxcmp1;
1793         u32 cp_cons, tmp_raw_cons;
1794         u32 raw_cons = cpr->cp_raw_cons;
1795         u32 rx_pkts = 0;
1796         u8 event = 0;
1797
1798         while (1) {
1799                 int rc;
1800
1801                 cp_cons = RING_CMP(raw_cons);
1802                 txcmp = &cpr->cp_desc_ring[CP_RING(cp_cons)][CP_IDX(cp_cons)];
1803
1804                 if (!TX_CMP_VALID(txcmp, raw_cons))
1805                         break;
1806
1807                 if ((TX_CMP_TYPE(txcmp) & 0x30) == 0x10) {
1808                         tmp_raw_cons = NEXT_RAW_CMP(raw_cons);
1809                         cp_cons = RING_CMP(tmp_raw_cons);
1810                         rxcmp1 = (struct rx_cmp_ext *)
1811                           &cpr->cp_desc_ring[CP_RING(cp_cons)][CP_IDX(cp_cons)];
1812
1813                         if (!RX_CMP_VALID(rxcmp1, tmp_raw_cons))
1814                                 break;
1815
1816                         /* force an error to recycle the buffer */
1817                         rxcmp1->rx_cmp_cfa_code_errors_v2 |=
1818                                 cpu_to_le32(RX_CMPL_ERRORS_CRC_ERROR);
1819
1820                         rc = bnxt_rx_pkt(bp, bnapi, &raw_cons, &event);
1821                         if (likely(rc == -EIO))
1822                                 rx_pkts++;
1823                         else if (rc == -EBUSY)  /* partial completion */
1824                                 break;
1825                 } else if (unlikely(TX_CMP_TYPE(txcmp) ==
1826                                     CMPL_BASE_TYPE_HWRM_DONE)) {
1827                         bnxt_hwrm_handler(bp, txcmp);
1828                 } else {
1829                         netdev_err(bp->dev,
1830                                    "Invalid completion received on special ring\n");
1831                 }
1832                 raw_cons = NEXT_RAW_CMP(raw_cons);
1833
1834                 if (rx_pkts == budget)
1835                         break;
1836         }
1837
1838         cpr->cp_raw_cons = raw_cons;
1839         BNXT_CP_DB(cpr->cp_doorbell, cpr->cp_raw_cons);
1840         writel(DB_KEY_RX | rxr->rx_prod, rxr->rx_doorbell);
1841         writel(DB_KEY_RX | rxr->rx_prod, rxr->rx_doorbell);
1842
1843         if (event & BNXT_AGG_EVENT) {
1844                 writel(DB_KEY_RX | rxr->rx_agg_prod, rxr->rx_agg_doorbell);
1845                 writel(DB_KEY_RX | rxr->rx_agg_prod, rxr->rx_agg_doorbell);
1846         }
1847
1848         if (!bnxt_has_work(bp, cpr) && rx_pkts < budget) {
1849                 napi_complete_done(napi, rx_pkts);
1850                 BNXT_CP_DB_REARM(cpr->cp_doorbell, cpr->cp_raw_cons);
1851         }
1852         return rx_pkts;
1853 }
1854
1855 static int bnxt_poll(struct napi_struct *napi, int budget)
1856 {
1857         struct bnxt_napi *bnapi = container_of(napi, struct bnxt_napi, napi);
1858         struct bnxt *bp = bnapi->bp;
1859         struct bnxt_cp_ring_info *cpr = &bnapi->cp_ring;
1860         int work_done = 0;
1861
1862         while (1) {
1863                 work_done += bnxt_poll_work(bp, bnapi, budget - work_done);
1864
1865                 if (work_done >= budget)
1866                         break;
1867
1868                 if (!bnxt_has_work(bp, cpr)) {
1869                         if (napi_complete_done(napi, work_done))
1870                                 BNXT_CP_DB_REARM(cpr->cp_doorbell,
1871                                                  cpr->cp_raw_cons);
1872                         break;
1873                 }
1874         }
1875         mmiowb();
1876         return work_done;
1877 }
1878
1879 static void bnxt_free_tx_skbs(struct bnxt *bp)
1880 {
1881         int i, max_idx;
1882         struct pci_dev *pdev = bp->pdev;
1883
1884         if (!bp->tx_ring)
1885                 return;
1886
1887         max_idx = bp->tx_nr_pages * TX_DESC_CNT;
1888         for (i = 0; i < bp->tx_nr_rings; i++) {
1889                 struct bnxt_tx_ring_info *txr = &bp->tx_ring[i];
1890                 int j;
1891
1892                 for (j = 0; j < max_idx;) {
1893                         struct bnxt_sw_tx_bd *tx_buf = &txr->tx_buf_ring[j];
1894                         struct sk_buff *skb = tx_buf->skb;
1895                         int k, last;
1896
1897                         if (!skb) {
1898                                 j++;
1899                                 continue;
1900                         }
1901
1902                         tx_buf->skb = NULL;
1903
1904                         if (tx_buf->is_push) {
1905                                 dev_kfree_skb(skb);
1906                                 j += 2;
1907                                 continue;
1908                         }
1909
1910                         dma_unmap_single(&pdev->dev,
1911                                          dma_unmap_addr(tx_buf, mapping),
1912                                          skb_headlen(skb),
1913                                          PCI_DMA_TODEVICE);
1914
1915                         last = tx_buf->nr_frags;
1916                         j += 2;
1917                         for (k = 0; k < last; k++, j++) {
1918                                 int ring_idx = j & bp->tx_ring_mask;
1919                                 skb_frag_t *frag = &skb_shinfo(skb)->frags[k];
1920
1921                                 tx_buf = &txr->tx_buf_ring[ring_idx];
1922                                 dma_unmap_page(
1923                                         &pdev->dev,
1924                                         dma_unmap_addr(tx_buf, mapping),
1925                                         skb_frag_size(frag), PCI_DMA_TODEVICE);
1926                         }
1927                         dev_kfree_skb(skb);
1928                 }
1929                 netdev_tx_reset_queue(netdev_get_tx_queue(bp->dev, i));
1930         }
1931 }
1932
1933 static void bnxt_free_rx_skbs(struct bnxt *bp)
1934 {
1935         int i, max_idx, max_agg_idx;
1936         struct pci_dev *pdev = bp->pdev;
1937
1938         if (!bp->rx_ring)
1939                 return;
1940
1941         max_idx = bp->rx_nr_pages * RX_DESC_CNT;
1942         max_agg_idx = bp->rx_agg_nr_pages * RX_DESC_CNT;
1943         for (i = 0; i < bp->rx_nr_rings; i++) {
1944                 struct bnxt_rx_ring_info *rxr = &bp->rx_ring[i];
1945                 int j;
1946
1947                 if (rxr->rx_tpa) {
1948                         for (j = 0; j < MAX_TPA; j++) {
1949                                 struct bnxt_tpa_info *tpa_info =
1950                                                         &rxr->rx_tpa[j];
1951                                 u8 *data = tpa_info->data;
1952
1953                                 if (!data)
1954                                         continue;
1955
1956                                 dma_unmap_single(&pdev->dev, tpa_info->mapping,
1957                                                  bp->rx_buf_use_size,
1958                                                  bp->rx_dir);
1959
1960                                 tpa_info->data = NULL;
1961
1962                                 kfree(data);
1963                         }
1964                 }
1965
1966                 for (j = 0; j < max_idx; j++) {
1967                         struct bnxt_sw_rx_bd *rx_buf = &rxr->rx_buf_ring[j];
1968                         void *data = rx_buf->data;
1969
1970                         if (!data)
1971                                 continue;
1972
1973                         dma_unmap_single(&pdev->dev, rx_buf->mapping,
1974                                          bp->rx_buf_use_size, bp->rx_dir);
1975
1976                         rx_buf->data = NULL;
1977
1978                         if (BNXT_RX_PAGE_MODE(bp))
1979                                 __free_page(data);
1980                         else
1981                                 kfree(data);
1982                 }
1983
1984                 for (j = 0; j < max_agg_idx; j++) {
1985                         struct bnxt_sw_rx_agg_bd *rx_agg_buf =
1986                                 &rxr->rx_agg_ring[j];
1987                         struct page *page = rx_agg_buf->page;
1988
1989                         if (!page)
1990                                 continue;
1991
1992                         dma_unmap_page(&pdev->dev, rx_agg_buf->mapping,
1993                                        BNXT_RX_PAGE_SIZE, PCI_DMA_FROMDEVICE);
1994
1995                         rx_agg_buf->page = NULL;
1996                         __clear_bit(j, rxr->rx_agg_bmap);
1997
1998                         __free_page(page);
1999                 }
2000                 if (rxr->rx_page) {
2001                         __free_page(rxr->rx_page);
2002                         rxr->rx_page = NULL;
2003                 }
2004         }
2005 }
2006
2007 static void bnxt_free_skbs(struct bnxt *bp)
2008 {
2009         bnxt_free_tx_skbs(bp);
2010         bnxt_free_rx_skbs(bp);
2011 }
2012
2013 static void bnxt_free_ring(struct bnxt *bp, struct bnxt_ring_struct *ring)
2014 {
2015         struct pci_dev *pdev = bp->pdev;
2016         int i;
2017
2018         for (i = 0; i < ring->nr_pages; i++) {
2019                 if (!ring->pg_arr[i])
2020                         continue;
2021
2022                 dma_free_coherent(&pdev->dev, ring->page_size,
2023                                   ring->pg_arr[i], ring->dma_arr[i]);
2024
2025                 ring->pg_arr[i] = NULL;
2026         }
2027         if (ring->pg_tbl) {
2028                 dma_free_coherent(&pdev->dev, ring->nr_pages * 8,
2029                                   ring->pg_tbl, ring->pg_tbl_map);
2030                 ring->pg_tbl = NULL;
2031         }
2032         if (ring->vmem_size && *ring->vmem) {
2033                 vfree(*ring->vmem);
2034                 *ring->vmem = NULL;
2035         }
2036 }
2037
2038 static int bnxt_alloc_ring(struct bnxt *bp, struct bnxt_ring_struct *ring)
2039 {
2040         int i;
2041         struct pci_dev *pdev = bp->pdev;
2042
2043         if (ring->nr_pages > 1) {
2044                 ring->pg_tbl = dma_alloc_coherent(&pdev->dev,
2045                                                   ring->nr_pages * 8,
2046                                                   &ring->pg_tbl_map,
2047                                                   GFP_KERNEL);
2048                 if (!ring->pg_tbl)
2049                         return -ENOMEM;
2050         }
2051
2052         for (i = 0; i < ring->nr_pages; i++) {
2053                 ring->pg_arr[i] = dma_alloc_coherent(&pdev->dev,
2054                                                      ring->page_size,
2055                                                      &ring->dma_arr[i],
2056                                                      GFP_KERNEL);
2057                 if (!ring->pg_arr[i])
2058                         return -ENOMEM;
2059
2060                 if (ring->nr_pages > 1)
2061                         ring->pg_tbl[i] = cpu_to_le64(ring->dma_arr[i]);
2062         }
2063
2064         if (ring->vmem_size) {
2065                 *ring->vmem = vzalloc(ring->vmem_size);
2066                 if (!(*ring->vmem))
2067                         return -ENOMEM;
2068         }
2069         return 0;
2070 }
2071
2072 static void bnxt_free_rx_rings(struct bnxt *bp)
2073 {
2074         int i;
2075
2076         if (!bp->rx_ring)
2077                 return;
2078
2079         for (i = 0; i < bp->rx_nr_rings; i++) {
2080                 struct bnxt_rx_ring_info *rxr = &bp->rx_ring[i];
2081                 struct bnxt_ring_struct *ring;
2082
2083                 kfree(rxr->rx_tpa);
2084                 rxr->rx_tpa = NULL;
2085
2086                 kfree(rxr->rx_agg_bmap);
2087                 rxr->rx_agg_bmap = NULL;
2088
2089                 ring = &rxr->rx_ring_struct;
2090                 bnxt_free_ring(bp, ring);
2091
2092                 ring = &rxr->rx_agg_ring_struct;
2093                 bnxt_free_ring(bp, ring);
2094         }
2095 }
2096
2097 static int bnxt_alloc_rx_rings(struct bnxt *bp)
2098 {
2099         int i, rc, agg_rings = 0, tpa_rings = 0;
2100
2101         if (!bp->rx_ring)
2102                 return -ENOMEM;
2103
2104         if (bp->flags & BNXT_FLAG_AGG_RINGS)
2105                 agg_rings = 1;
2106
2107         if (bp->flags & BNXT_FLAG_TPA)
2108                 tpa_rings = 1;
2109
2110         for (i = 0; i < bp->rx_nr_rings; i++) {
2111                 struct bnxt_rx_ring_info *rxr = &bp->rx_ring[i];
2112                 struct bnxt_ring_struct *ring;
2113
2114                 ring = &rxr->rx_ring_struct;
2115
2116                 rc = bnxt_alloc_ring(bp, ring);
2117                 if (rc)
2118                         return rc;
2119
2120                 if (agg_rings) {
2121                         u16 mem_size;
2122
2123                         ring = &rxr->rx_agg_ring_struct;
2124                         rc = bnxt_alloc_ring(bp, ring);
2125                         if (rc)
2126                                 return rc;
2127
2128                         rxr->rx_agg_bmap_size = bp->rx_agg_ring_mask + 1;
2129                         mem_size = rxr->rx_agg_bmap_size / 8;
2130                         rxr->rx_agg_bmap = kzalloc(mem_size, GFP_KERNEL);
2131                         if (!rxr->rx_agg_bmap)
2132                                 return -ENOMEM;
2133
2134                         if (tpa_rings) {
2135                                 rxr->rx_tpa = kcalloc(MAX_TPA,
2136                                                 sizeof(struct bnxt_tpa_info),
2137                                                 GFP_KERNEL);
2138                                 if (!rxr->rx_tpa)
2139                                         return -ENOMEM;
2140                         }
2141                 }
2142         }
2143         return 0;
2144 }
2145
2146 static void bnxt_free_tx_rings(struct bnxt *bp)
2147 {
2148         int i;
2149         struct pci_dev *pdev = bp->pdev;
2150
2151         if (!bp->tx_ring)
2152                 return;
2153
2154         for (i = 0; i < bp->tx_nr_rings; i++) {
2155                 struct bnxt_tx_ring_info *txr = &bp->tx_ring[i];
2156                 struct bnxt_ring_struct *ring;
2157
2158                 if (txr->tx_push) {
2159                         dma_free_coherent(&pdev->dev, bp->tx_push_size,
2160                                           txr->tx_push, txr->tx_push_mapping);
2161                         txr->tx_push = NULL;
2162                 }
2163
2164                 ring = &txr->tx_ring_struct;
2165
2166                 bnxt_free_ring(bp, ring);
2167         }
2168 }
2169
2170 static int bnxt_alloc_tx_rings(struct bnxt *bp)
2171 {
2172         int i, j, rc;
2173         struct pci_dev *pdev = bp->pdev;
2174
2175         bp->tx_push_size = 0;
2176         if (bp->tx_push_thresh) {
2177                 int push_size;
2178
2179                 push_size  = L1_CACHE_ALIGN(sizeof(struct tx_push_bd) +
2180                                         bp->tx_push_thresh);
2181
2182                 if (push_size > 256) {
2183                         push_size = 0;
2184                         bp->tx_push_thresh = 0;
2185                 }
2186
2187                 bp->tx_push_size = push_size;
2188         }
2189
2190         for (i = 0, j = 0; i < bp->tx_nr_rings; i++) {
2191                 struct bnxt_tx_ring_info *txr = &bp->tx_ring[i];
2192                 struct bnxt_ring_struct *ring;
2193
2194                 ring = &txr->tx_ring_struct;
2195
2196                 rc = bnxt_alloc_ring(bp, ring);
2197                 if (rc)
2198                         return rc;
2199
2200                 if (bp->tx_push_size) {
2201                         dma_addr_t mapping;
2202
2203                         /* One pre-allocated DMA buffer to backup
2204                          * TX push operation
2205                          */
2206                         txr->tx_push = dma_alloc_coherent(&pdev->dev,
2207                                                 bp->tx_push_size,
2208                                                 &txr->tx_push_mapping,
2209                                                 GFP_KERNEL);
2210
2211                         if (!txr->tx_push)
2212                                 return -ENOMEM;
2213
2214                         mapping = txr->tx_push_mapping +
2215                                 sizeof(struct tx_push_bd);
2216                         txr->data_mapping = cpu_to_le64(mapping);
2217
2218                         memset(txr->tx_push, 0, sizeof(struct tx_push_bd));
2219                 }
2220                 ring->queue_id = bp->q_info[j].queue_id;
2221                 if (i < bp->tx_nr_rings_xdp)
2222                         continue;
2223                 if (i % bp->tx_nr_rings_per_tc == (bp->tx_nr_rings_per_tc - 1))
2224                         j++;
2225         }
2226         return 0;
2227 }
2228
2229 static void bnxt_free_cp_rings(struct bnxt *bp)
2230 {
2231         int i;
2232
2233         if (!bp->bnapi)
2234                 return;
2235
2236         for (i = 0; i < bp->cp_nr_rings; i++) {
2237                 struct bnxt_napi *bnapi = bp->bnapi[i];
2238                 struct bnxt_cp_ring_info *cpr;
2239                 struct bnxt_ring_struct *ring;
2240
2241                 if (!bnapi)
2242                         continue;
2243
2244                 cpr = &bnapi->cp_ring;
2245                 ring = &cpr->cp_ring_struct;
2246
2247                 bnxt_free_ring(bp, ring);
2248         }
2249 }
2250
2251 static int bnxt_alloc_cp_rings(struct bnxt *bp)
2252 {
2253         int i, rc;
2254
2255         for (i = 0; i < bp->cp_nr_rings; i++) {
2256                 struct bnxt_napi *bnapi = bp->bnapi[i];
2257                 struct bnxt_cp_ring_info *cpr;
2258                 struct bnxt_ring_struct *ring;
2259
2260                 if (!bnapi)
2261                         continue;
2262
2263                 cpr = &bnapi->cp_ring;
2264                 ring = &cpr->cp_ring_struct;
2265
2266                 rc = bnxt_alloc_ring(bp, ring);
2267                 if (rc)
2268                         return rc;
2269         }
2270         return 0;
2271 }
2272
2273 static void bnxt_init_ring_struct(struct bnxt *bp)
2274 {
2275         int i;
2276
2277         for (i = 0; i < bp->cp_nr_rings; i++) {
2278                 struct bnxt_napi *bnapi = bp->bnapi[i];
2279                 struct bnxt_cp_ring_info *cpr;
2280                 struct bnxt_rx_ring_info *rxr;
2281                 struct bnxt_tx_ring_info *txr;
2282                 struct bnxt_ring_struct *ring;
2283
2284                 if (!bnapi)
2285                         continue;
2286
2287                 cpr = &bnapi->cp_ring;
2288                 ring = &cpr->cp_ring_struct;
2289                 ring->nr_pages = bp->cp_nr_pages;
2290                 ring->page_size = HW_CMPD_RING_SIZE;
2291                 ring->pg_arr = (void **)cpr->cp_desc_ring;
2292                 ring->dma_arr = cpr->cp_desc_mapping;
2293                 ring->vmem_size = 0;
2294
2295                 rxr = bnapi->rx_ring;
2296                 if (!rxr)
2297                         goto skip_rx;
2298
2299                 ring = &rxr->rx_ring_struct;
2300                 ring->nr_pages = bp->rx_nr_pages;
2301                 ring->page_size = HW_RXBD_RING_SIZE;
2302                 ring->pg_arr = (void **)rxr->rx_desc_ring;
2303                 ring->dma_arr = rxr->rx_desc_mapping;
2304                 ring->vmem_size = SW_RXBD_RING_SIZE * bp->rx_nr_pages;
2305                 ring->vmem = (void **)&rxr->rx_buf_ring;
2306
2307                 ring = &rxr->rx_agg_ring_struct;
2308                 ring->nr_pages = bp->rx_agg_nr_pages;
2309                 ring->page_size = HW_RXBD_RING_SIZE;
2310                 ring->pg_arr = (void **)rxr->rx_agg_desc_ring;
2311                 ring->dma_arr = rxr->rx_agg_desc_mapping;
2312                 ring->vmem_size = SW_RXBD_AGG_RING_SIZE * bp->rx_agg_nr_pages;
2313                 ring->vmem = (void **)&rxr->rx_agg_ring;
2314
2315 skip_rx:
2316                 txr = bnapi->tx_ring;
2317                 if (!txr)
2318                         continue;
2319
2320                 ring = &txr->tx_ring_struct;
2321                 ring->nr_pages = bp->tx_nr_pages;
2322                 ring->page_size = HW_RXBD_RING_SIZE;
2323                 ring->pg_arr = (void **)txr->tx_desc_ring;
2324                 ring->dma_arr = txr->tx_desc_mapping;
2325                 ring->vmem_size = SW_TXBD_RING_SIZE * bp->tx_nr_pages;
2326                 ring->vmem = (void **)&txr->tx_buf_ring;
2327         }
2328 }
2329
2330 static void bnxt_init_rxbd_pages(struct bnxt_ring_struct *ring, u32 type)
2331 {
2332         int i;
2333         u32 prod;
2334         struct rx_bd **rx_buf_ring;
2335
2336         rx_buf_ring = (struct rx_bd **)ring->pg_arr;
2337         for (i = 0, prod = 0; i < ring->nr_pages; i++) {
2338                 int j;
2339                 struct rx_bd *rxbd;
2340
2341                 rxbd = rx_buf_ring[i];
2342                 if (!rxbd)
2343                         continue;
2344
2345                 for (j = 0; j < RX_DESC_CNT; j++, rxbd++, prod++) {
2346                         rxbd->rx_bd_len_flags_type = cpu_to_le32(type);
2347                         rxbd->rx_bd_opaque = prod;
2348                 }
2349         }
2350 }
2351
2352 static int bnxt_init_one_rx_ring(struct bnxt *bp, int ring_nr)
2353 {
2354         struct net_device *dev = bp->dev;
2355         struct bnxt_rx_ring_info *rxr;
2356         struct bnxt_ring_struct *ring;
2357         u32 prod, type;
2358         int i;
2359
2360         type = (bp->rx_buf_use_size << RX_BD_LEN_SHIFT) |
2361                 RX_BD_TYPE_RX_PACKET_BD | RX_BD_FLAGS_EOP;
2362
2363         if (NET_IP_ALIGN == 2)
2364                 type |= RX_BD_FLAGS_SOP;
2365
2366         rxr = &bp->rx_ring[ring_nr];
2367         ring = &rxr->rx_ring_struct;
2368         bnxt_init_rxbd_pages(ring, type);
2369
2370         prod = rxr->rx_prod;
2371         for (i = 0; i < bp->rx_ring_size; i++) {
2372                 if (bnxt_alloc_rx_data(bp, rxr, prod, GFP_KERNEL) != 0) {
2373                         netdev_warn(dev, "init'ed rx ring %d with %d/%d skbs only\n",
2374                                     ring_nr, i, bp->rx_ring_size);
2375                         break;
2376                 }
2377                 prod = NEXT_RX(prod);
2378         }
2379         rxr->rx_prod = prod;
2380         ring->fw_ring_id = INVALID_HW_RING_ID;
2381
2382         ring = &rxr->rx_agg_ring_struct;
2383         ring->fw_ring_id = INVALID_HW_RING_ID;
2384
2385         if (!(bp->flags & BNXT_FLAG_AGG_RINGS))
2386                 return 0;
2387
2388         type = ((u32)BNXT_RX_PAGE_SIZE << RX_BD_LEN_SHIFT) |
2389                 RX_BD_TYPE_RX_AGG_BD | RX_BD_FLAGS_SOP;
2390
2391         bnxt_init_rxbd_pages(ring, type);
2392
2393         prod = rxr->rx_agg_prod;
2394         for (i = 0; i < bp->rx_agg_ring_size; i++) {
2395                 if (bnxt_alloc_rx_page(bp, rxr, prod, GFP_KERNEL) != 0) {
2396                         netdev_warn(dev, "init'ed rx ring %d with %d/%d pages only\n",
2397                                     ring_nr, i, bp->rx_ring_size);
2398                         break;
2399                 }
2400                 prod = NEXT_RX_AGG(prod);
2401         }
2402         rxr->rx_agg_prod = prod;
2403
2404         if (bp->flags & BNXT_FLAG_TPA) {
2405                 if (rxr->rx_tpa) {
2406                         u8 *data;
2407                         dma_addr_t mapping;
2408
2409                         for (i = 0; i < MAX_TPA; i++) {
2410                                 data = __bnxt_alloc_rx_data(bp, &mapping,
2411                                                             GFP_KERNEL);
2412                                 if (!data)
2413                                         return -ENOMEM;
2414
2415                                 rxr->rx_tpa[i].data = data;
2416                                 rxr->rx_tpa[i].data_ptr = data + bp->rx_offset;
2417                                 rxr->rx_tpa[i].mapping = mapping;
2418                         }
2419                 } else {
2420                         netdev_err(bp->dev, "No resource allocated for LRO/GRO\n");
2421                         return -ENOMEM;
2422                 }
2423         }
2424
2425         return 0;
2426 }
2427
2428 static int bnxt_init_rx_rings(struct bnxt *bp)
2429 {
2430         int i, rc = 0;
2431
2432         if (BNXT_RX_PAGE_MODE(bp)) {
2433                 bp->rx_offset = NET_IP_ALIGN;
2434                 bp->rx_dma_offset = 0;
2435         } else {
2436                 bp->rx_offset = BNXT_RX_OFFSET;
2437                 bp->rx_dma_offset = BNXT_RX_DMA_OFFSET;
2438         }
2439
2440         for (i = 0; i < bp->rx_nr_rings; i++) {
2441                 rc = bnxt_init_one_rx_ring(bp, i);
2442                 if (rc)
2443                         break;
2444         }
2445
2446         return rc;
2447 }
2448
2449 static int bnxt_init_tx_rings(struct bnxt *bp)
2450 {
2451         u16 i;
2452
2453         bp->tx_wake_thresh = max_t(int, bp->tx_ring_size / 2,
2454                                    MAX_SKB_FRAGS + 1);
2455
2456         for (i = 0; i < bp->tx_nr_rings; i++) {
2457                 struct bnxt_tx_ring_info *txr = &bp->tx_ring[i];
2458                 struct bnxt_ring_struct *ring = &txr->tx_ring_struct;
2459
2460                 ring->fw_ring_id = INVALID_HW_RING_ID;
2461         }
2462
2463         return 0;
2464 }
2465
2466 static void bnxt_free_ring_grps(struct bnxt *bp)
2467 {
2468         kfree(bp->grp_info);
2469         bp->grp_info = NULL;
2470 }
2471
2472 static int bnxt_init_ring_grps(struct bnxt *bp, bool irq_re_init)
2473 {
2474         int i;
2475
2476         if (irq_re_init) {
2477                 bp->grp_info = kcalloc(bp->cp_nr_rings,
2478                                        sizeof(struct bnxt_ring_grp_info),
2479                                        GFP_KERNEL);
2480                 if (!bp->grp_info)
2481                         return -ENOMEM;
2482         }
2483         for (i = 0; i < bp->cp_nr_rings; i++) {
2484                 if (irq_re_init)
2485                         bp->grp_info[i].fw_stats_ctx = INVALID_HW_RING_ID;
2486                 bp->grp_info[i].fw_grp_id = INVALID_HW_RING_ID;
2487                 bp->grp_info[i].rx_fw_ring_id = INVALID_HW_RING_ID;
2488                 bp->grp_info[i].agg_fw_ring_id = INVALID_HW_RING_ID;
2489                 bp->grp_info[i].cp_fw_ring_id = INVALID_HW_RING_ID;
2490         }
2491         return 0;
2492 }
2493
2494 static void bnxt_free_vnics(struct bnxt *bp)
2495 {
2496         kfree(bp->vnic_info);
2497         bp->vnic_info = NULL;
2498         bp->nr_vnics = 0;
2499 }
2500
2501 static int bnxt_alloc_vnics(struct bnxt *bp)
2502 {
2503         int num_vnics = 1;
2504
2505 #ifdef CONFIG_RFS_ACCEL
2506         if (bp->flags & BNXT_FLAG_RFS)
2507                 num_vnics += bp->rx_nr_rings;
2508 #endif
2509
2510         if (BNXT_CHIP_TYPE_NITRO_A0(bp))
2511                 num_vnics++;
2512
2513         bp->vnic_info = kcalloc(num_vnics, sizeof(struct bnxt_vnic_info),
2514                                 GFP_KERNEL);
2515         if (!bp->vnic_info)
2516                 return -ENOMEM;
2517
2518         bp->nr_vnics = num_vnics;
2519         return 0;
2520 }
2521
2522 static void bnxt_init_vnics(struct bnxt *bp)
2523 {
2524         int i;
2525
2526         for (i = 0; i < bp->nr_vnics; i++) {
2527                 struct bnxt_vnic_info *vnic = &bp->vnic_info[i];
2528
2529                 vnic->fw_vnic_id = INVALID_HW_RING_ID;
2530                 vnic->fw_rss_cos_lb_ctx[0] = INVALID_HW_RING_ID;
2531                 vnic->fw_rss_cos_lb_ctx[1] = INVALID_HW_RING_ID;
2532                 vnic->fw_l2_ctx_id = INVALID_HW_RING_ID;
2533
2534                 if (bp->vnic_info[i].rss_hash_key) {
2535                         if (i == 0)
2536                                 prandom_bytes(vnic->rss_hash_key,
2537                                               HW_HASH_KEY_SIZE);
2538                         else
2539                                 memcpy(vnic->rss_hash_key,
2540                                        bp->vnic_info[0].rss_hash_key,
2541                                        HW_HASH_KEY_SIZE);
2542                 }
2543         }
2544 }
2545
2546 static int bnxt_calc_nr_ring_pages(u32 ring_size, int desc_per_pg)
2547 {
2548         int pages;
2549
2550         pages = ring_size / desc_per_pg;
2551
2552         if (!pages)
2553                 return 1;
2554
2555         pages++;
2556
2557         while (pages & (pages - 1))
2558                 pages++;
2559
2560         return pages;
2561 }
2562
2563 static void bnxt_set_tpa_flags(struct bnxt *bp)
2564 {
2565         bp->flags &= ~BNXT_FLAG_TPA;
2566         if (bp->flags & BNXT_FLAG_NO_AGG_RINGS)
2567                 return;
2568         if (bp->dev->features & NETIF_F_LRO)
2569                 bp->flags |= BNXT_FLAG_LRO;
2570         if (bp->dev->features & NETIF_F_GRO)
2571                 bp->flags |= BNXT_FLAG_GRO;
2572 }
2573
2574 /* bp->rx_ring_size, bp->tx_ring_size, dev->mtu, BNXT_FLAG_{G|L}RO flags must
2575  * be set on entry.
2576  */
2577 void bnxt_set_ring_params(struct bnxt *bp)
2578 {
2579         u32 ring_size, rx_size, rx_space;
2580         u32 agg_factor = 0, agg_ring_size = 0;
2581
2582         /* 8 for CRC and VLAN */
2583         rx_size = SKB_DATA_ALIGN(bp->dev->mtu + ETH_HLEN + NET_IP_ALIGN + 8);
2584
2585         rx_space = rx_size + NET_SKB_PAD +
2586                 SKB_DATA_ALIGN(sizeof(struct skb_shared_info));
2587
2588         bp->rx_copy_thresh = BNXT_RX_COPY_THRESH;
2589         ring_size = bp->rx_ring_size;
2590         bp->rx_agg_ring_size = 0;
2591         bp->rx_agg_nr_pages = 0;
2592
2593         if (bp->flags & BNXT_FLAG_TPA)
2594                 agg_factor = min_t(u32, 4, 65536 / BNXT_RX_PAGE_SIZE);
2595
2596         bp->flags &= ~BNXT_FLAG_JUMBO;
2597         if (rx_space > PAGE_SIZE && !(bp->flags & BNXT_FLAG_NO_AGG_RINGS)) {
2598                 u32 jumbo_factor;
2599
2600                 bp->flags |= BNXT_FLAG_JUMBO;
2601                 jumbo_factor = PAGE_ALIGN(bp->dev->mtu - 40) >> PAGE_SHIFT;
2602                 if (jumbo_factor > agg_factor)
2603                         agg_factor = jumbo_factor;
2604         }
2605         agg_ring_size = ring_size * agg_factor;
2606
2607         if (agg_ring_size) {
2608                 bp->rx_agg_nr_pages = bnxt_calc_nr_ring_pages(agg_ring_size,
2609                                                         RX_DESC_CNT);
2610                 if (bp->rx_agg_nr_pages > MAX_RX_AGG_PAGES) {
2611                         u32 tmp = agg_ring_size;
2612
2613                         bp->rx_agg_nr_pages = MAX_RX_AGG_PAGES;
2614                         agg_ring_size = MAX_RX_AGG_PAGES * RX_DESC_CNT - 1;
2615                         netdev_warn(bp->dev, "rx agg ring size %d reduced to %d.\n",
2616                                     tmp, agg_ring_size);
2617                 }
2618                 bp->rx_agg_ring_size = agg_ring_size;
2619                 bp->rx_agg_ring_mask = (bp->rx_agg_nr_pages * RX_DESC_CNT) - 1;
2620                 rx_size = SKB_DATA_ALIGN(BNXT_RX_COPY_THRESH + NET_IP_ALIGN);
2621                 rx_space = rx_size + NET_SKB_PAD +
2622                         SKB_DATA_ALIGN(sizeof(struct skb_shared_info));
2623         }
2624
2625         bp->rx_buf_use_size = rx_size;
2626         bp->rx_buf_size = rx_space;
2627
2628         bp->rx_nr_pages = bnxt_calc_nr_ring_pages(ring_size, RX_DESC_CNT);
2629         bp->rx_ring_mask = (bp->rx_nr_pages * RX_DESC_CNT) - 1;
2630
2631         ring_size = bp->tx_ring_size;
2632         bp->tx_nr_pages = bnxt_calc_nr_ring_pages(ring_size, TX_DESC_CNT);
2633         bp->tx_ring_mask = (bp->tx_nr_pages * TX_DESC_CNT) - 1;
2634
2635         ring_size = bp->rx_ring_size * (2 + agg_factor) + bp->tx_ring_size;
2636         bp->cp_ring_size = ring_size;
2637
2638         bp->cp_nr_pages = bnxt_calc_nr_ring_pages(ring_size, CP_DESC_CNT);
2639         if (bp->cp_nr_pages > MAX_CP_PAGES) {
2640                 bp->cp_nr_pages = MAX_CP_PAGES;
2641                 bp->cp_ring_size = MAX_CP_PAGES * CP_DESC_CNT - 1;
2642                 netdev_warn(bp->dev, "completion ring size %d reduced to %d.\n",
2643                             ring_size, bp->cp_ring_size);
2644         }
2645         bp->cp_bit = bp->cp_nr_pages * CP_DESC_CNT;
2646         bp->cp_ring_mask = bp->cp_bit - 1;
2647 }
2648
2649 int bnxt_set_rx_skb_mode(struct bnxt *bp, bool page_mode)
2650 {
2651         if (page_mode) {
2652                 if (bp->dev->mtu > BNXT_MAX_PAGE_MODE_MTU)
2653                         return -EOPNOTSUPP;
2654                 bp->dev->max_mtu = BNXT_MAX_PAGE_MODE_MTU;
2655                 bp->flags &= ~BNXT_FLAG_AGG_RINGS;
2656                 bp->flags |= BNXT_FLAG_NO_AGG_RINGS | BNXT_FLAG_RX_PAGE_MODE;
2657                 bp->dev->hw_features &= ~NETIF_F_LRO;
2658                 bp->dev->features &= ~NETIF_F_LRO;
2659                 bp->rx_dir = DMA_BIDIRECTIONAL;
2660                 bp->rx_skb_func = bnxt_rx_page_skb;
2661         } else {
2662                 bp->dev->max_mtu = BNXT_MAX_MTU;
2663                 bp->flags &= ~BNXT_FLAG_RX_PAGE_MODE;
2664                 bp->rx_dir = DMA_FROM_DEVICE;
2665                 bp->rx_skb_func = bnxt_rx_skb;
2666         }
2667         return 0;
2668 }
2669
2670 static void bnxt_free_vnic_attributes(struct bnxt *bp)
2671 {
2672         int i;
2673         struct bnxt_vnic_info *vnic;
2674         struct pci_dev *pdev = bp->pdev;
2675
2676         if (!bp->vnic_info)
2677                 return;
2678
2679         for (i = 0; i < bp->nr_vnics; i++) {
2680                 vnic = &bp->vnic_info[i];
2681
2682                 kfree(vnic->fw_grp_ids);
2683                 vnic->fw_grp_ids = NULL;
2684
2685                 kfree(vnic->uc_list);
2686                 vnic->uc_list = NULL;
2687
2688                 if (vnic->mc_list) {
2689                         dma_free_coherent(&pdev->dev, vnic->mc_list_size,
2690                                           vnic->mc_list, vnic->mc_list_mapping);
2691                         vnic->mc_list = NULL;
2692                 }
2693
2694                 if (vnic->rss_table) {
2695                         dma_free_coherent(&pdev->dev, PAGE_SIZE,
2696                                           vnic->rss_table,
2697                                           vnic->rss_table_dma_addr);
2698                         vnic->rss_table = NULL;
2699                 }
2700
2701                 vnic->rss_hash_key = NULL;
2702                 vnic->flags = 0;
2703         }
2704 }
2705
2706 static int bnxt_alloc_vnic_attributes(struct bnxt *bp)
2707 {
2708         int i, rc = 0, size;
2709         struct bnxt_vnic_info *vnic;
2710         struct pci_dev *pdev = bp->pdev;
2711         int max_rings;
2712
2713         for (i = 0; i < bp->nr_vnics; i++) {
2714                 vnic = &bp->vnic_info[i];
2715
2716                 if (vnic->flags & BNXT_VNIC_UCAST_FLAG) {
2717                         int mem_size = (BNXT_MAX_UC_ADDRS - 1) * ETH_ALEN;
2718
2719                         if (mem_size > 0) {
2720                                 vnic->uc_list = kmalloc(mem_size, GFP_KERNEL);
2721                                 if (!vnic->uc_list) {
2722                                         rc = -ENOMEM;
2723                                         goto out;
2724                                 }
2725                         }
2726                 }
2727
2728                 if (vnic->flags & BNXT_VNIC_MCAST_FLAG) {
2729                         vnic->mc_list_size = BNXT_MAX_MC_ADDRS * ETH_ALEN;
2730                         vnic->mc_list =
2731                                 dma_alloc_coherent(&pdev->dev,
2732                                                    vnic->mc_list_size,
2733                                                    &vnic->mc_list_mapping,
2734                                                    GFP_KERNEL);
2735                         if (!vnic->mc_list) {
2736                                 rc = -ENOMEM;
2737                                 goto out;
2738                         }
2739                 }
2740
2741                 if (vnic->flags & BNXT_VNIC_RSS_FLAG)
2742                         max_rings = bp->rx_nr_rings;
2743                 else
2744                         max_rings = 1;
2745
2746                 vnic->fw_grp_ids = kcalloc(max_rings, sizeof(u16), GFP_KERNEL);
2747                 if (!vnic->fw_grp_ids) {
2748                         rc = -ENOMEM;
2749                         goto out;
2750                 }
2751
2752                 if ((bp->flags & BNXT_FLAG_NEW_RSS_CAP) &&
2753                     !(vnic->flags & BNXT_VNIC_RSS_FLAG))
2754                         continue;
2755
2756                 /* Allocate rss table and hash key */
2757                 vnic->rss_table = dma_alloc_coherent(&pdev->dev, PAGE_SIZE,
2758                                                      &vnic->rss_table_dma_addr,
2759                                                      GFP_KERNEL);
2760                 if (!vnic->rss_table) {
2761                         rc = -ENOMEM;
2762                         goto out;
2763                 }
2764
2765                 size = L1_CACHE_ALIGN(HW_HASH_INDEX_SIZE * sizeof(u16));
2766
2767                 vnic->rss_hash_key = ((void *)vnic->rss_table) + size;
2768                 vnic->rss_hash_key_dma_addr = vnic->rss_table_dma_addr + size;
2769         }
2770         return 0;
2771
2772 out:
2773         return rc;
2774 }
2775
2776 static void bnxt_free_hwrm_resources(struct bnxt *bp)
2777 {
2778         struct pci_dev *pdev = bp->pdev;
2779
2780         dma_free_coherent(&pdev->dev, PAGE_SIZE, bp->hwrm_cmd_resp_addr,
2781                           bp->hwrm_cmd_resp_dma_addr);
2782
2783         bp->hwrm_cmd_resp_addr = NULL;
2784         if (bp->hwrm_dbg_resp_addr) {
2785                 dma_free_coherent(&pdev->dev, HWRM_DBG_REG_BUF_SIZE,
2786                                   bp->hwrm_dbg_resp_addr,
2787                                   bp->hwrm_dbg_resp_dma_addr);
2788
2789                 bp->hwrm_dbg_resp_addr = NULL;
2790         }
2791 }
2792
2793 static int bnxt_alloc_hwrm_resources(struct bnxt *bp)
2794 {
2795         struct pci_dev *pdev = bp->pdev;
2796
2797         bp->hwrm_cmd_resp_addr = dma_alloc_coherent(&pdev->dev, PAGE_SIZE,
2798                                                    &bp->hwrm_cmd_resp_dma_addr,
2799                                                    GFP_KERNEL);
2800         if (!bp->hwrm_cmd_resp_addr)
2801                 return -ENOMEM;
2802         bp->hwrm_dbg_resp_addr = dma_alloc_coherent(&pdev->dev,
2803                                                     HWRM_DBG_REG_BUF_SIZE,
2804                                                     &bp->hwrm_dbg_resp_dma_addr,
2805                                                     GFP_KERNEL);
2806         if (!bp->hwrm_dbg_resp_addr)
2807                 netdev_warn(bp->dev, "fail to alloc debug register dma mem\n");
2808
2809         return 0;
2810 }
2811
2812 static void bnxt_free_stats(struct bnxt *bp)
2813 {
2814         u32 size, i;
2815         struct pci_dev *pdev = bp->pdev;
2816
2817         if (bp->hw_rx_port_stats) {
2818                 dma_free_coherent(&pdev->dev, bp->hw_port_stats_size,
2819                                   bp->hw_rx_port_stats,
2820                                   bp->hw_rx_port_stats_map);
2821                 bp->hw_rx_port_stats = NULL;
2822                 bp->flags &= ~BNXT_FLAG_PORT_STATS;
2823         }
2824
2825         if (!bp->bnapi)
2826                 return;
2827
2828         size = sizeof(struct ctx_hw_stats);
2829
2830         for (i = 0; i < bp->cp_nr_rings; i++) {
2831                 struct bnxt_napi *bnapi = bp->bnapi[i];
2832                 struct bnxt_cp_ring_info *cpr = &bnapi->cp_ring;
2833
2834                 if (cpr->hw_stats) {
2835                         dma_free_coherent(&pdev->dev, size, cpr->hw_stats,
2836                                           cpr->hw_stats_map);
2837                         cpr->hw_stats = NULL;
2838                 }
2839         }
2840 }
2841
2842 static int bnxt_alloc_stats(struct bnxt *bp)
2843 {
2844         u32 size, i;
2845         struct pci_dev *pdev = bp->pdev;
2846
2847         size = sizeof(struct ctx_hw_stats);
2848
2849         for (i = 0; i < bp->cp_nr_rings; i++) {
2850                 struct bnxt_napi *bnapi = bp->bnapi[i];
2851                 struct bnxt_cp_ring_info *cpr = &bnapi->cp_ring;
2852
2853                 cpr->hw_stats = dma_alloc_coherent(&pdev->dev, size,
2854                                                    &cpr->hw_stats_map,
2855                                                    GFP_KERNEL);
2856                 if (!cpr->hw_stats)
2857                         return -ENOMEM;
2858
2859                 cpr->hw_stats_ctx_id = INVALID_STATS_CTX_ID;
2860         }
2861
2862         if (BNXT_PF(bp) && bp->chip_num != CHIP_NUM_58700) {
2863                 bp->hw_port_stats_size = sizeof(struct rx_port_stats) +
2864                                          sizeof(struct tx_port_stats) + 1024;
2865
2866                 bp->hw_rx_port_stats =
2867                         dma_alloc_coherent(&pdev->dev, bp->hw_port_stats_size,
2868                                            &bp->hw_rx_port_stats_map,
2869                                            GFP_KERNEL);
2870                 if (!bp->hw_rx_port_stats)
2871                         return -ENOMEM;
2872
2873                 bp->hw_tx_port_stats = (void *)(bp->hw_rx_port_stats + 1) +
2874                                        512;
2875                 bp->hw_tx_port_stats_map = bp->hw_rx_port_stats_map +
2876                                            sizeof(struct rx_port_stats) + 512;
2877                 bp->flags |= BNXT_FLAG_PORT_STATS;
2878         }
2879         return 0;
2880 }
2881
2882 static void bnxt_clear_ring_indices(struct bnxt *bp)
2883 {
2884         int i;
2885
2886         if (!bp->bnapi)
2887                 return;
2888
2889         for (i = 0; i < bp->cp_nr_rings; i++) {
2890                 struct bnxt_napi *bnapi = bp->bnapi[i];
2891                 struct bnxt_cp_ring_info *cpr;
2892                 struct bnxt_rx_ring_info *rxr;
2893                 struct bnxt_tx_ring_info *txr;
2894
2895                 if (!bnapi)
2896                         continue;
2897
2898                 cpr = &bnapi->cp_ring;
2899                 cpr->cp_raw_cons = 0;
2900
2901                 txr = bnapi->tx_ring;
2902                 if (txr) {
2903                         txr->tx_prod = 0;
2904                         txr->tx_cons = 0;
2905                 }
2906
2907                 rxr = bnapi->rx_ring;
2908                 if (rxr) {
2909                         rxr->rx_prod = 0;
2910                         rxr->rx_agg_prod = 0;
2911                         rxr->rx_sw_agg_prod = 0;
2912                         rxr->rx_next_cons = 0;
2913                 }
2914         }
2915 }
2916
2917 static void bnxt_free_ntp_fltrs(struct bnxt *bp, bool irq_reinit)
2918 {
2919 #ifdef CONFIG_RFS_ACCEL
2920         int i;
2921
2922         /* Under rtnl_lock and all our NAPIs have been disabled.  It's
2923          * safe to delete the hash table.
2924          */
2925         for (i = 0; i < BNXT_NTP_FLTR_HASH_SIZE; i++) {
2926                 struct hlist_head *head;
2927                 struct hlist_node *tmp;
2928                 struct bnxt_ntuple_filter *fltr;
2929
2930                 head = &bp->ntp_fltr_hash_tbl[i];
2931                 hlist_for_each_entry_safe(fltr, tmp, head, hash) {
2932                         hlist_del(&fltr->hash);
2933                         kfree(fltr);
2934                 }
2935         }
2936         if (irq_reinit) {
2937                 kfree(bp->ntp_fltr_bmap);
2938                 bp->ntp_fltr_bmap = NULL;
2939         }
2940         bp->ntp_fltr_count = 0;
2941 #endif
2942 }
2943
2944 static int bnxt_alloc_ntp_fltrs(struct bnxt *bp)
2945 {
2946 #ifdef CONFIG_RFS_ACCEL
2947         int i, rc = 0;
2948
2949         if (!(bp->flags & BNXT_FLAG_RFS))
2950                 return 0;
2951
2952         for (i = 0; i < BNXT_NTP_FLTR_HASH_SIZE; i++)
2953                 INIT_HLIST_HEAD(&bp->ntp_fltr_hash_tbl[i]);
2954
2955         bp->ntp_fltr_count = 0;
2956         bp->ntp_fltr_bmap = kzalloc(BITS_TO_LONGS(BNXT_NTP_FLTR_MAX_FLTR),
2957                                     GFP_KERNEL);
2958
2959         if (!bp->ntp_fltr_bmap)
2960                 rc = -ENOMEM;
2961
2962         return rc;
2963 #else
2964         return 0;
2965 #endif
2966 }
2967
2968 static void bnxt_free_mem(struct bnxt *bp, bool irq_re_init)
2969 {
2970         bnxt_free_vnic_attributes(bp);
2971         bnxt_free_tx_rings(bp);
2972         bnxt_free_rx_rings(bp);
2973         bnxt_free_cp_rings(bp);
2974         bnxt_free_ntp_fltrs(bp, irq_re_init);
2975         if (irq_re_init) {
2976                 bnxt_free_stats(bp);
2977                 bnxt_free_ring_grps(bp);
2978                 bnxt_free_vnics(bp);
2979                 kfree(bp->tx_ring_map);
2980                 bp->tx_ring_map = NULL;
2981                 kfree(bp->tx_ring);
2982                 bp->tx_ring = NULL;
2983                 kfree(bp->rx_ring);
2984                 bp->rx_ring = NULL;
2985                 kfree(bp->bnapi);
2986                 bp->bnapi = NULL;
2987         } else {
2988                 bnxt_clear_ring_indices(bp);
2989         }
2990 }
2991
2992 static int bnxt_alloc_mem(struct bnxt *bp, bool irq_re_init)
2993 {
2994         int i, j, rc, size, arr_size;
2995         void *bnapi;
2996
2997         if (irq_re_init) {
2998                 /* Allocate bnapi mem pointer array and mem block for
2999                  * all queues
3000                  */
3001                 arr_size = L1_CACHE_ALIGN(sizeof(struct bnxt_napi *) *
3002                                 bp->cp_nr_rings);
3003                 size = L1_CACHE_ALIGN(sizeof(struct bnxt_napi));
3004                 bnapi = kzalloc(arr_size + size * bp->cp_nr_rings, GFP_KERNEL);
3005                 if (!bnapi)
3006                         return -ENOMEM;
3007
3008                 bp->bnapi = bnapi;
3009                 bnapi += arr_size;
3010                 for (i = 0; i < bp->cp_nr_rings; i++, bnapi += size) {
3011                         bp->bnapi[i] = bnapi;
3012                         bp->bnapi[i]->index = i;
3013                         bp->bnapi[i]->bp = bp;
3014                 }
3015
3016                 bp->rx_ring = kcalloc(bp->rx_nr_rings,
3017                                       sizeof(struct bnxt_rx_ring_info),
3018                                       GFP_KERNEL);
3019                 if (!bp->rx_ring)
3020                         return -ENOMEM;
3021
3022                 for (i = 0; i < bp->rx_nr_rings; i++) {
3023                         bp->rx_ring[i].bnapi = bp->bnapi[i];
3024                         bp->bnapi[i]->rx_ring = &bp->rx_ring[i];
3025                 }
3026
3027                 bp->tx_ring = kcalloc(bp->tx_nr_rings,
3028                                       sizeof(struct bnxt_tx_ring_info),
3029                                       GFP_KERNEL);
3030                 if (!bp->tx_ring)
3031                         return -ENOMEM;
3032
3033                 bp->tx_ring_map = kcalloc(bp->tx_nr_rings, sizeof(u16),
3034                                           GFP_KERNEL);
3035
3036                 if (!bp->tx_ring_map)
3037                         return -ENOMEM;
3038
3039                 if (bp->flags & BNXT_FLAG_SHARED_RINGS)
3040                         j = 0;
3041                 else
3042                         j = bp->rx_nr_rings;
3043
3044                 for (i = 0; i < bp->tx_nr_rings; i++, j++) {
3045                         bp->tx_ring[i].bnapi = bp->bnapi[j];
3046                         bp->bnapi[j]->tx_ring = &bp->tx_ring[i];
3047                         bp->tx_ring_map[i] = bp->tx_nr_rings_xdp + i;
3048                         if (i >= bp->tx_nr_rings_xdp)
3049                                 bp->tx_ring[i].txq_index = i -
3050                                         bp->tx_nr_rings_xdp;
3051                 }
3052
3053                 rc = bnxt_alloc_stats(bp);
3054                 if (rc)
3055                         goto alloc_mem_err;
3056
3057                 rc = bnxt_alloc_ntp_fltrs(bp);
3058                 if (rc)
3059                         goto alloc_mem_err;
3060
3061                 rc = bnxt_alloc_vnics(bp);
3062                 if (rc)
3063                         goto alloc_mem_err;
3064         }
3065
3066         bnxt_init_ring_struct(bp);
3067
3068         rc = bnxt_alloc_rx_rings(bp);
3069         if (rc)
3070                 goto alloc_mem_err;
3071
3072         rc = bnxt_alloc_tx_rings(bp);
3073         if (rc)
3074                 goto alloc_mem_err;
3075
3076         rc = bnxt_alloc_cp_rings(bp);
3077         if (rc)
3078                 goto alloc_mem_err;
3079
3080         bp->vnic_info[0].flags |= BNXT_VNIC_RSS_FLAG | BNXT_VNIC_MCAST_FLAG |
3081                                   BNXT_VNIC_UCAST_FLAG;
3082         rc = bnxt_alloc_vnic_attributes(bp);
3083         if (rc)
3084                 goto alloc_mem_err;
3085         return 0;
3086
3087 alloc_mem_err:
3088         bnxt_free_mem(bp, true);
3089         return rc;
3090 }
3091
3092 static void bnxt_disable_int(struct bnxt *bp)
3093 {
3094         int i;
3095
3096         if (!bp->bnapi)
3097                 return;
3098
3099         for (i = 0; i < bp->cp_nr_rings; i++) {
3100                 struct bnxt_napi *bnapi = bp->bnapi[i];
3101                 struct bnxt_cp_ring_info *cpr = &bnapi->cp_ring;
3102
3103                 BNXT_CP_DB(cpr->cp_doorbell, cpr->cp_raw_cons);
3104         }
3105 }
3106
3107 static void bnxt_disable_int_sync(struct bnxt *bp)
3108 {
3109         int i;
3110
3111         atomic_inc(&bp->intr_sem);
3112
3113         bnxt_disable_int(bp);
3114         for (i = 0; i < bp->cp_nr_rings; i++)
3115                 synchronize_irq(bp->irq_tbl[i].vector);
3116 }
3117
3118 static void bnxt_enable_int(struct bnxt *bp)
3119 {
3120         int i;
3121
3122         atomic_set(&bp->intr_sem, 0);
3123         for (i = 0; i < bp->cp_nr_rings; i++) {
3124                 struct bnxt_napi *bnapi = bp->bnapi[i];
3125                 struct bnxt_cp_ring_info *cpr = &bnapi->cp_ring;
3126
3127                 BNXT_CP_DB_REARM(cpr->cp_doorbell, cpr->cp_raw_cons);
3128         }
3129 }
3130
3131 void bnxt_hwrm_cmd_hdr_init(struct bnxt *bp, void *request, u16 req_type,
3132                             u16 cmpl_ring, u16 target_id)
3133 {
3134         struct input *req = request;
3135
3136         req->req_type = cpu_to_le16(req_type);
3137         req->cmpl_ring = cpu_to_le16(cmpl_ring);
3138         req->target_id = cpu_to_le16(target_id);
3139         req->resp_addr = cpu_to_le64(bp->hwrm_cmd_resp_dma_addr);
3140 }
3141
3142 static int bnxt_hwrm_do_send_msg(struct bnxt *bp, void *msg, u32 msg_len,
3143                                  int timeout, bool silent)
3144 {
3145         int i, intr_process, rc, tmo_count;
3146         struct input *req = msg;
3147         u32 *data = msg;
3148         __le32 *resp_len, *valid;
3149         u16 cp_ring_id, len = 0;
3150         struct hwrm_err_output *resp = bp->hwrm_cmd_resp_addr;
3151
3152         req->seq_id = cpu_to_le16(bp->hwrm_cmd_seq++);
3153         memset(resp, 0, PAGE_SIZE);
3154         cp_ring_id = le16_to_cpu(req->cmpl_ring);
3155         intr_process = (cp_ring_id == INVALID_HW_RING_ID) ? 0 : 1;
3156
3157         /* Write request msg to hwrm channel */
3158         __iowrite32_copy(bp->bar0, data, msg_len / 4);
3159
3160         for (i = msg_len; i < BNXT_HWRM_MAX_REQ_LEN; i += 4)
3161                 writel(0, bp->bar0 + i);
3162
3163         /* currently supports only one outstanding message */
3164         if (intr_process)
3165                 bp->hwrm_intr_seq_id = le16_to_cpu(req->seq_id);
3166
3167         /* Ring channel doorbell */
3168         writel(1, bp->bar0 + 0x100);
3169
3170         if (!timeout)
3171                 timeout = DFLT_HWRM_CMD_TIMEOUT;
3172
3173         i = 0;
3174         tmo_count = timeout * 40;
3175         if (intr_process) {
3176                 /* Wait until hwrm response cmpl interrupt is processed */
3177                 while (bp->hwrm_intr_seq_id != HWRM_SEQ_ID_INVALID &&
3178                        i++ < tmo_count) {
3179                         usleep_range(25, 40);
3180                 }
3181
3182                 if (bp->hwrm_intr_seq_id != HWRM_SEQ_ID_INVALID) {
3183                         netdev_err(bp->dev, "Resp cmpl intr err msg: 0x%x\n",
3184                                    le16_to_cpu(req->req_type));
3185                         return -1;
3186                 }
3187         } else {
3188                 /* Check if response len is updated */
3189                 resp_len = bp->hwrm_cmd_resp_addr + HWRM_RESP_LEN_OFFSET;
3190                 for (i = 0; i < tmo_count; i++) {
3191                         len = (le32_to_cpu(*resp_len) & HWRM_RESP_LEN_MASK) >>
3192                               HWRM_RESP_LEN_SFT;
3193                         if (len)
3194                                 break;
3195                         usleep_range(25, 40);
3196                 }
3197
3198                 if (i >= tmo_count) {
3199                         netdev_err(bp->dev, "Error (timeout: %d) msg {0x%x 0x%x} len:%d\n",
3200                                    timeout, le16_to_cpu(req->req_type),
3201                                    le16_to_cpu(req->seq_id), len);
3202                         return -1;
3203                 }
3204
3205                 /* Last word of resp contains valid bit */
3206                 valid = bp->hwrm_cmd_resp_addr + len - 4;
3207                 for (i = 0; i < 5; i++) {
3208                         if (le32_to_cpu(*valid) & HWRM_RESP_VALID_MASK)
3209                                 break;
3210                         udelay(1);
3211                 }
3212
3213                 if (i >= 5) {
3214                         netdev_err(bp->dev, "Error (timeout: %d) msg {0x%x 0x%x} len:%d v:%d\n",
3215                                    timeout, le16_to_cpu(req->req_type),
3216                                    le16_to_cpu(req->seq_id), len, *valid);
3217                         return -1;
3218                 }
3219         }
3220
3221         rc = le16_to_cpu(resp->error_code);
3222         if (rc && !silent)
3223                 netdev_err(bp->dev, "hwrm req_type 0x%x seq id 0x%x error 0x%x\n",
3224                            le16_to_cpu(resp->req_type),
3225                            le16_to_cpu(resp->seq_id), rc);
3226         return rc;
3227 }
3228
3229 int _hwrm_send_message(struct bnxt *bp, void *msg, u32 msg_len, int timeout)
3230 {
3231         return bnxt_hwrm_do_send_msg(bp, msg, msg_len, timeout, false);
3232 }
3233
3234 int hwrm_send_message(struct bnxt *bp, void *msg, u32 msg_len, int timeout)
3235 {
3236         int rc;
3237
3238         mutex_lock(&bp->hwrm_cmd_lock);
3239         rc = _hwrm_send_message(bp, msg, msg_len, timeout);
3240         mutex_unlock(&bp->hwrm_cmd_lock);
3241         return rc;
3242 }
3243
3244 int hwrm_send_message_silent(struct bnxt *bp, void *msg, u32 msg_len,
3245                              int timeout)
3246 {
3247         int rc;
3248
3249         mutex_lock(&bp->hwrm_cmd_lock);
3250         rc = bnxt_hwrm_do_send_msg(bp, msg, msg_len, timeout, true);
3251         mutex_unlock(&bp->hwrm_cmd_lock);
3252         return rc;
3253 }
3254
3255 int bnxt_hwrm_func_rgtr_async_events(struct bnxt *bp, unsigned long *bmap,
3256                                      int bmap_size)
3257 {
3258         struct hwrm_func_drv_rgtr_input req = {0};
3259         DECLARE_BITMAP(async_events_bmap, 256);
3260         u32 *events = (u32 *)async_events_bmap;
3261         int i;
3262
3263         bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_FUNC_DRV_RGTR, -1, -1);
3264
3265         req.enables =
3266                 cpu_to_le32(FUNC_DRV_RGTR_REQ_ENABLES_ASYNC_EVENT_FWD);
3267
3268         memset(async_events_bmap, 0, sizeof(async_events_bmap));
3269         for (i = 0; i < ARRAY_SIZE(bnxt_async_events_arr); i++)
3270                 __set_bit(bnxt_async_events_arr[i], async_events_bmap);
3271
3272         if (bmap && bmap_size) {
3273                 for (i = 0; i < bmap_size; i++) {
3274                         if (test_bit(i, bmap))
3275                                 __set_bit(i, async_events_bmap);
3276                 }
3277         }
3278
3279         for (i = 0; i < 8; i++)
3280                 req.async_event_fwd[i] |= cpu_to_le32(events[i]);
3281
3282         return hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT);
3283 }
3284
3285 static int bnxt_hwrm_func_drv_rgtr(struct bnxt *bp)
3286 {
3287         struct hwrm_func_drv_rgtr_input req = {0};
3288
3289         bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_FUNC_DRV_RGTR, -1, -1);
3290
3291         req.enables =
3292                 cpu_to_le32(FUNC_DRV_RGTR_REQ_ENABLES_OS_TYPE |
3293                             FUNC_DRV_RGTR_REQ_ENABLES_VER);
3294
3295         req.os_type = cpu_to_le16(FUNC_DRV_RGTR_REQ_OS_TYPE_LINUX);
3296         req.ver_maj = DRV_VER_MAJ;
3297         req.ver_min = DRV_VER_MIN;
3298         req.ver_upd = DRV_VER_UPD;
3299
3300         if (BNXT_PF(bp)) {
3301                 DECLARE_BITMAP(vf_req_snif_bmap, 256);
3302                 u32 *data = (u32 *)vf_req_snif_bmap;
3303                 int i;
3304
3305                 memset(vf_req_snif_bmap, 0, sizeof(vf_req_snif_bmap));
3306                 for (i = 0; i < ARRAY_SIZE(bnxt_vf_req_snif); i++)
3307                         __set_bit(bnxt_vf_req_snif[i], vf_req_snif_bmap);
3308
3309                 for (i = 0; i < 8; i++)
3310                         req.vf_req_fwd[i] = cpu_to_le32(data[i]);
3311
3312                 req.enables |=
3313                         cpu_to_le32(FUNC_DRV_RGTR_REQ_ENABLES_VF_REQ_FWD);
3314         }
3315
3316         return hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT);
3317 }
3318
3319 static int bnxt_hwrm_func_drv_unrgtr(struct bnxt *bp)
3320 {
3321         struct hwrm_func_drv_unrgtr_input req = {0};
3322
3323         bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_FUNC_DRV_UNRGTR, -1, -1);
3324         return hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT);
3325 }
3326
3327 static int bnxt_hwrm_tunnel_dst_port_free(struct bnxt *bp, u8 tunnel_type)
3328 {
3329         u32 rc = 0;
3330         struct hwrm_tunnel_dst_port_free_input req = {0};
3331
3332         bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_TUNNEL_DST_PORT_FREE, -1, -1);
3333         req.tunnel_type = tunnel_type;
3334
3335         switch (tunnel_type) {
3336         case TUNNEL_DST_PORT_FREE_REQ_TUNNEL_TYPE_VXLAN:
3337                 req.tunnel_dst_port_id = bp->vxlan_fw_dst_port_id;
3338                 break;
3339         case TUNNEL_DST_PORT_FREE_REQ_TUNNEL_TYPE_GENEVE:
3340                 req.tunnel_dst_port_id = bp->nge_fw_dst_port_id;
3341                 break;
3342         default:
3343                 break;
3344         }
3345
3346         rc = hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT);
3347         if (rc)
3348                 netdev_err(bp->dev, "hwrm_tunnel_dst_port_free failed. rc:%d\n",
3349                            rc);
3350         return rc;
3351 }
3352
3353 static int bnxt_hwrm_tunnel_dst_port_alloc(struct bnxt *bp, __be16 port,
3354                                            u8 tunnel_type)
3355 {
3356         u32 rc = 0;
3357         struct hwrm_tunnel_dst_port_alloc_input req = {0};
3358         struct hwrm_tunnel_dst_port_alloc_output *resp = bp->hwrm_cmd_resp_addr;
3359
3360         bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_TUNNEL_DST_PORT_ALLOC, -1, -1);
3361
3362         req.tunnel_type = tunnel_type;
3363         req.tunnel_dst_port_val = port;
3364
3365         mutex_lock(&bp->hwrm_cmd_lock);
3366         rc = _hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT);
3367         if (rc) {
3368                 netdev_err(bp->dev, "hwrm_tunnel_dst_port_alloc failed. rc:%d\n",
3369                            rc);
3370                 goto err_out;
3371         }
3372
3373         switch (tunnel_type) {
3374         case TUNNEL_DST_PORT_ALLOC_REQ_TUNNEL_TYPE_VXLAN:
3375                 bp->vxlan_fw_dst_port_id = resp->tunnel_dst_port_id;
3376                 break;
3377         case TUNNEL_DST_PORT_ALLOC_REQ_TUNNEL_TYPE_GENEVE:
3378                 bp->nge_fw_dst_port_id = resp->tunnel_dst_port_id;
3379                 break;
3380         default:
3381                 break;
3382         }
3383
3384 err_out:
3385         mutex_unlock(&bp->hwrm_cmd_lock);
3386         return rc;
3387 }
3388
3389 static int bnxt_hwrm_cfa_l2_set_rx_mask(struct bnxt *bp, u16 vnic_id)
3390 {
3391         struct hwrm_cfa_l2_set_rx_mask_input req = {0};
3392         struct bnxt_vnic_info *vnic = &bp->vnic_info[vnic_id];
3393
3394         bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_CFA_L2_SET_RX_MASK, -1, -1);
3395         req.vnic_id = cpu_to_le32(vnic->fw_vnic_id);
3396
3397         req.num_mc_entries = cpu_to_le32(vnic->mc_list_count);
3398         req.mc_tbl_addr = cpu_to_le64(vnic->mc_list_mapping);
3399         req.mask = cpu_to_le32(vnic->rx_mask);
3400         return hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT);
3401 }
3402
3403 #ifdef CONFIG_RFS_ACCEL
3404 static int bnxt_hwrm_cfa_ntuple_filter_free(struct bnxt *bp,
3405                                             struct bnxt_ntuple_filter *fltr)
3406 {
3407         struct hwrm_cfa_ntuple_filter_free_input req = {0};
3408
3409         bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_CFA_NTUPLE_FILTER_FREE, -1, -1);
3410         req.ntuple_filter_id = fltr->filter_id;
3411         return hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT);
3412 }
3413
3414 #define BNXT_NTP_FLTR_FLAGS                                     \
3415         (CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_L2_FILTER_ID |     \
3416          CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_ETHERTYPE |        \
3417          CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_SRC_MACADDR |      \
3418          CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_IPADDR_TYPE |      \
3419          CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_SRC_IPADDR |       \
3420          CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_SRC_IPADDR_MASK |  \
3421          CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_DST_IPADDR |       \
3422          CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_DST_IPADDR_MASK |  \
3423          CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_IP_PROTOCOL |      \
3424          CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_SRC_PORT |         \
3425          CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_SRC_PORT_MASK |    \
3426          CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_DST_PORT |         \
3427          CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_DST_PORT_MASK |    \
3428          CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_DST_ID)
3429
3430 static int bnxt_hwrm_cfa_ntuple_filter_alloc(struct bnxt *bp,
3431                                              struct bnxt_ntuple_filter *fltr)
3432 {
3433         int rc = 0;
3434         struct hwrm_cfa_ntuple_filter_alloc_input req = {0};
3435         struct hwrm_cfa_ntuple_filter_alloc_output *resp =
3436                 bp->hwrm_cmd_resp_addr;
3437         struct flow_keys *keys = &fltr->fkeys;
3438         struct bnxt_vnic_info *vnic = &bp->vnic_info[fltr->rxq + 1];
3439
3440         bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_CFA_NTUPLE_FILTER_ALLOC, -1, -1);
3441         req.l2_filter_id = bp->vnic_info[0].fw_l2_filter_id[fltr->l2_fltr_idx];
3442
3443         req.enables = cpu_to_le32(BNXT_NTP_FLTR_FLAGS);
3444
3445         req.ethertype = htons(ETH_P_IP);
3446         memcpy(req.src_macaddr, fltr->src_mac_addr, ETH_ALEN);
3447         req.ip_addr_type = CFA_NTUPLE_FILTER_ALLOC_REQ_IP_ADDR_TYPE_IPV4;
3448         req.ip_protocol = keys->basic.ip_proto;
3449
3450         if (keys->basic.n_proto == htons(ETH_P_IPV6)) {
3451                 int i;
3452
3453                 req.ethertype = htons(ETH_P_IPV6);
3454                 req.ip_addr_type =
3455                         CFA_NTUPLE_FILTER_ALLOC_REQ_IP_ADDR_TYPE_IPV6;
3456                 *(struct in6_addr *)&req.src_ipaddr[0] =
3457                         keys->addrs.v6addrs.src;
3458                 *(struct in6_addr *)&req.dst_ipaddr[0] =
3459                         keys->addrs.v6addrs.dst;
3460                 for (i = 0; i < 4; i++) {
3461                         req.src_ipaddr_mask[i] = cpu_to_be32(0xffffffff);
3462                         req.dst_ipaddr_mask[i] = cpu_to_be32(0xffffffff);
3463                 }
3464         } else {
3465                 req.src_ipaddr[0] = keys->addrs.v4addrs.src;
3466                 req.src_ipaddr_mask[0] = cpu_to_be32(0xffffffff);
3467                 req.dst_ipaddr[0] = keys->addrs.v4addrs.dst;
3468                 req.dst_ipaddr_mask[0] = cpu_to_be32(0xffffffff);
3469         }
3470
3471         req.src_port = keys->ports.src;
3472         req.src_port_mask = cpu_to_be16(0xffff);
3473         req.dst_port = keys->ports.dst;
3474         req.dst_port_mask = cpu_to_be16(0xffff);
3475
3476         req.dst_id = cpu_to_le16(vnic->fw_vnic_id);
3477         mutex_lock(&bp->hwrm_cmd_lock);
3478         rc = _hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT);
3479         if (!rc)
3480                 fltr->filter_id = resp->ntuple_filter_id;
3481         mutex_unlock(&bp->hwrm_cmd_lock);
3482         return rc;
3483 }
3484 #endif
3485
3486 static int bnxt_hwrm_set_vnic_filter(struct bnxt *bp, u16 vnic_id, u16 idx,
3487                                      u8 *mac_addr)
3488 {
3489         u32 rc = 0;
3490         struct hwrm_cfa_l2_filter_alloc_input req = {0};
3491         struct hwrm_cfa_l2_filter_alloc_output *resp = bp->hwrm_cmd_resp_addr;
3492
3493         bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_CFA_L2_FILTER_ALLOC, -1, -1);
3494         req.flags = cpu_to_le32(CFA_L2_FILTER_ALLOC_REQ_FLAGS_PATH_RX);
3495         if (!BNXT_CHIP_TYPE_NITRO_A0(bp))
3496                 req.flags |=
3497                         cpu_to_le32(CFA_L2_FILTER_ALLOC_REQ_FLAGS_OUTERMOST);
3498         req.dst_id = cpu_to_le16(bp->vnic_info[vnic_id].fw_vnic_id);
3499         req.enables =
3500                 cpu_to_le32(CFA_L2_FILTER_ALLOC_REQ_ENABLES_L2_ADDR |
3501                             CFA_L2_FILTER_ALLOC_REQ_ENABLES_DST_ID |
3502                             CFA_L2_FILTER_ALLOC_REQ_ENABLES_L2_ADDR_MASK);
3503         memcpy(req.l2_addr, mac_addr, ETH_ALEN);
3504         req.l2_addr_mask[0] = 0xff;
3505         req.l2_addr_mask[1] = 0xff;
3506         req.l2_addr_mask[2] = 0xff;
3507         req.l2_addr_mask[3] = 0xff;
3508         req.l2_addr_mask[4] = 0xff;
3509         req.l2_addr_mask[5] = 0xff;
3510
3511         mutex_lock(&bp->hwrm_cmd_lock);
3512         rc = _hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT);
3513         if (!rc)
3514                 bp->vnic_info[vnic_id].fw_l2_filter_id[idx] =
3515                                                         resp->l2_filter_id;
3516         mutex_unlock(&bp->hwrm_cmd_lock);
3517         return rc;
3518 }
3519
3520 static int bnxt_hwrm_clear_vnic_filter(struct bnxt *bp)
3521 {
3522         u16 i, j, num_of_vnics = 1; /* only vnic 0 supported */
3523         int rc = 0;
3524
3525         /* Any associated ntuple filters will also be cleared by firmware. */
3526         mutex_lock(&bp->hwrm_cmd_lock);
3527         for (i = 0; i < num_of_vnics; i++) {
3528                 struct bnxt_vnic_info *vnic = &bp->vnic_info[i];
3529
3530                 for (j = 0; j < vnic->uc_filter_count; j++) {
3531                         struct hwrm_cfa_l2_filter_free_input req = {0};
3532
3533                         bnxt_hwrm_cmd_hdr_init(bp, &req,
3534                                                HWRM_CFA_L2_FILTER_FREE, -1, -1);
3535
3536                         req.l2_filter_id = vnic->fw_l2_filter_id[j];
3537
3538                         rc = _hwrm_send_message(bp, &req, sizeof(req),
3539                                                 HWRM_CMD_TIMEOUT);
3540                 }
3541                 vnic->uc_filter_count = 0;
3542         }
3543         mutex_unlock(&bp->hwrm_cmd_lock);
3544
3545         return rc;
3546 }
3547
3548 static int bnxt_hwrm_vnic_set_tpa(struct bnxt *bp, u16 vnic_id, u32 tpa_flags)
3549 {
3550         struct bnxt_vnic_info *vnic = &bp->vnic_info[vnic_id];
3551         struct hwrm_vnic_tpa_cfg_input req = {0};
3552
3553         bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_VNIC_TPA_CFG, -1, -1);
3554
3555         if (tpa_flags) {
3556                 u16 mss = bp->dev->mtu - 40;
3557                 u32 nsegs, n, segs = 0, flags;
3558
3559                 flags = VNIC_TPA_CFG_REQ_FLAGS_TPA |
3560                         VNIC_TPA_CFG_REQ_FLAGS_ENCAP_TPA |
3561                         VNIC_TPA_CFG_REQ_FLAGS_RSC_WND_UPDATE |
3562                         VNIC_TPA_CFG_REQ_FLAGS_AGG_WITH_ECN |
3563                         VNIC_TPA_CFG_REQ_FLAGS_AGG_WITH_SAME_GRE_SEQ;
3564                 if (tpa_flags & BNXT_FLAG_GRO)
3565                         flags |= VNIC_TPA_CFG_REQ_FLAGS_GRO;
3566
3567                 req.flags = cpu_to_le32(flags);
3568
3569                 req.enables =
3570                         cpu_to_le32(VNIC_TPA_CFG_REQ_ENABLES_MAX_AGG_SEGS |
3571                                     VNIC_TPA_CFG_REQ_ENABLES_MAX_AGGS |
3572                                     VNIC_TPA_CFG_REQ_ENABLES_MIN_AGG_LEN);
3573
3574                 /* Number of segs are log2 units, and first packet is not
3575                  * included as part of this units.
3576                  */
3577                 if (mss <= BNXT_RX_PAGE_SIZE) {
3578                         n = BNXT_RX_PAGE_SIZE / mss;
3579                         nsegs = (MAX_SKB_FRAGS - 1) * n;
3580                 } else {
3581                         n = mss / BNXT_RX_PAGE_SIZE;
3582                         if (mss & (BNXT_RX_PAGE_SIZE - 1))
3583                                 n++;
3584                         nsegs = (MAX_SKB_FRAGS - n) / n;
3585                 }
3586
3587                 segs = ilog2(nsegs);
3588                 req.max_agg_segs = cpu_to_le16(segs);
3589                 req.max_aggs = cpu_to_le16(VNIC_TPA_CFG_REQ_MAX_AGGS_MAX);
3590
3591                 req.min_agg_len = cpu_to_le32(512);
3592         }
3593         req.vnic_id = cpu_to_le16(vnic->fw_vnic_id);
3594
3595         return hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT);
3596 }
3597
3598 static int bnxt_hwrm_vnic_set_rss(struct bnxt *bp, u16 vnic_id, bool set_rss)
3599 {
3600         u32 i, j, max_rings;
3601         struct bnxt_vnic_info *vnic = &bp->vnic_info[vnic_id];
3602         struct hwrm_vnic_rss_cfg_input req = {0};
3603
3604         if (vnic->fw_rss_cos_lb_ctx[0] == INVALID_HW_RING_ID)
3605                 return 0;
3606
3607         bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_VNIC_RSS_CFG, -1, -1);
3608         if (set_rss) {
3609                 req.hash_type = cpu_to_le32(bp->rss_hash_cfg);
3610                 if (vnic->flags & BNXT_VNIC_RSS_FLAG) {
3611                         if (BNXT_CHIP_TYPE_NITRO_A0(bp))
3612                                 max_rings = bp->rx_nr_rings - 1;
3613                         else
3614                                 max_rings = bp->rx_nr_rings;
3615                 } else {
3616                         max_rings = 1;
3617                 }
3618
3619                 /* Fill the RSS indirection table with ring group ids */
3620                 for (i = 0, j = 0; i < HW_HASH_INDEX_SIZE; i++, j++) {
3621                         if (j == max_rings)
3622                                 j = 0;
3623                         vnic->rss_table[i] = cpu_to_le16(vnic->fw_grp_ids[j]);
3624                 }
3625
3626                 req.ring_grp_tbl_addr = cpu_to_le64(vnic->rss_table_dma_addr);
3627                 req.hash_key_tbl_addr =
3628                         cpu_to_le64(vnic->rss_hash_key_dma_addr);
3629         }
3630         req.rss_ctx_idx = cpu_to_le16(vnic->fw_rss_cos_lb_ctx[0]);
3631         return hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT);
3632 }
3633
3634 static int bnxt_hwrm_vnic_set_hds(struct bnxt *bp, u16 vnic_id)
3635 {
3636         struct bnxt_vnic_info *vnic = &bp->vnic_info[vnic_id];
3637         struct hwrm_vnic_plcmodes_cfg_input req = {0};
3638
3639         bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_VNIC_PLCMODES_CFG, -1, -1);
3640         req.flags = cpu_to_le32(VNIC_PLCMODES_CFG_REQ_FLAGS_JUMBO_PLACEMENT |
3641                                 VNIC_PLCMODES_CFG_REQ_FLAGS_HDS_IPV4 |
3642                                 VNIC_PLCMODES_CFG_REQ_FLAGS_HDS_IPV6);
3643         req.enables =
3644                 cpu_to_le32(VNIC_PLCMODES_CFG_REQ_ENABLES_JUMBO_THRESH_VALID |
3645                             VNIC_PLCMODES_CFG_REQ_ENABLES_HDS_THRESHOLD_VALID);
3646         /* thresholds not implemented in firmware yet */
3647         req.jumbo_thresh = cpu_to_le16(bp->rx_copy_thresh);
3648         req.hds_threshold = cpu_to_le16(bp->rx_copy_thresh);
3649         req.vnic_id = cpu_to_le32(vnic->fw_vnic_id);
3650         return hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT);
3651 }
3652
3653 static void bnxt_hwrm_vnic_ctx_free_one(struct bnxt *bp, u16 vnic_id,
3654                                         u16 ctx_idx)
3655 {
3656         struct hwrm_vnic_rss_cos_lb_ctx_free_input req = {0};
3657
3658         bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_VNIC_RSS_COS_LB_CTX_FREE, -1, -1);
3659         req.rss_cos_lb_ctx_id =
3660                 cpu_to_le16(bp->vnic_info[vnic_id].fw_rss_cos_lb_ctx[ctx_idx]);
3661
3662         hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT);
3663         bp->vnic_info[vnic_id].fw_rss_cos_lb_ctx[ctx_idx] = INVALID_HW_RING_ID;
3664 }
3665
3666 static void bnxt_hwrm_vnic_ctx_free(struct bnxt *bp)
3667 {
3668         int i, j;
3669
3670         for (i = 0; i < bp->nr_vnics; i++) {
3671                 struct bnxt_vnic_info *vnic = &bp->vnic_info[i];
3672
3673                 for (j = 0; j < BNXT_MAX_CTX_PER_VNIC; j++) {
3674                         if (vnic->fw_rss_cos_lb_ctx[j] != INVALID_HW_RING_ID)
3675                                 bnxt_hwrm_vnic_ctx_free_one(bp, i, j);
3676                 }
3677         }
3678         bp->rsscos_nr_ctxs = 0;
3679 }
3680
3681 static int bnxt_hwrm_vnic_ctx_alloc(struct bnxt *bp, u16 vnic_id, u16 ctx_idx)
3682 {
3683         int rc;
3684         struct hwrm_vnic_rss_cos_lb_ctx_alloc_input req = {0};
3685         struct hwrm_vnic_rss_cos_lb_ctx_alloc_output *resp =
3686                                                 bp->hwrm_cmd_resp_addr;
3687
3688         bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_VNIC_RSS_COS_LB_CTX_ALLOC, -1,
3689                                -1);
3690
3691         mutex_lock(&bp->hwrm_cmd_lock);
3692         rc = _hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT);
3693         if (!rc)
3694                 bp->vnic_info[vnic_id].fw_rss_cos_lb_ctx[ctx_idx] =
3695                         le16_to_cpu(resp->rss_cos_lb_ctx_id);
3696         mutex_unlock(&bp->hwrm_cmd_lock);
3697
3698         return rc;
3699 }
3700
3701 int bnxt_hwrm_vnic_cfg(struct bnxt *bp, u16 vnic_id)
3702 {
3703         unsigned int ring = 0, grp_idx;
3704         struct bnxt_vnic_info *vnic = &bp->vnic_info[vnic_id];
3705         struct hwrm_vnic_cfg_input req = {0};
3706         u16 def_vlan = 0;
3707
3708         bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_VNIC_CFG, -1, -1);
3709
3710         req.enables = cpu_to_le32(VNIC_CFG_REQ_ENABLES_DFLT_RING_GRP);
3711         /* Only RSS support for now TBD: COS & LB */
3712         if (vnic->fw_rss_cos_lb_ctx[0] != INVALID_HW_RING_ID) {
3713                 req.rss_rule = cpu_to_le16(vnic->fw_rss_cos_lb_ctx[0]);
3714                 req.enables |= cpu_to_le32(VNIC_CFG_REQ_ENABLES_RSS_RULE |
3715                                            VNIC_CFG_REQ_ENABLES_MRU);
3716         } else if (vnic->flags & BNXT_VNIC_RFS_NEW_RSS_FLAG) {
3717                 req.rss_rule =
3718                         cpu_to_le16(bp->vnic_info[0].fw_rss_cos_lb_ctx[0]);
3719                 req.enables |= cpu_to_le32(VNIC_CFG_REQ_ENABLES_RSS_RULE |
3720                                            VNIC_CFG_REQ_ENABLES_MRU);
3721                 req.flags |= cpu_to_le32(VNIC_CFG_REQ_FLAGS_RSS_DFLT_CR_MODE);
3722         } else {
3723                 req.rss_rule = cpu_to_le16(0xffff);
3724         }
3725
3726         if (BNXT_CHIP_TYPE_NITRO_A0(bp) &&
3727             (vnic->fw_rss_cos_lb_ctx[0] != INVALID_HW_RING_ID)) {
3728                 req.cos_rule = cpu_to_le16(vnic->fw_rss_cos_lb_ctx[1]);
3729                 req.enables |= cpu_to_le32(VNIC_CFG_REQ_ENABLES_COS_RULE);
3730         } else {
3731                 req.cos_rule = cpu_to_le16(0xffff);
3732         }
3733
3734         if (vnic->flags & BNXT_VNIC_RSS_FLAG)
3735                 ring = 0;
3736         else if (vnic->flags & BNXT_VNIC_RFS_FLAG)
3737                 ring = vnic_id - 1;
3738         else if ((vnic_id == 1) && BNXT_CHIP_TYPE_NITRO_A0(bp))
3739                 ring = bp->rx_nr_rings - 1;
3740
3741         grp_idx = bp->rx_ring[ring].bnapi->index;
3742         req.vnic_id = cpu_to_le16(vnic->fw_vnic_id);
3743         req.dflt_ring_grp = cpu_to_le16(bp->grp_info[grp_idx].fw_grp_id);
3744
3745         req.lb_rule = cpu_to_le16(0xffff);
3746         req.mru = cpu_to_le16(bp->dev->mtu + ETH_HLEN + ETH_FCS_LEN +
3747                               VLAN_HLEN);
3748
3749 #ifdef CONFIG_BNXT_SRIOV
3750         if (BNXT_VF(bp))
3751                 def_vlan = bp->vf.vlan;
3752 #endif
3753         if ((bp->flags & BNXT_FLAG_STRIP_VLAN) || def_vlan)
3754                 req.flags |= cpu_to_le32(VNIC_CFG_REQ_FLAGS_VLAN_STRIP_MODE);
3755         if (!vnic_id && bnxt_ulp_registered(bp->edev, BNXT_ROCE_ULP))
3756                 req.flags |=
3757                         cpu_to_le32(VNIC_CFG_REQ_FLAGS_ROCE_DUAL_VNIC_MODE);
3758
3759         return hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT);
3760 }
3761
3762 static int bnxt_hwrm_vnic_free_one(struct bnxt *bp, u16 vnic_id)
3763 {
3764         u32 rc = 0;
3765
3766         if (bp->vnic_info[vnic_id].fw_vnic_id != INVALID_HW_RING_ID) {
3767                 struct hwrm_vnic_free_input req = {0};
3768
3769                 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_VNIC_FREE, -1, -1);
3770                 req.vnic_id =
3771                         cpu_to_le32(bp->vnic_info[vnic_id].fw_vnic_id);
3772
3773                 rc = hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT);
3774                 if (rc)
3775                         return rc;
3776                 bp->vnic_info[vnic_id].fw_vnic_id = INVALID_HW_RING_ID;
3777         }
3778         return rc;
3779 }
3780
3781 static void bnxt_hwrm_vnic_free(struct bnxt *bp)
3782 {
3783         u16 i;
3784
3785         for (i = 0; i < bp->nr_vnics; i++)
3786                 bnxt_hwrm_vnic_free_one(bp, i);
3787 }
3788
3789 static int bnxt_hwrm_vnic_alloc(struct bnxt *bp, u16 vnic_id,
3790                                 unsigned int start_rx_ring_idx,
3791                                 unsigned int nr_rings)
3792 {
3793         int rc = 0;
3794         unsigned int i, j, grp_idx, end_idx = start_rx_ring_idx + nr_rings;
3795         struct hwrm_vnic_alloc_input req = {0};
3796         struct hwrm_vnic_alloc_output *resp = bp->hwrm_cmd_resp_addr;
3797
3798         /* map ring groups to this vnic */
3799         for (i = start_rx_ring_idx, j = 0; i < end_idx; i++, j++) {
3800                 grp_idx = bp->rx_ring[i].bnapi->index;
3801                 if (bp->grp_info[grp_idx].fw_grp_id == INVALID_HW_RING_ID) {
3802                         netdev_err(bp->dev, "Not enough ring groups avail:%x req:%x\n",
3803                                    j, nr_rings);
3804                         break;
3805                 }
3806                 bp->vnic_info[vnic_id].fw_grp_ids[j] =
3807                                         bp->grp_info[grp_idx].fw_grp_id;
3808         }
3809
3810         bp->vnic_info[vnic_id].fw_rss_cos_lb_ctx[0] = INVALID_HW_RING_ID;
3811         bp->vnic_info[vnic_id].fw_rss_cos_lb_ctx[1] = INVALID_HW_RING_ID;
3812         if (vnic_id == 0)
3813                 req.flags = cpu_to_le32(VNIC_ALLOC_REQ_FLAGS_DEFAULT);
3814
3815         bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_VNIC_ALLOC, -1, -1);
3816
3817         mutex_lock(&bp->hwrm_cmd_lock);
3818         rc = _hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT);
3819         if (!rc)
3820                 bp->vnic_info[vnic_id].fw_vnic_id = le32_to_cpu(resp->vnic_id);
3821         mutex_unlock(&bp->hwrm_cmd_lock);
3822         return rc;
3823 }
3824
3825 static int bnxt_hwrm_vnic_qcaps(struct bnxt *bp)
3826 {
3827         struct hwrm_vnic_qcaps_output *resp = bp->hwrm_cmd_resp_addr;
3828         struct hwrm_vnic_qcaps_input req = {0};
3829         int rc;
3830
3831         if (bp->hwrm_spec_code < 0x10600)
3832                 return 0;
3833
3834         bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_VNIC_QCAPS, -1, -1);
3835         mutex_lock(&bp->hwrm_cmd_lock);
3836         rc = _hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT);
3837         if (!rc) {
3838                 if (resp->flags &
3839                     cpu_to_le32(VNIC_QCAPS_RESP_FLAGS_RSS_DFLT_CR_CAP))
3840                         bp->flags |= BNXT_FLAG_NEW_RSS_CAP;
3841         }
3842         mutex_unlock(&bp->hwrm_cmd_lock);
3843         return rc;
3844 }
3845
3846 static int bnxt_hwrm_ring_grp_alloc(struct bnxt *bp)
3847 {
3848         u16 i;
3849         u32 rc = 0;
3850
3851         mutex_lock(&bp->hwrm_cmd_lock);
3852         for (i = 0; i < bp->rx_nr_rings; i++) {
3853                 struct hwrm_ring_grp_alloc_input req = {0};
3854                 struct hwrm_ring_grp_alloc_output *resp =
3855                                         bp->hwrm_cmd_resp_addr;
3856                 unsigned int grp_idx = bp->rx_ring[i].bnapi->index;
3857
3858                 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_RING_GRP_ALLOC, -1, -1);
3859
3860                 req.cr = cpu_to_le16(bp->grp_info[grp_idx].cp_fw_ring_id);
3861                 req.rr = cpu_to_le16(bp->grp_info[grp_idx].rx_fw_ring_id);
3862                 req.ar = cpu_to_le16(bp->grp_info[grp_idx].agg_fw_ring_id);
3863                 req.sc = cpu_to_le16(bp->grp_info[grp_idx].fw_stats_ctx);
3864
3865                 rc = _hwrm_send_message(bp, &req, sizeof(req),
3866                                         HWRM_CMD_TIMEOUT);
3867                 if (rc)
3868                         break;
3869
3870                 bp->grp_info[grp_idx].fw_grp_id =
3871                         le32_to_cpu(resp->ring_group_id);
3872         }
3873         mutex_unlock(&bp->hwrm_cmd_lock);
3874         return rc;
3875 }
3876
3877 static int bnxt_hwrm_ring_grp_free(struct bnxt *bp)
3878 {
3879         u16 i;
3880         u32 rc = 0;
3881         struct hwrm_ring_grp_free_input req = {0};
3882
3883         if (!bp->grp_info)
3884                 return 0;
3885
3886         bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_RING_GRP_FREE, -1, -1);
3887
3888         mutex_lock(&bp->hwrm_cmd_lock);
3889         for (i = 0; i < bp->cp_nr_rings; i++) {
3890                 if (bp->grp_info[i].fw_grp_id == INVALID_HW_RING_ID)
3891                         continue;
3892                 req.ring_group_id =
3893                         cpu_to_le32(bp->grp_info[i].fw_grp_id);
3894
3895                 rc = _hwrm_send_message(bp, &req, sizeof(req),
3896                                         HWRM_CMD_TIMEOUT);
3897                 if (rc)
3898                         break;
3899                 bp->grp_info[i].fw_grp_id = INVALID_HW_RING_ID;
3900         }
3901         mutex_unlock(&bp->hwrm_cmd_lock);
3902         return rc;
3903 }
3904
3905 static int hwrm_ring_alloc_send_msg(struct bnxt *bp,
3906                                     struct bnxt_ring_struct *ring,
3907                                     u32 ring_type, u32 map_index,
3908                                     u32 stats_ctx_id)
3909 {
3910         int rc = 0, err = 0;
3911         struct hwrm_ring_alloc_input req = {0};
3912         struct hwrm_ring_alloc_output *resp = bp->hwrm_cmd_resp_addr;
3913         u16 ring_id;
3914
3915         bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_RING_ALLOC, -1, -1);
3916
3917         req.enables = 0;
3918         if (ring->nr_pages > 1) {
3919                 req.page_tbl_addr = cpu_to_le64(ring->pg_tbl_map);
3920                 /* Page size is in log2 units */
3921                 req.page_size = BNXT_PAGE_SHIFT;
3922                 req.page_tbl_depth = 1;
3923         } else {
3924                 req.page_tbl_addr =  cpu_to_le64(ring->dma_arr[0]);
3925         }
3926         req.fbo = 0;
3927         /* Association of ring index with doorbell index and MSIX number */
3928         req.logical_id = cpu_to_le16(map_index);
3929
3930         switch (ring_type) {
3931         case HWRM_RING_ALLOC_TX:
3932                 req.ring_type = RING_ALLOC_REQ_RING_TYPE_TX;
3933                 /* Association of transmit ring with completion ring */
3934                 req.cmpl_ring_id =
3935                         cpu_to_le16(bp->grp_info[map_index].cp_fw_ring_id);
3936                 req.length = cpu_to_le32(bp->tx_ring_mask + 1);
3937                 req.stat_ctx_id = cpu_to_le32(stats_ctx_id);
3938                 req.queue_id = cpu_to_le16(ring->queue_id);
3939                 break;
3940         case HWRM_RING_ALLOC_RX:
3941                 req.ring_type = RING_ALLOC_REQ_RING_TYPE_RX;
3942                 req.length = cpu_to_le32(bp->rx_ring_mask + 1);
3943                 break;
3944         case HWRM_RING_ALLOC_AGG:
3945                 req.ring_type = RING_ALLOC_REQ_RING_TYPE_RX;
3946                 req.length = cpu_to_le32(bp->rx_agg_ring_mask + 1);
3947                 break;
3948         case HWRM_RING_ALLOC_CMPL:
3949                 req.ring_type = RING_ALLOC_REQ_RING_TYPE_CMPL;
3950                 req.length = cpu_to_le32(bp->cp_ring_mask + 1);
3951                 if (bp->flags & BNXT_FLAG_USING_MSIX)
3952                         req.int_mode = RING_ALLOC_REQ_INT_MODE_MSIX;
3953                 break;
3954         default:
3955                 netdev_err(bp->dev, "hwrm alloc invalid ring type %d\n",
3956                            ring_type);
3957                 return -1;
3958         }
3959
3960         mutex_lock(&bp->hwrm_cmd_lock);
3961         rc = _hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT);
3962         err = le16_to_cpu(resp->error_code);
3963         ring_id = le16_to_cpu(resp->ring_id);
3964         mutex_unlock(&bp->hwrm_cmd_lock);
3965
3966         if (rc || err) {
3967                 switch (ring_type) {
3968                 case RING_FREE_REQ_RING_TYPE_CMPL:
3969                         netdev_err(bp->dev, "hwrm_ring_alloc cp failed. rc:%x err:%x\n",
3970                                    rc, err);
3971                         return -1;
3972
3973                 case RING_FREE_REQ_RING_TYPE_RX:
3974                         netdev_err(bp->dev, "hwrm_ring_alloc rx failed. rc:%x err:%x\n",
3975                                    rc, err);
3976                         return -1;
3977
3978                 case RING_FREE_REQ_RING_TYPE_TX:
3979                         netdev_err(bp->dev, "hwrm_ring_alloc tx failed. rc:%x err:%x\n",
3980                                    rc, err);
3981                         return -1;
3982
3983                 default:
3984                         netdev_err(bp->dev, "Invalid ring\n");
3985                         return -1;
3986                 }
3987         }
3988         ring->fw_ring_id = ring_id;
3989         return rc;
3990 }
3991
3992 static int bnxt_hwrm_set_async_event_cr(struct bnxt *bp, int idx)
3993 {
3994         int rc;
3995
3996         if (BNXT_PF(bp)) {
3997                 struct hwrm_func_cfg_input req = {0};
3998
3999                 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_FUNC_CFG, -1, -1);
4000                 req.fid = cpu_to_le16(0xffff);
4001                 req.enables = cpu_to_le32(FUNC_CFG_REQ_ENABLES_ASYNC_EVENT_CR);
4002                 req.async_event_cr = cpu_to_le16(idx);
4003                 rc = hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT);
4004         } else {
4005                 struct hwrm_func_vf_cfg_input req = {0};
4006
4007                 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_FUNC_VF_CFG, -1, -1);
4008                 req.enables =
4009                         cpu_to_le32(FUNC_VF_CFG_REQ_ENABLES_ASYNC_EVENT_CR);
4010                 req.async_event_cr = cpu_to_le16(idx);
4011                 rc = hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT);
4012         }
4013         return rc;
4014 }
4015
4016 static int bnxt_hwrm_ring_alloc(struct bnxt *bp)
4017 {
4018         int i, rc = 0;
4019
4020         for (i = 0; i < bp->cp_nr_rings; i++) {
4021                 struct bnxt_napi *bnapi = bp->bnapi[i];
4022                 struct bnxt_cp_ring_info *cpr = &bnapi->cp_ring;
4023                 struct bnxt_ring_struct *ring = &cpr->cp_ring_struct;
4024
4025                 cpr->cp_doorbell = bp->bar1 + i * 0x80;
4026                 rc = hwrm_ring_alloc_send_msg(bp, ring, HWRM_RING_ALLOC_CMPL, i,
4027                                               INVALID_STATS_CTX_ID);
4028                 if (rc)
4029                         goto err_out;
4030                 BNXT_CP_DB(cpr->cp_doorbell, cpr->cp_raw_cons);
4031                 bp->grp_info[i].cp_fw_ring_id = ring->fw_ring_id;
4032
4033                 if (!i) {
4034                         rc = bnxt_hwrm_set_async_event_cr(bp, ring->fw_ring_id);
4035                         if (rc)
4036                                 netdev_warn(bp->dev, "Failed to set async event completion ring.\n");
4037                 }
4038         }
4039
4040         for (i = 0; i < bp->tx_nr_rings; i++) {
4041                 struct bnxt_tx_ring_info *txr = &bp->tx_ring[i];
4042                 struct bnxt_ring_struct *ring = &txr->tx_ring_struct;
4043                 u32 map_idx = txr->bnapi->index;
4044                 u16 fw_stats_ctx = bp->grp_info[map_idx].fw_stats_ctx;
4045
4046                 rc = hwrm_ring_alloc_send_msg(bp, ring, HWRM_RING_ALLOC_TX,
4047                                               map_idx, fw_stats_ctx);
4048                 if (rc)
4049                         goto err_out;
4050                 txr->tx_doorbell = bp->bar1 + map_idx * 0x80;
4051         }
4052
4053         for (i = 0; i < bp->rx_nr_rings; i++) {
4054                 struct bnxt_rx_ring_info *rxr = &bp->rx_ring[i];
4055                 struct bnxt_ring_struct *ring = &rxr->rx_ring_struct;
4056                 u32 map_idx = rxr->bnapi->index;
4057
4058                 rc = hwrm_ring_alloc_send_msg(bp, ring, HWRM_RING_ALLOC_RX,
4059                                               map_idx, INVALID_STATS_CTX_ID);
4060                 if (rc)
4061                         goto err_out;
4062                 rxr->rx_doorbell = bp->bar1 + map_idx * 0x80;
4063                 writel(DB_KEY_RX | rxr->rx_prod, rxr->rx_doorbell);
4064                 bp->grp_info[map_idx].rx_fw_ring_id = ring->fw_ring_id;
4065         }
4066
4067         if (bp->flags & BNXT_FLAG_AGG_RINGS) {
4068                 for (i = 0; i < bp->rx_nr_rings; i++) {
4069                         struct bnxt_rx_ring_info *rxr = &bp->rx_ring[i];
4070                         struct bnxt_ring_struct *ring =
4071                                                 &rxr->rx_agg_ring_struct;
4072                         u32 grp_idx = rxr->bnapi->index;
4073                         u32 map_idx = grp_idx + bp->rx_nr_rings;
4074
4075                         rc = hwrm_ring_alloc_send_msg(bp, ring,
4076                                                       HWRM_RING_ALLOC_AGG,
4077                                                       map_idx,
4078                                                       INVALID_STATS_CTX_ID);
4079                         if (rc)
4080                                 goto err_out;
4081
4082                         rxr->rx_agg_doorbell = bp->bar1 + map_idx * 0x80;
4083                         writel(DB_KEY_RX | rxr->rx_agg_prod,
4084                                rxr->rx_agg_doorbell);
4085                         bp->grp_info[grp_idx].agg_fw_ring_id = ring->fw_ring_id;
4086                 }
4087         }
4088 err_out:
4089         return rc;
4090 }
4091
4092 static int hwrm_ring_free_send_msg(struct bnxt *bp,
4093                                    struct bnxt_ring_struct *ring,
4094                                    u32 ring_type, int cmpl_ring_id)
4095 {
4096         int rc;
4097         struct hwrm_ring_free_input req = {0};
4098         struct hwrm_ring_free_output *resp = bp->hwrm_cmd_resp_addr;
4099         u16 error_code;
4100
4101         bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_RING_FREE, cmpl_ring_id, -1);
4102         req.ring_type = ring_type;
4103         req.ring_id = cpu_to_le16(ring->fw_ring_id);
4104
4105         mutex_lock(&bp->hwrm_cmd_lock);
4106         rc = _hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT);
4107         error_code = le16_to_cpu(resp->error_code);
4108         mutex_unlock(&bp->hwrm_cmd_lock);
4109
4110         if (rc || error_code) {
4111                 switch (ring_type) {
4112                 case RING_FREE_REQ_RING_TYPE_CMPL:
4113                         netdev_err(bp->dev, "hwrm_ring_free cp failed. rc:%d\n",
4114                                    rc);
4115                         return rc;
4116                 case RING_FREE_REQ_RING_TYPE_RX:
4117                         netdev_err(bp->dev, "hwrm_ring_free rx failed. rc:%d\n",
4118                                    rc);
4119                         return rc;
4120                 case RING_FREE_REQ_RING_TYPE_TX:
4121                         netdev_err(bp->dev, "hwrm_ring_free tx failed. rc:%d\n",
4122                                    rc);
4123                         return rc;
4124                 default:
4125                         netdev_err(bp->dev, "Invalid ring\n");
4126                         return -1;
4127                 }
4128         }
4129         return 0;
4130 }
4131
4132 static void bnxt_hwrm_ring_free(struct bnxt *bp, bool close_path)
4133 {
4134         int i;
4135
4136         if (!bp->bnapi)
4137                 return;
4138
4139         for (i = 0; i < bp->tx_nr_rings; i++) {
4140                 struct bnxt_tx_ring_info *txr = &bp->tx_ring[i];
4141                 struct bnxt_ring_struct *ring = &txr->tx_ring_struct;
4142                 u32 grp_idx = txr->bnapi->index;
4143                 u32 cmpl_ring_id = bp->grp_info[grp_idx].cp_fw_ring_id;
4144
4145                 if (ring->fw_ring_id != INVALID_HW_RING_ID) {
4146                         hwrm_ring_free_send_msg(bp, ring,
4147                                                 RING_FREE_REQ_RING_TYPE_TX,
4148                                                 close_path ? cmpl_ring_id :
4149                                                 INVALID_HW_RING_ID);
4150                         ring->fw_ring_id = INVALID_HW_RING_ID;
4151                 }
4152         }
4153
4154         for (i = 0; i < bp->rx_nr_rings; i++) {
4155                 struct bnxt_rx_ring_info *rxr = &bp->rx_ring[i];
4156                 struct bnxt_ring_struct *ring = &rxr->rx_ring_struct;
4157                 u32 grp_idx = rxr->bnapi->index;
4158                 u32 cmpl_ring_id = bp->grp_info[grp_idx].cp_fw_ring_id;
4159
4160                 if (ring->fw_ring_id != INVALID_HW_RING_ID) {
4161                         hwrm_ring_free_send_msg(bp, ring,
4162                                                 RING_FREE_REQ_RING_TYPE_RX,
4163                                                 close_path ? cmpl_ring_id :
4164                                                 INVALID_HW_RING_ID);
4165                         ring->fw_ring_id = INVALID_HW_RING_ID;
4166                         bp->grp_info[grp_idx].rx_fw_ring_id =
4167                                 INVALID_HW_RING_ID;
4168                 }
4169         }
4170
4171         for (i = 0; i < bp->rx_nr_rings; i++) {
4172                 struct bnxt_rx_ring_info *rxr = &bp->rx_ring[i];
4173                 struct bnxt_ring_struct *ring = &rxr->rx_agg_ring_struct;
4174                 u32 grp_idx = rxr->bnapi->index;
4175                 u32 cmpl_ring_id = bp->grp_info[grp_idx].cp_fw_ring_id;
4176
4177                 if (ring->fw_ring_id != INVALID_HW_RING_ID) {
4178                         hwrm_ring_free_send_msg(bp, ring,
4179                                                 RING_FREE_REQ_RING_TYPE_RX,
4180                                                 close_path ? cmpl_ring_id :
4181                                                 INVALID_HW_RING_ID);
4182                         ring->fw_ring_id = INVALID_HW_RING_ID;
4183                         bp->grp_info[grp_idx].agg_fw_ring_id =
4184                                 INVALID_HW_RING_ID;
4185                 }
4186         }
4187
4188         /* The completion rings are about to be freed.  After that the
4189          * IRQ doorbell will not work anymore.  So we need to disable
4190          * IRQ here.
4191          */
4192         bnxt_disable_int_sync(bp);
4193
4194         for (i = 0; i < bp->cp_nr_rings; i++) {
4195                 struct bnxt_napi *bnapi = bp->bnapi[i];
4196                 struct bnxt_cp_ring_info *cpr = &bnapi->cp_ring;
4197                 struct bnxt_ring_struct *ring = &cpr->cp_ring_struct;
4198
4199                 if (ring->fw_ring_id != INVALID_HW_RING_ID) {
4200                         hwrm_ring_free_send_msg(bp, ring,
4201                                                 RING_FREE_REQ_RING_TYPE_CMPL,
4202                                                 INVALID_HW_RING_ID);
4203                         ring->fw_ring_id = INVALID_HW_RING_ID;
4204                         bp->grp_info[i].cp_fw_ring_id = INVALID_HW_RING_ID;
4205                 }
4206         }
4207 }
4208
4209 /* Caller must hold bp->hwrm_cmd_lock */
4210 int __bnxt_hwrm_get_tx_rings(struct bnxt *bp, u16 fid, int *tx_rings)
4211 {
4212         struct hwrm_func_qcfg_output *resp = bp->hwrm_cmd_resp_addr;
4213         struct hwrm_func_qcfg_input req = {0};
4214         int rc;
4215
4216         if (bp->hwrm_spec_code < 0x10601)
4217                 return 0;
4218
4219         bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_FUNC_QCFG, -1, -1);
4220         req.fid = cpu_to_le16(fid);
4221         rc = _hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT);
4222         if (!rc)
4223                 *tx_rings = le16_to_cpu(resp->alloc_tx_rings);
4224
4225         return rc;
4226 }
4227
4228 static int bnxt_hwrm_reserve_tx_rings(struct bnxt *bp, int *tx_rings)
4229 {
4230         struct hwrm_func_cfg_input req = {0};
4231         int rc;
4232
4233         if (bp->hwrm_spec_code < 0x10601)
4234                 return 0;
4235
4236         if (BNXT_VF(bp))
4237                 return 0;
4238
4239         bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_FUNC_CFG, -1, -1);
4240         req.fid = cpu_to_le16(0xffff);
4241         req.enables = cpu_to_le32(FUNC_CFG_REQ_ENABLES_NUM_TX_RINGS);
4242         req.num_tx_rings = cpu_to_le16(*tx_rings);
4243         rc = hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT);
4244         if (rc)
4245                 return rc;
4246
4247         mutex_lock(&bp->hwrm_cmd_lock);
4248         rc = __bnxt_hwrm_get_tx_rings(bp, 0xffff, tx_rings);
4249         mutex_unlock(&bp->hwrm_cmd_lock);
4250         return rc;
4251 }
4252
4253 static void bnxt_hwrm_set_coal_params(struct bnxt *bp, u32 max_bufs,
4254         u32 buf_tmrs, u16 flags,
4255         struct hwrm_ring_cmpl_ring_cfg_aggint_params_input *req)
4256 {
4257         req->flags = cpu_to_le16(flags);
4258         req->num_cmpl_dma_aggr = cpu_to_le16((u16)max_bufs);
4259         req->num_cmpl_dma_aggr_during_int = cpu_to_le16(max_bufs >> 16);
4260         req->cmpl_aggr_dma_tmr = cpu_to_le16((u16)buf_tmrs);
4261         req->cmpl_aggr_dma_tmr_during_int = cpu_to_le16(buf_tmrs >> 16);
4262         /* Minimum time between 2 interrupts set to buf_tmr x 2 */
4263         req->int_lat_tmr_min = cpu_to_le16((u16)buf_tmrs * 2);
4264         req->int_lat_tmr_max = cpu_to_le16((u16)buf_tmrs * 4);
4265         req->num_cmpl_aggr_int = cpu_to_le16((u16)max_bufs * 4);
4266 }
4267
4268 int bnxt_hwrm_set_coal(struct bnxt *bp)
4269 {
4270         int i, rc = 0;
4271         struct hwrm_ring_cmpl_ring_cfg_aggint_params_input req_rx = {0},
4272                                                            req_tx = {0}, *req;
4273         u16 max_buf, max_buf_irq;
4274         u16 buf_tmr, buf_tmr_irq;
4275         u32 flags;
4276
4277         bnxt_hwrm_cmd_hdr_init(bp, &req_rx,
4278                                HWRM_RING_CMPL_RING_CFG_AGGINT_PARAMS, -1, -1);
4279         bnxt_hwrm_cmd_hdr_init(bp, &req_tx,
4280                                HWRM_RING_CMPL_RING_CFG_AGGINT_PARAMS, -1, -1);
4281
4282         /* Each rx completion (2 records) should be DMAed immediately.
4283          * DMA 1/4 of the completion buffers at a time.
4284          */
4285         max_buf = min_t(u16, bp->rx_coal_bufs / 4, 2);
4286         /* max_buf must not be zero */
4287         max_buf = clamp_t(u16, max_buf, 1, 63);
4288         max_buf_irq = clamp_t(u16, bp->rx_coal_bufs_irq, 1, 63);
4289         buf_tmr = BNXT_USEC_TO_COAL_TIMER(bp->rx_coal_ticks);
4290         /* buf timer set to 1/4 of interrupt timer */
4291         buf_tmr = max_t(u16, buf_tmr / 4, 1);
4292         buf_tmr_irq = BNXT_USEC_TO_COAL_TIMER(bp->rx_coal_ticks_irq);
4293         buf_tmr_irq = max_t(u16, buf_tmr_irq, 1);
4294
4295         flags = RING_CMPL_RING_CFG_AGGINT_PARAMS_REQ_FLAGS_TIMER_RESET;
4296
4297         /* RING_IDLE generates more IRQs for lower latency.  Enable it only
4298          * if coal_ticks is less than 25 us.
4299          */
4300         if (bp->rx_coal_ticks < 25)
4301                 flags |= RING_CMPL_RING_CFG_AGGINT_PARAMS_REQ_FLAGS_RING_IDLE;
4302
4303         bnxt_hwrm_set_coal_params(bp, max_buf_irq << 16 | max_buf,
4304                                   buf_tmr_irq << 16 | buf_tmr, flags, &req_rx);
4305
4306         /* max_buf must not be zero */
4307         max_buf = clamp_t(u16, bp->tx_coal_bufs, 1, 63);
4308         max_buf_irq = clamp_t(u16, bp->tx_coal_bufs_irq, 1, 63);
4309         buf_tmr = BNXT_USEC_TO_COAL_TIMER(bp->tx_coal_ticks);
4310         /* buf timer set to 1/4 of interrupt timer */
4311         buf_tmr = max_t(u16, buf_tmr / 4, 1);
4312         buf_tmr_irq = BNXT_USEC_TO_COAL_TIMER(bp->tx_coal_ticks_irq);
4313         buf_tmr_irq = max_t(u16, buf_tmr_irq, 1);
4314
4315         flags = RING_CMPL_RING_CFG_AGGINT_PARAMS_REQ_FLAGS_TIMER_RESET;
4316         bnxt_hwrm_set_coal_params(bp, max_buf_irq << 16 | max_buf,
4317                                   buf_tmr_irq << 16 | buf_tmr, flags, &req_tx);
4318
4319         mutex_lock(&bp->hwrm_cmd_lock);
4320         for (i = 0; i < bp->cp_nr_rings; i++) {
4321                 struct bnxt_napi *bnapi = bp->bnapi[i];
4322
4323                 req = &req_rx;
4324                 if (!bnapi->rx_ring)
4325                         req = &req_tx;
4326                 req->ring_id = cpu_to_le16(bp->grp_info[i].cp_fw_ring_id);
4327
4328                 rc = _hwrm_send_message(bp, req, sizeof(*req),
4329                                         HWRM_CMD_TIMEOUT);
4330                 if (rc)
4331                         break;
4332         }
4333         mutex_unlock(&bp->hwrm_cmd_lock);
4334         return rc;
4335 }
4336
4337 static int bnxt_hwrm_stat_ctx_free(struct bnxt *bp)
4338 {
4339         int rc = 0, i;
4340         struct hwrm_stat_ctx_free_input req = {0};
4341
4342         if (!bp->bnapi)
4343                 return 0;
4344
4345         if (BNXT_CHIP_TYPE_NITRO_A0(bp))
4346                 return 0;
4347
4348         bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_STAT_CTX_FREE, -1, -1);
4349
4350         mutex_lock(&bp->hwrm_cmd_lock);
4351         for (i = 0; i < bp->cp_nr_rings; i++) {
4352                 struct bnxt_napi *bnapi = bp->bnapi[i];
4353                 struct bnxt_cp_ring_info *cpr = &bnapi->cp_ring;
4354
4355                 if (cpr->hw_stats_ctx_id != INVALID_STATS_CTX_ID) {
4356                         req.stat_ctx_id = cpu_to_le32(cpr->hw_stats_ctx_id);
4357
4358                         rc = _hwrm_send_message(bp, &req, sizeof(req),
4359                                                 HWRM_CMD_TIMEOUT);
4360                         if (rc)
4361                                 break;
4362
4363                         cpr->hw_stats_ctx_id = INVALID_STATS_CTX_ID;
4364                 }
4365         }
4366         mutex_unlock(&bp->hwrm_cmd_lock);
4367         return rc;
4368 }
4369
4370 static int bnxt_hwrm_stat_ctx_alloc(struct bnxt *bp)
4371 {
4372         int rc = 0, i;
4373         struct hwrm_stat_ctx_alloc_input req = {0};
4374         struct hwrm_stat_ctx_alloc_output *resp = bp->hwrm_cmd_resp_addr;
4375
4376         if (BNXT_CHIP_TYPE_NITRO_A0(bp))
4377                 return 0;
4378
4379         bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_STAT_CTX_ALLOC, -1, -1);
4380
4381         req.update_period_ms = cpu_to_le32(bp->stats_coal_ticks / 1000);
4382
4383         mutex_lock(&bp->hwrm_cmd_lock);
4384         for (i = 0; i < bp->cp_nr_rings; i++) {
4385                 struct bnxt_napi *bnapi = bp->bnapi[i];
4386                 struct bnxt_cp_ring_info *cpr = &bnapi->cp_ring;
4387
4388                 req.stats_dma_addr = cpu_to_le64(cpr->hw_stats_map);
4389
4390                 rc = _hwrm_send_message(bp, &req, sizeof(req),
4391                                         HWRM_CMD_TIMEOUT);
4392                 if (rc)
4393                         break;
4394
4395                 cpr->hw_stats_ctx_id = le32_to_cpu(resp->stat_ctx_id);
4396
4397                 bp->grp_info[i].fw_stats_ctx = cpr->hw_stats_ctx_id;
4398         }
4399         mutex_unlock(&bp->hwrm_cmd_lock);
4400         return rc;
4401 }
4402
4403 static int bnxt_hwrm_func_qcfg(struct bnxt *bp)
4404 {
4405         struct hwrm_func_qcfg_input req = {0};
4406         struct hwrm_func_qcfg_output *resp = bp->hwrm_cmd_resp_addr;
4407         int rc;
4408
4409         bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_FUNC_QCFG, -1, -1);
4410         req.fid = cpu_to_le16(0xffff);
4411         mutex_lock(&bp->hwrm_cmd_lock);
4412         rc = _hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT);
4413         if (rc)
4414                 goto func_qcfg_exit;
4415
4416 #ifdef CONFIG_BNXT_SRIOV
4417         if (BNXT_VF(bp)) {
4418                 struct bnxt_vf_info *vf = &bp->vf;
4419
4420                 vf->vlan = le16_to_cpu(resp->vlan) & VLAN_VID_MASK;
4421         }
4422 #endif
4423         switch (resp->port_partition_type) {
4424         case FUNC_QCFG_RESP_PORT_PARTITION_TYPE_NPAR1_0:
4425         case FUNC_QCFG_RESP_PORT_PARTITION_TYPE_NPAR1_5:
4426         case FUNC_QCFG_RESP_PORT_PARTITION_TYPE_NPAR2_0:
4427                 bp->port_partition_type = resp->port_partition_type;
4428                 break;
4429         }
4430
4431 func_qcfg_exit:
4432         mutex_unlock(&bp->hwrm_cmd_lock);
4433         return rc;
4434 }
4435
4436 static int bnxt_hwrm_func_qcaps(struct bnxt *bp)
4437 {
4438         int rc = 0;
4439         struct hwrm_func_qcaps_input req = {0};
4440         struct hwrm_func_qcaps_output *resp = bp->hwrm_cmd_resp_addr;
4441
4442         bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_FUNC_QCAPS, -1, -1);
4443         req.fid = cpu_to_le16(0xffff);
4444
4445         mutex_lock(&bp->hwrm_cmd_lock);
4446         rc = _hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT);
4447         if (rc)
4448                 goto hwrm_func_qcaps_exit;
4449
4450         if (resp->flags & cpu_to_le32(FUNC_QCAPS_RESP_FLAGS_ROCE_V1_SUPPORTED))
4451                 bp->flags |= BNXT_FLAG_ROCEV1_CAP;
4452         if (resp->flags & cpu_to_le32(FUNC_QCAPS_RESP_FLAGS_ROCE_V2_SUPPORTED))
4453                 bp->flags |= BNXT_FLAG_ROCEV2_CAP;
4454
4455         bp->tx_push_thresh = 0;
4456         if (resp->flags &
4457             cpu_to_le32(FUNC_QCAPS_RESP_FLAGS_PUSH_MODE_SUPPORTED))
4458                 bp->tx_push_thresh = BNXT_TX_PUSH_THRESH;
4459
4460         if (BNXT_PF(bp)) {
4461                 struct bnxt_pf_info *pf = &bp->pf;
4462
4463                 pf->fw_fid = le16_to_cpu(resp->fid);
4464                 pf->port_id = le16_to_cpu(resp->port_id);
4465                 bp->dev->dev_port = pf->port_id;
4466                 memcpy(pf->mac_addr, resp->mac_address, ETH_ALEN);
4467                 memcpy(bp->dev->dev_addr, pf->mac_addr, ETH_ALEN);
4468                 pf->max_rsscos_ctxs = le16_to_cpu(resp->max_rsscos_ctx);
4469                 pf->max_cp_rings = le16_to_cpu(resp->max_cmpl_rings);
4470                 pf->max_tx_rings = le16_to_cpu(resp->max_tx_rings);
4471                 pf->max_rx_rings = le16_to_cpu(resp->max_rx_rings);
4472                 pf->max_hw_ring_grps = le32_to_cpu(resp->max_hw_ring_grps);
4473                 if (!pf->max_hw_ring_grps)
4474                         pf->max_hw_ring_grps = pf->max_tx_rings;
4475                 pf->max_l2_ctxs = le16_to_cpu(resp->max_l2_ctxs);
4476                 pf->max_vnics = le16_to_cpu(resp->max_vnics);
4477                 pf->max_stat_ctxs = le16_to_cpu(resp->max_stat_ctx);
4478                 pf->first_vf_id = le16_to_cpu(resp->first_vf_id);
4479                 pf->max_vfs = le16_to_cpu(resp->max_vfs);
4480                 pf->max_encap_records = le32_to_cpu(resp->max_encap_records);
4481                 pf->max_decap_records = le32_to_cpu(resp->max_decap_records);
4482                 pf->max_tx_em_flows = le32_to_cpu(resp->max_tx_em_flows);
4483                 pf->max_tx_wm_flows = le32_to_cpu(resp->max_tx_wm_flows);
4484                 pf->max_rx_em_flows = le32_to_cpu(resp->max_rx_em_flows);
4485                 pf->max_rx_wm_flows = le32_to_cpu(resp->max_rx_wm_flows);
4486         } else {
4487 #ifdef CONFIG_BNXT_SRIOV
4488                 struct bnxt_vf_info *vf = &bp->vf;
4489
4490                 vf->fw_fid = le16_to_cpu(resp->fid);
4491
4492                 vf->max_rsscos_ctxs = le16_to_cpu(resp->max_rsscos_ctx);
4493                 vf->max_cp_rings = le16_to_cpu(resp->max_cmpl_rings);
4494                 vf->max_tx_rings = le16_to_cpu(resp->max_tx_rings);
4495                 vf->max_rx_rings = le16_to_cpu(resp->max_rx_rings);
4496                 vf->max_hw_ring_grps = le32_to_cpu(resp->max_hw_ring_grps);
4497                 if (!vf->max_hw_ring_grps)
4498                         vf->max_hw_ring_grps = vf->max_tx_rings;
4499                 vf->max_l2_ctxs = le16_to_cpu(resp->max_l2_ctxs);
4500                 vf->max_vnics = le16_to_cpu(resp->max_vnics);
4501                 vf->max_stat_ctxs = le16_to_cpu(resp->max_stat_ctx);
4502
4503                 memcpy(vf->mac_addr, resp->mac_address, ETH_ALEN);
4504                 mutex_unlock(&bp->hwrm_cmd_lock);
4505
4506                 if (is_valid_ether_addr(vf->mac_addr)) {
4507                         /* overwrite netdev dev_adr with admin VF MAC */
4508                         memcpy(bp->dev->dev_addr, vf->mac_addr, ETH_ALEN);
4509                 } else {
4510                         random_ether_addr(bp->dev->dev_addr);
4511                         rc = bnxt_approve_mac(bp, bp->dev->dev_addr);
4512                 }
4513                 return rc;
4514 #endif
4515         }
4516
4517 hwrm_func_qcaps_exit:
4518         mutex_unlock(&bp->hwrm_cmd_lock);
4519         return rc;
4520 }
4521
4522 static int bnxt_hwrm_func_reset(struct bnxt *bp)
4523 {
4524         struct hwrm_func_reset_input req = {0};
4525
4526         bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_FUNC_RESET, -1, -1);
4527         req.enables = 0;
4528
4529         return hwrm_send_message(bp, &req, sizeof(req), HWRM_RESET_TIMEOUT);
4530 }
4531
4532 static int bnxt_hwrm_queue_qportcfg(struct bnxt *bp)
4533 {
4534         int rc = 0;
4535         struct hwrm_queue_qportcfg_input req = {0};
4536         struct hwrm_queue_qportcfg_output *resp = bp->hwrm_cmd_resp_addr;
4537         u8 i, *qptr;
4538
4539         bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_QUEUE_QPORTCFG, -1, -1);
4540
4541         mutex_lock(&bp->hwrm_cmd_lock);
4542         rc = _hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT);
4543         if (rc)
4544                 goto qportcfg_exit;
4545
4546         if (!resp->max_configurable_queues) {
4547                 rc = -EINVAL;
4548                 goto qportcfg_exit;
4549         }
4550         bp->max_tc = resp->max_configurable_queues;
4551         bp->max_lltc = resp->max_configurable_lossless_queues;
4552         if (bp->max_tc > BNXT_MAX_QUEUE)
4553                 bp->max_tc = BNXT_MAX_QUEUE;
4554
4555         if (resp->queue_cfg_info & QUEUE_QPORTCFG_RESP_QUEUE_CFG_INFO_ASYM_CFG)
4556                 bp->max_tc = 1;
4557
4558         if (bp->max_lltc > bp->max_tc)
4559                 bp->max_lltc = bp->max_tc;
4560
4561         qptr = &resp->queue_id0;
4562         for (i = 0; i < bp->max_tc; i++) {
4563                 bp->q_info[i].queue_id = *qptr++;
4564                 bp->q_info[i].queue_profile = *qptr++;
4565         }
4566
4567 qportcfg_exit:
4568         mutex_unlock(&bp->hwrm_cmd_lock);
4569         return rc;
4570 }
4571
4572 static int bnxt_hwrm_ver_get(struct bnxt *bp)
4573 {
4574         int rc;
4575         struct hwrm_ver_get_input req = {0};
4576         struct hwrm_ver_get_output *resp = bp->hwrm_cmd_resp_addr;
4577
4578         bp->hwrm_max_req_len = HWRM_MAX_REQ_LEN;
4579         bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_VER_GET, -1, -1);
4580         req.hwrm_intf_maj = HWRM_VERSION_MAJOR;
4581         req.hwrm_intf_min = HWRM_VERSION_MINOR;
4582         req.hwrm_intf_upd = HWRM_VERSION_UPDATE;
4583         mutex_lock(&bp->hwrm_cmd_lock);
4584         rc = _hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT);
4585         if (rc)
4586                 goto hwrm_ver_get_exit;
4587
4588         memcpy(&bp->ver_resp, resp, sizeof(struct hwrm_ver_get_output));
4589
4590         bp->hwrm_spec_code = resp->hwrm_intf_maj << 16 |
4591                              resp->hwrm_intf_min << 8 | resp->hwrm_intf_upd;
4592         if (resp->hwrm_intf_maj < 1) {
4593                 netdev_warn(bp->dev, "HWRM interface %d.%d.%d is older than 1.0.0.\n",
4594                             resp->hwrm_intf_maj, resp->hwrm_intf_min,
4595                             resp->hwrm_intf_upd);
4596                 netdev_warn(bp->dev, "Please update firmware with HWRM interface 1.0.0 or newer.\n");
4597         }
4598         snprintf(bp->fw_ver_str, BC_HWRM_STR_LEN, "%d.%d.%d/%d.%d.%d",
4599                  resp->hwrm_fw_maj, resp->hwrm_fw_min, resp->hwrm_fw_bld,
4600                  resp->hwrm_intf_maj, resp->hwrm_intf_min, resp->hwrm_intf_upd);
4601
4602         bp->hwrm_cmd_timeout = le16_to_cpu(resp->def_req_timeout);
4603         if (!bp->hwrm_cmd_timeout)
4604                 bp->hwrm_cmd_timeout = DFLT_HWRM_CMD_TIMEOUT;
4605
4606         if (resp->hwrm_intf_maj >= 1)
4607                 bp->hwrm_max_req_len = le16_to_cpu(resp->max_req_win_len);
4608
4609         bp->chip_num = le16_to_cpu(resp->chip_num);
4610         if (bp->chip_num == CHIP_NUM_58700 && !resp->chip_rev &&
4611             !resp->chip_metal)
4612                 bp->flags |= BNXT_FLAG_CHIP_NITRO_A0;
4613
4614 hwrm_ver_get_exit:
4615         mutex_unlock(&bp->hwrm_cmd_lock);
4616         return rc;
4617 }
4618
4619 int bnxt_hwrm_fw_set_time(struct bnxt *bp)
4620 {
4621 #if IS_ENABLED(CONFIG_RTC_LIB)
4622         struct hwrm_fw_set_time_input req = {0};
4623         struct rtc_time tm;
4624         struct timeval tv;
4625
4626         if (bp->hwrm_spec_code < 0x10400)
4627                 return -EOPNOTSUPP;
4628
4629         do_gettimeofday(&tv);
4630         rtc_time_to_tm(tv.tv_sec, &tm);
4631         bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_FW_SET_TIME, -1, -1);
4632         req.year = cpu_to_le16(1900 + tm.tm_year);
4633         req.month = 1 + tm.tm_mon;
4634         req.day = tm.tm_mday;
4635         req.hour = tm.tm_hour;
4636         req.minute = tm.tm_min;
4637         req.second = tm.tm_sec;
4638         return hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT);
4639 #else
4640         return -EOPNOTSUPP;
4641 #endif
4642 }
4643
4644 static int bnxt_hwrm_port_qstats(struct bnxt *bp)
4645 {
4646         int rc;
4647         struct bnxt_pf_info *pf = &bp->pf;
4648         struct hwrm_port_qstats_input req = {0};
4649
4650         if (!(bp->flags & BNXT_FLAG_PORT_STATS))
4651                 return 0;
4652
4653         bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_PORT_QSTATS, -1, -1);
4654         req.port_id = cpu_to_le16(pf->port_id);
4655         req.tx_stat_host_addr = cpu_to_le64(bp->hw_tx_port_stats_map);
4656         req.rx_stat_host_addr = cpu_to_le64(bp->hw_rx_port_stats_map);
4657         rc = hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT);
4658         return rc;
4659 }
4660
4661 static void bnxt_hwrm_free_tunnel_ports(struct bnxt *bp)
4662 {
4663         if (bp->vxlan_port_cnt) {
4664                 bnxt_hwrm_tunnel_dst_port_free(
4665                         bp, TUNNEL_DST_PORT_FREE_REQ_TUNNEL_TYPE_VXLAN);
4666         }
4667         bp->vxlan_port_cnt = 0;
4668         if (bp->nge_port_cnt) {
4669                 bnxt_hwrm_tunnel_dst_port_free(
4670                         bp, TUNNEL_DST_PORT_FREE_REQ_TUNNEL_TYPE_GENEVE);
4671         }
4672         bp->nge_port_cnt = 0;
4673 }
4674
4675 static int bnxt_set_tpa(struct bnxt *bp, bool set_tpa)
4676 {
4677         int rc, i;
4678         u32 tpa_flags = 0;
4679
4680         if (set_tpa)
4681                 tpa_flags = bp->flags & BNXT_FLAG_TPA;
4682         for (i = 0; i < bp->nr_vnics; i++) {
4683                 rc = bnxt_hwrm_vnic_set_tpa(bp, i, tpa_flags);
4684                 if (rc) {
4685                         netdev_err(bp->dev, "hwrm vnic set tpa failure rc for vnic %d: %x\n",
4686                                    rc, i);
4687                         return rc;
4688                 }
4689         }
4690         return 0;
4691 }
4692
4693 static void bnxt_hwrm_clear_vnic_rss(struct bnxt *bp)
4694 {
4695         int i;
4696
4697         for (i = 0; i < bp->nr_vnics; i++)
4698                 bnxt_hwrm_vnic_set_rss(bp, i, false);
4699 }
4700
4701 static void bnxt_hwrm_resource_free(struct bnxt *bp, bool close_path,
4702                                     bool irq_re_init)
4703 {
4704         if (bp->vnic_info) {
4705                 bnxt_hwrm_clear_vnic_filter(bp);
4706                 /* clear all RSS setting before free vnic ctx */
4707                 bnxt_hwrm_clear_vnic_rss(bp);
4708                 bnxt_hwrm_vnic_ctx_free(bp);
4709                 /* before free the vnic, undo the vnic tpa settings */
4710                 if (bp->flags & BNXT_FLAG_TPA)
4711                         bnxt_set_tpa(bp, false);
4712                 bnxt_hwrm_vnic_free(bp);
4713         }
4714         bnxt_hwrm_ring_free(bp, close_path);
4715         bnxt_hwrm_ring_grp_free(bp);
4716         if (irq_re_init) {
4717                 bnxt_hwrm_stat_ctx_free(bp);
4718                 bnxt_hwrm_free_tunnel_ports(bp);
4719         }
4720 }
4721
4722 static int bnxt_setup_vnic(struct bnxt *bp, u16 vnic_id)
4723 {
4724         struct bnxt_vnic_info *vnic = &bp->vnic_info[vnic_id];
4725         int rc;
4726
4727         if (vnic->flags & BNXT_VNIC_RFS_NEW_RSS_FLAG)
4728                 goto skip_rss_ctx;
4729
4730         /* allocate context for vnic */
4731         rc = bnxt_hwrm_vnic_ctx_alloc(bp, vnic_id, 0);
4732         if (rc) {
4733                 netdev_err(bp->dev, "hwrm vnic %d alloc failure rc: %x\n",
4734                            vnic_id, rc);
4735                 goto vnic_setup_err;
4736         }
4737         bp->rsscos_nr_ctxs++;
4738
4739         if (BNXT_CHIP_TYPE_NITRO_A0(bp)) {
4740                 rc = bnxt_hwrm_vnic_ctx_alloc(bp, vnic_id, 1);
4741                 if (rc) {
4742                         netdev_err(bp->dev, "hwrm vnic %d cos ctx alloc failure rc: %x\n",
4743                                    vnic_id, rc);
4744                         goto vnic_setup_err;
4745                 }
4746                 bp->rsscos_nr_ctxs++;
4747         }
4748
4749 skip_rss_ctx:
4750         /* configure default vnic, ring grp */
4751         rc = bnxt_hwrm_vnic_cfg(bp, vnic_id);
4752         if (rc) {
4753                 netdev_err(bp->dev, "hwrm vnic %d cfg failure rc: %x\n",
4754                            vnic_id, rc);
4755                 goto vnic_setup_err;
4756         }
4757
4758         /* Enable RSS hashing on vnic */
4759         rc = bnxt_hwrm_vnic_set_rss(bp, vnic_id, true);
4760         if (rc) {
4761                 netdev_err(bp->dev, "hwrm vnic %d set rss failure rc: %x\n",
4762                            vnic_id, rc);
4763                 goto vnic_setup_err;
4764         }
4765
4766         if (bp->flags & BNXT_FLAG_AGG_RINGS) {
4767                 rc = bnxt_hwrm_vnic_set_hds(bp, vnic_id);
4768                 if (rc) {
4769                         netdev_err(bp->dev, "hwrm vnic %d set hds failure rc: %x\n",
4770                                    vnic_id, rc);
4771                 }
4772         }
4773
4774 vnic_setup_err:
4775         return rc;
4776 }
4777
4778 static int bnxt_alloc_rfs_vnics(struct bnxt *bp)
4779 {
4780 #ifdef CONFIG_RFS_ACCEL
4781         int i, rc = 0;
4782
4783         for (i = 0; i < bp->rx_nr_rings; i++) {
4784                 struct bnxt_vnic_info *vnic;
4785                 u16 vnic_id = i + 1;
4786                 u16 ring_id = i;
4787
4788                 if (vnic_id >= bp->nr_vnics)
4789                         break;
4790
4791                 vnic = &bp->vnic_info[vnic_id];
4792                 vnic->flags |= BNXT_VNIC_RFS_FLAG;
4793                 if (bp->flags & BNXT_FLAG_NEW_RSS_CAP)
4794                         vnic->flags |= BNXT_VNIC_RFS_NEW_RSS_FLAG;
4795                 rc = bnxt_hwrm_vnic_alloc(bp, vnic_id, ring_id, 1);
4796                 if (rc) {
4797                         netdev_err(bp->dev, "hwrm vnic %d alloc failure rc: %x\n",
4798                                    vnic_id, rc);
4799                         break;
4800                 }
4801                 rc = bnxt_setup_vnic(bp, vnic_id);
4802                 if (rc)
4803                         break;
4804         }
4805         return rc;
4806 #else
4807         return 0;
4808 #endif
4809 }
4810
4811 /* Allow PF and VF with default VLAN to be in promiscuous mode */
4812 static bool bnxt_promisc_ok(struct bnxt *bp)
4813 {
4814 #ifdef CONFIG_BNXT_SRIOV
4815         if (BNXT_VF(bp) && !bp->vf.vlan)
4816                 return false;
4817 #endif
4818         return true;
4819 }
4820
4821 static int bnxt_setup_nitroa0_vnic(struct bnxt *bp)
4822 {
4823         unsigned int rc = 0;
4824
4825         rc = bnxt_hwrm_vnic_alloc(bp, 1, bp->rx_nr_rings - 1, 1);
4826         if (rc) {
4827                 netdev_err(bp->dev, "Cannot allocate special vnic for NS2 A0: %x\n",
4828                            rc);
4829                 return rc;
4830         }
4831
4832         rc = bnxt_hwrm_vnic_cfg(bp, 1);
4833         if (rc) {
4834                 netdev_err(bp->dev, "Cannot allocate special vnic for NS2 A0: %x\n",
4835                            rc);
4836                 return rc;
4837         }
4838         return rc;
4839 }
4840
4841 static int bnxt_cfg_rx_mode(struct bnxt *);
4842 static bool bnxt_mc_list_updated(struct bnxt *, u32 *);
4843
4844 static int bnxt_init_chip(struct bnxt *bp, bool irq_re_init)
4845 {
4846         struct bnxt_vnic_info *vnic = &bp->vnic_info[0];
4847         int rc = 0;
4848         unsigned int rx_nr_rings = bp->rx_nr_rings;
4849
4850         if (irq_re_init) {
4851                 rc = bnxt_hwrm_stat_ctx_alloc(bp);
4852                 if (rc) {
4853                         netdev_err(bp->dev, "hwrm stat ctx alloc failure rc: %x\n",
4854                                    rc);
4855                         goto err_out;
4856                 }
4857         }
4858
4859         rc = bnxt_hwrm_ring_alloc(bp);
4860         if (rc) {
4861                 netdev_err(bp->dev, "hwrm ring alloc failure rc: %x\n", rc);
4862                 goto err_out;
4863         }
4864
4865         rc = bnxt_hwrm_ring_grp_alloc(bp);
4866         if (rc) {
4867                 netdev_err(bp->dev, "hwrm_ring_grp alloc failure: %x\n", rc);
4868                 goto err_out;
4869         }
4870
4871         if (BNXT_CHIP_TYPE_NITRO_A0(bp))
4872                 rx_nr_rings--;
4873
4874         /* default vnic 0 */
4875         rc = bnxt_hwrm_vnic_alloc(bp, 0, 0, rx_nr_rings);
4876         if (rc) {
4877                 netdev_err(bp->dev, "hwrm vnic alloc failure rc: %x\n", rc);
4878                 goto err_out;
4879         }
4880
4881         rc = bnxt_setup_vnic(bp, 0);
4882         if (rc)
4883                 goto err_out;
4884
4885         if (bp->flags & BNXT_FLAG_RFS) {
4886                 rc = bnxt_alloc_rfs_vnics(bp);
4887                 if (rc)
4888                         goto err_out;
4889         }
4890
4891         if (bp->flags & BNXT_FLAG_TPA) {
4892                 rc = bnxt_set_tpa(bp, true);
4893                 if (rc)
4894                         goto err_out;
4895         }
4896
4897         if (BNXT_VF(bp))
4898                 bnxt_update_vf_mac(bp);
4899
4900         /* Filter for default vnic 0 */
4901         rc = bnxt_hwrm_set_vnic_filter(bp, 0, 0, bp->dev->dev_addr);
4902         if (rc) {
4903                 netdev_err(bp->dev, "HWRM vnic filter failure rc: %x\n", rc);
4904                 goto err_out;
4905         }
4906         vnic->uc_filter_count = 1;
4907
4908         vnic->rx_mask = CFA_L2_SET_RX_MASK_REQ_MASK_BCAST;
4909
4910         if ((bp->dev->flags & IFF_PROMISC) && bnxt_promisc_ok(bp))
4911                 vnic->rx_mask |= CFA_L2_SET_RX_MASK_REQ_MASK_PROMISCUOUS;
4912
4913         if (bp->dev->flags & IFF_ALLMULTI) {
4914                 vnic->rx_mask |= CFA_L2_SET_RX_MASK_REQ_MASK_ALL_MCAST;
4915                 vnic->mc_list_count = 0;
4916         } else {
4917                 u32 mask = 0;
4918
4919                 bnxt_mc_list_updated(bp, &mask);
4920                 vnic->rx_mask |= mask;
4921         }
4922
4923         rc = bnxt_cfg_rx_mode(bp);
4924         if (rc)
4925                 goto err_out;
4926
4927         rc = bnxt_hwrm_set_coal(bp);
4928         if (rc)
4929                 netdev_warn(bp->dev, "HWRM set coalescing failure rc: %x\n",
4930                                 rc);
4931
4932         if (BNXT_CHIP_TYPE_NITRO_A0(bp)) {
4933                 rc = bnxt_setup_nitroa0_vnic(bp);
4934                 if (rc)
4935                         netdev_err(bp->dev, "Special vnic setup failure for NS2 A0 rc: %x\n",
4936                                    rc);
4937         }
4938
4939         if (BNXT_VF(bp)) {
4940                 bnxt_hwrm_func_qcfg(bp);
4941                 netdev_update_features(bp->dev);
4942         }
4943
4944         return 0;
4945
4946 err_out:
4947         bnxt_hwrm_resource_free(bp, 0, true);
4948
4949         return rc;
4950 }
4951
4952 static int bnxt_shutdown_nic(struct bnxt *bp, bool irq_re_init)
4953 {
4954         bnxt_hwrm_resource_free(bp, 1, irq_re_init);
4955         return 0;
4956 }
4957
4958 static int bnxt_init_nic(struct bnxt *bp, bool irq_re_init)
4959 {
4960         bnxt_init_rx_rings(bp);
4961         bnxt_init_tx_rings(bp);
4962         bnxt_init_ring_grps(bp, irq_re_init);
4963         bnxt_init_vnics(bp);
4964
4965         return bnxt_init_chip(bp, irq_re_init);
4966 }
4967
4968 static int bnxt_set_real_num_queues(struct bnxt *bp)
4969 {
4970         int rc;
4971         struct net_device *dev = bp->dev;
4972
4973         rc = netif_set_real_num_tx_queues(dev, bp->tx_nr_rings -
4974                                           bp->tx_nr_rings_xdp);
4975         if (rc)
4976                 return rc;
4977
4978         rc = netif_set_real_num_rx_queues(dev, bp->rx_nr_rings);
4979         if (rc)
4980                 return rc;
4981
4982 #ifdef CONFIG_RFS_ACCEL
4983         if (bp->flags & BNXT_FLAG_RFS)
4984                 dev->rx_cpu_rmap = alloc_irq_cpu_rmap(bp->rx_nr_rings);
4985 #endif
4986
4987         return rc;
4988 }
4989
4990 static int bnxt_trim_rings(struct bnxt *bp, int *rx, int *tx, int max,
4991                            bool shared)
4992 {
4993         int _rx = *rx, _tx = *tx;
4994
4995         if (shared) {
4996                 *rx = min_t(int, _rx, max);
4997                 *tx = min_t(int, _tx, max);
4998         } else {
4999                 if (max < 2)
5000                         return -ENOMEM;
5001
5002                 while (_rx + _tx > max) {
5003                         if (_rx > _tx && _rx > 1)
5004                                 _rx--;
5005                         else if (_tx > 1)
5006                                 _tx--;
5007                 }
5008                 *rx = _rx;
5009                 *tx = _tx;
5010         }
5011         return 0;
5012 }
5013
5014 static void bnxt_setup_msix(struct bnxt *bp)
5015 {
5016         const int len = sizeof(bp->irq_tbl[0].name);
5017         struct net_device *dev = bp->dev;
5018         int tcs, i;
5019
5020         tcs = netdev_get_num_tc(dev);
5021         if (tcs > 1) {
5022                 int i, off, count;
5023
5024                 for (i = 0; i < tcs; i++) {
5025                         count = bp->tx_nr_rings_per_tc;
5026                         off = i * count;
5027                         netdev_set_tc_queue(dev, i, count, off);
5028                 }
5029         }
5030
5031         for (i = 0; i < bp->cp_nr_rings; i++) {
5032                 char *attr;
5033
5034                 if (bp->flags & BNXT_FLAG_SHARED_RINGS)
5035                         attr = "TxRx";
5036                 else if (i < bp->rx_nr_rings)
5037                         attr = "rx";
5038                 else
5039                         attr = "tx";
5040
5041                 snprintf(bp->irq_tbl[i].name, len, "%s-%s-%d", dev->name, attr,
5042                          i);
5043                 bp->irq_tbl[i].handler = bnxt_msix;
5044         }
5045 }
5046
5047 static void bnxt_setup_inta(struct bnxt *bp)
5048 {
5049         const int len = sizeof(bp->irq_tbl[0].name);
5050
5051         if (netdev_get_num_tc(bp->dev))
5052                 netdev_reset_tc(bp->dev);
5053
5054         snprintf(bp->irq_tbl[0].name, len, "%s-%s-%d", bp->dev->name, "TxRx",
5055                  0);
5056         bp->irq_tbl[0].handler = bnxt_inta;
5057 }
5058
5059 static int bnxt_setup_int_mode(struct bnxt *bp)
5060 {
5061         int rc;
5062
5063         if (bp->flags & BNXT_FLAG_USING_MSIX)
5064                 bnxt_setup_msix(bp);
5065         else
5066                 bnxt_setup_inta(bp);
5067
5068         rc = bnxt_set_real_num_queues(bp);
5069         return rc;
5070 }
5071
5072 #ifdef CONFIG_RFS_ACCEL
5073 static unsigned int bnxt_get_max_func_rss_ctxs(struct bnxt *bp)
5074 {
5075 #if defined(CONFIG_BNXT_SRIOV)
5076         if (BNXT_VF(bp))
5077                 return bp->vf.max_rsscos_ctxs;
5078 #endif
5079         return bp->pf.max_rsscos_ctxs;
5080 }
5081
5082 static unsigned int bnxt_get_max_func_vnics(struct bnxt *bp)
5083 {
5084 #if defined(CONFIG_BNXT_SRIOV)
5085         if (BNXT_VF(bp))
5086                 return bp->vf.max_vnics;
5087 #endif
5088         return bp->pf.max_vnics;
5089 }
5090 #endif
5091
5092 unsigned int bnxt_get_max_func_stat_ctxs(struct bnxt *bp)
5093 {
5094 #if defined(CONFIG_BNXT_SRIOV)
5095         if (BNXT_VF(bp))
5096                 return bp->vf.max_stat_ctxs;
5097 #endif
5098         return bp->pf.max_stat_ctxs;
5099 }
5100
5101 void bnxt_set_max_func_stat_ctxs(struct bnxt *bp, unsigned int max)
5102 {
5103 #if defined(CONFIG_BNXT_SRIOV)
5104         if (BNXT_VF(bp))
5105                 bp->vf.max_stat_ctxs = max;
5106         else
5107 #endif
5108                 bp->pf.max_stat_ctxs = max;
5109 }
5110
5111 unsigned int bnxt_get_max_func_cp_rings(struct bnxt *bp)
5112 {
5113 #if defined(CONFIG_BNXT_SRIOV)
5114         if (BNXT_VF(bp))
5115                 return bp->vf.max_cp_rings;
5116 #endif
5117         return bp->pf.max_cp_rings;
5118 }
5119
5120 void bnxt_set_max_func_cp_rings(struct bnxt *bp, unsigned int max)
5121 {
5122 #if defined(CONFIG_BNXT_SRIOV)
5123         if (BNXT_VF(bp))
5124                 bp->vf.max_cp_rings = max;
5125         else
5126 #endif
5127                 bp->pf.max_cp_rings = max;
5128 }
5129
5130 static unsigned int bnxt_get_max_func_irqs(struct bnxt *bp)
5131 {
5132 #if defined(CONFIG_BNXT_SRIOV)
5133         if (BNXT_VF(bp))
5134                 return bp->vf.max_irqs;
5135 #endif
5136         return bp->pf.max_irqs;
5137 }
5138
5139 void bnxt_set_max_func_irqs(struct bnxt *bp, unsigned int max_irqs)
5140 {
5141 #if defined(CONFIG_BNXT_SRIOV)
5142         if (BNXT_VF(bp))
5143                 bp->vf.max_irqs = max_irqs;
5144         else
5145 #endif
5146                 bp->pf.max_irqs = max_irqs;
5147 }
5148
5149 static int bnxt_init_msix(struct bnxt *bp)
5150 {
5151         int i, total_vecs, rc = 0, min = 1;
5152         struct msix_entry *msix_ent;
5153
5154         total_vecs = bnxt_get_max_func_irqs(bp);
5155         msix_ent = kcalloc(total_vecs, sizeof(struct msix_entry), GFP_KERNEL);
5156         if (!msix_ent)
5157                 return -ENOMEM;
5158
5159         for (i = 0; i < total_vecs; i++) {
5160                 msix_ent[i].entry = i;
5161                 msix_ent[i].vector = 0;
5162         }
5163
5164         if (!(bp->flags & BNXT_FLAG_SHARED_RINGS))
5165                 min = 2;
5166
5167         total_vecs = pci_enable_msix_range(bp->pdev, msix_ent, min, total_vecs);
5168         if (total_vecs < 0) {
5169                 rc = -ENODEV;
5170                 goto msix_setup_exit;
5171         }
5172
5173         bp->irq_tbl = kcalloc(total_vecs, sizeof(struct bnxt_irq), GFP_KERNEL);
5174         if (bp->irq_tbl) {
5175                 for (i = 0; i < total_vecs; i++)
5176                         bp->irq_tbl[i].vector = msix_ent[i].vector;
5177
5178                 bp->total_irqs = total_vecs;
5179                 /* Trim rings based upon num of vectors allocated */
5180                 rc = bnxt_trim_rings(bp, &bp->rx_nr_rings, &bp->tx_nr_rings,
5181                                      total_vecs, min == 1);
5182                 if (rc)
5183                         goto msix_setup_exit;
5184
5185                 bp->tx_nr_rings_per_tc = bp->tx_nr_rings;
5186                 bp->cp_nr_rings = (min == 1) ?
5187                                   max_t(int, bp->tx_nr_rings, bp->rx_nr_rings) :
5188                                   bp->tx_nr_rings + bp->rx_nr_rings;
5189
5190         } else {
5191                 rc = -ENOMEM;
5192                 goto msix_setup_exit;
5193         }
5194         bp->flags |= BNXT_FLAG_USING_MSIX;
5195         kfree(msix_ent);
5196         return 0;
5197
5198 msix_setup_exit:
5199         netdev_err(bp->dev, "bnxt_init_msix err: %x\n", rc);
5200         kfree(bp->irq_tbl);
5201         bp->irq_tbl = NULL;
5202         pci_disable_msix(bp->pdev);
5203         kfree(msix_ent);
5204         return rc;
5205 }
5206
5207 static int bnxt_init_inta(struct bnxt *bp)
5208 {
5209         bp->irq_tbl = kcalloc(1, sizeof(struct bnxt_irq), GFP_KERNEL);
5210         if (!bp->irq_tbl)
5211                 return -ENOMEM;
5212
5213         bp->total_irqs = 1;
5214         bp->rx_nr_rings = 1;
5215         bp->tx_nr_rings = 1;
5216         bp->cp_nr_rings = 1;
5217         bp->tx_nr_rings_per_tc = bp->tx_nr_rings;
5218         bp->flags |= BNXT_FLAG_SHARED_RINGS;
5219         bp->irq_tbl[0].vector = bp->pdev->irq;
5220         return 0;
5221 }
5222
5223 static int bnxt_init_int_mode(struct bnxt *bp)
5224 {
5225         int rc = 0;
5226
5227         if (bp->flags & BNXT_FLAG_MSIX_CAP)
5228                 rc = bnxt_init_msix(bp);
5229
5230         if (!(bp->flags & BNXT_FLAG_USING_MSIX) && BNXT_PF(bp)) {
5231                 /* fallback to INTA */
5232                 rc = bnxt_init_inta(bp);
5233         }
5234         return rc;
5235 }
5236
5237 static void bnxt_clear_int_mode(struct bnxt *bp)
5238 {
5239         if (bp->flags & BNXT_FLAG_USING_MSIX)
5240                 pci_disable_msix(bp->pdev);
5241
5242         kfree(bp->irq_tbl);
5243         bp->irq_tbl = NULL;
5244         bp->flags &= ~BNXT_FLAG_USING_MSIX;
5245 }
5246
5247 static void bnxt_free_irq(struct bnxt *bp)
5248 {
5249         struct bnxt_irq *irq;
5250         int i;
5251
5252 #ifdef CONFIG_RFS_ACCEL
5253         free_irq_cpu_rmap(bp->dev->rx_cpu_rmap);
5254         bp->dev->rx_cpu_rmap = NULL;
5255 #endif
5256         if (!bp->irq_tbl)
5257                 return;
5258
5259         for (i = 0; i < bp->cp_nr_rings; i++) {
5260                 irq = &bp->irq_tbl[i];
5261                 if (irq->requested)
5262                         free_irq(irq->vector, bp->bnapi[i]);
5263                 irq->requested = 0;
5264         }
5265 }
5266
5267 static int bnxt_request_irq(struct bnxt *bp)
5268 {
5269         int i, j, rc = 0;
5270         unsigned long flags = 0;
5271 #ifdef CONFIG_RFS_ACCEL
5272         struct cpu_rmap *rmap = bp->dev->rx_cpu_rmap;
5273 #endif
5274
5275         if (!(bp->flags & BNXT_FLAG_USING_MSIX))
5276                 flags = IRQF_SHARED;
5277
5278         for (i = 0, j = 0; i < bp->cp_nr_rings; i++) {
5279                 struct bnxt_irq *irq = &bp->irq_tbl[i];
5280 #ifdef CONFIG_RFS_ACCEL
5281                 if (rmap && bp->bnapi[i]->rx_ring) {
5282                         rc = irq_cpu_rmap_add(rmap, irq->vector);
5283                         if (rc)
5284                                 netdev_warn(bp->dev, "failed adding irq rmap for ring %d\n",
5285                                             j);
5286                         j++;
5287                 }
5288 #endif
5289                 rc = request_irq(irq->vector, irq->handler, flags, irq->name,
5290                                  bp->bnapi[i]);
5291                 if (rc)
5292                         break;
5293
5294                 irq->requested = 1;
5295         }
5296         return rc;
5297 }
5298
5299 static void bnxt_del_napi(struct bnxt *bp)
5300 {
5301         int i;
5302
5303         if (!bp->bnapi)
5304                 return;
5305
5306         for (i = 0; i < bp->cp_nr_rings; i++) {
5307                 struct bnxt_napi *bnapi = bp->bnapi[i];
5308
5309                 napi_hash_del(&bnapi->napi);
5310                 netif_napi_del(&bnapi->napi);
5311         }
5312         /* We called napi_hash_del() before netif_napi_del(), we need
5313          * to respect an RCU grace period before freeing napi structures.
5314          */
5315         synchronize_net();
5316 }
5317
5318 static void bnxt_init_napi(struct bnxt *bp)
5319 {
5320         int i;
5321         unsigned int cp_nr_rings = bp->cp_nr_rings;
5322         struct bnxt_napi *bnapi;
5323
5324         if (bp->flags & BNXT_FLAG_USING_MSIX) {
5325                 if (BNXT_CHIP_TYPE_NITRO_A0(bp))
5326                         cp_nr_rings--;
5327                 for (i = 0; i < cp_nr_rings; i++) {
5328                         bnapi = bp->bnapi[i];
5329                         netif_napi_add(bp->dev, &bnapi->napi,
5330                                        bnxt_poll, 64);
5331                 }
5332                 if (BNXT_CHIP_TYPE_NITRO_A0(bp)) {
5333                         bnapi = bp->bnapi[cp_nr_rings];
5334                         netif_napi_add(bp->dev, &bnapi->napi,
5335                                        bnxt_poll_nitroa0, 64);
5336                 }
5337         } else {
5338                 bnapi = bp->bnapi[0];
5339                 netif_napi_add(bp->dev, &bnapi->napi, bnxt_poll, 64);
5340         }
5341 }
5342
5343 static void bnxt_disable_napi(struct bnxt *bp)
5344 {
5345         int i;
5346
5347         if (!bp->bnapi)
5348                 return;
5349
5350         for (i = 0; i < bp->cp_nr_rings; i++)
5351                 napi_disable(&bp->bnapi[i]->napi);
5352 }
5353
5354 static void bnxt_enable_napi(struct bnxt *bp)
5355 {
5356         int i;
5357
5358         for (i = 0; i < bp->cp_nr_rings; i++) {
5359                 bp->bnapi[i]->in_reset = false;
5360                 napi_enable(&bp->bnapi[i]->napi);
5361         }
5362 }
5363
5364 void bnxt_tx_disable(struct bnxt *bp)
5365 {
5366         int i;
5367         struct bnxt_tx_ring_info *txr;
5368         struct netdev_queue *txq;
5369
5370         if (bp->tx_ring) {
5371                 for (i = 0; i < bp->tx_nr_rings; i++) {
5372                         txr = &bp->tx_ring[i];
5373                         txq = netdev_get_tx_queue(bp->dev, i);
5374                         txr->dev_state = BNXT_DEV_STATE_CLOSING;
5375                 }
5376         }
5377         /* Stop all TX queues */
5378         netif_tx_disable(bp->dev);
5379         netif_carrier_off(bp->dev);
5380 }
5381
5382 void bnxt_tx_enable(struct bnxt *bp)
5383 {
5384         int i;
5385         struct bnxt_tx_ring_info *txr;
5386         struct netdev_queue *txq;
5387
5388         for (i = 0; i < bp->tx_nr_rings; i++) {
5389                 txr = &bp->tx_ring[i];
5390                 txq = netdev_get_tx_queue(bp->dev, i);
5391                 txr->dev_state = 0;
5392         }
5393         netif_tx_wake_all_queues(bp->dev);
5394         if (bp->link_info.link_up)
5395                 netif_carrier_on(bp->dev);
5396 }
5397
5398 static void bnxt_report_link(struct bnxt *bp)
5399 {
5400         if (bp->link_info.link_up) {
5401                 const char *duplex;
5402                 const char *flow_ctrl;
5403                 u16 speed;
5404
5405                 netif_carrier_on(bp->dev);
5406                 if (bp->link_info.duplex == BNXT_LINK_DUPLEX_FULL)
5407                         duplex = "full";
5408                 else
5409                         duplex = "half";
5410                 if (bp->link_info.pause == BNXT_LINK_PAUSE_BOTH)
5411                         flow_ctrl = "ON - receive & transmit";
5412                 else if (bp->link_info.pause == BNXT_LINK_PAUSE_TX)
5413                         flow_ctrl = "ON - transmit";
5414                 else if (bp->link_info.pause == BNXT_LINK_PAUSE_RX)
5415                         flow_ctrl = "ON - receive";
5416                 else
5417                         flow_ctrl = "none";
5418                 speed = bnxt_fw_to_ethtool_speed(bp->link_info.link_speed);
5419                 netdev_info(bp->dev, "NIC Link is Up, %d Mbps %s duplex, Flow control: %s\n",
5420                             speed, duplex, flow_ctrl);
5421                 if (bp->flags & BNXT_FLAG_EEE_CAP)
5422                         netdev_info(bp->dev, "EEE is %s\n",
5423                                     bp->eee.eee_active ? "active" :
5424                                                          "not active");
5425         } else {
5426                 netif_carrier_off(bp->dev);
5427                 netdev_err(bp->dev, "NIC Link is Down\n");
5428         }
5429 }
5430
5431 static int bnxt_hwrm_phy_qcaps(struct bnxt *bp)
5432 {
5433         int rc = 0;
5434         struct hwrm_port_phy_qcaps_input req = {0};
5435         struct hwrm_port_phy_qcaps_output *resp = bp->hwrm_cmd_resp_addr;
5436         struct bnxt_link_info *link_info = &bp->link_info;
5437
5438         if (bp->hwrm_spec_code < 0x10201)
5439                 return 0;
5440
5441         bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_PORT_PHY_QCAPS, -1, -1);
5442
5443         mutex_lock(&bp->hwrm_cmd_lock);
5444         rc = _hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT);
5445         if (rc)
5446                 goto hwrm_phy_qcaps_exit;
5447
5448         if (resp->eee_supported & PORT_PHY_QCAPS_RESP_EEE_SUPPORTED) {
5449                 struct ethtool_eee *eee = &bp->eee;
5450                 u16 fw_speeds = le16_to_cpu(resp->supported_speeds_eee_mode);
5451
5452                 bp->flags |= BNXT_FLAG_EEE_CAP;
5453                 eee->supported = _bnxt_fw_to_ethtool_adv_spds(fw_speeds, 0);
5454                 bp->lpi_tmr_lo = le32_to_cpu(resp->tx_lpi_timer_low) &
5455                                  PORT_PHY_QCAPS_RESP_TX_LPI_TIMER_LOW_MASK;
5456                 bp->lpi_tmr_hi = le32_to_cpu(resp->valid_tx_lpi_timer_high) &
5457                                  PORT_PHY_QCAPS_RESP_TX_LPI_TIMER_HIGH_MASK;
5458         }
5459         link_info->support_auto_speeds =
5460                 le16_to_cpu(resp->supported_speeds_auto_mode);
5461
5462 hwrm_phy_qcaps_exit:
5463         mutex_unlock(&bp->hwrm_cmd_lock);
5464         return rc;
5465 }
5466
5467 static int bnxt_update_link(struct bnxt *bp, bool chng_link_state)
5468 {
5469         int rc = 0;
5470         struct bnxt_link_info *link_info = &bp->link_info;
5471         struct hwrm_port_phy_qcfg_input req = {0};
5472         struct hwrm_port_phy_qcfg_output *resp = bp->hwrm_cmd_resp_addr;
5473         u8 link_up = link_info->link_up;
5474         u16 diff;
5475
5476         bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_PORT_PHY_QCFG, -1, -1);
5477
5478         mutex_lock(&bp->hwrm_cmd_lock);
5479         rc = _hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT);
5480         if (rc) {
5481                 mutex_unlock(&bp->hwrm_cmd_lock);
5482                 return rc;
5483         }
5484
5485         memcpy(&link_info->phy_qcfg_resp, resp, sizeof(*resp));
5486         link_info->phy_link_status = resp->link;
5487         link_info->duplex =  resp->duplex;
5488         link_info->pause = resp->pause;
5489         link_info->auto_mode = resp->auto_mode;
5490         link_info->auto_pause_setting = resp->auto_pause;
5491         link_info->lp_pause = resp->link_partner_adv_pause;
5492         link_info->force_pause_setting = resp->force_pause;
5493         link_info->duplex_setting = resp->duplex;
5494         if (link_info->phy_link_status == BNXT_LINK_LINK)
5495                 link_info->link_speed = le16_to_cpu(resp->link_speed);
5496         else
5497                 link_info->link_speed = 0;
5498         link_info->force_link_speed = le16_to_cpu(resp->force_link_speed);
5499         link_info->support_speeds = le16_to_cpu(resp->support_speeds);
5500         link_info->auto_link_speeds = le16_to_cpu(resp->auto_link_speed_mask);
5501         link_info->lp_auto_link_speeds =
5502                 le16_to_cpu(resp->link_partner_adv_speeds);
5503         link_info->preemphasis = le32_to_cpu(resp->preemphasis);
5504         link_info->phy_ver[0] = resp->phy_maj;
5505         link_info->phy_ver[1] = resp->phy_min;
5506         link_info->phy_ver[2] = resp->phy_bld;
5507         link_info->media_type = resp->media_type;
5508         link_info->phy_type = resp->phy_type;
5509         link_info->transceiver = resp->xcvr_pkg_type;
5510         link_info->phy_addr = resp->eee_config_phy_addr &
5511                               PORT_PHY_QCFG_RESP_PHY_ADDR_MASK;
5512         link_info->module_status = resp->module_status;
5513
5514         if (bp->flags & BNXT_FLAG_EEE_CAP) {
5515                 struct ethtool_eee *eee = &bp->eee;
5516                 u16 fw_speeds;
5517
5518                 eee->eee_active = 0;
5519                 if (resp->eee_config_phy_addr &
5520                     PORT_PHY_QCFG_RESP_EEE_CONFIG_EEE_ACTIVE) {
5521                         eee->eee_active = 1;
5522                         fw_speeds = le16_to_cpu(
5523                                 resp->link_partner_adv_eee_link_speed_mask);
5524                         eee->lp_advertised =
5525                                 _bnxt_fw_to_ethtool_adv_spds(fw_speeds, 0);
5526                 }
5527
5528                 /* Pull initial EEE config */
5529                 if (!chng_link_state) {
5530                         if (resp->eee_config_phy_addr &
5531                             PORT_PHY_QCFG_RESP_EEE_CONFIG_EEE_ENABLED)
5532                                 eee->eee_enabled = 1;
5533
5534                         fw_speeds = le16_to_cpu(resp->adv_eee_link_speed_mask);
5535                         eee->advertised =
5536                                 _bnxt_fw_to_ethtool_adv_spds(fw_speeds, 0);
5537
5538                         if (resp->eee_config_phy_addr &
5539                             PORT_PHY_QCFG_RESP_EEE_CONFIG_EEE_TX_LPI) {
5540                                 __le32 tmr;
5541
5542                                 eee->tx_lpi_enabled = 1;
5543                                 tmr = resp->xcvr_identifier_type_tx_lpi_timer;
5544                                 eee->tx_lpi_timer = le32_to_cpu(tmr) &
5545                                         PORT_PHY_QCFG_RESP_TX_LPI_TIMER_MASK;
5546                         }
5547                 }
5548         }
5549         /* TODO: need to add more logic to report VF link */
5550         if (chng_link_state) {
5551                 if (link_info->phy_link_status == BNXT_LINK_LINK)
5552                         link_info->link_up = 1;
5553                 else
5554                         link_info->link_up = 0;
5555                 if (link_up != link_info->link_up)
5556                         bnxt_report_link(bp);
5557         } else {
5558                 /* alwasy link down if not require to update link state */
5559                 link_info->link_up = 0;
5560         }
5561         mutex_unlock(&bp->hwrm_cmd_lock);
5562
5563         diff = link_info->support_auto_speeds ^ link_info->advertising;
5564         if ((link_info->support_auto_speeds | diff) !=
5565             link_info->support_auto_speeds) {
5566                 /* An advertised speed is no longer supported, so we need to
5567                  * update the advertisement settings.  Caller holds RTNL
5568                  * so we can modify link settings.
5569                  */
5570                 link_info->advertising = link_info->support_auto_speeds;
5571                 if (link_info->autoneg & BNXT_AUTONEG_SPEED)
5572                         bnxt_hwrm_set_link_setting(bp, true, false);
5573         }
5574         return 0;
5575 }
5576
5577 static void bnxt_get_port_module_status(struct bnxt *bp)
5578 {
5579         struct bnxt_link_info *link_info = &bp->link_info;
5580         struct hwrm_port_phy_qcfg_output *resp = &link_info->phy_qcfg_resp;
5581         u8 module_status;
5582
5583         if (bnxt_update_link(bp, true))
5584                 return;
5585
5586         module_status = link_info->module_status;
5587         switch (module_status) {
5588         case PORT_PHY_QCFG_RESP_MODULE_STATUS_DISABLETX:
5589         case PORT_PHY_QCFG_RESP_MODULE_STATUS_PWRDOWN:
5590         case PORT_PHY_QCFG_RESP_MODULE_STATUS_WARNINGMSG:
5591                 netdev_warn(bp->dev, "Unqualified SFP+ module detected on port %d\n",
5592                             bp->pf.port_id);
5593                 if (bp->hwrm_spec_code >= 0x10201) {
5594                         netdev_warn(bp->dev, "Module part number %s\n",
5595                                     resp->phy_vendor_partnumber);
5596                 }
5597                 if (module_status == PORT_PHY_QCFG_RESP_MODULE_STATUS_DISABLETX)
5598                         netdev_warn(bp->dev, "TX is disabled\n");
5599                 if (module_status == PORT_PHY_QCFG_RESP_MODULE_STATUS_PWRDOWN)
5600                         netdev_warn(bp->dev, "SFP+ module is shutdown\n");
5601         }
5602 }
5603
5604 static void
5605 bnxt_hwrm_set_pause_common(struct bnxt *bp, struct hwrm_port_phy_cfg_input *req)
5606 {
5607         if (bp->link_info.autoneg & BNXT_AUTONEG_FLOW_CTRL) {
5608                 if (bp->hwrm_spec_code >= 0x10201)
5609                         req->auto_pause =
5610                                 PORT_PHY_CFG_REQ_AUTO_PAUSE_AUTONEG_PAUSE;
5611                 if (bp->link_info.req_flow_ctrl & BNXT_LINK_PAUSE_RX)
5612                         req->auto_pause |= PORT_PHY_CFG_REQ_AUTO_PAUSE_RX;
5613                 if (bp->link_info.req_flow_ctrl & BNXT_LINK_PAUSE_TX)
5614                         req->auto_pause |= PORT_PHY_CFG_REQ_AUTO_PAUSE_TX;
5615                 req->enables |=
5616                         cpu_to_le32(PORT_PHY_CFG_REQ_ENABLES_AUTO_PAUSE);
5617         } else {
5618                 if (bp->link_info.req_flow_ctrl & BNXT_LINK_PAUSE_RX)
5619                         req->force_pause |= PORT_PHY_CFG_REQ_FORCE_PAUSE_RX;
5620                 if (bp->link_info.req_flow_ctrl & BNXT_LINK_PAUSE_TX)
5621                         req->force_pause |= PORT_PHY_CFG_REQ_FORCE_PAUSE_TX;
5622                 req->enables |=
5623                         cpu_to_le32(PORT_PHY_CFG_REQ_ENABLES_FORCE_PAUSE);
5624                 if (bp->hwrm_spec_code >= 0x10201) {
5625                         req->auto_pause = req->force_pause;
5626                         req->enables |= cpu_to_le32(
5627                                 PORT_PHY_CFG_REQ_ENABLES_AUTO_PAUSE);
5628                 }
5629         }
5630 }
5631
5632 static void bnxt_hwrm_set_link_common(struct bnxt *bp,
5633                                       struct hwrm_port_phy_cfg_input *req)
5634 {
5635         u8 autoneg = bp->link_info.autoneg;
5636         u16 fw_link_speed = bp->link_info.req_link_speed;
5637         u16 advertising = bp->link_info.advertising;
5638
5639         if (autoneg & BNXT_AUTONEG_SPEED) {
5640                 req->auto_mode |=
5641                         PORT_PHY_CFG_REQ_AUTO_MODE_SPEED_MASK;
5642
5643                 req->enables |= cpu_to_le32(
5644                         PORT_PHY_CFG_REQ_ENABLES_AUTO_LINK_SPEED_MASK);
5645                 req->auto_link_speed_mask = cpu_to_le16(advertising);
5646
5647                 req->enables |= cpu_to_le32(PORT_PHY_CFG_REQ_ENABLES_AUTO_MODE);
5648                 req->flags |=
5649                         cpu_to_le32(PORT_PHY_CFG_REQ_FLAGS_RESTART_AUTONEG);
5650         } else {
5651                 req->force_link_speed = cpu_to_le16(fw_link_speed);
5652                 req->flags |= cpu_to_le32(PORT_PHY_CFG_REQ_FLAGS_FORCE);
5653         }
5654
5655         /* tell chimp that the setting takes effect immediately */
5656         req->flags |= cpu_to_le32(PORT_PHY_CFG_REQ_FLAGS_RESET_PHY);
5657 }
5658
5659 int bnxt_hwrm_set_pause(struct bnxt *bp)
5660 {
5661         struct hwrm_port_phy_cfg_input req = {0};
5662         int rc;
5663
5664         bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_PORT_PHY_CFG, -1, -1);
5665         bnxt_hwrm_set_pause_common(bp, &req);
5666
5667         if ((bp->link_info.autoneg & BNXT_AUTONEG_FLOW_CTRL) ||
5668             bp->link_info.force_link_chng)
5669                 bnxt_hwrm_set_link_common(bp, &req);
5670
5671         mutex_lock(&bp->hwrm_cmd_lock);
5672         rc = _hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT);
5673         if (!rc && !(bp->link_info.autoneg & BNXT_AUTONEG_FLOW_CTRL)) {
5674                 /* since changing of pause setting doesn't trigger any link
5675                  * change event, the driver needs to update the current pause
5676                  * result upon successfully return of the phy_cfg command
5677                  */
5678                 bp->link_info.pause =
5679                 bp->link_info.force_pause_setting = bp->link_info.req_flow_ctrl;
5680                 bp->link_info.auto_pause_setting = 0;
5681                 if (!bp->link_info.force_link_chng)
5682                         bnxt_report_link(bp);
5683         }
5684         bp->link_info.force_link_chng = false;
5685         mutex_unlock(&bp->hwrm_cmd_lock);
5686         return rc;
5687 }
5688
5689 static void bnxt_hwrm_set_eee(struct bnxt *bp,
5690                               struct hwrm_port_phy_cfg_input *req)
5691 {
5692         struct ethtool_eee *eee = &bp->eee;
5693
5694         if (eee->eee_enabled) {
5695                 u16 eee_speeds;
5696                 u32 flags = PORT_PHY_CFG_REQ_FLAGS_EEE_ENABLE;
5697
5698                 if (eee->tx_lpi_enabled)
5699                         flags |= PORT_PHY_CFG_REQ_FLAGS_EEE_TX_LPI_ENABLE;
5700                 else
5701                         flags |= PORT_PHY_CFG_REQ_FLAGS_EEE_TX_LPI_DISABLE;
5702
5703                 req->flags |= cpu_to_le32(flags);
5704                 eee_speeds = bnxt_get_fw_auto_link_speeds(eee->advertised);
5705                 req->eee_link_speed_mask = cpu_to_le16(eee_speeds);
5706                 req->tx_lpi_timer = cpu_to_le32(eee->tx_lpi_timer);
5707         } else {
5708                 req->flags |= cpu_to_le32(PORT_PHY_CFG_REQ_FLAGS_EEE_DISABLE);
5709         }
5710 }
5711
5712 int bnxt_hwrm_set_link_setting(struct bnxt *bp, bool set_pause, bool set_eee)
5713 {
5714         struct hwrm_port_phy_cfg_input req = {0};
5715
5716         bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_PORT_PHY_CFG, -1, -1);
5717         if (set_pause)
5718                 bnxt_hwrm_set_pause_common(bp, &req);
5719
5720         bnxt_hwrm_set_link_common(bp, &req);
5721
5722         if (set_eee)
5723                 bnxt_hwrm_set_eee(bp, &req);
5724         return hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT);
5725 }
5726
5727 static int bnxt_hwrm_shutdown_link(struct bnxt *bp)
5728 {
5729         struct hwrm_port_phy_cfg_input req = {0};
5730
5731         if (!BNXT_SINGLE_PF(bp))
5732                 return 0;
5733
5734         if (pci_num_vf(bp->pdev))
5735                 return 0;
5736
5737         bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_PORT_PHY_CFG, -1, -1);
5738         req.flags = cpu_to_le32(PORT_PHY_CFG_REQ_FLAGS_FORCE_LINK_DWN);
5739         return hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT);
5740 }
5741
5742 static int bnxt_hwrm_port_led_qcaps(struct bnxt *bp)
5743 {
5744         struct hwrm_port_led_qcaps_output *resp = bp->hwrm_cmd_resp_addr;
5745         struct hwrm_port_led_qcaps_input req = {0};
5746         struct bnxt_pf_info *pf = &bp->pf;
5747         int rc;
5748
5749         if (BNXT_VF(bp) || bp->hwrm_spec_code < 0x10601)
5750                 return 0;
5751
5752         bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_PORT_LED_QCAPS, -1, -1);
5753         req.port_id = cpu_to_le16(pf->port_id);
5754         mutex_lock(&bp->hwrm_cmd_lock);
5755         rc = _hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT);
5756         if (rc) {
5757                 mutex_unlock(&bp->hwrm_cmd_lock);
5758                 return rc;
5759         }
5760         if (resp->num_leds > 0 && resp->num_leds < BNXT_MAX_LED) {
5761                 int i;
5762
5763                 bp->num_leds = resp->num_leds;
5764                 memcpy(bp->leds, &resp->led0_id, sizeof(bp->leds[0]) *
5765                                                  bp->num_leds);
5766                 for (i = 0; i < bp->num_leds; i++) {
5767                         struct bnxt_led_info *led = &bp->leds[i];
5768                         __le16 caps = led->led_state_caps;
5769
5770                         if (!led->led_group_id ||
5771                             !BNXT_LED_ALT_BLINK_CAP(caps)) {
5772                                 bp->num_leds = 0;
5773                                 break;
5774                         }
5775                 }
5776         }
5777         mutex_unlock(&bp->hwrm_cmd_lock);
5778         return 0;
5779 }
5780
5781 static bool bnxt_eee_config_ok(struct bnxt *bp)
5782 {
5783         struct ethtool_eee *eee = &bp->eee;
5784         struct bnxt_link_info *link_info = &bp->link_info;
5785
5786         if (!(bp->flags & BNXT_FLAG_EEE_CAP))
5787                 return true;
5788
5789         if (eee->eee_enabled) {
5790                 u32 advertising =
5791                         _bnxt_fw_to_ethtool_adv_spds(link_info->advertising, 0);
5792
5793                 if (!(link_info->autoneg & BNXT_AUTONEG_SPEED)) {
5794                         eee->eee_enabled = 0;
5795                         return false;
5796                 }
5797                 if (eee->advertised & ~advertising) {
5798                         eee->advertised = advertising & eee->supported;
5799                         return false;
5800                 }
5801         }
5802         return true;
5803 }
5804
5805 static int bnxt_update_phy_setting(struct bnxt *bp)
5806 {
5807         int rc;
5808         bool update_link = false;
5809         bool update_pause = false;
5810         bool update_eee = false;
5811         struct bnxt_link_info *link_info = &bp->link_info;
5812
5813         rc = bnxt_update_link(bp, true);
5814         if (rc) {
5815                 netdev_err(bp->dev, "failed to update link (rc: %x)\n",
5816                            rc);
5817                 return rc;
5818         }
5819         if ((link_info->autoneg & BNXT_AUTONEG_FLOW_CTRL) &&
5820             (link_info->auto_pause_setting & BNXT_LINK_PAUSE_BOTH) !=
5821             link_info->req_flow_ctrl)
5822                 update_pause = true;
5823         if (!(link_info->autoneg & BNXT_AUTONEG_FLOW_CTRL) &&
5824             link_info->force_pause_setting != link_info->req_flow_ctrl)
5825                 update_pause = true;
5826         if (!(link_info->autoneg & BNXT_AUTONEG_SPEED)) {
5827                 if (BNXT_AUTO_MODE(link_info->auto_mode))
5828                         update_link = true;
5829                 if (link_info->req_link_speed != link_info->force_link_speed)
5830                         update_link = true;
5831                 if (link_info->req_duplex != link_info->duplex_setting)
5832                         update_link = true;
5833         } else {
5834                 if (link_info->auto_mode == BNXT_LINK_AUTO_NONE)
5835                         update_link = true;
5836                 if (link_info->advertising != link_info->auto_link_speeds)
5837                         update_link = true;
5838         }
5839
5840         /* The last close may have shutdown the link, so need to call
5841          * PHY_CFG to bring it back up.
5842          */
5843         if (!netif_carrier_ok(bp->dev))
5844                 update_link = true;
5845
5846         if (!bnxt_eee_config_ok(bp))
5847                 update_eee = true;
5848
5849         if (update_link)
5850                 rc = bnxt_hwrm_set_link_setting(bp, update_pause, update_eee);
5851         else if (update_pause)
5852                 rc = bnxt_hwrm_set_pause(bp);
5853         if (rc) {
5854                 netdev_err(bp->dev, "failed to update phy setting (rc: %x)\n",
5855                            rc);
5856                 return rc;
5857         }
5858
5859         return rc;
5860 }
5861
5862 /* Common routine to pre-map certain register block to different GRC window.
5863  * A PF has 16 4K windows and a VF has 4 4K windows. However, only 15 windows
5864  * in PF and 3 windows in VF that can be customized to map in different
5865  * register blocks.
5866  */
5867 static void bnxt_preset_reg_win(struct bnxt *bp)
5868 {
5869         if (BNXT_PF(bp)) {
5870                 /* CAG registers map to GRC window #4 */
5871                 writel(BNXT_CAG_REG_BASE,
5872                        bp->bar0 + BNXT_GRCPF_REG_WINDOW_BASE_OUT + 12);
5873         }
5874 }
5875
5876 static int __bnxt_open_nic(struct bnxt *bp, bool irq_re_init, bool link_re_init)
5877 {
5878         int rc = 0;
5879
5880         bnxt_preset_reg_win(bp);
5881         netif_carrier_off(bp->dev);
5882         if (irq_re_init) {
5883                 rc = bnxt_setup_int_mode(bp);
5884                 if (rc) {
5885                         netdev_err(bp->dev, "bnxt_setup_int_mode err: %x\n",
5886                                    rc);
5887                         return rc;
5888                 }
5889         }
5890         if ((bp->flags & BNXT_FLAG_RFS) &&
5891             !(bp->flags & BNXT_FLAG_USING_MSIX)) {
5892                 /* disable RFS if falling back to INTA */
5893                 bp->dev->hw_features &= ~NETIF_F_NTUPLE;
5894                 bp->flags &= ~BNXT_FLAG_RFS;
5895         }
5896
5897         rc = bnxt_alloc_mem(bp, irq_re_init);
5898         if (rc) {
5899                 netdev_err(bp->dev, "bnxt_alloc_mem err: %x\n", rc);
5900                 goto open_err_free_mem;
5901         }
5902
5903         if (irq_re_init) {
5904                 bnxt_init_napi(bp);
5905                 rc = bnxt_request_irq(bp);
5906                 if (rc) {
5907                         netdev_err(bp->dev, "bnxt_request_irq err: %x\n", rc);
5908                         goto open_err;
5909                 }
5910         }
5911
5912         bnxt_enable_napi(bp);
5913
5914         rc = bnxt_init_nic(bp, irq_re_init);
5915         if (rc) {
5916                 netdev_err(bp->dev, "bnxt_init_nic err: %x\n", rc);
5917                 goto open_err;
5918         }
5919
5920         if (link_re_init) {
5921                 rc = bnxt_update_phy_setting(bp);
5922                 if (rc)
5923                         netdev_warn(bp->dev, "failed to update phy settings\n");
5924         }
5925
5926         if (irq_re_init)
5927                 udp_tunnel_get_rx_info(bp->dev);
5928
5929         set_bit(BNXT_STATE_OPEN, &bp->state);
5930         bnxt_enable_int(bp);
5931         /* Enable TX queues */
5932         bnxt_tx_enable(bp);
5933         mod_timer(&bp->timer, jiffies + bp->current_interval);
5934         /* Poll link status and check for SFP+ module status */
5935         bnxt_get_port_module_status(bp);
5936
5937         return 0;
5938
5939 open_err:
5940         bnxt_disable_napi(bp);
5941         bnxt_del_napi(bp);
5942
5943 open_err_free_mem:
5944         bnxt_free_skbs(bp);
5945         bnxt_free_irq(bp);
5946         bnxt_free_mem(bp, true);
5947         return rc;
5948 }
5949
5950 /* rtnl_lock held */
5951 int bnxt_open_nic(struct bnxt *bp, bool irq_re_init, bool link_re_init)
5952 {
5953         int rc = 0;
5954
5955         rc = __bnxt_open_nic(bp, irq_re_init, link_re_init);
5956         if (rc) {
5957                 netdev_err(bp->dev, "nic open fail (rc: %x)\n", rc);
5958                 dev_close(bp->dev);
5959         }
5960         return rc;
5961 }
5962
5963 static int bnxt_open(struct net_device *dev)
5964 {
5965         struct bnxt *bp = netdev_priv(dev);
5966
5967         return __bnxt_open_nic(bp, true, true);
5968 }
5969
5970 int bnxt_close_nic(struct bnxt *bp, bool irq_re_init, bool link_re_init)
5971 {
5972         int rc = 0;
5973
5974 #ifdef CONFIG_BNXT_SRIOV
5975         if (bp->sriov_cfg) {
5976                 rc = wait_event_interruptible_timeout(bp->sriov_cfg_wait,
5977                                                       !bp->sriov_cfg,
5978                                                       BNXT_SRIOV_CFG_WAIT_TMO);
5979                 if (rc)
5980                         netdev_warn(bp->dev, "timeout waiting for SRIOV config operation to complete!\n");
5981         }
5982 #endif
5983         /* Change device state to avoid TX queue wake up's */
5984         bnxt_tx_disable(bp);
5985
5986         clear_bit(BNXT_STATE_OPEN, &bp->state);
5987         smp_mb__after_atomic();
5988         while (test_bit(BNXT_STATE_IN_SP_TASK, &bp->state))
5989                 msleep(20);
5990
5991         /* Flush rings and and disable interrupts */
5992         bnxt_shutdown_nic(bp, irq_re_init);
5993
5994         /* TODO CHIMP_FW: Link/PHY related cleanup if (link_re_init) */
5995
5996         bnxt_disable_napi(bp);
5997         del_timer_sync(&bp->timer);
5998         bnxt_free_skbs(bp);
5999
6000         if (irq_re_init) {
6001                 bnxt_free_irq(bp);
6002                 bnxt_del_napi(bp);
6003         }
6004         bnxt_free_mem(bp, irq_re_init);
6005         return rc;
6006 }
6007
6008 static int bnxt_close(struct net_device *dev)
6009 {
6010         struct bnxt *bp = netdev_priv(dev);
6011
6012         bnxt_close_nic(bp, true, true);
6013         bnxt_hwrm_shutdown_link(bp);
6014         return 0;
6015 }
6016
6017 /* rtnl_lock held */
6018 static int bnxt_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd)
6019 {
6020         switch (cmd) {
6021         case SIOCGMIIPHY:
6022                 /* fallthru */
6023         case SIOCGMIIREG: {
6024                 if (!netif_running(dev))
6025                         return -EAGAIN;
6026
6027                 return 0;
6028         }
6029
6030         case SIOCSMIIREG:
6031                 if (!netif_running(dev))
6032                         return -EAGAIN;
6033
6034                 return 0;
6035
6036         default:
6037                 /* do nothing */
6038                 break;
6039         }
6040         return -EOPNOTSUPP;
6041 }
6042
6043 static void
6044 bnxt_get_stats64(struct net_device *dev, struct rtnl_link_stats64 *stats)
6045 {
6046         u32 i;
6047         struct bnxt *bp = netdev_priv(dev);
6048
6049         if (!bp->bnapi)
6050                 return;
6051
6052         /* TODO check if we need to synchronize with bnxt_close path */
6053         for (i = 0; i < bp->cp_nr_rings; i++) {
6054                 struct bnxt_napi *bnapi = bp->bnapi[i];
6055                 struct bnxt_cp_ring_info *cpr = &bnapi->cp_ring;
6056                 struct ctx_hw_stats *hw_stats = cpr->hw_stats;
6057
6058                 stats->rx_packets += le64_to_cpu(hw_stats->rx_ucast_pkts);
6059                 stats->rx_packets += le64_to_cpu(hw_stats->rx_mcast_pkts);
6060                 stats->rx_packets += le64_to_cpu(hw_stats->rx_bcast_pkts);
6061
6062                 stats->tx_packets += le64_to_cpu(hw_stats->tx_ucast_pkts);
6063                 stats->tx_packets += le64_to_cpu(hw_stats->tx_mcast_pkts);
6064                 stats->tx_packets += le64_to_cpu(hw_stats->tx_bcast_pkts);
6065
6066                 stats->rx_bytes += le64_to_cpu(hw_stats->rx_ucast_bytes);
6067                 stats->rx_bytes += le64_to_cpu(hw_stats->rx_mcast_bytes);
6068                 stats->rx_bytes += le64_to_cpu(hw_stats->rx_bcast_bytes);
6069
6070                 stats->tx_bytes += le64_to_cpu(hw_stats->tx_ucast_bytes);
6071                 stats->tx_bytes += le64_to_cpu(hw_stats->tx_mcast_bytes);
6072                 stats->tx_bytes += le64_to_cpu(hw_stats->tx_bcast_bytes);
6073
6074                 stats->rx_missed_errors +=
6075                         le64_to_cpu(hw_stats->rx_discard_pkts);
6076
6077                 stats->multicast += le64_to_cpu(hw_stats->rx_mcast_pkts);
6078
6079                 stats->tx_dropped += le64_to_cpu(hw_stats->tx_drop_pkts);
6080         }
6081
6082         if (bp->flags & BNXT_FLAG_PORT_STATS) {
6083                 struct rx_port_stats *rx = bp->hw_rx_port_stats;
6084                 struct tx_port_stats *tx = bp->hw_tx_port_stats;
6085
6086                 stats->rx_crc_errors = le64_to_cpu(rx->rx_fcs_err_frames);
6087                 stats->rx_frame_errors = le64_to_cpu(rx->rx_align_err_frames);
6088                 stats->rx_length_errors = le64_to_cpu(rx->rx_undrsz_frames) +
6089                                           le64_to_cpu(rx->rx_ovrsz_frames) +
6090                                           le64_to_cpu(rx->rx_runt_frames);
6091                 stats->rx_errors = le64_to_cpu(rx->rx_false_carrier_frames) +
6092                                    le64_to_cpu(rx->rx_jbr_frames);
6093                 stats->collisions = le64_to_cpu(tx->tx_total_collisions);
6094                 stats->tx_fifo_errors = le64_to_cpu(tx->tx_fifo_underruns);
6095                 stats->tx_errors = le64_to_cpu(tx->tx_err);
6096         }
6097 }
6098
6099 static bool bnxt_mc_list_updated(struct bnxt *bp, u32 *rx_mask)
6100 {
6101         struct net_device *dev = bp->dev;
6102         struct bnxt_vnic_info *vnic = &bp->vnic_info[0];
6103         struct netdev_hw_addr *ha;
6104         u8 *haddr;
6105         int mc_count = 0;
6106         bool update = false;
6107         int off = 0;
6108
6109         netdev_for_each_mc_addr(ha, dev) {
6110                 if (mc_count >= BNXT_MAX_MC_ADDRS) {
6111                         *rx_mask |= CFA_L2_SET_RX_MASK_REQ_MASK_ALL_MCAST;
6112                         vnic->mc_list_count = 0;
6113                         return false;
6114                 }
6115                 haddr = ha->addr;
6116                 if (!ether_addr_equal(haddr, vnic->mc_list + off)) {
6117                         memcpy(vnic->mc_list + off, haddr, ETH_ALEN);
6118                         update = true;
6119                 }
6120                 off += ETH_ALEN;
6121                 mc_count++;
6122         }
6123         if (mc_count)
6124                 *rx_mask |= CFA_L2_SET_RX_MASK_REQ_MASK_MCAST;
6125
6126         if (mc_count != vnic->mc_list_count) {
6127                 vnic->mc_list_count = mc_count;
6128                 update = true;
6129         }
6130         return update;
6131 }
6132
6133 static bool bnxt_uc_list_updated(struct bnxt *bp)
6134 {
6135         struct net_device *dev = bp->dev;
6136         struct bnxt_vnic_info *vnic = &bp->vnic_info[0];
6137         struct netdev_hw_addr *ha;
6138         int off = 0;
6139
6140         if (netdev_uc_count(dev) != (vnic->uc_filter_count - 1))
6141                 return true;
6142
6143         netdev_for_each_uc_addr(ha, dev) {
6144                 if (!ether_addr_equal(ha->addr, vnic->uc_list + off))
6145                         return true;
6146
6147                 off += ETH_ALEN;
6148         }
6149         return false;
6150 }
6151
6152 static void bnxt_set_rx_mode(struct net_device *dev)
6153 {
6154         struct bnxt *bp = netdev_priv(dev);
6155         struct bnxt_vnic_info *vnic = &bp->vnic_info[0];
6156         u32 mask = vnic->rx_mask;
6157         bool mc_update = false;
6158         bool uc_update;
6159
6160         if (!netif_running(dev))
6161                 return;
6162
6163         mask &= ~(CFA_L2_SET_RX_MASK_REQ_MASK_PROMISCUOUS |
6164                   CFA_L2_SET_RX_MASK_REQ_MASK_MCAST |
6165                   CFA_L2_SET_RX_MASK_REQ_MASK_ALL_MCAST);
6166
6167         if ((dev->flags & IFF_PROMISC) && bnxt_promisc_ok(bp))
6168                 mask |= CFA_L2_SET_RX_MASK_REQ_MASK_PROMISCUOUS;
6169
6170         uc_update = bnxt_uc_list_updated(bp);
6171
6172         if (dev->flags & IFF_ALLMULTI) {
6173                 mask |= CFA_L2_SET_RX_MASK_REQ_MASK_ALL_MCAST;
6174                 vnic->mc_list_count = 0;
6175         } else {
6176                 mc_update = bnxt_mc_list_updated(bp, &mask);
6177         }
6178
6179         if (mask != vnic->rx_mask || uc_update || mc_update) {
6180                 vnic->rx_mask = mask;
6181
6182                 set_bit(BNXT_RX_MASK_SP_EVENT, &bp->sp_event);
6183                 schedule_work(&bp->sp_task);
6184         }
6185 }
6186
6187 static int bnxt_cfg_rx_mode(struct bnxt *bp)
6188 {
6189         struct net_device *dev = bp->dev;
6190         struct bnxt_vnic_info *vnic = &bp->vnic_info[0];
6191         struct netdev_hw_addr *ha;
6192         int i, off = 0, rc;
6193         bool uc_update;
6194
6195         netif_addr_lock_bh(dev);
6196         uc_update = bnxt_uc_list_updated(bp);
6197         netif_addr_unlock_bh(dev);
6198
6199         if (!uc_update)
6200                 goto skip_uc;
6201
6202         mutex_lock(&bp->hwrm_cmd_lock);
6203         for (i = 1; i < vnic->uc_filter_count; i++) {
6204                 struct hwrm_cfa_l2_filter_free_input req = {0};
6205
6206                 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_CFA_L2_FILTER_FREE, -1,
6207                                        -1);
6208
6209                 req.l2_filter_id = vnic->fw_l2_filter_id[i];
6210
6211                 rc = _hwrm_send_message(bp, &req, sizeof(req),
6212                                         HWRM_CMD_TIMEOUT);
6213         }
6214         mutex_unlock(&bp->hwrm_cmd_lock);
6215
6216         vnic->uc_filter_count = 1;
6217
6218         netif_addr_lock_bh(dev);
6219         if (netdev_uc_count(dev) > (BNXT_MAX_UC_ADDRS - 1)) {
6220                 vnic->rx_mask |= CFA_L2_SET_RX_MASK_REQ_MASK_PROMISCUOUS;
6221         } else {
6222                 netdev_for_each_uc_addr(ha, dev) {
6223                         memcpy(vnic->uc_list + off, ha->addr, ETH_ALEN);
6224                         off += ETH_ALEN;
6225                         vnic->uc_filter_count++;
6226                 }
6227         }
6228         netif_addr_unlock_bh(dev);
6229
6230         for (i = 1, off = 0; i < vnic->uc_filter_count; i++, off += ETH_ALEN) {
6231                 rc = bnxt_hwrm_set_vnic_filter(bp, 0, i, vnic->uc_list + off);
6232                 if (rc) {
6233                         netdev_err(bp->dev, "HWRM vnic filter failure rc: %x\n",
6234                                    rc);
6235                         vnic->uc_filter_count = i;
6236                         return rc;
6237                 }
6238         }
6239
6240 skip_uc:
6241         rc = bnxt_hwrm_cfa_l2_set_rx_mask(bp, 0);
6242         if (rc)
6243                 netdev_err(bp->dev, "HWRM cfa l2 rx mask failure rc: %x\n",
6244                            rc);
6245
6246         return rc;
6247 }
6248
6249 /* If the chip and firmware supports RFS */
6250 static bool bnxt_rfs_supported(struct bnxt *bp)
6251 {
6252         if (BNXT_PF(bp) && !BNXT_CHIP_TYPE_NITRO_A0(bp))
6253                 return true;
6254         if (bp->flags & BNXT_FLAG_NEW_RSS_CAP)
6255                 return true;
6256         return false;
6257 }
6258
6259 /* If runtime conditions support RFS */
6260 static bool bnxt_rfs_capable(struct bnxt *bp)
6261 {
6262 #ifdef CONFIG_RFS_ACCEL
6263         int vnics, max_vnics, max_rss_ctxs;
6264
6265         if (BNXT_VF(bp) || !(bp->flags & BNXT_FLAG_MSIX_CAP))
6266                 return false;
6267
6268         vnics = 1 + bp->rx_nr_rings;
6269         max_vnics = bnxt_get_max_func_vnics(bp);
6270         max_rss_ctxs = bnxt_get_max_func_rss_ctxs(bp);
6271
6272         /* RSS contexts not a limiting factor */
6273         if (bp->flags & BNXT_FLAG_NEW_RSS_CAP)
6274                 max_rss_ctxs = max_vnics;
6275         if (vnics > max_vnics || vnics > max_rss_ctxs) {
6276                 netdev_warn(bp->dev,
6277                             "Not enough resources to support NTUPLE filters, enough resources for up to %d rx rings\n",
6278                             min(max_rss_ctxs - 1, max_vnics - 1));
6279                 return false;
6280         }
6281
6282         return true;
6283 #else
6284         return false;
6285 #endif
6286 }
6287
6288 static netdev_features_t bnxt_fix_features(struct net_device *dev,
6289                                            netdev_features_t features)
6290 {
6291         struct bnxt *bp = netdev_priv(dev);
6292
6293         if ((features & NETIF_F_NTUPLE) && !bnxt_rfs_capable(bp))
6294                 features &= ~NETIF_F_NTUPLE;
6295
6296         /* Both CTAG and STAG VLAN accelaration on the RX side have to be
6297          * turned on or off together.
6298          */
6299         if ((features & (NETIF_F_HW_VLAN_CTAG_RX | NETIF_F_HW_VLAN_STAG_RX)) !=
6300             (NETIF_F_HW_VLAN_CTAG_RX | NETIF_F_HW_VLAN_STAG_RX)) {
6301                 if (dev->features & NETIF_F_HW_VLAN_CTAG_RX)
6302                         features &= ~(NETIF_F_HW_VLAN_CTAG_RX |
6303                                       NETIF_F_HW_VLAN_STAG_RX);
6304                 else
6305                         features |= NETIF_F_HW_VLAN_CTAG_RX |
6306                                     NETIF_F_HW_VLAN_STAG_RX;
6307         }
6308 #ifdef CONFIG_BNXT_SRIOV
6309         if (BNXT_VF(bp)) {
6310                 if (bp->vf.vlan) {
6311                         features &= ~(NETIF_F_HW_VLAN_CTAG_RX |
6312                                       NETIF_F_HW_VLAN_STAG_RX);
6313                 }
6314         }
6315 #endif
6316         return features;
6317 }
6318
6319 static int bnxt_set_features(struct net_device *dev, netdev_features_t features)
6320 {
6321         struct bnxt *bp = netdev_priv(dev);
6322         u32 flags = bp->flags;
6323         u32 changes;
6324         int rc = 0;
6325         bool re_init = false;
6326         bool update_tpa = false;
6327
6328         flags &= ~BNXT_FLAG_ALL_CONFIG_FEATS;
6329         if ((features & NETIF_F_GRO) && !BNXT_CHIP_TYPE_NITRO_A0(bp))
6330                 flags |= BNXT_FLAG_GRO;
6331         if (features & NETIF_F_LRO)
6332                 flags |= BNXT_FLAG_LRO;
6333
6334         if (bp->flags & BNXT_FLAG_NO_AGG_RINGS)
6335                 flags &= ~BNXT_FLAG_TPA;
6336
6337         if (features & NETIF_F_HW_VLAN_CTAG_RX)
6338                 flags |= BNXT_FLAG_STRIP_VLAN;
6339
6340         if (features & NETIF_F_NTUPLE)
6341                 flags |= BNXT_FLAG_RFS;
6342
6343         changes = flags ^ bp->flags;
6344         if (changes & BNXT_FLAG_TPA) {
6345                 update_tpa = true;
6346                 if ((bp->flags & BNXT_FLAG_TPA) == 0 ||
6347                     (flags & BNXT_FLAG_TPA) == 0)
6348                         re_init = true;
6349         }
6350
6351         if (changes & ~BNXT_FLAG_TPA)
6352                 re_init = true;
6353
6354         if (flags != bp->flags) {
6355                 u32 old_flags = bp->flags;
6356
6357                 bp->flags = flags;
6358
6359                 if (!test_bit(BNXT_STATE_OPEN, &bp->state)) {
6360                         if (update_tpa)
6361                                 bnxt_set_ring_params(bp);
6362                         return rc;
6363                 }
6364
6365                 if (re_init) {
6366                         bnxt_close_nic(bp, false, false);
6367                         if (update_tpa)
6368                                 bnxt_set_ring_params(bp);
6369
6370                         return bnxt_open_nic(bp, false, false);
6371                 }
6372                 if (update_tpa) {
6373                         rc = bnxt_set_tpa(bp,
6374                                           (flags & BNXT_FLAG_TPA) ?
6375                                           true : false);
6376                         if (rc)
6377                                 bp->flags = old_flags;
6378                 }
6379         }
6380         return rc;
6381 }
6382
6383 static void bnxt_dump_tx_sw_state(struct bnxt_napi *bnapi)
6384 {
6385         struct bnxt_tx_ring_info *txr = bnapi->tx_ring;
6386         int i = bnapi->index;
6387
6388         if (!txr)
6389                 return;
6390
6391         netdev_info(bnapi->bp->dev, "[%d]: tx{fw_ring: %d prod: %x cons: %x}\n",
6392                     i, txr->tx_ring_struct.fw_ring_id, txr->tx_prod,
6393                     txr->tx_cons);
6394 }
6395
6396 static void bnxt_dump_rx_sw_state(struct bnxt_napi *bnapi)
6397 {
6398         struct bnxt_rx_ring_info *rxr = bnapi->rx_ring;
6399         int i = bnapi->index;
6400
6401         if (!rxr)
6402                 return;
6403
6404         netdev_info(bnapi->bp->dev, "[%d]: rx{fw_ring: %d prod: %x} rx_agg{fw_ring: %d agg_prod: %x sw_agg_prod: %x}\n",
6405                     i, rxr->rx_ring_struct.fw_ring_id, rxr->rx_prod,
6406                     rxr->rx_agg_ring_struct.fw_ring_id, rxr->rx_agg_prod,
6407                     rxr->rx_sw_agg_prod);
6408 }
6409
6410 static void bnxt_dump_cp_sw_state(struct bnxt_napi *bnapi)
6411 {
6412         struct bnxt_cp_ring_info *cpr = &bnapi->cp_ring;
6413         int i = bnapi->index;
6414
6415         netdev_info(bnapi->bp->dev, "[%d]: cp{fw_ring: %d raw_cons: %x}\n",
6416                     i, cpr->cp_ring_struct.fw_ring_id, cpr->cp_raw_cons);
6417 }
6418
6419 static void bnxt_dbg_dump_states(struct bnxt *bp)
6420 {
6421         int i;
6422         struct bnxt_napi *bnapi;
6423
6424         for (i = 0; i < bp->cp_nr_rings; i++) {
6425                 bnapi = bp->bnapi[i];
6426                 if (netif_msg_drv(bp)) {
6427                         bnxt_dump_tx_sw_state(bnapi);
6428                         bnxt_dump_rx_sw_state(bnapi);
6429                         bnxt_dump_cp_sw_state(bnapi);
6430                 }
6431         }
6432 }
6433
6434 static void bnxt_reset_task(struct bnxt *bp, bool silent)
6435 {
6436         if (!silent)
6437                 bnxt_dbg_dump_states(bp);
6438         if (netif_running(bp->dev)) {
6439                 bnxt_close_nic(bp, false, false);
6440                 bnxt_open_nic(bp, false, false);
6441         }
6442 }
6443
6444 static void bnxt_tx_timeout(struct net_device *dev)
6445 {
6446         struct bnxt *bp = netdev_priv(dev);
6447
6448         netdev_err(bp->dev,  "TX timeout detected, starting reset task!\n");
6449         set_bit(BNXT_RESET_TASK_SP_EVENT, &bp->sp_event);
6450         schedule_work(&bp->sp_task);
6451 }
6452
6453 #ifdef CONFIG_NET_POLL_CONTROLLER
6454 static void bnxt_poll_controller(struct net_device *dev)
6455 {
6456         struct bnxt *bp = netdev_priv(dev);
6457         int i;
6458
6459         for (i = 0; i < bp->cp_nr_rings; i++) {
6460                 struct bnxt_irq *irq = &bp->irq_tbl[i];
6461
6462                 disable_irq(irq->vector);
6463                 irq->handler(irq->vector, bp->bnapi[i]);
6464                 enable_irq(irq->vector);
6465         }
6466 }
6467 #endif
6468
6469 static void bnxt_timer(unsigned long data)
6470 {
6471         struct bnxt *bp = (struct bnxt *)data;
6472         struct net_device *dev = bp->dev;
6473
6474         if (!netif_running(dev))
6475                 return;
6476
6477         if (atomic_read(&bp->intr_sem) != 0)
6478                 goto bnxt_restart_timer;
6479
6480         if (bp->link_info.link_up && (bp->flags & BNXT_FLAG_PORT_STATS)) {
6481                 set_bit(BNXT_PERIODIC_STATS_SP_EVENT, &bp->sp_event);
6482                 schedule_work(&bp->sp_task);
6483         }
6484 bnxt_restart_timer:
6485         mod_timer(&bp->timer, jiffies + bp->current_interval);
6486 }
6487
6488 static void bnxt_rtnl_lock_sp(struct bnxt *bp)
6489 {
6490         /* We are called from bnxt_sp_task which has BNXT_STATE_IN_SP_TASK
6491          * set.  If the device is being closed, bnxt_close() may be holding
6492          * rtnl() and waiting for BNXT_STATE_IN_SP_TASK to clear.  So we
6493          * must clear BNXT_STATE_IN_SP_TASK before holding rtnl().
6494          */
6495         clear_bit(BNXT_STATE_IN_SP_TASK, &bp->state);
6496         rtnl_lock();
6497 }
6498
6499 static void bnxt_rtnl_unlock_sp(struct bnxt *bp)
6500 {
6501         set_bit(BNXT_STATE_IN_SP_TASK, &bp->state);
6502         rtnl_unlock();
6503 }
6504
6505 /* Only called from bnxt_sp_task() */
6506 static void bnxt_reset(struct bnxt *bp, bool silent)
6507 {
6508         bnxt_rtnl_lock_sp(bp);
6509         if (test_bit(BNXT_STATE_OPEN, &bp->state))
6510                 bnxt_reset_task(bp, silent);
6511         bnxt_rtnl_unlock_sp(bp);
6512 }
6513
6514 static void bnxt_cfg_ntp_filters(struct bnxt *);
6515
6516 static void bnxt_sp_task(struct work_struct *work)
6517 {
6518         struct bnxt *bp = container_of(work, struct bnxt, sp_task);
6519
6520         set_bit(BNXT_STATE_IN_SP_TASK, &bp->state);
6521         smp_mb__after_atomic();
6522         if (!test_bit(BNXT_STATE_OPEN, &bp->state)) {
6523                 clear_bit(BNXT_STATE_IN_SP_TASK, &bp->state);
6524                 return;
6525         }
6526
6527         if (test_and_clear_bit(BNXT_RX_MASK_SP_EVENT, &bp->sp_event))
6528                 bnxt_cfg_rx_mode(bp);
6529
6530         if (test_and_clear_bit(BNXT_RX_NTP_FLTR_SP_EVENT, &bp->sp_event))
6531                 bnxt_cfg_ntp_filters(bp);
6532         if (test_and_clear_bit(BNXT_HWRM_EXEC_FWD_REQ_SP_EVENT, &bp->sp_event))
6533                 bnxt_hwrm_exec_fwd_req(bp);
6534         if (test_and_clear_bit(BNXT_VXLAN_ADD_PORT_SP_EVENT, &bp->sp_event)) {
6535                 bnxt_hwrm_tunnel_dst_port_alloc(
6536                         bp, bp->vxlan_port,
6537                         TUNNEL_DST_PORT_FREE_REQ_TUNNEL_TYPE_VXLAN);
6538         }
6539         if (test_and_clear_bit(BNXT_VXLAN_DEL_PORT_SP_EVENT, &bp->sp_event)) {
6540                 bnxt_hwrm_tunnel_dst_port_free(
6541                         bp, TUNNEL_DST_PORT_FREE_REQ_TUNNEL_TYPE_VXLAN);
6542         }
6543         if (test_and_clear_bit(BNXT_GENEVE_ADD_PORT_SP_EVENT, &bp->sp_event)) {
6544                 bnxt_hwrm_tunnel_dst_port_alloc(
6545                         bp, bp->nge_port,
6546                         TUNNEL_DST_PORT_FREE_REQ_TUNNEL_TYPE_GENEVE);
6547         }
6548         if (test_and_clear_bit(BNXT_GENEVE_DEL_PORT_SP_EVENT, &bp->sp_event)) {
6549                 bnxt_hwrm_tunnel_dst_port_free(
6550                         bp, TUNNEL_DST_PORT_FREE_REQ_TUNNEL_TYPE_GENEVE);
6551         }
6552         if (test_and_clear_bit(BNXT_PERIODIC_STATS_SP_EVENT, &bp->sp_event))
6553                 bnxt_hwrm_port_qstats(bp);
6554
6555         /* These functions below will clear BNXT_STATE_IN_SP_TASK.  They
6556          * must be the last functions to be called before exiting.
6557          */
6558         if (test_and_clear_bit(BNXT_LINK_CHNG_SP_EVENT, &bp->sp_event)) {
6559                 int rc = 0;
6560
6561                 if (test_and_clear_bit(BNXT_LINK_SPEED_CHNG_SP_EVENT,
6562                                        &bp->sp_event))
6563                         bnxt_hwrm_phy_qcaps(bp);
6564
6565                 bnxt_rtnl_lock_sp(bp);
6566                 if (test_bit(BNXT_STATE_OPEN, &bp->state))
6567                         rc = bnxt_update_link(bp, true);
6568                 bnxt_rtnl_unlock_sp(bp);
6569                 if (rc)
6570                         netdev_err(bp->dev, "SP task can't update link (rc: %x)\n",
6571                                    rc);
6572         }
6573         if (test_and_clear_bit(BNXT_HWRM_PORT_MODULE_SP_EVENT, &bp->sp_event)) {
6574                 bnxt_rtnl_lock_sp(bp);
6575                 if (test_bit(BNXT_STATE_OPEN, &bp->state))
6576                         bnxt_get_port_module_status(bp);
6577                 bnxt_rtnl_unlock_sp(bp);
6578         }
6579         if (test_and_clear_bit(BNXT_RESET_TASK_SP_EVENT, &bp->sp_event))
6580                 bnxt_reset(bp, false);
6581
6582         if (test_and_clear_bit(BNXT_RESET_TASK_SILENT_SP_EVENT, &bp->sp_event))
6583                 bnxt_reset(bp, true);
6584
6585         smp_mb__before_atomic();
6586         clear_bit(BNXT_STATE_IN_SP_TASK, &bp->state);
6587 }
6588
6589 /* Under rtnl_lock */
6590 int bnxt_reserve_rings(struct bnxt *bp, int tx, int rx, int tcs, int tx_xdp)
6591 {
6592         int max_rx, max_tx, tx_sets = 1;
6593         int tx_rings_needed;
6594         bool sh = true;
6595         int rc;
6596
6597         if (!(bp->flags & BNXT_FLAG_SHARED_RINGS))
6598                 sh = false;
6599
6600         if (tcs)
6601                 tx_sets = tcs;
6602
6603         rc = bnxt_get_max_rings(bp, &max_rx, &max_tx, sh);
6604         if (rc)
6605                 return rc;
6606
6607         if (max_rx < rx)
6608                 return -ENOMEM;
6609
6610         tx_rings_needed = tx * tx_sets + tx_xdp;
6611         if (max_tx < tx_rings_needed)
6612                 return -ENOMEM;
6613
6614         if (bnxt_hwrm_reserve_tx_rings(bp, &tx_rings_needed) ||
6615             tx_rings_needed < (tx * tx_sets + tx_xdp))
6616                 return -ENOMEM;
6617         return 0;
6618 }
6619
6620 static int bnxt_init_board(struct pci_dev *pdev, struct net_device *dev)
6621 {
6622         int rc;
6623         struct bnxt *bp = netdev_priv(dev);
6624
6625         SET_NETDEV_DEV(dev, &pdev->dev);
6626
6627         /* enable device (incl. PCI PM wakeup), and bus-mastering */
6628         rc = pci_enable_device(pdev);
6629         if (rc) {
6630                 dev_err(&pdev->dev, "Cannot enable PCI device, aborting\n");
6631                 goto init_err;
6632         }
6633
6634         if (!(pci_resource_flags(pdev, 0) & IORESOURCE_MEM)) {
6635                 dev_err(&pdev->dev,
6636                         "Cannot find PCI device base address, aborting\n");
6637                 rc = -ENODEV;
6638                 goto init_err_disable;
6639         }
6640
6641         rc = pci_request_regions(pdev, DRV_MODULE_NAME);
6642         if (rc) {
6643                 dev_err(&pdev->dev, "Cannot obtain PCI resources, aborting\n");
6644                 goto init_err_disable;
6645         }
6646
6647         if (dma_set_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(64)) != 0 &&
6648             dma_set_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(32)) != 0) {
6649                 dev_err(&pdev->dev, "System does not support DMA, aborting\n");
6650                 goto init_err_disable;
6651         }
6652
6653         pci_set_master(pdev);
6654
6655         bp->dev = dev;
6656         bp->pdev = pdev;
6657
6658         bp->bar0 = pci_ioremap_bar(pdev, 0);
6659         if (!bp->bar0) {
6660                 dev_err(&pdev->dev, "Cannot map device registers, aborting\n");
6661                 rc = -ENOMEM;
6662                 goto init_err_release;
6663         }
6664
6665         bp->bar1 = pci_ioremap_bar(pdev, 2);
6666         if (!bp->bar1) {
6667                 dev_err(&pdev->dev, "Cannot map doorbell registers, aborting\n");
6668                 rc = -ENOMEM;
6669                 goto init_err_release;
6670         }
6671
6672         bp->bar2 = pci_ioremap_bar(pdev, 4);
6673         if (!bp->bar2) {
6674                 dev_err(&pdev->dev, "Cannot map bar4 registers, aborting\n");
6675                 rc = -ENOMEM;
6676                 goto init_err_release;
6677         }
6678
6679         pci_enable_pcie_error_reporting(pdev);
6680
6681         INIT_WORK(&bp->sp_task, bnxt_sp_task);
6682
6683         spin_lock_init(&bp->ntp_fltr_lock);
6684
6685         bp->rx_ring_size = BNXT_DEFAULT_RX_RING_SIZE;
6686         bp->tx_ring_size = BNXT_DEFAULT_TX_RING_SIZE;
6687
6688         /* tick values in micro seconds */
6689         bp->rx_coal_ticks = 12;
6690         bp->rx_coal_bufs = 30;
6691         bp->rx_coal_ticks_irq = 1;
6692         bp->rx_coal_bufs_irq = 2;
6693
6694         bp->tx_coal_ticks = 25;
6695         bp->tx_coal_bufs = 30;
6696         bp->tx_coal_ticks_irq = 2;
6697         bp->tx_coal_bufs_irq = 2;
6698
6699         bp->stats_coal_ticks = BNXT_DEF_STATS_COAL_TICKS;
6700
6701         init_timer(&bp->timer);
6702         bp->timer.data = (unsigned long)bp;
6703         bp->timer.function = bnxt_timer;
6704         bp->current_interval = BNXT_TIMER_INTERVAL;
6705
6706         clear_bit(BNXT_STATE_OPEN, &bp->state);
6707
6708         return 0;
6709
6710 init_err_release:
6711         if (bp->bar2) {
6712                 pci_iounmap(pdev, bp->bar2);
6713                 bp->bar2 = NULL;
6714         }
6715
6716         if (bp->bar1) {
6717                 pci_iounmap(pdev, bp->bar1);
6718                 bp->bar1 = NULL;
6719         }
6720
6721         if (bp->bar0) {
6722                 pci_iounmap(pdev, bp->bar0);
6723                 bp->bar0 = NULL;
6724         }
6725
6726         pci_release_regions(pdev);
6727
6728 init_err_disable:
6729         pci_disable_device(pdev);
6730
6731 init_err:
6732         return rc;
6733 }
6734
6735 /* rtnl_lock held */
6736 static int bnxt_change_mac_addr(struct net_device *dev, void *p)
6737 {
6738         struct sockaddr *addr = p;
6739         struct bnxt *bp = netdev_priv(dev);
6740         int rc = 0;
6741
6742         if (!is_valid_ether_addr(addr->sa_data))
6743                 return -EADDRNOTAVAIL;
6744
6745         rc = bnxt_approve_mac(bp, addr->sa_data);
6746         if (rc)
6747                 return rc;
6748
6749         if (ether_addr_equal(addr->sa_data, dev->dev_addr))
6750                 return 0;
6751
6752         memcpy(dev->dev_addr, addr->sa_data, dev->addr_len);
6753         if (netif_running(dev)) {
6754                 bnxt_close_nic(bp, false, false);
6755                 rc = bnxt_open_nic(bp, false, false);
6756         }
6757
6758         return rc;
6759 }
6760
6761 /* rtnl_lock held */
6762 static int bnxt_change_mtu(struct net_device *dev, int new_mtu)
6763 {
6764         struct bnxt *bp = netdev_priv(dev);
6765
6766         if (netif_running(dev))
6767                 bnxt_close_nic(bp, false, false);
6768
6769         dev->mtu = new_mtu;
6770         bnxt_set_ring_params(bp);
6771
6772         if (netif_running(dev))
6773                 return bnxt_open_nic(bp, false, false);
6774
6775         return 0;
6776 }
6777
6778 int bnxt_setup_mq_tc(struct net_device *dev, u8 tc)
6779 {
6780         struct bnxt *bp = netdev_priv(dev);
6781         bool sh = false;
6782         int rc;
6783
6784         if (tc > bp->max_tc) {
6785                 netdev_err(dev, "too many traffic classes requested: %d Max supported is %d\n",
6786                            tc, bp->max_tc);
6787                 return -EINVAL;
6788         }
6789
6790         if (netdev_get_num_tc(dev) == tc)
6791                 return 0;
6792
6793         if (bp->flags & BNXT_FLAG_SHARED_RINGS)
6794                 sh = true;
6795
6796         rc = bnxt_reserve_rings(bp, bp->tx_nr_rings_per_tc, bp->rx_nr_rings,
6797                                 tc, bp->tx_nr_rings_xdp);
6798         if (rc)
6799                 return rc;
6800
6801         /* Needs to close the device and do hw resource re-allocations */
6802         if (netif_running(bp->dev))
6803                 bnxt_close_nic(bp, true, false);
6804
6805         if (tc) {
6806                 bp->tx_nr_rings = bp->tx_nr_rings_per_tc * tc;
6807                 netdev_set_num_tc(dev, tc);
6808         } else {
6809                 bp->tx_nr_rings = bp->tx_nr_rings_per_tc;
6810                 netdev_reset_tc(dev);
6811         }
6812         bp->cp_nr_rings = sh ? max_t(int, bp->tx_nr_rings, bp->rx_nr_rings) :
6813                                bp->tx_nr_rings + bp->rx_nr_rings;
6814         bp->num_stat_ctxs = bp->cp_nr_rings;
6815
6816         if (netif_running(bp->dev))
6817                 return bnxt_open_nic(bp, true, false);
6818
6819         return 0;
6820 }
6821
6822 static int bnxt_setup_tc(struct net_device *dev, u32 handle, __be16 proto,
6823                          struct tc_to_netdev *ntc)
6824 {
6825         if (ntc->type != TC_SETUP_MQPRIO)
6826                 return -EINVAL;
6827
6828         return bnxt_setup_mq_tc(dev, ntc->tc);
6829 }
6830
6831 #ifdef CONFIG_RFS_ACCEL
6832 static bool bnxt_fltr_match(struct bnxt_ntuple_filter *f1,
6833                             struct bnxt_ntuple_filter *f2)
6834 {
6835         struct flow_keys *keys1 = &f1->fkeys;
6836         struct flow_keys *keys2 = &f2->fkeys;
6837
6838         if (keys1->addrs.v4addrs.src == keys2->addrs.v4addrs.src &&
6839             keys1->addrs.v4addrs.dst == keys2->addrs.v4addrs.dst &&
6840             keys1->ports.ports == keys2->ports.ports &&
6841             keys1->basic.ip_proto == keys2->basic.ip_proto &&
6842             keys1->basic.n_proto == keys2->basic.n_proto &&
6843             ether_addr_equal(f1->src_mac_addr, f2->src_mac_addr) &&
6844             ether_addr_equal(f1->dst_mac_addr, f2->dst_mac_addr))
6845                 return true;
6846
6847         return false;
6848 }
6849
6850 static int bnxt_rx_flow_steer(struct net_device *dev, const struct sk_buff *skb,
6851                               u16 rxq_index, u32 flow_id)
6852 {
6853         struct bnxt *bp = netdev_priv(dev);
6854         struct bnxt_ntuple_filter *fltr, *new_fltr;
6855         struct flow_keys *fkeys;
6856         struct ethhdr *eth = (struct ethhdr *)skb_mac_header(skb);
6857         int rc = 0, idx, bit_id, l2_idx = 0;
6858         struct hlist_head *head;
6859
6860         if (skb->encapsulation)
6861                 return -EPROTONOSUPPORT;
6862
6863         if (!ether_addr_equal(dev->dev_addr, eth->h_dest)) {
6864                 struct bnxt_vnic_info *vnic = &bp->vnic_info[0];
6865                 int off = 0, j;
6866
6867                 netif_addr_lock_bh(dev);
6868                 for (j = 0; j < vnic->uc_filter_count; j++, off += ETH_ALEN) {
6869                         if (ether_addr_equal(eth->h_dest,
6870                                              vnic->uc_list + off)) {
6871                                 l2_idx = j + 1;
6872                                 break;
6873                         }
6874                 }
6875                 netif_addr_unlock_bh(dev);
6876                 if (!l2_idx)
6877                         return -EINVAL;
6878         }
6879         new_fltr = kzalloc(sizeof(*new_fltr), GFP_ATOMIC);
6880         if (!new_fltr)
6881                 return -ENOMEM;
6882
6883         fkeys = &new_fltr->fkeys;
6884         if (!skb_flow_dissect_flow_keys(skb, fkeys, 0)) {
6885                 rc = -EPROTONOSUPPORT;
6886                 goto err_free;
6887         }
6888
6889         if ((fkeys->basic.n_proto != htons(ETH_P_IP) &&
6890              fkeys->basic.n_proto != htons(ETH_P_IPV6)) ||
6891             ((fkeys->basic.ip_proto != IPPROTO_TCP) &&
6892              (fkeys->basic.ip_proto != IPPROTO_UDP))) {
6893                 rc = -EPROTONOSUPPORT;
6894                 goto err_free;
6895         }
6896         if (fkeys->basic.n_proto == htons(ETH_P_IPV6) &&
6897             bp->hwrm_spec_code < 0x10601) {
6898                 rc = -EPROTONOSUPPORT;
6899                 goto err_free;
6900         }
6901
6902         memcpy(new_fltr->dst_mac_addr, eth->h_dest, ETH_ALEN);
6903         memcpy(new_fltr->src_mac_addr, eth->h_source, ETH_ALEN);
6904
6905         idx = skb_get_hash_raw(skb) & BNXT_NTP_FLTR_HASH_MASK;
6906         head = &bp->ntp_fltr_hash_tbl[idx];
6907         rcu_read_lock();
6908         hlist_for_each_entry_rcu(fltr, head, hash) {
6909                 if (bnxt_fltr_match(fltr, new_fltr)) {
6910                         rcu_read_unlock();
6911                         rc = 0;
6912                         goto err_free;
6913                 }
6914         }
6915         rcu_read_unlock();
6916
6917         spin_lock_bh(&bp->ntp_fltr_lock);
6918         bit_id = bitmap_find_free_region(bp->ntp_fltr_bmap,
6919                                          BNXT_NTP_FLTR_MAX_FLTR, 0);
6920         if (bit_id < 0) {
6921                 spin_unlock_bh(&bp->ntp_fltr_lock);
6922                 rc = -ENOMEM;
6923                 goto err_free;
6924         }
6925
6926         new_fltr->sw_id = (u16)bit_id;
6927         new_fltr->flow_id = flow_id;
6928         new_fltr->l2_fltr_idx = l2_idx;
6929         new_fltr->rxq = rxq_index;
6930         hlist_add_head_rcu(&new_fltr->hash, head);
6931         bp->ntp_fltr_count++;
6932         spin_unlock_bh(&bp->ntp_fltr_lock);
6933
6934         set_bit(BNXT_RX_NTP_FLTR_SP_EVENT, &bp->sp_event);
6935         schedule_work(&bp->sp_task);
6936
6937         return new_fltr->sw_id;
6938
6939 err_free:
6940         kfree(new_fltr);
6941         return rc;
6942 }
6943
6944 static void bnxt_cfg_ntp_filters(struct bnxt *bp)
6945 {
6946         int i;
6947
6948         for (i = 0; i < BNXT_NTP_FLTR_HASH_SIZE; i++) {
6949                 struct hlist_head *head;
6950                 struct hlist_node *tmp;
6951                 struct bnxt_ntuple_filter *fltr;
6952                 int rc;
6953
6954                 head = &bp->ntp_fltr_hash_tbl[i];
6955                 hlist_for_each_entry_safe(fltr, tmp, head, hash) {
6956                         bool del = false;
6957
6958                         if (test_bit(BNXT_FLTR_VALID, &fltr->state)) {
6959                                 if (rps_may_expire_flow(bp->dev, fltr->rxq,
6960                                                         fltr->flow_id,
6961                                                         fltr->sw_id)) {
6962                                         bnxt_hwrm_cfa_ntuple_filter_free(bp,
6963                                                                          fltr);
6964                                         del = true;
6965                                 }
6966                         } else {
6967                                 rc = bnxt_hwrm_cfa_ntuple_filter_alloc(bp,
6968                                                                        fltr);
6969                                 if (rc)
6970                                         del = true;
6971                                 else
6972                                         set_bit(BNXT_FLTR_VALID, &fltr->state);
6973                         }
6974
6975                         if (del) {
6976                                 spin_lock_bh(&bp->ntp_fltr_lock);
6977                                 hlist_del_rcu(&fltr->hash);
6978                                 bp->ntp_fltr_count--;
6979                                 spin_unlock_bh(&bp->ntp_fltr_lock);
6980                                 synchronize_rcu();
6981                                 clear_bit(fltr->sw_id, bp->ntp_fltr_bmap);
6982                                 kfree(fltr);
6983                         }
6984                 }
6985         }
6986         if (test_and_clear_bit(BNXT_HWRM_PF_UNLOAD_SP_EVENT, &bp->sp_event))
6987                 netdev_info(bp->dev, "Receive PF driver unload event!");
6988 }
6989
6990 #else
6991
6992 static void bnxt_cfg_ntp_filters(struct bnxt *bp)
6993 {
6994 }
6995
6996 #endif /* CONFIG_RFS_ACCEL */
6997
6998 static void bnxt_udp_tunnel_add(struct net_device *dev,
6999                                 struct udp_tunnel_info *ti)
7000 {
7001         struct bnxt *bp = netdev_priv(dev);
7002
7003         if (ti->sa_family != AF_INET6 && ti->sa_family != AF_INET)
7004                 return;
7005
7006         if (!netif_running(dev))
7007                 return;
7008
7009         switch (ti->type) {
7010         case UDP_TUNNEL_TYPE_VXLAN:
7011                 if (bp->vxlan_port_cnt && bp->vxlan_port != ti->port)
7012                         return;
7013
7014                 bp->vxlan_port_cnt++;
7015                 if (bp->vxlan_port_cnt == 1) {
7016                         bp->vxlan_port = ti->port;
7017                         set_bit(BNXT_VXLAN_ADD_PORT_SP_EVENT, &bp->sp_event);
7018                         schedule_work(&bp->sp_task);
7019                 }
7020                 break;
7021         case UDP_TUNNEL_TYPE_GENEVE:
7022                 if (bp->nge_port_cnt && bp->nge_port != ti->port)
7023                         return;
7024
7025                 bp->nge_port_cnt++;
7026                 if (bp->nge_port_cnt == 1) {
7027                         bp->nge_port = ti->port;
7028                         set_bit(BNXT_GENEVE_ADD_PORT_SP_EVENT, &bp->sp_event);
7029                 }
7030                 break;
7031         default:
7032                 return;
7033         }
7034
7035         schedule_work(&bp->sp_task);
7036 }
7037
7038 static void bnxt_udp_tunnel_del(struct net_device *dev,
7039                                 struct udp_tunnel_info *ti)
7040 {
7041         struct bnxt *bp = netdev_priv(dev);
7042
7043         if (ti->sa_family != AF_INET6 && ti->sa_family != AF_INET)
7044                 return;
7045
7046         if (!netif_running(dev))
7047                 return;
7048
7049         switch (ti->type) {
7050         case UDP_TUNNEL_TYPE_VXLAN:
7051                 if (!bp->vxlan_port_cnt || bp->vxlan_port != ti->port)
7052                         return;
7053                 bp->vxlan_port_cnt--;
7054
7055                 if (bp->vxlan_port_cnt != 0)
7056                         return;
7057
7058                 set_bit(BNXT_VXLAN_DEL_PORT_SP_EVENT, &bp->sp_event);
7059                 break;
7060         case UDP_TUNNEL_TYPE_GENEVE:
7061                 if (!bp->nge_port_cnt || bp->nge_port != ti->port)
7062                         return;
7063                 bp->nge_port_cnt--;
7064
7065                 if (bp->nge_port_cnt != 0)
7066                         return;
7067
7068                 set_bit(BNXT_GENEVE_DEL_PORT_SP_EVENT, &bp->sp_event);
7069                 break;
7070         default:
7071                 return;
7072         }
7073
7074         schedule_work(&bp->sp_task);
7075 }
7076
7077 static const struct net_device_ops bnxt_netdev_ops = {
7078         .ndo_open               = bnxt_open,
7079         .ndo_start_xmit         = bnxt_start_xmit,
7080         .ndo_stop               = bnxt_close,
7081         .ndo_get_stats64        = bnxt_get_stats64,
7082         .ndo_set_rx_mode        = bnxt_set_rx_mode,
7083         .ndo_do_ioctl           = bnxt_ioctl,
7084         .ndo_validate_addr      = eth_validate_addr,
7085         .ndo_set_mac_address    = bnxt_change_mac_addr,
7086         .ndo_change_mtu         = bnxt_change_mtu,
7087         .ndo_fix_features       = bnxt_fix_features,
7088         .ndo_set_features       = bnxt_set_features,
7089         .ndo_tx_timeout         = bnxt_tx_timeout,
7090 #ifdef CONFIG_BNXT_SRIOV
7091         .ndo_get_vf_config      = bnxt_get_vf_config,
7092         .ndo_set_vf_mac         = bnxt_set_vf_mac,
7093         .ndo_set_vf_vlan        = bnxt_set_vf_vlan,
7094         .ndo_set_vf_rate        = bnxt_set_vf_bw,
7095         .ndo_set_vf_link_state  = bnxt_set_vf_link_state,
7096         .ndo_set_vf_spoofchk    = bnxt_set_vf_spoofchk,
7097 #endif
7098 #ifdef CONFIG_NET_POLL_CONTROLLER
7099         .ndo_poll_controller    = bnxt_poll_controller,
7100 #endif
7101         .ndo_setup_tc           = bnxt_setup_tc,
7102 #ifdef CONFIG_RFS_ACCEL
7103         .ndo_rx_flow_steer      = bnxt_rx_flow_steer,
7104 #endif
7105         .ndo_udp_tunnel_add     = bnxt_udp_tunnel_add,
7106         .ndo_udp_tunnel_del     = bnxt_udp_tunnel_del,
7107 };
7108
7109 static void bnxt_remove_one(struct pci_dev *pdev)
7110 {
7111         struct net_device *dev = pci_get_drvdata(pdev);
7112         struct bnxt *bp = netdev_priv(dev);
7113
7114         if (BNXT_PF(bp))
7115                 bnxt_sriov_disable(bp);
7116
7117         pci_disable_pcie_error_reporting(pdev);
7118         unregister_netdev(dev);
7119         cancel_work_sync(&bp->sp_task);
7120         bp->sp_event = 0;
7121
7122         bnxt_clear_int_mode(bp);
7123         bnxt_hwrm_func_drv_unrgtr(bp);
7124         bnxt_free_hwrm_resources(bp);
7125         bnxt_dcb_free(bp);
7126         pci_iounmap(pdev, bp->bar2);
7127         pci_iounmap(pdev, bp->bar1);
7128         pci_iounmap(pdev, bp->bar0);
7129         kfree(bp->edev);
7130         bp->edev = NULL;
7131         free_netdev(dev);
7132
7133         pci_release_regions(pdev);
7134         pci_disable_device(pdev);
7135 }
7136
7137 static int bnxt_probe_phy(struct bnxt *bp)
7138 {
7139         int rc = 0;
7140         struct bnxt_link_info *link_info = &bp->link_info;
7141
7142         rc = bnxt_hwrm_phy_qcaps(bp);
7143         if (rc) {
7144                 netdev_err(bp->dev, "Probe phy can't get phy capabilities (rc: %x)\n",
7145                            rc);
7146                 return rc;
7147         }
7148
7149         rc = bnxt_update_link(bp, false);
7150         if (rc) {
7151                 netdev_err(bp->dev, "Probe phy can't update link (rc: %x)\n",
7152                            rc);
7153                 return rc;
7154         }
7155
7156         /* Older firmware does not have supported_auto_speeds, so assume
7157          * that all supported speeds can be autonegotiated.
7158          */
7159         if (link_info->auto_link_speeds && !link_info->support_auto_speeds)
7160                 link_info->support_auto_speeds = link_info->support_speeds;
7161
7162         /*initialize the ethool setting copy with NVM settings */
7163         if (BNXT_AUTO_MODE(link_info->auto_mode)) {
7164                 link_info->autoneg = BNXT_AUTONEG_SPEED;
7165                 if (bp->hwrm_spec_code >= 0x10201) {
7166                         if (link_info->auto_pause_setting &
7167                             PORT_PHY_CFG_REQ_AUTO_PAUSE_AUTONEG_PAUSE)
7168                                 link_info->autoneg |= BNXT_AUTONEG_FLOW_CTRL;
7169                 } else {
7170                         link_info->autoneg |= BNXT_AUTONEG_FLOW_CTRL;
7171                 }
7172                 link_info->advertising = link_info->auto_link_speeds;
7173         } else {
7174                 link_info->req_link_speed = link_info->force_link_speed;
7175                 link_info->req_duplex = link_info->duplex_setting;
7176         }
7177         if (link_info->autoneg & BNXT_AUTONEG_FLOW_CTRL)
7178                 link_info->req_flow_ctrl =
7179                         link_info->auto_pause_setting & BNXT_LINK_PAUSE_BOTH;
7180         else
7181                 link_info->req_flow_ctrl = link_info->force_pause_setting;
7182         return rc;
7183 }
7184
7185 static int bnxt_get_max_irq(struct pci_dev *pdev)
7186 {
7187         u16 ctrl;
7188
7189         if (!pdev->msix_cap)
7190                 return 1;
7191
7192         pci_read_config_word(pdev, pdev->msix_cap + PCI_MSIX_FLAGS, &ctrl);
7193         return (ctrl & PCI_MSIX_FLAGS_QSIZE) + 1;
7194 }
7195
7196 static void _bnxt_get_max_rings(struct bnxt *bp, int *max_rx, int *max_tx,
7197                                 int *max_cp)
7198 {
7199         int max_ring_grps = 0;
7200
7201 #ifdef CONFIG_BNXT_SRIOV
7202         if (!BNXT_PF(bp)) {
7203                 *max_tx = bp->vf.max_tx_rings;
7204                 *max_rx = bp->vf.max_rx_rings;
7205                 *max_cp = min_t(int, bp->vf.max_irqs, bp->vf.max_cp_rings);
7206                 *max_cp = min_t(int, *max_cp, bp->vf.max_stat_ctxs);
7207                 max_ring_grps = bp->vf.max_hw_ring_grps;
7208         } else
7209 #endif
7210         {
7211                 *max_tx = bp->pf.max_tx_rings;
7212                 *max_rx = bp->pf.max_rx_rings;
7213                 *max_cp = min_t(int, bp->pf.max_irqs, bp->pf.max_cp_rings);
7214                 *max_cp = min_t(int, *max_cp, bp->pf.max_stat_ctxs);
7215                 max_ring_grps = bp->pf.max_hw_ring_grps;
7216         }
7217         if (BNXT_CHIP_TYPE_NITRO_A0(bp) && BNXT_PF(bp)) {
7218                 *max_cp -= 1;
7219                 *max_rx -= 2;
7220         }
7221         if (bp->flags & BNXT_FLAG_AGG_RINGS)
7222                 *max_rx >>= 1;
7223         *max_rx = min_t(int, *max_rx, max_ring_grps);
7224 }
7225
7226 int bnxt_get_max_rings(struct bnxt *bp, int *max_rx, int *max_tx, bool shared)
7227 {
7228         int rx, tx, cp;
7229
7230         _bnxt_get_max_rings(bp, &rx, &tx, &cp);
7231         if (!rx || !tx || !cp)
7232                 return -ENOMEM;
7233
7234         *max_rx = rx;
7235         *max_tx = tx;
7236         return bnxt_trim_rings(bp, max_rx, max_tx, cp, shared);
7237 }
7238
7239 static int bnxt_get_dflt_rings(struct bnxt *bp, int *max_rx, int *max_tx,
7240                                bool shared)
7241 {
7242         int rc;
7243
7244         rc = bnxt_get_max_rings(bp, max_rx, max_tx, shared);
7245         if (rc && (bp->flags & BNXT_FLAG_AGG_RINGS)) {
7246                 /* Not enough rings, try disabling agg rings. */
7247                 bp->flags &= ~BNXT_FLAG_AGG_RINGS;
7248                 rc = bnxt_get_max_rings(bp, max_rx, max_tx, shared);
7249                 if (rc)
7250                         return rc;
7251                 bp->flags |= BNXT_FLAG_NO_AGG_RINGS;
7252                 bp->dev->hw_features &= ~NETIF_F_LRO;
7253                 bp->dev->features &= ~NETIF_F_LRO;
7254                 bnxt_set_ring_params(bp);
7255         }
7256
7257         if (bp->flags & BNXT_FLAG_ROCE_CAP) {
7258                 int max_cp, max_stat, max_irq;
7259
7260                 /* Reserve minimum resources for RoCE */
7261                 max_cp = bnxt_get_max_func_cp_rings(bp);
7262                 max_stat = bnxt_get_max_func_stat_ctxs(bp);
7263                 max_irq = bnxt_get_max_func_irqs(bp);
7264                 if (max_cp <= BNXT_MIN_ROCE_CP_RINGS ||
7265                     max_irq <= BNXT_MIN_ROCE_CP_RINGS ||
7266                     max_stat <= BNXT_MIN_ROCE_STAT_CTXS)
7267                         return 0;
7268
7269                 max_cp -= BNXT_MIN_ROCE_CP_RINGS;
7270                 max_irq -= BNXT_MIN_ROCE_CP_RINGS;
7271                 max_stat -= BNXT_MIN_ROCE_STAT_CTXS;
7272                 max_cp = min_t(int, max_cp, max_irq);
7273                 max_cp = min_t(int, max_cp, max_stat);
7274                 rc = bnxt_trim_rings(bp, max_rx, max_tx, max_cp, shared);
7275                 if (rc)
7276                         rc = 0;
7277         }
7278         return rc;
7279 }
7280
7281 static int bnxt_set_dflt_rings(struct bnxt *bp)
7282 {
7283         int dflt_rings, max_rx_rings, max_tx_rings, rc;
7284         bool sh = true;
7285
7286         if (sh)
7287                 bp->flags |= BNXT_FLAG_SHARED_RINGS;
7288         dflt_rings = netif_get_num_default_rss_queues();
7289         rc = bnxt_get_dflt_rings(bp, &max_rx_rings, &max_tx_rings, sh);
7290         if (rc)
7291                 return rc;
7292         bp->rx_nr_rings = min_t(int, dflt_rings, max_rx_rings);
7293         bp->tx_nr_rings_per_tc = min_t(int, dflt_rings, max_tx_rings);
7294
7295         rc = bnxt_hwrm_reserve_tx_rings(bp, &bp->tx_nr_rings_per_tc);
7296         if (rc)
7297                 netdev_warn(bp->dev, "Unable to reserve tx rings\n");
7298
7299         bp->tx_nr_rings = bp->tx_nr_rings_per_tc;
7300         bp->cp_nr_rings = sh ? max_t(int, bp->tx_nr_rings, bp->rx_nr_rings) :
7301                                bp->tx_nr_rings + bp->rx_nr_rings;
7302         bp->num_stat_ctxs = bp->cp_nr_rings;
7303         if (BNXT_CHIP_TYPE_NITRO_A0(bp)) {
7304                 bp->rx_nr_rings++;
7305                 bp->cp_nr_rings++;
7306         }
7307         return rc;
7308 }
7309
7310 void bnxt_restore_pf_fw_resources(struct bnxt *bp)
7311 {
7312         ASSERT_RTNL();
7313         bnxt_hwrm_func_qcaps(bp);
7314         bnxt_subtract_ulp_resources(bp, BNXT_ROCE_ULP);
7315 }
7316
7317 static void bnxt_parse_log_pcie_link(struct bnxt *bp)
7318 {
7319         enum pcie_link_width width = PCIE_LNK_WIDTH_UNKNOWN;
7320         enum pci_bus_speed speed = PCI_SPEED_UNKNOWN;
7321
7322         if (pcie_get_minimum_link(bp->pdev, &speed, &width) ||
7323             speed == PCI_SPEED_UNKNOWN || width == PCIE_LNK_WIDTH_UNKNOWN)
7324                 netdev_info(bp->dev, "Failed to determine PCIe Link Info\n");
7325         else
7326                 netdev_info(bp->dev, "PCIe: Speed %s Width x%d\n",
7327                             speed == PCIE_SPEED_2_5GT ? "2.5GT/s" :
7328                             speed == PCIE_SPEED_5_0GT ? "5.0GT/s" :
7329                             speed == PCIE_SPEED_8_0GT ? "8.0GT/s" :
7330                             "Unknown", width);
7331 }
7332
7333 static int bnxt_init_one(struct pci_dev *pdev, const struct pci_device_id *ent)
7334 {
7335         static int version_printed;
7336         struct net_device *dev;
7337         struct bnxt *bp;
7338         int rc, max_irqs;
7339
7340         if (pdev->device == 0x16cd && pci_is_bridge(pdev))
7341                 return -ENODEV;
7342
7343         if (version_printed++ == 0)
7344                 pr_info("%s", version);
7345
7346         max_irqs = bnxt_get_max_irq(pdev);
7347         dev = alloc_etherdev_mq(sizeof(*bp), max_irqs);
7348         if (!dev)
7349                 return -ENOMEM;
7350
7351         bp = netdev_priv(dev);
7352
7353         if (bnxt_vf_pciid(ent->driver_data))
7354                 bp->flags |= BNXT_FLAG_VF;
7355
7356         if (pdev->msix_cap)
7357                 bp->flags |= BNXT_FLAG_MSIX_CAP;
7358
7359         rc = bnxt_init_board(pdev, dev);
7360         if (rc < 0)
7361                 goto init_err_free;
7362
7363         dev->netdev_ops = &bnxt_netdev_ops;
7364         dev->watchdog_timeo = BNXT_TX_TIMEOUT;
7365         dev->ethtool_ops = &bnxt_ethtool_ops;
7366
7367         pci_set_drvdata(pdev, dev);
7368
7369         rc = bnxt_alloc_hwrm_resources(bp);
7370         if (rc)
7371                 goto init_err;
7372
7373         mutex_init(&bp->hwrm_cmd_lock);
7374         rc = bnxt_hwrm_ver_get(bp);
7375         if (rc)
7376                 goto init_err;
7377
7378         bnxt_hwrm_fw_set_time(bp);
7379
7380         dev->hw_features = NETIF_F_IP_CSUM | NETIF_F_IPV6_CSUM | NETIF_F_SG |
7381                            NETIF_F_TSO | NETIF_F_TSO6 |
7382                            NETIF_F_GSO_UDP_TUNNEL | NETIF_F_GSO_GRE |
7383                            NETIF_F_GSO_IPXIP4 |
7384                            NETIF_F_GSO_UDP_TUNNEL_CSUM | NETIF_F_GSO_GRE_CSUM |
7385                            NETIF_F_GSO_PARTIAL | NETIF_F_RXHASH |
7386                            NETIF_F_RXCSUM | NETIF_F_GRO;
7387
7388         if (!BNXT_CHIP_TYPE_NITRO_A0(bp))
7389                 dev->hw_features |= NETIF_F_LRO;
7390
7391         dev->hw_enc_features =
7392                         NETIF_F_IP_CSUM | NETIF_F_IPV6_CSUM | NETIF_F_SG |
7393                         NETIF_F_TSO | NETIF_F_TSO6 |
7394                         NETIF_F_GSO_UDP_TUNNEL | NETIF_F_GSO_GRE |
7395                         NETIF_F_GSO_UDP_TUNNEL_CSUM | NETIF_F_GSO_GRE_CSUM |
7396                         NETIF_F_GSO_IPXIP4 | NETIF_F_GSO_PARTIAL;
7397         dev->gso_partial_features = NETIF_F_GSO_UDP_TUNNEL_CSUM |
7398                                     NETIF_F_GSO_GRE_CSUM;
7399         dev->vlan_features = dev->hw_features | NETIF_F_HIGHDMA;
7400         dev->hw_features |= NETIF_F_HW_VLAN_CTAG_RX | NETIF_F_HW_VLAN_CTAG_TX |
7401                             NETIF_F_HW_VLAN_STAG_RX | NETIF_F_HW_VLAN_STAG_TX;
7402         dev->features |= dev->hw_features | NETIF_F_HIGHDMA;
7403         dev->priv_flags |= IFF_UNICAST_FLT;
7404
7405         /* MTU range: 60 - 9500 */
7406         dev->min_mtu = ETH_ZLEN;
7407         dev->max_mtu = BNXT_MAX_MTU;
7408
7409         bnxt_dcb_init(bp);
7410
7411 #ifdef CONFIG_BNXT_SRIOV
7412         init_waitqueue_head(&bp->sriov_cfg_wait);
7413 #endif
7414         bp->gro_func = bnxt_gro_func_5730x;
7415         if (BNXT_CHIP_NUM_57X1X(bp->chip_num))
7416                 bp->gro_func = bnxt_gro_func_5731x;
7417
7418         rc = bnxt_hwrm_func_drv_rgtr(bp);
7419         if (rc)
7420                 goto init_err;
7421
7422         rc = bnxt_hwrm_func_rgtr_async_events(bp, NULL, 0);
7423         if (rc)
7424                 goto init_err;
7425
7426         bp->ulp_probe = bnxt_ulp_probe;
7427
7428         /* Get the MAX capabilities for this function */
7429         rc = bnxt_hwrm_func_qcaps(bp);
7430         if (rc) {
7431                 netdev_err(bp->dev, "hwrm query capability failure rc: %x\n",
7432                            rc);
7433                 rc = -1;
7434                 goto init_err;
7435         }
7436
7437         rc = bnxt_hwrm_queue_qportcfg(bp);
7438         if (rc) {
7439                 netdev_err(bp->dev, "hwrm query qportcfg failure rc: %x\n",
7440                            rc);
7441                 rc = -1;
7442                 goto init_err;
7443         }
7444
7445         bnxt_hwrm_func_qcfg(bp);
7446         bnxt_hwrm_port_led_qcaps(bp);
7447
7448         bnxt_set_rx_skb_mode(bp, false);
7449         bnxt_set_tpa_flags(bp);
7450         bnxt_set_ring_params(bp);
7451         bnxt_set_max_func_irqs(bp, max_irqs);
7452         rc = bnxt_set_dflt_rings(bp);
7453         if (rc) {
7454                 netdev_err(bp->dev, "Not enough rings available.\n");
7455                 rc = -ENOMEM;
7456                 goto init_err;
7457         }
7458
7459         /* Default RSS hash cfg. */
7460         bp->rss_hash_cfg = VNIC_RSS_CFG_REQ_HASH_TYPE_IPV4 |
7461                            VNIC_RSS_CFG_REQ_HASH_TYPE_TCP_IPV4 |
7462                            VNIC_RSS_CFG_REQ_HASH_TYPE_IPV6 |
7463                            VNIC_RSS_CFG_REQ_HASH_TYPE_TCP_IPV6;
7464         if (!BNXT_CHIP_NUM_57X0X(bp->chip_num) &&
7465             !BNXT_CHIP_TYPE_NITRO_A0(bp) &&
7466             bp->hwrm_spec_code >= 0x10501) {
7467                 bp->flags |= BNXT_FLAG_UDP_RSS_CAP;
7468                 bp->rss_hash_cfg |= VNIC_RSS_CFG_REQ_HASH_TYPE_UDP_IPV4 |
7469                                     VNIC_RSS_CFG_REQ_HASH_TYPE_UDP_IPV6;
7470         }
7471
7472         bnxt_hwrm_vnic_qcaps(bp);
7473         if (bnxt_rfs_supported(bp)) {
7474                 dev->hw_features |= NETIF_F_NTUPLE;
7475                 if (bnxt_rfs_capable(bp)) {
7476                         bp->flags |= BNXT_FLAG_RFS;
7477                         dev->features |= NETIF_F_NTUPLE;
7478                 }
7479         }
7480
7481         if (dev->hw_features & NETIF_F_HW_VLAN_CTAG_RX)
7482                 bp->flags |= BNXT_FLAG_STRIP_VLAN;
7483
7484         rc = bnxt_probe_phy(bp);
7485         if (rc)
7486                 goto init_err;
7487
7488         rc = bnxt_hwrm_func_reset(bp);
7489         if (rc)
7490                 goto init_err;
7491
7492         rc = bnxt_init_int_mode(bp);
7493         if (rc)
7494                 goto init_err;
7495
7496         rc = register_netdev(dev);
7497         if (rc)
7498                 goto init_err_clr_int;
7499
7500         netdev_info(dev, "%s found at mem %lx, node addr %pM\n",
7501                     board_info[ent->driver_data].name,
7502                     (long)pci_resource_start(pdev, 0), dev->dev_addr);
7503
7504         bnxt_parse_log_pcie_link(bp);
7505
7506         return 0;
7507
7508 init_err_clr_int:
7509         bnxt_clear_int_mode(bp);
7510
7511 init_err:
7512         pci_iounmap(pdev, bp->bar0);
7513         pci_release_regions(pdev);
7514         pci_disable_device(pdev);
7515
7516 init_err_free:
7517         free_netdev(dev);
7518         return rc;
7519 }
7520
7521 /**
7522  * bnxt_io_error_detected - called when PCI error is detected
7523  * @pdev: Pointer to PCI device
7524  * @state: The current pci connection state
7525  *
7526  * This function is called after a PCI bus error affecting
7527  * this device has been detected.
7528  */
7529 static pci_ers_result_t bnxt_io_error_detected(struct pci_dev *pdev,
7530                                                pci_channel_state_t state)
7531 {
7532         struct net_device *netdev = pci_get_drvdata(pdev);
7533         struct bnxt *bp = netdev_priv(netdev);
7534
7535         netdev_info(netdev, "PCI I/O error detected\n");
7536
7537         rtnl_lock();
7538         netif_device_detach(netdev);
7539
7540         bnxt_ulp_stop(bp);
7541
7542         if (state == pci_channel_io_perm_failure) {
7543                 rtnl_unlock();
7544                 return PCI_ERS_RESULT_DISCONNECT;
7545         }
7546
7547         if (netif_running(netdev))
7548                 bnxt_close(netdev);
7549
7550         pci_disable_device(pdev);
7551         rtnl_unlock();
7552
7553         /* Request a slot slot reset. */
7554         return PCI_ERS_RESULT_NEED_RESET;
7555 }
7556
7557 /**
7558  * bnxt_io_slot_reset - called after the pci bus has been reset.
7559  * @pdev: Pointer to PCI device
7560  *
7561  * Restart the card from scratch, as if from a cold-boot.
7562  * At this point, the card has exprienced a hard reset,
7563  * followed by fixups by BIOS, and has its config space
7564  * set up identically to what it was at cold boot.
7565  */
7566 static pci_ers_result_t bnxt_io_slot_reset(struct pci_dev *pdev)
7567 {
7568         struct net_device *netdev = pci_get_drvdata(pdev);
7569         struct bnxt *bp = netdev_priv(netdev);
7570         int err = 0;
7571         pci_ers_result_t result = PCI_ERS_RESULT_DISCONNECT;
7572
7573         netdev_info(bp->dev, "PCI Slot Reset\n");
7574
7575         rtnl_lock();
7576
7577         if (pci_enable_device(pdev)) {
7578                 dev_err(&pdev->dev,
7579                         "Cannot re-enable PCI device after reset.\n");
7580         } else {
7581                 pci_set_master(pdev);
7582
7583                 err = bnxt_hwrm_func_reset(bp);
7584                 if (!err && netif_running(netdev))
7585                         err = bnxt_open(netdev);
7586
7587                 if (!err) {
7588                         result = PCI_ERS_RESULT_RECOVERED;
7589                         bnxt_ulp_start(bp);
7590                 }
7591         }
7592
7593         if (result != PCI_ERS_RESULT_RECOVERED && netif_running(netdev))
7594                 dev_close(netdev);
7595
7596         rtnl_unlock();
7597
7598         err = pci_cleanup_aer_uncorrect_error_status(pdev);
7599         if (err) {
7600                 dev_err(&pdev->dev,
7601                         "pci_cleanup_aer_uncorrect_error_status failed 0x%0x\n",
7602                          err); /* non-fatal, continue */
7603         }
7604
7605         return PCI_ERS_RESULT_RECOVERED;
7606 }
7607
7608 /**
7609  * bnxt_io_resume - called when traffic can start flowing again.
7610  * @pdev: Pointer to PCI device
7611  *
7612  * This callback is called when the error recovery driver tells
7613  * us that its OK to resume normal operation.
7614  */
7615 static void bnxt_io_resume(struct pci_dev *pdev)
7616 {
7617         struct net_device *netdev = pci_get_drvdata(pdev);
7618
7619         rtnl_lock();
7620
7621         netif_device_attach(netdev);
7622
7623         rtnl_unlock();
7624 }
7625
7626 static const struct pci_error_handlers bnxt_err_handler = {
7627         .error_detected = bnxt_io_error_detected,
7628         .slot_reset     = bnxt_io_slot_reset,
7629         .resume         = bnxt_io_resume
7630 };
7631
7632 static struct pci_driver bnxt_pci_driver = {
7633         .name           = DRV_MODULE_NAME,
7634         .id_table       = bnxt_pci_tbl,
7635         .probe          = bnxt_init_one,
7636         .remove         = bnxt_remove_one,
7637         .err_handler    = &bnxt_err_handler,
7638 #if defined(CONFIG_BNXT_SRIOV)
7639         .sriov_configure = bnxt_sriov_configure,
7640 #endif
7641 };
7642
7643 module_pci_driver(bnxt_pci_driver);