drivers/net/ethernet/broadcom/bnxt/bnxt.c

   1 /* Broadcom NetXtreme-C/E network driver.
   2  *
   3  * Copyright (c) 2014-2016 Broadcom Corporation
   4  *
   5  * This program is free software; you can redistribute it and/or modify
   6  * it under the terms of the GNU General Public License as published by
   7  * the Free Software Foundation.
   8  */
   9
  10 #include <linux/module.h>
  11
  12 #include <linux/stringify.h>
  13 #include <linux/kernel.h>
  14 #include <linux/timer.h>
  15 #include <linux/errno.h>
  16 #include <linux/ioport.h>
  17 #include <linux/slab.h>
  18 #include <linux/vmalloc.h>
  19 #include <linux/interrupt.h>
  20 #include <linux/pci.h>
  21 #include <linux/netdevice.h>
  22 #include <linux/etherdevice.h>
  23 #include <linux/skbuff.h>
  24 #include <linux/dma-mapping.h>
  25 #include <linux/bitops.h>
  26 #include <linux/io.h>
  27 #include <linux/irq.h>
  28 #include <linux/delay.h>
  29 #include <asm/byteorder.h>
  30 #include <asm/page.h>
  31 #include <linux/time.h>
  32 #include <linux/mii.h>
  33 #include <linux/if.h>
  34 #include <linux/if_vlan.h>
  35 #include <net/ip.h>
  36 #include <net/tcp.h>
  37 #include <net/udp.h>
  38 #include <net/checksum.h>
  39 #include <net/ip6_checksum.h>
  40 #include <net/udp_tunnel.h>
  41 #ifdef CONFIG_NET_RX_BUSY_POLL
  42 #include <net/busy_poll.h>
  43 #endif
  44 #include <linux/workqueue.h>
  45 #include <linux/prefetch.h>
  46 #include <linux/cache.h>
  47 #include <linux/log2.h>
  48 #include <linux/aer.h>
  49 #include <linux/bitmap.h>
  50 #include <linux/cpu_rmap.h>
  51
  52 #include "bnxt_hsi.h"
  53 #include "bnxt.h"
  54 #include "bnxt_sriov.h"
  55 #include "bnxt_ethtool.h"
  56
  57 #define BNXT_TX_TIMEOUT         (5 * HZ)
  58
  59 static const char version[] =
  60         "Broadcom NetXtreme-C/E driver " DRV_MODULE_NAME " v" DRV_MODULE_VERSION "\n";
  61
  62 MODULE_LICENSE("GPL");
  63 MODULE_DESCRIPTION("Broadcom BCM573xx network driver");
  64 MODULE_VERSION(DRV_MODULE_VERSION);
  65
  66 #define BNXT_RX_OFFSET (NET_SKB_PAD + NET_IP_ALIGN)
  67 #define BNXT_RX_DMA_OFFSET NET_SKB_PAD
  68 #define BNXT_RX_COPY_THRESH 256
  69
  70 #define BNXT_TX_PUSH_THRESH 164
  71
  72 enum board_idx {
  73         BCM57301,
  74         BCM57302,
  75         BCM57304,
  76         BCM57311,
  77         BCM57312,
  78         BCM57402,
  79         BCM57404,
  80         BCM57406,
  81         BCM57404_NPAR,
  82         BCM57412,
  83         BCM57414,
  84         BCM57416,
  85         BCM57417,
  86         BCM57414_NPAR,
  87         BCM57314,
  88         BCM57304_VF,
  89         BCM57404_VF,
  90         BCM57414_VF,
  91         BCM57314_VF,
  92 };
  93
  94 /* indexed by enum above */
  95 static const struct {
  96         char *name;
  97 } board_info[] = {
  98         { "Broadcom BCM57301 NetXtreme-C Single-port 10Gb Ethernet" },
  99         { "Broadcom BCM57302 NetXtreme-C Dual-port 10Gb/25Gb Ethernet" },
 100         { "Broadcom BCM57304 NetXtreme-C Dual-port 10Gb/25Gb/40Gb/50Gb Ethernet" },
 101         { "Broadcom BCM57311 NetXtreme-C Single-port 10Gb Ethernet" },
 102         { "Broadcom BCM57312 NetXtreme-C Dual-port 10Gb/25Gb Ethernet" },
 103         { "Broadcom BCM57402 NetXtreme-E Dual-port 10Gb Ethernet" },
 104         { "Broadcom BCM57404 NetXtreme-E Dual-port 10Gb/25Gb Ethernet" },
 105         { "Broadcom BCM57406 NetXtreme-E Dual-port 10GBase-T Ethernet" },
 106         { "Broadcom BCM57404 NetXtreme-E Ethernet Partition" },
 107         { "Broadcom BCM57412 NetXtreme-E Dual-port 10Gb Ethernet" },
 108         { "Broadcom BCM57414 NetXtreme-E Dual-port 10Gb/25Gb Ethernet" },
 109         { "Broadcom BCM57416 NetXtreme-E Dual-port 10GBase-T Ethernet" },
 110         { "Broadcom BCM57417 NetXtreme-E Dual-port 10GBase-T Ethernet" },
 111         { "Broadcom BCM57414 NetXtreme-E Ethernet Partition" },
 112         { "Broadcom BCM57314 NetXtreme-C Dual-port 10Gb/25Gb/40Gb/50Gb Ethernet" },
 113         { "Broadcom BCM57304 NetXtreme-C Ethernet Virtual Function" },
 114         { "Broadcom BCM57404 NetXtreme-E Ethernet Virtual Function" },
 115         { "Broadcom BCM57414 NetXtreme-E Ethernet Virtual Function" },
 116         { "Broadcom BCM57314 NetXtreme-E Ethernet Virtual Function" },
 117 };
 118
 119 static const struct pci_device_id bnxt_pci_tbl[] = {
 120         { PCI_VDEVICE(BROADCOM, 0x16c8), .driver_data = BCM57301 },
 121         { PCI_VDEVICE(BROADCOM, 0x16c9), .driver_data = BCM57302 },
 122         { PCI_VDEVICE(BROADCOM, 0x16ca), .driver_data = BCM57304 },
 123         { PCI_VDEVICE(BROADCOM, 0x16ce), .driver_data = BCM57311 },
 124         { PCI_VDEVICE(BROADCOM, 0x16cf), .driver_data = BCM57312 },
 125         { PCI_VDEVICE(BROADCOM, 0x16d0), .driver_data = BCM57402 },
 126         { PCI_VDEVICE(BROADCOM, 0x16d1), .driver_data = BCM57404 },
 127         { PCI_VDEVICE(BROADCOM, 0x16d2), .driver_data = BCM57406 },
 128         { PCI_VDEVICE(BROADCOM, 0x16d4), .driver_data = BCM57404_NPAR },
 129         { PCI_VDEVICE(BROADCOM, 0x16d6), .driver_data = BCM57412 },
 130         { PCI_VDEVICE(BROADCOM, 0x16d7), .driver_data = BCM57414 },
 131         { PCI_VDEVICE(BROADCOM, 0x16d8), .driver_data = BCM57416 },
 132         { PCI_VDEVICE(BROADCOM, 0x16d9), .driver_data = BCM57417 },
 133         { PCI_VDEVICE(BROADCOM, 0x16de), .driver_data = BCM57414_NPAR },
 134         { PCI_VDEVICE(BROADCOM, 0x16df), .driver_data = BCM57314 },
 135 #ifdef CONFIG_BNXT_SRIOV
 136         { PCI_VDEVICE(BROADCOM, 0x16cb), .driver_data = BCM57304_VF },
 137         { PCI_VDEVICE(BROADCOM, 0x16d3), .driver_data = BCM57404_VF },
 138         { PCI_VDEVICE(BROADCOM, 0x16dc), .driver_data = BCM57414_VF },
 139         { PCI_VDEVICE(BROADCOM, 0x16e1), .driver_data = BCM57314_VF },
 140 #endif
 141         { 0 }
 142 };
 143
 144 MODULE_DEVICE_TABLE(pci, bnxt_pci_tbl);
 145
 146 static const u16 bnxt_vf_req_snif[] = {
 147         HWRM_FUNC_CFG,
 148         HWRM_PORT_PHY_QCFG,
 149         HWRM_CFA_L2_FILTER_ALLOC,
 150 };
 151
 152 static const u16 bnxt_async_events_arr[] = {
 153         HWRM_ASYNC_EVENT_CMPL_EVENT_ID_LINK_STATUS_CHANGE,
 154         HWRM_ASYNC_EVENT_CMPL_EVENT_ID_PF_DRVR_UNLOAD,
 155         HWRM_ASYNC_EVENT_CMPL_EVENT_ID_PORT_CONN_NOT_ALLOWED,
 156         HWRM_ASYNC_EVENT_CMPL_EVENT_ID_VF_CFG_CHANGE,
 157         HWRM_ASYNC_EVENT_CMPL_EVENT_ID_LINK_SPEED_CFG_CHANGE,
 158 };
 159
 160 static bool bnxt_vf_pciid(enum board_idx idx)
 161 {
 162         return (idx == BCM57304_VF || idx == BCM57404_VF ||
 163                 idx == BCM57314_VF || idx == BCM57414_VF);
 164 }
 165
 166 #define DB_CP_REARM_FLAGS       (DB_KEY_CP | DB_IDX_VALID)
 167 #define DB_CP_FLAGS             (DB_KEY_CP | DB_IDX_VALID | DB_IRQ_DIS)
 168 #define DB_CP_IRQ_DIS_FLAGS     (DB_KEY_CP | DB_IRQ_DIS)
 169
 170 #define BNXT_CP_DB_REARM(db, raw_cons)                                  \
 171                 writel(DB_CP_REARM_FLAGS | RING_CMP(raw_cons), db)
 172
 173 #define BNXT_CP_DB(db, raw_cons)                                        \
 174                 writel(DB_CP_FLAGS | RING_CMP(raw_cons), db)
 175
 176 #define BNXT_CP_DB_IRQ_DIS(db)                                          \
 177                 writel(DB_CP_IRQ_DIS_FLAGS, db)
 178
 179 static inline u32 bnxt_tx_avail(struct bnxt *bp, struct bnxt_tx_ring_info *txr)
 180 {
 181         /* Tell compiler to fetch tx indices from memory. */
 182         barrier();
 183
 184         return bp->tx_ring_size -
 185                 ((txr->tx_prod - txr->tx_cons) & bp->tx_ring_mask);
 186 }
 187
 188 static const u16 bnxt_lhint_arr[] = {
 189         TX_BD_FLAGS_LHINT_512_AND_SMALLER,
 190         TX_BD_FLAGS_LHINT_512_TO_1023,
 191         TX_BD_FLAGS_LHINT_1024_TO_2047,
 192         TX_BD_FLAGS_LHINT_1024_TO_2047,
 193         TX_BD_FLAGS_LHINT_2048_AND_LARGER,
 194         TX_BD_FLAGS_LHINT_2048_AND_LARGER,
 195         TX_BD_FLAGS_LHINT_2048_AND_LARGER,
 196         TX_BD_FLAGS_LHINT_2048_AND_LARGER,
 197         TX_BD_FLAGS_LHINT_2048_AND_LARGER,
 198         TX_BD_FLAGS_LHINT_2048_AND_LARGER,
 199         TX_BD_FLAGS_LHINT_2048_AND_LARGER,
 200         TX_BD_FLAGS_LHINT_2048_AND_LARGER,
 201         TX_BD_FLAGS_LHINT_2048_AND_LARGER,
 202         TX_BD_FLAGS_LHINT_2048_AND_LARGER,
 203         TX_BD_FLAGS_LHINT_2048_AND_LARGER,
 204         TX_BD_FLAGS_LHINT_2048_AND_LARGER,
 205         TX_BD_FLAGS_LHINT_2048_AND_LARGER,
 206         TX_BD_FLAGS_LHINT_2048_AND_LARGER,
 207         TX_BD_FLAGS_LHINT_2048_AND_LARGER,
 208 };
 209
 210 static netdev_tx_t bnxt_start_xmit(struct sk_buff *skb, struct net_device *dev)
 211 {
 212         struct bnxt *bp = netdev_priv(dev);
 213         struct tx_bd *txbd;
 214         struct tx_bd_ext *txbd1;
 215         struct netdev_queue *txq;
 216         int i;
 217         dma_addr_t mapping;
 218         unsigned int length, pad = 0;
 219         u32 len, free_size, vlan_tag_flags, cfa_action, flags;
 220         u16 prod, last_frag;
 221         struct pci_dev *pdev = bp->pdev;
 222         struct bnxt_tx_ring_info *txr;
 223         struct bnxt_sw_tx_bd *tx_buf;
 224
 225         i = skb_get_queue_mapping(skb);
 226         if (unlikely(i >= bp->tx_nr_rings)) {
 227                 dev_kfree_skb_any(skb);
 228                 return NETDEV_TX_OK;
 229         }
 230
 231         txr = &bp->tx_ring[i];
 232         txq = netdev_get_tx_queue(dev, i);
 233         prod = txr->tx_prod;
 234
 235         free_size = bnxt_tx_avail(bp, txr);
 236         if (unlikely(free_size < skb_shinfo(skb)->nr_frags + 2)) {
 237                 netif_tx_stop_queue(txq);
 238                 return NETDEV_TX_BUSY;
 239         }
 240
 241         length = skb->len;
 242         len = skb_headlen(skb);
 243         last_frag = skb_shinfo(skb)->nr_frags;
 244
 245         txbd = &txr->tx_desc_ring[TX_RING(prod)][TX_IDX(prod)];
 246
 247         txbd->tx_bd_opaque = prod;
 248
 249         tx_buf = &txr->tx_buf_ring[prod];
 250         tx_buf->skb = skb;
 251         tx_buf->nr_frags = last_frag;
 252
 253         vlan_tag_flags = 0;
 254         cfa_action = 0;
 255         if (skb_vlan_tag_present(skb)) {
 256                 vlan_tag_flags = TX_BD_CFA_META_KEY_VLAN |
 257                                  skb_vlan_tag_get(skb);
 258                 /* Currently supports 8021Q, 8021AD vlan offloads
 259                  * QINQ1, QINQ2, QINQ3 vlan headers are deprecated
 260                  */
 261                 if (skb->vlan_proto == htons(ETH_P_8021Q))
 262                         vlan_tag_flags |= 1 << TX_BD_CFA_META_TPID_SHIFT;
 263         }
 264
 265         if (free_size == bp->tx_ring_size && length <= bp->tx_push_thresh) {
 266                 struct tx_push_buffer *tx_push_buf = txr->tx_push;
 267                 struct tx_push_bd *tx_push = &tx_push_buf->push_bd;
 268                 struct tx_bd_ext *tx_push1 = &tx_push->txbd2;
 269                 void *pdata = tx_push_buf->data;
 270                 u64 *end;
 271                 int j, push_len;
 272
 273                 /* Set COAL_NOW to be ready quickly for the next push */
 274                 tx_push->tx_bd_len_flags_type =
 275                         cpu_to_le32((length << TX_BD_LEN_SHIFT) |
 276                                         TX_BD_TYPE_LONG_TX_BD |
 277                                         TX_BD_FLAGS_LHINT_512_AND_SMALLER |
 278                                         TX_BD_FLAGS_COAL_NOW |
 279                                         TX_BD_FLAGS_PACKET_END |
 280                                         (2 << TX_BD_FLAGS_BD_CNT_SHIFT));
 281
 282                 if (skb->ip_summed == CHECKSUM_PARTIAL)
 283                         tx_push1->tx_bd_hsize_lflags =
 284                                         cpu_to_le32(TX_BD_FLAGS_TCP_UDP_CHKSUM);
 285                 else
 286                         tx_push1->tx_bd_hsize_lflags = 0;
 287
 288                 tx_push1->tx_bd_cfa_meta = cpu_to_le32(vlan_tag_flags);
 289                 tx_push1->tx_bd_cfa_action = cpu_to_le32(cfa_action);
 290
 291                 end = pdata + length;
 292                 end = PTR_ALIGN(end, 8) - 1;
 293                 *end = 0;
 294
 295                 skb_copy_from_linear_data(skb, pdata, len);
 296                 pdata += len;
 297                 for (j = 0; j < last_frag; j++) {
 298                         skb_frag_t *frag = &skb_shinfo(skb)->frags[j];
 299                         void *fptr;
 300
 301                         fptr = skb_frag_address_safe(frag);
 302                         if (!fptr)
 303                                 goto normal_tx;
 304
 305                         memcpy(pdata, fptr, skb_frag_size(frag));
 306                         pdata += skb_frag_size(frag);
 307                 }
 308
 309                 txbd->tx_bd_len_flags_type = tx_push->tx_bd_len_flags_type;
 310                 txbd->tx_bd_haddr = txr->data_mapping;
 311                 prod = NEXT_TX(prod);
 312                 txbd = &txr->tx_desc_ring[TX_RING(prod)][TX_IDX(prod)];
 313                 memcpy(txbd, tx_push1, sizeof(*txbd));
 314                 prod = NEXT_TX(prod);
 315                 tx_push->doorbell =
 316                         cpu_to_le32(DB_KEY_TX_PUSH | DB_LONG_TX_PUSH | prod);
 317                 txr->tx_prod = prod;
 318
 319                 tx_buf->is_push = 1;
 320                 netdev_tx_sent_queue(txq, skb->len);
 321                 wmb();  /* Sync is_push and byte queue before pushing data */
 322
 323                 push_len = (length + sizeof(*tx_push) + 7) / 8;
 324                 if (push_len > 16) {
 325                         __iowrite64_copy(txr->tx_doorbell, tx_push_buf, 16);
 326                         __iowrite64_copy(txr->tx_doorbell + 4, tx_push_buf + 1,
 327                                          push_len - 16);
 328                 } else {
 329                         __iowrite64_copy(txr->tx_doorbell, tx_push_buf,
 330                                          push_len);
 331                 }
 332
 333                 goto tx_done;
 334         }
 335
 336 normal_tx:
 337         if (length < BNXT_MIN_PKT_SIZE) {
 338                 pad = BNXT_MIN_PKT_SIZE - length;
 339                 if (skb_pad(skb, pad)) {
 340                         /* SKB already freed. */
 341                         tx_buf->skb = NULL;
 342                         return NETDEV_TX_OK;
 343                 }
 344                 length = BNXT_MIN_PKT_SIZE;
 345         }
 346
 347         mapping = dma_map_single(&pdev->dev, skb->data, len, DMA_TO_DEVICE);
 348
 349         if (unlikely(dma_mapping_error(&pdev->dev, mapping))) {
 350                 dev_kfree_skb_any(skb);
 351                 tx_buf->skb = NULL;
 352                 return NETDEV_TX_OK;
 353         }
 354
 355         dma_unmap_addr_set(tx_buf, mapping, mapping);
 356         flags = (len << TX_BD_LEN_SHIFT) | TX_BD_TYPE_LONG_TX_BD |
 357                 ((last_frag + 2) << TX_BD_FLAGS_BD_CNT_SHIFT);
 358
 359         txbd->tx_bd_haddr = cpu_to_le64(mapping);
 360
 361         prod = NEXT_TX(prod);
 362         txbd1 = (struct tx_bd_ext *)
 363                 &txr->tx_desc_ring[TX_RING(prod)][TX_IDX(prod)];
 364
 365         txbd1->tx_bd_hsize_lflags = 0;
 366         if (skb_is_gso(skb)) {
 367                 u32 hdr_len;
 368
 369                 if (skb->encapsulation)
 370                         hdr_len = skb_inner_network_offset(skb) +
 371                                 skb_inner_network_header_len(skb) +
 372                                 inner_tcp_hdrlen(skb);
 373                 else
 374                         hdr_len = skb_transport_offset(skb) +
 375                                 tcp_hdrlen(skb);
 376
 377                 txbd1->tx_bd_hsize_lflags = cpu_to_le32(TX_BD_FLAGS_LSO |
 378                                         TX_BD_FLAGS_T_IPID |
 379                                         (hdr_len << (TX_BD_HSIZE_SHIFT - 1)));
 380                 length = skb_shinfo(skb)->gso_size;
 381                 txbd1->tx_bd_mss = cpu_to_le32(length);
 382                 length += hdr_len;
 383         } else if (skb->ip_summed == CHECKSUM_PARTIAL) {
 384                 txbd1->tx_bd_hsize_lflags =
 385                         cpu_to_le32(TX_BD_FLAGS_TCP_UDP_CHKSUM);
 386                 txbd1->tx_bd_mss = 0;
 387         }
 388
 389         length >>= 9;
 390         flags |= bnxt_lhint_arr[length];
 391         txbd->tx_bd_len_flags_type = cpu_to_le32(flags);
 392
 393         txbd1->tx_bd_cfa_meta = cpu_to_le32(vlan_tag_flags);
 394         txbd1->tx_bd_cfa_action = cpu_to_le32(cfa_action);
 395         for (i = 0; i < last_frag; i++) {
 396                 skb_frag_t *frag = &skb_shinfo(skb)->frags[i];
 397
 398                 prod = NEXT_TX(prod);
 399                 txbd = &txr->tx_desc_ring[TX_RING(prod)][TX_IDX(prod)];
 400
 401                 len = skb_frag_size(frag);
 402                 mapping = skb_frag_dma_map(&pdev->dev, frag, 0, len,
 403                                            DMA_TO_DEVICE);
 404
 405                 if (unlikely(dma_mapping_error(&pdev->dev, mapping)))
 406                         goto tx_dma_error;
 407
 408                 tx_buf = &txr->tx_buf_ring[prod];
 409                 dma_unmap_addr_set(tx_buf, mapping, mapping);
 410
 411                 txbd->tx_bd_haddr = cpu_to_le64(mapping);
 412
 413                 flags = len << TX_BD_LEN_SHIFT;
 414                 txbd->tx_bd_len_flags_type = cpu_to_le32(flags);
 415         }
 416
 417         flags &= ~TX_BD_LEN;
 418         txbd->tx_bd_len_flags_type =
 419                 cpu_to_le32(((len + pad) << TX_BD_LEN_SHIFT) | flags |
 420                             TX_BD_FLAGS_PACKET_END);
 421
 422         netdev_tx_sent_queue(txq, skb->len);
 423
 424         /* Sync BD data before updating doorbell */
 425         wmb();
 426
 427         prod = NEXT_TX(prod);
 428         txr->tx_prod = prod;
 429
 430         writel(DB_KEY_TX | prod, txr->tx_doorbell);
 431         writel(DB_KEY_TX | prod, txr->tx_doorbell);
 432
 433 tx_done:
 434
 435         mmiowb();
 436
 437         if (unlikely(bnxt_tx_avail(bp, txr) <= MAX_SKB_FRAGS + 1)) {
 438                 netif_tx_stop_queue(txq);
 439
 440                 /* netif_tx_stop_queue() must be done before checking
 441                  * tx index in bnxt_tx_avail() below, because in
 442                  * bnxt_tx_int(), we update tx index before checking for
 443                  * netif_tx_queue_stopped().
 444                  */
 445                 smp_mb();
 446                 if (bnxt_tx_avail(bp, txr) > bp->tx_wake_thresh)
 447                         netif_tx_wake_queue(txq);
 448         }
 449         return NETDEV_TX_OK;
 450
 451 tx_dma_error:
 452         last_frag = i;
 453
 454         /* start back at beginning and unmap skb */
 455         prod = txr->tx_prod;
 456         tx_buf = &txr->tx_buf_ring[prod];
 457         tx_buf->skb = NULL;
 458         dma_unmap_single(&pdev->dev, dma_unmap_addr(tx_buf, mapping),
 459                          skb_headlen(skb), PCI_DMA_TODEVICE);
 460         prod = NEXT_TX(prod);
 461
 462         /* unmap remaining mapped pages */
 463         for (i = 0; i < last_frag; i++) {
 464                 prod = NEXT_TX(prod);
 465                 tx_buf = &txr->tx_buf_ring[prod];
 466                 dma_unmap_page(&pdev->dev, dma_unmap_addr(tx_buf, mapping),
 467                                skb_frag_size(&skb_shinfo(skb)->frags[i]),
 468                                PCI_DMA_TODEVICE);
 469         }
 470
 471         dev_kfree_skb_any(skb);
 472         return NETDEV_TX_OK;
 473 }
 474
 475 static void bnxt_tx_int(struct bnxt *bp, struct bnxt_napi *bnapi, int nr_pkts)
 476 {
 477         struct bnxt_tx_ring_info *txr = bnapi->tx_ring;
 478         int index = txr - &bp->tx_ring[0];
 479         struct netdev_queue *txq = netdev_get_tx_queue(bp->dev, index);
 480         u16 cons = txr->tx_cons;
 481         struct pci_dev *pdev = bp->pdev;
 482         int i;
 483         unsigned int tx_bytes = 0;
 484
 485         for (i = 0; i < nr_pkts; i++) {
 486                 struct bnxt_sw_tx_bd *tx_buf;
 487                 struct sk_buff *skb;
 488                 int j, last;
 489
 490                 tx_buf = &txr->tx_buf_ring[cons];
 491                 cons = NEXT_TX(cons);
 492                 skb = tx_buf->skb;
 493                 tx_buf->skb = NULL;
 494
 495                 if (tx_buf->is_push) {
 496                         tx_buf->is_push = 0;
 497                         goto next_tx_int;
 498                 }
 499
 500                 dma_unmap_single(&pdev->dev, dma_unmap_addr(tx_buf, mapping),
 501                                  skb_headlen(skb), PCI_DMA_TODEVICE);
 502                 last = tx_buf->nr_frags;
 503
 504                 for (j = 0; j < last; j++) {
 505                         cons = NEXT_TX(cons);
 506                         tx_buf = &txr->tx_buf_ring[cons];
 507                         dma_unmap_page(
 508                                 &pdev->dev,
 509                                 dma_unmap_addr(tx_buf, mapping),
 510                                 skb_frag_size(&skb_shinfo(skb)->frags[j]),
 511                                 PCI_DMA_TODEVICE);
 512                 }
 513
 514 next_tx_int:
 515                 cons = NEXT_TX(cons);
 516
 517                 tx_bytes += skb->len;
 518                 dev_kfree_skb_any(skb);
 519         }
 520
 521         netdev_tx_completed_queue(txq, nr_pkts, tx_bytes);
 522         txr->tx_cons = cons;
 523
 524         /* Need to make the tx_cons update visible to bnxt_start_xmit()
 525          * before checking for netif_tx_queue_stopped().  Without the
 526          * memory barrier, there is a small possibility that bnxt_start_xmit()
 527          * will miss it and cause the queue to be stopped forever.
 528          */
 529         smp_mb();
 530
 531         if (unlikely(netif_tx_queue_stopped(txq)) &&
 532             (bnxt_tx_avail(bp, txr) > bp->tx_wake_thresh)) {
 533                 __netif_tx_lock(txq, smp_processor_id());
 534                 if (netif_tx_queue_stopped(txq) &&
 535                     bnxt_tx_avail(bp, txr) > bp->tx_wake_thresh &&
 536                     txr->dev_state != BNXT_DEV_STATE_CLOSING)
 537                         netif_tx_wake_queue(txq);
 538                 __netif_tx_unlock(txq);
 539         }
 540 }
 541
 542 static inline u8 *__bnxt_alloc_rx_data(struct bnxt *bp, dma_addr_t *mapping,
 543                                        gfp_t gfp)
 544 {
 545         u8 *data;
 546         struct pci_dev *pdev = bp->pdev;
 547
 548         data = kmalloc(bp->rx_buf_size, gfp);
 549         if (!data)
 550                 return NULL;
 551
 552         *mapping = dma_map_single(&pdev->dev, data + BNXT_RX_DMA_OFFSET,
 553                                   bp->rx_buf_use_size, PCI_DMA_FROMDEVICE);
 554
 555         if (dma_mapping_error(&pdev->dev, *mapping)) {
 556                 kfree(data);
 557                 data = NULL;
 558         }
 559         return data;
 560 }
 561
 562 static inline int bnxt_alloc_rx_data(struct bnxt *bp,
 563                                      struct bnxt_rx_ring_info *rxr,
 564                                      u16 prod, gfp_t gfp)
 565 {
 566         struct rx_bd *rxbd = &rxr->rx_desc_ring[RX_RING(prod)][RX_IDX(prod)];
 567         struct bnxt_sw_rx_bd *rx_buf = &rxr->rx_buf_ring[prod];
 568         u8 *data;
 569         dma_addr_t mapping;
 570
 571         data = __bnxt_alloc_rx_data(bp, &mapping, gfp);
 572         if (!data)
 573                 return -ENOMEM;
 574
 575         rx_buf->data = data;
 576         dma_unmap_addr_set(rx_buf, mapping, mapping);
 577
 578         rxbd->rx_bd_haddr = cpu_to_le64(mapping);
 579
 580         return 0;
 581 }
 582
 583 static void bnxt_reuse_rx_data(struct bnxt_rx_ring_info *rxr, u16 cons,
 584                                u8 *data)
 585 {
 586         u16 prod = rxr->rx_prod;
 587         struct bnxt_sw_rx_bd *cons_rx_buf, *prod_rx_buf;
 588         struct rx_bd *cons_bd, *prod_bd;
 589
 590         prod_rx_buf = &rxr->rx_buf_ring[prod];
 591         cons_rx_buf = &rxr->rx_buf_ring[cons];
 592
 593         prod_rx_buf->data = data;
 594
 595         dma_unmap_addr_set(prod_rx_buf, mapping,
 596                            dma_unmap_addr(cons_rx_buf, mapping));
 597
 598         prod_bd = &rxr->rx_desc_ring[RX_RING(prod)][RX_IDX(prod)];
 599         cons_bd = &rxr->rx_desc_ring[RX_RING(cons)][RX_IDX(cons)];
 600
 601         prod_bd->rx_bd_haddr = cons_bd->rx_bd_haddr;
 602 }
 603
 604 static inline u16 bnxt_find_next_agg_idx(struct bnxt_rx_ring_info *rxr, u16 idx)
 605 {
 606         u16 next, max = rxr->rx_agg_bmap_size;
 607
 608         next = find_next_zero_bit(rxr->rx_agg_bmap, max, idx);
 609         if (next >= max)
 610                 next = find_first_zero_bit(rxr->rx_agg_bmap, max);
 611         return next;
 612 }
 613
 614 static inline int bnxt_alloc_rx_page(struct bnxt *bp,
 615                                      struct bnxt_rx_ring_info *rxr,
 616                                      u16 prod, gfp_t gfp)
 617 {
 618         struct rx_bd *rxbd =
 619                 &rxr->rx_agg_desc_ring[RX_RING(prod)][RX_IDX(prod)];
 620         struct bnxt_sw_rx_agg_bd *rx_agg_buf;
 621         struct pci_dev *pdev = bp->pdev;
 622         struct page *page;
 623         dma_addr_t mapping;
 624         u16 sw_prod = rxr->rx_sw_agg_prod;
 625         unsigned int offset = 0;
 626
 627         if (PAGE_SIZE > BNXT_RX_PAGE_SIZE) {
 628                 page = rxr->rx_page;
 629                 if (!page) {
 630                         page = alloc_page(gfp);
 631                         if (!page)
 632                                 return -ENOMEM;
 633                         rxr->rx_page = page;
 634                         rxr->rx_page_offset = 0;
 635                 }
 636                 offset = rxr->rx_page_offset;
 637                 rxr->rx_page_offset += BNXT_RX_PAGE_SIZE;
 638                 if (rxr->rx_page_offset == PAGE_SIZE)
 639                         rxr->rx_page = NULL;
 640                 else
 641                         get_page(page);
 642         } else {
 643                 page = alloc_page(gfp);
 644                 if (!page)
 645                         return -ENOMEM;
 646         }
 647
 648         mapping = dma_map_page(&pdev->dev, page, offset, BNXT_RX_PAGE_SIZE,
 649                                PCI_DMA_FROMDEVICE);
 650         if (dma_mapping_error(&pdev->dev, mapping)) {
 651                 __free_page(page);
 652                 return -EIO;
 653         }
 654
 655         if (unlikely(test_bit(sw_prod, rxr->rx_agg_bmap)))
 656                 sw_prod = bnxt_find_next_agg_idx(rxr, sw_prod);
 657
 658         __set_bit(sw_prod, rxr->rx_agg_bmap);
 659         rx_agg_buf = &rxr->rx_agg_ring[sw_prod];
 660         rxr->rx_sw_agg_prod = NEXT_RX_AGG(sw_prod);
 661
 662         rx_agg_buf->page = page;
 663         rx_agg_buf->offset = offset;
 664         rx_agg_buf->mapping = mapping;
 665         rxbd->rx_bd_haddr = cpu_to_le64(mapping);
 666         rxbd->rx_bd_opaque = sw_prod;
 667         return 0;
 668 }
 669
 670 static void bnxt_reuse_rx_agg_bufs(struct bnxt_napi *bnapi, u16 cp_cons,
 671                                    u32 agg_bufs)
 672 {
 673         struct bnxt *bp = bnapi->bp;
 674         struct bnxt_cp_ring_info *cpr = &bnapi->cp_ring;
 675         struct bnxt_rx_ring_info *rxr = bnapi->rx_ring;
 676         u16 prod = rxr->rx_agg_prod;
 677         u16 sw_prod = rxr->rx_sw_agg_prod;
 678         u32 i;
 679
 680         for (i = 0; i < agg_bufs; i++) {
 681                 u16 cons;
 682                 struct rx_agg_cmp *agg;
 683                 struct bnxt_sw_rx_agg_bd *cons_rx_buf, *prod_rx_buf;
 684                 struct rx_bd *prod_bd;
 685                 struct page *page;
 686
 687                 agg = (struct rx_agg_cmp *)
 688                         &cpr->cp_desc_ring[CP_RING(cp_cons)][CP_IDX(cp_cons)];
 689                 cons = agg->rx_agg_cmp_opaque;
 690                 __clear_bit(cons, rxr->rx_agg_bmap);
 691
 692                 if (unlikely(test_bit(sw_prod, rxr->rx_agg_bmap)))
 693                         sw_prod = bnxt_find_next_agg_idx(rxr, sw_prod);
 694
 695                 __set_bit(sw_prod, rxr->rx_agg_bmap);
 696                 prod_rx_buf = &rxr->rx_agg_ring[sw_prod];
 697                 cons_rx_buf = &rxr->rx_agg_ring[cons];
 698
 699                 /* It is possible for sw_prod to be equal to cons, so
 700                  * set cons_rx_buf->page to NULL first.
 701                  */
 702                 page = cons_rx_buf->page;
 703                 cons_rx_buf->page = NULL;
 704                 prod_rx_buf->page = page;
 705                 prod_rx_buf->offset = cons_rx_buf->offset;
 706
 707                 prod_rx_buf->mapping = cons_rx_buf->mapping;
 708
 709                 prod_bd = &rxr->rx_agg_desc_ring[RX_RING(prod)][RX_IDX(prod)];
 710
 711                 prod_bd->rx_bd_haddr = cpu_to_le64(cons_rx_buf->mapping);
 712                 prod_bd->rx_bd_opaque = sw_prod;
 713
 714                 prod = NEXT_RX_AGG(prod);
 715                 sw_prod = NEXT_RX_AGG(sw_prod);
 716                 cp_cons = NEXT_CMP(cp_cons);
 717         }
 718         rxr->rx_agg_prod = prod;
 719         rxr->rx_sw_agg_prod = sw_prod;
 720 }
 721
 722 static struct sk_buff *bnxt_rx_skb(struct bnxt *bp,
 723                                    struct bnxt_rx_ring_info *rxr, u16 cons,
 724                                    u16 prod, u8 *data, dma_addr_t dma_addr,
 725                                    unsigned int len)
 726 {
 727         int err;
 728         struct sk_buff *skb;
 729
 730         err = bnxt_alloc_rx_data(bp, rxr, prod, GFP_ATOMIC);
 731         if (unlikely(err)) {
 732                 bnxt_reuse_rx_data(rxr, cons, data);
 733                 return NULL;
 734         }
 735
 736         skb = build_skb(data, 0);
 737         dma_unmap_single(&bp->pdev->dev, dma_addr, bp->rx_buf_use_size,
 738                          PCI_DMA_FROMDEVICE);
 739         if (!skb) {
 740                 kfree(data);
 741                 return NULL;
 742         }
 743
 744         skb_reserve(skb, BNXT_RX_OFFSET);
 745         skb_put(skb, len);
 746         return skb;
 747 }
 748
 749 static struct sk_buff *bnxt_rx_pages(struct bnxt *bp, struct bnxt_napi *bnapi,
 750                                      struct sk_buff *skb, u16 cp_cons,
 751                                      u32 agg_bufs)
 752 {
 753         struct pci_dev *pdev = bp->pdev;
 754         struct bnxt_cp_ring_info *cpr = &bnapi->cp_ring;
 755         struct bnxt_rx_ring_info *rxr = bnapi->rx_ring;
 756         u16 prod = rxr->rx_agg_prod;
 757         u32 i;
 758
 759         for (i = 0; i < agg_bufs; i++) {
 760                 u16 cons, frag_len;
 761                 struct rx_agg_cmp *agg;
 762                 struct bnxt_sw_rx_agg_bd *cons_rx_buf;
 763                 struct page *page;
 764                 dma_addr_t mapping;
 765
 766                 agg = (struct rx_agg_cmp *)
 767                         &cpr->cp_desc_ring[CP_RING(cp_cons)][CP_IDX(cp_cons)];
 768                 cons = agg->rx_agg_cmp_opaque;
 769                 frag_len = (le32_to_cpu(agg->rx_agg_cmp_len_flags_type) &
 770                             RX_AGG_CMP_LEN) >> RX_AGG_CMP_LEN_SHIFT;
 771
 772                 cons_rx_buf = &rxr->rx_agg_ring[cons];
 773                 skb_fill_page_desc(skb, i, cons_rx_buf->page,
 774                                    cons_rx_buf->offset, frag_len);
 775                 __clear_bit(cons, rxr->rx_agg_bmap);
 776
 777                 /* It is possible for bnxt_alloc_rx_page() to allocate
 778                  * a sw_prod index that equals the cons index, so we
 779                  * need to clear the cons entry now.
 780                  */
 781                 mapping = dma_unmap_addr(cons_rx_buf, mapping);
 782                 page = cons_rx_buf->page;
 783                 cons_rx_buf->page = NULL;
 784
 785                 if (bnxt_alloc_rx_page(bp, rxr, prod, GFP_ATOMIC) != 0) {
 786                         struct skb_shared_info *shinfo;
 787                         unsigned int nr_frags;
 788
 789                         shinfo = skb_shinfo(skb);
 790                         nr_frags = --shinfo->nr_frags;
 791                         __skb_frag_set_page(&shinfo->frags[nr_frags], NULL);
 792
 793                         dev_kfree_skb(skb);
 794
 795                         cons_rx_buf->page = page;
 796
 797                         /* Update prod since possibly some pages have been
 798                          * allocated already.
 799                          */
 800                         rxr->rx_agg_prod = prod;
 801                         bnxt_reuse_rx_agg_bufs(bnapi, cp_cons, agg_bufs - i);
 802                         return NULL;
 803                 }
 804
 805                 dma_unmap_page(&pdev->dev, mapping, BNXT_RX_PAGE_SIZE,
 806                                PCI_DMA_FROMDEVICE);
 807
 808                 skb->data_len += frag_len;
 809                 skb->len += frag_len;
 810                 skb->truesize += PAGE_SIZE;
 811
 812                 prod = NEXT_RX_AGG(prod);
 813                 cp_cons = NEXT_CMP(cp_cons);
 814         }
 815         rxr->rx_agg_prod = prod;
 816         return skb;
 817 }
 818
 819 static int bnxt_agg_bufs_valid(struct bnxt *bp, struct bnxt_cp_ring_info *cpr,
 820                                u8 agg_bufs, u32 *raw_cons)
 821 {
 822         u16 last;
 823         struct rx_agg_cmp *agg;
 824
 825         *raw_cons = ADV_RAW_CMP(*raw_cons, agg_bufs);
 826         last = RING_CMP(*raw_cons);
 827         agg = (struct rx_agg_cmp *)
 828                 &cpr->cp_desc_ring[CP_RING(last)][CP_IDX(last)];
 829         return RX_AGG_CMP_VALID(agg, *raw_cons);
 830 }
 831
 832 static inline struct sk_buff *bnxt_copy_skb(struct bnxt_napi *bnapi, u8 *data,
 833                                             unsigned int len,
 834                                             dma_addr_t mapping)
 835 {
 836         struct bnxt *bp = bnapi->bp;
 837         struct pci_dev *pdev = bp->pdev;
 838         struct sk_buff *skb;
 839
 840         skb = napi_alloc_skb(&bnapi->napi, len);
 841         if (!skb)
 842                 return NULL;
 843
 844         dma_sync_single_for_cpu(&pdev->dev, mapping,
 845                                 bp->rx_copy_thresh, PCI_DMA_FROMDEVICE);
 846
 847         memcpy(skb->data - BNXT_RX_OFFSET, data, len + BNXT_RX_OFFSET);
 848
 849         dma_sync_single_for_device(&pdev->dev, mapping,
 850                                    bp->rx_copy_thresh,
 851                                    PCI_DMA_FROMDEVICE);
 852
 853         skb_put(skb, len);
 854         return skb;
 855 }
 856
 857 static int bnxt_discard_rx(struct bnxt *bp, struct bnxt_napi *bnapi,
 858                            u32 *raw_cons, void *cmp)
 859 {
 860         struct bnxt_cp_ring_info *cpr = &bnapi->cp_ring;
 861         struct rx_cmp *rxcmp = cmp;
 862         u32 tmp_raw_cons = *raw_cons;
 863         u8 cmp_type, agg_bufs = 0;
 864
 865         cmp_type = RX_CMP_TYPE(rxcmp);
 866
 867         if (cmp_type == CMP_TYPE_RX_L2_CMP) {
 868                 agg_bufs = (le32_to_cpu(rxcmp->rx_cmp_misc_v1) &
 869                             RX_CMP_AGG_BUFS) >>
 870                            RX_CMP_AGG_BUFS_SHIFT;
 871         } else if (cmp_type == CMP_TYPE_RX_L2_TPA_END_CMP) {
 872                 struct rx_tpa_end_cmp *tpa_end = cmp;
 873
 874                 agg_bufs = (le32_to_cpu(tpa_end->rx_tpa_end_cmp_misc_v1) &
 875                             RX_TPA_END_CMP_AGG_BUFS) >>
 876                            RX_TPA_END_CMP_AGG_BUFS_SHIFT;
 877         }
 878
 879         if (agg_bufs) {
 880                 if (!bnxt_agg_bufs_valid(bp, cpr, agg_bufs, &tmp_raw_cons))
 881                         return -EBUSY;
 882         }
 883         *raw_cons = tmp_raw_cons;
 884         return 0;
 885 }
 886
 887 static void bnxt_sched_reset(struct bnxt *bp, struct bnxt_rx_ring_info *rxr)
 888 {
 889         if (!rxr->bnapi->in_reset) {
 890                 rxr->bnapi->in_reset = true;
 891                 set_bit(BNXT_RESET_TASK_SP_EVENT, &bp->sp_event);
 892                 schedule_work(&bp->sp_task);
 893         }
 894         rxr->rx_next_cons = 0xffff;
 895 }
 896
 897 static void bnxt_tpa_start(struct bnxt *bp, struct bnxt_rx_ring_info *rxr,
 898                            struct rx_tpa_start_cmp *tpa_start,
 899                            struct rx_tpa_start_cmp_ext *tpa_start1)
 900 {
 901         u8 agg_id = TPA_START_AGG_ID(tpa_start);
 902         u16 cons, prod;
 903         struct bnxt_tpa_info *tpa_info;
 904         struct bnxt_sw_rx_bd *cons_rx_buf, *prod_rx_buf;
 905         struct rx_bd *prod_bd;
 906         dma_addr_t mapping;
 907
 908         cons = tpa_start->rx_tpa_start_cmp_opaque;
 909         prod = rxr->rx_prod;
 910         cons_rx_buf = &rxr->rx_buf_ring[cons];
 911         prod_rx_buf = &rxr->rx_buf_ring[prod];
 912         tpa_info = &rxr->rx_tpa[agg_id];
 913
 914         if (unlikely(cons != rxr->rx_next_cons)) {
 915                 bnxt_sched_reset(bp, rxr);
 916                 return;
 917         }
 918
 919         prod_rx_buf->data = tpa_info->data;
 920
 921         mapping = tpa_info->mapping;
 922         dma_unmap_addr_set(prod_rx_buf, mapping, mapping);
 923
 924         prod_bd = &rxr->rx_desc_ring[RX_RING(prod)][RX_IDX(prod)];
 925
 926         prod_bd->rx_bd_haddr = cpu_to_le64(mapping);
 927
 928         tpa_info->data = cons_rx_buf->data;
 929         cons_rx_buf->data = NULL;
 930         tpa_info->mapping = dma_unmap_addr(cons_rx_buf, mapping);
 931
 932         tpa_info->len =
 933                 le32_to_cpu(tpa_start->rx_tpa_start_cmp_len_flags_type) >>
 934                                 RX_TPA_START_CMP_LEN_SHIFT;
 935         if (likely(TPA_START_HASH_VALID(tpa_start))) {
 936                 u32 hash_type = TPA_START_HASH_TYPE(tpa_start);
 937
 938                 tpa_info->hash_type = PKT_HASH_TYPE_L4;
 939                 tpa_info->gso_type = SKB_GSO_TCPV4;
 940                 /* RSS profiles 1 and 3 with extract code 0 for inner 4-tuple */
 941                 if (hash_type == 3)
 942                         tpa_info->gso_type = SKB_GSO_TCPV6;
 943                 tpa_info->rss_hash =
 944                         le32_to_cpu(tpa_start->rx_tpa_start_cmp_rss_hash);
 945         } else {
 946                 tpa_info->hash_type = PKT_HASH_TYPE_NONE;
 947                 tpa_info->gso_type = 0;
 948                 if (netif_msg_rx_err(bp))
 949                         netdev_warn(bp->dev, "TPA packet without valid hash\n");
 950         }
 951         tpa_info->flags2 = le32_to_cpu(tpa_start1->rx_tpa_start_cmp_flags2);
 952         tpa_info->metadata = le32_to_cpu(tpa_start1->rx_tpa_start_cmp_metadata);
 953         tpa_info->hdr_info = le32_to_cpu(tpa_start1->rx_tpa_start_cmp_hdr_info);
 954
 955         rxr->rx_prod = NEXT_RX(prod);
 956         cons = NEXT_RX(cons);
 957         rxr->rx_next_cons = NEXT_RX(cons);
 958         cons_rx_buf = &rxr->rx_buf_ring[cons];
 959
 960         bnxt_reuse_rx_data(rxr, cons, cons_rx_buf->data);
 961         rxr->rx_prod = NEXT_RX(rxr->rx_prod);
 962         cons_rx_buf->data = NULL;
 963 }
 964
 965 static void bnxt_abort_tpa(struct bnxt *bp, struct bnxt_napi *bnapi,
 966                            u16 cp_cons, u32 agg_bufs)
 967 {
 968         if (agg_bufs)
 969                 bnxt_reuse_rx_agg_bufs(bnapi, cp_cons, agg_bufs);
 970 }
 971
 972 static struct sk_buff *bnxt_gro_func_5731x(struct bnxt_tpa_info *tpa_info,
 973                                            int payload_off, int tcp_ts,
 974                                            struct sk_buff *skb)
 975 {
 976 #ifdef CONFIG_INET
 977         struct tcphdr *th;
 978         int len, nw_off;
 979         u16 outer_ip_off, inner_ip_off, inner_mac_off;
 980         u32 hdr_info = tpa_info->hdr_info;
 981         bool loopback = false;
 982
 983         inner_ip_off = BNXT_TPA_INNER_L3_OFF(hdr_info);
 984         inner_mac_off = BNXT_TPA_INNER_L2_OFF(hdr_info);
 985         outer_ip_off = BNXT_TPA_OUTER_L3_OFF(hdr_info);
 986
 987         /* If the packet is an internal loopback packet, the offsets will
 988          * have an extra 4 bytes.
 989          */
 990         if (inner_mac_off == 4) {
 991                 loopback = true;
 992         } else if (inner_mac_off > 4) {
 993                 __be16 proto = *((__be16 *)(skb->data + inner_ip_off -
 994                                             ETH_HLEN - 2));
 995
 996                 /* We only support inner iPv4/ipv6.  If we don't see the
 997                  * correct protocol ID, it must be a loopback packet where
 998                  * the offsets are off by 4.
 999                  */
1000                 if (proto != htons(ETH_P_IP) && proto && htons(ETH_P_IPV6))
1001                         loopback = true;
1002         }
1003         if (loopback) {
1004                 /* internal loopback packet, subtract all offsets by 4 */
1005                 inner_ip_off -= 4;
1006                 inner_mac_off -= 4;
1007                 outer_ip_off -= 4;
1008         }
1009
1010         nw_off = inner_ip_off - ETH_HLEN;
1011         skb_set_network_header(skb, nw_off);
1012         if (tpa_info->flags2 & RX_TPA_START_CMP_FLAGS2_IP_TYPE) {
1013                 struct ipv6hdr *iph = ipv6_hdr(skb);
1014
1015                 skb_set_transport_header(skb, nw_off + sizeof(struct ipv6hdr));
1016                 len = skb->len - skb_transport_offset(skb);
1017                 th = tcp_hdr(skb);
1018                 th->check = ~tcp_v6_check(len, &iph->saddr, &iph->daddr, 0);
1019         } else {
1020                 struct iphdr *iph = ip_hdr(skb);
1021
1022                 skb_set_transport_header(skb, nw_off + sizeof(struct iphdr));
1023                 len = skb->len - skb_transport_offset(skb);
1024                 th = tcp_hdr(skb);
1025                 th->check = ~tcp_v4_check(len, iph->saddr, iph->daddr, 0);
1026         }
1027
1028         if (inner_mac_off) { /* tunnel */
1029                 struct udphdr *uh = NULL;
1030                 __be16 proto = *((__be16 *)(skb->data + outer_ip_off -
1031                                             ETH_HLEN - 2));
1032
1033                 if (proto == htons(ETH_P_IP)) {
1034                         struct iphdr *iph = (struct iphdr *)skb->data;
1035
1036                         if (iph->protocol == IPPROTO_UDP)
1037                                 uh = (struct udphdr *)(iph + 1);
1038                 } else {
1039                         struct ipv6hdr *iph = (struct ipv6hdr *)skb->data;
1040
1041                         if (iph->nexthdr == IPPROTO_UDP)
1042                                 uh = (struct udphdr *)(iph + 1);
1043                 }
1044                 if (uh) {
1045                         if (uh->check)
1046                                 skb_shinfo(skb)->gso_type |=
1047                                         SKB_GSO_UDP_TUNNEL_CSUM;
1048                         else
1049                                 skb_shinfo(skb)->gso_type |= SKB_GSO_UDP_TUNNEL;
1050                 }
1051         }
1052 #endif
1053         return skb;
1054 }
1055
1056 #define BNXT_IPV4_HDR_SIZE      (sizeof(struct iphdr) + sizeof(struct tcphdr))
1057 #define BNXT_IPV6_HDR_SIZE      (sizeof(struct ipv6hdr) + sizeof(struct tcphdr))
1058
1059 static struct sk_buff *bnxt_gro_func_5730x(struct bnxt_tpa_info *tpa_info,
1060                                            int payload_off, int tcp_ts,
1061                                            struct sk_buff *skb)
1062 {
1063 #ifdef CONFIG_INET
1064         struct tcphdr *th;
1065         int len, nw_off, tcp_opt_len;
1066
1067         if (tcp_ts)
1068                 tcp_opt_len = 12;
1069
1070         if (tpa_info->gso_type == SKB_GSO_TCPV4) {
1071                 struct iphdr *iph;
1072
1073                 nw_off = payload_off - BNXT_IPV4_HDR_SIZE - tcp_opt_len -
1074                          ETH_HLEN;
1075                 skb_set_network_header(skb, nw_off);
1076                 iph = ip_hdr(skb);
1077                 skb_set_transport_header(skb, nw_off + sizeof(struct iphdr));
1078                 len = skb->len - skb_transport_offset(skb);
1079                 th = tcp_hdr(skb);
1080                 th->check = ~tcp_v4_check(len, iph->saddr, iph->daddr, 0);
1081         } else if (tpa_info->gso_type == SKB_GSO_TCPV6) {
1082                 struct ipv6hdr *iph;
1083
1084                 nw_off = payload_off - BNXT_IPV6_HDR_SIZE - tcp_opt_len -
1085                          ETH_HLEN;
1086                 skb_set_network_header(skb, nw_off);
1087                 iph = ipv6_hdr(skb);
1088                 skb_set_transport_header(skb, nw_off + sizeof(struct ipv6hdr));
1089                 len = skb->len - skb_transport_offset(skb);
1090                 th = tcp_hdr(skb);
1091                 th->check = ~tcp_v6_check(len, &iph->saddr, &iph->daddr, 0);
1092         } else {
1093                 dev_kfree_skb_any(skb);
1094                 return NULL;
1095         }
1096         tcp_gro_complete(skb);
1097
1098         if (nw_off) { /* tunnel */
1099                 struct udphdr *uh = NULL;
1100
1101                 if (skb->protocol == htons(ETH_P_IP)) {
1102                         struct iphdr *iph = (struct iphdr *)skb->data;
1103
1104                         if (iph->protocol == IPPROTO_UDP)
1105                                 uh = (struct udphdr *)(iph + 1);
1106                 } else {
1107                         struct ipv6hdr *iph = (struct ipv6hdr *)skb->data;
1108
1109                         if (iph->nexthdr == IPPROTO_UDP)
1110                                 uh = (struct udphdr *)(iph + 1);
1111                 }
1112                 if (uh) {
1113                         if (uh->check)
1114                                 skb_shinfo(skb)->gso_type |=
1115                                         SKB_GSO_UDP_TUNNEL_CSUM;
1116                         else
1117                                 skb_shinfo(skb)->gso_type |= SKB_GSO_UDP_TUNNEL;
1118                 }
1119         }
1120 #endif
1121         return skb;
1122 }
1123
1124 static inline struct sk_buff *bnxt_gro_skb(struct bnxt *bp,
1125                                            struct bnxt_tpa_info *tpa_info,
1126                                            struct rx_tpa_end_cmp *tpa_end,
1127                                            struct rx_tpa_end_cmp_ext *tpa_end1,
1128                                            struct sk_buff *skb)
1129 {
1130 #ifdef CONFIG_INET
1131         int payload_off;
1132         u16 segs;
1133
1134         segs = TPA_END_TPA_SEGS(tpa_end);
1135         if (segs == 1)
1136                 return skb;
1137
1138         NAPI_GRO_CB(skb)->count = segs;
1139         skb_shinfo(skb)->gso_size =
1140                 le32_to_cpu(tpa_end1->rx_tpa_end_cmp_seg_len);
1141         skb_shinfo(skb)->gso_type = tpa_info->gso_type;
1142         payload_off = (le32_to_cpu(tpa_end->rx_tpa_end_cmp_misc_v1) &
1143                        RX_TPA_END_CMP_PAYLOAD_OFFSET) >>
1144                       RX_TPA_END_CMP_PAYLOAD_OFFSET_SHIFT;
1145         skb = bp->gro_func(tpa_info, payload_off, TPA_END_GRO_TS(tpa_end), skb);
1146 #endif
1147         return skb;
1148 }
1149
1150 static inline struct sk_buff *bnxt_tpa_end(struct bnxt *bp,
1151                                            struct bnxt_napi *bnapi,
1152                                            u32 *raw_cons,
1153                                            struct rx_tpa_end_cmp *tpa_end,
1154                                            struct rx_tpa_end_cmp_ext *tpa_end1,
1155                                            bool *agg_event)
1156 {
1157         struct bnxt_cp_ring_info *cpr = &bnapi->cp_ring;
1158         struct bnxt_rx_ring_info *rxr = bnapi->rx_ring;
1159         u8 agg_id = TPA_END_AGG_ID(tpa_end);
1160         u8 *data, agg_bufs;
1161         u16 cp_cons = RING_CMP(*raw_cons);
1162         unsigned int len;
1163         struct bnxt_tpa_info *tpa_info;
1164         dma_addr_t mapping;
1165         struct sk_buff *skb;
1166
1167         if (unlikely(bnapi->in_reset)) {
1168                 int rc = bnxt_discard_rx(bp, bnapi, raw_cons, tpa_end);
1169
1170                 if (rc < 0)
1171                         return ERR_PTR(-EBUSY);
1172                 return NULL;
1173         }
1174
1175         tpa_info = &rxr->rx_tpa[agg_id];
1176         data = tpa_info->data;
1177         prefetch(data);
1178         len = tpa_info->len;
1179         mapping = tpa_info->mapping;
1180
1181         agg_bufs = (le32_to_cpu(tpa_end->rx_tpa_end_cmp_misc_v1) &
1182                     RX_TPA_END_CMP_AGG_BUFS) >> RX_TPA_END_CMP_AGG_BUFS_SHIFT;
1183
1184         if (agg_bufs) {
1185                 if (!bnxt_agg_bufs_valid(bp, cpr, agg_bufs, raw_cons))
1186                         return ERR_PTR(-EBUSY);
1187
1188                 *agg_event = true;
1189                 cp_cons = NEXT_CMP(cp_cons);
1190         }
1191
1192         if (unlikely(agg_bufs > MAX_SKB_FRAGS)) {
1193                 bnxt_abort_tpa(bp, bnapi, cp_cons, agg_bufs);
1194                 netdev_warn(bp->dev, "TPA frags %d exceeded MAX_SKB_FRAGS %d\n",
1195                             agg_bufs, (int)MAX_SKB_FRAGS);
1196                 return NULL;
1197         }
1198
1199         if (len <= bp->rx_copy_thresh) {
1200                 skb = bnxt_copy_skb(bnapi, data, len, mapping);
1201                 if (!skb) {
1202                         bnxt_abort_tpa(bp, bnapi, cp_cons, agg_bufs);
1203                         return NULL;
1204                 }
1205         } else {
1206                 u8 *new_data;
1207                 dma_addr_t new_mapping;
1208
1209                 new_data = __bnxt_alloc_rx_data(bp, &new_mapping, GFP_ATOMIC);
1210                 if (!new_data) {
1211                         bnxt_abort_tpa(bp, bnapi, cp_cons, agg_bufs);
1212                         return NULL;
1213                 }
1214
1215                 tpa_info->data = new_data;
1216                 tpa_info->mapping = new_mapping;
1217
1218                 skb = build_skb(data, 0);
1219                 dma_unmap_single(&bp->pdev->dev, mapping, bp->rx_buf_use_size,
1220                                  PCI_DMA_FROMDEVICE);
1221
1222                 if (!skb) {
1223                         kfree(data);
1224                         bnxt_abort_tpa(bp, bnapi, cp_cons, agg_bufs);
1225                         return NULL;
1226                 }
1227                 skb_reserve(skb, BNXT_RX_OFFSET);
1228                 skb_put(skb, len);
1229         }
1230
1231         if (agg_bufs) {
1232                 skb = bnxt_rx_pages(bp, bnapi, skb, cp_cons, agg_bufs);
1233                 if (!skb) {
1234                         /* Page reuse already handled by bnxt_rx_pages(). */
1235                         return NULL;
1236                 }
1237         }
1238         skb->protocol = eth_type_trans(skb, bp->dev);
1239
1240         if (tpa_info->hash_type != PKT_HASH_TYPE_NONE)
1241                 skb_set_hash(skb, tpa_info->rss_hash, tpa_info->hash_type);
1242
1243         if ((tpa_info->flags2 & RX_CMP_FLAGS2_META_FORMAT_VLAN) &&
1244             (skb->dev->features & NETIF_F_HW_VLAN_CTAG_RX)) {
1245                 u16 vlan_proto = tpa_info->metadata >>
1246                         RX_CMP_FLAGS2_METADATA_TPID_SFT;
1247                 u16 vtag = tpa_info->metadata & RX_CMP_FLAGS2_METADATA_VID_MASK;
1248
1249                 __vlan_hwaccel_put_tag(skb, htons(vlan_proto), vtag);
1250         }
1251
1252         skb_checksum_none_assert(skb);
1253         if (likely(tpa_info->flags2 & RX_TPA_START_CMP_FLAGS2_L4_CS_CALC)) {
1254                 skb->ip_summed = CHECKSUM_UNNECESSARY;
1255                 skb->csum_level =
1256                         (tpa_info->flags2 & RX_CMP_FLAGS2_T_L4_CS_CALC) >> 3;
1257         }
1258
1259         if (TPA_END_GRO(tpa_end))
1260                 skb = bnxt_gro_skb(bp, tpa_info, tpa_end, tpa_end1, skb);
1261
1262         return skb;
1263 }
1264
1265 /* returns the following:
1266  * 1       - 1 packet successfully received
1267  * 0       - successful TPA_START, packet not completed yet
1268  * -EBUSY  - completion ring does not have all the agg buffers yet
1269  * -ENOMEM - packet aborted due to out of memory
1270  * -EIO    - packet aborted due to hw error indicated in BD
1271  */
1272 static int bnxt_rx_pkt(struct bnxt *bp, struct bnxt_napi *bnapi, u32 *raw_cons,
1273                        bool *agg_event)
1274 {
1275         struct bnxt_cp_ring_info *cpr = &bnapi->cp_ring;
1276         struct bnxt_rx_ring_info *rxr = bnapi->rx_ring;
1277         struct net_device *dev = bp->dev;
1278         struct rx_cmp *rxcmp;
1279         struct rx_cmp_ext *rxcmp1;
1280         u32 tmp_raw_cons = *raw_cons;
1281         u16 cons, prod, cp_cons = RING_CMP(tmp_raw_cons);
1282         struct bnxt_sw_rx_bd *rx_buf;
1283         unsigned int len;
1284         u8 *data, agg_bufs, cmp_type;
1285         dma_addr_t dma_addr;
1286         struct sk_buff *skb;
1287         int rc = 0;
1288
1289         rxcmp = (struct rx_cmp *)
1290                         &cpr->cp_desc_ring[CP_RING(cp_cons)][CP_IDX(cp_cons)];
1291
1292         tmp_raw_cons = NEXT_RAW_CMP(tmp_raw_cons);
1293         cp_cons = RING_CMP(tmp_raw_cons);
1294         rxcmp1 = (struct rx_cmp_ext *)
1295                         &cpr->cp_desc_ring[CP_RING(cp_cons)][CP_IDX(cp_cons)];
1296
1297         if (!RX_CMP_VALID(rxcmp1, tmp_raw_cons))
1298                 return -EBUSY;
1299
1300         cmp_type = RX_CMP_TYPE(rxcmp);
1301
1302         prod = rxr->rx_prod;
1303
1304         if (cmp_type == CMP_TYPE_RX_L2_TPA_START_CMP) {
1305                 bnxt_tpa_start(bp, rxr, (struct rx_tpa_start_cmp *)rxcmp,
1306                                (struct rx_tpa_start_cmp_ext *)rxcmp1);
1307
1308                 goto next_rx_no_prod;
1309
1310         } else if (cmp_type == CMP_TYPE_RX_L2_TPA_END_CMP) {
1311                 skb = bnxt_tpa_end(bp, bnapi, &tmp_raw_cons,
1312                                    (struct rx_tpa_end_cmp *)rxcmp,
1313                                    (struct rx_tpa_end_cmp_ext *)rxcmp1,
1314                                    agg_event);
1315
1316                 if (unlikely(IS_ERR(skb)))
1317                         return -EBUSY;
1318
1319                 rc = -ENOMEM;
1320                 if (likely(skb)) {
1321                         skb_record_rx_queue(skb, bnapi->index);
1322                         skb_mark_napi_id(skb, &bnapi->napi);
1323                         if (bnxt_busy_polling(bnapi))
1324                                 netif_receive_skb(skb);
1325                         else
1326                                 napi_gro_receive(&bnapi->napi, skb);
1327                         rc = 1;
1328                 }
1329                 goto next_rx_no_prod;
1330         }
1331
1332         cons = rxcmp->rx_cmp_opaque;
1333         rx_buf = &rxr->rx_buf_ring[cons];
1334         data = rx_buf->data;
1335         if (unlikely(cons != rxr->rx_next_cons)) {
1336                 int rc1 = bnxt_discard_rx(bp, bnapi, raw_cons, rxcmp);
1337
1338                 bnxt_sched_reset(bp, rxr);
1339                 return rc1;
1340         }
1341         prefetch(data);
1342
1343         agg_bufs = (le32_to_cpu(rxcmp->rx_cmp_misc_v1) & RX_CMP_AGG_BUFS) >>
1344                                 RX_CMP_AGG_BUFS_SHIFT;
1345
1346         if (agg_bufs) {
1347                 if (!bnxt_agg_bufs_valid(bp, cpr, agg_bufs, &tmp_raw_cons))
1348                         return -EBUSY;
1349
1350                 cp_cons = NEXT_CMP(cp_cons);
1351                 *agg_event = true;
1352         }
1353
1354         rx_buf->data = NULL;
1355         if (rxcmp1->rx_cmp_cfa_code_errors_v2 & RX_CMP_L2_ERRORS) {
1356                 bnxt_reuse_rx_data(rxr, cons, data);
1357                 if (agg_bufs)
1358                         bnxt_reuse_rx_agg_bufs(bnapi, cp_cons, agg_bufs);
1359
1360                 rc = -EIO;
1361                 goto next_rx;
1362         }
1363
1364         len = le32_to_cpu(rxcmp->rx_cmp_len_flags_type) >> RX_CMP_LEN_SHIFT;
1365         dma_addr = dma_unmap_addr(rx_buf, mapping);
1366
1367         if (len <= bp->rx_copy_thresh) {
1368                 skb = bnxt_copy_skb(bnapi, data, len, dma_addr);
1369                 bnxt_reuse_rx_data(rxr, cons, data);
1370                 if (!skb) {
1371                         rc = -ENOMEM;
1372                         goto next_rx;
1373                 }
1374         } else {
1375                 skb = bnxt_rx_skb(bp, rxr, cons, prod, data, dma_addr, len);
1376                 if (!skb) {
1377                         rc = -ENOMEM;
1378                         goto next_rx;
1379                 }
1380         }
1381
1382         if (agg_bufs) {
1383                 skb = bnxt_rx_pages(bp, bnapi, skb, cp_cons, agg_bufs);
1384                 if (!skb) {
1385                         rc = -ENOMEM;
1386                         goto next_rx;
1387                 }
1388         }
1389
1390         if (RX_CMP_HASH_VALID(rxcmp)) {
1391                 u32 hash_type = RX_CMP_HASH_TYPE(rxcmp);
1392                 enum pkt_hash_types type = PKT_HASH_TYPE_L4;
1393
1394                 /* RSS profiles 1 and 3 with extract code 0 for inner 4-tuple */
1395                 if (hash_type != 1 && hash_type != 3)
1396                         type = PKT_HASH_TYPE_L3;
1397                 skb_set_hash(skb, le32_to_cpu(rxcmp->rx_cmp_rss_hash), type);
1398         }
1399
1400         skb->protocol = eth_type_trans(skb, dev);
1401
1402         if ((rxcmp1->rx_cmp_flags2 &
1403              cpu_to_le32(RX_CMP_FLAGS2_META_FORMAT_VLAN)) &&
1404             (skb->dev->features & NETIF_F_HW_VLAN_CTAG_RX)) {
1405                 u32 meta_data = le32_to_cpu(rxcmp1->rx_cmp_meta_data);
1406                 u16 vtag = meta_data & RX_CMP_FLAGS2_METADATA_VID_MASK;
1407                 u16 vlan_proto = meta_data >> RX_CMP_FLAGS2_METADATA_TPID_SFT;
1408
1409                 __vlan_hwaccel_put_tag(skb, htons(vlan_proto), vtag);
1410         }
1411
1412         skb_checksum_none_assert(skb);
1413         if (RX_CMP_L4_CS_OK(rxcmp1)) {
1414                 if (dev->features & NETIF_F_RXCSUM) {
1415                         skb->ip_summed = CHECKSUM_UNNECESSARY;
1416                         skb->csum_level = RX_CMP_ENCAP(rxcmp1);
1417                 }
1418         } else {
1419                 if (rxcmp1->rx_cmp_cfa_code_errors_v2 & RX_CMP_L4_CS_ERR_BITS) {
1420                         if (dev->features & NETIF_F_RXCSUM)
1421                                 cpr->rx_l4_csum_errors++;
1422                 }
1423         }
1424
1425         skb_record_rx_queue(skb, bnapi->index);
1426         skb_mark_napi_id(skb, &bnapi->napi);
1427         if (bnxt_busy_polling(bnapi))
1428                 netif_receive_skb(skb);
1429         else
1430                 napi_gro_receive(&bnapi->napi, skb);
1431         rc = 1;
1432
1433 next_rx:
1434         rxr->rx_prod = NEXT_RX(prod);
1435         rxr->rx_next_cons = NEXT_RX(cons);
1436
1437 next_rx_no_prod:
1438         *raw_cons = tmp_raw_cons;
1439
1440         return rc;
1441 }
1442
1443 #define BNXT_GET_EVENT_PORT(data)       \
1444         ((data) &                               \
1445          HWRM_ASYNC_EVENT_CMPL_PORT_CONN_NOT_ALLOWED_EVENT_DATA1_PORT_ID_MASK)
1446
1447 static int bnxt_async_event_process(struct bnxt *bp,
1448                                     struct hwrm_async_event_cmpl *cmpl)
1449 {
1450         u16 event_id = le16_to_cpu(cmpl->event_id);
1451
1452         /* TODO CHIMP_FW: Define event id's for link change, error etc */
1453         switch (event_id) {
1454         case HWRM_ASYNC_EVENT_CMPL_EVENT_ID_LINK_SPEED_CFG_CHANGE: {
1455                 u32 data1 = le32_to_cpu(cmpl->event_data1);
1456                 struct bnxt_link_info *link_info = &bp->link_info;
1457
1458                 if (BNXT_VF(bp))
1459                         goto async_event_process_exit;
1460                 if (data1 & 0x20000) {
1461                         u16 fw_speed = link_info->force_link_speed;
1462                         u32 speed = bnxt_fw_to_ethtool_speed(fw_speed);
1463
1464                         netdev_warn(bp->dev, "Link speed %d no longer supported\n",
1465                                     speed);
1466                 }
1467                 /* fall thru */
1468         }
1469         case HWRM_ASYNC_EVENT_CMPL_EVENT_ID_LINK_STATUS_CHANGE:
1470                 set_bit(BNXT_LINK_CHNG_SP_EVENT, &bp->sp_event);
1471                 break;
1472         case HWRM_ASYNC_EVENT_CMPL_EVENT_ID_PF_DRVR_UNLOAD:
1473                 set_bit(BNXT_HWRM_PF_UNLOAD_SP_EVENT, &bp->sp_event);
1474                 break;
1475         case HWRM_ASYNC_EVENT_CMPL_EVENT_ID_PORT_CONN_NOT_ALLOWED: {
1476                 u32 data1 = le32_to_cpu(cmpl->event_data1);
1477                 u16 port_id = BNXT_GET_EVENT_PORT(data1);
1478
1479                 if (BNXT_VF(bp))
1480                         break;
1481
1482                 if (bp->pf.port_id != port_id)
1483                         break;
1484
1485                 set_bit(BNXT_HWRM_PORT_MODULE_SP_EVENT, &bp->sp_event);
1486                 break;
1487         }
1488         case HWRM_ASYNC_EVENT_CMPL_EVENT_ID_VF_CFG_CHANGE:
1489                 if (BNXT_PF(bp))
1490                         goto async_event_process_exit;
1491                 set_bit(BNXT_RESET_TASK_SILENT_SP_EVENT, &bp->sp_event);
1492                 break;
1493         default:
1494                 netdev_err(bp->dev, "unhandled ASYNC event (id 0x%x)\n",
1495                            event_id);
1496                 goto async_event_process_exit;
1497         }
1498         schedule_work(&bp->sp_task);
1499 async_event_process_exit:
1500         return 0;
1501 }
1502
1503 static int bnxt_hwrm_handler(struct bnxt *bp, struct tx_cmp *txcmp)
1504 {
1505         u16 cmpl_type = TX_CMP_TYPE(txcmp), vf_id, seq_id;
1506         struct hwrm_cmpl *h_cmpl = (struct hwrm_cmpl *)txcmp;
1507         struct hwrm_fwd_req_cmpl *fwd_req_cmpl =
1508                                 (struct hwrm_fwd_req_cmpl *)txcmp;
1509
1510         switch (cmpl_type) {
1511         case CMPL_BASE_TYPE_HWRM_DONE:
1512                 seq_id = le16_to_cpu(h_cmpl->sequence_id);
1513                 if (seq_id == bp->hwrm_intr_seq_id)
1514                         bp->hwrm_intr_seq_id = HWRM_SEQ_ID_INVALID;
1515                 else
1516                         netdev_err(bp->dev, "Invalid hwrm seq id %d\n", seq_id);
1517                 break;
1518
1519         case CMPL_BASE_TYPE_HWRM_FWD_REQ:
1520                 vf_id = le16_to_cpu(fwd_req_cmpl->source_id);
1521
1522                 if ((vf_id < bp->pf.first_vf_id) ||
1523                     (vf_id >= bp->pf.first_vf_id + bp->pf.active_vfs)) {
1524                         netdev_err(bp->dev, "Msg contains invalid VF id %x\n",
1525                                    vf_id);
1526                         return -EINVAL;
1527                 }
1528
1529                 set_bit(vf_id - bp->pf.first_vf_id, bp->pf.vf_event_bmap);
1530                 set_bit(BNXT_HWRM_EXEC_FWD_REQ_SP_EVENT, &bp->sp_event);
1531                 schedule_work(&bp->sp_task);
1532                 break;
1533
1534         case CMPL_BASE_TYPE_HWRM_ASYNC_EVENT:
1535                 bnxt_async_event_process(bp,
1536                                          (struct hwrm_async_event_cmpl *)txcmp);
1537
1538         default:
1539                 break;
1540         }
1541
1542         return 0;
1543 }
1544
1545 static irqreturn_t bnxt_msix(int irq, void *dev_instance)
1546 {
1547         struct bnxt_napi *bnapi = dev_instance;
1548         struct bnxt *bp = bnapi->bp;
1549         struct bnxt_cp_ring_info *cpr = &bnapi->cp_ring;
1550         u32 cons = RING_CMP(cpr->cp_raw_cons);
1551
1552         prefetch(&cpr->cp_desc_ring[CP_RING(cons)][CP_IDX(cons)]);
1553         napi_schedule(&bnapi->napi);
1554         return IRQ_HANDLED;
1555 }
1556
1557 static inline int bnxt_has_work(struct bnxt *bp, struct bnxt_cp_ring_info *cpr)
1558 {
1559         u32 raw_cons = cpr->cp_raw_cons;
1560         u16 cons = RING_CMP(raw_cons);
1561         struct tx_cmp *txcmp;
1562
1563         txcmp = &cpr->cp_desc_ring[CP_RING(cons)][CP_IDX(cons)];
1564
1565         return TX_CMP_VALID(txcmp, raw_cons);
1566 }
1567
1568 static irqreturn_t bnxt_inta(int irq, void *dev_instance)
1569 {
1570         struct bnxt_napi *bnapi = dev_instance;
1571         struct bnxt *bp = bnapi->bp;
1572         struct bnxt_cp_ring_info *cpr = &bnapi->cp_ring;
1573         u32 cons = RING_CMP(cpr->cp_raw_cons);
1574         u32 int_status;
1575
1576         prefetch(&cpr->cp_desc_ring[CP_RING(cons)][CP_IDX(cons)]);
1577
1578         if (!bnxt_has_work(bp, cpr)) {
1579                 int_status = readl(bp->bar0 + BNXT_CAG_REG_LEGACY_INT_STATUS);
1580                 /* return if erroneous interrupt */
1581                 if (!(int_status & (0x10000 << cpr->cp_ring_struct.fw_ring_id)))
1582                         return IRQ_NONE;
1583         }
1584
1585         /* disable ring IRQ */
1586         BNXT_CP_DB_IRQ_DIS(cpr->cp_doorbell);
1587
1588         /* Return here if interrupt is shared and is disabled. */
1589         if (unlikely(atomic_read(&bp->intr_sem) != 0))
1590                 return IRQ_HANDLED;
1591
1592         napi_schedule(&bnapi->napi);
1593         return IRQ_HANDLED;
1594 }
1595
1596 static int bnxt_poll_work(struct bnxt *bp, struct bnxt_napi *bnapi, int budget)
1597 {
1598         struct bnxt_cp_ring_info *cpr = &bnapi->cp_ring;
1599         u32 raw_cons = cpr->cp_raw_cons;
1600         u32 cons;
1601         int tx_pkts = 0;
1602         int rx_pkts = 0;
1603         bool rx_event = false;
1604         bool agg_event = false;
1605         struct tx_cmp *txcmp;
1606
1607         while (1) {
1608                 int rc;
1609
1610                 cons = RING_CMP(raw_cons);
1611                 txcmp = &cpr->cp_desc_ring[CP_RING(cons)][CP_IDX(cons)];
1612
1613                 if (!TX_CMP_VALID(txcmp, raw_cons))
1614                         break;
1615
1616                 /* The valid test of the entry must be done first before
1617                  * reading any further.
1618                  */
1619                 dma_rmb();
1620                 if (TX_CMP_TYPE(txcmp) == CMP_TYPE_TX_L2_CMP) {
1621                         tx_pkts++;
1622                         /* return full budget so NAPI will complete. */
1623                         if (unlikely(tx_pkts > bp->tx_wake_thresh))
1624                                 rx_pkts = budget;
1625                 } else if ((TX_CMP_TYPE(txcmp) & 0x30) == 0x10) {
1626                         rc = bnxt_rx_pkt(bp, bnapi, &raw_cons, &agg_event);
1627                         if (likely(rc >= 0))
1628                                 rx_pkts += rc;
1629                         else if (rc == -EBUSY)  /* partial completion */
1630                                 break;
1631                         rx_event = true;
1632                 } else if (unlikely((TX_CMP_TYPE(txcmp) ==
1633                                      CMPL_BASE_TYPE_HWRM_DONE) ||
1634                                     (TX_CMP_TYPE(txcmp) ==
1635                                      CMPL_BASE_TYPE_HWRM_FWD_REQ) ||
1636                                     (TX_CMP_TYPE(txcmp) ==
1637                                      CMPL_BASE_TYPE_HWRM_ASYNC_EVENT))) {
1638                         bnxt_hwrm_handler(bp, txcmp);
1639                 }
1640                 raw_cons = NEXT_RAW_CMP(raw_cons);
1641
1642                 if (rx_pkts == budget)
1643                         break;
1644         }
1645
1646         cpr->cp_raw_cons = raw_cons;
1647         /* ACK completion ring before freeing tx ring and producing new
1648          * buffers in rx/agg rings to prevent overflowing the completion
1649          * ring.
1650          */
1651         BNXT_CP_DB(cpr->cp_doorbell, cpr->cp_raw_cons);
1652
1653         if (tx_pkts)
1654                 bnxt_tx_int(bp, bnapi, tx_pkts);
1655
1656         if (rx_event) {
1657                 struct bnxt_rx_ring_info *rxr = bnapi->rx_ring;
1658
1659                 writel(DB_KEY_RX | rxr->rx_prod, rxr->rx_doorbell);
1660                 writel(DB_KEY_RX | rxr->rx_prod, rxr->rx_doorbell);
1661                 if (agg_event) {
1662                         writel(DB_KEY_RX | rxr->rx_agg_prod,
1663                                rxr->rx_agg_doorbell);
1664                         writel(DB_KEY_RX | rxr->rx_agg_prod,
1665                                rxr->rx_agg_doorbell);
1666                 }
1667         }
1668         return rx_pkts;
1669 }
1670
1671 static int bnxt_poll(struct napi_struct *napi, int budget)
1672 {
1673         struct bnxt_napi *bnapi = container_of(napi, struct bnxt_napi, napi);
1674         struct bnxt *bp = bnapi->bp;
1675         struct bnxt_cp_ring_info *cpr = &bnapi->cp_ring;
1676         int work_done = 0;
1677
1678         if (!bnxt_lock_napi(bnapi))
1679                 return budget;
1680
1681         while (1) {
1682                 work_done += bnxt_poll_work(bp, bnapi, budget - work_done);
1683
1684                 if (work_done >= budget)
1685                         break;
1686
1687                 if (!bnxt_has_work(bp, cpr)) {
1688                         napi_complete(napi);
1689                         BNXT_CP_DB_REARM(cpr->cp_doorbell, cpr->cp_raw_cons);
1690                         break;
1691                 }
1692         }
1693         mmiowb();
1694         bnxt_unlock_napi(bnapi);
1695         return work_done;
1696 }
1697
1698 #ifdef CONFIG_NET_RX_BUSY_POLL
1699 static int bnxt_busy_poll(struct napi_struct *napi)
1700 {
1701         struct bnxt_napi *bnapi = container_of(napi, struct bnxt_napi, napi);
1702         struct bnxt *bp = bnapi->bp;
1703         struct bnxt_cp_ring_info *cpr = &bnapi->cp_ring;
1704         int rx_work, budget = 4;
1705
1706         if (atomic_read(&bp->intr_sem) != 0)
1707                 return LL_FLUSH_FAILED;
1708
1709         if (!bnxt_lock_poll(bnapi))
1710                 return LL_FLUSH_BUSY;
1711
1712         rx_work = bnxt_poll_work(bp, bnapi, budget);
1713
1714         BNXT_CP_DB_REARM(cpr->cp_doorbell, cpr->cp_raw_cons);
1715
1716         bnxt_unlock_poll(bnapi);
1717         return rx_work;
1718 }
1719 #endif
1720
1721 static void bnxt_free_tx_skbs(struct bnxt *bp)
1722 {
1723         int i, max_idx;
1724         struct pci_dev *pdev = bp->pdev;
1725
1726         if (!bp->tx_ring)
1727                 return;
1728
1729         max_idx = bp->tx_nr_pages * TX_DESC_CNT;
1730         for (i = 0; i < bp->tx_nr_rings; i++) {
1731                 struct bnxt_tx_ring_info *txr = &bp->tx_ring[i];
1732                 int j;
1733
1734                 for (j = 0; j < max_idx;) {
1735                         struct bnxt_sw_tx_bd *tx_buf = &txr->tx_buf_ring[j];
1736                         struct sk_buff *skb = tx_buf->skb;
1737                         int k, last;
1738
1739                         if (!skb) {
1740                                 j++;
1741                                 continue;
1742                         }
1743
1744                         tx_buf->skb = NULL;
1745
1746                         if (tx_buf->is_push) {
1747                                 dev_kfree_skb(skb);
1748                                 j += 2;
1749                                 continue;
1750                         }
1751
1752                         dma_unmap_single(&pdev->dev,
1753                                          dma_unmap_addr(tx_buf, mapping),
1754                                          skb_headlen(skb),
1755                                          PCI_DMA_TODEVICE);
1756
1757                         last = tx_buf->nr_frags;
1758                         j += 2;
1759                         for (k = 0; k < last; k++, j++) {
1760                                 int ring_idx = j & bp->tx_ring_mask;
1761                                 skb_frag_t *frag = &skb_shinfo(skb)->frags[k];
1762
1763                                 tx_buf = &txr->tx_buf_ring[ring_idx];
1764                                 dma_unmap_page(
1765                                         &pdev->dev,
1766                                         dma_unmap_addr(tx_buf, mapping),
1767                                         skb_frag_size(frag), PCI_DMA_TODEVICE);
1768                         }
1769                         dev_kfree_skb(skb);
1770                 }
1771                 netdev_tx_reset_queue(netdev_get_tx_queue(bp->dev, i));
1772         }
1773 }
1774
1775 static void bnxt_free_rx_skbs(struct bnxt *bp)
1776 {
1777         int i, max_idx, max_agg_idx;
1778         struct pci_dev *pdev = bp->pdev;
1779
1780         if (!bp->rx_ring)
1781                 return;
1782
1783         max_idx = bp->rx_nr_pages * RX_DESC_CNT;
1784         max_agg_idx = bp->rx_agg_nr_pages * RX_DESC_CNT;
1785         for (i = 0; i < bp->rx_nr_rings; i++) {
1786                 struct bnxt_rx_ring_info *rxr = &bp->rx_ring[i];
1787                 int j;
1788
1789                 if (rxr->rx_tpa) {
1790                         for (j = 0; j < MAX_TPA; j++) {
1791                                 struct bnxt_tpa_info *tpa_info =
1792                                                         &rxr->rx_tpa[j];
1793                                 u8 *data = tpa_info->data;
1794
1795                                 if (!data)
1796                                         continue;
1797
1798                                 dma_unmap_single(
1799                                         &pdev->dev,
1800                                         dma_unmap_addr(tpa_info, mapping),
1801                                         bp->rx_buf_use_size,
1802                                         PCI_DMA_FROMDEVICE);
1803
1804                                 tpa_info->data = NULL;
1805
1806                                 kfree(data);
1807                         }
1808                 }
1809
1810                 for (j = 0; j < max_idx; j++) {
1811                         struct bnxt_sw_rx_bd *rx_buf = &rxr->rx_buf_ring[j];
1812                         u8 *data = rx_buf->data;
1813
1814                         if (!data)
1815                                 continue;
1816
1817                         dma_unmap_single(&pdev->dev,
1818                                          dma_unmap_addr(rx_buf, mapping),
1819                                          bp->rx_buf_use_size,
1820                                          PCI_DMA_FROMDEVICE);
1821
1822                         rx_buf->data = NULL;
1823
1824                         kfree(data);
1825                 }
1826
1827                 for (j = 0; j < max_agg_idx; j++) {
1828                         struct bnxt_sw_rx_agg_bd *rx_agg_buf =
1829                                 &rxr->rx_agg_ring[j];
1830                         struct page *page = rx_agg_buf->page;
1831
1832                         if (!page)
1833                                 continue;
1834
1835                         dma_unmap_page(&pdev->dev,
1836                                        dma_unmap_addr(rx_agg_buf, mapping),
1837                                        BNXT_RX_PAGE_SIZE, PCI_DMA_FROMDEVICE);
1838
1839                         rx_agg_buf->page = NULL;
1840                         __clear_bit(j, rxr->rx_agg_bmap);
1841
1842                         __free_page(page);
1843                 }
1844                 if (rxr->rx_page) {
1845                         __free_page(rxr->rx_page);
1846                         rxr->rx_page = NULL;
1847                 }
1848         }
1849 }
1850
1851 static void bnxt_free_skbs(struct bnxt *bp)
1852 {
1853         bnxt_free_tx_skbs(bp);
1854         bnxt_free_rx_skbs(bp);
1855 }
1856
1857 static void bnxt_free_ring(struct bnxt *bp, struct bnxt_ring_struct *ring)
1858 {
1859         struct pci_dev *pdev = bp->pdev;
1860         int i;
1861
1862         for (i = 0; i < ring->nr_pages; i++) {
1863                 if (!ring->pg_arr[i])
1864                         continue;
1865
1866                 dma_free_coherent(&pdev->dev, ring->page_size,
1867                                   ring->pg_arr[i], ring->dma_arr[i]);
1868
1869                 ring->pg_arr[i] = NULL;
1870         }
1871         if (ring->pg_tbl) {
1872                 dma_free_coherent(&pdev->dev, ring->nr_pages * 8,
1873                                   ring->pg_tbl, ring->pg_tbl_map);
1874                 ring->pg_tbl = NULL;
1875         }
1876         if (ring->vmem_size && *ring->vmem) {
1877                 vfree(*ring->vmem);
1878                 *ring->vmem = NULL;
1879         }
1880 }
1881
1882 static int bnxt_alloc_ring(struct bnxt *bp, struct bnxt_ring_struct *ring)
1883 {
1884         int i;
1885         struct pci_dev *pdev = bp->pdev;
1886
1887         if (ring->nr_pages > 1) {
1888                 ring->pg_tbl = dma_alloc_coherent(&pdev->dev,
1889                                                   ring->nr_pages * 8,
1890                                                   &ring->pg_tbl_map,
1891                                                   GFP_KERNEL);
1892                 if (!ring->pg_tbl)
1893                         return -ENOMEM;
1894         }
1895
1896         for (i = 0; i < ring->nr_pages; i++) {
1897                 ring->pg_arr[i] = dma_alloc_coherent(&pdev->dev,
1898                                                      ring->page_size,
1899                                                      &ring->dma_arr[i],
1900                                                      GFP_KERNEL);
1901                 if (!ring->pg_arr[i])
1902                         return -ENOMEM;
1903
1904                 if (ring->nr_pages > 1)
1905                         ring->pg_tbl[i] = cpu_to_le64(ring->dma_arr[i]);
1906         }
1907
1908         if (ring->vmem_size) {
1909                 *ring->vmem = vzalloc(ring->vmem_size);
1910                 if (!(*ring->vmem))
1911                         return -ENOMEM;
1912         }
1913         return 0;
1914 }
1915
1916 static void bnxt_free_rx_rings(struct bnxt *bp)
1917 {
1918         int i;
1919
1920         if (!bp->rx_ring)
1921                 return;
1922
1923         for (i = 0; i < bp->rx_nr_rings; i++) {
1924                 struct bnxt_rx_ring_info *rxr = &bp->rx_ring[i];
1925                 struct bnxt_ring_struct *ring;
1926
1927                 kfree(rxr->rx_tpa);
1928                 rxr->rx_tpa = NULL;
1929
1930                 kfree(rxr->rx_agg_bmap);
1931                 rxr->rx_agg_bmap = NULL;
1932
1933                 ring = &rxr->rx_ring_struct;
1934                 bnxt_free_ring(bp, ring);
1935
1936                 ring = &rxr->rx_agg_ring_struct;
1937                 bnxt_free_ring(bp, ring);
1938         }
1939 }
1940
1941 static int bnxt_alloc_rx_rings(struct bnxt *bp)
1942 {
1943         int i, rc, agg_rings = 0, tpa_rings = 0;
1944
1945         if (!bp->rx_ring)
1946                 return -ENOMEM;
1947
1948         if (bp->flags & BNXT_FLAG_AGG_RINGS)
1949                 agg_rings = 1;
1950
1951         if (bp->flags & BNXT_FLAG_TPA)
1952                 tpa_rings = 1;
1953
1954         for (i = 0; i < bp->rx_nr_rings; i++) {
1955                 struct bnxt_rx_ring_info *rxr = &bp->rx_ring[i];
1956                 struct bnxt_ring_struct *ring;
1957
1958                 ring = &rxr->rx_ring_struct;
1959
1960                 rc = bnxt_alloc_ring(bp, ring);
1961                 if (rc)
1962                         return rc;
1963
1964                 if (agg_rings) {
1965                         u16 mem_size;
1966
1967                         ring = &rxr->rx_agg_ring_struct;
1968                         rc = bnxt_alloc_ring(bp, ring);
1969                         if (rc)
1970                                 return rc;
1971
1972                         rxr->rx_agg_bmap_size = bp->rx_agg_ring_mask + 1;
1973                         mem_size = rxr->rx_agg_bmap_size / 8;
1974                         rxr->rx_agg_bmap = kzalloc(mem_size, GFP_KERNEL);
1975                         if (!rxr->rx_agg_bmap)
1976                                 return -ENOMEM;
1977
1978                         if (tpa_rings) {
1979                                 rxr->rx_tpa = kcalloc(MAX_TPA,
1980                                                 sizeof(struct bnxt_tpa_info),
1981                                                 GFP_KERNEL);
1982                                 if (!rxr->rx_tpa)
1983                                         return -ENOMEM;
1984                         }
1985                 }
1986         }
1987         return 0;
1988 }
1989
1990 static void bnxt_free_tx_rings(struct bnxt *bp)
1991 {
1992         int i;
1993         struct pci_dev *pdev = bp->pdev;
1994
1995         if (!bp->tx_ring)
1996                 return;
1997
1998         for (i = 0; i < bp->tx_nr_rings; i++) {
1999                 struct bnxt_tx_ring_info *txr = &bp->tx_ring[i];
2000                 struct bnxt_ring_struct *ring;
2001
2002                 if (txr->tx_push) {
2003                         dma_free_coherent(&pdev->dev, bp->tx_push_size,
2004                                           txr->tx_push, txr->tx_push_mapping);
2005                         txr->tx_push = NULL;
2006                 }
2007
2008                 ring = &txr->tx_ring_struct;
2009
2010                 bnxt_free_ring(bp, ring);
2011         }
2012 }
2013
2014 static int bnxt_alloc_tx_rings(struct bnxt *bp)
2015 {
2016         int i, j, rc;
2017         struct pci_dev *pdev = bp->pdev;
2018
2019         bp->tx_push_size = 0;
2020         if (bp->tx_push_thresh) {
2021                 int push_size;
2022
2023                 push_size  = L1_CACHE_ALIGN(sizeof(struct tx_push_bd) +
2024                                         bp->tx_push_thresh);
2025
2026                 if (push_size > 256) {
2027                         push_size = 0;
2028                         bp->tx_push_thresh = 0;
2029                 }
2030
2031                 bp->tx_push_size = push_size;
2032         }
2033
2034         for (i = 0, j = 0; i < bp->tx_nr_rings; i++) {
2035                 struct bnxt_tx_ring_info *txr = &bp->tx_ring[i];
2036                 struct bnxt_ring_struct *ring;
2037
2038                 ring = &txr->tx_ring_struct;
2039
2040                 rc = bnxt_alloc_ring(bp, ring);
2041                 if (rc)
2042                         return rc;
2043
2044                 if (bp->tx_push_size) {
2045                         dma_addr_t mapping;
2046
2047                         /* One pre-allocated DMA buffer to backup
2048                          * TX push operation
2049                          */
2050                         txr->tx_push = dma_alloc_coherent(&pdev->dev,
2051                                                 bp->tx_push_size,
2052                                                 &txr->tx_push_mapping,
2053                                                 GFP_KERNEL);
2054
2055                         if (!txr->tx_push)
2056                                 return -ENOMEM;
2057
2058                         mapping = txr->tx_push_mapping +
2059                                 sizeof(struct tx_push_bd);
2060                         txr->data_mapping = cpu_to_le64(mapping);
2061
2062                         memset(txr->tx_push, 0, sizeof(struct tx_push_bd));
2063                 }
2064                 ring->queue_id = bp->q_info[j].queue_id;
2065                 if (i % bp->tx_nr_rings_per_tc == (bp->tx_nr_rings_per_tc - 1))
2066                         j++;
2067         }
2068         return 0;
2069 }
2070
2071 static void bnxt_free_cp_rings(struct bnxt *bp)
2072 {
2073         int i;
2074
2075         if (!bp->bnapi)
2076                 return;
2077
2078         for (i = 0; i < bp->cp_nr_rings; i++) {
2079                 struct bnxt_napi *bnapi = bp->bnapi[i];
2080                 struct bnxt_cp_ring_info *cpr;
2081                 struct bnxt_ring_struct *ring;
2082
2083                 if (!bnapi)
2084                         continue;
2085
2086                 cpr = &bnapi->cp_ring;
2087                 ring = &cpr->cp_ring_struct;
2088
2089                 bnxt_free_ring(bp, ring);
2090         }
2091 }
2092
2093 static int bnxt_alloc_cp_rings(struct bnxt *bp)
2094 {
2095         int i, rc;
2096
2097         for (i = 0; i < bp->cp_nr_rings; i++) {
2098                 struct bnxt_napi *bnapi = bp->bnapi[i];
2099                 struct bnxt_cp_ring_info *cpr;
2100                 struct bnxt_ring_struct *ring;
2101
2102                 if (!bnapi)
2103                         continue;
2104
2105                 cpr = &bnapi->cp_ring;
2106                 ring = &cpr->cp_ring_struct;
2107
2108                 rc = bnxt_alloc_ring(bp, ring);
2109                 if (rc)
2110                         return rc;
2111         }
2112         return 0;
2113 }
2114
2115 static void bnxt_init_ring_struct(struct bnxt *bp)
2116 {
2117         int i;
2118
2119         for (i = 0; i < bp->cp_nr_rings; i++) {
2120                 struct bnxt_napi *bnapi = bp->bnapi[i];
2121                 struct bnxt_cp_ring_info *cpr;
2122                 struct bnxt_rx_ring_info *rxr;
2123                 struct bnxt_tx_ring_info *txr;
2124                 struct bnxt_ring_struct *ring;
2125
2126                 if (!bnapi)
2127                         continue;
2128
2129                 cpr = &bnapi->cp_ring;
2130                 ring = &cpr->cp_ring_struct;
2131                 ring->nr_pages = bp->cp_nr_pages;
2132                 ring->page_size = HW_CMPD_RING_SIZE;
2133                 ring->pg_arr = (void **)cpr->cp_desc_ring;
2134                 ring->dma_arr = cpr->cp_desc_mapping;
2135                 ring->vmem_size = 0;
2136
2137                 rxr = bnapi->rx_ring;
2138                 if (!rxr)
2139                         goto skip_rx;
2140
2141                 ring = &rxr->rx_ring_struct;
2142                 ring->nr_pages = bp->rx_nr_pages;
2143                 ring->page_size = HW_RXBD_RING_SIZE;
2144                 ring->pg_arr = (void **)rxr->rx_desc_ring;
2145                 ring->dma_arr = rxr->rx_desc_mapping;
2146                 ring->vmem_size = SW_RXBD_RING_SIZE * bp->rx_nr_pages;
2147                 ring->vmem = (void **)&rxr->rx_buf_ring;
2148
2149                 ring = &rxr->rx_agg_ring_struct;
2150                 ring->nr_pages = bp->rx_agg_nr_pages;
2151                 ring->page_size = HW_RXBD_RING_SIZE;
2152                 ring->pg_arr = (void **)rxr->rx_agg_desc_ring;
2153                 ring->dma_arr = rxr->rx_agg_desc_mapping;
2154                 ring->vmem_size = SW_RXBD_AGG_RING_SIZE * bp->rx_agg_nr_pages;
2155                 ring->vmem = (void **)&rxr->rx_agg_ring;
2156
2157 skip_rx:
2158                 txr = bnapi->tx_ring;
2159                 if (!txr)
2160                         continue;
2161
2162                 ring = &txr->tx_ring_struct;
2163                 ring->nr_pages = bp->tx_nr_pages;
2164                 ring->page_size = HW_RXBD_RING_SIZE;
2165                 ring->pg_arr = (void **)txr->tx_desc_ring;
2166                 ring->dma_arr = txr->tx_desc_mapping;
2167                 ring->vmem_size = SW_TXBD_RING_SIZE * bp->tx_nr_pages;
2168                 ring->vmem = (void **)&txr->tx_buf_ring;
2169         }
2170 }
2171
2172 static void bnxt_init_rxbd_pages(struct bnxt_ring_struct *ring, u32 type)
2173 {
2174         int i;
2175         u32 prod;
2176         struct rx_bd **rx_buf_ring;
2177
2178         rx_buf_ring = (struct rx_bd **)ring->pg_arr;
2179         for (i = 0, prod = 0; i < ring->nr_pages; i++) {
2180                 int j;
2181                 struct rx_bd *rxbd;
2182
2183                 rxbd = rx_buf_ring[i];
2184                 if (!rxbd)
2185                         continue;
2186
2187                 for (j = 0; j < RX_DESC_CNT; j++, rxbd++, prod++) {
2188                         rxbd->rx_bd_len_flags_type = cpu_to_le32(type);
2189                         rxbd->rx_bd_opaque = prod;
2190                 }
2191         }
2192 }
2193
2194 static int bnxt_init_one_rx_ring(struct bnxt *bp, int ring_nr)
2195 {
2196         struct net_device *dev = bp->dev;
2197         struct bnxt_rx_ring_info *rxr;
2198         struct bnxt_ring_struct *ring;
2199         u32 prod, type;
2200         int i;
2201
2202         type = (bp->rx_buf_use_size << RX_BD_LEN_SHIFT) |
2203                 RX_BD_TYPE_RX_PACKET_BD | RX_BD_FLAGS_EOP;
2204
2205         if (NET_IP_ALIGN == 2)
2206                 type |= RX_BD_FLAGS_SOP;
2207
2208         rxr = &bp->rx_ring[ring_nr];
2209         ring = &rxr->rx_ring_struct;
2210         bnxt_init_rxbd_pages(ring, type);
2211
2212         prod = rxr->rx_prod;
2213         for (i = 0; i < bp->rx_ring_size; i++) {
2214                 if (bnxt_alloc_rx_data(bp, rxr, prod, GFP_KERNEL) != 0) {
2215                         netdev_warn(dev, "init'ed rx ring %d with %d/%d skbs only\n",
2216                                     ring_nr, i, bp->rx_ring_size);
2217                         break;
2218                 }
2219                 prod = NEXT_RX(prod);
2220         }
2221         rxr->rx_prod = prod;
2222         ring->fw_ring_id = INVALID_HW_RING_ID;
2223
2224         ring = &rxr->rx_agg_ring_struct;
2225         ring->fw_ring_id = INVALID_HW_RING_ID;
2226
2227         if (!(bp->flags & BNXT_FLAG_AGG_RINGS))
2228                 return 0;
2229
2230         type = ((u32)BNXT_RX_PAGE_SIZE << RX_BD_LEN_SHIFT) |
2231                 RX_BD_TYPE_RX_AGG_BD | RX_BD_FLAGS_SOP;
2232
2233         bnxt_init_rxbd_pages(ring, type);
2234
2235         prod = rxr->rx_agg_prod;
2236         for (i = 0; i < bp->rx_agg_ring_size; i++) {
2237                 if (bnxt_alloc_rx_page(bp, rxr, prod, GFP_KERNEL) != 0) {
2238                         netdev_warn(dev, "init'ed rx ring %d with %d/%d pages only\n",
2239                                     ring_nr, i, bp->rx_ring_size);
2240                         break;
2241                 }
2242                 prod = NEXT_RX_AGG(prod);
2243         }
2244         rxr->rx_agg_prod = prod;
2245
2246         if (bp->flags & BNXT_FLAG_TPA) {
2247                 if (rxr->rx_tpa) {
2248                         u8 *data;
2249                         dma_addr_t mapping;
2250
2251                         for (i = 0; i < MAX_TPA; i++) {
2252                                 data = __bnxt_alloc_rx_data(bp, &mapping,
2253                                                             GFP_KERNEL);
2254                                 if (!data)
2255                                         return -ENOMEM;
2256
2257                                 rxr->rx_tpa[i].data = data;
2258                                 rxr->rx_tpa[i].mapping = mapping;
2259                         }
2260                 } else {
2261                         netdev_err(bp->dev, "No resource allocated for LRO/GRO\n");
2262                         return -ENOMEM;
2263                 }
2264         }
2265
2266         return 0;
2267 }
2268
2269 static int bnxt_init_rx_rings(struct bnxt *bp)
2270 {
2271         int i, rc = 0;
2272
2273         for (i = 0; i < bp->rx_nr_rings; i++) {
2274                 rc = bnxt_init_one_rx_ring(bp, i);
2275                 if (rc)
2276                         break;
2277         }
2278
2279         return rc;
2280 }
2281
2282 static int bnxt_init_tx_rings(struct bnxt *bp)
2283 {
2284         u16 i;
2285
2286         bp->tx_wake_thresh = max_t(int, bp->tx_ring_size / 2,
2287                                    MAX_SKB_FRAGS + 1);
2288
2289         for (i = 0; i < bp->tx_nr_rings; i++) {
2290                 struct bnxt_tx_ring_info *txr = &bp->tx_ring[i];
2291                 struct bnxt_ring_struct *ring = &txr->tx_ring_struct;
2292
2293                 ring->fw_ring_id = INVALID_HW_RING_ID;
2294         }
2295
2296         return 0;
2297 }
2298
2299 static void bnxt_free_ring_grps(struct bnxt *bp)
2300 {
2301         kfree(bp->grp_info);
2302         bp->grp_info = NULL;
2303 }
2304
2305 static int bnxt_init_ring_grps(struct bnxt *bp, bool irq_re_init)
2306 {
2307         int i;
2308
2309         if (irq_re_init) {
2310                 bp->grp_info = kcalloc(bp->cp_nr_rings,
2311                                        sizeof(struct bnxt_ring_grp_info),
2312                                        GFP_KERNEL);
2313                 if (!bp->grp_info)
2314                         return -ENOMEM;
2315         }
2316         for (i = 0; i < bp->cp_nr_rings; i++) {
2317                 if (irq_re_init)
2318                         bp->grp_info[i].fw_stats_ctx = INVALID_HW_RING_ID;
2319                 bp->grp_info[i].fw_grp_id = INVALID_HW_RING_ID;
2320                 bp->grp_info[i].rx_fw_ring_id = INVALID_HW_RING_ID;
2321                 bp->grp_info[i].agg_fw_ring_id = INVALID_HW_RING_ID;
2322                 bp->grp_info[i].cp_fw_ring_id = INVALID_HW_RING_ID;
2323         }
2324         return 0;
2325 }
2326
2327 static void bnxt_free_vnics(struct bnxt *bp)
2328 {
2329         kfree(bp->vnic_info);
2330         bp->vnic_info = NULL;
2331         bp->nr_vnics = 0;
2332 }
2333
2334 static int bnxt_alloc_vnics(struct bnxt *bp)
2335 {
2336         int num_vnics = 1;
2337
2338 #ifdef CONFIG_RFS_ACCEL
2339         if (bp->flags & BNXT_FLAG_RFS)
2340                 num_vnics += bp->rx_nr_rings;
2341 #endif
2342
2343         bp->vnic_info = kcalloc(num_vnics, sizeof(struct bnxt_vnic_info),
2344                                 GFP_KERNEL);
2345         if (!bp->vnic_info)
2346                 return -ENOMEM;
2347
2348         bp->nr_vnics = num_vnics;
2349         return 0;
2350 }
2351
2352 static void bnxt_init_vnics(struct bnxt *bp)
2353 {
2354         int i;
2355
2356         for (i = 0; i < bp->nr_vnics; i++) {
2357                 struct bnxt_vnic_info *vnic = &bp->vnic_info[i];
2358
2359                 vnic->fw_vnic_id = INVALID_HW_RING_ID;
2360                 vnic->fw_rss_cos_lb_ctx = INVALID_HW_RING_ID;
2361                 vnic->fw_l2_ctx_id = INVALID_HW_RING_ID;
2362
2363                 if (bp->vnic_info[i].rss_hash_key) {
2364                         if (i == 0)
2365                                 prandom_bytes(vnic->rss_hash_key,
2366                                               HW_HASH_KEY_SIZE);
2367                         else
2368                                 memcpy(vnic->rss_hash_key,
2369                                        bp->vnic_info[0].rss_hash_key,
2370                                        HW_HASH_KEY_SIZE);
2371                 }
2372         }
2373 }
2374
2375 static int bnxt_calc_nr_ring_pages(u32 ring_size, int desc_per_pg)
2376 {
2377         int pages;
2378
2379         pages = ring_size / desc_per_pg;
2380
2381         if (!pages)
2382                 return 1;
2383
2384         pages++;
2385
2386         while (pages & (pages - 1))
2387                 pages++;
2388
2389         return pages;
2390 }
2391
2392 static void bnxt_set_tpa_flags(struct bnxt *bp)
2393 {
2394         bp->flags &= ~BNXT_FLAG_TPA;
2395         if (bp->dev->features & NETIF_F_LRO)
2396                 bp->flags |= BNXT_FLAG_LRO;
2397         if (bp->dev->features & NETIF_F_GRO)
2398                 bp->flags |= BNXT_FLAG_GRO;
2399 }
2400
2401 /* bp->rx_ring_size, bp->tx_ring_size, dev->mtu, BNXT_FLAG_{G|L}RO flags must
2402  * be set on entry.
2403  */
2404 void bnxt_set_ring_params(struct bnxt *bp)
2405 {
2406         u32 ring_size, rx_size, rx_space;
2407         u32 agg_factor = 0, agg_ring_size = 0;
2408
2409         /* 8 for CRC and VLAN */
2410         rx_size = SKB_DATA_ALIGN(bp->dev->mtu + ETH_HLEN + NET_IP_ALIGN + 8);
2411
2412         rx_space = rx_size + NET_SKB_PAD +
2413                 SKB_DATA_ALIGN(sizeof(struct skb_shared_info));
2414
2415         bp->rx_copy_thresh = BNXT_RX_COPY_THRESH;
2416         ring_size = bp->rx_ring_size;
2417         bp->rx_agg_ring_size = 0;
2418         bp->rx_agg_nr_pages = 0;
2419
2420         if (bp->flags & BNXT_FLAG_TPA)
2421                 agg_factor = min_t(u32, 4, 65536 / BNXT_RX_PAGE_SIZE);
2422
2423         bp->flags &= ~BNXT_FLAG_JUMBO;
2424         if (rx_space > PAGE_SIZE) {
2425                 u32 jumbo_factor;
2426
2427                 bp->flags |= BNXT_FLAG_JUMBO;
2428                 jumbo_factor = PAGE_ALIGN(bp->dev->mtu - 40) >> PAGE_SHIFT;
2429                 if (jumbo_factor > agg_factor)
2430                         agg_factor = jumbo_factor;
2431         }
2432         agg_ring_size = ring_size * agg_factor;
2433
2434         if (agg_ring_size) {
2435                 bp->rx_agg_nr_pages = bnxt_calc_nr_ring_pages(agg_ring_size,
2436                                                         RX_DESC_CNT);
2437                 if (bp->rx_agg_nr_pages > MAX_RX_AGG_PAGES) {
2438                         u32 tmp = agg_ring_size;
2439
2440                         bp->rx_agg_nr_pages = MAX_RX_AGG_PAGES;
2441                         agg_ring_size = MAX_RX_AGG_PAGES * RX_DESC_CNT - 1;
2442                         netdev_warn(bp->dev, "rx agg ring size %d reduced to %d.\n",
2443                                     tmp, agg_ring_size);
2444                 }
2445                 bp->rx_agg_ring_size = agg_ring_size;
2446                 bp->rx_agg_ring_mask = (bp->rx_agg_nr_pages * RX_DESC_CNT) - 1;
2447                 rx_size = SKB_DATA_ALIGN(BNXT_RX_COPY_THRESH + NET_IP_ALIGN);
2448                 rx_space = rx_size + NET_SKB_PAD +
2449                         SKB_DATA_ALIGN(sizeof(struct skb_shared_info));
2450         }
2451
2452         bp->rx_buf_use_size = rx_size;
2453         bp->rx_buf_size = rx_space;
2454
2455         bp->rx_nr_pages = bnxt_calc_nr_ring_pages(ring_size, RX_DESC_CNT);
2456         bp->rx_ring_mask = (bp->rx_nr_pages * RX_DESC_CNT) - 1;
2457
2458         ring_size = bp->tx_ring_size;
2459         bp->tx_nr_pages = bnxt_calc_nr_ring_pages(ring_size, TX_DESC_CNT);
2460         bp->tx_ring_mask = (bp->tx_nr_pages * TX_DESC_CNT) - 1;
2461
2462         ring_size = bp->rx_ring_size * (2 + agg_factor) + bp->tx_ring_size;
2463         bp->cp_ring_size = ring_size;
2464
2465         bp->cp_nr_pages = bnxt_calc_nr_ring_pages(ring_size, CP_DESC_CNT);
2466         if (bp->cp_nr_pages > MAX_CP_PAGES) {
2467                 bp->cp_nr_pages = MAX_CP_PAGES;
2468                 bp->cp_ring_size = MAX_CP_PAGES * CP_DESC_CNT - 1;
2469                 netdev_warn(bp->dev, "completion ring size %d reduced to %d.\n",
2470                             ring_size, bp->cp_ring_size);
2471         }
2472         bp->cp_bit = bp->cp_nr_pages * CP_DESC_CNT;
2473         bp->cp_ring_mask = bp->cp_bit - 1;
2474 }
2475
2476 static void bnxt_free_vnic_attributes(struct bnxt *bp)
2477 {
2478         int i;
2479         struct bnxt_vnic_info *vnic;
2480         struct pci_dev *pdev = bp->pdev;
2481
2482         if (!bp->vnic_info)
2483                 return;
2484
2485         for (i = 0; i < bp->nr_vnics; i++) {
2486                 vnic = &bp->vnic_info[i];
2487
2488                 kfree(vnic->fw_grp_ids);
2489                 vnic->fw_grp_ids = NULL;
2490
2491                 kfree(vnic->uc_list);
2492                 vnic->uc_list = NULL;
2493
2494                 if (vnic->mc_list) {
2495                         dma_free_coherent(&pdev->dev, vnic->mc_list_size,
2496                                           vnic->mc_list, vnic->mc_list_mapping);
2497                         vnic->mc_list = NULL;
2498                 }
2499
2500                 if (vnic->rss_table) {
2501                         dma_free_coherent(&pdev->dev, PAGE_SIZE,
2502                                           vnic->rss_table,
2503                                           vnic->rss_table_dma_addr);
2504                         vnic->rss_table = NULL;
2505                 }
2506
2507                 vnic->rss_hash_key = NULL;
2508                 vnic->flags = 0;
2509         }
2510 }
2511
2512 static int bnxt_alloc_vnic_attributes(struct bnxt *bp)
2513 {
2514         int i, rc = 0, size;
2515         struct bnxt_vnic_info *vnic;
2516         struct pci_dev *pdev = bp->pdev;
2517         int max_rings;
2518
2519         for (i = 0; i < bp->nr_vnics; i++) {
2520                 vnic = &bp->vnic_info[i];
2521
2522                 if (vnic->flags & BNXT_VNIC_UCAST_FLAG) {
2523                         int mem_size = (BNXT_MAX_UC_ADDRS - 1) * ETH_ALEN;
2524
2525                         if (mem_size > 0) {
2526                                 vnic->uc_list = kmalloc(mem_size, GFP_KERNEL);
2527                                 if (!vnic->uc_list) {
2528                                         rc = -ENOMEM;
2529                                         goto out;
2530                                 }
2531                         }
2532                 }
2533
2534                 if (vnic->flags & BNXT_VNIC_MCAST_FLAG) {
2535                         vnic->mc_list_size = BNXT_MAX_MC_ADDRS * ETH_ALEN;
2536                         vnic->mc_list =
2537                                 dma_alloc_coherent(&pdev->dev,
2538                                                    vnic->mc_list_size,
2539                                                    &vnic->mc_list_mapping,
2540                                                    GFP_KERNEL);
2541                         if (!vnic->mc_list) {
2542                                 rc = -ENOMEM;
2543                                 goto out;
2544                         }
2545                 }
2546
2547                 if (vnic->flags & BNXT_VNIC_RSS_FLAG)
2548                         max_rings = bp->rx_nr_rings;
2549                 else
2550                         max_rings = 1;
2551
2552                 vnic->fw_grp_ids = kcalloc(max_rings, sizeof(u16), GFP_KERNEL);
2553                 if (!vnic->fw_grp_ids) {
2554                         rc = -ENOMEM;
2555                         goto out;
2556                 }
2557
2558                 /* Allocate rss table and hash key */
2559                 vnic->rss_table = dma_alloc_coherent(&pdev->dev, PAGE_SIZE,
2560                                                      &vnic->rss_table_dma_addr,
2561                                                      GFP_KERNEL);
2562                 if (!vnic->rss_table) {
2563                         rc = -ENOMEM;
2564                         goto out;
2565                 }
2566
2567                 size = L1_CACHE_ALIGN(HW_HASH_INDEX_SIZE * sizeof(u16));
2568
2569                 vnic->rss_hash_key = ((void *)vnic->rss_table) + size;
2570                 vnic->rss_hash_key_dma_addr = vnic->rss_table_dma_addr + size;
2571         }
2572         return 0;
2573
2574 out:
2575         return rc;
2576 }
2577
2578 static void bnxt_free_hwrm_resources(struct bnxt *bp)
2579 {
2580         struct pci_dev *pdev = bp->pdev;
2581
2582         dma_free_coherent(&pdev->dev, PAGE_SIZE, bp->hwrm_cmd_resp_addr,
2583                           bp->hwrm_cmd_resp_dma_addr);
2584
2585         bp->hwrm_cmd_resp_addr = NULL;
2586         if (bp->hwrm_dbg_resp_addr) {
2587                 dma_free_coherent(&pdev->dev, HWRM_DBG_REG_BUF_SIZE,
2588                                   bp->hwrm_dbg_resp_addr,
2589                                   bp->hwrm_dbg_resp_dma_addr);
2590
2591                 bp->hwrm_dbg_resp_addr = NULL;
2592         }
2593 }
2594
2595 static int bnxt_alloc_hwrm_resources(struct bnxt *bp)
2596 {
2597         struct pci_dev *pdev = bp->pdev;
2598
2599         bp->hwrm_cmd_resp_addr = dma_alloc_coherent(&pdev->dev, PAGE_SIZE,
2600                                                    &bp->hwrm_cmd_resp_dma_addr,
2601                                                    GFP_KERNEL);
2602         if (!bp->hwrm_cmd_resp_addr)
2603                 return -ENOMEM;
2604         bp->hwrm_dbg_resp_addr = dma_alloc_coherent(&pdev->dev,
2605                                                     HWRM_DBG_REG_BUF_SIZE,
2606                                                     &bp->hwrm_dbg_resp_dma_addr,
2607                                                     GFP_KERNEL);
2608         if (!bp->hwrm_dbg_resp_addr)
2609                 netdev_warn(bp->dev, "fail to alloc debug register dma mem\n");
2610
2611         return 0;
2612 }
2613
2614 static void bnxt_free_stats(struct bnxt *bp)
2615 {
2616         u32 size, i;
2617         struct pci_dev *pdev = bp->pdev;
2618
2619         if (bp->hw_rx_port_stats) {
2620                 dma_free_coherent(&pdev->dev, bp->hw_port_stats_size,
2621                                   bp->hw_rx_port_stats,
2622                                   bp->hw_rx_port_stats_map);
2623                 bp->hw_rx_port_stats = NULL;
2624                 bp->flags &= ~BNXT_FLAG_PORT_STATS;
2625         }
2626
2627         if (!bp->bnapi)
2628                 return;
2629
2630         size = sizeof(struct ctx_hw_stats);
2631
2632         for (i = 0; i < bp->cp_nr_rings; i++) {
2633                 struct bnxt_napi *bnapi = bp->bnapi[i];
2634                 struct bnxt_cp_ring_info *cpr = &bnapi->cp_ring;
2635
2636                 if (cpr->hw_stats) {
2637                         dma_free_coherent(&pdev->dev, size, cpr->hw_stats,
2638                                           cpr->hw_stats_map);
2639                         cpr->hw_stats = NULL;
2640                 }
2641         }
2642 }
2643
2644 static int bnxt_alloc_stats(struct bnxt *bp)
2645 {
2646         u32 size, i;
2647         struct pci_dev *pdev = bp->pdev;
2648
2649         size = sizeof(struct ctx_hw_stats);
2650
2651         for (i = 0; i < bp->cp_nr_rings; i++) {
2652                 struct bnxt_napi *bnapi = bp->bnapi[i];
2653                 struct bnxt_cp_ring_info *cpr = &bnapi->cp_ring;
2654
2655                 cpr->hw_stats = dma_alloc_coherent(&pdev->dev, size,
2656                                                    &cpr->hw_stats_map,
2657                                                    GFP_KERNEL);
2658                 if (!cpr->hw_stats)
2659                         return -ENOMEM;
2660
2661                 cpr->hw_stats_ctx_id = INVALID_STATS_CTX_ID;
2662         }
2663
2664         if (BNXT_PF(bp)) {
2665                 bp->hw_port_stats_size = sizeof(struct rx_port_stats) +
2666                                          sizeof(struct tx_port_stats) + 1024;
2667
2668                 bp->hw_rx_port_stats =
2669                         dma_alloc_coherent(&pdev->dev, bp->hw_port_stats_size,
2670                                            &bp->hw_rx_port_stats_map,
2671                                            GFP_KERNEL);
2672                 if (!bp->hw_rx_port_stats)
2673                         return -ENOMEM;
2674
2675                 bp->hw_tx_port_stats = (void *)(bp->hw_rx_port_stats + 1) +
2676                                        512;
2677                 bp->hw_tx_port_stats_map = bp->hw_rx_port_stats_map +
2678                                            sizeof(struct rx_port_stats) + 512;
2679                 bp->flags |= BNXT_FLAG_PORT_STATS;
2680         }
2681         return 0;
2682 }
2683
2684 static void bnxt_clear_ring_indices(struct bnxt *bp)
2685 {
2686         int i;
2687
2688         if (!bp->bnapi)
2689                 return;
2690
2691         for (i = 0; i < bp->cp_nr_rings; i++) {
2692                 struct bnxt_napi *bnapi = bp->bnapi[i];
2693                 struct bnxt_cp_ring_info *cpr;
2694                 struct bnxt_rx_ring_info *rxr;
2695                 struct bnxt_tx_ring_info *txr;
2696
2697                 if (!bnapi)
2698                         continue;
2699
2700                 cpr = &bnapi->cp_ring;
2701                 cpr->cp_raw_cons = 0;
2702
2703                 txr = bnapi->tx_ring;
2704                 if (txr) {
2705                         txr->tx_prod = 0;
2706                         txr->tx_cons = 0;
2707                 }
2708
2709                 rxr = bnapi->rx_ring;
2710                 if (rxr) {
2711                         rxr->rx_prod = 0;
2712                         rxr->rx_agg_prod = 0;
2713                         rxr->rx_sw_agg_prod = 0;
2714                         rxr->rx_next_cons = 0;
2715                 }
2716         }
2717 }
2718
2719 static void bnxt_free_ntp_fltrs(struct bnxt *bp, bool irq_reinit)
2720 {
2721 #ifdef CONFIG_RFS_ACCEL
2722         int i;
2723
2724         /* Under rtnl_lock and all our NAPIs have been disabled.  It's
2725          * safe to delete the hash table.
2726          */
2727         for (i = 0; i < BNXT_NTP_FLTR_HASH_SIZE; i++) {
2728                 struct hlist_head *head;
2729                 struct hlist_node *tmp;
2730                 struct bnxt_ntuple_filter *fltr;
2731
2732                 head = &bp->ntp_fltr_hash_tbl[i];
2733                 hlist_for_each_entry_safe(fltr, tmp, head, hash) {
2734                         hlist_del(&fltr->hash);
2735                         kfree(fltr);
2736                 }
2737         }
2738         if (irq_reinit) {
2739                 kfree(bp->ntp_fltr_bmap);
2740                 bp->ntp_fltr_bmap = NULL;
2741         }
2742         bp->ntp_fltr_count = 0;
2743 #endif
2744 }
2745
2746 static int bnxt_alloc_ntp_fltrs(struct bnxt *bp)
2747 {
2748 #ifdef CONFIG_RFS_ACCEL
2749         int i, rc = 0;
2750
2751         if (!(bp->flags & BNXT_FLAG_RFS))
2752                 return 0;
2753
2754         for (i = 0; i < BNXT_NTP_FLTR_HASH_SIZE; i++)
2755                 INIT_HLIST_HEAD(&bp->ntp_fltr_hash_tbl[i]);
2756
2757         bp->ntp_fltr_count = 0;
2758         bp->ntp_fltr_bmap = kzalloc(BITS_TO_LONGS(BNXT_NTP_FLTR_MAX_FLTR),
2759                                     GFP_KERNEL);
2760
2761         if (!bp->ntp_fltr_bmap)
2762                 rc = -ENOMEM;
2763
2764         return rc;
2765 #else
2766         return 0;
2767 #endif
2768 }
2769
2770 static void bnxt_free_mem(struct bnxt *bp, bool irq_re_init)
2771 {
2772         bnxt_free_vnic_attributes(bp);
2773         bnxt_free_tx_rings(bp);
2774         bnxt_free_rx_rings(bp);
2775         bnxt_free_cp_rings(bp);
2776         bnxt_free_ntp_fltrs(bp, irq_re_init);
2777         if (irq_re_init) {
2778                 bnxt_free_stats(bp);
2779                 bnxt_free_ring_grps(bp);
2780                 bnxt_free_vnics(bp);
2781                 kfree(bp->tx_ring);
2782                 bp->tx_ring = NULL;
2783                 kfree(bp->rx_ring);
2784                 bp->rx_ring = NULL;
2785                 kfree(bp->bnapi);
2786                 bp->bnapi = NULL;
2787         } else {
2788                 bnxt_clear_ring_indices(bp);
2789         }
2790 }
2791
2792 static int bnxt_alloc_mem(struct bnxt *bp, bool irq_re_init)
2793 {
2794         int i, j, rc, size, arr_size;
2795         void *bnapi;
2796
2797         if (irq_re_init) {
2798                 /* Allocate bnapi mem pointer array and mem block for
2799                  * all queues
2800                  */
2801                 arr_size = L1_CACHE_ALIGN(sizeof(struct bnxt_napi *) *
2802                                 bp->cp_nr_rings);
2803                 size = L1_CACHE_ALIGN(sizeof(struct bnxt_napi));
2804                 bnapi = kzalloc(arr_size + size * bp->cp_nr_rings, GFP_KERNEL);
2805                 if (!bnapi)
2806                         return -ENOMEM;
2807
2808                 bp->bnapi = bnapi;
2809                 bnapi += arr_size;
2810                 for (i = 0; i < bp->cp_nr_rings; i++, bnapi += size) {
2811                         bp->bnapi[i] = bnapi;
2812                         bp->bnapi[i]->index = i;
2813                         bp->bnapi[i]->bp = bp;
2814                 }
2815
2816                 bp->rx_ring = kcalloc(bp->rx_nr_rings,
2817                                       sizeof(struct bnxt_rx_ring_info),
2818                                       GFP_KERNEL);
2819                 if (!bp->rx_ring)
2820                         return -ENOMEM;
2821
2822                 for (i = 0; i < bp->rx_nr_rings; i++) {
2823                         bp->rx_ring[i].bnapi = bp->bnapi[i];
2824                         bp->bnapi[i]->rx_ring = &bp->rx_ring[i];
2825                 }
2826
2827                 bp->tx_ring = kcalloc(bp->tx_nr_rings,
2828                                       sizeof(struct bnxt_tx_ring_info),
2829                                       GFP_KERNEL);
2830                 if (!bp->tx_ring)
2831                         return -ENOMEM;
2832
2833                 if (bp->flags & BNXT_FLAG_SHARED_RINGS)
2834                         j = 0;
2835                 else
2836                         j = bp->rx_nr_rings;
2837
2838                 for (i = 0; i < bp->tx_nr_rings; i++, j++) {
2839                         bp->tx_ring[i].bnapi = bp->bnapi[j];
2840                         bp->bnapi[j]->tx_ring = &bp->tx_ring[i];
2841                 }
2842
2843                 rc = bnxt_alloc_stats(bp);
2844                 if (rc)
2845                         goto alloc_mem_err;
2846
2847                 rc = bnxt_alloc_ntp_fltrs(bp);
2848                 if (rc)
2849                         goto alloc_mem_err;
2850
2851                 rc = bnxt_alloc_vnics(bp);
2852                 if (rc)
2853                         goto alloc_mem_err;
2854         }
2855
2856         bnxt_init_ring_struct(bp);
2857
2858         rc = bnxt_alloc_rx_rings(bp);
2859         if (rc)
2860                 goto alloc_mem_err;
2861
2862         rc = bnxt_alloc_tx_rings(bp);
2863         if (rc)
2864                 goto alloc_mem_err;
2865
2866         rc = bnxt_alloc_cp_rings(bp);
2867         if (rc)
2868                 goto alloc_mem_err;
2869
2870         bp->vnic_info[0].flags |= BNXT_VNIC_RSS_FLAG | BNXT_VNIC_MCAST_FLAG |
2871                                   BNXT_VNIC_UCAST_FLAG;
2872         rc = bnxt_alloc_vnic_attributes(bp);
2873         if (rc)
2874                 goto alloc_mem_err;
2875         return 0;
2876
2877 alloc_mem_err:
2878         bnxt_free_mem(bp, true);
2879         return rc;
2880 }
2881
2882 void bnxt_hwrm_cmd_hdr_init(struct bnxt *bp, void *request, u16 req_type,
2883                             u16 cmpl_ring, u16 target_id)
2884 {
2885         struct input *req = request;
2886
2887         req->req_type = cpu_to_le16(req_type);
2888         req->cmpl_ring = cpu_to_le16(cmpl_ring);
2889         req->target_id = cpu_to_le16(target_id);
2890         req->resp_addr = cpu_to_le64(bp->hwrm_cmd_resp_dma_addr);
2891 }
2892
2893 static int bnxt_hwrm_do_send_msg(struct bnxt *bp, void *msg, u32 msg_len,
2894                                  int timeout, bool silent)
2895 {
2896         int i, intr_process, rc, tmo_count;
2897         struct input *req = msg;
2898         u32 *data = msg;
2899         __le32 *resp_len, *valid;
2900         u16 cp_ring_id, len = 0;
2901         struct hwrm_err_output *resp = bp->hwrm_cmd_resp_addr;
2902
2903         req->seq_id = cpu_to_le16(bp->hwrm_cmd_seq++);
2904         memset(resp, 0, PAGE_SIZE);
2905         cp_ring_id = le16_to_cpu(req->cmpl_ring);
2906         intr_process = (cp_ring_id == INVALID_HW_RING_ID) ? 0 : 1;
2907
2908         /* Write request msg to hwrm channel */
2909         __iowrite32_copy(bp->bar0, data, msg_len / 4);
2910
2911         for (i = msg_len; i < BNXT_HWRM_MAX_REQ_LEN; i += 4)
2912                 writel(0, bp->bar0 + i);
2913
2914         /* currently supports only one outstanding message */
2915         if (intr_process)
2916                 bp->hwrm_intr_seq_id = le16_to_cpu(req->seq_id);
2917
2918         /* Ring channel doorbell */
2919         writel(1, bp->bar0 + 0x100);
2920
2921         if (!timeout)
2922                 timeout = DFLT_HWRM_CMD_TIMEOUT;
2923
2924         i = 0;
2925         tmo_count = timeout * 40;
2926         if (intr_process) {
2927                 /* Wait until hwrm response cmpl interrupt is processed */
2928                 while (bp->hwrm_intr_seq_id != HWRM_SEQ_ID_INVALID &&
2929                        i++ < tmo_count) {
2930                         usleep_range(25, 40);
2931                 }
2932
2933                 if (bp->hwrm_intr_seq_id != HWRM_SEQ_ID_INVALID) {
2934                         netdev_err(bp->dev, "Resp cmpl intr err msg: 0x%x\n",
2935                                    le16_to_cpu(req->req_type));
2936                         return -1;
2937                 }
2938         } else {
2939                 /* Check if response len is updated */
2940                 resp_len = bp->hwrm_cmd_resp_addr + HWRM_RESP_LEN_OFFSET;
2941                 for (i = 0; i < tmo_count; i++) {
2942                         len = (le32_to_cpu(*resp_len) & HWRM_RESP_LEN_MASK) >>
2943                               HWRM_RESP_LEN_SFT;
2944                         if (len)
2945                                 break;
2946                         usleep_range(25, 40);
2947                 }
2948
2949                 if (i >= tmo_count) {
2950                         netdev_err(bp->dev, "Error (timeout: %d) msg {0x%x 0x%x} len:%d\n",
2951                                    timeout, le16_to_cpu(req->req_type),
2952                                    le16_to_cpu(req->seq_id), len);
2953                         return -1;
2954                 }
2955
2956                 /* Last word of resp contains valid bit */
2957                 valid = bp->hwrm_cmd_resp_addr + len - 4;
2958                 for (i = 0; i < 5; i++) {
2959                         if (le32_to_cpu(*valid) & HWRM_RESP_VALID_MASK)
2960                                 break;
2961                         udelay(1);
2962                 }
2963
2964                 if (i >= 5) {
2965                         netdev_err(bp->dev, "Error (timeout: %d) msg {0x%x 0x%x} len:%d v:%d\n",
2966                                    timeout, le16_to_cpu(req->req_type),
2967                                    le16_to_cpu(req->seq_id), len, *valid);
2968                         return -1;
2969                 }
2970         }
2971
2972         rc = le16_to_cpu(resp->error_code);
2973         if (rc && !silent)
2974                 netdev_err(bp->dev, "hwrm req_type 0x%x seq id 0x%x error 0x%x\n",
2975                            le16_to_cpu(resp->req_type),
2976                            le16_to_cpu(resp->seq_id), rc);
2977         return rc;
2978 }
2979
2980 int _hwrm_send_message(struct bnxt *bp, void *msg, u32 msg_len, int timeout)
2981 {
2982         return bnxt_hwrm_do_send_msg(bp, msg, msg_len, timeout, false);
2983 }
2984
2985 int hwrm_send_message(struct bnxt *bp, void *msg, u32 msg_len, int timeout)
2986 {
2987         int rc;
2988
2989         mutex_lock(&bp->hwrm_cmd_lock);
2990         rc = _hwrm_send_message(bp, msg, msg_len, timeout);
2991         mutex_unlock(&bp->hwrm_cmd_lock);
2992         return rc;
2993 }
2994
2995 int hwrm_send_message_silent(struct bnxt *bp, void *msg, u32 msg_len,
2996                              int timeout)
2997 {
2998         int rc;
2999
3000         mutex_lock(&bp->hwrm_cmd_lock);
3001         rc = bnxt_hwrm_do_send_msg(bp, msg, msg_len, timeout, true);
3002         mutex_unlock(&bp->hwrm_cmd_lock);
3003         return rc;
3004 }
3005
3006 static int bnxt_hwrm_func_drv_rgtr(struct bnxt *bp)
3007 {
3008         struct hwrm_func_drv_rgtr_input req = {0};
3009         int i;
3010         DECLARE_BITMAP(async_events_bmap, 256);
3011         u32 *events = (u32 *)async_events_bmap;
3012
3013         bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_FUNC_DRV_RGTR, -1, -1);
3014
3015         req.enables =
3016                 cpu_to_le32(FUNC_DRV_RGTR_REQ_ENABLES_OS_TYPE |
3017                             FUNC_DRV_RGTR_REQ_ENABLES_VER |
3018                             FUNC_DRV_RGTR_REQ_ENABLES_ASYNC_EVENT_FWD);
3019
3020         memset(async_events_bmap, 0, sizeof(async_events_bmap));
3021         for (i = 0; i < ARRAY_SIZE(bnxt_async_events_arr); i++)
3022                 __set_bit(bnxt_async_events_arr[i], async_events_bmap);
3023
3024         for (i = 0; i < 8; i++)
3025                 req.async_event_fwd[i] |= cpu_to_le32(events[i]);
3026
3027         req.os_type = cpu_to_le16(FUNC_DRV_RGTR_REQ_OS_TYPE_LINUX);
3028         req.ver_maj = DRV_VER_MAJ;
3029         req.ver_min = DRV_VER_MIN;
3030         req.ver_upd = DRV_VER_UPD;
3031
3032         if (BNXT_PF(bp)) {
3033                 DECLARE_BITMAP(vf_req_snif_bmap, 256);
3034                 u32 *data = (u32 *)vf_req_snif_bmap;
3035
3036                 memset(vf_req_snif_bmap, 0, sizeof(vf_req_snif_bmap));
3037                 for (i = 0; i < ARRAY_SIZE(bnxt_vf_req_snif); i++)
3038                         __set_bit(bnxt_vf_req_snif[i], vf_req_snif_bmap);
3039
3040                 for (i = 0; i < 8; i++)
3041                         req.vf_req_fwd[i] = cpu_to_le32(data[i]);
3042
3043                 req.enables |=
3044                         cpu_to_le32(FUNC_DRV_RGTR_REQ_ENABLES_VF_REQ_FWD);
3045         }
3046
3047         return hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT);
3048 }
3049
3050 static int bnxt_hwrm_func_drv_unrgtr(struct bnxt *bp)
3051 {
3052         struct hwrm_func_drv_unrgtr_input req = {0};
3053
3054         bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_FUNC_DRV_UNRGTR, -1, -1);
3055         return hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT);
3056 }
3057
3058 static int bnxt_hwrm_tunnel_dst_port_free(struct bnxt *bp, u8 tunnel_type)
3059 {
3060         u32 rc = 0;
3061         struct hwrm_tunnel_dst_port_free_input req = {0};
3062
3063         bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_TUNNEL_DST_PORT_FREE, -1, -1);
3064         req.tunnel_type = tunnel_type;
3065
3066         switch (tunnel_type) {
3067         case TUNNEL_DST_PORT_FREE_REQ_TUNNEL_TYPE_VXLAN:
3068                 req.tunnel_dst_port_id = bp->vxlan_fw_dst_port_id;
3069                 break;
3070         case TUNNEL_DST_PORT_FREE_REQ_TUNNEL_TYPE_GENEVE:
3071                 req.tunnel_dst_port_id = bp->nge_fw_dst_port_id;
3072                 break;
3073         default:
3074                 break;
3075         }
3076
3077         rc = hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT);
3078         if (rc)
3079                 netdev_err(bp->dev, "hwrm_tunnel_dst_port_free failed. rc:%d\n",
3080                            rc);
3081         return rc;
3082 }
3083
3084 static int bnxt_hwrm_tunnel_dst_port_alloc(struct bnxt *bp, __be16 port,
3085                                            u8 tunnel_type)
3086 {
3087         u32 rc = 0;
3088         struct hwrm_tunnel_dst_port_alloc_input req = {0};
3089         struct hwrm_tunnel_dst_port_alloc_output *resp = bp->hwrm_cmd_resp_addr;
3090
3091         bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_TUNNEL_DST_PORT_ALLOC, -1, -1);
3092
3093         req.tunnel_type = tunnel_type;
3094         req.tunnel_dst_port_val = port;
3095
3096         mutex_lock(&bp->hwrm_cmd_lock);
3097         rc = _hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT);
3098         if (rc) {
3099                 netdev_err(bp->dev, "hwrm_tunnel_dst_port_alloc failed. rc:%d\n",
3100                            rc);
3101                 goto err_out;
3102         }
3103
3104         if (tunnel_type & TUNNEL_DST_PORT_ALLOC_REQ_TUNNEL_TYPE_VXLAN)
3105                 bp->vxlan_fw_dst_port_id = resp->tunnel_dst_port_id;
3106
3107         else if (tunnel_type & TUNNEL_DST_PORT_ALLOC_REQ_TUNNEL_TYPE_GENEVE)
3108                 bp->nge_fw_dst_port_id = resp->tunnel_dst_port_id;
3109 err_out:
3110         mutex_unlock(&bp->hwrm_cmd_lock);
3111         return rc;
3112 }
3113
3114 static int bnxt_hwrm_cfa_l2_set_rx_mask(struct bnxt *bp, u16 vnic_id)
3115 {
3116         struct hwrm_cfa_l2_set_rx_mask_input req = {0};
3117         struct bnxt_vnic_info *vnic = &bp->vnic_info[vnic_id];
3118
3119         bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_CFA_L2_SET_RX_MASK, -1, -1);
3120         req.vnic_id = cpu_to_le32(vnic->fw_vnic_id);
3121
3122         req.num_mc_entries = cpu_to_le32(vnic->mc_list_count);
3123         req.mc_tbl_addr = cpu_to_le64(vnic->mc_list_mapping);
3124         req.mask = cpu_to_le32(vnic->rx_mask);
3125         return hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT);
3126 }
3127
3128 #ifdef CONFIG_RFS_ACCEL
3129 static int bnxt_hwrm_cfa_ntuple_filter_free(struct bnxt *bp,
3130                                             struct bnxt_ntuple_filter *fltr)
3131 {
3132         struct hwrm_cfa_ntuple_filter_free_input req = {0};
3133
3134         bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_CFA_NTUPLE_FILTER_FREE, -1, -1);
3135         req.ntuple_filter_id = fltr->filter_id;
3136         return hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT);
3137 }
3138
3139 #define BNXT_NTP_FLTR_FLAGS                                     \
3140         (CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_L2_FILTER_ID |     \
3141          CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_ETHERTYPE |        \
3142          CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_SRC_MACADDR |      \
3143          CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_IPADDR_TYPE |      \
3144          CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_SRC_IPADDR |       \
3145          CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_SRC_IPADDR_MASK |  \
3146          CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_DST_IPADDR |       \
3147          CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_DST_IPADDR_MASK |  \
3148          CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_IP_PROTOCOL |      \
3149          CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_SRC_PORT |         \
3150          CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_SRC_PORT_MASK |    \
3151          CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_DST_PORT |         \
3152          CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_DST_PORT_MASK |    \
3153          CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_DST_ID)
3154
3155 static int bnxt_hwrm_cfa_ntuple_filter_alloc(struct bnxt *bp,
3156                                              struct bnxt_ntuple_filter *fltr)
3157 {
3158         int rc = 0;
3159         struct hwrm_cfa_ntuple_filter_alloc_input req = {0};
3160         struct hwrm_cfa_ntuple_filter_alloc_output *resp =
3161                 bp->hwrm_cmd_resp_addr;
3162         struct flow_keys *keys = &fltr->fkeys;
3163         struct bnxt_vnic_info *vnic = &bp->vnic_info[fltr->rxq + 1];
3164
3165         bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_CFA_NTUPLE_FILTER_ALLOC, -1, -1);
3166         req.l2_filter_id = bp->vnic_info[0].fw_l2_filter_id[0];
3167
3168         req.enables = cpu_to_le32(BNXT_NTP_FLTR_FLAGS);
3169
3170         req.ethertype = htons(ETH_P_IP);
3171         memcpy(req.src_macaddr, fltr->src_mac_addr, ETH_ALEN);
3172         req.ip_addr_type = CFA_NTUPLE_FILTER_ALLOC_REQ_IP_ADDR_TYPE_IPV4;
3173         req.ip_protocol = keys->basic.ip_proto;
3174
3175         req.src_ipaddr[0] = keys->addrs.v4addrs.src;
3176         req.src_ipaddr_mask[0] = cpu_to_be32(0xffffffff);
3177         req.dst_ipaddr[0] = keys->addrs.v4addrs.dst;
3178         req.dst_ipaddr_mask[0] = cpu_to_be32(0xffffffff);
3179
3180         req.src_port = keys->ports.src;
3181         req.src_port_mask = cpu_to_be16(0xffff);
3182         req.dst_port = keys->ports.dst;
3183         req.dst_port_mask = cpu_to_be16(0xffff);
3184
3185         req.dst_id = cpu_to_le16(vnic->fw_vnic_id);
3186         mutex_lock(&bp->hwrm_cmd_lock);
3187         rc = _hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT);
3188         if (!rc)
3189                 fltr->filter_id = resp->ntuple_filter_id;
3190         mutex_unlock(&bp->hwrm_cmd_lock);
3191         return rc;
3192 }
3193 #endif
3194
3195 static int bnxt_hwrm_set_vnic_filter(struct bnxt *bp, u16 vnic_id, u16 idx,
3196                                      u8 *mac_addr)
3197 {
3198         u32 rc = 0;
3199         struct hwrm_cfa_l2_filter_alloc_input req = {0};
3200         struct hwrm_cfa_l2_filter_alloc_output *resp = bp->hwrm_cmd_resp_addr;
3201
3202         bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_CFA_L2_FILTER_ALLOC, -1, -1);
3203         req.flags = cpu_to_le32(CFA_L2_FILTER_ALLOC_REQ_FLAGS_PATH_RX |
3204                                 CFA_L2_FILTER_ALLOC_REQ_FLAGS_OUTERMOST);
3205         req.dst_id = cpu_to_le16(bp->vnic_info[vnic_id].fw_vnic_id);
3206         req.enables =
3207                 cpu_to_le32(CFA_L2_FILTER_ALLOC_REQ_ENABLES_L2_ADDR |
3208                             CFA_L2_FILTER_ALLOC_REQ_ENABLES_DST_ID |
3209                             CFA_L2_FILTER_ALLOC_REQ_ENABLES_L2_ADDR_MASK);
3210         memcpy(req.l2_addr, mac_addr, ETH_ALEN);
3211         req.l2_addr_mask[0] = 0xff;
3212         req.l2_addr_mask[1] = 0xff;
3213         req.l2_addr_mask[2] = 0xff;
3214         req.l2_addr_mask[3] = 0xff;
3215         req.l2_addr_mask[4] = 0xff;
3216         req.l2_addr_mask[5] = 0xff;
3217
3218         mutex_lock(&bp->hwrm_cmd_lock);
3219         rc = _hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT);
3220         if (!rc)
3221                 bp->vnic_info[vnic_id].fw_l2_filter_id[idx] =
3222                                                         resp->l2_filter_id;
3223         mutex_unlock(&bp->hwrm_cmd_lock);
3224         return rc;
3225 }
3226
3227 static int bnxt_hwrm_clear_vnic_filter(struct bnxt *bp)
3228 {
3229         u16 i, j, num_of_vnics = 1; /* only vnic 0 supported */
3230         int rc = 0;
3231
3232         /* Any associated ntuple filters will also be cleared by firmware. */
3233         mutex_lock(&bp->hwrm_cmd_lock);
3234         for (i = 0; i < num_of_vnics; i++) {
3235                 struct bnxt_vnic_info *vnic = &bp->vnic_info[i];
3236
3237                 for (j = 0; j < vnic->uc_filter_count; j++) {
3238                         struct hwrm_cfa_l2_filter_free_input req = {0};
3239
3240                         bnxt_hwrm_cmd_hdr_init(bp, &req,
3241                                                HWRM_CFA_L2_FILTER_FREE, -1, -1);
3242
3243                         req.l2_filter_id = vnic->fw_l2_filter_id[j];
3244
3245                         rc = _hwrm_send_message(bp, &req, sizeof(req),
3246                                                 HWRM_CMD_TIMEOUT);
3247                 }
3248                 vnic->uc_filter_count = 0;
3249         }
3250         mutex_unlock(&bp->hwrm_cmd_lock);
3251
3252         return rc;
3253 }
3254
3255 static int bnxt_hwrm_vnic_set_tpa(struct bnxt *bp, u16 vnic_id, u32 tpa_flags)
3256 {
3257         struct bnxt_vnic_info *vnic = &bp->vnic_info[vnic_id];
3258         struct hwrm_vnic_tpa_cfg_input req = {0};
3259
3260         bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_VNIC_TPA_CFG, -1, -1);
3261
3262         if (tpa_flags) {
3263                 u16 mss = bp->dev->mtu - 40;
3264                 u32 nsegs, n, segs = 0, flags;
3265
3266                 flags = VNIC_TPA_CFG_REQ_FLAGS_TPA |
3267                         VNIC_TPA_CFG_REQ_FLAGS_ENCAP_TPA |
3268                         VNIC_TPA_CFG_REQ_FLAGS_RSC_WND_UPDATE |
3269                         VNIC_TPA_CFG_REQ_FLAGS_AGG_WITH_ECN |
3270                         VNIC_TPA_CFG_REQ_FLAGS_AGG_WITH_SAME_GRE_SEQ;
3271                 if (tpa_flags & BNXT_FLAG_GRO)
3272                         flags |= VNIC_TPA_CFG_REQ_FLAGS_GRO;
3273
3274                 req.flags = cpu_to_le32(flags);
3275
3276                 req.enables =
3277                         cpu_to_le32(VNIC_TPA_CFG_REQ_ENABLES_MAX_AGG_SEGS |
3278                                     VNIC_TPA_CFG_REQ_ENABLES_MAX_AGGS |
3279                                     VNIC_TPA_CFG_REQ_ENABLES_MIN_AGG_LEN);
3280
3281                 /* Number of segs are log2 units, and first packet is not
3282                  * included as part of this units.
3283                  */
3284                 if (mss <= BNXT_RX_PAGE_SIZE) {
3285                         n = BNXT_RX_PAGE_SIZE / mss;
3286                         nsegs = (MAX_SKB_FRAGS - 1) * n;
3287                 } else {
3288                         n = mss / BNXT_RX_PAGE_SIZE;
3289                         if (mss & (BNXT_RX_PAGE_SIZE - 1))
3290                                 n++;
3291                         nsegs = (MAX_SKB_FRAGS - n) / n;
3292                 }
3293
3294                 segs = ilog2(nsegs);
3295                 req.max_agg_segs = cpu_to_le16(segs);
3296                 req.max_aggs = cpu_to_le16(VNIC_TPA_CFG_REQ_MAX_AGGS_MAX);
3297
3298                 req.min_agg_len = cpu_to_le32(512);
3299         }
3300         req.vnic_id = cpu_to_le16(vnic->fw_vnic_id);
3301
3302         return hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT);
3303 }
3304
3305 static int bnxt_hwrm_vnic_set_rss(struct bnxt *bp, u16 vnic_id, bool set_rss)
3306 {
3307         u32 i, j, max_rings;
3308         struct bnxt_vnic_info *vnic = &bp->vnic_info[vnic_id];
3309         struct hwrm_vnic_rss_cfg_input req = {0};
3310
3311         if (vnic->fw_rss_cos_lb_ctx == INVALID_HW_RING_ID)
3312                 return 0;
3313
3314         bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_VNIC_RSS_CFG, -1, -1);
3315         if (set_rss) {
3316                 vnic->hash_type = BNXT_RSS_HASH_TYPE_FLAG_IPV4 |
3317                                  BNXT_RSS_HASH_TYPE_FLAG_TCP_IPV4 |
3318                                  BNXT_RSS_HASH_TYPE_FLAG_IPV6 |
3319                                  BNXT_RSS_HASH_TYPE_FLAG_TCP_IPV6;
3320
3321                 req.hash_type = cpu_to_le32(vnic->hash_type);
3322
3323                 if (vnic->flags & BNXT_VNIC_RSS_FLAG)
3324                         max_rings = bp->rx_nr_rings;
3325                 else
3326                         max_rings = 1;
3327
3328                 /* Fill the RSS indirection table with ring group ids */
3329                 for (i = 0, j = 0; i < HW_HASH_INDEX_SIZE; i++, j++) {
3330                         if (j == max_rings)
3331                                 j = 0;
3332                         vnic->rss_table[i] = cpu_to_le16(vnic->fw_grp_ids[j]);
3333                 }
3334
3335                 req.ring_grp_tbl_addr = cpu_to_le64(vnic->rss_table_dma_addr);
3336                 req.hash_key_tbl_addr =
3337                         cpu_to_le64(vnic->rss_hash_key_dma_addr);
3338         }
3339         req.rss_ctx_idx = cpu_to_le16(vnic->fw_rss_cos_lb_ctx);
3340         return hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT);
3341 }
3342
3343 static int bnxt_hwrm_vnic_set_hds(struct bnxt *bp, u16 vnic_id)
3344 {
3345         struct bnxt_vnic_info *vnic = &bp->vnic_info[vnic_id];
3346         struct hwrm_vnic_plcmodes_cfg_input req = {0};
3347
3348         bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_VNIC_PLCMODES_CFG, -1, -1);
3349         req.flags = cpu_to_le32(VNIC_PLCMODES_CFG_REQ_FLAGS_JUMBO_PLACEMENT |
3350                                 VNIC_PLCMODES_CFG_REQ_FLAGS_HDS_IPV4 |
3351                                 VNIC_PLCMODES_CFG_REQ_FLAGS_HDS_IPV6);
3352         req.enables =
3353                 cpu_to_le32(VNIC_PLCMODES_CFG_REQ_ENABLES_JUMBO_THRESH_VALID |
3354                             VNIC_PLCMODES_CFG_REQ_ENABLES_HDS_THRESHOLD_VALID);
3355         /* thresholds not implemented in firmware yet */
3356         req.jumbo_thresh = cpu_to_le16(bp->rx_copy_thresh);
3357         req.hds_threshold = cpu_to_le16(bp->rx_copy_thresh);
3358         req.vnic_id = cpu_to_le32(vnic->fw_vnic_id);
3359         return hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT);
3360 }
3361
3362 static void bnxt_hwrm_vnic_ctx_free_one(struct bnxt *bp, u16 vnic_id)
3363 {
3364         struct hwrm_vnic_rss_cos_lb_ctx_free_input req = {0};
3365
3366         bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_VNIC_RSS_COS_LB_CTX_FREE, -1, -1);
3367         req.rss_cos_lb_ctx_id =
3368                 cpu_to_le16(bp->vnic_info[vnic_id].fw_rss_cos_lb_ctx);
3369
3370         hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT);
3371         bp->vnic_info[vnic_id].fw_rss_cos_lb_ctx = INVALID_HW_RING_ID;
3372 }
3373
3374 static void bnxt_hwrm_vnic_ctx_free(struct bnxt *bp)
3375 {
3376         int i;
3377
3378         for (i = 0; i < bp->nr_vnics; i++) {
3379                 struct bnxt_vnic_info *vnic = &bp->vnic_info[i];
3380
3381                 if (vnic->fw_rss_cos_lb_ctx != INVALID_HW_RING_ID)
3382                         bnxt_hwrm_vnic_ctx_free_one(bp, i);
3383         }
3384         bp->rsscos_nr_ctxs = 0;
3385 }
3386
3387 static int bnxt_hwrm_vnic_ctx_alloc(struct bnxt *bp, u16 vnic_id)
3388 {
3389         int rc;
3390         struct hwrm_vnic_rss_cos_lb_ctx_alloc_input req = {0};
3391         struct hwrm_vnic_rss_cos_lb_ctx_alloc_output *resp =
3392                                                 bp->hwrm_cmd_resp_addr;
3393
3394         bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_VNIC_RSS_COS_LB_CTX_ALLOC, -1,
3395                                -1);
3396
3397         mutex_lock(&bp->hwrm_cmd_lock);
3398         rc = _hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT);
3399         if (!rc)
3400                 bp->vnic_info[vnic_id].fw_rss_cos_lb_ctx =
3401                         le16_to_cpu(resp->rss_cos_lb_ctx_id);
3402         mutex_unlock(&bp->hwrm_cmd_lock);
3403
3404         return rc;
3405 }
3406
3407 static int bnxt_hwrm_vnic_cfg(struct bnxt *bp, u16 vnic_id)
3408 {
3409         unsigned int ring = 0, grp_idx;
3410         struct bnxt_vnic_info *vnic = &bp->vnic_info[vnic_id];
3411         struct hwrm_vnic_cfg_input req = {0};
3412         u16 def_vlan = 0;
3413
3414         bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_VNIC_CFG, -1, -1);
3415         /* Only RSS support for now TBD: COS & LB */
3416         req.enables = cpu_to_le32(VNIC_CFG_REQ_ENABLES_DFLT_RING_GRP |
3417                                   VNIC_CFG_REQ_ENABLES_RSS_RULE);
3418         req.rss_rule = cpu_to_le16(vnic->fw_rss_cos_lb_ctx);
3419         req.cos_rule = cpu_to_le16(0xffff);
3420         if (vnic->flags & BNXT_VNIC_RSS_FLAG)
3421                 ring = 0;
3422         else if (vnic->flags & BNXT_VNIC_RFS_FLAG)
3423                 ring = vnic_id - 1;
3424
3425         grp_idx = bp->rx_ring[ring].bnapi->index;
3426         req.vnic_id = cpu_to_le16(vnic->fw_vnic_id);
3427         req.dflt_ring_grp = cpu_to_le16(bp->grp_info[grp_idx].fw_grp_id);
3428
3429         req.lb_rule = cpu_to_le16(0xffff);
3430         req.mru = cpu_to_le16(bp->dev->mtu + ETH_HLEN + ETH_FCS_LEN +
3431                               VLAN_HLEN);
3432
3433 #ifdef CONFIG_BNXT_SRIOV
3434         if (BNXT_VF(bp))
3435                 def_vlan = bp->vf.vlan;
3436 #endif
3437         if ((bp->flags & BNXT_FLAG_STRIP_VLAN) || def_vlan)
3438                 req.flags |= cpu_to_le32(VNIC_CFG_REQ_FLAGS_VLAN_STRIP_MODE);
3439
3440         return hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT);
3441 }
3442
3443 static int bnxt_hwrm_vnic_free_one(struct bnxt *bp, u16 vnic_id)
3444 {
3445         u32 rc = 0;
3446
3447         if (bp->vnic_info[vnic_id].fw_vnic_id != INVALID_HW_RING_ID) {
3448                 struct hwrm_vnic_free_input req = {0};
3449
3450                 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_VNIC_FREE, -1, -1);
3451                 req.vnic_id =
3452                         cpu_to_le32(bp->vnic_info[vnic_id].fw_vnic_id);
3453
3454                 rc = hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT);
3455                 if (rc)
3456                         return rc;
3457                 bp->vnic_info[vnic_id].fw_vnic_id = INVALID_HW_RING_ID;
3458         }
3459         return rc;
3460 }
3461
3462 static void bnxt_hwrm_vnic_free(struct bnxt *bp)
3463 {
3464         u16 i;
3465
3466         for (i = 0; i < bp->nr_vnics; i++)
3467                 bnxt_hwrm_vnic_free_one(bp, i);
3468 }
3469
3470 static int bnxt_hwrm_vnic_alloc(struct bnxt *bp, u16 vnic_id,
3471                                 unsigned int start_rx_ring_idx,
3472                                 unsigned int nr_rings)
3473 {
3474         int rc = 0;
3475         unsigned int i, j, grp_idx, end_idx = start_rx_ring_idx + nr_rings;
3476         struct hwrm_vnic_alloc_input req = {0};
3477         struct hwrm_vnic_alloc_output *resp = bp->hwrm_cmd_resp_addr;
3478
3479         /* map ring groups to this vnic */
3480         for (i = start_rx_ring_idx, j = 0; i < end_idx; i++, j++) {
3481                 grp_idx = bp->rx_ring[i].bnapi->index;
3482                 if (bp->grp_info[grp_idx].fw_grp_id == INVALID_HW_RING_ID) {
3483                         netdev_err(bp->dev, "Not enough ring groups avail:%x req:%x\n",
3484                                    j, nr_rings);
3485                         break;
3486                 }
3487                 bp->vnic_info[vnic_id].fw_grp_ids[j] =
3488                                         bp->grp_info[grp_idx].fw_grp_id;
3489         }
3490
3491         bp->vnic_info[vnic_id].fw_rss_cos_lb_ctx = INVALID_HW_RING_ID;
3492         if (vnic_id == 0)
3493                 req.flags = cpu_to_le32(VNIC_ALLOC_REQ_FLAGS_DEFAULT);
3494
3495         bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_VNIC_ALLOC, -1, -1);
3496
3497         mutex_lock(&bp->hwrm_cmd_lock);
3498         rc = _hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT);
3499         if (!rc)
3500                 bp->vnic_info[vnic_id].fw_vnic_id = le32_to_cpu(resp->vnic_id);
3501         mutex_unlock(&bp->hwrm_cmd_lock);
3502         return rc;
3503 }
3504
3505 static int bnxt_hwrm_ring_grp_alloc(struct bnxt *bp)
3506 {
3507         u16 i;
3508         u32 rc = 0;
3509
3510         mutex_lock(&bp->hwrm_cmd_lock);
3511         for (i = 0; i < bp->rx_nr_rings; i++) {
3512                 struct hwrm_ring_grp_alloc_input req = {0};
3513                 struct hwrm_ring_grp_alloc_output *resp =
3514                                         bp->hwrm_cmd_resp_addr;
3515                 unsigned int grp_idx = bp->rx_ring[i].bnapi->index;
3516
3517                 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_RING_GRP_ALLOC, -1, -1);
3518
3519                 req.cr = cpu_to_le16(bp->grp_info[grp_idx].cp_fw_ring_id);
3520                 req.rr = cpu_to_le16(bp->grp_info[grp_idx].rx_fw_ring_id);
3521                 req.ar = cpu_to_le16(bp->grp_info[grp_idx].agg_fw_ring_id);
3522                 req.sc = cpu_to_le16(bp->grp_info[grp_idx].fw_stats_ctx);
3523
3524                 rc = _hwrm_send_message(bp, &req, sizeof(req),
3525                                         HWRM_CMD_TIMEOUT);
3526                 if (rc)
3527                         break;
3528
3529                 bp->grp_info[grp_idx].fw_grp_id =
3530                         le32_to_cpu(resp->ring_group_id);
3531         }
3532         mutex_unlock(&bp->hwrm_cmd_lock);
3533         return rc;
3534 }
3535
3536 static int bnxt_hwrm_ring_grp_free(struct bnxt *bp)
3537 {
3538         u16 i;
3539         u32 rc = 0;
3540         struct hwrm_ring_grp_free_input req = {0};
3541
3542         if (!bp->grp_info)
3543                 return 0;
3544
3545         bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_RING_GRP_FREE, -1, -1);
3546
3547         mutex_lock(&bp->hwrm_cmd_lock);
3548         for (i = 0; i < bp->cp_nr_rings; i++) {
3549                 if (bp->grp_info[i].fw_grp_id == INVALID_HW_RING_ID)
3550                         continue;
3551                 req.ring_group_id =
3552                         cpu_to_le32(bp->grp_info[i].fw_grp_id);
3553
3554                 rc = _hwrm_send_message(bp, &req, sizeof(req),
3555                                         HWRM_CMD_TIMEOUT);
3556                 if (rc)
3557                         break;
3558                 bp->grp_info[i].fw_grp_id = INVALID_HW_RING_ID;
3559         }
3560         mutex_unlock(&bp->hwrm_cmd_lock);
3561         return rc;
3562 }
3563
3564 static int hwrm_ring_alloc_send_msg(struct bnxt *bp,
3565                                     struct bnxt_ring_struct *ring,
3566                                     u32 ring_type, u32 map_index,
3567                                     u32 stats_ctx_id)
3568 {
3569         int rc = 0, err = 0;
3570         struct hwrm_ring_alloc_input req = {0};
3571         struct hwrm_ring_alloc_output *resp = bp->hwrm_cmd_resp_addr;
3572         u16 ring_id;
3573
3574         bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_RING_ALLOC, -1, -1);
3575
3576         req.enables = 0;
3577         if (ring->nr_pages > 1) {
3578                 req.page_tbl_addr = cpu_to_le64(ring->pg_tbl_map);
3579                 /* Page size is in log2 units */
3580                 req.page_size = BNXT_PAGE_SHIFT;
3581                 req.page_tbl_depth = 1;
3582         } else {
3583                 req.page_tbl_addr =  cpu_to_le64(ring->dma_arr[0]);
3584         }
3585         req.fbo = 0;
3586         /* Association of ring index with doorbell index and MSIX number */
3587         req.logical_id = cpu_to_le16(map_index);
3588
3589         switch (ring_type) {
3590         case HWRM_RING_ALLOC_TX:
3591                 req.ring_type = RING_ALLOC_REQ_RING_TYPE_TX;
3592                 /* Association of transmit ring with completion ring */
3593                 req.cmpl_ring_id =
3594                         cpu_to_le16(bp->grp_info[map_index].cp_fw_ring_id);
3595                 req.length = cpu_to_le32(bp->tx_ring_mask + 1);
3596                 req.stat_ctx_id = cpu_to_le32(stats_ctx_id);
3597                 req.queue_id = cpu_to_le16(ring->queue_id);
3598                 break;
3599         case HWRM_RING_ALLOC_RX:
3600                 req.ring_type = RING_ALLOC_REQ_RING_TYPE_RX;
3601                 req.length = cpu_to_le32(bp->rx_ring_mask + 1);
3602                 break;
3603         case HWRM_RING_ALLOC_AGG:
3604                 req.ring_type = RING_ALLOC_REQ_RING_TYPE_RX;
3605                 req.length = cpu_to_le32(bp->rx_agg_ring_mask + 1);
3606                 break;
3607         case HWRM_RING_ALLOC_CMPL:
3608                 req.ring_type = RING_ALLOC_REQ_RING_TYPE_CMPL;
3609                 req.length = cpu_to_le32(bp->cp_ring_mask + 1);
3610                 if (bp->flags & BNXT_FLAG_USING_MSIX)
3611                         req.int_mode = RING_ALLOC_REQ_INT_MODE_MSIX;
3612                 break;
3613         default:
3614                 netdev_err(bp->dev, "hwrm alloc invalid ring type %d\n",
3615                            ring_type);
3616                 return -1;
3617         }
3618
3619         mutex_lock(&bp->hwrm_cmd_lock);
3620         rc = _hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT);
3621         err = le16_to_cpu(resp->error_code);
3622         ring_id = le16_to_cpu(resp->ring_id);
3623         mutex_unlock(&bp->hwrm_cmd_lock);
3624
3625         if (rc || err) {
3626                 switch (ring_type) {
3627                 case RING_FREE_REQ_RING_TYPE_CMPL:
3628                         netdev_err(bp->dev, "hwrm_ring_alloc cp failed. rc:%x err:%x\n",
3629                                    rc, err);
3630                         return -1;
3631
3632                 case RING_FREE_REQ_RING_TYPE_RX:
3633                         netdev_err(bp->dev, "hwrm_ring_alloc rx failed. rc:%x err:%x\n",
3634                                    rc, err);
3635                         return -1;
3636
3637                 case RING_FREE_REQ_RING_TYPE_TX:
3638                         netdev_err(bp->dev, "hwrm_ring_alloc tx failed. rc:%x err:%x\n",
3639                                    rc, err);
3640                         return -1;
3641
3642                 default:
3643                         netdev_err(bp->dev, "Invalid ring\n");
3644                         return -1;
3645                 }
3646         }
3647         ring->fw_ring_id = ring_id;
3648         return rc;
3649 }
3650
3651 static int bnxt_hwrm_ring_alloc(struct bnxt *bp)
3652 {
3653         int i, rc = 0;
3654
3655         for (i = 0; i < bp->cp_nr_rings; i++) {
3656                 struct bnxt_napi *bnapi = bp->bnapi[i];
3657                 struct bnxt_cp_ring_info *cpr = &bnapi->cp_ring;
3658                 struct bnxt_ring_struct *ring = &cpr->cp_ring_struct;
3659
3660                 cpr->cp_doorbell = bp->bar1 + i * 0x80;
3661                 rc = hwrm_ring_alloc_send_msg(bp, ring, HWRM_RING_ALLOC_CMPL, i,
3662                                               INVALID_STATS_CTX_ID);
3663                 if (rc)
3664                         goto err_out;
3665                 BNXT_CP_DB(cpr->cp_doorbell, cpr->cp_raw_cons);
3666                 bp->grp_info[i].cp_fw_ring_id = ring->fw_ring_id;
3667         }
3668
3669         for (i = 0; i < bp->tx_nr_rings; i++) {
3670                 struct bnxt_tx_ring_info *txr = &bp->tx_ring[i];
3671                 struct bnxt_ring_struct *ring = &txr->tx_ring_struct;
3672                 u32 map_idx = txr->bnapi->index;
3673                 u16 fw_stats_ctx = bp->grp_info[map_idx].fw_stats_ctx;
3674
3675                 rc = hwrm_ring_alloc_send_msg(bp, ring, HWRM_RING_ALLOC_TX,
3676                                               map_idx, fw_stats_ctx);
3677                 if (rc)
3678                         goto err_out;
3679                 txr->tx_doorbell = bp->bar1 + map_idx * 0x80;
3680         }
3681
3682         for (i = 0; i < bp->rx_nr_rings; i++) {
3683                 struct bnxt_rx_ring_info *rxr = &bp->rx_ring[i];
3684                 struct bnxt_ring_struct *ring = &rxr->rx_ring_struct;
3685                 u32 map_idx = rxr->bnapi->index;
3686
3687                 rc = hwrm_ring_alloc_send_msg(bp, ring, HWRM_RING_ALLOC_RX,
3688                                               map_idx, INVALID_STATS_CTX_ID);
3689                 if (rc)
3690                         goto err_out;
3691                 rxr->rx_doorbell = bp->bar1 + map_idx * 0x80;
3692                 writel(DB_KEY_RX | rxr->rx_prod, rxr->rx_doorbell);
3693                 bp->grp_info[map_idx].rx_fw_ring_id = ring->fw_ring_id;
3694         }
3695
3696         if (bp->flags & BNXT_FLAG_AGG_RINGS) {
3697                 for (i = 0; i < bp->rx_nr_rings; i++) {
3698                         struct bnxt_rx_ring_info *rxr = &bp->rx_ring[i];
3699                         struct bnxt_ring_struct *ring =
3700                                                 &rxr->rx_agg_ring_struct;
3701                         u32 grp_idx = rxr->bnapi->index;
3702                         u32 map_idx = grp_idx + bp->rx_nr_rings;
3703
3704                         rc = hwrm_ring_alloc_send_msg(bp, ring,
3705                                                       HWRM_RING_ALLOC_AGG,
3706                                                       map_idx,
3707                                                       INVALID_STATS_CTX_ID);
3708                         if (rc)
3709                                 goto err_out;
3710
3711                         rxr->rx_agg_doorbell = bp->bar1 + map_idx * 0x80;
3712                         writel(DB_KEY_RX | rxr->rx_agg_prod,
3713                                rxr->rx_agg_doorbell);
3714                         bp->grp_info[grp_idx].agg_fw_ring_id = ring->fw_ring_id;
3715                 }
3716         }
3717 err_out:
3718         return rc;
3719 }
3720
3721 static int hwrm_ring_free_send_msg(struct bnxt *bp,
3722                                    struct bnxt_ring_struct *ring,
3723                                    u32 ring_type, int cmpl_ring_id)
3724 {
3725         int rc;
3726         struct hwrm_ring_free_input req = {0};
3727         struct hwrm_ring_free_output *resp = bp->hwrm_cmd_resp_addr;
3728         u16 error_code;
3729
3730         bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_RING_FREE, cmpl_ring_id, -1);
3731         req.ring_type = ring_type;
3732         req.ring_id = cpu_to_le16(ring->fw_ring_id);
3733
3734         mutex_lock(&bp->hwrm_cmd_lock);
3735         rc = _hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT);
3736         error_code = le16_to_cpu(resp->error_code);
3737         mutex_unlock(&bp->hwrm_cmd_lock);
3738
3739         if (rc || error_code) {
3740                 switch (ring_type) {
3741                 case RING_FREE_REQ_RING_TYPE_CMPL:
3742                         netdev_err(bp->dev, "hwrm_ring_free cp failed. rc:%d\n",
3743                                    rc);
3744                         return rc;
3745                 case RING_FREE_REQ_RING_TYPE_RX:
3746                         netdev_err(bp->dev, "hwrm_ring_free rx failed. rc:%d\n",
3747                                    rc);
3748                         return rc;
3749                 case RING_FREE_REQ_RING_TYPE_TX:
3750                         netdev_err(bp->dev, "hwrm_ring_free tx failed. rc:%d\n",
3751                                    rc);
3752                         return rc;
3753                 default:
3754                         netdev_err(bp->dev, "Invalid ring\n");
3755                         return -1;
3756                 }
3757         }
3758         return 0;
3759 }
3760
3761 static void bnxt_hwrm_ring_free(struct bnxt *bp, bool close_path)
3762 {
3763         int i;
3764
3765         if (!bp->bnapi)
3766                 return;
3767
3768         for (i = 0; i < bp->tx_nr_rings; i++) {
3769                 struct bnxt_tx_ring_info *txr = &bp->tx_ring[i];
3770                 struct bnxt_ring_struct *ring = &txr->tx_ring_struct;
3771                 u32 grp_idx = txr->bnapi->index;
3772                 u32 cmpl_ring_id = bp->grp_info[grp_idx].cp_fw_ring_id;
3773
3774                 if (ring->fw_ring_id != INVALID_HW_RING_ID) {
3775                         hwrm_ring_free_send_msg(bp, ring,
3776                                                 RING_FREE_REQ_RING_TYPE_TX,
3777                                                 close_path ? cmpl_ring_id :
3778                                                 INVALID_HW_RING_ID);
3779                         ring->fw_ring_id = INVALID_HW_RING_ID;
3780                 }
3781         }
3782
3783         for (i = 0; i < bp->rx_nr_rings; i++) {
3784                 struct bnxt_rx_ring_info *rxr = &bp->rx_ring[i];
3785                 struct bnxt_ring_struct *ring = &rxr->rx_ring_struct;
3786                 u32 grp_idx = rxr->bnapi->index;
3787                 u32 cmpl_ring_id = bp->grp_info[grp_idx].cp_fw_ring_id;
3788
3789                 if (ring->fw_ring_id != INVALID_HW_RING_ID) {
3790                         hwrm_ring_free_send_msg(bp, ring,
3791                                                 RING_FREE_REQ_RING_TYPE_RX,
3792                                                 close_path ? cmpl_ring_id :
3793                                                 INVALID_HW_RING_ID);
3794                         ring->fw_ring_id = INVALID_HW_RING_ID;
3795                         bp->grp_info[grp_idx].rx_fw_ring_id =
3796                                 INVALID_HW_RING_ID;
3797                 }
3798         }
3799
3800         for (i = 0; i < bp->rx_nr_rings; i++) {
3801                 struct bnxt_rx_ring_info *rxr = &bp->rx_ring[i];
3802                 struct bnxt_ring_struct *ring = &rxr->rx_agg_ring_struct;
3803                 u32 grp_idx = rxr->bnapi->index;
3804                 u32 cmpl_ring_id = bp->grp_info[grp_idx].cp_fw_ring_id;
3805
3806                 if (ring->fw_ring_id != INVALID_HW_RING_ID) {
3807                         hwrm_ring_free_send_msg(bp, ring,
3808                                                 RING_FREE_REQ_RING_TYPE_RX,
3809                                                 close_path ? cmpl_ring_id :
3810                                                 INVALID_HW_RING_ID);
3811                         ring->fw_ring_id = INVALID_HW_RING_ID;
3812                         bp->grp_info[grp_idx].agg_fw_ring_id =
3813                                 INVALID_HW_RING_ID;
3814                 }
3815         }
3816
3817         for (i = 0; i < bp->cp_nr_rings; i++) {
3818                 struct bnxt_napi *bnapi = bp->bnapi[i];
3819                 struct bnxt_cp_ring_info *cpr = &bnapi->cp_ring;
3820                 struct bnxt_ring_struct *ring = &cpr->cp_ring_struct;
3821
3822                 if (ring->fw_ring_id != INVALID_HW_RING_ID) {
3823                         hwrm_ring_free_send_msg(bp, ring,
3824                                                 RING_FREE_REQ_RING_TYPE_CMPL,
3825                                                 INVALID_HW_RING_ID);
3826                         ring->fw_ring_id = INVALID_HW_RING_ID;
3827                         bp->grp_info[i].cp_fw_ring_id = INVALID_HW_RING_ID;
3828                 }
3829         }
3830 }
3831
3832 static void bnxt_hwrm_set_coal_params(struct bnxt *bp, u32 max_bufs,
3833         u32 buf_tmrs, u16 flags,
3834         struct hwrm_ring_cmpl_ring_cfg_aggint_params_input *req)
3835 {
3836         req->flags = cpu_to_le16(flags);
3837         req->num_cmpl_dma_aggr = cpu_to_le16((u16)max_bufs);
3838         req->num_cmpl_dma_aggr_during_int = cpu_to_le16(max_bufs >> 16);
3839         req->cmpl_aggr_dma_tmr = cpu_to_le16((u16)buf_tmrs);
3840         req->cmpl_aggr_dma_tmr_during_int = cpu_to_le16(buf_tmrs >> 16);
3841         /* Minimum time between 2 interrupts set to buf_tmr x 2 */
3842         req->int_lat_tmr_min = cpu_to_le16((u16)buf_tmrs * 2);
3843         req->int_lat_tmr_max = cpu_to_le16((u16)buf_tmrs * 4);
3844         req->num_cmpl_aggr_int = cpu_to_le16((u16)max_bufs * 4);
3845 }
3846
3847 int bnxt_hwrm_set_coal(struct bnxt *bp)
3848 {
3849         int i, rc = 0;
3850         struct hwrm_ring_cmpl_ring_cfg_aggint_params_input req_rx = {0},
3851                                                            req_tx = {0}, *req;
3852         u16 max_buf, max_buf_irq;
3853         u16 buf_tmr, buf_tmr_irq;
3854         u32 flags;
3855
3856         bnxt_hwrm_cmd_hdr_init(bp, &req_rx,
3857                                HWRM_RING_CMPL_RING_CFG_AGGINT_PARAMS, -1, -1);
3858         bnxt_hwrm_cmd_hdr_init(bp, &req_tx,
3859                                HWRM_RING_CMPL_RING_CFG_AGGINT_PARAMS, -1, -1);
3860
3861         /* Each rx completion (2 records) should be DMAed immediately.
3862          * DMA 1/4 of the completion buffers at a time.
3863          */
3864         max_buf = min_t(u16, bp->rx_coal_bufs / 4, 2);
3865         /* max_buf must not be zero */
3866         max_buf = clamp_t(u16, max_buf, 1, 63);
3867         max_buf_irq = clamp_t(u16, bp->rx_coal_bufs_irq, 1, 63);
3868         buf_tmr = BNXT_USEC_TO_COAL_TIMER(bp->rx_coal_ticks);
3869         /* buf timer set to 1/4 of interrupt timer */
3870         buf_tmr = max_t(u16, buf_tmr / 4, 1);
3871         buf_tmr_irq = BNXT_USEC_TO_COAL_TIMER(bp->rx_coal_ticks_irq);
3872         buf_tmr_irq = max_t(u16, buf_tmr_irq, 1);
3873
3874         flags = RING_CMPL_RING_CFG_AGGINT_PARAMS_REQ_FLAGS_TIMER_RESET;
3875
3876         /* RING_IDLE generates more IRQs for lower latency.  Enable it only
3877          * if coal_ticks is less than 25 us.
3878          */
3879         if (bp->rx_coal_ticks < 25)
3880                 flags |= RING_CMPL_RING_CFG_AGGINT_PARAMS_REQ_FLAGS_RING_IDLE;
3881
3882         bnxt_hwrm_set_coal_params(bp, max_buf_irq << 16 | max_buf,
3883                                   buf_tmr_irq << 16 | buf_tmr, flags, &req_rx);
3884
3885         /* max_buf must not be zero */
3886         max_buf = clamp_t(u16, bp->tx_coal_bufs, 1, 63);
3887         max_buf_irq = clamp_t(u16, bp->tx_coal_bufs_irq, 1, 63);
3888         buf_tmr = BNXT_USEC_TO_COAL_TIMER(bp->tx_coal_ticks);
3889         /* buf timer set to 1/4 of interrupt timer */
3890         buf_tmr = max_t(u16, buf_tmr / 4, 1);
3891         buf_tmr_irq = BNXT_USEC_TO_COAL_TIMER(bp->tx_coal_ticks_irq);
3892         buf_tmr_irq = max_t(u16, buf_tmr_irq, 1);
3893
3894         flags = RING_CMPL_RING_CFG_AGGINT_PARAMS_REQ_FLAGS_TIMER_RESET;
3895         bnxt_hwrm_set_coal_params(bp, max_buf_irq << 16 | max_buf,
3896                                   buf_tmr_irq << 16 | buf_tmr, flags, &req_tx);
3897
3898         mutex_lock(&bp->hwrm_cmd_lock);
3899         for (i = 0; i < bp->cp_nr_rings; i++) {
3900                 struct bnxt_napi *bnapi = bp->bnapi[i];
3901
3902                 req = &req_rx;
3903                 if (!bnapi->rx_ring)
3904                         req = &req_tx;
3905                 req->ring_id = cpu_to_le16(bp->grp_info[i].cp_fw_ring_id);
3906
3907                 rc = _hwrm_send_message(bp, req, sizeof(*req),
3908                                         HWRM_CMD_TIMEOUT);
3909                 if (rc)
3910                         break;
3911         }
3912         mutex_unlock(&bp->hwrm_cmd_lock);
3913         return rc;
3914 }
3915
3916 static int bnxt_hwrm_stat_ctx_free(struct bnxt *bp)
3917 {
3918         int rc = 0, i;
3919         struct hwrm_stat_ctx_free_input req = {0};
3920
3921         if (!bp->bnapi)
3922                 return 0;
3923
3924         bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_STAT_CTX_FREE, -1, -1);
3925
3926         mutex_lock(&bp->hwrm_cmd_lock);
3927         for (i = 0; i < bp->cp_nr_rings; i++) {
3928                 struct bnxt_napi *bnapi = bp->bnapi[i];
3929                 struct bnxt_cp_ring_info *cpr = &bnapi->cp_ring;
3930
3931                 if (cpr->hw_stats_ctx_id != INVALID_STATS_CTX_ID) {
3932                         req.stat_ctx_id = cpu_to_le32(cpr->hw_stats_ctx_id);
3933
3934                         rc = _hwrm_send_message(bp, &req, sizeof(req),
3935                                                 HWRM_CMD_TIMEOUT);
3936                         if (rc)
3937                                 break;
3938
3939                         cpr->hw_stats_ctx_id = INVALID_STATS_CTX_ID;
3940                 }
3941         }
3942         mutex_unlock(&bp->hwrm_cmd_lock);
3943         return rc;
3944 }
3945
3946 static int bnxt_hwrm_stat_ctx_alloc(struct bnxt *bp)
3947 {
3948         int rc = 0, i;
3949         struct hwrm_stat_ctx_alloc_input req = {0};
3950         struct hwrm_stat_ctx_alloc_output *resp = bp->hwrm_cmd_resp_addr;
3951
3952         bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_STAT_CTX_ALLOC, -1, -1);
3953
3954         req.update_period_ms = cpu_to_le32(1000);
3955
3956         mutex_lock(&bp->hwrm_cmd_lock);
3957         for (i = 0; i < bp->cp_nr_rings; i++) {
3958                 struct bnxt_napi *bnapi = bp->bnapi[i];
3959                 struct bnxt_cp_ring_info *cpr = &bnapi->cp_ring;
3960
3961                 req.stats_dma_addr = cpu_to_le64(cpr->hw_stats_map);
3962
3963                 rc = _hwrm_send_message(bp, &req, sizeof(req),
3964                                         HWRM_CMD_TIMEOUT);
3965                 if (rc)
3966                         break;
3967
3968                 cpr->hw_stats_ctx_id = le32_to_cpu(resp->stat_ctx_id);
3969
3970                 bp->grp_info[i].fw_stats_ctx = cpr->hw_stats_ctx_id;
3971         }
3972         mutex_unlock(&bp->hwrm_cmd_lock);
3973         return 0;
3974 }
3975
3976 static int bnxt_hwrm_func_qcfg(struct bnxt *bp)
3977 {
3978         struct hwrm_func_qcfg_input req = {0};
3979         struct hwrm_func_qcfg_output *resp = bp->hwrm_cmd_resp_addr;
3980         int rc;
3981
3982         bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_FUNC_QCFG, -1, -1);
3983         req.fid = cpu_to_le16(0xffff);
3984         mutex_lock(&bp->hwrm_cmd_lock);
3985         rc = _hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT);
3986         if (rc)
3987                 goto func_qcfg_exit;
3988
3989 #ifdef CONFIG_BNXT_SRIOV
3990         if (BNXT_VF(bp)) {
3991                 struct bnxt_vf_info *vf = &bp->vf;
3992
3993                 vf->vlan = le16_to_cpu(resp->vlan) & VLAN_VID_MASK;
3994         }
3995 #endif
3996         switch (resp->port_partition_type) {
3997         case FUNC_QCFG_RESP_PORT_PARTITION_TYPE_NPAR1_0:
3998         case FUNC_QCFG_RESP_PORT_PARTITION_TYPE_NPAR1_5:
3999         case FUNC_QCFG_RESP_PORT_PARTITION_TYPE_NPAR2_0:
4000                 bp->port_partition_type = resp->port_partition_type;
4001                 break;
4002         }
4003
4004 func_qcfg_exit:
4005         mutex_unlock(&bp->hwrm_cmd_lock);
4006         return rc;
4007 }
4008
4009 int bnxt_hwrm_func_qcaps(struct bnxt *bp)
4010 {
4011         int rc = 0;
4012         struct hwrm_func_qcaps_input req = {0};
4013         struct hwrm_func_qcaps_output *resp = bp->hwrm_cmd_resp_addr;
4014
4015         bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_FUNC_QCAPS, -1, -1);
4016         req.fid = cpu_to_le16(0xffff);
4017
4018         mutex_lock(&bp->hwrm_cmd_lock);
4019         rc = _hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT);
4020         if (rc)
4021                 goto hwrm_func_qcaps_exit;
4022
4023         if (BNXT_PF(bp)) {
4024                 struct bnxt_pf_info *pf = &bp->pf;
4025
4026                 pf->fw_fid = le16_to_cpu(resp->fid);
4027                 pf->port_id = le16_to_cpu(resp->port_id);
4028                 memcpy(pf->mac_addr, resp->mac_address, ETH_ALEN);
4029                 memcpy(bp->dev->dev_addr, pf->mac_addr, ETH_ALEN);
4030                 pf->max_rsscos_ctxs = le16_to_cpu(resp->max_rsscos_ctx);
4031                 pf->max_cp_rings = le16_to_cpu(resp->max_cmpl_rings);
4032                 pf->max_tx_rings = le16_to_cpu(resp->max_tx_rings);
4033                 pf->max_rx_rings = le16_to_cpu(resp->max_rx_rings);
4034                 pf->max_hw_ring_grps = le32_to_cpu(resp->max_hw_ring_grps);
4035                 if (!pf->max_hw_ring_grps)
4036                         pf->max_hw_ring_grps = pf->max_tx_rings;
4037                 pf->max_l2_ctxs = le16_to_cpu(resp->max_l2_ctxs);
4038                 pf->max_vnics = le16_to_cpu(resp->max_vnics);
4039                 pf->max_stat_ctxs = le16_to_cpu(resp->max_stat_ctx);
4040                 pf->first_vf_id = le16_to_cpu(resp->first_vf_id);
4041                 pf->max_vfs = le16_to_cpu(resp->max_vfs);
4042                 pf->max_encap_records = le32_to_cpu(resp->max_encap_records);
4043                 pf->max_decap_records = le32_to_cpu(resp->max_decap_records);
4044                 pf->max_tx_em_flows = le32_to_cpu(resp->max_tx_em_flows);
4045                 pf->max_tx_wm_flows = le32_to_cpu(resp->max_tx_wm_flows);
4046                 pf->max_rx_em_flows = le32_to_cpu(resp->max_rx_em_flows);
4047                 pf->max_rx_wm_flows = le32_to_cpu(resp->max_rx_wm_flows);
4048         } else {
4049 #ifdef CONFIG_BNXT_SRIOV
4050                 struct bnxt_vf_info *vf = &bp->vf;
4051
4052                 vf->fw_fid = le16_to_cpu(resp->fid);
4053                 memcpy(vf->mac_addr, resp->mac_address, ETH_ALEN);
4054                 if (is_valid_ether_addr(vf->mac_addr))
4055                         /* overwrite netdev dev_adr with admin VF MAC */
4056                         memcpy(bp->dev->dev_addr, vf->mac_addr, ETH_ALEN);
4057                 else
4058                         random_ether_addr(bp->dev->dev_addr);
4059
4060                 vf->max_rsscos_ctxs = le16_to_cpu(resp->max_rsscos_ctx);
4061                 vf->max_cp_rings = le16_to_cpu(resp->max_cmpl_rings);
4062                 vf->max_tx_rings = le16_to_cpu(resp->max_tx_rings);
4063                 vf->max_rx_rings = le16_to_cpu(resp->max_rx_rings);
4064                 vf->max_hw_ring_grps = le32_to_cpu(resp->max_hw_ring_grps);
4065                 if (!vf->max_hw_ring_grps)
4066                         vf->max_hw_ring_grps = vf->max_tx_rings;
4067                 vf->max_l2_ctxs = le16_to_cpu(resp->max_l2_ctxs);
4068                 vf->max_vnics = le16_to_cpu(resp->max_vnics);
4069                 vf->max_stat_ctxs = le16_to_cpu(resp->max_stat_ctx);
4070 #endif
4071         }
4072
4073         bp->tx_push_thresh = 0;
4074         if (resp->flags &
4075             cpu_to_le32(FUNC_QCAPS_RESP_FLAGS_PUSH_MODE_SUPPORTED))
4076                 bp->tx_push_thresh = BNXT_TX_PUSH_THRESH;
4077
4078 hwrm_func_qcaps_exit:
4079         mutex_unlock(&bp->hwrm_cmd_lock);
4080         return rc;
4081 }
4082
4083 static int bnxt_hwrm_func_reset(struct bnxt *bp)
4084 {
4085         struct hwrm_func_reset_input req = {0};
4086
4087         bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_FUNC_RESET, -1, -1);
4088         req.enables = 0;
4089
4090         return hwrm_send_message(bp, &req, sizeof(req), HWRM_RESET_TIMEOUT);
4091 }
4092
4093 static int bnxt_hwrm_queue_qportcfg(struct bnxt *bp)
4094 {
4095         int rc = 0;
4096         struct hwrm_queue_qportcfg_input req = {0};
4097         struct hwrm_queue_qportcfg_output *resp = bp->hwrm_cmd_resp_addr;
4098         u8 i, *qptr;
4099
4100         bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_QUEUE_QPORTCFG, -1, -1);
4101
4102         mutex_lock(&bp->hwrm_cmd_lock);
4103         rc = _hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT);
4104         if (rc)
4105                 goto qportcfg_exit;
4106
4107         if (!resp->max_configurable_queues) {
4108                 rc = -EINVAL;
4109                 goto qportcfg_exit;
4110         }
4111         bp->max_tc = resp->max_configurable_queues;
4112         if (bp->max_tc > BNXT_MAX_QUEUE)
4113                 bp->max_tc = BNXT_MAX_QUEUE;
4114
4115         qptr = &resp->queue_id0;
4116         for (i = 0; i < bp->max_tc; i++) {
4117                 bp->q_info[i].queue_id = *qptr++;
4118                 bp->q_info[i].queue_profile = *qptr++;
4119         }
4120
4121 qportcfg_exit:
4122         mutex_unlock(&bp->hwrm_cmd_lock);
4123         return rc;
4124 }
4125
4126 static int bnxt_hwrm_ver_get(struct bnxt *bp)
4127 {
4128         int rc;
4129         struct hwrm_ver_get_input req = {0};
4130         struct hwrm_ver_get_output *resp = bp->hwrm_cmd_resp_addr;
4131
4132         bp->hwrm_max_req_len = HWRM_MAX_REQ_LEN;
4133         bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_VER_GET, -1, -1);
4134         req.hwrm_intf_maj = HWRM_VERSION_MAJOR;
4135         req.hwrm_intf_min = HWRM_VERSION_MINOR;
4136         req.hwrm_intf_upd = HWRM_VERSION_UPDATE;
4137         mutex_lock(&bp->hwrm_cmd_lock);
4138         rc = _hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT);
4139         if (rc)
4140                 goto hwrm_ver_get_exit;
4141
4142         memcpy(&bp->ver_resp, resp, sizeof(struct hwrm_ver_get_output));
4143
4144         bp->hwrm_spec_code = resp->hwrm_intf_maj << 16 |
4145                              resp->hwrm_intf_min << 8 | resp->hwrm_intf_upd;
4146         if (resp->hwrm_intf_maj < 1) {
4147                 netdev_warn(bp->dev, "HWRM interface %d.%d.%d is older than 1.0.0.\n",
4148                             resp->hwrm_intf_maj, resp->hwrm_intf_min,
4149                             resp->hwrm_intf_upd);
4150                 netdev_warn(bp->dev, "Please update firmware with HWRM interface 1.0.0 or newer.\n");
4151         }
4152         snprintf(bp->fw_ver_str, BC_HWRM_STR_LEN, "%d.%d.%d/%d.%d.%d",
4153                  resp->hwrm_fw_maj, resp->hwrm_fw_min, resp->hwrm_fw_bld,
4154                  resp->hwrm_intf_maj, resp->hwrm_intf_min, resp->hwrm_intf_upd);
4155
4156         bp->hwrm_cmd_timeout = le16_to_cpu(resp->def_req_timeout);
4157         if (!bp->hwrm_cmd_timeout)
4158                 bp->hwrm_cmd_timeout = DFLT_HWRM_CMD_TIMEOUT;
4159
4160         if (resp->hwrm_intf_maj >= 1)
4161                 bp->hwrm_max_req_len = le16_to_cpu(resp->max_req_win_len);
4162
4163         bp->chip_num = le16_to_cpu(resp->chip_num);
4164
4165 hwrm_ver_get_exit:
4166         mutex_unlock(&bp->hwrm_cmd_lock);
4167         return rc;
4168 }
4169
4170 static int bnxt_hwrm_port_qstats(struct bnxt *bp)
4171 {
4172         int rc;
4173         struct bnxt_pf_info *pf = &bp->pf;
4174         struct hwrm_port_qstats_input req = {0};
4175
4176         if (!(bp->flags & BNXT_FLAG_PORT_STATS))
4177                 return 0;
4178
4179         bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_PORT_QSTATS, -1, -1);
4180         req.port_id = cpu_to_le16(pf->port_id);
4181         req.tx_stat_host_addr = cpu_to_le64(bp->hw_tx_port_stats_map);
4182         req.rx_stat_host_addr = cpu_to_le64(bp->hw_rx_port_stats_map);
4183         rc = hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT);
4184         return rc;
4185 }
4186
4187 static void bnxt_hwrm_free_tunnel_ports(struct bnxt *bp)
4188 {
4189         if (bp->vxlan_port_cnt) {
4190                 bnxt_hwrm_tunnel_dst_port_free(
4191                         bp, TUNNEL_DST_PORT_FREE_REQ_TUNNEL_TYPE_VXLAN);
4192         }
4193         bp->vxlan_port_cnt = 0;
4194         if (bp->nge_port_cnt) {
4195                 bnxt_hwrm_tunnel_dst_port_free(
4196                         bp, TUNNEL_DST_PORT_FREE_REQ_TUNNEL_TYPE_GENEVE);
4197         }
4198         bp->nge_port_cnt = 0;
4199 }
4200
4201 static int bnxt_set_tpa(struct bnxt *bp, bool set_tpa)
4202 {
4203         int rc, i;
4204         u32 tpa_flags = 0;
4205
4206         if (set_tpa)
4207                 tpa_flags = bp->flags & BNXT_FLAG_TPA;
4208         for (i = 0; i < bp->nr_vnics; i++) {
4209                 rc = bnxt_hwrm_vnic_set_tpa(bp, i, tpa_flags);
4210                 if (rc) {
4211                         netdev_err(bp->dev, "hwrm vnic set tpa failure rc for vnic %d: %x\n",
4212                                    rc, i);
4213                         return rc;
4214                 }
4215         }
4216         return 0;
4217 }
4218
4219 static void bnxt_hwrm_clear_vnic_rss(struct bnxt *bp)
4220 {
4221         int i;
4222
4223         for (i = 0; i < bp->nr_vnics; i++)
4224                 bnxt_hwrm_vnic_set_rss(bp, i, false);
4225 }
4226
4227 static void bnxt_hwrm_resource_free(struct bnxt *bp, bool close_path,
4228                                     bool irq_re_init)
4229 {
4230         if (bp->vnic_info) {
4231                 bnxt_hwrm_clear_vnic_filter(bp);
4232                 /* clear all RSS setting before free vnic ctx */
4233                 bnxt_hwrm_clear_vnic_rss(bp);
4234                 bnxt_hwrm_vnic_ctx_free(bp);
4235                 /* before free the vnic, undo the vnic tpa settings */
4236                 if (bp->flags & BNXT_FLAG_TPA)
4237                         bnxt_set_tpa(bp, false);
4238                 bnxt_hwrm_vnic_free(bp);
4239         }
4240         bnxt_hwrm_ring_free(bp, close_path);
4241         bnxt_hwrm_ring_grp_free(bp);
4242         if (irq_re_init) {
4243                 bnxt_hwrm_stat_ctx_free(bp);
4244                 bnxt_hwrm_free_tunnel_ports(bp);
4245         }
4246 }
4247
4248 static int bnxt_setup_vnic(struct bnxt *bp, u16 vnic_id)
4249 {
4250         int rc;
4251
4252         /* allocate context for vnic */
4253         rc = bnxt_hwrm_vnic_ctx_alloc(bp, vnic_id);
4254         if (rc) {
4255                 netdev_err(bp->dev, "hwrm vnic %d alloc failure rc: %x\n",
4256                            vnic_id, rc);
4257                 goto vnic_setup_err;
4258         }
4259         bp->rsscos_nr_ctxs++;
4260
4261         /* configure default vnic, ring grp */
4262         rc = bnxt_hwrm_vnic_cfg(bp, vnic_id);
4263         if (rc) {
4264                 netdev_err(bp->dev, "hwrm vnic %d cfg failure rc: %x\n",
4265                            vnic_id, rc);
4266                 goto vnic_setup_err;
4267         }
4268
4269         /* Enable RSS hashing on vnic */
4270         rc = bnxt_hwrm_vnic_set_rss(bp, vnic_id, true);
4271         if (rc) {
4272                 netdev_err(bp->dev, "hwrm vnic %d set rss failure rc: %x\n",
4273                            vnic_id, rc);
4274                 goto vnic_setup_err;
4275         }
4276
4277         if (bp->flags & BNXT_FLAG_AGG_RINGS) {
4278                 rc = bnxt_hwrm_vnic_set_hds(bp, vnic_id);
4279                 if (rc) {
4280                         netdev_err(bp->dev, "hwrm vnic %d set hds failure rc: %x\n",
4281                                    vnic_id, rc);
4282                 }
4283         }
4284
4285 vnic_setup_err:
4286         return rc;
4287 }
4288
4289 static int bnxt_alloc_rfs_vnics(struct bnxt *bp)
4290 {
4291 #ifdef CONFIG_RFS_ACCEL
4292         int i, rc = 0;
4293
4294         for (i = 0; i < bp->rx_nr_rings; i++) {
4295                 u16 vnic_id = i + 1;
4296                 u16 ring_id = i;
4297
4298                 if (vnic_id >= bp->nr_vnics)
4299                         break;
4300
4301                 bp->vnic_info[vnic_id].flags |= BNXT_VNIC_RFS_FLAG;
4302                 rc = bnxt_hwrm_vnic_alloc(bp, vnic_id, ring_id, 1);
4303                 if (rc) {
4304                         netdev_err(bp->dev, "hwrm vnic %d alloc failure rc: %x\n",
4305                                    vnic_id, rc);
4306                         break;
4307                 }
4308                 rc = bnxt_setup_vnic(bp, vnic_id);
4309                 if (rc)
4310                         break;
4311         }
4312         return rc;
4313 #else
4314         return 0;
4315 #endif
4316 }
4317
4318 static int bnxt_cfg_rx_mode(struct bnxt *);
4319 static bool bnxt_mc_list_updated(struct bnxt *, u32 *);
4320
4321 static int bnxt_init_chip(struct bnxt *bp, bool irq_re_init)
4322 {
4323         struct bnxt_vnic_info *vnic = &bp->vnic_info[0];
4324         int rc = 0;
4325
4326         if (irq_re_init) {
4327                 rc = bnxt_hwrm_stat_ctx_alloc(bp);
4328                 if (rc) {
4329                         netdev_err(bp->dev, "hwrm stat ctx alloc failure rc: %x\n",
4330                                    rc);
4331                         goto err_out;
4332                 }
4333         }
4334
4335         rc = bnxt_hwrm_ring_alloc(bp);
4336         if (rc) {
4337                 netdev_err(bp->dev, "hwrm ring alloc failure rc: %x\n", rc);
4338                 goto err_out;
4339         }
4340
4341         rc = bnxt_hwrm_ring_grp_alloc(bp);
4342         if (rc) {
4343                 netdev_err(bp->dev, "hwrm_ring_grp alloc failure: %x\n", rc);
4344                 goto err_out;
4345         }
4346
4347         /* default vnic 0 */
4348         rc = bnxt_hwrm_vnic_alloc(bp, 0, 0, bp->rx_nr_rings);
4349         if (rc) {
4350                 netdev_err(bp->dev, "hwrm vnic alloc failure rc: %x\n", rc);
4351                 goto err_out;
4352         }
4353
4354         rc = bnxt_setup_vnic(bp, 0);
4355         if (rc)
4356                 goto err_out;
4357
4358         if (bp->flags & BNXT_FLAG_RFS) {
4359                 rc = bnxt_alloc_rfs_vnics(bp);
4360                 if (rc)
4361                         goto err_out;
4362         }
4363
4364         if (bp->flags & BNXT_FLAG_TPA) {
4365                 rc = bnxt_set_tpa(bp, true);
4366                 if (rc)
4367                         goto err_out;
4368         }
4369
4370         if (BNXT_VF(bp))
4371                 bnxt_update_vf_mac(bp);
4372
4373         /* Filter for default vnic 0 */
4374         rc = bnxt_hwrm_set_vnic_filter(bp, 0, 0, bp->dev->dev_addr);
4375         if (rc) {
4376                 netdev_err(bp->dev, "HWRM vnic filter failure rc: %x\n", rc);
4377                 goto err_out;
4378         }
4379         vnic->uc_filter_count = 1;
4380
4381         vnic->rx_mask = CFA_L2_SET_RX_MASK_REQ_MASK_BCAST;
4382
4383         if ((bp->dev->flags & IFF_PROMISC) && BNXT_PF(bp))
4384                 vnic->rx_mask |= CFA_L2_SET_RX_MASK_REQ_MASK_PROMISCUOUS;
4385
4386         if (bp->dev->flags & IFF_ALLMULTI) {
4387                 vnic->rx_mask |= CFA_L2_SET_RX_MASK_REQ_MASK_ALL_MCAST;
4388                 vnic->mc_list_count = 0;
4389         } else {
4390                 u32 mask = 0;
4391
4392                 bnxt_mc_list_updated(bp, &mask);
4393                 vnic->rx_mask |= mask;
4394         }
4395
4396         rc = bnxt_cfg_rx_mode(bp);
4397         if (rc)
4398                 goto err_out;
4399
4400         rc = bnxt_hwrm_set_coal(bp);
4401         if (rc)
4402                 netdev_warn(bp->dev, "HWRM set coalescing failure rc: %x\n",
4403                             rc);
4404
4405         if (BNXT_VF(bp)) {
4406                 bnxt_hwrm_func_qcfg(bp);
4407                 netdev_update_features(bp->dev);
4408         }
4409
4410         return 0;
4411
4412 err_out:
4413         bnxt_hwrm_resource_free(bp, 0, true);
4414
4415         return rc;
4416 }
4417
4418 static int bnxt_shutdown_nic(struct bnxt *bp, bool irq_re_init)
4419 {
4420         bnxt_hwrm_resource_free(bp, 1, irq_re_init);
4421         return 0;
4422 }
4423
4424 static int bnxt_init_nic(struct bnxt *bp, bool irq_re_init)
4425 {
4426         bnxt_init_rx_rings(bp);
4427         bnxt_init_tx_rings(bp);
4428         bnxt_init_ring_grps(bp, irq_re_init);
4429         bnxt_init_vnics(bp);
4430
4431         return bnxt_init_chip(bp, irq_re_init);
4432 }
4433
4434 static void bnxt_disable_int(struct bnxt *bp)
4435 {
4436         int i;
4437
4438         if (!bp->bnapi)
4439                 return;
4440
4441         for (i = 0; i < bp->cp_nr_rings; i++) {
4442                 struct bnxt_napi *bnapi = bp->bnapi[i];
4443                 struct bnxt_cp_ring_info *cpr = &bnapi->cp_ring;
4444
4445                 BNXT_CP_DB(cpr->cp_doorbell, cpr->cp_raw_cons);
4446         }
4447 }
4448
4449 static void bnxt_enable_int(struct bnxt *bp)
4450 {
4451         int i;
4452
4453         atomic_set(&bp->intr_sem, 0);
4454         for (i = 0; i < bp->cp_nr_rings; i++) {
4455                 struct bnxt_napi *bnapi = bp->bnapi[i];
4456                 struct bnxt_cp_ring_info *cpr = &bnapi->cp_ring;
4457
4458                 BNXT_CP_DB_REARM(cpr->cp_doorbell, cpr->cp_raw_cons);
4459         }
4460 }
4461
4462 static int bnxt_set_real_num_queues(struct bnxt *bp)
4463 {
4464         int rc;
4465         struct net_device *dev = bp->dev;
4466
4467         rc = netif_set_real_num_tx_queues(dev, bp->tx_nr_rings);
4468         if (rc)
4469                 return rc;
4470
4471         rc = netif_set_real_num_rx_queues(dev, bp->rx_nr_rings);
4472         if (rc)
4473                 return rc;
4474
4475 #ifdef CONFIG_RFS_ACCEL
4476         if (bp->flags & BNXT_FLAG_RFS)
4477                 dev->rx_cpu_rmap = alloc_irq_cpu_rmap(bp->rx_nr_rings);
4478 #endif
4479
4480         return rc;
4481 }
4482
4483 static int bnxt_trim_rings(struct bnxt *bp, int *rx, int *tx, int max,
4484                            bool shared)
4485 {
4486         int _rx = *rx, _tx = *tx;
4487
4488         if (shared) {
4489                 *rx = min_t(int, _rx, max);
4490                 *tx = min_t(int, _tx, max);
4491         } else {
4492                 if (max < 2)
4493                         return -ENOMEM;
4494
4495                 while (_rx + _tx > max) {
4496                         if (_rx > _tx && _rx > 1)
4497                                 _rx--;
4498                         else if (_tx > 1)
4499                                 _tx--;
4500                 }
4501                 *rx = _rx;
4502                 *tx = _tx;
4503         }
4504         return 0;
4505 }
4506
4507 static int bnxt_setup_msix(struct bnxt *bp)
4508 {
4509         struct msix_entry *msix_ent;
4510         struct net_device *dev = bp->dev;
4511         int i, total_vecs, rc = 0, min = 1;
4512         const int len = sizeof(bp->irq_tbl[0].name);
4513
4514         bp->flags &= ~BNXT_FLAG_USING_MSIX;
4515         total_vecs = bp->cp_nr_rings;
4516
4517         msix_ent = kcalloc(total_vecs, sizeof(struct msix_entry), GFP_KERNEL);
4518         if (!msix_ent)
4519                 return -ENOMEM;
4520
4521         for (i = 0; i < total_vecs; i++) {
4522                 msix_ent[i].entry = i;
4523                 msix_ent[i].vector = 0;
4524         }
4525
4526         if (!(bp->flags & BNXT_FLAG_SHARED_RINGS))
4527                 min = 2;
4528
4529         total_vecs = pci_enable_msix_range(bp->pdev, msix_ent, min, total_vecs);
4530         if (total_vecs < 0) {
4531                 rc = -ENODEV;
4532                 goto msix_setup_exit;
4533         }
4534
4535         bp->irq_tbl = kcalloc(total_vecs, sizeof(struct bnxt_irq), GFP_KERNEL);
4536         if (bp->irq_tbl) {
4537                 int tcs;
4538
4539                 /* Trim rings based upon num of vectors allocated */
4540                 rc = bnxt_trim_rings(bp, &bp->rx_nr_rings, &bp->tx_nr_rings,
4541                                      total_vecs, min == 1);
4542                 if (rc)
4543                         goto msix_setup_exit;
4544
4545                 bp->tx_nr_rings_per_tc = bp->tx_nr_rings;
4546                 tcs = netdev_get_num_tc(dev);
4547                 if (tcs > 1) {
4548                         bp->tx_nr_rings_per_tc = bp->tx_nr_rings / tcs;
4549                         if (bp->tx_nr_rings_per_tc == 0) {
4550                                 netdev_reset_tc(dev);
4551                                 bp->tx_nr_rings_per_tc = bp->tx_nr_rings;
4552                         } else {
4553                                 int i, off, count;
4554
4555                                 bp->tx_nr_rings = bp->tx_nr_rings_per_tc * tcs;
4556                                 for (i = 0; i < tcs; i++) {
4557                                         count = bp->tx_nr_rings_per_tc;
4558                                         off = i * count;
4559                                         netdev_set_tc_queue(dev, i, count, off);
4560                                 }
4561                         }
4562                 }
4563                 bp->cp_nr_rings = total_vecs;
4564
4565                 for (i = 0; i < bp->cp_nr_rings; i++) {
4566                         char *attr;
4567
4568                         bp->irq_tbl[i].vector = msix_ent[i].vector;
4569                         if (bp->flags & BNXT_FLAG_SHARED_RINGS)
4570                                 attr = "TxRx";
4571                         else if (i < bp->rx_nr_rings)
4572                                 attr = "rx";
4573                         else
4574                                 attr = "tx";
4575
4576                         snprintf(bp->irq_tbl[i].name, len,
4577                                  "%s-%s-%d", dev->name, attr, i);
4578                         bp->irq_tbl[i].handler = bnxt_msix;
4579                 }
4580                 rc = bnxt_set_real_num_queues(bp);
4581                 if (rc)
4582                         goto msix_setup_exit;
4583         } else {
4584                 rc = -ENOMEM;
4585                 goto msix_setup_exit;
4586         }
4587         bp->flags |= BNXT_FLAG_USING_MSIX;
4588         kfree(msix_ent);
4589         return 0;
4590
4591 msix_setup_exit:
4592         netdev_err(bp->dev, "bnxt_setup_msix err: %x\n", rc);
4593         pci_disable_msix(bp->pdev);
4594         kfree(msix_ent);
4595         return rc;
4596 }
4597
4598 static int bnxt_setup_inta(struct bnxt *bp)
4599 {
4600         int rc;
4601         const int len = sizeof(bp->irq_tbl[0].name);
4602
4603         if (netdev_get_num_tc(bp->dev))
4604                 netdev_reset_tc(bp->dev);
4605
4606         bp->irq_tbl = kcalloc(1, sizeof(struct bnxt_irq), GFP_KERNEL);
4607         if (!bp->irq_tbl) {
4608                 rc = -ENOMEM;
4609                 return rc;
4610         }
4611         bp->rx_nr_rings = 1;
4612         bp->tx_nr_rings = 1;
4613         bp->cp_nr_rings = 1;
4614         bp->tx_nr_rings_per_tc = bp->tx_nr_rings;
4615         bp->flags |= BNXT_FLAG_SHARED_RINGS;
4616         bp->irq_tbl[0].vector = bp->pdev->irq;
4617         snprintf(bp->irq_tbl[0].name, len,
4618                  "%s-%s-%d", bp->dev->name, "TxRx", 0);
4619         bp->irq_tbl[0].handler = bnxt_inta;
4620         rc = bnxt_set_real_num_queues(bp);
4621         return rc;
4622 }
4623
4624 static int bnxt_setup_int_mode(struct bnxt *bp)
4625 {
4626         int rc = 0;
4627
4628         if (bp->flags & BNXT_FLAG_MSIX_CAP)
4629                 rc = bnxt_setup_msix(bp);
4630
4631         if (!(bp->flags & BNXT_FLAG_USING_MSIX) && BNXT_PF(bp)) {
4632                 /* fallback to INTA */
4633                 rc = bnxt_setup_inta(bp);
4634         }
4635         return rc;
4636 }
4637
4638 static void bnxt_free_irq(struct bnxt *bp)
4639 {
4640         struct bnxt_irq *irq;
4641         int i;
4642
4643 #ifdef CONFIG_RFS_ACCEL
4644         free_irq_cpu_rmap(bp->dev->rx_cpu_rmap);
4645         bp->dev->rx_cpu_rmap = NULL;
4646 #endif
4647         if (!bp->irq_tbl)
4648                 return;
4649
4650         for (i = 0; i < bp->cp_nr_rings; i++) {
4651                 irq = &bp->irq_tbl[i];
4652                 if (irq->requested)
4653                         free_irq(irq->vector, bp->bnapi[i]);
4654                 irq->requested = 0;
4655         }
4656         if (bp->flags & BNXT_FLAG_USING_MSIX)
4657                 pci_disable_msix(bp->pdev);
4658         kfree(bp->irq_tbl);
4659         bp->irq_tbl = NULL;
4660 }
4661
4662 static int bnxt_request_irq(struct bnxt *bp)
4663 {
4664         int i, j, rc = 0;
4665         unsigned long flags = 0;
4666 #ifdef CONFIG_RFS_ACCEL
4667         struct cpu_rmap *rmap = bp->dev->rx_cpu_rmap;
4668 #endif
4669
4670         if (!(bp->flags & BNXT_FLAG_USING_MSIX))
4671                 flags = IRQF_SHARED;
4672
4673         for (i = 0, j = 0; i < bp->cp_nr_rings; i++) {
4674                 struct bnxt_irq *irq = &bp->irq_tbl[i];
4675 #ifdef CONFIG_RFS_ACCEL
4676                 if (rmap && bp->bnapi[i]->rx_ring) {
4677                         rc = irq_cpu_rmap_add(rmap, irq->vector);
4678                         if (rc)
4679                                 netdev_warn(bp->dev, "failed adding irq rmap for ring %d\n",
4680                                             j);
4681                         j++;
4682                 }
4683 #endif
4684                 rc = request_irq(irq->vector, irq->handler, flags, irq->name,
4685                                  bp->bnapi[i]);
4686                 if (rc)
4687                         break;
4688
4689                 irq->requested = 1;
4690         }
4691         return rc;
4692 }
4693
4694 static void bnxt_del_napi(struct bnxt *bp)
4695 {
4696         int i;
4697
4698         if (!bp->bnapi)
4699                 return;
4700
4701         for (i = 0; i < bp->cp_nr_rings; i++) {
4702                 struct bnxt_napi *bnapi = bp->bnapi[i];
4703
4704                 napi_hash_del(&bnapi->napi);
4705                 netif_napi_del(&bnapi->napi);
4706         }
4707 }
4708
4709 static void bnxt_init_napi(struct bnxt *bp)
4710 {
4711         int i;
4712         struct bnxt_napi *bnapi;
4713
4714         if (bp->flags & BNXT_FLAG_USING_MSIX) {
4715                 for (i = 0; i < bp->cp_nr_rings; i++) {
4716                         bnapi = bp->bnapi[i];
4717                         netif_napi_add(bp->dev, &bnapi->napi,
4718                                        bnxt_poll, 64);
4719                 }
4720         } else {
4721                 bnapi = bp->bnapi[0];
4722                 netif_napi_add(bp->dev, &bnapi->napi, bnxt_poll, 64);
4723         }
4724 }
4725
4726 static void bnxt_disable_napi(struct bnxt *bp)
4727 {
4728         int i;
4729
4730         if (!bp->bnapi)
4731                 return;
4732
4733         for (i = 0; i < bp->cp_nr_rings; i++) {
4734                 napi_disable(&bp->bnapi[i]->napi);
4735                 bnxt_disable_poll(bp->bnapi[i]);
4736         }
4737 }
4738
4739 static void bnxt_enable_napi(struct bnxt *bp)
4740 {
4741         int i;
4742
4743         for (i = 0; i < bp->cp_nr_rings; i++) {
4744                 bp->bnapi[i]->in_reset = false;
4745                 bnxt_enable_poll(bp->bnapi[i]);
4746                 napi_enable(&bp->bnapi[i]->napi);
4747         }
4748 }
4749
4750 static void bnxt_tx_disable(struct bnxt *bp)
4751 {
4752         int i;
4753         struct bnxt_tx_ring_info *txr;
4754         struct netdev_queue *txq;
4755
4756         if (bp->tx_ring) {
4757                 for (i = 0; i < bp->tx_nr_rings; i++) {
4758                         txr = &bp->tx_ring[i];
4759                         txq = netdev_get_tx_queue(bp->dev, i);
4760                         __netif_tx_lock(txq, smp_processor_id());
4761                         txr->dev_state = BNXT_DEV_STATE_CLOSING;
4762                         __netif_tx_unlock(txq);
4763                 }
4764         }
4765         /* Stop all TX queues */
4766         netif_tx_disable(bp->dev);
4767         netif_carrier_off(bp->dev);
4768 }
4769
4770 static void bnxt_tx_enable(struct bnxt *bp)
4771 {
4772         int i;
4773         struct bnxt_tx_ring_info *txr;
4774         struct netdev_queue *txq;
4775
4776         for (i = 0; i < bp->tx_nr_rings; i++) {
4777                 txr = &bp->tx_ring[i];
4778                 txq = netdev_get_tx_queue(bp->dev, i);
4779                 txr->dev_state = 0;
4780         }
4781         netif_tx_wake_all_queues(bp->dev);
4782         if (bp->link_info.link_up)
4783                 netif_carrier_on(bp->dev);
4784 }
4785
4786 static void bnxt_report_link(struct bnxt *bp)
4787 {
4788         if (bp->link_info.link_up) {
4789                 const char *duplex;
4790                 const char *flow_ctrl;
4791                 u16 speed;
4792
4793                 netif_carrier_on(bp->dev);
4794                 if (bp->link_info.duplex == BNXT_LINK_DUPLEX_FULL)
4795                         duplex = "full";
4796                 else
4797                         duplex = "half";
4798                 if (bp->link_info.pause == BNXT_LINK_PAUSE_BOTH)
4799                         flow_ctrl = "ON - receive & transmit";
4800                 else if (bp->link_info.pause == BNXT_LINK_PAUSE_TX)
4801                         flow_ctrl = "ON - transmit";
4802                 else if (bp->link_info.pause == BNXT_LINK_PAUSE_RX)
4803                         flow_ctrl = "ON - receive";
4804                 else
4805                         flow_ctrl = "none";
4806                 speed = bnxt_fw_to_ethtool_speed(bp->link_info.link_speed);
4807                 netdev_info(bp->dev, "NIC Link is Up, %d Mbps %s duplex, Flow control: %s\n",
4808                             speed, duplex, flow_ctrl);
4809                 if (bp->flags & BNXT_FLAG_EEE_CAP)
4810                         netdev_info(bp->dev, "EEE is %s\n",
4811                                     bp->eee.eee_active ? "active" :
4812                                                          "not active");
4813         } else {
4814                 netif_carrier_off(bp->dev);
4815                 netdev_err(bp->dev, "NIC Link is Down\n");
4816         }
4817 }
4818
4819 static int bnxt_hwrm_phy_qcaps(struct bnxt *bp)
4820 {
4821         int rc = 0;
4822         struct hwrm_port_phy_qcaps_input req = {0};
4823         struct hwrm_port_phy_qcaps_output *resp = bp->hwrm_cmd_resp_addr;
4824         struct bnxt_link_info *link_info = &bp->link_info;
4825
4826         if (bp->hwrm_spec_code < 0x10201)
4827                 return 0;
4828
4829         bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_PORT_PHY_QCAPS, -1, -1);
4830
4831         mutex_lock(&bp->hwrm_cmd_lock);
4832         rc = _hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT);
4833         if (rc)
4834                 goto hwrm_phy_qcaps_exit;
4835
4836         if (resp->eee_supported & PORT_PHY_QCAPS_RESP_EEE_SUPPORTED) {
4837                 struct ethtool_eee *eee = &bp->eee;
4838                 u16 fw_speeds = le16_to_cpu(resp->supported_speeds_eee_mode);
4839
4840                 bp->flags |= BNXT_FLAG_EEE_CAP;
4841                 eee->supported = _bnxt_fw_to_ethtool_adv_spds(fw_speeds, 0);
4842                 bp->lpi_tmr_lo = le32_to_cpu(resp->tx_lpi_timer_low) &
4843                                  PORT_PHY_QCAPS_RESP_TX_LPI_TIMER_LOW_MASK;
4844                 bp->lpi_tmr_hi = le32_to_cpu(resp->valid_tx_lpi_timer_high) &
4845                                  PORT_PHY_QCAPS_RESP_TX_LPI_TIMER_HIGH_MASK;
4846         }
4847         link_info->support_auto_speeds =
4848                 le16_to_cpu(resp->supported_speeds_auto_mode);
4849
4850 hwrm_phy_qcaps_exit:
4851         mutex_unlock(&bp->hwrm_cmd_lock);
4852         return rc;
4853 }
4854
4855 static int bnxt_update_link(struct bnxt *bp, bool chng_link_state)
4856 {
4857         int rc = 0;
4858         struct bnxt_link_info *link_info = &bp->link_info;
4859         struct hwrm_port_phy_qcfg_input req = {0};
4860         struct hwrm_port_phy_qcfg_output *resp = bp->hwrm_cmd_resp_addr;
4861         u8 link_up = link_info->link_up;
4862
4863         bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_PORT_PHY_QCFG, -1, -1);
4864
4865         mutex_lock(&bp->hwrm_cmd_lock);
4866         rc = _hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT);
4867         if (rc) {
4868                 mutex_unlock(&bp->hwrm_cmd_lock);
4869                 return rc;
4870         }
4871
4872         memcpy(&link_info->phy_qcfg_resp, resp, sizeof(*resp));
4873         link_info->phy_link_status = resp->link;
4874         link_info->duplex =  resp->duplex;
4875         link_info->pause = resp->pause;
4876         link_info->auto_mode = resp->auto_mode;
4877         link_info->auto_pause_setting = resp->auto_pause;
4878         link_info->lp_pause = resp->link_partner_adv_pause;
4879         link_info->force_pause_setting = resp->force_pause;
4880         link_info->duplex_setting = resp->duplex;
4881         if (link_info->phy_link_status == BNXT_LINK_LINK)
4882                 link_info->link_speed = le16_to_cpu(resp->link_speed);
4883         else
4884                 link_info->link_speed = 0;
4885         link_info->force_link_speed = le16_to_cpu(resp->force_link_speed);
4886         link_info->support_speeds = le16_to_cpu(resp->support_speeds);
4887         link_info->auto_link_speeds = le16_to_cpu(resp->auto_link_speed_mask);
4888         link_info->lp_auto_link_speeds =
4889                 le16_to_cpu(resp->link_partner_adv_speeds);
4890         link_info->preemphasis = le32_to_cpu(resp->preemphasis);
4891         link_info->phy_ver[0] = resp->phy_maj;
4892         link_info->phy_ver[1] = resp->phy_min;
4893         link_info->phy_ver[2] = resp->phy_bld;
4894         link_info->media_type = resp->media_type;
4895         link_info->phy_type = resp->phy_type;
4896         link_info->transceiver = resp->xcvr_pkg_type;
4897         link_info->phy_addr = resp->eee_config_phy_addr &
4898                               PORT_PHY_QCFG_RESP_PHY_ADDR_MASK;
4899         link_info->module_status = resp->module_status;
4900
4901         if (bp->flags & BNXT_FLAG_EEE_CAP) {
4902                 struct ethtool_eee *eee = &bp->eee;
4903                 u16 fw_speeds;
4904
4905                 eee->eee_active = 0;
4906                 if (resp->eee_config_phy_addr &
4907                     PORT_PHY_QCFG_RESP_EEE_CONFIG_EEE_ACTIVE) {
4908                         eee->eee_active = 1;
4909                         fw_speeds = le16_to_cpu(
4910                                 resp->link_partner_adv_eee_link_speed_mask);
4911                         eee->lp_advertised =
4912                                 _bnxt_fw_to_ethtool_adv_spds(fw_speeds, 0);
4913                 }
4914
4915                 /* Pull initial EEE config */
4916                 if (!chng_link_state) {
4917                         if (resp->eee_config_phy_addr &
4918                             PORT_PHY_QCFG_RESP_EEE_CONFIG_EEE_ENABLED)
4919                                 eee->eee_enabled = 1;
4920
4921                         fw_speeds = le16_to_cpu(resp->adv_eee_link_speed_mask);
4922                         eee->advertised =
4923                                 _bnxt_fw_to_ethtool_adv_spds(fw_speeds, 0);
4924
4925                         if (resp->eee_config_phy_addr &
4926                             PORT_PHY_QCFG_RESP_EEE_CONFIG_EEE_TX_LPI) {
4927                                 __le32 tmr;
4928
4929                                 eee->tx_lpi_enabled = 1;
4930                                 tmr = resp->xcvr_identifier_type_tx_lpi_timer;
4931                                 eee->tx_lpi_timer = le32_to_cpu(tmr) &
4932                                         PORT_PHY_QCFG_RESP_TX_LPI_TIMER_MASK;
4933                         }
4934                 }
4935         }
4936         /* TODO: need to add more logic to report VF link */
4937         if (chng_link_state) {
4938                 if (link_info->phy_link_status == BNXT_LINK_LINK)
4939                         link_info->link_up = 1;
4940                 else
4941                         link_info->link_up = 0;
4942                 if (link_up != link_info->link_up)
4943                         bnxt_report_link(bp);
4944         } else {
4945                 /* alwasy link down if not require to update link state */
4946                 link_info->link_up = 0;
4947         }
4948         mutex_unlock(&bp->hwrm_cmd_lock);
4949         return 0;
4950 }
4951
4952 static void bnxt_get_port_module_status(struct bnxt *bp)
4953 {
4954         struct bnxt_link_info *link_info = &bp->link_info;
4955         struct hwrm_port_phy_qcfg_output *resp = &link_info->phy_qcfg_resp;
4956         u8 module_status;
4957
4958         if (bnxt_update_link(bp, true))
4959                 return;
4960
4961         module_status = link_info->module_status;
4962         switch (module_status) {
4963         case PORT_PHY_QCFG_RESP_MODULE_STATUS_DISABLETX:
4964         case PORT_PHY_QCFG_RESP_MODULE_STATUS_PWRDOWN:
4965         case PORT_PHY_QCFG_RESP_MODULE_STATUS_WARNINGMSG:
4966                 netdev_warn(bp->dev, "Unqualified SFP+ module detected on port %d\n",
4967                             bp->pf.port_id);
4968                 if (bp->hwrm_spec_code >= 0x10201) {
4969                         netdev_warn(bp->dev, "Module part number %s\n",
4970                                     resp->phy_vendor_partnumber);
4971                 }
4972                 if (module_status == PORT_PHY_QCFG_RESP_MODULE_STATUS_DISABLETX)
4973                         netdev_warn(bp->dev, "TX is disabled\n");
4974                 if (module_status == PORT_PHY_QCFG_RESP_MODULE_STATUS_PWRDOWN)
4975                         netdev_warn(bp->dev, "SFP+ module is shutdown\n");
4976         }
4977 }
4978
4979 static void
4980 bnxt_hwrm_set_pause_common(struct bnxt *bp, struct hwrm_port_phy_cfg_input *req)
4981 {
4982         if (bp->link_info.autoneg & BNXT_AUTONEG_FLOW_CTRL) {
4983                 if (bp->hwrm_spec_code >= 0x10201)
4984                         req->auto_pause =
4985                                 PORT_PHY_CFG_REQ_AUTO_PAUSE_AUTONEG_PAUSE;
4986                 if (bp->link_info.req_flow_ctrl & BNXT_LINK_PAUSE_RX)
4987                         req->auto_pause |= PORT_PHY_CFG_REQ_AUTO_PAUSE_RX;
4988                 if (bp->link_info.req_flow_ctrl & BNXT_LINK_PAUSE_TX)
4989                         req->auto_pause |= PORT_PHY_CFG_REQ_AUTO_PAUSE_TX;
4990                 req->enables |=
4991                         cpu_to_le32(PORT_PHY_CFG_REQ_ENABLES_AUTO_PAUSE);
4992         } else {
4993                 if (bp->link_info.req_flow_ctrl & BNXT_LINK_PAUSE_RX)
4994                         req->force_pause |= PORT_PHY_CFG_REQ_FORCE_PAUSE_RX;
4995                 if (bp->link_info.req_flow_ctrl & BNXT_LINK_PAUSE_TX)
4996                         req->force_pause |= PORT_PHY_CFG_REQ_FORCE_PAUSE_TX;
4997                 req->enables |=
4998                         cpu_to_le32(PORT_PHY_CFG_REQ_ENABLES_FORCE_PAUSE);
4999                 if (bp->hwrm_spec_code >= 0x10201) {
5000                         req->auto_pause = req->force_pause;
5001                         req->enables |= cpu_to_le32(
5002                                 PORT_PHY_CFG_REQ_ENABLES_AUTO_PAUSE);
5003                 }
5004         }
5005 }
5006
5007 static void bnxt_hwrm_set_link_common(struct bnxt *bp,
5008                                       struct hwrm_port_phy_cfg_input *req)
5009 {
5010         u8 autoneg = bp->link_info.autoneg;
5011         u16 fw_link_speed = bp->link_info.req_link_speed;
5012         u32 advertising = bp->link_info.advertising;
5013
5014         if (autoneg & BNXT_AUTONEG_SPEED) {
5015                 req->auto_mode |=
5016                         PORT_PHY_CFG_REQ_AUTO_MODE_SPEED_MASK;
5017
5018                 req->enables |= cpu_to_le32(
5019                         PORT_PHY_CFG_REQ_ENABLES_AUTO_LINK_SPEED_MASK);
5020                 req->auto_link_speed_mask = cpu_to_le16(advertising);
5021
5022                 req->enables |= cpu_to_le32(PORT_PHY_CFG_REQ_ENABLES_AUTO_MODE);
5023                 req->flags |=
5024                         cpu_to_le32(PORT_PHY_CFG_REQ_FLAGS_RESTART_AUTONEG);
5025         } else {
5026                 req->force_link_speed = cpu_to_le16(fw_link_speed);
5027                 req->flags |= cpu_to_le32(PORT_PHY_CFG_REQ_FLAGS_FORCE);
5028         }
5029
5030         /* tell chimp that the setting takes effect immediately */
5031         req->flags |= cpu_to_le32(PORT_PHY_CFG_REQ_FLAGS_RESET_PHY);
5032 }
5033
5034 int bnxt_hwrm_set_pause(struct bnxt *bp)
5035 {
5036         struct hwrm_port_phy_cfg_input req = {0};
5037         int rc;
5038
5039         bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_PORT_PHY_CFG, -1, -1);
5040         bnxt_hwrm_set_pause_common(bp, &req);
5041
5042         if ((bp->link_info.autoneg & BNXT_AUTONEG_FLOW_CTRL) ||
5043             bp->link_info.force_link_chng)
5044                 bnxt_hwrm_set_link_common(bp, &req);
5045
5046         mutex_lock(&bp->hwrm_cmd_lock);
5047         rc = _hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT);
5048         if (!rc && !(bp->link_info.autoneg & BNXT_AUTONEG_FLOW_CTRL)) {
5049                 /* since changing of pause setting doesn't trigger any link
5050                  * change event, the driver needs to update the current pause
5051                  * result upon successfully return of the phy_cfg command
5052                  */
5053                 bp->link_info.pause =
5054                 bp->link_info.force_pause_setting = bp->link_info.req_flow_ctrl;
5055                 bp->link_info.auto_pause_setting = 0;
5056                 if (!bp->link_info.force_link_chng)
5057                         bnxt_report_link(bp);
5058         }
5059         bp->link_info.force_link_chng = false;
5060         mutex_unlock(&bp->hwrm_cmd_lock);
5061         return rc;
5062 }
5063
5064 static void bnxt_hwrm_set_eee(struct bnxt *bp,
5065                               struct hwrm_port_phy_cfg_input *req)
5066 {
5067         struct ethtool_eee *eee = &bp->eee;
5068
5069         if (eee->eee_enabled) {
5070                 u16 eee_speeds;
5071                 u32 flags = PORT_PHY_CFG_REQ_FLAGS_EEE_ENABLE;
5072
5073                 if (eee->tx_lpi_enabled)
5074                         flags |= PORT_PHY_CFG_REQ_FLAGS_EEE_TX_LPI_ENABLE;
5075                 else
5076                         flags |= PORT_PHY_CFG_REQ_FLAGS_EEE_TX_LPI_DISABLE;
5077
5078                 req->flags |= cpu_to_le32(flags);
5079                 eee_speeds = bnxt_get_fw_auto_link_speeds(eee->advertised);
5080                 req->eee_link_speed_mask = cpu_to_le16(eee_speeds);
5081                 req->tx_lpi_timer = cpu_to_le32(eee->tx_lpi_timer);
5082         } else {
5083                 req->flags |= cpu_to_le32(PORT_PHY_CFG_REQ_FLAGS_EEE_DISABLE);
5084         }
5085 }
5086
5087 int bnxt_hwrm_set_link_setting(struct bnxt *bp, bool set_pause, bool set_eee)
5088 {
5089         struct hwrm_port_phy_cfg_input req = {0};
5090
5091         bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_PORT_PHY_CFG, -1, -1);
5092         if (set_pause)
5093                 bnxt_hwrm_set_pause_common(bp, &req);
5094
5095         bnxt_hwrm_set_link_common(bp, &req);
5096
5097         if (set_eee)
5098                 bnxt_hwrm_set_eee(bp, &req);
5099         return hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT);
5100 }
5101
5102 static int bnxt_hwrm_shutdown_link(struct bnxt *bp)
5103 {
5104         struct hwrm_port_phy_cfg_input req = {0};
5105
5106         if (!BNXT_SINGLE_PF(bp))
5107                 return 0;
5108
5109         if (pci_num_vf(bp->pdev))
5110                 return 0;
5111
5112         bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_PORT_PHY_CFG, -1, -1);
5113         req.flags = cpu_to_le32(PORT_PHY_CFG_REQ_FLAGS_FORCE_LINK_DOWN);
5114         return hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT);
5115 }
5116
5117 static bool bnxt_eee_config_ok(struct bnxt *bp)
5118 {
5119         struct ethtool_eee *eee = &bp->eee;
5120         struct bnxt_link_info *link_info = &bp->link_info;
5121
5122         if (!(bp->flags & BNXT_FLAG_EEE_CAP))
5123                 return true;
5124
5125         if (eee->eee_enabled) {
5126                 u32 advertising =
5127                         _bnxt_fw_to_ethtool_adv_spds(link_info->advertising, 0);
5128
5129                 if (!(link_info->autoneg & BNXT_AUTONEG_SPEED)) {
5130                         eee->eee_enabled = 0;
5131                         return false;
5132                 }
5133                 if (eee->advertised & ~advertising) {
5134                         eee->advertised = advertising & eee->supported;
5135                         return false;
5136                 }
5137         }
5138         return true;
5139 }
5140
5141 static int bnxt_update_phy_setting(struct bnxt *bp)
5142 {
5143         int rc;
5144         bool update_link = false;
5145         bool update_pause = false;
5146         bool update_eee = false;
5147         struct bnxt_link_info *link_info = &bp->link_info;
5148
5149         rc = bnxt_update_link(bp, true);
5150         if (rc) {
5151                 netdev_err(bp->dev, "failed to update link (rc: %x)\n",
5152                            rc);
5153                 return rc;
5154         }
5155         if ((link_info->autoneg & BNXT_AUTONEG_FLOW_CTRL) &&
5156             (link_info->auto_pause_setting & BNXT_LINK_PAUSE_BOTH) !=
5157             link_info->req_flow_ctrl)
5158                 update_pause = true;
5159         if (!(link_info->autoneg & BNXT_AUTONEG_FLOW_CTRL) &&
5160             link_info->force_pause_setting != link_info->req_flow_ctrl)
5161                 update_pause = true;
5162         if (!(link_info->autoneg & BNXT_AUTONEG_SPEED)) {
5163                 if (BNXT_AUTO_MODE(link_info->auto_mode))
5164                         update_link = true;
5165                 if (link_info->req_link_speed != link_info->force_link_speed)
5166                         update_link = true;
5167                 if (link_info->req_duplex != link_info->duplex_setting)
5168                         update_link = true;
5169         } else {
5170                 if (link_info->auto_mode == BNXT_LINK_AUTO_NONE)
5171                         update_link = true;
5172                 if (link_info->advertising != link_info->auto_link_speeds)
5173                         update_link = true;
5174         }
5175
5176         if (!bnxt_eee_config_ok(bp))
5177                 update_eee = true;
5178
5179         if (update_link)
5180                 rc = bnxt_hwrm_set_link_setting(bp, update_pause, update_eee);
5181         else if (update_pause)
5182                 rc = bnxt_hwrm_set_pause(bp);
5183         if (rc) {
5184                 netdev_err(bp->dev, "failed to update phy setting (rc: %x)\n",
5185                            rc);
5186                 return rc;
5187         }
5188
5189         return rc;
5190 }
5191
5192 /* Common routine to pre-map certain register block to different GRC window.
5193  * A PF has 16 4K windows and a VF has 4 4K windows. However, only 15 windows
5194  * in PF and 3 windows in VF that can be customized to map in different
5195  * register blocks.
5196  */
5197 static void bnxt_preset_reg_win(struct bnxt *bp)
5198 {
5199         if (BNXT_PF(bp)) {
5200                 /* CAG registers map to GRC window #4 */
5201                 writel(BNXT_CAG_REG_BASE,
5202                        bp->bar0 + BNXT_GRCPF_REG_WINDOW_BASE_OUT + 12);
5203         }
5204 }
5205
5206 static int __bnxt_open_nic(struct bnxt *bp, bool irq_re_init, bool link_re_init)
5207 {
5208         int rc = 0;
5209
5210         bnxt_preset_reg_win(bp);
5211         netif_carrier_off(bp->dev);
5212         if (irq_re_init) {
5213                 rc = bnxt_setup_int_mode(bp);
5214                 if (rc) {
5215                         netdev_err(bp->dev, "bnxt_setup_int_mode err: %x\n",
5216                                    rc);
5217                         return rc;
5218                 }
5219         }
5220         if ((bp->flags & BNXT_FLAG_RFS) &&
5221             !(bp->flags & BNXT_FLAG_USING_MSIX)) {
5222                 /* disable RFS if falling back to INTA */
5223                 bp->dev->hw_features &= ~NETIF_F_NTUPLE;
5224                 bp->flags &= ~BNXT_FLAG_RFS;
5225         }
5226
5227         rc = bnxt_alloc_mem(bp, irq_re_init);
5228         if (rc) {
5229                 netdev_err(bp->dev, "bnxt_alloc_mem err: %x\n", rc);
5230                 goto open_err_free_mem;
5231         }
5232
5233         if (irq_re_init) {
5234                 bnxt_init_napi(bp);
5235                 rc = bnxt_request_irq(bp);
5236                 if (rc) {
5237                         netdev_err(bp->dev, "bnxt_request_irq err: %x\n", rc);
5238                         goto open_err;
5239                 }
5240         }
5241
5242         bnxt_enable_napi(bp);
5243
5244         rc = bnxt_init_nic(bp, irq_re_init);
5245         if (rc) {
5246                 netdev_err(bp->dev, "bnxt_init_nic err: %x\n", rc);
5247                 goto open_err;
5248         }
5249
5250         if (link_re_init) {
5251                 rc = bnxt_update_phy_setting(bp);
5252                 if (rc)
5253                         netdev_warn(bp->dev, "failed to update phy settings\n");
5254         }
5255
5256         if (irq_re_init)
5257                 udp_tunnel_get_rx_info(bp->dev);
5258
5259         set_bit(BNXT_STATE_OPEN, &bp->state);
5260         bnxt_enable_int(bp);
5261         /* Enable TX queues */
5262         bnxt_tx_enable(bp);
5263         mod_timer(&bp->timer, jiffies + bp->current_interval);
5264         /* Poll link status and check for SFP+ module status */
5265         bnxt_get_port_module_status(bp);
5266
5267         return 0;
5268
5269 open_err:
5270         bnxt_disable_napi(bp);
5271         bnxt_del_napi(bp);
5272
5273 open_err_free_mem:
5274         bnxt_free_skbs(bp);
5275         bnxt_free_irq(bp);
5276         bnxt_free_mem(bp, true);
5277         return rc;
5278 }
5279
5280 /* rtnl_lock held */
5281 int bnxt_open_nic(struct bnxt *bp, bool irq_re_init, bool link_re_init)
5282 {
5283         int rc = 0;
5284
5285         rc = __bnxt_open_nic(bp, irq_re_init, link_re_init);
5286         if (rc) {
5287                 netdev_err(bp->dev, "nic open fail (rc: %x)\n", rc);
5288                 dev_close(bp->dev);
5289         }
5290         return rc;
5291 }
5292
5293 static int bnxt_open(struct net_device *dev)
5294 {
5295         struct bnxt *bp = netdev_priv(dev);
5296         int rc = 0;
5297
5298         if (!test_bit(BNXT_STATE_FN_RST_DONE, &bp->state)) {
5299                 rc = bnxt_hwrm_func_reset(bp);
5300                 if (rc) {
5301                         netdev_err(bp->dev, "hwrm chip reset failure rc: %x\n",
5302                                    rc);
5303                         rc = -EBUSY;
5304                         return rc;
5305                 }
5306                 /* Do func_reset during the 1st PF open only to prevent killing
5307                  * the VFs when the PF is brought down and up.
5308                  */
5309                 if (BNXT_PF(bp))
5310                         set_bit(BNXT_STATE_FN_RST_DONE, &bp->state);
5311         }
5312         return __bnxt_open_nic(bp, true, true);
5313 }
5314
5315 static void bnxt_disable_int_sync(struct bnxt *bp)
5316 {
5317         int i;
5318
5319         atomic_inc(&bp->intr_sem);
5320         if (!netif_running(bp->dev))
5321                 return;
5322
5323         bnxt_disable_int(bp);
5324         for (i = 0; i < bp->cp_nr_rings; i++)
5325                 synchronize_irq(bp->irq_tbl[i].vector);
5326 }
5327
5328 int bnxt_close_nic(struct bnxt *bp, bool irq_re_init, bool link_re_init)
5329 {
5330         int rc = 0;
5331
5332 #ifdef CONFIG_BNXT_SRIOV
5333         if (bp->sriov_cfg) {
5334                 rc = wait_event_interruptible_timeout(bp->sriov_cfg_wait,
5335                                                       !bp->sriov_cfg,
5336                                                       BNXT_SRIOV_CFG_WAIT_TMO);
5337                 if (rc)
5338                         netdev_warn(bp->dev, "timeout waiting for SRIOV config operation to complete!\n");
5339         }
5340 #endif
5341         /* Change device state to avoid TX queue wake up's */
5342         bnxt_tx_disable(bp);
5343
5344         clear_bit(BNXT_STATE_OPEN, &bp->state);
5345         smp_mb__after_atomic();
5346         while (test_bit(BNXT_STATE_IN_SP_TASK, &bp->state))
5347                 msleep(20);
5348
5349         /* Flush rings before disabling interrupts */
5350         bnxt_shutdown_nic(bp, irq_re_init);
5351
5352         /* TODO CHIMP_FW: Link/PHY related cleanup if (link_re_init) */
5353
5354         bnxt_disable_napi(bp);
5355         bnxt_disable_int_sync(bp);
5356         del_timer_sync(&bp->timer);
5357         bnxt_free_skbs(bp);
5358
5359         if (irq_re_init) {
5360                 bnxt_free_irq(bp);
5361                 bnxt_del_napi(bp);
5362         }
5363         bnxt_free_mem(bp, irq_re_init);
5364         return rc;
5365 }
5366
5367 static int bnxt_close(struct net_device *dev)
5368 {
5369         struct bnxt *bp = netdev_priv(dev);
5370
5371         bnxt_close_nic(bp, true, true);
5372         bnxt_hwrm_shutdown_link(bp);
5373         return 0;
5374 }
5375
5376 /* rtnl_lock held */
5377 static int bnxt_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd)
5378 {
5379         switch (cmd) {
5380         case SIOCGMIIPHY:
5381                 /* fallthru */
5382         case SIOCGMIIREG: {
5383                 if (!netif_running(dev))
5384                         return -EAGAIN;
5385
5386                 return 0;
5387         }
5388
5389         case SIOCSMIIREG:
5390                 if (!netif_running(dev))
5391                         return -EAGAIN;
5392
5393                 return 0;
5394
5395         default:
5396                 /* do nothing */
5397                 break;
5398         }
5399         return -EOPNOTSUPP;
5400 }
5401
5402 static struct rtnl_link_stats64 *
5403 bnxt_get_stats64(struct net_device *dev, struct rtnl_link_stats64 *stats)
5404 {
5405         u32 i;
5406         struct bnxt *bp = netdev_priv(dev);
5407
5408         memset(stats, 0, sizeof(struct rtnl_link_stats64));
5409
5410         if (!bp->bnapi)
5411                 return stats;
5412
5413         /* TODO check if we need to synchronize with bnxt_close path */
5414         for (i = 0; i < bp->cp_nr_rings; i++) {
5415                 struct bnxt_napi *bnapi = bp->bnapi[i];
5416                 struct bnxt_cp_ring_info *cpr = &bnapi->cp_ring;
5417                 struct ctx_hw_stats *hw_stats = cpr->hw_stats;
5418
5419                 stats->rx_packets += le64_to_cpu(hw_stats->rx_ucast_pkts);
5420                 stats->rx_packets += le64_to_cpu(hw_stats->rx_mcast_pkts);
5421                 stats->rx_packets += le64_to_cpu(hw_stats->rx_bcast_pkts);
5422
5423                 stats->tx_packets += le64_to_cpu(hw_stats->tx_ucast_pkts);
5424                 stats->tx_packets += le64_to_cpu(hw_stats->tx_mcast_pkts);
5425                 stats->tx_packets += le64_to_cpu(hw_stats->tx_bcast_pkts);
5426
5427                 stats->rx_bytes += le64_to_cpu(hw_stats->rx_ucast_bytes);
5428                 stats->rx_bytes += le64_to_cpu(hw_stats->rx_mcast_bytes);
5429                 stats->rx_bytes += le64_to_cpu(hw_stats->rx_bcast_bytes);
5430
5431                 stats->tx_bytes += le64_to_cpu(hw_stats->tx_ucast_bytes);
5432                 stats->tx_bytes += le64_to_cpu(hw_stats->tx_mcast_bytes);
5433                 stats->tx_bytes += le64_to_cpu(hw_stats->tx_bcast_bytes);
5434
5435                 stats->rx_missed_errors +=
5436                         le64_to_cpu(hw_stats->rx_discard_pkts);
5437
5438                 stats->multicast += le64_to_cpu(hw_stats->rx_mcast_pkts);
5439
5440                 stats->tx_dropped += le64_to_cpu(hw_stats->tx_drop_pkts);
5441         }
5442
5443         if (bp->flags & BNXT_FLAG_PORT_STATS) {
5444                 struct rx_port_stats *rx = bp->hw_rx_port_stats;
5445                 struct tx_port_stats *tx = bp->hw_tx_port_stats;
5446
5447                 stats->rx_crc_errors = le64_to_cpu(rx->rx_fcs_err_frames);
5448                 stats->rx_frame_errors = le64_to_cpu(rx->rx_align_err_frames);
5449                 stats->rx_length_errors = le64_to_cpu(rx->rx_undrsz_frames) +
5450                                           le64_to_cpu(rx->rx_ovrsz_frames) +
5451                                           le64_to_cpu(rx->rx_runt_frames);
5452                 stats->rx_errors = le64_to_cpu(rx->rx_false_carrier_frames) +
5453                                    le64_to_cpu(rx->rx_jbr_frames);
5454                 stats->collisions = le64_to_cpu(tx->tx_total_collisions);
5455                 stats->tx_fifo_errors = le64_to_cpu(tx->tx_fifo_underruns);
5456                 stats->tx_errors = le64_to_cpu(tx->tx_err);
5457         }
5458
5459         return stats;
5460 }
5461
5462 static bool bnxt_mc_list_updated(struct bnxt *bp, u32 *rx_mask)
5463 {
5464         struct net_device *dev = bp->dev;
5465         struct bnxt_vnic_info *vnic = &bp->vnic_info[0];
5466         struct netdev_hw_addr *ha;
5467         u8 *haddr;
5468         int mc_count = 0;
5469         bool update = false;
5470         int off = 0;
5471
5472         netdev_for_each_mc_addr(ha, dev) {
5473                 if (mc_count >= BNXT_MAX_MC_ADDRS) {
5474                         *rx_mask |= CFA_L2_SET_RX_MASK_REQ_MASK_ALL_MCAST;
5475                         vnic->mc_list_count = 0;
5476                         return false;
5477                 }
5478                 haddr = ha->addr;
5479                 if (!ether_addr_equal(haddr, vnic->mc_list + off)) {
5480                         memcpy(vnic->mc_list + off, haddr, ETH_ALEN);
5481                         update = true;
5482                 }
5483                 off += ETH_ALEN;
5484                 mc_count++;
5485         }
5486         if (mc_count)
5487                 *rx_mask |= CFA_L2_SET_RX_MASK_REQ_MASK_MCAST;
5488
5489         if (mc_count != vnic->mc_list_count) {
5490                 vnic->mc_list_count = mc_count;
5491                 update = true;
5492         }
5493         return update;
5494 }
5495
5496 static bool bnxt_uc_list_updated(struct bnxt *bp)
5497 {
5498         struct net_device *dev = bp->dev;
5499         struct bnxt_vnic_info *vnic = &bp->vnic_info[0];
5500         struct netdev_hw_addr *ha;
5501         int off = 0;
5502
5503         if (netdev_uc_count(dev) != (vnic->uc_filter_count - 1))
5504                 return true;
5505
5506         netdev_for_each_uc_addr(ha, dev) {
5507                 if (!ether_addr_equal(ha->addr, vnic->uc_list + off))
5508                         return true;
5509
5510                 off += ETH_ALEN;
5511         }
5512         return false;
5513 }
5514
5515 static void bnxt_set_rx_mode(struct net_device *dev)
5516 {
5517         struct bnxt *bp = netdev_priv(dev);
5518         struct bnxt_vnic_info *vnic = &bp->vnic_info[0];
5519         u32 mask = vnic->rx_mask;
5520         bool mc_update = false;
5521         bool uc_update;
5522
5523         if (!netif_running(dev))
5524                 return;
5525
5526         mask &= ~(CFA_L2_SET_RX_MASK_REQ_MASK_PROMISCUOUS |
5527                   CFA_L2_SET_RX_MASK_REQ_MASK_MCAST |
5528                   CFA_L2_SET_RX_MASK_REQ_MASK_ALL_MCAST);
5529
5530         /* Only allow PF to be in promiscuous mode */
5531         if ((dev->flags & IFF_PROMISC) && BNXT_PF(bp))
5532                 mask |= CFA_L2_SET_RX_MASK_REQ_MASK_PROMISCUOUS;
5533
5534         uc_update = bnxt_uc_list_updated(bp);
5535
5536         if (dev->flags & IFF_ALLMULTI) {
5537                 mask |= CFA_L2_SET_RX_MASK_REQ_MASK_ALL_MCAST;
5538                 vnic->mc_list_count = 0;
5539         } else {
5540                 mc_update = bnxt_mc_list_updated(bp, &mask);
5541         }
5542
5543         if (mask != vnic->rx_mask || uc_update || mc_update) {
5544                 vnic->rx_mask = mask;
5545
5546                 set_bit(BNXT_RX_MASK_SP_EVENT, &bp->sp_event);
5547                 schedule_work(&bp->sp_task);
5548         }
5549 }
5550
5551 static int bnxt_cfg_rx_mode(struct bnxt *bp)
5552 {
5553         struct net_device *dev = bp->dev;
5554         struct bnxt_vnic_info *vnic = &bp->vnic_info[0];
5555         struct netdev_hw_addr *ha;
5556         int i, off = 0, rc;
5557         bool uc_update;
5558
5559         netif_addr_lock_bh(dev);
5560         uc_update = bnxt_uc_list_updated(bp);
5561         netif_addr_unlock_bh(dev);
5562
5563         if (!uc_update)
5564                 goto skip_uc;
5565
5566         mutex_lock(&bp->hwrm_cmd_lock);
5567         for (i = 1; i < vnic->uc_filter_count; i++) {
5568                 struct hwrm_cfa_l2_filter_free_input req = {0};
5569
5570                 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_CFA_L2_FILTER_FREE, -1,
5571                                        -1);
5572
5573                 req.l2_filter_id = vnic->fw_l2_filter_id[i];
5574
5575                 rc = _hwrm_send_message(bp, &req, sizeof(req),
5576                                         HWRM_CMD_TIMEOUT);
5577         }
5578         mutex_unlock(&bp->hwrm_cmd_lock);
5579
5580         vnic->uc_filter_count = 1;
5581
5582         netif_addr_lock_bh(dev);
5583         if (netdev_uc_count(dev) > (BNXT_MAX_UC_ADDRS - 1)) {
5584                 vnic->rx_mask |= CFA_L2_SET_RX_MASK_REQ_MASK_PROMISCUOUS;
5585         } else {
5586                 netdev_for_each_uc_addr(ha, dev) {
5587                         memcpy(vnic->uc_list + off, ha->addr, ETH_ALEN);
5588                         off += ETH_ALEN;
5589                         vnic->uc_filter_count++;
5590                 }
5591         }
5592         netif_addr_unlock_bh(dev);
5593
5594         for (i = 1, off = 0; i < vnic->uc_filter_count; i++, off += ETH_ALEN) {
5595                 rc = bnxt_hwrm_set_vnic_filter(bp, 0, i, vnic->uc_list + off);
5596                 if (rc) {
5597                         netdev_err(bp->dev, "HWRM vnic filter failure rc: %x\n",
5598                                    rc);
5599                         vnic->uc_filter_count = i;
5600                         return rc;
5601                 }
5602         }
5603
5604 skip_uc:
5605         rc = bnxt_hwrm_cfa_l2_set_rx_mask(bp, 0);
5606         if (rc)
5607                 netdev_err(bp->dev, "HWRM cfa l2 rx mask failure rc: %x\n",
5608                            rc);
5609
5610         return rc;
5611 }
5612
5613 static bool bnxt_rfs_capable(struct bnxt *bp)
5614 {
5615 #ifdef CONFIG_RFS_ACCEL
5616         struct bnxt_pf_info *pf = &bp->pf;
5617         int vnics;
5618
5619         if (BNXT_VF(bp) || !(bp->flags & BNXT_FLAG_MSIX_CAP))
5620                 return false;
5621
5622         vnics = 1 + bp->rx_nr_rings;
5623         if (vnics > pf->max_rsscos_ctxs || vnics > pf->max_vnics)
5624                 return false;
5625
5626         return true;
5627 #else
5628         return false;
5629 #endif
5630 }
5631
5632 static netdev_features_t bnxt_fix_features(struct net_device *dev,
5633                                            netdev_features_t features)
5634 {
5635         struct bnxt *bp = netdev_priv(dev);
5636
5637         if (!bnxt_rfs_capable(bp))
5638                 features &= ~NETIF_F_NTUPLE;
5639
5640         /* Both CTAG and STAG VLAN accelaration on the RX side have to be
5641          * turned on or off together.
5642          */
5643         if ((features & (NETIF_F_HW_VLAN_CTAG_RX | NETIF_F_HW_VLAN_STAG_RX)) !=
5644             (NETIF_F_HW_VLAN_CTAG_RX | NETIF_F_HW_VLAN_STAG_RX)) {
5645                 if (dev->features & NETIF_F_HW_VLAN_CTAG_RX)
5646                         features &= ~(NETIF_F_HW_VLAN_CTAG_RX |
5647                                       NETIF_F_HW_VLAN_STAG_RX);
5648                 else
5649                         features |= NETIF_F_HW_VLAN_CTAG_RX |
5650                                     NETIF_F_HW_VLAN_STAG_RX;
5651         }
5652 #ifdef CONFIG_BNXT_SRIOV
5653         if (BNXT_VF(bp)) {
5654                 if (bp->vf.vlan) {
5655                         features &= ~(NETIF_F_HW_VLAN_CTAG_RX |
5656                                       NETIF_F_HW_VLAN_STAG_RX);
5657                 }
5658         }
5659 #endif
5660         return features;
5661 }
5662
5663 static int bnxt_set_features(struct net_device *dev, netdev_features_t features)
5664 {
5665         struct bnxt *bp = netdev_priv(dev);
5666         u32 flags = bp->flags;
5667         u32 changes;
5668         int rc = 0;
5669         bool re_init = false;
5670         bool update_tpa = false;
5671
5672         flags &= ~BNXT_FLAG_ALL_CONFIG_FEATS;
5673         if ((features & NETIF_F_GRO) && (bp->pdev->revision > 0))
5674                 flags |= BNXT_FLAG_GRO;
5675         if (features & NETIF_F_LRO)
5676                 flags |= BNXT_FLAG_LRO;
5677
5678         if (features & NETIF_F_HW_VLAN_CTAG_RX)
5679                 flags |= BNXT_FLAG_STRIP_VLAN;
5680
5681         if (features & NETIF_F_NTUPLE)
5682                 flags |= BNXT_FLAG_RFS;
5683
5684         changes = flags ^ bp->flags;
5685         if (changes & BNXT_FLAG_TPA) {
5686                 update_tpa = true;
5687                 if ((bp->flags & BNXT_FLAG_TPA) == 0 ||
5688                     (flags & BNXT_FLAG_TPA) == 0)
5689                         re_init = true;
5690         }
5691
5692         if (changes & ~BNXT_FLAG_TPA)
5693                 re_init = true;
5694
5695         if (flags != bp->flags) {
5696                 u32 old_flags = bp->flags;
5697
5698                 bp->flags = flags;
5699
5700                 if (!test_bit(BNXT_STATE_OPEN, &bp->state)) {
5701                         if (update_tpa)
5702                                 bnxt_set_ring_params(bp);
5703                         return rc;
5704                 }
5705
5706                 if (re_init) {
5707                         bnxt_close_nic(bp, false, false);
5708                         if (update_tpa)
5709                                 bnxt_set_ring_params(bp);
5710
5711                         return bnxt_open_nic(bp, false, false);
5712                 }
5713                 if (update_tpa) {
5714                         rc = bnxt_set_tpa(bp,
5715                                           (flags & BNXT_FLAG_TPA) ?
5716                                           true : false);
5717                         if (rc)
5718                                 bp->flags = old_flags;
5719                 }
5720         }
5721         return rc;
5722 }
5723
5724 static void bnxt_dump_tx_sw_state(struct bnxt_napi *bnapi)
5725 {
5726         struct bnxt_tx_ring_info *txr = bnapi->tx_ring;
5727         int i = bnapi->index;
5728
5729         if (!txr)
5730                 return;
5731
5732         netdev_info(bnapi->bp->dev, "[%d]: tx{fw_ring: %d prod: %x cons: %x}\n",
5733                     i, txr->tx_ring_struct.fw_ring_id, txr->tx_prod,
5734                     txr->tx_cons);
5735 }
5736
5737 static void bnxt_dump_rx_sw_state(struct bnxt_napi *bnapi)
5738 {
5739         struct bnxt_rx_ring_info *rxr = bnapi->rx_ring;
5740         int i = bnapi->index;
5741
5742         if (!rxr)
5743                 return;
5744
5745         netdev_info(bnapi->bp->dev, "[%d]: rx{fw_ring: %d prod: %x} rx_agg{fw_ring: %d agg_prod: %x sw_agg_prod: %x}\n",
5746                     i, rxr->rx_ring_struct.fw_ring_id, rxr->rx_prod,
5747                     rxr->rx_agg_ring_struct.fw_ring_id, rxr->rx_agg_prod,
5748                     rxr->rx_sw_agg_prod);
5749 }
5750
5751 static void bnxt_dump_cp_sw_state(struct bnxt_napi *bnapi)
5752 {
5753         struct bnxt_cp_ring_info *cpr = &bnapi->cp_ring;
5754         int i = bnapi->index;
5755
5756         netdev_info(bnapi->bp->dev, "[%d]: cp{fw_ring: %d raw_cons: %x}\n",
5757                     i, cpr->cp_ring_struct.fw_ring_id, cpr->cp_raw_cons);
5758 }
5759
5760 static void bnxt_dbg_dump_states(struct bnxt *bp)
5761 {
5762         int i;
5763         struct bnxt_napi *bnapi;
5764
5765         for (i = 0; i < bp->cp_nr_rings; i++) {
5766                 bnapi = bp->bnapi[i];
5767                 if (netif_msg_drv(bp)) {
5768                         bnxt_dump_tx_sw_state(bnapi);
5769                         bnxt_dump_rx_sw_state(bnapi);
5770                         bnxt_dump_cp_sw_state(bnapi);
5771                 }
5772         }
5773 }
5774
5775 static void bnxt_reset_task(struct bnxt *bp, bool silent)
5776 {
5777         if (!silent)
5778                 bnxt_dbg_dump_states(bp);
5779         if (netif_running(bp->dev)) {
5780                 bnxt_close_nic(bp, false, false);
5781                 bnxt_open_nic(bp, false, false);
5782         }
5783 }
5784
5785 static void bnxt_tx_timeout(struct net_device *dev)
5786 {
5787         struct bnxt *bp = netdev_priv(dev);
5788
5789         netdev_err(bp->dev,  "TX timeout detected, starting reset task!\n");
5790         set_bit(BNXT_RESET_TASK_SP_EVENT, &bp->sp_event);
5791         schedule_work(&bp->sp_task);
5792 }
5793
5794 #ifdef CONFIG_NET_POLL_CONTROLLER
5795 static void bnxt_poll_controller(struct net_device *dev)
5796 {
5797         struct bnxt *bp = netdev_priv(dev);
5798         int i;
5799
5800         for (i = 0; i < bp->cp_nr_rings; i++) {
5801                 struct bnxt_irq *irq = &bp->irq_tbl[i];
5802
5803                 disable_irq(irq->vector);
5804                 irq->handler(irq->vector, bp->bnapi[i]);
5805                 enable_irq(irq->vector);
5806         }
5807 }
5808 #endif
5809
5810 static void bnxt_timer(unsigned long data)
5811 {
5812         struct bnxt *bp = (struct bnxt *)data;
5813         struct net_device *dev = bp->dev;
5814
5815         if (!netif_running(dev))
5816                 return;
5817
5818         if (atomic_read(&bp->intr_sem) != 0)
5819                 goto bnxt_restart_timer;
5820
5821         if (bp->link_info.link_up && (bp->flags & BNXT_FLAG_PORT_STATS)) {
5822                 set_bit(BNXT_PERIODIC_STATS_SP_EVENT, &bp->sp_event);
5823                 schedule_work(&bp->sp_task);
5824         }
5825 bnxt_restart_timer:
5826         mod_timer(&bp->timer, jiffies + bp->current_interval);
5827 }
5828
5829 /* Only called from bnxt_sp_task() */
5830 static void bnxt_reset(struct bnxt *bp, bool silent)
5831 {
5832         /* bnxt_reset_task() calls bnxt_close_nic() which waits
5833          * for BNXT_STATE_IN_SP_TASK to clear.
5834          * If there is a parallel dev_close(), bnxt_close() may be holding
5835          * rtnl() and waiting for BNXT_STATE_IN_SP_TASK to clear.  So we
5836          * must clear BNXT_STATE_IN_SP_TASK before holding rtnl().
5837          */
5838         clear_bit(BNXT_STATE_IN_SP_TASK, &bp->state);
5839         rtnl_lock();
5840         if (test_bit(BNXT_STATE_OPEN, &bp->state))
5841                 bnxt_reset_task(bp, silent);
5842         set_bit(BNXT_STATE_IN_SP_TASK, &bp->state);
5843         rtnl_unlock();
5844 }
5845
5846 static void bnxt_cfg_ntp_filters(struct bnxt *);
5847
5848 static void bnxt_sp_task(struct work_struct *work)
5849 {
5850         struct bnxt *bp = container_of(work, struct bnxt, sp_task);
5851         int rc;
5852
5853         set_bit(BNXT_STATE_IN_SP_TASK, &bp->state);
5854         smp_mb__after_atomic();
5855         if (!test_bit(BNXT_STATE_OPEN, &bp->state)) {
5856                 clear_bit(BNXT_STATE_IN_SP_TASK, &bp->state);
5857                 return;
5858         }
5859
5860         if (test_and_clear_bit(BNXT_RX_MASK_SP_EVENT, &bp->sp_event))
5861                 bnxt_cfg_rx_mode(bp);
5862
5863         if (test_and_clear_bit(BNXT_RX_NTP_FLTR_SP_EVENT, &bp->sp_event))
5864                 bnxt_cfg_ntp_filters(bp);
5865         if (test_and_clear_bit(BNXT_LINK_CHNG_SP_EVENT, &bp->sp_event)) {
5866                 rc = bnxt_update_link(bp, true);
5867                 if (rc)
5868                         netdev_err(bp->dev, "SP task can't update link (rc: %x)\n",
5869                                    rc);
5870         }
5871         if (test_and_clear_bit(BNXT_HWRM_EXEC_FWD_REQ_SP_EVENT, &bp->sp_event))
5872                 bnxt_hwrm_exec_fwd_req(bp);
5873         if (test_and_clear_bit(BNXT_VXLAN_ADD_PORT_SP_EVENT, &bp->sp_event)) {
5874                 bnxt_hwrm_tunnel_dst_port_alloc(
5875                         bp, bp->vxlan_port,
5876                         TUNNEL_DST_PORT_FREE_REQ_TUNNEL_TYPE_VXLAN);
5877         }
5878         if (test_and_clear_bit(BNXT_VXLAN_DEL_PORT_SP_EVENT, &bp->sp_event)) {
5879                 bnxt_hwrm_tunnel_dst_port_free(
5880                         bp, TUNNEL_DST_PORT_FREE_REQ_TUNNEL_TYPE_VXLAN);
5881         }
5882         if (test_and_clear_bit(BNXT_GENEVE_ADD_PORT_SP_EVENT, &bp->sp_event)) {
5883                 bnxt_hwrm_tunnel_dst_port_alloc(
5884                         bp, bp->nge_port,
5885                         TUNNEL_DST_PORT_FREE_REQ_TUNNEL_TYPE_GENEVE);
5886         }
5887         if (test_and_clear_bit(BNXT_GENEVE_DEL_PORT_SP_EVENT, &bp->sp_event)) {
5888                 bnxt_hwrm_tunnel_dst_port_free(
5889                         bp, TUNNEL_DST_PORT_FREE_REQ_TUNNEL_TYPE_GENEVE);
5890         }
5891         if (test_and_clear_bit(BNXT_RESET_TASK_SP_EVENT, &bp->sp_event))
5892                 bnxt_reset(bp, false);
5893
5894         if (test_and_clear_bit(BNXT_RESET_TASK_SILENT_SP_EVENT, &bp->sp_event))
5895                 bnxt_reset(bp, true);
5896
5897         if (test_and_clear_bit(BNXT_HWRM_PORT_MODULE_SP_EVENT, &bp->sp_event))
5898                 bnxt_get_port_module_status(bp);
5899
5900         if (test_and_clear_bit(BNXT_PERIODIC_STATS_SP_EVENT, &bp->sp_event))
5901                 bnxt_hwrm_port_qstats(bp);
5902
5903         smp_mb__before_atomic();
5904         clear_bit(BNXT_STATE_IN_SP_TASK, &bp->state);
5905 }
5906
5907 static int bnxt_init_board(struct pci_dev *pdev, struct net_device *dev)
5908 {
5909         int rc;
5910         struct bnxt *bp = netdev_priv(dev);
5911
5912         SET_NETDEV_DEV(dev, &pdev->dev);
5913
5914         /* enable device (incl. PCI PM wakeup), and bus-mastering */
5915         rc = pci_enable_device(pdev);
5916         if (rc) {
5917                 dev_err(&pdev->dev, "Cannot enable PCI device, aborting\n");
5918                 goto init_err;
5919         }
5920
5921         if (!(pci_resource_flags(pdev, 0) & IORESOURCE_MEM)) {
5922                 dev_err(&pdev->dev,
5923                         "Cannot find PCI device base address, aborting\n");
5924                 rc = -ENODEV;
5925                 goto init_err_disable;
5926         }
5927
5928         rc = pci_request_regions(pdev, DRV_MODULE_NAME);
5929         if (rc) {
5930                 dev_err(&pdev->dev, "Cannot obtain PCI resources, aborting\n");
5931                 goto init_err_disable;
5932         }
5933
5934         if (dma_set_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(64)) != 0 &&
5935             dma_set_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(32)) != 0) {
5936                 dev_err(&pdev->dev, "System does not support DMA, aborting\n");
5937                 goto init_err_disable;
5938         }
5939
5940         pci_set_master(pdev);
5941
5942         bp->dev = dev;
5943         bp->pdev = pdev;
5944
5945         bp->bar0 = pci_ioremap_bar(pdev, 0);
5946         if (!bp->bar0) {
5947                 dev_err(&pdev->dev, "Cannot map device registers, aborting\n");
5948                 rc = -ENOMEM;
5949                 goto init_err_release;
5950         }
5951
5952         bp->bar1 = pci_ioremap_bar(pdev, 2);
5953         if (!bp->bar1) {
5954                 dev_err(&pdev->dev, "Cannot map doorbell registers, aborting\n");
5955                 rc = -ENOMEM;
5956                 goto init_err_release;
5957         }
5958
5959         bp->bar2 = pci_ioremap_bar(pdev, 4);
5960         if (!bp->bar2) {
5961                 dev_err(&pdev->dev, "Cannot map bar4 registers, aborting\n");
5962                 rc = -ENOMEM;
5963                 goto init_err_release;
5964         }
5965
5966         pci_enable_pcie_error_reporting(pdev);
5967
5968         INIT_WORK(&bp->sp_task, bnxt_sp_task);
5969
5970         spin_lock_init(&bp->ntp_fltr_lock);
5971
5972         bp->rx_ring_size = BNXT_DEFAULT_RX_RING_SIZE;
5973         bp->tx_ring_size = BNXT_DEFAULT_TX_RING_SIZE;
5974
5975         /* tick values in micro seconds */
5976         bp->rx_coal_ticks = 12;
5977         bp->rx_coal_bufs = 30;
5978         bp->rx_coal_ticks_irq = 1;
5979         bp->rx_coal_bufs_irq = 2;
5980
5981         bp->tx_coal_ticks = 25;
5982         bp->tx_coal_bufs = 30;
5983         bp->tx_coal_ticks_irq = 2;
5984         bp->tx_coal_bufs_irq = 2;
5985
5986         init_timer(&bp->timer);
5987         bp->timer.data = (unsigned long)bp;
5988         bp->timer.function = bnxt_timer;
5989         bp->current_interval = BNXT_TIMER_INTERVAL;
5990
5991         clear_bit(BNXT_STATE_OPEN, &bp->state);
5992
5993         return 0;
5994
5995 init_err_release:
5996         if (bp->bar2) {
5997                 pci_iounmap(pdev, bp->bar2);
5998                 bp->bar2 = NULL;
5999         }
6000
6001         if (bp->bar1) {
6002                 pci_iounmap(pdev, bp->bar1);
6003                 bp->bar1 = NULL;
6004         }
6005
6006         if (bp->bar0) {
6007                 pci_iounmap(pdev, bp->bar0);
6008                 bp->bar0 = NULL;
6009         }
6010
6011         pci_release_regions(pdev);
6012
6013 init_err_disable:
6014         pci_disable_device(pdev);
6015
6016 init_err:
6017         return rc;
6018 }
6019
6020 /* rtnl_lock held */
6021 static int bnxt_change_mac_addr(struct net_device *dev, void *p)
6022 {
6023         struct sockaddr *addr = p;
6024         struct bnxt *bp = netdev_priv(dev);
6025         int rc = 0;
6026
6027         if (!is_valid_ether_addr(addr->sa_data))
6028                 return -EADDRNOTAVAIL;
6029
6030         rc = bnxt_approve_mac(bp, addr->sa_data);
6031         if (rc)
6032                 return rc;
6033
6034         if (ether_addr_equal(addr->sa_data, dev->dev_addr))
6035                 return 0;
6036
6037         memcpy(dev->dev_addr, addr->sa_data, dev->addr_len);
6038         if (netif_running(dev)) {
6039                 bnxt_close_nic(bp, false, false);
6040                 rc = bnxt_open_nic(bp, false, false);
6041         }
6042
6043         return rc;
6044 }
6045
6046 /* rtnl_lock held */
6047 static int bnxt_change_mtu(struct net_device *dev, int new_mtu)
6048 {
6049         struct bnxt *bp = netdev_priv(dev);
6050
6051         if (new_mtu < 60 || new_mtu > 9000)
6052                 return -EINVAL;
6053
6054         if (netif_running(dev))
6055                 bnxt_close_nic(bp, false, false);
6056
6057         dev->mtu = new_mtu;
6058         bnxt_set_ring_params(bp);
6059
6060         if (netif_running(dev))
6061                 return bnxt_open_nic(bp, false, false);
6062
6063         return 0;
6064 }
6065
6066 static int bnxt_setup_tc(struct net_device *dev, u32 handle, __be16 proto,
6067                          struct tc_to_netdev *ntc)
6068 {
6069         struct bnxt *bp = netdev_priv(dev);
6070         u8 tc;
6071
6072         if (ntc->type != TC_SETUP_MQPRIO)
6073                 return -EINVAL;
6074
6075         tc = ntc->tc;
6076
6077         if (tc > bp->max_tc) {
6078                 netdev_err(dev, "too many traffic classes requested: %d Max supported is %d\n",
6079                            tc, bp->max_tc);
6080                 return -EINVAL;
6081         }
6082
6083         if (netdev_get_num_tc(dev) == tc)
6084                 return 0;
6085
6086         if (tc) {
6087                 int max_rx_rings, max_tx_rings, rc;
6088                 bool sh = false;
6089
6090                 if (bp->flags & BNXT_FLAG_SHARED_RINGS)
6091                         sh = true;
6092
6093                 rc = bnxt_get_max_rings(bp, &max_rx_rings, &max_tx_rings, sh);
6094                 if (rc || bp->tx_nr_rings_per_tc * tc > max_tx_rings)
6095                         return -ENOMEM;
6096         }
6097
6098         /* Needs to close the device and do hw resource re-allocations */
6099         if (netif_running(bp->dev))
6100                 bnxt_close_nic(bp, true, false);
6101
6102         if (tc) {
6103                 bp->tx_nr_rings = bp->tx_nr_rings_per_tc * tc;
6104                 netdev_set_num_tc(dev, tc);
6105         } else {
6106                 bp->tx_nr_rings = bp->tx_nr_rings_per_tc;
6107                 netdev_reset_tc(dev);
6108         }
6109         bp->cp_nr_rings = max_t(int, bp->tx_nr_rings, bp->rx_nr_rings);
6110         bp->num_stat_ctxs = bp->cp_nr_rings;
6111
6112         if (netif_running(bp->dev))
6113                 return bnxt_open_nic(bp, true, false);
6114
6115         return 0;
6116 }
6117
6118 #ifdef CONFIG_RFS_ACCEL
6119 static bool bnxt_fltr_match(struct bnxt_ntuple_filter *f1,
6120                             struct bnxt_ntuple_filter *f2)
6121 {
6122         struct flow_keys *keys1 = &f1->fkeys;
6123         struct flow_keys *keys2 = &f2->fkeys;
6124
6125         if (keys1->addrs.v4addrs.src == keys2->addrs.v4addrs.src &&
6126             keys1->addrs.v4addrs.dst == keys2->addrs.v4addrs.dst &&
6127             keys1->ports.ports == keys2->ports.ports &&
6128             keys1->basic.ip_proto == keys2->basic.ip_proto &&
6129             keys1->basic.n_proto == keys2->basic.n_proto &&
6130             ether_addr_equal(f1->src_mac_addr, f2->src_mac_addr))
6131                 return true;
6132
6133         return false;
6134 }
6135
6136 static int bnxt_rx_flow_steer(struct net_device *dev, const struct sk_buff *skb,
6137                               u16 rxq_index, u32 flow_id)
6138 {
6139         struct bnxt *bp = netdev_priv(dev);
6140         struct bnxt_ntuple_filter *fltr, *new_fltr;
6141         struct flow_keys *fkeys;
6142         struct ethhdr *eth = (struct ethhdr *)skb_mac_header(skb);
6143         int rc = 0, idx, bit_id;
6144         struct hlist_head *head;
6145
6146         if (skb->encapsulation)
6147                 return -EPROTONOSUPPORT;
6148
6149         new_fltr = kzalloc(sizeof(*new_fltr), GFP_ATOMIC);
6150         if (!new_fltr)
6151                 return -ENOMEM;
6152
6153         fkeys = &new_fltr->fkeys;
6154         if (!skb_flow_dissect_flow_keys(skb, fkeys, 0)) {
6155                 rc = -EPROTONOSUPPORT;
6156                 goto err_free;
6157         }
6158
6159         if ((fkeys->basic.n_proto != htons(ETH_P_IP)) ||
6160             ((fkeys->basic.ip_proto != IPPROTO_TCP) &&
6161              (fkeys->basic.ip_proto != IPPROTO_UDP))) {
6162                 rc = -EPROTONOSUPPORT;
6163                 goto err_free;
6164         }
6165
6166         memcpy(new_fltr->src_mac_addr, eth->h_source, ETH_ALEN);
6167
6168         idx = skb_get_hash_raw(skb) & BNXT_NTP_FLTR_HASH_MASK;
6169         head = &bp->ntp_fltr_hash_tbl[idx];
6170         rcu_read_lock();
6171         hlist_for_each_entry_rcu(fltr, head, hash) {
6172                 if (bnxt_fltr_match(fltr, new_fltr)) {
6173                         rcu_read_unlock();
6174                         rc = 0;
6175                         goto err_free;
6176                 }
6177         }
6178         rcu_read_unlock();
6179
6180         spin_lock_bh(&bp->ntp_fltr_lock);
6181         bit_id = bitmap_find_free_region(bp->ntp_fltr_bmap,
6182                                          BNXT_NTP_FLTR_MAX_FLTR, 0);
6183         if (bit_id < 0) {
6184                 spin_unlock_bh(&bp->ntp_fltr_lock);
6185                 rc = -ENOMEM;
6186                 goto err_free;
6187         }
6188
6189         new_fltr->sw_id = (u16)bit_id;
6190         new_fltr->flow_id = flow_id;
6191         new_fltr->rxq = rxq_index;
6192         hlist_add_head_rcu(&new_fltr->hash, head);
6193         bp->ntp_fltr_count++;
6194         spin_unlock_bh(&bp->ntp_fltr_lock);
6195
6196         set_bit(BNXT_RX_NTP_FLTR_SP_EVENT, &bp->sp_event);
6197         schedule_work(&bp->sp_task);
6198
6199         return new_fltr->sw_id;
6200
6201 err_free:
6202         kfree(new_fltr);
6203         return rc;
6204 }
6205
6206 static void bnxt_cfg_ntp_filters(struct bnxt *bp)
6207 {
6208         int i;
6209
6210         for (i = 0; i < BNXT_NTP_FLTR_HASH_SIZE; i++) {
6211                 struct hlist_head *head;
6212                 struct hlist_node *tmp;
6213                 struct bnxt_ntuple_filter *fltr;
6214                 int rc;
6215
6216                 head = &bp->ntp_fltr_hash_tbl[i];
6217                 hlist_for_each_entry_safe(fltr, tmp, head, hash) {
6218                         bool del = false;
6219
6220                         if (test_bit(BNXT_FLTR_VALID, &fltr->state)) {
6221                                 if (rps_may_expire_flow(bp->dev, fltr->rxq,
6222                                                         fltr->flow_id,
6223                                                         fltr->sw_id)) {
6224                                         bnxt_hwrm_cfa_ntuple_filter_free(bp,
6225                                                                          fltr);
6226                                         del = true;
6227                                 }
6228                         } else {
6229                                 rc = bnxt_hwrm_cfa_ntuple_filter_alloc(bp,
6230                                                                        fltr);
6231                                 if (rc)
6232                                         del = true;
6233                                 else
6234                                         set_bit(BNXT_FLTR_VALID, &fltr->state);
6235                         }
6236
6237                         if (del) {
6238                                 spin_lock_bh(&bp->ntp_fltr_lock);
6239                                 hlist_del_rcu(&fltr->hash);
6240                                 bp->ntp_fltr_count--;
6241                                 spin_unlock_bh(&bp->ntp_fltr_lock);
6242                                 synchronize_rcu();
6243                                 clear_bit(fltr->sw_id, bp->ntp_fltr_bmap);
6244                                 kfree(fltr);
6245                         }
6246                 }
6247         }
6248         if (test_and_clear_bit(BNXT_HWRM_PF_UNLOAD_SP_EVENT, &bp->sp_event))
6249                 netdev_info(bp->dev, "Receive PF driver unload event!");
6250 }
6251
6252 #else
6253
6254 static void bnxt_cfg_ntp_filters(struct bnxt *bp)
6255 {
6256 }
6257
6258 #endif /* CONFIG_RFS_ACCEL */
6259
6260 static void bnxt_udp_tunnel_add(struct net_device *dev,
6261                                 struct udp_tunnel_info *ti)
6262 {
6263         struct bnxt *bp = netdev_priv(dev);
6264
6265         if (ti->sa_family != AF_INET6 && ti->sa_family != AF_INET)
6266                 return;
6267
6268         if (!netif_running(dev))
6269                 return;
6270
6271         switch (ti->type) {
6272         case UDP_TUNNEL_TYPE_VXLAN:
6273                 if (bp->vxlan_port_cnt && bp->vxlan_port != ti->port)
6274                         return;
6275
6276                 bp->vxlan_port_cnt++;
6277                 if (bp->vxlan_port_cnt == 1) {
6278                         bp->vxlan_port = ti->port;
6279                         set_bit(BNXT_VXLAN_ADD_PORT_SP_EVENT, &bp->sp_event);
6280                         schedule_work(&bp->sp_task);
6281                 }
6282                 break;
6283         case UDP_TUNNEL_TYPE_GENEVE:
6284                 if (bp->nge_port_cnt && bp->nge_port != ti->port)
6285                         return;
6286
6287                 bp->nge_port_cnt++;
6288                 if (bp->nge_port_cnt == 1) {
6289                         bp->nge_port = ti->port;
6290                         set_bit(BNXT_GENEVE_ADD_PORT_SP_EVENT, &bp->sp_event);
6291                 }
6292                 break;
6293         default:
6294                 return;
6295         }
6296
6297         schedule_work(&bp->sp_task);
6298 }
6299
6300 static void bnxt_udp_tunnel_del(struct net_device *dev,
6301                                 struct udp_tunnel_info *ti)
6302 {
6303         struct bnxt *bp = netdev_priv(dev);
6304
6305         if (ti->sa_family != AF_INET6 && ti->sa_family != AF_INET)
6306                 return;
6307
6308         if (!netif_running(dev))
6309                 return;
6310
6311         switch (ti->type) {
6312         case UDP_TUNNEL_TYPE_VXLAN:
6313                 if (!bp->vxlan_port_cnt || bp->vxlan_port != ti->port)
6314                         return;
6315                 bp->vxlan_port_cnt--;
6316
6317                 if (bp->vxlan_port_cnt != 0)
6318                         return;
6319
6320                 set_bit(BNXT_VXLAN_DEL_PORT_SP_EVENT, &bp->sp_event);
6321                 break;
6322         case UDP_TUNNEL_TYPE_GENEVE:
6323                 if (!bp->nge_port_cnt || bp->nge_port != ti->port)
6324                         return;
6325                 bp->nge_port_cnt--;
6326
6327                 if (bp->nge_port_cnt != 0)
6328                         return;
6329
6330                 set_bit(BNXT_GENEVE_DEL_PORT_SP_EVENT, &bp->sp_event);
6331                 break;
6332         default:
6333                 return;
6334         }
6335
6336         schedule_work(&bp->sp_task);
6337 }
6338
6339 static const struct net_device_ops bnxt_netdev_ops = {
6340         .ndo_open               = bnxt_open,
6341         .ndo_start_xmit         = bnxt_start_xmit,
6342         .ndo_stop               = bnxt_close,
6343         .ndo_get_stats64        = bnxt_get_stats64,
6344         .ndo_set_rx_mode        = bnxt_set_rx_mode,
6345         .ndo_do_ioctl           = bnxt_ioctl,
6346         .ndo_validate_addr      = eth_validate_addr,
6347         .ndo_set_mac_address    = bnxt_change_mac_addr,
6348         .ndo_change_mtu         = bnxt_change_mtu,
6349         .ndo_fix_features       = bnxt_fix_features,
6350         .ndo_set_features       = bnxt_set_features,
6351         .ndo_tx_timeout         = bnxt_tx_timeout,
6352 #ifdef CONFIG_BNXT_SRIOV
6353         .ndo_get_vf_config      = bnxt_get_vf_config,
6354         .ndo_set_vf_mac         = bnxt_set_vf_mac,
6355         .ndo_set_vf_vlan        = bnxt_set_vf_vlan,
6356         .ndo_set_vf_rate        = bnxt_set_vf_bw,
6357         .ndo_set_vf_link_state  = bnxt_set_vf_link_state,
6358         .ndo_set_vf_spoofchk    = bnxt_set_vf_spoofchk,
6359 #endif
6360 #ifdef CONFIG_NET_POLL_CONTROLLER
6361         .ndo_poll_controller    = bnxt_poll_controller,
6362 #endif
6363         .ndo_setup_tc           = bnxt_setup_tc,
6364 #ifdef CONFIG_RFS_ACCEL
6365         .ndo_rx_flow_steer      = bnxt_rx_flow_steer,
6366 #endif
6367         .ndo_udp_tunnel_add     = bnxt_udp_tunnel_add,
6368         .ndo_udp_tunnel_del     = bnxt_udp_tunnel_del,
6369 #ifdef CONFIG_NET_RX_BUSY_POLL
6370         .ndo_busy_poll          = bnxt_busy_poll,
6371 #endif
6372 };
6373
6374 static void bnxt_remove_one(struct pci_dev *pdev)
6375 {
6376         struct net_device *dev = pci_get_drvdata(pdev);
6377         struct bnxt *bp = netdev_priv(dev);
6378
6379         if (BNXT_PF(bp))
6380                 bnxt_sriov_disable(bp);
6381
6382         pci_disable_pcie_error_reporting(pdev);
6383         unregister_netdev(dev);
6384         cancel_work_sync(&bp->sp_task);
6385         bp->sp_event = 0;
6386
6387         bnxt_hwrm_func_drv_unrgtr(bp);
6388         bnxt_free_hwrm_resources(bp);
6389         pci_iounmap(pdev, bp->bar2);
6390         pci_iounmap(pdev, bp->bar1);
6391         pci_iounmap(pdev, bp->bar0);
6392         free_netdev(dev);
6393
6394         pci_release_regions(pdev);
6395         pci_disable_device(pdev);
6396 }
6397
6398 static int bnxt_probe_phy(struct bnxt *bp)
6399 {
6400         int rc = 0;
6401         struct bnxt_link_info *link_info = &bp->link_info;
6402
6403         rc = bnxt_hwrm_phy_qcaps(bp);
6404         if (rc) {
6405                 netdev_err(bp->dev, "Probe phy can't get phy capabilities (rc: %x)\n",
6406                            rc);
6407                 return rc;
6408         }
6409
6410         rc = bnxt_update_link(bp, false);
6411         if (rc) {
6412                 netdev_err(bp->dev, "Probe phy can't update link (rc: %x)\n",
6413                            rc);
6414                 return rc;
6415         }
6416
6417         /* Older firmware does not have supported_auto_speeds, so assume
6418          * that all supported speeds can be autonegotiated.
6419          */
6420         if (link_info->auto_link_speeds && !link_info->support_auto_speeds)
6421                 link_info->support_auto_speeds = link_info->support_speeds;
6422
6423         /*initialize the ethool setting copy with NVM settings */
6424         if (BNXT_AUTO_MODE(link_info->auto_mode)) {
6425                 link_info->autoneg = BNXT_AUTONEG_SPEED;
6426                 if (bp->hwrm_spec_code >= 0x10201) {
6427                         if (link_info->auto_pause_setting &
6428                             PORT_PHY_CFG_REQ_AUTO_PAUSE_AUTONEG_PAUSE)
6429                                 link_info->autoneg |= BNXT_AUTONEG_FLOW_CTRL;
6430                 } else {
6431                         link_info->autoneg |= BNXT_AUTONEG_FLOW_CTRL;
6432                 }
6433                 link_info->advertising = link_info->auto_link_speeds;
6434         } else {
6435                 link_info->req_link_speed = link_info->force_link_speed;
6436                 link_info->req_duplex = link_info->duplex_setting;
6437         }
6438         if (link_info->autoneg & BNXT_AUTONEG_FLOW_CTRL)
6439                 link_info->req_flow_ctrl =
6440                         link_info->auto_pause_setting & BNXT_LINK_PAUSE_BOTH;
6441         else
6442                 link_info->req_flow_ctrl = link_info->force_pause_setting;
6443         return rc;
6444 }
6445
6446 static int bnxt_get_max_irq(struct pci_dev *pdev)
6447 {
6448         u16 ctrl;
6449
6450         if (!pdev->msix_cap)
6451                 return 1;
6452
6453         pci_read_config_word(pdev, pdev->msix_cap + PCI_MSIX_FLAGS, &ctrl);
6454         return (ctrl & PCI_MSIX_FLAGS_QSIZE) + 1;
6455 }
6456
6457 static void _bnxt_get_max_rings(struct bnxt *bp, int *max_rx, int *max_tx,
6458                                 int *max_cp)
6459 {
6460         int max_ring_grps = 0;
6461
6462 #ifdef CONFIG_BNXT_SRIOV
6463         if (!BNXT_PF(bp)) {
6464                 *max_tx = bp->vf.max_tx_rings;
6465                 *max_rx = bp->vf.max_rx_rings;
6466                 *max_cp = min_t(int, bp->vf.max_irqs, bp->vf.max_cp_rings);
6467                 *max_cp = min_t(int, *max_cp, bp->vf.max_stat_ctxs);
6468                 max_ring_grps = bp->vf.max_hw_ring_grps;
6469         } else
6470 #endif
6471         {
6472                 *max_tx = bp->pf.max_tx_rings;
6473                 *max_rx = bp->pf.max_rx_rings;
6474                 *max_cp = min_t(int, bp->pf.max_irqs, bp->pf.max_cp_rings);
6475                 *max_cp = min_t(int, *max_cp, bp->pf.max_stat_ctxs);
6476                 max_ring_grps = bp->pf.max_hw_ring_grps;
6477         }
6478
6479         if (bp->flags & BNXT_FLAG_AGG_RINGS)
6480                 *max_rx >>= 1;
6481         *max_rx = min_t(int, *max_rx, max_ring_grps);
6482 }
6483
6484 int bnxt_get_max_rings(struct bnxt *bp, int *max_rx, int *max_tx, bool shared)
6485 {
6486         int rx, tx, cp;
6487
6488         _bnxt_get_max_rings(bp, &rx, &tx, &cp);
6489         if (!rx || !tx || !cp)
6490                 return -ENOMEM;
6491
6492         *max_rx = rx;
6493         *max_tx = tx;
6494         return bnxt_trim_rings(bp, max_rx, max_tx, cp, shared);
6495 }
6496
6497 static int bnxt_set_dflt_rings(struct bnxt *bp)
6498 {
6499         int dflt_rings, max_rx_rings, max_tx_rings, rc;
6500         bool sh = true;
6501
6502         if (sh)
6503                 bp->flags |= BNXT_FLAG_SHARED_RINGS;
6504         dflt_rings = netif_get_num_default_rss_queues();
6505         rc = bnxt_get_max_rings(bp, &max_rx_rings, &max_tx_rings, sh);
6506         if (rc)
6507                 return rc;
6508         bp->rx_nr_rings = min_t(int, dflt_rings, max_rx_rings);
6509         bp->tx_nr_rings_per_tc = min_t(int, dflt_rings, max_tx_rings);
6510         bp->tx_nr_rings = bp->tx_nr_rings_per_tc;
6511         bp->cp_nr_rings = sh ? max_t(int, bp->tx_nr_rings, bp->rx_nr_rings) :
6512                                bp->tx_nr_rings + bp->rx_nr_rings;
6513         bp->num_stat_ctxs = bp->cp_nr_rings;
6514         return rc;
6515 }
6516
6517 static void bnxt_parse_log_pcie_link(struct bnxt *bp)
6518 {
6519         enum pcie_link_width width = PCIE_LNK_WIDTH_UNKNOWN;
6520         enum pci_bus_speed speed = PCI_SPEED_UNKNOWN;
6521
6522         if (pcie_get_minimum_link(bp->pdev, &speed, &width) ||
6523             speed == PCI_SPEED_UNKNOWN || width == PCIE_LNK_WIDTH_UNKNOWN)
6524                 netdev_info(bp->dev, "Failed to determine PCIe Link Info\n");
6525         else
6526                 netdev_info(bp->dev, "PCIe: Speed %s Width x%d\n",
6527                             speed == PCIE_SPEED_2_5GT ? "2.5GT/s" :
6528                             speed == PCIE_SPEED_5_0GT ? "5.0GT/s" :
6529                             speed == PCIE_SPEED_8_0GT ? "8.0GT/s" :
6530                             "Unknown", width);
6531 }
6532
6533 static int bnxt_init_one(struct pci_dev *pdev, const struct pci_device_id *ent)
6534 {
6535         static int version_printed;
6536         struct net_device *dev;
6537         struct bnxt *bp;
6538         int rc, max_irqs;
6539
6540         if (version_printed++ == 0)
6541                 pr_info("%s", version);
6542
6543         max_irqs = bnxt_get_max_irq(pdev);
6544         dev = alloc_etherdev_mq(sizeof(*bp), max_irqs);
6545         if (!dev)
6546                 return -ENOMEM;
6547
6548         bp = netdev_priv(dev);
6549
6550         if (bnxt_vf_pciid(ent->driver_data))
6551                 bp->flags |= BNXT_FLAG_VF;
6552
6553         if (pdev->msix_cap)
6554                 bp->flags |= BNXT_FLAG_MSIX_CAP;
6555
6556         rc = bnxt_init_board(pdev, dev);
6557         if (rc < 0)
6558                 goto init_err_free;
6559
6560         dev->netdev_ops = &bnxt_netdev_ops;
6561         dev->watchdog_timeo = BNXT_TX_TIMEOUT;
6562         dev->ethtool_ops = &bnxt_ethtool_ops;
6563
6564         pci_set_drvdata(pdev, dev);
6565
6566         dev->hw_features = NETIF_F_IP_CSUM | NETIF_F_IPV6_CSUM | NETIF_F_SG |
6567                            NETIF_F_TSO | NETIF_F_TSO6 |
6568                            NETIF_F_GSO_UDP_TUNNEL | NETIF_F_GSO_GRE |
6569                            NETIF_F_GSO_IPXIP4 |
6570                            NETIF_F_GSO_UDP_TUNNEL_CSUM | NETIF_F_GSO_GRE_CSUM |
6571                            NETIF_F_GSO_PARTIAL | NETIF_F_RXHASH |
6572                            NETIF_F_RXCSUM | NETIF_F_LRO | NETIF_F_GRO;
6573
6574         dev->hw_enc_features =
6575                         NETIF_F_IP_CSUM | NETIF_F_IPV6_CSUM | NETIF_F_SG |
6576                         NETIF_F_TSO | NETIF_F_TSO6 |
6577                         NETIF_F_GSO_UDP_TUNNEL | NETIF_F_GSO_GRE |
6578                         NETIF_F_GSO_UDP_TUNNEL_CSUM | NETIF_F_GSO_GRE_CSUM |
6579                         NETIF_F_GSO_IPXIP4 | NETIF_F_GSO_PARTIAL;
6580         dev->gso_partial_features = NETIF_F_GSO_UDP_TUNNEL_CSUM |
6581                                     NETIF_F_GSO_GRE_CSUM;
6582         dev->vlan_features = dev->hw_features | NETIF_F_HIGHDMA;
6583         dev->hw_features |= NETIF_F_HW_VLAN_CTAG_RX | NETIF_F_HW_VLAN_CTAG_TX |
6584                             NETIF_F_HW_VLAN_STAG_RX | NETIF_F_HW_VLAN_STAG_TX;
6585         dev->features |= dev->hw_features | NETIF_F_HIGHDMA;
6586         dev->priv_flags |= IFF_UNICAST_FLT;
6587
6588 #ifdef CONFIG_BNXT_SRIOV
6589         init_waitqueue_head(&bp->sriov_cfg_wait);
6590 #endif
6591         rc = bnxt_alloc_hwrm_resources(bp);
6592         if (rc)
6593                 goto init_err;
6594
6595         mutex_init(&bp->hwrm_cmd_lock);
6596         rc = bnxt_hwrm_ver_get(bp);
6597         if (rc)
6598                 goto init_err;
6599
6600         bp->gro_func = bnxt_gro_func_5730x;
6601         if (BNXT_CHIP_NUM_57X1X(bp->chip_num))
6602                 bp->gro_func = bnxt_gro_func_5731x;
6603
6604         rc = bnxt_hwrm_func_drv_rgtr(bp);
6605         if (rc)
6606                 goto init_err;
6607
6608         /* Get the MAX capabilities for this function */
6609         rc = bnxt_hwrm_func_qcaps(bp);
6610         if (rc) {
6611                 netdev_err(bp->dev, "hwrm query capability failure rc: %x\n",
6612                            rc);
6613                 rc = -1;
6614                 goto init_err;
6615         }
6616
6617         rc = bnxt_hwrm_queue_qportcfg(bp);
6618         if (rc) {
6619                 netdev_err(bp->dev, "hwrm query qportcfg failure rc: %x\n",
6620                            rc);
6621                 rc = -1;
6622                 goto init_err;
6623         }
6624
6625         bnxt_hwrm_func_qcfg(bp);
6626
6627         bnxt_set_tpa_flags(bp);
6628         bnxt_set_ring_params(bp);
6629         if (BNXT_PF(bp))
6630                 bp->pf.max_irqs = max_irqs;
6631 #if defined(CONFIG_BNXT_SRIOV)
6632         else
6633                 bp->vf.max_irqs = max_irqs;
6634 #endif
6635         bnxt_set_dflt_rings(bp);
6636
6637         if (BNXT_PF(bp)) {
6638                 dev->hw_features |= NETIF_F_NTUPLE;
6639                 if (bnxt_rfs_capable(bp)) {
6640                         bp->flags |= BNXT_FLAG_RFS;
6641                         dev->features |= NETIF_F_NTUPLE;
6642                 }
6643         }
6644
6645         if (dev->hw_features & NETIF_F_HW_VLAN_CTAG_RX)
6646                 bp->flags |= BNXT_FLAG_STRIP_VLAN;
6647
6648         rc = bnxt_probe_phy(bp);
6649         if (rc)
6650                 goto init_err;
6651
6652         rc = register_netdev(dev);
6653         if (rc)
6654                 goto init_err;
6655
6656         netdev_info(dev, "%s found at mem %lx, node addr %pM\n",
6657                     board_info[ent->driver_data].name,
6658                     (long)pci_resource_start(pdev, 0), dev->dev_addr);
6659
6660         bnxt_parse_log_pcie_link(bp);
6661
6662         return 0;
6663
6664 init_err:
6665         pci_iounmap(pdev, bp->bar0);
6666         pci_release_regions(pdev);
6667         pci_disable_device(pdev);
6668
6669 init_err_free:
6670         free_netdev(dev);
6671         return rc;
6672 }
6673
6674 /**
6675  * bnxt_io_error_detected - called when PCI error is detected
6676  * @pdev: Pointer to PCI device
6677  * @state: The current pci connection state
6678  *
6679  * This function is called after a PCI bus error affecting
6680  * this device has been detected.
6681  */
6682 static pci_ers_result_t bnxt_io_error_detected(struct pci_dev *pdev,
6683                                                pci_channel_state_t state)
6684 {
6685         struct net_device *netdev = pci_get_drvdata(pdev);
6686         struct bnxt *bp = netdev_priv(netdev);
6687
6688         netdev_info(netdev, "PCI I/O error detected\n");
6689
6690         rtnl_lock();
6691         netif_device_detach(netdev);
6692
6693         if (state == pci_channel_io_perm_failure) {
6694                 rtnl_unlock();
6695                 return PCI_ERS_RESULT_DISCONNECT;
6696         }
6697
6698         if (netif_running(netdev))
6699                 bnxt_close(netdev);
6700
6701         /* So that func_reset will be done during slot_reset */
6702         clear_bit(BNXT_STATE_FN_RST_DONE, &bp->state);
6703         pci_disable_device(pdev);
6704         rtnl_unlock();
6705
6706         /* Request a slot slot reset. */
6707         return PCI_ERS_RESULT_NEED_RESET;
6708 }
6709
6710 /**
6711  * bnxt_io_slot_reset - called after the pci bus has been reset.
6712  * @pdev: Pointer to PCI device
6713  *
6714  * Restart the card from scratch, as if from a cold-boot.
6715  * At this point, the card has exprienced a hard reset,
6716  * followed by fixups by BIOS, and has its config space
6717  * set up identically to what it was at cold boot.
6718  */
6719 static pci_ers_result_t bnxt_io_slot_reset(struct pci_dev *pdev)
6720 {
6721         struct net_device *netdev = pci_get_drvdata(pdev);
6722         struct bnxt *bp = netdev_priv(netdev);
6723         int err = 0;
6724         pci_ers_result_t result = PCI_ERS_RESULT_DISCONNECT;
6725
6726         netdev_info(bp->dev, "PCI Slot Reset\n");
6727
6728         rtnl_lock();
6729
6730         if (pci_enable_device(pdev)) {
6731                 dev_err(&pdev->dev,
6732                         "Cannot re-enable PCI device after reset.\n");
6733         } else {
6734                 pci_set_master(pdev);
6735
6736                 if (netif_running(netdev))
6737                         err = bnxt_open(netdev);
6738
6739                 if (!err)
6740                         result = PCI_ERS_RESULT_RECOVERED;
6741         }
6742
6743         if (result != PCI_ERS_RESULT_RECOVERED && netif_running(netdev))
6744                 dev_close(netdev);
6745
6746         rtnl_unlock();
6747
6748         err = pci_cleanup_aer_uncorrect_error_status(pdev);
6749         if (err) {
6750                 dev_err(&pdev->dev,
6751                         "pci_cleanup_aer_uncorrect_error_status failed 0x%0x\n",
6752                          err); /* non-fatal, continue */
6753         }
6754
6755         return PCI_ERS_RESULT_RECOVERED;
6756 }
6757
6758 /**
6759  * bnxt_io_resume - called when traffic can start flowing again.
6760  * @pdev: Pointer to PCI device
6761  *
6762  * This callback is called when the error recovery driver tells
6763  * us that its OK to resume normal operation.
6764  */
6765 static void bnxt_io_resume(struct pci_dev *pdev)
6766 {
6767         struct net_device *netdev = pci_get_drvdata(pdev);
6768
6769         rtnl_lock();
6770
6771         netif_device_attach(netdev);
6772
6773         rtnl_unlock();
6774 }
6775
6776 static const struct pci_error_handlers bnxt_err_handler = {
6777         .error_detected = bnxt_io_error_detected,
6778         .slot_reset     = bnxt_io_slot_reset,
6779         .resume         = bnxt_io_resume
6780 };
6781
6782 static struct pci_driver bnxt_pci_driver = {
6783         .name           = DRV_MODULE_NAME,
6784         .id_table       = bnxt_pci_tbl,
6785         .probe          = bnxt_init_one,
6786         .remove         = bnxt_remove_one,
6787         .err_handler    = &bnxt_err_handler,
6788 #if defined(CONFIG_BNXT_SRIOV)
6789         .sriov_configure = bnxt_sriov_configure,
6790 #endif
6791 };
6792
6793 module_pci_driver(bnxt_pci_driver);