2 * tg3.c: Broadcom Tigon3 ethernet driver.
4 * Copyright (C) 2001, 2002, 2003, 2004 David S. Miller (davem@redhat.com)
5 * Copyright (C) 2001, 2002, 2003 Jeff Garzik (jgarzik@pobox.com)
6 * Copyright (C) 2004 Sun Microsystems Inc.
7 * Copyright (C) 2005-2011 Broadcom Corporation.
10 * Derived from proprietary unpublished source code,
11 * Copyright (C) 2000-2003 Broadcom Corporation.
13 * Permission is hereby granted for the distribution of this firmware
14 * data in hexadecimal or equivalent format, provided this copyright
15 * notice is accompanying it.
19 #include <linux/module.h>
20 #include <linux/moduleparam.h>
21 #include <linux/stringify.h>
22 #include <linux/kernel.h>
23 #include <linux/types.h>
24 #include <linux/compiler.h>
25 #include <linux/slab.h>
26 #include <linux/delay.h>
28 #include <linux/init.h>
29 #include <linux/interrupt.h>
30 #include <linux/ioport.h>
31 #include <linux/pci.h>
32 #include <linux/netdevice.h>
33 #include <linux/etherdevice.h>
34 #include <linux/skbuff.h>
35 #include <linux/ethtool.h>
36 #include <linux/mdio.h>
37 #include <linux/mii.h>
38 #include <linux/phy.h>
39 #include <linux/brcmphy.h>
40 #include <linux/if_vlan.h>
42 #include <linux/tcp.h>
43 #include <linux/workqueue.h>
44 #include <linux/prefetch.h>
45 #include <linux/dma-mapping.h>
46 #include <linux/firmware.h>
48 #include <net/checksum.h>
51 #include <asm/system.h>
53 #include <asm/byteorder.h>
54 #include <linux/uaccess.h>
57 #include <asm/idprom.h>
66 /* Functions & macros to verify TG3_FLAGS types */
68 static inline int _tg3_flag(enum TG3_FLAGS flag, unsigned long *bits)
70 return test_bit(flag, bits);
73 static inline void _tg3_flag_set(enum TG3_FLAGS flag, unsigned long *bits)
78 static inline void _tg3_flag_clear(enum TG3_FLAGS flag, unsigned long *bits)
80 clear_bit(flag, bits);
83 #define tg3_flag(tp, flag) \
84 _tg3_flag(TG3_FLAG_##flag, (tp)->tg3_flags)
85 #define tg3_flag_set(tp, flag) \
86 _tg3_flag_set(TG3_FLAG_##flag, (tp)->tg3_flags)
87 #define tg3_flag_clear(tp, flag) \
88 _tg3_flag_clear(TG3_FLAG_##flag, (tp)->tg3_flags)
90 #define DRV_MODULE_NAME "tg3"
92 #define TG3_MIN_NUM 122
93 #define DRV_MODULE_VERSION \
94 __stringify(TG3_MAJ_NUM) "." __stringify(TG3_MIN_NUM)
95 #define DRV_MODULE_RELDATE "December 7, 2011"
97 #define RESET_KIND_SHUTDOWN 0
98 #define RESET_KIND_INIT 1
99 #define RESET_KIND_SUSPEND 2
101 #define TG3_DEF_RX_MODE 0
102 #define TG3_DEF_TX_MODE 0
103 #define TG3_DEF_MSG_ENABLE \
113 #define TG3_GRC_LCLCTL_PWRSW_DELAY 100
115 /* length of time before we decide the hardware is borked,
116 * and dev->tx_timeout() should be called to fix the problem
119 #define TG3_TX_TIMEOUT (5 * HZ)
121 /* hardware minimum and maximum for a single frame's data payload */
122 #define TG3_MIN_MTU 60
123 #define TG3_MAX_MTU(tp) \
124 (tg3_flag(tp, JUMBO_CAPABLE) ? 9000 : 1500)
126 /* These numbers seem to be hard coded in the NIC firmware somehow.
127 * You can't change the ring sizes, but you can change where you place
128 * them in the NIC onboard memory.
130 #define TG3_RX_STD_RING_SIZE(tp) \
131 (tg3_flag(tp, LRG_PROD_RING_CAP) ? \
132 TG3_RX_STD_MAX_SIZE_5717 : TG3_RX_STD_MAX_SIZE_5700)
133 #define TG3_DEF_RX_RING_PENDING 200
134 #define TG3_RX_JMB_RING_SIZE(tp) \
135 (tg3_flag(tp, LRG_PROD_RING_CAP) ? \
136 TG3_RX_JMB_MAX_SIZE_5717 : TG3_RX_JMB_MAX_SIZE_5700)
137 #define TG3_DEF_RX_JUMBO_RING_PENDING 100
139 /* Do not place this n-ring entries value into the tp struct itself,
140 * we really want to expose these constants to GCC so that modulo et
141 * al. operations are done with shifts and masks instead of with
142 * hw multiply/modulo instructions. Another solution would be to
143 * replace things like '% foo' with '& (foo - 1)'.
146 #define TG3_TX_RING_SIZE 512
147 #define TG3_DEF_TX_RING_PENDING (TG3_TX_RING_SIZE - 1)
149 #define TG3_RX_STD_RING_BYTES(tp) \
150 (sizeof(struct tg3_rx_buffer_desc) * TG3_RX_STD_RING_SIZE(tp))
151 #define TG3_RX_JMB_RING_BYTES(tp) \
152 (sizeof(struct tg3_ext_rx_buffer_desc) * TG3_RX_JMB_RING_SIZE(tp))
153 #define TG3_RX_RCB_RING_BYTES(tp) \
154 (sizeof(struct tg3_rx_buffer_desc) * (tp->rx_ret_ring_mask + 1))
155 #define TG3_TX_RING_BYTES (sizeof(struct tg3_tx_buffer_desc) * \
157 #define NEXT_TX(N) (((N) + 1) & (TG3_TX_RING_SIZE - 1))
159 #define TG3_DMA_BYTE_ENAB 64
161 #define TG3_RX_STD_DMA_SZ 1536
162 #define TG3_RX_JMB_DMA_SZ 9046
164 #define TG3_RX_DMA_TO_MAP_SZ(x) ((x) + TG3_DMA_BYTE_ENAB)
166 #define TG3_RX_STD_MAP_SZ TG3_RX_DMA_TO_MAP_SZ(TG3_RX_STD_DMA_SZ)
167 #define TG3_RX_JMB_MAP_SZ TG3_RX_DMA_TO_MAP_SZ(TG3_RX_JMB_DMA_SZ)
169 #define TG3_RX_STD_BUFF_RING_SIZE(tp) \
170 (sizeof(struct ring_info) * TG3_RX_STD_RING_SIZE(tp))
172 #define TG3_RX_JMB_BUFF_RING_SIZE(tp) \
173 (sizeof(struct ring_info) * TG3_RX_JMB_RING_SIZE(tp))
175 /* Due to a hardware bug, the 5701 can only DMA to memory addresses
176 * that are at least dword aligned when used in PCIX mode. The driver
177 * works around this bug by double copying the packet. This workaround
178 * is built into the normal double copy length check for efficiency.
180 * However, the double copy is only necessary on those architectures
181 * where unaligned memory accesses are inefficient. For those architectures
182 * where unaligned memory accesses incur little penalty, we can reintegrate
183 * the 5701 in the normal rx path. Doing so saves a device structure
184 * dereference by hardcoding the double copy threshold in place.
186 #define TG3_RX_COPY_THRESHOLD 256
187 #if NET_IP_ALIGN == 0 || defined(CONFIG_HAVE_EFFICIENT_UNALIGNED_ACCESS)
188 #define TG3_RX_COPY_THRESH(tp) TG3_RX_COPY_THRESHOLD
190 #define TG3_RX_COPY_THRESH(tp) ((tp)->rx_copy_thresh)
193 #if (NET_IP_ALIGN != 0)
194 #define TG3_RX_OFFSET(tp) ((tp)->rx_offset)
196 #define TG3_RX_OFFSET(tp) (NET_SKB_PAD)
199 /* minimum number of free TX descriptors required to wake up TX process */
200 #define TG3_TX_WAKEUP_THRESH(tnapi) ((tnapi)->tx_pending / 4)
201 #define TG3_TX_BD_DMA_MAX_2K 2048
202 #define TG3_TX_BD_DMA_MAX_4K 4096
204 #define TG3_RAW_IP_ALIGN 2
206 #define TG3_FW_UPDATE_TIMEOUT_SEC 5
208 #define FIRMWARE_TG3 "tigon/tg3.bin"
209 #define FIRMWARE_TG3TSO "tigon/tg3_tso.bin"
210 #define FIRMWARE_TG3TSO5 "tigon/tg3_tso5.bin"
212 static char version[] __devinitdata =
213 DRV_MODULE_NAME ".c:v" DRV_MODULE_VERSION " (" DRV_MODULE_RELDATE ")";
215 MODULE_AUTHOR("David S. Miller (davem@redhat.com) and Jeff Garzik (jgarzik@pobox.com)");
216 MODULE_DESCRIPTION("Broadcom Tigon3 ethernet driver");
217 MODULE_LICENSE("GPL");
218 MODULE_VERSION(DRV_MODULE_VERSION);
219 MODULE_FIRMWARE(FIRMWARE_TG3);
220 MODULE_FIRMWARE(FIRMWARE_TG3TSO);
221 MODULE_FIRMWARE(FIRMWARE_TG3TSO5);
223 static int tg3_debug = -1; /* -1 == use TG3_DEF_MSG_ENABLE as value */
224 module_param(tg3_debug, int, 0);
225 MODULE_PARM_DESC(tg3_debug, "Tigon3 bitmapped debugging message enable value");
227 static DEFINE_PCI_DEVICE_TABLE(tg3_pci_tbl) = {
228 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5700)},
229 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5701)},
230 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5702)},
231 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5703)},
232 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5704)},
233 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5702FE)},
234 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5705)},
235 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5705_2)},
236 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5705M)},
237 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5705M_2)},
238 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5702X)},
239 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5703X)},
240 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5704S)},
241 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5702A3)},
242 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5703A3)},
243 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5782)},
244 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5788)},
245 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5789)},
246 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5901)},
247 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5901_2)},
248 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5704S_2)},
249 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5705F)},
250 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5721)},
251 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5722)},
252 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5751)},
253 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5751M)},
254 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5751F)},
255 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5752)},
256 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5752M)},
257 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5753)},
258 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5753M)},
259 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5753F)},
260 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5754)},
261 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5754M)},
262 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5755)},
263 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5755M)},
264 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5756)},
265 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5786)},
266 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5787)},
267 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5787M)},
268 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5787F)},
269 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5714)},
270 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5714S)},
271 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5715)},
272 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5715S)},
273 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5780)},
274 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5780S)},
275 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5781)},
276 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5906)},
277 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5906M)},
278 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5784)},
279 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5764)},
280 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5723)},
281 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5761)},
282 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5761E)},
283 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_5761S)},
284 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_5761SE)},
285 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_5785_G)},
286 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_5785_F)},
287 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_57780)},
288 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_57760)},
289 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_57790)},
290 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_57788)},
291 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_5717)},
292 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_5718)},
293 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_57781)},
294 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_57785)},
295 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_57761)},
296 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_57765)},
297 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_57791)},
298 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_57795)},
299 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_5719)},
300 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_5720)},
301 {PCI_DEVICE(PCI_VENDOR_ID_SYSKONNECT, PCI_DEVICE_ID_SYSKONNECT_9DXX)},
302 {PCI_DEVICE(PCI_VENDOR_ID_SYSKONNECT, PCI_DEVICE_ID_SYSKONNECT_9MXX)},
303 {PCI_DEVICE(PCI_VENDOR_ID_ALTIMA, PCI_DEVICE_ID_ALTIMA_AC1000)},
304 {PCI_DEVICE(PCI_VENDOR_ID_ALTIMA, PCI_DEVICE_ID_ALTIMA_AC1001)},
305 {PCI_DEVICE(PCI_VENDOR_ID_ALTIMA, PCI_DEVICE_ID_ALTIMA_AC1003)},
306 {PCI_DEVICE(PCI_VENDOR_ID_ALTIMA, PCI_DEVICE_ID_ALTIMA_AC9100)},
307 {PCI_DEVICE(PCI_VENDOR_ID_APPLE, PCI_DEVICE_ID_APPLE_TIGON3)},
308 {PCI_DEVICE(0x10cf, 0x11a2)}, /* Fujitsu 1000base-SX with BCM5703SKHB */
312 MODULE_DEVICE_TABLE(pci, tg3_pci_tbl);
314 static const struct {
315 const char string[ETH_GSTRING_LEN];
316 } ethtool_stats_keys[] = {
319 { "rx_ucast_packets" },
320 { "rx_mcast_packets" },
321 { "rx_bcast_packets" },
323 { "rx_align_errors" },
324 { "rx_xon_pause_rcvd" },
325 { "rx_xoff_pause_rcvd" },
326 { "rx_mac_ctrl_rcvd" },
327 { "rx_xoff_entered" },
328 { "rx_frame_too_long_errors" },
330 { "rx_undersize_packets" },
331 { "rx_in_length_errors" },
332 { "rx_out_length_errors" },
333 { "rx_64_or_less_octet_packets" },
334 { "rx_65_to_127_octet_packets" },
335 { "rx_128_to_255_octet_packets" },
336 { "rx_256_to_511_octet_packets" },
337 { "rx_512_to_1023_octet_packets" },
338 { "rx_1024_to_1522_octet_packets" },
339 { "rx_1523_to_2047_octet_packets" },
340 { "rx_2048_to_4095_octet_packets" },
341 { "rx_4096_to_8191_octet_packets" },
342 { "rx_8192_to_9022_octet_packets" },
349 { "tx_flow_control" },
351 { "tx_single_collisions" },
352 { "tx_mult_collisions" },
354 { "tx_excessive_collisions" },
355 { "tx_late_collisions" },
356 { "tx_collide_2times" },
357 { "tx_collide_3times" },
358 { "tx_collide_4times" },
359 { "tx_collide_5times" },
360 { "tx_collide_6times" },
361 { "tx_collide_7times" },
362 { "tx_collide_8times" },
363 { "tx_collide_9times" },
364 { "tx_collide_10times" },
365 { "tx_collide_11times" },
366 { "tx_collide_12times" },
367 { "tx_collide_13times" },
368 { "tx_collide_14times" },
369 { "tx_collide_15times" },
370 { "tx_ucast_packets" },
371 { "tx_mcast_packets" },
372 { "tx_bcast_packets" },
373 { "tx_carrier_sense_errors" },
377 { "dma_writeq_full" },
378 { "dma_write_prioq_full" },
382 { "rx_threshold_hit" },
384 { "dma_readq_full" },
385 { "dma_read_prioq_full" },
386 { "tx_comp_queue_full" },
388 { "ring_set_send_prod_index" },
389 { "ring_status_update" },
391 { "nic_avoided_irqs" },
392 { "nic_tx_threshold_hit" },
394 { "mbuf_lwm_thresh_hit" },
397 #define TG3_NUM_STATS ARRAY_SIZE(ethtool_stats_keys)
400 static const struct {
401 const char string[ETH_GSTRING_LEN];
402 } ethtool_test_keys[] = {
403 { "nvram test (online) " },
404 { "link test (online) " },
405 { "register test (offline)" },
406 { "memory test (offline)" },
407 { "mac loopback test (offline)" },
408 { "phy loopback test (offline)" },
409 { "ext loopback test (offline)" },
410 { "interrupt test (offline)" },
413 #define TG3_NUM_TEST ARRAY_SIZE(ethtool_test_keys)
416 static void tg3_write32(struct tg3 *tp, u32 off, u32 val)
418 writel(val, tp->regs + off);
421 static u32 tg3_read32(struct tg3 *tp, u32 off)
423 return readl(tp->regs + off);
426 static void tg3_ape_write32(struct tg3 *tp, u32 off, u32 val)
428 writel(val, tp->aperegs + off);
431 static u32 tg3_ape_read32(struct tg3 *tp, u32 off)
433 return readl(tp->aperegs + off);
436 static void tg3_write_indirect_reg32(struct tg3 *tp, u32 off, u32 val)
440 spin_lock_irqsave(&tp->indirect_lock, flags);
441 pci_write_config_dword(tp->pdev, TG3PCI_REG_BASE_ADDR, off);
442 pci_write_config_dword(tp->pdev, TG3PCI_REG_DATA, val);
443 spin_unlock_irqrestore(&tp->indirect_lock, flags);
446 static void tg3_write_flush_reg32(struct tg3 *tp, u32 off, u32 val)
448 writel(val, tp->regs + off);
449 readl(tp->regs + off);
452 static u32 tg3_read_indirect_reg32(struct tg3 *tp, u32 off)
457 spin_lock_irqsave(&tp->indirect_lock, flags);
458 pci_write_config_dword(tp->pdev, TG3PCI_REG_BASE_ADDR, off);
459 pci_read_config_dword(tp->pdev, TG3PCI_REG_DATA, &val);
460 spin_unlock_irqrestore(&tp->indirect_lock, flags);
464 static void tg3_write_indirect_mbox(struct tg3 *tp, u32 off, u32 val)
468 if (off == (MAILBOX_RCVRET_CON_IDX_0 + TG3_64BIT_REG_LOW)) {
469 pci_write_config_dword(tp->pdev, TG3PCI_RCV_RET_RING_CON_IDX +
470 TG3_64BIT_REG_LOW, val);
473 if (off == TG3_RX_STD_PROD_IDX_REG) {
474 pci_write_config_dword(tp->pdev, TG3PCI_STD_RING_PROD_IDX +
475 TG3_64BIT_REG_LOW, val);
479 spin_lock_irqsave(&tp->indirect_lock, flags);
480 pci_write_config_dword(tp->pdev, TG3PCI_REG_BASE_ADDR, off + 0x5600);
481 pci_write_config_dword(tp->pdev, TG3PCI_REG_DATA, val);
482 spin_unlock_irqrestore(&tp->indirect_lock, flags);
484 /* In indirect mode when disabling interrupts, we also need
485 * to clear the interrupt bit in the GRC local ctrl register.
487 if ((off == (MAILBOX_INTERRUPT_0 + TG3_64BIT_REG_LOW)) &&
489 pci_write_config_dword(tp->pdev, TG3PCI_MISC_LOCAL_CTRL,
490 tp->grc_local_ctrl|GRC_LCLCTRL_CLEARINT);
494 static u32 tg3_read_indirect_mbox(struct tg3 *tp, u32 off)
499 spin_lock_irqsave(&tp->indirect_lock, flags);
500 pci_write_config_dword(tp->pdev, TG3PCI_REG_BASE_ADDR, off + 0x5600);
501 pci_read_config_dword(tp->pdev, TG3PCI_REG_DATA, &val);
502 spin_unlock_irqrestore(&tp->indirect_lock, flags);
506 /* usec_wait specifies the wait time in usec when writing to certain registers
507 * where it is unsafe to read back the register without some delay.
508 * GRC_LOCAL_CTRL is one example if the GPIOs are toggled to switch power.
509 * TG3PCI_CLOCK_CTRL is another example if the clock frequencies are changed.
511 static void _tw32_flush(struct tg3 *tp, u32 off, u32 val, u32 usec_wait)
513 if (tg3_flag(tp, PCIX_TARGET_HWBUG) || tg3_flag(tp, ICH_WORKAROUND))
514 /* Non-posted methods */
515 tp->write32(tp, off, val);
518 tg3_write32(tp, off, val);
523 /* Wait again after the read for the posted method to guarantee that
524 * the wait time is met.
530 static inline void tw32_mailbox_flush(struct tg3 *tp, u32 off, u32 val)
532 tp->write32_mbox(tp, off, val);
533 if (!tg3_flag(tp, MBOX_WRITE_REORDER) && !tg3_flag(tp, ICH_WORKAROUND))
534 tp->read32_mbox(tp, off);
537 static void tg3_write32_tx_mbox(struct tg3 *tp, u32 off, u32 val)
539 void __iomem *mbox = tp->regs + off;
541 if (tg3_flag(tp, TXD_MBOX_HWBUG))
543 if (tg3_flag(tp, MBOX_WRITE_REORDER))
547 static u32 tg3_read32_mbox_5906(struct tg3 *tp, u32 off)
549 return readl(tp->regs + off + GRCMBOX_BASE);
552 static void tg3_write32_mbox_5906(struct tg3 *tp, u32 off, u32 val)
554 writel(val, tp->regs + off + GRCMBOX_BASE);
557 #define tw32_mailbox(reg, val) tp->write32_mbox(tp, reg, val)
558 #define tw32_mailbox_f(reg, val) tw32_mailbox_flush(tp, (reg), (val))
559 #define tw32_rx_mbox(reg, val) tp->write32_rx_mbox(tp, reg, val)
560 #define tw32_tx_mbox(reg, val) tp->write32_tx_mbox(tp, reg, val)
561 #define tr32_mailbox(reg) tp->read32_mbox(tp, reg)
563 #define tw32(reg, val) tp->write32(tp, reg, val)
564 #define tw32_f(reg, val) _tw32_flush(tp, (reg), (val), 0)
565 #define tw32_wait_f(reg, val, us) _tw32_flush(tp, (reg), (val), (us))
566 #define tr32(reg) tp->read32(tp, reg)
568 static void tg3_write_mem(struct tg3 *tp, u32 off, u32 val)
572 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906 &&
573 (off >= NIC_SRAM_STATS_BLK) && (off < NIC_SRAM_TX_BUFFER_DESC))
576 spin_lock_irqsave(&tp->indirect_lock, flags);
577 if (tg3_flag(tp, SRAM_USE_CONFIG)) {
578 pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_BASE_ADDR, off);
579 pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_DATA, val);
581 /* Always leave this as zero. */
582 pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_BASE_ADDR, 0);
584 tw32_f(TG3PCI_MEM_WIN_BASE_ADDR, off);
585 tw32_f(TG3PCI_MEM_WIN_DATA, val);
587 /* Always leave this as zero. */
588 tw32_f(TG3PCI_MEM_WIN_BASE_ADDR, 0);
590 spin_unlock_irqrestore(&tp->indirect_lock, flags);
593 static void tg3_read_mem(struct tg3 *tp, u32 off, u32 *val)
597 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906 &&
598 (off >= NIC_SRAM_STATS_BLK) && (off < NIC_SRAM_TX_BUFFER_DESC)) {
603 spin_lock_irqsave(&tp->indirect_lock, flags);
604 if (tg3_flag(tp, SRAM_USE_CONFIG)) {
605 pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_BASE_ADDR, off);
606 pci_read_config_dword(tp->pdev, TG3PCI_MEM_WIN_DATA, val);
608 /* Always leave this as zero. */
609 pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_BASE_ADDR, 0);
611 tw32_f(TG3PCI_MEM_WIN_BASE_ADDR, off);
612 *val = tr32(TG3PCI_MEM_WIN_DATA);
614 /* Always leave this as zero. */
615 tw32_f(TG3PCI_MEM_WIN_BASE_ADDR, 0);
617 spin_unlock_irqrestore(&tp->indirect_lock, flags);
620 static void tg3_ape_lock_init(struct tg3 *tp)
625 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5761)
626 regbase = TG3_APE_LOCK_GRANT;
628 regbase = TG3_APE_PER_LOCK_GRANT;
630 /* Make sure the driver hasn't any stale locks. */
631 for (i = TG3_APE_LOCK_PHY0; i <= TG3_APE_LOCK_GPIO; i++) {
633 case TG3_APE_LOCK_PHY0:
634 case TG3_APE_LOCK_PHY1:
635 case TG3_APE_LOCK_PHY2:
636 case TG3_APE_LOCK_PHY3:
637 bit = APE_LOCK_GRANT_DRIVER;
641 bit = APE_LOCK_GRANT_DRIVER;
643 bit = 1 << tp->pci_fn;
645 tg3_ape_write32(tp, regbase + 4 * i, bit);
650 static int tg3_ape_lock(struct tg3 *tp, int locknum)
654 u32 status, req, gnt, bit;
656 if (!tg3_flag(tp, ENABLE_APE))
660 case TG3_APE_LOCK_GPIO:
661 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5761)
663 case TG3_APE_LOCK_GRC:
664 case TG3_APE_LOCK_MEM:
666 bit = APE_LOCK_REQ_DRIVER;
668 bit = 1 << tp->pci_fn;
674 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5761) {
675 req = TG3_APE_LOCK_REQ;
676 gnt = TG3_APE_LOCK_GRANT;
678 req = TG3_APE_PER_LOCK_REQ;
679 gnt = TG3_APE_PER_LOCK_GRANT;
684 tg3_ape_write32(tp, req + off, bit);
686 /* Wait for up to 1 millisecond to acquire lock. */
687 for (i = 0; i < 100; i++) {
688 status = tg3_ape_read32(tp, gnt + off);
695 /* Revoke the lock request. */
696 tg3_ape_write32(tp, gnt + off, bit);
703 static void tg3_ape_unlock(struct tg3 *tp, int locknum)
707 if (!tg3_flag(tp, ENABLE_APE))
711 case TG3_APE_LOCK_GPIO:
712 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5761)
714 case TG3_APE_LOCK_GRC:
715 case TG3_APE_LOCK_MEM:
717 bit = APE_LOCK_GRANT_DRIVER;
719 bit = 1 << tp->pci_fn;
725 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5761)
726 gnt = TG3_APE_LOCK_GRANT;
728 gnt = TG3_APE_PER_LOCK_GRANT;
730 tg3_ape_write32(tp, gnt + 4 * locknum, bit);
733 static void tg3_ape_send_event(struct tg3 *tp, u32 event)
738 /* NCSI does not support APE events */
739 if (tg3_flag(tp, APE_HAS_NCSI))
742 apedata = tg3_ape_read32(tp, TG3_APE_SEG_SIG);
743 if (apedata != APE_SEG_SIG_MAGIC)
746 apedata = tg3_ape_read32(tp, TG3_APE_FW_STATUS);
747 if (!(apedata & APE_FW_STATUS_READY))
750 /* Wait for up to 1 millisecond for APE to service previous event. */
751 for (i = 0; i < 10; i++) {
752 if (tg3_ape_lock(tp, TG3_APE_LOCK_MEM))
755 apedata = tg3_ape_read32(tp, TG3_APE_EVENT_STATUS);
757 if (!(apedata & APE_EVENT_STATUS_EVENT_PENDING))
758 tg3_ape_write32(tp, TG3_APE_EVENT_STATUS,
759 event | APE_EVENT_STATUS_EVENT_PENDING);
761 tg3_ape_unlock(tp, TG3_APE_LOCK_MEM);
763 if (!(apedata & APE_EVENT_STATUS_EVENT_PENDING))
769 if (!(apedata & APE_EVENT_STATUS_EVENT_PENDING))
770 tg3_ape_write32(tp, TG3_APE_EVENT, APE_EVENT_1);
773 static void tg3_ape_driver_state_change(struct tg3 *tp, int kind)
778 if (!tg3_flag(tp, ENABLE_APE))
782 case RESET_KIND_INIT:
783 tg3_ape_write32(tp, TG3_APE_HOST_SEG_SIG,
784 APE_HOST_SEG_SIG_MAGIC);
785 tg3_ape_write32(tp, TG3_APE_HOST_SEG_LEN,
786 APE_HOST_SEG_LEN_MAGIC);
787 apedata = tg3_ape_read32(tp, TG3_APE_HOST_INIT_COUNT);
788 tg3_ape_write32(tp, TG3_APE_HOST_INIT_COUNT, ++apedata);
789 tg3_ape_write32(tp, TG3_APE_HOST_DRIVER_ID,
790 APE_HOST_DRIVER_ID_MAGIC(TG3_MAJ_NUM, TG3_MIN_NUM));
791 tg3_ape_write32(tp, TG3_APE_HOST_BEHAVIOR,
792 APE_HOST_BEHAV_NO_PHYLOCK);
793 tg3_ape_write32(tp, TG3_APE_HOST_DRVR_STATE,
794 TG3_APE_HOST_DRVR_STATE_START);
796 event = APE_EVENT_STATUS_STATE_START;
798 case RESET_KIND_SHUTDOWN:
799 /* With the interface we are currently using,
800 * APE does not track driver state. Wiping
801 * out the HOST SEGMENT SIGNATURE forces
802 * the APE to assume OS absent status.
804 tg3_ape_write32(tp, TG3_APE_HOST_SEG_SIG, 0x0);
806 if (device_may_wakeup(&tp->pdev->dev) &&
807 tg3_flag(tp, WOL_ENABLE)) {
808 tg3_ape_write32(tp, TG3_APE_HOST_WOL_SPEED,
809 TG3_APE_HOST_WOL_SPEED_AUTO);
810 apedata = TG3_APE_HOST_DRVR_STATE_WOL;
812 apedata = TG3_APE_HOST_DRVR_STATE_UNLOAD;
814 tg3_ape_write32(tp, TG3_APE_HOST_DRVR_STATE, apedata);
816 event = APE_EVENT_STATUS_STATE_UNLOAD;
818 case RESET_KIND_SUSPEND:
819 event = APE_EVENT_STATUS_STATE_SUSPEND;
825 event |= APE_EVENT_STATUS_DRIVER_EVNT | APE_EVENT_STATUS_STATE_CHNGE;
827 tg3_ape_send_event(tp, event);
830 static void tg3_disable_ints(struct tg3 *tp)
834 tw32(TG3PCI_MISC_HOST_CTRL,
835 (tp->misc_host_ctrl | MISC_HOST_CTRL_MASK_PCI_INT));
836 for (i = 0; i < tp->irq_max; i++)
837 tw32_mailbox_f(tp->napi[i].int_mbox, 0x00000001);
840 static void tg3_enable_ints(struct tg3 *tp)
847 tw32(TG3PCI_MISC_HOST_CTRL,
848 (tp->misc_host_ctrl & ~MISC_HOST_CTRL_MASK_PCI_INT));
850 tp->coal_now = tp->coalesce_mode | HOSTCC_MODE_ENABLE;
851 for (i = 0; i < tp->irq_cnt; i++) {
852 struct tg3_napi *tnapi = &tp->napi[i];
854 tw32_mailbox_f(tnapi->int_mbox, tnapi->last_tag << 24);
855 if (tg3_flag(tp, 1SHOT_MSI))
856 tw32_mailbox_f(tnapi->int_mbox, tnapi->last_tag << 24);
858 tp->coal_now |= tnapi->coal_now;
861 /* Force an initial interrupt */
862 if (!tg3_flag(tp, TAGGED_STATUS) &&
863 (tp->napi[0].hw_status->status & SD_STATUS_UPDATED))
864 tw32(GRC_LOCAL_CTRL, tp->grc_local_ctrl | GRC_LCLCTRL_SETINT);
866 tw32(HOSTCC_MODE, tp->coal_now);
868 tp->coal_now &= ~(tp->napi[0].coal_now | tp->napi[1].coal_now);
871 static inline unsigned int tg3_has_work(struct tg3_napi *tnapi)
873 struct tg3 *tp = tnapi->tp;
874 struct tg3_hw_status *sblk = tnapi->hw_status;
875 unsigned int work_exists = 0;
877 /* check for phy events */
878 if (!(tg3_flag(tp, USE_LINKCHG_REG) || tg3_flag(tp, POLL_SERDES))) {
879 if (sblk->status & SD_STATUS_LINK_CHG)
882 /* check for RX/TX work to do */
883 if (sblk->idx[0].tx_consumer != tnapi->tx_cons ||
884 *(tnapi->rx_rcb_prod_idx) != tnapi->rx_rcb_ptr)
891 * similar to tg3_enable_ints, but it accurately determines whether there
892 * is new work pending and can return without flushing the PIO write
893 * which reenables interrupts
895 static void tg3_int_reenable(struct tg3_napi *tnapi)
897 struct tg3 *tp = tnapi->tp;
899 tw32_mailbox(tnapi->int_mbox, tnapi->last_tag << 24);
902 /* When doing tagged status, this work check is unnecessary.
903 * The last_tag we write above tells the chip which piece of
904 * work we've completed.
906 if (!tg3_flag(tp, TAGGED_STATUS) && tg3_has_work(tnapi))
907 tw32(HOSTCC_MODE, tp->coalesce_mode |
908 HOSTCC_MODE_ENABLE | tnapi->coal_now);
911 static void tg3_switch_clocks(struct tg3 *tp)
916 if (tg3_flag(tp, CPMU_PRESENT) || tg3_flag(tp, 5780_CLASS))
919 clock_ctrl = tr32(TG3PCI_CLOCK_CTRL);
921 orig_clock_ctrl = clock_ctrl;
922 clock_ctrl &= (CLOCK_CTRL_FORCE_CLKRUN |
923 CLOCK_CTRL_CLKRUN_OENABLE |
925 tp->pci_clock_ctrl = clock_ctrl;
927 if (tg3_flag(tp, 5705_PLUS)) {
928 if (orig_clock_ctrl & CLOCK_CTRL_625_CORE) {
929 tw32_wait_f(TG3PCI_CLOCK_CTRL,
930 clock_ctrl | CLOCK_CTRL_625_CORE, 40);
932 } else if ((orig_clock_ctrl & CLOCK_CTRL_44MHZ_CORE) != 0) {
933 tw32_wait_f(TG3PCI_CLOCK_CTRL,
935 (CLOCK_CTRL_44MHZ_CORE | CLOCK_CTRL_ALTCLK),
937 tw32_wait_f(TG3PCI_CLOCK_CTRL,
938 clock_ctrl | (CLOCK_CTRL_ALTCLK),
941 tw32_wait_f(TG3PCI_CLOCK_CTRL, clock_ctrl, 40);
944 #define PHY_BUSY_LOOPS 5000
946 static int tg3_readphy(struct tg3 *tp, int reg, u32 *val)
952 if ((tp->mi_mode & MAC_MI_MODE_AUTO_POLL) != 0) {
954 (tp->mi_mode & ~MAC_MI_MODE_AUTO_POLL));
960 frame_val = ((tp->phy_addr << MI_COM_PHY_ADDR_SHIFT) &
961 MI_COM_PHY_ADDR_MASK);
962 frame_val |= ((reg << MI_COM_REG_ADDR_SHIFT) &
963 MI_COM_REG_ADDR_MASK);
964 frame_val |= (MI_COM_CMD_READ | MI_COM_START);
966 tw32_f(MAC_MI_COM, frame_val);
968 loops = PHY_BUSY_LOOPS;
971 frame_val = tr32(MAC_MI_COM);
973 if ((frame_val & MI_COM_BUSY) == 0) {
975 frame_val = tr32(MAC_MI_COM);
983 *val = frame_val & MI_COM_DATA_MASK;
987 if ((tp->mi_mode & MAC_MI_MODE_AUTO_POLL) != 0) {
988 tw32_f(MAC_MI_MODE, tp->mi_mode);
995 static int tg3_writephy(struct tg3 *tp, int reg, u32 val)
1001 if ((tp->phy_flags & TG3_PHYFLG_IS_FET) &&
1002 (reg == MII_CTRL1000 || reg == MII_TG3_AUX_CTRL))
1005 if ((tp->mi_mode & MAC_MI_MODE_AUTO_POLL) != 0) {
1007 (tp->mi_mode & ~MAC_MI_MODE_AUTO_POLL));
1011 frame_val = ((tp->phy_addr << MI_COM_PHY_ADDR_SHIFT) &
1012 MI_COM_PHY_ADDR_MASK);
1013 frame_val |= ((reg << MI_COM_REG_ADDR_SHIFT) &
1014 MI_COM_REG_ADDR_MASK);
1015 frame_val |= (val & MI_COM_DATA_MASK);
1016 frame_val |= (MI_COM_CMD_WRITE | MI_COM_START);
1018 tw32_f(MAC_MI_COM, frame_val);
1020 loops = PHY_BUSY_LOOPS;
1021 while (loops != 0) {
1023 frame_val = tr32(MAC_MI_COM);
1024 if ((frame_val & MI_COM_BUSY) == 0) {
1026 frame_val = tr32(MAC_MI_COM);
1036 if ((tp->mi_mode & MAC_MI_MODE_AUTO_POLL) != 0) {
1037 tw32_f(MAC_MI_MODE, tp->mi_mode);
1044 static int tg3_phy_cl45_write(struct tg3 *tp, u32 devad, u32 addr, u32 val)
1048 err = tg3_writephy(tp, MII_TG3_MMD_CTRL, devad);
1052 err = tg3_writephy(tp, MII_TG3_MMD_ADDRESS, addr);
1056 err = tg3_writephy(tp, MII_TG3_MMD_CTRL,
1057 MII_TG3_MMD_CTRL_DATA_NOINC | devad);
1061 err = tg3_writephy(tp, MII_TG3_MMD_ADDRESS, val);
1067 static int tg3_phy_cl45_read(struct tg3 *tp, u32 devad, u32 addr, u32 *val)
1071 err = tg3_writephy(tp, MII_TG3_MMD_CTRL, devad);
1075 err = tg3_writephy(tp, MII_TG3_MMD_ADDRESS, addr);
1079 err = tg3_writephy(tp, MII_TG3_MMD_CTRL,
1080 MII_TG3_MMD_CTRL_DATA_NOINC | devad);
1084 err = tg3_readphy(tp, MII_TG3_MMD_ADDRESS, val);
1090 static int tg3_phydsp_read(struct tg3 *tp, u32 reg, u32 *val)
1094 err = tg3_writephy(tp, MII_TG3_DSP_ADDRESS, reg);
1096 err = tg3_readphy(tp, MII_TG3_DSP_RW_PORT, val);
1101 static int tg3_phydsp_write(struct tg3 *tp, u32 reg, u32 val)
1105 err = tg3_writephy(tp, MII_TG3_DSP_ADDRESS, reg);
1107 err = tg3_writephy(tp, MII_TG3_DSP_RW_PORT, val);
1112 static int tg3_phy_auxctl_read(struct tg3 *tp, int reg, u32 *val)
1116 err = tg3_writephy(tp, MII_TG3_AUX_CTRL,
1117 (reg << MII_TG3_AUXCTL_MISC_RDSEL_SHIFT) |
1118 MII_TG3_AUXCTL_SHDWSEL_MISC);
1120 err = tg3_readphy(tp, MII_TG3_AUX_CTRL, val);
1125 static int tg3_phy_auxctl_write(struct tg3 *tp, int reg, u32 set)
1127 if (reg == MII_TG3_AUXCTL_SHDWSEL_MISC)
1128 set |= MII_TG3_AUXCTL_MISC_WREN;
1130 return tg3_writephy(tp, MII_TG3_AUX_CTRL, set | reg);
1133 #define TG3_PHY_AUXCTL_SMDSP_ENABLE(tp) \
1134 tg3_phy_auxctl_write((tp), MII_TG3_AUXCTL_SHDWSEL_AUXCTL, \
1135 MII_TG3_AUXCTL_ACTL_SMDSP_ENA | \
1136 MII_TG3_AUXCTL_ACTL_TX_6DB)
1138 #define TG3_PHY_AUXCTL_SMDSP_DISABLE(tp) \
1139 tg3_phy_auxctl_write((tp), MII_TG3_AUXCTL_SHDWSEL_AUXCTL, \
1140 MII_TG3_AUXCTL_ACTL_TX_6DB);
1142 static int tg3_bmcr_reset(struct tg3 *tp)
1147 /* OK, reset it, and poll the BMCR_RESET bit until it
1148 * clears or we time out.
1150 phy_control = BMCR_RESET;
1151 err = tg3_writephy(tp, MII_BMCR, phy_control);
1157 err = tg3_readphy(tp, MII_BMCR, &phy_control);
1161 if ((phy_control & BMCR_RESET) == 0) {
1173 static int tg3_mdio_read(struct mii_bus *bp, int mii_id, int reg)
1175 struct tg3 *tp = bp->priv;
1178 spin_lock_bh(&tp->lock);
1180 if (tg3_readphy(tp, reg, &val))
1183 spin_unlock_bh(&tp->lock);
1188 static int tg3_mdio_write(struct mii_bus *bp, int mii_id, int reg, u16 val)
1190 struct tg3 *tp = bp->priv;
1193 spin_lock_bh(&tp->lock);
1195 if (tg3_writephy(tp, reg, val))
1198 spin_unlock_bh(&tp->lock);
1203 static int tg3_mdio_reset(struct mii_bus *bp)
1208 static void tg3_mdio_config_5785(struct tg3 *tp)
1211 struct phy_device *phydev;
1213 phydev = tp->mdio_bus->phy_map[TG3_PHY_MII_ADDR];
1214 switch (phydev->drv->phy_id & phydev->drv->phy_id_mask) {
1215 case PHY_ID_BCM50610:
1216 case PHY_ID_BCM50610M:
1217 val = MAC_PHYCFG2_50610_LED_MODES;
1219 case PHY_ID_BCMAC131:
1220 val = MAC_PHYCFG2_AC131_LED_MODES;
1222 case PHY_ID_RTL8211C:
1223 val = MAC_PHYCFG2_RTL8211C_LED_MODES;
1225 case PHY_ID_RTL8201E:
1226 val = MAC_PHYCFG2_RTL8201E_LED_MODES;
1232 if (phydev->interface != PHY_INTERFACE_MODE_RGMII) {
1233 tw32(MAC_PHYCFG2, val);
1235 val = tr32(MAC_PHYCFG1);
1236 val &= ~(MAC_PHYCFG1_RGMII_INT |
1237 MAC_PHYCFG1_RXCLK_TO_MASK | MAC_PHYCFG1_TXCLK_TO_MASK);
1238 val |= MAC_PHYCFG1_RXCLK_TIMEOUT | MAC_PHYCFG1_TXCLK_TIMEOUT;
1239 tw32(MAC_PHYCFG1, val);
1244 if (!tg3_flag(tp, RGMII_INBAND_DISABLE))
1245 val |= MAC_PHYCFG2_EMODE_MASK_MASK |
1246 MAC_PHYCFG2_FMODE_MASK_MASK |
1247 MAC_PHYCFG2_GMODE_MASK_MASK |
1248 MAC_PHYCFG2_ACT_MASK_MASK |
1249 MAC_PHYCFG2_QUAL_MASK_MASK |
1250 MAC_PHYCFG2_INBAND_ENABLE;
1252 tw32(MAC_PHYCFG2, val);
1254 val = tr32(MAC_PHYCFG1);
1255 val &= ~(MAC_PHYCFG1_RXCLK_TO_MASK | MAC_PHYCFG1_TXCLK_TO_MASK |
1256 MAC_PHYCFG1_RGMII_EXT_RX_DEC | MAC_PHYCFG1_RGMII_SND_STAT_EN);
1257 if (!tg3_flag(tp, RGMII_INBAND_DISABLE)) {
1258 if (tg3_flag(tp, RGMII_EXT_IBND_RX_EN))
1259 val |= MAC_PHYCFG1_RGMII_EXT_RX_DEC;
1260 if (tg3_flag(tp, RGMII_EXT_IBND_TX_EN))
1261 val |= MAC_PHYCFG1_RGMII_SND_STAT_EN;
1263 val |= MAC_PHYCFG1_RXCLK_TIMEOUT | MAC_PHYCFG1_TXCLK_TIMEOUT |
1264 MAC_PHYCFG1_RGMII_INT | MAC_PHYCFG1_TXC_DRV;
1265 tw32(MAC_PHYCFG1, val);
1267 val = tr32(MAC_EXT_RGMII_MODE);
1268 val &= ~(MAC_RGMII_MODE_RX_INT_B |
1269 MAC_RGMII_MODE_RX_QUALITY |
1270 MAC_RGMII_MODE_RX_ACTIVITY |
1271 MAC_RGMII_MODE_RX_ENG_DET |
1272 MAC_RGMII_MODE_TX_ENABLE |
1273 MAC_RGMII_MODE_TX_LOWPWR |
1274 MAC_RGMII_MODE_TX_RESET);
1275 if (!tg3_flag(tp, RGMII_INBAND_DISABLE)) {
1276 if (tg3_flag(tp, RGMII_EXT_IBND_RX_EN))
1277 val |= MAC_RGMII_MODE_RX_INT_B |
1278 MAC_RGMII_MODE_RX_QUALITY |
1279 MAC_RGMII_MODE_RX_ACTIVITY |
1280 MAC_RGMII_MODE_RX_ENG_DET;
1281 if (tg3_flag(tp, RGMII_EXT_IBND_TX_EN))
1282 val |= MAC_RGMII_MODE_TX_ENABLE |
1283 MAC_RGMII_MODE_TX_LOWPWR |
1284 MAC_RGMII_MODE_TX_RESET;
1286 tw32(MAC_EXT_RGMII_MODE, val);
1289 static void tg3_mdio_start(struct tg3 *tp)
1291 tp->mi_mode &= ~MAC_MI_MODE_AUTO_POLL;
1292 tw32_f(MAC_MI_MODE, tp->mi_mode);
1295 if (tg3_flag(tp, MDIOBUS_INITED) &&
1296 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785)
1297 tg3_mdio_config_5785(tp);
1300 static int tg3_mdio_init(struct tg3 *tp)
1304 struct phy_device *phydev;
1306 if (tg3_flag(tp, 5717_PLUS)) {
1309 tp->phy_addr = tp->pci_fn + 1;
1311 if (tp->pci_chip_rev_id != CHIPREV_ID_5717_A0)
1312 is_serdes = tr32(SG_DIG_STATUS) & SG_DIG_IS_SERDES;
1314 is_serdes = tr32(TG3_CPMU_PHY_STRAP) &
1315 TG3_CPMU_PHY_STRAP_IS_SERDES;
1319 tp->phy_addr = TG3_PHY_MII_ADDR;
1323 if (!tg3_flag(tp, USE_PHYLIB) || tg3_flag(tp, MDIOBUS_INITED))
1326 tp->mdio_bus = mdiobus_alloc();
1327 if (tp->mdio_bus == NULL)
1330 tp->mdio_bus->name = "tg3 mdio bus";
1331 snprintf(tp->mdio_bus->id, MII_BUS_ID_SIZE, "%x",
1332 (tp->pdev->bus->number << 8) | tp->pdev->devfn);
1333 tp->mdio_bus->priv = tp;
1334 tp->mdio_bus->parent = &tp->pdev->dev;
1335 tp->mdio_bus->read = &tg3_mdio_read;
1336 tp->mdio_bus->write = &tg3_mdio_write;
1337 tp->mdio_bus->reset = &tg3_mdio_reset;
1338 tp->mdio_bus->phy_mask = ~(1 << TG3_PHY_MII_ADDR);
1339 tp->mdio_bus->irq = &tp->mdio_irq[0];
1341 for (i = 0; i < PHY_MAX_ADDR; i++)
1342 tp->mdio_bus->irq[i] = PHY_POLL;
1344 /* The bus registration will look for all the PHYs on the mdio bus.
1345 * Unfortunately, it does not ensure the PHY is powered up before
1346 * accessing the PHY ID registers. A chip reset is the
1347 * quickest way to bring the device back to an operational state..
1349 if (tg3_readphy(tp, MII_BMCR, ®) || (reg & BMCR_PDOWN))
1352 i = mdiobus_register(tp->mdio_bus);
1354 dev_warn(&tp->pdev->dev, "mdiobus_reg failed (0x%x)\n", i);
1355 mdiobus_free(tp->mdio_bus);
1359 phydev = tp->mdio_bus->phy_map[TG3_PHY_MII_ADDR];
1361 if (!phydev || !phydev->drv) {
1362 dev_warn(&tp->pdev->dev, "No PHY devices\n");
1363 mdiobus_unregister(tp->mdio_bus);
1364 mdiobus_free(tp->mdio_bus);
1368 switch (phydev->drv->phy_id & phydev->drv->phy_id_mask) {
1369 case PHY_ID_BCM57780:
1370 phydev->interface = PHY_INTERFACE_MODE_GMII;
1371 phydev->dev_flags |= PHY_BRCM_AUTO_PWRDWN_ENABLE;
1373 case PHY_ID_BCM50610:
1374 case PHY_ID_BCM50610M:
1375 phydev->dev_flags |= PHY_BRCM_CLEAR_RGMII_MODE |
1376 PHY_BRCM_RX_REFCLK_UNUSED |
1377 PHY_BRCM_DIS_TXCRXC_NOENRGY |
1378 PHY_BRCM_AUTO_PWRDWN_ENABLE;
1379 if (tg3_flag(tp, RGMII_INBAND_DISABLE))
1380 phydev->dev_flags |= PHY_BRCM_STD_IBND_DISABLE;
1381 if (tg3_flag(tp, RGMII_EXT_IBND_RX_EN))
1382 phydev->dev_flags |= PHY_BRCM_EXT_IBND_RX_ENABLE;
1383 if (tg3_flag(tp, RGMII_EXT_IBND_TX_EN))
1384 phydev->dev_flags |= PHY_BRCM_EXT_IBND_TX_ENABLE;
1386 case PHY_ID_RTL8211C:
1387 phydev->interface = PHY_INTERFACE_MODE_RGMII;
1389 case PHY_ID_RTL8201E:
1390 case PHY_ID_BCMAC131:
1391 phydev->interface = PHY_INTERFACE_MODE_MII;
1392 phydev->dev_flags |= PHY_BRCM_AUTO_PWRDWN_ENABLE;
1393 tp->phy_flags |= TG3_PHYFLG_IS_FET;
1397 tg3_flag_set(tp, MDIOBUS_INITED);
1399 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785)
1400 tg3_mdio_config_5785(tp);
1405 static void tg3_mdio_fini(struct tg3 *tp)
1407 if (tg3_flag(tp, MDIOBUS_INITED)) {
1408 tg3_flag_clear(tp, MDIOBUS_INITED);
1409 mdiobus_unregister(tp->mdio_bus);
1410 mdiobus_free(tp->mdio_bus);
1414 /* tp->lock is held. */
1415 static inline void tg3_generate_fw_event(struct tg3 *tp)
1419 val = tr32(GRC_RX_CPU_EVENT);
1420 val |= GRC_RX_CPU_DRIVER_EVENT;
1421 tw32_f(GRC_RX_CPU_EVENT, val);
1423 tp->last_event_jiffies = jiffies;
1426 #define TG3_FW_EVENT_TIMEOUT_USEC 2500
1428 /* tp->lock is held. */
1429 static void tg3_wait_for_event_ack(struct tg3 *tp)
1432 unsigned int delay_cnt;
1435 /* If enough time has passed, no wait is necessary. */
1436 time_remain = (long)(tp->last_event_jiffies + 1 +
1437 usecs_to_jiffies(TG3_FW_EVENT_TIMEOUT_USEC)) -
1439 if (time_remain < 0)
1442 /* Check if we can shorten the wait time. */
1443 delay_cnt = jiffies_to_usecs(time_remain);
1444 if (delay_cnt > TG3_FW_EVENT_TIMEOUT_USEC)
1445 delay_cnt = TG3_FW_EVENT_TIMEOUT_USEC;
1446 delay_cnt = (delay_cnt >> 3) + 1;
1448 for (i = 0; i < delay_cnt; i++) {
1449 if (!(tr32(GRC_RX_CPU_EVENT) & GRC_RX_CPU_DRIVER_EVENT))
1455 /* tp->lock is held. */
1456 static void tg3_ump_link_report(struct tg3 *tp)
1461 if (!tg3_flag(tp, 5780_CLASS) || !tg3_flag(tp, ENABLE_ASF))
1464 tg3_wait_for_event_ack(tp);
1466 tg3_write_mem(tp, NIC_SRAM_FW_CMD_MBOX, FWCMD_NICDRV_LINK_UPDATE);
1468 tg3_write_mem(tp, NIC_SRAM_FW_CMD_LEN_MBOX, 14);
1471 if (!tg3_readphy(tp, MII_BMCR, ®))
1473 if (!tg3_readphy(tp, MII_BMSR, ®))
1474 val |= (reg & 0xffff);
1475 tg3_write_mem(tp, NIC_SRAM_FW_CMD_DATA_MBOX, val);
1478 if (!tg3_readphy(tp, MII_ADVERTISE, ®))
1480 if (!tg3_readphy(tp, MII_LPA, ®))
1481 val |= (reg & 0xffff);
1482 tg3_write_mem(tp, NIC_SRAM_FW_CMD_DATA_MBOX + 4, val);
1485 if (!(tp->phy_flags & TG3_PHYFLG_MII_SERDES)) {
1486 if (!tg3_readphy(tp, MII_CTRL1000, ®))
1488 if (!tg3_readphy(tp, MII_STAT1000, ®))
1489 val |= (reg & 0xffff);
1491 tg3_write_mem(tp, NIC_SRAM_FW_CMD_DATA_MBOX + 8, val);
1493 if (!tg3_readphy(tp, MII_PHYADDR, ®))
1497 tg3_write_mem(tp, NIC_SRAM_FW_CMD_DATA_MBOX + 12, val);
1499 tg3_generate_fw_event(tp);
1502 /* tp->lock is held. */
1503 static void tg3_stop_fw(struct tg3 *tp)
1505 if (tg3_flag(tp, ENABLE_ASF) && !tg3_flag(tp, ENABLE_APE)) {
1506 /* Wait for RX cpu to ACK the previous event. */
1507 tg3_wait_for_event_ack(tp);
1509 tg3_write_mem(tp, NIC_SRAM_FW_CMD_MBOX, FWCMD_NICDRV_PAUSE_FW);
1511 tg3_generate_fw_event(tp);
1513 /* Wait for RX cpu to ACK this event. */
1514 tg3_wait_for_event_ack(tp);
1518 /* tp->lock is held. */
1519 static void tg3_write_sig_pre_reset(struct tg3 *tp, int kind)
1521 tg3_write_mem(tp, NIC_SRAM_FIRMWARE_MBOX,
1522 NIC_SRAM_FIRMWARE_MBOX_MAGIC1);
1524 if (tg3_flag(tp, ASF_NEW_HANDSHAKE)) {
1526 case RESET_KIND_INIT:
1527 tg3_write_mem(tp, NIC_SRAM_FW_DRV_STATE_MBOX,
1531 case RESET_KIND_SHUTDOWN:
1532 tg3_write_mem(tp, NIC_SRAM_FW_DRV_STATE_MBOX,
1536 case RESET_KIND_SUSPEND:
1537 tg3_write_mem(tp, NIC_SRAM_FW_DRV_STATE_MBOX,
1546 if (kind == RESET_KIND_INIT ||
1547 kind == RESET_KIND_SUSPEND)
1548 tg3_ape_driver_state_change(tp, kind);
1551 /* tp->lock is held. */
1552 static void tg3_write_sig_post_reset(struct tg3 *tp, int kind)
1554 if (tg3_flag(tp, ASF_NEW_HANDSHAKE)) {
1556 case RESET_KIND_INIT:
1557 tg3_write_mem(tp, NIC_SRAM_FW_DRV_STATE_MBOX,
1558 DRV_STATE_START_DONE);
1561 case RESET_KIND_SHUTDOWN:
1562 tg3_write_mem(tp, NIC_SRAM_FW_DRV_STATE_MBOX,
1563 DRV_STATE_UNLOAD_DONE);
1571 if (kind == RESET_KIND_SHUTDOWN)
1572 tg3_ape_driver_state_change(tp, kind);
1575 /* tp->lock is held. */
1576 static void tg3_write_sig_legacy(struct tg3 *tp, int kind)
1578 if (tg3_flag(tp, ENABLE_ASF)) {
1580 case RESET_KIND_INIT:
1581 tg3_write_mem(tp, NIC_SRAM_FW_DRV_STATE_MBOX,
1585 case RESET_KIND_SHUTDOWN:
1586 tg3_write_mem(tp, NIC_SRAM_FW_DRV_STATE_MBOX,
1590 case RESET_KIND_SUSPEND:
1591 tg3_write_mem(tp, NIC_SRAM_FW_DRV_STATE_MBOX,
1601 static int tg3_poll_fw(struct tg3 *tp)
1606 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
1607 /* Wait up to 20ms for init done. */
1608 for (i = 0; i < 200; i++) {
1609 if (tr32(VCPU_STATUS) & VCPU_STATUS_INIT_DONE)
1616 /* Wait for firmware initialization to complete. */
1617 for (i = 0; i < 100000; i++) {
1618 tg3_read_mem(tp, NIC_SRAM_FIRMWARE_MBOX, &val);
1619 if (val == ~NIC_SRAM_FIRMWARE_MBOX_MAGIC1)
1624 /* Chip might not be fitted with firmware. Some Sun onboard
1625 * parts are configured like that. So don't signal the timeout
1626 * of the above loop as an error, but do report the lack of
1627 * running firmware once.
1629 if (i >= 100000 && !tg3_flag(tp, NO_FWARE_REPORTED)) {
1630 tg3_flag_set(tp, NO_FWARE_REPORTED);
1632 netdev_info(tp->dev, "No firmware running\n");
1635 if (tp->pci_chip_rev_id == CHIPREV_ID_57765_A0) {
1636 /* The 57765 A0 needs a little more
1637 * time to do some important work.
1645 static void tg3_link_report(struct tg3 *tp)
1647 if (!netif_carrier_ok(tp->dev)) {
1648 netif_info(tp, link, tp->dev, "Link is down\n");
1649 tg3_ump_link_report(tp);
1650 } else if (netif_msg_link(tp)) {
1651 netdev_info(tp->dev, "Link is up at %d Mbps, %s duplex\n",
1652 (tp->link_config.active_speed == SPEED_1000 ?
1654 (tp->link_config.active_speed == SPEED_100 ?
1656 (tp->link_config.active_duplex == DUPLEX_FULL ?
1659 netdev_info(tp->dev, "Flow control is %s for TX and %s for RX\n",
1660 (tp->link_config.active_flowctrl & FLOW_CTRL_TX) ?
1662 (tp->link_config.active_flowctrl & FLOW_CTRL_RX) ?
1665 if (tp->phy_flags & TG3_PHYFLG_EEE_CAP)
1666 netdev_info(tp->dev, "EEE is %s\n",
1667 tp->setlpicnt ? "enabled" : "disabled");
1669 tg3_ump_link_report(tp);
1673 static u16 tg3_advert_flowctrl_1000X(u8 flow_ctrl)
1677 if ((flow_ctrl & FLOW_CTRL_TX) && (flow_ctrl & FLOW_CTRL_RX))
1678 miireg = ADVERTISE_1000XPAUSE;
1679 else if (flow_ctrl & FLOW_CTRL_TX)
1680 miireg = ADVERTISE_1000XPSE_ASYM;
1681 else if (flow_ctrl & FLOW_CTRL_RX)
1682 miireg = ADVERTISE_1000XPAUSE | ADVERTISE_1000XPSE_ASYM;
1689 static u8 tg3_resolve_flowctrl_1000X(u16 lcladv, u16 rmtadv)
1693 if (lcladv & rmtadv & ADVERTISE_1000XPAUSE) {
1694 cap = FLOW_CTRL_TX | FLOW_CTRL_RX;
1695 } else if (lcladv & rmtadv & ADVERTISE_1000XPSE_ASYM) {
1696 if (lcladv & ADVERTISE_1000XPAUSE)
1698 if (rmtadv & ADVERTISE_1000XPAUSE)
1705 static void tg3_setup_flow_control(struct tg3 *tp, u32 lcladv, u32 rmtadv)
1709 u32 old_rx_mode = tp->rx_mode;
1710 u32 old_tx_mode = tp->tx_mode;
1712 if (tg3_flag(tp, USE_PHYLIB))
1713 autoneg = tp->mdio_bus->phy_map[TG3_PHY_MII_ADDR]->autoneg;
1715 autoneg = tp->link_config.autoneg;
1717 if (autoneg == AUTONEG_ENABLE && tg3_flag(tp, PAUSE_AUTONEG)) {
1718 if (tp->phy_flags & TG3_PHYFLG_ANY_SERDES)
1719 flowctrl = tg3_resolve_flowctrl_1000X(lcladv, rmtadv);
1721 flowctrl = mii_resolve_flowctrl_fdx(lcladv, rmtadv);
1723 flowctrl = tp->link_config.flowctrl;
1725 tp->link_config.active_flowctrl = flowctrl;
1727 if (flowctrl & FLOW_CTRL_RX)
1728 tp->rx_mode |= RX_MODE_FLOW_CTRL_ENABLE;
1730 tp->rx_mode &= ~RX_MODE_FLOW_CTRL_ENABLE;
1732 if (old_rx_mode != tp->rx_mode)
1733 tw32_f(MAC_RX_MODE, tp->rx_mode);
1735 if (flowctrl & FLOW_CTRL_TX)
1736 tp->tx_mode |= TX_MODE_FLOW_CTRL_ENABLE;
1738 tp->tx_mode &= ~TX_MODE_FLOW_CTRL_ENABLE;
1740 if (old_tx_mode != tp->tx_mode)
1741 tw32_f(MAC_TX_MODE, tp->tx_mode);
1744 static void tg3_adjust_link(struct net_device *dev)
1746 u8 oldflowctrl, linkmesg = 0;
1747 u32 mac_mode, lcl_adv, rmt_adv;
1748 struct tg3 *tp = netdev_priv(dev);
1749 struct phy_device *phydev = tp->mdio_bus->phy_map[TG3_PHY_MII_ADDR];
1751 spin_lock_bh(&tp->lock);
1753 mac_mode = tp->mac_mode & ~(MAC_MODE_PORT_MODE_MASK |
1754 MAC_MODE_HALF_DUPLEX);
1756 oldflowctrl = tp->link_config.active_flowctrl;
1762 if (phydev->speed == SPEED_100 || phydev->speed == SPEED_10)
1763 mac_mode |= MAC_MODE_PORT_MODE_MII;
1764 else if (phydev->speed == SPEED_1000 ||
1765 GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5785)
1766 mac_mode |= MAC_MODE_PORT_MODE_GMII;
1768 mac_mode |= MAC_MODE_PORT_MODE_MII;
1770 if (phydev->duplex == DUPLEX_HALF)
1771 mac_mode |= MAC_MODE_HALF_DUPLEX;
1773 lcl_adv = mii_advertise_flowctrl(
1774 tp->link_config.flowctrl);
1777 rmt_adv = LPA_PAUSE_CAP;
1778 if (phydev->asym_pause)
1779 rmt_adv |= LPA_PAUSE_ASYM;
1782 tg3_setup_flow_control(tp, lcl_adv, rmt_adv);
1784 mac_mode |= MAC_MODE_PORT_MODE_GMII;
1786 if (mac_mode != tp->mac_mode) {
1787 tp->mac_mode = mac_mode;
1788 tw32_f(MAC_MODE, tp->mac_mode);
1792 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785) {
1793 if (phydev->speed == SPEED_10)
1795 MAC_MI_STAT_10MBPS_MODE |
1796 MAC_MI_STAT_LNKSTAT_ATTN_ENAB);
1798 tw32(MAC_MI_STAT, MAC_MI_STAT_LNKSTAT_ATTN_ENAB);
1801 if (phydev->speed == SPEED_1000 && phydev->duplex == DUPLEX_HALF)
1802 tw32(MAC_TX_LENGTHS,
1803 ((2 << TX_LENGTHS_IPG_CRS_SHIFT) |
1804 (6 << TX_LENGTHS_IPG_SHIFT) |
1805 (0xff << TX_LENGTHS_SLOT_TIME_SHIFT)));
1807 tw32(MAC_TX_LENGTHS,
1808 ((2 << TX_LENGTHS_IPG_CRS_SHIFT) |
1809 (6 << TX_LENGTHS_IPG_SHIFT) |
1810 (32 << TX_LENGTHS_SLOT_TIME_SHIFT)));
1812 if ((phydev->link && tp->link_config.active_speed == SPEED_INVALID) ||
1813 (!phydev->link && tp->link_config.active_speed != SPEED_INVALID) ||
1814 phydev->speed != tp->link_config.active_speed ||
1815 phydev->duplex != tp->link_config.active_duplex ||
1816 oldflowctrl != tp->link_config.active_flowctrl)
1819 tp->link_config.active_speed = phydev->speed;
1820 tp->link_config.active_duplex = phydev->duplex;
1822 spin_unlock_bh(&tp->lock);
1825 tg3_link_report(tp);
1828 static int tg3_phy_init(struct tg3 *tp)
1830 struct phy_device *phydev;
1832 if (tp->phy_flags & TG3_PHYFLG_IS_CONNECTED)
1835 /* Bring the PHY back to a known state. */
1838 phydev = tp->mdio_bus->phy_map[TG3_PHY_MII_ADDR];
1840 /* Attach the MAC to the PHY. */
1841 phydev = phy_connect(tp->dev, dev_name(&phydev->dev), tg3_adjust_link,
1842 phydev->dev_flags, phydev->interface);
1843 if (IS_ERR(phydev)) {
1844 dev_err(&tp->pdev->dev, "Could not attach to PHY\n");
1845 return PTR_ERR(phydev);
1848 /* Mask with MAC supported features. */
1849 switch (phydev->interface) {
1850 case PHY_INTERFACE_MODE_GMII:
1851 case PHY_INTERFACE_MODE_RGMII:
1852 if (!(tp->phy_flags & TG3_PHYFLG_10_100_ONLY)) {
1853 phydev->supported &= (PHY_GBIT_FEATURES |
1855 SUPPORTED_Asym_Pause);
1859 case PHY_INTERFACE_MODE_MII:
1860 phydev->supported &= (PHY_BASIC_FEATURES |
1862 SUPPORTED_Asym_Pause);
1865 phy_disconnect(tp->mdio_bus->phy_map[TG3_PHY_MII_ADDR]);
1869 tp->phy_flags |= TG3_PHYFLG_IS_CONNECTED;
1871 phydev->advertising = phydev->supported;
1876 static void tg3_phy_start(struct tg3 *tp)
1878 struct phy_device *phydev;
1880 if (!(tp->phy_flags & TG3_PHYFLG_IS_CONNECTED))
1883 phydev = tp->mdio_bus->phy_map[TG3_PHY_MII_ADDR];
1885 if (tp->phy_flags & TG3_PHYFLG_IS_LOW_POWER) {
1886 tp->phy_flags &= ~TG3_PHYFLG_IS_LOW_POWER;
1887 phydev->speed = tp->link_config.orig_speed;
1888 phydev->duplex = tp->link_config.orig_duplex;
1889 phydev->autoneg = tp->link_config.orig_autoneg;
1890 phydev->advertising = tp->link_config.orig_advertising;
1895 phy_start_aneg(phydev);
1898 static void tg3_phy_stop(struct tg3 *tp)
1900 if (!(tp->phy_flags & TG3_PHYFLG_IS_CONNECTED))
1903 phy_stop(tp->mdio_bus->phy_map[TG3_PHY_MII_ADDR]);
1906 static void tg3_phy_fini(struct tg3 *tp)
1908 if (tp->phy_flags & TG3_PHYFLG_IS_CONNECTED) {
1909 phy_disconnect(tp->mdio_bus->phy_map[TG3_PHY_MII_ADDR]);
1910 tp->phy_flags &= ~TG3_PHYFLG_IS_CONNECTED;
1914 static int tg3_phy_set_extloopbk(struct tg3 *tp)
1919 if (tp->phy_flags & TG3_PHYFLG_IS_FET)
1922 if ((tp->phy_id & TG3_PHY_ID_MASK) == TG3_PHY_ID_BCM5401) {
1923 /* Cannot do read-modify-write on 5401 */
1924 err = tg3_phy_auxctl_write(tp,
1925 MII_TG3_AUXCTL_SHDWSEL_AUXCTL,
1926 MII_TG3_AUXCTL_ACTL_EXTLOOPBK |
1931 err = tg3_phy_auxctl_read(tp,
1932 MII_TG3_AUXCTL_SHDWSEL_AUXCTL, &val);
1936 val |= MII_TG3_AUXCTL_ACTL_EXTLOOPBK;
1937 err = tg3_phy_auxctl_write(tp,
1938 MII_TG3_AUXCTL_SHDWSEL_AUXCTL, val);
1944 static void tg3_phy_fet_toggle_apd(struct tg3 *tp, bool enable)
1948 if (!tg3_readphy(tp, MII_TG3_FET_TEST, &phytest)) {
1951 tg3_writephy(tp, MII_TG3_FET_TEST,
1952 phytest | MII_TG3_FET_SHADOW_EN);
1953 if (!tg3_readphy(tp, MII_TG3_FET_SHDW_AUXSTAT2, &phy)) {
1955 phy |= MII_TG3_FET_SHDW_AUXSTAT2_APD;
1957 phy &= ~MII_TG3_FET_SHDW_AUXSTAT2_APD;
1958 tg3_writephy(tp, MII_TG3_FET_SHDW_AUXSTAT2, phy);
1960 tg3_writephy(tp, MII_TG3_FET_TEST, phytest);
1964 static void tg3_phy_toggle_apd(struct tg3 *tp, bool enable)
1968 if (!tg3_flag(tp, 5705_PLUS) ||
1969 (tg3_flag(tp, 5717_PLUS) &&
1970 (tp->phy_flags & TG3_PHYFLG_MII_SERDES)))
1973 if (tp->phy_flags & TG3_PHYFLG_IS_FET) {
1974 tg3_phy_fet_toggle_apd(tp, enable);
1978 reg = MII_TG3_MISC_SHDW_WREN |
1979 MII_TG3_MISC_SHDW_SCR5_SEL |
1980 MII_TG3_MISC_SHDW_SCR5_LPED |
1981 MII_TG3_MISC_SHDW_SCR5_DLPTLM |
1982 MII_TG3_MISC_SHDW_SCR5_SDTL |
1983 MII_TG3_MISC_SHDW_SCR5_C125OE;
1984 if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5784 || !enable)
1985 reg |= MII_TG3_MISC_SHDW_SCR5_DLLAPD;
1987 tg3_writephy(tp, MII_TG3_MISC_SHDW, reg);
1990 reg = MII_TG3_MISC_SHDW_WREN |
1991 MII_TG3_MISC_SHDW_APD_SEL |
1992 MII_TG3_MISC_SHDW_APD_WKTM_84MS;
1994 reg |= MII_TG3_MISC_SHDW_APD_ENABLE;
1996 tg3_writephy(tp, MII_TG3_MISC_SHDW, reg);
1999 static void tg3_phy_toggle_automdix(struct tg3 *tp, int enable)
2003 if (!tg3_flag(tp, 5705_PLUS) ||
2004 (tp->phy_flags & TG3_PHYFLG_ANY_SERDES))
2007 if (tp->phy_flags & TG3_PHYFLG_IS_FET) {
2010 if (!tg3_readphy(tp, MII_TG3_FET_TEST, &ephy)) {
2011 u32 reg = MII_TG3_FET_SHDW_MISCCTRL;
2013 tg3_writephy(tp, MII_TG3_FET_TEST,
2014 ephy | MII_TG3_FET_SHADOW_EN);
2015 if (!tg3_readphy(tp, reg, &phy)) {
2017 phy |= MII_TG3_FET_SHDW_MISCCTRL_MDIX;
2019 phy &= ~MII_TG3_FET_SHDW_MISCCTRL_MDIX;
2020 tg3_writephy(tp, reg, phy);
2022 tg3_writephy(tp, MII_TG3_FET_TEST, ephy);
2027 ret = tg3_phy_auxctl_read(tp,
2028 MII_TG3_AUXCTL_SHDWSEL_MISC, &phy);
2031 phy |= MII_TG3_AUXCTL_MISC_FORCE_AMDIX;
2033 phy &= ~MII_TG3_AUXCTL_MISC_FORCE_AMDIX;
2034 tg3_phy_auxctl_write(tp,
2035 MII_TG3_AUXCTL_SHDWSEL_MISC, phy);
2040 static void tg3_phy_set_wirespeed(struct tg3 *tp)
2045 if (tp->phy_flags & TG3_PHYFLG_NO_ETH_WIRE_SPEED)
2048 ret = tg3_phy_auxctl_read(tp, MII_TG3_AUXCTL_SHDWSEL_MISC, &val);
2050 tg3_phy_auxctl_write(tp, MII_TG3_AUXCTL_SHDWSEL_MISC,
2051 val | MII_TG3_AUXCTL_MISC_WIRESPD_EN);
2054 static void tg3_phy_apply_otp(struct tg3 *tp)
2063 if (TG3_PHY_AUXCTL_SMDSP_ENABLE(tp))
2066 phy = ((otp & TG3_OTP_AGCTGT_MASK) >> TG3_OTP_AGCTGT_SHIFT);
2067 phy |= MII_TG3_DSP_TAP1_AGCTGT_DFLT;
2068 tg3_phydsp_write(tp, MII_TG3_DSP_TAP1, phy);
2070 phy = ((otp & TG3_OTP_HPFFLTR_MASK) >> TG3_OTP_HPFFLTR_SHIFT) |
2071 ((otp & TG3_OTP_HPFOVER_MASK) >> TG3_OTP_HPFOVER_SHIFT);
2072 tg3_phydsp_write(tp, MII_TG3_DSP_AADJ1CH0, phy);
2074 phy = ((otp & TG3_OTP_LPFDIS_MASK) >> TG3_OTP_LPFDIS_SHIFT);
2075 phy |= MII_TG3_DSP_AADJ1CH3_ADCCKADJ;
2076 tg3_phydsp_write(tp, MII_TG3_DSP_AADJ1CH3, phy);
2078 phy = ((otp & TG3_OTP_VDAC_MASK) >> TG3_OTP_VDAC_SHIFT);
2079 tg3_phydsp_write(tp, MII_TG3_DSP_EXP75, phy);
2081 phy = ((otp & TG3_OTP_10BTAMP_MASK) >> TG3_OTP_10BTAMP_SHIFT);
2082 tg3_phydsp_write(tp, MII_TG3_DSP_EXP96, phy);
2084 phy = ((otp & TG3_OTP_ROFF_MASK) >> TG3_OTP_ROFF_SHIFT) |
2085 ((otp & TG3_OTP_RCOFF_MASK) >> TG3_OTP_RCOFF_SHIFT);
2086 tg3_phydsp_write(tp, MII_TG3_DSP_EXP97, phy);
2088 TG3_PHY_AUXCTL_SMDSP_DISABLE(tp);
2091 static void tg3_phy_eee_adjust(struct tg3 *tp, u32 current_link_up)
2095 if (!(tp->phy_flags & TG3_PHYFLG_EEE_CAP))
2100 if (tp->link_config.autoneg == AUTONEG_ENABLE &&
2101 current_link_up == 1 &&
2102 tp->link_config.active_duplex == DUPLEX_FULL &&
2103 (tp->link_config.active_speed == SPEED_100 ||
2104 tp->link_config.active_speed == SPEED_1000)) {
2107 if (tp->link_config.active_speed == SPEED_1000)
2108 eeectl = TG3_CPMU_EEE_CTRL_EXIT_16_5_US;
2110 eeectl = TG3_CPMU_EEE_CTRL_EXIT_36_US;
2112 tw32(TG3_CPMU_EEE_CTRL, eeectl);
2114 tg3_phy_cl45_read(tp, MDIO_MMD_AN,
2115 TG3_CL45_D7_EEERES_STAT, &val);
2117 if (val == TG3_CL45_D7_EEERES_STAT_LP_1000T ||
2118 val == TG3_CL45_D7_EEERES_STAT_LP_100TX)
2122 if (!tp->setlpicnt) {
2123 if (current_link_up == 1 &&
2124 !TG3_PHY_AUXCTL_SMDSP_ENABLE(tp)) {
2125 tg3_phydsp_write(tp, MII_TG3_DSP_TAP26, 0x0000);
2126 TG3_PHY_AUXCTL_SMDSP_DISABLE(tp);
2129 val = tr32(TG3_CPMU_EEE_MODE);
2130 tw32(TG3_CPMU_EEE_MODE, val & ~TG3_CPMU_EEEMD_LPI_ENABLE);
2134 static void tg3_phy_eee_enable(struct tg3 *tp)
2138 if (tp->link_config.active_speed == SPEED_1000 &&
2139 (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717 ||
2140 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5719 ||
2141 tg3_flag(tp, 57765_CLASS)) &&
2142 !TG3_PHY_AUXCTL_SMDSP_ENABLE(tp)) {
2143 val = MII_TG3_DSP_TAP26_ALNOKO |
2144 MII_TG3_DSP_TAP26_RMRXSTO;
2145 tg3_phydsp_write(tp, MII_TG3_DSP_TAP26, val);
2146 TG3_PHY_AUXCTL_SMDSP_DISABLE(tp);
2149 val = tr32(TG3_CPMU_EEE_MODE);
2150 tw32(TG3_CPMU_EEE_MODE, val | TG3_CPMU_EEEMD_LPI_ENABLE);
2153 static int tg3_wait_macro_done(struct tg3 *tp)
2160 if (!tg3_readphy(tp, MII_TG3_DSP_CONTROL, &tmp32)) {
2161 if ((tmp32 & 0x1000) == 0)
2171 static int tg3_phy_write_and_check_testpat(struct tg3 *tp, int *resetp)
2173 static const u32 test_pat[4][6] = {
2174 { 0x00005555, 0x00000005, 0x00002aaa, 0x0000000a, 0x00003456, 0x00000003 },
2175 { 0x00002aaa, 0x0000000a, 0x00003333, 0x00000003, 0x0000789a, 0x00000005 },
2176 { 0x00005a5a, 0x00000005, 0x00002a6a, 0x0000000a, 0x00001bcd, 0x00000003 },
2177 { 0x00002a5a, 0x0000000a, 0x000033c3, 0x00000003, 0x00002ef1, 0x00000005 }
2181 for (chan = 0; chan < 4; chan++) {
2184 tg3_writephy(tp, MII_TG3_DSP_ADDRESS,
2185 (chan * 0x2000) | 0x0200);
2186 tg3_writephy(tp, MII_TG3_DSP_CONTROL, 0x0002);
2188 for (i = 0; i < 6; i++)
2189 tg3_writephy(tp, MII_TG3_DSP_RW_PORT,
2192 tg3_writephy(tp, MII_TG3_DSP_CONTROL, 0x0202);
2193 if (tg3_wait_macro_done(tp)) {
2198 tg3_writephy(tp, MII_TG3_DSP_ADDRESS,
2199 (chan * 0x2000) | 0x0200);
2200 tg3_writephy(tp, MII_TG3_DSP_CONTROL, 0x0082);
2201 if (tg3_wait_macro_done(tp)) {
2206 tg3_writephy(tp, MII_TG3_DSP_CONTROL, 0x0802);
2207 if (tg3_wait_macro_done(tp)) {
2212 for (i = 0; i < 6; i += 2) {
2215 if (tg3_readphy(tp, MII_TG3_DSP_RW_PORT, &low) ||
2216 tg3_readphy(tp, MII_TG3_DSP_RW_PORT, &high) ||
2217 tg3_wait_macro_done(tp)) {
2223 if (low != test_pat[chan][i] ||
2224 high != test_pat[chan][i+1]) {
2225 tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x000b);
2226 tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x4001);
2227 tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x4005);
2237 static int tg3_phy_reset_chanpat(struct tg3 *tp)
2241 for (chan = 0; chan < 4; chan++) {
2244 tg3_writephy(tp, MII_TG3_DSP_ADDRESS,
2245 (chan * 0x2000) | 0x0200);
2246 tg3_writephy(tp, MII_TG3_DSP_CONTROL, 0x0002);
2247 for (i = 0; i < 6; i++)
2248 tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x000);
2249 tg3_writephy(tp, MII_TG3_DSP_CONTROL, 0x0202);
2250 if (tg3_wait_macro_done(tp))
2257 static int tg3_phy_reset_5703_4_5(struct tg3 *tp)
2259 u32 reg32, phy9_orig;
2260 int retries, do_phy_reset, err;
2266 err = tg3_bmcr_reset(tp);
2272 /* Disable transmitter and interrupt. */
2273 if (tg3_readphy(tp, MII_TG3_EXT_CTRL, ®32))
2277 tg3_writephy(tp, MII_TG3_EXT_CTRL, reg32);
2279 /* Set full-duplex, 1000 mbps. */
2280 tg3_writephy(tp, MII_BMCR,
2281 BMCR_FULLDPLX | BMCR_SPEED1000);
2283 /* Set to master mode. */
2284 if (tg3_readphy(tp, MII_CTRL1000, &phy9_orig))
2287 tg3_writephy(tp, MII_CTRL1000,
2288 CTL1000_AS_MASTER | CTL1000_ENABLE_MASTER);
2290 err = TG3_PHY_AUXCTL_SMDSP_ENABLE(tp);
2294 /* Block the PHY control access. */
2295 tg3_phydsp_write(tp, 0x8005, 0x0800);
2297 err = tg3_phy_write_and_check_testpat(tp, &do_phy_reset);
2300 } while (--retries);
2302 err = tg3_phy_reset_chanpat(tp);
2306 tg3_phydsp_write(tp, 0x8005, 0x0000);
2308 tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x8200);
2309 tg3_writephy(tp, MII_TG3_DSP_CONTROL, 0x0000);
2311 TG3_PHY_AUXCTL_SMDSP_DISABLE(tp);
2313 tg3_writephy(tp, MII_CTRL1000, phy9_orig);
2315 if (!tg3_readphy(tp, MII_TG3_EXT_CTRL, ®32)) {
2317 tg3_writephy(tp, MII_TG3_EXT_CTRL, reg32);
2324 /* This will reset the tigon3 PHY if there is no valid
2325 * link unless the FORCE argument is non-zero.
2327 static int tg3_phy_reset(struct tg3 *tp)
2332 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
2333 val = tr32(GRC_MISC_CFG);
2334 tw32_f(GRC_MISC_CFG, val & ~GRC_MISC_CFG_EPHY_IDDQ);
2337 err = tg3_readphy(tp, MII_BMSR, &val);
2338 err |= tg3_readphy(tp, MII_BMSR, &val);
2342 if (netif_running(tp->dev) && netif_carrier_ok(tp->dev)) {
2343 netif_carrier_off(tp->dev);
2344 tg3_link_report(tp);
2347 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703 ||
2348 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704 ||
2349 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705) {
2350 err = tg3_phy_reset_5703_4_5(tp);
2357 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5784 &&
2358 GET_CHIP_REV(tp->pci_chip_rev_id) != CHIPREV_5784_AX) {
2359 cpmuctrl = tr32(TG3_CPMU_CTRL);
2360 if (cpmuctrl & CPMU_CTRL_GPHY_10MB_RXONLY)
2362 cpmuctrl & ~CPMU_CTRL_GPHY_10MB_RXONLY);
2365 err = tg3_bmcr_reset(tp);
2369 if (cpmuctrl & CPMU_CTRL_GPHY_10MB_RXONLY) {
2370 val = MII_TG3_DSP_EXP8_AEDW | MII_TG3_DSP_EXP8_REJ2MHz;
2371 tg3_phydsp_write(tp, MII_TG3_DSP_EXP8, val);
2373 tw32(TG3_CPMU_CTRL, cpmuctrl);
2376 if (GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5784_AX ||
2377 GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5761_AX) {
2378 val = tr32(TG3_CPMU_LSPD_1000MB_CLK);
2379 if ((val & CPMU_LSPD_1000MB_MACCLK_MASK) ==
2380 CPMU_LSPD_1000MB_MACCLK_12_5) {
2381 val &= ~CPMU_LSPD_1000MB_MACCLK_MASK;
2383 tw32_f(TG3_CPMU_LSPD_1000MB_CLK, val);
2387 if (tg3_flag(tp, 5717_PLUS) &&
2388 (tp->phy_flags & TG3_PHYFLG_MII_SERDES))
2391 tg3_phy_apply_otp(tp);
2393 if (tp->phy_flags & TG3_PHYFLG_ENABLE_APD)
2394 tg3_phy_toggle_apd(tp, true);
2396 tg3_phy_toggle_apd(tp, false);
2399 if ((tp->phy_flags & TG3_PHYFLG_ADC_BUG) &&
2400 !TG3_PHY_AUXCTL_SMDSP_ENABLE(tp)) {
2401 tg3_phydsp_write(tp, 0x201f, 0x2aaa);
2402 tg3_phydsp_write(tp, 0x000a, 0x0323);
2403 TG3_PHY_AUXCTL_SMDSP_DISABLE(tp);
2406 if (tp->phy_flags & TG3_PHYFLG_5704_A0_BUG) {
2407 tg3_writephy(tp, MII_TG3_MISC_SHDW, 0x8d68);
2408 tg3_writephy(tp, MII_TG3_MISC_SHDW, 0x8d68);
2411 if (tp->phy_flags & TG3_PHYFLG_BER_BUG) {
2412 if (!TG3_PHY_AUXCTL_SMDSP_ENABLE(tp)) {
2413 tg3_phydsp_write(tp, 0x000a, 0x310b);
2414 tg3_phydsp_write(tp, 0x201f, 0x9506);
2415 tg3_phydsp_write(tp, 0x401f, 0x14e2);
2416 TG3_PHY_AUXCTL_SMDSP_DISABLE(tp);
2418 } else if (tp->phy_flags & TG3_PHYFLG_JITTER_BUG) {
2419 if (!TG3_PHY_AUXCTL_SMDSP_ENABLE(tp)) {
2420 tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x000a);
2421 if (tp->phy_flags & TG3_PHYFLG_ADJUST_TRIM) {
2422 tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x110b);
2423 tg3_writephy(tp, MII_TG3_TEST1,
2424 MII_TG3_TEST1_TRIM_EN | 0x4);
2426 tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x010b);
2428 TG3_PHY_AUXCTL_SMDSP_DISABLE(tp);
2432 /* Set Extended packet length bit (bit 14) on all chips that */
2433 /* support jumbo frames */
2434 if ((tp->phy_id & TG3_PHY_ID_MASK) == TG3_PHY_ID_BCM5401) {
2435 /* Cannot do read-modify-write on 5401 */
2436 tg3_phy_auxctl_write(tp, MII_TG3_AUXCTL_SHDWSEL_AUXCTL, 0x4c20);
2437 } else if (tg3_flag(tp, JUMBO_CAPABLE)) {
2438 /* Set bit 14 with read-modify-write to preserve other bits */
2439 err = tg3_phy_auxctl_read(tp,
2440 MII_TG3_AUXCTL_SHDWSEL_AUXCTL, &val);
2442 tg3_phy_auxctl_write(tp, MII_TG3_AUXCTL_SHDWSEL_AUXCTL,
2443 val | MII_TG3_AUXCTL_ACTL_EXTPKTLEN);
2446 /* Set phy register 0x10 bit 0 to high fifo elasticity to support
2447 * jumbo frames transmission.
2449 if (tg3_flag(tp, JUMBO_CAPABLE)) {
2450 if (!tg3_readphy(tp, MII_TG3_EXT_CTRL, &val))
2451 tg3_writephy(tp, MII_TG3_EXT_CTRL,
2452 val | MII_TG3_EXT_CTRL_FIFO_ELASTIC);
2455 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
2456 /* adjust output voltage */
2457 tg3_writephy(tp, MII_TG3_FET_PTEST, 0x12);
2460 tg3_phy_toggle_automdix(tp, 1);
2461 tg3_phy_set_wirespeed(tp);
2465 #define TG3_GPIO_MSG_DRVR_PRES 0x00000001
2466 #define TG3_GPIO_MSG_NEED_VAUX 0x00000002
2467 #define TG3_GPIO_MSG_MASK (TG3_GPIO_MSG_DRVR_PRES | \
2468 TG3_GPIO_MSG_NEED_VAUX)
2469 #define TG3_GPIO_MSG_ALL_DRVR_PRES_MASK \
2470 ((TG3_GPIO_MSG_DRVR_PRES << 0) | \
2471 (TG3_GPIO_MSG_DRVR_PRES << 4) | \
2472 (TG3_GPIO_MSG_DRVR_PRES << 8) | \
2473 (TG3_GPIO_MSG_DRVR_PRES << 12))
2475 #define TG3_GPIO_MSG_ALL_NEED_VAUX_MASK \
2476 ((TG3_GPIO_MSG_NEED_VAUX << 0) | \
2477 (TG3_GPIO_MSG_NEED_VAUX << 4) | \
2478 (TG3_GPIO_MSG_NEED_VAUX << 8) | \
2479 (TG3_GPIO_MSG_NEED_VAUX << 12))
2481 static inline u32 tg3_set_function_status(struct tg3 *tp, u32 newstat)
2485 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717 ||
2486 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5719)
2487 status = tg3_ape_read32(tp, TG3_APE_GPIO_MSG);
2489 status = tr32(TG3_CPMU_DRV_STATUS);
2491 shift = TG3_APE_GPIO_MSG_SHIFT + 4 * tp->pci_fn;
2492 status &= ~(TG3_GPIO_MSG_MASK << shift);
2493 status |= (newstat << shift);
2495 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717 ||
2496 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5719)
2497 tg3_ape_write32(tp, TG3_APE_GPIO_MSG, status);
2499 tw32(TG3_CPMU_DRV_STATUS, status);
2501 return status >> TG3_APE_GPIO_MSG_SHIFT;
2504 static inline int tg3_pwrsrc_switch_to_vmain(struct tg3 *tp)
2506 if (!tg3_flag(tp, IS_NIC))
2509 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717 ||
2510 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5719 ||
2511 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5720) {
2512 if (tg3_ape_lock(tp, TG3_APE_LOCK_GPIO))
2515 tg3_set_function_status(tp, TG3_GPIO_MSG_DRVR_PRES);
2517 tw32_wait_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl,
2518 TG3_GRC_LCLCTL_PWRSW_DELAY);
2520 tg3_ape_unlock(tp, TG3_APE_LOCK_GPIO);
2522 tw32_wait_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl,
2523 TG3_GRC_LCLCTL_PWRSW_DELAY);
2529 static void tg3_pwrsrc_die_with_vmain(struct tg3 *tp)
2533 if (!tg3_flag(tp, IS_NIC) ||
2534 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
2535 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701)
2538 grc_local_ctrl = tp->grc_local_ctrl | GRC_LCLCTRL_GPIO_OE1;
2540 tw32_wait_f(GRC_LOCAL_CTRL,
2541 grc_local_ctrl | GRC_LCLCTRL_GPIO_OUTPUT1,
2542 TG3_GRC_LCLCTL_PWRSW_DELAY);
2544 tw32_wait_f(GRC_LOCAL_CTRL,
2546 TG3_GRC_LCLCTL_PWRSW_DELAY);
2548 tw32_wait_f(GRC_LOCAL_CTRL,
2549 grc_local_ctrl | GRC_LCLCTRL_GPIO_OUTPUT1,
2550 TG3_GRC_LCLCTL_PWRSW_DELAY);
2553 static void tg3_pwrsrc_switch_to_vaux(struct tg3 *tp)
2555 if (!tg3_flag(tp, IS_NIC))
2558 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
2559 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701) {
2560 tw32_wait_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl |
2561 (GRC_LCLCTRL_GPIO_OE0 |
2562 GRC_LCLCTRL_GPIO_OE1 |
2563 GRC_LCLCTRL_GPIO_OE2 |
2564 GRC_LCLCTRL_GPIO_OUTPUT0 |
2565 GRC_LCLCTRL_GPIO_OUTPUT1),
2566 TG3_GRC_LCLCTL_PWRSW_DELAY);
2567 } else if (tp->pdev->device == PCI_DEVICE_ID_TIGON3_5761 ||
2568 tp->pdev->device == TG3PCI_DEVICE_TIGON3_5761S) {
2569 /* The 5761 non-e device swaps GPIO 0 and GPIO 2. */
2570 u32 grc_local_ctrl = GRC_LCLCTRL_GPIO_OE0 |
2571 GRC_LCLCTRL_GPIO_OE1 |
2572 GRC_LCLCTRL_GPIO_OE2 |
2573 GRC_LCLCTRL_GPIO_OUTPUT0 |
2574 GRC_LCLCTRL_GPIO_OUTPUT1 |
2576 tw32_wait_f(GRC_LOCAL_CTRL, grc_local_ctrl,
2577 TG3_GRC_LCLCTL_PWRSW_DELAY);
2579 grc_local_ctrl |= GRC_LCLCTRL_GPIO_OUTPUT2;
2580 tw32_wait_f(GRC_LOCAL_CTRL, grc_local_ctrl,
2581 TG3_GRC_LCLCTL_PWRSW_DELAY);
2583 grc_local_ctrl &= ~GRC_LCLCTRL_GPIO_OUTPUT0;
2584 tw32_wait_f(GRC_LOCAL_CTRL, grc_local_ctrl,
2585 TG3_GRC_LCLCTL_PWRSW_DELAY);
2588 u32 grc_local_ctrl = 0;
2590 /* Workaround to prevent overdrawing Amps. */
2591 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5714) {
2592 grc_local_ctrl |= GRC_LCLCTRL_GPIO_OE3;
2593 tw32_wait_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl |
2595 TG3_GRC_LCLCTL_PWRSW_DELAY);
2598 /* On 5753 and variants, GPIO2 cannot be used. */
2599 no_gpio2 = tp->nic_sram_data_cfg &
2600 NIC_SRAM_DATA_CFG_NO_GPIO2;
2602 grc_local_ctrl |= GRC_LCLCTRL_GPIO_OE0 |
2603 GRC_LCLCTRL_GPIO_OE1 |
2604 GRC_LCLCTRL_GPIO_OE2 |
2605 GRC_LCLCTRL_GPIO_OUTPUT1 |
2606 GRC_LCLCTRL_GPIO_OUTPUT2;
2608 grc_local_ctrl &= ~(GRC_LCLCTRL_GPIO_OE2 |
2609 GRC_LCLCTRL_GPIO_OUTPUT2);
2611 tw32_wait_f(GRC_LOCAL_CTRL,
2612 tp->grc_local_ctrl | grc_local_ctrl,
2613 TG3_GRC_LCLCTL_PWRSW_DELAY);
2615 grc_local_ctrl |= GRC_LCLCTRL_GPIO_OUTPUT0;
2617 tw32_wait_f(GRC_LOCAL_CTRL,
2618 tp->grc_local_ctrl | grc_local_ctrl,
2619 TG3_GRC_LCLCTL_PWRSW_DELAY);
2622 grc_local_ctrl &= ~GRC_LCLCTRL_GPIO_OUTPUT2;
2623 tw32_wait_f(GRC_LOCAL_CTRL,
2624 tp->grc_local_ctrl | grc_local_ctrl,
2625 TG3_GRC_LCLCTL_PWRSW_DELAY);
2630 static void tg3_frob_aux_power_5717(struct tg3 *tp, bool wol_enable)
2634 /* Serialize power state transitions */
2635 if (tg3_ape_lock(tp, TG3_APE_LOCK_GPIO))
2638 if (tg3_flag(tp, ENABLE_ASF) || tg3_flag(tp, ENABLE_APE) || wol_enable)
2639 msg = TG3_GPIO_MSG_NEED_VAUX;
2641 msg = tg3_set_function_status(tp, msg);
2643 if (msg & TG3_GPIO_MSG_ALL_DRVR_PRES_MASK)
2646 if (msg & TG3_GPIO_MSG_ALL_NEED_VAUX_MASK)
2647 tg3_pwrsrc_switch_to_vaux(tp);
2649 tg3_pwrsrc_die_with_vmain(tp);
2652 tg3_ape_unlock(tp, TG3_APE_LOCK_GPIO);
2655 static void tg3_frob_aux_power(struct tg3 *tp, bool include_wol)
2657 bool need_vaux = false;
2659 /* The GPIOs do something completely different on 57765. */
2660 if (!tg3_flag(tp, IS_NIC) || tg3_flag(tp, 57765_CLASS))
2663 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717 ||
2664 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5719 ||
2665 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5720) {
2666 tg3_frob_aux_power_5717(tp, include_wol ?
2667 tg3_flag(tp, WOL_ENABLE) != 0 : 0);
2671 if (tp->pdev_peer && tp->pdev_peer != tp->pdev) {
2672 struct net_device *dev_peer;
2674 dev_peer = pci_get_drvdata(tp->pdev_peer);
2676 /* remove_one() may have been run on the peer. */
2678 struct tg3 *tp_peer = netdev_priv(dev_peer);
2680 if (tg3_flag(tp_peer, INIT_COMPLETE))
2683 if ((include_wol && tg3_flag(tp_peer, WOL_ENABLE)) ||
2684 tg3_flag(tp_peer, ENABLE_ASF))
2689 if ((include_wol && tg3_flag(tp, WOL_ENABLE)) ||
2690 tg3_flag(tp, ENABLE_ASF))
2694 tg3_pwrsrc_switch_to_vaux(tp);
2696 tg3_pwrsrc_die_with_vmain(tp);
2699 static int tg3_5700_link_polarity(struct tg3 *tp, u32 speed)
2701 if (tp->led_ctrl == LED_CTRL_MODE_PHY_2)
2703 else if ((tp->phy_id & TG3_PHY_ID_MASK) == TG3_PHY_ID_BCM5411) {
2704 if (speed != SPEED_10)
2706 } else if (speed == SPEED_10)
2712 static int tg3_setup_phy(struct tg3 *, int);
2713 static int tg3_halt_cpu(struct tg3 *, u32);
2715 static void tg3_power_down_phy(struct tg3 *tp, bool do_low_power)
2719 if (tp->phy_flags & TG3_PHYFLG_PHY_SERDES) {
2720 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704) {
2721 u32 sg_dig_ctrl = tr32(SG_DIG_CTRL);
2722 u32 serdes_cfg = tr32(MAC_SERDES_CFG);
2725 SG_DIG_USING_HW_AUTONEG | SG_DIG_SOFT_RESET;
2726 tw32(SG_DIG_CTRL, sg_dig_ctrl);
2727 tw32(MAC_SERDES_CFG, serdes_cfg | (1 << 15));
2732 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
2734 val = tr32(GRC_MISC_CFG);
2735 tw32_f(GRC_MISC_CFG, val | GRC_MISC_CFG_EPHY_IDDQ);
2738 } else if (tp->phy_flags & TG3_PHYFLG_IS_FET) {
2740 if (!tg3_readphy(tp, MII_TG3_FET_TEST, &phytest)) {
2743 tg3_writephy(tp, MII_ADVERTISE, 0);
2744 tg3_writephy(tp, MII_BMCR,
2745 BMCR_ANENABLE | BMCR_ANRESTART);
2747 tg3_writephy(tp, MII_TG3_FET_TEST,
2748 phytest | MII_TG3_FET_SHADOW_EN);
2749 if (!tg3_readphy(tp, MII_TG3_FET_SHDW_AUXMODE4, &phy)) {
2750 phy |= MII_TG3_FET_SHDW_AUXMODE4_SBPD;
2752 MII_TG3_FET_SHDW_AUXMODE4,
2755 tg3_writephy(tp, MII_TG3_FET_TEST, phytest);
2758 } else if (do_low_power) {
2759 tg3_writephy(tp, MII_TG3_EXT_CTRL,
2760 MII_TG3_EXT_CTRL_FORCE_LED_OFF);
2762 val = MII_TG3_AUXCTL_PCTL_100TX_LPWR |
2763 MII_TG3_AUXCTL_PCTL_SPR_ISOLATE |
2764 MII_TG3_AUXCTL_PCTL_VREG_11V;
2765 tg3_phy_auxctl_write(tp, MII_TG3_AUXCTL_SHDWSEL_PWRCTL, val);
2768 /* The PHY should not be powered down on some chips because
2771 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
2772 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704 ||
2773 (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5780 &&
2774 (tp->phy_flags & TG3_PHYFLG_MII_SERDES)))
2777 if (GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5784_AX ||
2778 GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5761_AX) {
2779 val = tr32(TG3_CPMU_LSPD_1000MB_CLK);
2780 val &= ~CPMU_LSPD_1000MB_MACCLK_MASK;
2781 val |= CPMU_LSPD_1000MB_MACCLK_12_5;
2782 tw32_f(TG3_CPMU_LSPD_1000MB_CLK, val);
2785 tg3_writephy(tp, MII_BMCR, BMCR_PDOWN);
2788 /* tp->lock is held. */
2789 static int tg3_nvram_lock(struct tg3 *tp)
2791 if (tg3_flag(tp, NVRAM)) {
2794 if (tp->nvram_lock_cnt == 0) {
2795 tw32(NVRAM_SWARB, SWARB_REQ_SET1);
2796 for (i = 0; i < 8000; i++) {
2797 if (tr32(NVRAM_SWARB) & SWARB_GNT1)
2802 tw32(NVRAM_SWARB, SWARB_REQ_CLR1);
2806 tp->nvram_lock_cnt++;
2811 /* tp->lock is held. */
2812 static void tg3_nvram_unlock(struct tg3 *tp)
2814 if (tg3_flag(tp, NVRAM)) {
2815 if (tp->nvram_lock_cnt > 0)
2816 tp->nvram_lock_cnt--;
2817 if (tp->nvram_lock_cnt == 0)
2818 tw32_f(NVRAM_SWARB, SWARB_REQ_CLR1);
2822 /* tp->lock is held. */
2823 static void tg3_enable_nvram_access(struct tg3 *tp)
2825 if (tg3_flag(tp, 5750_PLUS) && !tg3_flag(tp, PROTECTED_NVRAM)) {
2826 u32 nvaccess = tr32(NVRAM_ACCESS);
2828 tw32(NVRAM_ACCESS, nvaccess | ACCESS_ENABLE);
2832 /* tp->lock is held. */
2833 static void tg3_disable_nvram_access(struct tg3 *tp)
2835 if (tg3_flag(tp, 5750_PLUS) && !tg3_flag(tp, PROTECTED_NVRAM)) {
2836 u32 nvaccess = tr32(NVRAM_ACCESS);
2838 tw32(NVRAM_ACCESS, nvaccess & ~ACCESS_ENABLE);
2842 static int tg3_nvram_read_using_eeprom(struct tg3 *tp,
2843 u32 offset, u32 *val)
2848 if (offset > EEPROM_ADDR_ADDR_MASK || (offset % 4) != 0)
2851 tmp = tr32(GRC_EEPROM_ADDR) & ~(EEPROM_ADDR_ADDR_MASK |
2852 EEPROM_ADDR_DEVID_MASK |
2854 tw32(GRC_EEPROM_ADDR,
2856 (0 << EEPROM_ADDR_DEVID_SHIFT) |
2857 ((offset << EEPROM_ADDR_ADDR_SHIFT) &
2858 EEPROM_ADDR_ADDR_MASK) |
2859 EEPROM_ADDR_READ | EEPROM_ADDR_START);
2861 for (i = 0; i < 1000; i++) {
2862 tmp = tr32(GRC_EEPROM_ADDR);
2864 if (tmp & EEPROM_ADDR_COMPLETE)
2868 if (!(tmp & EEPROM_ADDR_COMPLETE))
2871 tmp = tr32(GRC_EEPROM_DATA);
2874 * The data will always be opposite the native endian
2875 * format. Perform a blind byteswap to compensate.
2882 #define NVRAM_CMD_TIMEOUT 10000
2884 static int tg3_nvram_exec_cmd(struct tg3 *tp, u32 nvram_cmd)
2888 tw32(NVRAM_CMD, nvram_cmd);
2889 for (i = 0; i < NVRAM_CMD_TIMEOUT; i++) {
2891 if (tr32(NVRAM_CMD) & NVRAM_CMD_DONE) {
2897 if (i == NVRAM_CMD_TIMEOUT)
2903 static u32 tg3_nvram_phys_addr(struct tg3 *tp, u32 addr)
2905 if (tg3_flag(tp, NVRAM) &&
2906 tg3_flag(tp, NVRAM_BUFFERED) &&
2907 tg3_flag(tp, FLASH) &&
2908 !tg3_flag(tp, NO_NVRAM_ADDR_TRANS) &&
2909 (tp->nvram_jedecnum == JEDEC_ATMEL))
2911 addr = ((addr / tp->nvram_pagesize) <<
2912 ATMEL_AT45DB0X1B_PAGE_POS) +
2913 (addr % tp->nvram_pagesize);
2918 static u32 tg3_nvram_logical_addr(struct tg3 *tp, u32 addr)
2920 if (tg3_flag(tp, NVRAM) &&
2921 tg3_flag(tp, NVRAM_BUFFERED) &&
2922 tg3_flag(tp, FLASH) &&
2923 !tg3_flag(tp, NO_NVRAM_ADDR_TRANS) &&
2924 (tp->nvram_jedecnum == JEDEC_ATMEL))
2926 addr = ((addr >> ATMEL_AT45DB0X1B_PAGE_POS) *
2927 tp->nvram_pagesize) +
2928 (addr & ((1 << ATMEL_AT45DB0X1B_PAGE_POS) - 1));
2933 /* NOTE: Data read in from NVRAM is byteswapped according to
2934 * the byteswapping settings for all other register accesses.
2935 * tg3 devices are BE devices, so on a BE machine, the data
2936 * returned will be exactly as it is seen in NVRAM. On a LE
2937 * machine, the 32-bit value will be byteswapped.
2939 static int tg3_nvram_read(struct tg3 *tp, u32 offset, u32 *val)
2943 if (!tg3_flag(tp, NVRAM))
2944 return tg3_nvram_read_using_eeprom(tp, offset, val);
2946 offset = tg3_nvram_phys_addr(tp, offset);
2948 if (offset > NVRAM_ADDR_MSK)
2951 ret = tg3_nvram_lock(tp);
2955 tg3_enable_nvram_access(tp);
2957 tw32(NVRAM_ADDR, offset);
2958 ret = tg3_nvram_exec_cmd(tp, NVRAM_CMD_RD | NVRAM_CMD_GO |
2959 NVRAM_CMD_FIRST | NVRAM_CMD_LAST | NVRAM_CMD_DONE);
2962 *val = tr32(NVRAM_RDDATA);
2964 tg3_disable_nvram_access(tp);
2966 tg3_nvram_unlock(tp);
2971 /* Ensures NVRAM data is in bytestream format. */
2972 static int tg3_nvram_read_be32(struct tg3 *tp, u32 offset, __be32 *val)
2975 int res = tg3_nvram_read(tp, offset, &v);
2977 *val = cpu_to_be32(v);
2981 #define RX_CPU_SCRATCH_BASE 0x30000
2982 #define RX_CPU_SCRATCH_SIZE 0x04000
2983 #define TX_CPU_SCRATCH_BASE 0x34000
2984 #define TX_CPU_SCRATCH_SIZE 0x04000
2986 /* tp->lock is held. */
2987 static int tg3_halt_cpu(struct tg3 *tp, u32 offset)
2991 BUG_ON(offset == TX_CPU_BASE && tg3_flag(tp, 5705_PLUS));
2993 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
2994 u32 val = tr32(GRC_VCPU_EXT_CTRL);
2996 tw32(GRC_VCPU_EXT_CTRL, val | GRC_VCPU_EXT_CTRL_HALT_CPU);
2999 if (offset == RX_CPU_BASE) {
3000 for (i = 0; i < 10000; i++) {
3001 tw32(offset + CPU_STATE, 0xffffffff);
3002 tw32(offset + CPU_MODE, CPU_MODE_HALT);
3003 if (tr32(offset + CPU_MODE) & CPU_MODE_HALT)
3007 tw32(offset + CPU_STATE, 0xffffffff);
3008 tw32_f(offset + CPU_MODE, CPU_MODE_HALT);
3011 for (i = 0; i < 10000; i++) {
3012 tw32(offset + CPU_STATE, 0xffffffff);
3013 tw32(offset + CPU_MODE, CPU_MODE_HALT);
3014 if (tr32(offset + CPU_MODE) & CPU_MODE_HALT)
3020 netdev_err(tp->dev, "%s timed out, %s CPU\n",
3021 __func__, offset == RX_CPU_BASE ? "RX" : "TX");
3025 /* Clear firmware's nvram arbitration. */
3026 if (tg3_flag(tp, NVRAM))
3027 tw32(NVRAM_SWARB, SWARB_REQ_CLR0);
3032 unsigned int fw_base;
3033 unsigned int fw_len;
3034 const __be32 *fw_data;
3037 /* tp->lock is held. */
3038 static int tg3_load_firmware_cpu(struct tg3 *tp, u32 cpu_base,
3039 u32 cpu_scratch_base, int cpu_scratch_size,
3040 struct fw_info *info)
3042 int err, lock_err, i;
3043 void (*write_op)(struct tg3 *, u32, u32);
3045 if (cpu_base == TX_CPU_BASE && tg3_flag(tp, 5705_PLUS)) {
3047 "%s: Trying to load TX cpu firmware which is 5705\n",
3052 if (tg3_flag(tp, 5705_PLUS))
3053 write_op = tg3_write_mem;
3055 write_op = tg3_write_indirect_reg32;
3057 /* It is possible that bootcode is still loading at this point.
3058 * Get the nvram lock first before halting the cpu.
3060 lock_err = tg3_nvram_lock(tp);
3061 err = tg3_halt_cpu(tp, cpu_base);
3063 tg3_nvram_unlock(tp);
3067 for (i = 0; i < cpu_scratch_size; i += sizeof(u32))
3068 write_op(tp, cpu_scratch_base + i, 0);
3069 tw32(cpu_base + CPU_STATE, 0xffffffff);
3070 tw32(cpu_base + CPU_MODE, tr32(cpu_base+CPU_MODE)|CPU_MODE_HALT);
3071 for (i = 0; i < (info->fw_len / sizeof(u32)); i++)
3072 write_op(tp, (cpu_scratch_base +
3073 (info->fw_base & 0xffff) +
3075 be32_to_cpu(info->fw_data[i]));
3083 /* tp->lock is held. */
3084 static int tg3_load_5701_a0_firmware_fix(struct tg3 *tp)
3086 struct fw_info info;
3087 const __be32 *fw_data;
3090 fw_data = (void *)tp->fw->data;
3092 /* Firmware blob starts with version numbers, followed by
3093 start address and length. We are setting complete length.
3094 length = end_address_of_bss - start_address_of_text.
3095 Remainder is the blob to be loaded contiguously
3096 from start address. */
3098 info.fw_base = be32_to_cpu(fw_data[1]);
3099 info.fw_len = tp->fw->size - 12;
3100 info.fw_data = &fw_data[3];
3102 err = tg3_load_firmware_cpu(tp, RX_CPU_BASE,
3103 RX_CPU_SCRATCH_BASE, RX_CPU_SCRATCH_SIZE,
3108 err = tg3_load_firmware_cpu(tp, TX_CPU_BASE,
3109 TX_CPU_SCRATCH_BASE, TX_CPU_SCRATCH_SIZE,
3114 /* Now startup only the RX cpu. */
3115 tw32(RX_CPU_BASE + CPU_STATE, 0xffffffff);
3116 tw32_f(RX_CPU_BASE + CPU_PC, info.fw_base);
3118 for (i = 0; i < 5; i++) {
3119 if (tr32(RX_CPU_BASE + CPU_PC) == info.fw_base)
3121 tw32(RX_CPU_BASE + CPU_STATE, 0xffffffff);
3122 tw32(RX_CPU_BASE + CPU_MODE, CPU_MODE_HALT);
3123 tw32_f(RX_CPU_BASE + CPU_PC, info.fw_base);
3127 netdev_err(tp->dev, "%s fails to set RX CPU PC, is %08x "
3128 "should be %08x\n", __func__,
3129 tr32(RX_CPU_BASE + CPU_PC), info.fw_base);
3132 tw32(RX_CPU_BASE + CPU_STATE, 0xffffffff);
3133 tw32_f(RX_CPU_BASE + CPU_MODE, 0x00000000);
3138 /* tp->lock is held. */
3139 static int tg3_load_tso_firmware(struct tg3 *tp)
3141 struct fw_info info;
3142 const __be32 *fw_data;
3143 unsigned long cpu_base, cpu_scratch_base, cpu_scratch_size;
3146 if (tg3_flag(tp, HW_TSO_1) ||
3147 tg3_flag(tp, HW_TSO_2) ||
3148 tg3_flag(tp, HW_TSO_3))
3151 fw_data = (void *)tp->fw->data;
3153 /* Firmware blob starts with version numbers, followed by
3154 start address and length. We are setting complete length.
3155 length = end_address_of_bss - start_address_of_text.
3156 Remainder is the blob to be loaded contiguously
3157 from start address. */
3159 info.fw_base = be32_to_cpu(fw_data[1]);
3160 cpu_scratch_size = tp->fw_len;
3161 info.fw_len = tp->fw->size - 12;
3162 info.fw_data = &fw_data[3];
3164 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705) {
3165 cpu_base = RX_CPU_BASE;
3166 cpu_scratch_base = NIC_SRAM_MBUF_POOL_BASE5705;
3168 cpu_base = TX_CPU_BASE;
3169 cpu_scratch_base = TX_CPU_SCRATCH_BASE;
3170 cpu_scratch_size = TX_CPU_SCRATCH_SIZE;
3173 err = tg3_load_firmware_cpu(tp, cpu_base,
3174 cpu_scratch_base, cpu_scratch_size,
3179 /* Now startup the cpu. */
3180 tw32(cpu_base + CPU_STATE, 0xffffffff);
3181 tw32_f(cpu_base + CPU_PC, info.fw_base);
3183 for (i = 0; i < 5; i++) {
3184 if (tr32(cpu_base + CPU_PC) == info.fw_base)
3186 tw32(cpu_base + CPU_STATE, 0xffffffff);
3187 tw32(cpu_base + CPU_MODE, CPU_MODE_HALT);
3188 tw32_f(cpu_base + CPU_PC, info.fw_base);
3193 "%s fails to set CPU PC, is %08x should be %08x\n",
3194 __func__, tr32(cpu_base + CPU_PC), info.fw_base);
3197 tw32(cpu_base + CPU_STATE, 0xffffffff);
3198 tw32_f(cpu_base + CPU_MODE, 0x00000000);
3203 /* tp->lock is held. */
3204 static void __tg3_set_mac_addr(struct tg3 *tp, int skip_mac_1)
3206 u32 addr_high, addr_low;
3209 addr_high = ((tp->dev->dev_addr[0] << 8) |
3210 tp->dev->dev_addr[1]);
3211 addr_low = ((tp->dev->dev_addr[2] << 24) |
3212 (tp->dev->dev_addr[3] << 16) |
3213 (tp->dev->dev_addr[4] << 8) |
3214 (tp->dev->dev_addr[5] << 0));
3215 for (i = 0; i < 4; i++) {
3216 if (i == 1 && skip_mac_1)
3218 tw32(MAC_ADDR_0_HIGH + (i * 8), addr_high);
3219 tw32(MAC_ADDR_0_LOW + (i * 8), addr_low);
3222 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703 ||
3223 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704) {
3224 for (i = 0; i < 12; i++) {
3225 tw32(MAC_EXTADDR_0_HIGH + (i * 8), addr_high);
3226 tw32(MAC_EXTADDR_0_LOW + (i * 8), addr_low);
3230 addr_high = (tp->dev->dev_addr[0] +
3231 tp->dev->dev_addr[1] +
3232 tp->dev->dev_addr[2] +
3233 tp->dev->dev_addr[3] +
3234 tp->dev->dev_addr[4] +
3235 tp->dev->dev_addr[5]) &
3236 TX_BACKOFF_SEED_MASK;
3237 tw32(MAC_TX_BACKOFF_SEED, addr_high);
3240 static void tg3_enable_register_access(struct tg3 *tp)
3243 * Make sure register accesses (indirect or otherwise) will function
3246 pci_write_config_dword(tp->pdev,
3247 TG3PCI_MISC_HOST_CTRL, tp->misc_host_ctrl);
3250 static int tg3_power_up(struct tg3 *tp)
3254 tg3_enable_register_access(tp);
3256 err = pci_set_power_state(tp->pdev, PCI_D0);
3258 /* Switch out of Vaux if it is a NIC */
3259 tg3_pwrsrc_switch_to_vmain(tp);
3261 netdev_err(tp->dev, "Transition to D0 failed\n");
3267 static int tg3_power_down_prepare(struct tg3 *tp)
3270 bool device_should_wake, do_low_power;
3272 tg3_enable_register_access(tp);
3274 /* Restore the CLKREQ setting. */
3275 if (tg3_flag(tp, CLKREQ_BUG)) {
3278 pci_read_config_word(tp->pdev,
3279 pci_pcie_cap(tp->pdev) + PCI_EXP_LNKCTL,
3281 lnkctl |= PCI_EXP_LNKCTL_CLKREQ_EN;
3282 pci_write_config_word(tp->pdev,
3283 pci_pcie_cap(tp->pdev) + PCI_EXP_LNKCTL,
3287 misc_host_ctrl = tr32(TG3PCI_MISC_HOST_CTRL);
3288 tw32(TG3PCI_MISC_HOST_CTRL,
3289 misc_host_ctrl | MISC_HOST_CTRL_MASK_PCI_INT);
3291 device_should_wake = device_may_wakeup(&tp->pdev->dev) &&
3292 tg3_flag(tp, WOL_ENABLE);
3294 if (tg3_flag(tp, USE_PHYLIB)) {
3295 do_low_power = false;
3296 if ((tp->phy_flags & TG3_PHYFLG_IS_CONNECTED) &&
3297 !(tp->phy_flags & TG3_PHYFLG_IS_LOW_POWER)) {
3298 struct phy_device *phydev;
3299 u32 phyid, advertising;
3301 phydev = tp->mdio_bus->phy_map[TG3_PHY_MII_ADDR];
3303 tp->phy_flags |= TG3_PHYFLG_IS_LOW_POWER;
3305 tp->link_config.orig_speed = phydev->speed;
3306 tp->link_config.orig_duplex = phydev->duplex;
3307 tp->link_config.orig_autoneg = phydev->autoneg;
3308 tp->link_config.orig_advertising = phydev->advertising;
3310 advertising = ADVERTISED_TP |
3312 ADVERTISED_Autoneg |
3313 ADVERTISED_10baseT_Half;
3315 if (tg3_flag(tp, ENABLE_ASF) || device_should_wake) {
3316 if (tg3_flag(tp, WOL_SPEED_100MB))
3318 ADVERTISED_100baseT_Half |
3319 ADVERTISED_100baseT_Full |
3320 ADVERTISED_10baseT_Full;
3322 advertising |= ADVERTISED_10baseT_Full;
3325 phydev->advertising = advertising;
3327 phy_start_aneg(phydev);
3329 phyid = phydev->drv->phy_id & phydev->drv->phy_id_mask;
3330 if (phyid != PHY_ID_BCMAC131) {
3331 phyid &= PHY_BCM_OUI_MASK;
3332 if (phyid == PHY_BCM_OUI_1 ||
3333 phyid == PHY_BCM_OUI_2 ||
3334 phyid == PHY_BCM_OUI_3)
3335 do_low_power = true;
3339 do_low_power = true;
3341 if (!(tp->phy_flags & TG3_PHYFLG_IS_LOW_POWER)) {
3342 tp->phy_flags |= TG3_PHYFLG_IS_LOW_POWER;
3343 tp->link_config.orig_speed = tp->link_config.speed;
3344 tp->link_config.orig_duplex = tp->link_config.duplex;
3345 tp->link_config.orig_autoneg = tp->link_config.autoneg;
3348 if (!(tp->phy_flags & TG3_PHYFLG_ANY_SERDES)) {
3349 tp->link_config.speed = SPEED_10;
3350 tp->link_config.duplex = DUPLEX_HALF;
3351 tp->link_config.autoneg = AUTONEG_ENABLE;
3352 tg3_setup_phy(tp, 0);
3356 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
3359 val = tr32(GRC_VCPU_EXT_CTRL);
3360 tw32(GRC_VCPU_EXT_CTRL, val | GRC_VCPU_EXT_CTRL_DISABLE_WOL);
3361 } else if (!tg3_flag(tp, ENABLE_ASF)) {
3365 for (i = 0; i < 200; i++) {
3366 tg3_read_mem(tp, NIC_SRAM_FW_ASF_STATUS_MBOX, &val);
3367 if (val == ~NIC_SRAM_FIRMWARE_MBOX_MAGIC1)
3372 if (tg3_flag(tp, WOL_CAP))
3373 tg3_write_mem(tp, NIC_SRAM_WOL_MBOX, WOL_SIGNATURE |
3374 WOL_DRV_STATE_SHUTDOWN |
3378 if (device_should_wake) {
3381 if (!(tp->phy_flags & TG3_PHYFLG_PHY_SERDES)) {
3383 !(tp->phy_flags & TG3_PHYFLG_IS_FET)) {
3384 tg3_phy_auxctl_write(tp,
3385 MII_TG3_AUXCTL_SHDWSEL_PWRCTL,
3386 MII_TG3_AUXCTL_PCTL_WOL_EN |
3387 MII_TG3_AUXCTL_PCTL_100TX_LPWR |
3388 MII_TG3_AUXCTL_PCTL_CL_AB_TXDAC);
3392 if (tp->phy_flags & TG3_PHYFLG_MII_SERDES)
3393 mac_mode = MAC_MODE_PORT_MODE_GMII;
3395 mac_mode = MAC_MODE_PORT_MODE_MII;
3397 mac_mode |= tp->mac_mode & MAC_MODE_LINK_POLARITY;
3398 if (GET_ASIC_REV(tp->pci_chip_rev_id) ==
3400 u32 speed = tg3_flag(tp, WOL_SPEED_100MB) ?
3401 SPEED_100 : SPEED_10;
3402 if (tg3_5700_link_polarity(tp, speed))
3403 mac_mode |= MAC_MODE_LINK_POLARITY;
3405 mac_mode &= ~MAC_MODE_LINK_POLARITY;
3408 mac_mode = MAC_MODE_PORT_MODE_TBI;
3411 if (!tg3_flag(tp, 5750_PLUS))
3412 tw32(MAC_LED_CTRL, tp->led_ctrl);
3414 mac_mode |= MAC_MODE_MAGIC_PKT_ENABLE;
3415 if ((tg3_flag(tp, 5705_PLUS) && !tg3_flag(tp, 5780_CLASS)) &&
3416 (tg3_flag(tp, ENABLE_ASF) || tg3_flag(tp, ENABLE_APE)))
3417 mac_mode |= MAC_MODE_KEEP_FRAME_IN_WOL;
3419 if (tg3_flag(tp, ENABLE_APE))
3420 mac_mode |= MAC_MODE_APE_TX_EN |
3421 MAC_MODE_APE_RX_EN |
3422 MAC_MODE_TDE_ENABLE;
3424 tw32_f(MAC_MODE, mac_mode);
3427 tw32_f(MAC_RX_MODE, RX_MODE_ENABLE);
3431 if (!tg3_flag(tp, WOL_SPEED_100MB) &&
3432 (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
3433 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701)) {
3436 base_val = tp->pci_clock_ctrl;
3437 base_val |= (CLOCK_CTRL_RXCLK_DISABLE |
3438 CLOCK_CTRL_TXCLK_DISABLE);
3440 tw32_wait_f(TG3PCI_CLOCK_CTRL, base_val | CLOCK_CTRL_ALTCLK |
3441 CLOCK_CTRL_PWRDOWN_PLL133, 40);
3442 } else if (tg3_flag(tp, 5780_CLASS) ||
3443 tg3_flag(tp, CPMU_PRESENT) ||
3444 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
3446 } else if (!(tg3_flag(tp, 5750_PLUS) && tg3_flag(tp, ENABLE_ASF))) {
3447 u32 newbits1, newbits2;
3449 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
3450 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701) {
3451 newbits1 = (CLOCK_CTRL_RXCLK_DISABLE |
3452 CLOCK_CTRL_TXCLK_DISABLE |
3454 newbits2 = newbits1 | CLOCK_CTRL_44MHZ_CORE;
3455 } else if (tg3_flag(tp, 5705_PLUS)) {
3456 newbits1 = CLOCK_CTRL_625_CORE;
3457 newbits2 = newbits1 | CLOCK_CTRL_ALTCLK;
3459 newbits1 = CLOCK_CTRL_ALTCLK;
3460 newbits2 = newbits1 | CLOCK_CTRL_44MHZ_CORE;
3463 tw32_wait_f(TG3PCI_CLOCK_CTRL, tp->pci_clock_ctrl | newbits1,
3466 tw32_wait_f(TG3PCI_CLOCK_CTRL, tp->pci_clock_ctrl | newbits2,
3469 if (!tg3_flag(tp, 5705_PLUS)) {
3472 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
3473 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701) {
3474 newbits3 = (CLOCK_CTRL_RXCLK_DISABLE |
3475 CLOCK_CTRL_TXCLK_DISABLE |
3476 CLOCK_CTRL_44MHZ_CORE);
3478 newbits3 = CLOCK_CTRL_44MHZ_CORE;
3481 tw32_wait_f(TG3PCI_CLOCK_CTRL,
3482 tp->pci_clock_ctrl | newbits3, 40);
3486 if (!(device_should_wake) && !tg3_flag(tp, ENABLE_ASF))
3487 tg3_power_down_phy(tp, do_low_power);
3489 tg3_frob_aux_power(tp, true);
3491 /* Workaround for unstable PLL clock */
3492 if ((GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5750_AX) ||
3493 (GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5750_BX)) {
3494 u32 val = tr32(0x7d00);
3496 val &= ~((1 << 16) | (1 << 4) | (1 << 2) | (1 << 1) | 1);
3498 if (!tg3_flag(tp, ENABLE_ASF)) {
3501 err = tg3_nvram_lock(tp);
3502 tg3_halt_cpu(tp, RX_CPU_BASE);
3504 tg3_nvram_unlock(tp);
3508 tg3_write_sig_post_reset(tp, RESET_KIND_SHUTDOWN);
3513 static void tg3_power_down(struct tg3 *tp)
3515 tg3_power_down_prepare(tp);
3517 pci_wake_from_d3(tp->pdev, tg3_flag(tp, WOL_ENABLE));
3518 pci_set_power_state(tp->pdev, PCI_D3hot);
3521 static void tg3_aux_stat_to_speed_duplex(struct tg3 *tp, u32 val, u16 *speed, u8 *duplex)
3523 switch (val & MII_TG3_AUX_STAT_SPDMASK) {
3524 case MII_TG3_AUX_STAT_10HALF:
3526 *duplex = DUPLEX_HALF;
3529 case MII_TG3_AUX_STAT_10FULL:
3531 *duplex = DUPLEX_FULL;
3534 case MII_TG3_AUX_STAT_100HALF:
3536 *duplex = DUPLEX_HALF;
3539 case MII_TG3_AUX_STAT_100FULL:
3541 *duplex = DUPLEX_FULL;
3544 case MII_TG3_AUX_STAT_1000HALF:
3545 *speed = SPEED_1000;
3546 *duplex = DUPLEX_HALF;
3549 case MII_TG3_AUX_STAT_1000FULL:
3550 *speed = SPEED_1000;
3551 *duplex = DUPLEX_FULL;
3555 if (tp->phy_flags & TG3_PHYFLG_IS_FET) {
3556 *speed = (val & MII_TG3_AUX_STAT_100) ? SPEED_100 :
3558 *duplex = (val & MII_TG3_AUX_STAT_FULL) ? DUPLEX_FULL :
3562 *speed = SPEED_INVALID;
3563 *duplex = DUPLEX_INVALID;
3568 static int tg3_phy_autoneg_cfg(struct tg3 *tp, u32 advertise, u32 flowctrl)
3573 new_adv = ADVERTISE_CSMA;
3574 new_adv |= ethtool_adv_to_mii_adv_t(advertise) & ADVERTISE_ALL;
3575 new_adv |= mii_advertise_flowctrl(flowctrl);
3577 err = tg3_writephy(tp, MII_ADVERTISE, new_adv);
3581 if (!(tp->phy_flags & TG3_PHYFLG_10_100_ONLY)) {
3582 new_adv = ethtool_adv_to_mii_ctrl1000_t(advertise);
3584 if (tp->pci_chip_rev_id == CHIPREV_ID_5701_A0 ||
3585 tp->pci_chip_rev_id == CHIPREV_ID_5701_B0)
3586 new_adv |= CTL1000_AS_MASTER | CTL1000_ENABLE_MASTER;
3588 err = tg3_writephy(tp, MII_CTRL1000, new_adv);
3593 if (!(tp->phy_flags & TG3_PHYFLG_EEE_CAP))
3596 tw32(TG3_CPMU_EEE_MODE,
3597 tr32(TG3_CPMU_EEE_MODE) & ~TG3_CPMU_EEEMD_LPI_ENABLE);
3599 err = TG3_PHY_AUXCTL_SMDSP_ENABLE(tp);
3604 /* Advertise 100-BaseTX EEE ability */
3605 if (advertise & ADVERTISED_100baseT_Full)
3606 val |= MDIO_AN_EEE_ADV_100TX;
3607 /* Advertise 1000-BaseT EEE ability */
3608 if (advertise & ADVERTISED_1000baseT_Full)
3609 val |= MDIO_AN_EEE_ADV_1000T;
3610 err = tg3_phy_cl45_write(tp, MDIO_MMD_AN, MDIO_AN_EEE_ADV, val);
3614 switch (GET_ASIC_REV(tp->pci_chip_rev_id)) {
3616 case ASIC_REV_57765:
3617 case ASIC_REV_57766:
3619 /* If we advertised any eee advertisements above... */
3621 val = MII_TG3_DSP_TAP26_ALNOKO |
3622 MII_TG3_DSP_TAP26_RMRXSTO |
3623 MII_TG3_DSP_TAP26_OPCSINPT;
3624 tg3_phydsp_write(tp, MII_TG3_DSP_TAP26, val);
3627 if (!tg3_phydsp_read(tp, MII_TG3_DSP_CH34TP2, &val))
3628 tg3_phydsp_write(tp, MII_TG3_DSP_CH34TP2, val |
3629 MII_TG3_DSP_CH34TP2_HIBW01);
3632 err2 = TG3_PHY_AUXCTL_SMDSP_DISABLE(tp);
3641 static void tg3_phy_copper_begin(struct tg3 *tp)
3646 if (tp->phy_flags & TG3_PHYFLG_IS_LOW_POWER) {
3647 new_adv = ADVERTISED_10baseT_Half |
3648 ADVERTISED_10baseT_Full;
3649 if (tg3_flag(tp, WOL_SPEED_100MB))
3650 new_adv |= ADVERTISED_100baseT_Half |
3651 ADVERTISED_100baseT_Full;
3653 tg3_phy_autoneg_cfg(tp, new_adv,
3654 FLOW_CTRL_TX | FLOW_CTRL_RX);
3655 } else if (tp->link_config.speed == SPEED_INVALID) {
3656 if (tp->phy_flags & TG3_PHYFLG_10_100_ONLY)
3657 tp->link_config.advertising &=
3658 ~(ADVERTISED_1000baseT_Half |
3659 ADVERTISED_1000baseT_Full);
3661 tg3_phy_autoneg_cfg(tp, tp->link_config.advertising,
3662 tp->link_config.flowctrl);
3664 /* Asking for a specific link mode. */
3665 if (tp->link_config.speed == SPEED_1000) {
3666 if (tp->link_config.duplex == DUPLEX_FULL)
3667 new_adv = ADVERTISED_1000baseT_Full;
3669 new_adv = ADVERTISED_1000baseT_Half;
3670 } else if (tp->link_config.speed == SPEED_100) {
3671 if (tp->link_config.duplex == DUPLEX_FULL)
3672 new_adv = ADVERTISED_100baseT_Full;
3674 new_adv = ADVERTISED_100baseT_Half;
3676 if (tp->link_config.duplex == DUPLEX_FULL)
3677 new_adv = ADVERTISED_10baseT_Full;
3679 new_adv = ADVERTISED_10baseT_Half;
3682 tg3_phy_autoneg_cfg(tp, new_adv,
3683 tp->link_config.flowctrl);
3686 if (tp->link_config.autoneg == AUTONEG_DISABLE &&
3687 tp->link_config.speed != SPEED_INVALID) {
3688 u32 bmcr, orig_bmcr;
3690 tp->link_config.active_speed = tp->link_config.speed;
3691 tp->link_config.active_duplex = tp->link_config.duplex;
3694 switch (tp->link_config.speed) {
3700 bmcr |= BMCR_SPEED100;
3704 bmcr |= BMCR_SPEED1000;
3708 if (tp->link_config.duplex == DUPLEX_FULL)
3709 bmcr |= BMCR_FULLDPLX;
3711 if (!tg3_readphy(tp, MII_BMCR, &orig_bmcr) &&
3712 (bmcr != orig_bmcr)) {
3713 tg3_writephy(tp, MII_BMCR, BMCR_LOOPBACK);
3714 for (i = 0; i < 1500; i++) {
3718 if (tg3_readphy(tp, MII_BMSR, &tmp) ||
3719 tg3_readphy(tp, MII_BMSR, &tmp))
3721 if (!(tmp & BMSR_LSTATUS)) {
3726 tg3_writephy(tp, MII_BMCR, bmcr);
3730 tg3_writephy(tp, MII_BMCR,
3731 BMCR_ANENABLE | BMCR_ANRESTART);
3735 static int tg3_init_5401phy_dsp(struct tg3 *tp)
3739 /* Turn off tap power management. */
3740 /* Set Extended packet length bit */
3741 err = tg3_phy_auxctl_write(tp, MII_TG3_AUXCTL_SHDWSEL_AUXCTL, 0x4c20);
3743 err |= tg3_phydsp_write(tp, 0x0012, 0x1804);
3744 err |= tg3_phydsp_write(tp, 0x0013, 0x1204);
3745 err |= tg3_phydsp_write(tp, 0x8006, 0x0132);
3746 err |= tg3_phydsp_write(tp, 0x8006, 0x0232);
3747 err |= tg3_phydsp_write(tp, 0x201f, 0x0a20);
3754 static bool tg3_phy_copper_an_config_ok(struct tg3 *tp, u32 *lcladv)
3756 u32 advmsk, tgtadv, advertising;
3758 advertising = tp->link_config.advertising;
3759 tgtadv = ethtool_adv_to_mii_adv_t(advertising) & ADVERTISE_ALL;
3761 advmsk = ADVERTISE_ALL;
3762 if (tp->link_config.active_duplex == DUPLEX_FULL) {
3763 tgtadv |= mii_advertise_flowctrl(tp->link_config.flowctrl);
3764 advmsk |= ADVERTISE_PAUSE_CAP | ADVERTISE_PAUSE_ASYM;
3767 if (tg3_readphy(tp, MII_ADVERTISE, lcladv))
3770 if ((*lcladv & advmsk) != tgtadv)
3773 if (!(tp->phy_flags & TG3_PHYFLG_10_100_ONLY)) {
3776 tgtadv = ethtool_adv_to_mii_ctrl1000_t(advertising);
3778 if (tg3_readphy(tp, MII_CTRL1000, &tg3_ctrl))
3781 tg3_ctrl &= (ADVERTISE_1000HALF | ADVERTISE_1000FULL);
3782 if (tg3_ctrl != tgtadv)
3789 static bool tg3_phy_copper_fetch_rmtadv(struct tg3 *tp, u32 *rmtadv)
3793 if (!(tp->phy_flags & TG3_PHYFLG_10_100_ONLY)) {
3796 if (tg3_readphy(tp, MII_STAT1000, &val))
3799 lpeth = mii_stat1000_to_ethtool_lpa_t(val);
3802 if (tg3_readphy(tp, MII_LPA, rmtadv))
3805 lpeth |= mii_lpa_to_ethtool_lpa_t(*rmtadv);
3806 tp->link_config.rmt_adv = lpeth;
3811 static int tg3_setup_copper_phy(struct tg3 *tp, int force_reset)
3813 int current_link_up;
3815 u32 lcl_adv, rmt_adv;
3823 (MAC_STATUS_SYNC_CHANGED |
3824 MAC_STATUS_CFG_CHANGED |
3825 MAC_STATUS_MI_COMPLETION |
3826 MAC_STATUS_LNKSTATE_CHANGED));
3829 if ((tp->mi_mode & MAC_MI_MODE_AUTO_POLL) != 0) {
3831 (tp->mi_mode & ~MAC_MI_MODE_AUTO_POLL));
3835 tg3_phy_auxctl_write(tp, MII_TG3_AUXCTL_SHDWSEL_PWRCTL, 0);
3837 /* Some third-party PHYs need to be reset on link going
3840 if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703 ||
3841 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704 ||
3842 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705) &&
3843 netif_carrier_ok(tp->dev)) {
3844 tg3_readphy(tp, MII_BMSR, &bmsr);
3845 if (!tg3_readphy(tp, MII_BMSR, &bmsr) &&
3846 !(bmsr & BMSR_LSTATUS))
3852 if ((tp->phy_id & TG3_PHY_ID_MASK) == TG3_PHY_ID_BCM5401) {
3853 tg3_readphy(tp, MII_BMSR, &bmsr);
3854 if (tg3_readphy(tp, MII_BMSR, &bmsr) ||
3855 !tg3_flag(tp, INIT_COMPLETE))
3858 if (!(bmsr & BMSR_LSTATUS)) {
3859 err = tg3_init_5401phy_dsp(tp);
3863 tg3_readphy(tp, MII_BMSR, &bmsr);
3864 for (i = 0; i < 1000; i++) {
3866 if (!tg3_readphy(tp, MII_BMSR, &bmsr) &&
3867 (bmsr & BMSR_LSTATUS)) {
3873 if ((tp->phy_id & TG3_PHY_ID_REV_MASK) ==
3874 TG3_PHY_REV_BCM5401_B0 &&
3875 !(bmsr & BMSR_LSTATUS) &&
3876 tp->link_config.active_speed == SPEED_1000) {
3877 err = tg3_phy_reset(tp);
3879 err = tg3_init_5401phy_dsp(tp);
3884 } else if (tp->pci_chip_rev_id == CHIPREV_ID_5701_A0 ||
3885 tp->pci_chip_rev_id == CHIPREV_ID_5701_B0) {
3886 /* 5701 {A0,B0} CRC bug workaround */
3887 tg3_writephy(tp, 0x15, 0x0a75);
3888 tg3_writephy(tp, MII_TG3_MISC_SHDW, 0x8c68);
3889 tg3_writephy(tp, MII_TG3_MISC_SHDW, 0x8d68);
3890 tg3_writephy(tp, MII_TG3_MISC_SHDW, 0x8c68);
3893 /* Clear pending interrupts... */
3894 tg3_readphy(tp, MII_TG3_ISTAT, &val);
3895 tg3_readphy(tp, MII_TG3_ISTAT, &val);
3897 if (tp->phy_flags & TG3_PHYFLG_USE_MI_INTERRUPT)
3898 tg3_writephy(tp, MII_TG3_IMASK, ~MII_TG3_INT_LINKCHG);
3899 else if (!(tp->phy_flags & TG3_PHYFLG_IS_FET))
3900 tg3_writephy(tp, MII_TG3_IMASK, ~0);
3902 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
3903 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701) {
3904 if (tp->led_ctrl == LED_CTRL_MODE_PHY_1)
3905 tg3_writephy(tp, MII_TG3_EXT_CTRL,
3906 MII_TG3_EXT_CTRL_LNK3_LED_MODE);
3908 tg3_writephy(tp, MII_TG3_EXT_CTRL, 0);
3911 current_link_up = 0;
3912 current_speed = SPEED_INVALID;
3913 current_duplex = DUPLEX_INVALID;
3914 tp->phy_flags &= ~TG3_PHYFLG_MDIX_STATE;
3915 tp->link_config.rmt_adv = 0;
3917 if (tp->phy_flags & TG3_PHYFLG_CAPACITIVE_COUPLING) {
3918 err = tg3_phy_auxctl_read(tp,
3919 MII_TG3_AUXCTL_SHDWSEL_MISCTEST,
3921 if (!err && !(val & (1 << 10))) {
3922 tg3_phy_auxctl_write(tp,
3923 MII_TG3_AUXCTL_SHDWSEL_MISCTEST,
3930 for (i = 0; i < 100; i++) {
3931 tg3_readphy(tp, MII_BMSR, &bmsr);
3932 if (!tg3_readphy(tp, MII_BMSR, &bmsr) &&
3933 (bmsr & BMSR_LSTATUS))
3938 if (bmsr & BMSR_LSTATUS) {
3941 tg3_readphy(tp, MII_TG3_AUX_STAT, &aux_stat);
3942 for (i = 0; i < 2000; i++) {
3944 if (!tg3_readphy(tp, MII_TG3_AUX_STAT, &aux_stat) &&
3949 tg3_aux_stat_to_speed_duplex(tp, aux_stat,
3954 for (i = 0; i < 200; i++) {
3955 tg3_readphy(tp, MII_BMCR, &bmcr);
3956 if (tg3_readphy(tp, MII_BMCR, &bmcr))
3958 if (bmcr && bmcr != 0x7fff)
3966 tp->link_config.active_speed = current_speed;
3967 tp->link_config.active_duplex = current_duplex;
3969 if (tp->link_config.autoneg == AUTONEG_ENABLE) {
3970 if ((bmcr & BMCR_ANENABLE) &&
3971 tg3_phy_copper_an_config_ok(tp, &lcl_adv) &&
3972 tg3_phy_copper_fetch_rmtadv(tp, &rmt_adv))
3973 current_link_up = 1;
3975 if (!(bmcr & BMCR_ANENABLE) &&
3976 tp->link_config.speed == current_speed &&
3977 tp->link_config.duplex == current_duplex &&
3978 tp->link_config.flowctrl ==
3979 tp->link_config.active_flowctrl) {
3980 current_link_up = 1;
3984 if (current_link_up == 1 &&
3985 tp->link_config.active_duplex == DUPLEX_FULL) {
3988 if (tp->phy_flags & TG3_PHYFLG_IS_FET) {
3989 reg = MII_TG3_FET_GEN_STAT;
3990 bit = MII_TG3_FET_GEN_STAT_MDIXSTAT;
3992 reg = MII_TG3_EXT_STAT;
3993 bit = MII_TG3_EXT_STAT_MDIX;
3996 if (!tg3_readphy(tp, reg, &val) && (val & bit))
3997 tp->phy_flags |= TG3_PHYFLG_MDIX_STATE;
3999 tg3_setup_flow_control(tp, lcl_adv, rmt_adv);
4004 if (current_link_up == 0 || (tp->phy_flags & TG3_PHYFLG_IS_LOW_POWER)) {
4005 tg3_phy_copper_begin(tp);
4007 tg3_readphy(tp, MII_BMSR, &bmsr);
4008 if ((!tg3_readphy(tp, MII_BMSR, &bmsr) && (bmsr & BMSR_LSTATUS)) ||
4009 (tp->mac_mode & MAC_MODE_PORT_INT_LPBACK))
4010 current_link_up = 1;
4013 tp->mac_mode &= ~MAC_MODE_PORT_MODE_MASK;
4014 if (current_link_up == 1) {
4015 if (tp->link_config.active_speed == SPEED_100 ||
4016 tp->link_config.active_speed == SPEED_10)
4017 tp->mac_mode |= MAC_MODE_PORT_MODE_MII;
4019 tp->mac_mode |= MAC_MODE_PORT_MODE_GMII;
4020 } else if (tp->phy_flags & TG3_PHYFLG_IS_FET)
4021 tp->mac_mode |= MAC_MODE_PORT_MODE_MII;
4023 tp->mac_mode |= MAC_MODE_PORT_MODE_GMII;
4025 tp->mac_mode &= ~MAC_MODE_HALF_DUPLEX;
4026 if (tp->link_config.active_duplex == DUPLEX_HALF)
4027 tp->mac_mode |= MAC_MODE_HALF_DUPLEX;
4029 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700) {
4030 if (current_link_up == 1 &&
4031 tg3_5700_link_polarity(tp, tp->link_config.active_speed))
4032 tp->mac_mode |= MAC_MODE_LINK_POLARITY;
4034 tp->mac_mode &= ~MAC_MODE_LINK_POLARITY;
4037 /* ??? Without this setting Netgear GA302T PHY does not
4038 * ??? send/receive packets...
4040 if ((tp->phy_id & TG3_PHY_ID_MASK) == TG3_PHY_ID_BCM5411 &&
4041 tp->pci_chip_rev_id == CHIPREV_ID_5700_ALTIMA) {
4042 tp->mi_mode |= MAC_MI_MODE_AUTO_POLL;
4043 tw32_f(MAC_MI_MODE, tp->mi_mode);
4047 tw32_f(MAC_MODE, tp->mac_mode);
4050 tg3_phy_eee_adjust(tp, current_link_up);
4052 if (tg3_flag(tp, USE_LINKCHG_REG)) {
4053 /* Polled via timer. */
4054 tw32_f(MAC_EVENT, 0);
4056 tw32_f(MAC_EVENT, MAC_EVENT_LNKSTATE_CHANGED);
4060 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 &&
4061 current_link_up == 1 &&
4062 tp->link_config.active_speed == SPEED_1000 &&
4063 (tg3_flag(tp, PCIX_MODE) || tg3_flag(tp, PCI_HIGH_SPEED))) {
4066 (MAC_STATUS_SYNC_CHANGED |
4067 MAC_STATUS_CFG_CHANGED));
4070 NIC_SRAM_FIRMWARE_MBOX,
4071 NIC_SRAM_FIRMWARE_MBOX_MAGIC2);
4074 /* Prevent send BD corruption. */
4075 if (tg3_flag(tp, CLKREQ_BUG)) {
4076 u16 oldlnkctl, newlnkctl;
4078 pci_read_config_word(tp->pdev,
4079 pci_pcie_cap(tp->pdev) + PCI_EXP_LNKCTL,
4081 if (tp->link_config.active_speed == SPEED_100 ||
4082 tp->link_config.active_speed == SPEED_10)
4083 newlnkctl = oldlnkctl & ~PCI_EXP_LNKCTL_CLKREQ_EN;
4085 newlnkctl = oldlnkctl | PCI_EXP_LNKCTL_CLKREQ_EN;
4086 if (newlnkctl != oldlnkctl)
4087 pci_write_config_word(tp->pdev,
4088 pci_pcie_cap(tp->pdev) +
4089 PCI_EXP_LNKCTL, newlnkctl);
4092 if (current_link_up != netif_carrier_ok(tp->dev)) {
4093 if (current_link_up)
4094 netif_carrier_on(tp->dev);
4096 netif_carrier_off(tp->dev);
4097 tg3_link_report(tp);
4103 struct tg3_fiber_aneginfo {
4105 #define ANEG_STATE_UNKNOWN 0
4106 #define ANEG_STATE_AN_ENABLE 1
4107 #define ANEG_STATE_RESTART_INIT 2
4108 #define ANEG_STATE_RESTART 3
4109 #define ANEG_STATE_DISABLE_LINK_OK 4
4110 #define ANEG_STATE_ABILITY_DETECT_INIT 5
4111 #define ANEG_STATE_ABILITY_DETECT 6
4112 #define ANEG_STATE_ACK_DETECT_INIT 7
4113 #define ANEG_STATE_ACK_DETECT 8
4114 #define ANEG_STATE_COMPLETE_ACK_INIT 9
4115 #define ANEG_STATE_COMPLETE_ACK 10
4116 #define ANEG_STATE_IDLE_DETECT_INIT 11
4117 #define ANEG_STATE_IDLE_DETECT 12
4118 #define ANEG_STATE_LINK_OK 13
4119 #define ANEG_STATE_NEXT_PAGE_WAIT_INIT 14
4120 #define ANEG_STATE_NEXT_PAGE_WAIT 15
4123 #define MR_AN_ENABLE 0x00000001
4124 #define MR_RESTART_AN 0x00000002
4125 #define MR_AN_COMPLETE 0x00000004
4126 #define MR_PAGE_RX 0x00000008
4127 #define MR_NP_LOADED 0x00000010
4128 #define MR_TOGGLE_TX 0x00000020
4129 #define MR_LP_ADV_FULL_DUPLEX 0x00000040
4130 #define MR_LP_ADV_HALF_DUPLEX 0x00000080
4131 #define MR_LP_ADV_SYM_PAUSE 0x00000100
4132 #define MR_LP_ADV_ASYM_PAUSE 0x00000200
4133 #define MR_LP_ADV_REMOTE_FAULT1 0x00000400
4134 #define MR_LP_ADV_REMOTE_FAULT2 0x00000800
4135 #define MR_LP_ADV_NEXT_PAGE 0x00001000
4136 #define MR_TOGGLE_RX 0x00002000
4137 #define MR_NP_RX 0x00004000
4139 #define MR_LINK_OK 0x80000000
4141 unsigned long link_time, cur_time;
4143 u32 ability_match_cfg;
4144 int ability_match_count;
4146 char ability_match, idle_match, ack_match;
4148 u32 txconfig, rxconfig;
4149 #define ANEG_CFG_NP 0x00000080
4150 #define ANEG_CFG_ACK 0x00000040
4151 #define ANEG_CFG_RF2 0x00000020
4152 #define ANEG_CFG_RF1 0x00000010
4153 #define ANEG_CFG_PS2 0x00000001
4154 #define ANEG_CFG_PS1 0x00008000
4155 #define ANEG_CFG_HD 0x00004000
4156 #define ANEG_CFG_FD 0x00002000
4157 #define ANEG_CFG_INVAL 0x00001f06
4162 #define ANEG_TIMER_ENAB 2
4163 #define ANEG_FAILED -1
4165 #define ANEG_STATE_SETTLE_TIME 10000
4167 static int tg3_fiber_aneg_smachine(struct tg3 *tp,
4168 struct tg3_fiber_aneginfo *ap)
4171 unsigned long delta;
4175 if (ap->state == ANEG_STATE_UNKNOWN) {
4179 ap->ability_match_cfg = 0;
4180 ap->ability_match_count = 0;
4181 ap->ability_match = 0;
4187 if (tr32(MAC_STATUS) & MAC_STATUS_RCVD_CFG) {
4188 rx_cfg_reg = tr32(MAC_RX_AUTO_NEG);
4190 if (rx_cfg_reg != ap->ability_match_cfg) {
4191 ap->ability_match_cfg = rx_cfg_reg;
4192 ap->ability_match = 0;
4193 ap->ability_match_count = 0;
4195 if (++ap->ability_match_count > 1) {
4196 ap->ability_match = 1;
4197 ap->ability_match_cfg = rx_cfg_reg;
4200 if (rx_cfg_reg & ANEG_CFG_ACK)
4208 ap->ability_match_cfg = 0;
4209 ap->ability_match_count = 0;
4210 ap->ability_match = 0;
4216 ap->rxconfig = rx_cfg_reg;
4219 switch (ap->state) {
4220 case ANEG_STATE_UNKNOWN:
4221 if (ap->flags & (MR_AN_ENABLE | MR_RESTART_AN))
4222 ap->state = ANEG_STATE_AN_ENABLE;
4225 case ANEG_STATE_AN_ENABLE:
4226 ap->flags &= ~(MR_AN_COMPLETE | MR_PAGE_RX);
4227 if (ap->flags & MR_AN_ENABLE) {
4230 ap->ability_match_cfg = 0;
4231 ap->ability_match_count = 0;
4232 ap->ability_match = 0;
4236 ap->state = ANEG_STATE_RESTART_INIT;
4238 ap->state = ANEG_STATE_DISABLE_LINK_OK;
4242 case ANEG_STATE_RESTART_INIT:
4243 ap->link_time = ap->cur_time;
4244 ap->flags &= ~(MR_NP_LOADED);
4246 tw32(MAC_TX_AUTO_NEG, 0);
4247 tp->mac_mode |= MAC_MODE_SEND_CONFIGS;
4248 tw32_f(MAC_MODE, tp->mac_mode);
4251 ret = ANEG_TIMER_ENAB;
4252 ap->state = ANEG_STATE_RESTART;
4255 case ANEG_STATE_RESTART:
4256 delta = ap->cur_time - ap->link_time;
4257 if (delta > ANEG_STATE_SETTLE_TIME)
4258 ap->state = ANEG_STATE_ABILITY_DETECT_INIT;
4260 ret = ANEG_TIMER_ENAB;
4263 case ANEG_STATE_DISABLE_LINK_OK:
4267 case ANEG_STATE_ABILITY_DETECT_INIT:
4268 ap->flags &= ~(MR_TOGGLE_TX);
4269 ap->txconfig = ANEG_CFG_FD;
4270 flowctrl = tg3_advert_flowctrl_1000X(tp->link_config.flowctrl);
4271 if (flowctrl & ADVERTISE_1000XPAUSE)
4272 ap->txconfig |= ANEG_CFG_PS1;
4273 if (flowctrl & ADVERTISE_1000XPSE_ASYM)
4274 ap->txconfig |= ANEG_CFG_PS2;
4275 tw32(MAC_TX_AUTO_NEG, ap->txconfig);
4276 tp->mac_mode |= MAC_MODE_SEND_CONFIGS;
4277 tw32_f(MAC_MODE, tp->mac_mode);
4280 ap->state = ANEG_STATE_ABILITY_DETECT;
4283 case ANEG_STATE_ABILITY_DETECT:
4284 if (ap->ability_match != 0 && ap->rxconfig != 0)
4285 ap->state = ANEG_STATE_ACK_DETECT_INIT;
4288 case ANEG_STATE_ACK_DETECT_INIT:
4289 ap->txconfig |= ANEG_CFG_ACK;
4290 tw32(MAC_TX_AUTO_NEG, ap->txconfig);
4291 tp->mac_mode |= MAC_MODE_SEND_CONFIGS;
4292 tw32_f(MAC_MODE, tp->mac_mode);
4295 ap->state = ANEG_STATE_ACK_DETECT;
4298 case ANEG_STATE_ACK_DETECT:
4299 if (ap->ack_match != 0) {
4300 if ((ap->rxconfig & ~ANEG_CFG_ACK) ==
4301 (ap->ability_match_cfg & ~ANEG_CFG_ACK)) {
4302 ap->state = ANEG_STATE_COMPLETE_ACK_INIT;
4304 ap->state = ANEG_STATE_AN_ENABLE;
4306 } else if (ap->ability_match != 0 &&
4307 ap->rxconfig == 0) {
4308 ap->state = ANEG_STATE_AN_ENABLE;
4312 case ANEG_STATE_COMPLETE_ACK_INIT:
4313 if (ap->rxconfig & ANEG_CFG_INVAL) {
4317 ap->flags &= ~(MR_LP_ADV_FULL_DUPLEX |
4318 MR_LP_ADV_HALF_DUPLEX |
4319 MR_LP_ADV_SYM_PAUSE |
4320 MR_LP_ADV_ASYM_PAUSE |
4321 MR_LP_ADV_REMOTE_FAULT1 |
4322 MR_LP_ADV_REMOTE_FAULT2 |
4323 MR_LP_ADV_NEXT_PAGE |
4326 if (ap->rxconfig & ANEG_CFG_FD)
4327 ap->flags |= MR_LP_ADV_FULL_DUPLEX;
4328 if (ap->rxconfig & ANEG_CFG_HD)
4329 ap->flags |= MR_LP_ADV_HALF_DUPLEX;
4330 if (ap->rxconfig & ANEG_CFG_PS1)
4331 ap->flags |= MR_LP_ADV_SYM_PAUSE;
4332 if (ap->rxconfig & ANEG_CFG_PS2)
4333 ap->flags |= MR_LP_ADV_ASYM_PAUSE;
4334 if (ap->rxconfig & ANEG_CFG_RF1)
4335 ap->flags |= MR_LP_ADV_REMOTE_FAULT1;
4336 if (ap->rxconfig & ANEG_CFG_RF2)
4337 ap->flags |= MR_LP_ADV_REMOTE_FAULT2;
4338 if (ap->rxconfig & ANEG_CFG_NP)
4339 ap->flags |= MR_LP_ADV_NEXT_PAGE;
4341 ap->link_time = ap->cur_time;
4343 ap->flags ^= (MR_TOGGLE_TX);
4344 if (ap->rxconfig & 0x0008)
4345 ap->flags |= MR_TOGGLE_RX;
4346 if (ap->rxconfig & ANEG_CFG_NP)
4347 ap->flags |= MR_NP_RX;
4348 ap->flags |= MR_PAGE_RX;
4350 ap->state = ANEG_STATE_COMPLETE_ACK;
4351 ret = ANEG_TIMER_ENAB;
4354 case ANEG_STATE_COMPLETE_ACK:
4355 if (ap->ability_match != 0 &&
4356 ap->rxconfig == 0) {
4357 ap->state = ANEG_STATE_AN_ENABLE;
4360 delta = ap->cur_time - ap->link_time;
4361 if (delta > ANEG_STATE_SETTLE_TIME) {
4362 if (!(ap->flags & (MR_LP_ADV_NEXT_PAGE))) {
4363 ap->state = ANEG_STATE_IDLE_DETECT_INIT;
4365 if ((ap->txconfig & ANEG_CFG_NP) == 0 &&
4366 !(ap->flags & MR_NP_RX)) {
4367 ap->state = ANEG_STATE_IDLE_DETECT_INIT;
4375 case ANEG_STATE_IDLE_DETECT_INIT:
4376 ap->link_time = ap->cur_time;
4377 tp->mac_mode &= ~MAC_MODE_SEND_CONFIGS;
4378 tw32_f(MAC_MODE, tp->mac_mode);
4381 ap->state = ANEG_STATE_IDLE_DETECT;
4382 ret = ANEG_TIMER_ENAB;
4385 case ANEG_STATE_IDLE_DETECT:
4386 if (ap->ability_match != 0 &&
4387 ap->rxconfig == 0) {
4388 ap->state = ANEG_STATE_AN_ENABLE;
4391 delta = ap->cur_time - ap->link_time;
4392 if (delta > ANEG_STATE_SETTLE_TIME) {
4393 /* XXX another gem from the Broadcom driver :( */
4394 ap->state = ANEG_STATE_LINK_OK;
4398 case ANEG_STATE_LINK_OK:
4399 ap->flags |= (MR_AN_COMPLETE | MR_LINK_OK);
4403 case ANEG_STATE_NEXT_PAGE_WAIT_INIT:
4404 /* ??? unimplemented */
4407 case ANEG_STATE_NEXT_PAGE_WAIT:
4408 /* ??? unimplemented */
4419 static int fiber_autoneg(struct tg3 *tp, u32 *txflags, u32 *rxflags)
4422 struct tg3_fiber_aneginfo aninfo;
4423 int status = ANEG_FAILED;
4427 tw32_f(MAC_TX_AUTO_NEG, 0);
4429 tmp = tp->mac_mode & ~MAC_MODE_PORT_MODE_MASK;
4430 tw32_f(MAC_MODE, tmp | MAC_MODE_PORT_MODE_GMII);
4433 tw32_f(MAC_MODE, tp->mac_mode | MAC_MODE_SEND_CONFIGS);
4436 memset(&aninfo, 0, sizeof(aninfo));
4437 aninfo.flags |= MR_AN_ENABLE;
4438 aninfo.state = ANEG_STATE_UNKNOWN;
4439 aninfo.cur_time = 0;
4441 while (++tick < 195000) {
4442 status = tg3_fiber_aneg_smachine(tp, &aninfo);
4443 if (status == ANEG_DONE || status == ANEG_FAILED)
4449 tp->mac_mode &= ~MAC_MODE_SEND_CONFIGS;
4450 tw32_f(MAC_MODE, tp->mac_mode);
4453 *txflags = aninfo.txconfig;
4454 *rxflags = aninfo.flags;
4456 if (status == ANEG_DONE &&
4457 (aninfo.flags & (MR_AN_COMPLETE | MR_LINK_OK |
4458 MR_LP_ADV_FULL_DUPLEX)))
4464 static void tg3_init_bcm8002(struct tg3 *tp)
4466 u32 mac_status = tr32(MAC_STATUS);
4469 /* Reset when initting first time or we have a link. */
4470 if (tg3_flag(tp, INIT_COMPLETE) &&
4471 !(mac_status & MAC_STATUS_PCS_SYNCED))
4474 /* Set PLL lock range. */
4475 tg3_writephy(tp, 0x16, 0x8007);
4478 tg3_writephy(tp, MII_BMCR, BMCR_RESET);
4480 /* Wait for reset to complete. */
4481 /* XXX schedule_timeout() ... */
4482 for (i = 0; i < 500; i++)
4485 /* Config mode; select PMA/Ch 1 regs. */
4486 tg3_writephy(tp, 0x10, 0x8411);
4488 /* Enable auto-lock and comdet, select txclk for tx. */
4489 tg3_writephy(tp, 0x11, 0x0a10);
4491 tg3_writephy(tp, 0x18, 0x00a0);
4492 tg3_writephy(tp, 0x16, 0x41ff);
4494 /* Assert and deassert POR. */
4495 tg3_writephy(tp, 0x13, 0x0400);
4497 tg3_writephy(tp, 0x13, 0x0000);
4499 tg3_writephy(tp, 0x11, 0x0a50);
4501 tg3_writephy(tp, 0x11, 0x0a10);
4503 /* Wait for signal to stabilize */
4504 /* XXX schedule_timeout() ... */
4505 for (i = 0; i < 15000; i++)
4508 /* Deselect the channel register so we can read the PHYID
4511 tg3_writephy(tp, 0x10, 0x8011);
4514 static int tg3_setup_fiber_hw_autoneg(struct tg3 *tp, u32 mac_status)
4517 u32 sg_dig_ctrl, sg_dig_status;
4518 u32 serdes_cfg, expected_sg_dig_ctrl;
4519 int workaround, port_a;
4520 int current_link_up;
4523 expected_sg_dig_ctrl = 0;
4526 current_link_up = 0;
4528 if (tp->pci_chip_rev_id != CHIPREV_ID_5704_A0 &&
4529 tp->pci_chip_rev_id != CHIPREV_ID_5704_A1) {
4531 if (tr32(TG3PCI_DUAL_MAC_CTRL) & DUAL_MAC_CTRL_ID)
4534 /* preserve bits 0-11,13,14 for signal pre-emphasis */
4535 /* preserve bits 20-23 for voltage regulator */
4536 serdes_cfg = tr32(MAC_SERDES_CFG) & 0x00f06fff;
4539 sg_dig_ctrl = tr32(SG_DIG_CTRL);
4541 if (tp->link_config.autoneg != AUTONEG_ENABLE) {
4542 if (sg_dig_ctrl & SG_DIG_USING_HW_AUTONEG) {
4544 u32 val = serdes_cfg;
4550 tw32_f(MAC_SERDES_CFG, val);
4553 tw32_f(SG_DIG_CTRL, SG_DIG_COMMON_SETUP);
4555 if (mac_status & MAC_STATUS_PCS_SYNCED) {
4556 tg3_setup_flow_control(tp, 0, 0);
4557 current_link_up = 1;
4562 /* Want auto-negotiation. */
4563 expected_sg_dig_ctrl = SG_DIG_USING_HW_AUTONEG | SG_DIG_COMMON_SETUP;
4565 flowctrl = tg3_advert_flowctrl_1000X(tp->link_config.flowctrl);
4566 if (flowctrl & ADVERTISE_1000XPAUSE)
4567 expected_sg_dig_ctrl |= SG_DIG_PAUSE_CAP;
4568 if (flowctrl & ADVERTISE_1000XPSE_ASYM)
4569 expected_sg_dig_ctrl |= SG_DIG_ASYM_PAUSE;
4571 if (sg_dig_ctrl != expected_sg_dig_ctrl) {
4572 if ((tp->phy_flags & TG3_PHYFLG_PARALLEL_DETECT) &&
4573 tp->serdes_counter &&
4574 ((mac_status & (MAC_STATUS_PCS_SYNCED |
4575 MAC_STATUS_RCVD_CFG)) ==
4576 MAC_STATUS_PCS_SYNCED)) {
4577 tp->serdes_counter--;
4578 current_link_up = 1;
4583 tw32_f(MAC_SERDES_CFG, serdes_cfg | 0xc011000);
4584 tw32_f(SG_DIG_CTRL, expected_sg_dig_ctrl | SG_DIG_SOFT_RESET);
4586 tw32_f(SG_DIG_CTRL, expected_sg_dig_ctrl);
4588 tp->serdes_counter = SERDES_AN_TIMEOUT_5704S;
4589 tp->phy_flags &= ~TG3_PHYFLG_PARALLEL_DETECT;
4590 } else if (mac_status & (MAC_STATUS_PCS_SYNCED |
4591 MAC_STATUS_SIGNAL_DET)) {
4592 sg_dig_status = tr32(SG_DIG_STATUS);
4593 mac_status = tr32(MAC_STATUS);
4595 if ((sg_dig_status & SG_DIG_AUTONEG_COMPLETE) &&
4596 (mac_status & MAC_STATUS_PCS_SYNCED)) {
4597 u32 local_adv = 0, remote_adv = 0;
4599 if (sg_dig_ctrl & SG_DIG_PAUSE_CAP)
4600 local_adv |= ADVERTISE_1000XPAUSE;
4601 if (sg_dig_ctrl & SG_DIG_ASYM_PAUSE)
4602 local_adv |= ADVERTISE_1000XPSE_ASYM;
4604 if (sg_dig_status & SG_DIG_PARTNER_PAUSE_CAPABLE)
4605 remote_adv |= LPA_1000XPAUSE;
4606 if (sg_dig_status & SG_DIG_PARTNER_ASYM_PAUSE)
4607 remote_adv |= LPA_1000XPAUSE_ASYM;
4609 tp->link_config.rmt_adv =
4610 mii_adv_to_ethtool_adv_x(remote_adv);
4612 tg3_setup_flow_control(tp, local_adv, remote_adv);
4613 current_link_up = 1;
4614 tp->serdes_counter = 0;
4615 tp->phy_flags &= ~TG3_PHYFLG_PARALLEL_DETECT;
4616 } else if (!(sg_dig_status & SG_DIG_AUTONEG_COMPLETE)) {
4617 if (tp->serdes_counter)
4618 tp->serdes_counter--;
4621 u32 val = serdes_cfg;
4628 tw32_f(MAC_SERDES_CFG, val);
4631 tw32_f(SG_DIG_CTRL, SG_DIG_COMMON_SETUP);
4634 /* Link parallel detection - link is up */
4635 /* only if we have PCS_SYNC and not */
4636 /* receiving config code words */
4637 mac_status = tr32(MAC_STATUS);
4638 if ((mac_status & MAC_STATUS_PCS_SYNCED) &&
4639 !(mac_status & MAC_STATUS_RCVD_CFG)) {
4640 tg3_setup_flow_control(tp, 0, 0);
4641 current_link_up = 1;
4643 TG3_PHYFLG_PARALLEL_DETECT;
4644 tp->serdes_counter =
4645 SERDES_PARALLEL_DET_TIMEOUT;
4647 goto restart_autoneg;
4651 tp->serdes_counter = SERDES_AN_TIMEOUT_5704S;
4652 tp->phy_flags &= ~TG3_PHYFLG_PARALLEL_DETECT;
4656 return current_link_up;
4659 static int tg3_setup_fiber_by_hand(struct tg3 *tp, u32 mac_status)
4661 int current_link_up = 0;
4663 if (!(mac_status & MAC_STATUS_PCS_SYNCED))
4666 if (tp->link_config.autoneg == AUTONEG_ENABLE) {
4667 u32 txflags, rxflags;
4670 if (fiber_autoneg(tp, &txflags, &rxflags)) {
4671 u32 local_adv = 0, remote_adv = 0;
4673 if (txflags & ANEG_CFG_PS1)
4674 local_adv |= ADVERTISE_1000XPAUSE;
4675 if (txflags & ANEG_CFG_PS2)
4676 local_adv |= ADVERTISE_1000XPSE_ASYM;
4678 if (rxflags & MR_LP_ADV_SYM_PAUSE)
4679 remote_adv |= LPA_1000XPAUSE;
4680 if (rxflags & MR_LP_ADV_ASYM_PAUSE)
4681 remote_adv |= LPA_1000XPAUSE_ASYM;
4683 tp->link_config.rmt_adv =
4684 mii_adv_to_ethtool_adv_x(remote_adv);
4686 tg3_setup_flow_control(tp, local_adv, remote_adv);
4688 current_link_up = 1;
4690 for (i = 0; i < 30; i++) {
4693 (MAC_STATUS_SYNC_CHANGED |
4694 MAC_STATUS_CFG_CHANGED));
4696 if ((tr32(MAC_STATUS) &
4697 (MAC_STATUS_SYNC_CHANGED |
4698 MAC_STATUS_CFG_CHANGED)) == 0)
4702 mac_status = tr32(MAC_STATUS);
4703 if (current_link_up == 0 &&
4704 (mac_status & MAC_STATUS_PCS_SYNCED) &&
4705 !(mac_status & MAC_STATUS_RCVD_CFG))
4706 current_link_up = 1;
4708 tg3_setup_flow_control(tp, 0, 0);
4710 /* Forcing 1000FD link up. */
4711 current_link_up = 1;
4713 tw32_f(MAC_MODE, (tp->mac_mode | MAC_MODE_SEND_CONFIGS));
4716 tw32_f(MAC_MODE, tp->mac_mode);
4721 return current_link_up;
4724 static int tg3_setup_fiber_phy(struct tg3 *tp, int force_reset)
4727 u16 orig_active_speed;
4728 u8 orig_active_duplex;
4730 int current_link_up;
4733 orig_pause_cfg = tp->link_config.active_flowctrl;
4734 orig_active_speed = tp->link_config.active_speed;
4735 orig_active_duplex = tp->link_config.active_duplex;
4737 if (!tg3_flag(tp, HW_AUTONEG) &&
4738 netif_carrier_ok(tp->dev) &&
4739 tg3_flag(tp, INIT_COMPLETE)) {
4740 mac_status = tr32(MAC_STATUS);
4741 mac_status &= (MAC_STATUS_PCS_SYNCED |
4742 MAC_STATUS_SIGNAL_DET |
4743 MAC_STATUS_CFG_CHANGED |
4744 MAC_STATUS_RCVD_CFG);
4745 if (mac_status == (MAC_STATUS_PCS_SYNCED |
4746 MAC_STATUS_SIGNAL_DET)) {
4747 tw32_f(MAC_STATUS, (MAC_STATUS_SYNC_CHANGED |
4748 MAC_STATUS_CFG_CHANGED));
4753 tw32_f(MAC_TX_AUTO_NEG, 0);
4755 tp->mac_mode &= ~(MAC_MODE_PORT_MODE_MASK | MAC_MODE_HALF_DUPLEX);
4756 tp->mac_mode |= MAC_MODE_PORT_MODE_TBI;
4757 tw32_f(MAC_MODE, tp->mac_mode);
4760 if (tp->phy_id == TG3_PHY_ID_BCM8002)
4761 tg3_init_bcm8002(tp);
4763 /* Enable link change event even when serdes polling. */
4764 tw32_f(MAC_EVENT, MAC_EVENT_LNKSTATE_CHANGED);
4767 current_link_up = 0;
4768 tp->link_config.rmt_adv = 0;
4769 mac_status = tr32(MAC_STATUS);
4771 if (tg3_flag(tp, HW_AUTONEG))
4772 current_link_up = tg3_setup_fiber_hw_autoneg(tp, mac_status);
4774 current_link_up = tg3_setup_fiber_by_hand(tp, mac_status);
4776 tp->napi[0].hw_status->status =
4777 (SD_STATUS_UPDATED |
4778 (tp->napi[0].hw_status->status & ~SD_STATUS_LINK_CHG));
4780 for (i = 0; i < 100; i++) {
4781 tw32_f(MAC_STATUS, (MAC_STATUS_SYNC_CHANGED |
4782 MAC_STATUS_CFG_CHANGED));
4784 if ((tr32(MAC_STATUS) & (MAC_STATUS_SYNC_CHANGED |
4785 MAC_STATUS_CFG_CHANGED |
4786 MAC_STATUS_LNKSTATE_CHANGED)) == 0)
4790 mac_status = tr32(MAC_STATUS);
4791 if ((mac_status & MAC_STATUS_PCS_SYNCED) == 0) {
4792 current_link_up = 0;
4793 if (tp->link_config.autoneg == AUTONEG_ENABLE &&
4794 tp->serdes_counter == 0) {
4795 tw32_f(MAC_MODE, (tp->mac_mode |
4796 MAC_MODE_SEND_CONFIGS));
4798 tw32_f(MAC_MODE, tp->mac_mode);
4802 if (current_link_up == 1) {
4803 tp->link_config.active_speed = SPEED_1000;
4804 tp->link_config.active_duplex = DUPLEX_FULL;
4805 tw32(MAC_LED_CTRL, (tp->led_ctrl |
4806 LED_CTRL_LNKLED_OVERRIDE |
4807 LED_CTRL_1000MBPS_ON));
4809 tp->link_config.active_speed = SPEED_INVALID;
4810 tp->link_config.active_duplex = DUPLEX_INVALID;
4811 tw32(MAC_LED_CTRL, (tp->led_ctrl |
4812 LED_CTRL_LNKLED_OVERRIDE |
4813 LED_CTRL_TRAFFIC_OVERRIDE));
4816 if (current_link_up != netif_carrier_ok(tp->dev)) {
4817 if (current_link_up)
4818 netif_carrier_on(tp->dev);
4820 netif_carrier_off(tp->dev);
4821 tg3_link_report(tp);
4823 u32 now_pause_cfg = tp->link_config.active_flowctrl;
4824 if (orig_pause_cfg != now_pause_cfg ||
4825 orig_active_speed != tp->link_config.active_speed ||
4826 orig_active_duplex != tp->link_config.active_duplex)
4827 tg3_link_report(tp);
4833 static int tg3_setup_fiber_mii_phy(struct tg3 *tp, int force_reset)
4835 int current_link_up, err = 0;
4839 u32 local_adv, remote_adv;
4841 tp->mac_mode |= MAC_MODE_PORT_MODE_GMII;
4842 tw32_f(MAC_MODE, tp->mac_mode);
4848 (MAC_STATUS_SYNC_CHANGED |
4849 MAC_STATUS_CFG_CHANGED |
4850 MAC_STATUS_MI_COMPLETION |
4851 MAC_STATUS_LNKSTATE_CHANGED));
4857 current_link_up = 0;
4858 current_speed = SPEED_INVALID;
4859 current_duplex = DUPLEX_INVALID;
4860 tp->link_config.rmt_adv = 0;
4862 err |= tg3_readphy(tp, MII_BMSR, &bmsr);
4863 err |= tg3_readphy(tp, MII_BMSR, &bmsr);
4864 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5714) {
4865 if (tr32(MAC_TX_STATUS) & TX_STATUS_LINK_UP)
4866 bmsr |= BMSR_LSTATUS;
4868 bmsr &= ~BMSR_LSTATUS;
4871 err |= tg3_readphy(tp, MII_BMCR, &bmcr);
4873 if ((tp->link_config.autoneg == AUTONEG_ENABLE) && !force_reset &&
4874 (tp->phy_flags & TG3_PHYFLG_PARALLEL_DETECT)) {
4875 /* do nothing, just check for link up at the end */
4876 } else if (tp->link_config.autoneg == AUTONEG_ENABLE) {
4879 err |= tg3_readphy(tp, MII_ADVERTISE, &adv);
4880 newadv = adv & ~(ADVERTISE_1000XFULL | ADVERTISE_1000XHALF |
4881 ADVERTISE_1000XPAUSE |
4882 ADVERTISE_1000XPSE_ASYM |
4885 newadv |= tg3_advert_flowctrl_1000X(tp->link_config.flowctrl);
4886 newadv |= ethtool_adv_to_mii_adv_x(tp->link_config.advertising);
4888 if ((newadv != adv) || !(bmcr & BMCR_ANENABLE)) {
4889 tg3_writephy(tp, MII_ADVERTISE, newadv);
4890 bmcr |= BMCR_ANENABLE | BMCR_ANRESTART;
4891 tg3_writephy(tp, MII_BMCR, bmcr);
4893 tw32_f(MAC_EVENT, MAC_EVENT_LNKSTATE_CHANGED);
4894 tp->serdes_counter = SERDES_AN_TIMEOUT_5714S;
4895 tp->phy_flags &= ~TG3_PHYFLG_PARALLEL_DETECT;
4902 bmcr &= ~BMCR_SPEED1000;
4903 new_bmcr = bmcr & ~(BMCR_ANENABLE | BMCR_FULLDPLX);
4905 if (tp->link_config.duplex == DUPLEX_FULL)
4906 new_bmcr |= BMCR_FULLDPLX;
4908 if (new_bmcr != bmcr) {
4909 /* BMCR_SPEED1000 is a reserved bit that needs
4910 * to be set on write.
4912 new_bmcr |= BMCR_SPEED1000;
4914 /* Force a linkdown */
4915 if (netif_carrier_ok(tp->dev)) {
4918 err |= tg3_readphy(tp, MII_ADVERTISE, &adv);
4919 adv &= ~(ADVERTISE_1000XFULL |
4920 ADVERTISE_1000XHALF |
4922 tg3_writephy(tp, MII_ADVERTISE, adv);
4923 tg3_writephy(tp, MII_BMCR, bmcr |
4927 netif_carrier_off(tp->dev);
4929 tg3_writephy(tp, MII_BMCR, new_bmcr);
4931 err |= tg3_readphy(tp, MII_BMSR, &bmsr);
4932 err |= tg3_readphy(tp, MII_BMSR, &bmsr);
4933 if (GET_ASIC_REV(tp->pci_chip_rev_id) ==
4935 if (tr32(MAC_TX_STATUS) & TX_STATUS_LINK_UP)
4936 bmsr |= BMSR_LSTATUS;
4938 bmsr &= ~BMSR_LSTATUS;
4940 tp->phy_flags &= ~TG3_PHYFLG_PARALLEL_DETECT;
4944 if (bmsr & BMSR_LSTATUS) {
4945 current_speed = SPEED_1000;
4946 current_link_up = 1;
4947 if (bmcr & BMCR_FULLDPLX)
4948 current_duplex = DUPLEX_FULL;
4950 current_duplex = DUPLEX_HALF;
4955 if (bmcr & BMCR_ANENABLE) {
4958 err |= tg3_readphy(tp, MII_ADVERTISE, &local_adv);
4959 err |= tg3_readphy(tp, MII_LPA, &remote_adv);
4960 common = local_adv & remote_adv;
4961 if (common & (ADVERTISE_1000XHALF |
4962 ADVERTISE_1000XFULL)) {
4963 if (common & ADVERTISE_1000XFULL)
4964 current_duplex = DUPLEX_FULL;
4966 current_duplex = DUPLEX_HALF;
4968 tp->link_config.rmt_adv =
4969 mii_adv_to_ethtool_adv_x(remote_adv);
4970 } else if (!tg3_flag(tp, 5780_CLASS)) {
4971 /* Link is up via parallel detect */
4973 current_link_up = 0;
4978 if (current_link_up == 1 && current_duplex == DUPLEX_FULL)
4979 tg3_setup_flow_control(tp, local_adv, remote_adv);
4981 tp->mac_mode &= ~MAC_MODE_HALF_DUPLEX;
4982 if (tp->link_config.active_duplex == DUPLEX_HALF)
4983 tp->mac_mode |= MAC_MODE_HALF_DUPLEX;
4985 tw32_f(MAC_MODE, tp->mac_mode);
4988 tw32_f(MAC_EVENT, MAC_EVENT_LNKSTATE_CHANGED);
4990 tp->link_config.active_speed = current_speed;
4991 tp->link_config.active_duplex = current_duplex;
4993 if (current_link_up != netif_carrier_ok(tp->dev)) {
4994 if (current_link_up)
4995 netif_carrier_on(tp->dev);
4997 netif_carrier_off(tp->dev);
4998 tp->phy_flags &= ~TG3_PHYFLG_PARALLEL_DETECT;
5000 tg3_link_report(tp);
5005 static void tg3_serdes_parallel_detect(struct tg3 *tp)
5007 if (tp->serdes_counter) {
5008 /* Give autoneg time to complete. */
5009 tp->serdes_counter--;
5013 if (!netif_carrier_ok(tp->dev) &&
5014 (tp->link_config.autoneg == AUTONEG_ENABLE)) {
5017 tg3_readphy(tp, MII_BMCR, &bmcr);
5018 if (bmcr & BMCR_ANENABLE) {
5021 /* Select shadow register 0x1f */
5022 tg3_writephy(tp, MII_TG3_MISC_SHDW, 0x7c00);
5023 tg3_readphy(tp, MII_TG3_MISC_SHDW, &phy1);
5025 /* Select expansion interrupt status register */
5026 tg3_writephy(tp, MII_TG3_DSP_ADDRESS,
5027 MII_TG3_DSP_EXP1_INT_STAT);
5028 tg3_readphy(tp, MII_TG3_DSP_RW_PORT, &phy2);
5029 tg3_readphy(tp, MII_TG3_DSP_RW_PORT, &phy2);
5031 if ((phy1 & 0x10) && !(phy2 & 0x20)) {
5032 /* We have signal detect and not receiving
5033 * config code words, link is up by parallel
5037 bmcr &= ~BMCR_ANENABLE;
5038 bmcr |= BMCR_SPEED1000 | BMCR_FULLDPLX;
5039 tg3_writephy(tp, MII_BMCR, bmcr);
5040 tp->phy_flags |= TG3_PHYFLG_PARALLEL_DETECT;
5043 } else if (netif_carrier_ok(tp->dev) &&
5044 (tp->link_config.autoneg == AUTONEG_ENABLE) &&
5045 (tp->phy_flags & TG3_PHYFLG_PARALLEL_DETECT)) {
5048 /* Select expansion interrupt status register */
5049 tg3_writephy(tp, MII_TG3_DSP_ADDRESS,
5050 MII_TG3_DSP_EXP1_INT_STAT);
5051 tg3_readphy(tp, MII_TG3_DSP_RW_PORT, &phy2);
5055 /* Config code words received, turn on autoneg. */
5056 tg3_readphy(tp, MII_BMCR, &bmcr);
5057 tg3_writephy(tp, MII_BMCR, bmcr | BMCR_ANENABLE);
5059 tp->phy_flags &= ~TG3_PHYFLG_PARALLEL_DETECT;
5065 static int tg3_setup_phy(struct tg3 *tp, int force_reset)
5070 if (tp->phy_flags & TG3_PHYFLG_PHY_SERDES)
5071 err = tg3_setup_fiber_phy(tp, force_reset);
5072 else if (tp->phy_flags & TG3_PHYFLG_MII_SERDES)
5073 err = tg3_setup_fiber_mii_phy(tp, force_reset);
5075 err = tg3_setup_copper_phy(tp, force_reset);
5077 if (GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5784_AX) {
5080 val = tr32(TG3_CPMU_CLCK_STAT) & CPMU_CLCK_STAT_MAC_CLCK_MASK;
5081 if (val == CPMU_CLCK_STAT_MAC_CLCK_62_5)
5083 else if (val == CPMU_CLCK_STAT_MAC_CLCK_6_25)
5088 val = tr32(GRC_MISC_CFG) & ~GRC_MISC_CFG_PRESCALAR_MASK;
5089 val |= (scale << GRC_MISC_CFG_PRESCALAR_SHIFT);
5090 tw32(GRC_MISC_CFG, val);
5093 val = (2 << TX_LENGTHS_IPG_CRS_SHIFT) |
5094 (6 << TX_LENGTHS_IPG_SHIFT);
5095 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5720)
5096 val |= tr32(MAC_TX_LENGTHS) &
5097 (TX_LENGTHS_JMB_FRM_LEN_MSK |
5098 TX_LENGTHS_CNT_DWN_VAL_MSK);
5100 if (tp->link_config.active_speed == SPEED_1000 &&
5101 tp->link_config.active_duplex == DUPLEX_HALF)
5102 tw32(MAC_TX_LENGTHS, val |
5103 (0xff << TX_LENGTHS_SLOT_TIME_SHIFT));
5105 tw32(MAC_TX_LENGTHS, val |
5106 (32 << TX_LENGTHS_SLOT_TIME_SHIFT));
5108 if (!tg3_flag(tp, 5705_PLUS)) {
5109 if (netif_carrier_ok(tp->dev)) {
5110 tw32(HOSTCC_STAT_COAL_TICKS,
5111 tp->coal.stats_block_coalesce_usecs);
5113 tw32(HOSTCC_STAT_COAL_TICKS, 0);
5117 if (tg3_flag(tp, ASPM_WORKAROUND)) {
5118 val = tr32(PCIE_PWR_MGMT_THRESH);
5119 if (!netif_carrier_ok(tp->dev))
5120 val = (val & ~PCIE_PWR_MGMT_L1_THRESH_MSK) |
5123 val |= PCIE_PWR_MGMT_L1_THRESH_MSK;
5124 tw32(PCIE_PWR_MGMT_THRESH, val);
5130 static inline int tg3_irq_sync(struct tg3 *tp)
5132 return tp->irq_sync;
5135 static inline void tg3_rd32_loop(struct tg3 *tp, u32 *dst, u32 off, u32 len)
5139 dst = (u32 *)((u8 *)dst + off);
5140 for (i = 0; i < len; i += sizeof(u32))
5141 *dst++ = tr32(off + i);
5144 static void tg3_dump_legacy_regs(struct tg3 *tp, u32 *regs)
5146 tg3_rd32_loop(tp, regs, TG3PCI_VENDOR, 0xb0);
5147 tg3_rd32_loop(tp, regs, MAILBOX_INTERRUPT_0, 0x200);
5148 tg3_rd32_loop(tp, regs, MAC_MODE, 0x4f0);
5149 tg3_rd32_loop(tp, regs, SNDDATAI_MODE, 0xe0);
5150 tg3_rd32_loop(tp, regs, SNDDATAC_MODE, 0x04);
5151 tg3_rd32_loop(tp, regs, SNDBDS_MODE, 0x80);
5152 tg3_rd32_loop(tp, regs, SNDBDI_MODE, 0x48);
5153 tg3_rd32_loop(tp, regs, SNDBDC_MODE, 0x04);
5154 tg3_rd32_loop(tp, regs, RCVLPC_MODE, 0x20);
5155 tg3_rd32_loop(tp, regs, RCVLPC_SELLST_BASE, 0x15c);
5156 tg3_rd32_loop(tp, regs, RCVDBDI_MODE, 0x0c);
5157 tg3_rd32_loop(tp, regs, RCVDBDI_JUMBO_BD, 0x3c);
5158 tg3_rd32_loop(tp, regs, RCVDBDI_BD_PROD_IDX_0, 0x44);
5159 tg3_rd32_loop(tp, regs, RCVDCC_MODE, 0x04);
5160 tg3_rd32_loop(tp, regs, RCVBDI_MODE, 0x20);
5161 tg3_rd32_loop(tp, regs, RCVCC_MODE, 0x14);
5162 tg3_rd32_loop(tp, regs, RCVLSC_MODE, 0x08);
5163 tg3_rd32_loop(tp, regs, MBFREE_MODE, 0x08);
5164 tg3_rd32_loop(tp, regs, HOSTCC_MODE, 0x100);
5166 if (tg3_flag(tp, SUPPORT_MSIX))
5167 tg3_rd32_loop(tp, regs, HOSTCC_RXCOL_TICKS_VEC1, 0x180);
5169 tg3_rd32_loop(tp, regs, MEMARB_MODE, 0x10);
5170 tg3_rd32_loop(tp, regs, BUFMGR_MODE, 0x58);
5171 tg3_rd32_loop(tp, regs, RDMAC_MODE, 0x08);
5172 tg3_rd32_loop(tp, regs, WDMAC_MODE, 0x08);
5173 tg3_rd32_loop(tp, regs, RX_CPU_MODE, 0x04);
5174 tg3_rd32_loop(tp, regs, RX_CPU_STATE, 0x04);
5175 tg3_rd32_loop(tp, regs, RX_CPU_PGMCTR, 0x04);
5176 tg3_rd32_loop(tp, regs, RX_CPU_HWBKPT, 0x04);
5178 if (!tg3_flag(tp, 5705_PLUS)) {
5179 tg3_rd32_loop(tp, regs, TX_CPU_MODE, 0x04);
5180 tg3_rd32_loop(tp, regs, TX_CPU_STATE, 0x04);
5181 tg3_rd32_loop(tp, regs, TX_CPU_PGMCTR, 0x04);
5184 tg3_rd32_loop(tp, regs, GRCMBOX_INTERRUPT_0, 0x110);
5185 tg3_rd32_loop(tp, regs, FTQ_RESET, 0x120);
5186 tg3_rd32_loop(tp, regs, MSGINT_MODE, 0x0c);
5187 tg3_rd32_loop(tp, regs, DMAC_MODE, 0x04);
5188 tg3_rd32_loop(tp, regs, GRC_MODE, 0x4c);
5190 if (tg3_flag(tp, NVRAM))
5191 tg3_rd32_loop(tp, regs, NVRAM_CMD, 0x24);
5194 static void tg3_dump_state(struct tg3 *tp)
5199 regs = kzalloc(TG3_REG_BLK_SIZE, GFP_ATOMIC);
5201 netdev_err(tp->dev, "Failed allocating register dump buffer\n");
5205 if (tg3_flag(tp, PCI_EXPRESS)) {
5206 /* Read up to but not including private PCI registers */
5207 for (i = 0; i < TG3_PCIE_TLDLPL_PORT; i += sizeof(u32))
5208 regs[i / sizeof(u32)] = tr32(i);
5210 tg3_dump_legacy_regs(tp, regs);
5212 for (i = 0; i < TG3_REG_BLK_SIZE / sizeof(u32); i += 4) {
5213 if (!regs[i + 0] && !regs[i + 1] &&
5214 !regs[i + 2] && !regs[i + 3])
5217 netdev_err(tp->dev, "0x%08x: 0x%08x, 0x%08x, 0x%08x, 0x%08x\n",
5219 regs[i + 0], regs[i + 1], regs[i + 2], regs[i + 3]);
5224 for (i = 0; i < tp->irq_cnt; i++) {
5225 struct tg3_napi *tnapi = &tp->napi[i];
5227 /* SW status block */
5229 "%d: Host status block [%08x:%08x:(%04x:%04x:%04x):(%04x:%04x)]\n",
5231 tnapi->hw_status->status,
5232 tnapi->hw_status->status_tag,
5233 tnapi->hw_status->rx_jumbo_consumer,
5234 tnapi->hw_status->rx_consumer,
5235 tnapi->hw_status->rx_mini_consumer,
5236 tnapi->hw_status->idx[0].rx_producer,
5237 tnapi->hw_status->idx[0].tx_consumer);
5240 "%d: NAPI info [%08x:%08x:(%04x:%04x:%04x):%04x:(%04x:%04x:%04x:%04x)]\n",
5242 tnapi->last_tag, tnapi->last_irq_tag,
5243 tnapi->tx_prod, tnapi->tx_cons, tnapi->tx_pending,
5245 tnapi->prodring.rx_std_prod_idx,
5246 tnapi->prodring.rx_std_cons_idx,
5247 tnapi->prodring.rx_jmb_prod_idx,
5248 tnapi->prodring.rx_jmb_cons_idx);
5252 /* This is called whenever we suspect that the system chipset is re-
5253 * ordering the sequence of MMIO to the tx send mailbox. The symptom
5254 * is bogus tx completions. We try to recover by setting the
5255 * TG3_FLAG_MBOX_WRITE_REORDER flag and resetting the chip later
5258 static void tg3_tx_recover(struct tg3 *tp)
5260 BUG_ON(tg3_flag(tp, MBOX_WRITE_REORDER) ||
5261 tp->write32_tx_mbox == tg3_write_indirect_mbox);
5263 netdev_warn(tp->dev,
5264 "The system may be re-ordering memory-mapped I/O "
5265 "cycles to the network device, attempting to recover. "
5266 "Please report the problem to the driver maintainer "
5267 "and include system chipset information.\n");
5269 spin_lock(&tp->lock);
5270 tg3_flag_set(tp, TX_RECOVERY_PENDING);
5271 spin_unlock(&tp->lock);
5274 static inline u32 tg3_tx_avail(struct tg3_napi *tnapi)
5276 /* Tell compiler to fetch tx indices from memory. */
5278 return tnapi->tx_pending -
5279 ((tnapi->tx_prod - tnapi->tx_cons) & (TG3_TX_RING_SIZE - 1));
5282 /* Tigon3 never reports partial packet sends. So we do not
5283 * need special logic to handle SKBs that have not had all
5284 * of their frags sent yet, like SunGEM does.
5286 static void tg3_tx(struct tg3_napi *tnapi)
5288 struct tg3 *tp = tnapi->tp;
5289 u32 hw_idx = tnapi->hw_status->idx[0].tx_consumer;
5290 u32 sw_idx = tnapi->tx_cons;
5291 struct netdev_queue *txq;
5292 int index = tnapi - tp->napi;
5293 unsigned int pkts_compl = 0, bytes_compl = 0;
5295 if (tg3_flag(tp, ENABLE_TSS))
5298 txq = netdev_get_tx_queue(tp->dev, index);
5300 while (sw_idx != hw_idx) {
5301 struct tg3_tx_ring_info *ri = &tnapi->tx_buffers[sw_idx];
5302 struct sk_buff *skb = ri->skb;
5305 if (unlikely(skb == NULL)) {
5310 pci_unmap_single(tp->pdev,
5311 dma_unmap_addr(ri, mapping),
5317 while (ri->fragmented) {
5318 ri->fragmented = false;
5319 sw_idx = NEXT_TX(sw_idx);
5320 ri = &tnapi->tx_buffers[sw_idx];
5323 sw_idx = NEXT_TX(sw_idx);
5325 for (i = 0; i < skb_shinfo(skb)->nr_frags; i++) {
5326 ri = &tnapi->tx_buffers[sw_idx];
5327 if (unlikely(ri->skb != NULL || sw_idx == hw_idx))
5330 pci_unmap_page(tp->pdev,
5331 dma_unmap_addr(ri, mapping),
5332 skb_frag_size(&skb_shinfo(skb)->frags[i]),
5335 while (ri->fragmented) {
5336 ri->fragmented = false;
5337 sw_idx = NEXT_TX(sw_idx);
5338 ri = &tnapi->tx_buffers[sw_idx];
5341 sw_idx = NEXT_TX(sw_idx);
5345 bytes_compl += skb->len;
5349 if (unlikely(tx_bug)) {
5355 netdev_completed_queue(tp->dev, pkts_compl, bytes_compl);
5357 tnapi->tx_cons = sw_idx;
5359 /* Need to make the tx_cons update visible to tg3_start_xmit()
5360 * before checking for netif_queue_stopped(). Without the
5361 * memory barrier, there is a small possibility that tg3_start_xmit()
5362 * will miss it and cause the queue to be stopped forever.
5366 if (unlikely(netif_tx_queue_stopped(txq) &&
5367 (tg3_tx_avail(tnapi) > TG3_TX_WAKEUP_THRESH(tnapi)))) {
5368 __netif_tx_lock(txq, smp_processor_id());
5369 if (netif_tx_queue_stopped(txq) &&
5370 (tg3_tx_avail(tnapi) > TG3_TX_WAKEUP_THRESH(tnapi)))
5371 netif_tx_wake_queue(txq);
5372 __netif_tx_unlock(txq);
5376 static void tg3_rx_data_free(struct tg3 *tp, struct ring_info *ri, u32 map_sz)
5381 pci_unmap_single(tp->pdev, dma_unmap_addr(ri, mapping),
5382 map_sz, PCI_DMA_FROMDEVICE);
5387 /* Returns size of skb allocated or < 0 on error.
5389 * We only need to fill in the address because the other members
5390 * of the RX descriptor are invariant, see tg3_init_rings.
5392 * Note the purposeful assymetry of cpu vs. chip accesses. For
5393 * posting buffers we only dirty the first cache line of the RX
5394 * descriptor (containing the address). Whereas for the RX status
5395 * buffers the cpu only reads the last cacheline of the RX descriptor
5396 * (to fetch the error flags, vlan tag, checksum, and opaque cookie).
5398 static int tg3_alloc_rx_data(struct tg3 *tp, struct tg3_rx_prodring_set *tpr,
5399 u32 opaque_key, u32 dest_idx_unmasked)
5401 struct tg3_rx_buffer_desc *desc;
5402 struct ring_info *map;
5405 int skb_size, data_size, dest_idx;
5407 switch (opaque_key) {
5408 case RXD_OPAQUE_RING_STD:
5409 dest_idx = dest_idx_unmasked & tp->rx_std_ring_mask;
5410 desc = &tpr->rx_std[dest_idx];
5411 map = &tpr->rx_std_buffers[dest_idx];
5412 data_size = tp->rx_pkt_map_sz;
5415 case RXD_OPAQUE_RING_JUMBO:
5416 dest_idx = dest_idx_unmasked & tp->rx_jmb_ring_mask;
5417 desc = &tpr->rx_jmb[dest_idx].std;
5418 map = &tpr->rx_jmb_buffers[dest_idx];
5419 data_size = TG3_RX_JMB_MAP_SZ;
5426 /* Do not overwrite any of the map or rp information
5427 * until we are sure we can commit to a new buffer.
5429 * Callers depend upon this behavior and assume that
5430 * we leave everything unchanged if we fail.
5432 skb_size = SKB_DATA_ALIGN(data_size + TG3_RX_OFFSET(tp)) +
5433 SKB_DATA_ALIGN(sizeof(struct skb_shared_info));
5434 data = kmalloc(skb_size, GFP_ATOMIC);
5438 mapping = pci_map_single(tp->pdev,
5439 data + TG3_RX_OFFSET(tp),
5441 PCI_DMA_FROMDEVICE);
5442 if (pci_dma_mapping_error(tp->pdev, mapping)) {
5448 dma_unmap_addr_set(map, mapping, mapping);
5450 desc->addr_hi = ((u64)mapping >> 32);
5451 desc->addr_lo = ((u64)mapping & 0xffffffff);
5456 /* We only need to move over in the address because the other
5457 * members of the RX descriptor are invariant. See notes above
5458 * tg3_alloc_rx_data for full details.
5460 static void tg3_recycle_rx(struct tg3_napi *tnapi,
5461 struct tg3_rx_prodring_set *dpr,
5462 u32 opaque_key, int src_idx,
5463 u32 dest_idx_unmasked)
5465 struct tg3 *tp = tnapi->tp;
5466 struct tg3_rx_buffer_desc *src_desc, *dest_desc;
5467 struct ring_info *src_map, *dest_map;
5468 struct tg3_rx_prodring_set *spr = &tp->napi[0].prodring;
5471 switch (opaque_key) {
5472 case RXD_OPAQUE_RING_STD:
5473 dest_idx = dest_idx_unmasked & tp->rx_std_ring_mask;
5474 dest_desc = &dpr->rx_std[dest_idx];
5475 dest_map = &dpr->rx_std_buffers[dest_idx];
5476 src_desc = &spr->rx_std[src_idx];
5477 src_map = &spr->rx_std_buffers[src_idx];
5480 case RXD_OPAQUE_RING_JUMBO:
5481 dest_idx = dest_idx_unmasked & tp->rx_jmb_ring_mask;
5482 dest_desc = &dpr->rx_jmb[dest_idx].std;
5483 dest_map = &dpr->rx_jmb_buffers[dest_idx];
5484 src_desc = &spr->rx_jmb[src_idx].std;
5485 src_map = &spr->rx_jmb_buffers[src_idx];
5492 dest_map->data = src_map->data;
5493 dma_unmap_addr_set(dest_map, mapping,
5494 dma_unmap_addr(src_map, mapping));
5495 dest_desc->addr_hi = src_desc->addr_hi;
5496 dest_desc->addr_lo = src_desc->addr_lo;
5498 /* Ensure that the update to the skb happens after the physical
5499 * addresses have been transferred to the new BD location.
5503 src_map->data = NULL;
5506 /* The RX ring scheme is composed of multiple rings which post fresh
5507 * buffers to the chip, and one special ring the chip uses to report
5508 * status back to the host.
5510 * The special ring reports the status of received packets to the
5511 * host. The chip does not write into the original descriptor the
5512 * RX buffer was obtained from. The chip simply takes the original
5513 * descriptor as provided by the host, updates the status and length
5514 * field, then writes this into the next status ring entry.
5516 * Each ring the host uses to post buffers to the chip is described
5517 * by a TG3_BDINFO entry in the chips SRAM area. When a packet arrives,
5518 * it is first placed into the on-chip ram. When the packet's length
5519 * is known, it walks down the TG3_BDINFO entries to select the ring.
5520 * Each TG3_BDINFO specifies a MAXLEN field and the first TG3_BDINFO
5521 * which is within the range of the new packet's length is chosen.
5523 * The "separate ring for rx status" scheme may sound queer, but it makes
5524 * sense from a cache coherency perspective. If only the host writes
5525 * to the buffer post rings, and only the chip writes to the rx status
5526 * rings, then cache lines never move beyond shared-modified state.
5527 * If both the host and chip were to write into the same ring, cache line
5528 * eviction could occur since both entities want it in an exclusive state.
5530 static int tg3_rx(struct tg3_napi *tnapi, int budget)
5532 struct tg3 *tp = tnapi->tp;
5533 u32 work_mask, rx_std_posted = 0;
5534 u32 std_prod_idx, jmb_prod_idx;
5535 u32 sw_idx = tnapi->rx_rcb_ptr;
5538 struct tg3_rx_prodring_set *tpr = &tnapi->prodring;
5540 hw_idx = *(tnapi->rx_rcb_prod_idx);
5542 * We need to order the read of hw_idx and the read of
5543 * the opaque cookie.
5548 std_prod_idx = tpr->rx_std_prod_idx;
5549 jmb_prod_idx = tpr->rx_jmb_prod_idx;
5550 while (sw_idx != hw_idx && budget > 0) {
5551 struct ring_info *ri;
5552 struct tg3_rx_buffer_desc *desc = &tnapi->rx_rcb[sw_idx];
5554 struct sk_buff *skb;
5555 dma_addr_t dma_addr;
5556 u32 opaque_key, desc_idx, *post_ptr;
5559 desc_idx = desc->opaque & RXD_OPAQUE_INDEX_MASK;
5560 opaque_key = desc->opaque & RXD_OPAQUE_RING_MASK;
5561 if (opaque_key == RXD_OPAQUE_RING_STD) {
5562 ri = &tp->napi[0].prodring.rx_std_buffers[desc_idx];
5563 dma_addr = dma_unmap_addr(ri, mapping);
5565 post_ptr = &std_prod_idx;
5567 } else if (opaque_key == RXD_OPAQUE_RING_JUMBO) {
5568 ri = &tp->napi[0].prodring.rx_jmb_buffers[desc_idx];
5569 dma_addr = dma_unmap_addr(ri, mapping);
5571 post_ptr = &jmb_prod_idx;
5573 goto next_pkt_nopost;
5575 work_mask |= opaque_key;
5577 if ((desc->err_vlan & RXD_ERR_MASK) != 0 &&
5578 (desc->err_vlan != RXD_ERR_ODD_NIBBLE_RCVD_MII)) {
5580 tg3_recycle_rx(tnapi, tpr, opaque_key,
5581 desc_idx, *post_ptr);
5583 /* Other statistics kept track of by card. */
5588 prefetch(data + TG3_RX_OFFSET(tp));
5589 len = ((desc->idx_len & RXD_LEN_MASK) >> RXD_LEN_SHIFT) -
5592 if (len > TG3_RX_COPY_THRESH(tp)) {
5595 skb_size = tg3_alloc_rx_data(tp, tpr, opaque_key,
5600 pci_unmap_single(tp->pdev, dma_addr, skb_size,
5601 PCI_DMA_FROMDEVICE);
5603 skb = build_skb(data);
5606 goto drop_it_no_recycle;
5608 skb_reserve(skb, TG3_RX_OFFSET(tp));
5609 /* Ensure that the update to the data happens
5610 * after the usage of the old DMA mapping.
5617 tg3_recycle_rx(tnapi, tpr, opaque_key,
5618 desc_idx, *post_ptr);
5620 skb = netdev_alloc_skb(tp->dev,
5621 len + TG3_RAW_IP_ALIGN);
5623 goto drop_it_no_recycle;
5625 skb_reserve(skb, TG3_RAW_IP_ALIGN);
5626 pci_dma_sync_single_for_cpu(tp->pdev, dma_addr, len, PCI_DMA_FROMDEVICE);
5628 data + TG3_RX_OFFSET(tp),
5630 pci_dma_sync_single_for_device(tp->pdev, dma_addr, len, PCI_DMA_FROMDEVICE);
5634 if ((tp->dev->features & NETIF_F_RXCSUM) &&
5635 (desc->type_flags & RXD_FLAG_TCPUDP_CSUM) &&
5636 (((desc->ip_tcp_csum & RXD_TCPCSUM_MASK)
5637 >> RXD_TCPCSUM_SHIFT) == 0xffff))
5638 skb->ip_summed = CHECKSUM_UNNECESSARY;
5640 skb_checksum_none_assert(skb);
5642 skb->protocol = eth_type_trans(skb, tp->dev);
5644 if (len > (tp->dev->mtu + ETH_HLEN) &&
5645 skb->protocol != htons(ETH_P_8021Q)) {
5647 goto drop_it_no_recycle;
5650 if (desc->type_flags & RXD_FLAG_VLAN &&
5651 !(tp->rx_mode & RX_MODE_KEEP_VLAN_TAG))
5652 __vlan_hwaccel_put_tag(skb,
5653 desc->err_vlan & RXD_VLAN_MASK);
5655 napi_gro_receive(&tnapi->napi, skb);
5663 if (unlikely(rx_std_posted >= tp->rx_std_max_post)) {
5664 tpr->rx_std_prod_idx = std_prod_idx &
5665 tp->rx_std_ring_mask;
5666 tw32_rx_mbox(TG3_RX_STD_PROD_IDX_REG,
5667 tpr->rx_std_prod_idx);
5668 work_mask &= ~RXD_OPAQUE_RING_STD;
5673 sw_idx &= tp->rx_ret_ring_mask;
5675 /* Refresh hw_idx to see if there is new work */
5676 if (sw_idx == hw_idx) {
5677 hw_idx = *(tnapi->rx_rcb_prod_idx);
5682 /* ACK the status ring. */
5683 tnapi->rx_rcb_ptr = sw_idx;
5684 tw32_rx_mbox(tnapi->consmbox, sw_idx);
5686 /* Refill RX ring(s). */
5687 if (!tg3_flag(tp, ENABLE_RSS)) {
5688 if (work_mask & RXD_OPAQUE_RING_STD) {
5689 tpr->rx_std_prod_idx = std_prod_idx &
5690 tp->rx_std_ring_mask;
5691 tw32_rx_mbox(TG3_RX_STD_PROD_IDX_REG,
5692 tpr->rx_std_prod_idx);
5694 if (work_mask & RXD_OPAQUE_RING_JUMBO) {
5695 tpr->rx_jmb_prod_idx = jmb_prod_idx &
5696 tp->rx_jmb_ring_mask;
5697 tw32_rx_mbox(TG3_RX_JMB_PROD_IDX_REG,
5698 tpr->rx_jmb_prod_idx);
5701 } else if (work_mask) {
5702 /* rx_std_buffers[] and rx_jmb_buffers[] entries must be
5703 * updated before the producer indices can be updated.
5707 tpr->rx_std_prod_idx = std_prod_idx & tp->rx_std_ring_mask;
5708 tpr->rx_jmb_prod_idx = jmb_prod_idx & tp->rx_jmb_ring_mask;
5710 if (tnapi != &tp->napi[1])
5711 napi_schedule(&tp->napi[1].napi);
5717 static void tg3_poll_link(struct tg3 *tp)
5719 /* handle link change and other phy events */
5720 if (!(tg3_flag(tp, USE_LINKCHG_REG) || tg3_flag(tp, POLL_SERDES))) {
5721 struct tg3_hw_status *sblk = tp->napi[0].hw_status;
5723 if (sblk->status & SD_STATUS_LINK_CHG) {
5724 sblk->status = SD_STATUS_UPDATED |
5725 (sblk->status & ~SD_STATUS_LINK_CHG);
5726 spin_lock(&tp->lock);
5727 if (tg3_flag(tp, USE_PHYLIB)) {
5729 (MAC_STATUS_SYNC_CHANGED |
5730 MAC_STATUS_CFG_CHANGED |
5731 MAC_STATUS_MI_COMPLETION |
5732 MAC_STATUS_LNKSTATE_CHANGED));
5735 tg3_setup_phy(tp, 0);
5736 spin_unlock(&tp->lock);
5741 static int tg3_rx_prodring_xfer(struct tg3 *tp,
5742 struct tg3_rx_prodring_set *dpr,
5743 struct tg3_rx_prodring_set *spr)
5745 u32 si, di, cpycnt, src_prod_idx;
5749 src_prod_idx = spr->rx_std_prod_idx;
5751 /* Make sure updates to the rx_std_buffers[] entries and the
5752 * standard producer index are seen in the correct order.
5756 if (spr->rx_std_cons_idx == src_prod_idx)
5759 if (spr->rx_std_cons_idx < src_prod_idx)
5760 cpycnt = src_prod_idx - spr->rx_std_cons_idx;
5762 cpycnt = tp->rx_std_ring_mask + 1 -
5763 spr->rx_std_cons_idx;
5765 cpycnt = min(cpycnt,
5766 tp->rx_std_ring_mask + 1 - dpr->rx_std_prod_idx);
5768 si = spr->rx_std_cons_idx;
5769 di = dpr->rx_std_prod_idx;
5771 for (i = di; i < di + cpycnt; i++) {
5772 if (dpr->rx_std_buffers[i].data) {
5782 /* Ensure that updates to the rx_std_buffers ring and the
5783 * shadowed hardware producer ring from tg3_recycle_skb() are
5784 * ordered correctly WRT the skb check above.
5788 memcpy(&dpr->rx_std_buffers[di],
5789 &spr->rx_std_buffers[si],
5790 cpycnt * sizeof(struct ring_info));
5792 for (i = 0; i < cpycnt; i++, di++, si++) {
5793 struct tg3_rx_buffer_desc *sbd, *dbd;
5794 sbd = &spr->rx_std[si];
5795 dbd = &dpr->rx_std[di];
5796 dbd->addr_hi = sbd->addr_hi;
5797 dbd->addr_lo = sbd->addr_lo;
5800 spr->rx_std_cons_idx = (spr->rx_std_cons_idx + cpycnt) &
5801 tp->rx_std_ring_mask;
5802 dpr->rx_std_prod_idx = (dpr->rx_std_prod_idx + cpycnt) &
5803 tp->rx_std_ring_mask;
5807 src_prod_idx = spr->rx_jmb_prod_idx;
5809 /* Make sure updates to the rx_jmb_buffers[] entries and
5810 * the jumbo producer index are seen in the correct order.
5814 if (spr->rx_jmb_cons_idx == src_prod_idx)
5817 if (spr->rx_jmb_cons_idx < src_prod_idx)
5818 cpycnt = src_prod_idx - spr->rx_jmb_cons_idx;
5820 cpycnt = tp->rx_jmb_ring_mask + 1 -
5821 spr->rx_jmb_cons_idx;
5823 cpycnt = min(cpycnt,
5824 tp->rx_jmb_ring_mask + 1 - dpr->rx_jmb_prod_idx);
5826 si = spr->rx_jmb_cons_idx;
5827 di = dpr->rx_jmb_prod_idx;
5829 for (i = di; i < di + cpycnt; i++) {
5830 if (dpr->rx_jmb_buffers[i].data) {
5840 /* Ensure that updates to the rx_jmb_buffers ring and the
5841 * shadowed hardware producer ring from tg3_recycle_skb() are
5842 * ordered correctly WRT the skb check above.
5846 memcpy(&dpr->rx_jmb_buffers[di],
5847 &spr->rx_jmb_buffers[si],
5848 cpycnt * sizeof(struct ring_info));
5850 for (i = 0; i < cpycnt; i++, di++, si++) {
5851 struct tg3_rx_buffer_desc *sbd, *dbd;
5852 sbd = &spr->rx_jmb[si].std;
5853 dbd = &dpr->rx_jmb[di].std;
5854 dbd->addr_hi = sbd->addr_hi;
5855 dbd->addr_lo = sbd->addr_lo;
5858 spr->rx_jmb_cons_idx = (spr->rx_jmb_cons_idx + cpycnt) &
5859 tp->rx_jmb_ring_mask;
5860 dpr->rx_jmb_prod_idx = (dpr->rx_jmb_prod_idx + cpycnt) &
5861 tp->rx_jmb_ring_mask;
5867 static int tg3_poll_work(struct tg3_napi *tnapi, int work_done, int budget)
5869 struct tg3 *tp = tnapi->tp;
5871 /* run TX completion thread */
5872 if (tnapi->hw_status->idx[0].tx_consumer != tnapi->tx_cons) {
5874 if (unlikely(tg3_flag(tp, TX_RECOVERY_PENDING)))
5878 /* run RX thread, within the bounds set by NAPI.
5879 * All RX "locking" is done by ensuring outside
5880 * code synchronizes with tg3->napi.poll()
5882 if (*(tnapi->rx_rcb_prod_idx) != tnapi->rx_rcb_ptr)
5883 work_done += tg3_rx(tnapi, budget - work_done);
5885 if (tg3_flag(tp, ENABLE_RSS) && tnapi == &tp->napi[1]) {
5886 struct tg3_rx_prodring_set *dpr = &tp->napi[0].prodring;
5888 u32 std_prod_idx = dpr->rx_std_prod_idx;
5889 u32 jmb_prod_idx = dpr->rx_jmb_prod_idx;
5891 for (i = 1; i < tp->irq_cnt; i++)
5892 err |= tg3_rx_prodring_xfer(tp, dpr,
5893 &tp->napi[i].prodring);
5897 if (std_prod_idx != dpr->rx_std_prod_idx)
5898 tw32_rx_mbox(TG3_RX_STD_PROD_IDX_REG,
5899 dpr->rx_std_prod_idx);
5901 if (jmb_prod_idx != dpr->rx_jmb_prod_idx)
5902 tw32_rx_mbox(TG3_RX_JMB_PROD_IDX_REG,
5903 dpr->rx_jmb_prod_idx);
5908 tw32_f(HOSTCC_MODE, tp->coal_now);
5914 static inline void tg3_reset_task_schedule(struct tg3 *tp)
5916 if (!test_and_set_bit(TG3_FLAG_RESET_TASK_PENDING, tp->tg3_flags))
5917 schedule_work(&tp->reset_task);
5920 static inline void tg3_reset_task_cancel(struct tg3 *tp)
5922 cancel_work_sync(&tp->reset_task);
5923 tg3_flag_clear(tp, RESET_TASK_PENDING);
5926 static int tg3_poll_msix(struct napi_struct *napi, int budget)
5928 struct tg3_napi *tnapi = container_of(napi, struct tg3_napi, napi);
5929 struct tg3 *tp = tnapi->tp;
5931 struct tg3_hw_status *sblk = tnapi->hw_status;
5934 work_done = tg3_poll_work(tnapi, work_done, budget);
5936 if (unlikely(tg3_flag(tp, TX_RECOVERY_PENDING)))
5939 if (unlikely(work_done >= budget))
5942 /* tp->last_tag is used in tg3_int_reenable() below
5943 * to tell the hw how much work has been processed,
5944 * so we must read it before checking for more work.
5946 tnapi->last_tag = sblk->status_tag;
5947 tnapi->last_irq_tag = tnapi->last_tag;
5950 /* check for RX/TX work to do */
5951 if (likely(sblk->idx[0].tx_consumer == tnapi->tx_cons &&
5952 *(tnapi->rx_rcb_prod_idx) == tnapi->rx_rcb_ptr)) {
5953 napi_complete(napi);
5954 /* Reenable interrupts. */
5955 tw32_mailbox(tnapi->int_mbox, tnapi->last_tag << 24);
5964 /* work_done is guaranteed to be less than budget. */
5965 napi_complete(napi);
5966 tg3_reset_task_schedule(tp);
5970 static void tg3_process_error(struct tg3 *tp)
5973 bool real_error = false;
5975 if (tg3_flag(tp, ERROR_PROCESSED))
5978 /* Check Flow Attention register */
5979 val = tr32(HOSTCC_FLOW_ATTN);
5980 if (val & ~HOSTCC_FLOW_ATTN_MBUF_LWM) {
5981 netdev_err(tp->dev, "FLOW Attention error. Resetting chip.\n");
5985 if (tr32(MSGINT_STATUS) & ~MSGINT_STATUS_MSI_REQ) {
5986 netdev_err(tp->dev, "MSI Status error. Resetting chip.\n");
5990 if (tr32(RDMAC_STATUS) || tr32(WDMAC_STATUS)) {
5991 netdev_err(tp->dev, "DMA Status error. Resetting chip.\n");
6000 tg3_flag_set(tp, ERROR_PROCESSED);
6001 tg3_reset_task_schedule(tp);
6004 static int tg3_poll(struct napi_struct *napi, int budget)
6006 struct tg3_napi *tnapi = container_of(napi, struct tg3_napi, napi);
6007 struct tg3 *tp = tnapi->tp;
6009 struct tg3_hw_status *sblk = tnapi->hw_status;
6012 if (sblk->status & SD_STATUS_ERROR)
6013 tg3_process_error(tp);
6017 work_done = tg3_poll_work(tnapi, work_done, budget);
6019 if (unlikely(tg3_flag(tp, TX_RECOVERY_PENDING)))
6022 if (unlikely(work_done >= budget))
6025 if (tg3_flag(tp, TAGGED_STATUS)) {
6026 /* tp->last_tag is used in tg3_int_reenable() below
6027 * to tell the hw how much work has been processed,
6028 * so we must read it before checking for more work.
6030 tnapi->last_tag = sblk->status_tag;
6031 tnapi->last_irq_tag = tnapi->last_tag;
6034 sblk->status &= ~SD_STATUS_UPDATED;
6036 if (likely(!tg3_has_work(tnapi))) {
6037 napi_complete(napi);
6038 tg3_int_reenable(tnapi);
6046 /* work_done is guaranteed to be less than budget. */
6047 napi_complete(napi);
6048 tg3_reset_task_schedule(tp);
6052 static void tg3_napi_disable(struct tg3 *tp)
6056 for (i = tp->irq_cnt - 1; i >= 0; i--)
6057 napi_disable(&tp->napi[i].napi);
6060 static void tg3_napi_enable(struct tg3 *tp)
6064 for (i = 0; i < tp->irq_cnt; i++)
6065 napi_enable(&tp->napi[i].napi);
6068 static void tg3_napi_init(struct tg3 *tp)
6072 netif_napi_add(tp->dev, &tp->napi[0].napi, tg3_poll, 64);
6073 for (i = 1; i < tp->irq_cnt; i++)
6074 netif_napi_add(tp->dev, &tp->napi[i].napi, tg3_poll_msix, 64);
6077 static void tg3_napi_fini(struct tg3 *tp)
6081 for (i = 0; i < tp->irq_cnt; i++)
6082 netif_napi_del(&tp->napi[i].napi);
6085 static inline void tg3_netif_stop(struct tg3 *tp)
6087 tp->dev->trans_start = jiffies; /* prevent tx timeout */
6088 tg3_napi_disable(tp);
6089 netif_tx_disable(tp->dev);
6092 static inline void tg3_netif_start(struct tg3 *tp)
6094 /* NOTE: unconditional netif_tx_wake_all_queues is only
6095 * appropriate so long as all callers are assured to
6096 * have free tx slots (such as after tg3_init_hw)
6098 netif_tx_wake_all_queues(tp->dev);
6100 tg3_napi_enable(tp);
6101 tp->napi[0].hw_status->status |= SD_STATUS_UPDATED;
6102 tg3_enable_ints(tp);
6105 static void tg3_irq_quiesce(struct tg3 *tp)
6109 BUG_ON(tp->irq_sync);
6114 for (i = 0; i < tp->irq_cnt; i++)
6115 synchronize_irq(tp->napi[i].irq_vec);
6118 /* Fully shutdown all tg3 driver activity elsewhere in the system.
6119 * If irq_sync is non-zero, then the IRQ handler must be synchronized
6120 * with as well. Most of the time, this is not necessary except when
6121 * shutting down the device.
6123 static inline void tg3_full_lock(struct tg3 *tp, int irq_sync)
6125 spin_lock_bh(&tp->lock);
6127 tg3_irq_quiesce(tp);
6130 static inline void tg3_full_unlock(struct tg3 *tp)
6132 spin_unlock_bh(&tp->lock);
6135 /* One-shot MSI handler - Chip automatically disables interrupt
6136 * after sending MSI so driver doesn't have to do it.
6138 static irqreturn_t tg3_msi_1shot(int irq, void *dev_id)
6140 struct tg3_napi *tnapi = dev_id;
6141 struct tg3 *tp = tnapi->tp;
6143 prefetch(tnapi->hw_status);
6145 prefetch(&tnapi->rx_rcb[tnapi->rx_rcb_ptr]);
6147 if (likely(!tg3_irq_sync(tp)))
6148 napi_schedule(&tnapi->napi);
6153 /* MSI ISR - No need to check for interrupt sharing and no need to
6154 * flush status block and interrupt mailbox. PCI ordering rules
6155 * guarantee that MSI will arrive after the status block.
6157 static irqreturn_t tg3_msi(int irq, void *dev_id)
6159 struct tg3_napi *tnapi = dev_id;
6160 struct tg3 *tp = tnapi->tp;
6162 prefetch(tnapi->hw_status);
6164 prefetch(&tnapi->rx_rcb[tnapi->rx_rcb_ptr]);
6166 * Writing any value to intr-mbox-0 clears PCI INTA# and
6167 * chip-internal interrupt pending events.
6168 * Writing non-zero to intr-mbox-0 additional tells the
6169 * NIC to stop sending us irqs, engaging "in-intr-handler"
6172 tw32_mailbox(tnapi->int_mbox, 0x00000001);
6173 if (likely(!tg3_irq_sync(tp)))
6174 napi_schedule(&tnapi->napi);
6176 return IRQ_RETVAL(1);
6179 static irqreturn_t tg3_interrupt(int irq, void *dev_id)
6181 struct tg3_napi *tnapi = dev_id;
6182 struct tg3 *tp = tnapi->tp;
6183 struct tg3_hw_status *sblk = tnapi->hw_status;
6184 unsigned int handled = 1;
6186 /* In INTx mode, it is possible for the interrupt to arrive at
6187 * the CPU before the status block posted prior to the interrupt.
6188 * Reading the PCI State register will confirm whether the
6189 * interrupt is ours and will flush the status block.
6191 if (unlikely(!(sblk->status & SD_STATUS_UPDATED))) {
6192 if (tg3_flag(tp, CHIP_RESETTING) ||
6193 (tr32(TG3PCI_PCISTATE) & PCISTATE_INT_NOT_ACTIVE)) {
6200 * Writing any value to intr-mbox-0 clears PCI INTA# and
6201 * chip-internal interrupt pending events.
6202 * Writing non-zero to intr-mbox-0 additional tells the
6203 * NIC to stop sending us irqs, engaging "in-intr-handler"
6206 * Flush the mailbox to de-assert the IRQ immediately to prevent
6207 * spurious interrupts. The flush impacts performance but
6208 * excessive spurious interrupts can be worse in some cases.
6210 tw32_mailbox_f(MAILBOX_INTERRUPT_0 + TG3_64BIT_REG_LOW, 0x00000001);
6211 if (tg3_irq_sync(tp))
6213 sblk->status &= ~SD_STATUS_UPDATED;
6214 if (likely(tg3_has_work(tnapi))) {
6215 prefetch(&tnapi->rx_rcb[tnapi->rx_rcb_ptr]);
6216 napi_schedule(&tnapi->napi);
6218 /* No work, shared interrupt perhaps? re-enable
6219 * interrupts, and flush that PCI write
6221 tw32_mailbox_f(MAILBOX_INTERRUPT_0 + TG3_64BIT_REG_LOW,
6225 return IRQ_RETVAL(handled);
6228 static irqreturn_t tg3_interrupt_tagged(int irq, void *dev_id)
6230 struct tg3_napi *tnapi = dev_id;
6231 struct tg3 *tp = tnapi->tp;
6232 struct tg3_hw_status *sblk = tnapi->hw_status;
6233 unsigned int handled = 1;
6235 /* In INTx mode, it is possible for the interrupt to arrive at
6236 * the CPU before the status block posted prior to the interrupt.
6237 * Reading the PCI State register will confirm whether the
6238 * interrupt is ours and will flush the status block.
6240 if (unlikely(sblk->status_tag == tnapi->last_irq_tag)) {
6241 if (tg3_flag(tp, CHIP_RESETTING) ||
6242 (tr32(TG3PCI_PCISTATE) & PCISTATE_INT_NOT_ACTIVE)) {
6249 * writing any value to intr-mbox-0 clears PCI INTA# and
6250 * chip-internal interrupt pending events.
6251 * writing non-zero to intr-mbox-0 additional tells the
6252 * NIC to stop sending us irqs, engaging "in-intr-handler"
6255 * Flush the mailbox to de-assert the IRQ immediately to prevent
6256 * spurious interrupts. The flush impacts performance but
6257 * excessive spurious interrupts can be worse in some cases.
6259 tw32_mailbox_f(MAILBOX_INTERRUPT_0 + TG3_64BIT_REG_LOW, 0x00000001);
6262 * In a shared interrupt configuration, sometimes other devices'
6263 * interrupts will scream. We record the current status tag here
6264 * so that the above check can report that the screaming interrupts
6265 * are unhandled. Eventually they will be silenced.
6267 tnapi->last_irq_tag = sblk->status_tag;
6269 if (tg3_irq_sync(tp))
6272 prefetch(&tnapi->rx_rcb[tnapi->rx_rcb_ptr]);
6274 napi_schedule(&tnapi->napi);
6277 return IRQ_RETVAL(handled);
6280 /* ISR for interrupt test */
6281 static irqreturn_t tg3_test_isr(int irq, void *dev_id)
6283 struct tg3_napi *tnapi = dev_id;
6284 struct tg3 *tp = tnapi->tp;
6285 struct tg3_hw_status *sblk = tnapi->hw_status;
6287 if ((sblk->status & SD_STATUS_UPDATED) ||
6288 !(tr32(TG3PCI_PCISTATE) & PCISTATE_INT_NOT_ACTIVE)) {
6289 tg3_disable_ints(tp);
6290 return IRQ_RETVAL(1);
6292 return IRQ_RETVAL(0);
6295 static int tg3_init_hw(struct tg3 *, int);
6296 static int tg3_halt(struct tg3 *, int, int);
6298 /* Restart hardware after configuration changes, self-test, etc.
6299 * Invoked with tp->lock held.
6301 static int tg3_restart_hw(struct tg3 *tp, int reset_phy)
6302 __releases(tp->lock)
6303 __acquires(tp->lock)
6307 err = tg3_init_hw(tp, reset_phy);
6310 "Failed to re-initialize device, aborting\n");
6311 tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
6312 tg3_full_unlock(tp);
6313 del_timer_sync(&tp->timer);
6315 tg3_napi_enable(tp);
6317 tg3_full_lock(tp, 0);
6322 #ifdef CONFIG_NET_POLL_CONTROLLER
6323 static void tg3_poll_controller(struct net_device *dev)
6326 struct tg3 *tp = netdev_priv(dev);
6328 for (i = 0; i < tp->irq_cnt; i++)
6329 tg3_interrupt(tp->napi[i].irq_vec, &tp->napi[i]);
6333 static void tg3_reset_task(struct work_struct *work)
6335 struct tg3 *tp = container_of(work, struct tg3, reset_task);
6338 tg3_full_lock(tp, 0);
6340 if (!netif_running(tp->dev)) {
6341 tg3_flag_clear(tp, RESET_TASK_PENDING);
6342 tg3_full_unlock(tp);
6346 tg3_full_unlock(tp);
6352 tg3_full_lock(tp, 1);
6354 if (tg3_flag(tp, TX_RECOVERY_PENDING)) {
6355 tp->write32_tx_mbox = tg3_write32_tx_mbox;
6356 tp->write32_rx_mbox = tg3_write_flush_reg32;
6357 tg3_flag_set(tp, MBOX_WRITE_REORDER);
6358 tg3_flag_clear(tp, TX_RECOVERY_PENDING);
6361 tg3_halt(tp, RESET_KIND_SHUTDOWN, 0);
6362 err = tg3_init_hw(tp, 1);
6366 tg3_netif_start(tp);
6369 tg3_full_unlock(tp);
6374 tg3_flag_clear(tp, RESET_TASK_PENDING);
6377 static void tg3_tx_timeout(struct net_device *dev)
6379 struct tg3 *tp = netdev_priv(dev);
6381 if (netif_msg_tx_err(tp)) {
6382 netdev_err(dev, "transmit timed out, resetting\n");
6386 tg3_reset_task_schedule(tp);
6389 /* Test for DMA buffers crossing any 4GB boundaries: 4G, 8G, etc */
6390 static inline int tg3_4g_overflow_test(dma_addr_t mapping, int len)
6392 u32 base = (u32) mapping & 0xffffffff;
6394 return (base > 0xffffdcc0) && (base + len + 8 < base);
6397 /* Test for DMA addresses > 40-bit */
6398 static inline int tg3_40bit_overflow_test(struct tg3 *tp, dma_addr_t mapping,
6401 #if defined(CONFIG_HIGHMEM) && (BITS_PER_LONG == 64)
6402 if (tg3_flag(tp, 40BIT_DMA_BUG))
6403 return ((u64) mapping + len) > DMA_BIT_MASK(40);
6410 static inline void tg3_tx_set_bd(struct tg3_tx_buffer_desc *txbd,
6411 dma_addr_t mapping, u32 len, u32 flags,
6414 txbd->addr_hi = ((u64) mapping >> 32);
6415 txbd->addr_lo = ((u64) mapping & 0xffffffff);
6416 txbd->len_flags = (len << TXD_LEN_SHIFT) | (flags & 0x0000ffff);
6417 txbd->vlan_tag = (mss << TXD_MSS_SHIFT) | (vlan << TXD_VLAN_TAG_SHIFT);
6420 static bool tg3_tx_frag_set(struct tg3_napi *tnapi, u32 *entry, u32 *budget,
6421 dma_addr_t map, u32 len, u32 flags,
6424 struct tg3 *tp = tnapi->tp;
6427 if (tg3_flag(tp, SHORT_DMA_BUG) && len <= 8)
6430 if (tg3_4g_overflow_test(map, len))
6433 if (tg3_40bit_overflow_test(tp, map, len))
6436 if (tp->dma_limit) {
6437 u32 prvidx = *entry;
6438 u32 tmp_flag = flags & ~TXD_FLAG_END;
6439 while (len > tp->dma_limit && *budget) {
6440 u32 frag_len = tp->dma_limit;
6441 len -= tp->dma_limit;
6443 /* Avoid the 8byte DMA problem */
6445 len += tp->dma_limit / 2;
6446 frag_len = tp->dma_limit / 2;
6449 tnapi->tx_buffers[*entry].fragmented = true;
6451 tg3_tx_set_bd(&tnapi->tx_ring[*entry], map,
6452 frag_len, tmp_flag, mss, vlan);
6455 *entry = NEXT_TX(*entry);
6462 tg3_tx_set_bd(&tnapi->tx_ring[*entry], map,
6463 len, flags, mss, vlan);
6465 *entry = NEXT_TX(*entry);
6468 tnapi->tx_buffers[prvidx].fragmented = false;
6472 tg3_tx_set_bd(&tnapi->tx_ring[*entry], map,
6473 len, flags, mss, vlan);
6474 *entry = NEXT_TX(*entry);
6480 static void tg3_tx_skb_unmap(struct tg3_napi *tnapi, u32 entry, int last)
6483 struct sk_buff *skb;
6484 struct tg3_tx_ring_info *txb = &tnapi->tx_buffers[entry];
6489 pci_unmap_single(tnapi->tp->pdev,
6490 dma_unmap_addr(txb, mapping),
6494 while (txb->fragmented) {
6495 txb->fragmented = false;
6496 entry = NEXT_TX(entry);
6497 txb = &tnapi->tx_buffers[entry];
6500 for (i = 0; i <= last; i++) {
6501 const skb_frag_t *frag = &skb_shinfo(skb)->frags[i];
6503 entry = NEXT_TX(entry);
6504 txb = &tnapi->tx_buffers[entry];
6506 pci_unmap_page(tnapi->tp->pdev,
6507 dma_unmap_addr(txb, mapping),
6508 skb_frag_size(frag), PCI_DMA_TODEVICE);
6510 while (txb->fragmented) {
6511 txb->fragmented = false;
6512 entry = NEXT_TX(entry);
6513 txb = &tnapi->tx_buffers[entry];
6518 /* Workaround 4GB and 40-bit hardware DMA bugs. */
6519 static int tigon3_dma_hwbug_workaround(struct tg3_napi *tnapi,
6520 struct sk_buff **pskb,
6521 u32 *entry, u32 *budget,
6522 u32 base_flags, u32 mss, u32 vlan)
6524 struct tg3 *tp = tnapi->tp;
6525 struct sk_buff *new_skb, *skb = *pskb;
6526 dma_addr_t new_addr = 0;
6529 if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5701)
6530 new_skb = skb_copy(skb, GFP_ATOMIC);
6532 int more_headroom = 4 - ((unsigned long)skb->data & 3);
6534 new_skb = skb_copy_expand(skb,
6535 skb_headroom(skb) + more_headroom,
6536 skb_tailroom(skb), GFP_ATOMIC);
6542 /* New SKB is guaranteed to be linear. */
6543 new_addr = pci_map_single(tp->pdev, new_skb->data, new_skb->len,
6545 /* Make sure the mapping succeeded */
6546 if (pci_dma_mapping_error(tp->pdev, new_addr)) {
6547 dev_kfree_skb(new_skb);
6550 u32 save_entry = *entry;
6552 base_flags |= TXD_FLAG_END;
6554 tnapi->tx_buffers[*entry].skb = new_skb;
6555 dma_unmap_addr_set(&tnapi->tx_buffers[*entry],
6558 if (tg3_tx_frag_set(tnapi, entry, budget, new_addr,
6559 new_skb->len, base_flags,
6561 tg3_tx_skb_unmap(tnapi, save_entry, -1);
6562 dev_kfree_skb(new_skb);
6573 static netdev_tx_t tg3_start_xmit(struct sk_buff *, struct net_device *);
6575 /* Use GSO to workaround a rare TSO bug that may be triggered when the
6576 * TSO header is greater than 80 bytes.
6578 static int tg3_tso_bug(struct tg3 *tp, struct sk_buff *skb)
6580 struct sk_buff *segs, *nskb;
6581 u32 frag_cnt_est = skb_shinfo(skb)->gso_segs * 3;
6583 /* Estimate the number of fragments in the worst case */
6584 if (unlikely(tg3_tx_avail(&tp->napi[0]) <= frag_cnt_est)) {
6585 netif_stop_queue(tp->dev);
6587 /* netif_tx_stop_queue() must be done before checking
6588 * checking tx index in tg3_tx_avail() below, because in
6589 * tg3_tx(), we update tx index before checking for
6590 * netif_tx_queue_stopped().
6593 if (tg3_tx_avail(&tp->napi[0]) <= frag_cnt_est)
6594 return NETDEV_TX_BUSY;
6596 netif_wake_queue(tp->dev);
6599 segs = skb_gso_segment(skb, tp->dev->features & ~NETIF_F_TSO);
6601 goto tg3_tso_bug_end;
6607 tg3_start_xmit(nskb, tp->dev);
6613 return NETDEV_TX_OK;
6616 /* hard_start_xmit for devices that have the 4G bug and/or 40-bit bug and
6617 * support TG3_FLAG_HW_TSO_1 or firmware TSO only.
6619 static netdev_tx_t tg3_start_xmit(struct sk_buff *skb, struct net_device *dev)
6621 struct tg3 *tp = netdev_priv(dev);
6622 u32 len, entry, base_flags, mss, vlan = 0;
6624 int i = -1, would_hit_hwbug;
6626 struct tg3_napi *tnapi;
6627 struct netdev_queue *txq;
6630 txq = netdev_get_tx_queue(dev, skb_get_queue_mapping(skb));
6631 tnapi = &tp->napi[skb_get_queue_mapping(skb)];
6632 if (tg3_flag(tp, ENABLE_TSS))
6635 budget = tg3_tx_avail(tnapi);
6637 /* We are running in BH disabled context with netif_tx_lock
6638 * and TX reclaim runs via tp->napi.poll inside of a software
6639 * interrupt. Furthermore, IRQ processing runs lockless so we have
6640 * no IRQ context deadlocks to worry about either. Rejoice!
6642 if (unlikely(budget <= (skb_shinfo(skb)->nr_frags + 1))) {
6643 if (!netif_tx_queue_stopped(txq)) {
6644 netif_tx_stop_queue(txq);
6646 /* This is a hard error, log it. */
6648 "BUG! Tx Ring full when queue awake!\n");
6650 return NETDEV_TX_BUSY;
6653 entry = tnapi->tx_prod;
6655 if (skb->ip_summed == CHECKSUM_PARTIAL)
6656 base_flags |= TXD_FLAG_TCPUDP_CSUM;
6658 mss = skb_shinfo(skb)->gso_size;
6661 u32 tcp_opt_len, hdr_len;
6663 if (skb_header_cloned(skb) &&
6664 pskb_expand_head(skb, 0, 0, GFP_ATOMIC))
6668 tcp_opt_len = tcp_optlen(skb);
6670 if (skb_is_gso_v6(skb)) {
6671 hdr_len = skb_headlen(skb) - ETH_HLEN;
6675 ip_tcp_len = ip_hdrlen(skb) + sizeof(struct tcphdr);
6676 hdr_len = ip_tcp_len + tcp_opt_len;
6679 iph->tot_len = htons(mss + hdr_len);
6682 if (unlikely((ETH_HLEN + hdr_len) > 80) &&
6683 tg3_flag(tp, TSO_BUG))
6684 return tg3_tso_bug(tp, skb);
6686 base_flags |= (TXD_FLAG_CPU_PRE_DMA |
6687 TXD_FLAG_CPU_POST_DMA);
6689 if (tg3_flag(tp, HW_TSO_1) ||
6690 tg3_flag(tp, HW_TSO_2) ||
6691 tg3_flag(tp, HW_TSO_3)) {
6692 tcp_hdr(skb)->check = 0;
6693 base_flags &= ~TXD_FLAG_TCPUDP_CSUM;
6695 tcp_hdr(skb)->check = ~csum_tcpudp_magic(iph->saddr,
6700 if (tg3_flag(tp, HW_TSO_3)) {
6701 mss |= (hdr_len & 0xc) << 12;
6703 base_flags |= 0x00000010;
6704 base_flags |= (hdr_len & 0x3e0) << 5;
6705 } else if (tg3_flag(tp, HW_TSO_2))
6706 mss |= hdr_len << 9;
6707 else if (tg3_flag(tp, HW_TSO_1) ||
6708 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705) {
6709 if (tcp_opt_len || iph->ihl > 5) {
6712 tsflags = (iph->ihl - 5) + (tcp_opt_len >> 2);
6713 mss |= (tsflags << 11);
6716 if (tcp_opt_len || iph->ihl > 5) {
6719 tsflags = (iph->ihl - 5) + (tcp_opt_len >> 2);
6720 base_flags |= tsflags << 12;
6725 if (tg3_flag(tp, USE_JUMBO_BDFLAG) &&
6726 !mss && skb->len > VLAN_ETH_FRAME_LEN)
6727 base_flags |= TXD_FLAG_JMB_PKT;
6729 if (vlan_tx_tag_present(skb)) {
6730 base_flags |= TXD_FLAG_VLAN;
6731 vlan = vlan_tx_tag_get(skb);
6734 len = skb_headlen(skb);
6736 mapping = pci_map_single(tp->pdev, skb->data, len, PCI_DMA_TODEVICE);
6737 if (pci_dma_mapping_error(tp->pdev, mapping))
6741 tnapi->tx_buffers[entry].skb = skb;
6742 dma_unmap_addr_set(&tnapi->tx_buffers[entry], mapping, mapping);
6744 would_hit_hwbug = 0;
6746 if (tg3_flag(tp, 5701_DMA_BUG))
6747 would_hit_hwbug = 1;
6749 if (tg3_tx_frag_set(tnapi, &entry, &budget, mapping, len, base_flags |
6750 ((skb_shinfo(skb)->nr_frags == 0) ? TXD_FLAG_END : 0),
6752 would_hit_hwbug = 1;
6753 /* Now loop through additional data fragments, and queue them. */
6754 } else if (skb_shinfo(skb)->nr_frags > 0) {
6757 if (!tg3_flag(tp, HW_TSO_1) &&
6758 !tg3_flag(tp, HW_TSO_2) &&
6759 !tg3_flag(tp, HW_TSO_3))
6762 last = skb_shinfo(skb)->nr_frags - 1;
6763 for (i = 0; i <= last; i++) {
6764 skb_frag_t *frag = &skb_shinfo(skb)->frags[i];
6766 len = skb_frag_size(frag);
6767 mapping = skb_frag_dma_map(&tp->pdev->dev, frag, 0,
6768 len, DMA_TO_DEVICE);
6770 tnapi->tx_buffers[entry].skb = NULL;
6771 dma_unmap_addr_set(&tnapi->tx_buffers[entry], mapping,
6773 if (dma_mapping_error(&tp->pdev->dev, mapping))
6777 tg3_tx_frag_set(tnapi, &entry, &budget, mapping,
6779 ((i == last) ? TXD_FLAG_END : 0),
6781 would_hit_hwbug = 1;
6787 if (would_hit_hwbug) {
6788 tg3_tx_skb_unmap(tnapi, tnapi->tx_prod, i);
6790 /* If the workaround fails due to memory/mapping
6791 * failure, silently drop this packet.
6793 entry = tnapi->tx_prod;
6794 budget = tg3_tx_avail(tnapi);
6795 if (tigon3_dma_hwbug_workaround(tnapi, &skb, &entry, &budget,
6796 base_flags, mss, vlan))
6800 skb_tx_timestamp(skb);
6801 netdev_sent_queue(tp->dev, skb->len);
6803 /* Packets are ready, update Tx producer idx local and on card. */
6804 tw32_tx_mbox(tnapi->prodmbox, entry);
6806 tnapi->tx_prod = entry;
6807 if (unlikely(tg3_tx_avail(tnapi) <= (MAX_SKB_FRAGS + 1))) {
6808 netif_tx_stop_queue(txq);
6810 /* netif_tx_stop_queue() must be done before checking
6811 * checking tx index in tg3_tx_avail() below, because in
6812 * tg3_tx(), we update tx index before checking for
6813 * netif_tx_queue_stopped().
6816 if (tg3_tx_avail(tnapi) > TG3_TX_WAKEUP_THRESH(tnapi))
6817 netif_tx_wake_queue(txq);
6821 return NETDEV_TX_OK;
6824 tg3_tx_skb_unmap(tnapi, tnapi->tx_prod, --i);
6825 tnapi->tx_buffers[tnapi->tx_prod].skb = NULL;
6830 return NETDEV_TX_OK;
6833 static void tg3_mac_loopback(struct tg3 *tp, bool enable)
6836 tp->mac_mode &= ~(MAC_MODE_HALF_DUPLEX |
6837 MAC_MODE_PORT_MODE_MASK);
6839 tp->mac_mode |= MAC_MODE_PORT_INT_LPBACK;
6841 if (!tg3_flag(tp, 5705_PLUS))
6842 tp->mac_mode |= MAC_MODE_LINK_POLARITY;
6844 if (tp->phy_flags & TG3_PHYFLG_10_100_ONLY)
6845 tp->mac_mode |= MAC_MODE_PORT_MODE_MII;
6847 tp->mac_mode |= MAC_MODE_PORT_MODE_GMII;
6849 tp->mac_mode &= ~MAC_MODE_PORT_INT_LPBACK;
6851 if (tg3_flag(tp, 5705_PLUS) ||
6852 (tp->phy_flags & TG3_PHYFLG_PHY_SERDES) ||
6853 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700)
6854 tp->mac_mode &= ~MAC_MODE_LINK_POLARITY;
6857 tw32(MAC_MODE, tp->mac_mode);
6861 static int tg3_phy_lpbk_set(struct tg3 *tp, u32 speed, bool extlpbk)
6863 u32 val, bmcr, mac_mode, ptest = 0;
6865 tg3_phy_toggle_apd(tp, false);
6866 tg3_phy_toggle_automdix(tp, 0);
6868 if (extlpbk && tg3_phy_set_extloopbk(tp))
6871 bmcr = BMCR_FULLDPLX;
6876 bmcr |= BMCR_SPEED100;
6880 if (tp->phy_flags & TG3_PHYFLG_IS_FET) {
6882 bmcr |= BMCR_SPEED100;
6885 bmcr |= BMCR_SPEED1000;
6890 if (!(tp->phy_flags & TG3_PHYFLG_IS_FET)) {
6891 tg3_readphy(tp, MII_CTRL1000, &val);
6892 val |= CTL1000_AS_MASTER |
6893 CTL1000_ENABLE_MASTER;
6894 tg3_writephy(tp, MII_CTRL1000, val);
6896 ptest = MII_TG3_FET_PTEST_TRIM_SEL |
6897 MII_TG3_FET_PTEST_TRIM_2;
6898 tg3_writephy(tp, MII_TG3_FET_PTEST, ptest);
6901 bmcr |= BMCR_LOOPBACK;
6903 tg3_writephy(tp, MII_BMCR, bmcr);
6905 /* The write needs to be flushed for the FETs */
6906 if (tp->phy_flags & TG3_PHYFLG_IS_FET)
6907 tg3_readphy(tp, MII_BMCR, &bmcr);
6911 if ((tp->phy_flags & TG3_PHYFLG_IS_FET) &&
6912 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785) {
6913 tg3_writephy(tp, MII_TG3_FET_PTEST, ptest |
6914 MII_TG3_FET_PTEST_FRC_TX_LINK |
6915 MII_TG3_FET_PTEST_FRC_TX_LOCK);
6917 /* The write needs to be flushed for the AC131 */
6918 tg3_readphy(tp, MII_TG3_FET_PTEST, &val);
6921 /* Reset to prevent losing 1st rx packet intermittently */
6922 if ((tp->phy_flags & TG3_PHYFLG_MII_SERDES) &&
6923 tg3_flag(tp, 5780_CLASS)) {
6924 tw32_f(MAC_RX_MODE, RX_MODE_RESET);
6926 tw32_f(MAC_RX_MODE, tp->rx_mode);
6929 mac_mode = tp->mac_mode &
6930 ~(MAC_MODE_PORT_MODE_MASK | MAC_MODE_HALF_DUPLEX);
6931 if (speed == SPEED_1000)
6932 mac_mode |= MAC_MODE_PORT_MODE_GMII;
6934 mac_mode |= MAC_MODE_PORT_MODE_MII;
6936 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700) {
6937 u32 masked_phy_id = tp->phy_id & TG3_PHY_ID_MASK;
6939 if (masked_phy_id == TG3_PHY_ID_BCM5401)
6940 mac_mode &= ~MAC_MODE_LINK_POLARITY;
6941 else if (masked_phy_id == TG3_PHY_ID_BCM5411)
6942 mac_mode |= MAC_MODE_LINK_POLARITY;
6944 tg3_writephy(tp, MII_TG3_EXT_CTRL,
6945 MII_TG3_EXT_CTRL_LNK3_LED_MODE);
6948 tw32(MAC_MODE, mac_mode);
6954 static void tg3_set_loopback(struct net_device *dev, netdev_features_t features)
6956 struct tg3 *tp = netdev_priv(dev);
6958 if (features & NETIF_F_LOOPBACK) {
6959 if (tp->mac_mode & MAC_MODE_PORT_INT_LPBACK)
6962 spin_lock_bh(&tp->lock);
6963 tg3_mac_loopback(tp, true);
6964 netif_carrier_on(tp->dev);
6965 spin_unlock_bh(&tp->lock);
6966 netdev_info(dev, "Internal MAC loopback mode enabled.\n");
6968 if (!(tp->mac_mode & MAC_MODE_PORT_INT_LPBACK))
6971 spin_lock_bh(&tp->lock);
6972 tg3_mac_loopback(tp, false);
6973 /* Force link status check */
6974 tg3_setup_phy(tp, 1);
6975 spin_unlock_bh(&tp->lock);
6976 netdev_info(dev, "Internal MAC loopback mode disabled.\n");
6980 static netdev_features_t tg3_fix_features(struct net_device *dev,
6981 netdev_features_t features)
6983 struct tg3 *tp = netdev_priv(dev);
6985 if (dev->mtu > ETH_DATA_LEN && tg3_flag(tp, 5780_CLASS))
6986 features &= ~NETIF_F_ALL_TSO;
6991 static int tg3_set_features(struct net_device *dev, netdev_features_t features)
6993 netdev_features_t changed = dev->features ^ features;
6995 if ((changed & NETIF_F_LOOPBACK) && netif_running(dev))
6996 tg3_set_loopback(dev, features);
7001 static inline void tg3_set_mtu(struct net_device *dev, struct tg3 *tp,
7006 if (new_mtu > ETH_DATA_LEN) {
7007 if (tg3_flag(tp, 5780_CLASS)) {
7008 netdev_update_features(dev);
7009 tg3_flag_clear(tp, TSO_CAPABLE);
7011 tg3_flag_set(tp, JUMBO_RING_ENABLE);
7014 if (tg3_flag(tp, 5780_CLASS)) {
7015 tg3_flag_set(tp, TSO_CAPABLE);
7016 netdev_update_features(dev);
7018 tg3_flag_clear(tp, JUMBO_RING_ENABLE);
7022 static int tg3_change_mtu(struct net_device *dev, int new_mtu)
7024 struct tg3 *tp = netdev_priv(dev);
7027 if (new_mtu < TG3_MIN_MTU || new_mtu > TG3_MAX_MTU(tp))
7030 if (!netif_running(dev)) {
7031 /* We'll just catch it later when the
7034 tg3_set_mtu(dev, tp, new_mtu);
7042 tg3_full_lock(tp, 1);
7044 tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
7046 tg3_set_mtu(dev, tp, new_mtu);
7048 err = tg3_restart_hw(tp, 0);
7051 tg3_netif_start(tp);
7053 tg3_full_unlock(tp);
7061 static void tg3_rx_prodring_free(struct tg3 *tp,
7062 struct tg3_rx_prodring_set *tpr)
7066 if (tpr != &tp->napi[0].prodring) {
7067 for (i = tpr->rx_std_cons_idx; i != tpr->rx_std_prod_idx;
7068 i = (i + 1) & tp->rx_std_ring_mask)
7069 tg3_rx_data_free(tp, &tpr->rx_std_buffers[i],
7072 if (tg3_flag(tp, JUMBO_CAPABLE)) {
7073 for (i = tpr->rx_jmb_cons_idx;
7074 i != tpr->rx_jmb_prod_idx;
7075 i = (i + 1) & tp->rx_jmb_ring_mask) {
7076 tg3_rx_data_free(tp, &tpr->rx_jmb_buffers[i],
7084 for (i = 0; i <= tp->rx_std_ring_mask; i++)
7085 tg3_rx_data_free(tp, &tpr->rx_std_buffers[i],
7088 if (tg3_flag(tp, JUMBO_CAPABLE) && !tg3_flag(tp, 5780_CLASS)) {
7089 for (i = 0; i <= tp->rx_jmb_ring_mask; i++)
7090 tg3_rx_data_free(tp, &tpr->rx_jmb_buffers[i],
7095 /* Initialize rx rings for packet processing.
7097 * The chip has been shut down and the driver detached from
7098 * the networking, so no interrupts or new tx packets will
7099 * end up in the driver. tp->{tx,}lock are held and thus
7102 static int tg3_rx_prodring_alloc(struct tg3 *tp,
7103 struct tg3_rx_prodring_set *tpr)
7105 u32 i, rx_pkt_dma_sz;
7107 tpr->rx_std_cons_idx = 0;
7108 tpr->rx_std_prod_idx = 0;
7109 tpr->rx_jmb_cons_idx = 0;
7110 tpr->rx_jmb_prod_idx = 0;
7112 if (tpr != &tp->napi[0].prodring) {
7113 memset(&tpr->rx_std_buffers[0], 0,
7114 TG3_RX_STD_BUFF_RING_SIZE(tp));
7115 if (tpr->rx_jmb_buffers)
7116 memset(&tpr->rx_jmb_buffers[0], 0,
7117 TG3_RX_JMB_BUFF_RING_SIZE(tp));
7121 /* Zero out all descriptors. */
7122 memset(tpr->rx_std, 0, TG3_RX_STD_RING_BYTES(tp));
7124 rx_pkt_dma_sz = TG3_RX_STD_DMA_SZ;
7125 if (tg3_flag(tp, 5780_CLASS) &&
7126 tp->dev->mtu > ETH_DATA_LEN)
7127 rx_pkt_dma_sz = TG3_RX_JMB_DMA_SZ;
7128 tp->rx_pkt_map_sz = TG3_RX_DMA_TO_MAP_SZ(rx_pkt_dma_sz);
7130 /* Initialize invariants of the rings, we only set this
7131 * stuff once. This works because the card does not
7132 * write into the rx buffer posting rings.
7134 for (i = 0; i <= tp->rx_std_ring_mask; i++) {
7135 struct tg3_rx_buffer_desc *rxd;
7137 rxd = &tpr->rx_std[i];
7138 rxd->idx_len = rx_pkt_dma_sz << RXD_LEN_SHIFT;
7139 rxd->type_flags = (RXD_FLAG_END << RXD_FLAGS_SHIFT);
7140 rxd->opaque = (RXD_OPAQUE_RING_STD |
7141 (i << RXD_OPAQUE_INDEX_SHIFT));
7144 /* Now allocate fresh SKBs for each rx ring. */
7145 for (i = 0; i < tp->rx_pending; i++) {
7146 if (tg3_alloc_rx_data(tp, tpr, RXD_OPAQUE_RING_STD, i) < 0) {
7147 netdev_warn(tp->dev,
7148 "Using a smaller RX standard ring. Only "
7149 "%d out of %d buffers were allocated "
7150 "successfully\n", i, tp->rx_pending);
7158 if (!tg3_flag(tp, JUMBO_CAPABLE) || tg3_flag(tp, 5780_CLASS))
7161 memset(tpr->rx_jmb, 0, TG3_RX_JMB_RING_BYTES(tp));
7163 if (!tg3_flag(tp, JUMBO_RING_ENABLE))
7166 for (i = 0; i <= tp->rx_jmb_ring_mask; i++) {
7167 struct tg3_rx_buffer_desc *rxd;
7169 rxd = &tpr->rx_jmb[i].std;
7170 rxd->idx_len = TG3_RX_JMB_DMA_SZ << RXD_LEN_SHIFT;
7171 rxd->type_flags = (RXD_FLAG_END << RXD_FLAGS_SHIFT) |
7173 rxd->opaque = (RXD_OPAQUE_RING_JUMBO |
7174 (i << RXD_OPAQUE_INDEX_SHIFT));
7177 for (i = 0; i < tp->rx_jumbo_pending; i++) {
7178 if (tg3_alloc_rx_data(tp, tpr, RXD_OPAQUE_RING_JUMBO, i) < 0) {
7179 netdev_warn(tp->dev,
7180 "Using a smaller RX jumbo ring. Only %d "
7181 "out of %d buffers were allocated "
7182 "successfully\n", i, tp->rx_jumbo_pending);
7185 tp->rx_jumbo_pending = i;
7194 tg3_rx_prodring_free(tp, tpr);
7198 static void tg3_rx_prodring_fini(struct tg3 *tp,
7199 struct tg3_rx_prodring_set *tpr)
7201 kfree(tpr->rx_std_buffers);
7202 tpr->rx_std_buffers = NULL;
7203 kfree(tpr->rx_jmb_buffers);
7204 tpr->rx_jmb_buffers = NULL;
7206 dma_free_coherent(&tp->pdev->dev, TG3_RX_STD_RING_BYTES(tp),
7207 tpr->rx_std, tpr->rx_std_mapping);
7211 dma_free_coherent(&tp->pdev->dev, TG3_RX_JMB_RING_BYTES(tp),
7212 tpr->rx_jmb, tpr->rx_jmb_mapping);
7217 static int tg3_rx_prodring_init(struct tg3 *tp,
7218 struct tg3_rx_prodring_set *tpr)
7220 tpr->rx_std_buffers = kzalloc(TG3_RX_STD_BUFF_RING_SIZE(tp),
7222 if (!tpr->rx_std_buffers)
7225 tpr->rx_std = dma_alloc_coherent(&tp->pdev->dev,
7226 TG3_RX_STD_RING_BYTES(tp),
7227 &tpr->rx_std_mapping,
7232 if (tg3_flag(tp, JUMBO_CAPABLE) && !tg3_flag(tp, 5780_CLASS)) {
7233 tpr->rx_jmb_buffers = kzalloc(TG3_RX_JMB_BUFF_RING_SIZE(tp),
7235 if (!tpr->rx_jmb_buffers)
7238 tpr->rx_jmb = dma_alloc_coherent(&tp->pdev->dev,
7239 TG3_RX_JMB_RING_BYTES(tp),
7240 &tpr->rx_jmb_mapping,
7249 tg3_rx_prodring_fini(tp, tpr);
7253 /* Free up pending packets in all rx/tx rings.
7255 * The chip has been shut down and the driver detached from
7256 * the networking, so no interrupts or new tx packets will
7257 * end up in the driver. tp->{tx,}lock is not held and we are not
7258 * in an interrupt context and thus may sleep.
7260 static void tg3_free_rings(struct tg3 *tp)
7264 for (j = 0; j < tp->irq_cnt; j++) {
7265 struct tg3_napi *tnapi = &tp->napi[j];
7267 tg3_rx_prodring_free(tp, &tnapi->prodring);
7269 if (!tnapi->tx_buffers)
7272 for (i = 0; i < TG3_TX_RING_SIZE; i++) {
7273 struct sk_buff *skb = tnapi->tx_buffers[i].skb;
7278 tg3_tx_skb_unmap(tnapi, i,
7279 skb_shinfo(skb)->nr_frags - 1);
7281 dev_kfree_skb_any(skb);
7284 netdev_reset_queue(tp->dev);
7287 /* Initialize tx/rx rings for packet processing.
7289 * The chip has been shut down and the driver detached from
7290 * the networking, so no interrupts or new tx packets will
7291 * end up in the driver. tp->{tx,}lock are held and thus
7294 static int tg3_init_rings(struct tg3 *tp)
7298 /* Free up all the SKBs. */
7301 for (i = 0; i < tp->irq_cnt; i++) {
7302 struct tg3_napi *tnapi = &tp->napi[i];
7304 tnapi->last_tag = 0;
7305 tnapi->last_irq_tag = 0;
7306 tnapi->hw_status->status = 0;
7307 tnapi->hw_status->status_tag = 0;
7308 memset(tnapi->hw_status, 0, TG3_HW_STATUS_SIZE);
7313 memset(tnapi->tx_ring, 0, TG3_TX_RING_BYTES);
7315 tnapi->rx_rcb_ptr = 0;
7317 memset(tnapi->rx_rcb, 0, TG3_RX_RCB_RING_BYTES(tp));
7319 if (tg3_rx_prodring_alloc(tp, &tnapi->prodring)) {
7329 * Must not be invoked with interrupt sources disabled and
7330 * the hardware shutdown down.
7332 static void tg3_free_consistent(struct tg3 *tp)
7336 for (i = 0; i < tp->irq_cnt; i++) {
7337 struct tg3_napi *tnapi = &tp->napi[i];
7339 if (tnapi->tx_ring) {
7340 dma_free_coherent(&tp->pdev->dev, TG3_TX_RING_BYTES,
7341 tnapi->tx_ring, tnapi->tx_desc_mapping);
7342 tnapi->tx_ring = NULL;
7345 kfree(tnapi->tx_buffers);
7346 tnapi->tx_buffers = NULL;
7348 if (tnapi->rx_rcb) {
7349 dma_free_coherent(&tp->pdev->dev,
7350 TG3_RX_RCB_RING_BYTES(tp),
7352 tnapi->rx_rcb_mapping);
7353 tnapi->rx_rcb = NULL;
7356 tg3_rx_prodring_fini(tp, &tnapi->prodring);
7358 if (tnapi->hw_status) {
7359 dma_free_coherent(&tp->pdev->dev, TG3_HW_STATUS_SIZE,
7361 tnapi->status_mapping);
7362 tnapi->hw_status = NULL;
7367 dma_free_coherent(&tp->pdev->dev, sizeof(struct tg3_hw_stats),
7368 tp->hw_stats, tp->stats_mapping);
7369 tp->hw_stats = NULL;
7374 * Must not be invoked with interrupt sources disabled and
7375 * the hardware shutdown down. Can sleep.
7377 static int tg3_alloc_consistent(struct tg3 *tp)
7381 tp->hw_stats = dma_alloc_coherent(&tp->pdev->dev,
7382 sizeof(struct tg3_hw_stats),
7388 memset(tp->hw_stats, 0, sizeof(struct tg3_hw_stats));
7390 for (i = 0; i < tp->irq_cnt; i++) {
7391 struct tg3_napi *tnapi = &tp->napi[i];
7392 struct tg3_hw_status *sblk;
7394 tnapi->hw_status = dma_alloc_coherent(&tp->pdev->dev,
7396 &tnapi->status_mapping,
7398 if (!tnapi->hw_status)
7401 memset(tnapi->hw_status, 0, TG3_HW_STATUS_SIZE);
7402 sblk = tnapi->hw_status;
7404 if (tg3_rx_prodring_init(tp, &tnapi->prodring))
7407 /* If multivector TSS is enabled, vector 0 does not handle
7408 * tx interrupts. Don't allocate any resources for it.
7410 if ((!i && !tg3_flag(tp, ENABLE_TSS)) ||
7411 (i && tg3_flag(tp, ENABLE_TSS))) {
7412 tnapi->tx_buffers = kzalloc(
7413 sizeof(struct tg3_tx_ring_info) *
7414 TG3_TX_RING_SIZE, GFP_KERNEL);
7415 if (!tnapi->tx_buffers)
7418 tnapi->tx_ring = dma_alloc_coherent(&tp->pdev->dev,
7420 &tnapi->tx_desc_mapping,
7422 if (!tnapi->tx_ring)
7427 * When RSS is enabled, the status block format changes
7428 * slightly. The "rx_jumbo_consumer", "reserved",
7429 * and "rx_mini_consumer" members get mapped to the
7430 * other three rx return ring producer indexes.
7434 tnapi->rx_rcb_prod_idx = &sblk->idx[0].rx_producer;
7437 tnapi->rx_rcb_prod_idx = &sblk->rx_jumbo_consumer;
7440 tnapi->rx_rcb_prod_idx = &sblk->reserved;
7443 tnapi->rx_rcb_prod_idx = &sblk->rx_mini_consumer;
7448 * If multivector RSS is enabled, vector 0 does not handle
7449 * rx or tx interrupts. Don't allocate any resources for it.
7451 if (!i && tg3_flag(tp, ENABLE_RSS))
7454 tnapi->rx_rcb = dma_alloc_coherent(&tp->pdev->dev,
7455 TG3_RX_RCB_RING_BYTES(tp),
7456 &tnapi->rx_rcb_mapping,
7461 memset(tnapi->rx_rcb, 0, TG3_RX_RCB_RING_BYTES(tp));
7467 tg3_free_consistent(tp);
7471 #define MAX_WAIT_CNT 1000
7473 /* To stop a block, clear the enable bit and poll till it
7474 * clears. tp->lock is held.
7476 static int tg3_stop_block(struct tg3 *tp, unsigned long ofs, u32 enable_bit, int silent)
7481 if (tg3_flag(tp, 5705_PLUS)) {
7488 /* We can't enable/disable these bits of the
7489 * 5705/5750, just say success.
7502 for (i = 0; i < MAX_WAIT_CNT; i++) {
7505 if ((val & enable_bit) == 0)
7509 if (i == MAX_WAIT_CNT && !silent) {
7510 dev_err(&tp->pdev->dev,
7511 "tg3_stop_block timed out, ofs=%lx enable_bit=%x\n",
7519 /* tp->lock is held. */
7520 static int tg3_abort_hw(struct tg3 *tp, int silent)
7524 tg3_disable_ints(tp);
7526 tp->rx_mode &= ~RX_MODE_ENABLE;
7527 tw32_f(MAC_RX_MODE, tp->rx_mode);
7530 err = tg3_stop_block(tp, RCVBDI_MODE, RCVBDI_MODE_ENABLE, silent);
7531 err |= tg3_stop_block(tp, RCVLPC_MODE, RCVLPC_MODE_ENABLE, silent);
7532 err |= tg3_stop_block(tp, RCVLSC_MODE, RCVLSC_MODE_ENABLE, silent);
7533 err |= tg3_stop_block(tp, RCVDBDI_MODE, RCVDBDI_MODE_ENABLE, silent);
7534 err |= tg3_stop_block(tp, RCVDCC_MODE, RCVDCC_MODE_ENABLE, silent);
7535 err |= tg3_stop_block(tp, RCVCC_MODE, RCVCC_MODE_ENABLE, silent);
7537 err |= tg3_stop_block(tp, SNDBDS_MODE, SNDBDS_MODE_ENABLE, silent);
7538 err |= tg3_stop_block(tp, SNDBDI_MODE, SNDBDI_MODE_ENABLE, silent);
7539 err |= tg3_stop_block(tp, SNDDATAI_MODE, SNDDATAI_MODE_ENABLE, silent);
7540 err |= tg3_stop_block(tp, RDMAC_MODE, RDMAC_MODE_ENABLE, silent);
7541 err |= tg3_stop_block(tp, SNDDATAC_MODE, SNDDATAC_MODE_ENABLE, silent);
7542 err |= tg3_stop_block(tp, DMAC_MODE, DMAC_MODE_ENABLE, silent);
7543 err |= tg3_stop_block(tp, SNDBDC_MODE, SNDBDC_MODE_ENABLE, silent);
7545 tp->mac_mode &= ~MAC_MODE_TDE_ENABLE;
7546 tw32_f(MAC_MODE, tp->mac_mode);
7549 tp->tx_mode &= ~TX_MODE_ENABLE;
7550 tw32_f(MAC_TX_MODE, tp->tx_mode);
7552 for (i = 0; i < MAX_WAIT_CNT; i++) {
7554 if (!(tr32(MAC_TX_MODE) & TX_MODE_ENABLE))
7557 if (i >= MAX_WAIT_CNT) {
7558 dev_err(&tp->pdev->dev,
7559 "%s timed out, TX_MODE_ENABLE will not clear "
7560 "MAC_TX_MODE=%08x\n", __func__, tr32(MAC_TX_MODE));
7564 err |= tg3_stop_block(tp, HOSTCC_MODE, HOSTCC_MODE_ENABLE, silent);
7565 err |= tg3_stop_block(tp, WDMAC_MODE, WDMAC_MODE_ENABLE, silent);
7566 err |= tg3_stop_block(tp, MBFREE_MODE, MBFREE_MODE_ENABLE, silent);
7568 tw32(FTQ_RESET, 0xffffffff);
7569 tw32(FTQ_RESET, 0x00000000);
7571 err |= tg3_stop_block(tp, BUFMGR_MODE, BUFMGR_MODE_ENABLE, silent);
7572 err |= tg3_stop_block(tp, MEMARB_MODE, MEMARB_MODE_ENABLE, silent);
7574 for (i = 0; i < tp->irq_cnt; i++) {
7575 struct tg3_napi *tnapi = &tp->napi[i];
7576 if (tnapi->hw_status)
7577 memset(tnapi->hw_status, 0, TG3_HW_STATUS_SIZE);
7583 /* Save PCI command register before chip reset */
7584 static void tg3_save_pci_state(struct tg3 *tp)
7586 pci_read_config_word(tp->pdev, PCI_COMMAND, &tp->pci_cmd);
7589 /* Restore PCI state after chip reset */
7590 static void tg3_restore_pci_state(struct tg3 *tp)
7594 /* Re-enable indirect register accesses. */
7595 pci_write_config_dword(tp->pdev, TG3PCI_MISC_HOST_CTRL,
7596 tp->misc_host_ctrl);
7598 /* Set MAX PCI retry to zero. */
7599 val = (PCISTATE_ROM_ENABLE | PCISTATE_ROM_RETRY_ENABLE);
7600 if (tp->pci_chip_rev_id == CHIPREV_ID_5704_A0 &&
7601 tg3_flag(tp, PCIX_MODE))
7602 val |= PCISTATE_RETRY_SAME_DMA;
7603 /* Allow reads and writes to the APE register and memory space. */
7604 if (tg3_flag(tp, ENABLE_APE))
7605 val |= PCISTATE_ALLOW_APE_CTLSPC_WR |
7606 PCISTATE_ALLOW_APE_SHMEM_WR |
7607 PCISTATE_ALLOW_APE_PSPACE_WR;
7608 pci_write_config_dword(tp->pdev, TG3PCI_PCISTATE, val);
7610 pci_write_config_word(tp->pdev, PCI_COMMAND, tp->pci_cmd);
7612 if (!tg3_flag(tp, PCI_EXPRESS)) {
7613 pci_write_config_byte(tp->pdev, PCI_CACHE_LINE_SIZE,
7614 tp->pci_cacheline_sz);
7615 pci_write_config_byte(tp->pdev, PCI_LATENCY_TIMER,
7619 /* Make sure PCI-X relaxed ordering bit is clear. */
7620 if (tg3_flag(tp, PCIX_MODE)) {
7623 pci_read_config_word(tp->pdev, tp->pcix_cap + PCI_X_CMD,
7625 pcix_cmd &= ~PCI_X_CMD_ERO;
7626 pci_write_config_word(tp->pdev, tp->pcix_cap + PCI_X_CMD,
7630 if (tg3_flag(tp, 5780_CLASS)) {
7632 /* Chip reset on 5780 will reset MSI enable bit,
7633 * so need to restore it.
7635 if (tg3_flag(tp, USING_MSI)) {
7638 pci_read_config_word(tp->pdev,
7639 tp->msi_cap + PCI_MSI_FLAGS,
7641 pci_write_config_word(tp->pdev,
7642 tp->msi_cap + PCI_MSI_FLAGS,
7643 ctrl | PCI_MSI_FLAGS_ENABLE);
7644 val = tr32(MSGINT_MODE);
7645 tw32(MSGINT_MODE, val | MSGINT_MODE_ENABLE);
7650 /* tp->lock is held. */
7651 static int tg3_chip_reset(struct tg3 *tp)
7654 void (*write_op)(struct tg3 *, u32, u32);
7659 tg3_ape_lock(tp, TG3_APE_LOCK_GRC);
7661 /* No matching tg3_nvram_unlock() after this because
7662 * chip reset below will undo the nvram lock.
7664 tp->nvram_lock_cnt = 0;
7666 /* GRC_MISC_CFG core clock reset will clear the memory
7667 * enable bit in PCI register 4 and the MSI enable bit
7668 * on some chips, so we save relevant registers here.
7670 tg3_save_pci_state(tp);
7672 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5752 ||
7673 tg3_flag(tp, 5755_PLUS))
7674 tw32(GRC_FASTBOOT_PC, 0);
7677 * We must avoid the readl() that normally takes place.
7678 * It locks machines, causes machine checks, and other
7679 * fun things. So, temporarily disable the 5701
7680 * hardware workaround, while we do the reset.
7682 write_op = tp->write32;
7683 if (write_op == tg3_write_flush_reg32)
7684 tp->write32 = tg3_write32;
7686 /* Prevent the irq handler from reading or writing PCI registers
7687 * during chip reset when the memory enable bit in the PCI command
7688 * register may be cleared. The chip does not generate interrupt
7689 * at this time, but the irq handler may still be called due to irq
7690 * sharing or irqpoll.
7692 tg3_flag_set(tp, CHIP_RESETTING);
7693 for (i = 0; i < tp->irq_cnt; i++) {
7694 struct tg3_napi *tnapi = &tp->napi[i];
7695 if (tnapi->hw_status) {
7696 tnapi->hw_status->status = 0;
7697 tnapi->hw_status->status_tag = 0;
7699 tnapi->last_tag = 0;
7700 tnapi->last_irq_tag = 0;
7704 for (i = 0; i < tp->irq_cnt; i++)
7705 synchronize_irq(tp->napi[i].irq_vec);
7707 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57780) {
7708 val = tr32(TG3_PCIE_LNKCTL) & ~TG3_PCIE_LNKCTL_L1_PLL_PD_EN;
7709 tw32(TG3_PCIE_LNKCTL, val | TG3_PCIE_LNKCTL_L1_PLL_PD_DIS);
7713 val = GRC_MISC_CFG_CORECLK_RESET;
7715 if (tg3_flag(tp, PCI_EXPRESS)) {
7716 /* Force PCIe 1.0a mode */
7717 if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5785 &&
7718 !tg3_flag(tp, 57765_PLUS) &&
7719 tr32(TG3_PCIE_PHY_TSTCTL) ==
7720 (TG3_PCIE_PHY_TSTCTL_PCIE10 | TG3_PCIE_PHY_TSTCTL_PSCRAM))
7721 tw32(TG3_PCIE_PHY_TSTCTL, TG3_PCIE_PHY_TSTCTL_PSCRAM);
7723 if (tp->pci_chip_rev_id != CHIPREV_ID_5750_A0) {
7724 tw32(GRC_MISC_CFG, (1 << 29));
7729 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
7730 tw32(VCPU_STATUS, tr32(VCPU_STATUS) | VCPU_STATUS_DRV_RESET);
7731 tw32(GRC_VCPU_EXT_CTRL,
7732 tr32(GRC_VCPU_EXT_CTRL) & ~GRC_VCPU_EXT_CTRL_HALT_CPU);
7735 /* Manage gphy power for all CPMU absent PCIe devices. */
7736 if (tg3_flag(tp, 5705_PLUS) && !tg3_flag(tp, CPMU_PRESENT))
7737 val |= GRC_MISC_CFG_KEEP_GPHY_POWER;
7739 tw32(GRC_MISC_CFG, val);
7741 /* restore 5701 hardware bug workaround write method */
7742 tp->write32 = write_op;
7744 /* Unfortunately, we have to delay before the PCI read back.
7745 * Some 575X chips even will not respond to a PCI cfg access
7746 * when the reset command is given to the chip.
7748 * How do these hardware designers expect things to work
7749 * properly if the PCI write is posted for a long period
7750 * of time? It is always necessary to have some method by
7751 * which a register read back can occur to push the write
7752 * out which does the reset.
7754 * For most tg3 variants the trick below was working.
7759 /* Flush PCI posted writes. The normal MMIO registers
7760 * are inaccessible at this time so this is the only
7761 * way to make this reliably (actually, this is no longer
7762 * the case, see above). I tried to use indirect
7763 * register read/write but this upset some 5701 variants.
7765 pci_read_config_dword(tp->pdev, PCI_COMMAND, &val);
7769 if (tg3_flag(tp, PCI_EXPRESS) && pci_pcie_cap(tp->pdev)) {
7772 if (tp->pci_chip_rev_id == CHIPREV_ID_5750_A0) {
7776 /* Wait for link training to complete. */
7777 for (i = 0; i < 5000; i++)
7780 pci_read_config_dword(tp->pdev, 0xc4, &cfg_val);
7781 pci_write_config_dword(tp->pdev, 0xc4,
7782 cfg_val | (1 << 15));
7785 /* Clear the "no snoop" and "relaxed ordering" bits. */
7786 pci_read_config_word(tp->pdev,
7787 pci_pcie_cap(tp->pdev) + PCI_EXP_DEVCTL,
7789 val16 &= ~(PCI_EXP_DEVCTL_RELAX_EN |
7790 PCI_EXP_DEVCTL_NOSNOOP_EN);
7792 * Older PCIe devices only support the 128 byte
7793 * MPS setting. Enforce the restriction.
7795 if (!tg3_flag(tp, CPMU_PRESENT))
7796 val16 &= ~PCI_EXP_DEVCTL_PAYLOAD;
7797 pci_write_config_word(tp->pdev,
7798 pci_pcie_cap(tp->pdev) + PCI_EXP_DEVCTL,
7801 /* Clear error status */
7802 pci_write_config_word(tp->pdev,
7803 pci_pcie_cap(tp->pdev) + PCI_EXP_DEVSTA,
7804 PCI_EXP_DEVSTA_CED |
7805 PCI_EXP_DEVSTA_NFED |
7806 PCI_EXP_DEVSTA_FED |
7807 PCI_EXP_DEVSTA_URD);
7810 tg3_restore_pci_state(tp);
7812 tg3_flag_clear(tp, CHIP_RESETTING);
7813 tg3_flag_clear(tp, ERROR_PROCESSED);
7816 if (tg3_flag(tp, 5780_CLASS))
7817 val = tr32(MEMARB_MODE);
7818 tw32(MEMARB_MODE, val | MEMARB_MODE_ENABLE);
7820 if (tp->pci_chip_rev_id == CHIPREV_ID_5750_A3) {
7822 tw32(0x5000, 0x400);
7825 tw32(GRC_MODE, tp->grc_mode);
7827 if (tp->pci_chip_rev_id == CHIPREV_ID_5705_A0) {
7830 tw32(0xc4, val | (1 << 15));
7833 if ((tp->nic_sram_data_cfg & NIC_SRAM_DATA_CFG_MINI_PCI) != 0 &&
7834 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705) {
7835 tp->pci_clock_ctrl |= CLOCK_CTRL_CLKRUN_OENABLE;
7836 if (tp->pci_chip_rev_id == CHIPREV_ID_5705_A0)
7837 tp->pci_clock_ctrl |= CLOCK_CTRL_FORCE_CLKRUN;
7838 tw32(TG3PCI_CLOCK_CTRL, tp->pci_clock_ctrl);
7841 if (tp->phy_flags & TG3_PHYFLG_PHY_SERDES) {
7842 tp->mac_mode = MAC_MODE_PORT_MODE_TBI;
7844 } else if (tp->phy_flags & TG3_PHYFLG_MII_SERDES) {
7845 tp->mac_mode = MAC_MODE_PORT_MODE_GMII;
7850 tw32_f(MAC_MODE, val);
7853 tg3_ape_unlock(tp, TG3_APE_LOCK_GRC);
7855 err = tg3_poll_fw(tp);
7861 if (tg3_flag(tp, PCI_EXPRESS) &&
7862 tp->pci_chip_rev_id != CHIPREV_ID_5750_A0 &&
7863 GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5785 &&
7864 !tg3_flag(tp, 57765_PLUS)) {
7867 tw32(0x7c00, val | (1 << 25));
7870 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5720) {
7871 val = tr32(TG3_CPMU_CLCK_ORIDE);
7872 tw32(TG3_CPMU_CLCK_ORIDE, val & ~CPMU_CLCK_ORIDE_MAC_ORIDE_EN);
7875 /* Reprobe ASF enable state. */
7876 tg3_flag_clear(tp, ENABLE_ASF);
7877 tg3_flag_clear(tp, ASF_NEW_HANDSHAKE);
7878 tg3_read_mem(tp, NIC_SRAM_DATA_SIG, &val);
7879 if (val == NIC_SRAM_DATA_SIG_MAGIC) {
7882 tg3_read_mem(tp, NIC_SRAM_DATA_CFG, &nic_cfg);
7883 if (nic_cfg & NIC_SRAM_DATA_CFG_ASF_ENABLE) {
7884 tg3_flag_set(tp, ENABLE_ASF);
7885 tp->last_event_jiffies = jiffies;
7886 if (tg3_flag(tp, 5750_PLUS))
7887 tg3_flag_set(tp, ASF_NEW_HANDSHAKE);
7894 static struct rtnl_link_stats64 *tg3_get_stats64(struct net_device *,
7895 struct rtnl_link_stats64 *);
7896 static struct tg3_ethtool_stats *tg3_get_estats(struct tg3 *,
7897 struct tg3_ethtool_stats *);
7899 /* tp->lock is held. */
7900 static int tg3_halt(struct tg3 *tp, int kind, int silent)
7906 tg3_write_sig_pre_reset(tp, kind);
7908 tg3_abort_hw(tp, silent);
7909 err = tg3_chip_reset(tp);
7911 __tg3_set_mac_addr(tp, 0);
7913 tg3_write_sig_legacy(tp, kind);
7914 tg3_write_sig_post_reset(tp, kind);
7917 /* Save the stats across chip resets... */
7918 tg3_get_stats64(tp->dev, &tp->net_stats_prev),
7919 tg3_get_estats(tp, &tp->estats_prev);
7921 /* And make sure the next sample is new data */
7922 memset(tp->hw_stats, 0, sizeof(struct tg3_hw_stats));
7931 static int tg3_set_mac_addr(struct net_device *dev, void *p)
7933 struct tg3 *tp = netdev_priv(dev);
7934 struct sockaddr *addr = p;
7935 int err = 0, skip_mac_1 = 0;
7937 if (!is_valid_ether_addr(addr->sa_data))
7940 memcpy(dev->dev_addr, addr->sa_data, dev->addr_len);
7942 if (!netif_running(dev))
7945 if (tg3_flag(tp, ENABLE_ASF)) {
7946 u32 addr0_high, addr0_low, addr1_high, addr1_low;
7948 addr0_high = tr32(MAC_ADDR_0_HIGH);
7949 addr0_low = tr32(MAC_ADDR_0_LOW);
7950 addr1_high = tr32(MAC_ADDR_1_HIGH);
7951 addr1_low = tr32(MAC_ADDR_1_LOW);
7953 /* Skip MAC addr 1 if ASF is using it. */
7954 if ((addr0_high != addr1_high || addr0_low != addr1_low) &&
7955 !(addr1_high == 0 && addr1_low == 0))
7958 spin_lock_bh(&tp->lock);
7959 __tg3_set_mac_addr(tp, skip_mac_1);
7960 spin_unlock_bh(&tp->lock);
7965 /* tp->lock is held. */
7966 static void tg3_set_bdinfo(struct tg3 *tp, u32 bdinfo_addr,
7967 dma_addr_t mapping, u32 maxlen_flags,
7971 (bdinfo_addr + TG3_BDINFO_HOST_ADDR + TG3_64BIT_REG_HIGH),
7972 ((u64) mapping >> 32));
7974 (bdinfo_addr + TG3_BDINFO_HOST_ADDR + TG3_64BIT_REG_LOW),
7975 ((u64) mapping & 0xffffffff));
7977 (bdinfo_addr + TG3_BDINFO_MAXLEN_FLAGS),
7980 if (!tg3_flag(tp, 5705_PLUS))
7982 (bdinfo_addr + TG3_BDINFO_NIC_ADDR),
7986 static void __tg3_set_rx_mode(struct net_device *);
7987 static void __tg3_set_coalesce(struct tg3 *tp, struct ethtool_coalesce *ec)
7991 if (!tg3_flag(tp, ENABLE_TSS)) {
7992 tw32(HOSTCC_TXCOL_TICKS, ec->tx_coalesce_usecs);
7993 tw32(HOSTCC_TXMAX_FRAMES, ec->tx_max_coalesced_frames);
7994 tw32(HOSTCC_TXCOAL_MAXF_INT, ec->tx_max_coalesced_frames_irq);
7996 tw32(HOSTCC_TXCOL_TICKS, 0);
7997 tw32(HOSTCC_TXMAX_FRAMES, 0);
7998 tw32(HOSTCC_TXCOAL_MAXF_INT, 0);
8001 if (!tg3_flag(tp, ENABLE_RSS)) {
8002 tw32(HOSTCC_RXCOL_TICKS, ec->rx_coalesce_usecs);
8003 tw32(HOSTCC_RXMAX_FRAMES, ec->rx_max_coalesced_frames);
8004 tw32(HOSTCC_RXCOAL_MAXF_INT, ec->rx_max_coalesced_frames_irq);
8006 tw32(HOSTCC_RXCOL_TICKS, 0);
8007 tw32(HOSTCC_RXMAX_FRAMES, 0);
8008 tw32(HOSTCC_RXCOAL_MAXF_INT, 0);
8011 if (!tg3_flag(tp, 5705_PLUS)) {
8012 u32 val = ec->stats_block_coalesce_usecs;
8014 tw32(HOSTCC_RXCOAL_TICK_INT, ec->rx_coalesce_usecs_irq);
8015 tw32(HOSTCC_TXCOAL_TICK_INT, ec->tx_coalesce_usecs_irq);
8017 if (!netif_carrier_ok(tp->dev))
8020 tw32(HOSTCC_STAT_COAL_TICKS, val);
8023 for (i = 0; i < tp->irq_cnt - 1; i++) {
8026 reg = HOSTCC_RXCOL_TICKS_VEC1 + i * 0x18;
8027 tw32(reg, ec->rx_coalesce_usecs);
8028 reg = HOSTCC_RXMAX_FRAMES_VEC1 + i * 0x18;
8029 tw32(reg, ec->rx_max_coalesced_frames);
8030 reg = HOSTCC_RXCOAL_MAXF_INT_VEC1 + i * 0x18;
8031 tw32(reg, ec->rx_max_coalesced_frames_irq);
8033 if (tg3_flag(tp, ENABLE_TSS)) {
8034 reg = HOSTCC_TXCOL_TICKS_VEC1 + i * 0x18;
8035 tw32(reg, ec->tx_coalesce_usecs);
8036 reg = HOSTCC_TXMAX_FRAMES_VEC1 + i * 0x18;
8037 tw32(reg, ec->tx_max_coalesced_frames);
8038 reg = HOSTCC_TXCOAL_MAXF_INT_VEC1 + i * 0x18;
8039 tw32(reg, ec->tx_max_coalesced_frames_irq);
8043 for (; i < tp->irq_max - 1; i++) {
8044 tw32(HOSTCC_RXCOL_TICKS_VEC1 + i * 0x18, 0);
8045 tw32(HOSTCC_RXMAX_FRAMES_VEC1 + i * 0x18, 0);
8046 tw32(HOSTCC_RXCOAL_MAXF_INT_VEC1 + i * 0x18, 0);
8048 if (tg3_flag(tp, ENABLE_TSS)) {
8049 tw32(HOSTCC_TXCOL_TICKS_VEC1 + i * 0x18, 0);
8050 tw32(HOSTCC_TXMAX_FRAMES_VEC1 + i * 0x18, 0);
8051 tw32(HOSTCC_TXCOAL_MAXF_INT_VEC1 + i * 0x18, 0);
8056 /* tp->lock is held. */
8057 static void tg3_rings_reset(struct tg3 *tp)
8060 u32 stblk, txrcb, rxrcb, limit;
8061 struct tg3_napi *tnapi = &tp->napi[0];
8063 /* Disable all transmit rings but the first. */
8064 if (!tg3_flag(tp, 5705_PLUS))
8065 limit = NIC_SRAM_SEND_RCB + TG3_BDINFO_SIZE * 16;
8066 else if (tg3_flag(tp, 5717_PLUS))
8067 limit = NIC_SRAM_SEND_RCB + TG3_BDINFO_SIZE * 4;
8068 else if (tg3_flag(tp, 57765_CLASS))
8069 limit = NIC_SRAM_SEND_RCB + TG3_BDINFO_SIZE * 2;
8071 limit = NIC_SRAM_SEND_RCB + TG3_BDINFO_SIZE;
8073 for (txrcb = NIC_SRAM_SEND_RCB + TG3_BDINFO_SIZE;
8074 txrcb < limit; txrcb += TG3_BDINFO_SIZE)
8075 tg3_write_mem(tp, txrcb + TG3_BDINFO_MAXLEN_FLAGS,
8076 BDINFO_FLAGS_DISABLED);
8079 /* Disable all receive return rings but the first. */
8080 if (tg3_flag(tp, 5717_PLUS))
8081 limit = NIC_SRAM_RCV_RET_RCB + TG3_BDINFO_SIZE * 17;
8082 else if (!tg3_flag(tp, 5705_PLUS))
8083 limit = NIC_SRAM_RCV_RET_RCB + TG3_BDINFO_SIZE * 16;
8084 else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5755 ||
8085 tg3_flag(tp, 57765_CLASS))
8086 limit = NIC_SRAM_RCV_RET_RCB + TG3_BDINFO_SIZE * 4;
8088 limit = NIC_SRAM_RCV_RET_RCB + TG3_BDINFO_SIZE;
8090 for (rxrcb = NIC_SRAM_RCV_RET_RCB + TG3_BDINFO_SIZE;
8091 rxrcb < limit; rxrcb += TG3_BDINFO_SIZE)
8092 tg3_write_mem(tp, rxrcb + TG3_BDINFO_MAXLEN_FLAGS,
8093 BDINFO_FLAGS_DISABLED);
8095 /* Disable interrupts */
8096 tw32_mailbox_f(tp->napi[0].int_mbox, 1);
8097 tp->napi[0].chk_msi_cnt = 0;
8098 tp->napi[0].last_rx_cons = 0;
8099 tp->napi[0].last_tx_cons = 0;
8101 /* Zero mailbox registers. */
8102 if (tg3_flag(tp, SUPPORT_MSIX)) {
8103 for (i = 1; i < tp->irq_max; i++) {
8104 tp->napi[i].tx_prod = 0;
8105 tp->napi[i].tx_cons = 0;
8106 if (tg3_flag(tp, ENABLE_TSS))
8107 tw32_mailbox(tp->napi[i].prodmbox, 0);
8108 tw32_rx_mbox(tp->napi[i].consmbox, 0);
8109 tw32_mailbox_f(tp->napi[i].int_mbox, 1);
8110 tp->napi[i].chk_msi_cnt = 0;
8111 tp->napi[i].last_rx_cons = 0;
8112 tp->napi[i].last_tx_cons = 0;
8114 if (!tg3_flag(tp, ENABLE_TSS))
8115 tw32_mailbox(tp->napi[0].prodmbox, 0);
8117 tp->napi[0].tx_prod = 0;
8118 tp->napi[0].tx_cons = 0;
8119 tw32_mailbox(tp->napi[0].prodmbox, 0);
8120 tw32_rx_mbox(tp->napi[0].consmbox, 0);
8123 /* Make sure the NIC-based send BD rings are disabled. */
8124 if (!tg3_flag(tp, 5705_PLUS)) {
8125 u32 mbox = MAILBOX_SNDNIC_PROD_IDX_0 + TG3_64BIT_REG_LOW;
8126 for (i = 0; i < 16; i++)
8127 tw32_tx_mbox(mbox + i * 8, 0);
8130 txrcb = NIC_SRAM_SEND_RCB;
8131 rxrcb = NIC_SRAM_RCV_RET_RCB;
8133 /* Clear status block in ram. */
8134 memset(tnapi->hw_status, 0, TG3_HW_STATUS_SIZE);
8136 /* Set status block DMA address */
8137 tw32(HOSTCC_STATUS_BLK_HOST_ADDR + TG3_64BIT_REG_HIGH,
8138 ((u64) tnapi->status_mapping >> 32));
8139 tw32(HOSTCC_STATUS_BLK_HOST_ADDR + TG3_64BIT_REG_LOW,
8140 ((u64) tnapi->status_mapping & 0xffffffff));
8142 if (tnapi->tx_ring) {
8143 tg3_set_bdinfo(tp, txrcb, tnapi->tx_desc_mapping,
8144 (TG3_TX_RING_SIZE <<
8145 BDINFO_FLAGS_MAXLEN_SHIFT),
8146 NIC_SRAM_TX_BUFFER_DESC);
8147 txrcb += TG3_BDINFO_SIZE;
8150 if (tnapi->rx_rcb) {
8151 tg3_set_bdinfo(tp, rxrcb, tnapi->rx_rcb_mapping,
8152 (tp->rx_ret_ring_mask + 1) <<
8153 BDINFO_FLAGS_MAXLEN_SHIFT, 0);
8154 rxrcb += TG3_BDINFO_SIZE;
8157 stblk = HOSTCC_STATBLCK_RING1;
8159 for (i = 1, tnapi++; i < tp->irq_cnt; i++, tnapi++) {
8160 u64 mapping = (u64)tnapi->status_mapping;
8161 tw32(stblk + TG3_64BIT_REG_HIGH, mapping >> 32);
8162 tw32(stblk + TG3_64BIT_REG_LOW, mapping & 0xffffffff);
8164 /* Clear status block in ram. */
8165 memset(tnapi->hw_status, 0, TG3_HW_STATUS_SIZE);
8167 if (tnapi->tx_ring) {
8168 tg3_set_bdinfo(tp, txrcb, tnapi->tx_desc_mapping,
8169 (TG3_TX_RING_SIZE <<
8170 BDINFO_FLAGS_MAXLEN_SHIFT),
8171 NIC_SRAM_TX_BUFFER_DESC);
8172 txrcb += TG3_BDINFO_SIZE;
8175 tg3_set_bdinfo(tp, rxrcb, tnapi->rx_rcb_mapping,
8176 ((tp->rx_ret_ring_mask + 1) <<
8177 BDINFO_FLAGS_MAXLEN_SHIFT), 0);
8180 rxrcb += TG3_BDINFO_SIZE;
8184 static void tg3_setup_rxbd_thresholds(struct tg3 *tp)
8186 u32 val, bdcache_maxcnt, host_rep_thresh, nic_rep_thresh;
8188 if (!tg3_flag(tp, 5750_PLUS) ||
8189 tg3_flag(tp, 5780_CLASS) ||
8190 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5750 ||
8191 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5752 ||
8192 tg3_flag(tp, 57765_PLUS))
8193 bdcache_maxcnt = TG3_SRAM_RX_STD_BDCACHE_SIZE_5700;
8194 else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5755 ||
8195 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5787)
8196 bdcache_maxcnt = TG3_SRAM_RX_STD_BDCACHE_SIZE_5755;
8198 bdcache_maxcnt = TG3_SRAM_RX_STD_BDCACHE_SIZE_5906;
8200 nic_rep_thresh = min(bdcache_maxcnt / 2, tp->rx_std_max_post);
8201 host_rep_thresh = max_t(u32, tp->rx_pending / 8, 1);
8203 val = min(nic_rep_thresh, host_rep_thresh);
8204 tw32(RCVBDI_STD_THRESH, val);
8206 if (tg3_flag(tp, 57765_PLUS))
8207 tw32(STD_REPLENISH_LWM, bdcache_maxcnt);
8209 if (!tg3_flag(tp, JUMBO_CAPABLE) || tg3_flag(tp, 5780_CLASS))
8212 bdcache_maxcnt = TG3_SRAM_RX_JMB_BDCACHE_SIZE_5700;
8214 host_rep_thresh = max_t(u32, tp->rx_jumbo_pending / 8, 1);
8216 val = min(bdcache_maxcnt / 2, host_rep_thresh);
8217 tw32(RCVBDI_JUMBO_THRESH, val);
8219 if (tg3_flag(tp, 57765_PLUS))
8220 tw32(JMB_REPLENISH_LWM, bdcache_maxcnt);
8223 static void tg3_rss_init_dflt_indir_tbl(struct tg3 *tp)
8227 for (i = 0; i < TG3_RSS_INDIR_TBL_SIZE; i++)
8228 tp->rss_ind_tbl[i] =
8229 ethtool_rxfh_indir_default(i, tp->irq_cnt - 1);
8232 static void tg3_rss_check_indir_tbl(struct tg3 *tp)
8236 if (!tg3_flag(tp, SUPPORT_MSIX))
8239 if (tp->irq_cnt <= 2) {
8240 memset(&tp->rss_ind_tbl[0], 0, sizeof(tp->rss_ind_tbl));
8244 /* Validate table against current IRQ count */
8245 for (i = 0; i < TG3_RSS_INDIR_TBL_SIZE; i++) {
8246 if (tp->rss_ind_tbl[i] >= tp->irq_cnt - 1)
8250 if (i != TG3_RSS_INDIR_TBL_SIZE)
8251 tg3_rss_init_dflt_indir_tbl(tp);
8254 static void tg3_rss_write_indir_tbl(struct tg3 *tp)
8257 u32 reg = MAC_RSS_INDIR_TBL_0;
8259 while (i < TG3_RSS_INDIR_TBL_SIZE) {
8260 u32 val = tp->rss_ind_tbl[i];
8262 for (; i % 8; i++) {
8264 val |= tp->rss_ind_tbl[i];
8271 /* tp->lock is held. */
8272 static int tg3_reset_hw(struct tg3 *tp, int reset_phy)
8274 u32 val, rdmac_mode;
8276 struct tg3_rx_prodring_set *tpr = &tp->napi[0].prodring;
8278 tg3_disable_ints(tp);
8282 tg3_write_sig_pre_reset(tp, RESET_KIND_INIT);
8284 if (tg3_flag(tp, INIT_COMPLETE))
8285 tg3_abort_hw(tp, 1);
8287 /* Enable MAC control of LPI */
8288 if (tp->phy_flags & TG3_PHYFLG_EEE_CAP) {
8289 tw32_f(TG3_CPMU_EEE_LNKIDL_CTRL,
8290 TG3_CPMU_EEE_LNKIDL_PCIE_NL0 |
8291 TG3_CPMU_EEE_LNKIDL_UART_IDL);
8293 tw32_f(TG3_CPMU_EEE_CTRL,
8294 TG3_CPMU_EEE_CTRL_EXIT_20_1_US);
8296 val = TG3_CPMU_EEEMD_ERLY_L1_XIT_DET |
8297 TG3_CPMU_EEEMD_LPI_IN_TX |
8298 TG3_CPMU_EEEMD_LPI_IN_RX |
8299 TG3_CPMU_EEEMD_EEE_ENABLE;
8301 if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5717)
8302 val |= TG3_CPMU_EEEMD_SND_IDX_DET_EN;
8304 if (tg3_flag(tp, ENABLE_APE))
8305 val |= TG3_CPMU_EEEMD_APE_TX_DET_EN;
8307 tw32_f(TG3_CPMU_EEE_MODE, val);
8309 tw32_f(TG3_CPMU_EEE_DBTMR1,
8310 TG3_CPMU_DBTMR1_PCIEXIT_2047US |
8311 TG3_CPMU_DBTMR1_LNKIDLE_2047US);
8313 tw32_f(TG3_CPMU_EEE_DBTMR2,
8314 TG3_CPMU_DBTMR2_APE_TX_2047US |
8315 TG3_CPMU_DBTMR2_TXIDXEQ_2047US);
8321 err = tg3_chip_reset(tp);
8325 tg3_write_sig_legacy(tp, RESET_KIND_INIT);
8327 if (GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5784_AX) {
8328 val = tr32(TG3_CPMU_CTRL);
8329 val &= ~(CPMU_CTRL_LINK_AWARE_MODE | CPMU_CTRL_LINK_IDLE_MODE);
8330 tw32(TG3_CPMU_CTRL, val);
8332 val = tr32(TG3_CPMU_LSPD_10MB_CLK);
8333 val &= ~CPMU_LSPD_10MB_MACCLK_MASK;
8334 val |= CPMU_LSPD_10MB_MACCLK_6_25;
8335 tw32(TG3_CPMU_LSPD_10MB_CLK, val);
8337 val = tr32(TG3_CPMU_LNK_AWARE_PWRMD);
8338 val &= ~CPMU_LNK_AWARE_MACCLK_MASK;
8339 val |= CPMU_LNK_AWARE_MACCLK_6_25;
8340 tw32(TG3_CPMU_LNK_AWARE_PWRMD, val);
8342 val = tr32(TG3_CPMU_HST_ACC);
8343 val &= ~CPMU_HST_ACC_MACCLK_MASK;
8344 val |= CPMU_HST_ACC_MACCLK_6_25;
8345 tw32(TG3_CPMU_HST_ACC, val);
8348 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57780) {
8349 val = tr32(PCIE_PWR_MGMT_THRESH) & ~PCIE_PWR_MGMT_L1_THRESH_MSK;
8350 val |= PCIE_PWR_MGMT_EXT_ASPM_TMR_EN |
8351 PCIE_PWR_MGMT_L1_THRESH_4MS;
8352 tw32(PCIE_PWR_MGMT_THRESH, val);
8354 val = tr32(TG3_PCIE_EIDLE_DELAY) & ~TG3_PCIE_EIDLE_DELAY_MASK;
8355 tw32(TG3_PCIE_EIDLE_DELAY, val | TG3_PCIE_EIDLE_DELAY_13_CLKS);
8357 tw32(TG3_CORR_ERR_STAT, TG3_CORR_ERR_STAT_CLEAR);
8359 val = tr32(TG3_PCIE_LNKCTL) & ~TG3_PCIE_LNKCTL_L1_PLL_PD_EN;
8360 tw32(TG3_PCIE_LNKCTL, val | TG3_PCIE_LNKCTL_L1_PLL_PD_DIS);
8363 if (tg3_flag(tp, L1PLLPD_EN)) {
8364 u32 grc_mode = tr32(GRC_MODE);
8366 /* Access the lower 1K of PL PCIE block registers. */
8367 val = grc_mode & ~GRC_MODE_PCIE_PORT_MASK;
8368 tw32(GRC_MODE, val | GRC_MODE_PCIE_PL_SEL);
8370 val = tr32(TG3_PCIE_TLDLPL_PORT + TG3_PCIE_PL_LO_PHYCTL1);
8371 tw32(TG3_PCIE_TLDLPL_PORT + TG3_PCIE_PL_LO_PHYCTL1,
8372 val | TG3_PCIE_PL_LO_PHYCTL1_L1PLLPD_EN);
8374 tw32(GRC_MODE, grc_mode);
8377 if (tg3_flag(tp, 57765_CLASS)) {
8378 if (tp->pci_chip_rev_id == CHIPREV_ID_57765_A0) {
8379 u32 grc_mode = tr32(GRC_MODE);
8381 /* Access the lower 1K of PL PCIE block registers. */
8382 val = grc_mode & ~GRC_MODE_PCIE_PORT_MASK;
8383 tw32(GRC_MODE, val | GRC_MODE_PCIE_PL_SEL);
8385 val = tr32(TG3_PCIE_TLDLPL_PORT +
8386 TG3_PCIE_PL_LO_PHYCTL5);
8387 tw32(TG3_PCIE_TLDLPL_PORT + TG3_PCIE_PL_LO_PHYCTL5,
8388 val | TG3_PCIE_PL_LO_PHYCTL5_DIS_L2CLKREQ);
8390 tw32(GRC_MODE, grc_mode);
8393 if (GET_CHIP_REV(tp->pci_chip_rev_id) != CHIPREV_57765_AX) {
8394 u32 grc_mode = tr32(GRC_MODE);
8396 /* Access the lower 1K of DL PCIE block registers. */
8397 val = grc_mode & ~GRC_MODE_PCIE_PORT_MASK;
8398 tw32(GRC_MODE, val | GRC_MODE_PCIE_DL_SEL);
8400 val = tr32(TG3_PCIE_TLDLPL_PORT +
8401 TG3_PCIE_DL_LO_FTSMAX);
8402 val &= ~TG3_PCIE_DL_LO_FTSMAX_MSK;
8403 tw32(TG3_PCIE_TLDLPL_PORT + TG3_PCIE_DL_LO_FTSMAX,
8404 val | TG3_PCIE_DL_LO_FTSMAX_VAL);
8406 tw32(GRC_MODE, grc_mode);
8409 val = tr32(TG3_CPMU_LSPD_10MB_CLK);
8410 val &= ~CPMU_LSPD_10MB_MACCLK_MASK;
8411 val |= CPMU_LSPD_10MB_MACCLK_6_25;
8412 tw32(TG3_CPMU_LSPD_10MB_CLK, val);
8415 /* This works around an issue with Athlon chipsets on
8416 * B3 tigon3 silicon. This bit has no effect on any
8417 * other revision. But do not set this on PCI Express
8418 * chips and don't even touch the clocks if the CPMU is present.
8420 if (!tg3_flag(tp, CPMU_PRESENT)) {
8421 if (!tg3_flag(tp, PCI_EXPRESS))
8422 tp->pci_clock_ctrl |= CLOCK_CTRL_DELAY_PCI_GRANT;
8423 tw32_f(TG3PCI_CLOCK_CTRL, tp->pci_clock_ctrl);
8426 if (tp->pci_chip_rev_id == CHIPREV_ID_5704_A0 &&
8427 tg3_flag(tp, PCIX_MODE)) {
8428 val = tr32(TG3PCI_PCISTATE);
8429 val |= PCISTATE_RETRY_SAME_DMA;
8430 tw32(TG3PCI_PCISTATE, val);
8433 if (tg3_flag(tp, ENABLE_APE)) {
8434 /* Allow reads and writes to the
8435 * APE register and memory space.
8437 val = tr32(TG3PCI_PCISTATE);
8438 val |= PCISTATE_ALLOW_APE_CTLSPC_WR |
8439 PCISTATE_ALLOW_APE_SHMEM_WR |
8440 PCISTATE_ALLOW_APE_PSPACE_WR;
8441 tw32(TG3PCI_PCISTATE, val);
8444 if (GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5704_BX) {
8445 /* Enable some hw fixes. */
8446 val = tr32(TG3PCI_MSI_DATA);
8447 val |= (1 << 26) | (1 << 28) | (1 << 29);
8448 tw32(TG3PCI_MSI_DATA, val);
8451 /* Descriptor ring init may make accesses to the
8452 * NIC SRAM area to setup the TX descriptors, so we
8453 * can only do this after the hardware has been
8454 * successfully reset.
8456 err = tg3_init_rings(tp);
8460 if (tg3_flag(tp, 57765_PLUS)) {
8461 val = tr32(TG3PCI_DMA_RW_CTRL) &
8462 ~DMA_RWCTRL_DIS_CACHE_ALIGNMENT;
8463 if (tp->pci_chip_rev_id == CHIPREV_ID_57765_A0)
8464 val &= ~DMA_RWCTRL_CRDRDR_RDMA_MRRS_MSK;
8465 if (!tg3_flag(tp, 57765_CLASS) &&
8466 GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5717)
8467 val |= DMA_RWCTRL_TAGGED_STAT_WA;
8468 tw32(TG3PCI_DMA_RW_CTRL, val | tp->dma_rwctrl);
8469 } else if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5784 &&
8470 GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5761) {
8471 /* This value is determined during the probe time DMA
8472 * engine test, tg3_test_dma.
8474 tw32(TG3PCI_DMA_RW_CTRL, tp->dma_rwctrl);
8477 tp->grc_mode &= ~(GRC_MODE_HOST_SENDBDS |
8478 GRC_MODE_4X_NIC_SEND_RINGS |
8479 GRC_MODE_NO_TX_PHDR_CSUM |
8480 GRC_MODE_NO_RX_PHDR_CSUM);
8481 tp->grc_mode |= GRC_MODE_HOST_SENDBDS;
8483 /* Pseudo-header checksum is done by hardware logic and not
8484 * the offload processers, so make the chip do the pseudo-
8485 * header checksums on receive. For transmit it is more
8486 * convenient to do the pseudo-header checksum in software
8487 * as Linux does that on transmit for us in all cases.
8489 tp->grc_mode |= GRC_MODE_NO_TX_PHDR_CSUM;
8493 (GRC_MODE_IRQ_ON_MAC_ATTN | GRC_MODE_HOST_STACKUP));
8495 /* Setup the timer prescalar register. Clock is always 66Mhz. */
8496 val = tr32(GRC_MISC_CFG);
8498 val |= (65 << GRC_MISC_CFG_PRESCALAR_SHIFT);
8499 tw32(GRC_MISC_CFG, val);
8501 /* Initialize MBUF/DESC pool. */
8502 if (tg3_flag(tp, 5750_PLUS)) {
8504 } else if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5705) {
8505 tw32(BUFMGR_MB_POOL_ADDR, NIC_SRAM_MBUF_POOL_BASE);
8506 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704)
8507 tw32(BUFMGR_MB_POOL_SIZE, NIC_SRAM_MBUF_POOL_SIZE64);
8509 tw32(BUFMGR_MB_POOL_SIZE, NIC_SRAM_MBUF_POOL_SIZE96);
8510 tw32(BUFMGR_DMA_DESC_POOL_ADDR, NIC_SRAM_DMA_DESC_POOL_BASE);
8511 tw32(BUFMGR_DMA_DESC_POOL_SIZE, NIC_SRAM_DMA_DESC_POOL_SIZE);
8512 } else if (tg3_flag(tp, TSO_CAPABLE)) {
8515 fw_len = tp->fw_len;
8516 fw_len = (fw_len + (0x80 - 1)) & ~(0x80 - 1);
8517 tw32(BUFMGR_MB_POOL_ADDR,
8518 NIC_SRAM_MBUF_POOL_BASE5705 + fw_len);
8519 tw32(BUFMGR_MB_POOL_SIZE,
8520 NIC_SRAM_MBUF_POOL_SIZE5705 - fw_len - 0xa00);
8523 if (tp->dev->mtu <= ETH_DATA_LEN) {
8524 tw32(BUFMGR_MB_RDMA_LOW_WATER,
8525 tp->bufmgr_config.mbuf_read_dma_low_water);
8526 tw32(BUFMGR_MB_MACRX_LOW_WATER,
8527 tp->bufmgr_config.mbuf_mac_rx_low_water);
8528 tw32(BUFMGR_MB_HIGH_WATER,
8529 tp->bufmgr_config.mbuf_high_water);
8531 tw32(BUFMGR_MB_RDMA_LOW_WATER,
8532 tp->bufmgr_config.mbuf_read_dma_low_water_jumbo);
8533 tw32(BUFMGR_MB_MACRX_LOW_WATER,
8534 tp->bufmgr_config.mbuf_mac_rx_low_water_jumbo);
8535 tw32(BUFMGR_MB_HIGH_WATER,
8536 tp->bufmgr_config.mbuf_high_water_jumbo);
8538 tw32(BUFMGR_DMA_LOW_WATER,
8539 tp->bufmgr_config.dma_low_water);
8540 tw32(BUFMGR_DMA_HIGH_WATER,
8541 tp->bufmgr_config.dma_high_water);
8543 val = BUFMGR_MODE_ENABLE | BUFMGR_MODE_ATTN_ENABLE;
8544 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5719)
8545 val |= BUFMGR_MODE_NO_TX_UNDERRUN;
8546 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717 ||
8547 tp->pci_chip_rev_id == CHIPREV_ID_5719_A0 ||
8548 tp->pci_chip_rev_id == CHIPREV_ID_5720_A0)
8549 val |= BUFMGR_MODE_MBLOW_ATTN_ENAB;
8550 tw32(BUFMGR_MODE, val);
8551 for (i = 0; i < 2000; i++) {
8552 if (tr32(BUFMGR_MODE) & BUFMGR_MODE_ENABLE)
8557 netdev_err(tp->dev, "%s cannot enable BUFMGR\n", __func__);
8561 if (tp->pci_chip_rev_id == CHIPREV_ID_5906_A1)
8562 tw32(ISO_PKT_TX, (tr32(ISO_PKT_TX) & ~0x3) | 0x2);
8564 tg3_setup_rxbd_thresholds(tp);
8566 /* Initialize TG3_BDINFO's at:
8567 * RCVDBDI_STD_BD: standard eth size rx ring
8568 * RCVDBDI_JUMBO_BD: jumbo frame rx ring
8569 * RCVDBDI_MINI_BD: small frame rx ring (??? does not work)
8572 * TG3_BDINFO_HOST_ADDR: high/low parts of DMA address of ring
8573 * TG3_BDINFO_MAXLEN_FLAGS: (rx max buffer size << 16) |
8574 * ring attribute flags
8575 * TG3_BDINFO_NIC_ADDR: location of descriptors in nic SRAM
8577 * Standard receive ring @ NIC_SRAM_RX_BUFFER_DESC, 512 entries.
8578 * Jumbo receive ring @ NIC_SRAM_RX_JUMBO_BUFFER_DESC, 256 entries.
8580 * The size of each ring is fixed in the firmware, but the location is
8583 tw32(RCVDBDI_STD_BD + TG3_BDINFO_HOST_ADDR + TG3_64BIT_REG_HIGH,
8584 ((u64) tpr->rx_std_mapping >> 32));
8585 tw32(RCVDBDI_STD_BD + TG3_BDINFO_HOST_ADDR + TG3_64BIT_REG_LOW,
8586 ((u64) tpr->rx_std_mapping & 0xffffffff));
8587 if (!tg3_flag(tp, 5717_PLUS))
8588 tw32(RCVDBDI_STD_BD + TG3_BDINFO_NIC_ADDR,
8589 NIC_SRAM_RX_BUFFER_DESC);
8591 /* Disable the mini ring */
8592 if (!tg3_flag(tp, 5705_PLUS))
8593 tw32(RCVDBDI_MINI_BD + TG3_BDINFO_MAXLEN_FLAGS,
8594 BDINFO_FLAGS_DISABLED);
8596 /* Program the jumbo buffer descriptor ring control
8597 * blocks on those devices that have them.
8599 if (tp->pci_chip_rev_id == CHIPREV_ID_5719_A0 ||
8600 (tg3_flag(tp, JUMBO_CAPABLE) && !tg3_flag(tp, 5780_CLASS))) {
8602 if (tg3_flag(tp, JUMBO_RING_ENABLE)) {
8603 tw32(RCVDBDI_JUMBO_BD + TG3_BDINFO_HOST_ADDR + TG3_64BIT_REG_HIGH,
8604 ((u64) tpr->rx_jmb_mapping >> 32));
8605 tw32(RCVDBDI_JUMBO_BD + TG3_BDINFO_HOST_ADDR + TG3_64BIT_REG_LOW,
8606 ((u64) tpr->rx_jmb_mapping & 0xffffffff));
8607 val = TG3_RX_JMB_RING_SIZE(tp) <<
8608 BDINFO_FLAGS_MAXLEN_SHIFT;
8609 tw32(RCVDBDI_JUMBO_BD + TG3_BDINFO_MAXLEN_FLAGS,
8610 val | BDINFO_FLAGS_USE_EXT_RECV);
8611 if (!tg3_flag(tp, USE_JUMBO_BDFLAG) ||
8612 tg3_flag(tp, 57765_CLASS))
8613 tw32(RCVDBDI_JUMBO_BD + TG3_BDINFO_NIC_ADDR,
8614 NIC_SRAM_RX_JUMBO_BUFFER_DESC);
8616 tw32(RCVDBDI_JUMBO_BD + TG3_BDINFO_MAXLEN_FLAGS,
8617 BDINFO_FLAGS_DISABLED);
8620 if (tg3_flag(tp, 57765_PLUS)) {
8621 val = TG3_RX_STD_RING_SIZE(tp);
8622 val <<= BDINFO_FLAGS_MAXLEN_SHIFT;
8623 val |= (TG3_RX_STD_DMA_SZ << 2);
8625 val = TG3_RX_STD_DMA_SZ << BDINFO_FLAGS_MAXLEN_SHIFT;
8627 val = TG3_RX_STD_MAX_SIZE_5700 << BDINFO_FLAGS_MAXLEN_SHIFT;
8629 tw32(RCVDBDI_STD_BD + TG3_BDINFO_MAXLEN_FLAGS, val);
8631 tpr->rx_std_prod_idx = tp->rx_pending;
8632 tw32_rx_mbox(TG3_RX_STD_PROD_IDX_REG, tpr->rx_std_prod_idx);
8634 tpr->rx_jmb_prod_idx =
8635 tg3_flag(tp, JUMBO_RING_ENABLE) ? tp->rx_jumbo_pending : 0;
8636 tw32_rx_mbox(TG3_RX_JMB_PROD_IDX_REG, tpr->rx_jmb_prod_idx);
8638 tg3_rings_reset(tp);
8640 /* Initialize MAC address and backoff seed. */
8641 __tg3_set_mac_addr(tp, 0);
8643 /* MTU + ethernet header + FCS + optional VLAN tag */
8644 tw32(MAC_RX_MTU_SIZE,
8645 tp->dev->mtu + ETH_HLEN + ETH_FCS_LEN + VLAN_HLEN);
8647 /* The slot time is changed by tg3_setup_phy if we
8648 * run at gigabit with half duplex.
8650 val = (2 << TX_LENGTHS_IPG_CRS_SHIFT) |
8651 (6 << TX_LENGTHS_IPG_SHIFT) |
8652 (32 << TX_LENGTHS_SLOT_TIME_SHIFT);
8654 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5720)
8655 val |= tr32(MAC_TX_LENGTHS) &
8656 (TX_LENGTHS_JMB_FRM_LEN_MSK |
8657 TX_LENGTHS_CNT_DWN_VAL_MSK);
8659 tw32(MAC_TX_LENGTHS, val);
8661 /* Receive rules. */
8662 tw32(MAC_RCV_RULE_CFG, RCV_RULE_CFG_DEFAULT_CLASS);
8663 tw32(RCVLPC_CONFIG, 0x0181);
8665 /* Calculate RDMAC_MODE setting early, we need it to determine
8666 * the RCVLPC_STATE_ENABLE mask.
8668 rdmac_mode = (RDMAC_MODE_ENABLE | RDMAC_MODE_TGTABORT_ENAB |
8669 RDMAC_MODE_MSTABORT_ENAB | RDMAC_MODE_PARITYERR_ENAB |
8670 RDMAC_MODE_ADDROFLOW_ENAB | RDMAC_MODE_FIFOOFLOW_ENAB |
8671 RDMAC_MODE_FIFOURUN_ENAB | RDMAC_MODE_FIFOOREAD_ENAB |
8672 RDMAC_MODE_LNGREAD_ENAB);
8674 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717)
8675 rdmac_mode |= RDMAC_MODE_MULT_DMA_RD_DIS;
8677 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5784 ||
8678 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785 ||
8679 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57780)
8680 rdmac_mode |= RDMAC_MODE_BD_SBD_CRPT_ENAB |
8681 RDMAC_MODE_MBUF_RBD_CRPT_ENAB |
8682 RDMAC_MODE_MBUF_SBD_CRPT_ENAB;
8684 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705 &&
8685 tp->pci_chip_rev_id != CHIPREV_ID_5705_A0) {
8686 if (tg3_flag(tp, TSO_CAPABLE) &&
8687 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705) {
8688 rdmac_mode |= RDMAC_MODE_FIFO_SIZE_128;
8689 } else if (!(tr32(TG3PCI_PCISTATE) & PCISTATE_BUS_SPEED_HIGH) &&
8690 !tg3_flag(tp, IS_5788)) {
8691 rdmac_mode |= RDMAC_MODE_FIFO_LONG_BURST;
8695 if (tg3_flag(tp, PCI_EXPRESS))
8696 rdmac_mode |= RDMAC_MODE_FIFO_LONG_BURST;
8698 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57766)
8699 rdmac_mode |= RDMAC_MODE_JMB_2K_MMRR;
8701 if (tg3_flag(tp, HW_TSO_1) ||
8702 tg3_flag(tp, HW_TSO_2) ||
8703 tg3_flag(tp, HW_TSO_3))
8704 rdmac_mode |= RDMAC_MODE_IPV4_LSO_EN;
8706 if (tg3_flag(tp, 57765_PLUS) ||
8707 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785 ||
8708 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57780)
8709 rdmac_mode |= RDMAC_MODE_IPV6_LSO_EN;
8711 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5720)
8712 rdmac_mode |= tr32(RDMAC_MODE) & RDMAC_MODE_H2BNC_VLAN_DET;
8714 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5761 ||
8715 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5784 ||
8716 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785 ||
8717 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57780 ||
8718 tg3_flag(tp, 57765_PLUS)) {
8719 val = tr32(TG3_RDMA_RSRVCTRL_REG);
8720 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5719 ||
8721 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5720) {
8722 val &= ~(TG3_RDMA_RSRVCTRL_TXMRGN_MASK |
8723 TG3_RDMA_RSRVCTRL_FIFO_LWM_MASK |
8724 TG3_RDMA_RSRVCTRL_FIFO_HWM_MASK);
8725 val |= TG3_RDMA_RSRVCTRL_TXMRGN_320B |
8726 TG3_RDMA_RSRVCTRL_FIFO_LWM_1_5K |
8727 TG3_RDMA_RSRVCTRL_FIFO_HWM_1_5K;
8729 tw32(TG3_RDMA_RSRVCTRL_REG,
8730 val | TG3_RDMA_RSRVCTRL_FIFO_OFLW_FIX);
8733 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5719 ||
8734 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5720) {
8735 val = tr32(TG3_LSO_RD_DMA_CRPTEN_CTRL);
8736 tw32(TG3_LSO_RD_DMA_CRPTEN_CTRL, val |
8737 TG3_LSO_RD_DMA_CRPTEN_CTRL_BLEN_BD_4K |
8738 TG3_LSO_RD_DMA_CRPTEN_CTRL_BLEN_LSO_4K);
8741 /* Receive/send statistics. */
8742 if (tg3_flag(tp, 5750_PLUS)) {
8743 val = tr32(RCVLPC_STATS_ENABLE);
8744 val &= ~RCVLPC_STATSENAB_DACK_FIX;
8745 tw32(RCVLPC_STATS_ENABLE, val);
8746 } else if ((rdmac_mode & RDMAC_MODE_FIFO_SIZE_128) &&
8747 tg3_flag(tp, TSO_CAPABLE)) {
8748 val = tr32(RCVLPC_STATS_ENABLE);
8749 val &= ~RCVLPC_STATSENAB_LNGBRST_RFIX;
8750 tw32(RCVLPC_STATS_ENABLE, val);
8752 tw32(RCVLPC_STATS_ENABLE, 0xffffff);
8754 tw32(RCVLPC_STATSCTRL, RCVLPC_STATSCTRL_ENABLE);
8755 tw32(SNDDATAI_STATSENAB, 0xffffff);
8756 tw32(SNDDATAI_STATSCTRL,
8757 (SNDDATAI_SCTRL_ENABLE |
8758 SNDDATAI_SCTRL_FASTUPD));
8760 /* Setup host coalescing engine. */
8761 tw32(HOSTCC_MODE, 0);
8762 for (i = 0; i < 2000; i++) {
8763 if (!(tr32(HOSTCC_MODE) & HOSTCC_MODE_ENABLE))
8768 __tg3_set_coalesce(tp, &tp->coal);
8770 if (!tg3_flag(tp, 5705_PLUS)) {
8771 /* Status/statistics block address. See tg3_timer,
8772 * the tg3_periodic_fetch_stats call there, and
8773 * tg3_get_stats to see how this works for 5705/5750 chips.
8775 tw32(HOSTCC_STATS_BLK_HOST_ADDR + TG3_64BIT_REG_HIGH,
8776 ((u64) tp->stats_mapping >> 32));
8777 tw32(HOSTCC_STATS_BLK_HOST_ADDR + TG3_64BIT_REG_LOW,
8778 ((u64) tp->stats_mapping & 0xffffffff));
8779 tw32(HOSTCC_STATS_BLK_NIC_ADDR, NIC_SRAM_STATS_BLK);
8781 tw32(HOSTCC_STATUS_BLK_NIC_ADDR, NIC_SRAM_STATUS_BLK);
8783 /* Clear statistics and status block memory areas */
8784 for (i = NIC_SRAM_STATS_BLK;
8785 i < NIC_SRAM_STATUS_BLK + TG3_HW_STATUS_SIZE;
8787 tg3_write_mem(tp, i, 0);
8792 tw32(HOSTCC_MODE, HOSTCC_MODE_ENABLE | tp->coalesce_mode);
8794 tw32(RCVCC_MODE, RCVCC_MODE_ENABLE | RCVCC_MODE_ATTN_ENABLE);
8795 tw32(RCVLPC_MODE, RCVLPC_MODE_ENABLE);
8796 if (!tg3_flag(tp, 5705_PLUS))
8797 tw32(RCVLSC_MODE, RCVLSC_MODE_ENABLE | RCVLSC_MODE_ATTN_ENABLE);
8799 if (tp->phy_flags & TG3_PHYFLG_MII_SERDES) {
8800 tp->phy_flags &= ~TG3_PHYFLG_PARALLEL_DETECT;
8801 /* reset to prevent losing 1st rx packet intermittently */
8802 tw32_f(MAC_RX_MODE, RX_MODE_RESET);
8806 tp->mac_mode |= MAC_MODE_TXSTAT_ENABLE | MAC_MODE_RXSTAT_ENABLE |
8807 MAC_MODE_TDE_ENABLE | MAC_MODE_RDE_ENABLE |
8808 MAC_MODE_FHDE_ENABLE;
8809 if (tg3_flag(tp, ENABLE_APE))
8810 tp->mac_mode |= MAC_MODE_APE_TX_EN | MAC_MODE_APE_RX_EN;
8811 if (!tg3_flag(tp, 5705_PLUS) &&
8812 !(tp->phy_flags & TG3_PHYFLG_PHY_SERDES) &&
8813 GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5700)
8814 tp->mac_mode |= MAC_MODE_LINK_POLARITY;
8815 tw32_f(MAC_MODE, tp->mac_mode | MAC_MODE_RXSTAT_CLEAR | MAC_MODE_TXSTAT_CLEAR);
8818 /* tp->grc_local_ctrl is partially set up during tg3_get_invariants().
8819 * If TG3_FLAG_IS_NIC is zero, we should read the
8820 * register to preserve the GPIO settings for LOMs. The GPIOs,
8821 * whether used as inputs or outputs, are set by boot code after
8824 if (!tg3_flag(tp, IS_NIC)) {
8827 gpio_mask = GRC_LCLCTRL_GPIO_OE0 | GRC_LCLCTRL_GPIO_OE1 |
8828 GRC_LCLCTRL_GPIO_OE2 | GRC_LCLCTRL_GPIO_OUTPUT0 |
8829 GRC_LCLCTRL_GPIO_OUTPUT1 | GRC_LCLCTRL_GPIO_OUTPUT2;
8831 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5752)
8832 gpio_mask |= GRC_LCLCTRL_GPIO_OE3 |
8833 GRC_LCLCTRL_GPIO_OUTPUT3;
8835 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5755)
8836 gpio_mask |= GRC_LCLCTRL_GPIO_UART_SEL;
8838 tp->grc_local_ctrl &= ~gpio_mask;
8839 tp->grc_local_ctrl |= tr32(GRC_LOCAL_CTRL) & gpio_mask;
8841 /* GPIO1 must be driven high for eeprom write protect */
8842 if (tg3_flag(tp, EEPROM_WRITE_PROT))
8843 tp->grc_local_ctrl |= (GRC_LCLCTRL_GPIO_OE1 |
8844 GRC_LCLCTRL_GPIO_OUTPUT1);
8846 tw32_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl);
8849 if (tg3_flag(tp, USING_MSIX) && tp->irq_cnt > 1) {
8850 val = tr32(MSGINT_MODE);
8851 val |= MSGINT_MODE_MULTIVEC_EN | MSGINT_MODE_ENABLE;
8852 if (!tg3_flag(tp, 1SHOT_MSI))
8853 val |= MSGINT_MODE_ONE_SHOT_DISABLE;
8854 tw32(MSGINT_MODE, val);
8857 if (!tg3_flag(tp, 5705_PLUS)) {
8858 tw32_f(DMAC_MODE, DMAC_MODE_ENABLE);
8862 val = (WDMAC_MODE_ENABLE | WDMAC_MODE_TGTABORT_ENAB |
8863 WDMAC_MODE_MSTABORT_ENAB | WDMAC_MODE_PARITYERR_ENAB |
8864 WDMAC_MODE_ADDROFLOW_ENAB | WDMAC_MODE_FIFOOFLOW_ENAB |
8865 WDMAC_MODE_FIFOURUN_ENAB | WDMAC_MODE_FIFOOREAD_ENAB |
8866 WDMAC_MODE_LNGREAD_ENAB);
8868 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705 &&
8869 tp->pci_chip_rev_id != CHIPREV_ID_5705_A0) {
8870 if (tg3_flag(tp, TSO_CAPABLE) &&
8871 (tp->pci_chip_rev_id == CHIPREV_ID_5705_A1 ||
8872 tp->pci_chip_rev_id == CHIPREV_ID_5705_A2)) {
8874 } else if (!(tr32(TG3PCI_PCISTATE) & PCISTATE_BUS_SPEED_HIGH) &&
8875 !tg3_flag(tp, IS_5788)) {
8876 val |= WDMAC_MODE_RX_ACCEL;
8880 /* Enable host coalescing bug fix */
8881 if (tg3_flag(tp, 5755_PLUS))
8882 val |= WDMAC_MODE_STATUS_TAG_FIX;
8884 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785)
8885 val |= WDMAC_MODE_BURST_ALL_DATA;
8887 tw32_f(WDMAC_MODE, val);
8890 if (tg3_flag(tp, PCIX_MODE)) {
8893 pci_read_config_word(tp->pdev, tp->pcix_cap + PCI_X_CMD,
8895 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703) {
8896 pcix_cmd &= ~PCI_X_CMD_MAX_READ;
8897 pcix_cmd |= PCI_X_CMD_READ_2K;
8898 } else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704) {
8899 pcix_cmd &= ~(PCI_X_CMD_MAX_SPLIT | PCI_X_CMD_MAX_READ);
8900 pcix_cmd |= PCI_X_CMD_READ_2K;
8902 pci_write_config_word(tp->pdev, tp->pcix_cap + PCI_X_CMD,
8906 tw32_f(RDMAC_MODE, rdmac_mode);
8909 tw32(RCVDCC_MODE, RCVDCC_MODE_ENABLE | RCVDCC_MODE_ATTN_ENABLE);
8910 if (!tg3_flag(tp, 5705_PLUS))
8911 tw32(MBFREE_MODE, MBFREE_MODE_ENABLE);
8913 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5761)
8915 SNDDATAC_MODE_ENABLE | SNDDATAC_MODE_CDELAY);
8917 tw32(SNDDATAC_MODE, SNDDATAC_MODE_ENABLE);
8919 tw32(SNDBDC_MODE, SNDBDC_MODE_ENABLE | SNDBDC_MODE_ATTN_ENABLE);
8920 tw32(RCVBDI_MODE, RCVBDI_MODE_ENABLE | RCVBDI_MODE_RCB_ATTN_ENAB);
8921 val = RCVDBDI_MODE_ENABLE | RCVDBDI_MODE_INV_RING_SZ;
8922 if (tg3_flag(tp, LRG_PROD_RING_CAP))
8923 val |= RCVDBDI_MODE_LRG_RING_SZ;
8924 tw32(RCVDBDI_MODE, val);
8925 tw32(SNDDATAI_MODE, SNDDATAI_MODE_ENABLE);
8926 if (tg3_flag(tp, HW_TSO_1) ||
8927 tg3_flag(tp, HW_TSO_2) ||
8928 tg3_flag(tp, HW_TSO_3))
8929 tw32(SNDDATAI_MODE, SNDDATAI_MODE_ENABLE | 0x8);
8930 val = SNDBDI_MODE_ENABLE | SNDBDI_MODE_ATTN_ENABLE;
8931 if (tg3_flag(tp, ENABLE_TSS))
8932 val |= SNDBDI_MODE_MULTI_TXQ_EN;
8933 tw32(SNDBDI_MODE, val);
8934 tw32(SNDBDS_MODE, SNDBDS_MODE_ENABLE | SNDBDS_MODE_ATTN_ENABLE);
8936 if (tp->pci_chip_rev_id == CHIPREV_ID_5701_A0) {
8937 err = tg3_load_5701_a0_firmware_fix(tp);
8942 if (tg3_flag(tp, TSO_CAPABLE)) {
8943 err = tg3_load_tso_firmware(tp);
8948 tp->tx_mode = TX_MODE_ENABLE;
8950 if (tg3_flag(tp, 5755_PLUS) ||
8951 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906)
8952 tp->tx_mode |= TX_MODE_MBUF_LOCKUP_FIX;
8954 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5720) {
8955 val = TX_MODE_JMB_FRM_LEN | TX_MODE_CNT_DN_MODE;
8956 tp->tx_mode &= ~val;
8957 tp->tx_mode |= tr32(MAC_TX_MODE) & val;
8960 tw32_f(MAC_TX_MODE, tp->tx_mode);
8963 if (tg3_flag(tp, ENABLE_RSS)) {
8964 tg3_rss_write_indir_tbl(tp);
8966 /* Setup the "secret" hash key. */
8967 tw32(MAC_RSS_HASH_KEY_0, 0x5f865437);
8968 tw32(MAC_RSS_HASH_KEY_1, 0xe4ac62cc);
8969 tw32(MAC_RSS_HASH_KEY_2, 0x50103a45);
8970 tw32(MAC_RSS_HASH_KEY_3, 0x36621985);
8971 tw32(MAC_RSS_HASH_KEY_4, 0xbf14c0e8);
8972 tw32(MAC_RSS_HASH_KEY_5, 0x1bc27a1e);
8973 tw32(MAC_RSS_HASH_KEY_6, 0x84f4b556);
8974 tw32(MAC_RSS_HASH_KEY_7, 0x094ea6fe);
8975 tw32(MAC_RSS_HASH_KEY_8, 0x7dda01e7);
8976 tw32(MAC_RSS_HASH_KEY_9, 0xc04d7481);
8979 tp->rx_mode = RX_MODE_ENABLE;
8980 if (tg3_flag(tp, 5755_PLUS))
8981 tp->rx_mode |= RX_MODE_IPV6_CSUM_ENABLE;
8983 if (tg3_flag(tp, ENABLE_RSS))
8984 tp->rx_mode |= RX_MODE_RSS_ENABLE |
8985 RX_MODE_RSS_ITBL_HASH_BITS_7 |
8986 RX_MODE_RSS_IPV6_HASH_EN |
8987 RX_MODE_RSS_TCP_IPV6_HASH_EN |
8988 RX_MODE_RSS_IPV4_HASH_EN |
8989 RX_MODE_RSS_TCP_IPV4_HASH_EN;
8991 tw32_f(MAC_RX_MODE, tp->rx_mode);
8994 tw32(MAC_LED_CTRL, tp->led_ctrl);
8996 tw32(MAC_MI_STAT, MAC_MI_STAT_LNKSTAT_ATTN_ENAB);
8997 if (tp->phy_flags & TG3_PHYFLG_PHY_SERDES) {
8998 tw32_f(MAC_RX_MODE, RX_MODE_RESET);
9001 tw32_f(MAC_RX_MODE, tp->rx_mode);
9004 if (tp->phy_flags & TG3_PHYFLG_PHY_SERDES) {
9005 if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704) &&
9006 !(tp->phy_flags & TG3_PHYFLG_SERDES_PREEMPHASIS)) {
9007 /* Set drive transmission level to 1.2V */
9008 /* only if the signal pre-emphasis bit is not set */
9009 val = tr32(MAC_SERDES_CFG);
9012 tw32(MAC_SERDES_CFG, val);
9014 if (tp->pci_chip_rev_id == CHIPREV_ID_5703_A1)
9015 tw32(MAC_SERDES_CFG, 0x616000);
9018 /* Prevent chip from dropping frames when flow control
9021 if (tg3_flag(tp, 57765_CLASS))
9025 tw32_f(MAC_LOW_WMARK_MAX_RX_FRAME, val);
9027 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704 &&
9028 (tp->phy_flags & TG3_PHYFLG_PHY_SERDES)) {
9029 /* Use hardware link auto-negotiation */
9030 tg3_flag_set(tp, HW_AUTONEG);
9033 if ((tp->phy_flags & TG3_PHYFLG_MII_SERDES) &&
9034 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5714) {
9037 tmp = tr32(SERDES_RX_CTRL);
9038 tw32(SERDES_RX_CTRL, tmp | SERDES_RX_SIG_DETECT);
9039 tp->grc_local_ctrl &= ~GRC_LCLCTRL_USE_EXT_SIG_DETECT;
9040 tp->grc_local_ctrl |= GRC_LCLCTRL_USE_SIG_DETECT;
9041 tw32(GRC_LOCAL_CTRL, tp->grc_local_ctrl);
9044 if (!tg3_flag(tp, USE_PHYLIB)) {
9045 if (tp->phy_flags & TG3_PHYFLG_IS_LOW_POWER) {
9046 tp->phy_flags &= ~TG3_PHYFLG_IS_LOW_POWER;
9047 tp->link_config.speed = tp->link_config.orig_speed;
9048 tp->link_config.duplex = tp->link_config.orig_duplex;
9049 tp->link_config.autoneg = tp->link_config.orig_autoneg;
9052 err = tg3_setup_phy(tp, 0);
9056 if (!(tp->phy_flags & TG3_PHYFLG_PHY_SERDES) &&
9057 !(tp->phy_flags & TG3_PHYFLG_IS_FET)) {
9060 /* Clear CRC stats. */
9061 if (!tg3_readphy(tp, MII_TG3_TEST1, &tmp)) {
9062 tg3_writephy(tp, MII_TG3_TEST1,
9063 tmp | MII_TG3_TEST1_CRC_EN);
9064 tg3_readphy(tp, MII_TG3_RXR_COUNTERS, &tmp);
9069 __tg3_set_rx_mode(tp->dev);
9071 /* Initialize receive rules. */
9072 tw32(MAC_RCV_RULE_0, 0xc2000000 & RCV_RULE_DISABLE_MASK);
9073 tw32(MAC_RCV_VALUE_0, 0xffffffff & RCV_RULE_DISABLE_MASK);
9074 tw32(MAC_RCV_RULE_1, 0x86000004 & RCV_RULE_DISABLE_MASK);
9075 tw32(MAC_RCV_VALUE_1, 0xffffffff & RCV_RULE_DISABLE_MASK);
9077 if (tg3_flag(tp, 5705_PLUS) && !tg3_flag(tp, 5780_CLASS))
9081 if (tg3_flag(tp, ENABLE_ASF))
9085 tw32(MAC_RCV_RULE_15, 0); tw32(MAC_RCV_VALUE_15, 0);
9087 tw32(MAC_RCV_RULE_14, 0); tw32(MAC_RCV_VALUE_14, 0);
9089 tw32(MAC_RCV_RULE_13, 0); tw32(MAC_RCV_VALUE_13, 0);
9091 tw32(MAC_RCV_RULE_12, 0); tw32(MAC_RCV_VALUE_12, 0);
9093 tw32(MAC_RCV_RULE_11, 0); tw32(MAC_RCV_VALUE_11, 0);
9095 tw32(MAC_RCV_RULE_10, 0); tw32(MAC_RCV_VALUE_10, 0);
9097 tw32(MAC_RCV_RULE_9, 0); tw32(MAC_RCV_VALUE_9, 0);
9099 tw32(MAC_RCV_RULE_8, 0); tw32(MAC_RCV_VALUE_8, 0);
9101 tw32(MAC_RCV_RULE_7, 0); tw32(MAC_RCV_VALUE_7, 0);
9103 tw32(MAC_RCV_RULE_6, 0); tw32(MAC_RCV_VALUE_6, 0);
9105 tw32(MAC_RCV_RULE_5, 0); tw32(MAC_RCV_VALUE_5, 0);
9107 tw32(MAC_RCV_RULE_4, 0); tw32(MAC_RCV_VALUE_4, 0);
9109 /* tw32(MAC_RCV_RULE_3, 0); tw32(MAC_RCV_VALUE_3, 0); */
9111 /* tw32(MAC_RCV_RULE_2, 0); tw32(MAC_RCV_VALUE_2, 0); */
9119 if (tg3_flag(tp, ENABLE_APE))
9120 /* Write our heartbeat update interval to APE. */
9121 tg3_ape_write32(tp, TG3_APE_HOST_HEARTBEAT_INT_MS,
9122 APE_HOST_HEARTBEAT_INT_DISABLE);
9124 tg3_write_sig_post_reset(tp, RESET_KIND_INIT);
9129 /* Called at device open time to get the chip ready for
9130 * packet processing. Invoked with tp->lock held.
9132 static int tg3_init_hw(struct tg3 *tp, int reset_phy)
9134 tg3_switch_clocks(tp);
9136 tw32(TG3PCI_MEM_WIN_BASE_ADDR, 0);
9138 return tg3_reset_hw(tp, reset_phy);
9141 #define TG3_STAT_ADD32(PSTAT, REG) \
9142 do { u32 __val = tr32(REG); \
9143 (PSTAT)->low += __val; \
9144 if ((PSTAT)->low < __val) \
9145 (PSTAT)->high += 1; \
9148 static void tg3_periodic_fetch_stats(struct tg3 *tp)
9150 struct tg3_hw_stats *sp = tp->hw_stats;
9152 if (!netif_carrier_ok(tp->dev))
9155 TG3_STAT_ADD32(&sp->tx_octets, MAC_TX_STATS_OCTETS);
9156 TG3_STAT_ADD32(&sp->tx_collisions, MAC_TX_STATS_COLLISIONS);
9157 TG3_STAT_ADD32(&sp->tx_xon_sent, MAC_TX_STATS_XON_SENT);
9158 TG3_STAT_ADD32(&sp->tx_xoff_sent, MAC_TX_STATS_XOFF_SENT);
9159 TG3_STAT_ADD32(&sp->tx_mac_errors, MAC_TX_STATS_MAC_ERRORS);
9160 TG3_STAT_ADD32(&sp->tx_single_collisions, MAC_TX_STATS_SINGLE_COLLISIONS);
9161 TG3_STAT_ADD32(&sp->tx_mult_collisions, MAC_TX_STATS_MULT_COLLISIONS);
9162 TG3_STAT_ADD32(&sp->tx_deferred, MAC_TX_STATS_DEFERRED);
9163 TG3_STAT_ADD32(&sp->tx_excessive_collisions, MAC_TX_STATS_EXCESSIVE_COL);
9164 TG3_STAT_ADD32(&sp->tx_late_collisions, MAC_TX_STATS_LATE_COL);
9165 TG3_STAT_ADD32(&sp->tx_ucast_packets, MAC_TX_STATS_UCAST);
9166 TG3_STAT_ADD32(&sp->tx_mcast_packets, MAC_TX_STATS_MCAST);
9167 TG3_STAT_ADD32(&sp->tx_bcast_packets, MAC_TX_STATS_BCAST);
9169 TG3_STAT_ADD32(&sp->rx_octets, MAC_RX_STATS_OCTETS);
9170 TG3_STAT_ADD32(&sp->rx_fragments, MAC_RX_STATS_FRAGMENTS);
9171 TG3_STAT_ADD32(&sp->rx_ucast_packets, MAC_RX_STATS_UCAST);
9172 TG3_STAT_ADD32(&sp->rx_mcast_packets, MAC_RX_STATS_MCAST);
9173 TG3_STAT_ADD32(&sp->rx_bcast_packets, MAC_RX_STATS_BCAST);
9174 TG3_STAT_ADD32(&sp->rx_fcs_errors, MAC_RX_STATS_FCS_ERRORS);
9175 TG3_STAT_ADD32(&sp->rx_align_errors, MAC_RX_STATS_ALIGN_ERRORS);
9176 TG3_STAT_ADD32(&sp->rx_xon_pause_rcvd, MAC_RX_STATS_XON_PAUSE_RECVD);
9177 TG3_STAT_ADD32(&sp->rx_xoff_pause_rcvd, MAC_RX_STATS_XOFF_PAUSE_RECVD);
9178 TG3_STAT_ADD32(&sp->rx_mac_ctrl_rcvd, MAC_RX_STATS_MAC_CTRL_RECVD);
9179 TG3_STAT_ADD32(&sp->rx_xoff_entered, MAC_RX_STATS_XOFF_ENTERED);
9180 TG3_STAT_ADD32(&sp->rx_frame_too_long_errors, MAC_RX_STATS_FRAME_TOO_LONG);
9181 TG3_STAT_ADD32(&sp->rx_jabbers, MAC_RX_STATS_JABBERS);
9182 TG3_STAT_ADD32(&sp->rx_undersize_packets, MAC_RX_STATS_UNDERSIZE);
9184 TG3_STAT_ADD32(&sp->rxbds_empty, RCVLPC_NO_RCV_BD_CNT);
9185 if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5717 &&
9186 tp->pci_chip_rev_id != CHIPREV_ID_5719_A0 &&
9187 tp->pci_chip_rev_id != CHIPREV_ID_5720_A0) {
9188 TG3_STAT_ADD32(&sp->rx_discards, RCVLPC_IN_DISCARDS_CNT);
9190 u32 val = tr32(HOSTCC_FLOW_ATTN);
9191 val = (val & HOSTCC_FLOW_ATTN_MBUF_LWM) ? 1 : 0;
9193 tw32(HOSTCC_FLOW_ATTN, HOSTCC_FLOW_ATTN_MBUF_LWM);
9194 sp->rx_discards.low += val;
9195 if (sp->rx_discards.low < val)
9196 sp->rx_discards.high += 1;
9198 sp->mbuf_lwm_thresh_hit = sp->rx_discards;
9200 TG3_STAT_ADD32(&sp->rx_errors, RCVLPC_IN_ERRORS_CNT);
9203 static void tg3_chk_missed_msi(struct tg3 *tp)
9207 for (i = 0; i < tp->irq_cnt; i++) {
9208 struct tg3_napi *tnapi = &tp->napi[i];
9210 if (tg3_has_work(tnapi)) {
9211 if (tnapi->last_rx_cons == tnapi->rx_rcb_ptr &&
9212 tnapi->last_tx_cons == tnapi->tx_cons) {
9213 if (tnapi->chk_msi_cnt < 1) {
9214 tnapi->chk_msi_cnt++;
9220 tnapi->chk_msi_cnt = 0;
9221 tnapi->last_rx_cons = tnapi->rx_rcb_ptr;
9222 tnapi->last_tx_cons = tnapi->tx_cons;
9226 static void tg3_timer(unsigned long __opaque)
9228 struct tg3 *tp = (struct tg3 *) __opaque;
9230 if (tp->irq_sync || tg3_flag(tp, RESET_TASK_PENDING))
9233 spin_lock(&tp->lock);
9235 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717 ||
9236 tg3_flag(tp, 57765_CLASS))
9237 tg3_chk_missed_msi(tp);
9239 if (!tg3_flag(tp, TAGGED_STATUS)) {
9240 /* All of this garbage is because when using non-tagged
9241 * IRQ status the mailbox/status_block protocol the chip
9242 * uses with the cpu is race prone.
9244 if (tp->napi[0].hw_status->status & SD_STATUS_UPDATED) {
9245 tw32(GRC_LOCAL_CTRL,
9246 tp->grc_local_ctrl | GRC_LCLCTRL_SETINT);
9248 tw32(HOSTCC_MODE, tp->coalesce_mode |
9249 HOSTCC_MODE_ENABLE | HOSTCC_MODE_NOW);
9252 if (!(tr32(WDMAC_MODE) & WDMAC_MODE_ENABLE)) {
9253 spin_unlock(&tp->lock);
9254 tg3_reset_task_schedule(tp);
9259 /* This part only runs once per second. */
9260 if (!--tp->timer_counter) {
9261 if (tg3_flag(tp, 5705_PLUS))
9262 tg3_periodic_fetch_stats(tp);
9264 if (tp->setlpicnt && !--tp->setlpicnt)
9265 tg3_phy_eee_enable(tp);
9267 if (tg3_flag(tp, USE_LINKCHG_REG)) {
9271 mac_stat = tr32(MAC_STATUS);
9274 if (tp->phy_flags & TG3_PHYFLG_USE_MI_INTERRUPT) {
9275 if (mac_stat & MAC_STATUS_MI_INTERRUPT)
9277 } else if (mac_stat & MAC_STATUS_LNKSTATE_CHANGED)
9281 tg3_setup_phy(tp, 0);
9282 } else if (tg3_flag(tp, POLL_SERDES)) {
9283 u32 mac_stat = tr32(MAC_STATUS);
9286 if (netif_carrier_ok(tp->dev) &&
9287 (mac_stat & MAC_STATUS_LNKSTATE_CHANGED)) {
9290 if (!netif_carrier_ok(tp->dev) &&
9291 (mac_stat & (MAC_STATUS_PCS_SYNCED |
9292 MAC_STATUS_SIGNAL_DET))) {
9296 if (!tp->serdes_counter) {
9299 ~MAC_MODE_PORT_MODE_MASK));
9301 tw32_f(MAC_MODE, tp->mac_mode);
9304 tg3_setup_phy(tp, 0);
9306 } else if ((tp->phy_flags & TG3_PHYFLG_MII_SERDES) &&
9307 tg3_flag(tp, 5780_CLASS)) {
9308 tg3_serdes_parallel_detect(tp);
9311 tp->timer_counter = tp->timer_multiplier;
9314 /* Heartbeat is only sent once every 2 seconds.
9316 * The heartbeat is to tell the ASF firmware that the host
9317 * driver is still alive. In the event that the OS crashes,
9318 * ASF needs to reset the hardware to free up the FIFO space
9319 * that may be filled with rx packets destined for the host.
9320 * If the FIFO is full, ASF will no longer function properly.
9322 * Unintended resets have been reported on real time kernels
9323 * where the timer doesn't run on time. Netpoll will also have
9326 * The new FWCMD_NICDRV_ALIVE3 command tells the ASF firmware
9327 * to check the ring condition when the heartbeat is expiring
9328 * before doing the reset. This will prevent most unintended
9331 if (!--tp->asf_counter) {
9332 if (tg3_flag(tp, ENABLE_ASF) && !tg3_flag(tp, ENABLE_APE)) {
9333 tg3_wait_for_event_ack(tp);
9335 tg3_write_mem(tp, NIC_SRAM_FW_CMD_MBOX,
9336 FWCMD_NICDRV_ALIVE3);
9337 tg3_write_mem(tp, NIC_SRAM_FW_CMD_LEN_MBOX, 4);
9338 tg3_write_mem(tp, NIC_SRAM_FW_CMD_DATA_MBOX,
9339 TG3_FW_UPDATE_TIMEOUT_SEC);
9341 tg3_generate_fw_event(tp);
9343 tp->asf_counter = tp->asf_multiplier;
9346 spin_unlock(&tp->lock);
9349 tp->timer.expires = jiffies + tp->timer_offset;
9350 add_timer(&tp->timer);
9353 static int tg3_request_irq(struct tg3 *tp, int irq_num)
9356 unsigned long flags;
9358 struct tg3_napi *tnapi = &tp->napi[irq_num];
9360 if (tp->irq_cnt == 1)
9361 name = tp->dev->name;
9363 name = &tnapi->irq_lbl[0];
9364 snprintf(name, IFNAMSIZ, "%s-%d", tp->dev->name, irq_num);
9365 name[IFNAMSIZ-1] = 0;
9368 if (tg3_flag(tp, USING_MSI) || tg3_flag(tp, USING_MSIX)) {
9370 if (tg3_flag(tp, 1SHOT_MSI))
9375 if (tg3_flag(tp, TAGGED_STATUS))
9376 fn = tg3_interrupt_tagged;
9377 flags = IRQF_SHARED;
9380 return request_irq(tnapi->irq_vec, fn, flags, name, tnapi);
9383 static int tg3_test_interrupt(struct tg3 *tp)
9385 struct tg3_napi *tnapi = &tp->napi[0];
9386 struct net_device *dev = tp->dev;
9387 int err, i, intr_ok = 0;
9390 if (!netif_running(dev))
9393 tg3_disable_ints(tp);
9395 free_irq(tnapi->irq_vec, tnapi);
9398 * Turn off MSI one shot mode. Otherwise this test has no
9399 * observable way to know whether the interrupt was delivered.
9401 if (tg3_flag(tp, 57765_PLUS)) {
9402 val = tr32(MSGINT_MODE) | MSGINT_MODE_ONE_SHOT_DISABLE;
9403 tw32(MSGINT_MODE, val);
9406 err = request_irq(tnapi->irq_vec, tg3_test_isr,
9407 IRQF_SHARED | IRQF_SAMPLE_RANDOM, dev->name, tnapi);
9411 tnapi->hw_status->status &= ~SD_STATUS_UPDATED;
9412 tg3_enable_ints(tp);
9414 tw32_f(HOSTCC_MODE, tp->coalesce_mode | HOSTCC_MODE_ENABLE |
9417 for (i = 0; i < 5; i++) {
9418 u32 int_mbox, misc_host_ctrl;
9420 int_mbox = tr32_mailbox(tnapi->int_mbox);
9421 misc_host_ctrl = tr32(TG3PCI_MISC_HOST_CTRL);
9423 if ((int_mbox != 0) ||
9424 (misc_host_ctrl & MISC_HOST_CTRL_MASK_PCI_INT)) {
9429 if (tg3_flag(tp, 57765_PLUS) &&
9430 tnapi->hw_status->status_tag != tnapi->last_tag)
9431 tw32_mailbox_f(tnapi->int_mbox, tnapi->last_tag << 24);
9436 tg3_disable_ints(tp);
9438 free_irq(tnapi->irq_vec, tnapi);
9440 err = tg3_request_irq(tp, 0);
9446 /* Reenable MSI one shot mode. */
9447 if (tg3_flag(tp, 57765_PLUS) && tg3_flag(tp, 1SHOT_MSI)) {
9448 val = tr32(MSGINT_MODE) & ~MSGINT_MODE_ONE_SHOT_DISABLE;
9449 tw32(MSGINT_MODE, val);
9457 /* Returns 0 if MSI test succeeds or MSI test fails and INTx mode is
9458 * successfully restored
9460 static int tg3_test_msi(struct tg3 *tp)
9465 if (!tg3_flag(tp, USING_MSI))
9468 /* Turn off SERR reporting in case MSI terminates with Master
9471 pci_read_config_word(tp->pdev, PCI_COMMAND, &pci_cmd);
9472 pci_write_config_word(tp->pdev, PCI_COMMAND,
9473 pci_cmd & ~PCI_COMMAND_SERR);
9475 err = tg3_test_interrupt(tp);
9477 pci_write_config_word(tp->pdev, PCI_COMMAND, pci_cmd);
9482 /* other failures */
9486 /* MSI test failed, go back to INTx mode */
9487 netdev_warn(tp->dev, "No interrupt was generated using MSI. Switching "
9488 "to INTx mode. Please report this failure to the PCI "
9489 "maintainer and include system chipset information\n");
9491 free_irq(tp->napi[0].irq_vec, &tp->napi[0]);
9493 pci_disable_msi(tp->pdev);
9495 tg3_flag_clear(tp, USING_MSI);
9496 tp->napi[0].irq_vec = tp->pdev->irq;
9498 err = tg3_request_irq(tp, 0);
9502 /* Need to reset the chip because the MSI cycle may have terminated
9503 * with Master Abort.
9505 tg3_full_lock(tp, 1);
9507 tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
9508 err = tg3_init_hw(tp, 1);
9510 tg3_full_unlock(tp);
9513 free_irq(tp->napi[0].irq_vec, &tp->napi[0]);
9518 static int tg3_request_firmware(struct tg3 *tp)
9520 const __be32 *fw_data;
9522 if (request_firmware(&tp->fw, tp->fw_needed, &tp->pdev->dev)) {
9523 netdev_err(tp->dev, "Failed to load firmware \"%s\"\n",
9528 fw_data = (void *)tp->fw->data;
9530 /* Firmware blob starts with version numbers, followed by
9531 * start address and _full_ length including BSS sections
9532 * (which must be longer than the actual data, of course
9535 tp->fw_len = be32_to_cpu(fw_data[2]); /* includes bss */
9536 if (tp->fw_len < (tp->fw->size - 12)) {
9537 netdev_err(tp->dev, "bogus length %d in \"%s\"\n",
9538 tp->fw_len, tp->fw_needed);
9539 release_firmware(tp->fw);
9544 /* We no longer need firmware; we have it. */
9545 tp->fw_needed = NULL;
9549 static bool tg3_enable_msix(struct tg3 *tp)
9551 int i, rc, cpus = num_online_cpus();
9552 struct msix_entry msix_ent[tp->irq_max];
9555 /* Just fallback to the simpler MSI mode. */
9559 * We want as many rx rings enabled as there are cpus.
9560 * The first MSIX vector only deals with link interrupts, etc,
9561 * so we add one to the number of vectors we are requesting.
9563 tp->irq_cnt = min_t(unsigned, cpus + 1, tp->irq_max);
9565 for (i = 0; i < tp->irq_max; i++) {
9566 msix_ent[i].entry = i;
9567 msix_ent[i].vector = 0;
9570 rc = pci_enable_msix(tp->pdev, msix_ent, tp->irq_cnt);
9573 } else if (rc != 0) {
9574 if (pci_enable_msix(tp->pdev, msix_ent, rc))
9576 netdev_notice(tp->dev, "Requested %d MSI-X vectors, received %d\n",
9581 for (i = 0; i < tp->irq_max; i++)
9582 tp->napi[i].irq_vec = msix_ent[i].vector;
9584 netif_set_real_num_tx_queues(tp->dev, 1);
9585 rc = tp->irq_cnt > 1 ? tp->irq_cnt - 1 : 1;
9586 if (netif_set_real_num_rx_queues(tp->dev, rc)) {
9587 pci_disable_msix(tp->pdev);
9591 if (tp->irq_cnt > 1) {
9592 tg3_flag_set(tp, ENABLE_RSS);
9594 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5719 ||
9595 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5720) {
9596 tg3_flag_set(tp, ENABLE_TSS);
9597 netif_set_real_num_tx_queues(tp->dev, tp->irq_cnt - 1);
9604 static void tg3_ints_init(struct tg3 *tp)
9606 if ((tg3_flag(tp, SUPPORT_MSI) || tg3_flag(tp, SUPPORT_MSIX)) &&
9607 !tg3_flag(tp, TAGGED_STATUS)) {
9608 /* All MSI supporting chips should support tagged
9609 * status. Assert that this is the case.
9611 netdev_warn(tp->dev,
9612 "MSI without TAGGED_STATUS? Not using MSI\n");
9616 if (tg3_flag(tp, SUPPORT_MSIX) && tg3_enable_msix(tp))
9617 tg3_flag_set(tp, USING_MSIX);
9618 else if (tg3_flag(tp, SUPPORT_MSI) && pci_enable_msi(tp->pdev) == 0)
9619 tg3_flag_set(tp, USING_MSI);
9621 if (tg3_flag(tp, USING_MSI) || tg3_flag(tp, USING_MSIX)) {
9622 u32 msi_mode = tr32(MSGINT_MODE);
9623 if (tg3_flag(tp, USING_MSIX) && tp->irq_cnt > 1)
9624 msi_mode |= MSGINT_MODE_MULTIVEC_EN;
9625 if (!tg3_flag(tp, 1SHOT_MSI))
9626 msi_mode |= MSGINT_MODE_ONE_SHOT_DISABLE;
9627 tw32(MSGINT_MODE, msi_mode | MSGINT_MODE_ENABLE);
9630 if (!tg3_flag(tp, USING_MSIX)) {
9632 tp->napi[0].irq_vec = tp->pdev->irq;
9633 netif_set_real_num_tx_queues(tp->dev, 1);
9634 netif_set_real_num_rx_queues(tp->dev, 1);
9638 static void tg3_ints_fini(struct tg3 *tp)
9640 if (tg3_flag(tp, USING_MSIX))
9641 pci_disable_msix(tp->pdev);
9642 else if (tg3_flag(tp, USING_MSI))
9643 pci_disable_msi(tp->pdev);
9644 tg3_flag_clear(tp, USING_MSI);
9645 tg3_flag_clear(tp, USING_MSIX);
9646 tg3_flag_clear(tp, ENABLE_RSS);
9647 tg3_flag_clear(tp, ENABLE_TSS);
9650 static int tg3_open(struct net_device *dev)
9652 struct tg3 *tp = netdev_priv(dev);
9655 if (tp->fw_needed) {
9656 err = tg3_request_firmware(tp);
9657 if (tp->pci_chip_rev_id == CHIPREV_ID_5701_A0) {
9661 netdev_warn(tp->dev, "TSO capability disabled\n");
9662 tg3_flag_clear(tp, TSO_CAPABLE);
9663 } else if (!tg3_flag(tp, TSO_CAPABLE)) {
9664 netdev_notice(tp->dev, "TSO capability restored\n");
9665 tg3_flag_set(tp, TSO_CAPABLE);
9669 netif_carrier_off(tp->dev);
9671 err = tg3_power_up(tp);
9675 tg3_full_lock(tp, 0);
9677 tg3_disable_ints(tp);
9678 tg3_flag_clear(tp, INIT_COMPLETE);
9680 tg3_full_unlock(tp);
9683 * Setup interrupts first so we know how
9684 * many NAPI resources to allocate
9688 tg3_rss_check_indir_tbl(tp);
9690 /* The placement of this call is tied
9691 * to the setup and use of Host TX descriptors.
9693 err = tg3_alloc_consistent(tp);
9699 tg3_napi_enable(tp);
9701 for (i = 0; i < tp->irq_cnt; i++) {
9702 struct tg3_napi *tnapi = &tp->napi[i];
9703 err = tg3_request_irq(tp, i);
9705 for (i--; i >= 0; i--) {
9706 tnapi = &tp->napi[i];
9707 free_irq(tnapi->irq_vec, tnapi);
9713 tg3_full_lock(tp, 0);
9715 err = tg3_init_hw(tp, 1);
9717 tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
9720 if (tg3_flag(tp, TAGGED_STATUS) &&
9721 GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5717 &&
9722 !tg3_flag(tp, 57765_CLASS))
9723 tp->timer_offset = HZ;
9725 tp->timer_offset = HZ / 10;
9727 BUG_ON(tp->timer_offset > HZ);
9728 tp->timer_counter = tp->timer_multiplier =
9729 (HZ / tp->timer_offset);
9730 tp->asf_counter = tp->asf_multiplier =
9731 ((HZ / tp->timer_offset) * 2);
9733 init_timer(&tp->timer);
9734 tp->timer.expires = jiffies + tp->timer_offset;
9735 tp->timer.data = (unsigned long) tp;
9736 tp->timer.function = tg3_timer;
9739 tg3_full_unlock(tp);
9744 if (tg3_flag(tp, USING_MSI)) {
9745 err = tg3_test_msi(tp);
9748 tg3_full_lock(tp, 0);
9749 tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
9751 tg3_full_unlock(tp);
9756 if (!tg3_flag(tp, 57765_PLUS) && tg3_flag(tp, USING_MSI)) {
9757 u32 val = tr32(PCIE_TRANSACTION_CFG);
9759 tw32(PCIE_TRANSACTION_CFG,
9760 val | PCIE_TRANS_CFG_1SHOT_MSI);
9766 tg3_full_lock(tp, 0);
9768 add_timer(&tp->timer);
9769 tg3_flag_set(tp, INIT_COMPLETE);
9770 tg3_enable_ints(tp);
9772 tg3_full_unlock(tp);
9774 netif_tx_start_all_queues(dev);
9777 * Reset loopback feature if it was turned on while the device was down
9778 * make sure that it's installed properly now.
9780 if (dev->features & NETIF_F_LOOPBACK)
9781 tg3_set_loopback(dev, dev->features);
9786 for (i = tp->irq_cnt - 1; i >= 0; i--) {
9787 struct tg3_napi *tnapi = &tp->napi[i];
9788 free_irq(tnapi->irq_vec, tnapi);
9792 tg3_napi_disable(tp);
9794 tg3_free_consistent(tp);
9798 tg3_frob_aux_power(tp, false);
9799 pci_set_power_state(tp->pdev, PCI_D3hot);
9803 static int tg3_close(struct net_device *dev)
9806 struct tg3 *tp = netdev_priv(dev);
9808 tg3_napi_disable(tp);
9809 tg3_reset_task_cancel(tp);
9811 netif_tx_stop_all_queues(dev);
9813 del_timer_sync(&tp->timer);
9817 tg3_full_lock(tp, 1);
9819 tg3_disable_ints(tp);
9821 tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
9823 tg3_flag_clear(tp, INIT_COMPLETE);
9825 tg3_full_unlock(tp);
9827 for (i = tp->irq_cnt - 1; i >= 0; i--) {
9828 struct tg3_napi *tnapi = &tp->napi[i];
9829 free_irq(tnapi->irq_vec, tnapi);
9834 /* Clear stats across close / open calls */
9835 memset(&tp->net_stats_prev, 0, sizeof(tp->net_stats_prev));
9836 memset(&tp->estats_prev, 0, sizeof(tp->estats_prev));
9840 tg3_free_consistent(tp);
9844 netif_carrier_off(tp->dev);
9849 static inline u64 get_stat64(tg3_stat64_t *val)
9851 return ((u64)val->high << 32) | ((u64)val->low);
9854 static u64 calc_crc_errors(struct tg3 *tp)
9856 struct tg3_hw_stats *hw_stats = tp->hw_stats;
9858 if (!(tp->phy_flags & TG3_PHYFLG_PHY_SERDES) &&
9859 (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
9860 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701)) {
9863 spin_lock_bh(&tp->lock);
9864 if (!tg3_readphy(tp, MII_TG3_TEST1, &val)) {
9865 tg3_writephy(tp, MII_TG3_TEST1,
9866 val | MII_TG3_TEST1_CRC_EN);
9867 tg3_readphy(tp, MII_TG3_RXR_COUNTERS, &val);
9870 spin_unlock_bh(&tp->lock);
9872 tp->phy_crc_errors += val;
9874 return tp->phy_crc_errors;
9877 return get_stat64(&hw_stats->rx_fcs_errors);
9880 #define ESTAT_ADD(member) \
9881 estats->member = old_estats->member + \
9882 get_stat64(&hw_stats->member)
9884 static struct tg3_ethtool_stats *tg3_get_estats(struct tg3 *tp,
9885 struct tg3_ethtool_stats *estats)
9887 struct tg3_ethtool_stats *old_estats = &tp->estats_prev;
9888 struct tg3_hw_stats *hw_stats = tp->hw_stats;
9893 ESTAT_ADD(rx_octets);
9894 ESTAT_ADD(rx_fragments);
9895 ESTAT_ADD(rx_ucast_packets);
9896 ESTAT_ADD(rx_mcast_packets);
9897 ESTAT_ADD(rx_bcast_packets);
9898 ESTAT_ADD(rx_fcs_errors);
9899 ESTAT_ADD(rx_align_errors);
9900 ESTAT_ADD(rx_xon_pause_rcvd);
9901 ESTAT_ADD(rx_xoff_pause_rcvd);
9902 ESTAT_ADD(rx_mac_ctrl_rcvd);
9903 ESTAT_ADD(rx_xoff_entered);
9904 ESTAT_ADD(rx_frame_too_long_errors);
9905 ESTAT_ADD(rx_jabbers);
9906 ESTAT_ADD(rx_undersize_packets);
9907 ESTAT_ADD(rx_in_length_errors);
9908 ESTAT_ADD(rx_out_length_errors);
9909 ESTAT_ADD(rx_64_or_less_octet_packets);
9910 ESTAT_ADD(rx_65_to_127_octet_packets);
9911 ESTAT_ADD(rx_128_to_255_octet_packets);
9912 ESTAT_ADD(rx_256_to_511_octet_packets);
9913 ESTAT_ADD(rx_512_to_1023_octet_packets);
9914 ESTAT_ADD(rx_1024_to_1522_octet_packets);
9915 ESTAT_ADD(rx_1523_to_2047_octet_packets);
9916 ESTAT_ADD(rx_2048_to_4095_octet_packets);
9917 ESTAT_ADD(rx_4096_to_8191_octet_packets);
9918 ESTAT_ADD(rx_8192_to_9022_octet_packets);
9920 ESTAT_ADD(tx_octets);
9921 ESTAT_ADD(tx_collisions);
9922 ESTAT_ADD(tx_xon_sent);
9923 ESTAT_ADD(tx_xoff_sent);
9924 ESTAT_ADD(tx_flow_control);
9925 ESTAT_ADD(tx_mac_errors);
9926 ESTAT_ADD(tx_single_collisions);
9927 ESTAT_ADD(tx_mult_collisions);
9928 ESTAT_ADD(tx_deferred);
9929 ESTAT_ADD(tx_excessive_collisions);
9930 ESTAT_ADD(tx_late_collisions);
9931 ESTAT_ADD(tx_collide_2times);
9932 ESTAT_ADD(tx_collide_3times);
9933 ESTAT_ADD(tx_collide_4times);
9934 ESTAT_ADD(tx_collide_5times);
9935 ESTAT_ADD(tx_collide_6times);
9936 ESTAT_ADD(tx_collide_7times);
9937 ESTAT_ADD(tx_collide_8times);
9938 ESTAT_ADD(tx_collide_9times);
9939 ESTAT_ADD(tx_collide_10times);
9940 ESTAT_ADD(tx_collide_11times);
9941 ESTAT_ADD(tx_collide_12times);
9942 ESTAT_ADD(tx_collide_13times);
9943 ESTAT_ADD(tx_collide_14times);
9944 ESTAT_ADD(tx_collide_15times);
9945 ESTAT_ADD(tx_ucast_packets);
9946 ESTAT_ADD(tx_mcast_packets);
9947 ESTAT_ADD(tx_bcast_packets);
9948 ESTAT_ADD(tx_carrier_sense_errors);
9949 ESTAT_ADD(tx_discards);
9950 ESTAT_ADD(tx_errors);
9952 ESTAT_ADD(dma_writeq_full);
9953 ESTAT_ADD(dma_write_prioq_full);
9954 ESTAT_ADD(rxbds_empty);
9955 ESTAT_ADD(rx_discards);
9956 ESTAT_ADD(rx_errors);
9957 ESTAT_ADD(rx_threshold_hit);
9959 ESTAT_ADD(dma_readq_full);
9960 ESTAT_ADD(dma_read_prioq_full);
9961 ESTAT_ADD(tx_comp_queue_full);
9963 ESTAT_ADD(ring_set_send_prod_index);
9964 ESTAT_ADD(ring_status_update);
9965 ESTAT_ADD(nic_irqs);
9966 ESTAT_ADD(nic_avoided_irqs);
9967 ESTAT_ADD(nic_tx_threshold_hit);
9969 ESTAT_ADD(mbuf_lwm_thresh_hit);
9974 static struct rtnl_link_stats64 *tg3_get_stats64(struct net_device *dev,
9975 struct rtnl_link_stats64 *stats)
9977 struct tg3 *tp = netdev_priv(dev);
9978 struct rtnl_link_stats64 *old_stats = &tp->net_stats_prev;
9979 struct tg3_hw_stats *hw_stats = tp->hw_stats;
9984 stats->rx_packets = old_stats->rx_packets +
9985 get_stat64(&hw_stats->rx_ucast_packets) +
9986 get_stat64(&hw_stats->rx_mcast_packets) +
9987 get_stat64(&hw_stats->rx_bcast_packets);
9989 stats->tx_packets = old_stats->tx_packets +
9990 get_stat64(&hw_stats->tx_ucast_packets) +
9991 get_stat64(&hw_stats->tx_mcast_packets) +
9992 get_stat64(&hw_stats->tx_bcast_packets);
9994 stats->rx_bytes = old_stats->rx_bytes +
9995 get_stat64(&hw_stats->rx_octets);
9996 stats->tx_bytes = old_stats->tx_bytes +
9997 get_stat64(&hw_stats->tx_octets);
9999 stats->rx_errors = old_stats->rx_errors +
10000 get_stat64(&hw_stats->rx_errors);
10001 stats->tx_errors = old_stats->tx_errors +
10002 get_stat64(&hw_stats->tx_errors) +
10003 get_stat64(&hw_stats->tx_mac_errors) +
10004 get_stat64(&hw_stats->tx_carrier_sense_errors) +
10005 get_stat64(&hw_stats->tx_discards);
10007 stats->multicast = old_stats->multicast +
10008 get_stat64(&hw_stats->rx_mcast_packets);
10009 stats->collisions = old_stats->collisions +
10010 get_stat64(&hw_stats->tx_collisions);
10012 stats->rx_length_errors = old_stats->rx_length_errors +
10013 get_stat64(&hw_stats->rx_frame_too_long_errors) +
10014 get_stat64(&hw_stats->rx_undersize_packets);
10016 stats->rx_over_errors = old_stats->rx_over_errors +
10017 get_stat64(&hw_stats->rxbds_empty);
10018 stats->rx_frame_errors = old_stats->rx_frame_errors +
10019 get_stat64(&hw_stats->rx_align_errors);
10020 stats->tx_aborted_errors = old_stats->tx_aborted_errors +
10021 get_stat64(&hw_stats->tx_discards);
10022 stats->tx_carrier_errors = old_stats->tx_carrier_errors +
10023 get_stat64(&hw_stats->tx_carrier_sense_errors);
10025 stats->rx_crc_errors = old_stats->rx_crc_errors +
10026 calc_crc_errors(tp);
10028 stats->rx_missed_errors = old_stats->rx_missed_errors +
10029 get_stat64(&hw_stats->rx_discards);
10031 stats->rx_dropped = tp->rx_dropped;
10032 stats->tx_dropped = tp->tx_dropped;
10037 static inline u32 calc_crc(unsigned char *buf, int len)
10045 for (j = 0; j < len; j++) {
10048 for (k = 0; k < 8; k++) {
10061 static void tg3_set_multi(struct tg3 *tp, unsigned int accept_all)
10063 /* accept or reject all multicast frames */
10064 tw32(MAC_HASH_REG_0, accept_all ? 0xffffffff : 0);
10065 tw32(MAC_HASH_REG_1, accept_all ? 0xffffffff : 0);
10066 tw32(MAC_HASH_REG_2, accept_all ? 0xffffffff : 0);
10067 tw32(MAC_HASH_REG_3, accept_all ? 0xffffffff : 0);
10070 static void __tg3_set_rx_mode(struct net_device *dev)
10072 struct tg3 *tp = netdev_priv(dev);
10075 rx_mode = tp->rx_mode & ~(RX_MODE_PROMISC |
10076 RX_MODE_KEEP_VLAN_TAG);
10078 #if !defined(CONFIG_VLAN_8021Q) && !defined(CONFIG_VLAN_8021Q_MODULE)
10079 /* When ASF is in use, we always keep the RX_MODE_KEEP_VLAN_TAG
10082 if (!tg3_flag(tp, ENABLE_ASF))
10083 rx_mode |= RX_MODE_KEEP_VLAN_TAG;
10086 if (dev->flags & IFF_PROMISC) {
10087 /* Promiscuous mode. */
10088 rx_mode |= RX_MODE_PROMISC;
10089 } else if (dev->flags & IFF_ALLMULTI) {
10090 /* Accept all multicast. */
10091 tg3_set_multi(tp, 1);
10092 } else if (netdev_mc_empty(dev)) {
10093 /* Reject all multicast. */
10094 tg3_set_multi(tp, 0);
10096 /* Accept one or more multicast(s). */
10097 struct netdev_hw_addr *ha;
10098 u32 mc_filter[4] = { 0, };
10103 netdev_for_each_mc_addr(ha, dev) {
10104 crc = calc_crc(ha->addr, ETH_ALEN);
10106 regidx = (bit & 0x60) >> 5;
10108 mc_filter[regidx] |= (1 << bit);
10111 tw32(MAC_HASH_REG_0, mc_filter[0]);
10112 tw32(MAC_HASH_REG_1, mc_filter[1]);
10113 tw32(MAC_HASH_REG_2, mc_filter[2]);
10114 tw32(MAC_HASH_REG_3, mc_filter[3]);
10117 if (rx_mode != tp->rx_mode) {
10118 tp->rx_mode = rx_mode;
10119 tw32_f(MAC_RX_MODE, rx_mode);
10124 static void tg3_set_rx_mode(struct net_device *dev)
10126 struct tg3 *tp = netdev_priv(dev);
10128 if (!netif_running(dev))
10131 tg3_full_lock(tp, 0);
10132 __tg3_set_rx_mode(dev);
10133 tg3_full_unlock(tp);
10136 static int tg3_get_regs_len(struct net_device *dev)
10138 return TG3_REG_BLK_SIZE;
10141 static void tg3_get_regs(struct net_device *dev,
10142 struct ethtool_regs *regs, void *_p)
10144 struct tg3 *tp = netdev_priv(dev);
10148 memset(_p, 0, TG3_REG_BLK_SIZE);
10150 if (tp->phy_flags & TG3_PHYFLG_IS_LOW_POWER)
10153 tg3_full_lock(tp, 0);
10155 tg3_dump_legacy_regs(tp, (u32 *)_p);
10157 tg3_full_unlock(tp);
10160 static int tg3_get_eeprom_len(struct net_device *dev)
10162 struct tg3 *tp = netdev_priv(dev);
10164 return tp->nvram_size;
10167 static int tg3_get_eeprom(struct net_device *dev, struct ethtool_eeprom *eeprom, u8 *data)
10169 struct tg3 *tp = netdev_priv(dev);
10172 u32 i, offset, len, b_offset, b_count;
10175 if (tg3_flag(tp, NO_NVRAM))
10178 if (tp->phy_flags & TG3_PHYFLG_IS_LOW_POWER)
10181 offset = eeprom->offset;
10185 eeprom->magic = TG3_EEPROM_MAGIC;
10188 /* adjustments to start on required 4 byte boundary */
10189 b_offset = offset & 3;
10190 b_count = 4 - b_offset;
10191 if (b_count > len) {
10192 /* i.e. offset=1 len=2 */
10195 ret = tg3_nvram_read_be32(tp, offset-b_offset, &val);
10198 memcpy(data, ((char *)&val) + b_offset, b_count);
10201 eeprom->len += b_count;
10204 /* read bytes up to the last 4 byte boundary */
10205 pd = &data[eeprom->len];
10206 for (i = 0; i < (len - (len & 3)); i += 4) {
10207 ret = tg3_nvram_read_be32(tp, offset + i, &val);
10212 memcpy(pd + i, &val, 4);
10217 /* read last bytes not ending on 4 byte boundary */
10218 pd = &data[eeprom->len];
10220 b_offset = offset + len - b_count;
10221 ret = tg3_nvram_read_be32(tp, b_offset, &val);
10224 memcpy(pd, &val, b_count);
10225 eeprom->len += b_count;
10230 static int tg3_nvram_write_block(struct tg3 *tp, u32 offset, u32 len, u8 *buf);
10232 static int tg3_set_eeprom(struct net_device *dev, struct ethtool_eeprom *eeprom, u8 *data)
10234 struct tg3 *tp = netdev_priv(dev);
10236 u32 offset, len, b_offset, odd_len;
10240 if (tp->phy_flags & TG3_PHYFLG_IS_LOW_POWER)
10243 if (tg3_flag(tp, NO_NVRAM) ||
10244 eeprom->magic != TG3_EEPROM_MAGIC)
10247 offset = eeprom->offset;
10250 if ((b_offset = (offset & 3))) {
10251 /* adjustments to start on required 4 byte boundary */
10252 ret = tg3_nvram_read_be32(tp, offset-b_offset, &start);
10263 /* adjustments to end on required 4 byte boundary */
10265 len = (len + 3) & ~3;
10266 ret = tg3_nvram_read_be32(tp, offset+len-4, &end);
10272 if (b_offset || odd_len) {
10273 buf = kmalloc(len, GFP_KERNEL);
10277 memcpy(buf, &start, 4);
10279 memcpy(buf+len-4, &end, 4);
10280 memcpy(buf + b_offset, data, eeprom->len);
10283 ret = tg3_nvram_write_block(tp, offset, len, buf);
10291 static int tg3_get_settings(struct net_device *dev, struct ethtool_cmd *cmd)
10293 struct tg3 *tp = netdev_priv(dev);
10295 if (tg3_flag(tp, USE_PHYLIB)) {
10296 struct phy_device *phydev;
10297 if (!(tp->phy_flags & TG3_PHYFLG_IS_CONNECTED))
10299 phydev = tp->mdio_bus->phy_map[TG3_PHY_MII_ADDR];
10300 return phy_ethtool_gset(phydev, cmd);
10303 cmd->supported = (SUPPORTED_Autoneg);
10305 if (!(tp->phy_flags & TG3_PHYFLG_10_100_ONLY))
10306 cmd->supported |= (SUPPORTED_1000baseT_Half |
10307 SUPPORTED_1000baseT_Full);
10309 if (!(tp->phy_flags & TG3_PHYFLG_ANY_SERDES)) {
10310 cmd->supported |= (SUPPORTED_100baseT_Half |
10311 SUPPORTED_100baseT_Full |
10312 SUPPORTED_10baseT_Half |
10313 SUPPORTED_10baseT_Full |
10315 cmd->port = PORT_TP;
10317 cmd->supported |= SUPPORTED_FIBRE;
10318 cmd->port = PORT_FIBRE;
10321 cmd->advertising = tp->link_config.advertising;
10322 if (tg3_flag(tp, PAUSE_AUTONEG)) {
10323 if (tp->link_config.flowctrl & FLOW_CTRL_RX) {
10324 if (tp->link_config.flowctrl & FLOW_CTRL_TX) {
10325 cmd->advertising |= ADVERTISED_Pause;
10327 cmd->advertising |= ADVERTISED_Pause |
10328 ADVERTISED_Asym_Pause;
10330 } else if (tp->link_config.flowctrl & FLOW_CTRL_TX) {
10331 cmd->advertising |= ADVERTISED_Asym_Pause;
10334 if (netif_running(dev) && netif_carrier_ok(dev)) {
10335 ethtool_cmd_speed_set(cmd, tp->link_config.active_speed);
10336 cmd->duplex = tp->link_config.active_duplex;
10337 cmd->lp_advertising = tp->link_config.rmt_adv;
10338 if (!(tp->phy_flags & TG3_PHYFLG_ANY_SERDES)) {
10339 if (tp->phy_flags & TG3_PHYFLG_MDIX_STATE)
10340 cmd->eth_tp_mdix = ETH_TP_MDI_X;
10342 cmd->eth_tp_mdix = ETH_TP_MDI;
10345 ethtool_cmd_speed_set(cmd, SPEED_INVALID);
10346 cmd->duplex = DUPLEX_INVALID;
10347 cmd->eth_tp_mdix = ETH_TP_MDI_INVALID;
10349 cmd->phy_address = tp->phy_addr;
10350 cmd->transceiver = XCVR_INTERNAL;
10351 cmd->autoneg = tp->link_config.autoneg;
10357 static int tg3_set_settings(struct net_device *dev, struct ethtool_cmd *cmd)
10359 struct tg3 *tp = netdev_priv(dev);
10360 u32 speed = ethtool_cmd_speed(cmd);
10362 if (tg3_flag(tp, USE_PHYLIB)) {
10363 struct phy_device *phydev;
10364 if (!(tp->phy_flags & TG3_PHYFLG_IS_CONNECTED))
10366 phydev = tp->mdio_bus->phy_map[TG3_PHY_MII_ADDR];
10367 return phy_ethtool_sset(phydev, cmd);
10370 if (cmd->autoneg != AUTONEG_ENABLE &&
10371 cmd->autoneg != AUTONEG_DISABLE)
10374 if (cmd->autoneg == AUTONEG_DISABLE &&
10375 cmd->duplex != DUPLEX_FULL &&
10376 cmd->duplex != DUPLEX_HALF)
10379 if (cmd->autoneg == AUTONEG_ENABLE) {
10380 u32 mask = ADVERTISED_Autoneg |
10382 ADVERTISED_Asym_Pause;
10384 if (!(tp->phy_flags & TG3_PHYFLG_10_100_ONLY))
10385 mask |= ADVERTISED_1000baseT_Half |
10386 ADVERTISED_1000baseT_Full;
10388 if (!(tp->phy_flags & TG3_PHYFLG_ANY_SERDES))
10389 mask |= ADVERTISED_100baseT_Half |
10390 ADVERTISED_100baseT_Full |
10391 ADVERTISED_10baseT_Half |
10392 ADVERTISED_10baseT_Full |
10395 mask |= ADVERTISED_FIBRE;
10397 if (cmd->advertising & ~mask)
10400 mask &= (ADVERTISED_1000baseT_Half |
10401 ADVERTISED_1000baseT_Full |
10402 ADVERTISED_100baseT_Half |
10403 ADVERTISED_100baseT_Full |
10404 ADVERTISED_10baseT_Half |
10405 ADVERTISED_10baseT_Full);
10407 cmd->advertising &= mask;
10409 if (tp->phy_flags & TG3_PHYFLG_ANY_SERDES) {
10410 if (speed != SPEED_1000)
10413 if (cmd->duplex != DUPLEX_FULL)
10416 if (speed != SPEED_100 &&
10422 tg3_full_lock(tp, 0);
10424 tp->link_config.autoneg = cmd->autoneg;
10425 if (cmd->autoneg == AUTONEG_ENABLE) {
10426 tp->link_config.advertising = (cmd->advertising |
10427 ADVERTISED_Autoneg);
10428 tp->link_config.speed = SPEED_INVALID;
10429 tp->link_config.duplex = DUPLEX_INVALID;
10431 tp->link_config.advertising = 0;
10432 tp->link_config.speed = speed;
10433 tp->link_config.duplex = cmd->duplex;
10436 tp->link_config.orig_speed = tp->link_config.speed;
10437 tp->link_config.orig_duplex = tp->link_config.duplex;
10438 tp->link_config.orig_autoneg = tp->link_config.autoneg;
10440 if (netif_running(dev))
10441 tg3_setup_phy(tp, 1);
10443 tg3_full_unlock(tp);
10448 static void tg3_get_drvinfo(struct net_device *dev, struct ethtool_drvinfo *info)
10450 struct tg3 *tp = netdev_priv(dev);
10452 strlcpy(info->driver, DRV_MODULE_NAME, sizeof(info->driver));
10453 strlcpy(info->version, DRV_MODULE_VERSION, sizeof(info->version));
10454 strlcpy(info->fw_version, tp->fw_ver, sizeof(info->fw_version));
10455 strlcpy(info->bus_info, pci_name(tp->pdev), sizeof(info->bus_info));
10458 static void tg3_get_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
10460 struct tg3 *tp = netdev_priv(dev);
10462 if (tg3_flag(tp, WOL_CAP) && device_can_wakeup(&tp->pdev->dev))
10463 wol->supported = WAKE_MAGIC;
10465 wol->supported = 0;
10467 if (tg3_flag(tp, WOL_ENABLE) && device_can_wakeup(&tp->pdev->dev))
10468 wol->wolopts = WAKE_MAGIC;
10469 memset(&wol->sopass, 0, sizeof(wol->sopass));
10472 static int tg3_set_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
10474 struct tg3 *tp = netdev_priv(dev);
10475 struct device *dp = &tp->pdev->dev;
10477 if (wol->wolopts & ~WAKE_MAGIC)
10479 if ((wol->wolopts & WAKE_MAGIC) &&
10480 !(tg3_flag(tp, WOL_CAP) && device_can_wakeup(dp)))
10483 device_set_wakeup_enable(dp, wol->wolopts & WAKE_MAGIC);
10485 spin_lock_bh(&tp->lock);
10486 if (device_may_wakeup(dp))
10487 tg3_flag_set(tp, WOL_ENABLE);
10489 tg3_flag_clear(tp, WOL_ENABLE);
10490 spin_unlock_bh(&tp->lock);
10495 static u32 tg3_get_msglevel(struct net_device *dev)
10497 struct tg3 *tp = netdev_priv(dev);
10498 return tp->msg_enable;
10501 static void tg3_set_msglevel(struct net_device *dev, u32 value)
10503 struct tg3 *tp = netdev_priv(dev);
10504 tp->msg_enable = value;
10507 static int tg3_nway_reset(struct net_device *dev)
10509 struct tg3 *tp = netdev_priv(dev);
10512 if (!netif_running(dev))
10515 if (tp->phy_flags & TG3_PHYFLG_PHY_SERDES)
10518 if (tg3_flag(tp, USE_PHYLIB)) {
10519 if (!(tp->phy_flags & TG3_PHYFLG_IS_CONNECTED))
10521 r = phy_start_aneg(tp->mdio_bus->phy_map[TG3_PHY_MII_ADDR]);
10525 spin_lock_bh(&tp->lock);
10527 tg3_readphy(tp, MII_BMCR, &bmcr);
10528 if (!tg3_readphy(tp, MII_BMCR, &bmcr) &&
10529 ((bmcr & BMCR_ANENABLE) ||
10530 (tp->phy_flags & TG3_PHYFLG_PARALLEL_DETECT))) {
10531 tg3_writephy(tp, MII_BMCR, bmcr | BMCR_ANRESTART |
10535 spin_unlock_bh(&tp->lock);
10541 static void tg3_get_ringparam(struct net_device *dev, struct ethtool_ringparam *ering)
10543 struct tg3 *tp = netdev_priv(dev);
10545 ering->rx_max_pending = tp->rx_std_ring_mask;
10546 if (tg3_flag(tp, JUMBO_RING_ENABLE))
10547 ering->rx_jumbo_max_pending = tp->rx_jmb_ring_mask;
10549 ering->rx_jumbo_max_pending = 0;
10551 ering->tx_max_pending = TG3_TX_RING_SIZE - 1;
10553 ering->rx_pending = tp->rx_pending;
10554 if (tg3_flag(tp, JUMBO_RING_ENABLE))
10555 ering->rx_jumbo_pending = tp->rx_jumbo_pending;
10557 ering->rx_jumbo_pending = 0;
10559 ering->tx_pending = tp->napi[0].tx_pending;
10562 static int tg3_set_ringparam(struct net_device *dev, struct ethtool_ringparam *ering)
10564 struct tg3 *tp = netdev_priv(dev);
10565 int i, irq_sync = 0, err = 0;
10567 if ((ering->rx_pending > tp->rx_std_ring_mask) ||
10568 (ering->rx_jumbo_pending > tp->rx_jmb_ring_mask) ||
10569 (ering->tx_pending > TG3_TX_RING_SIZE - 1) ||
10570 (ering->tx_pending <= MAX_SKB_FRAGS) ||
10571 (tg3_flag(tp, TSO_BUG) &&
10572 (ering->tx_pending <= (MAX_SKB_FRAGS * 3))))
10575 if (netif_running(dev)) {
10577 tg3_netif_stop(tp);
10581 tg3_full_lock(tp, irq_sync);
10583 tp->rx_pending = ering->rx_pending;
10585 if (tg3_flag(tp, MAX_RXPEND_64) &&
10586 tp->rx_pending > 63)
10587 tp->rx_pending = 63;
10588 tp->rx_jumbo_pending = ering->rx_jumbo_pending;
10590 for (i = 0; i < tp->irq_max; i++)
10591 tp->napi[i].tx_pending = ering->tx_pending;
10593 if (netif_running(dev)) {
10594 tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
10595 err = tg3_restart_hw(tp, 1);
10597 tg3_netif_start(tp);
10600 tg3_full_unlock(tp);
10602 if (irq_sync && !err)
10608 static void tg3_get_pauseparam(struct net_device *dev, struct ethtool_pauseparam *epause)
10610 struct tg3 *tp = netdev_priv(dev);
10612 epause->autoneg = !!tg3_flag(tp, PAUSE_AUTONEG);
10614 if (tp->link_config.flowctrl & FLOW_CTRL_RX)
10615 epause->rx_pause = 1;
10617 epause->rx_pause = 0;
10619 if (tp->link_config.flowctrl & FLOW_CTRL_TX)
10620 epause->tx_pause = 1;
10622 epause->tx_pause = 0;
10625 static int tg3_set_pauseparam(struct net_device *dev, struct ethtool_pauseparam *epause)
10627 struct tg3 *tp = netdev_priv(dev);
10630 if (tg3_flag(tp, USE_PHYLIB)) {
10632 struct phy_device *phydev;
10634 phydev = tp->mdio_bus->phy_map[TG3_PHY_MII_ADDR];
10636 if (!(phydev->supported & SUPPORTED_Pause) ||
10637 (!(phydev->supported & SUPPORTED_Asym_Pause) &&
10638 (epause->rx_pause != epause->tx_pause)))
10641 tp->link_config.flowctrl = 0;
10642 if (epause->rx_pause) {
10643 tp->link_config.flowctrl |= FLOW_CTRL_RX;
10645 if (epause->tx_pause) {
10646 tp->link_config.flowctrl |= FLOW_CTRL_TX;
10647 newadv = ADVERTISED_Pause;
10649 newadv = ADVERTISED_Pause |
10650 ADVERTISED_Asym_Pause;
10651 } else if (epause->tx_pause) {
10652 tp->link_config.flowctrl |= FLOW_CTRL_TX;
10653 newadv = ADVERTISED_Asym_Pause;
10657 if (epause->autoneg)
10658 tg3_flag_set(tp, PAUSE_AUTONEG);
10660 tg3_flag_clear(tp, PAUSE_AUTONEG);
10662 if (tp->phy_flags & TG3_PHYFLG_IS_CONNECTED) {
10663 u32 oldadv = phydev->advertising &
10664 (ADVERTISED_Pause | ADVERTISED_Asym_Pause);
10665 if (oldadv != newadv) {
10666 phydev->advertising &=
10667 ~(ADVERTISED_Pause |
10668 ADVERTISED_Asym_Pause);
10669 phydev->advertising |= newadv;
10670 if (phydev->autoneg) {
10672 * Always renegotiate the link to
10673 * inform our link partner of our
10674 * flow control settings, even if the
10675 * flow control is forced. Let
10676 * tg3_adjust_link() do the final
10677 * flow control setup.
10679 return phy_start_aneg(phydev);
10683 if (!epause->autoneg)
10684 tg3_setup_flow_control(tp, 0, 0);
10686 tp->link_config.orig_advertising &=
10687 ~(ADVERTISED_Pause |
10688 ADVERTISED_Asym_Pause);
10689 tp->link_config.orig_advertising |= newadv;
10694 if (netif_running(dev)) {
10695 tg3_netif_stop(tp);
10699 tg3_full_lock(tp, irq_sync);
10701 if (epause->autoneg)
10702 tg3_flag_set(tp, PAUSE_AUTONEG);
10704 tg3_flag_clear(tp, PAUSE_AUTONEG);
10705 if (epause->rx_pause)
10706 tp->link_config.flowctrl |= FLOW_CTRL_RX;
10708 tp->link_config.flowctrl &= ~FLOW_CTRL_RX;
10709 if (epause->tx_pause)
10710 tp->link_config.flowctrl |= FLOW_CTRL_TX;
10712 tp->link_config.flowctrl &= ~FLOW_CTRL_TX;
10714 if (netif_running(dev)) {
10715 tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
10716 err = tg3_restart_hw(tp, 1);
10718 tg3_netif_start(tp);
10721 tg3_full_unlock(tp);
10727 static int tg3_get_sset_count(struct net_device *dev, int sset)
10731 return TG3_NUM_TEST;
10733 return TG3_NUM_STATS;
10735 return -EOPNOTSUPP;
10739 static int tg3_get_rxnfc(struct net_device *dev, struct ethtool_rxnfc *info,
10740 u32 *rules __always_unused)
10742 struct tg3 *tp = netdev_priv(dev);
10744 if (!tg3_flag(tp, SUPPORT_MSIX))
10745 return -EOPNOTSUPP;
10747 switch (info->cmd) {
10748 case ETHTOOL_GRXRINGS:
10749 if (netif_running(tp->dev))
10750 info->data = tp->irq_cnt;
10752 info->data = num_online_cpus();
10753 if (info->data > TG3_IRQ_MAX_VECS_RSS)
10754 info->data = TG3_IRQ_MAX_VECS_RSS;
10757 /* The first interrupt vector only
10758 * handles link interrupts.
10764 return -EOPNOTSUPP;
10768 static u32 tg3_get_rxfh_indir_size(struct net_device *dev)
10771 struct tg3 *tp = netdev_priv(dev);
10773 if (tg3_flag(tp, SUPPORT_MSIX))
10774 size = TG3_RSS_INDIR_TBL_SIZE;
10779 static int tg3_get_rxfh_indir(struct net_device *dev, u32 *indir)
10781 struct tg3 *tp = netdev_priv(dev);
10784 for (i = 0; i < TG3_RSS_INDIR_TBL_SIZE; i++)
10785 indir[i] = tp->rss_ind_tbl[i];
10790 static int tg3_set_rxfh_indir(struct net_device *dev, const u32 *indir)
10792 struct tg3 *tp = netdev_priv(dev);
10795 for (i = 0; i < TG3_RSS_INDIR_TBL_SIZE; i++)
10796 tp->rss_ind_tbl[i] = indir[i];
10798 if (!netif_running(dev) || !tg3_flag(tp, ENABLE_RSS))
10801 /* It is legal to write the indirection
10802 * table while the device is running.
10804 tg3_full_lock(tp, 0);
10805 tg3_rss_write_indir_tbl(tp);
10806 tg3_full_unlock(tp);
10811 static void tg3_get_strings(struct net_device *dev, u32 stringset, u8 *buf)
10813 switch (stringset) {
10815 memcpy(buf, ðtool_stats_keys, sizeof(ethtool_stats_keys));
10818 memcpy(buf, ðtool_test_keys, sizeof(ethtool_test_keys));
10821 WARN_ON(1); /* we need a WARN() */
10826 static int tg3_set_phys_id(struct net_device *dev,
10827 enum ethtool_phys_id_state state)
10829 struct tg3 *tp = netdev_priv(dev);
10831 if (!netif_running(tp->dev))
10835 case ETHTOOL_ID_ACTIVE:
10836 return 1; /* cycle on/off once per second */
10838 case ETHTOOL_ID_ON:
10839 tw32(MAC_LED_CTRL, LED_CTRL_LNKLED_OVERRIDE |
10840 LED_CTRL_1000MBPS_ON |
10841 LED_CTRL_100MBPS_ON |
10842 LED_CTRL_10MBPS_ON |
10843 LED_CTRL_TRAFFIC_OVERRIDE |
10844 LED_CTRL_TRAFFIC_BLINK |
10845 LED_CTRL_TRAFFIC_LED);
10848 case ETHTOOL_ID_OFF:
10849 tw32(MAC_LED_CTRL, LED_CTRL_LNKLED_OVERRIDE |
10850 LED_CTRL_TRAFFIC_OVERRIDE);
10853 case ETHTOOL_ID_INACTIVE:
10854 tw32(MAC_LED_CTRL, tp->led_ctrl);
10861 static void tg3_get_ethtool_stats(struct net_device *dev,
10862 struct ethtool_stats *estats, u64 *tmp_stats)
10864 struct tg3 *tp = netdev_priv(dev);
10866 tg3_get_estats(tp, (struct tg3_ethtool_stats *)tmp_stats);
10869 static __be32 *tg3_vpd_readblock(struct tg3 *tp, u32 *vpdlen)
10873 u32 offset = 0, len = 0;
10876 if (tg3_flag(tp, NO_NVRAM) || tg3_nvram_read(tp, 0, &magic))
10879 if (magic == TG3_EEPROM_MAGIC) {
10880 for (offset = TG3_NVM_DIR_START;
10881 offset < TG3_NVM_DIR_END;
10882 offset += TG3_NVM_DIRENT_SIZE) {
10883 if (tg3_nvram_read(tp, offset, &val))
10886 if ((val >> TG3_NVM_DIRTYPE_SHIFT) ==
10887 TG3_NVM_DIRTYPE_EXTVPD)
10891 if (offset != TG3_NVM_DIR_END) {
10892 len = (val & TG3_NVM_DIRTYPE_LENMSK) * 4;
10893 if (tg3_nvram_read(tp, offset + 4, &offset))
10896 offset = tg3_nvram_logical_addr(tp, offset);
10900 if (!offset || !len) {
10901 offset = TG3_NVM_VPD_OFF;
10902 len = TG3_NVM_VPD_LEN;
10905 buf = kmalloc(len, GFP_KERNEL);
10909 if (magic == TG3_EEPROM_MAGIC) {
10910 for (i = 0; i < len; i += 4) {
10911 /* The data is in little-endian format in NVRAM.
10912 * Use the big-endian read routines to preserve
10913 * the byte order as it exists in NVRAM.
10915 if (tg3_nvram_read_be32(tp, offset + i, &buf[i/4]))
10921 unsigned int pos = 0;
10923 ptr = (u8 *)&buf[0];
10924 for (i = 0; pos < len && i < 3; i++, pos += cnt, ptr += cnt) {
10925 cnt = pci_read_vpd(tp->pdev, pos,
10927 if (cnt == -ETIMEDOUT || cnt == -EINTR)
10945 #define NVRAM_TEST_SIZE 0x100
10946 #define NVRAM_SELFBOOT_FORMAT1_0_SIZE 0x14
10947 #define NVRAM_SELFBOOT_FORMAT1_2_SIZE 0x18
10948 #define NVRAM_SELFBOOT_FORMAT1_3_SIZE 0x1c
10949 #define NVRAM_SELFBOOT_FORMAT1_4_SIZE 0x20
10950 #define NVRAM_SELFBOOT_FORMAT1_5_SIZE 0x24
10951 #define NVRAM_SELFBOOT_FORMAT1_6_SIZE 0x50
10952 #define NVRAM_SELFBOOT_HW_SIZE 0x20
10953 #define NVRAM_SELFBOOT_DATA_SIZE 0x1c
10955 static int tg3_test_nvram(struct tg3 *tp)
10957 u32 csum, magic, len;
10959 int i, j, k, err = 0, size;
10961 if (tg3_flag(tp, NO_NVRAM))
10964 if (tg3_nvram_read(tp, 0, &magic) != 0)
10967 if (magic == TG3_EEPROM_MAGIC)
10968 size = NVRAM_TEST_SIZE;
10969 else if ((magic & TG3_EEPROM_MAGIC_FW_MSK) == TG3_EEPROM_MAGIC_FW) {
10970 if ((magic & TG3_EEPROM_SB_FORMAT_MASK) ==
10971 TG3_EEPROM_SB_FORMAT_1) {
10972 switch (magic & TG3_EEPROM_SB_REVISION_MASK) {
10973 case TG3_EEPROM_SB_REVISION_0:
10974 size = NVRAM_SELFBOOT_FORMAT1_0_SIZE;
10976 case TG3_EEPROM_SB_REVISION_2:
10977 size = NVRAM_SELFBOOT_FORMAT1_2_SIZE;
10979 case TG3_EEPROM_SB_REVISION_3:
10980 size = NVRAM_SELFBOOT_FORMAT1_3_SIZE;
10982 case TG3_EEPROM_SB_REVISION_4:
10983 size = NVRAM_SELFBOOT_FORMAT1_4_SIZE;
10985 case TG3_EEPROM_SB_REVISION_5:
10986 size = NVRAM_SELFBOOT_FORMAT1_5_SIZE;
10988 case TG3_EEPROM_SB_REVISION_6:
10989 size = NVRAM_SELFBOOT_FORMAT1_6_SIZE;
10996 } else if ((magic & TG3_EEPROM_MAGIC_HW_MSK) == TG3_EEPROM_MAGIC_HW)
10997 size = NVRAM_SELFBOOT_HW_SIZE;
11001 buf = kmalloc(size, GFP_KERNEL);
11006 for (i = 0, j = 0; i < size; i += 4, j++) {
11007 err = tg3_nvram_read_be32(tp, i, &buf[j]);
11014 /* Selfboot format */
11015 magic = be32_to_cpu(buf[0]);
11016 if ((magic & TG3_EEPROM_MAGIC_FW_MSK) ==
11017 TG3_EEPROM_MAGIC_FW) {
11018 u8 *buf8 = (u8 *) buf, csum8 = 0;
11020 if ((magic & TG3_EEPROM_SB_REVISION_MASK) ==
11021 TG3_EEPROM_SB_REVISION_2) {
11022 /* For rev 2, the csum doesn't include the MBA. */
11023 for (i = 0; i < TG3_EEPROM_SB_F1R2_MBA_OFF; i++)
11025 for (i = TG3_EEPROM_SB_F1R2_MBA_OFF + 4; i < size; i++)
11028 for (i = 0; i < size; i++)
11041 if ((magic & TG3_EEPROM_MAGIC_HW_MSK) ==
11042 TG3_EEPROM_MAGIC_HW) {
11043 u8 data[NVRAM_SELFBOOT_DATA_SIZE];
11044 u8 parity[NVRAM_SELFBOOT_DATA_SIZE];
11045 u8 *buf8 = (u8 *) buf;
11047 /* Separate the parity bits and the data bytes. */
11048 for (i = 0, j = 0, k = 0; i < NVRAM_SELFBOOT_HW_SIZE; i++) {
11049 if ((i == 0) || (i == 8)) {
11053 for (l = 0, msk = 0x80; l < 7; l++, msk >>= 1)
11054 parity[k++] = buf8[i] & msk;
11056 } else if (i == 16) {
11060 for (l = 0, msk = 0x20; l < 6; l++, msk >>= 1)
11061 parity[k++] = buf8[i] & msk;
11064 for (l = 0, msk = 0x80; l < 8; l++, msk >>= 1)
11065 parity[k++] = buf8[i] & msk;
11068 data[j++] = buf8[i];
11072 for (i = 0; i < NVRAM_SELFBOOT_DATA_SIZE; i++) {
11073 u8 hw8 = hweight8(data[i]);
11075 if ((hw8 & 0x1) && parity[i])
11077 else if (!(hw8 & 0x1) && !parity[i])
11086 /* Bootstrap checksum at offset 0x10 */
11087 csum = calc_crc((unsigned char *) buf, 0x10);
11088 if (csum != le32_to_cpu(buf[0x10/4]))
11091 /* Manufacturing block starts at offset 0x74, checksum at 0xfc */
11092 csum = calc_crc((unsigned char *) &buf[0x74/4], 0x88);
11093 if (csum != le32_to_cpu(buf[0xfc/4]))
11098 buf = tg3_vpd_readblock(tp, &len);
11102 i = pci_vpd_find_tag((u8 *)buf, 0, len, PCI_VPD_LRDT_RO_DATA);
11104 j = pci_vpd_lrdt_size(&((u8 *)buf)[i]);
11108 if (i + PCI_VPD_LRDT_TAG_SIZE + j > len)
11111 i += PCI_VPD_LRDT_TAG_SIZE;
11112 j = pci_vpd_find_info_keyword((u8 *)buf, i, j,
11113 PCI_VPD_RO_KEYWORD_CHKSUM);
11117 j += PCI_VPD_INFO_FLD_HDR_SIZE;
11119 for (i = 0; i <= j; i++)
11120 csum8 += ((u8 *)buf)[i];
11134 #define TG3_SERDES_TIMEOUT_SEC 2
11135 #define TG3_COPPER_TIMEOUT_SEC 6
11137 static int tg3_test_link(struct tg3 *tp)
11141 if (!netif_running(tp->dev))
11144 if (tp->phy_flags & TG3_PHYFLG_ANY_SERDES)
11145 max = TG3_SERDES_TIMEOUT_SEC;
11147 max = TG3_COPPER_TIMEOUT_SEC;
11149 for (i = 0; i < max; i++) {
11150 if (netif_carrier_ok(tp->dev))
11153 if (msleep_interruptible(1000))
11160 /* Only test the commonly used registers */
11161 static int tg3_test_registers(struct tg3 *tp)
11163 int i, is_5705, is_5750;
11164 u32 offset, read_mask, write_mask, val, save_val, read_val;
11168 #define TG3_FL_5705 0x1
11169 #define TG3_FL_NOT_5705 0x2
11170 #define TG3_FL_NOT_5788 0x4
11171 #define TG3_FL_NOT_5750 0x8
11175 /* MAC Control Registers */
11176 { MAC_MODE, TG3_FL_NOT_5705,
11177 0x00000000, 0x00ef6f8c },
11178 { MAC_MODE, TG3_FL_5705,
11179 0x00000000, 0x01ef6b8c },
11180 { MAC_STATUS, TG3_FL_NOT_5705,
11181 0x03800107, 0x00000000 },
11182 { MAC_STATUS, TG3_FL_5705,
11183 0x03800100, 0x00000000 },
11184 { MAC_ADDR_0_HIGH, 0x0000,
11185 0x00000000, 0x0000ffff },
11186 { MAC_ADDR_0_LOW, 0x0000,
11187 0x00000000, 0xffffffff },
11188 { MAC_RX_MTU_SIZE, 0x0000,
11189 0x00000000, 0x0000ffff },
11190 { MAC_TX_MODE, 0x0000,
11191 0x00000000, 0x00000070 },
11192 { MAC_TX_LENGTHS, 0x0000,
11193 0x00000000, 0x00003fff },
11194 { MAC_RX_MODE, TG3_FL_NOT_5705,
11195 0x00000000, 0x000007fc },
11196 { MAC_RX_MODE, TG3_FL_5705,
11197 0x00000000, 0x000007dc },
11198 { MAC_HASH_REG_0, 0x0000,
11199 0x00000000, 0xffffffff },
11200 { MAC_HASH_REG_1, 0x0000,
11201 0x00000000, 0xffffffff },
11202 { MAC_HASH_REG_2, 0x0000,
11203 0x00000000, 0xffffffff },
11204 { MAC_HASH_REG_3, 0x0000,
11205 0x00000000, 0xffffffff },
11207 /* Receive Data and Receive BD Initiator Control Registers. */
11208 { RCVDBDI_JUMBO_BD+0, TG3_FL_NOT_5705,
11209 0x00000000, 0xffffffff },
11210 { RCVDBDI_JUMBO_BD+4, TG3_FL_NOT_5705,
11211 0x00000000, 0xffffffff },
11212 { RCVDBDI_JUMBO_BD+8, TG3_FL_NOT_5705,
11213 0x00000000, 0x00000003 },
11214 { RCVDBDI_JUMBO_BD+0xc, TG3_FL_NOT_5705,
11215 0x00000000, 0xffffffff },
11216 { RCVDBDI_STD_BD+0, 0x0000,
11217 0x00000000, 0xffffffff },
11218 { RCVDBDI_STD_BD+4, 0x0000,
11219 0x00000000, 0xffffffff },
11220 { RCVDBDI_STD_BD+8, 0x0000,
11221 0x00000000, 0xffff0002 },
11222 { RCVDBDI_STD_BD+0xc, 0x0000,
11223 0x00000000, 0xffffffff },
11225 /* Receive BD Initiator Control Registers. */
11226 { RCVBDI_STD_THRESH, TG3_FL_NOT_5705,
11227 0x00000000, 0xffffffff },
11228 { RCVBDI_STD_THRESH, TG3_FL_5705,
11229 0x00000000, 0x000003ff },
11230 { RCVBDI_JUMBO_THRESH, TG3_FL_NOT_5705,
11231 0x00000000, 0xffffffff },
11233 /* Host Coalescing Control Registers. */
11234 { HOSTCC_MODE, TG3_FL_NOT_5705,
11235 0x00000000, 0x00000004 },
11236 { HOSTCC_MODE, TG3_FL_5705,
11237 0x00000000, 0x000000f6 },
11238 { HOSTCC_RXCOL_TICKS, TG3_FL_NOT_5705,
11239 0x00000000, 0xffffffff },
11240 { HOSTCC_RXCOL_TICKS, TG3_FL_5705,
11241 0x00000000, 0x000003ff },
11242 { HOSTCC_TXCOL_TICKS, TG3_FL_NOT_5705,
11243 0x00000000, 0xffffffff },
11244 { HOSTCC_TXCOL_TICKS, TG3_FL_5705,
11245 0x00000000, 0x000003ff },
11246 { HOSTCC_RXMAX_FRAMES, TG3_FL_NOT_5705,
11247 0x00000000, 0xffffffff },
11248 { HOSTCC_RXMAX_FRAMES, TG3_FL_5705 | TG3_FL_NOT_5788,
11249 0x00000000, 0x000000ff },
11250 { HOSTCC_TXMAX_FRAMES, TG3_FL_NOT_5705,
11251 0x00000000, 0xffffffff },
11252 { HOSTCC_TXMAX_FRAMES, TG3_FL_5705 | TG3_FL_NOT_5788,
11253 0x00000000, 0x000000ff },
11254 { HOSTCC_RXCOAL_TICK_INT, TG3_FL_NOT_5705,
11255 0x00000000, 0xffffffff },
11256 { HOSTCC_TXCOAL_TICK_INT, TG3_FL_NOT_5705,
11257 0x00000000, 0xffffffff },
11258 { HOSTCC_RXCOAL_MAXF_INT, TG3_FL_NOT_5705,
11259 0x00000000, 0xffffffff },
11260 { HOSTCC_RXCOAL_MAXF_INT, TG3_FL_5705 | TG3_FL_NOT_5788,
11261 0x00000000, 0x000000ff },
11262 { HOSTCC_TXCOAL_MAXF_INT, TG3_FL_NOT_5705,
11263 0x00000000, 0xffffffff },
11264 { HOSTCC_TXCOAL_MAXF_INT, TG3_FL_5705 | TG3_FL_NOT_5788,
11265 0x00000000, 0x000000ff },
11266 { HOSTCC_STAT_COAL_TICKS, TG3_FL_NOT_5705,
11267 0x00000000, 0xffffffff },
11268 { HOSTCC_STATS_BLK_HOST_ADDR, TG3_FL_NOT_5705,
11269 0x00000000, 0xffffffff },
11270 { HOSTCC_STATS_BLK_HOST_ADDR+4, TG3_FL_NOT_5705,
11271 0x00000000, 0xffffffff },
11272 { HOSTCC_STATUS_BLK_HOST_ADDR, 0x0000,
11273 0x00000000, 0xffffffff },
11274 { HOSTCC_STATUS_BLK_HOST_ADDR+4, 0x0000,
11275 0x00000000, 0xffffffff },
11276 { HOSTCC_STATS_BLK_NIC_ADDR, 0x0000,
11277 0xffffffff, 0x00000000 },
11278 { HOSTCC_STATUS_BLK_NIC_ADDR, 0x0000,
11279 0xffffffff, 0x00000000 },
11281 /* Buffer Manager Control Registers. */
11282 { BUFMGR_MB_POOL_ADDR, TG3_FL_NOT_5750,
11283 0x00000000, 0x007fff80 },
11284 { BUFMGR_MB_POOL_SIZE, TG3_FL_NOT_5750,
11285 0x00000000, 0x007fffff },
11286 { BUFMGR_MB_RDMA_LOW_WATER, 0x0000,
11287 0x00000000, 0x0000003f },
11288 { BUFMGR_MB_MACRX_LOW_WATER, 0x0000,
11289 0x00000000, 0x000001ff },
11290 { BUFMGR_MB_HIGH_WATER, 0x0000,
11291 0x00000000, 0x000001ff },
11292 { BUFMGR_DMA_DESC_POOL_ADDR, TG3_FL_NOT_5705,
11293 0xffffffff, 0x00000000 },
11294 { BUFMGR_DMA_DESC_POOL_SIZE, TG3_FL_NOT_5705,
11295 0xffffffff, 0x00000000 },
11297 /* Mailbox Registers */
11298 { GRCMBOX_RCVSTD_PROD_IDX+4, 0x0000,
11299 0x00000000, 0x000001ff },
11300 { GRCMBOX_RCVJUMBO_PROD_IDX+4, TG3_FL_NOT_5705,
11301 0x00000000, 0x000001ff },
11302 { GRCMBOX_RCVRET_CON_IDX_0+4, 0x0000,
11303 0x00000000, 0x000007ff },
11304 { GRCMBOX_SNDHOST_PROD_IDX_0+4, 0x0000,
11305 0x00000000, 0x000001ff },
11307 { 0xffff, 0x0000, 0x00000000, 0x00000000 },
11310 is_5705 = is_5750 = 0;
11311 if (tg3_flag(tp, 5705_PLUS)) {
11313 if (tg3_flag(tp, 5750_PLUS))
11317 for (i = 0; reg_tbl[i].offset != 0xffff; i++) {
11318 if (is_5705 && (reg_tbl[i].flags & TG3_FL_NOT_5705))
11321 if (!is_5705 && (reg_tbl[i].flags & TG3_FL_5705))
11324 if (tg3_flag(tp, IS_5788) &&
11325 (reg_tbl[i].flags & TG3_FL_NOT_5788))
11328 if (is_5750 && (reg_tbl[i].flags & TG3_FL_NOT_5750))
11331 offset = (u32) reg_tbl[i].offset;
11332 read_mask = reg_tbl[i].read_mask;
11333 write_mask = reg_tbl[i].write_mask;
11335 /* Save the original register content */
11336 save_val = tr32(offset);
11338 /* Determine the read-only value. */
11339 read_val = save_val & read_mask;
11341 /* Write zero to the register, then make sure the read-only bits
11342 * are not changed and the read/write bits are all zeros.
11346 val = tr32(offset);
11348 /* Test the read-only and read/write bits. */
11349 if (((val & read_mask) != read_val) || (val & write_mask))
11352 /* Write ones to all the bits defined by RdMask and WrMask, then
11353 * make sure the read-only bits are not changed and the
11354 * read/write bits are all ones.
11356 tw32(offset, read_mask | write_mask);
11358 val = tr32(offset);
11360 /* Test the read-only bits. */
11361 if ((val & read_mask) != read_val)
11364 /* Test the read/write bits. */
11365 if ((val & write_mask) != write_mask)
11368 tw32(offset, save_val);
11374 if (netif_msg_hw(tp))
11375 netdev_err(tp->dev,
11376 "Register test failed at offset %x\n", offset);
11377 tw32(offset, save_val);
11381 static int tg3_do_mem_test(struct tg3 *tp, u32 offset, u32 len)
11383 static const u32 test_pattern[] = { 0x00000000, 0xffffffff, 0xaa55a55a };
11387 for (i = 0; i < ARRAY_SIZE(test_pattern); i++) {
11388 for (j = 0; j < len; j += 4) {
11391 tg3_write_mem(tp, offset + j, test_pattern[i]);
11392 tg3_read_mem(tp, offset + j, &val);
11393 if (val != test_pattern[i])
11400 static int tg3_test_memory(struct tg3 *tp)
11402 static struct mem_entry {
11405 } mem_tbl_570x[] = {
11406 { 0x00000000, 0x00b50},
11407 { 0x00002000, 0x1c000},
11408 { 0xffffffff, 0x00000}
11409 }, mem_tbl_5705[] = {
11410 { 0x00000100, 0x0000c},
11411 { 0x00000200, 0x00008},
11412 { 0x00004000, 0x00800},
11413 { 0x00006000, 0x01000},
11414 { 0x00008000, 0x02000},
11415 { 0x00010000, 0x0e000},
11416 { 0xffffffff, 0x00000}
11417 }, mem_tbl_5755[] = {
11418 { 0x00000200, 0x00008},
11419 { 0x00004000, 0x00800},
11420 { 0x00006000, 0x00800},
11421 { 0x00008000, 0x02000},
11422 { 0x00010000, 0x0c000},
11423 { 0xffffffff, 0x00000}
11424 }, mem_tbl_5906[] = {
11425 { 0x00000200, 0x00008},
11426 { 0x00004000, 0x00400},
11427 { 0x00006000, 0x00400},
11428 { 0x00008000, 0x01000},
11429 { 0x00010000, 0x01000},
11430 { 0xffffffff, 0x00000}
11431 }, mem_tbl_5717[] = {
11432 { 0x00000200, 0x00008},
11433 { 0x00010000, 0x0a000},
11434 { 0x00020000, 0x13c00},
11435 { 0xffffffff, 0x00000}
11436 }, mem_tbl_57765[] = {
11437 { 0x00000200, 0x00008},
11438 { 0x00004000, 0x00800},
11439 { 0x00006000, 0x09800},
11440 { 0x00010000, 0x0a000},
11441 { 0xffffffff, 0x00000}
11443 struct mem_entry *mem_tbl;
11447 if (tg3_flag(tp, 5717_PLUS))
11448 mem_tbl = mem_tbl_5717;
11449 else if (tg3_flag(tp, 57765_CLASS))
11450 mem_tbl = mem_tbl_57765;
11451 else if (tg3_flag(tp, 5755_PLUS))
11452 mem_tbl = mem_tbl_5755;
11453 else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906)
11454 mem_tbl = mem_tbl_5906;
11455 else if (tg3_flag(tp, 5705_PLUS))
11456 mem_tbl = mem_tbl_5705;
11458 mem_tbl = mem_tbl_570x;
11460 for (i = 0; mem_tbl[i].offset != 0xffffffff; i++) {
11461 err = tg3_do_mem_test(tp, mem_tbl[i].offset, mem_tbl[i].len);
11469 #define TG3_TSO_MSS 500
11471 #define TG3_TSO_IP_HDR_LEN 20
11472 #define TG3_TSO_TCP_HDR_LEN 20
11473 #define TG3_TSO_TCP_OPT_LEN 12
11475 static const u8 tg3_tso_header[] = {
11477 0x45, 0x00, 0x00, 0x00,
11478 0x00, 0x00, 0x40, 0x00,
11479 0x40, 0x06, 0x00, 0x00,
11480 0x0a, 0x00, 0x00, 0x01,
11481 0x0a, 0x00, 0x00, 0x02,
11482 0x0d, 0x00, 0xe0, 0x00,
11483 0x00, 0x00, 0x01, 0x00,
11484 0x00, 0x00, 0x02, 0x00,
11485 0x80, 0x10, 0x10, 0x00,
11486 0x14, 0x09, 0x00, 0x00,
11487 0x01, 0x01, 0x08, 0x0a,
11488 0x11, 0x11, 0x11, 0x11,
11489 0x11, 0x11, 0x11, 0x11,
11492 static int tg3_run_loopback(struct tg3 *tp, u32 pktsz, bool tso_loopback)
11494 u32 rx_start_idx, rx_idx, tx_idx, opaque_key;
11495 u32 base_flags = 0, mss = 0, desc_idx, coal_now, data_off, val;
11497 struct sk_buff *skb;
11498 u8 *tx_data, *rx_data;
11500 int num_pkts, tx_len, rx_len, i, err;
11501 struct tg3_rx_buffer_desc *desc;
11502 struct tg3_napi *tnapi, *rnapi;
11503 struct tg3_rx_prodring_set *tpr = &tp->napi[0].prodring;
11505 tnapi = &tp->napi[0];
11506 rnapi = &tp->napi[0];
11507 if (tp->irq_cnt > 1) {
11508 if (tg3_flag(tp, ENABLE_RSS))
11509 rnapi = &tp->napi[1];
11510 if (tg3_flag(tp, ENABLE_TSS))
11511 tnapi = &tp->napi[1];
11513 coal_now = tnapi->coal_now | rnapi->coal_now;
11518 skb = netdev_alloc_skb(tp->dev, tx_len);
11522 tx_data = skb_put(skb, tx_len);
11523 memcpy(tx_data, tp->dev->dev_addr, 6);
11524 memset(tx_data + 6, 0x0, 8);
11526 tw32(MAC_RX_MTU_SIZE, tx_len + ETH_FCS_LEN);
11528 if (tso_loopback) {
11529 struct iphdr *iph = (struct iphdr *)&tx_data[ETH_HLEN];
11531 u32 hdr_len = TG3_TSO_IP_HDR_LEN + TG3_TSO_TCP_HDR_LEN +
11532 TG3_TSO_TCP_OPT_LEN;
11534 memcpy(tx_data + ETH_ALEN * 2, tg3_tso_header,
11535 sizeof(tg3_tso_header));
11538 val = tx_len - ETH_ALEN * 2 - sizeof(tg3_tso_header);
11539 num_pkts = DIV_ROUND_UP(val, TG3_TSO_MSS);
11541 /* Set the total length field in the IP header */
11542 iph->tot_len = htons((u16)(mss + hdr_len));
11544 base_flags = (TXD_FLAG_CPU_PRE_DMA |
11545 TXD_FLAG_CPU_POST_DMA);
11547 if (tg3_flag(tp, HW_TSO_1) ||
11548 tg3_flag(tp, HW_TSO_2) ||
11549 tg3_flag(tp, HW_TSO_3)) {
11551 val = ETH_HLEN + TG3_TSO_IP_HDR_LEN;
11552 th = (struct tcphdr *)&tx_data[val];
11555 base_flags |= TXD_FLAG_TCPUDP_CSUM;
11557 if (tg3_flag(tp, HW_TSO_3)) {
11558 mss |= (hdr_len & 0xc) << 12;
11559 if (hdr_len & 0x10)
11560 base_flags |= 0x00000010;
11561 base_flags |= (hdr_len & 0x3e0) << 5;
11562 } else if (tg3_flag(tp, HW_TSO_2))
11563 mss |= hdr_len << 9;
11564 else if (tg3_flag(tp, HW_TSO_1) ||
11565 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705) {
11566 mss |= (TG3_TSO_TCP_OPT_LEN << 9);
11568 base_flags |= (TG3_TSO_TCP_OPT_LEN << 10);
11571 data_off = ETH_ALEN * 2 + sizeof(tg3_tso_header);
11574 data_off = ETH_HLEN;
11577 for (i = data_off; i < tx_len; i++)
11578 tx_data[i] = (u8) (i & 0xff);
11580 map = pci_map_single(tp->pdev, skb->data, tx_len, PCI_DMA_TODEVICE);
11581 if (pci_dma_mapping_error(tp->pdev, map)) {
11582 dev_kfree_skb(skb);
11586 val = tnapi->tx_prod;
11587 tnapi->tx_buffers[val].skb = skb;
11588 dma_unmap_addr_set(&tnapi->tx_buffers[val], mapping, map);
11590 tw32_f(HOSTCC_MODE, tp->coalesce_mode | HOSTCC_MODE_ENABLE |
11595 rx_start_idx = rnapi->hw_status->idx[0].rx_producer;
11597 budget = tg3_tx_avail(tnapi);
11598 if (tg3_tx_frag_set(tnapi, &val, &budget, map, tx_len,
11599 base_flags | TXD_FLAG_END, mss, 0)) {
11600 tnapi->tx_buffers[val].skb = NULL;
11601 dev_kfree_skb(skb);
11607 tw32_tx_mbox(tnapi->prodmbox, tnapi->tx_prod);
11608 tr32_mailbox(tnapi->prodmbox);
11612 /* 350 usec to allow enough time on some 10/100 Mbps devices. */
11613 for (i = 0; i < 35; i++) {
11614 tw32_f(HOSTCC_MODE, tp->coalesce_mode | HOSTCC_MODE_ENABLE |
11619 tx_idx = tnapi->hw_status->idx[0].tx_consumer;
11620 rx_idx = rnapi->hw_status->idx[0].rx_producer;
11621 if ((tx_idx == tnapi->tx_prod) &&
11622 (rx_idx == (rx_start_idx + num_pkts)))
11626 tg3_tx_skb_unmap(tnapi, tnapi->tx_prod - 1, -1);
11627 dev_kfree_skb(skb);
11629 if (tx_idx != tnapi->tx_prod)
11632 if (rx_idx != rx_start_idx + num_pkts)
11636 while (rx_idx != rx_start_idx) {
11637 desc = &rnapi->rx_rcb[rx_start_idx++];
11638 desc_idx = desc->opaque & RXD_OPAQUE_INDEX_MASK;
11639 opaque_key = desc->opaque & RXD_OPAQUE_RING_MASK;
11641 if ((desc->err_vlan & RXD_ERR_MASK) != 0 &&
11642 (desc->err_vlan != RXD_ERR_ODD_NIBBLE_RCVD_MII))
11645 rx_len = ((desc->idx_len & RXD_LEN_MASK) >> RXD_LEN_SHIFT)
11648 if (!tso_loopback) {
11649 if (rx_len != tx_len)
11652 if (pktsz <= TG3_RX_STD_DMA_SZ - ETH_FCS_LEN) {
11653 if (opaque_key != RXD_OPAQUE_RING_STD)
11656 if (opaque_key != RXD_OPAQUE_RING_JUMBO)
11659 } else if ((desc->type_flags & RXD_FLAG_TCPUDP_CSUM) &&
11660 (desc->ip_tcp_csum & RXD_TCPCSUM_MASK)
11661 >> RXD_TCPCSUM_SHIFT != 0xffff) {
11665 if (opaque_key == RXD_OPAQUE_RING_STD) {
11666 rx_data = tpr->rx_std_buffers[desc_idx].data;
11667 map = dma_unmap_addr(&tpr->rx_std_buffers[desc_idx],
11669 } else if (opaque_key == RXD_OPAQUE_RING_JUMBO) {
11670 rx_data = tpr->rx_jmb_buffers[desc_idx].data;
11671 map = dma_unmap_addr(&tpr->rx_jmb_buffers[desc_idx],
11676 pci_dma_sync_single_for_cpu(tp->pdev, map, rx_len,
11677 PCI_DMA_FROMDEVICE);
11679 rx_data += TG3_RX_OFFSET(tp);
11680 for (i = data_off; i < rx_len; i++, val++) {
11681 if (*(rx_data + i) != (u8) (val & 0xff))
11688 /* tg3_free_rings will unmap and free the rx_data */
11693 #define TG3_STD_LOOPBACK_FAILED 1
11694 #define TG3_JMB_LOOPBACK_FAILED 2
11695 #define TG3_TSO_LOOPBACK_FAILED 4
11696 #define TG3_LOOPBACK_FAILED \
11697 (TG3_STD_LOOPBACK_FAILED | \
11698 TG3_JMB_LOOPBACK_FAILED | \
11699 TG3_TSO_LOOPBACK_FAILED)
11701 static int tg3_test_loopback(struct tg3 *tp, u64 *data, bool do_extlpbk)
11706 eee_cap = tp->phy_flags & TG3_PHYFLG_EEE_CAP;
11707 tp->phy_flags &= ~TG3_PHYFLG_EEE_CAP;
11709 if (!netif_running(tp->dev)) {
11710 data[0] = TG3_LOOPBACK_FAILED;
11711 data[1] = TG3_LOOPBACK_FAILED;
11713 data[2] = TG3_LOOPBACK_FAILED;
11717 err = tg3_reset_hw(tp, 1);
11719 data[0] = TG3_LOOPBACK_FAILED;
11720 data[1] = TG3_LOOPBACK_FAILED;
11722 data[2] = TG3_LOOPBACK_FAILED;
11726 if (tg3_flag(tp, ENABLE_RSS)) {
11729 /* Reroute all rx packets to the 1st queue */
11730 for (i = MAC_RSS_INDIR_TBL_0;
11731 i < MAC_RSS_INDIR_TBL_0 + TG3_RSS_INDIR_TBL_SIZE; i += 4)
11735 /* HW errata - mac loopback fails in some cases on 5780.
11736 * Normal traffic and PHY loopback are not affected by
11737 * errata. Also, the MAC loopback test is deprecated for
11738 * all newer ASIC revisions.
11740 if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5780 &&
11741 !tg3_flag(tp, CPMU_PRESENT)) {
11742 tg3_mac_loopback(tp, true);
11744 if (tg3_run_loopback(tp, ETH_FRAME_LEN, false))
11745 data[0] |= TG3_STD_LOOPBACK_FAILED;
11747 if (tg3_flag(tp, JUMBO_RING_ENABLE) &&
11748 tg3_run_loopback(tp, 9000 + ETH_HLEN, false))
11749 data[0] |= TG3_JMB_LOOPBACK_FAILED;
11751 tg3_mac_loopback(tp, false);
11754 if (!(tp->phy_flags & TG3_PHYFLG_PHY_SERDES) &&
11755 !tg3_flag(tp, USE_PHYLIB)) {
11758 tg3_phy_lpbk_set(tp, 0, false);
11760 /* Wait for link */
11761 for (i = 0; i < 100; i++) {
11762 if (tr32(MAC_TX_STATUS) & TX_STATUS_LINK_UP)
11767 if (tg3_run_loopback(tp, ETH_FRAME_LEN, false))
11768 data[1] |= TG3_STD_LOOPBACK_FAILED;
11769 if (tg3_flag(tp, TSO_CAPABLE) &&
11770 tg3_run_loopback(tp, ETH_FRAME_LEN, true))
11771 data[1] |= TG3_TSO_LOOPBACK_FAILED;
11772 if (tg3_flag(tp, JUMBO_RING_ENABLE) &&
11773 tg3_run_loopback(tp, 9000 + ETH_HLEN, false))
11774 data[1] |= TG3_JMB_LOOPBACK_FAILED;
11777 tg3_phy_lpbk_set(tp, 0, true);
11779 /* All link indications report up, but the hardware
11780 * isn't really ready for about 20 msec. Double it
11785 if (tg3_run_loopback(tp, ETH_FRAME_LEN, false))
11786 data[2] |= TG3_STD_LOOPBACK_FAILED;
11787 if (tg3_flag(tp, TSO_CAPABLE) &&
11788 tg3_run_loopback(tp, ETH_FRAME_LEN, true))
11789 data[2] |= TG3_TSO_LOOPBACK_FAILED;
11790 if (tg3_flag(tp, JUMBO_RING_ENABLE) &&
11791 tg3_run_loopback(tp, 9000 + ETH_HLEN, false))
11792 data[2] |= TG3_JMB_LOOPBACK_FAILED;
11795 /* Re-enable gphy autopowerdown. */
11796 if (tp->phy_flags & TG3_PHYFLG_ENABLE_APD)
11797 tg3_phy_toggle_apd(tp, true);
11800 err = (data[0] | data[1] | data[2]) ? -EIO : 0;
11803 tp->phy_flags |= eee_cap;
11808 static void tg3_self_test(struct net_device *dev, struct ethtool_test *etest,
11811 struct tg3 *tp = netdev_priv(dev);
11812 bool doextlpbk = etest->flags & ETH_TEST_FL_EXTERNAL_LB;
11814 if ((tp->phy_flags & TG3_PHYFLG_IS_LOW_POWER) &&
11815 tg3_power_up(tp)) {
11816 etest->flags |= ETH_TEST_FL_FAILED;
11817 memset(data, 1, sizeof(u64) * TG3_NUM_TEST);
11821 memset(data, 0, sizeof(u64) * TG3_NUM_TEST);
11823 if (tg3_test_nvram(tp) != 0) {
11824 etest->flags |= ETH_TEST_FL_FAILED;
11827 if (!doextlpbk && tg3_test_link(tp)) {
11828 etest->flags |= ETH_TEST_FL_FAILED;
11831 if (etest->flags & ETH_TEST_FL_OFFLINE) {
11832 int err, err2 = 0, irq_sync = 0;
11834 if (netif_running(dev)) {
11836 tg3_netif_stop(tp);
11840 tg3_full_lock(tp, irq_sync);
11842 tg3_halt(tp, RESET_KIND_SUSPEND, 1);
11843 err = tg3_nvram_lock(tp);
11844 tg3_halt_cpu(tp, RX_CPU_BASE);
11845 if (!tg3_flag(tp, 5705_PLUS))
11846 tg3_halt_cpu(tp, TX_CPU_BASE);
11848 tg3_nvram_unlock(tp);
11850 if (tp->phy_flags & TG3_PHYFLG_MII_SERDES)
11853 if (tg3_test_registers(tp) != 0) {
11854 etest->flags |= ETH_TEST_FL_FAILED;
11858 if (tg3_test_memory(tp) != 0) {
11859 etest->flags |= ETH_TEST_FL_FAILED;
11864 etest->flags |= ETH_TEST_FL_EXTERNAL_LB_DONE;
11866 if (tg3_test_loopback(tp, &data[4], doextlpbk))
11867 etest->flags |= ETH_TEST_FL_FAILED;
11869 tg3_full_unlock(tp);
11871 if (tg3_test_interrupt(tp) != 0) {
11872 etest->flags |= ETH_TEST_FL_FAILED;
11876 tg3_full_lock(tp, 0);
11878 tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
11879 if (netif_running(dev)) {
11880 tg3_flag_set(tp, INIT_COMPLETE);
11881 err2 = tg3_restart_hw(tp, 1);
11883 tg3_netif_start(tp);
11886 tg3_full_unlock(tp);
11888 if (irq_sync && !err2)
11891 if (tp->phy_flags & TG3_PHYFLG_IS_LOW_POWER)
11892 tg3_power_down(tp);
11896 static int tg3_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd)
11898 struct mii_ioctl_data *data = if_mii(ifr);
11899 struct tg3 *tp = netdev_priv(dev);
11902 if (tg3_flag(tp, USE_PHYLIB)) {
11903 struct phy_device *phydev;
11904 if (!(tp->phy_flags & TG3_PHYFLG_IS_CONNECTED))
11906 phydev = tp->mdio_bus->phy_map[TG3_PHY_MII_ADDR];
11907 return phy_mii_ioctl(phydev, ifr, cmd);
11912 data->phy_id = tp->phy_addr;
11915 case SIOCGMIIREG: {
11918 if (tp->phy_flags & TG3_PHYFLG_PHY_SERDES)
11919 break; /* We have no PHY */
11921 if (!netif_running(dev))
11924 spin_lock_bh(&tp->lock);
11925 err = tg3_readphy(tp, data->reg_num & 0x1f, &mii_regval);
11926 spin_unlock_bh(&tp->lock);
11928 data->val_out = mii_regval;
11934 if (tp->phy_flags & TG3_PHYFLG_PHY_SERDES)
11935 break; /* We have no PHY */
11937 if (!netif_running(dev))
11940 spin_lock_bh(&tp->lock);
11941 err = tg3_writephy(tp, data->reg_num & 0x1f, data->val_in);
11942 spin_unlock_bh(&tp->lock);
11950 return -EOPNOTSUPP;
11953 static int tg3_get_coalesce(struct net_device *dev, struct ethtool_coalesce *ec)
11955 struct tg3 *tp = netdev_priv(dev);
11957 memcpy(ec, &tp->coal, sizeof(*ec));
11961 static int tg3_set_coalesce(struct net_device *dev, struct ethtool_coalesce *ec)
11963 struct tg3 *tp = netdev_priv(dev);
11964 u32 max_rxcoal_tick_int = 0, max_txcoal_tick_int = 0;
11965 u32 max_stat_coal_ticks = 0, min_stat_coal_ticks = 0;
11967 if (!tg3_flag(tp, 5705_PLUS)) {
11968 max_rxcoal_tick_int = MAX_RXCOAL_TICK_INT;
11969 max_txcoal_tick_int = MAX_TXCOAL_TICK_INT;
11970 max_stat_coal_ticks = MAX_STAT_COAL_TICKS;
11971 min_stat_coal_ticks = MIN_STAT_COAL_TICKS;
11974 if ((ec->rx_coalesce_usecs > MAX_RXCOL_TICKS) ||
11975 (ec->tx_coalesce_usecs > MAX_TXCOL_TICKS) ||
11976 (ec->rx_max_coalesced_frames > MAX_RXMAX_FRAMES) ||
11977 (ec->tx_max_coalesced_frames > MAX_TXMAX_FRAMES) ||
11978 (ec->rx_coalesce_usecs_irq > max_rxcoal_tick_int) ||
11979 (ec->tx_coalesce_usecs_irq > max_txcoal_tick_int) ||
11980 (ec->rx_max_coalesced_frames_irq > MAX_RXCOAL_MAXF_INT) ||
11981 (ec->tx_max_coalesced_frames_irq > MAX_TXCOAL_MAXF_INT) ||
11982 (ec->stats_block_coalesce_usecs > max_stat_coal_ticks) ||
11983 (ec->stats_block_coalesce_usecs < min_stat_coal_ticks))
11986 /* No rx interrupts will be generated if both are zero */
11987 if ((ec->rx_coalesce_usecs == 0) &&
11988 (ec->rx_max_coalesced_frames == 0))
11991 /* No tx interrupts will be generated if both are zero */
11992 if ((ec->tx_coalesce_usecs == 0) &&
11993 (ec->tx_max_coalesced_frames == 0))
11996 /* Only copy relevant parameters, ignore all others. */
11997 tp->coal.rx_coalesce_usecs = ec->rx_coalesce_usecs;
11998 tp->coal.tx_coalesce_usecs = ec->tx_coalesce_usecs;
11999 tp->coal.rx_max_coalesced_frames = ec->rx_max_coalesced_frames;
12000 tp->coal.tx_max_coalesced_frames = ec->tx_max_coalesced_frames;
12001 tp->coal.rx_coalesce_usecs_irq = ec->rx_coalesce_usecs_irq;
12002 tp->coal.tx_coalesce_usecs_irq = ec->tx_coalesce_usecs_irq;
12003 tp->coal.rx_max_coalesced_frames_irq = ec->rx_max_coalesced_frames_irq;
12004 tp->coal.tx_max_coalesced_frames_irq = ec->tx_max_coalesced_frames_irq;
12005 tp->coal.stats_block_coalesce_usecs = ec->stats_block_coalesce_usecs;
12007 if (netif_running(dev)) {
12008 tg3_full_lock(tp, 0);
12009 __tg3_set_coalesce(tp, &tp->coal);
12010 tg3_full_unlock(tp);
12015 static const struct ethtool_ops tg3_ethtool_ops = {
12016 .get_settings = tg3_get_settings,
12017 .set_settings = tg3_set_settings,
12018 .get_drvinfo = tg3_get_drvinfo,
12019 .get_regs_len = tg3_get_regs_len,
12020 .get_regs = tg3_get_regs,
12021 .get_wol = tg3_get_wol,
12022 .set_wol = tg3_set_wol,
12023 .get_msglevel = tg3_get_msglevel,
12024 .set_msglevel = tg3_set_msglevel,
12025 .nway_reset = tg3_nway_reset,
12026 .get_link = ethtool_op_get_link,
12027 .get_eeprom_len = tg3_get_eeprom_len,
12028 .get_eeprom = tg3_get_eeprom,
12029 .set_eeprom = tg3_set_eeprom,
12030 .get_ringparam = tg3_get_ringparam,
12031 .set_ringparam = tg3_set_ringparam,
12032 .get_pauseparam = tg3_get_pauseparam,
12033 .set_pauseparam = tg3_set_pauseparam,
12034 .self_test = tg3_self_test,
12035 .get_strings = tg3_get_strings,
12036 .set_phys_id = tg3_set_phys_id,
12037 .get_ethtool_stats = tg3_get_ethtool_stats,
12038 .get_coalesce = tg3_get_coalesce,
12039 .set_coalesce = tg3_set_coalesce,
12040 .get_sset_count = tg3_get_sset_count,
12041 .get_rxnfc = tg3_get_rxnfc,
12042 .get_rxfh_indir_size = tg3_get_rxfh_indir_size,
12043 .get_rxfh_indir = tg3_get_rxfh_indir,
12044 .set_rxfh_indir = tg3_set_rxfh_indir,
12047 static void __devinit tg3_get_eeprom_size(struct tg3 *tp)
12049 u32 cursize, val, magic;
12051 tp->nvram_size = EEPROM_CHIP_SIZE;
12053 if (tg3_nvram_read(tp, 0, &magic) != 0)
12056 if ((magic != TG3_EEPROM_MAGIC) &&
12057 ((magic & TG3_EEPROM_MAGIC_FW_MSK) != TG3_EEPROM_MAGIC_FW) &&
12058 ((magic & TG3_EEPROM_MAGIC_HW_MSK) != TG3_EEPROM_MAGIC_HW))
12062 * Size the chip by reading offsets at increasing powers of two.
12063 * When we encounter our validation signature, we know the addressing
12064 * has wrapped around, and thus have our chip size.
12068 while (cursize < tp->nvram_size) {
12069 if (tg3_nvram_read(tp, cursize, &val) != 0)
12078 tp->nvram_size = cursize;
12081 static void __devinit tg3_get_nvram_size(struct tg3 *tp)
12085 if (tg3_flag(tp, NO_NVRAM) || tg3_nvram_read(tp, 0, &val) != 0)
12088 /* Selfboot format */
12089 if (val != TG3_EEPROM_MAGIC) {
12090 tg3_get_eeprom_size(tp);
12094 if (tg3_nvram_read(tp, 0xf0, &val) == 0) {
12096 /* This is confusing. We want to operate on the
12097 * 16-bit value at offset 0xf2. The tg3_nvram_read()
12098 * call will read from NVRAM and byteswap the data
12099 * according to the byteswapping settings for all
12100 * other register accesses. This ensures the data we
12101 * want will always reside in the lower 16-bits.
12102 * However, the data in NVRAM is in LE format, which
12103 * means the data from the NVRAM read will always be
12104 * opposite the endianness of the CPU. The 16-bit
12105 * byteswap then brings the data to CPU endianness.
12107 tp->nvram_size = swab16((u16)(val & 0x0000ffff)) * 1024;
12111 tp->nvram_size = TG3_NVRAM_SIZE_512KB;
12114 static void __devinit tg3_get_nvram_info(struct tg3 *tp)
12118 nvcfg1 = tr32(NVRAM_CFG1);
12119 if (nvcfg1 & NVRAM_CFG1_FLASHIF_ENAB) {
12120 tg3_flag_set(tp, FLASH);
12122 nvcfg1 &= ~NVRAM_CFG1_COMPAT_BYPASS;
12123 tw32(NVRAM_CFG1, nvcfg1);
12126 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5750 ||
12127 tg3_flag(tp, 5780_CLASS)) {
12128 switch (nvcfg1 & NVRAM_CFG1_VENDOR_MASK) {
12129 case FLASH_VENDOR_ATMEL_FLASH_BUFFERED:
12130 tp->nvram_jedecnum = JEDEC_ATMEL;
12131 tp->nvram_pagesize = ATMEL_AT45DB0X1B_PAGE_SIZE;
12132 tg3_flag_set(tp, NVRAM_BUFFERED);
12134 case FLASH_VENDOR_ATMEL_FLASH_UNBUFFERED:
12135 tp->nvram_jedecnum = JEDEC_ATMEL;
12136 tp->nvram_pagesize = ATMEL_AT25F512_PAGE_SIZE;
12138 case FLASH_VENDOR_ATMEL_EEPROM:
12139 tp->nvram_jedecnum = JEDEC_ATMEL;
12140 tp->nvram_pagesize = ATMEL_AT24C512_CHIP_SIZE;
12141 tg3_flag_set(tp, NVRAM_BUFFERED);
12143 case FLASH_VENDOR_ST:
12144 tp->nvram_jedecnum = JEDEC_ST;
12145 tp->nvram_pagesize = ST_M45PEX0_PAGE_SIZE;
12146 tg3_flag_set(tp, NVRAM_BUFFERED);
12148 case FLASH_VENDOR_SAIFUN:
12149 tp->nvram_jedecnum = JEDEC_SAIFUN;
12150 tp->nvram_pagesize = SAIFUN_SA25F0XX_PAGE_SIZE;
12152 case FLASH_VENDOR_SST_SMALL:
12153 case FLASH_VENDOR_SST_LARGE:
12154 tp->nvram_jedecnum = JEDEC_SST;
12155 tp->nvram_pagesize = SST_25VF0X0_PAGE_SIZE;
12159 tp->nvram_jedecnum = JEDEC_ATMEL;
12160 tp->nvram_pagesize = ATMEL_AT45DB0X1B_PAGE_SIZE;
12161 tg3_flag_set(tp, NVRAM_BUFFERED);
12165 static void __devinit tg3_nvram_get_pagesize(struct tg3 *tp, u32 nvmcfg1)
12167 switch (nvmcfg1 & NVRAM_CFG1_5752PAGE_SIZE_MASK) {
12168 case FLASH_5752PAGE_SIZE_256:
12169 tp->nvram_pagesize = 256;
12171 case FLASH_5752PAGE_SIZE_512:
12172 tp->nvram_pagesize = 512;
12174 case FLASH_5752PAGE_SIZE_1K:
12175 tp->nvram_pagesize = 1024;
12177 case FLASH_5752PAGE_SIZE_2K:
12178 tp->nvram_pagesize = 2048;
12180 case FLASH_5752PAGE_SIZE_4K:
12181 tp->nvram_pagesize = 4096;
12183 case FLASH_5752PAGE_SIZE_264:
12184 tp->nvram_pagesize = 264;
12186 case FLASH_5752PAGE_SIZE_528:
12187 tp->nvram_pagesize = 528;
12192 static void __devinit tg3_get_5752_nvram_info(struct tg3 *tp)
12196 nvcfg1 = tr32(NVRAM_CFG1);
12198 /* NVRAM protection for TPM */
12199 if (nvcfg1 & (1 << 27))
12200 tg3_flag_set(tp, PROTECTED_NVRAM);
12202 switch (nvcfg1 & NVRAM_CFG1_5752VENDOR_MASK) {
12203 case FLASH_5752VENDOR_ATMEL_EEPROM_64KHZ:
12204 case FLASH_5752VENDOR_ATMEL_EEPROM_376KHZ:
12205 tp->nvram_jedecnum = JEDEC_ATMEL;
12206 tg3_flag_set(tp, NVRAM_BUFFERED);
12208 case FLASH_5752VENDOR_ATMEL_FLASH_BUFFERED:
12209 tp->nvram_jedecnum = JEDEC_ATMEL;
12210 tg3_flag_set(tp, NVRAM_BUFFERED);
12211 tg3_flag_set(tp, FLASH);
12213 case FLASH_5752VENDOR_ST_M45PE10:
12214 case FLASH_5752VENDOR_ST_M45PE20:
12215 case FLASH_5752VENDOR_ST_M45PE40:
12216 tp->nvram_jedecnum = JEDEC_ST;
12217 tg3_flag_set(tp, NVRAM_BUFFERED);
12218 tg3_flag_set(tp, FLASH);
12222 if (tg3_flag(tp, FLASH)) {
12223 tg3_nvram_get_pagesize(tp, nvcfg1);
12225 /* For eeprom, set pagesize to maximum eeprom size */
12226 tp->nvram_pagesize = ATMEL_AT24C512_CHIP_SIZE;
12228 nvcfg1 &= ~NVRAM_CFG1_COMPAT_BYPASS;
12229 tw32(NVRAM_CFG1, nvcfg1);
12233 static void __devinit tg3_get_5755_nvram_info(struct tg3 *tp)
12235 u32 nvcfg1, protect = 0;
12237 nvcfg1 = tr32(NVRAM_CFG1);
12239 /* NVRAM protection for TPM */
12240 if (nvcfg1 & (1 << 27)) {
12241 tg3_flag_set(tp, PROTECTED_NVRAM);
12245 nvcfg1 &= NVRAM_CFG1_5752VENDOR_MASK;
12247 case FLASH_5755VENDOR_ATMEL_FLASH_1:
12248 case FLASH_5755VENDOR_ATMEL_FLASH_2:
12249 case FLASH_5755VENDOR_ATMEL_FLASH_3:
12250 case FLASH_5755VENDOR_ATMEL_FLASH_5:
12251 tp->nvram_jedecnum = JEDEC_ATMEL;
12252 tg3_flag_set(tp, NVRAM_BUFFERED);
12253 tg3_flag_set(tp, FLASH);
12254 tp->nvram_pagesize = 264;
12255 if (nvcfg1 == FLASH_5755VENDOR_ATMEL_FLASH_1 ||
12256 nvcfg1 == FLASH_5755VENDOR_ATMEL_FLASH_5)
12257 tp->nvram_size = (protect ? 0x3e200 :
12258 TG3_NVRAM_SIZE_512KB);
12259 else if (nvcfg1 == FLASH_5755VENDOR_ATMEL_FLASH_2)
12260 tp->nvram_size = (protect ? 0x1f200 :
12261 TG3_NVRAM_SIZE_256KB);
12263 tp->nvram_size = (protect ? 0x1f200 :
12264 TG3_NVRAM_SIZE_128KB);
12266 case FLASH_5752VENDOR_ST_M45PE10:
12267 case FLASH_5752VENDOR_ST_M45PE20:
12268 case FLASH_5752VENDOR_ST_M45PE40:
12269 tp->nvram_jedecnum = JEDEC_ST;
12270 tg3_flag_set(tp, NVRAM_BUFFERED);
12271 tg3_flag_set(tp, FLASH);
12272 tp->nvram_pagesize = 256;
12273 if (nvcfg1 == FLASH_5752VENDOR_ST_M45PE10)
12274 tp->nvram_size = (protect ?
12275 TG3_NVRAM_SIZE_64KB :
12276 TG3_NVRAM_SIZE_128KB);
12277 else if (nvcfg1 == FLASH_5752VENDOR_ST_M45PE20)
12278 tp->nvram_size = (protect ?
12279 TG3_NVRAM_SIZE_64KB :
12280 TG3_NVRAM_SIZE_256KB);
12282 tp->nvram_size = (protect ?
12283 TG3_NVRAM_SIZE_128KB :
12284 TG3_NVRAM_SIZE_512KB);
12289 static void __devinit tg3_get_5787_nvram_info(struct tg3 *tp)
12293 nvcfg1 = tr32(NVRAM_CFG1);
12295 switch (nvcfg1 & NVRAM_CFG1_5752VENDOR_MASK) {
12296 case FLASH_5787VENDOR_ATMEL_EEPROM_64KHZ:
12297 case FLASH_5787VENDOR_ATMEL_EEPROM_376KHZ:
12298 case FLASH_5787VENDOR_MICRO_EEPROM_64KHZ:
12299 case FLASH_5787VENDOR_MICRO_EEPROM_376KHZ:
12300 tp->nvram_jedecnum = JEDEC_ATMEL;
12301 tg3_flag_set(tp, NVRAM_BUFFERED);
12302 tp->nvram_pagesize = ATMEL_AT24C512_CHIP_SIZE;
12304 nvcfg1 &= ~NVRAM_CFG1_COMPAT_BYPASS;
12305 tw32(NVRAM_CFG1, nvcfg1);
12307 case FLASH_5752VENDOR_ATMEL_FLASH_BUFFERED:
12308 case FLASH_5755VENDOR_ATMEL_FLASH_1:
12309 case FLASH_5755VENDOR_ATMEL_FLASH_2:
12310 case FLASH_5755VENDOR_ATMEL_FLASH_3:
12311 tp->nvram_jedecnum = JEDEC_ATMEL;
12312 tg3_flag_set(tp, NVRAM_BUFFERED);
12313 tg3_flag_set(tp, FLASH);
12314 tp->nvram_pagesize = 264;
12316 case FLASH_5752VENDOR_ST_M45PE10:
12317 case FLASH_5752VENDOR_ST_M45PE20:
12318 case FLASH_5752VENDOR_ST_M45PE40:
12319 tp->nvram_jedecnum = JEDEC_ST;
12320 tg3_flag_set(tp, NVRAM_BUFFERED);
12321 tg3_flag_set(tp, FLASH);
12322 tp->nvram_pagesize = 256;
12327 static void __devinit tg3_get_5761_nvram_info(struct tg3 *tp)
12329 u32 nvcfg1, protect = 0;
12331 nvcfg1 = tr32(NVRAM_CFG1);
12333 /* NVRAM protection for TPM */
12334 if (nvcfg1 & (1 << 27)) {
12335 tg3_flag_set(tp, PROTECTED_NVRAM);
12339 nvcfg1 &= NVRAM_CFG1_5752VENDOR_MASK;
12341 case FLASH_5761VENDOR_ATMEL_ADB021D:
12342 case FLASH_5761VENDOR_ATMEL_ADB041D:
12343 case FLASH_5761VENDOR_ATMEL_ADB081D:
12344 case FLASH_5761VENDOR_ATMEL_ADB161D:
12345 case FLASH_5761VENDOR_ATMEL_MDB021D:
12346 case FLASH_5761VENDOR_ATMEL_MDB041D:
12347 case FLASH_5761VENDOR_ATMEL_MDB081D:
12348 case FLASH_5761VENDOR_ATMEL_MDB161D:
12349 tp->nvram_jedecnum = JEDEC_ATMEL;
12350 tg3_flag_set(tp, NVRAM_BUFFERED);
12351 tg3_flag_set(tp, FLASH);
12352 tg3_flag_set(tp, NO_NVRAM_ADDR_TRANS);
12353 tp->nvram_pagesize = 256;
12355 case FLASH_5761VENDOR_ST_A_M45PE20:
12356 case FLASH_5761VENDOR_ST_A_M45PE40:
12357 case FLASH_5761VENDOR_ST_A_M45PE80:
12358 case FLASH_5761VENDOR_ST_A_M45PE16:
12359 case FLASH_5761VENDOR_ST_M_M45PE20:
12360 case FLASH_5761VENDOR_ST_M_M45PE40:
12361 case FLASH_5761VENDOR_ST_M_M45PE80:
12362 case FLASH_5761VENDOR_ST_M_M45PE16:
12363 tp->nvram_jedecnum = JEDEC_ST;
12364 tg3_flag_set(tp, NVRAM_BUFFERED);
12365 tg3_flag_set(tp, FLASH);
12366 tp->nvram_pagesize = 256;
12371 tp->nvram_size = tr32(NVRAM_ADDR_LOCKOUT);
12374 case FLASH_5761VENDOR_ATMEL_ADB161D:
12375 case FLASH_5761VENDOR_ATMEL_MDB161D:
12376 case FLASH_5761VENDOR_ST_A_M45PE16:
12377 case FLASH_5761VENDOR_ST_M_M45PE16:
12378 tp->nvram_size = TG3_NVRAM_SIZE_2MB;
12380 case FLASH_5761VENDOR_ATMEL_ADB081D:
12381 case FLASH_5761VENDOR_ATMEL_MDB081D:
12382 case FLASH_5761VENDOR_ST_A_M45PE80:
12383 case FLASH_5761VENDOR_ST_M_M45PE80:
12384 tp->nvram_size = TG3_NVRAM_SIZE_1MB;
12386 case FLASH_5761VENDOR_ATMEL_ADB041D:
12387 case FLASH_5761VENDOR_ATMEL_MDB041D:
12388 case FLASH_5761VENDOR_ST_A_M45PE40:
12389 case FLASH_5761VENDOR_ST_M_M45PE40:
12390 tp->nvram_size = TG3_NVRAM_SIZE_512KB;
12392 case FLASH_5761VENDOR_ATMEL_ADB021D:
12393 case FLASH_5761VENDOR_ATMEL_MDB021D:
12394 case FLASH_5761VENDOR_ST_A_M45PE20:
12395 case FLASH_5761VENDOR_ST_M_M45PE20:
12396 tp->nvram_size = TG3_NVRAM_SIZE_256KB;
12402 static void __devinit tg3_get_5906_nvram_info(struct tg3 *tp)
12404 tp->nvram_jedecnum = JEDEC_ATMEL;
12405 tg3_flag_set(tp, NVRAM_BUFFERED);
12406 tp->nvram_pagesize = ATMEL_AT24C512_CHIP_SIZE;
12409 static void __devinit tg3_get_57780_nvram_info(struct tg3 *tp)
12413 nvcfg1 = tr32(NVRAM_CFG1);
12415 switch (nvcfg1 & NVRAM_CFG1_5752VENDOR_MASK) {
12416 case FLASH_5787VENDOR_ATMEL_EEPROM_376KHZ:
12417 case FLASH_5787VENDOR_MICRO_EEPROM_376KHZ:
12418 tp->nvram_jedecnum = JEDEC_ATMEL;
12419 tg3_flag_set(tp, NVRAM_BUFFERED);
12420 tp->nvram_pagesize = ATMEL_AT24C512_CHIP_SIZE;
12422 nvcfg1 &= ~NVRAM_CFG1_COMPAT_BYPASS;
12423 tw32(NVRAM_CFG1, nvcfg1);
12425 case FLASH_5752VENDOR_ATMEL_FLASH_BUFFERED:
12426 case FLASH_57780VENDOR_ATMEL_AT45DB011D:
12427 case FLASH_57780VENDOR_ATMEL_AT45DB011B:
12428 case FLASH_57780VENDOR_ATMEL_AT45DB021D:
12429 case FLASH_57780VENDOR_ATMEL_AT45DB021B:
12430 case FLASH_57780VENDOR_ATMEL_AT45DB041D:
12431 case FLASH_57780VENDOR_ATMEL_AT45DB041B:
12432 tp->nvram_jedecnum = JEDEC_ATMEL;
12433 tg3_flag_set(tp, NVRAM_BUFFERED);
12434 tg3_flag_set(tp, FLASH);
12436 switch (nvcfg1 & NVRAM_CFG1_5752VENDOR_MASK) {
12437 case FLASH_5752VENDOR_ATMEL_FLASH_BUFFERED:
12438 case FLASH_57780VENDOR_ATMEL_AT45DB011D:
12439 case FLASH_57780VENDOR_ATMEL_AT45DB011B:
12440 tp->nvram_size = TG3_NVRAM_SIZE_128KB;
12442 case FLASH_57780VENDOR_ATMEL_AT45DB021D:
12443 case FLASH_57780VENDOR_ATMEL_AT45DB021B:
12444 tp->nvram_size = TG3_NVRAM_SIZE_256KB;
12446 case FLASH_57780VENDOR_ATMEL_AT45DB041D:
12447 case FLASH_57780VENDOR_ATMEL_AT45DB041B:
12448 tp->nvram_size = TG3_NVRAM_SIZE_512KB;
12452 case FLASH_5752VENDOR_ST_M45PE10:
12453 case FLASH_5752VENDOR_ST_M45PE20:
12454 case FLASH_5752VENDOR_ST_M45PE40:
12455 tp->nvram_jedecnum = JEDEC_ST;
12456 tg3_flag_set(tp, NVRAM_BUFFERED);
12457 tg3_flag_set(tp, FLASH);
12459 switch (nvcfg1 & NVRAM_CFG1_5752VENDOR_MASK) {
12460 case FLASH_5752VENDOR_ST_M45PE10:
12461 tp->nvram_size = TG3_NVRAM_SIZE_128KB;
12463 case FLASH_5752VENDOR_ST_M45PE20:
12464 tp->nvram_size = TG3_NVRAM_SIZE_256KB;
12466 case FLASH_5752VENDOR_ST_M45PE40:
12467 tp->nvram_size = TG3_NVRAM_SIZE_512KB;
12472 tg3_flag_set(tp, NO_NVRAM);
12476 tg3_nvram_get_pagesize(tp, nvcfg1);
12477 if (tp->nvram_pagesize != 264 && tp->nvram_pagesize != 528)
12478 tg3_flag_set(tp, NO_NVRAM_ADDR_TRANS);
12482 static void __devinit tg3_get_5717_nvram_info(struct tg3 *tp)
12486 nvcfg1 = tr32(NVRAM_CFG1);
12488 switch (nvcfg1 & NVRAM_CFG1_5752VENDOR_MASK) {
12489 case FLASH_5717VENDOR_ATMEL_EEPROM:
12490 case FLASH_5717VENDOR_MICRO_EEPROM:
12491 tp->nvram_jedecnum = JEDEC_ATMEL;
12492 tg3_flag_set(tp, NVRAM_BUFFERED);
12493 tp->nvram_pagesize = ATMEL_AT24C512_CHIP_SIZE;
12495 nvcfg1 &= ~NVRAM_CFG1_COMPAT_BYPASS;
12496 tw32(NVRAM_CFG1, nvcfg1);
12498 case FLASH_5717VENDOR_ATMEL_MDB011D:
12499 case FLASH_5717VENDOR_ATMEL_ADB011B:
12500 case FLASH_5717VENDOR_ATMEL_ADB011D:
12501 case FLASH_5717VENDOR_ATMEL_MDB021D:
12502 case FLASH_5717VENDOR_ATMEL_ADB021B:
12503 case FLASH_5717VENDOR_ATMEL_ADB021D:
12504 case FLASH_5717VENDOR_ATMEL_45USPT:
12505 tp->nvram_jedecnum = JEDEC_ATMEL;
12506 tg3_flag_set(tp, NVRAM_BUFFERED);
12507 tg3_flag_set(tp, FLASH);
12509 switch (nvcfg1 & NVRAM_CFG1_5752VENDOR_MASK) {
12510 case FLASH_5717VENDOR_ATMEL_MDB021D:
12511 /* Detect size with tg3_nvram_get_size() */
12513 case FLASH_5717VENDOR_ATMEL_ADB021B:
12514 case FLASH_5717VENDOR_ATMEL_ADB021D:
12515 tp->nvram_size = TG3_NVRAM_SIZE_256KB;
12518 tp->nvram_size = TG3_NVRAM_SIZE_128KB;
12522 case FLASH_5717VENDOR_ST_M_M25PE10:
12523 case FLASH_5717VENDOR_ST_A_M25PE10:
12524 case FLASH_5717VENDOR_ST_M_M45PE10:
12525 case FLASH_5717VENDOR_ST_A_M45PE10:
12526 case FLASH_5717VENDOR_ST_M_M25PE20:
12527 case FLASH_5717VENDOR_ST_A_M25PE20:
12528 case FLASH_5717VENDOR_ST_M_M45PE20:
12529 case FLASH_5717VENDOR_ST_A_M45PE20:
12530 case FLASH_5717VENDOR_ST_25USPT:
12531 case FLASH_5717VENDOR_ST_45USPT:
12532 tp->nvram_jedecnum = JEDEC_ST;
12533 tg3_flag_set(tp, NVRAM_BUFFERED);
12534 tg3_flag_set(tp, FLASH);
12536 switch (nvcfg1 & NVRAM_CFG1_5752VENDOR_MASK) {
12537 case FLASH_5717VENDOR_ST_M_M25PE20:
12538 case FLASH_5717VENDOR_ST_M_M45PE20:
12539 /* Detect size with tg3_nvram_get_size() */
12541 case FLASH_5717VENDOR_ST_A_M25PE20:
12542 case FLASH_5717VENDOR_ST_A_M45PE20:
12543 tp->nvram_size = TG3_NVRAM_SIZE_256KB;
12546 tp->nvram_size = TG3_NVRAM_SIZE_128KB;
12551 tg3_flag_set(tp, NO_NVRAM);
12555 tg3_nvram_get_pagesize(tp, nvcfg1);
12556 if (tp->nvram_pagesize != 264 && tp->nvram_pagesize != 528)
12557 tg3_flag_set(tp, NO_NVRAM_ADDR_TRANS);
12560 static void __devinit tg3_get_5720_nvram_info(struct tg3 *tp)
12562 u32 nvcfg1, nvmpinstrp;
12564 nvcfg1 = tr32(NVRAM_CFG1);
12565 nvmpinstrp = nvcfg1 & NVRAM_CFG1_5752VENDOR_MASK;
12567 switch (nvmpinstrp) {
12568 case FLASH_5720_EEPROM_HD:
12569 case FLASH_5720_EEPROM_LD:
12570 tp->nvram_jedecnum = JEDEC_ATMEL;
12571 tg3_flag_set(tp, NVRAM_BUFFERED);
12573 nvcfg1 &= ~NVRAM_CFG1_COMPAT_BYPASS;
12574 tw32(NVRAM_CFG1, nvcfg1);
12575 if (nvmpinstrp == FLASH_5720_EEPROM_HD)
12576 tp->nvram_pagesize = ATMEL_AT24C512_CHIP_SIZE;
12578 tp->nvram_pagesize = ATMEL_AT24C02_CHIP_SIZE;
12580 case FLASH_5720VENDOR_M_ATMEL_DB011D:
12581 case FLASH_5720VENDOR_A_ATMEL_DB011B:
12582 case FLASH_5720VENDOR_A_ATMEL_DB011D:
12583 case FLASH_5720VENDOR_M_ATMEL_DB021D:
12584 case FLASH_5720VENDOR_A_ATMEL_DB021B:
12585 case FLASH_5720VENDOR_A_ATMEL_DB021D:
12586 case FLASH_5720VENDOR_M_ATMEL_DB041D:
12587 case FLASH_5720VENDOR_A_ATMEL_DB041B:
12588 case FLASH_5720VENDOR_A_ATMEL_DB041D:
12589 case FLASH_5720VENDOR_M_ATMEL_DB081D:
12590 case FLASH_5720VENDOR_A_ATMEL_DB081D:
12591 case FLASH_5720VENDOR_ATMEL_45USPT:
12592 tp->nvram_jedecnum = JEDEC_ATMEL;
12593 tg3_flag_set(tp, NVRAM_BUFFERED);
12594 tg3_flag_set(tp, FLASH);
12596 switch (nvmpinstrp) {
12597 case FLASH_5720VENDOR_M_ATMEL_DB021D:
12598 case FLASH_5720VENDOR_A_ATMEL_DB021B:
12599 case FLASH_5720VENDOR_A_ATMEL_DB021D:
12600 tp->nvram_size = TG3_NVRAM_SIZE_256KB;
12602 case FLASH_5720VENDOR_M_ATMEL_DB041D:
12603 case FLASH_5720VENDOR_A_ATMEL_DB041B:
12604 case FLASH_5720VENDOR_A_ATMEL_DB041D:
12605 tp->nvram_size = TG3_NVRAM_SIZE_512KB;
12607 case FLASH_5720VENDOR_M_ATMEL_DB081D:
12608 case FLASH_5720VENDOR_A_ATMEL_DB081D:
12609 tp->nvram_size = TG3_NVRAM_SIZE_1MB;
12612 tp->nvram_size = TG3_NVRAM_SIZE_128KB;
12616 case FLASH_5720VENDOR_M_ST_M25PE10:
12617 case FLASH_5720VENDOR_M_ST_M45PE10:
12618 case FLASH_5720VENDOR_A_ST_M25PE10:
12619 case FLASH_5720VENDOR_A_ST_M45PE10:
12620 case FLASH_5720VENDOR_M_ST_M25PE20:
12621 case FLASH_5720VENDOR_M_ST_M45PE20:
12622 case FLASH_5720VENDOR_A_ST_M25PE20:
12623 case FLASH_5720VENDOR_A_ST_M45PE20:
12624 case FLASH_5720VENDOR_M_ST_M25PE40:
12625 case FLASH_5720VENDOR_M_ST_M45PE40:
12626 case FLASH_5720VENDOR_A_ST_M25PE40:
12627 case FLASH_5720VENDOR_A_ST_M45PE40:
12628 case FLASH_5720VENDOR_M_ST_M25PE80:
12629 case FLASH_5720VENDOR_M_ST_M45PE80:
12630 case FLASH_5720VENDOR_A_ST_M25PE80:
12631 case FLASH_5720VENDOR_A_ST_M45PE80:
12632 case FLASH_5720VENDOR_ST_25USPT:
12633 case FLASH_5720VENDOR_ST_45USPT:
12634 tp->nvram_jedecnum = JEDEC_ST;
12635 tg3_flag_set(tp, NVRAM_BUFFERED);
12636 tg3_flag_set(tp, FLASH);
12638 switch (nvmpinstrp) {
12639 case FLASH_5720VENDOR_M_ST_M25PE20:
12640 case FLASH_5720VENDOR_M_ST_M45PE20:
12641 case FLASH_5720VENDOR_A_ST_M25PE20:
12642 case FLASH_5720VENDOR_A_ST_M45PE20:
12643 tp->nvram_size = TG3_NVRAM_SIZE_256KB;
12645 case FLASH_5720VENDOR_M_ST_M25PE40:
12646 case FLASH_5720VENDOR_M_ST_M45PE40:
12647 case FLASH_5720VENDOR_A_ST_M25PE40:
12648 case FLASH_5720VENDOR_A_ST_M45PE40:
12649 tp->nvram_size = TG3_NVRAM_SIZE_512KB;
12651 case FLASH_5720VENDOR_M_ST_M25PE80:
12652 case FLASH_5720VENDOR_M_ST_M45PE80:
12653 case FLASH_5720VENDOR_A_ST_M25PE80:
12654 case FLASH_5720VENDOR_A_ST_M45PE80:
12655 tp->nvram_size = TG3_NVRAM_SIZE_1MB;
12658 tp->nvram_size = TG3_NVRAM_SIZE_128KB;
12663 tg3_flag_set(tp, NO_NVRAM);
12667 tg3_nvram_get_pagesize(tp, nvcfg1);
12668 if (tp->nvram_pagesize != 264 && tp->nvram_pagesize != 528)
12669 tg3_flag_set(tp, NO_NVRAM_ADDR_TRANS);
12672 /* Chips other than 5700/5701 use the NVRAM for fetching info. */
12673 static void __devinit tg3_nvram_init(struct tg3 *tp)
12675 tw32_f(GRC_EEPROM_ADDR,
12676 (EEPROM_ADDR_FSM_RESET |
12677 (EEPROM_DEFAULT_CLOCK_PERIOD <<
12678 EEPROM_ADDR_CLKPERD_SHIFT)));
12682 /* Enable seeprom accesses. */
12683 tw32_f(GRC_LOCAL_CTRL,
12684 tr32(GRC_LOCAL_CTRL) | GRC_LCLCTRL_AUTO_SEEPROM);
12687 if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5700 &&
12688 GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5701) {
12689 tg3_flag_set(tp, NVRAM);
12691 if (tg3_nvram_lock(tp)) {
12692 netdev_warn(tp->dev,
12693 "Cannot get nvram lock, %s failed\n",
12697 tg3_enable_nvram_access(tp);
12699 tp->nvram_size = 0;
12701 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5752)
12702 tg3_get_5752_nvram_info(tp);
12703 else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5755)
12704 tg3_get_5755_nvram_info(tp);
12705 else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5787 ||
12706 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5784 ||
12707 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785)
12708 tg3_get_5787_nvram_info(tp);
12709 else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5761)
12710 tg3_get_5761_nvram_info(tp);
12711 else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906)
12712 tg3_get_5906_nvram_info(tp);
12713 else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57780 ||
12714 tg3_flag(tp, 57765_CLASS))
12715 tg3_get_57780_nvram_info(tp);
12716 else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717 ||
12717 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5719)
12718 tg3_get_5717_nvram_info(tp);
12719 else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5720)
12720 tg3_get_5720_nvram_info(tp);
12722 tg3_get_nvram_info(tp);
12724 if (tp->nvram_size == 0)
12725 tg3_get_nvram_size(tp);
12727 tg3_disable_nvram_access(tp);
12728 tg3_nvram_unlock(tp);
12731 tg3_flag_clear(tp, NVRAM);
12732 tg3_flag_clear(tp, NVRAM_BUFFERED);
12734 tg3_get_eeprom_size(tp);
12738 static int tg3_nvram_write_block_using_eeprom(struct tg3 *tp,
12739 u32 offset, u32 len, u8 *buf)
12744 for (i = 0; i < len; i += 4) {
12750 memcpy(&data, buf + i, 4);
12753 * The SEEPROM interface expects the data to always be opposite
12754 * the native endian format. We accomplish this by reversing
12755 * all the operations that would have been performed on the
12756 * data from a call to tg3_nvram_read_be32().
12758 tw32(GRC_EEPROM_DATA, swab32(be32_to_cpu(data)));
12760 val = tr32(GRC_EEPROM_ADDR);
12761 tw32(GRC_EEPROM_ADDR, val | EEPROM_ADDR_COMPLETE);
12763 val &= ~(EEPROM_ADDR_ADDR_MASK | EEPROM_ADDR_DEVID_MASK |
12765 tw32(GRC_EEPROM_ADDR, val |
12766 (0 << EEPROM_ADDR_DEVID_SHIFT) |
12767 (addr & EEPROM_ADDR_ADDR_MASK) |
12768 EEPROM_ADDR_START |
12769 EEPROM_ADDR_WRITE);
12771 for (j = 0; j < 1000; j++) {
12772 val = tr32(GRC_EEPROM_ADDR);
12774 if (val & EEPROM_ADDR_COMPLETE)
12778 if (!(val & EEPROM_ADDR_COMPLETE)) {
12787 /* offset and length are dword aligned */
12788 static int tg3_nvram_write_block_unbuffered(struct tg3 *tp, u32 offset, u32 len,
12792 u32 pagesize = tp->nvram_pagesize;
12793 u32 pagemask = pagesize - 1;
12797 tmp = kmalloc(pagesize, GFP_KERNEL);
12803 u32 phy_addr, page_off, size;
12805 phy_addr = offset & ~pagemask;
12807 for (j = 0; j < pagesize; j += 4) {
12808 ret = tg3_nvram_read_be32(tp, phy_addr + j,
12809 (__be32 *) (tmp + j));
12816 page_off = offset & pagemask;
12823 memcpy(tmp + page_off, buf, size);
12825 offset = offset + (pagesize - page_off);
12827 tg3_enable_nvram_access(tp);
12830 * Before we can erase the flash page, we need
12831 * to issue a special "write enable" command.
12833 nvram_cmd = NVRAM_CMD_WREN | NVRAM_CMD_GO | NVRAM_CMD_DONE;
12835 if (tg3_nvram_exec_cmd(tp, nvram_cmd))
12838 /* Erase the target page */
12839 tw32(NVRAM_ADDR, phy_addr);
12841 nvram_cmd = NVRAM_CMD_GO | NVRAM_CMD_DONE | NVRAM_CMD_WR |
12842 NVRAM_CMD_FIRST | NVRAM_CMD_LAST | NVRAM_CMD_ERASE;
12844 if (tg3_nvram_exec_cmd(tp, nvram_cmd))
12847 /* Issue another write enable to start the write. */
12848 nvram_cmd = NVRAM_CMD_WREN | NVRAM_CMD_GO | NVRAM_CMD_DONE;
12850 if (tg3_nvram_exec_cmd(tp, nvram_cmd))
12853 for (j = 0; j < pagesize; j += 4) {
12856 data = *((__be32 *) (tmp + j));
12858 tw32(NVRAM_WRDATA, be32_to_cpu(data));
12860 tw32(NVRAM_ADDR, phy_addr + j);
12862 nvram_cmd = NVRAM_CMD_GO | NVRAM_CMD_DONE |
12866 nvram_cmd |= NVRAM_CMD_FIRST;
12867 else if (j == (pagesize - 4))
12868 nvram_cmd |= NVRAM_CMD_LAST;
12870 if ((ret = tg3_nvram_exec_cmd(tp, nvram_cmd)))
12877 nvram_cmd = NVRAM_CMD_WRDI | NVRAM_CMD_GO | NVRAM_CMD_DONE;
12878 tg3_nvram_exec_cmd(tp, nvram_cmd);
12885 /* offset and length are dword aligned */
12886 static int tg3_nvram_write_block_buffered(struct tg3 *tp, u32 offset, u32 len,
12891 for (i = 0; i < len; i += 4, offset += 4) {
12892 u32 page_off, phy_addr, nvram_cmd;
12895 memcpy(&data, buf + i, 4);
12896 tw32(NVRAM_WRDATA, be32_to_cpu(data));
12898 page_off = offset % tp->nvram_pagesize;
12900 phy_addr = tg3_nvram_phys_addr(tp, offset);
12902 tw32(NVRAM_ADDR, phy_addr);
12904 nvram_cmd = NVRAM_CMD_GO | NVRAM_CMD_DONE | NVRAM_CMD_WR;
12906 if (page_off == 0 || i == 0)
12907 nvram_cmd |= NVRAM_CMD_FIRST;
12908 if (page_off == (tp->nvram_pagesize - 4))
12909 nvram_cmd |= NVRAM_CMD_LAST;
12911 if (i == (len - 4))
12912 nvram_cmd |= NVRAM_CMD_LAST;
12914 if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5752 &&
12915 !tg3_flag(tp, 5755_PLUS) &&
12916 (tp->nvram_jedecnum == JEDEC_ST) &&
12917 (nvram_cmd & NVRAM_CMD_FIRST)) {
12919 if ((ret = tg3_nvram_exec_cmd(tp,
12920 NVRAM_CMD_WREN | NVRAM_CMD_GO |
12925 if (!tg3_flag(tp, FLASH)) {
12926 /* We always do complete word writes to eeprom. */
12927 nvram_cmd |= (NVRAM_CMD_FIRST | NVRAM_CMD_LAST);
12930 if ((ret = tg3_nvram_exec_cmd(tp, nvram_cmd)))
12936 /* offset and length are dword aligned */
12937 static int tg3_nvram_write_block(struct tg3 *tp, u32 offset, u32 len, u8 *buf)
12941 if (tg3_flag(tp, EEPROM_WRITE_PROT)) {
12942 tw32_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl &
12943 ~GRC_LCLCTRL_GPIO_OUTPUT1);
12947 if (!tg3_flag(tp, NVRAM)) {
12948 ret = tg3_nvram_write_block_using_eeprom(tp, offset, len, buf);
12952 ret = tg3_nvram_lock(tp);
12956 tg3_enable_nvram_access(tp);
12957 if (tg3_flag(tp, 5750_PLUS) && !tg3_flag(tp, PROTECTED_NVRAM))
12958 tw32(NVRAM_WRITE1, 0x406);
12960 grc_mode = tr32(GRC_MODE);
12961 tw32(GRC_MODE, grc_mode | GRC_MODE_NVRAM_WR_ENABLE);
12963 if (tg3_flag(tp, NVRAM_BUFFERED) || !tg3_flag(tp, FLASH)) {
12964 ret = tg3_nvram_write_block_buffered(tp, offset, len,
12967 ret = tg3_nvram_write_block_unbuffered(tp, offset, len,
12971 grc_mode = tr32(GRC_MODE);
12972 tw32(GRC_MODE, grc_mode & ~GRC_MODE_NVRAM_WR_ENABLE);
12974 tg3_disable_nvram_access(tp);
12975 tg3_nvram_unlock(tp);
12978 if (tg3_flag(tp, EEPROM_WRITE_PROT)) {
12979 tw32_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl);
12986 struct subsys_tbl_ent {
12987 u16 subsys_vendor, subsys_devid;
12991 static struct subsys_tbl_ent subsys_id_to_phy_id[] __devinitdata = {
12992 /* Broadcom boards. */
12993 { TG3PCI_SUBVENDOR_ID_BROADCOM,
12994 TG3PCI_SUBDEVICE_ID_BROADCOM_95700A6, TG3_PHY_ID_BCM5401 },
12995 { TG3PCI_SUBVENDOR_ID_BROADCOM,
12996 TG3PCI_SUBDEVICE_ID_BROADCOM_95701A5, TG3_PHY_ID_BCM5701 },
12997 { TG3PCI_SUBVENDOR_ID_BROADCOM,
12998 TG3PCI_SUBDEVICE_ID_BROADCOM_95700T6, TG3_PHY_ID_BCM8002 },
12999 { TG3PCI_SUBVENDOR_ID_BROADCOM,
13000 TG3PCI_SUBDEVICE_ID_BROADCOM_95700A9, 0 },
13001 { TG3PCI_SUBVENDOR_ID_BROADCOM,
13002 TG3PCI_SUBDEVICE_ID_BROADCOM_95701T1, TG3_PHY_ID_BCM5701 },
13003 { TG3PCI_SUBVENDOR_ID_BROADCOM,
13004 TG3PCI_SUBDEVICE_ID_BROADCOM_95701T8, TG3_PHY_ID_BCM5701 },
13005 { TG3PCI_SUBVENDOR_ID_BROADCOM,
13006 TG3PCI_SUBDEVICE_ID_BROADCOM_95701A7, 0 },
13007 { TG3PCI_SUBVENDOR_ID_BROADCOM,
13008 TG3PCI_SUBDEVICE_ID_BROADCOM_95701A10, TG3_PHY_ID_BCM5701 },
13009 { TG3PCI_SUBVENDOR_ID_BROADCOM,
13010 TG3PCI_SUBDEVICE_ID_BROADCOM_95701A12, TG3_PHY_ID_BCM5701 },
13011 { TG3PCI_SUBVENDOR_ID_BROADCOM,
13012 TG3PCI_SUBDEVICE_ID_BROADCOM_95703AX1, TG3_PHY_ID_BCM5703 },
13013 { TG3PCI_SUBVENDOR_ID_BROADCOM,
13014 TG3PCI_SUBDEVICE_ID_BROADCOM_95703AX2, TG3_PHY_ID_BCM5703 },
13017 { TG3PCI_SUBVENDOR_ID_3COM,
13018 TG3PCI_SUBDEVICE_ID_3COM_3C996T, TG3_PHY_ID_BCM5401 },
13019 { TG3PCI_SUBVENDOR_ID_3COM,
13020 TG3PCI_SUBDEVICE_ID_3COM_3C996BT, TG3_PHY_ID_BCM5701 },
13021 { TG3PCI_SUBVENDOR_ID_3COM,
13022 TG3PCI_SUBDEVICE_ID_3COM_3C996SX, 0 },
13023 { TG3PCI_SUBVENDOR_ID_3COM,
13024 TG3PCI_SUBDEVICE_ID_3COM_3C1000T, TG3_PHY_ID_BCM5701 },
13025 { TG3PCI_SUBVENDOR_ID_3COM,
13026 TG3PCI_SUBDEVICE_ID_3COM_3C940BR01, TG3_PHY_ID_BCM5701 },
13029 { TG3PCI_SUBVENDOR_ID_DELL,
13030 TG3PCI_SUBDEVICE_ID_DELL_VIPER, TG3_PHY_ID_BCM5401 },
13031 { TG3PCI_SUBVENDOR_ID_DELL,
13032 TG3PCI_SUBDEVICE_ID_DELL_JAGUAR, TG3_PHY_ID_BCM5401 },
13033 { TG3PCI_SUBVENDOR_ID_DELL,
13034 TG3PCI_SUBDEVICE_ID_DELL_MERLOT, TG3_PHY_ID_BCM5411 },
13035 { TG3PCI_SUBVENDOR_ID_DELL,
13036 TG3PCI_SUBDEVICE_ID_DELL_SLIM_MERLOT, TG3_PHY_ID_BCM5411 },
13038 /* Compaq boards. */
13039 { TG3PCI_SUBVENDOR_ID_COMPAQ,
13040 TG3PCI_SUBDEVICE_ID_COMPAQ_BANSHEE, TG3_PHY_ID_BCM5701 },
13041 { TG3PCI_SUBVENDOR_ID_COMPAQ,
13042 TG3PCI_SUBDEVICE_ID_COMPAQ_BANSHEE_2, TG3_PHY_ID_BCM5701 },
13043 { TG3PCI_SUBVENDOR_ID_COMPAQ,
13044 TG3PCI_SUBDEVICE_ID_COMPAQ_CHANGELING, 0 },
13045 { TG3PCI_SUBVENDOR_ID_COMPAQ,
13046 TG3PCI_SUBDEVICE_ID_COMPAQ_NC7780, TG3_PHY_ID_BCM5701 },
13047 { TG3PCI_SUBVENDOR_ID_COMPAQ,
13048 TG3PCI_SUBDEVICE_ID_COMPAQ_NC7780_2, TG3_PHY_ID_BCM5701 },
13051 { TG3PCI_SUBVENDOR_ID_IBM,
13052 TG3PCI_SUBDEVICE_ID_IBM_5703SAX2, 0 }
13055 static struct subsys_tbl_ent * __devinit tg3_lookup_by_subsys(struct tg3 *tp)
13059 for (i = 0; i < ARRAY_SIZE(subsys_id_to_phy_id); i++) {
13060 if ((subsys_id_to_phy_id[i].subsys_vendor ==
13061 tp->pdev->subsystem_vendor) &&
13062 (subsys_id_to_phy_id[i].subsys_devid ==
13063 tp->pdev->subsystem_device))
13064 return &subsys_id_to_phy_id[i];
13069 static void __devinit tg3_get_eeprom_hw_cfg(struct tg3 *tp)
13073 tp->phy_id = TG3_PHY_ID_INVALID;
13074 tp->led_ctrl = LED_CTRL_MODE_PHY_1;
13076 /* Assume an onboard device and WOL capable by default. */
13077 tg3_flag_set(tp, EEPROM_WRITE_PROT);
13078 tg3_flag_set(tp, WOL_CAP);
13080 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
13081 if (!(tr32(PCIE_TRANSACTION_CFG) & PCIE_TRANS_CFG_LOM)) {
13082 tg3_flag_clear(tp, EEPROM_WRITE_PROT);
13083 tg3_flag_set(tp, IS_NIC);
13085 val = tr32(VCPU_CFGSHDW);
13086 if (val & VCPU_CFGSHDW_ASPM_DBNC)
13087 tg3_flag_set(tp, ASPM_WORKAROUND);
13088 if ((val & VCPU_CFGSHDW_WOL_ENABLE) &&
13089 (val & VCPU_CFGSHDW_WOL_MAGPKT)) {
13090 tg3_flag_set(tp, WOL_ENABLE);
13091 device_set_wakeup_enable(&tp->pdev->dev, true);
13096 tg3_read_mem(tp, NIC_SRAM_DATA_SIG, &val);
13097 if (val == NIC_SRAM_DATA_SIG_MAGIC) {
13098 u32 nic_cfg, led_cfg;
13099 u32 nic_phy_id, ver, cfg2 = 0, cfg4 = 0, eeprom_phy_id;
13100 int eeprom_phy_serdes = 0;
13102 tg3_read_mem(tp, NIC_SRAM_DATA_CFG, &nic_cfg);
13103 tp->nic_sram_data_cfg = nic_cfg;
13105 tg3_read_mem(tp, NIC_SRAM_DATA_VER, &ver);
13106 ver >>= NIC_SRAM_DATA_VER_SHIFT;
13107 if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5700 &&
13108 GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5701 &&
13109 GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5703 &&
13110 (ver > 0) && (ver < 0x100))
13111 tg3_read_mem(tp, NIC_SRAM_DATA_CFG_2, &cfg2);
13113 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785)
13114 tg3_read_mem(tp, NIC_SRAM_DATA_CFG_4, &cfg4);
13116 if ((nic_cfg & NIC_SRAM_DATA_CFG_PHY_TYPE_MASK) ==
13117 NIC_SRAM_DATA_CFG_PHY_TYPE_FIBER)
13118 eeprom_phy_serdes = 1;
13120 tg3_read_mem(tp, NIC_SRAM_DATA_PHY_ID, &nic_phy_id);
13121 if (nic_phy_id != 0) {
13122 u32 id1 = nic_phy_id & NIC_SRAM_DATA_PHY_ID1_MASK;
13123 u32 id2 = nic_phy_id & NIC_SRAM_DATA_PHY_ID2_MASK;
13125 eeprom_phy_id = (id1 >> 16) << 10;
13126 eeprom_phy_id |= (id2 & 0xfc00) << 16;
13127 eeprom_phy_id |= (id2 & 0x03ff) << 0;
13131 tp->phy_id = eeprom_phy_id;
13132 if (eeprom_phy_serdes) {
13133 if (!tg3_flag(tp, 5705_PLUS))
13134 tp->phy_flags |= TG3_PHYFLG_PHY_SERDES;
13136 tp->phy_flags |= TG3_PHYFLG_MII_SERDES;
13139 if (tg3_flag(tp, 5750_PLUS))
13140 led_cfg = cfg2 & (NIC_SRAM_DATA_CFG_LED_MODE_MASK |
13141 SHASTA_EXT_LED_MODE_MASK);
13143 led_cfg = nic_cfg & NIC_SRAM_DATA_CFG_LED_MODE_MASK;
13147 case NIC_SRAM_DATA_CFG_LED_MODE_PHY_1:
13148 tp->led_ctrl = LED_CTRL_MODE_PHY_1;
13151 case NIC_SRAM_DATA_CFG_LED_MODE_PHY_2:
13152 tp->led_ctrl = LED_CTRL_MODE_PHY_2;
13155 case NIC_SRAM_DATA_CFG_LED_MODE_MAC:
13156 tp->led_ctrl = LED_CTRL_MODE_MAC;
13158 /* Default to PHY_1_MODE if 0 (MAC_MODE) is
13159 * read on some older 5700/5701 bootcode.
13161 if (GET_ASIC_REV(tp->pci_chip_rev_id) ==
13163 GET_ASIC_REV(tp->pci_chip_rev_id) ==
13165 tp->led_ctrl = LED_CTRL_MODE_PHY_1;
13169 case SHASTA_EXT_LED_SHARED:
13170 tp->led_ctrl = LED_CTRL_MODE_SHARED;
13171 if (tp->pci_chip_rev_id != CHIPREV_ID_5750_A0 &&
13172 tp->pci_chip_rev_id != CHIPREV_ID_5750_A1)
13173 tp->led_ctrl |= (LED_CTRL_MODE_PHY_1 |
13174 LED_CTRL_MODE_PHY_2);
13177 case SHASTA_EXT_LED_MAC:
13178 tp->led_ctrl = LED_CTRL_MODE_SHASTA_MAC;
13181 case SHASTA_EXT_LED_COMBO:
13182 tp->led_ctrl = LED_CTRL_MODE_COMBO;
13183 if (tp->pci_chip_rev_id != CHIPREV_ID_5750_A0)
13184 tp->led_ctrl |= (LED_CTRL_MODE_PHY_1 |
13185 LED_CTRL_MODE_PHY_2);
13190 if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
13191 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701) &&
13192 tp->pdev->subsystem_vendor == PCI_VENDOR_ID_DELL)
13193 tp->led_ctrl = LED_CTRL_MODE_PHY_2;
13195 if (GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5784_AX)
13196 tp->led_ctrl = LED_CTRL_MODE_PHY_1;
13198 if (nic_cfg & NIC_SRAM_DATA_CFG_EEPROM_WP) {
13199 tg3_flag_set(tp, EEPROM_WRITE_PROT);
13200 if ((tp->pdev->subsystem_vendor ==
13201 PCI_VENDOR_ID_ARIMA) &&
13202 (tp->pdev->subsystem_device == 0x205a ||
13203 tp->pdev->subsystem_device == 0x2063))
13204 tg3_flag_clear(tp, EEPROM_WRITE_PROT);
13206 tg3_flag_clear(tp, EEPROM_WRITE_PROT);
13207 tg3_flag_set(tp, IS_NIC);
13210 if (nic_cfg & NIC_SRAM_DATA_CFG_ASF_ENABLE) {
13211 tg3_flag_set(tp, ENABLE_ASF);
13212 if (tg3_flag(tp, 5750_PLUS))
13213 tg3_flag_set(tp, ASF_NEW_HANDSHAKE);
13216 if ((nic_cfg & NIC_SRAM_DATA_CFG_APE_ENABLE) &&
13217 tg3_flag(tp, 5750_PLUS))
13218 tg3_flag_set(tp, ENABLE_APE);
13220 if (tp->phy_flags & TG3_PHYFLG_ANY_SERDES &&
13221 !(nic_cfg & NIC_SRAM_DATA_CFG_FIBER_WOL))
13222 tg3_flag_clear(tp, WOL_CAP);
13224 if (tg3_flag(tp, WOL_CAP) &&
13225 (nic_cfg & NIC_SRAM_DATA_CFG_WOL_ENABLE)) {
13226 tg3_flag_set(tp, WOL_ENABLE);
13227 device_set_wakeup_enable(&tp->pdev->dev, true);
13230 if (cfg2 & (1 << 17))
13231 tp->phy_flags |= TG3_PHYFLG_CAPACITIVE_COUPLING;
13233 /* serdes signal pre-emphasis in register 0x590 set by */
13234 /* bootcode if bit 18 is set */
13235 if (cfg2 & (1 << 18))
13236 tp->phy_flags |= TG3_PHYFLG_SERDES_PREEMPHASIS;
13238 if ((tg3_flag(tp, 57765_PLUS) ||
13239 (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5784 &&
13240 GET_CHIP_REV(tp->pci_chip_rev_id) != CHIPREV_5784_AX)) &&
13241 (cfg2 & NIC_SRAM_DATA_CFG_2_APD_EN))
13242 tp->phy_flags |= TG3_PHYFLG_ENABLE_APD;
13244 if (tg3_flag(tp, PCI_EXPRESS) &&
13245 GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5785 &&
13246 !tg3_flag(tp, 57765_PLUS)) {
13249 tg3_read_mem(tp, NIC_SRAM_DATA_CFG_3, &cfg3);
13250 if (cfg3 & NIC_SRAM_ASPM_DEBOUNCE)
13251 tg3_flag_set(tp, ASPM_WORKAROUND);
13254 if (cfg4 & NIC_SRAM_RGMII_INBAND_DISABLE)
13255 tg3_flag_set(tp, RGMII_INBAND_DISABLE);
13256 if (cfg4 & NIC_SRAM_RGMII_EXT_IBND_RX_EN)
13257 tg3_flag_set(tp, RGMII_EXT_IBND_RX_EN);
13258 if (cfg4 & NIC_SRAM_RGMII_EXT_IBND_TX_EN)
13259 tg3_flag_set(tp, RGMII_EXT_IBND_TX_EN);
13262 if (tg3_flag(tp, WOL_CAP))
13263 device_set_wakeup_enable(&tp->pdev->dev,
13264 tg3_flag(tp, WOL_ENABLE));
13266 device_set_wakeup_capable(&tp->pdev->dev, false);
13269 static int __devinit tg3_issue_otp_command(struct tg3 *tp, u32 cmd)
13274 tw32(OTP_CTRL, cmd | OTP_CTRL_OTP_CMD_START);
13275 tw32(OTP_CTRL, cmd);
13277 /* Wait for up to 1 ms for command to execute. */
13278 for (i = 0; i < 100; i++) {
13279 val = tr32(OTP_STATUS);
13280 if (val & OTP_STATUS_CMD_DONE)
13285 return (val & OTP_STATUS_CMD_DONE) ? 0 : -EBUSY;
13288 /* Read the gphy configuration from the OTP region of the chip. The gphy
13289 * configuration is a 32-bit value that straddles the alignment boundary.
13290 * We do two 32-bit reads and then shift and merge the results.
13292 static u32 __devinit tg3_read_otp_phycfg(struct tg3 *tp)
13294 u32 bhalf_otp, thalf_otp;
13296 tw32(OTP_MODE, OTP_MODE_OTP_THRU_GRC);
13298 if (tg3_issue_otp_command(tp, OTP_CTRL_OTP_CMD_INIT))
13301 tw32(OTP_ADDRESS, OTP_ADDRESS_MAGIC1);
13303 if (tg3_issue_otp_command(tp, OTP_CTRL_OTP_CMD_READ))
13306 thalf_otp = tr32(OTP_READ_DATA);
13308 tw32(OTP_ADDRESS, OTP_ADDRESS_MAGIC2);
13310 if (tg3_issue_otp_command(tp, OTP_CTRL_OTP_CMD_READ))
13313 bhalf_otp = tr32(OTP_READ_DATA);
13315 return ((thalf_otp & 0x0000ffff) << 16) | (bhalf_otp >> 16);
13318 static void __devinit tg3_phy_init_link_config(struct tg3 *tp)
13320 u32 adv = ADVERTISED_Autoneg;
13322 if (!(tp->phy_flags & TG3_PHYFLG_10_100_ONLY))
13323 adv |= ADVERTISED_1000baseT_Half |
13324 ADVERTISED_1000baseT_Full;
13326 if (!(tp->phy_flags & TG3_PHYFLG_ANY_SERDES))
13327 adv |= ADVERTISED_100baseT_Half |
13328 ADVERTISED_100baseT_Full |
13329 ADVERTISED_10baseT_Half |
13330 ADVERTISED_10baseT_Full |
13333 adv |= ADVERTISED_FIBRE;
13335 tp->link_config.advertising = adv;
13336 tp->link_config.speed = SPEED_INVALID;
13337 tp->link_config.duplex = DUPLEX_INVALID;
13338 tp->link_config.autoneg = AUTONEG_ENABLE;
13339 tp->link_config.active_speed = SPEED_INVALID;
13340 tp->link_config.active_duplex = DUPLEX_INVALID;
13341 tp->link_config.orig_speed = SPEED_INVALID;
13342 tp->link_config.orig_duplex = DUPLEX_INVALID;
13343 tp->link_config.orig_autoneg = AUTONEG_INVALID;
13346 static int __devinit tg3_phy_probe(struct tg3 *tp)
13348 u32 hw_phy_id_1, hw_phy_id_2;
13349 u32 hw_phy_id, hw_phy_id_masked;
13352 /* flow control autonegotiation is default behavior */
13353 tg3_flag_set(tp, PAUSE_AUTONEG);
13354 tp->link_config.flowctrl = FLOW_CTRL_TX | FLOW_CTRL_RX;
13356 if (tg3_flag(tp, USE_PHYLIB))
13357 return tg3_phy_init(tp);
13359 /* Reading the PHY ID register can conflict with ASF
13360 * firmware access to the PHY hardware.
13363 if (tg3_flag(tp, ENABLE_ASF) || tg3_flag(tp, ENABLE_APE)) {
13364 hw_phy_id = hw_phy_id_masked = TG3_PHY_ID_INVALID;
13366 /* Now read the physical PHY_ID from the chip and verify
13367 * that it is sane. If it doesn't look good, we fall back
13368 * to either the hard-coded table based PHY_ID and failing
13369 * that the value found in the eeprom area.
13371 err |= tg3_readphy(tp, MII_PHYSID1, &hw_phy_id_1);
13372 err |= tg3_readphy(tp, MII_PHYSID2, &hw_phy_id_2);
13374 hw_phy_id = (hw_phy_id_1 & 0xffff) << 10;
13375 hw_phy_id |= (hw_phy_id_2 & 0xfc00) << 16;
13376 hw_phy_id |= (hw_phy_id_2 & 0x03ff) << 0;
13378 hw_phy_id_masked = hw_phy_id & TG3_PHY_ID_MASK;
13381 if (!err && TG3_KNOWN_PHY_ID(hw_phy_id_masked)) {
13382 tp->phy_id = hw_phy_id;
13383 if (hw_phy_id_masked == TG3_PHY_ID_BCM8002)
13384 tp->phy_flags |= TG3_PHYFLG_PHY_SERDES;
13386 tp->phy_flags &= ~TG3_PHYFLG_PHY_SERDES;
13388 if (tp->phy_id != TG3_PHY_ID_INVALID) {
13389 /* Do nothing, phy ID already set up in
13390 * tg3_get_eeprom_hw_cfg().
13393 struct subsys_tbl_ent *p;
13395 /* No eeprom signature? Try the hardcoded
13396 * subsys device table.
13398 p = tg3_lookup_by_subsys(tp);
13402 tp->phy_id = p->phy_id;
13404 tp->phy_id == TG3_PHY_ID_BCM8002)
13405 tp->phy_flags |= TG3_PHYFLG_PHY_SERDES;
13409 if (!(tp->phy_flags & TG3_PHYFLG_ANY_SERDES) &&
13410 (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5719 ||
13411 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5720 ||
13412 (tp->pdev->device == TG3PCI_DEVICE_TIGON3_5718 &&
13413 tp->pci_chip_rev_id != CHIPREV_ID_5717_A0) ||
13414 (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57765 &&
13415 tp->pci_chip_rev_id != CHIPREV_ID_57765_A0)))
13416 tp->phy_flags |= TG3_PHYFLG_EEE_CAP;
13418 tg3_phy_init_link_config(tp);
13420 if (!(tp->phy_flags & TG3_PHYFLG_ANY_SERDES) &&
13421 !tg3_flag(tp, ENABLE_APE) &&
13422 !tg3_flag(tp, ENABLE_ASF)) {
13425 tg3_readphy(tp, MII_BMSR, &bmsr);
13426 if (!tg3_readphy(tp, MII_BMSR, &bmsr) &&
13427 (bmsr & BMSR_LSTATUS))
13428 goto skip_phy_reset;
13430 err = tg3_phy_reset(tp);
13434 tg3_phy_set_wirespeed(tp);
13436 if (!tg3_phy_copper_an_config_ok(tp, &dummy)) {
13437 tg3_phy_autoneg_cfg(tp, tp->link_config.advertising,
13438 tp->link_config.flowctrl);
13440 tg3_writephy(tp, MII_BMCR,
13441 BMCR_ANENABLE | BMCR_ANRESTART);
13446 if ((tp->phy_id & TG3_PHY_ID_MASK) == TG3_PHY_ID_BCM5401) {
13447 err = tg3_init_5401phy_dsp(tp);
13451 err = tg3_init_5401phy_dsp(tp);
13457 static void __devinit tg3_read_vpd(struct tg3 *tp)
13460 unsigned int block_end, rosize, len;
13464 vpd_data = (u8 *)tg3_vpd_readblock(tp, &vpdlen);
13468 i = pci_vpd_find_tag(vpd_data, 0, vpdlen, PCI_VPD_LRDT_RO_DATA);
13470 goto out_not_found;
13472 rosize = pci_vpd_lrdt_size(&vpd_data[i]);
13473 block_end = i + PCI_VPD_LRDT_TAG_SIZE + rosize;
13474 i += PCI_VPD_LRDT_TAG_SIZE;
13476 if (block_end > vpdlen)
13477 goto out_not_found;
13479 j = pci_vpd_find_info_keyword(vpd_data, i, rosize,
13480 PCI_VPD_RO_KEYWORD_MFR_ID);
13482 len = pci_vpd_info_field_size(&vpd_data[j]);
13484 j += PCI_VPD_INFO_FLD_HDR_SIZE;
13485 if (j + len > block_end || len != 4 ||
13486 memcmp(&vpd_data[j], "1028", 4))
13489 j = pci_vpd_find_info_keyword(vpd_data, i, rosize,
13490 PCI_VPD_RO_KEYWORD_VENDOR0);
13494 len = pci_vpd_info_field_size(&vpd_data[j]);
13496 j += PCI_VPD_INFO_FLD_HDR_SIZE;
13497 if (j + len > block_end)
13500 memcpy(tp->fw_ver, &vpd_data[j], len);
13501 strncat(tp->fw_ver, " bc ", vpdlen - len - 1);
13505 i = pci_vpd_find_info_keyword(vpd_data, i, rosize,
13506 PCI_VPD_RO_KEYWORD_PARTNO);
13508 goto out_not_found;
13510 len = pci_vpd_info_field_size(&vpd_data[i]);
13512 i += PCI_VPD_INFO_FLD_HDR_SIZE;
13513 if (len > TG3_BPN_SIZE ||
13514 (len + i) > vpdlen)
13515 goto out_not_found;
13517 memcpy(tp->board_part_number, &vpd_data[i], len);
13521 if (tp->board_part_number[0])
13525 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717) {
13526 if (tp->pdev->device == TG3PCI_DEVICE_TIGON3_5717)
13527 strcpy(tp->board_part_number, "BCM5717");
13528 else if (tp->pdev->device == TG3PCI_DEVICE_TIGON3_5718)
13529 strcpy(tp->board_part_number, "BCM5718");
13532 } else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57780) {
13533 if (tp->pdev->device == TG3PCI_DEVICE_TIGON3_57780)
13534 strcpy(tp->board_part_number, "BCM57780");
13535 else if (tp->pdev->device == TG3PCI_DEVICE_TIGON3_57760)
13536 strcpy(tp->board_part_number, "BCM57760");
13537 else if (tp->pdev->device == TG3PCI_DEVICE_TIGON3_57790)
13538 strcpy(tp->board_part_number, "BCM57790");
13539 else if (tp->pdev->device == TG3PCI_DEVICE_TIGON3_57788)
13540 strcpy(tp->board_part_number, "BCM57788");
13543 } else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57765) {
13544 if (tp->pdev->device == TG3PCI_DEVICE_TIGON3_57761)
13545 strcpy(tp->board_part_number, "BCM57761");
13546 else if (tp->pdev->device == TG3PCI_DEVICE_TIGON3_57765)
13547 strcpy(tp->board_part_number, "BCM57765");
13548 else if (tp->pdev->device == TG3PCI_DEVICE_TIGON3_57781)
13549 strcpy(tp->board_part_number, "BCM57781");
13550 else if (tp->pdev->device == TG3PCI_DEVICE_TIGON3_57785)
13551 strcpy(tp->board_part_number, "BCM57785");
13552 else if (tp->pdev->device == TG3PCI_DEVICE_TIGON3_57791)
13553 strcpy(tp->board_part_number, "BCM57791");
13554 else if (tp->pdev->device == TG3PCI_DEVICE_TIGON3_57795)
13555 strcpy(tp->board_part_number, "BCM57795");
13558 } else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57766) {
13559 if (tp->pdev->device == TG3PCI_DEVICE_TIGON3_57762)
13560 strcpy(tp->board_part_number, "BCM57762");
13561 else if (tp->pdev->device == TG3PCI_DEVICE_TIGON3_57766)
13562 strcpy(tp->board_part_number, "BCM57766");
13563 else if (tp->pdev->device == TG3PCI_DEVICE_TIGON3_57782)
13564 strcpy(tp->board_part_number, "BCM57782");
13565 else if (tp->pdev->device == TG3PCI_DEVICE_TIGON3_57786)
13566 strcpy(tp->board_part_number, "BCM57786");
13569 } else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
13570 strcpy(tp->board_part_number, "BCM95906");
13573 strcpy(tp->board_part_number, "none");
13577 static int __devinit tg3_fw_img_is_valid(struct tg3 *tp, u32 offset)
13581 if (tg3_nvram_read(tp, offset, &val) ||
13582 (val & 0xfc000000) != 0x0c000000 ||
13583 tg3_nvram_read(tp, offset + 4, &val) ||
13590 static void __devinit tg3_read_bc_ver(struct tg3 *tp)
13592 u32 val, offset, start, ver_offset;
13594 bool newver = false;
13596 if (tg3_nvram_read(tp, 0xc, &offset) ||
13597 tg3_nvram_read(tp, 0x4, &start))
13600 offset = tg3_nvram_logical_addr(tp, offset);
13602 if (tg3_nvram_read(tp, offset, &val))
13605 if ((val & 0xfc000000) == 0x0c000000) {
13606 if (tg3_nvram_read(tp, offset + 4, &val))
13613 dst_off = strlen(tp->fw_ver);
13616 if (TG3_VER_SIZE - dst_off < 16 ||
13617 tg3_nvram_read(tp, offset + 8, &ver_offset))
13620 offset = offset + ver_offset - start;
13621 for (i = 0; i < 16; i += 4) {
13623 if (tg3_nvram_read_be32(tp, offset + i, &v))
13626 memcpy(tp->fw_ver + dst_off + i, &v, sizeof(v));
13631 if (tg3_nvram_read(tp, TG3_NVM_PTREV_BCVER, &ver_offset))
13634 major = (ver_offset & TG3_NVM_BCVER_MAJMSK) >>
13635 TG3_NVM_BCVER_MAJSFT;
13636 minor = ver_offset & TG3_NVM_BCVER_MINMSK;
13637 snprintf(&tp->fw_ver[dst_off], TG3_VER_SIZE - dst_off,
13638 "v%d.%02d", major, minor);
13642 static void __devinit tg3_read_hwsb_ver(struct tg3 *tp)
13644 u32 val, major, minor;
13646 /* Use native endian representation */
13647 if (tg3_nvram_read(tp, TG3_NVM_HWSB_CFG1, &val))
13650 major = (val & TG3_NVM_HWSB_CFG1_MAJMSK) >>
13651 TG3_NVM_HWSB_CFG1_MAJSFT;
13652 minor = (val & TG3_NVM_HWSB_CFG1_MINMSK) >>
13653 TG3_NVM_HWSB_CFG1_MINSFT;
13655 snprintf(&tp->fw_ver[0], 32, "sb v%d.%02d", major, minor);
13658 static void __devinit tg3_read_sb_ver(struct tg3 *tp, u32 val)
13660 u32 offset, major, minor, build;
13662 strncat(tp->fw_ver, "sb", TG3_VER_SIZE - strlen(tp->fw_ver) - 1);
13664 if ((val & TG3_EEPROM_SB_FORMAT_MASK) != TG3_EEPROM_SB_FORMAT_1)
13667 switch (val & TG3_EEPROM_SB_REVISION_MASK) {
13668 case TG3_EEPROM_SB_REVISION_0:
13669 offset = TG3_EEPROM_SB_F1R0_EDH_OFF;
13671 case TG3_EEPROM_SB_REVISION_2:
13672 offset = TG3_EEPROM_SB_F1R2_EDH_OFF;
13674 case TG3_EEPROM_SB_REVISION_3:
13675 offset = TG3_EEPROM_SB_F1R3_EDH_OFF;
13677 case TG3_EEPROM_SB_REVISION_4:
13678 offset = TG3_EEPROM_SB_F1R4_EDH_OFF;
13680 case TG3_EEPROM_SB_REVISION_5:
13681 offset = TG3_EEPROM_SB_F1R5_EDH_OFF;
13683 case TG3_EEPROM_SB_REVISION_6:
13684 offset = TG3_EEPROM_SB_F1R6_EDH_OFF;
13690 if (tg3_nvram_read(tp, offset, &val))
13693 build = (val & TG3_EEPROM_SB_EDH_BLD_MASK) >>
13694 TG3_EEPROM_SB_EDH_BLD_SHFT;
13695 major = (val & TG3_EEPROM_SB_EDH_MAJ_MASK) >>
13696 TG3_EEPROM_SB_EDH_MAJ_SHFT;
13697 minor = val & TG3_EEPROM_SB_EDH_MIN_MASK;
13699 if (minor > 99 || build > 26)
13702 offset = strlen(tp->fw_ver);
13703 snprintf(&tp->fw_ver[offset], TG3_VER_SIZE - offset,
13704 " v%d.%02d", major, minor);
13707 offset = strlen(tp->fw_ver);
13708 if (offset < TG3_VER_SIZE - 1)
13709 tp->fw_ver[offset] = 'a' + build - 1;
13713 static void __devinit tg3_read_mgmtfw_ver(struct tg3 *tp)
13715 u32 val, offset, start;
13718 for (offset = TG3_NVM_DIR_START;
13719 offset < TG3_NVM_DIR_END;
13720 offset += TG3_NVM_DIRENT_SIZE) {
13721 if (tg3_nvram_read(tp, offset, &val))
13724 if ((val >> TG3_NVM_DIRTYPE_SHIFT) == TG3_NVM_DIRTYPE_ASFINI)
13728 if (offset == TG3_NVM_DIR_END)
13731 if (!tg3_flag(tp, 5705_PLUS))
13732 start = 0x08000000;
13733 else if (tg3_nvram_read(tp, offset - 4, &start))
13736 if (tg3_nvram_read(tp, offset + 4, &offset) ||
13737 !tg3_fw_img_is_valid(tp, offset) ||
13738 tg3_nvram_read(tp, offset + 8, &val))
13741 offset += val - start;
13743 vlen = strlen(tp->fw_ver);
13745 tp->fw_ver[vlen++] = ',';
13746 tp->fw_ver[vlen++] = ' ';
13748 for (i = 0; i < 4; i++) {
13750 if (tg3_nvram_read_be32(tp, offset, &v))
13753 offset += sizeof(v);
13755 if (vlen > TG3_VER_SIZE - sizeof(v)) {
13756 memcpy(&tp->fw_ver[vlen], &v, TG3_VER_SIZE - vlen);
13760 memcpy(&tp->fw_ver[vlen], &v, sizeof(v));
13765 static void __devinit tg3_read_dash_ver(struct tg3 *tp)
13771 if (!tg3_flag(tp, ENABLE_APE) || !tg3_flag(tp, ENABLE_ASF))
13774 apedata = tg3_ape_read32(tp, TG3_APE_SEG_SIG);
13775 if (apedata != APE_SEG_SIG_MAGIC)
13778 apedata = tg3_ape_read32(tp, TG3_APE_FW_STATUS);
13779 if (!(apedata & APE_FW_STATUS_READY))
13782 apedata = tg3_ape_read32(tp, TG3_APE_FW_VERSION);
13784 if (tg3_ape_read32(tp, TG3_APE_FW_FEATURES) & TG3_APE_FW_FEATURE_NCSI) {
13785 tg3_flag_set(tp, APE_HAS_NCSI);
13791 vlen = strlen(tp->fw_ver);
13793 snprintf(&tp->fw_ver[vlen], TG3_VER_SIZE - vlen, " %s v%d.%d.%d.%d",
13795 (apedata & APE_FW_VERSION_MAJMSK) >> APE_FW_VERSION_MAJSFT,
13796 (apedata & APE_FW_VERSION_MINMSK) >> APE_FW_VERSION_MINSFT,
13797 (apedata & APE_FW_VERSION_REVMSK) >> APE_FW_VERSION_REVSFT,
13798 (apedata & APE_FW_VERSION_BLDMSK));
13801 static void __devinit tg3_read_fw_ver(struct tg3 *tp)
13804 bool vpd_vers = false;
13806 if (tp->fw_ver[0] != 0)
13809 if (tg3_flag(tp, NO_NVRAM)) {
13810 strcat(tp->fw_ver, "sb");
13814 if (tg3_nvram_read(tp, 0, &val))
13817 if (val == TG3_EEPROM_MAGIC)
13818 tg3_read_bc_ver(tp);
13819 else if ((val & TG3_EEPROM_MAGIC_FW_MSK) == TG3_EEPROM_MAGIC_FW)
13820 tg3_read_sb_ver(tp, val);
13821 else if ((val & TG3_EEPROM_MAGIC_HW_MSK) == TG3_EEPROM_MAGIC_HW)
13822 tg3_read_hwsb_ver(tp);
13829 if (tg3_flag(tp, ENABLE_APE)) {
13830 if (tg3_flag(tp, ENABLE_ASF))
13831 tg3_read_dash_ver(tp);
13832 } else if (tg3_flag(tp, ENABLE_ASF)) {
13833 tg3_read_mgmtfw_ver(tp);
13837 tp->fw_ver[TG3_VER_SIZE - 1] = 0;
13840 static struct pci_dev * __devinit tg3_find_peer(struct tg3 *);
13842 static inline u32 tg3_rx_ret_ring_size(struct tg3 *tp)
13844 if (tg3_flag(tp, LRG_PROD_RING_CAP))
13845 return TG3_RX_RET_MAX_SIZE_5717;
13846 else if (tg3_flag(tp, JUMBO_CAPABLE) && !tg3_flag(tp, 5780_CLASS))
13847 return TG3_RX_RET_MAX_SIZE_5700;
13849 return TG3_RX_RET_MAX_SIZE_5705;
13852 static DEFINE_PCI_DEVICE_TABLE(tg3_write_reorder_chipsets) = {
13853 { PCI_DEVICE(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_FE_GATE_700C) },
13854 { PCI_DEVICE(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_8131_BRIDGE) },
13855 { PCI_DEVICE(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8385_0) },
13859 static int __devinit tg3_get_invariants(struct tg3 *tp)
13862 u32 pci_state_reg, grc_misc_cfg;
13867 /* Force memory write invalidate off. If we leave it on,
13868 * then on 5700_BX chips we have to enable a workaround.
13869 * The workaround is to set the TG3PCI_DMA_RW_CTRL boundary
13870 * to match the cacheline size. The Broadcom driver have this
13871 * workaround but turns MWI off all the times so never uses
13872 * it. This seems to suggest that the workaround is insufficient.
13874 pci_read_config_word(tp->pdev, PCI_COMMAND, &pci_cmd);
13875 pci_cmd &= ~PCI_COMMAND_INVALIDATE;
13876 pci_write_config_word(tp->pdev, PCI_COMMAND, pci_cmd);
13878 /* Important! -- Make sure register accesses are byteswapped
13879 * correctly. Also, for those chips that require it, make
13880 * sure that indirect register accesses are enabled before
13881 * the first operation.
13883 pci_read_config_dword(tp->pdev, TG3PCI_MISC_HOST_CTRL,
13885 tp->misc_host_ctrl |= (misc_ctrl_reg &
13886 MISC_HOST_CTRL_CHIPREV);
13887 pci_write_config_dword(tp->pdev, TG3PCI_MISC_HOST_CTRL,
13888 tp->misc_host_ctrl);
13890 tp->pci_chip_rev_id = (misc_ctrl_reg >>
13891 MISC_HOST_CTRL_CHIPREV_SHIFT);
13892 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_USE_PROD_ID_REG) {
13893 u32 prod_id_asic_rev;
13895 if (tp->pdev->device == TG3PCI_DEVICE_TIGON3_5717 ||
13896 tp->pdev->device == TG3PCI_DEVICE_TIGON3_5718 ||
13897 tp->pdev->device == TG3PCI_DEVICE_TIGON3_5719 ||
13898 tp->pdev->device == TG3PCI_DEVICE_TIGON3_5720)
13899 pci_read_config_dword(tp->pdev,
13900 TG3PCI_GEN2_PRODID_ASICREV,
13901 &prod_id_asic_rev);
13902 else if (tp->pdev->device == TG3PCI_DEVICE_TIGON3_57781 ||
13903 tp->pdev->device == TG3PCI_DEVICE_TIGON3_57785 ||
13904 tp->pdev->device == TG3PCI_DEVICE_TIGON3_57761 ||
13905 tp->pdev->device == TG3PCI_DEVICE_TIGON3_57765 ||
13906 tp->pdev->device == TG3PCI_DEVICE_TIGON3_57791 ||
13907 tp->pdev->device == TG3PCI_DEVICE_TIGON3_57795 ||
13908 tp->pdev->device == TG3PCI_DEVICE_TIGON3_57762 ||
13909 tp->pdev->device == TG3PCI_DEVICE_TIGON3_57766 ||
13910 tp->pdev->device == TG3PCI_DEVICE_TIGON3_57782 ||
13911 tp->pdev->device == TG3PCI_DEVICE_TIGON3_57786)
13912 pci_read_config_dword(tp->pdev,
13913 TG3PCI_GEN15_PRODID_ASICREV,
13914 &prod_id_asic_rev);
13916 pci_read_config_dword(tp->pdev, TG3PCI_PRODID_ASICREV,
13917 &prod_id_asic_rev);
13919 tp->pci_chip_rev_id = prod_id_asic_rev;
13922 /* Wrong chip ID in 5752 A0. This code can be removed later
13923 * as A0 is not in production.
13925 if (tp->pci_chip_rev_id == CHIPREV_ID_5752_A0_HW)
13926 tp->pci_chip_rev_id = CHIPREV_ID_5752_A0;
13928 /* If we have 5702/03 A1 or A2 on certain ICH chipsets,
13929 * we need to disable memory and use config. cycles
13930 * only to access all registers. The 5702/03 chips
13931 * can mistakenly decode the special cycles from the
13932 * ICH chipsets as memory write cycles, causing corruption
13933 * of register and memory space. Only certain ICH bridges
13934 * will drive special cycles with non-zero data during the
13935 * address phase which can fall within the 5703's address
13936 * range. This is not an ICH bug as the PCI spec allows
13937 * non-zero address during special cycles. However, only
13938 * these ICH bridges are known to drive non-zero addresses
13939 * during special cycles.
13941 * Since special cycles do not cross PCI bridges, we only
13942 * enable this workaround if the 5703 is on the secondary
13943 * bus of these ICH bridges.
13945 if ((tp->pci_chip_rev_id == CHIPREV_ID_5703_A1) ||
13946 (tp->pci_chip_rev_id == CHIPREV_ID_5703_A2)) {
13947 static struct tg3_dev_id {
13951 } ich_chipsets[] = {
13952 { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801AA_8,
13954 { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801AB_8,
13956 { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801BA_11,
13958 { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801BA_6,
13962 struct tg3_dev_id *pci_id = &ich_chipsets[0];
13963 struct pci_dev *bridge = NULL;
13965 while (pci_id->vendor != 0) {
13966 bridge = pci_get_device(pci_id->vendor, pci_id->device,
13972 if (pci_id->rev != PCI_ANY_ID) {
13973 if (bridge->revision > pci_id->rev)
13976 if (bridge->subordinate &&
13977 (bridge->subordinate->number ==
13978 tp->pdev->bus->number)) {
13979 tg3_flag_set(tp, ICH_WORKAROUND);
13980 pci_dev_put(bridge);
13986 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701) {
13987 static struct tg3_dev_id {
13990 } bridge_chipsets[] = {
13991 { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_PXH_0 },
13992 { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_PXH_1 },
13995 struct tg3_dev_id *pci_id = &bridge_chipsets[0];
13996 struct pci_dev *bridge = NULL;
13998 while (pci_id->vendor != 0) {
13999 bridge = pci_get_device(pci_id->vendor,
14006 if (bridge->subordinate &&
14007 (bridge->subordinate->number <=
14008 tp->pdev->bus->number) &&
14009 (bridge->subordinate->subordinate >=
14010 tp->pdev->bus->number)) {
14011 tg3_flag_set(tp, 5701_DMA_BUG);
14012 pci_dev_put(bridge);
14018 /* The EPB bridge inside 5714, 5715, and 5780 cannot support
14019 * DMA addresses > 40-bit. This bridge may have other additional
14020 * 57xx devices behind it in some 4-port NIC designs for example.
14021 * Any tg3 device found behind the bridge will also need the 40-bit
14024 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5780 ||
14025 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5714) {
14026 tg3_flag_set(tp, 5780_CLASS);
14027 tg3_flag_set(tp, 40BIT_DMA_BUG);
14028 tp->msi_cap = pci_find_capability(tp->pdev, PCI_CAP_ID_MSI);
14030 struct pci_dev *bridge = NULL;
14033 bridge = pci_get_device(PCI_VENDOR_ID_SERVERWORKS,
14034 PCI_DEVICE_ID_SERVERWORKS_EPB,
14036 if (bridge && bridge->subordinate &&
14037 (bridge->subordinate->number <=
14038 tp->pdev->bus->number) &&
14039 (bridge->subordinate->subordinate >=
14040 tp->pdev->bus->number)) {
14041 tg3_flag_set(tp, 40BIT_DMA_BUG);
14042 pci_dev_put(bridge);
14048 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704 ||
14049 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5714)
14050 tp->pdev_peer = tg3_find_peer(tp);
14052 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717 ||
14053 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5719 ||
14054 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5720)
14055 tg3_flag_set(tp, 5717_PLUS);
14057 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57765 ||
14058 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57766)
14059 tg3_flag_set(tp, 57765_CLASS);
14061 if (tg3_flag(tp, 57765_CLASS) || tg3_flag(tp, 5717_PLUS))
14062 tg3_flag_set(tp, 57765_PLUS);
14064 /* Intentionally exclude ASIC_REV_5906 */
14065 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5755 ||
14066 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5787 ||
14067 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5784 ||
14068 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5761 ||
14069 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785 ||
14070 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57780 ||
14071 tg3_flag(tp, 57765_PLUS))
14072 tg3_flag_set(tp, 5755_PLUS);
14074 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5750 ||
14075 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5752 ||
14076 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906 ||
14077 tg3_flag(tp, 5755_PLUS) ||
14078 tg3_flag(tp, 5780_CLASS))
14079 tg3_flag_set(tp, 5750_PLUS);
14081 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705 ||
14082 tg3_flag(tp, 5750_PLUS))
14083 tg3_flag_set(tp, 5705_PLUS);
14085 /* Determine TSO capabilities */
14086 if (tp->pci_chip_rev_id == CHIPREV_ID_5719_A0)
14087 ; /* Do nothing. HW bug. */
14088 else if (tg3_flag(tp, 57765_PLUS))
14089 tg3_flag_set(tp, HW_TSO_3);
14090 else if (tg3_flag(tp, 5755_PLUS) ||
14091 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906)
14092 tg3_flag_set(tp, HW_TSO_2);
14093 else if (tg3_flag(tp, 5750_PLUS)) {
14094 tg3_flag_set(tp, HW_TSO_1);
14095 tg3_flag_set(tp, TSO_BUG);
14096 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5750 &&
14097 tp->pci_chip_rev_id >= CHIPREV_ID_5750_C2)
14098 tg3_flag_clear(tp, TSO_BUG);
14099 } else if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5700 &&
14100 GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5701 &&
14101 tp->pci_chip_rev_id != CHIPREV_ID_5705_A0) {
14102 tg3_flag_set(tp, TSO_BUG);
14103 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705)
14104 tp->fw_needed = FIRMWARE_TG3TSO5;
14106 tp->fw_needed = FIRMWARE_TG3TSO;
14109 /* Selectively allow TSO based on operating conditions */
14110 if (tg3_flag(tp, HW_TSO_1) ||
14111 tg3_flag(tp, HW_TSO_2) ||
14112 tg3_flag(tp, HW_TSO_3) ||
14114 /* For firmware TSO, assume ASF is disabled.
14115 * We'll disable TSO later if we discover ASF
14116 * is enabled in tg3_get_eeprom_hw_cfg().
14118 tg3_flag_set(tp, TSO_CAPABLE);
14120 tg3_flag_clear(tp, TSO_CAPABLE);
14121 tg3_flag_clear(tp, TSO_BUG);
14122 tp->fw_needed = NULL;
14125 if (tp->pci_chip_rev_id == CHIPREV_ID_5701_A0)
14126 tp->fw_needed = FIRMWARE_TG3;
14130 if (tg3_flag(tp, 5750_PLUS)) {
14131 tg3_flag_set(tp, SUPPORT_MSI);
14132 if (GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5750_AX ||
14133 GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5750_BX ||
14134 (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5714 &&
14135 tp->pci_chip_rev_id <= CHIPREV_ID_5714_A2 &&
14136 tp->pdev_peer == tp->pdev))
14137 tg3_flag_clear(tp, SUPPORT_MSI);
14139 if (tg3_flag(tp, 5755_PLUS) ||
14140 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
14141 tg3_flag_set(tp, 1SHOT_MSI);
14144 if (tg3_flag(tp, 57765_PLUS)) {
14145 tg3_flag_set(tp, SUPPORT_MSIX);
14146 tp->irq_max = TG3_IRQ_MAX_VECS;
14147 tg3_rss_init_dflt_indir_tbl(tp);
14151 if (tg3_flag(tp, 5755_PLUS))
14152 tg3_flag_set(tp, SHORT_DMA_BUG);
14154 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5719)
14155 tp->dma_limit = TG3_TX_BD_DMA_MAX_4K;
14156 else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57766)
14157 tp->dma_limit = TG3_TX_BD_DMA_MAX_2K;
14159 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717 ||
14160 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5719 ||
14161 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5720)
14162 tg3_flag_set(tp, LRG_PROD_RING_CAP);
14164 if (tg3_flag(tp, 57765_PLUS) &&
14165 tp->pci_chip_rev_id != CHIPREV_ID_5719_A0)
14166 tg3_flag_set(tp, USE_JUMBO_BDFLAG);
14168 if (!tg3_flag(tp, 5705_PLUS) ||
14169 tg3_flag(tp, 5780_CLASS) ||
14170 tg3_flag(tp, USE_JUMBO_BDFLAG))
14171 tg3_flag_set(tp, JUMBO_CAPABLE);
14173 pci_read_config_dword(tp->pdev, TG3PCI_PCISTATE,
14176 if (pci_is_pcie(tp->pdev)) {
14179 tg3_flag_set(tp, PCI_EXPRESS);
14181 if (tp->pci_chip_rev_id == CHIPREV_ID_5719_A0) {
14182 int readrq = pcie_get_readrq(tp->pdev);
14184 pcie_set_readrq(tp->pdev, 2048);
14187 pci_read_config_word(tp->pdev,
14188 pci_pcie_cap(tp->pdev) + PCI_EXP_LNKCTL,
14190 if (lnkctl & PCI_EXP_LNKCTL_CLKREQ_EN) {
14191 if (GET_ASIC_REV(tp->pci_chip_rev_id) ==
14193 tg3_flag_clear(tp, HW_TSO_2);
14194 tg3_flag_clear(tp, TSO_CAPABLE);
14196 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5784 ||
14197 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5761 ||
14198 tp->pci_chip_rev_id == CHIPREV_ID_57780_A0 ||
14199 tp->pci_chip_rev_id == CHIPREV_ID_57780_A1)
14200 tg3_flag_set(tp, CLKREQ_BUG);
14201 } else if (tp->pci_chip_rev_id == CHIPREV_ID_5717_A0) {
14202 tg3_flag_set(tp, L1PLLPD_EN);
14204 } else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785) {
14205 /* BCM5785 devices are effectively PCIe devices, and should
14206 * follow PCIe codepaths, but do not have a PCIe capabilities
14209 tg3_flag_set(tp, PCI_EXPRESS);
14210 } else if (!tg3_flag(tp, 5705_PLUS) ||
14211 tg3_flag(tp, 5780_CLASS)) {
14212 tp->pcix_cap = pci_find_capability(tp->pdev, PCI_CAP_ID_PCIX);
14213 if (!tp->pcix_cap) {
14214 dev_err(&tp->pdev->dev,
14215 "Cannot find PCI-X capability, aborting\n");
14219 if (!(pci_state_reg & PCISTATE_CONV_PCI_MODE))
14220 tg3_flag_set(tp, PCIX_MODE);
14223 /* If we have an AMD 762 or VIA K8T800 chipset, write
14224 * reordering to the mailbox registers done by the host
14225 * controller can cause major troubles. We read back from
14226 * every mailbox register write to force the writes to be
14227 * posted to the chip in order.
14229 if (pci_dev_present(tg3_write_reorder_chipsets) &&
14230 !tg3_flag(tp, PCI_EXPRESS))
14231 tg3_flag_set(tp, MBOX_WRITE_REORDER);
14233 pci_read_config_byte(tp->pdev, PCI_CACHE_LINE_SIZE,
14234 &tp->pci_cacheline_sz);
14235 pci_read_config_byte(tp->pdev, PCI_LATENCY_TIMER,
14236 &tp->pci_lat_timer);
14237 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703 &&
14238 tp->pci_lat_timer < 64) {
14239 tp->pci_lat_timer = 64;
14240 pci_write_config_byte(tp->pdev, PCI_LATENCY_TIMER,
14241 tp->pci_lat_timer);
14244 /* Important! -- It is critical that the PCI-X hw workaround
14245 * situation is decided before the first MMIO register access.
14247 if (GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5700_BX) {
14248 /* 5700 BX chips need to have their TX producer index
14249 * mailboxes written twice to workaround a bug.
14251 tg3_flag_set(tp, TXD_MBOX_HWBUG);
14253 /* If we are in PCI-X mode, enable register write workaround.
14255 * The workaround is to use indirect register accesses
14256 * for all chip writes not to mailbox registers.
14258 if (tg3_flag(tp, PCIX_MODE)) {
14261 tg3_flag_set(tp, PCIX_TARGET_HWBUG);
14263 /* The chip can have it's power management PCI config
14264 * space registers clobbered due to this bug.
14265 * So explicitly force the chip into D0 here.
14267 pci_read_config_dword(tp->pdev,
14268 tp->pm_cap + PCI_PM_CTRL,
14270 pm_reg &= ~PCI_PM_CTRL_STATE_MASK;
14271 pm_reg |= PCI_PM_CTRL_PME_ENABLE | 0 /* D0 */;
14272 pci_write_config_dword(tp->pdev,
14273 tp->pm_cap + PCI_PM_CTRL,
14276 /* Also, force SERR#/PERR# in PCI command. */
14277 pci_read_config_word(tp->pdev, PCI_COMMAND, &pci_cmd);
14278 pci_cmd |= PCI_COMMAND_PARITY | PCI_COMMAND_SERR;
14279 pci_write_config_word(tp->pdev, PCI_COMMAND, pci_cmd);
14283 if ((pci_state_reg & PCISTATE_BUS_SPEED_HIGH) != 0)
14284 tg3_flag_set(tp, PCI_HIGH_SPEED);
14285 if ((pci_state_reg & PCISTATE_BUS_32BIT) != 0)
14286 tg3_flag_set(tp, PCI_32BIT);
14288 /* Chip-specific fixup from Broadcom driver */
14289 if ((tp->pci_chip_rev_id == CHIPREV_ID_5704_A0) &&
14290 (!(pci_state_reg & PCISTATE_RETRY_SAME_DMA))) {
14291 pci_state_reg |= PCISTATE_RETRY_SAME_DMA;
14292 pci_write_config_dword(tp->pdev, TG3PCI_PCISTATE, pci_state_reg);
14295 /* Default fast path register access methods */
14296 tp->read32 = tg3_read32;
14297 tp->write32 = tg3_write32;
14298 tp->read32_mbox = tg3_read32;
14299 tp->write32_mbox = tg3_write32;
14300 tp->write32_tx_mbox = tg3_write32;
14301 tp->write32_rx_mbox = tg3_write32;
14303 /* Various workaround register access methods */
14304 if (tg3_flag(tp, PCIX_TARGET_HWBUG))
14305 tp->write32 = tg3_write_indirect_reg32;
14306 else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701 ||
14307 (tg3_flag(tp, PCI_EXPRESS) &&
14308 tp->pci_chip_rev_id == CHIPREV_ID_5750_A0)) {
14310 * Back to back register writes can cause problems on these
14311 * chips, the workaround is to read back all reg writes
14312 * except those to mailbox regs.
14314 * See tg3_write_indirect_reg32().
14316 tp->write32 = tg3_write_flush_reg32;
14319 if (tg3_flag(tp, TXD_MBOX_HWBUG) || tg3_flag(tp, MBOX_WRITE_REORDER)) {
14320 tp->write32_tx_mbox = tg3_write32_tx_mbox;
14321 if (tg3_flag(tp, MBOX_WRITE_REORDER))
14322 tp->write32_rx_mbox = tg3_write_flush_reg32;
14325 if (tg3_flag(tp, ICH_WORKAROUND)) {
14326 tp->read32 = tg3_read_indirect_reg32;
14327 tp->write32 = tg3_write_indirect_reg32;
14328 tp->read32_mbox = tg3_read_indirect_mbox;
14329 tp->write32_mbox = tg3_write_indirect_mbox;
14330 tp->write32_tx_mbox = tg3_write_indirect_mbox;
14331 tp->write32_rx_mbox = tg3_write_indirect_mbox;
14336 pci_read_config_word(tp->pdev, PCI_COMMAND, &pci_cmd);
14337 pci_cmd &= ~PCI_COMMAND_MEMORY;
14338 pci_write_config_word(tp->pdev, PCI_COMMAND, pci_cmd);
14340 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
14341 tp->read32_mbox = tg3_read32_mbox_5906;
14342 tp->write32_mbox = tg3_write32_mbox_5906;
14343 tp->write32_tx_mbox = tg3_write32_mbox_5906;
14344 tp->write32_rx_mbox = tg3_write32_mbox_5906;
14347 if (tp->write32 == tg3_write_indirect_reg32 ||
14348 (tg3_flag(tp, PCIX_MODE) &&
14349 (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
14350 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701)))
14351 tg3_flag_set(tp, SRAM_USE_CONFIG);
14353 /* The memory arbiter has to be enabled in order for SRAM accesses
14354 * to succeed. Normally on powerup the tg3 chip firmware will make
14355 * sure it is enabled, but other entities such as system netboot
14356 * code might disable it.
14358 val = tr32(MEMARB_MODE);
14359 tw32(MEMARB_MODE, val | MEMARB_MODE_ENABLE);
14361 tp->pci_fn = PCI_FUNC(tp->pdev->devfn) & 3;
14362 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704 ||
14363 tg3_flag(tp, 5780_CLASS)) {
14364 if (tg3_flag(tp, PCIX_MODE)) {
14365 pci_read_config_dword(tp->pdev,
14366 tp->pcix_cap + PCI_X_STATUS,
14368 tp->pci_fn = val & 0x7;
14370 } else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717) {
14371 tg3_read_mem(tp, NIC_SRAM_CPMU_STATUS, &val);
14372 if ((val & NIC_SRAM_CPMUSTAT_SIG_MSK) ==
14373 NIC_SRAM_CPMUSTAT_SIG) {
14374 tp->pci_fn = val & TG3_CPMU_STATUS_FMSK_5717;
14375 tp->pci_fn = tp->pci_fn ? 1 : 0;
14377 } else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5719 ||
14378 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5720) {
14379 tg3_read_mem(tp, NIC_SRAM_CPMU_STATUS, &val);
14380 if ((val & NIC_SRAM_CPMUSTAT_SIG_MSK) ==
14381 NIC_SRAM_CPMUSTAT_SIG) {
14382 tp->pci_fn = (val & TG3_CPMU_STATUS_FMSK_5719) >>
14383 TG3_CPMU_STATUS_FSHFT_5719;
14387 /* Get eeprom hw config before calling tg3_set_power_state().
14388 * In particular, the TG3_FLAG_IS_NIC flag must be
14389 * determined before calling tg3_set_power_state() so that
14390 * we know whether or not to switch out of Vaux power.
14391 * When the flag is set, it means that GPIO1 is used for eeprom
14392 * write protect and also implies that it is a LOM where GPIOs
14393 * are not used to switch power.
14395 tg3_get_eeprom_hw_cfg(tp);
14397 if (tp->fw_needed && tg3_flag(tp, ENABLE_ASF)) {
14398 tg3_flag_clear(tp, TSO_CAPABLE);
14399 tg3_flag_clear(tp, TSO_BUG);
14400 tp->fw_needed = NULL;
14403 if (tg3_flag(tp, ENABLE_APE)) {
14404 /* Allow reads and writes to the
14405 * APE register and memory space.
14407 pci_state_reg |= PCISTATE_ALLOW_APE_CTLSPC_WR |
14408 PCISTATE_ALLOW_APE_SHMEM_WR |
14409 PCISTATE_ALLOW_APE_PSPACE_WR;
14410 pci_write_config_dword(tp->pdev, TG3PCI_PCISTATE,
14413 tg3_ape_lock_init(tp);
14416 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5784 ||
14417 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5761 ||
14418 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785 ||
14419 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57780 ||
14420 tg3_flag(tp, 57765_PLUS))
14421 tg3_flag_set(tp, CPMU_PRESENT);
14423 /* Set up tp->grc_local_ctrl before calling
14424 * tg3_pwrsrc_switch_to_vmain(). GPIO1 driven high
14425 * will bring 5700's external PHY out of reset.
14426 * It is also used as eeprom write protect on LOMs.
14428 tp->grc_local_ctrl = GRC_LCLCTRL_INT_ON_ATTN | GRC_LCLCTRL_AUTO_SEEPROM;
14429 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
14430 tg3_flag(tp, EEPROM_WRITE_PROT))
14431 tp->grc_local_ctrl |= (GRC_LCLCTRL_GPIO_OE1 |
14432 GRC_LCLCTRL_GPIO_OUTPUT1);
14433 /* Unused GPIO3 must be driven as output on 5752 because there
14434 * are no pull-up resistors on unused GPIO pins.
14436 else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5752)
14437 tp->grc_local_ctrl |= GRC_LCLCTRL_GPIO_OE3;
14439 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5755 ||
14440 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57780 ||
14441 tg3_flag(tp, 57765_CLASS))
14442 tp->grc_local_ctrl |= GRC_LCLCTRL_GPIO_UART_SEL;
14444 if (tp->pdev->device == PCI_DEVICE_ID_TIGON3_5761 ||
14445 tp->pdev->device == TG3PCI_DEVICE_TIGON3_5761S) {
14446 /* Turn off the debug UART. */
14447 tp->grc_local_ctrl |= GRC_LCLCTRL_GPIO_UART_SEL;
14448 if (tg3_flag(tp, IS_NIC))
14449 /* Keep VMain power. */
14450 tp->grc_local_ctrl |= GRC_LCLCTRL_GPIO_OE0 |
14451 GRC_LCLCTRL_GPIO_OUTPUT0;
14454 /* Switch out of Vaux if it is a NIC */
14455 tg3_pwrsrc_switch_to_vmain(tp);
14457 /* Derive initial jumbo mode from MTU assigned in
14458 * ether_setup() via the alloc_etherdev() call
14460 if (tp->dev->mtu > ETH_DATA_LEN && !tg3_flag(tp, 5780_CLASS))
14461 tg3_flag_set(tp, JUMBO_RING_ENABLE);
14463 /* Determine WakeOnLan speed to use. */
14464 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
14465 tp->pci_chip_rev_id == CHIPREV_ID_5701_A0 ||
14466 tp->pci_chip_rev_id == CHIPREV_ID_5701_B0 ||
14467 tp->pci_chip_rev_id == CHIPREV_ID_5701_B2) {
14468 tg3_flag_clear(tp, WOL_SPEED_100MB);
14470 tg3_flag_set(tp, WOL_SPEED_100MB);
14473 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906)
14474 tp->phy_flags |= TG3_PHYFLG_IS_FET;
14476 /* A few boards don't want Ethernet@WireSpeed phy feature */
14477 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
14478 (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705 &&
14479 (tp->pci_chip_rev_id != CHIPREV_ID_5705_A0) &&
14480 (tp->pci_chip_rev_id != CHIPREV_ID_5705_A1)) ||
14481 (tp->phy_flags & TG3_PHYFLG_IS_FET) ||
14482 (tp->phy_flags & TG3_PHYFLG_ANY_SERDES))
14483 tp->phy_flags |= TG3_PHYFLG_NO_ETH_WIRE_SPEED;
14485 if (GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5703_AX ||
14486 GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5704_AX)
14487 tp->phy_flags |= TG3_PHYFLG_ADC_BUG;
14488 if (tp->pci_chip_rev_id == CHIPREV_ID_5704_A0)
14489 tp->phy_flags |= TG3_PHYFLG_5704_A0_BUG;
14491 if (tg3_flag(tp, 5705_PLUS) &&
14492 !(tp->phy_flags & TG3_PHYFLG_IS_FET) &&
14493 GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5785 &&
14494 GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_57780 &&
14495 !tg3_flag(tp, 57765_PLUS)) {
14496 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5755 ||
14497 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5787 ||
14498 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5784 ||
14499 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5761) {
14500 if (tp->pdev->device != PCI_DEVICE_ID_TIGON3_5756 &&
14501 tp->pdev->device != PCI_DEVICE_ID_TIGON3_5722)
14502 tp->phy_flags |= TG3_PHYFLG_JITTER_BUG;
14503 if (tp->pdev->device == PCI_DEVICE_ID_TIGON3_5755M)
14504 tp->phy_flags |= TG3_PHYFLG_ADJUST_TRIM;
14506 tp->phy_flags |= TG3_PHYFLG_BER_BUG;
14509 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5784 &&
14510 GET_CHIP_REV(tp->pci_chip_rev_id) != CHIPREV_5784_AX) {
14511 tp->phy_otp = tg3_read_otp_phycfg(tp);
14512 if (tp->phy_otp == 0)
14513 tp->phy_otp = TG3_OTP_DEFAULT;
14516 if (tg3_flag(tp, CPMU_PRESENT))
14517 tp->mi_mode = MAC_MI_MODE_500KHZ_CONST;
14519 tp->mi_mode = MAC_MI_MODE_BASE;
14521 tp->coalesce_mode = 0;
14522 if (GET_CHIP_REV(tp->pci_chip_rev_id) != CHIPREV_5700_AX &&
14523 GET_CHIP_REV(tp->pci_chip_rev_id) != CHIPREV_5700_BX)
14524 tp->coalesce_mode |= HOSTCC_MODE_32BYTE;
14526 /* Set these bits to enable statistics workaround. */
14527 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717 ||
14528 tp->pci_chip_rev_id == CHIPREV_ID_5719_A0 ||
14529 tp->pci_chip_rev_id == CHIPREV_ID_5720_A0) {
14530 tp->coalesce_mode |= HOSTCC_MODE_ATTN;
14531 tp->grc_mode |= GRC_MODE_IRQ_ON_FLOW_ATTN;
14534 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785 ||
14535 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57780)
14536 tg3_flag_set(tp, USE_PHYLIB);
14538 err = tg3_mdio_init(tp);
14542 /* Initialize data/descriptor byte/word swapping. */
14543 val = tr32(GRC_MODE);
14544 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5720)
14545 val &= (GRC_MODE_BYTE_SWAP_B2HRX_DATA |
14546 GRC_MODE_WORD_SWAP_B2HRX_DATA |
14547 GRC_MODE_B2HRX_ENABLE |
14548 GRC_MODE_HTX2B_ENABLE |
14549 GRC_MODE_HOST_STACKUP);
14551 val &= GRC_MODE_HOST_STACKUP;
14553 tw32(GRC_MODE, val | tp->grc_mode);
14555 tg3_switch_clocks(tp);
14557 /* Clear this out for sanity. */
14558 tw32(TG3PCI_MEM_WIN_BASE_ADDR, 0);
14560 pci_read_config_dword(tp->pdev, TG3PCI_PCISTATE,
14562 if ((pci_state_reg & PCISTATE_CONV_PCI_MODE) == 0 &&
14563 !tg3_flag(tp, PCIX_TARGET_HWBUG)) {
14564 u32 chiprevid = GET_CHIP_REV_ID(tp->misc_host_ctrl);
14566 if (chiprevid == CHIPREV_ID_5701_A0 ||
14567 chiprevid == CHIPREV_ID_5701_B0 ||
14568 chiprevid == CHIPREV_ID_5701_B2 ||
14569 chiprevid == CHIPREV_ID_5701_B5) {
14570 void __iomem *sram_base;
14572 /* Write some dummy words into the SRAM status block
14573 * area, see if it reads back correctly. If the return
14574 * value is bad, force enable the PCIX workaround.
14576 sram_base = tp->regs + NIC_SRAM_WIN_BASE + NIC_SRAM_STATS_BLK;
14578 writel(0x00000000, sram_base);
14579 writel(0x00000000, sram_base + 4);
14580 writel(0xffffffff, sram_base + 4);
14581 if (readl(sram_base) != 0x00000000)
14582 tg3_flag_set(tp, PCIX_TARGET_HWBUG);
14587 tg3_nvram_init(tp);
14589 grc_misc_cfg = tr32(GRC_MISC_CFG);
14590 grc_misc_cfg &= GRC_MISC_CFG_BOARD_ID_MASK;
14592 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705 &&
14593 (grc_misc_cfg == GRC_MISC_CFG_BOARD_ID_5788 ||
14594 grc_misc_cfg == GRC_MISC_CFG_BOARD_ID_5788M))
14595 tg3_flag_set(tp, IS_5788);
14597 if (!tg3_flag(tp, IS_5788) &&
14598 GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5700)
14599 tg3_flag_set(tp, TAGGED_STATUS);
14600 if (tg3_flag(tp, TAGGED_STATUS)) {
14601 tp->coalesce_mode |= (HOSTCC_MODE_CLRTICK_RXBD |
14602 HOSTCC_MODE_CLRTICK_TXBD);
14604 tp->misc_host_ctrl |= MISC_HOST_CTRL_TAGGED_STATUS;
14605 pci_write_config_dword(tp->pdev, TG3PCI_MISC_HOST_CTRL,
14606 tp->misc_host_ctrl);
14609 /* Preserve the APE MAC_MODE bits */
14610 if (tg3_flag(tp, ENABLE_APE))
14611 tp->mac_mode = MAC_MODE_APE_TX_EN | MAC_MODE_APE_RX_EN;
14615 /* these are limited to 10/100 only */
14616 if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703 &&
14617 (grc_misc_cfg == 0x8000 || grc_misc_cfg == 0x4000)) ||
14618 (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705 &&
14619 tp->pdev->vendor == PCI_VENDOR_ID_BROADCOM &&
14620 (tp->pdev->device == PCI_DEVICE_ID_TIGON3_5901 ||
14621 tp->pdev->device == PCI_DEVICE_ID_TIGON3_5901_2 ||
14622 tp->pdev->device == PCI_DEVICE_ID_TIGON3_5705F)) ||
14623 (tp->pdev->vendor == PCI_VENDOR_ID_BROADCOM &&
14624 (tp->pdev->device == PCI_DEVICE_ID_TIGON3_5751F ||
14625 tp->pdev->device == PCI_DEVICE_ID_TIGON3_5753F ||
14626 tp->pdev->device == PCI_DEVICE_ID_TIGON3_5787F)) ||
14627 tp->pdev->device == TG3PCI_DEVICE_TIGON3_57790 ||
14628 tp->pdev->device == TG3PCI_DEVICE_TIGON3_57791 ||
14629 tp->pdev->device == TG3PCI_DEVICE_TIGON3_57795 ||
14630 (tp->phy_flags & TG3_PHYFLG_IS_FET))
14631 tp->phy_flags |= TG3_PHYFLG_10_100_ONLY;
14633 err = tg3_phy_probe(tp);
14635 dev_err(&tp->pdev->dev, "phy probe failed, err %d\n", err);
14636 /* ... but do not return immediately ... */
14641 tg3_read_fw_ver(tp);
14643 if (tp->phy_flags & TG3_PHYFLG_PHY_SERDES) {
14644 tp->phy_flags &= ~TG3_PHYFLG_USE_MI_INTERRUPT;
14646 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700)
14647 tp->phy_flags |= TG3_PHYFLG_USE_MI_INTERRUPT;
14649 tp->phy_flags &= ~TG3_PHYFLG_USE_MI_INTERRUPT;
14652 /* 5700 {AX,BX} chips have a broken status block link
14653 * change bit implementation, so we must use the
14654 * status register in those cases.
14656 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700)
14657 tg3_flag_set(tp, USE_LINKCHG_REG);
14659 tg3_flag_clear(tp, USE_LINKCHG_REG);
14661 /* The led_ctrl is set during tg3_phy_probe, here we might
14662 * have to force the link status polling mechanism based
14663 * upon subsystem IDs.
14665 if (tp->pdev->subsystem_vendor == PCI_VENDOR_ID_DELL &&
14666 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701 &&
14667 !(tp->phy_flags & TG3_PHYFLG_PHY_SERDES)) {
14668 tp->phy_flags |= TG3_PHYFLG_USE_MI_INTERRUPT;
14669 tg3_flag_set(tp, USE_LINKCHG_REG);
14672 /* For all SERDES we poll the MAC status register. */
14673 if (tp->phy_flags & TG3_PHYFLG_PHY_SERDES)
14674 tg3_flag_set(tp, POLL_SERDES);
14676 tg3_flag_clear(tp, POLL_SERDES);
14678 tp->rx_offset = NET_SKB_PAD + NET_IP_ALIGN;
14679 tp->rx_copy_thresh = TG3_RX_COPY_THRESHOLD;
14680 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701 &&
14681 tg3_flag(tp, PCIX_MODE)) {
14682 tp->rx_offset = NET_SKB_PAD;
14683 #ifndef CONFIG_HAVE_EFFICIENT_UNALIGNED_ACCESS
14684 tp->rx_copy_thresh = ~(u16)0;
14688 tp->rx_std_ring_mask = TG3_RX_STD_RING_SIZE(tp) - 1;
14689 tp->rx_jmb_ring_mask = TG3_RX_JMB_RING_SIZE(tp) - 1;
14690 tp->rx_ret_ring_mask = tg3_rx_ret_ring_size(tp) - 1;
14692 tp->rx_std_max_post = tp->rx_std_ring_mask + 1;
14694 /* Increment the rx prod index on the rx std ring by at most
14695 * 8 for these chips to workaround hw errata.
14697 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5750 ||
14698 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5752 ||
14699 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5755)
14700 tp->rx_std_max_post = 8;
14702 if (tg3_flag(tp, ASPM_WORKAROUND))
14703 tp->pwrmgmt_thresh = tr32(PCIE_PWR_MGMT_THRESH) &
14704 PCIE_PWR_MGMT_L1_THRESH_MSK;
14709 #ifdef CONFIG_SPARC
14710 static int __devinit tg3_get_macaddr_sparc(struct tg3 *tp)
14712 struct net_device *dev = tp->dev;
14713 struct pci_dev *pdev = tp->pdev;
14714 struct device_node *dp = pci_device_to_OF_node(pdev);
14715 const unsigned char *addr;
14718 addr = of_get_property(dp, "local-mac-address", &len);
14719 if (addr && len == 6) {
14720 memcpy(dev->dev_addr, addr, 6);
14721 memcpy(dev->perm_addr, dev->dev_addr, 6);
14727 static int __devinit tg3_get_default_macaddr_sparc(struct tg3 *tp)
14729 struct net_device *dev = tp->dev;
14731 memcpy(dev->dev_addr, idprom->id_ethaddr, 6);
14732 memcpy(dev->perm_addr, idprom->id_ethaddr, 6);
14737 static int __devinit tg3_get_device_address(struct tg3 *tp)
14739 struct net_device *dev = tp->dev;
14740 u32 hi, lo, mac_offset;
14743 #ifdef CONFIG_SPARC
14744 if (!tg3_get_macaddr_sparc(tp))
14749 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704 ||
14750 tg3_flag(tp, 5780_CLASS)) {
14751 if (tr32(TG3PCI_DUAL_MAC_CTRL) & DUAL_MAC_CTRL_ID)
14753 if (tg3_nvram_lock(tp))
14754 tw32_f(NVRAM_CMD, NVRAM_CMD_RESET);
14756 tg3_nvram_unlock(tp);
14757 } else if (tg3_flag(tp, 5717_PLUS)) {
14758 if (tp->pci_fn & 1)
14760 if (tp->pci_fn > 1)
14761 mac_offset += 0x18c;
14762 } else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906)
14765 /* First try to get it from MAC address mailbox. */
14766 tg3_read_mem(tp, NIC_SRAM_MAC_ADDR_HIGH_MBOX, &hi);
14767 if ((hi >> 16) == 0x484b) {
14768 dev->dev_addr[0] = (hi >> 8) & 0xff;
14769 dev->dev_addr[1] = (hi >> 0) & 0xff;
14771 tg3_read_mem(tp, NIC_SRAM_MAC_ADDR_LOW_MBOX, &lo);
14772 dev->dev_addr[2] = (lo >> 24) & 0xff;
14773 dev->dev_addr[3] = (lo >> 16) & 0xff;
14774 dev->dev_addr[4] = (lo >> 8) & 0xff;
14775 dev->dev_addr[5] = (lo >> 0) & 0xff;
14777 /* Some old bootcode may report a 0 MAC address in SRAM */
14778 addr_ok = is_valid_ether_addr(&dev->dev_addr[0]);
14781 /* Next, try NVRAM. */
14782 if (!tg3_flag(tp, NO_NVRAM) &&
14783 !tg3_nvram_read_be32(tp, mac_offset + 0, &hi) &&
14784 !tg3_nvram_read_be32(tp, mac_offset + 4, &lo)) {
14785 memcpy(&dev->dev_addr[0], ((char *)&hi) + 2, 2);
14786 memcpy(&dev->dev_addr[2], (char *)&lo, sizeof(lo));
14788 /* Finally just fetch it out of the MAC control regs. */
14790 hi = tr32(MAC_ADDR_0_HIGH);
14791 lo = tr32(MAC_ADDR_0_LOW);
14793 dev->dev_addr[5] = lo & 0xff;
14794 dev->dev_addr[4] = (lo >> 8) & 0xff;
14795 dev->dev_addr[3] = (lo >> 16) & 0xff;
14796 dev->dev_addr[2] = (lo >> 24) & 0xff;
14797 dev->dev_addr[1] = hi & 0xff;
14798 dev->dev_addr[0] = (hi >> 8) & 0xff;
14802 if (!is_valid_ether_addr(&dev->dev_addr[0])) {
14803 #ifdef CONFIG_SPARC
14804 if (!tg3_get_default_macaddr_sparc(tp))
14809 memcpy(dev->perm_addr, dev->dev_addr, dev->addr_len);
14813 #define BOUNDARY_SINGLE_CACHELINE 1
14814 #define BOUNDARY_MULTI_CACHELINE 2
14816 static u32 __devinit tg3_calc_dma_bndry(struct tg3 *tp, u32 val)
14818 int cacheline_size;
14822 pci_read_config_byte(tp->pdev, PCI_CACHE_LINE_SIZE, &byte);
14824 cacheline_size = 1024;
14826 cacheline_size = (int) byte * 4;
14828 /* On 5703 and later chips, the boundary bits have no
14831 if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5700 &&
14832 GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5701 &&
14833 !tg3_flag(tp, PCI_EXPRESS))
14836 #if defined(CONFIG_PPC64) || defined(CONFIG_IA64) || defined(CONFIG_PARISC)
14837 goal = BOUNDARY_MULTI_CACHELINE;
14839 #if defined(CONFIG_SPARC64) || defined(CONFIG_ALPHA)
14840 goal = BOUNDARY_SINGLE_CACHELINE;
14846 if (tg3_flag(tp, 57765_PLUS)) {
14847 val = goal ? 0 : DMA_RWCTRL_DIS_CACHE_ALIGNMENT;
14854 /* PCI controllers on most RISC systems tend to disconnect
14855 * when a device tries to burst across a cache-line boundary.
14856 * Therefore, letting tg3 do so just wastes PCI bandwidth.
14858 * Unfortunately, for PCI-E there are only limited
14859 * write-side controls for this, and thus for reads
14860 * we will still get the disconnects. We'll also waste
14861 * these PCI cycles for both read and write for chips
14862 * other than 5700 and 5701 which do not implement the
14865 if (tg3_flag(tp, PCIX_MODE) && !tg3_flag(tp, PCI_EXPRESS)) {
14866 switch (cacheline_size) {
14871 if (goal == BOUNDARY_SINGLE_CACHELINE) {
14872 val |= (DMA_RWCTRL_READ_BNDRY_128_PCIX |
14873 DMA_RWCTRL_WRITE_BNDRY_128_PCIX);
14875 val |= (DMA_RWCTRL_READ_BNDRY_384_PCIX |
14876 DMA_RWCTRL_WRITE_BNDRY_384_PCIX);
14881 val |= (DMA_RWCTRL_READ_BNDRY_256_PCIX |
14882 DMA_RWCTRL_WRITE_BNDRY_256_PCIX);
14886 val |= (DMA_RWCTRL_READ_BNDRY_384_PCIX |
14887 DMA_RWCTRL_WRITE_BNDRY_384_PCIX);
14890 } else if (tg3_flag(tp, PCI_EXPRESS)) {
14891 switch (cacheline_size) {
14895 if (goal == BOUNDARY_SINGLE_CACHELINE) {
14896 val &= ~DMA_RWCTRL_WRITE_BNDRY_DISAB_PCIE;
14897 val |= DMA_RWCTRL_WRITE_BNDRY_64_PCIE;
14903 val &= ~DMA_RWCTRL_WRITE_BNDRY_DISAB_PCIE;
14904 val |= DMA_RWCTRL_WRITE_BNDRY_128_PCIE;
14908 switch (cacheline_size) {
14910 if (goal == BOUNDARY_SINGLE_CACHELINE) {
14911 val |= (DMA_RWCTRL_READ_BNDRY_16 |
14912 DMA_RWCTRL_WRITE_BNDRY_16);
14917 if (goal == BOUNDARY_SINGLE_CACHELINE) {
14918 val |= (DMA_RWCTRL_READ_BNDRY_32 |
14919 DMA_RWCTRL_WRITE_BNDRY_32);
14924 if (goal == BOUNDARY_SINGLE_CACHELINE) {
14925 val |= (DMA_RWCTRL_READ_BNDRY_64 |
14926 DMA_RWCTRL_WRITE_BNDRY_64);
14931 if (goal == BOUNDARY_SINGLE_CACHELINE) {
14932 val |= (DMA_RWCTRL_READ_BNDRY_128 |
14933 DMA_RWCTRL_WRITE_BNDRY_128);
14938 val |= (DMA_RWCTRL_READ_BNDRY_256 |
14939 DMA_RWCTRL_WRITE_BNDRY_256);
14942 val |= (DMA_RWCTRL_READ_BNDRY_512 |
14943 DMA_RWCTRL_WRITE_BNDRY_512);
14947 val |= (DMA_RWCTRL_READ_BNDRY_1024 |
14948 DMA_RWCTRL_WRITE_BNDRY_1024);
14957 static int __devinit tg3_do_test_dma(struct tg3 *tp, u32 *buf, dma_addr_t buf_dma, int size, int to_device)
14959 struct tg3_internal_buffer_desc test_desc;
14960 u32 sram_dma_descs;
14963 sram_dma_descs = NIC_SRAM_DMA_DESC_POOL_BASE;
14965 tw32(FTQ_RCVBD_COMP_FIFO_ENQDEQ, 0);
14966 tw32(FTQ_RCVDATA_COMP_FIFO_ENQDEQ, 0);
14967 tw32(RDMAC_STATUS, 0);
14968 tw32(WDMAC_STATUS, 0);
14970 tw32(BUFMGR_MODE, 0);
14971 tw32(FTQ_RESET, 0);
14973 test_desc.addr_hi = ((u64) buf_dma) >> 32;
14974 test_desc.addr_lo = buf_dma & 0xffffffff;
14975 test_desc.nic_mbuf = 0x00002100;
14976 test_desc.len = size;
14979 * HP ZX1 was seeing test failures for 5701 cards running at 33Mhz
14980 * the *second* time the tg3 driver was getting loaded after an
14983 * Broadcom tells me:
14984 * ...the DMA engine is connected to the GRC block and a DMA
14985 * reset may affect the GRC block in some unpredictable way...
14986 * The behavior of resets to individual blocks has not been tested.
14988 * Broadcom noted the GRC reset will also reset all sub-components.
14991 test_desc.cqid_sqid = (13 << 8) | 2;
14993 tw32_f(RDMAC_MODE, RDMAC_MODE_ENABLE);
14996 test_desc.cqid_sqid = (16 << 8) | 7;
14998 tw32_f(WDMAC_MODE, WDMAC_MODE_ENABLE);
15001 test_desc.flags = 0x00000005;
15003 for (i = 0; i < (sizeof(test_desc) / sizeof(u32)); i++) {
15006 val = *(((u32 *)&test_desc) + i);
15007 pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_BASE_ADDR,
15008 sram_dma_descs + (i * sizeof(u32)));
15009 pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_DATA, val);
15011 pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_BASE_ADDR, 0);
15014 tw32(FTQ_DMA_HIGH_READ_FIFO_ENQDEQ, sram_dma_descs);
15016 tw32(FTQ_DMA_HIGH_WRITE_FIFO_ENQDEQ, sram_dma_descs);
15019 for (i = 0; i < 40; i++) {
15023 val = tr32(FTQ_RCVBD_COMP_FIFO_ENQDEQ);
15025 val = tr32(FTQ_RCVDATA_COMP_FIFO_ENQDEQ);
15026 if ((val & 0xffff) == sram_dma_descs) {
15037 #define TEST_BUFFER_SIZE 0x2000
15039 static DEFINE_PCI_DEVICE_TABLE(tg3_dma_wait_state_chipsets) = {
15040 { PCI_DEVICE(PCI_VENDOR_ID_APPLE, PCI_DEVICE_ID_APPLE_UNI_N_PCI15) },
15044 static int __devinit tg3_test_dma(struct tg3 *tp)
15046 dma_addr_t buf_dma;
15047 u32 *buf, saved_dma_rwctrl;
15050 buf = dma_alloc_coherent(&tp->pdev->dev, TEST_BUFFER_SIZE,
15051 &buf_dma, GFP_KERNEL);
15057 tp->dma_rwctrl = ((0x7 << DMA_RWCTRL_PCI_WRITE_CMD_SHIFT) |
15058 (0x6 << DMA_RWCTRL_PCI_READ_CMD_SHIFT));
15060 tp->dma_rwctrl = tg3_calc_dma_bndry(tp, tp->dma_rwctrl);
15062 if (tg3_flag(tp, 57765_PLUS))
15065 if (tg3_flag(tp, PCI_EXPRESS)) {
15066 /* DMA read watermark not used on PCIE */
15067 tp->dma_rwctrl |= 0x00180000;
15068 } else if (!tg3_flag(tp, PCIX_MODE)) {
15069 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705 ||
15070 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5750)
15071 tp->dma_rwctrl |= 0x003f0000;
15073 tp->dma_rwctrl |= 0x003f000f;
15075 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703 ||
15076 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704) {
15077 u32 ccval = (tr32(TG3PCI_CLOCK_CTRL) & 0x1f);
15078 u32 read_water = 0x7;
15080 /* If the 5704 is behind the EPB bridge, we can
15081 * do the less restrictive ONE_DMA workaround for
15082 * better performance.
15084 if (tg3_flag(tp, 40BIT_DMA_BUG) &&
15085 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704)
15086 tp->dma_rwctrl |= 0x8000;
15087 else if (ccval == 0x6 || ccval == 0x7)
15088 tp->dma_rwctrl |= DMA_RWCTRL_ONE_DMA;
15090 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703)
15092 /* Set bit 23 to enable PCIX hw bug fix */
15094 (read_water << DMA_RWCTRL_READ_WATER_SHIFT) |
15095 (0x3 << DMA_RWCTRL_WRITE_WATER_SHIFT) |
15097 } else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5780) {
15098 /* 5780 always in PCIX mode */
15099 tp->dma_rwctrl |= 0x00144000;
15100 } else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5714) {
15101 /* 5714 always in PCIX mode */
15102 tp->dma_rwctrl |= 0x00148000;
15104 tp->dma_rwctrl |= 0x001b000f;
15108 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703 ||
15109 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704)
15110 tp->dma_rwctrl &= 0xfffffff0;
15112 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
15113 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701) {
15114 /* Remove this if it causes problems for some boards. */
15115 tp->dma_rwctrl |= DMA_RWCTRL_USE_MEM_READ_MULT;
15117 /* On 5700/5701 chips, we need to set this bit.
15118 * Otherwise the chip will issue cacheline transactions
15119 * to streamable DMA memory with not all the byte
15120 * enables turned on. This is an error on several
15121 * RISC PCI controllers, in particular sparc64.
15123 * On 5703/5704 chips, this bit has been reassigned
15124 * a different meaning. In particular, it is used
15125 * on those chips to enable a PCI-X workaround.
15127 tp->dma_rwctrl |= DMA_RWCTRL_ASSERT_ALL_BE;
15130 tw32(TG3PCI_DMA_RW_CTRL, tp->dma_rwctrl);
15133 /* Unneeded, already done by tg3_get_invariants. */
15134 tg3_switch_clocks(tp);
15137 if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5700 &&
15138 GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5701)
15141 /* It is best to perform DMA test with maximum write burst size
15142 * to expose the 5700/5701 write DMA bug.
15144 saved_dma_rwctrl = tp->dma_rwctrl;
15145 tp->dma_rwctrl &= ~DMA_RWCTRL_WRITE_BNDRY_MASK;
15146 tw32(TG3PCI_DMA_RW_CTRL, tp->dma_rwctrl);
15151 for (i = 0; i < TEST_BUFFER_SIZE / sizeof(u32); i++)
15154 /* Send the buffer to the chip. */
15155 ret = tg3_do_test_dma(tp, buf, buf_dma, TEST_BUFFER_SIZE, 1);
15157 dev_err(&tp->pdev->dev,
15158 "%s: Buffer write failed. err = %d\n",
15164 /* validate data reached card RAM correctly. */
15165 for (i = 0; i < TEST_BUFFER_SIZE / sizeof(u32); i++) {
15167 tg3_read_mem(tp, 0x2100 + (i*4), &val);
15168 if (le32_to_cpu(val) != p[i]) {
15169 dev_err(&tp->pdev->dev,
15170 "%s: Buffer corrupted on device! "
15171 "(%d != %d)\n", __func__, val, i);
15172 /* ret = -ENODEV here? */
15177 /* Now read it back. */
15178 ret = tg3_do_test_dma(tp, buf, buf_dma, TEST_BUFFER_SIZE, 0);
15180 dev_err(&tp->pdev->dev, "%s: Buffer read failed. "
15181 "err = %d\n", __func__, ret);
15186 for (i = 0; i < TEST_BUFFER_SIZE / sizeof(u32); i++) {
15190 if ((tp->dma_rwctrl & DMA_RWCTRL_WRITE_BNDRY_MASK) !=
15191 DMA_RWCTRL_WRITE_BNDRY_16) {
15192 tp->dma_rwctrl &= ~DMA_RWCTRL_WRITE_BNDRY_MASK;
15193 tp->dma_rwctrl |= DMA_RWCTRL_WRITE_BNDRY_16;
15194 tw32(TG3PCI_DMA_RW_CTRL, tp->dma_rwctrl);
15197 dev_err(&tp->pdev->dev,
15198 "%s: Buffer corrupted on read back! "
15199 "(%d != %d)\n", __func__, p[i], i);
15205 if (i == (TEST_BUFFER_SIZE / sizeof(u32))) {
15211 if ((tp->dma_rwctrl & DMA_RWCTRL_WRITE_BNDRY_MASK) !=
15212 DMA_RWCTRL_WRITE_BNDRY_16) {
15213 /* DMA test passed without adjusting DMA boundary,
15214 * now look for chipsets that are known to expose the
15215 * DMA bug without failing the test.
15217 if (pci_dev_present(tg3_dma_wait_state_chipsets)) {
15218 tp->dma_rwctrl &= ~DMA_RWCTRL_WRITE_BNDRY_MASK;
15219 tp->dma_rwctrl |= DMA_RWCTRL_WRITE_BNDRY_16;
15221 /* Safe to use the calculated DMA boundary. */
15222 tp->dma_rwctrl = saved_dma_rwctrl;
15225 tw32(TG3PCI_DMA_RW_CTRL, tp->dma_rwctrl);
15229 dma_free_coherent(&tp->pdev->dev, TEST_BUFFER_SIZE, buf, buf_dma);
15234 static void __devinit tg3_init_bufmgr_config(struct tg3 *tp)
15236 if (tg3_flag(tp, 57765_PLUS)) {
15237 tp->bufmgr_config.mbuf_read_dma_low_water =
15238 DEFAULT_MB_RDMA_LOW_WATER_5705;
15239 tp->bufmgr_config.mbuf_mac_rx_low_water =
15240 DEFAULT_MB_MACRX_LOW_WATER_57765;
15241 tp->bufmgr_config.mbuf_high_water =
15242 DEFAULT_MB_HIGH_WATER_57765;
15244 tp->bufmgr_config.mbuf_read_dma_low_water_jumbo =
15245 DEFAULT_MB_RDMA_LOW_WATER_5705;
15246 tp->bufmgr_config.mbuf_mac_rx_low_water_jumbo =
15247 DEFAULT_MB_MACRX_LOW_WATER_JUMBO_57765;
15248 tp->bufmgr_config.mbuf_high_water_jumbo =
15249 DEFAULT_MB_HIGH_WATER_JUMBO_57765;
15250 } else if (tg3_flag(tp, 5705_PLUS)) {
15251 tp->bufmgr_config.mbuf_read_dma_low_water =
15252 DEFAULT_MB_RDMA_LOW_WATER_5705;
15253 tp->bufmgr_config.mbuf_mac_rx_low_water =
15254 DEFAULT_MB_MACRX_LOW_WATER_5705;
15255 tp->bufmgr_config.mbuf_high_water =
15256 DEFAULT_MB_HIGH_WATER_5705;
15257 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
15258 tp->bufmgr_config.mbuf_mac_rx_low_water =
15259 DEFAULT_MB_MACRX_LOW_WATER_5906;
15260 tp->bufmgr_config.mbuf_high_water =
15261 DEFAULT_MB_HIGH_WATER_5906;
15264 tp->bufmgr_config.mbuf_read_dma_low_water_jumbo =
15265 DEFAULT_MB_RDMA_LOW_WATER_JUMBO_5780;
15266 tp->bufmgr_config.mbuf_mac_rx_low_water_jumbo =
15267 DEFAULT_MB_MACRX_LOW_WATER_JUMBO_5780;
15268 tp->bufmgr_config.mbuf_high_water_jumbo =
15269 DEFAULT_MB_HIGH_WATER_JUMBO_5780;
15271 tp->bufmgr_config.mbuf_read_dma_low_water =
15272 DEFAULT_MB_RDMA_LOW_WATER;
15273 tp->bufmgr_config.mbuf_mac_rx_low_water =
15274 DEFAULT_MB_MACRX_LOW_WATER;
15275 tp->bufmgr_config.mbuf_high_water =
15276 DEFAULT_MB_HIGH_WATER;
15278 tp->bufmgr_config.mbuf_read_dma_low_water_jumbo =
15279 DEFAULT_MB_RDMA_LOW_WATER_JUMBO;
15280 tp->bufmgr_config.mbuf_mac_rx_low_water_jumbo =
15281 DEFAULT_MB_MACRX_LOW_WATER_JUMBO;
15282 tp->bufmgr_config.mbuf_high_water_jumbo =
15283 DEFAULT_MB_HIGH_WATER_JUMBO;
15286 tp->bufmgr_config.dma_low_water = DEFAULT_DMA_LOW_WATER;
15287 tp->bufmgr_config.dma_high_water = DEFAULT_DMA_HIGH_WATER;
15290 static char * __devinit tg3_phy_string(struct tg3 *tp)
15292 switch (tp->phy_id & TG3_PHY_ID_MASK) {
15293 case TG3_PHY_ID_BCM5400: return "5400";
15294 case TG3_PHY_ID_BCM5401: return "5401";
15295 case TG3_PHY_ID_BCM5411: return "5411";
15296 case TG3_PHY_ID_BCM5701: return "5701";
15297 case TG3_PHY_ID_BCM5703: return "5703";
15298 case TG3_PHY_ID_BCM5704: return "5704";
15299 case TG3_PHY_ID_BCM5705: return "5705";
15300 case TG3_PHY_ID_BCM5750: return "5750";
15301 case TG3_PHY_ID_BCM5752: return "5752";
15302 case TG3_PHY_ID_BCM5714: return "5714";
15303 case TG3_PHY_ID_BCM5780: return "5780";
15304 case TG3_PHY_ID_BCM5755: return "5755";
15305 case TG3_PHY_ID_BCM5787: return "5787";
15306 case TG3_PHY_ID_BCM5784: return "5784";
15307 case TG3_PHY_ID_BCM5756: return "5722/5756";
15308 case TG3_PHY_ID_BCM5906: return "5906";
15309 case TG3_PHY_ID_BCM5761: return "5761";
15310 case TG3_PHY_ID_BCM5718C: return "5718C";
15311 case TG3_PHY_ID_BCM5718S: return "5718S";
15312 case TG3_PHY_ID_BCM57765: return "57765";
15313 case TG3_PHY_ID_BCM5719C: return "5719C";
15314 case TG3_PHY_ID_BCM5720C: return "5720C";
15315 case TG3_PHY_ID_BCM8002: return "8002/serdes";
15316 case 0: return "serdes";
15317 default: return "unknown";
15321 static char * __devinit tg3_bus_string(struct tg3 *tp, char *str)
15323 if (tg3_flag(tp, PCI_EXPRESS)) {
15324 strcpy(str, "PCI Express");
15326 } else if (tg3_flag(tp, PCIX_MODE)) {
15327 u32 clock_ctrl = tr32(TG3PCI_CLOCK_CTRL) & 0x1f;
15329 strcpy(str, "PCIX:");
15331 if ((clock_ctrl == 7) ||
15332 ((tr32(GRC_MISC_CFG) & GRC_MISC_CFG_BOARD_ID_MASK) ==
15333 GRC_MISC_CFG_BOARD_ID_5704CIOBE))
15334 strcat(str, "133MHz");
15335 else if (clock_ctrl == 0)
15336 strcat(str, "33MHz");
15337 else if (clock_ctrl == 2)
15338 strcat(str, "50MHz");
15339 else if (clock_ctrl == 4)
15340 strcat(str, "66MHz");
15341 else if (clock_ctrl == 6)
15342 strcat(str, "100MHz");
15344 strcpy(str, "PCI:");
15345 if (tg3_flag(tp, PCI_HIGH_SPEED))
15346 strcat(str, "66MHz");
15348 strcat(str, "33MHz");
15350 if (tg3_flag(tp, PCI_32BIT))
15351 strcat(str, ":32-bit");
15353 strcat(str, ":64-bit");
15357 static struct pci_dev * __devinit tg3_find_peer(struct tg3 *tp)
15359 struct pci_dev *peer;
15360 unsigned int func, devnr = tp->pdev->devfn & ~7;
15362 for (func = 0; func < 8; func++) {
15363 peer = pci_get_slot(tp->pdev->bus, devnr | func);
15364 if (peer && peer != tp->pdev)
15368 /* 5704 can be configured in single-port mode, set peer to
15369 * tp->pdev in that case.
15377 * We don't need to keep the refcount elevated; there's no way
15378 * to remove one half of this device without removing the other
15385 static void __devinit tg3_init_coal(struct tg3 *tp)
15387 struct ethtool_coalesce *ec = &tp->coal;
15389 memset(ec, 0, sizeof(*ec));
15390 ec->cmd = ETHTOOL_GCOALESCE;
15391 ec->rx_coalesce_usecs = LOW_RXCOL_TICKS;
15392 ec->tx_coalesce_usecs = LOW_TXCOL_TICKS;
15393 ec->rx_max_coalesced_frames = LOW_RXMAX_FRAMES;
15394 ec->tx_max_coalesced_frames = LOW_TXMAX_FRAMES;
15395 ec->rx_coalesce_usecs_irq = DEFAULT_RXCOAL_TICK_INT;
15396 ec->tx_coalesce_usecs_irq = DEFAULT_TXCOAL_TICK_INT;
15397 ec->rx_max_coalesced_frames_irq = DEFAULT_RXCOAL_MAXF_INT;
15398 ec->tx_max_coalesced_frames_irq = DEFAULT_TXCOAL_MAXF_INT;
15399 ec->stats_block_coalesce_usecs = DEFAULT_STAT_COAL_TICKS;
15401 if (tp->coalesce_mode & (HOSTCC_MODE_CLRTICK_RXBD |
15402 HOSTCC_MODE_CLRTICK_TXBD)) {
15403 ec->rx_coalesce_usecs = LOW_RXCOL_TICKS_CLRTCKS;
15404 ec->rx_coalesce_usecs_irq = DEFAULT_RXCOAL_TICK_INT_CLRTCKS;
15405 ec->tx_coalesce_usecs = LOW_TXCOL_TICKS_CLRTCKS;
15406 ec->tx_coalesce_usecs_irq = DEFAULT_TXCOAL_TICK_INT_CLRTCKS;
15409 if (tg3_flag(tp, 5705_PLUS)) {
15410 ec->rx_coalesce_usecs_irq = 0;
15411 ec->tx_coalesce_usecs_irq = 0;
15412 ec->stats_block_coalesce_usecs = 0;
15416 static const struct net_device_ops tg3_netdev_ops = {
15417 .ndo_open = tg3_open,
15418 .ndo_stop = tg3_close,
15419 .ndo_start_xmit = tg3_start_xmit,
15420 .ndo_get_stats64 = tg3_get_stats64,
15421 .ndo_validate_addr = eth_validate_addr,
15422 .ndo_set_rx_mode = tg3_set_rx_mode,
15423 .ndo_set_mac_address = tg3_set_mac_addr,
15424 .ndo_do_ioctl = tg3_ioctl,
15425 .ndo_tx_timeout = tg3_tx_timeout,
15426 .ndo_change_mtu = tg3_change_mtu,
15427 .ndo_fix_features = tg3_fix_features,
15428 .ndo_set_features = tg3_set_features,
15429 #ifdef CONFIG_NET_POLL_CONTROLLER
15430 .ndo_poll_controller = tg3_poll_controller,
15434 static int __devinit tg3_init_one(struct pci_dev *pdev,
15435 const struct pci_device_id *ent)
15437 struct net_device *dev;
15439 int i, err, pm_cap;
15440 u32 sndmbx, rcvmbx, intmbx;
15442 u64 dma_mask, persist_dma_mask;
15443 netdev_features_t features = 0;
15445 printk_once(KERN_INFO "%s\n", version);
15447 err = pci_enable_device(pdev);
15449 dev_err(&pdev->dev, "Cannot enable PCI device, aborting\n");
15453 err = pci_request_regions(pdev, DRV_MODULE_NAME);
15455 dev_err(&pdev->dev, "Cannot obtain PCI resources, aborting\n");
15456 goto err_out_disable_pdev;
15459 pci_set_master(pdev);
15461 /* Find power-management capability. */
15462 pm_cap = pci_find_capability(pdev, PCI_CAP_ID_PM);
15464 dev_err(&pdev->dev,
15465 "Cannot find Power Management capability, aborting\n");
15467 goto err_out_free_res;
15470 err = pci_set_power_state(pdev, PCI_D0);
15472 dev_err(&pdev->dev, "Transition to D0 failed, aborting\n");
15473 goto err_out_free_res;
15476 dev = alloc_etherdev_mq(sizeof(*tp), TG3_IRQ_MAX_VECS);
15478 dev_err(&pdev->dev, "Etherdev alloc failed, aborting\n");
15480 goto err_out_power_down;
15483 SET_NETDEV_DEV(dev, &pdev->dev);
15485 tp = netdev_priv(dev);
15488 tp->pm_cap = pm_cap;
15489 tp->rx_mode = TG3_DEF_RX_MODE;
15490 tp->tx_mode = TG3_DEF_TX_MODE;
15493 tp->msg_enable = tg3_debug;
15495 tp->msg_enable = TG3_DEF_MSG_ENABLE;
15497 /* The word/byte swap controls here control register access byte
15498 * swapping. DMA data byte swapping is controlled in the GRC_MODE
15501 tp->misc_host_ctrl =
15502 MISC_HOST_CTRL_MASK_PCI_INT |
15503 MISC_HOST_CTRL_WORD_SWAP |
15504 MISC_HOST_CTRL_INDIR_ACCESS |
15505 MISC_HOST_CTRL_PCISTATE_RW;
15507 /* The NONFRM (non-frame) byte/word swap controls take effect
15508 * on descriptor entries, anything which isn't packet data.
15510 * The StrongARM chips on the board (one for tx, one for rx)
15511 * are running in big-endian mode.
15513 tp->grc_mode = (GRC_MODE_WSWAP_DATA | GRC_MODE_BSWAP_DATA |
15514 GRC_MODE_WSWAP_NONFRM_DATA);
15515 #ifdef __BIG_ENDIAN
15516 tp->grc_mode |= GRC_MODE_BSWAP_NONFRM_DATA;
15518 spin_lock_init(&tp->lock);
15519 spin_lock_init(&tp->indirect_lock);
15520 INIT_WORK(&tp->reset_task, tg3_reset_task);
15522 tp->regs = pci_ioremap_bar(pdev, BAR_0);
15524 dev_err(&pdev->dev, "Cannot map device registers, aborting\n");
15526 goto err_out_free_dev;
15529 if (tp->pdev->device == PCI_DEVICE_ID_TIGON3_5761 ||
15530 tp->pdev->device == PCI_DEVICE_ID_TIGON3_5761E ||
15531 tp->pdev->device == TG3PCI_DEVICE_TIGON3_5761S ||
15532 tp->pdev->device == TG3PCI_DEVICE_TIGON3_5761SE ||
15533 tp->pdev->device == TG3PCI_DEVICE_TIGON3_5717 ||
15534 tp->pdev->device == TG3PCI_DEVICE_TIGON3_5718 ||
15535 tp->pdev->device == TG3PCI_DEVICE_TIGON3_5719 ||
15536 tp->pdev->device == TG3PCI_DEVICE_TIGON3_5720) {
15537 tg3_flag_set(tp, ENABLE_APE);
15538 tp->aperegs = pci_ioremap_bar(pdev, BAR_2);
15539 if (!tp->aperegs) {
15540 dev_err(&pdev->dev,
15541 "Cannot map APE registers, aborting\n");
15543 goto err_out_iounmap;
15547 tp->rx_pending = TG3_DEF_RX_RING_PENDING;
15548 tp->rx_jumbo_pending = TG3_DEF_RX_JUMBO_RING_PENDING;
15550 dev->ethtool_ops = &tg3_ethtool_ops;
15551 dev->watchdog_timeo = TG3_TX_TIMEOUT;
15552 dev->netdev_ops = &tg3_netdev_ops;
15553 dev->irq = pdev->irq;
15555 err = tg3_get_invariants(tp);
15557 dev_err(&pdev->dev,
15558 "Problem fetching invariants of chip, aborting\n");
15559 goto err_out_apeunmap;
15562 /* The EPB bridge inside 5714, 5715, and 5780 and any
15563 * device behind the EPB cannot support DMA addresses > 40-bit.
15564 * On 64-bit systems with IOMMU, use 40-bit dma_mask.
15565 * On 64-bit systems without IOMMU, use 64-bit dma_mask and
15566 * do DMA address check in tg3_start_xmit().
15568 if (tg3_flag(tp, IS_5788))
15569 persist_dma_mask = dma_mask = DMA_BIT_MASK(32);
15570 else if (tg3_flag(tp, 40BIT_DMA_BUG)) {
15571 persist_dma_mask = dma_mask = DMA_BIT_MASK(40);
15572 #ifdef CONFIG_HIGHMEM
15573 dma_mask = DMA_BIT_MASK(64);
15576 persist_dma_mask = dma_mask = DMA_BIT_MASK(64);
15578 /* Configure DMA attributes. */
15579 if (dma_mask > DMA_BIT_MASK(32)) {
15580 err = pci_set_dma_mask(pdev, dma_mask);
15582 features |= NETIF_F_HIGHDMA;
15583 err = pci_set_consistent_dma_mask(pdev,
15586 dev_err(&pdev->dev, "Unable to obtain 64 bit "
15587 "DMA for consistent allocations\n");
15588 goto err_out_apeunmap;
15592 if (err || dma_mask == DMA_BIT_MASK(32)) {
15593 err = pci_set_dma_mask(pdev, DMA_BIT_MASK(32));
15595 dev_err(&pdev->dev,
15596 "No usable DMA configuration, aborting\n");
15597 goto err_out_apeunmap;
15601 tg3_init_bufmgr_config(tp);
15603 features |= NETIF_F_HW_VLAN_TX | NETIF_F_HW_VLAN_RX;
15605 /* 5700 B0 chips do not support checksumming correctly due
15606 * to hardware bugs.
15608 if (tp->pci_chip_rev_id != CHIPREV_ID_5700_B0) {
15609 features |= NETIF_F_SG | NETIF_F_IP_CSUM | NETIF_F_RXCSUM;
15611 if (tg3_flag(tp, 5755_PLUS))
15612 features |= NETIF_F_IPV6_CSUM;
15615 /* TSO is on by default on chips that support hardware TSO.
15616 * Firmware TSO on older chips gives lower performance, so it
15617 * is off by default, but can be enabled using ethtool.
15619 if ((tg3_flag(tp, HW_TSO_1) ||
15620 tg3_flag(tp, HW_TSO_2) ||
15621 tg3_flag(tp, HW_TSO_3)) &&
15622 (features & NETIF_F_IP_CSUM))
15623 features |= NETIF_F_TSO;
15624 if (tg3_flag(tp, HW_TSO_2) || tg3_flag(tp, HW_TSO_3)) {
15625 if (features & NETIF_F_IPV6_CSUM)
15626 features |= NETIF_F_TSO6;
15627 if (tg3_flag(tp, HW_TSO_3) ||
15628 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5761 ||
15629 (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5784 &&
15630 GET_CHIP_REV(tp->pci_chip_rev_id) != CHIPREV_5784_AX) ||
15631 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785 ||
15632 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57780)
15633 features |= NETIF_F_TSO_ECN;
15636 dev->features |= features;
15637 dev->vlan_features |= features;
15640 * Add loopback capability only for a subset of devices that support
15641 * MAC-LOOPBACK. Eventually this need to be enhanced to allow INT-PHY
15642 * loopback for the remaining devices.
15644 if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5780 &&
15645 !tg3_flag(tp, CPMU_PRESENT))
15646 /* Add the loopback capability */
15647 features |= NETIF_F_LOOPBACK;
15649 dev->hw_features |= features;
15651 if (tp->pci_chip_rev_id == CHIPREV_ID_5705_A1 &&
15652 !tg3_flag(tp, TSO_CAPABLE) &&
15653 !(tr32(TG3PCI_PCISTATE) & PCISTATE_BUS_SPEED_HIGH)) {
15654 tg3_flag_set(tp, MAX_RXPEND_64);
15655 tp->rx_pending = 63;
15658 err = tg3_get_device_address(tp);
15660 dev_err(&pdev->dev,
15661 "Could not obtain valid ethernet address, aborting\n");
15662 goto err_out_apeunmap;
15666 * Reset chip in case UNDI or EFI driver did not shutdown
15667 * DMA self test will enable WDMAC and we'll see (spurious)
15668 * pending DMA on the PCI bus at that point.
15670 if ((tr32(HOSTCC_MODE) & HOSTCC_MODE_ENABLE) ||
15671 (tr32(WDMAC_MODE) & WDMAC_MODE_ENABLE)) {
15672 tw32(MEMARB_MODE, MEMARB_MODE_ENABLE);
15673 tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
15676 err = tg3_test_dma(tp);
15678 dev_err(&pdev->dev, "DMA engine test failed, aborting\n");
15679 goto err_out_apeunmap;
15682 intmbx = MAILBOX_INTERRUPT_0 + TG3_64BIT_REG_LOW;
15683 rcvmbx = MAILBOX_RCVRET_CON_IDX_0 + TG3_64BIT_REG_LOW;
15684 sndmbx = MAILBOX_SNDHOST_PROD_IDX_0 + TG3_64BIT_REG_LOW;
15685 for (i = 0; i < tp->irq_max; i++) {
15686 struct tg3_napi *tnapi = &tp->napi[i];
15689 tnapi->tx_pending = TG3_DEF_TX_RING_PENDING;
15691 tnapi->int_mbox = intmbx;
15697 tnapi->consmbox = rcvmbx;
15698 tnapi->prodmbox = sndmbx;
15701 tnapi->coal_now = HOSTCC_MODE_COAL_VEC1_NOW << (i - 1);
15703 tnapi->coal_now = HOSTCC_MODE_NOW;
15705 if (!tg3_flag(tp, SUPPORT_MSIX))
15709 * If we support MSIX, we'll be using RSS. If we're using
15710 * RSS, the first vector only handles link interrupts and the
15711 * remaining vectors handle rx and tx interrupts. Reuse the
15712 * mailbox values for the next iteration. The values we setup
15713 * above are still useful for the single vectored mode.
15728 pci_set_drvdata(pdev, dev);
15730 if (tg3_flag(tp, 5717_PLUS)) {
15731 /* Resume a low-power mode */
15732 tg3_frob_aux_power(tp, false);
15735 err = register_netdev(dev);
15737 dev_err(&pdev->dev, "Cannot register net device, aborting\n");
15738 goto err_out_apeunmap;
15741 netdev_info(dev, "Tigon3 [partno(%s) rev %04x] (%s) MAC address %pM\n",
15742 tp->board_part_number,
15743 tp->pci_chip_rev_id,
15744 tg3_bus_string(tp, str),
15747 if (tp->phy_flags & TG3_PHYFLG_IS_CONNECTED) {
15748 struct phy_device *phydev;
15749 phydev = tp->mdio_bus->phy_map[TG3_PHY_MII_ADDR];
15751 "attached PHY driver [%s] (mii_bus:phy_addr=%s)\n",
15752 phydev->drv->name, dev_name(&phydev->dev));
15756 if (tp->phy_flags & TG3_PHYFLG_10_100_ONLY)
15757 ethtype = "10/100Base-TX";
15758 else if (tp->phy_flags & TG3_PHYFLG_ANY_SERDES)
15759 ethtype = "1000Base-SX";
15761 ethtype = "10/100/1000Base-T";
15763 netdev_info(dev, "attached PHY is %s (%s Ethernet) "
15764 "(WireSpeed[%d], EEE[%d])\n",
15765 tg3_phy_string(tp), ethtype,
15766 (tp->phy_flags & TG3_PHYFLG_NO_ETH_WIRE_SPEED) == 0,
15767 (tp->phy_flags & TG3_PHYFLG_EEE_CAP) != 0);
15770 netdev_info(dev, "RXcsums[%d] LinkChgREG[%d] MIirq[%d] ASF[%d] TSOcap[%d]\n",
15771 (dev->features & NETIF_F_RXCSUM) != 0,
15772 tg3_flag(tp, USE_LINKCHG_REG) != 0,
15773 (tp->phy_flags & TG3_PHYFLG_USE_MI_INTERRUPT) != 0,
15774 tg3_flag(tp, ENABLE_ASF) != 0,
15775 tg3_flag(tp, TSO_CAPABLE) != 0);
15776 netdev_info(dev, "dma_rwctrl[%08x] dma_mask[%d-bit]\n",
15778 pdev->dma_mask == DMA_BIT_MASK(32) ? 32 :
15779 ((u64)pdev->dma_mask) == DMA_BIT_MASK(40) ? 40 : 64);
15781 pci_save_state(pdev);
15787 iounmap(tp->aperegs);
15788 tp->aperegs = NULL;
15800 err_out_power_down:
15801 pci_set_power_state(pdev, PCI_D3hot);
15804 pci_release_regions(pdev);
15806 err_out_disable_pdev:
15807 pci_disable_device(pdev);
15808 pci_set_drvdata(pdev, NULL);
15812 static void __devexit tg3_remove_one(struct pci_dev *pdev)
15814 struct net_device *dev = pci_get_drvdata(pdev);
15817 struct tg3 *tp = netdev_priv(dev);
15820 release_firmware(tp->fw);
15822 tg3_reset_task_cancel(tp);
15824 if (tg3_flag(tp, USE_PHYLIB)) {
15829 unregister_netdev(dev);
15831 iounmap(tp->aperegs);
15832 tp->aperegs = NULL;
15839 pci_release_regions(pdev);
15840 pci_disable_device(pdev);
15841 pci_set_drvdata(pdev, NULL);
15845 #ifdef CONFIG_PM_SLEEP
15846 static int tg3_suspend(struct device *device)
15848 struct pci_dev *pdev = to_pci_dev(device);
15849 struct net_device *dev = pci_get_drvdata(pdev);
15850 struct tg3 *tp = netdev_priv(dev);
15853 if (!netif_running(dev))
15856 tg3_reset_task_cancel(tp);
15858 tg3_netif_stop(tp);
15860 del_timer_sync(&tp->timer);
15862 tg3_full_lock(tp, 1);
15863 tg3_disable_ints(tp);
15864 tg3_full_unlock(tp);
15866 netif_device_detach(dev);
15868 tg3_full_lock(tp, 0);
15869 tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
15870 tg3_flag_clear(tp, INIT_COMPLETE);
15871 tg3_full_unlock(tp);
15873 err = tg3_power_down_prepare(tp);
15877 tg3_full_lock(tp, 0);
15879 tg3_flag_set(tp, INIT_COMPLETE);
15880 err2 = tg3_restart_hw(tp, 1);
15884 tp->timer.expires = jiffies + tp->timer_offset;
15885 add_timer(&tp->timer);
15887 netif_device_attach(dev);
15888 tg3_netif_start(tp);
15891 tg3_full_unlock(tp);
15900 static int tg3_resume(struct device *device)
15902 struct pci_dev *pdev = to_pci_dev(device);
15903 struct net_device *dev = pci_get_drvdata(pdev);
15904 struct tg3 *tp = netdev_priv(dev);
15907 if (!netif_running(dev))
15910 netif_device_attach(dev);
15912 tg3_full_lock(tp, 0);
15914 tg3_flag_set(tp, INIT_COMPLETE);
15915 err = tg3_restart_hw(tp, 1);
15919 tp->timer.expires = jiffies + tp->timer_offset;
15920 add_timer(&tp->timer);
15922 tg3_netif_start(tp);
15925 tg3_full_unlock(tp);
15933 static SIMPLE_DEV_PM_OPS(tg3_pm_ops, tg3_suspend, tg3_resume);
15934 #define TG3_PM_OPS (&tg3_pm_ops)
15938 #define TG3_PM_OPS NULL
15940 #endif /* CONFIG_PM_SLEEP */
15943 * tg3_io_error_detected - called when PCI error is detected
15944 * @pdev: Pointer to PCI device
15945 * @state: The current pci connection state
15947 * This function is called after a PCI bus error affecting
15948 * this device has been detected.
15950 static pci_ers_result_t tg3_io_error_detected(struct pci_dev *pdev,
15951 pci_channel_state_t state)
15953 struct net_device *netdev = pci_get_drvdata(pdev);
15954 struct tg3 *tp = netdev_priv(netdev);
15955 pci_ers_result_t err = PCI_ERS_RESULT_NEED_RESET;
15957 netdev_info(netdev, "PCI I/O error detected\n");
15961 if (!netif_running(netdev))
15966 tg3_netif_stop(tp);
15968 del_timer_sync(&tp->timer);
15970 /* Want to make sure that the reset task doesn't run */
15971 tg3_reset_task_cancel(tp);
15972 tg3_flag_clear(tp, TX_RECOVERY_PENDING);
15974 netif_device_detach(netdev);
15976 /* Clean up software state, even if MMIO is blocked */
15977 tg3_full_lock(tp, 0);
15978 tg3_halt(tp, RESET_KIND_SHUTDOWN, 0);
15979 tg3_full_unlock(tp);
15982 if (state == pci_channel_io_perm_failure)
15983 err = PCI_ERS_RESULT_DISCONNECT;
15985 pci_disable_device(pdev);
15993 * tg3_io_slot_reset - called after the pci bus has been reset.
15994 * @pdev: Pointer to PCI device
15996 * Restart the card from scratch, as if from a cold-boot.
15997 * At this point, the card has exprienced a hard reset,
15998 * followed by fixups by BIOS, and has its config space
15999 * set up identically to what it was at cold boot.
16001 static pci_ers_result_t tg3_io_slot_reset(struct pci_dev *pdev)
16003 struct net_device *netdev = pci_get_drvdata(pdev);
16004 struct tg3 *tp = netdev_priv(netdev);
16005 pci_ers_result_t rc = PCI_ERS_RESULT_DISCONNECT;
16010 if (pci_enable_device(pdev)) {
16011 netdev_err(netdev, "Cannot re-enable PCI device after reset.\n");
16015 pci_set_master(pdev);
16016 pci_restore_state(pdev);
16017 pci_save_state(pdev);
16019 if (!netif_running(netdev)) {
16020 rc = PCI_ERS_RESULT_RECOVERED;
16024 err = tg3_power_up(tp);
16028 rc = PCI_ERS_RESULT_RECOVERED;
16037 * tg3_io_resume - called when traffic can start flowing again.
16038 * @pdev: Pointer to PCI device
16040 * This callback is called when the error recovery driver tells
16041 * us that its OK to resume normal operation.
16043 static void tg3_io_resume(struct pci_dev *pdev)
16045 struct net_device *netdev = pci_get_drvdata(pdev);
16046 struct tg3 *tp = netdev_priv(netdev);
16051 if (!netif_running(netdev))
16054 tg3_full_lock(tp, 0);
16055 tg3_flag_set(tp, INIT_COMPLETE);
16056 err = tg3_restart_hw(tp, 1);
16057 tg3_full_unlock(tp);
16059 netdev_err(netdev, "Cannot restart hardware after reset.\n");
16063 netif_device_attach(netdev);
16065 tp->timer.expires = jiffies + tp->timer_offset;
16066 add_timer(&tp->timer);
16068 tg3_netif_start(tp);
16076 static struct pci_error_handlers tg3_err_handler = {
16077 .error_detected = tg3_io_error_detected,
16078 .slot_reset = tg3_io_slot_reset,
16079 .resume = tg3_io_resume
16082 static struct pci_driver tg3_driver = {
16083 .name = DRV_MODULE_NAME,
16084 .id_table = tg3_pci_tbl,
16085 .probe = tg3_init_one,
16086 .remove = __devexit_p(tg3_remove_one),
16087 .err_handler = &tg3_err_handler,
16088 .driver.pm = TG3_PM_OPS,
16091 static int __init tg3_init(void)
16093 return pci_register_driver(&tg3_driver);
16096 static void __exit tg3_cleanup(void)
16098 pci_unregister_driver(&tg3_driver);
16101 module_init(tg3_init);
16102 module_exit(tg3_cleanup);