2 * tg3.c: Broadcom Tigon3 ethernet driver.
4 * Copyright (C) 2001, 2002, 2003, 2004 David S. Miller (davem@redhat.com)
5 * Copyright (C) 2001, 2002, 2003 Jeff Garzik (jgarzik@pobox.com)
6 * Copyright (C) 2004 Sun Microsystems Inc.
7 * Copyright (C) 2005-2011 Broadcom Corporation.
10 * Derived from proprietary unpublished source code,
11 * Copyright (C) 2000-2003 Broadcom Corporation.
13 * Permission is hereby granted for the distribution of this firmware
14 * data in hexadecimal or equivalent format, provided this copyright
15 * notice is accompanying it.
19 #include <linux/module.h>
20 #include <linux/moduleparam.h>
21 #include <linux/stringify.h>
22 #include <linux/kernel.h>
23 #include <linux/types.h>
24 #include <linux/compiler.h>
25 #include <linux/slab.h>
26 #include <linux/delay.h>
28 #include <linux/init.h>
29 #include <linux/interrupt.h>
30 #include <linux/ioport.h>
31 #include <linux/pci.h>
32 #include <linux/netdevice.h>
33 #include <linux/etherdevice.h>
34 #include <linux/skbuff.h>
35 #include <linux/ethtool.h>
36 #include <linux/mdio.h>
37 #include <linux/mii.h>
38 #include <linux/phy.h>
39 #include <linux/brcmphy.h>
40 #include <linux/if_vlan.h>
42 #include <linux/tcp.h>
43 #include <linux/workqueue.h>
44 #include <linux/prefetch.h>
45 #include <linux/dma-mapping.h>
46 #include <linux/firmware.h>
48 #include <net/checksum.h>
51 #include <asm/system.h>
53 #include <asm/byteorder.h>
54 #include <linux/uaccess.h>
57 #include <asm/idprom.h>
66 /* Functions & macros to verify TG3_FLAGS types */
68 static inline int _tg3_flag(enum TG3_FLAGS flag, unsigned long *bits)
70 return test_bit(flag, bits);
73 static inline void _tg3_flag_set(enum TG3_FLAGS flag, unsigned long *bits)
78 static inline void _tg3_flag_clear(enum TG3_FLAGS flag, unsigned long *bits)
80 clear_bit(flag, bits);
83 #define tg3_flag(tp, flag) \
84 _tg3_flag(TG3_FLAG_##flag, (tp)->tg3_flags)
85 #define tg3_flag_set(tp, flag) \
86 _tg3_flag_set(TG3_FLAG_##flag, (tp)->tg3_flags)
87 #define tg3_flag_clear(tp, flag) \
88 _tg3_flag_clear(TG3_FLAG_##flag, (tp)->tg3_flags)
90 #define DRV_MODULE_NAME "tg3"
92 #define TG3_MIN_NUM 122
93 #define DRV_MODULE_VERSION \
94 __stringify(TG3_MAJ_NUM) "." __stringify(TG3_MIN_NUM)
95 #define DRV_MODULE_RELDATE "December 7, 2011"
97 #define RESET_KIND_SHUTDOWN 0
98 #define RESET_KIND_INIT 1
99 #define RESET_KIND_SUSPEND 2
101 #define TG3_DEF_RX_MODE 0
102 #define TG3_DEF_TX_MODE 0
103 #define TG3_DEF_MSG_ENABLE \
113 #define TG3_GRC_LCLCTL_PWRSW_DELAY 100
115 /* length of time before we decide the hardware is borked,
116 * and dev->tx_timeout() should be called to fix the problem
119 #define TG3_TX_TIMEOUT (5 * HZ)
121 /* hardware minimum and maximum for a single frame's data payload */
122 #define TG3_MIN_MTU 60
123 #define TG3_MAX_MTU(tp) \
124 (tg3_flag(tp, JUMBO_CAPABLE) ? 9000 : 1500)
126 /* These numbers seem to be hard coded in the NIC firmware somehow.
127 * You can't change the ring sizes, but you can change where you place
128 * them in the NIC onboard memory.
130 #define TG3_RX_STD_RING_SIZE(tp) \
131 (tg3_flag(tp, LRG_PROD_RING_CAP) ? \
132 TG3_RX_STD_MAX_SIZE_5717 : TG3_RX_STD_MAX_SIZE_5700)
133 #define TG3_DEF_RX_RING_PENDING 200
134 #define TG3_RX_JMB_RING_SIZE(tp) \
135 (tg3_flag(tp, LRG_PROD_RING_CAP) ? \
136 TG3_RX_JMB_MAX_SIZE_5717 : TG3_RX_JMB_MAX_SIZE_5700)
137 #define TG3_DEF_RX_JUMBO_RING_PENDING 100
139 /* Do not place this n-ring entries value into the tp struct itself,
140 * we really want to expose these constants to GCC so that modulo et
141 * al. operations are done with shifts and masks instead of with
142 * hw multiply/modulo instructions. Another solution would be to
143 * replace things like '% foo' with '& (foo - 1)'.
146 #define TG3_TX_RING_SIZE 512
147 #define TG3_DEF_TX_RING_PENDING (TG3_TX_RING_SIZE - 1)
149 #define TG3_RX_STD_RING_BYTES(tp) \
150 (sizeof(struct tg3_rx_buffer_desc) * TG3_RX_STD_RING_SIZE(tp))
151 #define TG3_RX_JMB_RING_BYTES(tp) \
152 (sizeof(struct tg3_ext_rx_buffer_desc) * TG3_RX_JMB_RING_SIZE(tp))
153 #define TG3_RX_RCB_RING_BYTES(tp) \
154 (sizeof(struct tg3_rx_buffer_desc) * (tp->rx_ret_ring_mask + 1))
155 #define TG3_TX_RING_BYTES (sizeof(struct tg3_tx_buffer_desc) * \
157 #define NEXT_TX(N) (((N) + 1) & (TG3_TX_RING_SIZE - 1))
159 #define TG3_DMA_BYTE_ENAB 64
161 #define TG3_RX_STD_DMA_SZ 1536
162 #define TG3_RX_JMB_DMA_SZ 9046
164 #define TG3_RX_DMA_TO_MAP_SZ(x) ((x) + TG3_DMA_BYTE_ENAB)
166 #define TG3_RX_STD_MAP_SZ TG3_RX_DMA_TO_MAP_SZ(TG3_RX_STD_DMA_SZ)
167 #define TG3_RX_JMB_MAP_SZ TG3_RX_DMA_TO_MAP_SZ(TG3_RX_JMB_DMA_SZ)
169 #define TG3_RX_STD_BUFF_RING_SIZE(tp) \
170 (sizeof(struct ring_info) * TG3_RX_STD_RING_SIZE(tp))
172 #define TG3_RX_JMB_BUFF_RING_SIZE(tp) \
173 (sizeof(struct ring_info) * TG3_RX_JMB_RING_SIZE(tp))
175 /* Due to a hardware bug, the 5701 can only DMA to memory addresses
176 * that are at least dword aligned when used in PCIX mode. The driver
177 * works around this bug by double copying the packet. This workaround
178 * is built into the normal double copy length check for efficiency.
180 * However, the double copy is only necessary on those architectures
181 * where unaligned memory accesses are inefficient. For those architectures
182 * where unaligned memory accesses incur little penalty, we can reintegrate
183 * the 5701 in the normal rx path. Doing so saves a device structure
184 * dereference by hardcoding the double copy threshold in place.
186 #define TG3_RX_COPY_THRESHOLD 256
187 #if NET_IP_ALIGN == 0 || defined(CONFIG_HAVE_EFFICIENT_UNALIGNED_ACCESS)
188 #define TG3_RX_COPY_THRESH(tp) TG3_RX_COPY_THRESHOLD
190 #define TG3_RX_COPY_THRESH(tp) ((tp)->rx_copy_thresh)
193 #if (NET_IP_ALIGN != 0)
194 #define TG3_RX_OFFSET(tp) ((tp)->rx_offset)
196 #define TG3_RX_OFFSET(tp) (NET_SKB_PAD)
199 /* minimum number of free TX descriptors required to wake up TX process */
200 #define TG3_TX_WAKEUP_THRESH(tnapi) ((tnapi)->tx_pending / 4)
201 #define TG3_TX_BD_DMA_MAX_2K 2048
202 #define TG3_TX_BD_DMA_MAX_4K 4096
204 #define TG3_RAW_IP_ALIGN 2
206 #define TG3_FW_UPDATE_TIMEOUT_SEC 5
208 #define FIRMWARE_TG3 "tigon/tg3.bin"
209 #define FIRMWARE_TG3TSO "tigon/tg3_tso.bin"
210 #define FIRMWARE_TG3TSO5 "tigon/tg3_tso5.bin"
212 static char version[] __devinitdata =
213 DRV_MODULE_NAME ".c:v" DRV_MODULE_VERSION " (" DRV_MODULE_RELDATE ")";
215 MODULE_AUTHOR("David S. Miller (davem@redhat.com) and Jeff Garzik (jgarzik@pobox.com)");
216 MODULE_DESCRIPTION("Broadcom Tigon3 ethernet driver");
217 MODULE_LICENSE("GPL");
218 MODULE_VERSION(DRV_MODULE_VERSION);
219 MODULE_FIRMWARE(FIRMWARE_TG3);
220 MODULE_FIRMWARE(FIRMWARE_TG3TSO);
221 MODULE_FIRMWARE(FIRMWARE_TG3TSO5);
223 static int tg3_debug = -1; /* -1 == use TG3_DEF_MSG_ENABLE as value */
224 module_param(tg3_debug, int, 0);
225 MODULE_PARM_DESC(tg3_debug, "Tigon3 bitmapped debugging message enable value");
227 static DEFINE_PCI_DEVICE_TABLE(tg3_pci_tbl) = {
228 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5700)},
229 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5701)},
230 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5702)},
231 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5703)},
232 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5704)},
233 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5702FE)},
234 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5705)},
235 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5705_2)},
236 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5705M)},
237 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5705M_2)},
238 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5702X)},
239 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5703X)},
240 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5704S)},
241 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5702A3)},
242 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5703A3)},
243 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5782)},
244 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5788)},
245 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5789)},
246 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5901)},
247 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5901_2)},
248 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5704S_2)},
249 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5705F)},
250 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5721)},
251 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5722)},
252 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5751)},
253 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5751M)},
254 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5751F)},
255 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5752)},
256 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5752M)},
257 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5753)},
258 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5753M)},
259 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5753F)},
260 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5754)},
261 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5754M)},
262 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5755)},
263 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5755M)},
264 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5756)},
265 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5786)},
266 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5787)},
267 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5787M)},
268 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5787F)},
269 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5714)},
270 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5714S)},
271 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5715)},
272 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5715S)},
273 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5780)},
274 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5780S)},
275 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5781)},
276 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5906)},
277 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5906M)},
278 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5784)},
279 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5764)},
280 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5723)},
281 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5761)},
282 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5761E)},
283 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_5761S)},
284 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_5761SE)},
285 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_5785_G)},
286 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_5785_F)},
287 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_57780)},
288 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_57760)},
289 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_57790)},
290 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_57788)},
291 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_5717)},
292 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_5718)},
293 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_57781)},
294 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_57785)},
295 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_57761)},
296 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_57765)},
297 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_57791)},
298 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_57795)},
299 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_5719)},
300 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_5720)},
301 {PCI_DEVICE(PCI_VENDOR_ID_SYSKONNECT, PCI_DEVICE_ID_SYSKONNECT_9DXX)},
302 {PCI_DEVICE(PCI_VENDOR_ID_SYSKONNECT, PCI_DEVICE_ID_SYSKONNECT_9MXX)},
303 {PCI_DEVICE(PCI_VENDOR_ID_ALTIMA, PCI_DEVICE_ID_ALTIMA_AC1000)},
304 {PCI_DEVICE(PCI_VENDOR_ID_ALTIMA, PCI_DEVICE_ID_ALTIMA_AC1001)},
305 {PCI_DEVICE(PCI_VENDOR_ID_ALTIMA, PCI_DEVICE_ID_ALTIMA_AC1003)},
306 {PCI_DEVICE(PCI_VENDOR_ID_ALTIMA, PCI_DEVICE_ID_ALTIMA_AC9100)},
307 {PCI_DEVICE(PCI_VENDOR_ID_APPLE, PCI_DEVICE_ID_APPLE_TIGON3)},
308 {PCI_DEVICE(0x10cf, 0x11a2)}, /* Fujitsu 1000base-SX with BCM5703SKHB */
312 MODULE_DEVICE_TABLE(pci, tg3_pci_tbl);
314 static const struct {
315 const char string[ETH_GSTRING_LEN];
316 } ethtool_stats_keys[] = {
319 { "rx_ucast_packets" },
320 { "rx_mcast_packets" },
321 { "rx_bcast_packets" },
323 { "rx_align_errors" },
324 { "rx_xon_pause_rcvd" },
325 { "rx_xoff_pause_rcvd" },
326 { "rx_mac_ctrl_rcvd" },
327 { "rx_xoff_entered" },
328 { "rx_frame_too_long_errors" },
330 { "rx_undersize_packets" },
331 { "rx_in_length_errors" },
332 { "rx_out_length_errors" },
333 { "rx_64_or_less_octet_packets" },
334 { "rx_65_to_127_octet_packets" },
335 { "rx_128_to_255_octet_packets" },
336 { "rx_256_to_511_octet_packets" },
337 { "rx_512_to_1023_octet_packets" },
338 { "rx_1024_to_1522_octet_packets" },
339 { "rx_1523_to_2047_octet_packets" },
340 { "rx_2048_to_4095_octet_packets" },
341 { "rx_4096_to_8191_octet_packets" },
342 { "rx_8192_to_9022_octet_packets" },
349 { "tx_flow_control" },
351 { "tx_single_collisions" },
352 { "tx_mult_collisions" },
354 { "tx_excessive_collisions" },
355 { "tx_late_collisions" },
356 { "tx_collide_2times" },
357 { "tx_collide_3times" },
358 { "tx_collide_4times" },
359 { "tx_collide_5times" },
360 { "tx_collide_6times" },
361 { "tx_collide_7times" },
362 { "tx_collide_8times" },
363 { "tx_collide_9times" },
364 { "tx_collide_10times" },
365 { "tx_collide_11times" },
366 { "tx_collide_12times" },
367 { "tx_collide_13times" },
368 { "tx_collide_14times" },
369 { "tx_collide_15times" },
370 { "tx_ucast_packets" },
371 { "tx_mcast_packets" },
372 { "tx_bcast_packets" },
373 { "tx_carrier_sense_errors" },
377 { "dma_writeq_full" },
378 { "dma_write_prioq_full" },
382 { "rx_threshold_hit" },
384 { "dma_readq_full" },
385 { "dma_read_prioq_full" },
386 { "tx_comp_queue_full" },
388 { "ring_set_send_prod_index" },
389 { "ring_status_update" },
391 { "nic_avoided_irqs" },
392 { "nic_tx_threshold_hit" },
394 { "mbuf_lwm_thresh_hit" },
397 #define TG3_NUM_STATS ARRAY_SIZE(ethtool_stats_keys)
400 static const struct {
401 const char string[ETH_GSTRING_LEN];
402 } ethtool_test_keys[] = {
403 { "nvram test (online) " },
404 { "link test (online) " },
405 { "register test (offline)" },
406 { "memory test (offline)" },
407 { "mac loopback test (offline)" },
408 { "phy loopback test (offline)" },
409 { "ext loopback test (offline)" },
410 { "interrupt test (offline)" },
413 #define TG3_NUM_TEST ARRAY_SIZE(ethtool_test_keys)
416 static void tg3_write32(struct tg3 *tp, u32 off, u32 val)
418 writel(val, tp->regs + off);
421 static u32 tg3_read32(struct tg3 *tp, u32 off)
423 return readl(tp->regs + off);
426 static void tg3_ape_write32(struct tg3 *tp, u32 off, u32 val)
428 writel(val, tp->aperegs + off);
431 static u32 tg3_ape_read32(struct tg3 *tp, u32 off)
433 return readl(tp->aperegs + off);
436 static void tg3_write_indirect_reg32(struct tg3 *tp, u32 off, u32 val)
440 spin_lock_irqsave(&tp->indirect_lock, flags);
441 pci_write_config_dword(tp->pdev, TG3PCI_REG_BASE_ADDR, off);
442 pci_write_config_dword(tp->pdev, TG3PCI_REG_DATA, val);
443 spin_unlock_irqrestore(&tp->indirect_lock, flags);
446 static void tg3_write_flush_reg32(struct tg3 *tp, u32 off, u32 val)
448 writel(val, tp->regs + off);
449 readl(tp->regs + off);
452 static u32 tg3_read_indirect_reg32(struct tg3 *tp, u32 off)
457 spin_lock_irqsave(&tp->indirect_lock, flags);
458 pci_write_config_dword(tp->pdev, TG3PCI_REG_BASE_ADDR, off);
459 pci_read_config_dword(tp->pdev, TG3PCI_REG_DATA, &val);
460 spin_unlock_irqrestore(&tp->indirect_lock, flags);
464 static void tg3_write_indirect_mbox(struct tg3 *tp, u32 off, u32 val)
468 if (off == (MAILBOX_RCVRET_CON_IDX_0 + TG3_64BIT_REG_LOW)) {
469 pci_write_config_dword(tp->pdev, TG3PCI_RCV_RET_RING_CON_IDX +
470 TG3_64BIT_REG_LOW, val);
473 if (off == TG3_RX_STD_PROD_IDX_REG) {
474 pci_write_config_dword(tp->pdev, TG3PCI_STD_RING_PROD_IDX +
475 TG3_64BIT_REG_LOW, val);
479 spin_lock_irqsave(&tp->indirect_lock, flags);
480 pci_write_config_dword(tp->pdev, TG3PCI_REG_BASE_ADDR, off + 0x5600);
481 pci_write_config_dword(tp->pdev, TG3PCI_REG_DATA, val);
482 spin_unlock_irqrestore(&tp->indirect_lock, flags);
484 /* In indirect mode when disabling interrupts, we also need
485 * to clear the interrupt bit in the GRC local ctrl register.
487 if ((off == (MAILBOX_INTERRUPT_0 + TG3_64BIT_REG_LOW)) &&
489 pci_write_config_dword(tp->pdev, TG3PCI_MISC_LOCAL_CTRL,
490 tp->grc_local_ctrl|GRC_LCLCTRL_CLEARINT);
494 static u32 tg3_read_indirect_mbox(struct tg3 *tp, u32 off)
499 spin_lock_irqsave(&tp->indirect_lock, flags);
500 pci_write_config_dword(tp->pdev, TG3PCI_REG_BASE_ADDR, off + 0x5600);
501 pci_read_config_dword(tp->pdev, TG3PCI_REG_DATA, &val);
502 spin_unlock_irqrestore(&tp->indirect_lock, flags);
506 /* usec_wait specifies the wait time in usec when writing to certain registers
507 * where it is unsafe to read back the register without some delay.
508 * GRC_LOCAL_CTRL is one example if the GPIOs are toggled to switch power.
509 * TG3PCI_CLOCK_CTRL is another example if the clock frequencies are changed.
511 static void _tw32_flush(struct tg3 *tp, u32 off, u32 val, u32 usec_wait)
513 if (tg3_flag(tp, PCIX_TARGET_HWBUG) || tg3_flag(tp, ICH_WORKAROUND))
514 /* Non-posted methods */
515 tp->write32(tp, off, val);
518 tg3_write32(tp, off, val);
523 /* Wait again after the read for the posted method to guarantee that
524 * the wait time is met.
530 static inline void tw32_mailbox_flush(struct tg3 *tp, u32 off, u32 val)
532 tp->write32_mbox(tp, off, val);
533 if (!tg3_flag(tp, MBOX_WRITE_REORDER) && !tg3_flag(tp, ICH_WORKAROUND))
534 tp->read32_mbox(tp, off);
537 static void tg3_write32_tx_mbox(struct tg3 *tp, u32 off, u32 val)
539 void __iomem *mbox = tp->regs + off;
541 if (tg3_flag(tp, TXD_MBOX_HWBUG))
543 if (tg3_flag(tp, MBOX_WRITE_REORDER))
547 static u32 tg3_read32_mbox_5906(struct tg3 *tp, u32 off)
549 return readl(tp->regs + off + GRCMBOX_BASE);
552 static void tg3_write32_mbox_5906(struct tg3 *tp, u32 off, u32 val)
554 writel(val, tp->regs + off + GRCMBOX_BASE);
557 #define tw32_mailbox(reg, val) tp->write32_mbox(tp, reg, val)
558 #define tw32_mailbox_f(reg, val) tw32_mailbox_flush(tp, (reg), (val))
559 #define tw32_rx_mbox(reg, val) tp->write32_rx_mbox(tp, reg, val)
560 #define tw32_tx_mbox(reg, val) tp->write32_tx_mbox(tp, reg, val)
561 #define tr32_mailbox(reg) tp->read32_mbox(tp, reg)
563 #define tw32(reg, val) tp->write32(tp, reg, val)
564 #define tw32_f(reg, val) _tw32_flush(tp, (reg), (val), 0)
565 #define tw32_wait_f(reg, val, us) _tw32_flush(tp, (reg), (val), (us))
566 #define tr32(reg) tp->read32(tp, reg)
568 static void tg3_write_mem(struct tg3 *tp, u32 off, u32 val)
572 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906 &&
573 (off >= NIC_SRAM_STATS_BLK) && (off < NIC_SRAM_TX_BUFFER_DESC))
576 spin_lock_irqsave(&tp->indirect_lock, flags);
577 if (tg3_flag(tp, SRAM_USE_CONFIG)) {
578 pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_BASE_ADDR, off);
579 pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_DATA, val);
581 /* Always leave this as zero. */
582 pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_BASE_ADDR, 0);
584 tw32_f(TG3PCI_MEM_WIN_BASE_ADDR, off);
585 tw32_f(TG3PCI_MEM_WIN_DATA, val);
587 /* Always leave this as zero. */
588 tw32_f(TG3PCI_MEM_WIN_BASE_ADDR, 0);
590 spin_unlock_irqrestore(&tp->indirect_lock, flags);
593 static void tg3_read_mem(struct tg3 *tp, u32 off, u32 *val)
597 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906 &&
598 (off >= NIC_SRAM_STATS_BLK) && (off < NIC_SRAM_TX_BUFFER_DESC)) {
603 spin_lock_irqsave(&tp->indirect_lock, flags);
604 if (tg3_flag(tp, SRAM_USE_CONFIG)) {
605 pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_BASE_ADDR, off);
606 pci_read_config_dword(tp->pdev, TG3PCI_MEM_WIN_DATA, val);
608 /* Always leave this as zero. */
609 pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_BASE_ADDR, 0);
611 tw32_f(TG3PCI_MEM_WIN_BASE_ADDR, off);
612 *val = tr32(TG3PCI_MEM_WIN_DATA);
614 /* Always leave this as zero. */
615 tw32_f(TG3PCI_MEM_WIN_BASE_ADDR, 0);
617 spin_unlock_irqrestore(&tp->indirect_lock, flags);
620 static void tg3_ape_lock_init(struct tg3 *tp)
625 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5761)
626 regbase = TG3_APE_LOCK_GRANT;
628 regbase = TG3_APE_PER_LOCK_GRANT;
630 /* Make sure the driver hasn't any stale locks. */
631 for (i = TG3_APE_LOCK_PHY0; i <= TG3_APE_LOCK_GPIO; i++) {
633 case TG3_APE_LOCK_PHY0:
634 case TG3_APE_LOCK_PHY1:
635 case TG3_APE_LOCK_PHY2:
636 case TG3_APE_LOCK_PHY3:
637 bit = APE_LOCK_GRANT_DRIVER;
641 bit = APE_LOCK_GRANT_DRIVER;
643 bit = 1 << tp->pci_fn;
645 tg3_ape_write32(tp, regbase + 4 * i, bit);
650 static int tg3_ape_lock(struct tg3 *tp, int locknum)
654 u32 status, req, gnt, bit;
656 if (!tg3_flag(tp, ENABLE_APE))
660 case TG3_APE_LOCK_GPIO:
661 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5761)
663 case TG3_APE_LOCK_GRC:
664 case TG3_APE_LOCK_MEM:
666 bit = APE_LOCK_REQ_DRIVER;
668 bit = 1 << tp->pci_fn;
674 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5761) {
675 req = TG3_APE_LOCK_REQ;
676 gnt = TG3_APE_LOCK_GRANT;
678 req = TG3_APE_PER_LOCK_REQ;
679 gnt = TG3_APE_PER_LOCK_GRANT;
684 tg3_ape_write32(tp, req + off, bit);
686 /* Wait for up to 1 millisecond to acquire lock. */
687 for (i = 0; i < 100; i++) {
688 status = tg3_ape_read32(tp, gnt + off);
695 /* Revoke the lock request. */
696 tg3_ape_write32(tp, gnt + off, bit);
703 static void tg3_ape_unlock(struct tg3 *tp, int locknum)
707 if (!tg3_flag(tp, ENABLE_APE))
711 case TG3_APE_LOCK_GPIO:
712 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5761)
714 case TG3_APE_LOCK_GRC:
715 case TG3_APE_LOCK_MEM:
717 bit = APE_LOCK_GRANT_DRIVER;
719 bit = 1 << tp->pci_fn;
725 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5761)
726 gnt = TG3_APE_LOCK_GRANT;
728 gnt = TG3_APE_PER_LOCK_GRANT;
730 tg3_ape_write32(tp, gnt + 4 * locknum, bit);
733 static void tg3_ape_send_event(struct tg3 *tp, u32 event)
738 /* NCSI does not support APE events */
739 if (tg3_flag(tp, APE_HAS_NCSI))
742 apedata = tg3_ape_read32(tp, TG3_APE_SEG_SIG);
743 if (apedata != APE_SEG_SIG_MAGIC)
746 apedata = tg3_ape_read32(tp, TG3_APE_FW_STATUS);
747 if (!(apedata & APE_FW_STATUS_READY))
750 /* Wait for up to 1 millisecond for APE to service previous event. */
751 for (i = 0; i < 10; i++) {
752 if (tg3_ape_lock(tp, TG3_APE_LOCK_MEM))
755 apedata = tg3_ape_read32(tp, TG3_APE_EVENT_STATUS);
757 if (!(apedata & APE_EVENT_STATUS_EVENT_PENDING))
758 tg3_ape_write32(tp, TG3_APE_EVENT_STATUS,
759 event | APE_EVENT_STATUS_EVENT_PENDING);
761 tg3_ape_unlock(tp, TG3_APE_LOCK_MEM);
763 if (!(apedata & APE_EVENT_STATUS_EVENT_PENDING))
769 if (!(apedata & APE_EVENT_STATUS_EVENT_PENDING))
770 tg3_ape_write32(tp, TG3_APE_EVENT, APE_EVENT_1);
773 static void tg3_ape_driver_state_change(struct tg3 *tp, int kind)
778 if (!tg3_flag(tp, ENABLE_APE))
782 case RESET_KIND_INIT:
783 tg3_ape_write32(tp, TG3_APE_HOST_SEG_SIG,
784 APE_HOST_SEG_SIG_MAGIC);
785 tg3_ape_write32(tp, TG3_APE_HOST_SEG_LEN,
786 APE_HOST_SEG_LEN_MAGIC);
787 apedata = tg3_ape_read32(tp, TG3_APE_HOST_INIT_COUNT);
788 tg3_ape_write32(tp, TG3_APE_HOST_INIT_COUNT, ++apedata);
789 tg3_ape_write32(tp, TG3_APE_HOST_DRIVER_ID,
790 APE_HOST_DRIVER_ID_MAGIC(TG3_MAJ_NUM, TG3_MIN_NUM));
791 tg3_ape_write32(tp, TG3_APE_HOST_BEHAVIOR,
792 APE_HOST_BEHAV_NO_PHYLOCK);
793 tg3_ape_write32(tp, TG3_APE_HOST_DRVR_STATE,
794 TG3_APE_HOST_DRVR_STATE_START);
796 event = APE_EVENT_STATUS_STATE_START;
798 case RESET_KIND_SHUTDOWN:
799 /* With the interface we are currently using,
800 * APE does not track driver state. Wiping
801 * out the HOST SEGMENT SIGNATURE forces
802 * the APE to assume OS absent status.
804 tg3_ape_write32(tp, TG3_APE_HOST_SEG_SIG, 0x0);
806 if (device_may_wakeup(&tp->pdev->dev) &&
807 tg3_flag(tp, WOL_ENABLE)) {
808 tg3_ape_write32(tp, TG3_APE_HOST_WOL_SPEED,
809 TG3_APE_HOST_WOL_SPEED_AUTO);
810 apedata = TG3_APE_HOST_DRVR_STATE_WOL;
812 apedata = TG3_APE_HOST_DRVR_STATE_UNLOAD;
814 tg3_ape_write32(tp, TG3_APE_HOST_DRVR_STATE, apedata);
816 event = APE_EVENT_STATUS_STATE_UNLOAD;
818 case RESET_KIND_SUSPEND:
819 event = APE_EVENT_STATUS_STATE_SUSPEND;
825 event |= APE_EVENT_STATUS_DRIVER_EVNT | APE_EVENT_STATUS_STATE_CHNGE;
827 tg3_ape_send_event(tp, event);
830 static void tg3_disable_ints(struct tg3 *tp)
834 tw32(TG3PCI_MISC_HOST_CTRL,
835 (tp->misc_host_ctrl | MISC_HOST_CTRL_MASK_PCI_INT));
836 for (i = 0; i < tp->irq_max; i++)
837 tw32_mailbox_f(tp->napi[i].int_mbox, 0x00000001);
840 static void tg3_enable_ints(struct tg3 *tp)
847 tw32(TG3PCI_MISC_HOST_CTRL,
848 (tp->misc_host_ctrl & ~MISC_HOST_CTRL_MASK_PCI_INT));
850 tp->coal_now = tp->coalesce_mode | HOSTCC_MODE_ENABLE;
851 for (i = 0; i < tp->irq_cnt; i++) {
852 struct tg3_napi *tnapi = &tp->napi[i];
854 tw32_mailbox_f(tnapi->int_mbox, tnapi->last_tag << 24);
855 if (tg3_flag(tp, 1SHOT_MSI))
856 tw32_mailbox_f(tnapi->int_mbox, tnapi->last_tag << 24);
858 tp->coal_now |= tnapi->coal_now;
861 /* Force an initial interrupt */
862 if (!tg3_flag(tp, TAGGED_STATUS) &&
863 (tp->napi[0].hw_status->status & SD_STATUS_UPDATED))
864 tw32(GRC_LOCAL_CTRL, tp->grc_local_ctrl | GRC_LCLCTRL_SETINT);
866 tw32(HOSTCC_MODE, tp->coal_now);
868 tp->coal_now &= ~(tp->napi[0].coal_now | tp->napi[1].coal_now);
871 static inline unsigned int tg3_has_work(struct tg3_napi *tnapi)
873 struct tg3 *tp = tnapi->tp;
874 struct tg3_hw_status *sblk = tnapi->hw_status;
875 unsigned int work_exists = 0;
877 /* check for phy events */
878 if (!(tg3_flag(tp, USE_LINKCHG_REG) || tg3_flag(tp, POLL_SERDES))) {
879 if (sblk->status & SD_STATUS_LINK_CHG)
882 /* check for RX/TX work to do */
883 if (sblk->idx[0].tx_consumer != tnapi->tx_cons ||
884 *(tnapi->rx_rcb_prod_idx) != tnapi->rx_rcb_ptr)
891 * similar to tg3_enable_ints, but it accurately determines whether there
892 * is new work pending and can return without flushing the PIO write
893 * which reenables interrupts
895 static void tg3_int_reenable(struct tg3_napi *tnapi)
897 struct tg3 *tp = tnapi->tp;
899 tw32_mailbox(tnapi->int_mbox, tnapi->last_tag << 24);
902 /* When doing tagged status, this work check is unnecessary.
903 * The last_tag we write above tells the chip which piece of
904 * work we've completed.
906 if (!tg3_flag(tp, TAGGED_STATUS) && tg3_has_work(tnapi))
907 tw32(HOSTCC_MODE, tp->coalesce_mode |
908 HOSTCC_MODE_ENABLE | tnapi->coal_now);
911 static void tg3_switch_clocks(struct tg3 *tp)
916 if (tg3_flag(tp, CPMU_PRESENT) || tg3_flag(tp, 5780_CLASS))
919 clock_ctrl = tr32(TG3PCI_CLOCK_CTRL);
921 orig_clock_ctrl = clock_ctrl;
922 clock_ctrl &= (CLOCK_CTRL_FORCE_CLKRUN |
923 CLOCK_CTRL_CLKRUN_OENABLE |
925 tp->pci_clock_ctrl = clock_ctrl;
927 if (tg3_flag(tp, 5705_PLUS)) {
928 if (orig_clock_ctrl & CLOCK_CTRL_625_CORE) {
929 tw32_wait_f(TG3PCI_CLOCK_CTRL,
930 clock_ctrl | CLOCK_CTRL_625_CORE, 40);
932 } else if ((orig_clock_ctrl & CLOCK_CTRL_44MHZ_CORE) != 0) {
933 tw32_wait_f(TG3PCI_CLOCK_CTRL,
935 (CLOCK_CTRL_44MHZ_CORE | CLOCK_CTRL_ALTCLK),
937 tw32_wait_f(TG3PCI_CLOCK_CTRL,
938 clock_ctrl | (CLOCK_CTRL_ALTCLK),
941 tw32_wait_f(TG3PCI_CLOCK_CTRL, clock_ctrl, 40);
944 #define PHY_BUSY_LOOPS 5000
946 static int tg3_readphy(struct tg3 *tp, int reg, u32 *val)
952 if ((tp->mi_mode & MAC_MI_MODE_AUTO_POLL) != 0) {
954 (tp->mi_mode & ~MAC_MI_MODE_AUTO_POLL));
960 frame_val = ((tp->phy_addr << MI_COM_PHY_ADDR_SHIFT) &
961 MI_COM_PHY_ADDR_MASK);
962 frame_val |= ((reg << MI_COM_REG_ADDR_SHIFT) &
963 MI_COM_REG_ADDR_MASK);
964 frame_val |= (MI_COM_CMD_READ | MI_COM_START);
966 tw32_f(MAC_MI_COM, frame_val);
968 loops = PHY_BUSY_LOOPS;
971 frame_val = tr32(MAC_MI_COM);
973 if ((frame_val & MI_COM_BUSY) == 0) {
975 frame_val = tr32(MAC_MI_COM);
983 *val = frame_val & MI_COM_DATA_MASK;
987 if ((tp->mi_mode & MAC_MI_MODE_AUTO_POLL) != 0) {
988 tw32_f(MAC_MI_MODE, tp->mi_mode);
995 static int tg3_writephy(struct tg3 *tp, int reg, u32 val)
1001 if ((tp->phy_flags & TG3_PHYFLG_IS_FET) &&
1002 (reg == MII_CTRL1000 || reg == MII_TG3_AUX_CTRL))
1005 if ((tp->mi_mode & MAC_MI_MODE_AUTO_POLL) != 0) {
1007 (tp->mi_mode & ~MAC_MI_MODE_AUTO_POLL));
1011 frame_val = ((tp->phy_addr << MI_COM_PHY_ADDR_SHIFT) &
1012 MI_COM_PHY_ADDR_MASK);
1013 frame_val |= ((reg << MI_COM_REG_ADDR_SHIFT) &
1014 MI_COM_REG_ADDR_MASK);
1015 frame_val |= (val & MI_COM_DATA_MASK);
1016 frame_val |= (MI_COM_CMD_WRITE | MI_COM_START);
1018 tw32_f(MAC_MI_COM, frame_val);
1020 loops = PHY_BUSY_LOOPS;
1021 while (loops != 0) {
1023 frame_val = tr32(MAC_MI_COM);
1024 if ((frame_val & MI_COM_BUSY) == 0) {
1026 frame_val = tr32(MAC_MI_COM);
1036 if ((tp->mi_mode & MAC_MI_MODE_AUTO_POLL) != 0) {
1037 tw32_f(MAC_MI_MODE, tp->mi_mode);
1044 static int tg3_phy_cl45_write(struct tg3 *tp, u32 devad, u32 addr, u32 val)
1048 err = tg3_writephy(tp, MII_TG3_MMD_CTRL, devad);
1052 err = tg3_writephy(tp, MII_TG3_MMD_ADDRESS, addr);
1056 err = tg3_writephy(tp, MII_TG3_MMD_CTRL,
1057 MII_TG3_MMD_CTRL_DATA_NOINC | devad);
1061 err = tg3_writephy(tp, MII_TG3_MMD_ADDRESS, val);
1067 static int tg3_phy_cl45_read(struct tg3 *tp, u32 devad, u32 addr, u32 *val)
1071 err = tg3_writephy(tp, MII_TG3_MMD_CTRL, devad);
1075 err = tg3_writephy(tp, MII_TG3_MMD_ADDRESS, addr);
1079 err = tg3_writephy(tp, MII_TG3_MMD_CTRL,
1080 MII_TG3_MMD_CTRL_DATA_NOINC | devad);
1084 err = tg3_readphy(tp, MII_TG3_MMD_ADDRESS, val);
1090 static int tg3_phydsp_read(struct tg3 *tp, u32 reg, u32 *val)
1094 err = tg3_writephy(tp, MII_TG3_DSP_ADDRESS, reg);
1096 err = tg3_readphy(tp, MII_TG3_DSP_RW_PORT, val);
1101 static int tg3_phydsp_write(struct tg3 *tp, u32 reg, u32 val)
1105 err = tg3_writephy(tp, MII_TG3_DSP_ADDRESS, reg);
1107 err = tg3_writephy(tp, MII_TG3_DSP_RW_PORT, val);
1112 static int tg3_phy_auxctl_read(struct tg3 *tp, int reg, u32 *val)
1116 err = tg3_writephy(tp, MII_TG3_AUX_CTRL,
1117 (reg << MII_TG3_AUXCTL_MISC_RDSEL_SHIFT) |
1118 MII_TG3_AUXCTL_SHDWSEL_MISC);
1120 err = tg3_readphy(tp, MII_TG3_AUX_CTRL, val);
1125 static int tg3_phy_auxctl_write(struct tg3 *tp, int reg, u32 set)
1127 if (reg == MII_TG3_AUXCTL_SHDWSEL_MISC)
1128 set |= MII_TG3_AUXCTL_MISC_WREN;
1130 return tg3_writephy(tp, MII_TG3_AUX_CTRL, set | reg);
1133 #define TG3_PHY_AUXCTL_SMDSP_ENABLE(tp) \
1134 tg3_phy_auxctl_write((tp), MII_TG3_AUXCTL_SHDWSEL_AUXCTL, \
1135 MII_TG3_AUXCTL_ACTL_SMDSP_ENA | \
1136 MII_TG3_AUXCTL_ACTL_TX_6DB)
1138 #define TG3_PHY_AUXCTL_SMDSP_DISABLE(tp) \
1139 tg3_phy_auxctl_write((tp), MII_TG3_AUXCTL_SHDWSEL_AUXCTL, \
1140 MII_TG3_AUXCTL_ACTL_TX_6DB);
1142 static int tg3_bmcr_reset(struct tg3 *tp)
1147 /* OK, reset it, and poll the BMCR_RESET bit until it
1148 * clears or we time out.
1150 phy_control = BMCR_RESET;
1151 err = tg3_writephy(tp, MII_BMCR, phy_control);
1157 err = tg3_readphy(tp, MII_BMCR, &phy_control);
1161 if ((phy_control & BMCR_RESET) == 0) {
1173 static int tg3_mdio_read(struct mii_bus *bp, int mii_id, int reg)
1175 struct tg3 *tp = bp->priv;
1178 spin_lock_bh(&tp->lock);
1180 if (tg3_readphy(tp, reg, &val))
1183 spin_unlock_bh(&tp->lock);
1188 static int tg3_mdio_write(struct mii_bus *bp, int mii_id, int reg, u16 val)
1190 struct tg3 *tp = bp->priv;
1193 spin_lock_bh(&tp->lock);
1195 if (tg3_writephy(tp, reg, val))
1198 spin_unlock_bh(&tp->lock);
1203 static int tg3_mdio_reset(struct mii_bus *bp)
1208 static void tg3_mdio_config_5785(struct tg3 *tp)
1211 struct phy_device *phydev;
1213 phydev = tp->mdio_bus->phy_map[TG3_PHY_MII_ADDR];
1214 switch (phydev->drv->phy_id & phydev->drv->phy_id_mask) {
1215 case PHY_ID_BCM50610:
1216 case PHY_ID_BCM50610M:
1217 val = MAC_PHYCFG2_50610_LED_MODES;
1219 case PHY_ID_BCMAC131:
1220 val = MAC_PHYCFG2_AC131_LED_MODES;
1222 case PHY_ID_RTL8211C:
1223 val = MAC_PHYCFG2_RTL8211C_LED_MODES;
1225 case PHY_ID_RTL8201E:
1226 val = MAC_PHYCFG2_RTL8201E_LED_MODES;
1232 if (phydev->interface != PHY_INTERFACE_MODE_RGMII) {
1233 tw32(MAC_PHYCFG2, val);
1235 val = tr32(MAC_PHYCFG1);
1236 val &= ~(MAC_PHYCFG1_RGMII_INT |
1237 MAC_PHYCFG1_RXCLK_TO_MASK | MAC_PHYCFG1_TXCLK_TO_MASK);
1238 val |= MAC_PHYCFG1_RXCLK_TIMEOUT | MAC_PHYCFG1_TXCLK_TIMEOUT;
1239 tw32(MAC_PHYCFG1, val);
1244 if (!tg3_flag(tp, RGMII_INBAND_DISABLE))
1245 val |= MAC_PHYCFG2_EMODE_MASK_MASK |
1246 MAC_PHYCFG2_FMODE_MASK_MASK |
1247 MAC_PHYCFG2_GMODE_MASK_MASK |
1248 MAC_PHYCFG2_ACT_MASK_MASK |
1249 MAC_PHYCFG2_QUAL_MASK_MASK |
1250 MAC_PHYCFG2_INBAND_ENABLE;
1252 tw32(MAC_PHYCFG2, val);
1254 val = tr32(MAC_PHYCFG1);
1255 val &= ~(MAC_PHYCFG1_RXCLK_TO_MASK | MAC_PHYCFG1_TXCLK_TO_MASK |
1256 MAC_PHYCFG1_RGMII_EXT_RX_DEC | MAC_PHYCFG1_RGMII_SND_STAT_EN);
1257 if (!tg3_flag(tp, RGMII_INBAND_DISABLE)) {
1258 if (tg3_flag(tp, RGMII_EXT_IBND_RX_EN))
1259 val |= MAC_PHYCFG1_RGMII_EXT_RX_DEC;
1260 if (tg3_flag(tp, RGMII_EXT_IBND_TX_EN))
1261 val |= MAC_PHYCFG1_RGMII_SND_STAT_EN;
1263 val |= MAC_PHYCFG1_RXCLK_TIMEOUT | MAC_PHYCFG1_TXCLK_TIMEOUT |
1264 MAC_PHYCFG1_RGMII_INT | MAC_PHYCFG1_TXC_DRV;
1265 tw32(MAC_PHYCFG1, val);
1267 val = tr32(MAC_EXT_RGMII_MODE);
1268 val &= ~(MAC_RGMII_MODE_RX_INT_B |
1269 MAC_RGMII_MODE_RX_QUALITY |
1270 MAC_RGMII_MODE_RX_ACTIVITY |
1271 MAC_RGMII_MODE_RX_ENG_DET |
1272 MAC_RGMII_MODE_TX_ENABLE |
1273 MAC_RGMII_MODE_TX_LOWPWR |
1274 MAC_RGMII_MODE_TX_RESET);
1275 if (!tg3_flag(tp, RGMII_INBAND_DISABLE)) {
1276 if (tg3_flag(tp, RGMII_EXT_IBND_RX_EN))
1277 val |= MAC_RGMII_MODE_RX_INT_B |
1278 MAC_RGMII_MODE_RX_QUALITY |
1279 MAC_RGMII_MODE_RX_ACTIVITY |
1280 MAC_RGMII_MODE_RX_ENG_DET;
1281 if (tg3_flag(tp, RGMII_EXT_IBND_TX_EN))
1282 val |= MAC_RGMII_MODE_TX_ENABLE |
1283 MAC_RGMII_MODE_TX_LOWPWR |
1284 MAC_RGMII_MODE_TX_RESET;
1286 tw32(MAC_EXT_RGMII_MODE, val);
1289 static void tg3_mdio_start(struct tg3 *tp)
1291 tp->mi_mode &= ~MAC_MI_MODE_AUTO_POLL;
1292 tw32_f(MAC_MI_MODE, tp->mi_mode);
1295 if (tg3_flag(tp, MDIOBUS_INITED) &&
1296 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785)
1297 tg3_mdio_config_5785(tp);
1300 static int tg3_mdio_init(struct tg3 *tp)
1304 struct phy_device *phydev;
1306 if (tg3_flag(tp, 5717_PLUS)) {
1309 tp->phy_addr = tp->pci_fn + 1;
1311 if (tp->pci_chip_rev_id != CHIPREV_ID_5717_A0)
1312 is_serdes = tr32(SG_DIG_STATUS) & SG_DIG_IS_SERDES;
1314 is_serdes = tr32(TG3_CPMU_PHY_STRAP) &
1315 TG3_CPMU_PHY_STRAP_IS_SERDES;
1319 tp->phy_addr = TG3_PHY_MII_ADDR;
1323 if (!tg3_flag(tp, USE_PHYLIB) || tg3_flag(tp, MDIOBUS_INITED))
1326 tp->mdio_bus = mdiobus_alloc();
1327 if (tp->mdio_bus == NULL)
1330 tp->mdio_bus->name = "tg3 mdio bus";
1331 snprintf(tp->mdio_bus->id, MII_BUS_ID_SIZE, "%x",
1332 (tp->pdev->bus->number << 8) | tp->pdev->devfn);
1333 tp->mdio_bus->priv = tp;
1334 tp->mdio_bus->parent = &tp->pdev->dev;
1335 tp->mdio_bus->read = &tg3_mdio_read;
1336 tp->mdio_bus->write = &tg3_mdio_write;
1337 tp->mdio_bus->reset = &tg3_mdio_reset;
1338 tp->mdio_bus->phy_mask = ~(1 << TG3_PHY_MII_ADDR);
1339 tp->mdio_bus->irq = &tp->mdio_irq[0];
1341 for (i = 0; i < PHY_MAX_ADDR; i++)
1342 tp->mdio_bus->irq[i] = PHY_POLL;
1344 /* The bus registration will look for all the PHYs on the mdio bus.
1345 * Unfortunately, it does not ensure the PHY is powered up before
1346 * accessing the PHY ID registers. A chip reset is the
1347 * quickest way to bring the device back to an operational state..
1349 if (tg3_readphy(tp, MII_BMCR, ®) || (reg & BMCR_PDOWN))
1352 i = mdiobus_register(tp->mdio_bus);
1354 dev_warn(&tp->pdev->dev, "mdiobus_reg failed (0x%x)\n", i);
1355 mdiobus_free(tp->mdio_bus);
1359 phydev = tp->mdio_bus->phy_map[TG3_PHY_MII_ADDR];
1361 if (!phydev || !phydev->drv) {
1362 dev_warn(&tp->pdev->dev, "No PHY devices\n");
1363 mdiobus_unregister(tp->mdio_bus);
1364 mdiobus_free(tp->mdio_bus);
1368 switch (phydev->drv->phy_id & phydev->drv->phy_id_mask) {
1369 case PHY_ID_BCM57780:
1370 phydev->interface = PHY_INTERFACE_MODE_GMII;
1371 phydev->dev_flags |= PHY_BRCM_AUTO_PWRDWN_ENABLE;
1373 case PHY_ID_BCM50610:
1374 case PHY_ID_BCM50610M:
1375 phydev->dev_flags |= PHY_BRCM_CLEAR_RGMII_MODE |
1376 PHY_BRCM_RX_REFCLK_UNUSED |
1377 PHY_BRCM_DIS_TXCRXC_NOENRGY |
1378 PHY_BRCM_AUTO_PWRDWN_ENABLE;
1379 if (tg3_flag(tp, RGMII_INBAND_DISABLE))
1380 phydev->dev_flags |= PHY_BRCM_STD_IBND_DISABLE;
1381 if (tg3_flag(tp, RGMII_EXT_IBND_RX_EN))
1382 phydev->dev_flags |= PHY_BRCM_EXT_IBND_RX_ENABLE;
1383 if (tg3_flag(tp, RGMII_EXT_IBND_TX_EN))
1384 phydev->dev_flags |= PHY_BRCM_EXT_IBND_TX_ENABLE;
1386 case PHY_ID_RTL8211C:
1387 phydev->interface = PHY_INTERFACE_MODE_RGMII;
1389 case PHY_ID_RTL8201E:
1390 case PHY_ID_BCMAC131:
1391 phydev->interface = PHY_INTERFACE_MODE_MII;
1392 phydev->dev_flags |= PHY_BRCM_AUTO_PWRDWN_ENABLE;
1393 tp->phy_flags |= TG3_PHYFLG_IS_FET;
1397 tg3_flag_set(tp, MDIOBUS_INITED);
1399 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785)
1400 tg3_mdio_config_5785(tp);
1405 static void tg3_mdio_fini(struct tg3 *tp)
1407 if (tg3_flag(tp, MDIOBUS_INITED)) {
1408 tg3_flag_clear(tp, MDIOBUS_INITED);
1409 mdiobus_unregister(tp->mdio_bus);
1410 mdiobus_free(tp->mdio_bus);
1414 /* tp->lock is held. */
1415 static inline void tg3_generate_fw_event(struct tg3 *tp)
1419 val = tr32(GRC_RX_CPU_EVENT);
1420 val |= GRC_RX_CPU_DRIVER_EVENT;
1421 tw32_f(GRC_RX_CPU_EVENT, val);
1423 tp->last_event_jiffies = jiffies;
1426 #define TG3_FW_EVENT_TIMEOUT_USEC 2500
1428 /* tp->lock is held. */
1429 static void tg3_wait_for_event_ack(struct tg3 *tp)
1432 unsigned int delay_cnt;
1435 /* If enough time has passed, no wait is necessary. */
1436 time_remain = (long)(tp->last_event_jiffies + 1 +
1437 usecs_to_jiffies(TG3_FW_EVENT_TIMEOUT_USEC)) -
1439 if (time_remain < 0)
1442 /* Check if we can shorten the wait time. */
1443 delay_cnt = jiffies_to_usecs(time_remain);
1444 if (delay_cnt > TG3_FW_EVENT_TIMEOUT_USEC)
1445 delay_cnt = TG3_FW_EVENT_TIMEOUT_USEC;
1446 delay_cnt = (delay_cnt >> 3) + 1;
1448 for (i = 0; i < delay_cnt; i++) {
1449 if (!(tr32(GRC_RX_CPU_EVENT) & GRC_RX_CPU_DRIVER_EVENT))
1455 /* tp->lock is held. */
1456 static void tg3_ump_link_report(struct tg3 *tp)
1461 if (!tg3_flag(tp, 5780_CLASS) || !tg3_flag(tp, ENABLE_ASF))
1464 tg3_wait_for_event_ack(tp);
1466 tg3_write_mem(tp, NIC_SRAM_FW_CMD_MBOX, FWCMD_NICDRV_LINK_UPDATE);
1468 tg3_write_mem(tp, NIC_SRAM_FW_CMD_LEN_MBOX, 14);
1471 if (!tg3_readphy(tp, MII_BMCR, ®))
1473 if (!tg3_readphy(tp, MII_BMSR, ®))
1474 val |= (reg & 0xffff);
1475 tg3_write_mem(tp, NIC_SRAM_FW_CMD_DATA_MBOX, val);
1478 if (!tg3_readphy(tp, MII_ADVERTISE, ®))
1480 if (!tg3_readphy(tp, MII_LPA, ®))
1481 val |= (reg & 0xffff);
1482 tg3_write_mem(tp, NIC_SRAM_FW_CMD_DATA_MBOX + 4, val);
1485 if (!(tp->phy_flags & TG3_PHYFLG_MII_SERDES)) {
1486 if (!tg3_readphy(tp, MII_CTRL1000, ®))
1488 if (!tg3_readphy(tp, MII_STAT1000, ®))
1489 val |= (reg & 0xffff);
1491 tg3_write_mem(tp, NIC_SRAM_FW_CMD_DATA_MBOX + 8, val);
1493 if (!tg3_readphy(tp, MII_PHYADDR, ®))
1497 tg3_write_mem(tp, NIC_SRAM_FW_CMD_DATA_MBOX + 12, val);
1499 tg3_generate_fw_event(tp);
1502 /* tp->lock is held. */
1503 static void tg3_stop_fw(struct tg3 *tp)
1505 if (tg3_flag(tp, ENABLE_ASF) && !tg3_flag(tp, ENABLE_APE)) {
1506 /* Wait for RX cpu to ACK the previous event. */
1507 tg3_wait_for_event_ack(tp);
1509 tg3_write_mem(tp, NIC_SRAM_FW_CMD_MBOX, FWCMD_NICDRV_PAUSE_FW);
1511 tg3_generate_fw_event(tp);
1513 /* Wait for RX cpu to ACK this event. */
1514 tg3_wait_for_event_ack(tp);
1518 /* tp->lock is held. */
1519 static void tg3_write_sig_pre_reset(struct tg3 *tp, int kind)
1521 tg3_write_mem(tp, NIC_SRAM_FIRMWARE_MBOX,
1522 NIC_SRAM_FIRMWARE_MBOX_MAGIC1);
1524 if (tg3_flag(tp, ASF_NEW_HANDSHAKE)) {
1526 case RESET_KIND_INIT:
1527 tg3_write_mem(tp, NIC_SRAM_FW_DRV_STATE_MBOX,
1531 case RESET_KIND_SHUTDOWN:
1532 tg3_write_mem(tp, NIC_SRAM_FW_DRV_STATE_MBOX,
1536 case RESET_KIND_SUSPEND:
1537 tg3_write_mem(tp, NIC_SRAM_FW_DRV_STATE_MBOX,
1546 if (kind == RESET_KIND_INIT ||
1547 kind == RESET_KIND_SUSPEND)
1548 tg3_ape_driver_state_change(tp, kind);
1551 /* tp->lock is held. */
1552 static void tg3_write_sig_post_reset(struct tg3 *tp, int kind)
1554 if (tg3_flag(tp, ASF_NEW_HANDSHAKE)) {
1556 case RESET_KIND_INIT:
1557 tg3_write_mem(tp, NIC_SRAM_FW_DRV_STATE_MBOX,
1558 DRV_STATE_START_DONE);
1561 case RESET_KIND_SHUTDOWN:
1562 tg3_write_mem(tp, NIC_SRAM_FW_DRV_STATE_MBOX,
1563 DRV_STATE_UNLOAD_DONE);
1571 if (kind == RESET_KIND_SHUTDOWN)
1572 tg3_ape_driver_state_change(tp, kind);
1575 /* tp->lock is held. */
1576 static void tg3_write_sig_legacy(struct tg3 *tp, int kind)
1578 if (tg3_flag(tp, ENABLE_ASF)) {
1580 case RESET_KIND_INIT:
1581 tg3_write_mem(tp, NIC_SRAM_FW_DRV_STATE_MBOX,
1585 case RESET_KIND_SHUTDOWN:
1586 tg3_write_mem(tp, NIC_SRAM_FW_DRV_STATE_MBOX,
1590 case RESET_KIND_SUSPEND:
1591 tg3_write_mem(tp, NIC_SRAM_FW_DRV_STATE_MBOX,
1601 static int tg3_poll_fw(struct tg3 *tp)
1606 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
1607 /* Wait up to 20ms for init done. */
1608 for (i = 0; i < 200; i++) {
1609 if (tr32(VCPU_STATUS) & VCPU_STATUS_INIT_DONE)
1616 /* Wait for firmware initialization to complete. */
1617 for (i = 0; i < 100000; i++) {
1618 tg3_read_mem(tp, NIC_SRAM_FIRMWARE_MBOX, &val);
1619 if (val == ~NIC_SRAM_FIRMWARE_MBOX_MAGIC1)
1624 /* Chip might not be fitted with firmware. Some Sun onboard
1625 * parts are configured like that. So don't signal the timeout
1626 * of the above loop as an error, but do report the lack of
1627 * running firmware once.
1629 if (i >= 100000 && !tg3_flag(tp, NO_FWARE_REPORTED)) {
1630 tg3_flag_set(tp, NO_FWARE_REPORTED);
1632 netdev_info(tp->dev, "No firmware running\n");
1635 if (tp->pci_chip_rev_id == CHIPREV_ID_57765_A0) {
1636 /* The 57765 A0 needs a little more
1637 * time to do some important work.
1645 static void tg3_link_report(struct tg3 *tp)
1647 if (!netif_carrier_ok(tp->dev)) {
1648 netif_info(tp, link, tp->dev, "Link is down\n");
1649 tg3_ump_link_report(tp);
1650 } else if (netif_msg_link(tp)) {
1651 netdev_info(tp->dev, "Link is up at %d Mbps, %s duplex\n",
1652 (tp->link_config.active_speed == SPEED_1000 ?
1654 (tp->link_config.active_speed == SPEED_100 ?
1656 (tp->link_config.active_duplex == DUPLEX_FULL ?
1659 netdev_info(tp->dev, "Flow control is %s for TX and %s for RX\n",
1660 (tp->link_config.active_flowctrl & FLOW_CTRL_TX) ?
1662 (tp->link_config.active_flowctrl & FLOW_CTRL_RX) ?
1665 if (tp->phy_flags & TG3_PHYFLG_EEE_CAP)
1666 netdev_info(tp->dev, "EEE is %s\n",
1667 tp->setlpicnt ? "enabled" : "disabled");
1669 tg3_ump_link_report(tp);
1673 static u16 tg3_advert_flowctrl_1000X(u8 flow_ctrl)
1677 if ((flow_ctrl & FLOW_CTRL_TX) && (flow_ctrl & FLOW_CTRL_RX))
1678 miireg = ADVERTISE_1000XPAUSE;
1679 else if (flow_ctrl & FLOW_CTRL_TX)
1680 miireg = ADVERTISE_1000XPSE_ASYM;
1681 else if (flow_ctrl & FLOW_CTRL_RX)
1682 miireg = ADVERTISE_1000XPAUSE | ADVERTISE_1000XPSE_ASYM;
1689 static u8 tg3_resolve_flowctrl_1000X(u16 lcladv, u16 rmtadv)
1693 if (lcladv & rmtadv & ADVERTISE_1000XPAUSE) {
1694 cap = FLOW_CTRL_TX | FLOW_CTRL_RX;
1695 } else if (lcladv & rmtadv & ADVERTISE_1000XPSE_ASYM) {
1696 if (lcladv & ADVERTISE_1000XPAUSE)
1698 if (rmtadv & ADVERTISE_1000XPAUSE)
1705 static void tg3_setup_flow_control(struct tg3 *tp, u32 lcladv, u32 rmtadv)
1709 u32 old_rx_mode = tp->rx_mode;
1710 u32 old_tx_mode = tp->tx_mode;
1712 if (tg3_flag(tp, USE_PHYLIB))
1713 autoneg = tp->mdio_bus->phy_map[TG3_PHY_MII_ADDR]->autoneg;
1715 autoneg = tp->link_config.autoneg;
1717 if (autoneg == AUTONEG_ENABLE && tg3_flag(tp, PAUSE_AUTONEG)) {
1718 if (tp->phy_flags & TG3_PHYFLG_ANY_SERDES)
1719 flowctrl = tg3_resolve_flowctrl_1000X(lcladv, rmtadv);
1721 flowctrl = mii_resolve_flowctrl_fdx(lcladv, rmtadv);
1723 flowctrl = tp->link_config.flowctrl;
1725 tp->link_config.active_flowctrl = flowctrl;
1727 if (flowctrl & FLOW_CTRL_RX)
1728 tp->rx_mode |= RX_MODE_FLOW_CTRL_ENABLE;
1730 tp->rx_mode &= ~RX_MODE_FLOW_CTRL_ENABLE;
1732 if (old_rx_mode != tp->rx_mode)
1733 tw32_f(MAC_RX_MODE, tp->rx_mode);
1735 if (flowctrl & FLOW_CTRL_TX)
1736 tp->tx_mode |= TX_MODE_FLOW_CTRL_ENABLE;
1738 tp->tx_mode &= ~TX_MODE_FLOW_CTRL_ENABLE;
1740 if (old_tx_mode != tp->tx_mode)
1741 tw32_f(MAC_TX_MODE, tp->tx_mode);
1744 static void tg3_adjust_link(struct net_device *dev)
1746 u8 oldflowctrl, linkmesg = 0;
1747 u32 mac_mode, lcl_adv, rmt_adv;
1748 struct tg3 *tp = netdev_priv(dev);
1749 struct phy_device *phydev = tp->mdio_bus->phy_map[TG3_PHY_MII_ADDR];
1751 spin_lock_bh(&tp->lock);
1753 mac_mode = tp->mac_mode & ~(MAC_MODE_PORT_MODE_MASK |
1754 MAC_MODE_HALF_DUPLEX);
1756 oldflowctrl = tp->link_config.active_flowctrl;
1762 if (phydev->speed == SPEED_100 || phydev->speed == SPEED_10)
1763 mac_mode |= MAC_MODE_PORT_MODE_MII;
1764 else if (phydev->speed == SPEED_1000 ||
1765 GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5785)
1766 mac_mode |= MAC_MODE_PORT_MODE_GMII;
1768 mac_mode |= MAC_MODE_PORT_MODE_MII;
1770 if (phydev->duplex == DUPLEX_HALF)
1771 mac_mode |= MAC_MODE_HALF_DUPLEX;
1773 lcl_adv = mii_advertise_flowctrl(
1774 tp->link_config.flowctrl);
1777 rmt_adv = LPA_PAUSE_CAP;
1778 if (phydev->asym_pause)
1779 rmt_adv |= LPA_PAUSE_ASYM;
1782 tg3_setup_flow_control(tp, lcl_adv, rmt_adv);
1784 mac_mode |= MAC_MODE_PORT_MODE_GMII;
1786 if (mac_mode != tp->mac_mode) {
1787 tp->mac_mode = mac_mode;
1788 tw32_f(MAC_MODE, tp->mac_mode);
1792 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785) {
1793 if (phydev->speed == SPEED_10)
1795 MAC_MI_STAT_10MBPS_MODE |
1796 MAC_MI_STAT_LNKSTAT_ATTN_ENAB);
1798 tw32(MAC_MI_STAT, MAC_MI_STAT_LNKSTAT_ATTN_ENAB);
1801 if (phydev->speed == SPEED_1000 && phydev->duplex == DUPLEX_HALF)
1802 tw32(MAC_TX_LENGTHS,
1803 ((2 << TX_LENGTHS_IPG_CRS_SHIFT) |
1804 (6 << TX_LENGTHS_IPG_SHIFT) |
1805 (0xff << TX_LENGTHS_SLOT_TIME_SHIFT)));
1807 tw32(MAC_TX_LENGTHS,
1808 ((2 << TX_LENGTHS_IPG_CRS_SHIFT) |
1809 (6 << TX_LENGTHS_IPG_SHIFT) |
1810 (32 << TX_LENGTHS_SLOT_TIME_SHIFT)));
1812 if ((phydev->link && tp->link_config.active_speed == SPEED_INVALID) ||
1813 (!phydev->link && tp->link_config.active_speed != SPEED_INVALID) ||
1814 phydev->speed != tp->link_config.active_speed ||
1815 phydev->duplex != tp->link_config.active_duplex ||
1816 oldflowctrl != tp->link_config.active_flowctrl)
1819 tp->link_config.active_speed = phydev->speed;
1820 tp->link_config.active_duplex = phydev->duplex;
1822 spin_unlock_bh(&tp->lock);
1825 tg3_link_report(tp);
1828 static int tg3_phy_init(struct tg3 *tp)
1830 struct phy_device *phydev;
1832 if (tp->phy_flags & TG3_PHYFLG_IS_CONNECTED)
1835 /* Bring the PHY back to a known state. */
1838 phydev = tp->mdio_bus->phy_map[TG3_PHY_MII_ADDR];
1840 /* Attach the MAC to the PHY. */
1841 phydev = phy_connect(tp->dev, dev_name(&phydev->dev), tg3_adjust_link,
1842 phydev->dev_flags, phydev->interface);
1843 if (IS_ERR(phydev)) {
1844 dev_err(&tp->pdev->dev, "Could not attach to PHY\n");
1845 return PTR_ERR(phydev);
1848 /* Mask with MAC supported features. */
1849 switch (phydev->interface) {
1850 case PHY_INTERFACE_MODE_GMII:
1851 case PHY_INTERFACE_MODE_RGMII:
1852 if (!(tp->phy_flags & TG3_PHYFLG_10_100_ONLY)) {
1853 phydev->supported &= (PHY_GBIT_FEATURES |
1855 SUPPORTED_Asym_Pause);
1859 case PHY_INTERFACE_MODE_MII:
1860 phydev->supported &= (PHY_BASIC_FEATURES |
1862 SUPPORTED_Asym_Pause);
1865 phy_disconnect(tp->mdio_bus->phy_map[TG3_PHY_MII_ADDR]);
1869 tp->phy_flags |= TG3_PHYFLG_IS_CONNECTED;
1871 phydev->advertising = phydev->supported;
1876 static void tg3_phy_start(struct tg3 *tp)
1878 struct phy_device *phydev;
1880 if (!(tp->phy_flags & TG3_PHYFLG_IS_CONNECTED))
1883 phydev = tp->mdio_bus->phy_map[TG3_PHY_MII_ADDR];
1885 if (tp->phy_flags & TG3_PHYFLG_IS_LOW_POWER) {
1886 tp->phy_flags &= ~TG3_PHYFLG_IS_LOW_POWER;
1887 phydev->speed = tp->link_config.orig_speed;
1888 phydev->duplex = tp->link_config.orig_duplex;
1889 phydev->autoneg = tp->link_config.orig_autoneg;
1890 phydev->advertising = tp->link_config.orig_advertising;
1895 phy_start_aneg(phydev);
1898 static void tg3_phy_stop(struct tg3 *tp)
1900 if (!(tp->phy_flags & TG3_PHYFLG_IS_CONNECTED))
1903 phy_stop(tp->mdio_bus->phy_map[TG3_PHY_MII_ADDR]);
1906 static void tg3_phy_fini(struct tg3 *tp)
1908 if (tp->phy_flags & TG3_PHYFLG_IS_CONNECTED) {
1909 phy_disconnect(tp->mdio_bus->phy_map[TG3_PHY_MII_ADDR]);
1910 tp->phy_flags &= ~TG3_PHYFLG_IS_CONNECTED;
1914 static int tg3_phy_set_extloopbk(struct tg3 *tp)
1919 if (tp->phy_flags & TG3_PHYFLG_IS_FET)
1922 if ((tp->phy_id & TG3_PHY_ID_MASK) == TG3_PHY_ID_BCM5401) {
1923 /* Cannot do read-modify-write on 5401 */
1924 err = tg3_phy_auxctl_write(tp,
1925 MII_TG3_AUXCTL_SHDWSEL_AUXCTL,
1926 MII_TG3_AUXCTL_ACTL_EXTLOOPBK |
1931 err = tg3_phy_auxctl_read(tp,
1932 MII_TG3_AUXCTL_SHDWSEL_AUXCTL, &val);
1936 val |= MII_TG3_AUXCTL_ACTL_EXTLOOPBK;
1937 err = tg3_phy_auxctl_write(tp,
1938 MII_TG3_AUXCTL_SHDWSEL_AUXCTL, val);
1944 static void tg3_phy_fet_toggle_apd(struct tg3 *tp, bool enable)
1948 if (!tg3_readphy(tp, MII_TG3_FET_TEST, &phytest)) {
1951 tg3_writephy(tp, MII_TG3_FET_TEST,
1952 phytest | MII_TG3_FET_SHADOW_EN);
1953 if (!tg3_readphy(tp, MII_TG3_FET_SHDW_AUXSTAT2, &phy)) {
1955 phy |= MII_TG3_FET_SHDW_AUXSTAT2_APD;
1957 phy &= ~MII_TG3_FET_SHDW_AUXSTAT2_APD;
1958 tg3_writephy(tp, MII_TG3_FET_SHDW_AUXSTAT2, phy);
1960 tg3_writephy(tp, MII_TG3_FET_TEST, phytest);
1964 static void tg3_phy_toggle_apd(struct tg3 *tp, bool enable)
1968 if (!tg3_flag(tp, 5705_PLUS) ||
1969 (tg3_flag(tp, 5717_PLUS) &&
1970 (tp->phy_flags & TG3_PHYFLG_MII_SERDES)))
1973 if (tp->phy_flags & TG3_PHYFLG_IS_FET) {
1974 tg3_phy_fet_toggle_apd(tp, enable);
1978 reg = MII_TG3_MISC_SHDW_WREN |
1979 MII_TG3_MISC_SHDW_SCR5_SEL |
1980 MII_TG3_MISC_SHDW_SCR5_LPED |
1981 MII_TG3_MISC_SHDW_SCR5_DLPTLM |
1982 MII_TG3_MISC_SHDW_SCR5_SDTL |
1983 MII_TG3_MISC_SHDW_SCR5_C125OE;
1984 if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5784 || !enable)
1985 reg |= MII_TG3_MISC_SHDW_SCR5_DLLAPD;
1987 tg3_writephy(tp, MII_TG3_MISC_SHDW, reg);
1990 reg = MII_TG3_MISC_SHDW_WREN |
1991 MII_TG3_MISC_SHDW_APD_SEL |
1992 MII_TG3_MISC_SHDW_APD_WKTM_84MS;
1994 reg |= MII_TG3_MISC_SHDW_APD_ENABLE;
1996 tg3_writephy(tp, MII_TG3_MISC_SHDW, reg);
1999 static void tg3_phy_toggle_automdix(struct tg3 *tp, int enable)
2003 if (!tg3_flag(tp, 5705_PLUS) ||
2004 (tp->phy_flags & TG3_PHYFLG_ANY_SERDES))
2007 if (tp->phy_flags & TG3_PHYFLG_IS_FET) {
2010 if (!tg3_readphy(tp, MII_TG3_FET_TEST, &ephy)) {
2011 u32 reg = MII_TG3_FET_SHDW_MISCCTRL;
2013 tg3_writephy(tp, MII_TG3_FET_TEST,
2014 ephy | MII_TG3_FET_SHADOW_EN);
2015 if (!tg3_readphy(tp, reg, &phy)) {
2017 phy |= MII_TG3_FET_SHDW_MISCCTRL_MDIX;
2019 phy &= ~MII_TG3_FET_SHDW_MISCCTRL_MDIX;
2020 tg3_writephy(tp, reg, phy);
2022 tg3_writephy(tp, MII_TG3_FET_TEST, ephy);
2027 ret = tg3_phy_auxctl_read(tp,
2028 MII_TG3_AUXCTL_SHDWSEL_MISC, &phy);
2031 phy |= MII_TG3_AUXCTL_MISC_FORCE_AMDIX;
2033 phy &= ~MII_TG3_AUXCTL_MISC_FORCE_AMDIX;
2034 tg3_phy_auxctl_write(tp,
2035 MII_TG3_AUXCTL_SHDWSEL_MISC, phy);
2040 static void tg3_phy_set_wirespeed(struct tg3 *tp)
2045 if (tp->phy_flags & TG3_PHYFLG_NO_ETH_WIRE_SPEED)
2048 ret = tg3_phy_auxctl_read(tp, MII_TG3_AUXCTL_SHDWSEL_MISC, &val);
2050 tg3_phy_auxctl_write(tp, MII_TG3_AUXCTL_SHDWSEL_MISC,
2051 val | MII_TG3_AUXCTL_MISC_WIRESPD_EN);
2054 static void tg3_phy_apply_otp(struct tg3 *tp)
2063 if (TG3_PHY_AUXCTL_SMDSP_ENABLE(tp))
2066 phy = ((otp & TG3_OTP_AGCTGT_MASK) >> TG3_OTP_AGCTGT_SHIFT);
2067 phy |= MII_TG3_DSP_TAP1_AGCTGT_DFLT;
2068 tg3_phydsp_write(tp, MII_TG3_DSP_TAP1, phy);
2070 phy = ((otp & TG3_OTP_HPFFLTR_MASK) >> TG3_OTP_HPFFLTR_SHIFT) |
2071 ((otp & TG3_OTP_HPFOVER_MASK) >> TG3_OTP_HPFOVER_SHIFT);
2072 tg3_phydsp_write(tp, MII_TG3_DSP_AADJ1CH0, phy);
2074 phy = ((otp & TG3_OTP_LPFDIS_MASK) >> TG3_OTP_LPFDIS_SHIFT);
2075 phy |= MII_TG3_DSP_AADJ1CH3_ADCCKADJ;
2076 tg3_phydsp_write(tp, MII_TG3_DSP_AADJ1CH3, phy);
2078 phy = ((otp & TG3_OTP_VDAC_MASK) >> TG3_OTP_VDAC_SHIFT);
2079 tg3_phydsp_write(tp, MII_TG3_DSP_EXP75, phy);
2081 phy = ((otp & TG3_OTP_10BTAMP_MASK) >> TG3_OTP_10BTAMP_SHIFT);
2082 tg3_phydsp_write(tp, MII_TG3_DSP_EXP96, phy);
2084 phy = ((otp & TG3_OTP_ROFF_MASK) >> TG3_OTP_ROFF_SHIFT) |
2085 ((otp & TG3_OTP_RCOFF_MASK) >> TG3_OTP_RCOFF_SHIFT);
2086 tg3_phydsp_write(tp, MII_TG3_DSP_EXP97, phy);
2088 TG3_PHY_AUXCTL_SMDSP_DISABLE(tp);
2091 static void tg3_phy_eee_adjust(struct tg3 *tp, u32 current_link_up)
2095 if (!(tp->phy_flags & TG3_PHYFLG_EEE_CAP))
2100 if (tp->link_config.autoneg == AUTONEG_ENABLE &&
2101 current_link_up == 1 &&
2102 tp->link_config.active_duplex == DUPLEX_FULL &&
2103 (tp->link_config.active_speed == SPEED_100 ||
2104 tp->link_config.active_speed == SPEED_1000)) {
2107 if (tp->link_config.active_speed == SPEED_1000)
2108 eeectl = TG3_CPMU_EEE_CTRL_EXIT_16_5_US;
2110 eeectl = TG3_CPMU_EEE_CTRL_EXIT_36_US;
2112 tw32(TG3_CPMU_EEE_CTRL, eeectl);
2114 tg3_phy_cl45_read(tp, MDIO_MMD_AN,
2115 TG3_CL45_D7_EEERES_STAT, &val);
2117 if (val == TG3_CL45_D7_EEERES_STAT_LP_1000T ||
2118 val == TG3_CL45_D7_EEERES_STAT_LP_100TX)
2122 if (!tp->setlpicnt) {
2123 if (current_link_up == 1 &&
2124 !TG3_PHY_AUXCTL_SMDSP_ENABLE(tp)) {
2125 tg3_phydsp_write(tp, MII_TG3_DSP_TAP26, 0x0000);
2126 TG3_PHY_AUXCTL_SMDSP_DISABLE(tp);
2129 val = tr32(TG3_CPMU_EEE_MODE);
2130 tw32(TG3_CPMU_EEE_MODE, val & ~TG3_CPMU_EEEMD_LPI_ENABLE);
2134 static void tg3_phy_eee_enable(struct tg3 *tp)
2138 if (tp->link_config.active_speed == SPEED_1000 &&
2139 (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717 ||
2140 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5719 ||
2141 tg3_flag(tp, 57765_CLASS)) &&
2142 !TG3_PHY_AUXCTL_SMDSP_ENABLE(tp)) {
2143 val = MII_TG3_DSP_TAP26_ALNOKO |
2144 MII_TG3_DSP_TAP26_RMRXSTO;
2145 tg3_phydsp_write(tp, MII_TG3_DSP_TAP26, val);
2146 TG3_PHY_AUXCTL_SMDSP_DISABLE(tp);
2149 val = tr32(TG3_CPMU_EEE_MODE);
2150 tw32(TG3_CPMU_EEE_MODE, val | TG3_CPMU_EEEMD_LPI_ENABLE);
2153 static int tg3_wait_macro_done(struct tg3 *tp)
2160 if (!tg3_readphy(tp, MII_TG3_DSP_CONTROL, &tmp32)) {
2161 if ((tmp32 & 0x1000) == 0)
2171 static int tg3_phy_write_and_check_testpat(struct tg3 *tp, int *resetp)
2173 static const u32 test_pat[4][6] = {
2174 { 0x00005555, 0x00000005, 0x00002aaa, 0x0000000a, 0x00003456, 0x00000003 },
2175 { 0x00002aaa, 0x0000000a, 0x00003333, 0x00000003, 0x0000789a, 0x00000005 },
2176 { 0x00005a5a, 0x00000005, 0x00002a6a, 0x0000000a, 0x00001bcd, 0x00000003 },
2177 { 0x00002a5a, 0x0000000a, 0x000033c3, 0x00000003, 0x00002ef1, 0x00000005 }
2181 for (chan = 0; chan < 4; chan++) {
2184 tg3_writephy(tp, MII_TG3_DSP_ADDRESS,
2185 (chan * 0x2000) | 0x0200);
2186 tg3_writephy(tp, MII_TG3_DSP_CONTROL, 0x0002);
2188 for (i = 0; i < 6; i++)
2189 tg3_writephy(tp, MII_TG3_DSP_RW_PORT,
2192 tg3_writephy(tp, MII_TG3_DSP_CONTROL, 0x0202);
2193 if (tg3_wait_macro_done(tp)) {
2198 tg3_writephy(tp, MII_TG3_DSP_ADDRESS,
2199 (chan * 0x2000) | 0x0200);
2200 tg3_writephy(tp, MII_TG3_DSP_CONTROL, 0x0082);
2201 if (tg3_wait_macro_done(tp)) {
2206 tg3_writephy(tp, MII_TG3_DSP_CONTROL, 0x0802);
2207 if (tg3_wait_macro_done(tp)) {
2212 for (i = 0; i < 6; i += 2) {
2215 if (tg3_readphy(tp, MII_TG3_DSP_RW_PORT, &low) ||
2216 tg3_readphy(tp, MII_TG3_DSP_RW_PORT, &high) ||
2217 tg3_wait_macro_done(tp)) {
2223 if (low != test_pat[chan][i] ||
2224 high != test_pat[chan][i+1]) {
2225 tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x000b);
2226 tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x4001);
2227 tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x4005);
2237 static int tg3_phy_reset_chanpat(struct tg3 *tp)
2241 for (chan = 0; chan < 4; chan++) {
2244 tg3_writephy(tp, MII_TG3_DSP_ADDRESS,
2245 (chan * 0x2000) | 0x0200);
2246 tg3_writephy(tp, MII_TG3_DSP_CONTROL, 0x0002);
2247 for (i = 0; i < 6; i++)
2248 tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x000);
2249 tg3_writephy(tp, MII_TG3_DSP_CONTROL, 0x0202);
2250 if (tg3_wait_macro_done(tp))
2257 static int tg3_phy_reset_5703_4_5(struct tg3 *tp)
2259 u32 reg32, phy9_orig;
2260 int retries, do_phy_reset, err;
2266 err = tg3_bmcr_reset(tp);
2272 /* Disable transmitter and interrupt. */
2273 if (tg3_readphy(tp, MII_TG3_EXT_CTRL, ®32))
2277 tg3_writephy(tp, MII_TG3_EXT_CTRL, reg32);
2279 /* Set full-duplex, 1000 mbps. */
2280 tg3_writephy(tp, MII_BMCR,
2281 BMCR_FULLDPLX | BMCR_SPEED1000);
2283 /* Set to master mode. */
2284 if (tg3_readphy(tp, MII_CTRL1000, &phy9_orig))
2287 tg3_writephy(tp, MII_CTRL1000,
2288 CTL1000_AS_MASTER | CTL1000_ENABLE_MASTER);
2290 err = TG3_PHY_AUXCTL_SMDSP_ENABLE(tp);
2294 /* Block the PHY control access. */
2295 tg3_phydsp_write(tp, 0x8005, 0x0800);
2297 err = tg3_phy_write_and_check_testpat(tp, &do_phy_reset);
2300 } while (--retries);
2302 err = tg3_phy_reset_chanpat(tp);
2306 tg3_phydsp_write(tp, 0x8005, 0x0000);
2308 tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x8200);
2309 tg3_writephy(tp, MII_TG3_DSP_CONTROL, 0x0000);
2311 TG3_PHY_AUXCTL_SMDSP_DISABLE(tp);
2313 tg3_writephy(tp, MII_CTRL1000, phy9_orig);
2315 if (!tg3_readphy(tp, MII_TG3_EXT_CTRL, ®32)) {
2317 tg3_writephy(tp, MII_TG3_EXT_CTRL, reg32);
2324 /* This will reset the tigon3 PHY if there is no valid
2325 * link unless the FORCE argument is non-zero.
2327 static int tg3_phy_reset(struct tg3 *tp)
2332 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
2333 val = tr32(GRC_MISC_CFG);
2334 tw32_f(GRC_MISC_CFG, val & ~GRC_MISC_CFG_EPHY_IDDQ);
2337 err = tg3_readphy(tp, MII_BMSR, &val);
2338 err |= tg3_readphy(tp, MII_BMSR, &val);
2342 if (netif_running(tp->dev) && netif_carrier_ok(tp->dev)) {
2343 netif_carrier_off(tp->dev);
2344 tg3_link_report(tp);
2347 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703 ||
2348 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704 ||
2349 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705) {
2350 err = tg3_phy_reset_5703_4_5(tp);
2357 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5784 &&
2358 GET_CHIP_REV(tp->pci_chip_rev_id) != CHIPREV_5784_AX) {
2359 cpmuctrl = tr32(TG3_CPMU_CTRL);
2360 if (cpmuctrl & CPMU_CTRL_GPHY_10MB_RXONLY)
2362 cpmuctrl & ~CPMU_CTRL_GPHY_10MB_RXONLY);
2365 err = tg3_bmcr_reset(tp);
2369 if (cpmuctrl & CPMU_CTRL_GPHY_10MB_RXONLY) {
2370 val = MII_TG3_DSP_EXP8_AEDW | MII_TG3_DSP_EXP8_REJ2MHz;
2371 tg3_phydsp_write(tp, MII_TG3_DSP_EXP8, val);
2373 tw32(TG3_CPMU_CTRL, cpmuctrl);
2376 if (GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5784_AX ||
2377 GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5761_AX) {
2378 val = tr32(TG3_CPMU_LSPD_1000MB_CLK);
2379 if ((val & CPMU_LSPD_1000MB_MACCLK_MASK) ==
2380 CPMU_LSPD_1000MB_MACCLK_12_5) {
2381 val &= ~CPMU_LSPD_1000MB_MACCLK_MASK;
2383 tw32_f(TG3_CPMU_LSPD_1000MB_CLK, val);
2387 if (tg3_flag(tp, 5717_PLUS) &&
2388 (tp->phy_flags & TG3_PHYFLG_MII_SERDES))
2391 tg3_phy_apply_otp(tp);
2393 if (tp->phy_flags & TG3_PHYFLG_ENABLE_APD)
2394 tg3_phy_toggle_apd(tp, true);
2396 tg3_phy_toggle_apd(tp, false);
2399 if ((tp->phy_flags & TG3_PHYFLG_ADC_BUG) &&
2400 !TG3_PHY_AUXCTL_SMDSP_ENABLE(tp)) {
2401 tg3_phydsp_write(tp, 0x201f, 0x2aaa);
2402 tg3_phydsp_write(tp, 0x000a, 0x0323);
2403 TG3_PHY_AUXCTL_SMDSP_DISABLE(tp);
2406 if (tp->phy_flags & TG3_PHYFLG_5704_A0_BUG) {
2407 tg3_writephy(tp, MII_TG3_MISC_SHDW, 0x8d68);
2408 tg3_writephy(tp, MII_TG3_MISC_SHDW, 0x8d68);
2411 if (tp->phy_flags & TG3_PHYFLG_BER_BUG) {
2412 if (!TG3_PHY_AUXCTL_SMDSP_ENABLE(tp)) {
2413 tg3_phydsp_write(tp, 0x000a, 0x310b);
2414 tg3_phydsp_write(tp, 0x201f, 0x9506);
2415 tg3_phydsp_write(tp, 0x401f, 0x14e2);
2416 TG3_PHY_AUXCTL_SMDSP_DISABLE(tp);
2418 } else if (tp->phy_flags & TG3_PHYFLG_JITTER_BUG) {
2419 if (!TG3_PHY_AUXCTL_SMDSP_ENABLE(tp)) {
2420 tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x000a);
2421 if (tp->phy_flags & TG3_PHYFLG_ADJUST_TRIM) {
2422 tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x110b);
2423 tg3_writephy(tp, MII_TG3_TEST1,
2424 MII_TG3_TEST1_TRIM_EN | 0x4);
2426 tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x010b);
2428 TG3_PHY_AUXCTL_SMDSP_DISABLE(tp);
2432 /* Set Extended packet length bit (bit 14) on all chips that */
2433 /* support jumbo frames */
2434 if ((tp->phy_id & TG3_PHY_ID_MASK) == TG3_PHY_ID_BCM5401) {
2435 /* Cannot do read-modify-write on 5401 */
2436 tg3_phy_auxctl_write(tp, MII_TG3_AUXCTL_SHDWSEL_AUXCTL, 0x4c20);
2437 } else if (tg3_flag(tp, JUMBO_CAPABLE)) {
2438 /* Set bit 14 with read-modify-write to preserve other bits */
2439 err = tg3_phy_auxctl_read(tp,
2440 MII_TG3_AUXCTL_SHDWSEL_AUXCTL, &val);
2442 tg3_phy_auxctl_write(tp, MII_TG3_AUXCTL_SHDWSEL_AUXCTL,
2443 val | MII_TG3_AUXCTL_ACTL_EXTPKTLEN);
2446 /* Set phy register 0x10 bit 0 to high fifo elasticity to support
2447 * jumbo frames transmission.
2449 if (tg3_flag(tp, JUMBO_CAPABLE)) {
2450 if (!tg3_readphy(tp, MII_TG3_EXT_CTRL, &val))
2451 tg3_writephy(tp, MII_TG3_EXT_CTRL,
2452 val | MII_TG3_EXT_CTRL_FIFO_ELASTIC);
2455 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
2456 /* adjust output voltage */
2457 tg3_writephy(tp, MII_TG3_FET_PTEST, 0x12);
2460 tg3_phy_toggle_automdix(tp, 1);
2461 tg3_phy_set_wirespeed(tp);
2465 #define TG3_GPIO_MSG_DRVR_PRES 0x00000001
2466 #define TG3_GPIO_MSG_NEED_VAUX 0x00000002
2467 #define TG3_GPIO_MSG_MASK (TG3_GPIO_MSG_DRVR_PRES | \
2468 TG3_GPIO_MSG_NEED_VAUX)
2469 #define TG3_GPIO_MSG_ALL_DRVR_PRES_MASK \
2470 ((TG3_GPIO_MSG_DRVR_PRES << 0) | \
2471 (TG3_GPIO_MSG_DRVR_PRES << 4) | \
2472 (TG3_GPIO_MSG_DRVR_PRES << 8) | \
2473 (TG3_GPIO_MSG_DRVR_PRES << 12))
2475 #define TG3_GPIO_MSG_ALL_NEED_VAUX_MASK \
2476 ((TG3_GPIO_MSG_NEED_VAUX << 0) | \
2477 (TG3_GPIO_MSG_NEED_VAUX << 4) | \
2478 (TG3_GPIO_MSG_NEED_VAUX << 8) | \
2479 (TG3_GPIO_MSG_NEED_VAUX << 12))
2481 static inline u32 tg3_set_function_status(struct tg3 *tp, u32 newstat)
2485 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717 ||
2486 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5719)
2487 status = tg3_ape_read32(tp, TG3_APE_GPIO_MSG);
2489 status = tr32(TG3_CPMU_DRV_STATUS);
2491 shift = TG3_APE_GPIO_MSG_SHIFT + 4 * tp->pci_fn;
2492 status &= ~(TG3_GPIO_MSG_MASK << shift);
2493 status |= (newstat << shift);
2495 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717 ||
2496 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5719)
2497 tg3_ape_write32(tp, TG3_APE_GPIO_MSG, status);
2499 tw32(TG3_CPMU_DRV_STATUS, status);
2501 return status >> TG3_APE_GPIO_MSG_SHIFT;
2504 static inline int tg3_pwrsrc_switch_to_vmain(struct tg3 *tp)
2506 if (!tg3_flag(tp, IS_NIC))
2509 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717 ||
2510 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5719 ||
2511 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5720) {
2512 if (tg3_ape_lock(tp, TG3_APE_LOCK_GPIO))
2515 tg3_set_function_status(tp, TG3_GPIO_MSG_DRVR_PRES);
2517 tw32_wait_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl,
2518 TG3_GRC_LCLCTL_PWRSW_DELAY);
2520 tg3_ape_unlock(tp, TG3_APE_LOCK_GPIO);
2522 tw32_wait_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl,
2523 TG3_GRC_LCLCTL_PWRSW_DELAY);
2529 static void tg3_pwrsrc_die_with_vmain(struct tg3 *tp)
2533 if (!tg3_flag(tp, IS_NIC) ||
2534 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
2535 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701)
2538 grc_local_ctrl = tp->grc_local_ctrl | GRC_LCLCTRL_GPIO_OE1;
2540 tw32_wait_f(GRC_LOCAL_CTRL,
2541 grc_local_ctrl | GRC_LCLCTRL_GPIO_OUTPUT1,
2542 TG3_GRC_LCLCTL_PWRSW_DELAY);
2544 tw32_wait_f(GRC_LOCAL_CTRL,
2546 TG3_GRC_LCLCTL_PWRSW_DELAY);
2548 tw32_wait_f(GRC_LOCAL_CTRL,
2549 grc_local_ctrl | GRC_LCLCTRL_GPIO_OUTPUT1,
2550 TG3_GRC_LCLCTL_PWRSW_DELAY);
2553 static void tg3_pwrsrc_switch_to_vaux(struct tg3 *tp)
2555 if (!tg3_flag(tp, IS_NIC))
2558 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
2559 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701) {
2560 tw32_wait_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl |
2561 (GRC_LCLCTRL_GPIO_OE0 |
2562 GRC_LCLCTRL_GPIO_OE1 |
2563 GRC_LCLCTRL_GPIO_OE2 |
2564 GRC_LCLCTRL_GPIO_OUTPUT0 |
2565 GRC_LCLCTRL_GPIO_OUTPUT1),
2566 TG3_GRC_LCLCTL_PWRSW_DELAY);
2567 } else if (tp->pdev->device == PCI_DEVICE_ID_TIGON3_5761 ||
2568 tp->pdev->device == TG3PCI_DEVICE_TIGON3_5761S) {
2569 /* The 5761 non-e device swaps GPIO 0 and GPIO 2. */
2570 u32 grc_local_ctrl = GRC_LCLCTRL_GPIO_OE0 |
2571 GRC_LCLCTRL_GPIO_OE1 |
2572 GRC_LCLCTRL_GPIO_OE2 |
2573 GRC_LCLCTRL_GPIO_OUTPUT0 |
2574 GRC_LCLCTRL_GPIO_OUTPUT1 |
2576 tw32_wait_f(GRC_LOCAL_CTRL, grc_local_ctrl,
2577 TG3_GRC_LCLCTL_PWRSW_DELAY);
2579 grc_local_ctrl |= GRC_LCLCTRL_GPIO_OUTPUT2;
2580 tw32_wait_f(GRC_LOCAL_CTRL, grc_local_ctrl,
2581 TG3_GRC_LCLCTL_PWRSW_DELAY);
2583 grc_local_ctrl &= ~GRC_LCLCTRL_GPIO_OUTPUT0;
2584 tw32_wait_f(GRC_LOCAL_CTRL, grc_local_ctrl,
2585 TG3_GRC_LCLCTL_PWRSW_DELAY);
2588 u32 grc_local_ctrl = 0;
2590 /* Workaround to prevent overdrawing Amps. */
2591 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5714) {
2592 grc_local_ctrl |= GRC_LCLCTRL_GPIO_OE3;
2593 tw32_wait_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl |
2595 TG3_GRC_LCLCTL_PWRSW_DELAY);
2598 /* On 5753 and variants, GPIO2 cannot be used. */
2599 no_gpio2 = tp->nic_sram_data_cfg &
2600 NIC_SRAM_DATA_CFG_NO_GPIO2;
2602 grc_local_ctrl |= GRC_LCLCTRL_GPIO_OE0 |
2603 GRC_LCLCTRL_GPIO_OE1 |
2604 GRC_LCLCTRL_GPIO_OE2 |
2605 GRC_LCLCTRL_GPIO_OUTPUT1 |
2606 GRC_LCLCTRL_GPIO_OUTPUT2;
2608 grc_local_ctrl &= ~(GRC_LCLCTRL_GPIO_OE2 |
2609 GRC_LCLCTRL_GPIO_OUTPUT2);
2611 tw32_wait_f(GRC_LOCAL_CTRL,
2612 tp->grc_local_ctrl | grc_local_ctrl,
2613 TG3_GRC_LCLCTL_PWRSW_DELAY);
2615 grc_local_ctrl |= GRC_LCLCTRL_GPIO_OUTPUT0;
2617 tw32_wait_f(GRC_LOCAL_CTRL,
2618 tp->grc_local_ctrl | grc_local_ctrl,
2619 TG3_GRC_LCLCTL_PWRSW_DELAY);
2622 grc_local_ctrl &= ~GRC_LCLCTRL_GPIO_OUTPUT2;
2623 tw32_wait_f(GRC_LOCAL_CTRL,
2624 tp->grc_local_ctrl | grc_local_ctrl,
2625 TG3_GRC_LCLCTL_PWRSW_DELAY);
2630 static void tg3_frob_aux_power_5717(struct tg3 *tp, bool wol_enable)
2634 /* Serialize power state transitions */
2635 if (tg3_ape_lock(tp, TG3_APE_LOCK_GPIO))
2638 if (tg3_flag(tp, ENABLE_ASF) || tg3_flag(tp, ENABLE_APE) || wol_enable)
2639 msg = TG3_GPIO_MSG_NEED_VAUX;
2641 msg = tg3_set_function_status(tp, msg);
2643 if (msg & TG3_GPIO_MSG_ALL_DRVR_PRES_MASK)
2646 if (msg & TG3_GPIO_MSG_ALL_NEED_VAUX_MASK)
2647 tg3_pwrsrc_switch_to_vaux(tp);
2649 tg3_pwrsrc_die_with_vmain(tp);
2652 tg3_ape_unlock(tp, TG3_APE_LOCK_GPIO);
2655 static void tg3_frob_aux_power(struct tg3 *tp, bool include_wol)
2657 bool need_vaux = false;
2659 /* The GPIOs do something completely different on 57765. */
2660 if (!tg3_flag(tp, IS_NIC) || tg3_flag(tp, 57765_CLASS))
2663 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717 ||
2664 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5719 ||
2665 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5720) {
2666 tg3_frob_aux_power_5717(tp, include_wol ?
2667 tg3_flag(tp, WOL_ENABLE) != 0 : 0);
2671 if (tp->pdev_peer && tp->pdev_peer != tp->pdev) {
2672 struct net_device *dev_peer;
2674 dev_peer = pci_get_drvdata(tp->pdev_peer);
2676 /* remove_one() may have been run on the peer. */
2678 struct tg3 *tp_peer = netdev_priv(dev_peer);
2680 if (tg3_flag(tp_peer, INIT_COMPLETE))
2683 if ((include_wol && tg3_flag(tp_peer, WOL_ENABLE)) ||
2684 tg3_flag(tp_peer, ENABLE_ASF))
2689 if ((include_wol && tg3_flag(tp, WOL_ENABLE)) ||
2690 tg3_flag(tp, ENABLE_ASF))
2694 tg3_pwrsrc_switch_to_vaux(tp);
2696 tg3_pwrsrc_die_with_vmain(tp);
2699 static int tg3_5700_link_polarity(struct tg3 *tp, u32 speed)
2701 if (tp->led_ctrl == LED_CTRL_MODE_PHY_2)
2703 else if ((tp->phy_id & TG3_PHY_ID_MASK) == TG3_PHY_ID_BCM5411) {
2704 if (speed != SPEED_10)
2706 } else if (speed == SPEED_10)
2712 static void tg3_power_down_phy(struct tg3 *tp, bool do_low_power)
2716 if (tp->phy_flags & TG3_PHYFLG_PHY_SERDES) {
2717 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704) {
2718 u32 sg_dig_ctrl = tr32(SG_DIG_CTRL);
2719 u32 serdes_cfg = tr32(MAC_SERDES_CFG);
2722 SG_DIG_USING_HW_AUTONEG | SG_DIG_SOFT_RESET;
2723 tw32(SG_DIG_CTRL, sg_dig_ctrl);
2724 tw32(MAC_SERDES_CFG, serdes_cfg | (1 << 15));
2729 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
2731 val = tr32(GRC_MISC_CFG);
2732 tw32_f(GRC_MISC_CFG, val | GRC_MISC_CFG_EPHY_IDDQ);
2735 } else if (tp->phy_flags & TG3_PHYFLG_IS_FET) {
2737 if (!tg3_readphy(tp, MII_TG3_FET_TEST, &phytest)) {
2740 tg3_writephy(tp, MII_ADVERTISE, 0);
2741 tg3_writephy(tp, MII_BMCR,
2742 BMCR_ANENABLE | BMCR_ANRESTART);
2744 tg3_writephy(tp, MII_TG3_FET_TEST,
2745 phytest | MII_TG3_FET_SHADOW_EN);
2746 if (!tg3_readphy(tp, MII_TG3_FET_SHDW_AUXMODE4, &phy)) {
2747 phy |= MII_TG3_FET_SHDW_AUXMODE4_SBPD;
2749 MII_TG3_FET_SHDW_AUXMODE4,
2752 tg3_writephy(tp, MII_TG3_FET_TEST, phytest);
2755 } else if (do_low_power) {
2756 tg3_writephy(tp, MII_TG3_EXT_CTRL,
2757 MII_TG3_EXT_CTRL_FORCE_LED_OFF);
2759 val = MII_TG3_AUXCTL_PCTL_100TX_LPWR |
2760 MII_TG3_AUXCTL_PCTL_SPR_ISOLATE |
2761 MII_TG3_AUXCTL_PCTL_VREG_11V;
2762 tg3_phy_auxctl_write(tp, MII_TG3_AUXCTL_SHDWSEL_PWRCTL, val);
2765 /* The PHY should not be powered down on some chips because
2768 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
2769 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704 ||
2770 (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5780 &&
2771 (tp->phy_flags & TG3_PHYFLG_MII_SERDES)))
2774 if (GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5784_AX ||
2775 GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5761_AX) {
2776 val = tr32(TG3_CPMU_LSPD_1000MB_CLK);
2777 val &= ~CPMU_LSPD_1000MB_MACCLK_MASK;
2778 val |= CPMU_LSPD_1000MB_MACCLK_12_5;
2779 tw32_f(TG3_CPMU_LSPD_1000MB_CLK, val);
2782 tg3_writephy(tp, MII_BMCR, BMCR_PDOWN);
2785 /* tp->lock is held. */
2786 static int tg3_nvram_lock(struct tg3 *tp)
2788 if (tg3_flag(tp, NVRAM)) {
2791 if (tp->nvram_lock_cnt == 0) {
2792 tw32(NVRAM_SWARB, SWARB_REQ_SET1);
2793 for (i = 0; i < 8000; i++) {
2794 if (tr32(NVRAM_SWARB) & SWARB_GNT1)
2799 tw32(NVRAM_SWARB, SWARB_REQ_CLR1);
2803 tp->nvram_lock_cnt++;
2808 /* tp->lock is held. */
2809 static void tg3_nvram_unlock(struct tg3 *tp)
2811 if (tg3_flag(tp, NVRAM)) {
2812 if (tp->nvram_lock_cnt > 0)
2813 tp->nvram_lock_cnt--;
2814 if (tp->nvram_lock_cnt == 0)
2815 tw32_f(NVRAM_SWARB, SWARB_REQ_CLR1);
2819 /* tp->lock is held. */
2820 static void tg3_enable_nvram_access(struct tg3 *tp)
2822 if (tg3_flag(tp, 5750_PLUS) && !tg3_flag(tp, PROTECTED_NVRAM)) {
2823 u32 nvaccess = tr32(NVRAM_ACCESS);
2825 tw32(NVRAM_ACCESS, nvaccess | ACCESS_ENABLE);
2829 /* tp->lock is held. */
2830 static void tg3_disable_nvram_access(struct tg3 *tp)
2832 if (tg3_flag(tp, 5750_PLUS) && !tg3_flag(tp, PROTECTED_NVRAM)) {
2833 u32 nvaccess = tr32(NVRAM_ACCESS);
2835 tw32(NVRAM_ACCESS, nvaccess & ~ACCESS_ENABLE);
2839 static int tg3_nvram_read_using_eeprom(struct tg3 *tp,
2840 u32 offset, u32 *val)
2845 if (offset > EEPROM_ADDR_ADDR_MASK || (offset % 4) != 0)
2848 tmp = tr32(GRC_EEPROM_ADDR) & ~(EEPROM_ADDR_ADDR_MASK |
2849 EEPROM_ADDR_DEVID_MASK |
2851 tw32(GRC_EEPROM_ADDR,
2853 (0 << EEPROM_ADDR_DEVID_SHIFT) |
2854 ((offset << EEPROM_ADDR_ADDR_SHIFT) &
2855 EEPROM_ADDR_ADDR_MASK) |
2856 EEPROM_ADDR_READ | EEPROM_ADDR_START);
2858 for (i = 0; i < 1000; i++) {
2859 tmp = tr32(GRC_EEPROM_ADDR);
2861 if (tmp & EEPROM_ADDR_COMPLETE)
2865 if (!(tmp & EEPROM_ADDR_COMPLETE))
2868 tmp = tr32(GRC_EEPROM_DATA);
2871 * The data will always be opposite the native endian
2872 * format. Perform a blind byteswap to compensate.
2879 #define NVRAM_CMD_TIMEOUT 10000
2881 static int tg3_nvram_exec_cmd(struct tg3 *tp, u32 nvram_cmd)
2885 tw32(NVRAM_CMD, nvram_cmd);
2886 for (i = 0; i < NVRAM_CMD_TIMEOUT; i++) {
2888 if (tr32(NVRAM_CMD) & NVRAM_CMD_DONE) {
2894 if (i == NVRAM_CMD_TIMEOUT)
2900 static u32 tg3_nvram_phys_addr(struct tg3 *tp, u32 addr)
2902 if (tg3_flag(tp, NVRAM) &&
2903 tg3_flag(tp, NVRAM_BUFFERED) &&
2904 tg3_flag(tp, FLASH) &&
2905 !tg3_flag(tp, NO_NVRAM_ADDR_TRANS) &&
2906 (tp->nvram_jedecnum == JEDEC_ATMEL))
2908 addr = ((addr / tp->nvram_pagesize) <<
2909 ATMEL_AT45DB0X1B_PAGE_POS) +
2910 (addr % tp->nvram_pagesize);
2915 static u32 tg3_nvram_logical_addr(struct tg3 *tp, u32 addr)
2917 if (tg3_flag(tp, NVRAM) &&
2918 tg3_flag(tp, NVRAM_BUFFERED) &&
2919 tg3_flag(tp, FLASH) &&
2920 !tg3_flag(tp, NO_NVRAM_ADDR_TRANS) &&
2921 (tp->nvram_jedecnum == JEDEC_ATMEL))
2923 addr = ((addr >> ATMEL_AT45DB0X1B_PAGE_POS) *
2924 tp->nvram_pagesize) +
2925 (addr & ((1 << ATMEL_AT45DB0X1B_PAGE_POS) - 1));
2930 /* NOTE: Data read in from NVRAM is byteswapped according to
2931 * the byteswapping settings for all other register accesses.
2932 * tg3 devices are BE devices, so on a BE machine, the data
2933 * returned will be exactly as it is seen in NVRAM. On a LE
2934 * machine, the 32-bit value will be byteswapped.
2936 static int tg3_nvram_read(struct tg3 *tp, u32 offset, u32 *val)
2940 if (!tg3_flag(tp, NVRAM))
2941 return tg3_nvram_read_using_eeprom(tp, offset, val);
2943 offset = tg3_nvram_phys_addr(tp, offset);
2945 if (offset > NVRAM_ADDR_MSK)
2948 ret = tg3_nvram_lock(tp);
2952 tg3_enable_nvram_access(tp);
2954 tw32(NVRAM_ADDR, offset);
2955 ret = tg3_nvram_exec_cmd(tp, NVRAM_CMD_RD | NVRAM_CMD_GO |
2956 NVRAM_CMD_FIRST | NVRAM_CMD_LAST | NVRAM_CMD_DONE);
2959 *val = tr32(NVRAM_RDDATA);
2961 tg3_disable_nvram_access(tp);
2963 tg3_nvram_unlock(tp);
2968 /* Ensures NVRAM data is in bytestream format. */
2969 static int tg3_nvram_read_be32(struct tg3 *tp, u32 offset, __be32 *val)
2972 int res = tg3_nvram_read(tp, offset, &v);
2974 *val = cpu_to_be32(v);
2978 static int tg3_nvram_write_block_using_eeprom(struct tg3 *tp,
2979 u32 offset, u32 len, u8 *buf)
2984 for (i = 0; i < len; i += 4) {
2990 memcpy(&data, buf + i, 4);
2993 * The SEEPROM interface expects the data to always be opposite
2994 * the native endian format. We accomplish this by reversing
2995 * all the operations that would have been performed on the
2996 * data from a call to tg3_nvram_read_be32().
2998 tw32(GRC_EEPROM_DATA, swab32(be32_to_cpu(data)));
3000 val = tr32(GRC_EEPROM_ADDR);
3001 tw32(GRC_EEPROM_ADDR, val | EEPROM_ADDR_COMPLETE);
3003 val &= ~(EEPROM_ADDR_ADDR_MASK | EEPROM_ADDR_DEVID_MASK |
3005 tw32(GRC_EEPROM_ADDR, val |
3006 (0 << EEPROM_ADDR_DEVID_SHIFT) |
3007 (addr & EEPROM_ADDR_ADDR_MASK) |
3011 for (j = 0; j < 1000; j++) {
3012 val = tr32(GRC_EEPROM_ADDR);
3014 if (val & EEPROM_ADDR_COMPLETE)
3018 if (!(val & EEPROM_ADDR_COMPLETE)) {
3027 /* offset and length are dword aligned */
3028 static int tg3_nvram_write_block_unbuffered(struct tg3 *tp, u32 offset, u32 len,
3032 u32 pagesize = tp->nvram_pagesize;
3033 u32 pagemask = pagesize - 1;
3037 tmp = kmalloc(pagesize, GFP_KERNEL);
3043 u32 phy_addr, page_off, size;
3045 phy_addr = offset & ~pagemask;
3047 for (j = 0; j < pagesize; j += 4) {
3048 ret = tg3_nvram_read_be32(tp, phy_addr + j,
3049 (__be32 *) (tmp + j));
3056 page_off = offset & pagemask;
3063 memcpy(tmp + page_off, buf, size);
3065 offset = offset + (pagesize - page_off);
3067 tg3_enable_nvram_access(tp);
3070 * Before we can erase the flash page, we need
3071 * to issue a special "write enable" command.
3073 nvram_cmd = NVRAM_CMD_WREN | NVRAM_CMD_GO | NVRAM_CMD_DONE;
3075 if (tg3_nvram_exec_cmd(tp, nvram_cmd))
3078 /* Erase the target page */
3079 tw32(NVRAM_ADDR, phy_addr);
3081 nvram_cmd = NVRAM_CMD_GO | NVRAM_CMD_DONE | NVRAM_CMD_WR |
3082 NVRAM_CMD_FIRST | NVRAM_CMD_LAST | NVRAM_CMD_ERASE;
3084 if (tg3_nvram_exec_cmd(tp, nvram_cmd))
3087 /* Issue another write enable to start the write. */
3088 nvram_cmd = NVRAM_CMD_WREN | NVRAM_CMD_GO | NVRAM_CMD_DONE;
3090 if (tg3_nvram_exec_cmd(tp, nvram_cmd))
3093 for (j = 0; j < pagesize; j += 4) {
3096 data = *((__be32 *) (tmp + j));
3098 tw32(NVRAM_WRDATA, be32_to_cpu(data));
3100 tw32(NVRAM_ADDR, phy_addr + j);
3102 nvram_cmd = NVRAM_CMD_GO | NVRAM_CMD_DONE |
3106 nvram_cmd |= NVRAM_CMD_FIRST;
3107 else if (j == (pagesize - 4))
3108 nvram_cmd |= NVRAM_CMD_LAST;
3110 ret = tg3_nvram_exec_cmd(tp, nvram_cmd);
3118 nvram_cmd = NVRAM_CMD_WRDI | NVRAM_CMD_GO | NVRAM_CMD_DONE;
3119 tg3_nvram_exec_cmd(tp, nvram_cmd);
3126 /* offset and length are dword aligned */
3127 static int tg3_nvram_write_block_buffered(struct tg3 *tp, u32 offset, u32 len,
3132 for (i = 0; i < len; i += 4, offset += 4) {
3133 u32 page_off, phy_addr, nvram_cmd;
3136 memcpy(&data, buf + i, 4);
3137 tw32(NVRAM_WRDATA, be32_to_cpu(data));
3139 page_off = offset % tp->nvram_pagesize;
3141 phy_addr = tg3_nvram_phys_addr(tp, offset);
3143 tw32(NVRAM_ADDR, phy_addr);
3145 nvram_cmd = NVRAM_CMD_GO | NVRAM_CMD_DONE | NVRAM_CMD_WR;
3147 if (page_off == 0 || i == 0)
3148 nvram_cmd |= NVRAM_CMD_FIRST;
3149 if (page_off == (tp->nvram_pagesize - 4))
3150 nvram_cmd |= NVRAM_CMD_LAST;
3153 nvram_cmd |= NVRAM_CMD_LAST;
3155 if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5752 &&
3156 !tg3_flag(tp, 5755_PLUS) &&
3157 (tp->nvram_jedecnum == JEDEC_ST) &&
3158 (nvram_cmd & NVRAM_CMD_FIRST)) {
3161 cmd = NVRAM_CMD_WREN | NVRAM_CMD_GO | NVRAM_CMD_DONE;
3162 ret = tg3_nvram_exec_cmd(tp, cmd);
3166 if (!tg3_flag(tp, FLASH)) {
3167 /* We always do complete word writes to eeprom. */
3168 nvram_cmd |= (NVRAM_CMD_FIRST | NVRAM_CMD_LAST);
3171 ret = tg3_nvram_exec_cmd(tp, nvram_cmd);
3178 /* offset and length are dword aligned */
3179 static int tg3_nvram_write_block(struct tg3 *tp, u32 offset, u32 len, u8 *buf)
3183 if (tg3_flag(tp, EEPROM_WRITE_PROT)) {
3184 tw32_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl &
3185 ~GRC_LCLCTRL_GPIO_OUTPUT1);
3189 if (!tg3_flag(tp, NVRAM)) {
3190 ret = tg3_nvram_write_block_using_eeprom(tp, offset, len, buf);
3194 ret = tg3_nvram_lock(tp);
3198 tg3_enable_nvram_access(tp);
3199 if (tg3_flag(tp, 5750_PLUS) && !tg3_flag(tp, PROTECTED_NVRAM))
3200 tw32(NVRAM_WRITE1, 0x406);
3202 grc_mode = tr32(GRC_MODE);
3203 tw32(GRC_MODE, grc_mode | GRC_MODE_NVRAM_WR_ENABLE);
3205 if (tg3_flag(tp, NVRAM_BUFFERED) || !tg3_flag(tp, FLASH)) {
3206 ret = tg3_nvram_write_block_buffered(tp, offset, len,
3209 ret = tg3_nvram_write_block_unbuffered(tp, offset, len,
3213 grc_mode = tr32(GRC_MODE);
3214 tw32(GRC_MODE, grc_mode & ~GRC_MODE_NVRAM_WR_ENABLE);
3216 tg3_disable_nvram_access(tp);
3217 tg3_nvram_unlock(tp);
3220 if (tg3_flag(tp, EEPROM_WRITE_PROT)) {
3221 tw32_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl);
3228 #define RX_CPU_SCRATCH_BASE 0x30000
3229 #define RX_CPU_SCRATCH_SIZE 0x04000
3230 #define TX_CPU_SCRATCH_BASE 0x34000
3231 #define TX_CPU_SCRATCH_SIZE 0x04000
3233 /* tp->lock is held. */
3234 static int tg3_halt_cpu(struct tg3 *tp, u32 offset)
3238 BUG_ON(offset == TX_CPU_BASE && tg3_flag(tp, 5705_PLUS));
3240 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
3241 u32 val = tr32(GRC_VCPU_EXT_CTRL);
3243 tw32(GRC_VCPU_EXT_CTRL, val | GRC_VCPU_EXT_CTRL_HALT_CPU);
3246 if (offset == RX_CPU_BASE) {
3247 for (i = 0; i < 10000; i++) {
3248 tw32(offset + CPU_STATE, 0xffffffff);
3249 tw32(offset + CPU_MODE, CPU_MODE_HALT);
3250 if (tr32(offset + CPU_MODE) & CPU_MODE_HALT)
3254 tw32(offset + CPU_STATE, 0xffffffff);
3255 tw32_f(offset + CPU_MODE, CPU_MODE_HALT);
3258 for (i = 0; i < 10000; i++) {
3259 tw32(offset + CPU_STATE, 0xffffffff);
3260 tw32(offset + CPU_MODE, CPU_MODE_HALT);
3261 if (tr32(offset + CPU_MODE) & CPU_MODE_HALT)
3267 netdev_err(tp->dev, "%s timed out, %s CPU\n",
3268 __func__, offset == RX_CPU_BASE ? "RX" : "TX");
3272 /* Clear firmware's nvram arbitration. */
3273 if (tg3_flag(tp, NVRAM))
3274 tw32(NVRAM_SWARB, SWARB_REQ_CLR0);
3279 unsigned int fw_base;
3280 unsigned int fw_len;
3281 const __be32 *fw_data;
3284 /* tp->lock is held. */
3285 static int tg3_load_firmware_cpu(struct tg3 *tp, u32 cpu_base,
3286 u32 cpu_scratch_base, int cpu_scratch_size,
3287 struct fw_info *info)
3289 int err, lock_err, i;
3290 void (*write_op)(struct tg3 *, u32, u32);
3292 if (cpu_base == TX_CPU_BASE && tg3_flag(tp, 5705_PLUS)) {
3294 "%s: Trying to load TX cpu firmware which is 5705\n",
3299 if (tg3_flag(tp, 5705_PLUS))
3300 write_op = tg3_write_mem;
3302 write_op = tg3_write_indirect_reg32;
3304 /* It is possible that bootcode is still loading at this point.
3305 * Get the nvram lock first before halting the cpu.
3307 lock_err = tg3_nvram_lock(tp);
3308 err = tg3_halt_cpu(tp, cpu_base);
3310 tg3_nvram_unlock(tp);
3314 for (i = 0; i < cpu_scratch_size; i += sizeof(u32))
3315 write_op(tp, cpu_scratch_base + i, 0);
3316 tw32(cpu_base + CPU_STATE, 0xffffffff);
3317 tw32(cpu_base + CPU_MODE, tr32(cpu_base+CPU_MODE)|CPU_MODE_HALT);
3318 for (i = 0; i < (info->fw_len / sizeof(u32)); i++)
3319 write_op(tp, (cpu_scratch_base +
3320 (info->fw_base & 0xffff) +
3322 be32_to_cpu(info->fw_data[i]));
3330 /* tp->lock is held. */
3331 static int tg3_load_5701_a0_firmware_fix(struct tg3 *tp)
3333 struct fw_info info;
3334 const __be32 *fw_data;
3337 fw_data = (void *)tp->fw->data;
3339 /* Firmware blob starts with version numbers, followed by
3340 start address and length. We are setting complete length.
3341 length = end_address_of_bss - start_address_of_text.
3342 Remainder is the blob to be loaded contiguously
3343 from start address. */
3345 info.fw_base = be32_to_cpu(fw_data[1]);
3346 info.fw_len = tp->fw->size - 12;
3347 info.fw_data = &fw_data[3];
3349 err = tg3_load_firmware_cpu(tp, RX_CPU_BASE,
3350 RX_CPU_SCRATCH_BASE, RX_CPU_SCRATCH_SIZE,
3355 err = tg3_load_firmware_cpu(tp, TX_CPU_BASE,
3356 TX_CPU_SCRATCH_BASE, TX_CPU_SCRATCH_SIZE,
3361 /* Now startup only the RX cpu. */
3362 tw32(RX_CPU_BASE + CPU_STATE, 0xffffffff);
3363 tw32_f(RX_CPU_BASE + CPU_PC, info.fw_base);
3365 for (i = 0; i < 5; i++) {
3366 if (tr32(RX_CPU_BASE + CPU_PC) == info.fw_base)
3368 tw32(RX_CPU_BASE + CPU_STATE, 0xffffffff);
3369 tw32(RX_CPU_BASE + CPU_MODE, CPU_MODE_HALT);
3370 tw32_f(RX_CPU_BASE + CPU_PC, info.fw_base);
3374 netdev_err(tp->dev, "%s fails to set RX CPU PC, is %08x "
3375 "should be %08x\n", __func__,
3376 tr32(RX_CPU_BASE + CPU_PC), info.fw_base);
3379 tw32(RX_CPU_BASE + CPU_STATE, 0xffffffff);
3380 tw32_f(RX_CPU_BASE + CPU_MODE, 0x00000000);
3385 /* tp->lock is held. */
3386 static int tg3_load_tso_firmware(struct tg3 *tp)
3388 struct fw_info info;
3389 const __be32 *fw_data;
3390 unsigned long cpu_base, cpu_scratch_base, cpu_scratch_size;
3393 if (tg3_flag(tp, HW_TSO_1) ||
3394 tg3_flag(tp, HW_TSO_2) ||
3395 tg3_flag(tp, HW_TSO_3))
3398 fw_data = (void *)tp->fw->data;
3400 /* Firmware blob starts with version numbers, followed by
3401 start address and length. We are setting complete length.
3402 length = end_address_of_bss - start_address_of_text.
3403 Remainder is the blob to be loaded contiguously
3404 from start address. */
3406 info.fw_base = be32_to_cpu(fw_data[1]);
3407 cpu_scratch_size = tp->fw_len;
3408 info.fw_len = tp->fw->size - 12;
3409 info.fw_data = &fw_data[3];
3411 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705) {
3412 cpu_base = RX_CPU_BASE;
3413 cpu_scratch_base = NIC_SRAM_MBUF_POOL_BASE5705;
3415 cpu_base = TX_CPU_BASE;
3416 cpu_scratch_base = TX_CPU_SCRATCH_BASE;
3417 cpu_scratch_size = TX_CPU_SCRATCH_SIZE;
3420 err = tg3_load_firmware_cpu(tp, cpu_base,
3421 cpu_scratch_base, cpu_scratch_size,
3426 /* Now startup the cpu. */
3427 tw32(cpu_base + CPU_STATE, 0xffffffff);
3428 tw32_f(cpu_base + CPU_PC, info.fw_base);
3430 for (i = 0; i < 5; i++) {
3431 if (tr32(cpu_base + CPU_PC) == info.fw_base)
3433 tw32(cpu_base + CPU_STATE, 0xffffffff);
3434 tw32(cpu_base + CPU_MODE, CPU_MODE_HALT);
3435 tw32_f(cpu_base + CPU_PC, info.fw_base);
3440 "%s fails to set CPU PC, is %08x should be %08x\n",
3441 __func__, tr32(cpu_base + CPU_PC), info.fw_base);
3444 tw32(cpu_base + CPU_STATE, 0xffffffff);
3445 tw32_f(cpu_base + CPU_MODE, 0x00000000);
3450 /* tp->lock is held. */
3451 static void __tg3_set_mac_addr(struct tg3 *tp, int skip_mac_1)
3453 u32 addr_high, addr_low;
3456 addr_high = ((tp->dev->dev_addr[0] << 8) |
3457 tp->dev->dev_addr[1]);
3458 addr_low = ((tp->dev->dev_addr[2] << 24) |
3459 (tp->dev->dev_addr[3] << 16) |
3460 (tp->dev->dev_addr[4] << 8) |
3461 (tp->dev->dev_addr[5] << 0));
3462 for (i = 0; i < 4; i++) {
3463 if (i == 1 && skip_mac_1)
3465 tw32(MAC_ADDR_0_HIGH + (i * 8), addr_high);
3466 tw32(MAC_ADDR_0_LOW + (i * 8), addr_low);
3469 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703 ||
3470 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704) {
3471 for (i = 0; i < 12; i++) {
3472 tw32(MAC_EXTADDR_0_HIGH + (i * 8), addr_high);
3473 tw32(MAC_EXTADDR_0_LOW + (i * 8), addr_low);
3477 addr_high = (tp->dev->dev_addr[0] +
3478 tp->dev->dev_addr[1] +
3479 tp->dev->dev_addr[2] +
3480 tp->dev->dev_addr[3] +
3481 tp->dev->dev_addr[4] +
3482 tp->dev->dev_addr[5]) &
3483 TX_BACKOFF_SEED_MASK;
3484 tw32(MAC_TX_BACKOFF_SEED, addr_high);
3487 static void tg3_enable_register_access(struct tg3 *tp)
3490 * Make sure register accesses (indirect or otherwise) will function
3493 pci_write_config_dword(tp->pdev,
3494 TG3PCI_MISC_HOST_CTRL, tp->misc_host_ctrl);
3497 static int tg3_power_up(struct tg3 *tp)
3501 tg3_enable_register_access(tp);
3503 err = pci_set_power_state(tp->pdev, PCI_D0);
3505 /* Switch out of Vaux if it is a NIC */
3506 tg3_pwrsrc_switch_to_vmain(tp);
3508 netdev_err(tp->dev, "Transition to D0 failed\n");
3514 static int tg3_setup_phy(struct tg3 *, int);
3516 static int tg3_power_down_prepare(struct tg3 *tp)
3519 bool device_should_wake, do_low_power;
3521 tg3_enable_register_access(tp);
3523 /* Restore the CLKREQ setting. */
3524 if (tg3_flag(tp, CLKREQ_BUG)) {
3527 pci_read_config_word(tp->pdev,
3528 pci_pcie_cap(tp->pdev) + PCI_EXP_LNKCTL,
3530 lnkctl |= PCI_EXP_LNKCTL_CLKREQ_EN;
3531 pci_write_config_word(tp->pdev,
3532 pci_pcie_cap(tp->pdev) + PCI_EXP_LNKCTL,
3536 misc_host_ctrl = tr32(TG3PCI_MISC_HOST_CTRL);
3537 tw32(TG3PCI_MISC_HOST_CTRL,
3538 misc_host_ctrl | MISC_HOST_CTRL_MASK_PCI_INT);
3540 device_should_wake = device_may_wakeup(&tp->pdev->dev) &&
3541 tg3_flag(tp, WOL_ENABLE);
3543 if (tg3_flag(tp, USE_PHYLIB)) {
3544 do_low_power = false;
3545 if ((tp->phy_flags & TG3_PHYFLG_IS_CONNECTED) &&
3546 !(tp->phy_flags & TG3_PHYFLG_IS_LOW_POWER)) {
3547 struct phy_device *phydev;
3548 u32 phyid, advertising;
3550 phydev = tp->mdio_bus->phy_map[TG3_PHY_MII_ADDR];
3552 tp->phy_flags |= TG3_PHYFLG_IS_LOW_POWER;
3554 tp->link_config.orig_speed = phydev->speed;
3555 tp->link_config.orig_duplex = phydev->duplex;
3556 tp->link_config.orig_autoneg = phydev->autoneg;
3557 tp->link_config.orig_advertising = phydev->advertising;
3559 advertising = ADVERTISED_TP |
3561 ADVERTISED_Autoneg |
3562 ADVERTISED_10baseT_Half;
3564 if (tg3_flag(tp, ENABLE_ASF) || device_should_wake) {
3565 if (tg3_flag(tp, WOL_SPEED_100MB))
3567 ADVERTISED_100baseT_Half |
3568 ADVERTISED_100baseT_Full |
3569 ADVERTISED_10baseT_Full;
3571 advertising |= ADVERTISED_10baseT_Full;
3574 phydev->advertising = advertising;
3576 phy_start_aneg(phydev);
3578 phyid = phydev->drv->phy_id & phydev->drv->phy_id_mask;
3579 if (phyid != PHY_ID_BCMAC131) {
3580 phyid &= PHY_BCM_OUI_MASK;
3581 if (phyid == PHY_BCM_OUI_1 ||
3582 phyid == PHY_BCM_OUI_2 ||
3583 phyid == PHY_BCM_OUI_3)
3584 do_low_power = true;
3588 do_low_power = true;
3590 if (!(tp->phy_flags & TG3_PHYFLG_IS_LOW_POWER)) {
3591 tp->phy_flags |= TG3_PHYFLG_IS_LOW_POWER;
3592 tp->link_config.orig_speed = tp->link_config.speed;
3593 tp->link_config.orig_duplex = tp->link_config.duplex;
3594 tp->link_config.orig_autoneg = tp->link_config.autoneg;
3597 if (!(tp->phy_flags & TG3_PHYFLG_ANY_SERDES)) {
3598 tp->link_config.speed = SPEED_10;
3599 tp->link_config.duplex = DUPLEX_HALF;
3600 tp->link_config.autoneg = AUTONEG_ENABLE;
3601 tg3_setup_phy(tp, 0);
3605 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
3608 val = tr32(GRC_VCPU_EXT_CTRL);
3609 tw32(GRC_VCPU_EXT_CTRL, val | GRC_VCPU_EXT_CTRL_DISABLE_WOL);
3610 } else if (!tg3_flag(tp, ENABLE_ASF)) {
3614 for (i = 0; i < 200; i++) {
3615 tg3_read_mem(tp, NIC_SRAM_FW_ASF_STATUS_MBOX, &val);
3616 if (val == ~NIC_SRAM_FIRMWARE_MBOX_MAGIC1)
3621 if (tg3_flag(tp, WOL_CAP))
3622 tg3_write_mem(tp, NIC_SRAM_WOL_MBOX, WOL_SIGNATURE |
3623 WOL_DRV_STATE_SHUTDOWN |
3627 if (device_should_wake) {
3630 if (!(tp->phy_flags & TG3_PHYFLG_PHY_SERDES)) {
3632 !(tp->phy_flags & TG3_PHYFLG_IS_FET)) {
3633 tg3_phy_auxctl_write(tp,
3634 MII_TG3_AUXCTL_SHDWSEL_PWRCTL,
3635 MII_TG3_AUXCTL_PCTL_WOL_EN |
3636 MII_TG3_AUXCTL_PCTL_100TX_LPWR |
3637 MII_TG3_AUXCTL_PCTL_CL_AB_TXDAC);
3641 if (tp->phy_flags & TG3_PHYFLG_MII_SERDES)
3642 mac_mode = MAC_MODE_PORT_MODE_GMII;
3644 mac_mode = MAC_MODE_PORT_MODE_MII;
3646 mac_mode |= tp->mac_mode & MAC_MODE_LINK_POLARITY;
3647 if (GET_ASIC_REV(tp->pci_chip_rev_id) ==
3649 u32 speed = tg3_flag(tp, WOL_SPEED_100MB) ?
3650 SPEED_100 : SPEED_10;
3651 if (tg3_5700_link_polarity(tp, speed))
3652 mac_mode |= MAC_MODE_LINK_POLARITY;
3654 mac_mode &= ~MAC_MODE_LINK_POLARITY;
3657 mac_mode = MAC_MODE_PORT_MODE_TBI;
3660 if (!tg3_flag(tp, 5750_PLUS))
3661 tw32(MAC_LED_CTRL, tp->led_ctrl);
3663 mac_mode |= MAC_MODE_MAGIC_PKT_ENABLE;
3664 if ((tg3_flag(tp, 5705_PLUS) && !tg3_flag(tp, 5780_CLASS)) &&
3665 (tg3_flag(tp, ENABLE_ASF) || tg3_flag(tp, ENABLE_APE)))
3666 mac_mode |= MAC_MODE_KEEP_FRAME_IN_WOL;
3668 if (tg3_flag(tp, ENABLE_APE))
3669 mac_mode |= MAC_MODE_APE_TX_EN |
3670 MAC_MODE_APE_RX_EN |
3671 MAC_MODE_TDE_ENABLE;
3673 tw32_f(MAC_MODE, mac_mode);
3676 tw32_f(MAC_RX_MODE, RX_MODE_ENABLE);
3680 if (!tg3_flag(tp, WOL_SPEED_100MB) &&
3681 (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
3682 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701)) {
3685 base_val = tp->pci_clock_ctrl;
3686 base_val |= (CLOCK_CTRL_RXCLK_DISABLE |
3687 CLOCK_CTRL_TXCLK_DISABLE);
3689 tw32_wait_f(TG3PCI_CLOCK_CTRL, base_val | CLOCK_CTRL_ALTCLK |
3690 CLOCK_CTRL_PWRDOWN_PLL133, 40);
3691 } else if (tg3_flag(tp, 5780_CLASS) ||
3692 tg3_flag(tp, CPMU_PRESENT) ||
3693 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
3695 } else if (!(tg3_flag(tp, 5750_PLUS) && tg3_flag(tp, ENABLE_ASF))) {
3696 u32 newbits1, newbits2;
3698 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
3699 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701) {
3700 newbits1 = (CLOCK_CTRL_RXCLK_DISABLE |
3701 CLOCK_CTRL_TXCLK_DISABLE |
3703 newbits2 = newbits1 | CLOCK_CTRL_44MHZ_CORE;
3704 } else if (tg3_flag(tp, 5705_PLUS)) {
3705 newbits1 = CLOCK_CTRL_625_CORE;
3706 newbits2 = newbits1 | CLOCK_CTRL_ALTCLK;
3708 newbits1 = CLOCK_CTRL_ALTCLK;
3709 newbits2 = newbits1 | CLOCK_CTRL_44MHZ_CORE;
3712 tw32_wait_f(TG3PCI_CLOCK_CTRL, tp->pci_clock_ctrl | newbits1,
3715 tw32_wait_f(TG3PCI_CLOCK_CTRL, tp->pci_clock_ctrl | newbits2,
3718 if (!tg3_flag(tp, 5705_PLUS)) {
3721 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
3722 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701) {
3723 newbits3 = (CLOCK_CTRL_RXCLK_DISABLE |
3724 CLOCK_CTRL_TXCLK_DISABLE |
3725 CLOCK_CTRL_44MHZ_CORE);
3727 newbits3 = CLOCK_CTRL_44MHZ_CORE;
3730 tw32_wait_f(TG3PCI_CLOCK_CTRL,
3731 tp->pci_clock_ctrl | newbits3, 40);
3735 if (!(device_should_wake) && !tg3_flag(tp, ENABLE_ASF))
3736 tg3_power_down_phy(tp, do_low_power);
3738 tg3_frob_aux_power(tp, true);
3740 /* Workaround for unstable PLL clock */
3741 if ((GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5750_AX) ||
3742 (GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5750_BX)) {
3743 u32 val = tr32(0x7d00);
3745 val &= ~((1 << 16) | (1 << 4) | (1 << 2) | (1 << 1) | 1);
3747 if (!tg3_flag(tp, ENABLE_ASF)) {
3750 err = tg3_nvram_lock(tp);
3751 tg3_halt_cpu(tp, RX_CPU_BASE);
3753 tg3_nvram_unlock(tp);
3757 tg3_write_sig_post_reset(tp, RESET_KIND_SHUTDOWN);
3762 static void tg3_power_down(struct tg3 *tp)
3764 tg3_power_down_prepare(tp);
3766 pci_wake_from_d3(tp->pdev, tg3_flag(tp, WOL_ENABLE));
3767 pci_set_power_state(tp->pdev, PCI_D3hot);
3770 static void tg3_aux_stat_to_speed_duplex(struct tg3 *tp, u32 val, u16 *speed, u8 *duplex)
3772 switch (val & MII_TG3_AUX_STAT_SPDMASK) {
3773 case MII_TG3_AUX_STAT_10HALF:
3775 *duplex = DUPLEX_HALF;
3778 case MII_TG3_AUX_STAT_10FULL:
3780 *duplex = DUPLEX_FULL;
3783 case MII_TG3_AUX_STAT_100HALF:
3785 *duplex = DUPLEX_HALF;
3788 case MII_TG3_AUX_STAT_100FULL:
3790 *duplex = DUPLEX_FULL;
3793 case MII_TG3_AUX_STAT_1000HALF:
3794 *speed = SPEED_1000;
3795 *duplex = DUPLEX_HALF;
3798 case MII_TG3_AUX_STAT_1000FULL:
3799 *speed = SPEED_1000;
3800 *duplex = DUPLEX_FULL;
3804 if (tp->phy_flags & TG3_PHYFLG_IS_FET) {
3805 *speed = (val & MII_TG3_AUX_STAT_100) ? SPEED_100 :
3807 *duplex = (val & MII_TG3_AUX_STAT_FULL) ? DUPLEX_FULL :
3811 *speed = SPEED_INVALID;
3812 *duplex = DUPLEX_INVALID;
3817 static int tg3_phy_autoneg_cfg(struct tg3 *tp, u32 advertise, u32 flowctrl)
3822 new_adv = ADVERTISE_CSMA;
3823 new_adv |= ethtool_adv_to_mii_adv_t(advertise) & ADVERTISE_ALL;
3824 new_adv |= mii_advertise_flowctrl(flowctrl);
3826 err = tg3_writephy(tp, MII_ADVERTISE, new_adv);
3830 if (!(tp->phy_flags & TG3_PHYFLG_10_100_ONLY)) {
3831 new_adv = ethtool_adv_to_mii_ctrl1000_t(advertise);
3833 if (tp->pci_chip_rev_id == CHIPREV_ID_5701_A0 ||
3834 tp->pci_chip_rev_id == CHIPREV_ID_5701_B0)
3835 new_adv |= CTL1000_AS_MASTER | CTL1000_ENABLE_MASTER;
3837 err = tg3_writephy(tp, MII_CTRL1000, new_adv);
3842 if (!(tp->phy_flags & TG3_PHYFLG_EEE_CAP))
3845 tw32(TG3_CPMU_EEE_MODE,
3846 tr32(TG3_CPMU_EEE_MODE) & ~TG3_CPMU_EEEMD_LPI_ENABLE);
3848 err = TG3_PHY_AUXCTL_SMDSP_ENABLE(tp);
3853 /* Advertise 100-BaseTX EEE ability */
3854 if (advertise & ADVERTISED_100baseT_Full)
3855 val |= MDIO_AN_EEE_ADV_100TX;
3856 /* Advertise 1000-BaseT EEE ability */
3857 if (advertise & ADVERTISED_1000baseT_Full)
3858 val |= MDIO_AN_EEE_ADV_1000T;
3859 err = tg3_phy_cl45_write(tp, MDIO_MMD_AN, MDIO_AN_EEE_ADV, val);
3863 switch (GET_ASIC_REV(tp->pci_chip_rev_id)) {
3865 case ASIC_REV_57765:
3866 case ASIC_REV_57766:
3868 /* If we advertised any eee advertisements above... */
3870 val = MII_TG3_DSP_TAP26_ALNOKO |
3871 MII_TG3_DSP_TAP26_RMRXSTO |
3872 MII_TG3_DSP_TAP26_OPCSINPT;
3873 tg3_phydsp_write(tp, MII_TG3_DSP_TAP26, val);
3876 if (!tg3_phydsp_read(tp, MII_TG3_DSP_CH34TP2, &val))
3877 tg3_phydsp_write(tp, MII_TG3_DSP_CH34TP2, val |
3878 MII_TG3_DSP_CH34TP2_HIBW01);
3881 err2 = TG3_PHY_AUXCTL_SMDSP_DISABLE(tp);
3890 static void tg3_phy_copper_begin(struct tg3 *tp)
3895 if (tp->phy_flags & TG3_PHYFLG_IS_LOW_POWER) {
3896 new_adv = ADVERTISED_10baseT_Half |
3897 ADVERTISED_10baseT_Full;
3898 if (tg3_flag(tp, WOL_SPEED_100MB))
3899 new_adv |= ADVERTISED_100baseT_Half |
3900 ADVERTISED_100baseT_Full;
3902 tg3_phy_autoneg_cfg(tp, new_adv,
3903 FLOW_CTRL_TX | FLOW_CTRL_RX);
3904 } else if (tp->link_config.speed == SPEED_INVALID) {
3905 if (tp->phy_flags & TG3_PHYFLG_10_100_ONLY)
3906 tp->link_config.advertising &=
3907 ~(ADVERTISED_1000baseT_Half |
3908 ADVERTISED_1000baseT_Full);
3910 tg3_phy_autoneg_cfg(tp, tp->link_config.advertising,
3911 tp->link_config.flowctrl);
3913 /* Asking for a specific link mode. */
3914 if (tp->link_config.speed == SPEED_1000) {
3915 if (tp->link_config.duplex == DUPLEX_FULL)
3916 new_adv = ADVERTISED_1000baseT_Full;
3918 new_adv = ADVERTISED_1000baseT_Half;
3919 } else if (tp->link_config.speed == SPEED_100) {
3920 if (tp->link_config.duplex == DUPLEX_FULL)
3921 new_adv = ADVERTISED_100baseT_Full;
3923 new_adv = ADVERTISED_100baseT_Half;
3925 if (tp->link_config.duplex == DUPLEX_FULL)
3926 new_adv = ADVERTISED_10baseT_Full;
3928 new_adv = ADVERTISED_10baseT_Half;
3931 tg3_phy_autoneg_cfg(tp, new_adv,
3932 tp->link_config.flowctrl);
3935 if (tp->link_config.autoneg == AUTONEG_DISABLE &&
3936 tp->link_config.speed != SPEED_INVALID) {
3937 u32 bmcr, orig_bmcr;
3939 tp->link_config.active_speed = tp->link_config.speed;
3940 tp->link_config.active_duplex = tp->link_config.duplex;
3943 switch (tp->link_config.speed) {
3949 bmcr |= BMCR_SPEED100;
3953 bmcr |= BMCR_SPEED1000;
3957 if (tp->link_config.duplex == DUPLEX_FULL)
3958 bmcr |= BMCR_FULLDPLX;
3960 if (!tg3_readphy(tp, MII_BMCR, &orig_bmcr) &&
3961 (bmcr != orig_bmcr)) {
3962 tg3_writephy(tp, MII_BMCR, BMCR_LOOPBACK);
3963 for (i = 0; i < 1500; i++) {
3967 if (tg3_readphy(tp, MII_BMSR, &tmp) ||
3968 tg3_readphy(tp, MII_BMSR, &tmp))
3970 if (!(tmp & BMSR_LSTATUS)) {
3975 tg3_writephy(tp, MII_BMCR, bmcr);
3979 tg3_writephy(tp, MII_BMCR,
3980 BMCR_ANENABLE | BMCR_ANRESTART);
3984 static int tg3_init_5401phy_dsp(struct tg3 *tp)
3988 /* Turn off tap power management. */
3989 /* Set Extended packet length bit */
3990 err = tg3_phy_auxctl_write(tp, MII_TG3_AUXCTL_SHDWSEL_AUXCTL, 0x4c20);
3992 err |= tg3_phydsp_write(tp, 0x0012, 0x1804);
3993 err |= tg3_phydsp_write(tp, 0x0013, 0x1204);
3994 err |= tg3_phydsp_write(tp, 0x8006, 0x0132);
3995 err |= tg3_phydsp_write(tp, 0x8006, 0x0232);
3996 err |= tg3_phydsp_write(tp, 0x201f, 0x0a20);
4003 static bool tg3_phy_copper_an_config_ok(struct tg3 *tp, u32 *lcladv)
4005 u32 advmsk, tgtadv, advertising;
4007 advertising = tp->link_config.advertising;
4008 tgtadv = ethtool_adv_to_mii_adv_t(advertising) & ADVERTISE_ALL;
4010 advmsk = ADVERTISE_ALL;
4011 if (tp->link_config.active_duplex == DUPLEX_FULL) {
4012 tgtadv |= mii_advertise_flowctrl(tp->link_config.flowctrl);
4013 advmsk |= ADVERTISE_PAUSE_CAP | ADVERTISE_PAUSE_ASYM;
4016 if (tg3_readphy(tp, MII_ADVERTISE, lcladv))
4019 if ((*lcladv & advmsk) != tgtadv)
4022 if (!(tp->phy_flags & TG3_PHYFLG_10_100_ONLY)) {
4025 tgtadv = ethtool_adv_to_mii_ctrl1000_t(advertising);
4027 if (tg3_readphy(tp, MII_CTRL1000, &tg3_ctrl))
4030 tg3_ctrl &= (ADVERTISE_1000HALF | ADVERTISE_1000FULL);
4031 if (tg3_ctrl != tgtadv)
4038 static bool tg3_phy_copper_fetch_rmtadv(struct tg3 *tp, u32 *rmtadv)
4042 if (!(tp->phy_flags & TG3_PHYFLG_10_100_ONLY)) {
4045 if (tg3_readphy(tp, MII_STAT1000, &val))
4048 lpeth = mii_stat1000_to_ethtool_lpa_t(val);
4051 if (tg3_readphy(tp, MII_LPA, rmtadv))
4054 lpeth |= mii_lpa_to_ethtool_lpa_t(*rmtadv);
4055 tp->link_config.rmt_adv = lpeth;
4060 static int tg3_setup_copper_phy(struct tg3 *tp, int force_reset)
4062 int current_link_up;
4064 u32 lcl_adv, rmt_adv;
4072 (MAC_STATUS_SYNC_CHANGED |
4073 MAC_STATUS_CFG_CHANGED |
4074 MAC_STATUS_MI_COMPLETION |
4075 MAC_STATUS_LNKSTATE_CHANGED));
4078 if ((tp->mi_mode & MAC_MI_MODE_AUTO_POLL) != 0) {
4080 (tp->mi_mode & ~MAC_MI_MODE_AUTO_POLL));
4084 tg3_phy_auxctl_write(tp, MII_TG3_AUXCTL_SHDWSEL_PWRCTL, 0);
4086 /* Some third-party PHYs need to be reset on link going
4089 if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703 ||
4090 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704 ||
4091 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705) &&
4092 netif_carrier_ok(tp->dev)) {
4093 tg3_readphy(tp, MII_BMSR, &bmsr);
4094 if (!tg3_readphy(tp, MII_BMSR, &bmsr) &&
4095 !(bmsr & BMSR_LSTATUS))
4101 if ((tp->phy_id & TG3_PHY_ID_MASK) == TG3_PHY_ID_BCM5401) {
4102 tg3_readphy(tp, MII_BMSR, &bmsr);
4103 if (tg3_readphy(tp, MII_BMSR, &bmsr) ||
4104 !tg3_flag(tp, INIT_COMPLETE))
4107 if (!(bmsr & BMSR_LSTATUS)) {
4108 err = tg3_init_5401phy_dsp(tp);
4112 tg3_readphy(tp, MII_BMSR, &bmsr);
4113 for (i = 0; i < 1000; i++) {
4115 if (!tg3_readphy(tp, MII_BMSR, &bmsr) &&
4116 (bmsr & BMSR_LSTATUS)) {
4122 if ((tp->phy_id & TG3_PHY_ID_REV_MASK) ==
4123 TG3_PHY_REV_BCM5401_B0 &&
4124 !(bmsr & BMSR_LSTATUS) &&
4125 tp->link_config.active_speed == SPEED_1000) {
4126 err = tg3_phy_reset(tp);
4128 err = tg3_init_5401phy_dsp(tp);
4133 } else if (tp->pci_chip_rev_id == CHIPREV_ID_5701_A0 ||
4134 tp->pci_chip_rev_id == CHIPREV_ID_5701_B0) {
4135 /* 5701 {A0,B0} CRC bug workaround */
4136 tg3_writephy(tp, 0x15, 0x0a75);
4137 tg3_writephy(tp, MII_TG3_MISC_SHDW, 0x8c68);
4138 tg3_writephy(tp, MII_TG3_MISC_SHDW, 0x8d68);
4139 tg3_writephy(tp, MII_TG3_MISC_SHDW, 0x8c68);
4142 /* Clear pending interrupts... */
4143 tg3_readphy(tp, MII_TG3_ISTAT, &val);
4144 tg3_readphy(tp, MII_TG3_ISTAT, &val);
4146 if (tp->phy_flags & TG3_PHYFLG_USE_MI_INTERRUPT)
4147 tg3_writephy(tp, MII_TG3_IMASK, ~MII_TG3_INT_LINKCHG);
4148 else if (!(tp->phy_flags & TG3_PHYFLG_IS_FET))
4149 tg3_writephy(tp, MII_TG3_IMASK, ~0);
4151 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
4152 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701) {
4153 if (tp->led_ctrl == LED_CTRL_MODE_PHY_1)
4154 tg3_writephy(tp, MII_TG3_EXT_CTRL,
4155 MII_TG3_EXT_CTRL_LNK3_LED_MODE);
4157 tg3_writephy(tp, MII_TG3_EXT_CTRL, 0);
4160 current_link_up = 0;
4161 current_speed = SPEED_INVALID;
4162 current_duplex = DUPLEX_INVALID;
4163 tp->phy_flags &= ~TG3_PHYFLG_MDIX_STATE;
4164 tp->link_config.rmt_adv = 0;
4166 if (tp->phy_flags & TG3_PHYFLG_CAPACITIVE_COUPLING) {
4167 err = tg3_phy_auxctl_read(tp,
4168 MII_TG3_AUXCTL_SHDWSEL_MISCTEST,
4170 if (!err && !(val & (1 << 10))) {
4171 tg3_phy_auxctl_write(tp,
4172 MII_TG3_AUXCTL_SHDWSEL_MISCTEST,
4179 for (i = 0; i < 100; i++) {
4180 tg3_readphy(tp, MII_BMSR, &bmsr);
4181 if (!tg3_readphy(tp, MII_BMSR, &bmsr) &&
4182 (bmsr & BMSR_LSTATUS))
4187 if (bmsr & BMSR_LSTATUS) {
4190 tg3_readphy(tp, MII_TG3_AUX_STAT, &aux_stat);
4191 for (i = 0; i < 2000; i++) {
4193 if (!tg3_readphy(tp, MII_TG3_AUX_STAT, &aux_stat) &&
4198 tg3_aux_stat_to_speed_duplex(tp, aux_stat,
4203 for (i = 0; i < 200; i++) {
4204 tg3_readphy(tp, MII_BMCR, &bmcr);
4205 if (tg3_readphy(tp, MII_BMCR, &bmcr))
4207 if (bmcr && bmcr != 0x7fff)
4215 tp->link_config.active_speed = current_speed;
4216 tp->link_config.active_duplex = current_duplex;
4218 if (tp->link_config.autoneg == AUTONEG_ENABLE) {
4219 if ((bmcr & BMCR_ANENABLE) &&
4220 tg3_phy_copper_an_config_ok(tp, &lcl_adv) &&
4221 tg3_phy_copper_fetch_rmtadv(tp, &rmt_adv))
4222 current_link_up = 1;
4224 if (!(bmcr & BMCR_ANENABLE) &&
4225 tp->link_config.speed == current_speed &&
4226 tp->link_config.duplex == current_duplex &&
4227 tp->link_config.flowctrl ==
4228 tp->link_config.active_flowctrl) {
4229 current_link_up = 1;
4233 if (current_link_up == 1 &&
4234 tp->link_config.active_duplex == DUPLEX_FULL) {
4237 if (tp->phy_flags & TG3_PHYFLG_IS_FET) {
4238 reg = MII_TG3_FET_GEN_STAT;
4239 bit = MII_TG3_FET_GEN_STAT_MDIXSTAT;
4241 reg = MII_TG3_EXT_STAT;
4242 bit = MII_TG3_EXT_STAT_MDIX;
4245 if (!tg3_readphy(tp, reg, &val) && (val & bit))
4246 tp->phy_flags |= TG3_PHYFLG_MDIX_STATE;
4248 tg3_setup_flow_control(tp, lcl_adv, rmt_adv);
4253 if (current_link_up == 0 || (tp->phy_flags & TG3_PHYFLG_IS_LOW_POWER)) {
4254 tg3_phy_copper_begin(tp);
4256 tg3_readphy(tp, MII_BMSR, &bmsr);
4257 if ((!tg3_readphy(tp, MII_BMSR, &bmsr) && (bmsr & BMSR_LSTATUS)) ||
4258 (tp->mac_mode & MAC_MODE_PORT_INT_LPBACK))
4259 current_link_up = 1;
4262 tp->mac_mode &= ~MAC_MODE_PORT_MODE_MASK;
4263 if (current_link_up == 1) {
4264 if (tp->link_config.active_speed == SPEED_100 ||
4265 tp->link_config.active_speed == SPEED_10)
4266 tp->mac_mode |= MAC_MODE_PORT_MODE_MII;
4268 tp->mac_mode |= MAC_MODE_PORT_MODE_GMII;
4269 } else if (tp->phy_flags & TG3_PHYFLG_IS_FET)
4270 tp->mac_mode |= MAC_MODE_PORT_MODE_MII;
4272 tp->mac_mode |= MAC_MODE_PORT_MODE_GMII;
4274 tp->mac_mode &= ~MAC_MODE_HALF_DUPLEX;
4275 if (tp->link_config.active_duplex == DUPLEX_HALF)
4276 tp->mac_mode |= MAC_MODE_HALF_DUPLEX;
4278 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700) {
4279 if (current_link_up == 1 &&
4280 tg3_5700_link_polarity(tp, tp->link_config.active_speed))
4281 tp->mac_mode |= MAC_MODE_LINK_POLARITY;
4283 tp->mac_mode &= ~MAC_MODE_LINK_POLARITY;
4286 /* ??? Without this setting Netgear GA302T PHY does not
4287 * ??? send/receive packets...
4289 if ((tp->phy_id & TG3_PHY_ID_MASK) == TG3_PHY_ID_BCM5411 &&
4290 tp->pci_chip_rev_id == CHIPREV_ID_5700_ALTIMA) {
4291 tp->mi_mode |= MAC_MI_MODE_AUTO_POLL;
4292 tw32_f(MAC_MI_MODE, tp->mi_mode);
4296 tw32_f(MAC_MODE, tp->mac_mode);
4299 tg3_phy_eee_adjust(tp, current_link_up);
4301 if (tg3_flag(tp, USE_LINKCHG_REG)) {
4302 /* Polled via timer. */
4303 tw32_f(MAC_EVENT, 0);
4305 tw32_f(MAC_EVENT, MAC_EVENT_LNKSTATE_CHANGED);
4309 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 &&
4310 current_link_up == 1 &&
4311 tp->link_config.active_speed == SPEED_1000 &&
4312 (tg3_flag(tp, PCIX_MODE) || tg3_flag(tp, PCI_HIGH_SPEED))) {
4315 (MAC_STATUS_SYNC_CHANGED |
4316 MAC_STATUS_CFG_CHANGED));
4319 NIC_SRAM_FIRMWARE_MBOX,
4320 NIC_SRAM_FIRMWARE_MBOX_MAGIC2);
4323 /* Prevent send BD corruption. */
4324 if (tg3_flag(tp, CLKREQ_BUG)) {
4325 u16 oldlnkctl, newlnkctl;
4327 pci_read_config_word(tp->pdev,
4328 pci_pcie_cap(tp->pdev) + PCI_EXP_LNKCTL,
4330 if (tp->link_config.active_speed == SPEED_100 ||
4331 tp->link_config.active_speed == SPEED_10)
4332 newlnkctl = oldlnkctl & ~PCI_EXP_LNKCTL_CLKREQ_EN;
4334 newlnkctl = oldlnkctl | PCI_EXP_LNKCTL_CLKREQ_EN;
4335 if (newlnkctl != oldlnkctl)
4336 pci_write_config_word(tp->pdev,
4337 pci_pcie_cap(tp->pdev) +
4338 PCI_EXP_LNKCTL, newlnkctl);
4341 if (current_link_up != netif_carrier_ok(tp->dev)) {
4342 if (current_link_up)
4343 netif_carrier_on(tp->dev);
4345 netif_carrier_off(tp->dev);
4346 tg3_link_report(tp);
4352 struct tg3_fiber_aneginfo {
4354 #define ANEG_STATE_UNKNOWN 0
4355 #define ANEG_STATE_AN_ENABLE 1
4356 #define ANEG_STATE_RESTART_INIT 2
4357 #define ANEG_STATE_RESTART 3
4358 #define ANEG_STATE_DISABLE_LINK_OK 4
4359 #define ANEG_STATE_ABILITY_DETECT_INIT 5
4360 #define ANEG_STATE_ABILITY_DETECT 6
4361 #define ANEG_STATE_ACK_DETECT_INIT 7
4362 #define ANEG_STATE_ACK_DETECT 8
4363 #define ANEG_STATE_COMPLETE_ACK_INIT 9
4364 #define ANEG_STATE_COMPLETE_ACK 10
4365 #define ANEG_STATE_IDLE_DETECT_INIT 11
4366 #define ANEG_STATE_IDLE_DETECT 12
4367 #define ANEG_STATE_LINK_OK 13
4368 #define ANEG_STATE_NEXT_PAGE_WAIT_INIT 14
4369 #define ANEG_STATE_NEXT_PAGE_WAIT 15
4372 #define MR_AN_ENABLE 0x00000001
4373 #define MR_RESTART_AN 0x00000002
4374 #define MR_AN_COMPLETE 0x00000004
4375 #define MR_PAGE_RX 0x00000008
4376 #define MR_NP_LOADED 0x00000010
4377 #define MR_TOGGLE_TX 0x00000020
4378 #define MR_LP_ADV_FULL_DUPLEX 0x00000040
4379 #define MR_LP_ADV_HALF_DUPLEX 0x00000080
4380 #define MR_LP_ADV_SYM_PAUSE 0x00000100
4381 #define MR_LP_ADV_ASYM_PAUSE 0x00000200
4382 #define MR_LP_ADV_REMOTE_FAULT1 0x00000400
4383 #define MR_LP_ADV_REMOTE_FAULT2 0x00000800
4384 #define MR_LP_ADV_NEXT_PAGE 0x00001000
4385 #define MR_TOGGLE_RX 0x00002000
4386 #define MR_NP_RX 0x00004000
4388 #define MR_LINK_OK 0x80000000
4390 unsigned long link_time, cur_time;
4392 u32 ability_match_cfg;
4393 int ability_match_count;
4395 char ability_match, idle_match, ack_match;
4397 u32 txconfig, rxconfig;
4398 #define ANEG_CFG_NP 0x00000080
4399 #define ANEG_CFG_ACK 0x00000040
4400 #define ANEG_CFG_RF2 0x00000020
4401 #define ANEG_CFG_RF1 0x00000010
4402 #define ANEG_CFG_PS2 0x00000001
4403 #define ANEG_CFG_PS1 0x00008000
4404 #define ANEG_CFG_HD 0x00004000
4405 #define ANEG_CFG_FD 0x00002000
4406 #define ANEG_CFG_INVAL 0x00001f06
4411 #define ANEG_TIMER_ENAB 2
4412 #define ANEG_FAILED -1
4414 #define ANEG_STATE_SETTLE_TIME 10000
4416 static int tg3_fiber_aneg_smachine(struct tg3 *tp,
4417 struct tg3_fiber_aneginfo *ap)
4420 unsigned long delta;
4424 if (ap->state == ANEG_STATE_UNKNOWN) {
4428 ap->ability_match_cfg = 0;
4429 ap->ability_match_count = 0;
4430 ap->ability_match = 0;
4436 if (tr32(MAC_STATUS) & MAC_STATUS_RCVD_CFG) {
4437 rx_cfg_reg = tr32(MAC_RX_AUTO_NEG);
4439 if (rx_cfg_reg != ap->ability_match_cfg) {
4440 ap->ability_match_cfg = rx_cfg_reg;
4441 ap->ability_match = 0;
4442 ap->ability_match_count = 0;
4444 if (++ap->ability_match_count > 1) {
4445 ap->ability_match = 1;
4446 ap->ability_match_cfg = rx_cfg_reg;
4449 if (rx_cfg_reg & ANEG_CFG_ACK)
4457 ap->ability_match_cfg = 0;
4458 ap->ability_match_count = 0;
4459 ap->ability_match = 0;
4465 ap->rxconfig = rx_cfg_reg;
4468 switch (ap->state) {
4469 case ANEG_STATE_UNKNOWN:
4470 if (ap->flags & (MR_AN_ENABLE | MR_RESTART_AN))
4471 ap->state = ANEG_STATE_AN_ENABLE;
4474 case ANEG_STATE_AN_ENABLE:
4475 ap->flags &= ~(MR_AN_COMPLETE | MR_PAGE_RX);
4476 if (ap->flags & MR_AN_ENABLE) {
4479 ap->ability_match_cfg = 0;
4480 ap->ability_match_count = 0;
4481 ap->ability_match = 0;
4485 ap->state = ANEG_STATE_RESTART_INIT;
4487 ap->state = ANEG_STATE_DISABLE_LINK_OK;
4491 case ANEG_STATE_RESTART_INIT:
4492 ap->link_time = ap->cur_time;
4493 ap->flags &= ~(MR_NP_LOADED);
4495 tw32(MAC_TX_AUTO_NEG, 0);
4496 tp->mac_mode |= MAC_MODE_SEND_CONFIGS;
4497 tw32_f(MAC_MODE, tp->mac_mode);
4500 ret = ANEG_TIMER_ENAB;
4501 ap->state = ANEG_STATE_RESTART;
4504 case ANEG_STATE_RESTART:
4505 delta = ap->cur_time - ap->link_time;
4506 if (delta > ANEG_STATE_SETTLE_TIME)
4507 ap->state = ANEG_STATE_ABILITY_DETECT_INIT;
4509 ret = ANEG_TIMER_ENAB;
4512 case ANEG_STATE_DISABLE_LINK_OK:
4516 case ANEG_STATE_ABILITY_DETECT_INIT:
4517 ap->flags &= ~(MR_TOGGLE_TX);
4518 ap->txconfig = ANEG_CFG_FD;
4519 flowctrl = tg3_advert_flowctrl_1000X(tp->link_config.flowctrl);
4520 if (flowctrl & ADVERTISE_1000XPAUSE)
4521 ap->txconfig |= ANEG_CFG_PS1;
4522 if (flowctrl & ADVERTISE_1000XPSE_ASYM)
4523 ap->txconfig |= ANEG_CFG_PS2;
4524 tw32(MAC_TX_AUTO_NEG, ap->txconfig);
4525 tp->mac_mode |= MAC_MODE_SEND_CONFIGS;
4526 tw32_f(MAC_MODE, tp->mac_mode);
4529 ap->state = ANEG_STATE_ABILITY_DETECT;
4532 case ANEG_STATE_ABILITY_DETECT:
4533 if (ap->ability_match != 0 && ap->rxconfig != 0)
4534 ap->state = ANEG_STATE_ACK_DETECT_INIT;
4537 case ANEG_STATE_ACK_DETECT_INIT:
4538 ap->txconfig |= ANEG_CFG_ACK;
4539 tw32(MAC_TX_AUTO_NEG, ap->txconfig);
4540 tp->mac_mode |= MAC_MODE_SEND_CONFIGS;
4541 tw32_f(MAC_MODE, tp->mac_mode);
4544 ap->state = ANEG_STATE_ACK_DETECT;
4547 case ANEG_STATE_ACK_DETECT:
4548 if (ap->ack_match != 0) {
4549 if ((ap->rxconfig & ~ANEG_CFG_ACK) ==
4550 (ap->ability_match_cfg & ~ANEG_CFG_ACK)) {
4551 ap->state = ANEG_STATE_COMPLETE_ACK_INIT;
4553 ap->state = ANEG_STATE_AN_ENABLE;
4555 } else if (ap->ability_match != 0 &&
4556 ap->rxconfig == 0) {
4557 ap->state = ANEG_STATE_AN_ENABLE;
4561 case ANEG_STATE_COMPLETE_ACK_INIT:
4562 if (ap->rxconfig & ANEG_CFG_INVAL) {
4566 ap->flags &= ~(MR_LP_ADV_FULL_DUPLEX |
4567 MR_LP_ADV_HALF_DUPLEX |
4568 MR_LP_ADV_SYM_PAUSE |
4569 MR_LP_ADV_ASYM_PAUSE |
4570 MR_LP_ADV_REMOTE_FAULT1 |
4571 MR_LP_ADV_REMOTE_FAULT2 |
4572 MR_LP_ADV_NEXT_PAGE |
4575 if (ap->rxconfig & ANEG_CFG_FD)
4576 ap->flags |= MR_LP_ADV_FULL_DUPLEX;
4577 if (ap->rxconfig & ANEG_CFG_HD)
4578 ap->flags |= MR_LP_ADV_HALF_DUPLEX;
4579 if (ap->rxconfig & ANEG_CFG_PS1)
4580 ap->flags |= MR_LP_ADV_SYM_PAUSE;
4581 if (ap->rxconfig & ANEG_CFG_PS2)
4582 ap->flags |= MR_LP_ADV_ASYM_PAUSE;
4583 if (ap->rxconfig & ANEG_CFG_RF1)
4584 ap->flags |= MR_LP_ADV_REMOTE_FAULT1;
4585 if (ap->rxconfig & ANEG_CFG_RF2)
4586 ap->flags |= MR_LP_ADV_REMOTE_FAULT2;
4587 if (ap->rxconfig & ANEG_CFG_NP)
4588 ap->flags |= MR_LP_ADV_NEXT_PAGE;
4590 ap->link_time = ap->cur_time;
4592 ap->flags ^= (MR_TOGGLE_TX);
4593 if (ap->rxconfig & 0x0008)
4594 ap->flags |= MR_TOGGLE_RX;
4595 if (ap->rxconfig & ANEG_CFG_NP)
4596 ap->flags |= MR_NP_RX;
4597 ap->flags |= MR_PAGE_RX;
4599 ap->state = ANEG_STATE_COMPLETE_ACK;
4600 ret = ANEG_TIMER_ENAB;
4603 case ANEG_STATE_COMPLETE_ACK:
4604 if (ap->ability_match != 0 &&
4605 ap->rxconfig == 0) {
4606 ap->state = ANEG_STATE_AN_ENABLE;
4609 delta = ap->cur_time - ap->link_time;
4610 if (delta > ANEG_STATE_SETTLE_TIME) {
4611 if (!(ap->flags & (MR_LP_ADV_NEXT_PAGE))) {
4612 ap->state = ANEG_STATE_IDLE_DETECT_INIT;
4614 if ((ap->txconfig & ANEG_CFG_NP) == 0 &&
4615 !(ap->flags & MR_NP_RX)) {
4616 ap->state = ANEG_STATE_IDLE_DETECT_INIT;
4624 case ANEG_STATE_IDLE_DETECT_INIT:
4625 ap->link_time = ap->cur_time;
4626 tp->mac_mode &= ~MAC_MODE_SEND_CONFIGS;
4627 tw32_f(MAC_MODE, tp->mac_mode);
4630 ap->state = ANEG_STATE_IDLE_DETECT;
4631 ret = ANEG_TIMER_ENAB;
4634 case ANEG_STATE_IDLE_DETECT:
4635 if (ap->ability_match != 0 &&
4636 ap->rxconfig == 0) {
4637 ap->state = ANEG_STATE_AN_ENABLE;
4640 delta = ap->cur_time - ap->link_time;
4641 if (delta > ANEG_STATE_SETTLE_TIME) {
4642 /* XXX another gem from the Broadcom driver :( */
4643 ap->state = ANEG_STATE_LINK_OK;
4647 case ANEG_STATE_LINK_OK:
4648 ap->flags |= (MR_AN_COMPLETE | MR_LINK_OK);
4652 case ANEG_STATE_NEXT_PAGE_WAIT_INIT:
4653 /* ??? unimplemented */
4656 case ANEG_STATE_NEXT_PAGE_WAIT:
4657 /* ??? unimplemented */
4668 static int fiber_autoneg(struct tg3 *tp, u32 *txflags, u32 *rxflags)
4671 struct tg3_fiber_aneginfo aninfo;
4672 int status = ANEG_FAILED;
4676 tw32_f(MAC_TX_AUTO_NEG, 0);
4678 tmp = tp->mac_mode & ~MAC_MODE_PORT_MODE_MASK;
4679 tw32_f(MAC_MODE, tmp | MAC_MODE_PORT_MODE_GMII);
4682 tw32_f(MAC_MODE, tp->mac_mode | MAC_MODE_SEND_CONFIGS);
4685 memset(&aninfo, 0, sizeof(aninfo));
4686 aninfo.flags |= MR_AN_ENABLE;
4687 aninfo.state = ANEG_STATE_UNKNOWN;
4688 aninfo.cur_time = 0;
4690 while (++tick < 195000) {
4691 status = tg3_fiber_aneg_smachine(tp, &aninfo);
4692 if (status == ANEG_DONE || status == ANEG_FAILED)
4698 tp->mac_mode &= ~MAC_MODE_SEND_CONFIGS;
4699 tw32_f(MAC_MODE, tp->mac_mode);
4702 *txflags = aninfo.txconfig;
4703 *rxflags = aninfo.flags;
4705 if (status == ANEG_DONE &&
4706 (aninfo.flags & (MR_AN_COMPLETE | MR_LINK_OK |
4707 MR_LP_ADV_FULL_DUPLEX)))
4713 static void tg3_init_bcm8002(struct tg3 *tp)
4715 u32 mac_status = tr32(MAC_STATUS);
4718 /* Reset when initting first time or we have a link. */
4719 if (tg3_flag(tp, INIT_COMPLETE) &&
4720 !(mac_status & MAC_STATUS_PCS_SYNCED))
4723 /* Set PLL lock range. */
4724 tg3_writephy(tp, 0x16, 0x8007);
4727 tg3_writephy(tp, MII_BMCR, BMCR_RESET);
4729 /* Wait for reset to complete. */
4730 /* XXX schedule_timeout() ... */
4731 for (i = 0; i < 500; i++)
4734 /* Config mode; select PMA/Ch 1 regs. */
4735 tg3_writephy(tp, 0x10, 0x8411);
4737 /* Enable auto-lock and comdet, select txclk for tx. */
4738 tg3_writephy(tp, 0x11, 0x0a10);
4740 tg3_writephy(tp, 0x18, 0x00a0);
4741 tg3_writephy(tp, 0x16, 0x41ff);
4743 /* Assert and deassert POR. */
4744 tg3_writephy(tp, 0x13, 0x0400);
4746 tg3_writephy(tp, 0x13, 0x0000);
4748 tg3_writephy(tp, 0x11, 0x0a50);
4750 tg3_writephy(tp, 0x11, 0x0a10);
4752 /* Wait for signal to stabilize */
4753 /* XXX schedule_timeout() ... */
4754 for (i = 0; i < 15000; i++)
4757 /* Deselect the channel register so we can read the PHYID
4760 tg3_writephy(tp, 0x10, 0x8011);
4763 static int tg3_setup_fiber_hw_autoneg(struct tg3 *tp, u32 mac_status)
4766 u32 sg_dig_ctrl, sg_dig_status;
4767 u32 serdes_cfg, expected_sg_dig_ctrl;
4768 int workaround, port_a;
4769 int current_link_up;
4772 expected_sg_dig_ctrl = 0;
4775 current_link_up = 0;
4777 if (tp->pci_chip_rev_id != CHIPREV_ID_5704_A0 &&
4778 tp->pci_chip_rev_id != CHIPREV_ID_5704_A1) {
4780 if (tr32(TG3PCI_DUAL_MAC_CTRL) & DUAL_MAC_CTRL_ID)
4783 /* preserve bits 0-11,13,14 for signal pre-emphasis */
4784 /* preserve bits 20-23 for voltage regulator */
4785 serdes_cfg = tr32(MAC_SERDES_CFG) & 0x00f06fff;
4788 sg_dig_ctrl = tr32(SG_DIG_CTRL);
4790 if (tp->link_config.autoneg != AUTONEG_ENABLE) {
4791 if (sg_dig_ctrl & SG_DIG_USING_HW_AUTONEG) {
4793 u32 val = serdes_cfg;
4799 tw32_f(MAC_SERDES_CFG, val);
4802 tw32_f(SG_DIG_CTRL, SG_DIG_COMMON_SETUP);
4804 if (mac_status & MAC_STATUS_PCS_SYNCED) {
4805 tg3_setup_flow_control(tp, 0, 0);
4806 current_link_up = 1;
4811 /* Want auto-negotiation. */
4812 expected_sg_dig_ctrl = SG_DIG_USING_HW_AUTONEG | SG_DIG_COMMON_SETUP;
4814 flowctrl = tg3_advert_flowctrl_1000X(tp->link_config.flowctrl);
4815 if (flowctrl & ADVERTISE_1000XPAUSE)
4816 expected_sg_dig_ctrl |= SG_DIG_PAUSE_CAP;
4817 if (flowctrl & ADVERTISE_1000XPSE_ASYM)
4818 expected_sg_dig_ctrl |= SG_DIG_ASYM_PAUSE;
4820 if (sg_dig_ctrl != expected_sg_dig_ctrl) {
4821 if ((tp->phy_flags & TG3_PHYFLG_PARALLEL_DETECT) &&
4822 tp->serdes_counter &&
4823 ((mac_status & (MAC_STATUS_PCS_SYNCED |
4824 MAC_STATUS_RCVD_CFG)) ==
4825 MAC_STATUS_PCS_SYNCED)) {
4826 tp->serdes_counter--;
4827 current_link_up = 1;
4832 tw32_f(MAC_SERDES_CFG, serdes_cfg | 0xc011000);
4833 tw32_f(SG_DIG_CTRL, expected_sg_dig_ctrl | SG_DIG_SOFT_RESET);
4835 tw32_f(SG_DIG_CTRL, expected_sg_dig_ctrl);
4837 tp->serdes_counter = SERDES_AN_TIMEOUT_5704S;
4838 tp->phy_flags &= ~TG3_PHYFLG_PARALLEL_DETECT;
4839 } else if (mac_status & (MAC_STATUS_PCS_SYNCED |
4840 MAC_STATUS_SIGNAL_DET)) {
4841 sg_dig_status = tr32(SG_DIG_STATUS);
4842 mac_status = tr32(MAC_STATUS);
4844 if ((sg_dig_status & SG_DIG_AUTONEG_COMPLETE) &&
4845 (mac_status & MAC_STATUS_PCS_SYNCED)) {
4846 u32 local_adv = 0, remote_adv = 0;
4848 if (sg_dig_ctrl & SG_DIG_PAUSE_CAP)
4849 local_adv |= ADVERTISE_1000XPAUSE;
4850 if (sg_dig_ctrl & SG_DIG_ASYM_PAUSE)
4851 local_adv |= ADVERTISE_1000XPSE_ASYM;
4853 if (sg_dig_status & SG_DIG_PARTNER_PAUSE_CAPABLE)
4854 remote_adv |= LPA_1000XPAUSE;
4855 if (sg_dig_status & SG_DIG_PARTNER_ASYM_PAUSE)
4856 remote_adv |= LPA_1000XPAUSE_ASYM;
4858 tp->link_config.rmt_adv =
4859 mii_adv_to_ethtool_adv_x(remote_adv);
4861 tg3_setup_flow_control(tp, local_adv, remote_adv);
4862 current_link_up = 1;
4863 tp->serdes_counter = 0;
4864 tp->phy_flags &= ~TG3_PHYFLG_PARALLEL_DETECT;
4865 } else if (!(sg_dig_status & SG_DIG_AUTONEG_COMPLETE)) {
4866 if (tp->serdes_counter)
4867 tp->serdes_counter--;
4870 u32 val = serdes_cfg;
4877 tw32_f(MAC_SERDES_CFG, val);
4880 tw32_f(SG_DIG_CTRL, SG_DIG_COMMON_SETUP);
4883 /* Link parallel detection - link is up */
4884 /* only if we have PCS_SYNC and not */
4885 /* receiving config code words */
4886 mac_status = tr32(MAC_STATUS);
4887 if ((mac_status & MAC_STATUS_PCS_SYNCED) &&
4888 !(mac_status & MAC_STATUS_RCVD_CFG)) {
4889 tg3_setup_flow_control(tp, 0, 0);
4890 current_link_up = 1;
4892 TG3_PHYFLG_PARALLEL_DETECT;
4893 tp->serdes_counter =
4894 SERDES_PARALLEL_DET_TIMEOUT;
4896 goto restart_autoneg;
4900 tp->serdes_counter = SERDES_AN_TIMEOUT_5704S;
4901 tp->phy_flags &= ~TG3_PHYFLG_PARALLEL_DETECT;
4905 return current_link_up;
4908 static int tg3_setup_fiber_by_hand(struct tg3 *tp, u32 mac_status)
4910 int current_link_up = 0;
4912 if (!(mac_status & MAC_STATUS_PCS_SYNCED))
4915 if (tp->link_config.autoneg == AUTONEG_ENABLE) {
4916 u32 txflags, rxflags;
4919 if (fiber_autoneg(tp, &txflags, &rxflags)) {
4920 u32 local_adv = 0, remote_adv = 0;
4922 if (txflags & ANEG_CFG_PS1)
4923 local_adv |= ADVERTISE_1000XPAUSE;
4924 if (txflags & ANEG_CFG_PS2)
4925 local_adv |= ADVERTISE_1000XPSE_ASYM;
4927 if (rxflags & MR_LP_ADV_SYM_PAUSE)
4928 remote_adv |= LPA_1000XPAUSE;
4929 if (rxflags & MR_LP_ADV_ASYM_PAUSE)
4930 remote_adv |= LPA_1000XPAUSE_ASYM;
4932 tp->link_config.rmt_adv =
4933 mii_adv_to_ethtool_adv_x(remote_adv);
4935 tg3_setup_flow_control(tp, local_adv, remote_adv);
4937 current_link_up = 1;
4939 for (i = 0; i < 30; i++) {
4942 (MAC_STATUS_SYNC_CHANGED |
4943 MAC_STATUS_CFG_CHANGED));
4945 if ((tr32(MAC_STATUS) &
4946 (MAC_STATUS_SYNC_CHANGED |
4947 MAC_STATUS_CFG_CHANGED)) == 0)
4951 mac_status = tr32(MAC_STATUS);
4952 if (current_link_up == 0 &&
4953 (mac_status & MAC_STATUS_PCS_SYNCED) &&
4954 !(mac_status & MAC_STATUS_RCVD_CFG))
4955 current_link_up = 1;
4957 tg3_setup_flow_control(tp, 0, 0);
4959 /* Forcing 1000FD link up. */
4960 current_link_up = 1;
4962 tw32_f(MAC_MODE, (tp->mac_mode | MAC_MODE_SEND_CONFIGS));
4965 tw32_f(MAC_MODE, tp->mac_mode);
4970 return current_link_up;
4973 static int tg3_setup_fiber_phy(struct tg3 *tp, int force_reset)
4976 u16 orig_active_speed;
4977 u8 orig_active_duplex;
4979 int current_link_up;
4982 orig_pause_cfg = tp->link_config.active_flowctrl;
4983 orig_active_speed = tp->link_config.active_speed;
4984 orig_active_duplex = tp->link_config.active_duplex;
4986 if (!tg3_flag(tp, HW_AUTONEG) &&
4987 netif_carrier_ok(tp->dev) &&
4988 tg3_flag(tp, INIT_COMPLETE)) {
4989 mac_status = tr32(MAC_STATUS);
4990 mac_status &= (MAC_STATUS_PCS_SYNCED |
4991 MAC_STATUS_SIGNAL_DET |
4992 MAC_STATUS_CFG_CHANGED |
4993 MAC_STATUS_RCVD_CFG);
4994 if (mac_status == (MAC_STATUS_PCS_SYNCED |
4995 MAC_STATUS_SIGNAL_DET)) {
4996 tw32_f(MAC_STATUS, (MAC_STATUS_SYNC_CHANGED |
4997 MAC_STATUS_CFG_CHANGED));
5002 tw32_f(MAC_TX_AUTO_NEG, 0);
5004 tp->mac_mode &= ~(MAC_MODE_PORT_MODE_MASK | MAC_MODE_HALF_DUPLEX);
5005 tp->mac_mode |= MAC_MODE_PORT_MODE_TBI;
5006 tw32_f(MAC_MODE, tp->mac_mode);
5009 if (tp->phy_id == TG3_PHY_ID_BCM8002)
5010 tg3_init_bcm8002(tp);
5012 /* Enable link change event even when serdes polling. */
5013 tw32_f(MAC_EVENT, MAC_EVENT_LNKSTATE_CHANGED);
5016 current_link_up = 0;
5017 tp->link_config.rmt_adv = 0;
5018 mac_status = tr32(MAC_STATUS);
5020 if (tg3_flag(tp, HW_AUTONEG))
5021 current_link_up = tg3_setup_fiber_hw_autoneg(tp, mac_status);
5023 current_link_up = tg3_setup_fiber_by_hand(tp, mac_status);
5025 tp->napi[0].hw_status->status =
5026 (SD_STATUS_UPDATED |
5027 (tp->napi[0].hw_status->status & ~SD_STATUS_LINK_CHG));
5029 for (i = 0; i < 100; i++) {
5030 tw32_f(MAC_STATUS, (MAC_STATUS_SYNC_CHANGED |
5031 MAC_STATUS_CFG_CHANGED));
5033 if ((tr32(MAC_STATUS) & (MAC_STATUS_SYNC_CHANGED |
5034 MAC_STATUS_CFG_CHANGED |
5035 MAC_STATUS_LNKSTATE_CHANGED)) == 0)
5039 mac_status = tr32(MAC_STATUS);
5040 if ((mac_status & MAC_STATUS_PCS_SYNCED) == 0) {
5041 current_link_up = 0;
5042 if (tp->link_config.autoneg == AUTONEG_ENABLE &&
5043 tp->serdes_counter == 0) {
5044 tw32_f(MAC_MODE, (tp->mac_mode |
5045 MAC_MODE_SEND_CONFIGS));
5047 tw32_f(MAC_MODE, tp->mac_mode);
5051 if (current_link_up == 1) {
5052 tp->link_config.active_speed = SPEED_1000;
5053 tp->link_config.active_duplex = DUPLEX_FULL;
5054 tw32(MAC_LED_CTRL, (tp->led_ctrl |
5055 LED_CTRL_LNKLED_OVERRIDE |
5056 LED_CTRL_1000MBPS_ON));
5058 tp->link_config.active_speed = SPEED_INVALID;
5059 tp->link_config.active_duplex = DUPLEX_INVALID;
5060 tw32(MAC_LED_CTRL, (tp->led_ctrl |
5061 LED_CTRL_LNKLED_OVERRIDE |
5062 LED_CTRL_TRAFFIC_OVERRIDE));
5065 if (current_link_up != netif_carrier_ok(tp->dev)) {
5066 if (current_link_up)
5067 netif_carrier_on(tp->dev);
5069 netif_carrier_off(tp->dev);
5070 tg3_link_report(tp);
5072 u32 now_pause_cfg = tp->link_config.active_flowctrl;
5073 if (orig_pause_cfg != now_pause_cfg ||
5074 orig_active_speed != tp->link_config.active_speed ||
5075 orig_active_duplex != tp->link_config.active_duplex)
5076 tg3_link_report(tp);
5082 static int tg3_setup_fiber_mii_phy(struct tg3 *tp, int force_reset)
5084 int current_link_up, err = 0;
5088 u32 local_adv, remote_adv;
5090 tp->mac_mode |= MAC_MODE_PORT_MODE_GMII;
5091 tw32_f(MAC_MODE, tp->mac_mode);
5097 (MAC_STATUS_SYNC_CHANGED |
5098 MAC_STATUS_CFG_CHANGED |
5099 MAC_STATUS_MI_COMPLETION |
5100 MAC_STATUS_LNKSTATE_CHANGED));
5106 current_link_up = 0;
5107 current_speed = SPEED_INVALID;
5108 current_duplex = DUPLEX_INVALID;
5109 tp->link_config.rmt_adv = 0;
5111 err |= tg3_readphy(tp, MII_BMSR, &bmsr);
5112 err |= tg3_readphy(tp, MII_BMSR, &bmsr);
5113 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5714) {
5114 if (tr32(MAC_TX_STATUS) & TX_STATUS_LINK_UP)
5115 bmsr |= BMSR_LSTATUS;
5117 bmsr &= ~BMSR_LSTATUS;
5120 err |= tg3_readphy(tp, MII_BMCR, &bmcr);
5122 if ((tp->link_config.autoneg == AUTONEG_ENABLE) && !force_reset &&
5123 (tp->phy_flags & TG3_PHYFLG_PARALLEL_DETECT)) {
5124 /* do nothing, just check for link up at the end */
5125 } else if (tp->link_config.autoneg == AUTONEG_ENABLE) {
5128 err |= tg3_readphy(tp, MII_ADVERTISE, &adv);
5129 newadv = adv & ~(ADVERTISE_1000XFULL | ADVERTISE_1000XHALF |
5130 ADVERTISE_1000XPAUSE |
5131 ADVERTISE_1000XPSE_ASYM |
5134 newadv |= tg3_advert_flowctrl_1000X(tp->link_config.flowctrl);
5135 newadv |= ethtool_adv_to_mii_adv_x(tp->link_config.advertising);
5137 if ((newadv != adv) || !(bmcr & BMCR_ANENABLE)) {
5138 tg3_writephy(tp, MII_ADVERTISE, newadv);
5139 bmcr |= BMCR_ANENABLE | BMCR_ANRESTART;
5140 tg3_writephy(tp, MII_BMCR, bmcr);
5142 tw32_f(MAC_EVENT, MAC_EVENT_LNKSTATE_CHANGED);
5143 tp->serdes_counter = SERDES_AN_TIMEOUT_5714S;
5144 tp->phy_flags &= ~TG3_PHYFLG_PARALLEL_DETECT;
5151 bmcr &= ~BMCR_SPEED1000;
5152 new_bmcr = bmcr & ~(BMCR_ANENABLE | BMCR_FULLDPLX);
5154 if (tp->link_config.duplex == DUPLEX_FULL)
5155 new_bmcr |= BMCR_FULLDPLX;
5157 if (new_bmcr != bmcr) {
5158 /* BMCR_SPEED1000 is a reserved bit that needs
5159 * to be set on write.
5161 new_bmcr |= BMCR_SPEED1000;
5163 /* Force a linkdown */
5164 if (netif_carrier_ok(tp->dev)) {
5167 err |= tg3_readphy(tp, MII_ADVERTISE, &adv);
5168 adv &= ~(ADVERTISE_1000XFULL |
5169 ADVERTISE_1000XHALF |
5171 tg3_writephy(tp, MII_ADVERTISE, adv);
5172 tg3_writephy(tp, MII_BMCR, bmcr |
5176 netif_carrier_off(tp->dev);
5178 tg3_writephy(tp, MII_BMCR, new_bmcr);
5180 err |= tg3_readphy(tp, MII_BMSR, &bmsr);
5181 err |= tg3_readphy(tp, MII_BMSR, &bmsr);
5182 if (GET_ASIC_REV(tp->pci_chip_rev_id) ==
5184 if (tr32(MAC_TX_STATUS) & TX_STATUS_LINK_UP)
5185 bmsr |= BMSR_LSTATUS;
5187 bmsr &= ~BMSR_LSTATUS;
5189 tp->phy_flags &= ~TG3_PHYFLG_PARALLEL_DETECT;
5193 if (bmsr & BMSR_LSTATUS) {
5194 current_speed = SPEED_1000;
5195 current_link_up = 1;
5196 if (bmcr & BMCR_FULLDPLX)
5197 current_duplex = DUPLEX_FULL;
5199 current_duplex = DUPLEX_HALF;
5204 if (bmcr & BMCR_ANENABLE) {
5207 err |= tg3_readphy(tp, MII_ADVERTISE, &local_adv);
5208 err |= tg3_readphy(tp, MII_LPA, &remote_adv);
5209 common = local_adv & remote_adv;
5210 if (common & (ADVERTISE_1000XHALF |
5211 ADVERTISE_1000XFULL)) {
5212 if (common & ADVERTISE_1000XFULL)
5213 current_duplex = DUPLEX_FULL;
5215 current_duplex = DUPLEX_HALF;
5217 tp->link_config.rmt_adv =
5218 mii_adv_to_ethtool_adv_x(remote_adv);
5219 } else if (!tg3_flag(tp, 5780_CLASS)) {
5220 /* Link is up via parallel detect */
5222 current_link_up = 0;
5227 if (current_link_up == 1 && current_duplex == DUPLEX_FULL)
5228 tg3_setup_flow_control(tp, local_adv, remote_adv);
5230 tp->mac_mode &= ~MAC_MODE_HALF_DUPLEX;
5231 if (tp->link_config.active_duplex == DUPLEX_HALF)
5232 tp->mac_mode |= MAC_MODE_HALF_DUPLEX;
5234 tw32_f(MAC_MODE, tp->mac_mode);
5237 tw32_f(MAC_EVENT, MAC_EVENT_LNKSTATE_CHANGED);
5239 tp->link_config.active_speed = current_speed;
5240 tp->link_config.active_duplex = current_duplex;
5242 if (current_link_up != netif_carrier_ok(tp->dev)) {
5243 if (current_link_up)
5244 netif_carrier_on(tp->dev);
5246 netif_carrier_off(tp->dev);
5247 tp->phy_flags &= ~TG3_PHYFLG_PARALLEL_DETECT;
5249 tg3_link_report(tp);
5254 static void tg3_serdes_parallel_detect(struct tg3 *tp)
5256 if (tp->serdes_counter) {
5257 /* Give autoneg time to complete. */
5258 tp->serdes_counter--;
5262 if (!netif_carrier_ok(tp->dev) &&
5263 (tp->link_config.autoneg == AUTONEG_ENABLE)) {
5266 tg3_readphy(tp, MII_BMCR, &bmcr);
5267 if (bmcr & BMCR_ANENABLE) {
5270 /* Select shadow register 0x1f */
5271 tg3_writephy(tp, MII_TG3_MISC_SHDW, 0x7c00);
5272 tg3_readphy(tp, MII_TG3_MISC_SHDW, &phy1);
5274 /* Select expansion interrupt status register */
5275 tg3_writephy(tp, MII_TG3_DSP_ADDRESS,
5276 MII_TG3_DSP_EXP1_INT_STAT);
5277 tg3_readphy(tp, MII_TG3_DSP_RW_PORT, &phy2);
5278 tg3_readphy(tp, MII_TG3_DSP_RW_PORT, &phy2);
5280 if ((phy1 & 0x10) && !(phy2 & 0x20)) {
5281 /* We have signal detect and not receiving
5282 * config code words, link is up by parallel
5286 bmcr &= ~BMCR_ANENABLE;
5287 bmcr |= BMCR_SPEED1000 | BMCR_FULLDPLX;
5288 tg3_writephy(tp, MII_BMCR, bmcr);
5289 tp->phy_flags |= TG3_PHYFLG_PARALLEL_DETECT;
5292 } else if (netif_carrier_ok(tp->dev) &&
5293 (tp->link_config.autoneg == AUTONEG_ENABLE) &&
5294 (tp->phy_flags & TG3_PHYFLG_PARALLEL_DETECT)) {
5297 /* Select expansion interrupt status register */
5298 tg3_writephy(tp, MII_TG3_DSP_ADDRESS,
5299 MII_TG3_DSP_EXP1_INT_STAT);
5300 tg3_readphy(tp, MII_TG3_DSP_RW_PORT, &phy2);
5304 /* Config code words received, turn on autoneg. */
5305 tg3_readphy(tp, MII_BMCR, &bmcr);
5306 tg3_writephy(tp, MII_BMCR, bmcr | BMCR_ANENABLE);
5308 tp->phy_flags &= ~TG3_PHYFLG_PARALLEL_DETECT;
5314 static int tg3_setup_phy(struct tg3 *tp, int force_reset)
5319 if (tp->phy_flags & TG3_PHYFLG_PHY_SERDES)
5320 err = tg3_setup_fiber_phy(tp, force_reset);
5321 else if (tp->phy_flags & TG3_PHYFLG_MII_SERDES)
5322 err = tg3_setup_fiber_mii_phy(tp, force_reset);
5324 err = tg3_setup_copper_phy(tp, force_reset);
5326 if (GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5784_AX) {
5329 val = tr32(TG3_CPMU_CLCK_STAT) & CPMU_CLCK_STAT_MAC_CLCK_MASK;
5330 if (val == CPMU_CLCK_STAT_MAC_CLCK_62_5)
5332 else if (val == CPMU_CLCK_STAT_MAC_CLCK_6_25)
5337 val = tr32(GRC_MISC_CFG) & ~GRC_MISC_CFG_PRESCALAR_MASK;
5338 val |= (scale << GRC_MISC_CFG_PRESCALAR_SHIFT);
5339 tw32(GRC_MISC_CFG, val);
5342 val = (2 << TX_LENGTHS_IPG_CRS_SHIFT) |
5343 (6 << TX_LENGTHS_IPG_SHIFT);
5344 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5720)
5345 val |= tr32(MAC_TX_LENGTHS) &
5346 (TX_LENGTHS_JMB_FRM_LEN_MSK |
5347 TX_LENGTHS_CNT_DWN_VAL_MSK);
5349 if (tp->link_config.active_speed == SPEED_1000 &&
5350 tp->link_config.active_duplex == DUPLEX_HALF)
5351 tw32(MAC_TX_LENGTHS, val |
5352 (0xff << TX_LENGTHS_SLOT_TIME_SHIFT));
5354 tw32(MAC_TX_LENGTHS, val |
5355 (32 << TX_LENGTHS_SLOT_TIME_SHIFT));
5357 if (!tg3_flag(tp, 5705_PLUS)) {
5358 if (netif_carrier_ok(tp->dev)) {
5359 tw32(HOSTCC_STAT_COAL_TICKS,
5360 tp->coal.stats_block_coalesce_usecs);
5362 tw32(HOSTCC_STAT_COAL_TICKS, 0);
5366 if (tg3_flag(tp, ASPM_WORKAROUND)) {
5367 val = tr32(PCIE_PWR_MGMT_THRESH);
5368 if (!netif_carrier_ok(tp->dev))
5369 val = (val & ~PCIE_PWR_MGMT_L1_THRESH_MSK) |
5372 val |= PCIE_PWR_MGMT_L1_THRESH_MSK;
5373 tw32(PCIE_PWR_MGMT_THRESH, val);
5379 static inline int tg3_irq_sync(struct tg3 *tp)
5381 return tp->irq_sync;
5384 static inline void tg3_rd32_loop(struct tg3 *tp, u32 *dst, u32 off, u32 len)
5388 dst = (u32 *)((u8 *)dst + off);
5389 for (i = 0; i < len; i += sizeof(u32))
5390 *dst++ = tr32(off + i);
5393 static void tg3_dump_legacy_regs(struct tg3 *tp, u32 *regs)
5395 tg3_rd32_loop(tp, regs, TG3PCI_VENDOR, 0xb0);
5396 tg3_rd32_loop(tp, regs, MAILBOX_INTERRUPT_0, 0x200);
5397 tg3_rd32_loop(tp, regs, MAC_MODE, 0x4f0);
5398 tg3_rd32_loop(tp, regs, SNDDATAI_MODE, 0xe0);
5399 tg3_rd32_loop(tp, regs, SNDDATAC_MODE, 0x04);
5400 tg3_rd32_loop(tp, regs, SNDBDS_MODE, 0x80);
5401 tg3_rd32_loop(tp, regs, SNDBDI_MODE, 0x48);
5402 tg3_rd32_loop(tp, regs, SNDBDC_MODE, 0x04);
5403 tg3_rd32_loop(tp, regs, RCVLPC_MODE, 0x20);
5404 tg3_rd32_loop(tp, regs, RCVLPC_SELLST_BASE, 0x15c);
5405 tg3_rd32_loop(tp, regs, RCVDBDI_MODE, 0x0c);
5406 tg3_rd32_loop(tp, regs, RCVDBDI_JUMBO_BD, 0x3c);
5407 tg3_rd32_loop(tp, regs, RCVDBDI_BD_PROD_IDX_0, 0x44);
5408 tg3_rd32_loop(tp, regs, RCVDCC_MODE, 0x04);
5409 tg3_rd32_loop(tp, regs, RCVBDI_MODE, 0x20);
5410 tg3_rd32_loop(tp, regs, RCVCC_MODE, 0x14);
5411 tg3_rd32_loop(tp, regs, RCVLSC_MODE, 0x08);
5412 tg3_rd32_loop(tp, regs, MBFREE_MODE, 0x08);
5413 tg3_rd32_loop(tp, regs, HOSTCC_MODE, 0x100);
5415 if (tg3_flag(tp, SUPPORT_MSIX))
5416 tg3_rd32_loop(tp, regs, HOSTCC_RXCOL_TICKS_VEC1, 0x180);
5418 tg3_rd32_loop(tp, regs, MEMARB_MODE, 0x10);
5419 tg3_rd32_loop(tp, regs, BUFMGR_MODE, 0x58);
5420 tg3_rd32_loop(tp, regs, RDMAC_MODE, 0x08);
5421 tg3_rd32_loop(tp, regs, WDMAC_MODE, 0x08);
5422 tg3_rd32_loop(tp, regs, RX_CPU_MODE, 0x04);
5423 tg3_rd32_loop(tp, regs, RX_CPU_STATE, 0x04);
5424 tg3_rd32_loop(tp, regs, RX_CPU_PGMCTR, 0x04);
5425 tg3_rd32_loop(tp, regs, RX_CPU_HWBKPT, 0x04);
5427 if (!tg3_flag(tp, 5705_PLUS)) {
5428 tg3_rd32_loop(tp, regs, TX_CPU_MODE, 0x04);
5429 tg3_rd32_loop(tp, regs, TX_CPU_STATE, 0x04);
5430 tg3_rd32_loop(tp, regs, TX_CPU_PGMCTR, 0x04);
5433 tg3_rd32_loop(tp, regs, GRCMBOX_INTERRUPT_0, 0x110);
5434 tg3_rd32_loop(tp, regs, FTQ_RESET, 0x120);
5435 tg3_rd32_loop(tp, regs, MSGINT_MODE, 0x0c);
5436 tg3_rd32_loop(tp, regs, DMAC_MODE, 0x04);
5437 tg3_rd32_loop(tp, regs, GRC_MODE, 0x4c);
5439 if (tg3_flag(tp, NVRAM))
5440 tg3_rd32_loop(tp, regs, NVRAM_CMD, 0x24);
5443 static void tg3_dump_state(struct tg3 *tp)
5448 regs = kzalloc(TG3_REG_BLK_SIZE, GFP_ATOMIC);
5450 netdev_err(tp->dev, "Failed allocating register dump buffer\n");
5454 if (tg3_flag(tp, PCI_EXPRESS)) {
5455 /* Read up to but not including private PCI registers */
5456 for (i = 0; i < TG3_PCIE_TLDLPL_PORT; i += sizeof(u32))
5457 regs[i / sizeof(u32)] = tr32(i);
5459 tg3_dump_legacy_regs(tp, regs);
5461 for (i = 0; i < TG3_REG_BLK_SIZE / sizeof(u32); i += 4) {
5462 if (!regs[i + 0] && !regs[i + 1] &&
5463 !regs[i + 2] && !regs[i + 3])
5466 netdev_err(tp->dev, "0x%08x: 0x%08x, 0x%08x, 0x%08x, 0x%08x\n",
5468 regs[i + 0], regs[i + 1], regs[i + 2], regs[i + 3]);
5473 for (i = 0; i < tp->irq_cnt; i++) {
5474 struct tg3_napi *tnapi = &tp->napi[i];
5476 /* SW status block */
5478 "%d: Host status block [%08x:%08x:(%04x:%04x:%04x):(%04x:%04x)]\n",
5480 tnapi->hw_status->status,
5481 tnapi->hw_status->status_tag,
5482 tnapi->hw_status->rx_jumbo_consumer,
5483 tnapi->hw_status->rx_consumer,
5484 tnapi->hw_status->rx_mini_consumer,
5485 tnapi->hw_status->idx[0].rx_producer,
5486 tnapi->hw_status->idx[0].tx_consumer);
5489 "%d: NAPI info [%08x:%08x:(%04x:%04x:%04x):%04x:(%04x:%04x:%04x:%04x)]\n",
5491 tnapi->last_tag, tnapi->last_irq_tag,
5492 tnapi->tx_prod, tnapi->tx_cons, tnapi->tx_pending,
5494 tnapi->prodring.rx_std_prod_idx,
5495 tnapi->prodring.rx_std_cons_idx,
5496 tnapi->prodring.rx_jmb_prod_idx,
5497 tnapi->prodring.rx_jmb_cons_idx);
5501 /* This is called whenever we suspect that the system chipset is re-
5502 * ordering the sequence of MMIO to the tx send mailbox. The symptom
5503 * is bogus tx completions. We try to recover by setting the
5504 * TG3_FLAG_MBOX_WRITE_REORDER flag and resetting the chip later
5507 static void tg3_tx_recover(struct tg3 *tp)
5509 BUG_ON(tg3_flag(tp, MBOX_WRITE_REORDER) ||
5510 tp->write32_tx_mbox == tg3_write_indirect_mbox);
5512 netdev_warn(tp->dev,
5513 "The system may be re-ordering memory-mapped I/O "
5514 "cycles to the network device, attempting to recover. "
5515 "Please report the problem to the driver maintainer "
5516 "and include system chipset information.\n");
5518 spin_lock(&tp->lock);
5519 tg3_flag_set(tp, TX_RECOVERY_PENDING);
5520 spin_unlock(&tp->lock);
5523 static inline u32 tg3_tx_avail(struct tg3_napi *tnapi)
5525 /* Tell compiler to fetch tx indices from memory. */
5527 return tnapi->tx_pending -
5528 ((tnapi->tx_prod - tnapi->tx_cons) & (TG3_TX_RING_SIZE - 1));
5531 /* Tigon3 never reports partial packet sends. So we do not
5532 * need special logic to handle SKBs that have not had all
5533 * of their frags sent yet, like SunGEM does.
5535 static void tg3_tx(struct tg3_napi *tnapi)
5537 struct tg3 *tp = tnapi->tp;
5538 u32 hw_idx = tnapi->hw_status->idx[0].tx_consumer;
5539 u32 sw_idx = tnapi->tx_cons;
5540 struct netdev_queue *txq;
5541 int index = tnapi - tp->napi;
5542 unsigned int pkts_compl = 0, bytes_compl = 0;
5544 if (tg3_flag(tp, ENABLE_TSS))
5547 txq = netdev_get_tx_queue(tp->dev, index);
5549 while (sw_idx != hw_idx) {
5550 struct tg3_tx_ring_info *ri = &tnapi->tx_buffers[sw_idx];
5551 struct sk_buff *skb = ri->skb;
5554 if (unlikely(skb == NULL)) {
5559 pci_unmap_single(tp->pdev,
5560 dma_unmap_addr(ri, mapping),
5566 while (ri->fragmented) {
5567 ri->fragmented = false;
5568 sw_idx = NEXT_TX(sw_idx);
5569 ri = &tnapi->tx_buffers[sw_idx];
5572 sw_idx = NEXT_TX(sw_idx);
5574 for (i = 0; i < skb_shinfo(skb)->nr_frags; i++) {
5575 ri = &tnapi->tx_buffers[sw_idx];
5576 if (unlikely(ri->skb != NULL || sw_idx == hw_idx))
5579 pci_unmap_page(tp->pdev,
5580 dma_unmap_addr(ri, mapping),
5581 skb_frag_size(&skb_shinfo(skb)->frags[i]),
5584 while (ri->fragmented) {
5585 ri->fragmented = false;
5586 sw_idx = NEXT_TX(sw_idx);
5587 ri = &tnapi->tx_buffers[sw_idx];
5590 sw_idx = NEXT_TX(sw_idx);
5594 bytes_compl += skb->len;
5598 if (unlikely(tx_bug)) {
5604 netdev_completed_queue(tp->dev, pkts_compl, bytes_compl);
5606 tnapi->tx_cons = sw_idx;
5608 /* Need to make the tx_cons update visible to tg3_start_xmit()
5609 * before checking for netif_queue_stopped(). Without the
5610 * memory barrier, there is a small possibility that tg3_start_xmit()
5611 * will miss it and cause the queue to be stopped forever.
5615 if (unlikely(netif_tx_queue_stopped(txq) &&
5616 (tg3_tx_avail(tnapi) > TG3_TX_WAKEUP_THRESH(tnapi)))) {
5617 __netif_tx_lock(txq, smp_processor_id());
5618 if (netif_tx_queue_stopped(txq) &&
5619 (tg3_tx_avail(tnapi) > TG3_TX_WAKEUP_THRESH(tnapi)))
5620 netif_tx_wake_queue(txq);
5621 __netif_tx_unlock(txq);
5625 static void tg3_rx_data_free(struct tg3 *tp, struct ring_info *ri, u32 map_sz)
5630 pci_unmap_single(tp->pdev, dma_unmap_addr(ri, mapping),
5631 map_sz, PCI_DMA_FROMDEVICE);
5636 /* Returns size of skb allocated or < 0 on error.
5638 * We only need to fill in the address because the other members
5639 * of the RX descriptor are invariant, see tg3_init_rings.
5641 * Note the purposeful assymetry of cpu vs. chip accesses. For
5642 * posting buffers we only dirty the first cache line of the RX
5643 * descriptor (containing the address). Whereas for the RX status
5644 * buffers the cpu only reads the last cacheline of the RX descriptor
5645 * (to fetch the error flags, vlan tag, checksum, and opaque cookie).
5647 static int tg3_alloc_rx_data(struct tg3 *tp, struct tg3_rx_prodring_set *tpr,
5648 u32 opaque_key, u32 dest_idx_unmasked)
5650 struct tg3_rx_buffer_desc *desc;
5651 struct ring_info *map;
5654 int skb_size, data_size, dest_idx;
5656 switch (opaque_key) {
5657 case RXD_OPAQUE_RING_STD:
5658 dest_idx = dest_idx_unmasked & tp->rx_std_ring_mask;
5659 desc = &tpr->rx_std[dest_idx];
5660 map = &tpr->rx_std_buffers[dest_idx];
5661 data_size = tp->rx_pkt_map_sz;
5664 case RXD_OPAQUE_RING_JUMBO:
5665 dest_idx = dest_idx_unmasked & tp->rx_jmb_ring_mask;
5666 desc = &tpr->rx_jmb[dest_idx].std;
5667 map = &tpr->rx_jmb_buffers[dest_idx];
5668 data_size = TG3_RX_JMB_MAP_SZ;
5675 /* Do not overwrite any of the map or rp information
5676 * until we are sure we can commit to a new buffer.
5678 * Callers depend upon this behavior and assume that
5679 * we leave everything unchanged if we fail.
5681 skb_size = SKB_DATA_ALIGN(data_size + TG3_RX_OFFSET(tp)) +
5682 SKB_DATA_ALIGN(sizeof(struct skb_shared_info));
5683 data = kmalloc(skb_size, GFP_ATOMIC);
5687 mapping = pci_map_single(tp->pdev,
5688 data + TG3_RX_OFFSET(tp),
5690 PCI_DMA_FROMDEVICE);
5691 if (pci_dma_mapping_error(tp->pdev, mapping)) {
5697 dma_unmap_addr_set(map, mapping, mapping);
5699 desc->addr_hi = ((u64)mapping >> 32);
5700 desc->addr_lo = ((u64)mapping & 0xffffffff);
5705 /* We only need to move over in the address because the other
5706 * members of the RX descriptor are invariant. See notes above
5707 * tg3_alloc_rx_data for full details.
5709 static void tg3_recycle_rx(struct tg3_napi *tnapi,
5710 struct tg3_rx_prodring_set *dpr,
5711 u32 opaque_key, int src_idx,
5712 u32 dest_idx_unmasked)
5714 struct tg3 *tp = tnapi->tp;
5715 struct tg3_rx_buffer_desc *src_desc, *dest_desc;
5716 struct ring_info *src_map, *dest_map;
5717 struct tg3_rx_prodring_set *spr = &tp->napi[0].prodring;
5720 switch (opaque_key) {
5721 case RXD_OPAQUE_RING_STD:
5722 dest_idx = dest_idx_unmasked & tp->rx_std_ring_mask;
5723 dest_desc = &dpr->rx_std[dest_idx];
5724 dest_map = &dpr->rx_std_buffers[dest_idx];
5725 src_desc = &spr->rx_std[src_idx];
5726 src_map = &spr->rx_std_buffers[src_idx];
5729 case RXD_OPAQUE_RING_JUMBO:
5730 dest_idx = dest_idx_unmasked & tp->rx_jmb_ring_mask;
5731 dest_desc = &dpr->rx_jmb[dest_idx].std;
5732 dest_map = &dpr->rx_jmb_buffers[dest_idx];
5733 src_desc = &spr->rx_jmb[src_idx].std;
5734 src_map = &spr->rx_jmb_buffers[src_idx];
5741 dest_map->data = src_map->data;
5742 dma_unmap_addr_set(dest_map, mapping,
5743 dma_unmap_addr(src_map, mapping));
5744 dest_desc->addr_hi = src_desc->addr_hi;
5745 dest_desc->addr_lo = src_desc->addr_lo;
5747 /* Ensure that the update to the skb happens after the physical
5748 * addresses have been transferred to the new BD location.
5752 src_map->data = NULL;
5755 /* The RX ring scheme is composed of multiple rings which post fresh
5756 * buffers to the chip, and one special ring the chip uses to report
5757 * status back to the host.
5759 * The special ring reports the status of received packets to the
5760 * host. The chip does not write into the original descriptor the
5761 * RX buffer was obtained from. The chip simply takes the original
5762 * descriptor as provided by the host, updates the status and length
5763 * field, then writes this into the next status ring entry.
5765 * Each ring the host uses to post buffers to the chip is described
5766 * by a TG3_BDINFO entry in the chips SRAM area. When a packet arrives,
5767 * it is first placed into the on-chip ram. When the packet's length
5768 * is known, it walks down the TG3_BDINFO entries to select the ring.
5769 * Each TG3_BDINFO specifies a MAXLEN field and the first TG3_BDINFO
5770 * which is within the range of the new packet's length is chosen.
5772 * The "separate ring for rx status" scheme may sound queer, but it makes
5773 * sense from a cache coherency perspective. If only the host writes
5774 * to the buffer post rings, and only the chip writes to the rx status
5775 * rings, then cache lines never move beyond shared-modified state.
5776 * If both the host and chip were to write into the same ring, cache line
5777 * eviction could occur since both entities want it in an exclusive state.
5779 static int tg3_rx(struct tg3_napi *tnapi, int budget)
5781 struct tg3 *tp = tnapi->tp;
5782 u32 work_mask, rx_std_posted = 0;
5783 u32 std_prod_idx, jmb_prod_idx;
5784 u32 sw_idx = tnapi->rx_rcb_ptr;
5787 struct tg3_rx_prodring_set *tpr = &tnapi->prodring;
5789 hw_idx = *(tnapi->rx_rcb_prod_idx);
5791 * We need to order the read of hw_idx and the read of
5792 * the opaque cookie.
5797 std_prod_idx = tpr->rx_std_prod_idx;
5798 jmb_prod_idx = tpr->rx_jmb_prod_idx;
5799 while (sw_idx != hw_idx && budget > 0) {
5800 struct ring_info *ri;
5801 struct tg3_rx_buffer_desc *desc = &tnapi->rx_rcb[sw_idx];
5803 struct sk_buff *skb;
5804 dma_addr_t dma_addr;
5805 u32 opaque_key, desc_idx, *post_ptr;
5808 desc_idx = desc->opaque & RXD_OPAQUE_INDEX_MASK;
5809 opaque_key = desc->opaque & RXD_OPAQUE_RING_MASK;
5810 if (opaque_key == RXD_OPAQUE_RING_STD) {
5811 ri = &tp->napi[0].prodring.rx_std_buffers[desc_idx];
5812 dma_addr = dma_unmap_addr(ri, mapping);
5814 post_ptr = &std_prod_idx;
5816 } else if (opaque_key == RXD_OPAQUE_RING_JUMBO) {
5817 ri = &tp->napi[0].prodring.rx_jmb_buffers[desc_idx];
5818 dma_addr = dma_unmap_addr(ri, mapping);
5820 post_ptr = &jmb_prod_idx;
5822 goto next_pkt_nopost;
5824 work_mask |= opaque_key;
5826 if ((desc->err_vlan & RXD_ERR_MASK) != 0 &&
5827 (desc->err_vlan != RXD_ERR_ODD_NIBBLE_RCVD_MII)) {
5829 tg3_recycle_rx(tnapi, tpr, opaque_key,
5830 desc_idx, *post_ptr);
5832 /* Other statistics kept track of by card. */
5837 prefetch(data + TG3_RX_OFFSET(tp));
5838 len = ((desc->idx_len & RXD_LEN_MASK) >> RXD_LEN_SHIFT) -
5841 if (len > TG3_RX_COPY_THRESH(tp)) {
5844 skb_size = tg3_alloc_rx_data(tp, tpr, opaque_key,
5849 pci_unmap_single(tp->pdev, dma_addr, skb_size,
5850 PCI_DMA_FROMDEVICE);
5852 skb = build_skb(data);
5855 goto drop_it_no_recycle;
5857 skb_reserve(skb, TG3_RX_OFFSET(tp));
5858 /* Ensure that the update to the data happens
5859 * after the usage of the old DMA mapping.
5866 tg3_recycle_rx(tnapi, tpr, opaque_key,
5867 desc_idx, *post_ptr);
5869 skb = netdev_alloc_skb(tp->dev,
5870 len + TG3_RAW_IP_ALIGN);
5872 goto drop_it_no_recycle;
5874 skb_reserve(skb, TG3_RAW_IP_ALIGN);
5875 pci_dma_sync_single_for_cpu(tp->pdev, dma_addr, len, PCI_DMA_FROMDEVICE);
5877 data + TG3_RX_OFFSET(tp),
5879 pci_dma_sync_single_for_device(tp->pdev, dma_addr, len, PCI_DMA_FROMDEVICE);
5883 if ((tp->dev->features & NETIF_F_RXCSUM) &&
5884 (desc->type_flags & RXD_FLAG_TCPUDP_CSUM) &&
5885 (((desc->ip_tcp_csum & RXD_TCPCSUM_MASK)
5886 >> RXD_TCPCSUM_SHIFT) == 0xffff))
5887 skb->ip_summed = CHECKSUM_UNNECESSARY;
5889 skb_checksum_none_assert(skb);
5891 skb->protocol = eth_type_trans(skb, tp->dev);
5893 if (len > (tp->dev->mtu + ETH_HLEN) &&
5894 skb->protocol != htons(ETH_P_8021Q)) {
5896 goto drop_it_no_recycle;
5899 if (desc->type_flags & RXD_FLAG_VLAN &&
5900 !(tp->rx_mode & RX_MODE_KEEP_VLAN_TAG))
5901 __vlan_hwaccel_put_tag(skb,
5902 desc->err_vlan & RXD_VLAN_MASK);
5904 napi_gro_receive(&tnapi->napi, skb);
5912 if (unlikely(rx_std_posted >= tp->rx_std_max_post)) {
5913 tpr->rx_std_prod_idx = std_prod_idx &
5914 tp->rx_std_ring_mask;
5915 tw32_rx_mbox(TG3_RX_STD_PROD_IDX_REG,
5916 tpr->rx_std_prod_idx);
5917 work_mask &= ~RXD_OPAQUE_RING_STD;
5922 sw_idx &= tp->rx_ret_ring_mask;
5924 /* Refresh hw_idx to see if there is new work */
5925 if (sw_idx == hw_idx) {
5926 hw_idx = *(tnapi->rx_rcb_prod_idx);
5931 /* ACK the status ring. */
5932 tnapi->rx_rcb_ptr = sw_idx;
5933 tw32_rx_mbox(tnapi->consmbox, sw_idx);
5935 /* Refill RX ring(s). */
5936 if (!tg3_flag(tp, ENABLE_RSS)) {
5937 if (work_mask & RXD_OPAQUE_RING_STD) {
5938 tpr->rx_std_prod_idx = std_prod_idx &
5939 tp->rx_std_ring_mask;
5940 tw32_rx_mbox(TG3_RX_STD_PROD_IDX_REG,
5941 tpr->rx_std_prod_idx);
5943 if (work_mask & RXD_OPAQUE_RING_JUMBO) {
5944 tpr->rx_jmb_prod_idx = jmb_prod_idx &
5945 tp->rx_jmb_ring_mask;
5946 tw32_rx_mbox(TG3_RX_JMB_PROD_IDX_REG,
5947 tpr->rx_jmb_prod_idx);
5950 } else if (work_mask) {
5951 /* rx_std_buffers[] and rx_jmb_buffers[] entries must be
5952 * updated before the producer indices can be updated.
5956 tpr->rx_std_prod_idx = std_prod_idx & tp->rx_std_ring_mask;
5957 tpr->rx_jmb_prod_idx = jmb_prod_idx & tp->rx_jmb_ring_mask;
5959 if (tnapi != &tp->napi[1])
5960 napi_schedule(&tp->napi[1].napi);
5966 static void tg3_poll_link(struct tg3 *tp)
5968 /* handle link change and other phy events */
5969 if (!(tg3_flag(tp, USE_LINKCHG_REG) || tg3_flag(tp, POLL_SERDES))) {
5970 struct tg3_hw_status *sblk = tp->napi[0].hw_status;
5972 if (sblk->status & SD_STATUS_LINK_CHG) {
5973 sblk->status = SD_STATUS_UPDATED |
5974 (sblk->status & ~SD_STATUS_LINK_CHG);
5975 spin_lock(&tp->lock);
5976 if (tg3_flag(tp, USE_PHYLIB)) {
5978 (MAC_STATUS_SYNC_CHANGED |
5979 MAC_STATUS_CFG_CHANGED |
5980 MAC_STATUS_MI_COMPLETION |
5981 MAC_STATUS_LNKSTATE_CHANGED));
5984 tg3_setup_phy(tp, 0);
5985 spin_unlock(&tp->lock);
5990 static int tg3_rx_prodring_xfer(struct tg3 *tp,
5991 struct tg3_rx_prodring_set *dpr,
5992 struct tg3_rx_prodring_set *spr)
5994 u32 si, di, cpycnt, src_prod_idx;
5998 src_prod_idx = spr->rx_std_prod_idx;
6000 /* Make sure updates to the rx_std_buffers[] entries and the
6001 * standard producer index are seen in the correct order.
6005 if (spr->rx_std_cons_idx == src_prod_idx)
6008 if (spr->rx_std_cons_idx < src_prod_idx)
6009 cpycnt = src_prod_idx - spr->rx_std_cons_idx;
6011 cpycnt = tp->rx_std_ring_mask + 1 -
6012 spr->rx_std_cons_idx;
6014 cpycnt = min(cpycnt,
6015 tp->rx_std_ring_mask + 1 - dpr->rx_std_prod_idx);
6017 si = spr->rx_std_cons_idx;
6018 di = dpr->rx_std_prod_idx;
6020 for (i = di; i < di + cpycnt; i++) {
6021 if (dpr->rx_std_buffers[i].data) {
6031 /* Ensure that updates to the rx_std_buffers ring and the
6032 * shadowed hardware producer ring from tg3_recycle_skb() are
6033 * ordered correctly WRT the skb check above.
6037 memcpy(&dpr->rx_std_buffers[di],
6038 &spr->rx_std_buffers[si],
6039 cpycnt * sizeof(struct ring_info));
6041 for (i = 0; i < cpycnt; i++, di++, si++) {
6042 struct tg3_rx_buffer_desc *sbd, *dbd;
6043 sbd = &spr->rx_std[si];
6044 dbd = &dpr->rx_std[di];
6045 dbd->addr_hi = sbd->addr_hi;
6046 dbd->addr_lo = sbd->addr_lo;
6049 spr->rx_std_cons_idx = (spr->rx_std_cons_idx + cpycnt) &
6050 tp->rx_std_ring_mask;
6051 dpr->rx_std_prod_idx = (dpr->rx_std_prod_idx + cpycnt) &
6052 tp->rx_std_ring_mask;
6056 src_prod_idx = spr->rx_jmb_prod_idx;
6058 /* Make sure updates to the rx_jmb_buffers[] entries and
6059 * the jumbo producer index are seen in the correct order.
6063 if (spr->rx_jmb_cons_idx == src_prod_idx)
6066 if (spr->rx_jmb_cons_idx < src_prod_idx)
6067 cpycnt = src_prod_idx - spr->rx_jmb_cons_idx;
6069 cpycnt = tp->rx_jmb_ring_mask + 1 -
6070 spr->rx_jmb_cons_idx;
6072 cpycnt = min(cpycnt,
6073 tp->rx_jmb_ring_mask + 1 - dpr->rx_jmb_prod_idx);
6075 si = spr->rx_jmb_cons_idx;
6076 di = dpr->rx_jmb_prod_idx;
6078 for (i = di; i < di + cpycnt; i++) {
6079 if (dpr->rx_jmb_buffers[i].data) {
6089 /* Ensure that updates to the rx_jmb_buffers ring and the
6090 * shadowed hardware producer ring from tg3_recycle_skb() are
6091 * ordered correctly WRT the skb check above.
6095 memcpy(&dpr->rx_jmb_buffers[di],
6096 &spr->rx_jmb_buffers[si],
6097 cpycnt * sizeof(struct ring_info));
6099 for (i = 0; i < cpycnt; i++, di++, si++) {
6100 struct tg3_rx_buffer_desc *sbd, *dbd;
6101 sbd = &spr->rx_jmb[si].std;
6102 dbd = &dpr->rx_jmb[di].std;
6103 dbd->addr_hi = sbd->addr_hi;
6104 dbd->addr_lo = sbd->addr_lo;
6107 spr->rx_jmb_cons_idx = (spr->rx_jmb_cons_idx + cpycnt) &
6108 tp->rx_jmb_ring_mask;
6109 dpr->rx_jmb_prod_idx = (dpr->rx_jmb_prod_idx + cpycnt) &
6110 tp->rx_jmb_ring_mask;
6116 static int tg3_poll_work(struct tg3_napi *tnapi, int work_done, int budget)
6118 struct tg3 *tp = tnapi->tp;
6120 /* run TX completion thread */
6121 if (tnapi->hw_status->idx[0].tx_consumer != tnapi->tx_cons) {
6123 if (unlikely(tg3_flag(tp, TX_RECOVERY_PENDING)))
6127 /* run RX thread, within the bounds set by NAPI.
6128 * All RX "locking" is done by ensuring outside
6129 * code synchronizes with tg3->napi.poll()
6131 if (*(tnapi->rx_rcb_prod_idx) != tnapi->rx_rcb_ptr)
6132 work_done += tg3_rx(tnapi, budget - work_done);
6134 if (tg3_flag(tp, ENABLE_RSS) && tnapi == &tp->napi[1]) {
6135 struct tg3_rx_prodring_set *dpr = &tp->napi[0].prodring;
6137 u32 std_prod_idx = dpr->rx_std_prod_idx;
6138 u32 jmb_prod_idx = dpr->rx_jmb_prod_idx;
6140 for (i = 1; i < tp->irq_cnt; i++)
6141 err |= tg3_rx_prodring_xfer(tp, dpr,
6142 &tp->napi[i].prodring);
6146 if (std_prod_idx != dpr->rx_std_prod_idx)
6147 tw32_rx_mbox(TG3_RX_STD_PROD_IDX_REG,
6148 dpr->rx_std_prod_idx);
6150 if (jmb_prod_idx != dpr->rx_jmb_prod_idx)
6151 tw32_rx_mbox(TG3_RX_JMB_PROD_IDX_REG,
6152 dpr->rx_jmb_prod_idx);
6157 tw32_f(HOSTCC_MODE, tp->coal_now);
6163 static inline void tg3_reset_task_schedule(struct tg3 *tp)
6165 if (!test_and_set_bit(TG3_FLAG_RESET_TASK_PENDING, tp->tg3_flags))
6166 schedule_work(&tp->reset_task);
6169 static inline void tg3_reset_task_cancel(struct tg3 *tp)
6171 cancel_work_sync(&tp->reset_task);
6172 tg3_flag_clear(tp, RESET_TASK_PENDING);
6175 static int tg3_poll_msix(struct napi_struct *napi, int budget)
6177 struct tg3_napi *tnapi = container_of(napi, struct tg3_napi, napi);
6178 struct tg3 *tp = tnapi->tp;
6180 struct tg3_hw_status *sblk = tnapi->hw_status;
6183 work_done = tg3_poll_work(tnapi, work_done, budget);
6185 if (unlikely(tg3_flag(tp, TX_RECOVERY_PENDING)))
6188 if (unlikely(work_done >= budget))
6191 /* tp->last_tag is used in tg3_int_reenable() below
6192 * to tell the hw how much work has been processed,
6193 * so we must read it before checking for more work.
6195 tnapi->last_tag = sblk->status_tag;
6196 tnapi->last_irq_tag = tnapi->last_tag;
6199 /* check for RX/TX work to do */
6200 if (likely(sblk->idx[0].tx_consumer == tnapi->tx_cons &&
6201 *(tnapi->rx_rcb_prod_idx) == tnapi->rx_rcb_ptr)) {
6202 napi_complete(napi);
6203 /* Reenable interrupts. */
6204 tw32_mailbox(tnapi->int_mbox, tnapi->last_tag << 24);
6213 /* work_done is guaranteed to be less than budget. */
6214 napi_complete(napi);
6215 tg3_reset_task_schedule(tp);
6219 static void tg3_process_error(struct tg3 *tp)
6222 bool real_error = false;
6224 if (tg3_flag(tp, ERROR_PROCESSED))
6227 /* Check Flow Attention register */
6228 val = tr32(HOSTCC_FLOW_ATTN);
6229 if (val & ~HOSTCC_FLOW_ATTN_MBUF_LWM) {
6230 netdev_err(tp->dev, "FLOW Attention error. Resetting chip.\n");
6234 if (tr32(MSGINT_STATUS) & ~MSGINT_STATUS_MSI_REQ) {
6235 netdev_err(tp->dev, "MSI Status error. Resetting chip.\n");
6239 if (tr32(RDMAC_STATUS) || tr32(WDMAC_STATUS)) {
6240 netdev_err(tp->dev, "DMA Status error. Resetting chip.\n");
6249 tg3_flag_set(tp, ERROR_PROCESSED);
6250 tg3_reset_task_schedule(tp);
6253 static int tg3_poll(struct napi_struct *napi, int budget)
6255 struct tg3_napi *tnapi = container_of(napi, struct tg3_napi, napi);
6256 struct tg3 *tp = tnapi->tp;
6258 struct tg3_hw_status *sblk = tnapi->hw_status;
6261 if (sblk->status & SD_STATUS_ERROR)
6262 tg3_process_error(tp);
6266 work_done = tg3_poll_work(tnapi, work_done, budget);
6268 if (unlikely(tg3_flag(tp, TX_RECOVERY_PENDING)))
6271 if (unlikely(work_done >= budget))
6274 if (tg3_flag(tp, TAGGED_STATUS)) {
6275 /* tp->last_tag is used in tg3_int_reenable() below
6276 * to tell the hw how much work has been processed,
6277 * so we must read it before checking for more work.
6279 tnapi->last_tag = sblk->status_tag;
6280 tnapi->last_irq_tag = tnapi->last_tag;
6283 sblk->status &= ~SD_STATUS_UPDATED;
6285 if (likely(!tg3_has_work(tnapi))) {
6286 napi_complete(napi);
6287 tg3_int_reenable(tnapi);
6295 /* work_done is guaranteed to be less than budget. */
6296 napi_complete(napi);
6297 tg3_reset_task_schedule(tp);
6301 static void tg3_napi_disable(struct tg3 *tp)
6305 for (i = tp->irq_cnt - 1; i >= 0; i--)
6306 napi_disable(&tp->napi[i].napi);
6309 static void tg3_napi_enable(struct tg3 *tp)
6313 for (i = 0; i < tp->irq_cnt; i++)
6314 napi_enable(&tp->napi[i].napi);
6317 static void tg3_napi_init(struct tg3 *tp)
6321 netif_napi_add(tp->dev, &tp->napi[0].napi, tg3_poll, 64);
6322 for (i = 1; i < tp->irq_cnt; i++)
6323 netif_napi_add(tp->dev, &tp->napi[i].napi, tg3_poll_msix, 64);
6326 static void tg3_napi_fini(struct tg3 *tp)
6330 for (i = 0; i < tp->irq_cnt; i++)
6331 netif_napi_del(&tp->napi[i].napi);
6334 static inline void tg3_netif_stop(struct tg3 *tp)
6336 tp->dev->trans_start = jiffies; /* prevent tx timeout */
6337 tg3_napi_disable(tp);
6338 netif_tx_disable(tp->dev);
6341 static inline void tg3_netif_start(struct tg3 *tp)
6343 /* NOTE: unconditional netif_tx_wake_all_queues is only
6344 * appropriate so long as all callers are assured to
6345 * have free tx slots (such as after tg3_init_hw)
6347 netif_tx_wake_all_queues(tp->dev);
6349 tg3_napi_enable(tp);
6350 tp->napi[0].hw_status->status |= SD_STATUS_UPDATED;
6351 tg3_enable_ints(tp);
6354 static void tg3_irq_quiesce(struct tg3 *tp)
6358 BUG_ON(tp->irq_sync);
6363 for (i = 0; i < tp->irq_cnt; i++)
6364 synchronize_irq(tp->napi[i].irq_vec);
6367 /* Fully shutdown all tg3 driver activity elsewhere in the system.
6368 * If irq_sync is non-zero, then the IRQ handler must be synchronized
6369 * with as well. Most of the time, this is not necessary except when
6370 * shutting down the device.
6372 static inline void tg3_full_lock(struct tg3 *tp, int irq_sync)
6374 spin_lock_bh(&tp->lock);
6376 tg3_irq_quiesce(tp);
6379 static inline void tg3_full_unlock(struct tg3 *tp)
6381 spin_unlock_bh(&tp->lock);
6384 /* One-shot MSI handler - Chip automatically disables interrupt
6385 * after sending MSI so driver doesn't have to do it.
6387 static irqreturn_t tg3_msi_1shot(int irq, void *dev_id)
6389 struct tg3_napi *tnapi = dev_id;
6390 struct tg3 *tp = tnapi->tp;
6392 prefetch(tnapi->hw_status);
6394 prefetch(&tnapi->rx_rcb[tnapi->rx_rcb_ptr]);
6396 if (likely(!tg3_irq_sync(tp)))
6397 napi_schedule(&tnapi->napi);
6402 /* MSI ISR - No need to check for interrupt sharing and no need to
6403 * flush status block and interrupt mailbox. PCI ordering rules
6404 * guarantee that MSI will arrive after the status block.
6406 static irqreturn_t tg3_msi(int irq, void *dev_id)
6408 struct tg3_napi *tnapi = dev_id;
6409 struct tg3 *tp = tnapi->tp;
6411 prefetch(tnapi->hw_status);
6413 prefetch(&tnapi->rx_rcb[tnapi->rx_rcb_ptr]);
6415 * Writing any value to intr-mbox-0 clears PCI INTA# and
6416 * chip-internal interrupt pending events.
6417 * Writing non-zero to intr-mbox-0 additional tells the
6418 * NIC to stop sending us irqs, engaging "in-intr-handler"
6421 tw32_mailbox(tnapi->int_mbox, 0x00000001);
6422 if (likely(!tg3_irq_sync(tp)))
6423 napi_schedule(&tnapi->napi);
6425 return IRQ_RETVAL(1);
6428 static irqreturn_t tg3_interrupt(int irq, void *dev_id)
6430 struct tg3_napi *tnapi = dev_id;
6431 struct tg3 *tp = tnapi->tp;
6432 struct tg3_hw_status *sblk = tnapi->hw_status;
6433 unsigned int handled = 1;
6435 /* In INTx mode, it is possible for the interrupt to arrive at
6436 * the CPU before the status block posted prior to the interrupt.
6437 * Reading the PCI State register will confirm whether the
6438 * interrupt is ours and will flush the status block.
6440 if (unlikely(!(sblk->status & SD_STATUS_UPDATED))) {
6441 if (tg3_flag(tp, CHIP_RESETTING) ||
6442 (tr32(TG3PCI_PCISTATE) & PCISTATE_INT_NOT_ACTIVE)) {
6449 * Writing any value to intr-mbox-0 clears PCI INTA# and
6450 * chip-internal interrupt pending events.
6451 * Writing non-zero to intr-mbox-0 additional tells the
6452 * NIC to stop sending us irqs, engaging "in-intr-handler"
6455 * Flush the mailbox to de-assert the IRQ immediately to prevent
6456 * spurious interrupts. The flush impacts performance but
6457 * excessive spurious interrupts can be worse in some cases.
6459 tw32_mailbox_f(MAILBOX_INTERRUPT_0 + TG3_64BIT_REG_LOW, 0x00000001);
6460 if (tg3_irq_sync(tp))
6462 sblk->status &= ~SD_STATUS_UPDATED;
6463 if (likely(tg3_has_work(tnapi))) {
6464 prefetch(&tnapi->rx_rcb[tnapi->rx_rcb_ptr]);
6465 napi_schedule(&tnapi->napi);
6467 /* No work, shared interrupt perhaps? re-enable
6468 * interrupts, and flush that PCI write
6470 tw32_mailbox_f(MAILBOX_INTERRUPT_0 + TG3_64BIT_REG_LOW,
6474 return IRQ_RETVAL(handled);
6477 static irqreturn_t tg3_interrupt_tagged(int irq, void *dev_id)
6479 struct tg3_napi *tnapi = dev_id;
6480 struct tg3 *tp = tnapi->tp;
6481 struct tg3_hw_status *sblk = tnapi->hw_status;
6482 unsigned int handled = 1;
6484 /* In INTx mode, it is possible for the interrupt to arrive at
6485 * the CPU before the status block posted prior to the interrupt.
6486 * Reading the PCI State register will confirm whether the
6487 * interrupt is ours and will flush the status block.
6489 if (unlikely(sblk->status_tag == tnapi->last_irq_tag)) {
6490 if (tg3_flag(tp, CHIP_RESETTING) ||
6491 (tr32(TG3PCI_PCISTATE) & PCISTATE_INT_NOT_ACTIVE)) {
6498 * writing any value to intr-mbox-0 clears PCI INTA# and
6499 * chip-internal interrupt pending events.
6500 * writing non-zero to intr-mbox-0 additional tells the
6501 * NIC to stop sending us irqs, engaging "in-intr-handler"
6504 * Flush the mailbox to de-assert the IRQ immediately to prevent
6505 * spurious interrupts. The flush impacts performance but
6506 * excessive spurious interrupts can be worse in some cases.
6508 tw32_mailbox_f(MAILBOX_INTERRUPT_0 + TG3_64BIT_REG_LOW, 0x00000001);
6511 * In a shared interrupt configuration, sometimes other devices'
6512 * interrupts will scream. We record the current status tag here
6513 * so that the above check can report that the screaming interrupts
6514 * are unhandled. Eventually they will be silenced.
6516 tnapi->last_irq_tag = sblk->status_tag;
6518 if (tg3_irq_sync(tp))
6521 prefetch(&tnapi->rx_rcb[tnapi->rx_rcb_ptr]);
6523 napi_schedule(&tnapi->napi);
6526 return IRQ_RETVAL(handled);
6529 /* ISR for interrupt test */
6530 static irqreturn_t tg3_test_isr(int irq, void *dev_id)
6532 struct tg3_napi *tnapi = dev_id;
6533 struct tg3 *tp = tnapi->tp;
6534 struct tg3_hw_status *sblk = tnapi->hw_status;
6536 if ((sblk->status & SD_STATUS_UPDATED) ||
6537 !(tr32(TG3PCI_PCISTATE) & PCISTATE_INT_NOT_ACTIVE)) {
6538 tg3_disable_ints(tp);
6539 return IRQ_RETVAL(1);
6541 return IRQ_RETVAL(0);
6544 #ifdef CONFIG_NET_POLL_CONTROLLER
6545 static void tg3_poll_controller(struct net_device *dev)
6548 struct tg3 *tp = netdev_priv(dev);
6550 for (i = 0; i < tp->irq_cnt; i++)
6551 tg3_interrupt(tp->napi[i].irq_vec, &tp->napi[i]);
6555 static void tg3_tx_timeout(struct net_device *dev)
6557 struct tg3 *tp = netdev_priv(dev);
6559 if (netif_msg_tx_err(tp)) {
6560 netdev_err(dev, "transmit timed out, resetting\n");
6564 tg3_reset_task_schedule(tp);
6567 /* Test for DMA buffers crossing any 4GB boundaries: 4G, 8G, etc */
6568 static inline int tg3_4g_overflow_test(dma_addr_t mapping, int len)
6570 u32 base = (u32) mapping & 0xffffffff;
6572 return (base > 0xffffdcc0) && (base + len + 8 < base);
6575 /* Test for DMA addresses > 40-bit */
6576 static inline int tg3_40bit_overflow_test(struct tg3 *tp, dma_addr_t mapping,
6579 #if defined(CONFIG_HIGHMEM) && (BITS_PER_LONG == 64)
6580 if (tg3_flag(tp, 40BIT_DMA_BUG))
6581 return ((u64) mapping + len) > DMA_BIT_MASK(40);
6588 static inline void tg3_tx_set_bd(struct tg3_tx_buffer_desc *txbd,
6589 dma_addr_t mapping, u32 len, u32 flags,
6592 txbd->addr_hi = ((u64) mapping >> 32);
6593 txbd->addr_lo = ((u64) mapping & 0xffffffff);
6594 txbd->len_flags = (len << TXD_LEN_SHIFT) | (flags & 0x0000ffff);
6595 txbd->vlan_tag = (mss << TXD_MSS_SHIFT) | (vlan << TXD_VLAN_TAG_SHIFT);
6598 static bool tg3_tx_frag_set(struct tg3_napi *tnapi, u32 *entry, u32 *budget,
6599 dma_addr_t map, u32 len, u32 flags,
6602 struct tg3 *tp = tnapi->tp;
6605 if (tg3_flag(tp, SHORT_DMA_BUG) && len <= 8)
6608 if (tg3_4g_overflow_test(map, len))
6611 if (tg3_40bit_overflow_test(tp, map, len))
6614 if (tp->dma_limit) {
6615 u32 prvidx = *entry;
6616 u32 tmp_flag = flags & ~TXD_FLAG_END;
6617 while (len > tp->dma_limit && *budget) {
6618 u32 frag_len = tp->dma_limit;
6619 len -= tp->dma_limit;
6621 /* Avoid the 8byte DMA problem */
6623 len += tp->dma_limit / 2;
6624 frag_len = tp->dma_limit / 2;
6627 tnapi->tx_buffers[*entry].fragmented = true;
6629 tg3_tx_set_bd(&tnapi->tx_ring[*entry], map,
6630 frag_len, tmp_flag, mss, vlan);
6633 *entry = NEXT_TX(*entry);
6640 tg3_tx_set_bd(&tnapi->tx_ring[*entry], map,
6641 len, flags, mss, vlan);
6643 *entry = NEXT_TX(*entry);
6646 tnapi->tx_buffers[prvidx].fragmented = false;
6650 tg3_tx_set_bd(&tnapi->tx_ring[*entry], map,
6651 len, flags, mss, vlan);
6652 *entry = NEXT_TX(*entry);
6658 static void tg3_tx_skb_unmap(struct tg3_napi *tnapi, u32 entry, int last)
6661 struct sk_buff *skb;
6662 struct tg3_tx_ring_info *txb = &tnapi->tx_buffers[entry];
6667 pci_unmap_single(tnapi->tp->pdev,
6668 dma_unmap_addr(txb, mapping),
6672 while (txb->fragmented) {
6673 txb->fragmented = false;
6674 entry = NEXT_TX(entry);
6675 txb = &tnapi->tx_buffers[entry];
6678 for (i = 0; i <= last; i++) {
6679 const skb_frag_t *frag = &skb_shinfo(skb)->frags[i];
6681 entry = NEXT_TX(entry);
6682 txb = &tnapi->tx_buffers[entry];
6684 pci_unmap_page(tnapi->tp->pdev,
6685 dma_unmap_addr(txb, mapping),
6686 skb_frag_size(frag), PCI_DMA_TODEVICE);
6688 while (txb->fragmented) {
6689 txb->fragmented = false;
6690 entry = NEXT_TX(entry);
6691 txb = &tnapi->tx_buffers[entry];
6696 /* Workaround 4GB and 40-bit hardware DMA bugs. */
6697 static int tigon3_dma_hwbug_workaround(struct tg3_napi *tnapi,
6698 struct sk_buff **pskb,
6699 u32 *entry, u32 *budget,
6700 u32 base_flags, u32 mss, u32 vlan)
6702 struct tg3 *tp = tnapi->tp;
6703 struct sk_buff *new_skb, *skb = *pskb;
6704 dma_addr_t new_addr = 0;
6707 if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5701)
6708 new_skb = skb_copy(skb, GFP_ATOMIC);
6710 int more_headroom = 4 - ((unsigned long)skb->data & 3);
6712 new_skb = skb_copy_expand(skb,
6713 skb_headroom(skb) + more_headroom,
6714 skb_tailroom(skb), GFP_ATOMIC);
6720 /* New SKB is guaranteed to be linear. */
6721 new_addr = pci_map_single(tp->pdev, new_skb->data, new_skb->len,
6723 /* Make sure the mapping succeeded */
6724 if (pci_dma_mapping_error(tp->pdev, new_addr)) {
6725 dev_kfree_skb(new_skb);
6728 u32 save_entry = *entry;
6730 base_flags |= TXD_FLAG_END;
6732 tnapi->tx_buffers[*entry].skb = new_skb;
6733 dma_unmap_addr_set(&tnapi->tx_buffers[*entry],
6736 if (tg3_tx_frag_set(tnapi, entry, budget, new_addr,
6737 new_skb->len, base_flags,
6739 tg3_tx_skb_unmap(tnapi, save_entry, -1);
6740 dev_kfree_skb(new_skb);
6751 static netdev_tx_t tg3_start_xmit(struct sk_buff *, struct net_device *);
6753 /* Use GSO to workaround a rare TSO bug that may be triggered when the
6754 * TSO header is greater than 80 bytes.
6756 static int tg3_tso_bug(struct tg3 *tp, struct sk_buff *skb)
6758 struct sk_buff *segs, *nskb;
6759 u32 frag_cnt_est = skb_shinfo(skb)->gso_segs * 3;
6761 /* Estimate the number of fragments in the worst case */
6762 if (unlikely(tg3_tx_avail(&tp->napi[0]) <= frag_cnt_est)) {
6763 netif_stop_queue(tp->dev);
6765 /* netif_tx_stop_queue() must be done before checking
6766 * checking tx index in tg3_tx_avail() below, because in
6767 * tg3_tx(), we update tx index before checking for
6768 * netif_tx_queue_stopped().
6771 if (tg3_tx_avail(&tp->napi[0]) <= frag_cnt_est)
6772 return NETDEV_TX_BUSY;
6774 netif_wake_queue(tp->dev);
6777 segs = skb_gso_segment(skb, tp->dev->features & ~NETIF_F_TSO);
6779 goto tg3_tso_bug_end;
6785 tg3_start_xmit(nskb, tp->dev);
6791 return NETDEV_TX_OK;
6794 /* hard_start_xmit for devices that have the 4G bug and/or 40-bit bug and
6795 * support TG3_FLAG_HW_TSO_1 or firmware TSO only.
6797 static netdev_tx_t tg3_start_xmit(struct sk_buff *skb, struct net_device *dev)
6799 struct tg3 *tp = netdev_priv(dev);
6800 u32 len, entry, base_flags, mss, vlan = 0;
6802 int i = -1, would_hit_hwbug;
6804 struct tg3_napi *tnapi;
6805 struct netdev_queue *txq;
6808 txq = netdev_get_tx_queue(dev, skb_get_queue_mapping(skb));
6809 tnapi = &tp->napi[skb_get_queue_mapping(skb)];
6810 if (tg3_flag(tp, ENABLE_TSS))
6813 budget = tg3_tx_avail(tnapi);
6815 /* We are running in BH disabled context with netif_tx_lock
6816 * and TX reclaim runs via tp->napi.poll inside of a software
6817 * interrupt. Furthermore, IRQ processing runs lockless so we have
6818 * no IRQ context deadlocks to worry about either. Rejoice!
6820 if (unlikely(budget <= (skb_shinfo(skb)->nr_frags + 1))) {
6821 if (!netif_tx_queue_stopped(txq)) {
6822 netif_tx_stop_queue(txq);
6824 /* This is a hard error, log it. */
6826 "BUG! Tx Ring full when queue awake!\n");
6828 return NETDEV_TX_BUSY;
6831 entry = tnapi->tx_prod;
6833 if (skb->ip_summed == CHECKSUM_PARTIAL)
6834 base_flags |= TXD_FLAG_TCPUDP_CSUM;
6836 mss = skb_shinfo(skb)->gso_size;
6839 u32 tcp_opt_len, hdr_len;
6841 if (skb_header_cloned(skb) &&
6842 pskb_expand_head(skb, 0, 0, GFP_ATOMIC))
6846 tcp_opt_len = tcp_optlen(skb);
6848 hdr_len = skb_transport_offset(skb) + tcp_hdrlen(skb) - ETH_HLEN;
6850 if (!skb_is_gso_v6(skb)) {
6852 iph->tot_len = htons(mss + hdr_len);
6855 if (unlikely((ETH_HLEN + hdr_len) > 80) &&
6856 tg3_flag(tp, TSO_BUG))
6857 return tg3_tso_bug(tp, skb);
6859 base_flags |= (TXD_FLAG_CPU_PRE_DMA |
6860 TXD_FLAG_CPU_POST_DMA);
6862 if (tg3_flag(tp, HW_TSO_1) ||
6863 tg3_flag(tp, HW_TSO_2) ||
6864 tg3_flag(tp, HW_TSO_3)) {
6865 tcp_hdr(skb)->check = 0;
6866 base_flags &= ~TXD_FLAG_TCPUDP_CSUM;
6868 tcp_hdr(skb)->check = ~csum_tcpudp_magic(iph->saddr,
6873 if (tg3_flag(tp, HW_TSO_3)) {
6874 mss |= (hdr_len & 0xc) << 12;
6876 base_flags |= 0x00000010;
6877 base_flags |= (hdr_len & 0x3e0) << 5;
6878 } else if (tg3_flag(tp, HW_TSO_2))
6879 mss |= hdr_len << 9;
6880 else if (tg3_flag(tp, HW_TSO_1) ||
6881 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705) {
6882 if (tcp_opt_len || iph->ihl > 5) {
6885 tsflags = (iph->ihl - 5) + (tcp_opt_len >> 2);
6886 mss |= (tsflags << 11);
6889 if (tcp_opt_len || iph->ihl > 5) {
6892 tsflags = (iph->ihl - 5) + (tcp_opt_len >> 2);
6893 base_flags |= tsflags << 12;
6898 if (tg3_flag(tp, USE_JUMBO_BDFLAG) &&
6899 !mss && skb->len > VLAN_ETH_FRAME_LEN)
6900 base_flags |= TXD_FLAG_JMB_PKT;
6902 if (vlan_tx_tag_present(skb)) {
6903 base_flags |= TXD_FLAG_VLAN;
6904 vlan = vlan_tx_tag_get(skb);
6907 len = skb_headlen(skb);
6909 mapping = pci_map_single(tp->pdev, skb->data, len, PCI_DMA_TODEVICE);
6910 if (pci_dma_mapping_error(tp->pdev, mapping))
6914 tnapi->tx_buffers[entry].skb = skb;
6915 dma_unmap_addr_set(&tnapi->tx_buffers[entry], mapping, mapping);
6917 would_hit_hwbug = 0;
6919 if (tg3_flag(tp, 5701_DMA_BUG))
6920 would_hit_hwbug = 1;
6922 if (tg3_tx_frag_set(tnapi, &entry, &budget, mapping, len, base_flags |
6923 ((skb_shinfo(skb)->nr_frags == 0) ? TXD_FLAG_END : 0),
6925 would_hit_hwbug = 1;
6926 } else if (skb_shinfo(skb)->nr_frags > 0) {
6929 if (!tg3_flag(tp, HW_TSO_1) &&
6930 !tg3_flag(tp, HW_TSO_2) &&
6931 !tg3_flag(tp, HW_TSO_3))
6934 /* Now loop through additional data
6935 * fragments, and queue them.
6937 last = skb_shinfo(skb)->nr_frags - 1;
6938 for (i = 0; i <= last; i++) {
6939 skb_frag_t *frag = &skb_shinfo(skb)->frags[i];
6941 len = skb_frag_size(frag);
6942 mapping = skb_frag_dma_map(&tp->pdev->dev, frag, 0,
6943 len, DMA_TO_DEVICE);
6945 tnapi->tx_buffers[entry].skb = NULL;
6946 dma_unmap_addr_set(&tnapi->tx_buffers[entry], mapping,
6948 if (dma_mapping_error(&tp->pdev->dev, mapping))
6952 tg3_tx_frag_set(tnapi, &entry, &budget, mapping,
6954 ((i == last) ? TXD_FLAG_END : 0),
6956 would_hit_hwbug = 1;
6962 if (would_hit_hwbug) {
6963 tg3_tx_skb_unmap(tnapi, tnapi->tx_prod, i);
6965 /* If the workaround fails due to memory/mapping
6966 * failure, silently drop this packet.
6968 entry = tnapi->tx_prod;
6969 budget = tg3_tx_avail(tnapi);
6970 if (tigon3_dma_hwbug_workaround(tnapi, &skb, &entry, &budget,
6971 base_flags, mss, vlan))
6975 skb_tx_timestamp(skb);
6976 netdev_sent_queue(tp->dev, skb->len);
6978 /* Packets are ready, update Tx producer idx local and on card. */
6979 tw32_tx_mbox(tnapi->prodmbox, entry);
6981 tnapi->tx_prod = entry;
6982 if (unlikely(tg3_tx_avail(tnapi) <= (MAX_SKB_FRAGS + 1))) {
6983 netif_tx_stop_queue(txq);
6985 /* netif_tx_stop_queue() must be done before checking
6986 * checking tx index in tg3_tx_avail() below, because in
6987 * tg3_tx(), we update tx index before checking for
6988 * netif_tx_queue_stopped().
6991 if (tg3_tx_avail(tnapi) > TG3_TX_WAKEUP_THRESH(tnapi))
6992 netif_tx_wake_queue(txq);
6996 return NETDEV_TX_OK;
6999 tg3_tx_skb_unmap(tnapi, tnapi->tx_prod, --i);
7000 tnapi->tx_buffers[tnapi->tx_prod].skb = NULL;
7005 return NETDEV_TX_OK;
7008 static void tg3_mac_loopback(struct tg3 *tp, bool enable)
7011 tp->mac_mode &= ~(MAC_MODE_HALF_DUPLEX |
7012 MAC_MODE_PORT_MODE_MASK);
7014 tp->mac_mode |= MAC_MODE_PORT_INT_LPBACK;
7016 if (!tg3_flag(tp, 5705_PLUS))
7017 tp->mac_mode |= MAC_MODE_LINK_POLARITY;
7019 if (tp->phy_flags & TG3_PHYFLG_10_100_ONLY)
7020 tp->mac_mode |= MAC_MODE_PORT_MODE_MII;
7022 tp->mac_mode |= MAC_MODE_PORT_MODE_GMII;
7024 tp->mac_mode &= ~MAC_MODE_PORT_INT_LPBACK;
7026 if (tg3_flag(tp, 5705_PLUS) ||
7027 (tp->phy_flags & TG3_PHYFLG_PHY_SERDES) ||
7028 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700)
7029 tp->mac_mode &= ~MAC_MODE_LINK_POLARITY;
7032 tw32(MAC_MODE, tp->mac_mode);
7036 static int tg3_phy_lpbk_set(struct tg3 *tp, u32 speed, bool extlpbk)
7038 u32 val, bmcr, mac_mode, ptest = 0;
7040 tg3_phy_toggle_apd(tp, false);
7041 tg3_phy_toggle_automdix(tp, 0);
7043 if (extlpbk && tg3_phy_set_extloopbk(tp))
7046 bmcr = BMCR_FULLDPLX;
7051 bmcr |= BMCR_SPEED100;
7055 if (tp->phy_flags & TG3_PHYFLG_IS_FET) {
7057 bmcr |= BMCR_SPEED100;
7060 bmcr |= BMCR_SPEED1000;
7065 if (!(tp->phy_flags & TG3_PHYFLG_IS_FET)) {
7066 tg3_readphy(tp, MII_CTRL1000, &val);
7067 val |= CTL1000_AS_MASTER |
7068 CTL1000_ENABLE_MASTER;
7069 tg3_writephy(tp, MII_CTRL1000, val);
7071 ptest = MII_TG3_FET_PTEST_TRIM_SEL |
7072 MII_TG3_FET_PTEST_TRIM_2;
7073 tg3_writephy(tp, MII_TG3_FET_PTEST, ptest);
7076 bmcr |= BMCR_LOOPBACK;
7078 tg3_writephy(tp, MII_BMCR, bmcr);
7080 /* The write needs to be flushed for the FETs */
7081 if (tp->phy_flags & TG3_PHYFLG_IS_FET)
7082 tg3_readphy(tp, MII_BMCR, &bmcr);
7086 if ((tp->phy_flags & TG3_PHYFLG_IS_FET) &&
7087 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785) {
7088 tg3_writephy(tp, MII_TG3_FET_PTEST, ptest |
7089 MII_TG3_FET_PTEST_FRC_TX_LINK |
7090 MII_TG3_FET_PTEST_FRC_TX_LOCK);
7092 /* The write needs to be flushed for the AC131 */
7093 tg3_readphy(tp, MII_TG3_FET_PTEST, &val);
7096 /* Reset to prevent losing 1st rx packet intermittently */
7097 if ((tp->phy_flags & TG3_PHYFLG_MII_SERDES) &&
7098 tg3_flag(tp, 5780_CLASS)) {
7099 tw32_f(MAC_RX_MODE, RX_MODE_RESET);
7101 tw32_f(MAC_RX_MODE, tp->rx_mode);
7104 mac_mode = tp->mac_mode &
7105 ~(MAC_MODE_PORT_MODE_MASK | MAC_MODE_HALF_DUPLEX);
7106 if (speed == SPEED_1000)
7107 mac_mode |= MAC_MODE_PORT_MODE_GMII;
7109 mac_mode |= MAC_MODE_PORT_MODE_MII;
7111 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700) {
7112 u32 masked_phy_id = tp->phy_id & TG3_PHY_ID_MASK;
7114 if (masked_phy_id == TG3_PHY_ID_BCM5401)
7115 mac_mode &= ~MAC_MODE_LINK_POLARITY;
7116 else if (masked_phy_id == TG3_PHY_ID_BCM5411)
7117 mac_mode |= MAC_MODE_LINK_POLARITY;
7119 tg3_writephy(tp, MII_TG3_EXT_CTRL,
7120 MII_TG3_EXT_CTRL_LNK3_LED_MODE);
7123 tw32(MAC_MODE, mac_mode);
7129 static void tg3_set_loopback(struct net_device *dev, netdev_features_t features)
7131 struct tg3 *tp = netdev_priv(dev);
7133 if (features & NETIF_F_LOOPBACK) {
7134 if (tp->mac_mode & MAC_MODE_PORT_INT_LPBACK)
7137 spin_lock_bh(&tp->lock);
7138 tg3_mac_loopback(tp, true);
7139 netif_carrier_on(tp->dev);
7140 spin_unlock_bh(&tp->lock);
7141 netdev_info(dev, "Internal MAC loopback mode enabled.\n");
7143 if (!(tp->mac_mode & MAC_MODE_PORT_INT_LPBACK))
7146 spin_lock_bh(&tp->lock);
7147 tg3_mac_loopback(tp, false);
7148 /* Force link status check */
7149 tg3_setup_phy(tp, 1);
7150 spin_unlock_bh(&tp->lock);
7151 netdev_info(dev, "Internal MAC loopback mode disabled.\n");
7155 static netdev_features_t tg3_fix_features(struct net_device *dev,
7156 netdev_features_t features)
7158 struct tg3 *tp = netdev_priv(dev);
7160 if (dev->mtu > ETH_DATA_LEN && tg3_flag(tp, 5780_CLASS))
7161 features &= ~NETIF_F_ALL_TSO;
7166 static int tg3_set_features(struct net_device *dev, netdev_features_t features)
7168 netdev_features_t changed = dev->features ^ features;
7170 if ((changed & NETIF_F_LOOPBACK) && netif_running(dev))
7171 tg3_set_loopback(dev, features);
7176 static void tg3_rx_prodring_free(struct tg3 *tp,
7177 struct tg3_rx_prodring_set *tpr)
7181 if (tpr != &tp->napi[0].prodring) {
7182 for (i = tpr->rx_std_cons_idx; i != tpr->rx_std_prod_idx;
7183 i = (i + 1) & tp->rx_std_ring_mask)
7184 tg3_rx_data_free(tp, &tpr->rx_std_buffers[i],
7187 if (tg3_flag(tp, JUMBO_CAPABLE)) {
7188 for (i = tpr->rx_jmb_cons_idx;
7189 i != tpr->rx_jmb_prod_idx;
7190 i = (i + 1) & tp->rx_jmb_ring_mask) {
7191 tg3_rx_data_free(tp, &tpr->rx_jmb_buffers[i],
7199 for (i = 0; i <= tp->rx_std_ring_mask; i++)
7200 tg3_rx_data_free(tp, &tpr->rx_std_buffers[i],
7203 if (tg3_flag(tp, JUMBO_CAPABLE) && !tg3_flag(tp, 5780_CLASS)) {
7204 for (i = 0; i <= tp->rx_jmb_ring_mask; i++)
7205 tg3_rx_data_free(tp, &tpr->rx_jmb_buffers[i],
7210 /* Initialize rx rings for packet processing.
7212 * The chip has been shut down and the driver detached from
7213 * the networking, so no interrupts or new tx packets will
7214 * end up in the driver. tp->{tx,}lock are held and thus
7217 static int tg3_rx_prodring_alloc(struct tg3 *tp,
7218 struct tg3_rx_prodring_set *tpr)
7220 u32 i, rx_pkt_dma_sz;
7222 tpr->rx_std_cons_idx = 0;
7223 tpr->rx_std_prod_idx = 0;
7224 tpr->rx_jmb_cons_idx = 0;
7225 tpr->rx_jmb_prod_idx = 0;
7227 if (tpr != &tp->napi[0].prodring) {
7228 memset(&tpr->rx_std_buffers[0], 0,
7229 TG3_RX_STD_BUFF_RING_SIZE(tp));
7230 if (tpr->rx_jmb_buffers)
7231 memset(&tpr->rx_jmb_buffers[0], 0,
7232 TG3_RX_JMB_BUFF_RING_SIZE(tp));
7236 /* Zero out all descriptors. */
7237 memset(tpr->rx_std, 0, TG3_RX_STD_RING_BYTES(tp));
7239 rx_pkt_dma_sz = TG3_RX_STD_DMA_SZ;
7240 if (tg3_flag(tp, 5780_CLASS) &&
7241 tp->dev->mtu > ETH_DATA_LEN)
7242 rx_pkt_dma_sz = TG3_RX_JMB_DMA_SZ;
7243 tp->rx_pkt_map_sz = TG3_RX_DMA_TO_MAP_SZ(rx_pkt_dma_sz);
7245 /* Initialize invariants of the rings, we only set this
7246 * stuff once. This works because the card does not
7247 * write into the rx buffer posting rings.
7249 for (i = 0; i <= tp->rx_std_ring_mask; i++) {
7250 struct tg3_rx_buffer_desc *rxd;
7252 rxd = &tpr->rx_std[i];
7253 rxd->idx_len = rx_pkt_dma_sz << RXD_LEN_SHIFT;
7254 rxd->type_flags = (RXD_FLAG_END << RXD_FLAGS_SHIFT);
7255 rxd->opaque = (RXD_OPAQUE_RING_STD |
7256 (i << RXD_OPAQUE_INDEX_SHIFT));
7259 /* Now allocate fresh SKBs for each rx ring. */
7260 for (i = 0; i < tp->rx_pending; i++) {
7261 if (tg3_alloc_rx_data(tp, tpr, RXD_OPAQUE_RING_STD, i) < 0) {
7262 netdev_warn(tp->dev,
7263 "Using a smaller RX standard ring. Only "
7264 "%d out of %d buffers were allocated "
7265 "successfully\n", i, tp->rx_pending);
7273 if (!tg3_flag(tp, JUMBO_CAPABLE) || tg3_flag(tp, 5780_CLASS))
7276 memset(tpr->rx_jmb, 0, TG3_RX_JMB_RING_BYTES(tp));
7278 if (!tg3_flag(tp, JUMBO_RING_ENABLE))
7281 for (i = 0; i <= tp->rx_jmb_ring_mask; i++) {
7282 struct tg3_rx_buffer_desc *rxd;
7284 rxd = &tpr->rx_jmb[i].std;
7285 rxd->idx_len = TG3_RX_JMB_DMA_SZ << RXD_LEN_SHIFT;
7286 rxd->type_flags = (RXD_FLAG_END << RXD_FLAGS_SHIFT) |
7288 rxd->opaque = (RXD_OPAQUE_RING_JUMBO |
7289 (i << RXD_OPAQUE_INDEX_SHIFT));
7292 for (i = 0; i < tp->rx_jumbo_pending; i++) {
7293 if (tg3_alloc_rx_data(tp, tpr, RXD_OPAQUE_RING_JUMBO, i) < 0) {
7294 netdev_warn(tp->dev,
7295 "Using a smaller RX jumbo ring. Only %d "
7296 "out of %d buffers were allocated "
7297 "successfully\n", i, tp->rx_jumbo_pending);
7300 tp->rx_jumbo_pending = i;
7309 tg3_rx_prodring_free(tp, tpr);
7313 static void tg3_rx_prodring_fini(struct tg3 *tp,
7314 struct tg3_rx_prodring_set *tpr)
7316 kfree(tpr->rx_std_buffers);
7317 tpr->rx_std_buffers = NULL;
7318 kfree(tpr->rx_jmb_buffers);
7319 tpr->rx_jmb_buffers = NULL;
7321 dma_free_coherent(&tp->pdev->dev, TG3_RX_STD_RING_BYTES(tp),
7322 tpr->rx_std, tpr->rx_std_mapping);
7326 dma_free_coherent(&tp->pdev->dev, TG3_RX_JMB_RING_BYTES(tp),
7327 tpr->rx_jmb, tpr->rx_jmb_mapping);
7332 static int tg3_rx_prodring_init(struct tg3 *tp,
7333 struct tg3_rx_prodring_set *tpr)
7335 tpr->rx_std_buffers = kzalloc(TG3_RX_STD_BUFF_RING_SIZE(tp),
7337 if (!tpr->rx_std_buffers)
7340 tpr->rx_std = dma_alloc_coherent(&tp->pdev->dev,
7341 TG3_RX_STD_RING_BYTES(tp),
7342 &tpr->rx_std_mapping,
7347 if (tg3_flag(tp, JUMBO_CAPABLE) && !tg3_flag(tp, 5780_CLASS)) {
7348 tpr->rx_jmb_buffers = kzalloc(TG3_RX_JMB_BUFF_RING_SIZE(tp),
7350 if (!tpr->rx_jmb_buffers)
7353 tpr->rx_jmb = dma_alloc_coherent(&tp->pdev->dev,
7354 TG3_RX_JMB_RING_BYTES(tp),
7355 &tpr->rx_jmb_mapping,
7364 tg3_rx_prodring_fini(tp, tpr);
7368 /* Free up pending packets in all rx/tx rings.
7370 * The chip has been shut down and the driver detached from
7371 * the networking, so no interrupts or new tx packets will
7372 * end up in the driver. tp->{tx,}lock is not held and we are not
7373 * in an interrupt context and thus may sleep.
7375 static void tg3_free_rings(struct tg3 *tp)
7379 for (j = 0; j < tp->irq_cnt; j++) {
7380 struct tg3_napi *tnapi = &tp->napi[j];
7382 tg3_rx_prodring_free(tp, &tnapi->prodring);
7384 if (!tnapi->tx_buffers)
7387 for (i = 0; i < TG3_TX_RING_SIZE; i++) {
7388 struct sk_buff *skb = tnapi->tx_buffers[i].skb;
7393 tg3_tx_skb_unmap(tnapi, i,
7394 skb_shinfo(skb)->nr_frags - 1);
7396 dev_kfree_skb_any(skb);
7399 netdev_reset_queue(tp->dev);
7402 /* Initialize tx/rx rings for packet processing.
7404 * The chip has been shut down and the driver detached from
7405 * the networking, so no interrupts or new tx packets will
7406 * end up in the driver. tp->{tx,}lock are held and thus
7409 static int tg3_init_rings(struct tg3 *tp)
7413 /* Free up all the SKBs. */
7416 for (i = 0; i < tp->irq_cnt; i++) {
7417 struct tg3_napi *tnapi = &tp->napi[i];
7419 tnapi->last_tag = 0;
7420 tnapi->last_irq_tag = 0;
7421 tnapi->hw_status->status = 0;
7422 tnapi->hw_status->status_tag = 0;
7423 memset(tnapi->hw_status, 0, TG3_HW_STATUS_SIZE);
7428 memset(tnapi->tx_ring, 0, TG3_TX_RING_BYTES);
7430 tnapi->rx_rcb_ptr = 0;
7432 memset(tnapi->rx_rcb, 0, TG3_RX_RCB_RING_BYTES(tp));
7434 if (tg3_rx_prodring_alloc(tp, &tnapi->prodring)) {
7444 * Must not be invoked with interrupt sources disabled and
7445 * the hardware shutdown down.
7447 static void tg3_free_consistent(struct tg3 *tp)
7451 for (i = 0; i < tp->irq_cnt; i++) {
7452 struct tg3_napi *tnapi = &tp->napi[i];
7454 if (tnapi->tx_ring) {
7455 dma_free_coherent(&tp->pdev->dev, TG3_TX_RING_BYTES,
7456 tnapi->tx_ring, tnapi->tx_desc_mapping);
7457 tnapi->tx_ring = NULL;
7460 kfree(tnapi->tx_buffers);
7461 tnapi->tx_buffers = NULL;
7463 if (tnapi->rx_rcb) {
7464 dma_free_coherent(&tp->pdev->dev,
7465 TG3_RX_RCB_RING_BYTES(tp),
7467 tnapi->rx_rcb_mapping);
7468 tnapi->rx_rcb = NULL;
7471 tg3_rx_prodring_fini(tp, &tnapi->prodring);
7473 if (tnapi->hw_status) {
7474 dma_free_coherent(&tp->pdev->dev, TG3_HW_STATUS_SIZE,
7476 tnapi->status_mapping);
7477 tnapi->hw_status = NULL;
7482 dma_free_coherent(&tp->pdev->dev, sizeof(struct tg3_hw_stats),
7483 tp->hw_stats, tp->stats_mapping);
7484 tp->hw_stats = NULL;
7489 * Must not be invoked with interrupt sources disabled and
7490 * the hardware shutdown down. Can sleep.
7492 static int tg3_alloc_consistent(struct tg3 *tp)
7496 tp->hw_stats = dma_alloc_coherent(&tp->pdev->dev,
7497 sizeof(struct tg3_hw_stats),
7503 memset(tp->hw_stats, 0, sizeof(struct tg3_hw_stats));
7505 for (i = 0; i < tp->irq_cnt; i++) {
7506 struct tg3_napi *tnapi = &tp->napi[i];
7507 struct tg3_hw_status *sblk;
7509 tnapi->hw_status = dma_alloc_coherent(&tp->pdev->dev,
7511 &tnapi->status_mapping,
7513 if (!tnapi->hw_status)
7516 memset(tnapi->hw_status, 0, TG3_HW_STATUS_SIZE);
7517 sblk = tnapi->hw_status;
7519 if (tg3_rx_prodring_init(tp, &tnapi->prodring))
7522 /* If multivector TSS is enabled, vector 0 does not handle
7523 * tx interrupts. Don't allocate any resources for it.
7525 if ((!i && !tg3_flag(tp, ENABLE_TSS)) ||
7526 (i && tg3_flag(tp, ENABLE_TSS))) {
7527 tnapi->tx_buffers = kzalloc(
7528 sizeof(struct tg3_tx_ring_info) *
7529 TG3_TX_RING_SIZE, GFP_KERNEL);
7530 if (!tnapi->tx_buffers)
7533 tnapi->tx_ring = dma_alloc_coherent(&tp->pdev->dev,
7535 &tnapi->tx_desc_mapping,
7537 if (!tnapi->tx_ring)
7542 * When RSS is enabled, the status block format changes
7543 * slightly. The "rx_jumbo_consumer", "reserved",
7544 * and "rx_mini_consumer" members get mapped to the
7545 * other three rx return ring producer indexes.
7549 tnapi->rx_rcb_prod_idx = &sblk->idx[0].rx_producer;
7552 tnapi->rx_rcb_prod_idx = &sblk->rx_jumbo_consumer;
7555 tnapi->rx_rcb_prod_idx = &sblk->reserved;
7558 tnapi->rx_rcb_prod_idx = &sblk->rx_mini_consumer;
7563 * If multivector RSS is enabled, vector 0 does not handle
7564 * rx or tx interrupts. Don't allocate any resources for it.
7566 if (!i && tg3_flag(tp, ENABLE_RSS))
7569 tnapi->rx_rcb = dma_alloc_coherent(&tp->pdev->dev,
7570 TG3_RX_RCB_RING_BYTES(tp),
7571 &tnapi->rx_rcb_mapping,
7576 memset(tnapi->rx_rcb, 0, TG3_RX_RCB_RING_BYTES(tp));
7582 tg3_free_consistent(tp);
7586 #define MAX_WAIT_CNT 1000
7588 /* To stop a block, clear the enable bit and poll till it
7589 * clears. tp->lock is held.
7591 static int tg3_stop_block(struct tg3 *tp, unsigned long ofs, u32 enable_bit, int silent)
7596 if (tg3_flag(tp, 5705_PLUS)) {
7603 /* We can't enable/disable these bits of the
7604 * 5705/5750, just say success.
7617 for (i = 0; i < MAX_WAIT_CNT; i++) {
7620 if ((val & enable_bit) == 0)
7624 if (i == MAX_WAIT_CNT && !silent) {
7625 dev_err(&tp->pdev->dev,
7626 "tg3_stop_block timed out, ofs=%lx enable_bit=%x\n",
7634 /* tp->lock is held. */
7635 static int tg3_abort_hw(struct tg3 *tp, int silent)
7639 tg3_disable_ints(tp);
7641 tp->rx_mode &= ~RX_MODE_ENABLE;
7642 tw32_f(MAC_RX_MODE, tp->rx_mode);
7645 err = tg3_stop_block(tp, RCVBDI_MODE, RCVBDI_MODE_ENABLE, silent);
7646 err |= tg3_stop_block(tp, RCVLPC_MODE, RCVLPC_MODE_ENABLE, silent);
7647 err |= tg3_stop_block(tp, RCVLSC_MODE, RCVLSC_MODE_ENABLE, silent);
7648 err |= tg3_stop_block(tp, RCVDBDI_MODE, RCVDBDI_MODE_ENABLE, silent);
7649 err |= tg3_stop_block(tp, RCVDCC_MODE, RCVDCC_MODE_ENABLE, silent);
7650 err |= tg3_stop_block(tp, RCVCC_MODE, RCVCC_MODE_ENABLE, silent);
7652 err |= tg3_stop_block(tp, SNDBDS_MODE, SNDBDS_MODE_ENABLE, silent);
7653 err |= tg3_stop_block(tp, SNDBDI_MODE, SNDBDI_MODE_ENABLE, silent);
7654 err |= tg3_stop_block(tp, SNDDATAI_MODE, SNDDATAI_MODE_ENABLE, silent);
7655 err |= tg3_stop_block(tp, RDMAC_MODE, RDMAC_MODE_ENABLE, silent);
7656 err |= tg3_stop_block(tp, SNDDATAC_MODE, SNDDATAC_MODE_ENABLE, silent);
7657 err |= tg3_stop_block(tp, DMAC_MODE, DMAC_MODE_ENABLE, silent);
7658 err |= tg3_stop_block(tp, SNDBDC_MODE, SNDBDC_MODE_ENABLE, silent);
7660 tp->mac_mode &= ~MAC_MODE_TDE_ENABLE;
7661 tw32_f(MAC_MODE, tp->mac_mode);
7664 tp->tx_mode &= ~TX_MODE_ENABLE;
7665 tw32_f(MAC_TX_MODE, tp->tx_mode);
7667 for (i = 0; i < MAX_WAIT_CNT; i++) {
7669 if (!(tr32(MAC_TX_MODE) & TX_MODE_ENABLE))
7672 if (i >= MAX_WAIT_CNT) {
7673 dev_err(&tp->pdev->dev,
7674 "%s timed out, TX_MODE_ENABLE will not clear "
7675 "MAC_TX_MODE=%08x\n", __func__, tr32(MAC_TX_MODE));
7679 err |= tg3_stop_block(tp, HOSTCC_MODE, HOSTCC_MODE_ENABLE, silent);
7680 err |= tg3_stop_block(tp, WDMAC_MODE, WDMAC_MODE_ENABLE, silent);
7681 err |= tg3_stop_block(tp, MBFREE_MODE, MBFREE_MODE_ENABLE, silent);
7683 tw32(FTQ_RESET, 0xffffffff);
7684 tw32(FTQ_RESET, 0x00000000);
7686 err |= tg3_stop_block(tp, BUFMGR_MODE, BUFMGR_MODE_ENABLE, silent);
7687 err |= tg3_stop_block(tp, MEMARB_MODE, MEMARB_MODE_ENABLE, silent);
7689 for (i = 0; i < tp->irq_cnt; i++) {
7690 struct tg3_napi *tnapi = &tp->napi[i];
7691 if (tnapi->hw_status)
7692 memset(tnapi->hw_status, 0, TG3_HW_STATUS_SIZE);
7698 /* Save PCI command register before chip reset */
7699 static void tg3_save_pci_state(struct tg3 *tp)
7701 pci_read_config_word(tp->pdev, PCI_COMMAND, &tp->pci_cmd);
7704 /* Restore PCI state after chip reset */
7705 static void tg3_restore_pci_state(struct tg3 *tp)
7709 /* Re-enable indirect register accesses. */
7710 pci_write_config_dword(tp->pdev, TG3PCI_MISC_HOST_CTRL,
7711 tp->misc_host_ctrl);
7713 /* Set MAX PCI retry to zero. */
7714 val = (PCISTATE_ROM_ENABLE | PCISTATE_ROM_RETRY_ENABLE);
7715 if (tp->pci_chip_rev_id == CHIPREV_ID_5704_A0 &&
7716 tg3_flag(tp, PCIX_MODE))
7717 val |= PCISTATE_RETRY_SAME_DMA;
7718 /* Allow reads and writes to the APE register and memory space. */
7719 if (tg3_flag(tp, ENABLE_APE))
7720 val |= PCISTATE_ALLOW_APE_CTLSPC_WR |
7721 PCISTATE_ALLOW_APE_SHMEM_WR |
7722 PCISTATE_ALLOW_APE_PSPACE_WR;
7723 pci_write_config_dword(tp->pdev, TG3PCI_PCISTATE, val);
7725 pci_write_config_word(tp->pdev, PCI_COMMAND, tp->pci_cmd);
7727 if (!tg3_flag(tp, PCI_EXPRESS)) {
7728 pci_write_config_byte(tp->pdev, PCI_CACHE_LINE_SIZE,
7729 tp->pci_cacheline_sz);
7730 pci_write_config_byte(tp->pdev, PCI_LATENCY_TIMER,
7734 /* Make sure PCI-X relaxed ordering bit is clear. */
7735 if (tg3_flag(tp, PCIX_MODE)) {
7738 pci_read_config_word(tp->pdev, tp->pcix_cap + PCI_X_CMD,
7740 pcix_cmd &= ~PCI_X_CMD_ERO;
7741 pci_write_config_word(tp->pdev, tp->pcix_cap + PCI_X_CMD,
7745 if (tg3_flag(tp, 5780_CLASS)) {
7747 /* Chip reset on 5780 will reset MSI enable bit,
7748 * so need to restore it.
7750 if (tg3_flag(tp, USING_MSI)) {
7753 pci_read_config_word(tp->pdev,
7754 tp->msi_cap + PCI_MSI_FLAGS,
7756 pci_write_config_word(tp->pdev,
7757 tp->msi_cap + PCI_MSI_FLAGS,
7758 ctrl | PCI_MSI_FLAGS_ENABLE);
7759 val = tr32(MSGINT_MODE);
7760 tw32(MSGINT_MODE, val | MSGINT_MODE_ENABLE);
7765 /* tp->lock is held. */
7766 static int tg3_chip_reset(struct tg3 *tp)
7769 void (*write_op)(struct tg3 *, u32, u32);
7774 tg3_ape_lock(tp, TG3_APE_LOCK_GRC);
7776 /* No matching tg3_nvram_unlock() after this because
7777 * chip reset below will undo the nvram lock.
7779 tp->nvram_lock_cnt = 0;
7781 /* GRC_MISC_CFG core clock reset will clear the memory
7782 * enable bit in PCI register 4 and the MSI enable bit
7783 * on some chips, so we save relevant registers here.
7785 tg3_save_pci_state(tp);
7787 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5752 ||
7788 tg3_flag(tp, 5755_PLUS))
7789 tw32(GRC_FASTBOOT_PC, 0);
7792 * We must avoid the readl() that normally takes place.
7793 * It locks machines, causes machine checks, and other
7794 * fun things. So, temporarily disable the 5701
7795 * hardware workaround, while we do the reset.
7797 write_op = tp->write32;
7798 if (write_op == tg3_write_flush_reg32)
7799 tp->write32 = tg3_write32;
7801 /* Prevent the irq handler from reading or writing PCI registers
7802 * during chip reset when the memory enable bit in the PCI command
7803 * register may be cleared. The chip does not generate interrupt
7804 * at this time, but the irq handler may still be called due to irq
7805 * sharing or irqpoll.
7807 tg3_flag_set(tp, CHIP_RESETTING);
7808 for (i = 0; i < tp->irq_cnt; i++) {
7809 struct tg3_napi *tnapi = &tp->napi[i];
7810 if (tnapi->hw_status) {
7811 tnapi->hw_status->status = 0;
7812 tnapi->hw_status->status_tag = 0;
7814 tnapi->last_tag = 0;
7815 tnapi->last_irq_tag = 0;
7819 for (i = 0; i < tp->irq_cnt; i++)
7820 synchronize_irq(tp->napi[i].irq_vec);
7822 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57780) {
7823 val = tr32(TG3_PCIE_LNKCTL) & ~TG3_PCIE_LNKCTL_L1_PLL_PD_EN;
7824 tw32(TG3_PCIE_LNKCTL, val | TG3_PCIE_LNKCTL_L1_PLL_PD_DIS);
7828 val = GRC_MISC_CFG_CORECLK_RESET;
7830 if (tg3_flag(tp, PCI_EXPRESS)) {
7831 /* Force PCIe 1.0a mode */
7832 if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5785 &&
7833 !tg3_flag(tp, 57765_PLUS) &&
7834 tr32(TG3_PCIE_PHY_TSTCTL) ==
7835 (TG3_PCIE_PHY_TSTCTL_PCIE10 | TG3_PCIE_PHY_TSTCTL_PSCRAM))
7836 tw32(TG3_PCIE_PHY_TSTCTL, TG3_PCIE_PHY_TSTCTL_PSCRAM);
7838 if (tp->pci_chip_rev_id != CHIPREV_ID_5750_A0) {
7839 tw32(GRC_MISC_CFG, (1 << 29));
7844 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
7845 tw32(VCPU_STATUS, tr32(VCPU_STATUS) | VCPU_STATUS_DRV_RESET);
7846 tw32(GRC_VCPU_EXT_CTRL,
7847 tr32(GRC_VCPU_EXT_CTRL) & ~GRC_VCPU_EXT_CTRL_HALT_CPU);
7850 /* Manage gphy power for all CPMU absent PCIe devices. */
7851 if (tg3_flag(tp, 5705_PLUS) && !tg3_flag(tp, CPMU_PRESENT))
7852 val |= GRC_MISC_CFG_KEEP_GPHY_POWER;
7854 tw32(GRC_MISC_CFG, val);
7856 /* restore 5701 hardware bug workaround write method */
7857 tp->write32 = write_op;
7859 /* Unfortunately, we have to delay before the PCI read back.
7860 * Some 575X chips even will not respond to a PCI cfg access
7861 * when the reset command is given to the chip.
7863 * How do these hardware designers expect things to work
7864 * properly if the PCI write is posted for a long period
7865 * of time? It is always necessary to have some method by
7866 * which a register read back can occur to push the write
7867 * out which does the reset.
7869 * For most tg3 variants the trick below was working.
7874 /* Flush PCI posted writes. The normal MMIO registers
7875 * are inaccessible at this time so this is the only
7876 * way to make this reliably (actually, this is no longer
7877 * the case, see above). I tried to use indirect
7878 * register read/write but this upset some 5701 variants.
7880 pci_read_config_dword(tp->pdev, PCI_COMMAND, &val);
7884 if (tg3_flag(tp, PCI_EXPRESS) && pci_pcie_cap(tp->pdev)) {
7887 if (tp->pci_chip_rev_id == CHIPREV_ID_5750_A0) {
7891 /* Wait for link training to complete. */
7892 for (i = 0; i < 5000; i++)
7895 pci_read_config_dword(tp->pdev, 0xc4, &cfg_val);
7896 pci_write_config_dword(tp->pdev, 0xc4,
7897 cfg_val | (1 << 15));
7900 /* Clear the "no snoop" and "relaxed ordering" bits. */
7901 pci_read_config_word(tp->pdev,
7902 pci_pcie_cap(tp->pdev) + PCI_EXP_DEVCTL,
7904 val16 &= ~(PCI_EXP_DEVCTL_RELAX_EN |
7905 PCI_EXP_DEVCTL_NOSNOOP_EN);
7907 * Older PCIe devices only support the 128 byte
7908 * MPS setting. Enforce the restriction.
7910 if (!tg3_flag(tp, CPMU_PRESENT))
7911 val16 &= ~PCI_EXP_DEVCTL_PAYLOAD;
7912 pci_write_config_word(tp->pdev,
7913 pci_pcie_cap(tp->pdev) + PCI_EXP_DEVCTL,
7916 /* Clear error status */
7917 pci_write_config_word(tp->pdev,
7918 pci_pcie_cap(tp->pdev) + PCI_EXP_DEVSTA,
7919 PCI_EXP_DEVSTA_CED |
7920 PCI_EXP_DEVSTA_NFED |
7921 PCI_EXP_DEVSTA_FED |
7922 PCI_EXP_DEVSTA_URD);
7925 tg3_restore_pci_state(tp);
7927 tg3_flag_clear(tp, CHIP_RESETTING);
7928 tg3_flag_clear(tp, ERROR_PROCESSED);
7931 if (tg3_flag(tp, 5780_CLASS))
7932 val = tr32(MEMARB_MODE);
7933 tw32(MEMARB_MODE, val | MEMARB_MODE_ENABLE);
7935 if (tp->pci_chip_rev_id == CHIPREV_ID_5750_A3) {
7937 tw32(0x5000, 0x400);
7940 tw32(GRC_MODE, tp->grc_mode);
7942 if (tp->pci_chip_rev_id == CHIPREV_ID_5705_A0) {
7945 tw32(0xc4, val | (1 << 15));
7948 if ((tp->nic_sram_data_cfg & NIC_SRAM_DATA_CFG_MINI_PCI) != 0 &&
7949 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705) {
7950 tp->pci_clock_ctrl |= CLOCK_CTRL_CLKRUN_OENABLE;
7951 if (tp->pci_chip_rev_id == CHIPREV_ID_5705_A0)
7952 tp->pci_clock_ctrl |= CLOCK_CTRL_FORCE_CLKRUN;
7953 tw32(TG3PCI_CLOCK_CTRL, tp->pci_clock_ctrl);
7956 if (tp->phy_flags & TG3_PHYFLG_PHY_SERDES) {
7957 tp->mac_mode = MAC_MODE_PORT_MODE_TBI;
7959 } else if (tp->phy_flags & TG3_PHYFLG_MII_SERDES) {
7960 tp->mac_mode = MAC_MODE_PORT_MODE_GMII;
7965 tw32_f(MAC_MODE, val);
7968 tg3_ape_unlock(tp, TG3_APE_LOCK_GRC);
7970 err = tg3_poll_fw(tp);
7976 if (tg3_flag(tp, PCI_EXPRESS) &&
7977 tp->pci_chip_rev_id != CHIPREV_ID_5750_A0 &&
7978 GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5785 &&
7979 !tg3_flag(tp, 57765_PLUS)) {
7982 tw32(0x7c00, val | (1 << 25));
7985 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5720) {
7986 val = tr32(TG3_CPMU_CLCK_ORIDE);
7987 tw32(TG3_CPMU_CLCK_ORIDE, val & ~CPMU_CLCK_ORIDE_MAC_ORIDE_EN);
7990 /* Reprobe ASF enable state. */
7991 tg3_flag_clear(tp, ENABLE_ASF);
7992 tg3_flag_clear(tp, ASF_NEW_HANDSHAKE);
7993 tg3_read_mem(tp, NIC_SRAM_DATA_SIG, &val);
7994 if (val == NIC_SRAM_DATA_SIG_MAGIC) {
7997 tg3_read_mem(tp, NIC_SRAM_DATA_CFG, &nic_cfg);
7998 if (nic_cfg & NIC_SRAM_DATA_CFG_ASF_ENABLE) {
7999 tg3_flag_set(tp, ENABLE_ASF);
8000 tp->last_event_jiffies = jiffies;
8001 if (tg3_flag(tp, 5750_PLUS))
8002 tg3_flag_set(tp, ASF_NEW_HANDSHAKE);
8009 static struct rtnl_link_stats64 *tg3_get_stats64(struct net_device *,
8010 struct rtnl_link_stats64 *);
8011 static struct tg3_ethtool_stats *tg3_get_estats(struct tg3 *,
8012 struct tg3_ethtool_stats *);
8014 /* tp->lock is held. */
8015 static int tg3_halt(struct tg3 *tp, int kind, int silent)
8021 tg3_write_sig_pre_reset(tp, kind);
8023 tg3_abort_hw(tp, silent);
8024 err = tg3_chip_reset(tp);
8026 __tg3_set_mac_addr(tp, 0);
8028 tg3_write_sig_legacy(tp, kind);
8029 tg3_write_sig_post_reset(tp, kind);
8032 /* Save the stats across chip resets... */
8033 tg3_get_stats64(tp->dev, &tp->net_stats_prev),
8034 tg3_get_estats(tp, &tp->estats_prev);
8036 /* And make sure the next sample is new data */
8037 memset(tp->hw_stats, 0, sizeof(struct tg3_hw_stats));
8046 static int tg3_set_mac_addr(struct net_device *dev, void *p)
8048 struct tg3 *tp = netdev_priv(dev);
8049 struct sockaddr *addr = p;
8050 int err = 0, skip_mac_1 = 0;
8052 if (!is_valid_ether_addr(addr->sa_data))
8055 memcpy(dev->dev_addr, addr->sa_data, dev->addr_len);
8057 if (!netif_running(dev))
8060 if (tg3_flag(tp, ENABLE_ASF)) {
8061 u32 addr0_high, addr0_low, addr1_high, addr1_low;
8063 addr0_high = tr32(MAC_ADDR_0_HIGH);
8064 addr0_low = tr32(MAC_ADDR_0_LOW);
8065 addr1_high = tr32(MAC_ADDR_1_HIGH);
8066 addr1_low = tr32(MAC_ADDR_1_LOW);
8068 /* Skip MAC addr 1 if ASF is using it. */
8069 if ((addr0_high != addr1_high || addr0_low != addr1_low) &&
8070 !(addr1_high == 0 && addr1_low == 0))
8073 spin_lock_bh(&tp->lock);
8074 __tg3_set_mac_addr(tp, skip_mac_1);
8075 spin_unlock_bh(&tp->lock);
8080 /* tp->lock is held. */
8081 static void tg3_set_bdinfo(struct tg3 *tp, u32 bdinfo_addr,
8082 dma_addr_t mapping, u32 maxlen_flags,
8086 (bdinfo_addr + TG3_BDINFO_HOST_ADDR + TG3_64BIT_REG_HIGH),
8087 ((u64) mapping >> 32));
8089 (bdinfo_addr + TG3_BDINFO_HOST_ADDR + TG3_64BIT_REG_LOW),
8090 ((u64) mapping & 0xffffffff));
8092 (bdinfo_addr + TG3_BDINFO_MAXLEN_FLAGS),
8095 if (!tg3_flag(tp, 5705_PLUS))
8097 (bdinfo_addr + TG3_BDINFO_NIC_ADDR),
8101 static void __tg3_set_coalesce(struct tg3 *tp, struct ethtool_coalesce *ec)
8105 if (!tg3_flag(tp, ENABLE_TSS)) {
8106 tw32(HOSTCC_TXCOL_TICKS, ec->tx_coalesce_usecs);
8107 tw32(HOSTCC_TXMAX_FRAMES, ec->tx_max_coalesced_frames);
8108 tw32(HOSTCC_TXCOAL_MAXF_INT, ec->tx_max_coalesced_frames_irq);
8110 tw32(HOSTCC_TXCOL_TICKS, 0);
8111 tw32(HOSTCC_TXMAX_FRAMES, 0);
8112 tw32(HOSTCC_TXCOAL_MAXF_INT, 0);
8115 if (!tg3_flag(tp, ENABLE_RSS)) {
8116 tw32(HOSTCC_RXCOL_TICKS, ec->rx_coalesce_usecs);
8117 tw32(HOSTCC_RXMAX_FRAMES, ec->rx_max_coalesced_frames);
8118 tw32(HOSTCC_RXCOAL_MAXF_INT, ec->rx_max_coalesced_frames_irq);
8120 tw32(HOSTCC_RXCOL_TICKS, 0);
8121 tw32(HOSTCC_RXMAX_FRAMES, 0);
8122 tw32(HOSTCC_RXCOAL_MAXF_INT, 0);
8125 if (!tg3_flag(tp, 5705_PLUS)) {
8126 u32 val = ec->stats_block_coalesce_usecs;
8128 tw32(HOSTCC_RXCOAL_TICK_INT, ec->rx_coalesce_usecs_irq);
8129 tw32(HOSTCC_TXCOAL_TICK_INT, ec->tx_coalesce_usecs_irq);
8131 if (!netif_carrier_ok(tp->dev))
8134 tw32(HOSTCC_STAT_COAL_TICKS, val);
8137 for (i = 0; i < tp->irq_cnt - 1; i++) {
8140 reg = HOSTCC_RXCOL_TICKS_VEC1 + i * 0x18;
8141 tw32(reg, ec->rx_coalesce_usecs);
8142 reg = HOSTCC_RXMAX_FRAMES_VEC1 + i * 0x18;
8143 tw32(reg, ec->rx_max_coalesced_frames);
8144 reg = HOSTCC_RXCOAL_MAXF_INT_VEC1 + i * 0x18;
8145 tw32(reg, ec->rx_max_coalesced_frames_irq);
8147 if (tg3_flag(tp, ENABLE_TSS)) {
8148 reg = HOSTCC_TXCOL_TICKS_VEC1 + i * 0x18;
8149 tw32(reg, ec->tx_coalesce_usecs);
8150 reg = HOSTCC_TXMAX_FRAMES_VEC1 + i * 0x18;
8151 tw32(reg, ec->tx_max_coalesced_frames);
8152 reg = HOSTCC_TXCOAL_MAXF_INT_VEC1 + i * 0x18;
8153 tw32(reg, ec->tx_max_coalesced_frames_irq);
8157 for (; i < tp->irq_max - 1; i++) {
8158 tw32(HOSTCC_RXCOL_TICKS_VEC1 + i * 0x18, 0);
8159 tw32(HOSTCC_RXMAX_FRAMES_VEC1 + i * 0x18, 0);
8160 tw32(HOSTCC_RXCOAL_MAXF_INT_VEC1 + i * 0x18, 0);
8162 if (tg3_flag(tp, ENABLE_TSS)) {
8163 tw32(HOSTCC_TXCOL_TICKS_VEC1 + i * 0x18, 0);
8164 tw32(HOSTCC_TXMAX_FRAMES_VEC1 + i * 0x18, 0);
8165 tw32(HOSTCC_TXCOAL_MAXF_INT_VEC1 + i * 0x18, 0);
8170 /* tp->lock is held. */
8171 static void tg3_rings_reset(struct tg3 *tp)
8174 u32 stblk, txrcb, rxrcb, limit;
8175 struct tg3_napi *tnapi = &tp->napi[0];
8177 /* Disable all transmit rings but the first. */
8178 if (!tg3_flag(tp, 5705_PLUS))
8179 limit = NIC_SRAM_SEND_RCB + TG3_BDINFO_SIZE * 16;
8180 else if (tg3_flag(tp, 5717_PLUS))
8181 limit = NIC_SRAM_SEND_RCB + TG3_BDINFO_SIZE * 4;
8182 else if (tg3_flag(tp, 57765_CLASS))
8183 limit = NIC_SRAM_SEND_RCB + TG3_BDINFO_SIZE * 2;
8185 limit = NIC_SRAM_SEND_RCB + TG3_BDINFO_SIZE;
8187 for (txrcb = NIC_SRAM_SEND_RCB + TG3_BDINFO_SIZE;
8188 txrcb < limit; txrcb += TG3_BDINFO_SIZE)
8189 tg3_write_mem(tp, txrcb + TG3_BDINFO_MAXLEN_FLAGS,
8190 BDINFO_FLAGS_DISABLED);
8193 /* Disable all receive return rings but the first. */
8194 if (tg3_flag(tp, 5717_PLUS))
8195 limit = NIC_SRAM_RCV_RET_RCB + TG3_BDINFO_SIZE * 17;
8196 else if (!tg3_flag(tp, 5705_PLUS))
8197 limit = NIC_SRAM_RCV_RET_RCB + TG3_BDINFO_SIZE * 16;
8198 else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5755 ||
8199 tg3_flag(tp, 57765_CLASS))
8200 limit = NIC_SRAM_RCV_RET_RCB + TG3_BDINFO_SIZE * 4;
8202 limit = NIC_SRAM_RCV_RET_RCB + TG3_BDINFO_SIZE;
8204 for (rxrcb = NIC_SRAM_RCV_RET_RCB + TG3_BDINFO_SIZE;
8205 rxrcb < limit; rxrcb += TG3_BDINFO_SIZE)
8206 tg3_write_mem(tp, rxrcb + TG3_BDINFO_MAXLEN_FLAGS,
8207 BDINFO_FLAGS_DISABLED);
8209 /* Disable interrupts */
8210 tw32_mailbox_f(tp->napi[0].int_mbox, 1);
8211 tp->napi[0].chk_msi_cnt = 0;
8212 tp->napi[0].last_rx_cons = 0;
8213 tp->napi[0].last_tx_cons = 0;
8215 /* Zero mailbox registers. */
8216 if (tg3_flag(tp, SUPPORT_MSIX)) {
8217 for (i = 1; i < tp->irq_max; i++) {
8218 tp->napi[i].tx_prod = 0;
8219 tp->napi[i].tx_cons = 0;
8220 if (tg3_flag(tp, ENABLE_TSS))
8221 tw32_mailbox(tp->napi[i].prodmbox, 0);
8222 tw32_rx_mbox(tp->napi[i].consmbox, 0);
8223 tw32_mailbox_f(tp->napi[i].int_mbox, 1);
8224 tp->napi[i].chk_msi_cnt = 0;
8225 tp->napi[i].last_rx_cons = 0;
8226 tp->napi[i].last_tx_cons = 0;
8228 if (!tg3_flag(tp, ENABLE_TSS))
8229 tw32_mailbox(tp->napi[0].prodmbox, 0);
8231 tp->napi[0].tx_prod = 0;
8232 tp->napi[0].tx_cons = 0;
8233 tw32_mailbox(tp->napi[0].prodmbox, 0);
8234 tw32_rx_mbox(tp->napi[0].consmbox, 0);
8237 /* Make sure the NIC-based send BD rings are disabled. */
8238 if (!tg3_flag(tp, 5705_PLUS)) {
8239 u32 mbox = MAILBOX_SNDNIC_PROD_IDX_0 + TG3_64BIT_REG_LOW;
8240 for (i = 0; i < 16; i++)
8241 tw32_tx_mbox(mbox + i * 8, 0);
8244 txrcb = NIC_SRAM_SEND_RCB;
8245 rxrcb = NIC_SRAM_RCV_RET_RCB;
8247 /* Clear status block in ram. */
8248 memset(tnapi->hw_status, 0, TG3_HW_STATUS_SIZE);
8250 /* Set status block DMA address */
8251 tw32(HOSTCC_STATUS_BLK_HOST_ADDR + TG3_64BIT_REG_HIGH,
8252 ((u64) tnapi->status_mapping >> 32));
8253 tw32(HOSTCC_STATUS_BLK_HOST_ADDR + TG3_64BIT_REG_LOW,
8254 ((u64) tnapi->status_mapping & 0xffffffff));
8256 if (tnapi->tx_ring) {
8257 tg3_set_bdinfo(tp, txrcb, tnapi->tx_desc_mapping,
8258 (TG3_TX_RING_SIZE <<
8259 BDINFO_FLAGS_MAXLEN_SHIFT),
8260 NIC_SRAM_TX_BUFFER_DESC);
8261 txrcb += TG3_BDINFO_SIZE;
8264 if (tnapi->rx_rcb) {
8265 tg3_set_bdinfo(tp, rxrcb, tnapi->rx_rcb_mapping,
8266 (tp->rx_ret_ring_mask + 1) <<
8267 BDINFO_FLAGS_MAXLEN_SHIFT, 0);
8268 rxrcb += TG3_BDINFO_SIZE;
8271 stblk = HOSTCC_STATBLCK_RING1;
8273 for (i = 1, tnapi++; i < tp->irq_cnt; i++, tnapi++) {
8274 u64 mapping = (u64)tnapi->status_mapping;
8275 tw32(stblk + TG3_64BIT_REG_HIGH, mapping >> 32);
8276 tw32(stblk + TG3_64BIT_REG_LOW, mapping & 0xffffffff);
8278 /* Clear status block in ram. */
8279 memset(tnapi->hw_status, 0, TG3_HW_STATUS_SIZE);
8281 if (tnapi->tx_ring) {
8282 tg3_set_bdinfo(tp, txrcb, tnapi->tx_desc_mapping,
8283 (TG3_TX_RING_SIZE <<
8284 BDINFO_FLAGS_MAXLEN_SHIFT),
8285 NIC_SRAM_TX_BUFFER_DESC);
8286 txrcb += TG3_BDINFO_SIZE;
8289 tg3_set_bdinfo(tp, rxrcb, tnapi->rx_rcb_mapping,
8290 ((tp->rx_ret_ring_mask + 1) <<
8291 BDINFO_FLAGS_MAXLEN_SHIFT), 0);
8294 rxrcb += TG3_BDINFO_SIZE;
8298 static void tg3_setup_rxbd_thresholds(struct tg3 *tp)
8300 u32 val, bdcache_maxcnt, host_rep_thresh, nic_rep_thresh;
8302 if (!tg3_flag(tp, 5750_PLUS) ||
8303 tg3_flag(tp, 5780_CLASS) ||
8304 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5750 ||
8305 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5752 ||
8306 tg3_flag(tp, 57765_PLUS))
8307 bdcache_maxcnt = TG3_SRAM_RX_STD_BDCACHE_SIZE_5700;
8308 else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5755 ||
8309 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5787)
8310 bdcache_maxcnt = TG3_SRAM_RX_STD_BDCACHE_SIZE_5755;
8312 bdcache_maxcnt = TG3_SRAM_RX_STD_BDCACHE_SIZE_5906;
8314 nic_rep_thresh = min(bdcache_maxcnt / 2, tp->rx_std_max_post);
8315 host_rep_thresh = max_t(u32, tp->rx_pending / 8, 1);
8317 val = min(nic_rep_thresh, host_rep_thresh);
8318 tw32(RCVBDI_STD_THRESH, val);
8320 if (tg3_flag(tp, 57765_PLUS))
8321 tw32(STD_REPLENISH_LWM, bdcache_maxcnt);
8323 if (!tg3_flag(tp, JUMBO_CAPABLE) || tg3_flag(tp, 5780_CLASS))
8326 bdcache_maxcnt = TG3_SRAM_RX_JMB_BDCACHE_SIZE_5700;
8328 host_rep_thresh = max_t(u32, tp->rx_jumbo_pending / 8, 1);
8330 val = min(bdcache_maxcnt / 2, host_rep_thresh);
8331 tw32(RCVBDI_JUMBO_THRESH, val);
8333 if (tg3_flag(tp, 57765_PLUS))
8334 tw32(JMB_REPLENISH_LWM, bdcache_maxcnt);
8337 static inline u32 calc_crc(unsigned char *buf, int len)
8345 for (j = 0; j < len; j++) {
8348 for (k = 0; k < 8; k++) {
8361 static void tg3_set_multi(struct tg3 *tp, unsigned int accept_all)
8363 /* accept or reject all multicast frames */
8364 tw32(MAC_HASH_REG_0, accept_all ? 0xffffffff : 0);
8365 tw32(MAC_HASH_REG_1, accept_all ? 0xffffffff : 0);
8366 tw32(MAC_HASH_REG_2, accept_all ? 0xffffffff : 0);
8367 tw32(MAC_HASH_REG_3, accept_all ? 0xffffffff : 0);
8370 static void __tg3_set_rx_mode(struct net_device *dev)
8372 struct tg3 *tp = netdev_priv(dev);
8375 rx_mode = tp->rx_mode & ~(RX_MODE_PROMISC |
8376 RX_MODE_KEEP_VLAN_TAG);
8378 #if !defined(CONFIG_VLAN_8021Q) && !defined(CONFIG_VLAN_8021Q_MODULE)
8379 /* When ASF is in use, we always keep the RX_MODE_KEEP_VLAN_TAG
8382 if (!tg3_flag(tp, ENABLE_ASF))
8383 rx_mode |= RX_MODE_KEEP_VLAN_TAG;
8386 if (dev->flags & IFF_PROMISC) {
8387 /* Promiscuous mode. */
8388 rx_mode |= RX_MODE_PROMISC;
8389 } else if (dev->flags & IFF_ALLMULTI) {
8390 /* Accept all multicast. */
8391 tg3_set_multi(tp, 1);
8392 } else if (netdev_mc_empty(dev)) {
8393 /* Reject all multicast. */
8394 tg3_set_multi(tp, 0);
8396 /* Accept one or more multicast(s). */
8397 struct netdev_hw_addr *ha;
8398 u32 mc_filter[4] = { 0, };
8403 netdev_for_each_mc_addr(ha, dev) {
8404 crc = calc_crc(ha->addr, ETH_ALEN);
8406 regidx = (bit & 0x60) >> 5;
8408 mc_filter[regidx] |= (1 << bit);
8411 tw32(MAC_HASH_REG_0, mc_filter[0]);
8412 tw32(MAC_HASH_REG_1, mc_filter[1]);
8413 tw32(MAC_HASH_REG_2, mc_filter[2]);
8414 tw32(MAC_HASH_REG_3, mc_filter[3]);
8417 if (rx_mode != tp->rx_mode) {
8418 tp->rx_mode = rx_mode;
8419 tw32_f(MAC_RX_MODE, rx_mode);
8424 static void tg3_rss_init_dflt_indir_tbl(struct tg3 *tp)
8428 for (i = 0; i < TG3_RSS_INDIR_TBL_SIZE; i++)
8429 tp->rss_ind_tbl[i] =
8430 ethtool_rxfh_indir_default(i, tp->irq_cnt - 1);
8433 static void tg3_rss_check_indir_tbl(struct tg3 *tp)
8437 if (!tg3_flag(tp, SUPPORT_MSIX))
8440 if (tp->irq_cnt <= 2) {
8441 memset(&tp->rss_ind_tbl[0], 0, sizeof(tp->rss_ind_tbl));
8445 /* Validate table against current IRQ count */
8446 for (i = 0; i < TG3_RSS_INDIR_TBL_SIZE; i++) {
8447 if (tp->rss_ind_tbl[i] >= tp->irq_cnt - 1)
8451 if (i != TG3_RSS_INDIR_TBL_SIZE)
8452 tg3_rss_init_dflt_indir_tbl(tp);
8455 static void tg3_rss_write_indir_tbl(struct tg3 *tp)
8458 u32 reg = MAC_RSS_INDIR_TBL_0;
8460 while (i < TG3_RSS_INDIR_TBL_SIZE) {
8461 u32 val = tp->rss_ind_tbl[i];
8463 for (; i % 8; i++) {
8465 val |= tp->rss_ind_tbl[i];
8472 /* tp->lock is held. */
8473 static int tg3_reset_hw(struct tg3 *tp, int reset_phy)
8475 u32 val, rdmac_mode;
8477 struct tg3_rx_prodring_set *tpr = &tp->napi[0].prodring;
8479 tg3_disable_ints(tp);
8483 tg3_write_sig_pre_reset(tp, RESET_KIND_INIT);
8485 if (tg3_flag(tp, INIT_COMPLETE))
8486 tg3_abort_hw(tp, 1);
8488 /* Enable MAC control of LPI */
8489 if (tp->phy_flags & TG3_PHYFLG_EEE_CAP) {
8490 tw32_f(TG3_CPMU_EEE_LNKIDL_CTRL,
8491 TG3_CPMU_EEE_LNKIDL_PCIE_NL0 |
8492 TG3_CPMU_EEE_LNKIDL_UART_IDL);
8494 tw32_f(TG3_CPMU_EEE_CTRL,
8495 TG3_CPMU_EEE_CTRL_EXIT_20_1_US);
8497 val = TG3_CPMU_EEEMD_ERLY_L1_XIT_DET |
8498 TG3_CPMU_EEEMD_LPI_IN_TX |
8499 TG3_CPMU_EEEMD_LPI_IN_RX |
8500 TG3_CPMU_EEEMD_EEE_ENABLE;
8502 if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5717)
8503 val |= TG3_CPMU_EEEMD_SND_IDX_DET_EN;
8505 if (tg3_flag(tp, ENABLE_APE))
8506 val |= TG3_CPMU_EEEMD_APE_TX_DET_EN;
8508 tw32_f(TG3_CPMU_EEE_MODE, val);
8510 tw32_f(TG3_CPMU_EEE_DBTMR1,
8511 TG3_CPMU_DBTMR1_PCIEXIT_2047US |
8512 TG3_CPMU_DBTMR1_LNKIDLE_2047US);
8514 tw32_f(TG3_CPMU_EEE_DBTMR2,
8515 TG3_CPMU_DBTMR2_APE_TX_2047US |
8516 TG3_CPMU_DBTMR2_TXIDXEQ_2047US);
8522 err = tg3_chip_reset(tp);
8526 tg3_write_sig_legacy(tp, RESET_KIND_INIT);
8528 if (GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5784_AX) {
8529 val = tr32(TG3_CPMU_CTRL);
8530 val &= ~(CPMU_CTRL_LINK_AWARE_MODE | CPMU_CTRL_LINK_IDLE_MODE);
8531 tw32(TG3_CPMU_CTRL, val);
8533 val = tr32(TG3_CPMU_LSPD_10MB_CLK);
8534 val &= ~CPMU_LSPD_10MB_MACCLK_MASK;
8535 val |= CPMU_LSPD_10MB_MACCLK_6_25;
8536 tw32(TG3_CPMU_LSPD_10MB_CLK, val);
8538 val = tr32(TG3_CPMU_LNK_AWARE_PWRMD);
8539 val &= ~CPMU_LNK_AWARE_MACCLK_MASK;
8540 val |= CPMU_LNK_AWARE_MACCLK_6_25;
8541 tw32(TG3_CPMU_LNK_AWARE_PWRMD, val);
8543 val = tr32(TG3_CPMU_HST_ACC);
8544 val &= ~CPMU_HST_ACC_MACCLK_MASK;
8545 val |= CPMU_HST_ACC_MACCLK_6_25;
8546 tw32(TG3_CPMU_HST_ACC, val);
8549 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57780) {
8550 val = tr32(PCIE_PWR_MGMT_THRESH) & ~PCIE_PWR_MGMT_L1_THRESH_MSK;
8551 val |= PCIE_PWR_MGMT_EXT_ASPM_TMR_EN |
8552 PCIE_PWR_MGMT_L1_THRESH_4MS;
8553 tw32(PCIE_PWR_MGMT_THRESH, val);
8555 val = tr32(TG3_PCIE_EIDLE_DELAY) & ~TG3_PCIE_EIDLE_DELAY_MASK;
8556 tw32(TG3_PCIE_EIDLE_DELAY, val | TG3_PCIE_EIDLE_DELAY_13_CLKS);
8558 tw32(TG3_CORR_ERR_STAT, TG3_CORR_ERR_STAT_CLEAR);
8560 val = tr32(TG3_PCIE_LNKCTL) & ~TG3_PCIE_LNKCTL_L1_PLL_PD_EN;
8561 tw32(TG3_PCIE_LNKCTL, val | TG3_PCIE_LNKCTL_L1_PLL_PD_DIS);
8564 if (tg3_flag(tp, L1PLLPD_EN)) {
8565 u32 grc_mode = tr32(GRC_MODE);
8567 /* Access the lower 1K of PL PCIE block registers. */
8568 val = grc_mode & ~GRC_MODE_PCIE_PORT_MASK;
8569 tw32(GRC_MODE, val | GRC_MODE_PCIE_PL_SEL);
8571 val = tr32(TG3_PCIE_TLDLPL_PORT + TG3_PCIE_PL_LO_PHYCTL1);
8572 tw32(TG3_PCIE_TLDLPL_PORT + TG3_PCIE_PL_LO_PHYCTL1,
8573 val | TG3_PCIE_PL_LO_PHYCTL1_L1PLLPD_EN);
8575 tw32(GRC_MODE, grc_mode);
8578 if (tg3_flag(tp, 57765_CLASS)) {
8579 if (tp->pci_chip_rev_id == CHIPREV_ID_57765_A0) {
8580 u32 grc_mode = tr32(GRC_MODE);
8582 /* Access the lower 1K of PL PCIE block registers. */
8583 val = grc_mode & ~GRC_MODE_PCIE_PORT_MASK;
8584 tw32(GRC_MODE, val | GRC_MODE_PCIE_PL_SEL);
8586 val = tr32(TG3_PCIE_TLDLPL_PORT +
8587 TG3_PCIE_PL_LO_PHYCTL5);
8588 tw32(TG3_PCIE_TLDLPL_PORT + TG3_PCIE_PL_LO_PHYCTL5,
8589 val | TG3_PCIE_PL_LO_PHYCTL5_DIS_L2CLKREQ);
8591 tw32(GRC_MODE, grc_mode);
8594 if (GET_CHIP_REV(tp->pci_chip_rev_id) != CHIPREV_57765_AX) {
8595 u32 grc_mode = tr32(GRC_MODE);
8597 /* Access the lower 1K of DL PCIE block registers. */
8598 val = grc_mode & ~GRC_MODE_PCIE_PORT_MASK;
8599 tw32(GRC_MODE, val | GRC_MODE_PCIE_DL_SEL);
8601 val = tr32(TG3_PCIE_TLDLPL_PORT +
8602 TG3_PCIE_DL_LO_FTSMAX);
8603 val &= ~TG3_PCIE_DL_LO_FTSMAX_MSK;
8604 tw32(TG3_PCIE_TLDLPL_PORT + TG3_PCIE_DL_LO_FTSMAX,
8605 val | TG3_PCIE_DL_LO_FTSMAX_VAL);
8607 tw32(GRC_MODE, grc_mode);
8610 val = tr32(TG3_CPMU_LSPD_10MB_CLK);
8611 val &= ~CPMU_LSPD_10MB_MACCLK_MASK;
8612 val |= CPMU_LSPD_10MB_MACCLK_6_25;
8613 tw32(TG3_CPMU_LSPD_10MB_CLK, val);
8616 /* This works around an issue with Athlon chipsets on
8617 * B3 tigon3 silicon. This bit has no effect on any
8618 * other revision. But do not set this on PCI Express
8619 * chips and don't even touch the clocks if the CPMU is present.
8621 if (!tg3_flag(tp, CPMU_PRESENT)) {
8622 if (!tg3_flag(tp, PCI_EXPRESS))
8623 tp->pci_clock_ctrl |= CLOCK_CTRL_DELAY_PCI_GRANT;
8624 tw32_f(TG3PCI_CLOCK_CTRL, tp->pci_clock_ctrl);
8627 if (tp->pci_chip_rev_id == CHIPREV_ID_5704_A0 &&
8628 tg3_flag(tp, PCIX_MODE)) {
8629 val = tr32(TG3PCI_PCISTATE);
8630 val |= PCISTATE_RETRY_SAME_DMA;
8631 tw32(TG3PCI_PCISTATE, val);
8634 if (tg3_flag(tp, ENABLE_APE)) {
8635 /* Allow reads and writes to the
8636 * APE register and memory space.
8638 val = tr32(TG3PCI_PCISTATE);
8639 val |= PCISTATE_ALLOW_APE_CTLSPC_WR |
8640 PCISTATE_ALLOW_APE_SHMEM_WR |
8641 PCISTATE_ALLOW_APE_PSPACE_WR;
8642 tw32(TG3PCI_PCISTATE, val);
8645 if (GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5704_BX) {
8646 /* Enable some hw fixes. */
8647 val = tr32(TG3PCI_MSI_DATA);
8648 val |= (1 << 26) | (1 << 28) | (1 << 29);
8649 tw32(TG3PCI_MSI_DATA, val);
8652 /* Descriptor ring init may make accesses to the
8653 * NIC SRAM area to setup the TX descriptors, so we
8654 * can only do this after the hardware has been
8655 * successfully reset.
8657 err = tg3_init_rings(tp);
8661 if (tg3_flag(tp, 57765_PLUS)) {
8662 val = tr32(TG3PCI_DMA_RW_CTRL) &
8663 ~DMA_RWCTRL_DIS_CACHE_ALIGNMENT;
8664 if (tp->pci_chip_rev_id == CHIPREV_ID_57765_A0)
8665 val &= ~DMA_RWCTRL_CRDRDR_RDMA_MRRS_MSK;
8666 if (!tg3_flag(tp, 57765_CLASS) &&
8667 GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5717)
8668 val |= DMA_RWCTRL_TAGGED_STAT_WA;
8669 tw32(TG3PCI_DMA_RW_CTRL, val | tp->dma_rwctrl);
8670 } else if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5784 &&
8671 GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5761) {
8672 /* This value is determined during the probe time DMA
8673 * engine test, tg3_test_dma.
8675 tw32(TG3PCI_DMA_RW_CTRL, tp->dma_rwctrl);
8678 tp->grc_mode &= ~(GRC_MODE_HOST_SENDBDS |
8679 GRC_MODE_4X_NIC_SEND_RINGS |
8680 GRC_MODE_NO_TX_PHDR_CSUM |
8681 GRC_MODE_NO_RX_PHDR_CSUM);
8682 tp->grc_mode |= GRC_MODE_HOST_SENDBDS;
8684 /* Pseudo-header checksum is done by hardware logic and not
8685 * the offload processers, so make the chip do the pseudo-
8686 * header checksums on receive. For transmit it is more
8687 * convenient to do the pseudo-header checksum in software
8688 * as Linux does that on transmit for us in all cases.
8690 tp->grc_mode |= GRC_MODE_NO_TX_PHDR_CSUM;
8694 (GRC_MODE_IRQ_ON_MAC_ATTN | GRC_MODE_HOST_STACKUP));
8696 /* Setup the timer prescalar register. Clock is always 66Mhz. */
8697 val = tr32(GRC_MISC_CFG);
8699 val |= (65 << GRC_MISC_CFG_PRESCALAR_SHIFT);
8700 tw32(GRC_MISC_CFG, val);
8702 /* Initialize MBUF/DESC pool. */
8703 if (tg3_flag(tp, 5750_PLUS)) {
8705 } else if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5705) {
8706 tw32(BUFMGR_MB_POOL_ADDR, NIC_SRAM_MBUF_POOL_BASE);
8707 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704)
8708 tw32(BUFMGR_MB_POOL_SIZE, NIC_SRAM_MBUF_POOL_SIZE64);
8710 tw32(BUFMGR_MB_POOL_SIZE, NIC_SRAM_MBUF_POOL_SIZE96);
8711 tw32(BUFMGR_DMA_DESC_POOL_ADDR, NIC_SRAM_DMA_DESC_POOL_BASE);
8712 tw32(BUFMGR_DMA_DESC_POOL_SIZE, NIC_SRAM_DMA_DESC_POOL_SIZE);
8713 } else if (tg3_flag(tp, TSO_CAPABLE)) {
8716 fw_len = tp->fw_len;
8717 fw_len = (fw_len + (0x80 - 1)) & ~(0x80 - 1);
8718 tw32(BUFMGR_MB_POOL_ADDR,
8719 NIC_SRAM_MBUF_POOL_BASE5705 + fw_len);
8720 tw32(BUFMGR_MB_POOL_SIZE,
8721 NIC_SRAM_MBUF_POOL_SIZE5705 - fw_len - 0xa00);
8724 if (tp->dev->mtu <= ETH_DATA_LEN) {
8725 tw32(BUFMGR_MB_RDMA_LOW_WATER,
8726 tp->bufmgr_config.mbuf_read_dma_low_water);
8727 tw32(BUFMGR_MB_MACRX_LOW_WATER,
8728 tp->bufmgr_config.mbuf_mac_rx_low_water);
8729 tw32(BUFMGR_MB_HIGH_WATER,
8730 tp->bufmgr_config.mbuf_high_water);
8732 tw32(BUFMGR_MB_RDMA_LOW_WATER,
8733 tp->bufmgr_config.mbuf_read_dma_low_water_jumbo);
8734 tw32(BUFMGR_MB_MACRX_LOW_WATER,
8735 tp->bufmgr_config.mbuf_mac_rx_low_water_jumbo);
8736 tw32(BUFMGR_MB_HIGH_WATER,
8737 tp->bufmgr_config.mbuf_high_water_jumbo);
8739 tw32(BUFMGR_DMA_LOW_WATER,
8740 tp->bufmgr_config.dma_low_water);
8741 tw32(BUFMGR_DMA_HIGH_WATER,
8742 tp->bufmgr_config.dma_high_water);
8744 val = BUFMGR_MODE_ENABLE | BUFMGR_MODE_ATTN_ENABLE;
8745 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5719)
8746 val |= BUFMGR_MODE_NO_TX_UNDERRUN;
8747 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717 ||
8748 tp->pci_chip_rev_id == CHIPREV_ID_5719_A0 ||
8749 tp->pci_chip_rev_id == CHIPREV_ID_5720_A0)
8750 val |= BUFMGR_MODE_MBLOW_ATTN_ENAB;
8751 tw32(BUFMGR_MODE, val);
8752 for (i = 0; i < 2000; i++) {
8753 if (tr32(BUFMGR_MODE) & BUFMGR_MODE_ENABLE)
8758 netdev_err(tp->dev, "%s cannot enable BUFMGR\n", __func__);
8762 if (tp->pci_chip_rev_id == CHIPREV_ID_5906_A1)
8763 tw32(ISO_PKT_TX, (tr32(ISO_PKT_TX) & ~0x3) | 0x2);
8765 tg3_setup_rxbd_thresholds(tp);
8767 /* Initialize TG3_BDINFO's at:
8768 * RCVDBDI_STD_BD: standard eth size rx ring
8769 * RCVDBDI_JUMBO_BD: jumbo frame rx ring
8770 * RCVDBDI_MINI_BD: small frame rx ring (??? does not work)
8773 * TG3_BDINFO_HOST_ADDR: high/low parts of DMA address of ring
8774 * TG3_BDINFO_MAXLEN_FLAGS: (rx max buffer size << 16) |
8775 * ring attribute flags
8776 * TG3_BDINFO_NIC_ADDR: location of descriptors in nic SRAM
8778 * Standard receive ring @ NIC_SRAM_RX_BUFFER_DESC, 512 entries.
8779 * Jumbo receive ring @ NIC_SRAM_RX_JUMBO_BUFFER_DESC, 256 entries.
8781 * The size of each ring is fixed in the firmware, but the location is
8784 tw32(RCVDBDI_STD_BD + TG3_BDINFO_HOST_ADDR + TG3_64BIT_REG_HIGH,
8785 ((u64) tpr->rx_std_mapping >> 32));
8786 tw32(RCVDBDI_STD_BD + TG3_BDINFO_HOST_ADDR + TG3_64BIT_REG_LOW,
8787 ((u64) tpr->rx_std_mapping & 0xffffffff));
8788 if (!tg3_flag(tp, 5717_PLUS))
8789 tw32(RCVDBDI_STD_BD + TG3_BDINFO_NIC_ADDR,
8790 NIC_SRAM_RX_BUFFER_DESC);
8792 /* Disable the mini ring */
8793 if (!tg3_flag(tp, 5705_PLUS))
8794 tw32(RCVDBDI_MINI_BD + TG3_BDINFO_MAXLEN_FLAGS,
8795 BDINFO_FLAGS_DISABLED);
8797 /* Program the jumbo buffer descriptor ring control
8798 * blocks on those devices that have them.
8800 if (tp->pci_chip_rev_id == CHIPREV_ID_5719_A0 ||
8801 (tg3_flag(tp, JUMBO_CAPABLE) && !tg3_flag(tp, 5780_CLASS))) {
8803 if (tg3_flag(tp, JUMBO_RING_ENABLE)) {
8804 tw32(RCVDBDI_JUMBO_BD + TG3_BDINFO_HOST_ADDR + TG3_64BIT_REG_HIGH,
8805 ((u64) tpr->rx_jmb_mapping >> 32));
8806 tw32(RCVDBDI_JUMBO_BD + TG3_BDINFO_HOST_ADDR + TG3_64BIT_REG_LOW,
8807 ((u64) tpr->rx_jmb_mapping & 0xffffffff));
8808 val = TG3_RX_JMB_RING_SIZE(tp) <<
8809 BDINFO_FLAGS_MAXLEN_SHIFT;
8810 tw32(RCVDBDI_JUMBO_BD + TG3_BDINFO_MAXLEN_FLAGS,
8811 val | BDINFO_FLAGS_USE_EXT_RECV);
8812 if (!tg3_flag(tp, USE_JUMBO_BDFLAG) ||
8813 tg3_flag(tp, 57765_CLASS))
8814 tw32(RCVDBDI_JUMBO_BD + TG3_BDINFO_NIC_ADDR,
8815 NIC_SRAM_RX_JUMBO_BUFFER_DESC);
8817 tw32(RCVDBDI_JUMBO_BD + TG3_BDINFO_MAXLEN_FLAGS,
8818 BDINFO_FLAGS_DISABLED);
8821 if (tg3_flag(tp, 57765_PLUS)) {
8822 val = TG3_RX_STD_RING_SIZE(tp);
8823 val <<= BDINFO_FLAGS_MAXLEN_SHIFT;
8824 val |= (TG3_RX_STD_DMA_SZ << 2);
8826 val = TG3_RX_STD_DMA_SZ << BDINFO_FLAGS_MAXLEN_SHIFT;
8828 val = TG3_RX_STD_MAX_SIZE_5700 << BDINFO_FLAGS_MAXLEN_SHIFT;
8830 tw32(RCVDBDI_STD_BD + TG3_BDINFO_MAXLEN_FLAGS, val);
8832 tpr->rx_std_prod_idx = tp->rx_pending;
8833 tw32_rx_mbox(TG3_RX_STD_PROD_IDX_REG, tpr->rx_std_prod_idx);
8835 tpr->rx_jmb_prod_idx =
8836 tg3_flag(tp, JUMBO_RING_ENABLE) ? tp->rx_jumbo_pending : 0;
8837 tw32_rx_mbox(TG3_RX_JMB_PROD_IDX_REG, tpr->rx_jmb_prod_idx);
8839 tg3_rings_reset(tp);
8841 /* Initialize MAC address and backoff seed. */
8842 __tg3_set_mac_addr(tp, 0);
8844 /* MTU + ethernet header + FCS + optional VLAN tag */
8845 tw32(MAC_RX_MTU_SIZE,
8846 tp->dev->mtu + ETH_HLEN + ETH_FCS_LEN + VLAN_HLEN);
8848 /* The slot time is changed by tg3_setup_phy if we
8849 * run at gigabit with half duplex.
8851 val = (2 << TX_LENGTHS_IPG_CRS_SHIFT) |
8852 (6 << TX_LENGTHS_IPG_SHIFT) |
8853 (32 << TX_LENGTHS_SLOT_TIME_SHIFT);
8855 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5720)
8856 val |= tr32(MAC_TX_LENGTHS) &
8857 (TX_LENGTHS_JMB_FRM_LEN_MSK |
8858 TX_LENGTHS_CNT_DWN_VAL_MSK);
8860 tw32(MAC_TX_LENGTHS, val);
8862 /* Receive rules. */
8863 tw32(MAC_RCV_RULE_CFG, RCV_RULE_CFG_DEFAULT_CLASS);
8864 tw32(RCVLPC_CONFIG, 0x0181);
8866 /* Calculate RDMAC_MODE setting early, we need it to determine
8867 * the RCVLPC_STATE_ENABLE mask.
8869 rdmac_mode = (RDMAC_MODE_ENABLE | RDMAC_MODE_TGTABORT_ENAB |
8870 RDMAC_MODE_MSTABORT_ENAB | RDMAC_MODE_PARITYERR_ENAB |
8871 RDMAC_MODE_ADDROFLOW_ENAB | RDMAC_MODE_FIFOOFLOW_ENAB |
8872 RDMAC_MODE_FIFOURUN_ENAB | RDMAC_MODE_FIFOOREAD_ENAB |
8873 RDMAC_MODE_LNGREAD_ENAB);
8875 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717)
8876 rdmac_mode |= RDMAC_MODE_MULT_DMA_RD_DIS;
8878 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5784 ||
8879 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785 ||
8880 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57780)
8881 rdmac_mode |= RDMAC_MODE_BD_SBD_CRPT_ENAB |
8882 RDMAC_MODE_MBUF_RBD_CRPT_ENAB |
8883 RDMAC_MODE_MBUF_SBD_CRPT_ENAB;
8885 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705 &&
8886 tp->pci_chip_rev_id != CHIPREV_ID_5705_A0) {
8887 if (tg3_flag(tp, TSO_CAPABLE) &&
8888 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705) {
8889 rdmac_mode |= RDMAC_MODE_FIFO_SIZE_128;
8890 } else if (!(tr32(TG3PCI_PCISTATE) & PCISTATE_BUS_SPEED_HIGH) &&
8891 !tg3_flag(tp, IS_5788)) {
8892 rdmac_mode |= RDMAC_MODE_FIFO_LONG_BURST;
8896 if (tg3_flag(tp, PCI_EXPRESS))
8897 rdmac_mode |= RDMAC_MODE_FIFO_LONG_BURST;
8899 if (tg3_flag(tp, HW_TSO_1) ||
8900 tg3_flag(tp, HW_TSO_2) ||
8901 tg3_flag(tp, HW_TSO_3))
8902 rdmac_mode |= RDMAC_MODE_IPV4_LSO_EN;
8904 if (tg3_flag(tp, 57765_PLUS) ||
8905 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785 ||
8906 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57780)
8907 rdmac_mode |= RDMAC_MODE_IPV6_LSO_EN;
8909 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5720)
8910 rdmac_mode |= tr32(RDMAC_MODE) & RDMAC_MODE_H2BNC_VLAN_DET;
8912 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5761 ||
8913 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5784 ||
8914 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785 ||
8915 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57780 ||
8916 tg3_flag(tp, 57765_PLUS)) {
8917 val = tr32(TG3_RDMA_RSRVCTRL_REG);
8918 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5719 ||
8919 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5720) {
8920 val &= ~(TG3_RDMA_RSRVCTRL_TXMRGN_MASK |
8921 TG3_RDMA_RSRVCTRL_FIFO_LWM_MASK |
8922 TG3_RDMA_RSRVCTRL_FIFO_HWM_MASK);
8923 val |= TG3_RDMA_RSRVCTRL_TXMRGN_320B |
8924 TG3_RDMA_RSRVCTRL_FIFO_LWM_1_5K |
8925 TG3_RDMA_RSRVCTRL_FIFO_HWM_1_5K;
8927 tw32(TG3_RDMA_RSRVCTRL_REG,
8928 val | TG3_RDMA_RSRVCTRL_FIFO_OFLW_FIX);
8931 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5719 ||
8932 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5720) {
8933 val = tr32(TG3_LSO_RD_DMA_CRPTEN_CTRL);
8934 tw32(TG3_LSO_RD_DMA_CRPTEN_CTRL, val |
8935 TG3_LSO_RD_DMA_CRPTEN_CTRL_BLEN_BD_4K |
8936 TG3_LSO_RD_DMA_CRPTEN_CTRL_BLEN_LSO_4K);
8939 /* Receive/send statistics. */
8940 if (tg3_flag(tp, 5750_PLUS)) {
8941 val = tr32(RCVLPC_STATS_ENABLE);
8942 val &= ~RCVLPC_STATSENAB_DACK_FIX;
8943 tw32(RCVLPC_STATS_ENABLE, val);
8944 } else if ((rdmac_mode & RDMAC_MODE_FIFO_SIZE_128) &&
8945 tg3_flag(tp, TSO_CAPABLE)) {
8946 val = tr32(RCVLPC_STATS_ENABLE);
8947 val &= ~RCVLPC_STATSENAB_LNGBRST_RFIX;
8948 tw32(RCVLPC_STATS_ENABLE, val);
8950 tw32(RCVLPC_STATS_ENABLE, 0xffffff);
8952 tw32(RCVLPC_STATSCTRL, RCVLPC_STATSCTRL_ENABLE);
8953 tw32(SNDDATAI_STATSENAB, 0xffffff);
8954 tw32(SNDDATAI_STATSCTRL,
8955 (SNDDATAI_SCTRL_ENABLE |
8956 SNDDATAI_SCTRL_FASTUPD));
8958 /* Setup host coalescing engine. */
8959 tw32(HOSTCC_MODE, 0);
8960 for (i = 0; i < 2000; i++) {
8961 if (!(tr32(HOSTCC_MODE) & HOSTCC_MODE_ENABLE))
8966 __tg3_set_coalesce(tp, &tp->coal);
8968 if (!tg3_flag(tp, 5705_PLUS)) {
8969 /* Status/statistics block address. See tg3_timer,
8970 * the tg3_periodic_fetch_stats call there, and
8971 * tg3_get_stats to see how this works for 5705/5750 chips.
8973 tw32(HOSTCC_STATS_BLK_HOST_ADDR + TG3_64BIT_REG_HIGH,
8974 ((u64) tp->stats_mapping >> 32));
8975 tw32(HOSTCC_STATS_BLK_HOST_ADDR + TG3_64BIT_REG_LOW,
8976 ((u64) tp->stats_mapping & 0xffffffff));
8977 tw32(HOSTCC_STATS_BLK_NIC_ADDR, NIC_SRAM_STATS_BLK);
8979 tw32(HOSTCC_STATUS_BLK_NIC_ADDR, NIC_SRAM_STATUS_BLK);
8981 /* Clear statistics and status block memory areas */
8982 for (i = NIC_SRAM_STATS_BLK;
8983 i < NIC_SRAM_STATUS_BLK + TG3_HW_STATUS_SIZE;
8985 tg3_write_mem(tp, i, 0);
8990 tw32(HOSTCC_MODE, HOSTCC_MODE_ENABLE | tp->coalesce_mode);
8992 tw32(RCVCC_MODE, RCVCC_MODE_ENABLE | RCVCC_MODE_ATTN_ENABLE);
8993 tw32(RCVLPC_MODE, RCVLPC_MODE_ENABLE);
8994 if (!tg3_flag(tp, 5705_PLUS))
8995 tw32(RCVLSC_MODE, RCVLSC_MODE_ENABLE | RCVLSC_MODE_ATTN_ENABLE);
8997 if (tp->phy_flags & TG3_PHYFLG_MII_SERDES) {
8998 tp->phy_flags &= ~TG3_PHYFLG_PARALLEL_DETECT;
8999 /* reset to prevent losing 1st rx packet intermittently */
9000 tw32_f(MAC_RX_MODE, RX_MODE_RESET);
9004 tp->mac_mode |= MAC_MODE_TXSTAT_ENABLE | MAC_MODE_RXSTAT_ENABLE |
9005 MAC_MODE_TDE_ENABLE | MAC_MODE_RDE_ENABLE |
9006 MAC_MODE_FHDE_ENABLE;
9007 if (tg3_flag(tp, ENABLE_APE))
9008 tp->mac_mode |= MAC_MODE_APE_TX_EN | MAC_MODE_APE_RX_EN;
9009 if (!tg3_flag(tp, 5705_PLUS) &&
9010 !(tp->phy_flags & TG3_PHYFLG_PHY_SERDES) &&
9011 GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5700)
9012 tp->mac_mode |= MAC_MODE_LINK_POLARITY;
9013 tw32_f(MAC_MODE, tp->mac_mode | MAC_MODE_RXSTAT_CLEAR | MAC_MODE_TXSTAT_CLEAR);
9016 /* tp->grc_local_ctrl is partially set up during tg3_get_invariants().
9017 * If TG3_FLAG_IS_NIC is zero, we should read the
9018 * register to preserve the GPIO settings for LOMs. The GPIOs,
9019 * whether used as inputs or outputs, are set by boot code after
9022 if (!tg3_flag(tp, IS_NIC)) {
9025 gpio_mask = GRC_LCLCTRL_GPIO_OE0 | GRC_LCLCTRL_GPIO_OE1 |
9026 GRC_LCLCTRL_GPIO_OE2 | GRC_LCLCTRL_GPIO_OUTPUT0 |
9027 GRC_LCLCTRL_GPIO_OUTPUT1 | GRC_LCLCTRL_GPIO_OUTPUT2;
9029 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5752)
9030 gpio_mask |= GRC_LCLCTRL_GPIO_OE3 |
9031 GRC_LCLCTRL_GPIO_OUTPUT3;
9033 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5755)
9034 gpio_mask |= GRC_LCLCTRL_GPIO_UART_SEL;
9036 tp->grc_local_ctrl &= ~gpio_mask;
9037 tp->grc_local_ctrl |= tr32(GRC_LOCAL_CTRL) & gpio_mask;
9039 /* GPIO1 must be driven high for eeprom write protect */
9040 if (tg3_flag(tp, EEPROM_WRITE_PROT))
9041 tp->grc_local_ctrl |= (GRC_LCLCTRL_GPIO_OE1 |
9042 GRC_LCLCTRL_GPIO_OUTPUT1);
9044 tw32_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl);
9047 if (tg3_flag(tp, USING_MSIX)) {
9048 val = tr32(MSGINT_MODE);
9049 val |= MSGINT_MODE_ENABLE;
9050 if (tp->irq_cnt > 1)
9051 val |= MSGINT_MODE_MULTIVEC_EN;
9052 if (!tg3_flag(tp, 1SHOT_MSI))
9053 val |= MSGINT_MODE_ONE_SHOT_DISABLE;
9054 tw32(MSGINT_MODE, val);
9057 if (!tg3_flag(tp, 5705_PLUS)) {
9058 tw32_f(DMAC_MODE, DMAC_MODE_ENABLE);
9062 val = (WDMAC_MODE_ENABLE | WDMAC_MODE_TGTABORT_ENAB |
9063 WDMAC_MODE_MSTABORT_ENAB | WDMAC_MODE_PARITYERR_ENAB |
9064 WDMAC_MODE_ADDROFLOW_ENAB | WDMAC_MODE_FIFOOFLOW_ENAB |
9065 WDMAC_MODE_FIFOURUN_ENAB | WDMAC_MODE_FIFOOREAD_ENAB |
9066 WDMAC_MODE_LNGREAD_ENAB);
9068 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705 &&
9069 tp->pci_chip_rev_id != CHIPREV_ID_5705_A0) {
9070 if (tg3_flag(tp, TSO_CAPABLE) &&
9071 (tp->pci_chip_rev_id == CHIPREV_ID_5705_A1 ||
9072 tp->pci_chip_rev_id == CHIPREV_ID_5705_A2)) {
9074 } else if (!(tr32(TG3PCI_PCISTATE) & PCISTATE_BUS_SPEED_HIGH) &&
9075 !tg3_flag(tp, IS_5788)) {
9076 val |= WDMAC_MODE_RX_ACCEL;
9080 /* Enable host coalescing bug fix */
9081 if (tg3_flag(tp, 5755_PLUS))
9082 val |= WDMAC_MODE_STATUS_TAG_FIX;
9084 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785)
9085 val |= WDMAC_MODE_BURST_ALL_DATA;
9087 tw32_f(WDMAC_MODE, val);
9090 if (tg3_flag(tp, PCIX_MODE)) {
9093 pci_read_config_word(tp->pdev, tp->pcix_cap + PCI_X_CMD,
9095 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703) {
9096 pcix_cmd &= ~PCI_X_CMD_MAX_READ;
9097 pcix_cmd |= PCI_X_CMD_READ_2K;
9098 } else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704) {
9099 pcix_cmd &= ~(PCI_X_CMD_MAX_SPLIT | PCI_X_CMD_MAX_READ);
9100 pcix_cmd |= PCI_X_CMD_READ_2K;
9102 pci_write_config_word(tp->pdev, tp->pcix_cap + PCI_X_CMD,
9106 tw32_f(RDMAC_MODE, rdmac_mode);
9109 tw32(RCVDCC_MODE, RCVDCC_MODE_ENABLE | RCVDCC_MODE_ATTN_ENABLE);
9110 if (!tg3_flag(tp, 5705_PLUS))
9111 tw32(MBFREE_MODE, MBFREE_MODE_ENABLE);
9113 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5761)
9115 SNDDATAC_MODE_ENABLE | SNDDATAC_MODE_CDELAY);
9117 tw32(SNDDATAC_MODE, SNDDATAC_MODE_ENABLE);
9119 tw32(SNDBDC_MODE, SNDBDC_MODE_ENABLE | SNDBDC_MODE_ATTN_ENABLE);
9120 tw32(RCVBDI_MODE, RCVBDI_MODE_ENABLE | RCVBDI_MODE_RCB_ATTN_ENAB);
9121 val = RCVDBDI_MODE_ENABLE | RCVDBDI_MODE_INV_RING_SZ;
9122 if (tg3_flag(tp, LRG_PROD_RING_CAP))
9123 val |= RCVDBDI_MODE_LRG_RING_SZ;
9124 tw32(RCVDBDI_MODE, val);
9125 tw32(SNDDATAI_MODE, SNDDATAI_MODE_ENABLE);
9126 if (tg3_flag(tp, HW_TSO_1) ||
9127 tg3_flag(tp, HW_TSO_2) ||
9128 tg3_flag(tp, HW_TSO_3))
9129 tw32(SNDDATAI_MODE, SNDDATAI_MODE_ENABLE | 0x8);
9130 val = SNDBDI_MODE_ENABLE | SNDBDI_MODE_ATTN_ENABLE;
9131 if (tg3_flag(tp, ENABLE_TSS))
9132 val |= SNDBDI_MODE_MULTI_TXQ_EN;
9133 tw32(SNDBDI_MODE, val);
9134 tw32(SNDBDS_MODE, SNDBDS_MODE_ENABLE | SNDBDS_MODE_ATTN_ENABLE);
9136 if (tp->pci_chip_rev_id == CHIPREV_ID_5701_A0) {
9137 err = tg3_load_5701_a0_firmware_fix(tp);
9142 if (tg3_flag(tp, TSO_CAPABLE)) {
9143 err = tg3_load_tso_firmware(tp);
9148 tp->tx_mode = TX_MODE_ENABLE;
9150 if (tg3_flag(tp, 5755_PLUS) ||
9151 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906)
9152 tp->tx_mode |= TX_MODE_MBUF_LOCKUP_FIX;
9154 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5720) {
9155 val = TX_MODE_JMB_FRM_LEN | TX_MODE_CNT_DN_MODE;
9156 tp->tx_mode &= ~val;
9157 tp->tx_mode |= tr32(MAC_TX_MODE) & val;
9160 tw32_f(MAC_TX_MODE, tp->tx_mode);
9163 if (tg3_flag(tp, ENABLE_RSS)) {
9164 tg3_rss_write_indir_tbl(tp);
9166 /* Setup the "secret" hash key. */
9167 tw32(MAC_RSS_HASH_KEY_0, 0x5f865437);
9168 tw32(MAC_RSS_HASH_KEY_1, 0xe4ac62cc);
9169 tw32(MAC_RSS_HASH_KEY_2, 0x50103a45);
9170 tw32(MAC_RSS_HASH_KEY_3, 0x36621985);
9171 tw32(MAC_RSS_HASH_KEY_4, 0xbf14c0e8);
9172 tw32(MAC_RSS_HASH_KEY_5, 0x1bc27a1e);
9173 tw32(MAC_RSS_HASH_KEY_6, 0x84f4b556);
9174 tw32(MAC_RSS_HASH_KEY_7, 0x094ea6fe);
9175 tw32(MAC_RSS_HASH_KEY_8, 0x7dda01e7);
9176 tw32(MAC_RSS_HASH_KEY_9, 0xc04d7481);
9179 tp->rx_mode = RX_MODE_ENABLE;
9180 if (tg3_flag(tp, 5755_PLUS))
9181 tp->rx_mode |= RX_MODE_IPV6_CSUM_ENABLE;
9183 if (tg3_flag(tp, ENABLE_RSS))
9184 tp->rx_mode |= RX_MODE_RSS_ENABLE |
9185 RX_MODE_RSS_ITBL_HASH_BITS_7 |
9186 RX_MODE_RSS_IPV6_HASH_EN |
9187 RX_MODE_RSS_TCP_IPV6_HASH_EN |
9188 RX_MODE_RSS_IPV4_HASH_EN |
9189 RX_MODE_RSS_TCP_IPV4_HASH_EN;
9191 tw32_f(MAC_RX_MODE, tp->rx_mode);
9194 tw32(MAC_LED_CTRL, tp->led_ctrl);
9196 tw32(MAC_MI_STAT, MAC_MI_STAT_LNKSTAT_ATTN_ENAB);
9197 if (tp->phy_flags & TG3_PHYFLG_PHY_SERDES) {
9198 tw32_f(MAC_RX_MODE, RX_MODE_RESET);
9201 tw32_f(MAC_RX_MODE, tp->rx_mode);
9204 if (tp->phy_flags & TG3_PHYFLG_PHY_SERDES) {
9205 if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704) &&
9206 !(tp->phy_flags & TG3_PHYFLG_SERDES_PREEMPHASIS)) {
9207 /* Set drive transmission level to 1.2V */
9208 /* only if the signal pre-emphasis bit is not set */
9209 val = tr32(MAC_SERDES_CFG);
9212 tw32(MAC_SERDES_CFG, val);
9214 if (tp->pci_chip_rev_id == CHIPREV_ID_5703_A1)
9215 tw32(MAC_SERDES_CFG, 0x616000);
9218 /* Prevent chip from dropping frames when flow control
9221 if (tg3_flag(tp, 57765_CLASS))
9225 tw32_f(MAC_LOW_WMARK_MAX_RX_FRAME, val);
9227 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704 &&
9228 (tp->phy_flags & TG3_PHYFLG_PHY_SERDES)) {
9229 /* Use hardware link auto-negotiation */
9230 tg3_flag_set(tp, HW_AUTONEG);
9233 if ((tp->phy_flags & TG3_PHYFLG_MII_SERDES) &&
9234 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5714) {
9237 tmp = tr32(SERDES_RX_CTRL);
9238 tw32(SERDES_RX_CTRL, tmp | SERDES_RX_SIG_DETECT);
9239 tp->grc_local_ctrl &= ~GRC_LCLCTRL_USE_EXT_SIG_DETECT;
9240 tp->grc_local_ctrl |= GRC_LCLCTRL_USE_SIG_DETECT;
9241 tw32(GRC_LOCAL_CTRL, tp->grc_local_ctrl);
9244 if (!tg3_flag(tp, USE_PHYLIB)) {
9245 if (tp->phy_flags & TG3_PHYFLG_IS_LOW_POWER) {
9246 tp->phy_flags &= ~TG3_PHYFLG_IS_LOW_POWER;
9247 tp->link_config.speed = tp->link_config.orig_speed;
9248 tp->link_config.duplex = tp->link_config.orig_duplex;
9249 tp->link_config.autoneg = tp->link_config.orig_autoneg;
9252 err = tg3_setup_phy(tp, 0);
9256 if (!(tp->phy_flags & TG3_PHYFLG_PHY_SERDES) &&
9257 !(tp->phy_flags & TG3_PHYFLG_IS_FET)) {
9260 /* Clear CRC stats. */
9261 if (!tg3_readphy(tp, MII_TG3_TEST1, &tmp)) {
9262 tg3_writephy(tp, MII_TG3_TEST1,
9263 tmp | MII_TG3_TEST1_CRC_EN);
9264 tg3_readphy(tp, MII_TG3_RXR_COUNTERS, &tmp);
9269 __tg3_set_rx_mode(tp->dev);
9271 /* Initialize receive rules. */
9272 tw32(MAC_RCV_RULE_0, 0xc2000000 & RCV_RULE_DISABLE_MASK);
9273 tw32(MAC_RCV_VALUE_0, 0xffffffff & RCV_RULE_DISABLE_MASK);
9274 tw32(MAC_RCV_RULE_1, 0x86000004 & RCV_RULE_DISABLE_MASK);
9275 tw32(MAC_RCV_VALUE_1, 0xffffffff & RCV_RULE_DISABLE_MASK);
9277 if (tg3_flag(tp, 5705_PLUS) && !tg3_flag(tp, 5780_CLASS))
9281 if (tg3_flag(tp, ENABLE_ASF))
9285 tw32(MAC_RCV_RULE_15, 0); tw32(MAC_RCV_VALUE_15, 0);
9287 tw32(MAC_RCV_RULE_14, 0); tw32(MAC_RCV_VALUE_14, 0);
9289 tw32(MAC_RCV_RULE_13, 0); tw32(MAC_RCV_VALUE_13, 0);
9291 tw32(MAC_RCV_RULE_12, 0); tw32(MAC_RCV_VALUE_12, 0);
9293 tw32(MAC_RCV_RULE_11, 0); tw32(MAC_RCV_VALUE_11, 0);
9295 tw32(MAC_RCV_RULE_10, 0); tw32(MAC_RCV_VALUE_10, 0);
9297 tw32(MAC_RCV_RULE_9, 0); tw32(MAC_RCV_VALUE_9, 0);
9299 tw32(MAC_RCV_RULE_8, 0); tw32(MAC_RCV_VALUE_8, 0);
9301 tw32(MAC_RCV_RULE_7, 0); tw32(MAC_RCV_VALUE_7, 0);
9303 tw32(MAC_RCV_RULE_6, 0); tw32(MAC_RCV_VALUE_6, 0);
9305 tw32(MAC_RCV_RULE_5, 0); tw32(MAC_RCV_VALUE_5, 0);
9307 tw32(MAC_RCV_RULE_4, 0); tw32(MAC_RCV_VALUE_4, 0);
9309 /* tw32(MAC_RCV_RULE_3, 0); tw32(MAC_RCV_VALUE_3, 0); */
9311 /* tw32(MAC_RCV_RULE_2, 0); tw32(MAC_RCV_VALUE_2, 0); */
9319 if (tg3_flag(tp, ENABLE_APE))
9320 /* Write our heartbeat update interval to APE. */
9321 tg3_ape_write32(tp, TG3_APE_HOST_HEARTBEAT_INT_MS,
9322 APE_HOST_HEARTBEAT_INT_DISABLE);
9324 tg3_write_sig_post_reset(tp, RESET_KIND_INIT);
9329 /* Called at device open time to get the chip ready for
9330 * packet processing. Invoked with tp->lock held.
9332 static int tg3_init_hw(struct tg3 *tp, int reset_phy)
9334 tg3_switch_clocks(tp);
9336 tw32(TG3PCI_MEM_WIN_BASE_ADDR, 0);
9338 return tg3_reset_hw(tp, reset_phy);
9341 /* Restart hardware after configuration changes, self-test, etc.
9342 * Invoked with tp->lock held.
9344 static int tg3_restart_hw(struct tg3 *tp, int reset_phy)
9345 __releases(tp->lock)
9346 __acquires(tp->lock)
9350 err = tg3_init_hw(tp, reset_phy);
9353 "Failed to re-initialize device, aborting\n");
9354 tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
9355 tg3_full_unlock(tp);
9356 del_timer_sync(&tp->timer);
9358 tg3_napi_enable(tp);
9360 tg3_full_lock(tp, 0);
9365 static void tg3_reset_task(struct work_struct *work)
9367 struct tg3 *tp = container_of(work, struct tg3, reset_task);
9370 tg3_full_lock(tp, 0);
9372 if (!netif_running(tp->dev)) {
9373 tg3_flag_clear(tp, RESET_TASK_PENDING);
9374 tg3_full_unlock(tp);
9378 tg3_full_unlock(tp);
9384 tg3_full_lock(tp, 1);
9386 if (tg3_flag(tp, TX_RECOVERY_PENDING)) {
9387 tp->write32_tx_mbox = tg3_write32_tx_mbox;
9388 tp->write32_rx_mbox = tg3_write_flush_reg32;
9389 tg3_flag_set(tp, MBOX_WRITE_REORDER);
9390 tg3_flag_clear(tp, TX_RECOVERY_PENDING);
9393 tg3_halt(tp, RESET_KIND_SHUTDOWN, 0);
9394 err = tg3_init_hw(tp, 1);
9398 tg3_netif_start(tp);
9401 tg3_full_unlock(tp);
9406 tg3_flag_clear(tp, RESET_TASK_PENDING);
9409 #define TG3_STAT_ADD32(PSTAT, REG) \
9410 do { u32 __val = tr32(REG); \
9411 (PSTAT)->low += __val; \
9412 if ((PSTAT)->low < __val) \
9413 (PSTAT)->high += 1; \
9416 static void tg3_periodic_fetch_stats(struct tg3 *tp)
9418 struct tg3_hw_stats *sp = tp->hw_stats;
9420 if (!netif_carrier_ok(tp->dev))
9423 TG3_STAT_ADD32(&sp->tx_octets, MAC_TX_STATS_OCTETS);
9424 TG3_STAT_ADD32(&sp->tx_collisions, MAC_TX_STATS_COLLISIONS);
9425 TG3_STAT_ADD32(&sp->tx_xon_sent, MAC_TX_STATS_XON_SENT);
9426 TG3_STAT_ADD32(&sp->tx_xoff_sent, MAC_TX_STATS_XOFF_SENT);
9427 TG3_STAT_ADD32(&sp->tx_mac_errors, MAC_TX_STATS_MAC_ERRORS);
9428 TG3_STAT_ADD32(&sp->tx_single_collisions, MAC_TX_STATS_SINGLE_COLLISIONS);
9429 TG3_STAT_ADD32(&sp->tx_mult_collisions, MAC_TX_STATS_MULT_COLLISIONS);
9430 TG3_STAT_ADD32(&sp->tx_deferred, MAC_TX_STATS_DEFERRED);
9431 TG3_STAT_ADD32(&sp->tx_excessive_collisions, MAC_TX_STATS_EXCESSIVE_COL);
9432 TG3_STAT_ADD32(&sp->tx_late_collisions, MAC_TX_STATS_LATE_COL);
9433 TG3_STAT_ADD32(&sp->tx_ucast_packets, MAC_TX_STATS_UCAST);
9434 TG3_STAT_ADD32(&sp->tx_mcast_packets, MAC_TX_STATS_MCAST);
9435 TG3_STAT_ADD32(&sp->tx_bcast_packets, MAC_TX_STATS_BCAST);
9437 TG3_STAT_ADD32(&sp->rx_octets, MAC_RX_STATS_OCTETS);
9438 TG3_STAT_ADD32(&sp->rx_fragments, MAC_RX_STATS_FRAGMENTS);
9439 TG3_STAT_ADD32(&sp->rx_ucast_packets, MAC_RX_STATS_UCAST);
9440 TG3_STAT_ADD32(&sp->rx_mcast_packets, MAC_RX_STATS_MCAST);
9441 TG3_STAT_ADD32(&sp->rx_bcast_packets, MAC_RX_STATS_BCAST);
9442 TG3_STAT_ADD32(&sp->rx_fcs_errors, MAC_RX_STATS_FCS_ERRORS);
9443 TG3_STAT_ADD32(&sp->rx_align_errors, MAC_RX_STATS_ALIGN_ERRORS);
9444 TG3_STAT_ADD32(&sp->rx_xon_pause_rcvd, MAC_RX_STATS_XON_PAUSE_RECVD);
9445 TG3_STAT_ADD32(&sp->rx_xoff_pause_rcvd, MAC_RX_STATS_XOFF_PAUSE_RECVD);
9446 TG3_STAT_ADD32(&sp->rx_mac_ctrl_rcvd, MAC_RX_STATS_MAC_CTRL_RECVD);
9447 TG3_STAT_ADD32(&sp->rx_xoff_entered, MAC_RX_STATS_XOFF_ENTERED);
9448 TG3_STAT_ADD32(&sp->rx_frame_too_long_errors, MAC_RX_STATS_FRAME_TOO_LONG);
9449 TG3_STAT_ADD32(&sp->rx_jabbers, MAC_RX_STATS_JABBERS);
9450 TG3_STAT_ADD32(&sp->rx_undersize_packets, MAC_RX_STATS_UNDERSIZE);
9452 TG3_STAT_ADD32(&sp->rxbds_empty, RCVLPC_NO_RCV_BD_CNT);
9453 if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5717 &&
9454 tp->pci_chip_rev_id != CHIPREV_ID_5719_A0 &&
9455 tp->pci_chip_rev_id != CHIPREV_ID_5720_A0) {
9456 TG3_STAT_ADD32(&sp->rx_discards, RCVLPC_IN_DISCARDS_CNT);
9458 u32 val = tr32(HOSTCC_FLOW_ATTN);
9459 val = (val & HOSTCC_FLOW_ATTN_MBUF_LWM) ? 1 : 0;
9461 tw32(HOSTCC_FLOW_ATTN, HOSTCC_FLOW_ATTN_MBUF_LWM);
9462 sp->rx_discards.low += val;
9463 if (sp->rx_discards.low < val)
9464 sp->rx_discards.high += 1;
9466 sp->mbuf_lwm_thresh_hit = sp->rx_discards;
9468 TG3_STAT_ADD32(&sp->rx_errors, RCVLPC_IN_ERRORS_CNT);
9471 static void tg3_chk_missed_msi(struct tg3 *tp)
9475 for (i = 0; i < tp->irq_cnt; i++) {
9476 struct tg3_napi *tnapi = &tp->napi[i];
9478 if (tg3_has_work(tnapi)) {
9479 if (tnapi->last_rx_cons == tnapi->rx_rcb_ptr &&
9480 tnapi->last_tx_cons == tnapi->tx_cons) {
9481 if (tnapi->chk_msi_cnt < 1) {
9482 tnapi->chk_msi_cnt++;
9488 tnapi->chk_msi_cnt = 0;
9489 tnapi->last_rx_cons = tnapi->rx_rcb_ptr;
9490 tnapi->last_tx_cons = tnapi->tx_cons;
9494 static void tg3_timer(unsigned long __opaque)
9496 struct tg3 *tp = (struct tg3 *) __opaque;
9498 if (tp->irq_sync || tg3_flag(tp, RESET_TASK_PENDING))
9501 spin_lock(&tp->lock);
9503 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717 ||
9504 tg3_flag(tp, 57765_CLASS))
9505 tg3_chk_missed_msi(tp);
9507 if (!tg3_flag(tp, TAGGED_STATUS)) {
9508 /* All of this garbage is because when using non-tagged
9509 * IRQ status the mailbox/status_block protocol the chip
9510 * uses with the cpu is race prone.
9512 if (tp->napi[0].hw_status->status & SD_STATUS_UPDATED) {
9513 tw32(GRC_LOCAL_CTRL,
9514 tp->grc_local_ctrl | GRC_LCLCTRL_SETINT);
9516 tw32(HOSTCC_MODE, tp->coalesce_mode |
9517 HOSTCC_MODE_ENABLE | HOSTCC_MODE_NOW);
9520 if (!(tr32(WDMAC_MODE) & WDMAC_MODE_ENABLE)) {
9521 spin_unlock(&tp->lock);
9522 tg3_reset_task_schedule(tp);
9527 /* This part only runs once per second. */
9528 if (!--tp->timer_counter) {
9529 if (tg3_flag(tp, 5705_PLUS))
9530 tg3_periodic_fetch_stats(tp);
9532 if (tp->setlpicnt && !--tp->setlpicnt)
9533 tg3_phy_eee_enable(tp);
9535 if (tg3_flag(tp, USE_LINKCHG_REG)) {
9539 mac_stat = tr32(MAC_STATUS);
9542 if (tp->phy_flags & TG3_PHYFLG_USE_MI_INTERRUPT) {
9543 if (mac_stat & MAC_STATUS_MI_INTERRUPT)
9545 } else if (mac_stat & MAC_STATUS_LNKSTATE_CHANGED)
9549 tg3_setup_phy(tp, 0);
9550 } else if (tg3_flag(tp, POLL_SERDES)) {
9551 u32 mac_stat = tr32(MAC_STATUS);
9554 if (netif_carrier_ok(tp->dev) &&
9555 (mac_stat & MAC_STATUS_LNKSTATE_CHANGED)) {
9558 if (!netif_carrier_ok(tp->dev) &&
9559 (mac_stat & (MAC_STATUS_PCS_SYNCED |
9560 MAC_STATUS_SIGNAL_DET))) {
9564 if (!tp->serdes_counter) {
9567 ~MAC_MODE_PORT_MODE_MASK));
9569 tw32_f(MAC_MODE, tp->mac_mode);
9572 tg3_setup_phy(tp, 0);
9574 } else if ((tp->phy_flags & TG3_PHYFLG_MII_SERDES) &&
9575 tg3_flag(tp, 5780_CLASS)) {
9576 tg3_serdes_parallel_detect(tp);
9579 tp->timer_counter = tp->timer_multiplier;
9582 /* Heartbeat is only sent once every 2 seconds.
9584 * The heartbeat is to tell the ASF firmware that the host
9585 * driver is still alive. In the event that the OS crashes,
9586 * ASF needs to reset the hardware to free up the FIFO space
9587 * that may be filled with rx packets destined for the host.
9588 * If the FIFO is full, ASF will no longer function properly.
9590 * Unintended resets have been reported on real time kernels
9591 * where the timer doesn't run on time. Netpoll will also have
9594 * The new FWCMD_NICDRV_ALIVE3 command tells the ASF firmware
9595 * to check the ring condition when the heartbeat is expiring
9596 * before doing the reset. This will prevent most unintended
9599 if (!--tp->asf_counter) {
9600 if (tg3_flag(tp, ENABLE_ASF) && !tg3_flag(tp, ENABLE_APE)) {
9601 tg3_wait_for_event_ack(tp);
9603 tg3_write_mem(tp, NIC_SRAM_FW_CMD_MBOX,
9604 FWCMD_NICDRV_ALIVE3);
9605 tg3_write_mem(tp, NIC_SRAM_FW_CMD_LEN_MBOX, 4);
9606 tg3_write_mem(tp, NIC_SRAM_FW_CMD_DATA_MBOX,
9607 TG3_FW_UPDATE_TIMEOUT_SEC);
9609 tg3_generate_fw_event(tp);
9611 tp->asf_counter = tp->asf_multiplier;
9614 spin_unlock(&tp->lock);
9617 tp->timer.expires = jiffies + tp->timer_offset;
9618 add_timer(&tp->timer);
9621 static int tg3_request_irq(struct tg3 *tp, int irq_num)
9624 unsigned long flags;
9626 struct tg3_napi *tnapi = &tp->napi[irq_num];
9628 if (tp->irq_cnt == 1)
9629 name = tp->dev->name;
9631 name = &tnapi->irq_lbl[0];
9632 snprintf(name, IFNAMSIZ, "%s-%d", tp->dev->name, irq_num);
9633 name[IFNAMSIZ-1] = 0;
9636 if (tg3_flag(tp, USING_MSI) || tg3_flag(tp, USING_MSIX)) {
9638 if (tg3_flag(tp, 1SHOT_MSI))
9643 if (tg3_flag(tp, TAGGED_STATUS))
9644 fn = tg3_interrupt_tagged;
9645 flags = IRQF_SHARED;
9648 return request_irq(tnapi->irq_vec, fn, flags, name, tnapi);
9651 static int tg3_test_interrupt(struct tg3 *tp)
9653 struct tg3_napi *tnapi = &tp->napi[0];
9654 struct net_device *dev = tp->dev;
9655 int err, i, intr_ok = 0;
9658 if (!netif_running(dev))
9661 tg3_disable_ints(tp);
9663 free_irq(tnapi->irq_vec, tnapi);
9666 * Turn off MSI one shot mode. Otherwise this test has no
9667 * observable way to know whether the interrupt was delivered.
9669 if (tg3_flag(tp, 57765_PLUS)) {
9670 val = tr32(MSGINT_MODE) | MSGINT_MODE_ONE_SHOT_DISABLE;
9671 tw32(MSGINT_MODE, val);
9674 err = request_irq(tnapi->irq_vec, tg3_test_isr,
9675 IRQF_SHARED | IRQF_SAMPLE_RANDOM, dev->name, tnapi);
9679 tnapi->hw_status->status &= ~SD_STATUS_UPDATED;
9680 tg3_enable_ints(tp);
9682 tw32_f(HOSTCC_MODE, tp->coalesce_mode | HOSTCC_MODE_ENABLE |
9685 for (i = 0; i < 5; i++) {
9686 u32 int_mbox, misc_host_ctrl;
9688 int_mbox = tr32_mailbox(tnapi->int_mbox);
9689 misc_host_ctrl = tr32(TG3PCI_MISC_HOST_CTRL);
9691 if ((int_mbox != 0) ||
9692 (misc_host_ctrl & MISC_HOST_CTRL_MASK_PCI_INT)) {
9697 if (tg3_flag(tp, 57765_PLUS) &&
9698 tnapi->hw_status->status_tag != tnapi->last_tag)
9699 tw32_mailbox_f(tnapi->int_mbox, tnapi->last_tag << 24);
9704 tg3_disable_ints(tp);
9706 free_irq(tnapi->irq_vec, tnapi);
9708 err = tg3_request_irq(tp, 0);
9714 /* Reenable MSI one shot mode. */
9715 if (tg3_flag(tp, 57765_PLUS) && tg3_flag(tp, 1SHOT_MSI)) {
9716 val = tr32(MSGINT_MODE) & ~MSGINT_MODE_ONE_SHOT_DISABLE;
9717 tw32(MSGINT_MODE, val);
9725 /* Returns 0 if MSI test succeeds or MSI test fails and INTx mode is
9726 * successfully restored
9728 static int tg3_test_msi(struct tg3 *tp)
9733 if (!tg3_flag(tp, USING_MSI))
9736 /* Turn off SERR reporting in case MSI terminates with Master
9739 pci_read_config_word(tp->pdev, PCI_COMMAND, &pci_cmd);
9740 pci_write_config_word(tp->pdev, PCI_COMMAND,
9741 pci_cmd & ~PCI_COMMAND_SERR);
9743 err = tg3_test_interrupt(tp);
9745 pci_write_config_word(tp->pdev, PCI_COMMAND, pci_cmd);
9750 /* other failures */
9754 /* MSI test failed, go back to INTx mode */
9755 netdev_warn(tp->dev, "No interrupt was generated using MSI. Switching "
9756 "to INTx mode. Please report this failure to the PCI "
9757 "maintainer and include system chipset information\n");
9759 free_irq(tp->napi[0].irq_vec, &tp->napi[0]);
9761 pci_disable_msi(tp->pdev);
9763 tg3_flag_clear(tp, USING_MSI);
9764 tp->napi[0].irq_vec = tp->pdev->irq;
9766 err = tg3_request_irq(tp, 0);
9770 /* Need to reset the chip because the MSI cycle may have terminated
9771 * with Master Abort.
9773 tg3_full_lock(tp, 1);
9775 tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
9776 err = tg3_init_hw(tp, 1);
9778 tg3_full_unlock(tp);
9781 free_irq(tp->napi[0].irq_vec, &tp->napi[0]);
9786 static int tg3_request_firmware(struct tg3 *tp)
9788 const __be32 *fw_data;
9790 if (request_firmware(&tp->fw, tp->fw_needed, &tp->pdev->dev)) {
9791 netdev_err(tp->dev, "Failed to load firmware \"%s\"\n",
9796 fw_data = (void *)tp->fw->data;
9798 /* Firmware blob starts with version numbers, followed by
9799 * start address and _full_ length including BSS sections
9800 * (which must be longer than the actual data, of course
9803 tp->fw_len = be32_to_cpu(fw_data[2]); /* includes bss */
9804 if (tp->fw_len < (tp->fw->size - 12)) {
9805 netdev_err(tp->dev, "bogus length %d in \"%s\"\n",
9806 tp->fw_len, tp->fw_needed);
9807 release_firmware(tp->fw);
9812 /* We no longer need firmware; we have it. */
9813 tp->fw_needed = NULL;
9817 static bool tg3_enable_msix(struct tg3 *tp)
9820 struct msix_entry msix_ent[tp->irq_max];
9822 tp->irq_cnt = num_online_cpus();
9823 if (tp->irq_cnt > 1) {
9824 /* We want as many rx rings enabled as there are cpus.
9825 * In multiqueue MSI-X mode, the first MSI-X vector
9826 * only deals with link interrupts, etc, so we add
9827 * one to the number of vectors we are requesting.
9829 tp->irq_cnt = min_t(unsigned, tp->irq_cnt + 1, tp->irq_max);
9832 for (i = 0; i < tp->irq_max; i++) {
9833 msix_ent[i].entry = i;
9834 msix_ent[i].vector = 0;
9837 rc = pci_enable_msix(tp->pdev, msix_ent, tp->irq_cnt);
9840 } else if (rc != 0) {
9841 if (pci_enable_msix(tp->pdev, msix_ent, rc))
9843 netdev_notice(tp->dev, "Requested %d MSI-X vectors, received %d\n",
9848 for (i = 0; i < tp->irq_max; i++)
9849 tp->napi[i].irq_vec = msix_ent[i].vector;
9851 netif_set_real_num_tx_queues(tp->dev, 1);
9852 rc = tp->irq_cnt > 1 ? tp->irq_cnt - 1 : 1;
9853 if (netif_set_real_num_rx_queues(tp->dev, rc)) {
9854 pci_disable_msix(tp->pdev);
9858 if (tp->irq_cnt > 1) {
9859 tg3_flag_set(tp, ENABLE_RSS);
9861 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5719 ||
9862 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5720) {
9863 tg3_flag_set(tp, ENABLE_TSS);
9864 netif_set_real_num_tx_queues(tp->dev, tp->irq_cnt - 1);
9871 static void tg3_ints_init(struct tg3 *tp)
9873 if ((tg3_flag(tp, SUPPORT_MSI) || tg3_flag(tp, SUPPORT_MSIX)) &&
9874 !tg3_flag(tp, TAGGED_STATUS)) {
9875 /* All MSI supporting chips should support tagged
9876 * status. Assert that this is the case.
9878 netdev_warn(tp->dev,
9879 "MSI without TAGGED_STATUS? Not using MSI\n");
9883 if (tg3_flag(tp, SUPPORT_MSIX) && tg3_enable_msix(tp))
9884 tg3_flag_set(tp, USING_MSIX);
9885 else if (tg3_flag(tp, SUPPORT_MSI) && pci_enable_msi(tp->pdev) == 0)
9886 tg3_flag_set(tp, USING_MSI);
9888 if (tg3_flag(tp, USING_MSI) || tg3_flag(tp, USING_MSIX)) {
9889 u32 msi_mode = tr32(MSGINT_MODE);
9890 if (tg3_flag(tp, USING_MSIX) && tp->irq_cnt > 1)
9891 msi_mode |= MSGINT_MODE_MULTIVEC_EN;
9892 if (!tg3_flag(tp, 1SHOT_MSI))
9893 msi_mode |= MSGINT_MODE_ONE_SHOT_DISABLE;
9894 tw32(MSGINT_MODE, msi_mode | MSGINT_MODE_ENABLE);
9897 if (!tg3_flag(tp, USING_MSIX)) {
9899 tp->napi[0].irq_vec = tp->pdev->irq;
9900 netif_set_real_num_tx_queues(tp->dev, 1);
9901 netif_set_real_num_rx_queues(tp->dev, 1);
9905 static void tg3_ints_fini(struct tg3 *tp)
9907 if (tg3_flag(tp, USING_MSIX))
9908 pci_disable_msix(tp->pdev);
9909 else if (tg3_flag(tp, USING_MSI))
9910 pci_disable_msi(tp->pdev);
9911 tg3_flag_clear(tp, USING_MSI);
9912 tg3_flag_clear(tp, USING_MSIX);
9913 tg3_flag_clear(tp, ENABLE_RSS);
9914 tg3_flag_clear(tp, ENABLE_TSS);
9917 static int tg3_open(struct net_device *dev)
9919 struct tg3 *tp = netdev_priv(dev);
9922 if (tp->fw_needed) {
9923 err = tg3_request_firmware(tp);
9924 if (tp->pci_chip_rev_id == CHIPREV_ID_5701_A0) {
9928 netdev_warn(tp->dev, "TSO capability disabled\n");
9929 tg3_flag_clear(tp, TSO_CAPABLE);
9930 } else if (!tg3_flag(tp, TSO_CAPABLE)) {
9931 netdev_notice(tp->dev, "TSO capability restored\n");
9932 tg3_flag_set(tp, TSO_CAPABLE);
9936 netif_carrier_off(tp->dev);
9938 err = tg3_power_up(tp);
9942 tg3_full_lock(tp, 0);
9944 tg3_disable_ints(tp);
9945 tg3_flag_clear(tp, INIT_COMPLETE);
9947 tg3_full_unlock(tp);
9950 * Setup interrupts first so we know how
9951 * many NAPI resources to allocate
9955 tg3_rss_check_indir_tbl(tp);
9957 /* The placement of this call is tied
9958 * to the setup and use of Host TX descriptors.
9960 err = tg3_alloc_consistent(tp);
9966 tg3_napi_enable(tp);
9968 for (i = 0; i < tp->irq_cnt; i++) {
9969 struct tg3_napi *tnapi = &tp->napi[i];
9970 err = tg3_request_irq(tp, i);
9972 for (i--; i >= 0; i--) {
9973 tnapi = &tp->napi[i];
9974 free_irq(tnapi->irq_vec, tnapi);
9980 tg3_full_lock(tp, 0);
9982 err = tg3_init_hw(tp, 1);
9984 tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
9987 if (tg3_flag(tp, TAGGED_STATUS) &&
9988 GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5717 &&
9989 !tg3_flag(tp, 57765_CLASS))
9990 tp->timer_offset = HZ;
9992 tp->timer_offset = HZ / 10;
9994 BUG_ON(tp->timer_offset > HZ);
9995 tp->timer_counter = tp->timer_multiplier =
9996 (HZ / tp->timer_offset);
9997 tp->asf_counter = tp->asf_multiplier =
9998 ((HZ / tp->timer_offset) * 2);
10000 init_timer(&tp->timer);
10001 tp->timer.expires = jiffies + tp->timer_offset;
10002 tp->timer.data = (unsigned long) tp;
10003 tp->timer.function = tg3_timer;
10006 tg3_full_unlock(tp);
10011 if (tg3_flag(tp, USING_MSI)) {
10012 err = tg3_test_msi(tp);
10015 tg3_full_lock(tp, 0);
10016 tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
10017 tg3_free_rings(tp);
10018 tg3_full_unlock(tp);
10023 if (!tg3_flag(tp, 57765_PLUS) && tg3_flag(tp, USING_MSI)) {
10024 u32 val = tr32(PCIE_TRANSACTION_CFG);
10026 tw32(PCIE_TRANSACTION_CFG,
10027 val | PCIE_TRANS_CFG_1SHOT_MSI);
10033 tg3_full_lock(tp, 0);
10035 add_timer(&tp->timer);
10036 tg3_flag_set(tp, INIT_COMPLETE);
10037 tg3_enable_ints(tp);
10039 tg3_full_unlock(tp);
10041 netif_tx_start_all_queues(dev);
10044 * Reset loopback feature if it was turned on while the device was down
10045 * make sure that it's installed properly now.
10047 if (dev->features & NETIF_F_LOOPBACK)
10048 tg3_set_loopback(dev, dev->features);
10053 for (i = tp->irq_cnt - 1; i >= 0; i--) {
10054 struct tg3_napi *tnapi = &tp->napi[i];
10055 free_irq(tnapi->irq_vec, tnapi);
10059 tg3_napi_disable(tp);
10061 tg3_free_consistent(tp);
10065 tg3_frob_aux_power(tp, false);
10066 pci_set_power_state(tp->pdev, PCI_D3hot);
10070 static int tg3_close(struct net_device *dev)
10073 struct tg3 *tp = netdev_priv(dev);
10075 tg3_napi_disable(tp);
10076 tg3_reset_task_cancel(tp);
10078 netif_tx_stop_all_queues(dev);
10080 del_timer_sync(&tp->timer);
10084 tg3_full_lock(tp, 1);
10086 tg3_disable_ints(tp);
10088 tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
10089 tg3_free_rings(tp);
10090 tg3_flag_clear(tp, INIT_COMPLETE);
10092 tg3_full_unlock(tp);
10094 for (i = tp->irq_cnt - 1; i >= 0; i--) {
10095 struct tg3_napi *tnapi = &tp->napi[i];
10096 free_irq(tnapi->irq_vec, tnapi);
10101 /* Clear stats across close / open calls */
10102 memset(&tp->net_stats_prev, 0, sizeof(tp->net_stats_prev));
10103 memset(&tp->estats_prev, 0, sizeof(tp->estats_prev));
10107 tg3_free_consistent(tp);
10109 tg3_power_down(tp);
10111 netif_carrier_off(tp->dev);
10116 static inline u64 get_stat64(tg3_stat64_t *val)
10118 return ((u64)val->high << 32) | ((u64)val->low);
10121 static u64 calc_crc_errors(struct tg3 *tp)
10123 struct tg3_hw_stats *hw_stats = tp->hw_stats;
10125 if (!(tp->phy_flags & TG3_PHYFLG_PHY_SERDES) &&
10126 (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
10127 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701)) {
10130 spin_lock_bh(&tp->lock);
10131 if (!tg3_readphy(tp, MII_TG3_TEST1, &val)) {
10132 tg3_writephy(tp, MII_TG3_TEST1,
10133 val | MII_TG3_TEST1_CRC_EN);
10134 tg3_readphy(tp, MII_TG3_RXR_COUNTERS, &val);
10137 spin_unlock_bh(&tp->lock);
10139 tp->phy_crc_errors += val;
10141 return tp->phy_crc_errors;
10144 return get_stat64(&hw_stats->rx_fcs_errors);
10147 #define ESTAT_ADD(member) \
10148 estats->member = old_estats->member + \
10149 get_stat64(&hw_stats->member)
10151 static struct tg3_ethtool_stats *tg3_get_estats(struct tg3 *tp,
10152 struct tg3_ethtool_stats *estats)
10154 struct tg3_ethtool_stats *old_estats = &tp->estats_prev;
10155 struct tg3_hw_stats *hw_stats = tp->hw_stats;
10160 ESTAT_ADD(rx_octets);
10161 ESTAT_ADD(rx_fragments);
10162 ESTAT_ADD(rx_ucast_packets);
10163 ESTAT_ADD(rx_mcast_packets);
10164 ESTAT_ADD(rx_bcast_packets);
10165 ESTAT_ADD(rx_fcs_errors);
10166 ESTAT_ADD(rx_align_errors);
10167 ESTAT_ADD(rx_xon_pause_rcvd);
10168 ESTAT_ADD(rx_xoff_pause_rcvd);
10169 ESTAT_ADD(rx_mac_ctrl_rcvd);
10170 ESTAT_ADD(rx_xoff_entered);
10171 ESTAT_ADD(rx_frame_too_long_errors);
10172 ESTAT_ADD(rx_jabbers);
10173 ESTAT_ADD(rx_undersize_packets);
10174 ESTAT_ADD(rx_in_length_errors);
10175 ESTAT_ADD(rx_out_length_errors);
10176 ESTAT_ADD(rx_64_or_less_octet_packets);
10177 ESTAT_ADD(rx_65_to_127_octet_packets);
10178 ESTAT_ADD(rx_128_to_255_octet_packets);
10179 ESTAT_ADD(rx_256_to_511_octet_packets);
10180 ESTAT_ADD(rx_512_to_1023_octet_packets);
10181 ESTAT_ADD(rx_1024_to_1522_octet_packets);
10182 ESTAT_ADD(rx_1523_to_2047_octet_packets);
10183 ESTAT_ADD(rx_2048_to_4095_octet_packets);
10184 ESTAT_ADD(rx_4096_to_8191_octet_packets);
10185 ESTAT_ADD(rx_8192_to_9022_octet_packets);
10187 ESTAT_ADD(tx_octets);
10188 ESTAT_ADD(tx_collisions);
10189 ESTAT_ADD(tx_xon_sent);
10190 ESTAT_ADD(tx_xoff_sent);
10191 ESTAT_ADD(tx_flow_control);
10192 ESTAT_ADD(tx_mac_errors);
10193 ESTAT_ADD(tx_single_collisions);
10194 ESTAT_ADD(tx_mult_collisions);
10195 ESTAT_ADD(tx_deferred);
10196 ESTAT_ADD(tx_excessive_collisions);
10197 ESTAT_ADD(tx_late_collisions);
10198 ESTAT_ADD(tx_collide_2times);
10199 ESTAT_ADD(tx_collide_3times);
10200 ESTAT_ADD(tx_collide_4times);
10201 ESTAT_ADD(tx_collide_5times);
10202 ESTAT_ADD(tx_collide_6times);
10203 ESTAT_ADD(tx_collide_7times);
10204 ESTAT_ADD(tx_collide_8times);
10205 ESTAT_ADD(tx_collide_9times);
10206 ESTAT_ADD(tx_collide_10times);
10207 ESTAT_ADD(tx_collide_11times);
10208 ESTAT_ADD(tx_collide_12times);
10209 ESTAT_ADD(tx_collide_13times);
10210 ESTAT_ADD(tx_collide_14times);
10211 ESTAT_ADD(tx_collide_15times);
10212 ESTAT_ADD(tx_ucast_packets);
10213 ESTAT_ADD(tx_mcast_packets);
10214 ESTAT_ADD(tx_bcast_packets);
10215 ESTAT_ADD(tx_carrier_sense_errors);
10216 ESTAT_ADD(tx_discards);
10217 ESTAT_ADD(tx_errors);
10219 ESTAT_ADD(dma_writeq_full);
10220 ESTAT_ADD(dma_write_prioq_full);
10221 ESTAT_ADD(rxbds_empty);
10222 ESTAT_ADD(rx_discards);
10223 ESTAT_ADD(rx_errors);
10224 ESTAT_ADD(rx_threshold_hit);
10226 ESTAT_ADD(dma_readq_full);
10227 ESTAT_ADD(dma_read_prioq_full);
10228 ESTAT_ADD(tx_comp_queue_full);
10230 ESTAT_ADD(ring_set_send_prod_index);
10231 ESTAT_ADD(ring_status_update);
10232 ESTAT_ADD(nic_irqs);
10233 ESTAT_ADD(nic_avoided_irqs);
10234 ESTAT_ADD(nic_tx_threshold_hit);
10236 ESTAT_ADD(mbuf_lwm_thresh_hit);
10241 static struct rtnl_link_stats64 *tg3_get_stats64(struct net_device *dev,
10242 struct rtnl_link_stats64 *stats)
10244 struct tg3 *tp = netdev_priv(dev);
10245 struct rtnl_link_stats64 *old_stats = &tp->net_stats_prev;
10246 struct tg3_hw_stats *hw_stats = tp->hw_stats;
10251 stats->rx_packets = old_stats->rx_packets +
10252 get_stat64(&hw_stats->rx_ucast_packets) +
10253 get_stat64(&hw_stats->rx_mcast_packets) +
10254 get_stat64(&hw_stats->rx_bcast_packets);
10256 stats->tx_packets = old_stats->tx_packets +
10257 get_stat64(&hw_stats->tx_ucast_packets) +
10258 get_stat64(&hw_stats->tx_mcast_packets) +
10259 get_stat64(&hw_stats->tx_bcast_packets);
10261 stats->rx_bytes = old_stats->rx_bytes +
10262 get_stat64(&hw_stats->rx_octets);
10263 stats->tx_bytes = old_stats->tx_bytes +
10264 get_stat64(&hw_stats->tx_octets);
10266 stats->rx_errors = old_stats->rx_errors +
10267 get_stat64(&hw_stats->rx_errors);
10268 stats->tx_errors = old_stats->tx_errors +
10269 get_stat64(&hw_stats->tx_errors) +
10270 get_stat64(&hw_stats->tx_mac_errors) +
10271 get_stat64(&hw_stats->tx_carrier_sense_errors) +
10272 get_stat64(&hw_stats->tx_discards);
10274 stats->multicast = old_stats->multicast +
10275 get_stat64(&hw_stats->rx_mcast_packets);
10276 stats->collisions = old_stats->collisions +
10277 get_stat64(&hw_stats->tx_collisions);
10279 stats->rx_length_errors = old_stats->rx_length_errors +
10280 get_stat64(&hw_stats->rx_frame_too_long_errors) +
10281 get_stat64(&hw_stats->rx_undersize_packets);
10283 stats->rx_over_errors = old_stats->rx_over_errors +
10284 get_stat64(&hw_stats->rxbds_empty);
10285 stats->rx_frame_errors = old_stats->rx_frame_errors +
10286 get_stat64(&hw_stats->rx_align_errors);
10287 stats->tx_aborted_errors = old_stats->tx_aborted_errors +
10288 get_stat64(&hw_stats->tx_discards);
10289 stats->tx_carrier_errors = old_stats->tx_carrier_errors +
10290 get_stat64(&hw_stats->tx_carrier_sense_errors);
10292 stats->rx_crc_errors = old_stats->rx_crc_errors +
10293 calc_crc_errors(tp);
10295 stats->rx_missed_errors = old_stats->rx_missed_errors +
10296 get_stat64(&hw_stats->rx_discards);
10298 stats->rx_dropped = tp->rx_dropped;
10299 stats->tx_dropped = tp->tx_dropped;
10304 static int tg3_get_regs_len(struct net_device *dev)
10306 return TG3_REG_BLK_SIZE;
10309 static void tg3_get_regs(struct net_device *dev,
10310 struct ethtool_regs *regs, void *_p)
10312 struct tg3 *tp = netdev_priv(dev);
10316 memset(_p, 0, TG3_REG_BLK_SIZE);
10318 if (tp->phy_flags & TG3_PHYFLG_IS_LOW_POWER)
10321 tg3_full_lock(tp, 0);
10323 tg3_dump_legacy_regs(tp, (u32 *)_p);
10325 tg3_full_unlock(tp);
10328 static int tg3_get_eeprom_len(struct net_device *dev)
10330 struct tg3 *tp = netdev_priv(dev);
10332 return tp->nvram_size;
10335 static int tg3_get_eeprom(struct net_device *dev, struct ethtool_eeprom *eeprom, u8 *data)
10337 struct tg3 *tp = netdev_priv(dev);
10340 u32 i, offset, len, b_offset, b_count;
10343 if (tg3_flag(tp, NO_NVRAM))
10346 if (tp->phy_flags & TG3_PHYFLG_IS_LOW_POWER)
10349 offset = eeprom->offset;
10353 eeprom->magic = TG3_EEPROM_MAGIC;
10356 /* adjustments to start on required 4 byte boundary */
10357 b_offset = offset & 3;
10358 b_count = 4 - b_offset;
10359 if (b_count > len) {
10360 /* i.e. offset=1 len=2 */
10363 ret = tg3_nvram_read_be32(tp, offset-b_offset, &val);
10366 memcpy(data, ((char *)&val) + b_offset, b_count);
10369 eeprom->len += b_count;
10372 /* read bytes up to the last 4 byte boundary */
10373 pd = &data[eeprom->len];
10374 for (i = 0; i < (len - (len & 3)); i += 4) {
10375 ret = tg3_nvram_read_be32(tp, offset + i, &val);
10380 memcpy(pd + i, &val, 4);
10385 /* read last bytes not ending on 4 byte boundary */
10386 pd = &data[eeprom->len];
10388 b_offset = offset + len - b_count;
10389 ret = tg3_nvram_read_be32(tp, b_offset, &val);
10392 memcpy(pd, &val, b_count);
10393 eeprom->len += b_count;
10398 static int tg3_set_eeprom(struct net_device *dev, struct ethtool_eeprom *eeprom, u8 *data)
10400 struct tg3 *tp = netdev_priv(dev);
10402 u32 offset, len, b_offset, odd_len;
10406 if (tp->phy_flags & TG3_PHYFLG_IS_LOW_POWER)
10409 if (tg3_flag(tp, NO_NVRAM) ||
10410 eeprom->magic != TG3_EEPROM_MAGIC)
10413 offset = eeprom->offset;
10416 if ((b_offset = (offset & 3))) {
10417 /* adjustments to start on required 4 byte boundary */
10418 ret = tg3_nvram_read_be32(tp, offset-b_offset, &start);
10429 /* adjustments to end on required 4 byte boundary */
10431 len = (len + 3) & ~3;
10432 ret = tg3_nvram_read_be32(tp, offset+len-4, &end);
10438 if (b_offset || odd_len) {
10439 buf = kmalloc(len, GFP_KERNEL);
10443 memcpy(buf, &start, 4);
10445 memcpy(buf+len-4, &end, 4);
10446 memcpy(buf + b_offset, data, eeprom->len);
10449 ret = tg3_nvram_write_block(tp, offset, len, buf);
10457 static int tg3_get_settings(struct net_device *dev, struct ethtool_cmd *cmd)
10459 struct tg3 *tp = netdev_priv(dev);
10461 if (tg3_flag(tp, USE_PHYLIB)) {
10462 struct phy_device *phydev;
10463 if (!(tp->phy_flags & TG3_PHYFLG_IS_CONNECTED))
10465 phydev = tp->mdio_bus->phy_map[TG3_PHY_MII_ADDR];
10466 return phy_ethtool_gset(phydev, cmd);
10469 cmd->supported = (SUPPORTED_Autoneg);
10471 if (!(tp->phy_flags & TG3_PHYFLG_10_100_ONLY))
10472 cmd->supported |= (SUPPORTED_1000baseT_Half |
10473 SUPPORTED_1000baseT_Full);
10475 if (!(tp->phy_flags & TG3_PHYFLG_ANY_SERDES)) {
10476 cmd->supported |= (SUPPORTED_100baseT_Half |
10477 SUPPORTED_100baseT_Full |
10478 SUPPORTED_10baseT_Half |
10479 SUPPORTED_10baseT_Full |
10481 cmd->port = PORT_TP;
10483 cmd->supported |= SUPPORTED_FIBRE;
10484 cmd->port = PORT_FIBRE;
10487 cmd->advertising = tp->link_config.advertising;
10488 if (tg3_flag(tp, PAUSE_AUTONEG)) {
10489 if (tp->link_config.flowctrl & FLOW_CTRL_RX) {
10490 if (tp->link_config.flowctrl & FLOW_CTRL_TX) {
10491 cmd->advertising |= ADVERTISED_Pause;
10493 cmd->advertising |= ADVERTISED_Pause |
10494 ADVERTISED_Asym_Pause;
10496 } else if (tp->link_config.flowctrl & FLOW_CTRL_TX) {
10497 cmd->advertising |= ADVERTISED_Asym_Pause;
10500 if (netif_running(dev) && netif_carrier_ok(dev)) {
10501 ethtool_cmd_speed_set(cmd, tp->link_config.active_speed);
10502 cmd->duplex = tp->link_config.active_duplex;
10503 cmd->lp_advertising = tp->link_config.rmt_adv;
10504 if (!(tp->phy_flags & TG3_PHYFLG_ANY_SERDES)) {
10505 if (tp->phy_flags & TG3_PHYFLG_MDIX_STATE)
10506 cmd->eth_tp_mdix = ETH_TP_MDI_X;
10508 cmd->eth_tp_mdix = ETH_TP_MDI;
10511 ethtool_cmd_speed_set(cmd, SPEED_INVALID);
10512 cmd->duplex = DUPLEX_INVALID;
10513 cmd->eth_tp_mdix = ETH_TP_MDI_INVALID;
10515 cmd->phy_address = tp->phy_addr;
10516 cmd->transceiver = XCVR_INTERNAL;
10517 cmd->autoneg = tp->link_config.autoneg;
10523 static int tg3_set_settings(struct net_device *dev, struct ethtool_cmd *cmd)
10525 struct tg3 *tp = netdev_priv(dev);
10526 u32 speed = ethtool_cmd_speed(cmd);
10528 if (tg3_flag(tp, USE_PHYLIB)) {
10529 struct phy_device *phydev;
10530 if (!(tp->phy_flags & TG3_PHYFLG_IS_CONNECTED))
10532 phydev = tp->mdio_bus->phy_map[TG3_PHY_MII_ADDR];
10533 return phy_ethtool_sset(phydev, cmd);
10536 if (cmd->autoneg != AUTONEG_ENABLE &&
10537 cmd->autoneg != AUTONEG_DISABLE)
10540 if (cmd->autoneg == AUTONEG_DISABLE &&
10541 cmd->duplex != DUPLEX_FULL &&
10542 cmd->duplex != DUPLEX_HALF)
10545 if (cmd->autoneg == AUTONEG_ENABLE) {
10546 u32 mask = ADVERTISED_Autoneg |
10548 ADVERTISED_Asym_Pause;
10550 if (!(tp->phy_flags & TG3_PHYFLG_10_100_ONLY))
10551 mask |= ADVERTISED_1000baseT_Half |
10552 ADVERTISED_1000baseT_Full;
10554 if (!(tp->phy_flags & TG3_PHYFLG_ANY_SERDES))
10555 mask |= ADVERTISED_100baseT_Half |
10556 ADVERTISED_100baseT_Full |
10557 ADVERTISED_10baseT_Half |
10558 ADVERTISED_10baseT_Full |
10561 mask |= ADVERTISED_FIBRE;
10563 if (cmd->advertising & ~mask)
10566 mask &= (ADVERTISED_1000baseT_Half |
10567 ADVERTISED_1000baseT_Full |
10568 ADVERTISED_100baseT_Half |
10569 ADVERTISED_100baseT_Full |
10570 ADVERTISED_10baseT_Half |
10571 ADVERTISED_10baseT_Full);
10573 cmd->advertising &= mask;
10575 if (tp->phy_flags & TG3_PHYFLG_ANY_SERDES) {
10576 if (speed != SPEED_1000)
10579 if (cmd->duplex != DUPLEX_FULL)
10582 if (speed != SPEED_100 &&
10588 tg3_full_lock(tp, 0);
10590 tp->link_config.autoneg = cmd->autoneg;
10591 if (cmd->autoneg == AUTONEG_ENABLE) {
10592 tp->link_config.advertising = (cmd->advertising |
10593 ADVERTISED_Autoneg);
10594 tp->link_config.speed = SPEED_INVALID;
10595 tp->link_config.duplex = DUPLEX_INVALID;
10597 tp->link_config.advertising = 0;
10598 tp->link_config.speed = speed;
10599 tp->link_config.duplex = cmd->duplex;
10602 tp->link_config.orig_speed = tp->link_config.speed;
10603 tp->link_config.orig_duplex = tp->link_config.duplex;
10604 tp->link_config.orig_autoneg = tp->link_config.autoneg;
10606 if (netif_running(dev))
10607 tg3_setup_phy(tp, 1);
10609 tg3_full_unlock(tp);
10614 static void tg3_get_drvinfo(struct net_device *dev, struct ethtool_drvinfo *info)
10616 struct tg3 *tp = netdev_priv(dev);
10618 strlcpy(info->driver, DRV_MODULE_NAME, sizeof(info->driver));
10619 strlcpy(info->version, DRV_MODULE_VERSION, sizeof(info->version));
10620 strlcpy(info->fw_version, tp->fw_ver, sizeof(info->fw_version));
10621 strlcpy(info->bus_info, pci_name(tp->pdev), sizeof(info->bus_info));
10624 static void tg3_get_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
10626 struct tg3 *tp = netdev_priv(dev);
10628 if (tg3_flag(tp, WOL_CAP) && device_can_wakeup(&tp->pdev->dev))
10629 wol->supported = WAKE_MAGIC;
10631 wol->supported = 0;
10633 if (tg3_flag(tp, WOL_ENABLE) && device_can_wakeup(&tp->pdev->dev))
10634 wol->wolopts = WAKE_MAGIC;
10635 memset(&wol->sopass, 0, sizeof(wol->sopass));
10638 static int tg3_set_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
10640 struct tg3 *tp = netdev_priv(dev);
10641 struct device *dp = &tp->pdev->dev;
10643 if (wol->wolopts & ~WAKE_MAGIC)
10645 if ((wol->wolopts & WAKE_MAGIC) &&
10646 !(tg3_flag(tp, WOL_CAP) && device_can_wakeup(dp)))
10649 device_set_wakeup_enable(dp, wol->wolopts & WAKE_MAGIC);
10651 spin_lock_bh(&tp->lock);
10652 if (device_may_wakeup(dp))
10653 tg3_flag_set(tp, WOL_ENABLE);
10655 tg3_flag_clear(tp, WOL_ENABLE);
10656 spin_unlock_bh(&tp->lock);
10661 static u32 tg3_get_msglevel(struct net_device *dev)
10663 struct tg3 *tp = netdev_priv(dev);
10664 return tp->msg_enable;
10667 static void tg3_set_msglevel(struct net_device *dev, u32 value)
10669 struct tg3 *tp = netdev_priv(dev);
10670 tp->msg_enable = value;
10673 static int tg3_nway_reset(struct net_device *dev)
10675 struct tg3 *tp = netdev_priv(dev);
10678 if (!netif_running(dev))
10681 if (tp->phy_flags & TG3_PHYFLG_PHY_SERDES)
10684 if (tg3_flag(tp, USE_PHYLIB)) {
10685 if (!(tp->phy_flags & TG3_PHYFLG_IS_CONNECTED))
10687 r = phy_start_aneg(tp->mdio_bus->phy_map[TG3_PHY_MII_ADDR]);
10691 spin_lock_bh(&tp->lock);
10693 tg3_readphy(tp, MII_BMCR, &bmcr);
10694 if (!tg3_readphy(tp, MII_BMCR, &bmcr) &&
10695 ((bmcr & BMCR_ANENABLE) ||
10696 (tp->phy_flags & TG3_PHYFLG_PARALLEL_DETECT))) {
10697 tg3_writephy(tp, MII_BMCR, bmcr | BMCR_ANRESTART |
10701 spin_unlock_bh(&tp->lock);
10707 static void tg3_get_ringparam(struct net_device *dev, struct ethtool_ringparam *ering)
10709 struct tg3 *tp = netdev_priv(dev);
10711 ering->rx_max_pending = tp->rx_std_ring_mask;
10712 if (tg3_flag(tp, JUMBO_RING_ENABLE))
10713 ering->rx_jumbo_max_pending = tp->rx_jmb_ring_mask;
10715 ering->rx_jumbo_max_pending = 0;
10717 ering->tx_max_pending = TG3_TX_RING_SIZE - 1;
10719 ering->rx_pending = tp->rx_pending;
10720 if (tg3_flag(tp, JUMBO_RING_ENABLE))
10721 ering->rx_jumbo_pending = tp->rx_jumbo_pending;
10723 ering->rx_jumbo_pending = 0;
10725 ering->tx_pending = tp->napi[0].tx_pending;
10728 static int tg3_set_ringparam(struct net_device *dev, struct ethtool_ringparam *ering)
10730 struct tg3 *tp = netdev_priv(dev);
10731 int i, irq_sync = 0, err = 0;
10733 if ((ering->rx_pending > tp->rx_std_ring_mask) ||
10734 (ering->rx_jumbo_pending > tp->rx_jmb_ring_mask) ||
10735 (ering->tx_pending > TG3_TX_RING_SIZE - 1) ||
10736 (ering->tx_pending <= MAX_SKB_FRAGS) ||
10737 (tg3_flag(tp, TSO_BUG) &&
10738 (ering->tx_pending <= (MAX_SKB_FRAGS * 3))))
10741 if (netif_running(dev)) {
10743 tg3_netif_stop(tp);
10747 tg3_full_lock(tp, irq_sync);
10749 tp->rx_pending = ering->rx_pending;
10751 if (tg3_flag(tp, MAX_RXPEND_64) &&
10752 tp->rx_pending > 63)
10753 tp->rx_pending = 63;
10754 tp->rx_jumbo_pending = ering->rx_jumbo_pending;
10756 for (i = 0; i < tp->irq_max; i++)
10757 tp->napi[i].tx_pending = ering->tx_pending;
10759 if (netif_running(dev)) {
10760 tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
10761 err = tg3_restart_hw(tp, 1);
10763 tg3_netif_start(tp);
10766 tg3_full_unlock(tp);
10768 if (irq_sync && !err)
10774 static void tg3_get_pauseparam(struct net_device *dev, struct ethtool_pauseparam *epause)
10776 struct tg3 *tp = netdev_priv(dev);
10778 epause->autoneg = !!tg3_flag(tp, PAUSE_AUTONEG);
10780 if (tp->link_config.flowctrl & FLOW_CTRL_RX)
10781 epause->rx_pause = 1;
10783 epause->rx_pause = 0;
10785 if (tp->link_config.flowctrl & FLOW_CTRL_TX)
10786 epause->tx_pause = 1;
10788 epause->tx_pause = 0;
10791 static int tg3_set_pauseparam(struct net_device *dev, struct ethtool_pauseparam *epause)
10793 struct tg3 *tp = netdev_priv(dev);
10796 if (tg3_flag(tp, USE_PHYLIB)) {
10798 struct phy_device *phydev;
10800 phydev = tp->mdio_bus->phy_map[TG3_PHY_MII_ADDR];
10802 if (!(phydev->supported & SUPPORTED_Pause) ||
10803 (!(phydev->supported & SUPPORTED_Asym_Pause) &&
10804 (epause->rx_pause != epause->tx_pause)))
10807 tp->link_config.flowctrl = 0;
10808 if (epause->rx_pause) {
10809 tp->link_config.flowctrl |= FLOW_CTRL_RX;
10811 if (epause->tx_pause) {
10812 tp->link_config.flowctrl |= FLOW_CTRL_TX;
10813 newadv = ADVERTISED_Pause;
10815 newadv = ADVERTISED_Pause |
10816 ADVERTISED_Asym_Pause;
10817 } else if (epause->tx_pause) {
10818 tp->link_config.flowctrl |= FLOW_CTRL_TX;
10819 newadv = ADVERTISED_Asym_Pause;
10823 if (epause->autoneg)
10824 tg3_flag_set(tp, PAUSE_AUTONEG);
10826 tg3_flag_clear(tp, PAUSE_AUTONEG);
10828 if (tp->phy_flags & TG3_PHYFLG_IS_CONNECTED) {
10829 u32 oldadv = phydev->advertising &
10830 (ADVERTISED_Pause | ADVERTISED_Asym_Pause);
10831 if (oldadv != newadv) {
10832 phydev->advertising &=
10833 ~(ADVERTISED_Pause |
10834 ADVERTISED_Asym_Pause);
10835 phydev->advertising |= newadv;
10836 if (phydev->autoneg) {
10838 * Always renegotiate the link to
10839 * inform our link partner of our
10840 * flow control settings, even if the
10841 * flow control is forced. Let
10842 * tg3_adjust_link() do the final
10843 * flow control setup.
10845 return phy_start_aneg(phydev);
10849 if (!epause->autoneg)
10850 tg3_setup_flow_control(tp, 0, 0);
10852 tp->link_config.orig_advertising &=
10853 ~(ADVERTISED_Pause |
10854 ADVERTISED_Asym_Pause);
10855 tp->link_config.orig_advertising |= newadv;
10860 if (netif_running(dev)) {
10861 tg3_netif_stop(tp);
10865 tg3_full_lock(tp, irq_sync);
10867 if (epause->autoneg)
10868 tg3_flag_set(tp, PAUSE_AUTONEG);
10870 tg3_flag_clear(tp, PAUSE_AUTONEG);
10871 if (epause->rx_pause)
10872 tp->link_config.flowctrl |= FLOW_CTRL_RX;
10874 tp->link_config.flowctrl &= ~FLOW_CTRL_RX;
10875 if (epause->tx_pause)
10876 tp->link_config.flowctrl |= FLOW_CTRL_TX;
10878 tp->link_config.flowctrl &= ~FLOW_CTRL_TX;
10880 if (netif_running(dev)) {
10881 tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
10882 err = tg3_restart_hw(tp, 1);
10884 tg3_netif_start(tp);
10887 tg3_full_unlock(tp);
10893 static int tg3_get_sset_count(struct net_device *dev, int sset)
10897 return TG3_NUM_TEST;
10899 return TG3_NUM_STATS;
10901 return -EOPNOTSUPP;
10905 static int tg3_get_rxnfc(struct net_device *dev, struct ethtool_rxnfc *info,
10906 u32 *rules __always_unused)
10908 struct tg3 *tp = netdev_priv(dev);
10910 if (!tg3_flag(tp, SUPPORT_MSIX))
10911 return -EOPNOTSUPP;
10913 switch (info->cmd) {
10914 case ETHTOOL_GRXRINGS:
10915 if (netif_running(tp->dev))
10916 info->data = tp->irq_cnt;
10918 info->data = num_online_cpus();
10919 if (info->data > TG3_IRQ_MAX_VECS_RSS)
10920 info->data = TG3_IRQ_MAX_VECS_RSS;
10923 /* The first interrupt vector only
10924 * handles link interrupts.
10930 return -EOPNOTSUPP;
10934 static u32 tg3_get_rxfh_indir_size(struct net_device *dev)
10937 struct tg3 *tp = netdev_priv(dev);
10939 if (tg3_flag(tp, SUPPORT_MSIX))
10940 size = TG3_RSS_INDIR_TBL_SIZE;
10945 static int tg3_get_rxfh_indir(struct net_device *dev, u32 *indir)
10947 struct tg3 *tp = netdev_priv(dev);
10950 for (i = 0; i < TG3_RSS_INDIR_TBL_SIZE; i++)
10951 indir[i] = tp->rss_ind_tbl[i];
10956 static int tg3_set_rxfh_indir(struct net_device *dev, const u32 *indir)
10958 struct tg3 *tp = netdev_priv(dev);
10961 for (i = 0; i < TG3_RSS_INDIR_TBL_SIZE; i++)
10962 tp->rss_ind_tbl[i] = indir[i];
10964 if (!netif_running(dev) || !tg3_flag(tp, ENABLE_RSS))
10967 /* It is legal to write the indirection
10968 * table while the device is running.
10970 tg3_full_lock(tp, 0);
10971 tg3_rss_write_indir_tbl(tp);
10972 tg3_full_unlock(tp);
10977 static void tg3_get_strings(struct net_device *dev, u32 stringset, u8 *buf)
10979 switch (stringset) {
10981 memcpy(buf, ðtool_stats_keys, sizeof(ethtool_stats_keys));
10984 memcpy(buf, ðtool_test_keys, sizeof(ethtool_test_keys));
10987 WARN_ON(1); /* we need a WARN() */
10992 static int tg3_set_phys_id(struct net_device *dev,
10993 enum ethtool_phys_id_state state)
10995 struct tg3 *tp = netdev_priv(dev);
10997 if (!netif_running(tp->dev))
11001 case ETHTOOL_ID_ACTIVE:
11002 return 1; /* cycle on/off once per second */
11004 case ETHTOOL_ID_ON:
11005 tw32(MAC_LED_CTRL, LED_CTRL_LNKLED_OVERRIDE |
11006 LED_CTRL_1000MBPS_ON |
11007 LED_CTRL_100MBPS_ON |
11008 LED_CTRL_10MBPS_ON |
11009 LED_CTRL_TRAFFIC_OVERRIDE |
11010 LED_CTRL_TRAFFIC_BLINK |
11011 LED_CTRL_TRAFFIC_LED);
11014 case ETHTOOL_ID_OFF:
11015 tw32(MAC_LED_CTRL, LED_CTRL_LNKLED_OVERRIDE |
11016 LED_CTRL_TRAFFIC_OVERRIDE);
11019 case ETHTOOL_ID_INACTIVE:
11020 tw32(MAC_LED_CTRL, tp->led_ctrl);
11027 static void tg3_get_ethtool_stats(struct net_device *dev,
11028 struct ethtool_stats *estats, u64 *tmp_stats)
11030 struct tg3 *tp = netdev_priv(dev);
11032 tg3_get_estats(tp, (struct tg3_ethtool_stats *)tmp_stats);
11035 static __be32 *tg3_vpd_readblock(struct tg3 *tp, u32 *vpdlen)
11039 u32 offset = 0, len = 0;
11042 if (tg3_flag(tp, NO_NVRAM) || tg3_nvram_read(tp, 0, &magic))
11045 if (magic == TG3_EEPROM_MAGIC) {
11046 for (offset = TG3_NVM_DIR_START;
11047 offset < TG3_NVM_DIR_END;
11048 offset += TG3_NVM_DIRENT_SIZE) {
11049 if (tg3_nvram_read(tp, offset, &val))
11052 if ((val >> TG3_NVM_DIRTYPE_SHIFT) ==
11053 TG3_NVM_DIRTYPE_EXTVPD)
11057 if (offset != TG3_NVM_DIR_END) {
11058 len = (val & TG3_NVM_DIRTYPE_LENMSK) * 4;
11059 if (tg3_nvram_read(tp, offset + 4, &offset))
11062 offset = tg3_nvram_logical_addr(tp, offset);
11066 if (!offset || !len) {
11067 offset = TG3_NVM_VPD_OFF;
11068 len = TG3_NVM_VPD_LEN;
11071 buf = kmalloc(len, GFP_KERNEL);
11075 if (magic == TG3_EEPROM_MAGIC) {
11076 for (i = 0; i < len; i += 4) {
11077 /* The data is in little-endian format in NVRAM.
11078 * Use the big-endian read routines to preserve
11079 * the byte order as it exists in NVRAM.
11081 if (tg3_nvram_read_be32(tp, offset + i, &buf[i/4]))
11087 unsigned int pos = 0;
11089 ptr = (u8 *)&buf[0];
11090 for (i = 0; pos < len && i < 3; i++, pos += cnt, ptr += cnt) {
11091 cnt = pci_read_vpd(tp->pdev, pos,
11093 if (cnt == -ETIMEDOUT || cnt == -EINTR)
11111 #define NVRAM_TEST_SIZE 0x100
11112 #define NVRAM_SELFBOOT_FORMAT1_0_SIZE 0x14
11113 #define NVRAM_SELFBOOT_FORMAT1_2_SIZE 0x18
11114 #define NVRAM_SELFBOOT_FORMAT1_3_SIZE 0x1c
11115 #define NVRAM_SELFBOOT_FORMAT1_4_SIZE 0x20
11116 #define NVRAM_SELFBOOT_FORMAT1_5_SIZE 0x24
11117 #define NVRAM_SELFBOOT_FORMAT1_6_SIZE 0x50
11118 #define NVRAM_SELFBOOT_HW_SIZE 0x20
11119 #define NVRAM_SELFBOOT_DATA_SIZE 0x1c
11121 static int tg3_test_nvram(struct tg3 *tp)
11123 u32 csum, magic, len;
11125 int i, j, k, err = 0, size;
11127 if (tg3_flag(tp, NO_NVRAM))
11130 if (tg3_nvram_read(tp, 0, &magic) != 0)
11133 if (magic == TG3_EEPROM_MAGIC)
11134 size = NVRAM_TEST_SIZE;
11135 else if ((magic & TG3_EEPROM_MAGIC_FW_MSK) == TG3_EEPROM_MAGIC_FW) {
11136 if ((magic & TG3_EEPROM_SB_FORMAT_MASK) ==
11137 TG3_EEPROM_SB_FORMAT_1) {
11138 switch (magic & TG3_EEPROM_SB_REVISION_MASK) {
11139 case TG3_EEPROM_SB_REVISION_0:
11140 size = NVRAM_SELFBOOT_FORMAT1_0_SIZE;
11142 case TG3_EEPROM_SB_REVISION_2:
11143 size = NVRAM_SELFBOOT_FORMAT1_2_SIZE;
11145 case TG3_EEPROM_SB_REVISION_3:
11146 size = NVRAM_SELFBOOT_FORMAT1_3_SIZE;
11148 case TG3_EEPROM_SB_REVISION_4:
11149 size = NVRAM_SELFBOOT_FORMAT1_4_SIZE;
11151 case TG3_EEPROM_SB_REVISION_5:
11152 size = NVRAM_SELFBOOT_FORMAT1_5_SIZE;
11154 case TG3_EEPROM_SB_REVISION_6:
11155 size = NVRAM_SELFBOOT_FORMAT1_6_SIZE;
11162 } else if ((magic & TG3_EEPROM_MAGIC_HW_MSK) == TG3_EEPROM_MAGIC_HW)
11163 size = NVRAM_SELFBOOT_HW_SIZE;
11167 buf = kmalloc(size, GFP_KERNEL);
11172 for (i = 0, j = 0; i < size; i += 4, j++) {
11173 err = tg3_nvram_read_be32(tp, i, &buf[j]);
11180 /* Selfboot format */
11181 magic = be32_to_cpu(buf[0]);
11182 if ((magic & TG3_EEPROM_MAGIC_FW_MSK) ==
11183 TG3_EEPROM_MAGIC_FW) {
11184 u8 *buf8 = (u8 *) buf, csum8 = 0;
11186 if ((magic & TG3_EEPROM_SB_REVISION_MASK) ==
11187 TG3_EEPROM_SB_REVISION_2) {
11188 /* For rev 2, the csum doesn't include the MBA. */
11189 for (i = 0; i < TG3_EEPROM_SB_F1R2_MBA_OFF; i++)
11191 for (i = TG3_EEPROM_SB_F1R2_MBA_OFF + 4; i < size; i++)
11194 for (i = 0; i < size; i++)
11207 if ((magic & TG3_EEPROM_MAGIC_HW_MSK) ==
11208 TG3_EEPROM_MAGIC_HW) {
11209 u8 data[NVRAM_SELFBOOT_DATA_SIZE];
11210 u8 parity[NVRAM_SELFBOOT_DATA_SIZE];
11211 u8 *buf8 = (u8 *) buf;
11213 /* Separate the parity bits and the data bytes. */
11214 for (i = 0, j = 0, k = 0; i < NVRAM_SELFBOOT_HW_SIZE; i++) {
11215 if ((i == 0) || (i == 8)) {
11219 for (l = 0, msk = 0x80; l < 7; l++, msk >>= 1)
11220 parity[k++] = buf8[i] & msk;
11222 } else if (i == 16) {
11226 for (l = 0, msk = 0x20; l < 6; l++, msk >>= 1)
11227 parity[k++] = buf8[i] & msk;
11230 for (l = 0, msk = 0x80; l < 8; l++, msk >>= 1)
11231 parity[k++] = buf8[i] & msk;
11234 data[j++] = buf8[i];
11238 for (i = 0; i < NVRAM_SELFBOOT_DATA_SIZE; i++) {
11239 u8 hw8 = hweight8(data[i]);
11241 if ((hw8 & 0x1) && parity[i])
11243 else if (!(hw8 & 0x1) && !parity[i])
11252 /* Bootstrap checksum at offset 0x10 */
11253 csum = calc_crc((unsigned char *) buf, 0x10);
11254 if (csum != le32_to_cpu(buf[0x10/4]))
11257 /* Manufacturing block starts at offset 0x74, checksum at 0xfc */
11258 csum = calc_crc((unsigned char *) &buf[0x74/4], 0x88);
11259 if (csum != le32_to_cpu(buf[0xfc/4]))
11264 buf = tg3_vpd_readblock(tp, &len);
11268 i = pci_vpd_find_tag((u8 *)buf, 0, len, PCI_VPD_LRDT_RO_DATA);
11270 j = pci_vpd_lrdt_size(&((u8 *)buf)[i]);
11274 if (i + PCI_VPD_LRDT_TAG_SIZE + j > len)
11277 i += PCI_VPD_LRDT_TAG_SIZE;
11278 j = pci_vpd_find_info_keyword((u8 *)buf, i, j,
11279 PCI_VPD_RO_KEYWORD_CHKSUM);
11283 j += PCI_VPD_INFO_FLD_HDR_SIZE;
11285 for (i = 0; i <= j; i++)
11286 csum8 += ((u8 *)buf)[i];
11300 #define TG3_SERDES_TIMEOUT_SEC 2
11301 #define TG3_COPPER_TIMEOUT_SEC 6
11303 static int tg3_test_link(struct tg3 *tp)
11307 if (!netif_running(tp->dev))
11310 if (tp->phy_flags & TG3_PHYFLG_ANY_SERDES)
11311 max = TG3_SERDES_TIMEOUT_SEC;
11313 max = TG3_COPPER_TIMEOUT_SEC;
11315 for (i = 0; i < max; i++) {
11316 if (netif_carrier_ok(tp->dev))
11319 if (msleep_interruptible(1000))
11326 /* Only test the commonly used registers */
11327 static int tg3_test_registers(struct tg3 *tp)
11329 int i, is_5705, is_5750;
11330 u32 offset, read_mask, write_mask, val, save_val, read_val;
11334 #define TG3_FL_5705 0x1
11335 #define TG3_FL_NOT_5705 0x2
11336 #define TG3_FL_NOT_5788 0x4
11337 #define TG3_FL_NOT_5750 0x8
11341 /* MAC Control Registers */
11342 { MAC_MODE, TG3_FL_NOT_5705,
11343 0x00000000, 0x00ef6f8c },
11344 { MAC_MODE, TG3_FL_5705,
11345 0x00000000, 0x01ef6b8c },
11346 { MAC_STATUS, TG3_FL_NOT_5705,
11347 0x03800107, 0x00000000 },
11348 { MAC_STATUS, TG3_FL_5705,
11349 0x03800100, 0x00000000 },
11350 { MAC_ADDR_0_HIGH, 0x0000,
11351 0x00000000, 0x0000ffff },
11352 { MAC_ADDR_0_LOW, 0x0000,
11353 0x00000000, 0xffffffff },
11354 { MAC_RX_MTU_SIZE, 0x0000,
11355 0x00000000, 0x0000ffff },
11356 { MAC_TX_MODE, 0x0000,
11357 0x00000000, 0x00000070 },
11358 { MAC_TX_LENGTHS, 0x0000,
11359 0x00000000, 0x00003fff },
11360 { MAC_RX_MODE, TG3_FL_NOT_5705,
11361 0x00000000, 0x000007fc },
11362 { MAC_RX_MODE, TG3_FL_5705,
11363 0x00000000, 0x000007dc },
11364 { MAC_HASH_REG_0, 0x0000,
11365 0x00000000, 0xffffffff },
11366 { MAC_HASH_REG_1, 0x0000,
11367 0x00000000, 0xffffffff },
11368 { MAC_HASH_REG_2, 0x0000,
11369 0x00000000, 0xffffffff },
11370 { MAC_HASH_REG_3, 0x0000,
11371 0x00000000, 0xffffffff },
11373 /* Receive Data and Receive BD Initiator Control Registers. */
11374 { RCVDBDI_JUMBO_BD+0, TG3_FL_NOT_5705,
11375 0x00000000, 0xffffffff },
11376 { RCVDBDI_JUMBO_BD+4, TG3_FL_NOT_5705,
11377 0x00000000, 0xffffffff },
11378 { RCVDBDI_JUMBO_BD+8, TG3_FL_NOT_5705,
11379 0x00000000, 0x00000003 },
11380 { RCVDBDI_JUMBO_BD+0xc, TG3_FL_NOT_5705,
11381 0x00000000, 0xffffffff },
11382 { RCVDBDI_STD_BD+0, 0x0000,
11383 0x00000000, 0xffffffff },
11384 { RCVDBDI_STD_BD+4, 0x0000,
11385 0x00000000, 0xffffffff },
11386 { RCVDBDI_STD_BD+8, 0x0000,
11387 0x00000000, 0xffff0002 },
11388 { RCVDBDI_STD_BD+0xc, 0x0000,
11389 0x00000000, 0xffffffff },
11391 /* Receive BD Initiator Control Registers. */
11392 { RCVBDI_STD_THRESH, TG3_FL_NOT_5705,
11393 0x00000000, 0xffffffff },
11394 { RCVBDI_STD_THRESH, TG3_FL_5705,
11395 0x00000000, 0x000003ff },
11396 { RCVBDI_JUMBO_THRESH, TG3_FL_NOT_5705,
11397 0x00000000, 0xffffffff },
11399 /* Host Coalescing Control Registers. */
11400 { HOSTCC_MODE, TG3_FL_NOT_5705,
11401 0x00000000, 0x00000004 },
11402 { HOSTCC_MODE, TG3_FL_5705,
11403 0x00000000, 0x000000f6 },
11404 { HOSTCC_RXCOL_TICKS, TG3_FL_NOT_5705,
11405 0x00000000, 0xffffffff },
11406 { HOSTCC_RXCOL_TICKS, TG3_FL_5705,
11407 0x00000000, 0x000003ff },
11408 { HOSTCC_TXCOL_TICKS, TG3_FL_NOT_5705,
11409 0x00000000, 0xffffffff },
11410 { HOSTCC_TXCOL_TICKS, TG3_FL_5705,
11411 0x00000000, 0x000003ff },
11412 { HOSTCC_RXMAX_FRAMES, TG3_FL_NOT_5705,
11413 0x00000000, 0xffffffff },
11414 { HOSTCC_RXMAX_FRAMES, TG3_FL_5705 | TG3_FL_NOT_5788,
11415 0x00000000, 0x000000ff },
11416 { HOSTCC_TXMAX_FRAMES, TG3_FL_NOT_5705,
11417 0x00000000, 0xffffffff },
11418 { HOSTCC_TXMAX_FRAMES, TG3_FL_5705 | TG3_FL_NOT_5788,
11419 0x00000000, 0x000000ff },
11420 { HOSTCC_RXCOAL_TICK_INT, TG3_FL_NOT_5705,
11421 0x00000000, 0xffffffff },
11422 { HOSTCC_TXCOAL_TICK_INT, TG3_FL_NOT_5705,
11423 0x00000000, 0xffffffff },
11424 { HOSTCC_RXCOAL_MAXF_INT, TG3_FL_NOT_5705,
11425 0x00000000, 0xffffffff },
11426 { HOSTCC_RXCOAL_MAXF_INT, TG3_FL_5705 | TG3_FL_NOT_5788,
11427 0x00000000, 0x000000ff },
11428 { HOSTCC_TXCOAL_MAXF_INT, TG3_FL_NOT_5705,
11429 0x00000000, 0xffffffff },
11430 { HOSTCC_TXCOAL_MAXF_INT, TG3_FL_5705 | TG3_FL_NOT_5788,
11431 0x00000000, 0x000000ff },
11432 { HOSTCC_STAT_COAL_TICKS, TG3_FL_NOT_5705,
11433 0x00000000, 0xffffffff },
11434 { HOSTCC_STATS_BLK_HOST_ADDR, TG3_FL_NOT_5705,
11435 0x00000000, 0xffffffff },
11436 { HOSTCC_STATS_BLK_HOST_ADDR+4, TG3_FL_NOT_5705,
11437 0x00000000, 0xffffffff },
11438 { HOSTCC_STATUS_BLK_HOST_ADDR, 0x0000,
11439 0x00000000, 0xffffffff },
11440 { HOSTCC_STATUS_BLK_HOST_ADDR+4, 0x0000,
11441 0x00000000, 0xffffffff },
11442 { HOSTCC_STATS_BLK_NIC_ADDR, 0x0000,
11443 0xffffffff, 0x00000000 },
11444 { HOSTCC_STATUS_BLK_NIC_ADDR, 0x0000,
11445 0xffffffff, 0x00000000 },
11447 /* Buffer Manager Control Registers. */
11448 { BUFMGR_MB_POOL_ADDR, TG3_FL_NOT_5750,
11449 0x00000000, 0x007fff80 },
11450 { BUFMGR_MB_POOL_SIZE, TG3_FL_NOT_5750,
11451 0x00000000, 0x007fffff },
11452 { BUFMGR_MB_RDMA_LOW_WATER, 0x0000,
11453 0x00000000, 0x0000003f },
11454 { BUFMGR_MB_MACRX_LOW_WATER, 0x0000,
11455 0x00000000, 0x000001ff },
11456 { BUFMGR_MB_HIGH_WATER, 0x0000,
11457 0x00000000, 0x000001ff },
11458 { BUFMGR_DMA_DESC_POOL_ADDR, TG3_FL_NOT_5705,
11459 0xffffffff, 0x00000000 },
11460 { BUFMGR_DMA_DESC_POOL_SIZE, TG3_FL_NOT_5705,
11461 0xffffffff, 0x00000000 },
11463 /* Mailbox Registers */
11464 { GRCMBOX_RCVSTD_PROD_IDX+4, 0x0000,
11465 0x00000000, 0x000001ff },
11466 { GRCMBOX_RCVJUMBO_PROD_IDX+4, TG3_FL_NOT_5705,
11467 0x00000000, 0x000001ff },
11468 { GRCMBOX_RCVRET_CON_IDX_0+4, 0x0000,
11469 0x00000000, 0x000007ff },
11470 { GRCMBOX_SNDHOST_PROD_IDX_0+4, 0x0000,
11471 0x00000000, 0x000001ff },
11473 { 0xffff, 0x0000, 0x00000000, 0x00000000 },
11476 is_5705 = is_5750 = 0;
11477 if (tg3_flag(tp, 5705_PLUS)) {
11479 if (tg3_flag(tp, 5750_PLUS))
11483 for (i = 0; reg_tbl[i].offset != 0xffff; i++) {
11484 if (is_5705 && (reg_tbl[i].flags & TG3_FL_NOT_5705))
11487 if (!is_5705 && (reg_tbl[i].flags & TG3_FL_5705))
11490 if (tg3_flag(tp, IS_5788) &&
11491 (reg_tbl[i].flags & TG3_FL_NOT_5788))
11494 if (is_5750 && (reg_tbl[i].flags & TG3_FL_NOT_5750))
11497 offset = (u32) reg_tbl[i].offset;
11498 read_mask = reg_tbl[i].read_mask;
11499 write_mask = reg_tbl[i].write_mask;
11501 /* Save the original register content */
11502 save_val = tr32(offset);
11504 /* Determine the read-only value. */
11505 read_val = save_val & read_mask;
11507 /* Write zero to the register, then make sure the read-only bits
11508 * are not changed and the read/write bits are all zeros.
11512 val = tr32(offset);
11514 /* Test the read-only and read/write bits. */
11515 if (((val & read_mask) != read_val) || (val & write_mask))
11518 /* Write ones to all the bits defined by RdMask and WrMask, then
11519 * make sure the read-only bits are not changed and the
11520 * read/write bits are all ones.
11522 tw32(offset, read_mask | write_mask);
11524 val = tr32(offset);
11526 /* Test the read-only bits. */
11527 if ((val & read_mask) != read_val)
11530 /* Test the read/write bits. */
11531 if ((val & write_mask) != write_mask)
11534 tw32(offset, save_val);
11540 if (netif_msg_hw(tp))
11541 netdev_err(tp->dev,
11542 "Register test failed at offset %x\n", offset);
11543 tw32(offset, save_val);
11547 static int tg3_do_mem_test(struct tg3 *tp, u32 offset, u32 len)
11549 static const u32 test_pattern[] = { 0x00000000, 0xffffffff, 0xaa55a55a };
11553 for (i = 0; i < ARRAY_SIZE(test_pattern); i++) {
11554 for (j = 0; j < len; j += 4) {
11557 tg3_write_mem(tp, offset + j, test_pattern[i]);
11558 tg3_read_mem(tp, offset + j, &val);
11559 if (val != test_pattern[i])
11566 static int tg3_test_memory(struct tg3 *tp)
11568 static struct mem_entry {
11571 } mem_tbl_570x[] = {
11572 { 0x00000000, 0x00b50},
11573 { 0x00002000, 0x1c000},
11574 { 0xffffffff, 0x00000}
11575 }, mem_tbl_5705[] = {
11576 { 0x00000100, 0x0000c},
11577 { 0x00000200, 0x00008},
11578 { 0x00004000, 0x00800},
11579 { 0x00006000, 0x01000},
11580 { 0x00008000, 0x02000},
11581 { 0x00010000, 0x0e000},
11582 { 0xffffffff, 0x00000}
11583 }, mem_tbl_5755[] = {
11584 { 0x00000200, 0x00008},
11585 { 0x00004000, 0x00800},
11586 { 0x00006000, 0x00800},
11587 { 0x00008000, 0x02000},
11588 { 0x00010000, 0x0c000},
11589 { 0xffffffff, 0x00000}
11590 }, mem_tbl_5906[] = {
11591 { 0x00000200, 0x00008},
11592 { 0x00004000, 0x00400},
11593 { 0x00006000, 0x00400},
11594 { 0x00008000, 0x01000},
11595 { 0x00010000, 0x01000},
11596 { 0xffffffff, 0x00000}
11597 }, mem_tbl_5717[] = {
11598 { 0x00000200, 0x00008},
11599 { 0x00010000, 0x0a000},
11600 { 0x00020000, 0x13c00},
11601 { 0xffffffff, 0x00000}
11602 }, mem_tbl_57765[] = {
11603 { 0x00000200, 0x00008},
11604 { 0x00004000, 0x00800},
11605 { 0x00006000, 0x09800},
11606 { 0x00010000, 0x0a000},
11607 { 0xffffffff, 0x00000}
11609 struct mem_entry *mem_tbl;
11613 if (tg3_flag(tp, 5717_PLUS))
11614 mem_tbl = mem_tbl_5717;
11615 else if (tg3_flag(tp, 57765_CLASS))
11616 mem_tbl = mem_tbl_57765;
11617 else if (tg3_flag(tp, 5755_PLUS))
11618 mem_tbl = mem_tbl_5755;
11619 else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906)
11620 mem_tbl = mem_tbl_5906;
11621 else if (tg3_flag(tp, 5705_PLUS))
11622 mem_tbl = mem_tbl_5705;
11624 mem_tbl = mem_tbl_570x;
11626 for (i = 0; mem_tbl[i].offset != 0xffffffff; i++) {
11627 err = tg3_do_mem_test(tp, mem_tbl[i].offset, mem_tbl[i].len);
11635 #define TG3_TSO_MSS 500
11637 #define TG3_TSO_IP_HDR_LEN 20
11638 #define TG3_TSO_TCP_HDR_LEN 20
11639 #define TG3_TSO_TCP_OPT_LEN 12
11641 static const u8 tg3_tso_header[] = {
11643 0x45, 0x00, 0x00, 0x00,
11644 0x00, 0x00, 0x40, 0x00,
11645 0x40, 0x06, 0x00, 0x00,
11646 0x0a, 0x00, 0x00, 0x01,
11647 0x0a, 0x00, 0x00, 0x02,
11648 0x0d, 0x00, 0xe0, 0x00,
11649 0x00, 0x00, 0x01, 0x00,
11650 0x00, 0x00, 0x02, 0x00,
11651 0x80, 0x10, 0x10, 0x00,
11652 0x14, 0x09, 0x00, 0x00,
11653 0x01, 0x01, 0x08, 0x0a,
11654 0x11, 0x11, 0x11, 0x11,
11655 0x11, 0x11, 0x11, 0x11,
11658 static int tg3_run_loopback(struct tg3 *tp, u32 pktsz, bool tso_loopback)
11660 u32 rx_start_idx, rx_idx, tx_idx, opaque_key;
11661 u32 base_flags = 0, mss = 0, desc_idx, coal_now, data_off, val;
11663 struct sk_buff *skb;
11664 u8 *tx_data, *rx_data;
11666 int num_pkts, tx_len, rx_len, i, err;
11667 struct tg3_rx_buffer_desc *desc;
11668 struct tg3_napi *tnapi, *rnapi;
11669 struct tg3_rx_prodring_set *tpr = &tp->napi[0].prodring;
11671 tnapi = &tp->napi[0];
11672 rnapi = &tp->napi[0];
11673 if (tp->irq_cnt > 1) {
11674 if (tg3_flag(tp, ENABLE_RSS))
11675 rnapi = &tp->napi[1];
11676 if (tg3_flag(tp, ENABLE_TSS))
11677 tnapi = &tp->napi[1];
11679 coal_now = tnapi->coal_now | rnapi->coal_now;
11684 skb = netdev_alloc_skb(tp->dev, tx_len);
11688 tx_data = skb_put(skb, tx_len);
11689 memcpy(tx_data, tp->dev->dev_addr, 6);
11690 memset(tx_data + 6, 0x0, 8);
11692 tw32(MAC_RX_MTU_SIZE, tx_len + ETH_FCS_LEN);
11694 if (tso_loopback) {
11695 struct iphdr *iph = (struct iphdr *)&tx_data[ETH_HLEN];
11697 u32 hdr_len = TG3_TSO_IP_HDR_LEN + TG3_TSO_TCP_HDR_LEN +
11698 TG3_TSO_TCP_OPT_LEN;
11700 memcpy(tx_data + ETH_ALEN * 2, tg3_tso_header,
11701 sizeof(tg3_tso_header));
11704 val = tx_len - ETH_ALEN * 2 - sizeof(tg3_tso_header);
11705 num_pkts = DIV_ROUND_UP(val, TG3_TSO_MSS);
11707 /* Set the total length field in the IP header */
11708 iph->tot_len = htons((u16)(mss + hdr_len));
11710 base_flags = (TXD_FLAG_CPU_PRE_DMA |
11711 TXD_FLAG_CPU_POST_DMA);
11713 if (tg3_flag(tp, HW_TSO_1) ||
11714 tg3_flag(tp, HW_TSO_2) ||
11715 tg3_flag(tp, HW_TSO_3)) {
11717 val = ETH_HLEN + TG3_TSO_IP_HDR_LEN;
11718 th = (struct tcphdr *)&tx_data[val];
11721 base_flags |= TXD_FLAG_TCPUDP_CSUM;
11723 if (tg3_flag(tp, HW_TSO_3)) {
11724 mss |= (hdr_len & 0xc) << 12;
11725 if (hdr_len & 0x10)
11726 base_flags |= 0x00000010;
11727 base_flags |= (hdr_len & 0x3e0) << 5;
11728 } else if (tg3_flag(tp, HW_TSO_2))
11729 mss |= hdr_len << 9;
11730 else if (tg3_flag(tp, HW_TSO_1) ||
11731 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705) {
11732 mss |= (TG3_TSO_TCP_OPT_LEN << 9);
11734 base_flags |= (TG3_TSO_TCP_OPT_LEN << 10);
11737 data_off = ETH_ALEN * 2 + sizeof(tg3_tso_header);
11740 data_off = ETH_HLEN;
11743 for (i = data_off; i < tx_len; i++)
11744 tx_data[i] = (u8) (i & 0xff);
11746 map = pci_map_single(tp->pdev, skb->data, tx_len, PCI_DMA_TODEVICE);
11747 if (pci_dma_mapping_error(tp->pdev, map)) {
11748 dev_kfree_skb(skb);
11752 val = tnapi->tx_prod;
11753 tnapi->tx_buffers[val].skb = skb;
11754 dma_unmap_addr_set(&tnapi->tx_buffers[val], mapping, map);
11756 tw32_f(HOSTCC_MODE, tp->coalesce_mode | HOSTCC_MODE_ENABLE |
11761 rx_start_idx = rnapi->hw_status->idx[0].rx_producer;
11763 budget = tg3_tx_avail(tnapi);
11764 if (tg3_tx_frag_set(tnapi, &val, &budget, map, tx_len,
11765 base_flags | TXD_FLAG_END, mss, 0)) {
11766 tnapi->tx_buffers[val].skb = NULL;
11767 dev_kfree_skb(skb);
11773 tw32_tx_mbox(tnapi->prodmbox, tnapi->tx_prod);
11774 tr32_mailbox(tnapi->prodmbox);
11778 /* 350 usec to allow enough time on some 10/100 Mbps devices. */
11779 for (i = 0; i < 35; i++) {
11780 tw32_f(HOSTCC_MODE, tp->coalesce_mode | HOSTCC_MODE_ENABLE |
11785 tx_idx = tnapi->hw_status->idx[0].tx_consumer;
11786 rx_idx = rnapi->hw_status->idx[0].rx_producer;
11787 if ((tx_idx == tnapi->tx_prod) &&
11788 (rx_idx == (rx_start_idx + num_pkts)))
11792 tg3_tx_skb_unmap(tnapi, tnapi->tx_prod - 1, -1);
11793 dev_kfree_skb(skb);
11795 if (tx_idx != tnapi->tx_prod)
11798 if (rx_idx != rx_start_idx + num_pkts)
11802 while (rx_idx != rx_start_idx) {
11803 desc = &rnapi->rx_rcb[rx_start_idx++];
11804 desc_idx = desc->opaque & RXD_OPAQUE_INDEX_MASK;
11805 opaque_key = desc->opaque & RXD_OPAQUE_RING_MASK;
11807 if ((desc->err_vlan & RXD_ERR_MASK) != 0 &&
11808 (desc->err_vlan != RXD_ERR_ODD_NIBBLE_RCVD_MII))
11811 rx_len = ((desc->idx_len & RXD_LEN_MASK) >> RXD_LEN_SHIFT)
11814 if (!tso_loopback) {
11815 if (rx_len != tx_len)
11818 if (pktsz <= TG3_RX_STD_DMA_SZ - ETH_FCS_LEN) {
11819 if (opaque_key != RXD_OPAQUE_RING_STD)
11822 if (opaque_key != RXD_OPAQUE_RING_JUMBO)
11825 } else if ((desc->type_flags & RXD_FLAG_TCPUDP_CSUM) &&
11826 (desc->ip_tcp_csum & RXD_TCPCSUM_MASK)
11827 >> RXD_TCPCSUM_SHIFT != 0xffff) {
11831 if (opaque_key == RXD_OPAQUE_RING_STD) {
11832 rx_data = tpr->rx_std_buffers[desc_idx].data;
11833 map = dma_unmap_addr(&tpr->rx_std_buffers[desc_idx],
11835 } else if (opaque_key == RXD_OPAQUE_RING_JUMBO) {
11836 rx_data = tpr->rx_jmb_buffers[desc_idx].data;
11837 map = dma_unmap_addr(&tpr->rx_jmb_buffers[desc_idx],
11842 pci_dma_sync_single_for_cpu(tp->pdev, map, rx_len,
11843 PCI_DMA_FROMDEVICE);
11845 rx_data += TG3_RX_OFFSET(tp);
11846 for (i = data_off; i < rx_len; i++, val++) {
11847 if (*(rx_data + i) != (u8) (val & 0xff))
11854 /* tg3_free_rings will unmap and free the rx_data */
11859 #define TG3_STD_LOOPBACK_FAILED 1
11860 #define TG3_JMB_LOOPBACK_FAILED 2
11861 #define TG3_TSO_LOOPBACK_FAILED 4
11862 #define TG3_LOOPBACK_FAILED \
11863 (TG3_STD_LOOPBACK_FAILED | \
11864 TG3_JMB_LOOPBACK_FAILED | \
11865 TG3_TSO_LOOPBACK_FAILED)
11867 static int tg3_test_loopback(struct tg3 *tp, u64 *data, bool do_extlpbk)
11872 eee_cap = tp->phy_flags & TG3_PHYFLG_EEE_CAP;
11873 tp->phy_flags &= ~TG3_PHYFLG_EEE_CAP;
11875 if (!netif_running(tp->dev)) {
11876 data[0] = TG3_LOOPBACK_FAILED;
11877 data[1] = TG3_LOOPBACK_FAILED;
11879 data[2] = TG3_LOOPBACK_FAILED;
11883 err = tg3_reset_hw(tp, 1);
11885 data[0] = TG3_LOOPBACK_FAILED;
11886 data[1] = TG3_LOOPBACK_FAILED;
11888 data[2] = TG3_LOOPBACK_FAILED;
11892 if (tg3_flag(tp, ENABLE_RSS)) {
11895 /* Reroute all rx packets to the 1st queue */
11896 for (i = MAC_RSS_INDIR_TBL_0;
11897 i < MAC_RSS_INDIR_TBL_0 + TG3_RSS_INDIR_TBL_SIZE; i += 4)
11901 /* HW errata - mac loopback fails in some cases on 5780.
11902 * Normal traffic and PHY loopback are not affected by
11903 * errata. Also, the MAC loopback test is deprecated for
11904 * all newer ASIC revisions.
11906 if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5780 &&
11907 !tg3_flag(tp, CPMU_PRESENT)) {
11908 tg3_mac_loopback(tp, true);
11910 if (tg3_run_loopback(tp, ETH_FRAME_LEN, false))
11911 data[0] |= TG3_STD_LOOPBACK_FAILED;
11913 if (tg3_flag(tp, JUMBO_RING_ENABLE) &&
11914 tg3_run_loopback(tp, 9000 + ETH_HLEN, false))
11915 data[0] |= TG3_JMB_LOOPBACK_FAILED;
11917 tg3_mac_loopback(tp, false);
11920 if (!(tp->phy_flags & TG3_PHYFLG_PHY_SERDES) &&
11921 !tg3_flag(tp, USE_PHYLIB)) {
11924 tg3_phy_lpbk_set(tp, 0, false);
11926 /* Wait for link */
11927 for (i = 0; i < 100; i++) {
11928 if (tr32(MAC_TX_STATUS) & TX_STATUS_LINK_UP)
11933 if (tg3_run_loopback(tp, ETH_FRAME_LEN, false))
11934 data[1] |= TG3_STD_LOOPBACK_FAILED;
11935 if (tg3_flag(tp, TSO_CAPABLE) &&
11936 tg3_run_loopback(tp, ETH_FRAME_LEN, true))
11937 data[1] |= TG3_TSO_LOOPBACK_FAILED;
11938 if (tg3_flag(tp, JUMBO_RING_ENABLE) &&
11939 tg3_run_loopback(tp, 9000 + ETH_HLEN, false))
11940 data[1] |= TG3_JMB_LOOPBACK_FAILED;
11943 tg3_phy_lpbk_set(tp, 0, true);
11945 /* All link indications report up, but the hardware
11946 * isn't really ready for about 20 msec. Double it
11951 if (tg3_run_loopback(tp, ETH_FRAME_LEN, false))
11952 data[2] |= TG3_STD_LOOPBACK_FAILED;
11953 if (tg3_flag(tp, TSO_CAPABLE) &&
11954 tg3_run_loopback(tp, ETH_FRAME_LEN, true))
11955 data[2] |= TG3_TSO_LOOPBACK_FAILED;
11956 if (tg3_flag(tp, JUMBO_RING_ENABLE) &&
11957 tg3_run_loopback(tp, 9000 + ETH_HLEN, false))
11958 data[2] |= TG3_JMB_LOOPBACK_FAILED;
11961 /* Re-enable gphy autopowerdown. */
11962 if (tp->phy_flags & TG3_PHYFLG_ENABLE_APD)
11963 tg3_phy_toggle_apd(tp, true);
11966 err = (data[0] | data[1] | data[2]) ? -EIO : 0;
11969 tp->phy_flags |= eee_cap;
11974 static void tg3_self_test(struct net_device *dev, struct ethtool_test *etest,
11977 struct tg3 *tp = netdev_priv(dev);
11978 bool doextlpbk = etest->flags & ETH_TEST_FL_EXTERNAL_LB;
11980 if ((tp->phy_flags & TG3_PHYFLG_IS_LOW_POWER) &&
11981 tg3_power_up(tp)) {
11982 etest->flags |= ETH_TEST_FL_FAILED;
11983 memset(data, 1, sizeof(u64) * TG3_NUM_TEST);
11987 memset(data, 0, sizeof(u64) * TG3_NUM_TEST);
11989 if (tg3_test_nvram(tp) != 0) {
11990 etest->flags |= ETH_TEST_FL_FAILED;
11993 if (!doextlpbk && tg3_test_link(tp)) {
11994 etest->flags |= ETH_TEST_FL_FAILED;
11997 if (etest->flags & ETH_TEST_FL_OFFLINE) {
11998 int err, err2 = 0, irq_sync = 0;
12000 if (netif_running(dev)) {
12002 tg3_netif_stop(tp);
12006 tg3_full_lock(tp, irq_sync);
12008 tg3_halt(tp, RESET_KIND_SUSPEND, 1);
12009 err = tg3_nvram_lock(tp);
12010 tg3_halt_cpu(tp, RX_CPU_BASE);
12011 if (!tg3_flag(tp, 5705_PLUS))
12012 tg3_halt_cpu(tp, TX_CPU_BASE);
12014 tg3_nvram_unlock(tp);
12016 if (tp->phy_flags & TG3_PHYFLG_MII_SERDES)
12019 if (tg3_test_registers(tp) != 0) {
12020 etest->flags |= ETH_TEST_FL_FAILED;
12024 if (tg3_test_memory(tp) != 0) {
12025 etest->flags |= ETH_TEST_FL_FAILED;
12030 etest->flags |= ETH_TEST_FL_EXTERNAL_LB_DONE;
12032 if (tg3_test_loopback(tp, &data[4], doextlpbk))
12033 etest->flags |= ETH_TEST_FL_FAILED;
12035 tg3_full_unlock(tp);
12037 if (tg3_test_interrupt(tp) != 0) {
12038 etest->flags |= ETH_TEST_FL_FAILED;
12042 tg3_full_lock(tp, 0);
12044 tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
12045 if (netif_running(dev)) {
12046 tg3_flag_set(tp, INIT_COMPLETE);
12047 err2 = tg3_restart_hw(tp, 1);
12049 tg3_netif_start(tp);
12052 tg3_full_unlock(tp);
12054 if (irq_sync && !err2)
12057 if (tp->phy_flags & TG3_PHYFLG_IS_LOW_POWER)
12058 tg3_power_down(tp);
12062 static int tg3_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd)
12064 struct mii_ioctl_data *data = if_mii(ifr);
12065 struct tg3 *tp = netdev_priv(dev);
12068 if (tg3_flag(tp, USE_PHYLIB)) {
12069 struct phy_device *phydev;
12070 if (!(tp->phy_flags & TG3_PHYFLG_IS_CONNECTED))
12072 phydev = tp->mdio_bus->phy_map[TG3_PHY_MII_ADDR];
12073 return phy_mii_ioctl(phydev, ifr, cmd);
12078 data->phy_id = tp->phy_addr;
12081 case SIOCGMIIREG: {
12084 if (tp->phy_flags & TG3_PHYFLG_PHY_SERDES)
12085 break; /* We have no PHY */
12087 if (!netif_running(dev))
12090 spin_lock_bh(&tp->lock);
12091 err = tg3_readphy(tp, data->reg_num & 0x1f, &mii_regval);
12092 spin_unlock_bh(&tp->lock);
12094 data->val_out = mii_regval;
12100 if (tp->phy_flags & TG3_PHYFLG_PHY_SERDES)
12101 break; /* We have no PHY */
12103 if (!netif_running(dev))
12106 spin_lock_bh(&tp->lock);
12107 err = tg3_writephy(tp, data->reg_num & 0x1f, data->val_in);
12108 spin_unlock_bh(&tp->lock);
12116 return -EOPNOTSUPP;
12119 static int tg3_get_coalesce(struct net_device *dev, struct ethtool_coalesce *ec)
12121 struct tg3 *tp = netdev_priv(dev);
12123 memcpy(ec, &tp->coal, sizeof(*ec));
12127 static int tg3_set_coalesce(struct net_device *dev, struct ethtool_coalesce *ec)
12129 struct tg3 *tp = netdev_priv(dev);
12130 u32 max_rxcoal_tick_int = 0, max_txcoal_tick_int = 0;
12131 u32 max_stat_coal_ticks = 0, min_stat_coal_ticks = 0;
12133 if (!tg3_flag(tp, 5705_PLUS)) {
12134 max_rxcoal_tick_int = MAX_RXCOAL_TICK_INT;
12135 max_txcoal_tick_int = MAX_TXCOAL_TICK_INT;
12136 max_stat_coal_ticks = MAX_STAT_COAL_TICKS;
12137 min_stat_coal_ticks = MIN_STAT_COAL_TICKS;
12140 if ((ec->rx_coalesce_usecs > MAX_RXCOL_TICKS) ||
12141 (ec->tx_coalesce_usecs > MAX_TXCOL_TICKS) ||
12142 (ec->rx_max_coalesced_frames > MAX_RXMAX_FRAMES) ||
12143 (ec->tx_max_coalesced_frames > MAX_TXMAX_FRAMES) ||
12144 (ec->rx_coalesce_usecs_irq > max_rxcoal_tick_int) ||
12145 (ec->tx_coalesce_usecs_irq > max_txcoal_tick_int) ||
12146 (ec->rx_max_coalesced_frames_irq > MAX_RXCOAL_MAXF_INT) ||
12147 (ec->tx_max_coalesced_frames_irq > MAX_TXCOAL_MAXF_INT) ||
12148 (ec->stats_block_coalesce_usecs > max_stat_coal_ticks) ||
12149 (ec->stats_block_coalesce_usecs < min_stat_coal_ticks))
12152 /* No rx interrupts will be generated if both are zero */
12153 if ((ec->rx_coalesce_usecs == 0) &&
12154 (ec->rx_max_coalesced_frames == 0))
12157 /* No tx interrupts will be generated if both are zero */
12158 if ((ec->tx_coalesce_usecs == 0) &&
12159 (ec->tx_max_coalesced_frames == 0))
12162 /* Only copy relevant parameters, ignore all others. */
12163 tp->coal.rx_coalesce_usecs = ec->rx_coalesce_usecs;
12164 tp->coal.tx_coalesce_usecs = ec->tx_coalesce_usecs;
12165 tp->coal.rx_max_coalesced_frames = ec->rx_max_coalesced_frames;
12166 tp->coal.tx_max_coalesced_frames = ec->tx_max_coalesced_frames;
12167 tp->coal.rx_coalesce_usecs_irq = ec->rx_coalesce_usecs_irq;
12168 tp->coal.tx_coalesce_usecs_irq = ec->tx_coalesce_usecs_irq;
12169 tp->coal.rx_max_coalesced_frames_irq = ec->rx_max_coalesced_frames_irq;
12170 tp->coal.tx_max_coalesced_frames_irq = ec->tx_max_coalesced_frames_irq;
12171 tp->coal.stats_block_coalesce_usecs = ec->stats_block_coalesce_usecs;
12173 if (netif_running(dev)) {
12174 tg3_full_lock(tp, 0);
12175 __tg3_set_coalesce(tp, &tp->coal);
12176 tg3_full_unlock(tp);
12181 static const struct ethtool_ops tg3_ethtool_ops = {
12182 .get_settings = tg3_get_settings,
12183 .set_settings = tg3_set_settings,
12184 .get_drvinfo = tg3_get_drvinfo,
12185 .get_regs_len = tg3_get_regs_len,
12186 .get_regs = tg3_get_regs,
12187 .get_wol = tg3_get_wol,
12188 .set_wol = tg3_set_wol,
12189 .get_msglevel = tg3_get_msglevel,
12190 .set_msglevel = tg3_set_msglevel,
12191 .nway_reset = tg3_nway_reset,
12192 .get_link = ethtool_op_get_link,
12193 .get_eeprom_len = tg3_get_eeprom_len,
12194 .get_eeprom = tg3_get_eeprom,
12195 .set_eeprom = tg3_set_eeprom,
12196 .get_ringparam = tg3_get_ringparam,
12197 .set_ringparam = tg3_set_ringparam,
12198 .get_pauseparam = tg3_get_pauseparam,
12199 .set_pauseparam = tg3_set_pauseparam,
12200 .self_test = tg3_self_test,
12201 .get_strings = tg3_get_strings,
12202 .set_phys_id = tg3_set_phys_id,
12203 .get_ethtool_stats = tg3_get_ethtool_stats,
12204 .get_coalesce = tg3_get_coalesce,
12205 .set_coalesce = tg3_set_coalesce,
12206 .get_sset_count = tg3_get_sset_count,
12207 .get_rxnfc = tg3_get_rxnfc,
12208 .get_rxfh_indir_size = tg3_get_rxfh_indir_size,
12209 .get_rxfh_indir = tg3_get_rxfh_indir,
12210 .set_rxfh_indir = tg3_set_rxfh_indir,
12213 static void tg3_set_rx_mode(struct net_device *dev)
12215 struct tg3 *tp = netdev_priv(dev);
12217 if (!netif_running(dev))
12220 tg3_full_lock(tp, 0);
12221 __tg3_set_rx_mode(dev);
12222 tg3_full_unlock(tp);
12225 static inline void tg3_set_mtu(struct net_device *dev, struct tg3 *tp,
12228 dev->mtu = new_mtu;
12230 if (new_mtu > ETH_DATA_LEN) {
12231 if (tg3_flag(tp, 5780_CLASS)) {
12232 netdev_update_features(dev);
12233 tg3_flag_clear(tp, TSO_CAPABLE);
12235 tg3_flag_set(tp, JUMBO_RING_ENABLE);
12238 if (tg3_flag(tp, 5780_CLASS)) {
12239 tg3_flag_set(tp, TSO_CAPABLE);
12240 netdev_update_features(dev);
12242 tg3_flag_clear(tp, JUMBO_RING_ENABLE);
12246 static int tg3_change_mtu(struct net_device *dev, int new_mtu)
12248 struct tg3 *tp = netdev_priv(dev);
12251 if (new_mtu < TG3_MIN_MTU || new_mtu > TG3_MAX_MTU(tp))
12254 if (!netif_running(dev)) {
12255 /* We'll just catch it later when the
12258 tg3_set_mtu(dev, tp, new_mtu);
12264 tg3_netif_stop(tp);
12266 tg3_full_lock(tp, 1);
12268 tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
12270 tg3_set_mtu(dev, tp, new_mtu);
12272 err = tg3_restart_hw(tp, 0);
12275 tg3_netif_start(tp);
12277 tg3_full_unlock(tp);
12285 static const struct net_device_ops tg3_netdev_ops = {
12286 .ndo_open = tg3_open,
12287 .ndo_stop = tg3_close,
12288 .ndo_start_xmit = tg3_start_xmit,
12289 .ndo_get_stats64 = tg3_get_stats64,
12290 .ndo_validate_addr = eth_validate_addr,
12291 .ndo_set_rx_mode = tg3_set_rx_mode,
12292 .ndo_set_mac_address = tg3_set_mac_addr,
12293 .ndo_do_ioctl = tg3_ioctl,
12294 .ndo_tx_timeout = tg3_tx_timeout,
12295 .ndo_change_mtu = tg3_change_mtu,
12296 .ndo_fix_features = tg3_fix_features,
12297 .ndo_set_features = tg3_set_features,
12298 #ifdef CONFIG_NET_POLL_CONTROLLER
12299 .ndo_poll_controller = tg3_poll_controller,
12303 static void __devinit tg3_get_eeprom_size(struct tg3 *tp)
12305 u32 cursize, val, magic;
12307 tp->nvram_size = EEPROM_CHIP_SIZE;
12309 if (tg3_nvram_read(tp, 0, &magic) != 0)
12312 if ((magic != TG3_EEPROM_MAGIC) &&
12313 ((magic & TG3_EEPROM_MAGIC_FW_MSK) != TG3_EEPROM_MAGIC_FW) &&
12314 ((magic & TG3_EEPROM_MAGIC_HW_MSK) != TG3_EEPROM_MAGIC_HW))
12318 * Size the chip by reading offsets at increasing powers of two.
12319 * When we encounter our validation signature, we know the addressing
12320 * has wrapped around, and thus have our chip size.
12324 while (cursize < tp->nvram_size) {
12325 if (tg3_nvram_read(tp, cursize, &val) != 0)
12334 tp->nvram_size = cursize;
12337 static void __devinit tg3_get_nvram_size(struct tg3 *tp)
12341 if (tg3_flag(tp, NO_NVRAM) || tg3_nvram_read(tp, 0, &val) != 0)
12344 /* Selfboot format */
12345 if (val != TG3_EEPROM_MAGIC) {
12346 tg3_get_eeprom_size(tp);
12350 if (tg3_nvram_read(tp, 0xf0, &val) == 0) {
12352 /* This is confusing. We want to operate on the
12353 * 16-bit value at offset 0xf2. The tg3_nvram_read()
12354 * call will read from NVRAM and byteswap the data
12355 * according to the byteswapping settings for all
12356 * other register accesses. This ensures the data we
12357 * want will always reside in the lower 16-bits.
12358 * However, the data in NVRAM is in LE format, which
12359 * means the data from the NVRAM read will always be
12360 * opposite the endianness of the CPU. The 16-bit
12361 * byteswap then brings the data to CPU endianness.
12363 tp->nvram_size = swab16((u16)(val & 0x0000ffff)) * 1024;
12367 tp->nvram_size = TG3_NVRAM_SIZE_512KB;
12370 static void __devinit tg3_get_nvram_info(struct tg3 *tp)
12374 nvcfg1 = tr32(NVRAM_CFG1);
12375 if (nvcfg1 & NVRAM_CFG1_FLASHIF_ENAB) {
12376 tg3_flag_set(tp, FLASH);
12378 nvcfg1 &= ~NVRAM_CFG1_COMPAT_BYPASS;
12379 tw32(NVRAM_CFG1, nvcfg1);
12382 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5750 ||
12383 tg3_flag(tp, 5780_CLASS)) {
12384 switch (nvcfg1 & NVRAM_CFG1_VENDOR_MASK) {
12385 case FLASH_VENDOR_ATMEL_FLASH_BUFFERED:
12386 tp->nvram_jedecnum = JEDEC_ATMEL;
12387 tp->nvram_pagesize = ATMEL_AT45DB0X1B_PAGE_SIZE;
12388 tg3_flag_set(tp, NVRAM_BUFFERED);
12390 case FLASH_VENDOR_ATMEL_FLASH_UNBUFFERED:
12391 tp->nvram_jedecnum = JEDEC_ATMEL;
12392 tp->nvram_pagesize = ATMEL_AT25F512_PAGE_SIZE;
12394 case FLASH_VENDOR_ATMEL_EEPROM:
12395 tp->nvram_jedecnum = JEDEC_ATMEL;
12396 tp->nvram_pagesize = ATMEL_AT24C512_CHIP_SIZE;
12397 tg3_flag_set(tp, NVRAM_BUFFERED);
12399 case FLASH_VENDOR_ST:
12400 tp->nvram_jedecnum = JEDEC_ST;
12401 tp->nvram_pagesize = ST_M45PEX0_PAGE_SIZE;
12402 tg3_flag_set(tp, NVRAM_BUFFERED);
12404 case FLASH_VENDOR_SAIFUN:
12405 tp->nvram_jedecnum = JEDEC_SAIFUN;
12406 tp->nvram_pagesize = SAIFUN_SA25F0XX_PAGE_SIZE;
12408 case FLASH_VENDOR_SST_SMALL:
12409 case FLASH_VENDOR_SST_LARGE:
12410 tp->nvram_jedecnum = JEDEC_SST;
12411 tp->nvram_pagesize = SST_25VF0X0_PAGE_SIZE;
12415 tp->nvram_jedecnum = JEDEC_ATMEL;
12416 tp->nvram_pagesize = ATMEL_AT45DB0X1B_PAGE_SIZE;
12417 tg3_flag_set(tp, NVRAM_BUFFERED);
12421 static void __devinit tg3_nvram_get_pagesize(struct tg3 *tp, u32 nvmcfg1)
12423 switch (nvmcfg1 & NVRAM_CFG1_5752PAGE_SIZE_MASK) {
12424 case FLASH_5752PAGE_SIZE_256:
12425 tp->nvram_pagesize = 256;
12427 case FLASH_5752PAGE_SIZE_512:
12428 tp->nvram_pagesize = 512;
12430 case FLASH_5752PAGE_SIZE_1K:
12431 tp->nvram_pagesize = 1024;
12433 case FLASH_5752PAGE_SIZE_2K:
12434 tp->nvram_pagesize = 2048;
12436 case FLASH_5752PAGE_SIZE_4K:
12437 tp->nvram_pagesize = 4096;
12439 case FLASH_5752PAGE_SIZE_264:
12440 tp->nvram_pagesize = 264;
12442 case FLASH_5752PAGE_SIZE_528:
12443 tp->nvram_pagesize = 528;
12448 static void __devinit tg3_get_5752_nvram_info(struct tg3 *tp)
12452 nvcfg1 = tr32(NVRAM_CFG1);
12454 /* NVRAM protection for TPM */
12455 if (nvcfg1 & (1 << 27))
12456 tg3_flag_set(tp, PROTECTED_NVRAM);
12458 switch (nvcfg1 & NVRAM_CFG1_5752VENDOR_MASK) {
12459 case FLASH_5752VENDOR_ATMEL_EEPROM_64KHZ:
12460 case FLASH_5752VENDOR_ATMEL_EEPROM_376KHZ:
12461 tp->nvram_jedecnum = JEDEC_ATMEL;
12462 tg3_flag_set(tp, NVRAM_BUFFERED);
12464 case FLASH_5752VENDOR_ATMEL_FLASH_BUFFERED:
12465 tp->nvram_jedecnum = JEDEC_ATMEL;
12466 tg3_flag_set(tp, NVRAM_BUFFERED);
12467 tg3_flag_set(tp, FLASH);
12469 case FLASH_5752VENDOR_ST_M45PE10:
12470 case FLASH_5752VENDOR_ST_M45PE20:
12471 case FLASH_5752VENDOR_ST_M45PE40:
12472 tp->nvram_jedecnum = JEDEC_ST;
12473 tg3_flag_set(tp, NVRAM_BUFFERED);
12474 tg3_flag_set(tp, FLASH);
12478 if (tg3_flag(tp, FLASH)) {
12479 tg3_nvram_get_pagesize(tp, nvcfg1);
12481 /* For eeprom, set pagesize to maximum eeprom size */
12482 tp->nvram_pagesize = ATMEL_AT24C512_CHIP_SIZE;
12484 nvcfg1 &= ~NVRAM_CFG1_COMPAT_BYPASS;
12485 tw32(NVRAM_CFG1, nvcfg1);
12489 static void __devinit tg3_get_5755_nvram_info(struct tg3 *tp)
12491 u32 nvcfg1, protect = 0;
12493 nvcfg1 = tr32(NVRAM_CFG1);
12495 /* NVRAM protection for TPM */
12496 if (nvcfg1 & (1 << 27)) {
12497 tg3_flag_set(tp, PROTECTED_NVRAM);
12501 nvcfg1 &= NVRAM_CFG1_5752VENDOR_MASK;
12503 case FLASH_5755VENDOR_ATMEL_FLASH_1:
12504 case FLASH_5755VENDOR_ATMEL_FLASH_2:
12505 case FLASH_5755VENDOR_ATMEL_FLASH_3:
12506 case FLASH_5755VENDOR_ATMEL_FLASH_5:
12507 tp->nvram_jedecnum = JEDEC_ATMEL;
12508 tg3_flag_set(tp, NVRAM_BUFFERED);
12509 tg3_flag_set(tp, FLASH);
12510 tp->nvram_pagesize = 264;
12511 if (nvcfg1 == FLASH_5755VENDOR_ATMEL_FLASH_1 ||
12512 nvcfg1 == FLASH_5755VENDOR_ATMEL_FLASH_5)
12513 tp->nvram_size = (protect ? 0x3e200 :
12514 TG3_NVRAM_SIZE_512KB);
12515 else if (nvcfg1 == FLASH_5755VENDOR_ATMEL_FLASH_2)
12516 tp->nvram_size = (protect ? 0x1f200 :
12517 TG3_NVRAM_SIZE_256KB);
12519 tp->nvram_size = (protect ? 0x1f200 :
12520 TG3_NVRAM_SIZE_128KB);
12522 case FLASH_5752VENDOR_ST_M45PE10:
12523 case FLASH_5752VENDOR_ST_M45PE20:
12524 case FLASH_5752VENDOR_ST_M45PE40:
12525 tp->nvram_jedecnum = JEDEC_ST;
12526 tg3_flag_set(tp, NVRAM_BUFFERED);
12527 tg3_flag_set(tp, FLASH);
12528 tp->nvram_pagesize = 256;
12529 if (nvcfg1 == FLASH_5752VENDOR_ST_M45PE10)
12530 tp->nvram_size = (protect ?
12531 TG3_NVRAM_SIZE_64KB :
12532 TG3_NVRAM_SIZE_128KB);
12533 else if (nvcfg1 == FLASH_5752VENDOR_ST_M45PE20)
12534 tp->nvram_size = (protect ?
12535 TG3_NVRAM_SIZE_64KB :
12536 TG3_NVRAM_SIZE_256KB);
12538 tp->nvram_size = (protect ?
12539 TG3_NVRAM_SIZE_128KB :
12540 TG3_NVRAM_SIZE_512KB);
12545 static void __devinit tg3_get_5787_nvram_info(struct tg3 *tp)
12549 nvcfg1 = tr32(NVRAM_CFG1);
12551 switch (nvcfg1 & NVRAM_CFG1_5752VENDOR_MASK) {
12552 case FLASH_5787VENDOR_ATMEL_EEPROM_64KHZ:
12553 case FLASH_5787VENDOR_ATMEL_EEPROM_376KHZ:
12554 case FLASH_5787VENDOR_MICRO_EEPROM_64KHZ:
12555 case FLASH_5787VENDOR_MICRO_EEPROM_376KHZ:
12556 tp->nvram_jedecnum = JEDEC_ATMEL;
12557 tg3_flag_set(tp, NVRAM_BUFFERED);
12558 tp->nvram_pagesize = ATMEL_AT24C512_CHIP_SIZE;
12560 nvcfg1 &= ~NVRAM_CFG1_COMPAT_BYPASS;
12561 tw32(NVRAM_CFG1, nvcfg1);
12563 case FLASH_5752VENDOR_ATMEL_FLASH_BUFFERED:
12564 case FLASH_5755VENDOR_ATMEL_FLASH_1:
12565 case FLASH_5755VENDOR_ATMEL_FLASH_2:
12566 case FLASH_5755VENDOR_ATMEL_FLASH_3:
12567 tp->nvram_jedecnum = JEDEC_ATMEL;
12568 tg3_flag_set(tp, NVRAM_BUFFERED);
12569 tg3_flag_set(tp, FLASH);
12570 tp->nvram_pagesize = 264;
12572 case FLASH_5752VENDOR_ST_M45PE10:
12573 case FLASH_5752VENDOR_ST_M45PE20:
12574 case FLASH_5752VENDOR_ST_M45PE40:
12575 tp->nvram_jedecnum = JEDEC_ST;
12576 tg3_flag_set(tp, NVRAM_BUFFERED);
12577 tg3_flag_set(tp, FLASH);
12578 tp->nvram_pagesize = 256;
12583 static void __devinit tg3_get_5761_nvram_info(struct tg3 *tp)
12585 u32 nvcfg1, protect = 0;
12587 nvcfg1 = tr32(NVRAM_CFG1);
12589 /* NVRAM protection for TPM */
12590 if (nvcfg1 & (1 << 27)) {
12591 tg3_flag_set(tp, PROTECTED_NVRAM);
12595 nvcfg1 &= NVRAM_CFG1_5752VENDOR_MASK;
12597 case FLASH_5761VENDOR_ATMEL_ADB021D:
12598 case FLASH_5761VENDOR_ATMEL_ADB041D:
12599 case FLASH_5761VENDOR_ATMEL_ADB081D:
12600 case FLASH_5761VENDOR_ATMEL_ADB161D:
12601 case FLASH_5761VENDOR_ATMEL_MDB021D:
12602 case FLASH_5761VENDOR_ATMEL_MDB041D:
12603 case FLASH_5761VENDOR_ATMEL_MDB081D:
12604 case FLASH_5761VENDOR_ATMEL_MDB161D:
12605 tp->nvram_jedecnum = JEDEC_ATMEL;
12606 tg3_flag_set(tp, NVRAM_BUFFERED);
12607 tg3_flag_set(tp, FLASH);
12608 tg3_flag_set(tp, NO_NVRAM_ADDR_TRANS);
12609 tp->nvram_pagesize = 256;
12611 case FLASH_5761VENDOR_ST_A_M45PE20:
12612 case FLASH_5761VENDOR_ST_A_M45PE40:
12613 case FLASH_5761VENDOR_ST_A_M45PE80:
12614 case FLASH_5761VENDOR_ST_A_M45PE16:
12615 case FLASH_5761VENDOR_ST_M_M45PE20:
12616 case FLASH_5761VENDOR_ST_M_M45PE40:
12617 case FLASH_5761VENDOR_ST_M_M45PE80:
12618 case FLASH_5761VENDOR_ST_M_M45PE16:
12619 tp->nvram_jedecnum = JEDEC_ST;
12620 tg3_flag_set(tp, NVRAM_BUFFERED);
12621 tg3_flag_set(tp, FLASH);
12622 tp->nvram_pagesize = 256;
12627 tp->nvram_size = tr32(NVRAM_ADDR_LOCKOUT);
12630 case FLASH_5761VENDOR_ATMEL_ADB161D:
12631 case FLASH_5761VENDOR_ATMEL_MDB161D:
12632 case FLASH_5761VENDOR_ST_A_M45PE16:
12633 case FLASH_5761VENDOR_ST_M_M45PE16:
12634 tp->nvram_size = TG3_NVRAM_SIZE_2MB;
12636 case FLASH_5761VENDOR_ATMEL_ADB081D:
12637 case FLASH_5761VENDOR_ATMEL_MDB081D:
12638 case FLASH_5761VENDOR_ST_A_M45PE80:
12639 case FLASH_5761VENDOR_ST_M_M45PE80:
12640 tp->nvram_size = TG3_NVRAM_SIZE_1MB;
12642 case FLASH_5761VENDOR_ATMEL_ADB041D:
12643 case FLASH_5761VENDOR_ATMEL_MDB041D:
12644 case FLASH_5761VENDOR_ST_A_M45PE40:
12645 case FLASH_5761VENDOR_ST_M_M45PE40:
12646 tp->nvram_size = TG3_NVRAM_SIZE_512KB;
12648 case FLASH_5761VENDOR_ATMEL_ADB021D:
12649 case FLASH_5761VENDOR_ATMEL_MDB021D:
12650 case FLASH_5761VENDOR_ST_A_M45PE20:
12651 case FLASH_5761VENDOR_ST_M_M45PE20:
12652 tp->nvram_size = TG3_NVRAM_SIZE_256KB;
12658 static void __devinit tg3_get_5906_nvram_info(struct tg3 *tp)
12660 tp->nvram_jedecnum = JEDEC_ATMEL;
12661 tg3_flag_set(tp, NVRAM_BUFFERED);
12662 tp->nvram_pagesize = ATMEL_AT24C512_CHIP_SIZE;
12665 static void __devinit tg3_get_57780_nvram_info(struct tg3 *tp)
12669 nvcfg1 = tr32(NVRAM_CFG1);
12671 switch (nvcfg1 & NVRAM_CFG1_5752VENDOR_MASK) {
12672 case FLASH_5787VENDOR_ATMEL_EEPROM_376KHZ:
12673 case FLASH_5787VENDOR_MICRO_EEPROM_376KHZ:
12674 tp->nvram_jedecnum = JEDEC_ATMEL;
12675 tg3_flag_set(tp, NVRAM_BUFFERED);
12676 tp->nvram_pagesize = ATMEL_AT24C512_CHIP_SIZE;
12678 nvcfg1 &= ~NVRAM_CFG1_COMPAT_BYPASS;
12679 tw32(NVRAM_CFG1, nvcfg1);
12681 case FLASH_5752VENDOR_ATMEL_FLASH_BUFFERED:
12682 case FLASH_57780VENDOR_ATMEL_AT45DB011D:
12683 case FLASH_57780VENDOR_ATMEL_AT45DB011B:
12684 case FLASH_57780VENDOR_ATMEL_AT45DB021D:
12685 case FLASH_57780VENDOR_ATMEL_AT45DB021B:
12686 case FLASH_57780VENDOR_ATMEL_AT45DB041D:
12687 case FLASH_57780VENDOR_ATMEL_AT45DB041B:
12688 tp->nvram_jedecnum = JEDEC_ATMEL;
12689 tg3_flag_set(tp, NVRAM_BUFFERED);
12690 tg3_flag_set(tp, FLASH);
12692 switch (nvcfg1 & NVRAM_CFG1_5752VENDOR_MASK) {
12693 case FLASH_5752VENDOR_ATMEL_FLASH_BUFFERED:
12694 case FLASH_57780VENDOR_ATMEL_AT45DB011D:
12695 case FLASH_57780VENDOR_ATMEL_AT45DB011B:
12696 tp->nvram_size = TG3_NVRAM_SIZE_128KB;
12698 case FLASH_57780VENDOR_ATMEL_AT45DB021D:
12699 case FLASH_57780VENDOR_ATMEL_AT45DB021B:
12700 tp->nvram_size = TG3_NVRAM_SIZE_256KB;
12702 case FLASH_57780VENDOR_ATMEL_AT45DB041D:
12703 case FLASH_57780VENDOR_ATMEL_AT45DB041B:
12704 tp->nvram_size = TG3_NVRAM_SIZE_512KB;
12708 case FLASH_5752VENDOR_ST_M45PE10:
12709 case FLASH_5752VENDOR_ST_M45PE20:
12710 case FLASH_5752VENDOR_ST_M45PE40:
12711 tp->nvram_jedecnum = JEDEC_ST;
12712 tg3_flag_set(tp, NVRAM_BUFFERED);
12713 tg3_flag_set(tp, FLASH);
12715 switch (nvcfg1 & NVRAM_CFG1_5752VENDOR_MASK) {
12716 case FLASH_5752VENDOR_ST_M45PE10:
12717 tp->nvram_size = TG3_NVRAM_SIZE_128KB;
12719 case FLASH_5752VENDOR_ST_M45PE20:
12720 tp->nvram_size = TG3_NVRAM_SIZE_256KB;
12722 case FLASH_5752VENDOR_ST_M45PE40:
12723 tp->nvram_size = TG3_NVRAM_SIZE_512KB;
12728 tg3_flag_set(tp, NO_NVRAM);
12732 tg3_nvram_get_pagesize(tp, nvcfg1);
12733 if (tp->nvram_pagesize != 264 && tp->nvram_pagesize != 528)
12734 tg3_flag_set(tp, NO_NVRAM_ADDR_TRANS);
12738 static void __devinit tg3_get_5717_nvram_info(struct tg3 *tp)
12742 nvcfg1 = tr32(NVRAM_CFG1);
12744 switch (nvcfg1 & NVRAM_CFG1_5752VENDOR_MASK) {
12745 case FLASH_5717VENDOR_ATMEL_EEPROM:
12746 case FLASH_5717VENDOR_MICRO_EEPROM:
12747 tp->nvram_jedecnum = JEDEC_ATMEL;
12748 tg3_flag_set(tp, NVRAM_BUFFERED);
12749 tp->nvram_pagesize = ATMEL_AT24C512_CHIP_SIZE;
12751 nvcfg1 &= ~NVRAM_CFG1_COMPAT_BYPASS;
12752 tw32(NVRAM_CFG1, nvcfg1);
12754 case FLASH_5717VENDOR_ATMEL_MDB011D:
12755 case FLASH_5717VENDOR_ATMEL_ADB011B:
12756 case FLASH_5717VENDOR_ATMEL_ADB011D:
12757 case FLASH_5717VENDOR_ATMEL_MDB021D:
12758 case FLASH_5717VENDOR_ATMEL_ADB021B:
12759 case FLASH_5717VENDOR_ATMEL_ADB021D:
12760 case FLASH_5717VENDOR_ATMEL_45USPT:
12761 tp->nvram_jedecnum = JEDEC_ATMEL;
12762 tg3_flag_set(tp, NVRAM_BUFFERED);
12763 tg3_flag_set(tp, FLASH);
12765 switch (nvcfg1 & NVRAM_CFG1_5752VENDOR_MASK) {
12766 case FLASH_5717VENDOR_ATMEL_MDB021D:
12767 /* Detect size with tg3_nvram_get_size() */
12769 case FLASH_5717VENDOR_ATMEL_ADB021B:
12770 case FLASH_5717VENDOR_ATMEL_ADB021D:
12771 tp->nvram_size = TG3_NVRAM_SIZE_256KB;
12774 tp->nvram_size = TG3_NVRAM_SIZE_128KB;
12778 case FLASH_5717VENDOR_ST_M_M25PE10:
12779 case FLASH_5717VENDOR_ST_A_M25PE10:
12780 case FLASH_5717VENDOR_ST_M_M45PE10:
12781 case FLASH_5717VENDOR_ST_A_M45PE10:
12782 case FLASH_5717VENDOR_ST_M_M25PE20:
12783 case FLASH_5717VENDOR_ST_A_M25PE20:
12784 case FLASH_5717VENDOR_ST_M_M45PE20:
12785 case FLASH_5717VENDOR_ST_A_M45PE20:
12786 case FLASH_5717VENDOR_ST_25USPT:
12787 case FLASH_5717VENDOR_ST_45USPT:
12788 tp->nvram_jedecnum = JEDEC_ST;
12789 tg3_flag_set(tp, NVRAM_BUFFERED);
12790 tg3_flag_set(tp, FLASH);
12792 switch (nvcfg1 & NVRAM_CFG1_5752VENDOR_MASK) {
12793 case FLASH_5717VENDOR_ST_M_M25PE20:
12794 case FLASH_5717VENDOR_ST_M_M45PE20:
12795 /* Detect size with tg3_nvram_get_size() */
12797 case FLASH_5717VENDOR_ST_A_M25PE20:
12798 case FLASH_5717VENDOR_ST_A_M45PE20:
12799 tp->nvram_size = TG3_NVRAM_SIZE_256KB;
12802 tp->nvram_size = TG3_NVRAM_SIZE_128KB;
12807 tg3_flag_set(tp, NO_NVRAM);
12811 tg3_nvram_get_pagesize(tp, nvcfg1);
12812 if (tp->nvram_pagesize != 264 && tp->nvram_pagesize != 528)
12813 tg3_flag_set(tp, NO_NVRAM_ADDR_TRANS);
12816 static void __devinit tg3_get_5720_nvram_info(struct tg3 *tp)
12818 u32 nvcfg1, nvmpinstrp;
12820 nvcfg1 = tr32(NVRAM_CFG1);
12821 nvmpinstrp = nvcfg1 & NVRAM_CFG1_5752VENDOR_MASK;
12823 switch (nvmpinstrp) {
12824 case FLASH_5720_EEPROM_HD:
12825 case FLASH_5720_EEPROM_LD:
12826 tp->nvram_jedecnum = JEDEC_ATMEL;
12827 tg3_flag_set(tp, NVRAM_BUFFERED);
12829 nvcfg1 &= ~NVRAM_CFG1_COMPAT_BYPASS;
12830 tw32(NVRAM_CFG1, nvcfg1);
12831 if (nvmpinstrp == FLASH_5720_EEPROM_HD)
12832 tp->nvram_pagesize = ATMEL_AT24C512_CHIP_SIZE;
12834 tp->nvram_pagesize = ATMEL_AT24C02_CHIP_SIZE;
12836 case FLASH_5720VENDOR_M_ATMEL_DB011D:
12837 case FLASH_5720VENDOR_A_ATMEL_DB011B:
12838 case FLASH_5720VENDOR_A_ATMEL_DB011D:
12839 case FLASH_5720VENDOR_M_ATMEL_DB021D:
12840 case FLASH_5720VENDOR_A_ATMEL_DB021B:
12841 case FLASH_5720VENDOR_A_ATMEL_DB021D:
12842 case FLASH_5720VENDOR_M_ATMEL_DB041D:
12843 case FLASH_5720VENDOR_A_ATMEL_DB041B:
12844 case FLASH_5720VENDOR_A_ATMEL_DB041D:
12845 case FLASH_5720VENDOR_M_ATMEL_DB081D:
12846 case FLASH_5720VENDOR_A_ATMEL_DB081D:
12847 case FLASH_5720VENDOR_ATMEL_45USPT:
12848 tp->nvram_jedecnum = JEDEC_ATMEL;
12849 tg3_flag_set(tp, NVRAM_BUFFERED);
12850 tg3_flag_set(tp, FLASH);
12852 switch (nvmpinstrp) {
12853 case FLASH_5720VENDOR_M_ATMEL_DB021D:
12854 case FLASH_5720VENDOR_A_ATMEL_DB021B:
12855 case FLASH_5720VENDOR_A_ATMEL_DB021D:
12856 tp->nvram_size = TG3_NVRAM_SIZE_256KB;
12858 case FLASH_5720VENDOR_M_ATMEL_DB041D:
12859 case FLASH_5720VENDOR_A_ATMEL_DB041B:
12860 case FLASH_5720VENDOR_A_ATMEL_DB041D:
12861 tp->nvram_size = TG3_NVRAM_SIZE_512KB;
12863 case FLASH_5720VENDOR_M_ATMEL_DB081D:
12864 case FLASH_5720VENDOR_A_ATMEL_DB081D:
12865 tp->nvram_size = TG3_NVRAM_SIZE_1MB;
12868 tp->nvram_size = TG3_NVRAM_SIZE_128KB;
12872 case FLASH_5720VENDOR_M_ST_M25PE10:
12873 case FLASH_5720VENDOR_M_ST_M45PE10:
12874 case FLASH_5720VENDOR_A_ST_M25PE10:
12875 case FLASH_5720VENDOR_A_ST_M45PE10:
12876 case FLASH_5720VENDOR_M_ST_M25PE20:
12877 case FLASH_5720VENDOR_M_ST_M45PE20:
12878 case FLASH_5720VENDOR_A_ST_M25PE20:
12879 case FLASH_5720VENDOR_A_ST_M45PE20:
12880 case FLASH_5720VENDOR_M_ST_M25PE40:
12881 case FLASH_5720VENDOR_M_ST_M45PE40:
12882 case FLASH_5720VENDOR_A_ST_M25PE40:
12883 case FLASH_5720VENDOR_A_ST_M45PE40:
12884 case FLASH_5720VENDOR_M_ST_M25PE80:
12885 case FLASH_5720VENDOR_M_ST_M45PE80:
12886 case FLASH_5720VENDOR_A_ST_M25PE80:
12887 case FLASH_5720VENDOR_A_ST_M45PE80:
12888 case FLASH_5720VENDOR_ST_25USPT:
12889 case FLASH_5720VENDOR_ST_45USPT:
12890 tp->nvram_jedecnum = JEDEC_ST;
12891 tg3_flag_set(tp, NVRAM_BUFFERED);
12892 tg3_flag_set(tp, FLASH);
12894 switch (nvmpinstrp) {
12895 case FLASH_5720VENDOR_M_ST_M25PE20:
12896 case FLASH_5720VENDOR_M_ST_M45PE20:
12897 case FLASH_5720VENDOR_A_ST_M25PE20:
12898 case FLASH_5720VENDOR_A_ST_M45PE20:
12899 tp->nvram_size = TG3_NVRAM_SIZE_256KB;
12901 case FLASH_5720VENDOR_M_ST_M25PE40:
12902 case FLASH_5720VENDOR_M_ST_M45PE40:
12903 case FLASH_5720VENDOR_A_ST_M25PE40:
12904 case FLASH_5720VENDOR_A_ST_M45PE40:
12905 tp->nvram_size = TG3_NVRAM_SIZE_512KB;
12907 case FLASH_5720VENDOR_M_ST_M25PE80:
12908 case FLASH_5720VENDOR_M_ST_M45PE80:
12909 case FLASH_5720VENDOR_A_ST_M25PE80:
12910 case FLASH_5720VENDOR_A_ST_M45PE80:
12911 tp->nvram_size = TG3_NVRAM_SIZE_1MB;
12914 tp->nvram_size = TG3_NVRAM_SIZE_128KB;
12919 tg3_flag_set(tp, NO_NVRAM);
12923 tg3_nvram_get_pagesize(tp, nvcfg1);
12924 if (tp->nvram_pagesize != 264 && tp->nvram_pagesize != 528)
12925 tg3_flag_set(tp, NO_NVRAM_ADDR_TRANS);
12928 /* Chips other than 5700/5701 use the NVRAM for fetching info. */
12929 static void __devinit tg3_nvram_init(struct tg3 *tp)
12931 tw32_f(GRC_EEPROM_ADDR,
12932 (EEPROM_ADDR_FSM_RESET |
12933 (EEPROM_DEFAULT_CLOCK_PERIOD <<
12934 EEPROM_ADDR_CLKPERD_SHIFT)));
12938 /* Enable seeprom accesses. */
12939 tw32_f(GRC_LOCAL_CTRL,
12940 tr32(GRC_LOCAL_CTRL) | GRC_LCLCTRL_AUTO_SEEPROM);
12943 if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5700 &&
12944 GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5701) {
12945 tg3_flag_set(tp, NVRAM);
12947 if (tg3_nvram_lock(tp)) {
12948 netdev_warn(tp->dev,
12949 "Cannot get nvram lock, %s failed\n",
12953 tg3_enable_nvram_access(tp);
12955 tp->nvram_size = 0;
12957 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5752)
12958 tg3_get_5752_nvram_info(tp);
12959 else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5755)
12960 tg3_get_5755_nvram_info(tp);
12961 else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5787 ||
12962 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5784 ||
12963 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785)
12964 tg3_get_5787_nvram_info(tp);
12965 else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5761)
12966 tg3_get_5761_nvram_info(tp);
12967 else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906)
12968 tg3_get_5906_nvram_info(tp);
12969 else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57780 ||
12970 tg3_flag(tp, 57765_CLASS))
12971 tg3_get_57780_nvram_info(tp);
12972 else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717 ||
12973 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5719)
12974 tg3_get_5717_nvram_info(tp);
12975 else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5720)
12976 tg3_get_5720_nvram_info(tp);
12978 tg3_get_nvram_info(tp);
12980 if (tp->nvram_size == 0)
12981 tg3_get_nvram_size(tp);
12983 tg3_disable_nvram_access(tp);
12984 tg3_nvram_unlock(tp);
12987 tg3_flag_clear(tp, NVRAM);
12988 tg3_flag_clear(tp, NVRAM_BUFFERED);
12990 tg3_get_eeprom_size(tp);
12994 struct subsys_tbl_ent {
12995 u16 subsys_vendor, subsys_devid;
12999 static struct subsys_tbl_ent subsys_id_to_phy_id[] __devinitdata = {
13000 /* Broadcom boards. */
13001 { TG3PCI_SUBVENDOR_ID_BROADCOM,
13002 TG3PCI_SUBDEVICE_ID_BROADCOM_95700A6, TG3_PHY_ID_BCM5401 },
13003 { TG3PCI_SUBVENDOR_ID_BROADCOM,
13004 TG3PCI_SUBDEVICE_ID_BROADCOM_95701A5, TG3_PHY_ID_BCM5701 },
13005 { TG3PCI_SUBVENDOR_ID_BROADCOM,
13006 TG3PCI_SUBDEVICE_ID_BROADCOM_95700T6, TG3_PHY_ID_BCM8002 },
13007 { TG3PCI_SUBVENDOR_ID_BROADCOM,
13008 TG3PCI_SUBDEVICE_ID_BROADCOM_95700A9, 0 },
13009 { TG3PCI_SUBVENDOR_ID_BROADCOM,
13010 TG3PCI_SUBDEVICE_ID_BROADCOM_95701T1, TG3_PHY_ID_BCM5701 },
13011 { TG3PCI_SUBVENDOR_ID_BROADCOM,
13012 TG3PCI_SUBDEVICE_ID_BROADCOM_95701T8, TG3_PHY_ID_BCM5701 },
13013 { TG3PCI_SUBVENDOR_ID_BROADCOM,
13014 TG3PCI_SUBDEVICE_ID_BROADCOM_95701A7, 0 },
13015 { TG3PCI_SUBVENDOR_ID_BROADCOM,
13016 TG3PCI_SUBDEVICE_ID_BROADCOM_95701A10, TG3_PHY_ID_BCM5701 },
13017 { TG3PCI_SUBVENDOR_ID_BROADCOM,
13018 TG3PCI_SUBDEVICE_ID_BROADCOM_95701A12, TG3_PHY_ID_BCM5701 },
13019 { TG3PCI_SUBVENDOR_ID_BROADCOM,
13020 TG3PCI_SUBDEVICE_ID_BROADCOM_95703AX1, TG3_PHY_ID_BCM5703 },
13021 { TG3PCI_SUBVENDOR_ID_BROADCOM,
13022 TG3PCI_SUBDEVICE_ID_BROADCOM_95703AX2, TG3_PHY_ID_BCM5703 },
13025 { TG3PCI_SUBVENDOR_ID_3COM,
13026 TG3PCI_SUBDEVICE_ID_3COM_3C996T, TG3_PHY_ID_BCM5401 },
13027 { TG3PCI_SUBVENDOR_ID_3COM,
13028 TG3PCI_SUBDEVICE_ID_3COM_3C996BT, TG3_PHY_ID_BCM5701 },
13029 { TG3PCI_SUBVENDOR_ID_3COM,
13030 TG3PCI_SUBDEVICE_ID_3COM_3C996SX, 0 },
13031 { TG3PCI_SUBVENDOR_ID_3COM,
13032 TG3PCI_SUBDEVICE_ID_3COM_3C1000T, TG3_PHY_ID_BCM5701 },
13033 { TG3PCI_SUBVENDOR_ID_3COM,
13034 TG3PCI_SUBDEVICE_ID_3COM_3C940BR01, TG3_PHY_ID_BCM5701 },
13037 { TG3PCI_SUBVENDOR_ID_DELL,
13038 TG3PCI_SUBDEVICE_ID_DELL_VIPER, TG3_PHY_ID_BCM5401 },
13039 { TG3PCI_SUBVENDOR_ID_DELL,
13040 TG3PCI_SUBDEVICE_ID_DELL_JAGUAR, TG3_PHY_ID_BCM5401 },
13041 { TG3PCI_SUBVENDOR_ID_DELL,
13042 TG3PCI_SUBDEVICE_ID_DELL_MERLOT, TG3_PHY_ID_BCM5411 },
13043 { TG3PCI_SUBVENDOR_ID_DELL,
13044 TG3PCI_SUBDEVICE_ID_DELL_SLIM_MERLOT, TG3_PHY_ID_BCM5411 },
13046 /* Compaq boards. */
13047 { TG3PCI_SUBVENDOR_ID_COMPAQ,
13048 TG3PCI_SUBDEVICE_ID_COMPAQ_BANSHEE, TG3_PHY_ID_BCM5701 },
13049 { TG3PCI_SUBVENDOR_ID_COMPAQ,
13050 TG3PCI_SUBDEVICE_ID_COMPAQ_BANSHEE_2, TG3_PHY_ID_BCM5701 },
13051 { TG3PCI_SUBVENDOR_ID_COMPAQ,
13052 TG3PCI_SUBDEVICE_ID_COMPAQ_CHANGELING, 0 },
13053 { TG3PCI_SUBVENDOR_ID_COMPAQ,
13054 TG3PCI_SUBDEVICE_ID_COMPAQ_NC7780, TG3_PHY_ID_BCM5701 },
13055 { TG3PCI_SUBVENDOR_ID_COMPAQ,
13056 TG3PCI_SUBDEVICE_ID_COMPAQ_NC7780_2, TG3_PHY_ID_BCM5701 },
13059 { TG3PCI_SUBVENDOR_ID_IBM,
13060 TG3PCI_SUBDEVICE_ID_IBM_5703SAX2, 0 }
13063 static struct subsys_tbl_ent * __devinit tg3_lookup_by_subsys(struct tg3 *tp)
13067 for (i = 0; i < ARRAY_SIZE(subsys_id_to_phy_id); i++) {
13068 if ((subsys_id_to_phy_id[i].subsys_vendor ==
13069 tp->pdev->subsystem_vendor) &&
13070 (subsys_id_to_phy_id[i].subsys_devid ==
13071 tp->pdev->subsystem_device))
13072 return &subsys_id_to_phy_id[i];
13077 static void __devinit tg3_get_eeprom_hw_cfg(struct tg3 *tp)
13081 tp->phy_id = TG3_PHY_ID_INVALID;
13082 tp->led_ctrl = LED_CTRL_MODE_PHY_1;
13084 /* Assume an onboard device and WOL capable by default. */
13085 tg3_flag_set(tp, EEPROM_WRITE_PROT);
13086 tg3_flag_set(tp, WOL_CAP);
13088 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
13089 if (!(tr32(PCIE_TRANSACTION_CFG) & PCIE_TRANS_CFG_LOM)) {
13090 tg3_flag_clear(tp, EEPROM_WRITE_PROT);
13091 tg3_flag_set(tp, IS_NIC);
13093 val = tr32(VCPU_CFGSHDW);
13094 if (val & VCPU_CFGSHDW_ASPM_DBNC)
13095 tg3_flag_set(tp, ASPM_WORKAROUND);
13096 if ((val & VCPU_CFGSHDW_WOL_ENABLE) &&
13097 (val & VCPU_CFGSHDW_WOL_MAGPKT)) {
13098 tg3_flag_set(tp, WOL_ENABLE);
13099 device_set_wakeup_enable(&tp->pdev->dev, true);
13104 tg3_read_mem(tp, NIC_SRAM_DATA_SIG, &val);
13105 if (val == NIC_SRAM_DATA_SIG_MAGIC) {
13106 u32 nic_cfg, led_cfg;
13107 u32 nic_phy_id, ver, cfg2 = 0, cfg4 = 0, eeprom_phy_id;
13108 int eeprom_phy_serdes = 0;
13110 tg3_read_mem(tp, NIC_SRAM_DATA_CFG, &nic_cfg);
13111 tp->nic_sram_data_cfg = nic_cfg;
13113 tg3_read_mem(tp, NIC_SRAM_DATA_VER, &ver);
13114 ver >>= NIC_SRAM_DATA_VER_SHIFT;
13115 if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5700 &&
13116 GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5701 &&
13117 GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5703 &&
13118 (ver > 0) && (ver < 0x100))
13119 tg3_read_mem(tp, NIC_SRAM_DATA_CFG_2, &cfg2);
13121 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785)
13122 tg3_read_mem(tp, NIC_SRAM_DATA_CFG_4, &cfg4);
13124 if ((nic_cfg & NIC_SRAM_DATA_CFG_PHY_TYPE_MASK) ==
13125 NIC_SRAM_DATA_CFG_PHY_TYPE_FIBER)
13126 eeprom_phy_serdes = 1;
13128 tg3_read_mem(tp, NIC_SRAM_DATA_PHY_ID, &nic_phy_id);
13129 if (nic_phy_id != 0) {
13130 u32 id1 = nic_phy_id & NIC_SRAM_DATA_PHY_ID1_MASK;
13131 u32 id2 = nic_phy_id & NIC_SRAM_DATA_PHY_ID2_MASK;
13133 eeprom_phy_id = (id1 >> 16) << 10;
13134 eeprom_phy_id |= (id2 & 0xfc00) << 16;
13135 eeprom_phy_id |= (id2 & 0x03ff) << 0;
13139 tp->phy_id = eeprom_phy_id;
13140 if (eeprom_phy_serdes) {
13141 if (!tg3_flag(tp, 5705_PLUS))
13142 tp->phy_flags |= TG3_PHYFLG_PHY_SERDES;
13144 tp->phy_flags |= TG3_PHYFLG_MII_SERDES;
13147 if (tg3_flag(tp, 5750_PLUS))
13148 led_cfg = cfg2 & (NIC_SRAM_DATA_CFG_LED_MODE_MASK |
13149 SHASTA_EXT_LED_MODE_MASK);
13151 led_cfg = nic_cfg & NIC_SRAM_DATA_CFG_LED_MODE_MASK;
13155 case NIC_SRAM_DATA_CFG_LED_MODE_PHY_1:
13156 tp->led_ctrl = LED_CTRL_MODE_PHY_1;
13159 case NIC_SRAM_DATA_CFG_LED_MODE_PHY_2:
13160 tp->led_ctrl = LED_CTRL_MODE_PHY_2;
13163 case NIC_SRAM_DATA_CFG_LED_MODE_MAC:
13164 tp->led_ctrl = LED_CTRL_MODE_MAC;
13166 /* Default to PHY_1_MODE if 0 (MAC_MODE) is
13167 * read on some older 5700/5701 bootcode.
13169 if (GET_ASIC_REV(tp->pci_chip_rev_id) ==
13171 GET_ASIC_REV(tp->pci_chip_rev_id) ==
13173 tp->led_ctrl = LED_CTRL_MODE_PHY_1;
13177 case SHASTA_EXT_LED_SHARED:
13178 tp->led_ctrl = LED_CTRL_MODE_SHARED;
13179 if (tp->pci_chip_rev_id != CHIPREV_ID_5750_A0 &&
13180 tp->pci_chip_rev_id != CHIPREV_ID_5750_A1)
13181 tp->led_ctrl |= (LED_CTRL_MODE_PHY_1 |
13182 LED_CTRL_MODE_PHY_2);
13185 case SHASTA_EXT_LED_MAC:
13186 tp->led_ctrl = LED_CTRL_MODE_SHASTA_MAC;
13189 case SHASTA_EXT_LED_COMBO:
13190 tp->led_ctrl = LED_CTRL_MODE_COMBO;
13191 if (tp->pci_chip_rev_id != CHIPREV_ID_5750_A0)
13192 tp->led_ctrl |= (LED_CTRL_MODE_PHY_1 |
13193 LED_CTRL_MODE_PHY_2);
13198 if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
13199 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701) &&
13200 tp->pdev->subsystem_vendor == PCI_VENDOR_ID_DELL)
13201 tp->led_ctrl = LED_CTRL_MODE_PHY_2;
13203 if (GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5784_AX)
13204 tp->led_ctrl = LED_CTRL_MODE_PHY_1;
13206 if (nic_cfg & NIC_SRAM_DATA_CFG_EEPROM_WP) {
13207 tg3_flag_set(tp, EEPROM_WRITE_PROT);
13208 if ((tp->pdev->subsystem_vendor ==
13209 PCI_VENDOR_ID_ARIMA) &&
13210 (tp->pdev->subsystem_device == 0x205a ||
13211 tp->pdev->subsystem_device == 0x2063))
13212 tg3_flag_clear(tp, EEPROM_WRITE_PROT);
13214 tg3_flag_clear(tp, EEPROM_WRITE_PROT);
13215 tg3_flag_set(tp, IS_NIC);
13218 if (nic_cfg & NIC_SRAM_DATA_CFG_ASF_ENABLE) {
13219 tg3_flag_set(tp, ENABLE_ASF);
13220 if (tg3_flag(tp, 5750_PLUS))
13221 tg3_flag_set(tp, ASF_NEW_HANDSHAKE);
13224 if ((nic_cfg & NIC_SRAM_DATA_CFG_APE_ENABLE) &&
13225 tg3_flag(tp, 5750_PLUS))
13226 tg3_flag_set(tp, ENABLE_APE);
13228 if (tp->phy_flags & TG3_PHYFLG_ANY_SERDES &&
13229 !(nic_cfg & NIC_SRAM_DATA_CFG_FIBER_WOL))
13230 tg3_flag_clear(tp, WOL_CAP);
13232 if (tg3_flag(tp, WOL_CAP) &&
13233 (nic_cfg & NIC_SRAM_DATA_CFG_WOL_ENABLE)) {
13234 tg3_flag_set(tp, WOL_ENABLE);
13235 device_set_wakeup_enable(&tp->pdev->dev, true);
13238 if (cfg2 & (1 << 17))
13239 tp->phy_flags |= TG3_PHYFLG_CAPACITIVE_COUPLING;
13241 /* serdes signal pre-emphasis in register 0x590 set by */
13242 /* bootcode if bit 18 is set */
13243 if (cfg2 & (1 << 18))
13244 tp->phy_flags |= TG3_PHYFLG_SERDES_PREEMPHASIS;
13246 if ((tg3_flag(tp, 57765_PLUS) ||
13247 (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5784 &&
13248 GET_CHIP_REV(tp->pci_chip_rev_id) != CHIPREV_5784_AX)) &&
13249 (cfg2 & NIC_SRAM_DATA_CFG_2_APD_EN))
13250 tp->phy_flags |= TG3_PHYFLG_ENABLE_APD;
13252 if (tg3_flag(tp, PCI_EXPRESS) &&
13253 GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5785 &&
13254 !tg3_flag(tp, 57765_PLUS)) {
13257 tg3_read_mem(tp, NIC_SRAM_DATA_CFG_3, &cfg3);
13258 if (cfg3 & NIC_SRAM_ASPM_DEBOUNCE)
13259 tg3_flag_set(tp, ASPM_WORKAROUND);
13262 if (cfg4 & NIC_SRAM_RGMII_INBAND_DISABLE)
13263 tg3_flag_set(tp, RGMII_INBAND_DISABLE);
13264 if (cfg4 & NIC_SRAM_RGMII_EXT_IBND_RX_EN)
13265 tg3_flag_set(tp, RGMII_EXT_IBND_RX_EN);
13266 if (cfg4 & NIC_SRAM_RGMII_EXT_IBND_TX_EN)
13267 tg3_flag_set(tp, RGMII_EXT_IBND_TX_EN);
13270 if (tg3_flag(tp, WOL_CAP))
13271 device_set_wakeup_enable(&tp->pdev->dev,
13272 tg3_flag(tp, WOL_ENABLE));
13274 device_set_wakeup_capable(&tp->pdev->dev, false);
13277 static int __devinit tg3_issue_otp_command(struct tg3 *tp, u32 cmd)
13282 tw32(OTP_CTRL, cmd | OTP_CTRL_OTP_CMD_START);
13283 tw32(OTP_CTRL, cmd);
13285 /* Wait for up to 1 ms for command to execute. */
13286 for (i = 0; i < 100; i++) {
13287 val = tr32(OTP_STATUS);
13288 if (val & OTP_STATUS_CMD_DONE)
13293 return (val & OTP_STATUS_CMD_DONE) ? 0 : -EBUSY;
13296 /* Read the gphy configuration from the OTP region of the chip. The gphy
13297 * configuration is a 32-bit value that straddles the alignment boundary.
13298 * We do two 32-bit reads and then shift and merge the results.
13300 static u32 __devinit tg3_read_otp_phycfg(struct tg3 *tp)
13302 u32 bhalf_otp, thalf_otp;
13304 tw32(OTP_MODE, OTP_MODE_OTP_THRU_GRC);
13306 if (tg3_issue_otp_command(tp, OTP_CTRL_OTP_CMD_INIT))
13309 tw32(OTP_ADDRESS, OTP_ADDRESS_MAGIC1);
13311 if (tg3_issue_otp_command(tp, OTP_CTRL_OTP_CMD_READ))
13314 thalf_otp = tr32(OTP_READ_DATA);
13316 tw32(OTP_ADDRESS, OTP_ADDRESS_MAGIC2);
13318 if (tg3_issue_otp_command(tp, OTP_CTRL_OTP_CMD_READ))
13321 bhalf_otp = tr32(OTP_READ_DATA);
13323 return ((thalf_otp & 0x0000ffff) << 16) | (bhalf_otp >> 16);
13326 static void __devinit tg3_phy_init_link_config(struct tg3 *tp)
13328 u32 adv = ADVERTISED_Autoneg;
13330 if (!(tp->phy_flags & TG3_PHYFLG_10_100_ONLY))
13331 adv |= ADVERTISED_1000baseT_Half |
13332 ADVERTISED_1000baseT_Full;
13334 if (!(tp->phy_flags & TG3_PHYFLG_ANY_SERDES))
13335 adv |= ADVERTISED_100baseT_Half |
13336 ADVERTISED_100baseT_Full |
13337 ADVERTISED_10baseT_Half |
13338 ADVERTISED_10baseT_Full |
13341 adv |= ADVERTISED_FIBRE;
13343 tp->link_config.advertising = adv;
13344 tp->link_config.speed = SPEED_INVALID;
13345 tp->link_config.duplex = DUPLEX_INVALID;
13346 tp->link_config.autoneg = AUTONEG_ENABLE;
13347 tp->link_config.active_speed = SPEED_INVALID;
13348 tp->link_config.active_duplex = DUPLEX_INVALID;
13349 tp->link_config.orig_speed = SPEED_INVALID;
13350 tp->link_config.orig_duplex = DUPLEX_INVALID;
13351 tp->link_config.orig_autoneg = AUTONEG_INVALID;
13354 static int __devinit tg3_phy_probe(struct tg3 *tp)
13356 u32 hw_phy_id_1, hw_phy_id_2;
13357 u32 hw_phy_id, hw_phy_id_masked;
13360 /* flow control autonegotiation is default behavior */
13361 tg3_flag_set(tp, PAUSE_AUTONEG);
13362 tp->link_config.flowctrl = FLOW_CTRL_TX | FLOW_CTRL_RX;
13364 if (tg3_flag(tp, USE_PHYLIB))
13365 return tg3_phy_init(tp);
13367 /* Reading the PHY ID register can conflict with ASF
13368 * firmware access to the PHY hardware.
13371 if (tg3_flag(tp, ENABLE_ASF) || tg3_flag(tp, ENABLE_APE)) {
13372 hw_phy_id = hw_phy_id_masked = TG3_PHY_ID_INVALID;
13374 /* Now read the physical PHY_ID from the chip and verify
13375 * that it is sane. If it doesn't look good, we fall back
13376 * to either the hard-coded table based PHY_ID and failing
13377 * that the value found in the eeprom area.
13379 err |= tg3_readphy(tp, MII_PHYSID1, &hw_phy_id_1);
13380 err |= tg3_readphy(tp, MII_PHYSID2, &hw_phy_id_2);
13382 hw_phy_id = (hw_phy_id_1 & 0xffff) << 10;
13383 hw_phy_id |= (hw_phy_id_2 & 0xfc00) << 16;
13384 hw_phy_id |= (hw_phy_id_2 & 0x03ff) << 0;
13386 hw_phy_id_masked = hw_phy_id & TG3_PHY_ID_MASK;
13389 if (!err && TG3_KNOWN_PHY_ID(hw_phy_id_masked)) {
13390 tp->phy_id = hw_phy_id;
13391 if (hw_phy_id_masked == TG3_PHY_ID_BCM8002)
13392 tp->phy_flags |= TG3_PHYFLG_PHY_SERDES;
13394 tp->phy_flags &= ~TG3_PHYFLG_PHY_SERDES;
13396 if (tp->phy_id != TG3_PHY_ID_INVALID) {
13397 /* Do nothing, phy ID already set up in
13398 * tg3_get_eeprom_hw_cfg().
13401 struct subsys_tbl_ent *p;
13403 /* No eeprom signature? Try the hardcoded
13404 * subsys device table.
13406 p = tg3_lookup_by_subsys(tp);
13410 tp->phy_id = p->phy_id;
13412 tp->phy_id == TG3_PHY_ID_BCM8002)
13413 tp->phy_flags |= TG3_PHYFLG_PHY_SERDES;
13417 if (!(tp->phy_flags & TG3_PHYFLG_ANY_SERDES) &&
13418 (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5719 ||
13419 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5720 ||
13420 (tp->pdev->device == TG3PCI_DEVICE_TIGON3_5718 &&
13421 tp->pci_chip_rev_id != CHIPREV_ID_5717_A0) ||
13422 (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57765 &&
13423 tp->pci_chip_rev_id != CHIPREV_ID_57765_A0)))
13424 tp->phy_flags |= TG3_PHYFLG_EEE_CAP;
13426 tg3_phy_init_link_config(tp);
13428 if (!(tp->phy_flags & TG3_PHYFLG_ANY_SERDES) &&
13429 !tg3_flag(tp, ENABLE_APE) &&
13430 !tg3_flag(tp, ENABLE_ASF)) {
13433 tg3_readphy(tp, MII_BMSR, &bmsr);
13434 if (!tg3_readphy(tp, MII_BMSR, &bmsr) &&
13435 (bmsr & BMSR_LSTATUS))
13436 goto skip_phy_reset;
13438 err = tg3_phy_reset(tp);
13442 tg3_phy_set_wirespeed(tp);
13444 if (!tg3_phy_copper_an_config_ok(tp, &dummy)) {
13445 tg3_phy_autoneg_cfg(tp, tp->link_config.advertising,
13446 tp->link_config.flowctrl);
13448 tg3_writephy(tp, MII_BMCR,
13449 BMCR_ANENABLE | BMCR_ANRESTART);
13454 if ((tp->phy_id & TG3_PHY_ID_MASK) == TG3_PHY_ID_BCM5401) {
13455 err = tg3_init_5401phy_dsp(tp);
13459 err = tg3_init_5401phy_dsp(tp);
13465 static void __devinit tg3_read_vpd(struct tg3 *tp)
13468 unsigned int block_end, rosize, len;
13472 vpd_data = (u8 *)tg3_vpd_readblock(tp, &vpdlen);
13476 i = pci_vpd_find_tag(vpd_data, 0, vpdlen, PCI_VPD_LRDT_RO_DATA);
13478 goto out_not_found;
13480 rosize = pci_vpd_lrdt_size(&vpd_data[i]);
13481 block_end = i + PCI_VPD_LRDT_TAG_SIZE + rosize;
13482 i += PCI_VPD_LRDT_TAG_SIZE;
13484 if (block_end > vpdlen)
13485 goto out_not_found;
13487 j = pci_vpd_find_info_keyword(vpd_data, i, rosize,
13488 PCI_VPD_RO_KEYWORD_MFR_ID);
13490 len = pci_vpd_info_field_size(&vpd_data[j]);
13492 j += PCI_VPD_INFO_FLD_HDR_SIZE;
13493 if (j + len > block_end || len != 4 ||
13494 memcmp(&vpd_data[j], "1028", 4))
13497 j = pci_vpd_find_info_keyword(vpd_data, i, rosize,
13498 PCI_VPD_RO_KEYWORD_VENDOR0);
13502 len = pci_vpd_info_field_size(&vpd_data[j]);
13504 j += PCI_VPD_INFO_FLD_HDR_SIZE;
13505 if (j + len > block_end)
13508 memcpy(tp->fw_ver, &vpd_data[j], len);
13509 strncat(tp->fw_ver, " bc ", vpdlen - len - 1);
13513 i = pci_vpd_find_info_keyword(vpd_data, i, rosize,
13514 PCI_VPD_RO_KEYWORD_PARTNO);
13516 goto out_not_found;
13518 len = pci_vpd_info_field_size(&vpd_data[i]);
13520 i += PCI_VPD_INFO_FLD_HDR_SIZE;
13521 if (len > TG3_BPN_SIZE ||
13522 (len + i) > vpdlen)
13523 goto out_not_found;
13525 memcpy(tp->board_part_number, &vpd_data[i], len);
13529 if (tp->board_part_number[0])
13533 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717) {
13534 if (tp->pdev->device == TG3PCI_DEVICE_TIGON3_5717)
13535 strcpy(tp->board_part_number, "BCM5717");
13536 else if (tp->pdev->device == TG3PCI_DEVICE_TIGON3_5718)
13537 strcpy(tp->board_part_number, "BCM5718");
13540 } else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57780) {
13541 if (tp->pdev->device == TG3PCI_DEVICE_TIGON3_57780)
13542 strcpy(tp->board_part_number, "BCM57780");
13543 else if (tp->pdev->device == TG3PCI_DEVICE_TIGON3_57760)
13544 strcpy(tp->board_part_number, "BCM57760");
13545 else if (tp->pdev->device == TG3PCI_DEVICE_TIGON3_57790)
13546 strcpy(tp->board_part_number, "BCM57790");
13547 else if (tp->pdev->device == TG3PCI_DEVICE_TIGON3_57788)
13548 strcpy(tp->board_part_number, "BCM57788");
13551 } else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57765) {
13552 if (tp->pdev->device == TG3PCI_DEVICE_TIGON3_57761)
13553 strcpy(tp->board_part_number, "BCM57761");
13554 else if (tp->pdev->device == TG3PCI_DEVICE_TIGON3_57765)
13555 strcpy(tp->board_part_number, "BCM57765");
13556 else if (tp->pdev->device == TG3PCI_DEVICE_TIGON3_57781)
13557 strcpy(tp->board_part_number, "BCM57781");
13558 else if (tp->pdev->device == TG3PCI_DEVICE_TIGON3_57785)
13559 strcpy(tp->board_part_number, "BCM57785");
13560 else if (tp->pdev->device == TG3PCI_DEVICE_TIGON3_57791)
13561 strcpy(tp->board_part_number, "BCM57791");
13562 else if (tp->pdev->device == TG3PCI_DEVICE_TIGON3_57795)
13563 strcpy(tp->board_part_number, "BCM57795");
13566 } else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57766) {
13567 if (tp->pdev->device == TG3PCI_DEVICE_TIGON3_57762)
13568 strcpy(tp->board_part_number, "BCM57762");
13569 else if (tp->pdev->device == TG3PCI_DEVICE_TIGON3_57766)
13570 strcpy(tp->board_part_number, "BCM57766");
13571 else if (tp->pdev->device == TG3PCI_DEVICE_TIGON3_57782)
13572 strcpy(tp->board_part_number, "BCM57782");
13573 else if (tp->pdev->device == TG3PCI_DEVICE_TIGON3_57786)
13574 strcpy(tp->board_part_number, "BCM57786");
13577 } else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
13578 strcpy(tp->board_part_number, "BCM95906");
13581 strcpy(tp->board_part_number, "none");
13585 static int __devinit tg3_fw_img_is_valid(struct tg3 *tp, u32 offset)
13589 if (tg3_nvram_read(tp, offset, &val) ||
13590 (val & 0xfc000000) != 0x0c000000 ||
13591 tg3_nvram_read(tp, offset + 4, &val) ||
13598 static void __devinit tg3_read_bc_ver(struct tg3 *tp)
13600 u32 val, offset, start, ver_offset;
13602 bool newver = false;
13604 if (tg3_nvram_read(tp, 0xc, &offset) ||
13605 tg3_nvram_read(tp, 0x4, &start))
13608 offset = tg3_nvram_logical_addr(tp, offset);
13610 if (tg3_nvram_read(tp, offset, &val))
13613 if ((val & 0xfc000000) == 0x0c000000) {
13614 if (tg3_nvram_read(tp, offset + 4, &val))
13621 dst_off = strlen(tp->fw_ver);
13624 if (TG3_VER_SIZE - dst_off < 16 ||
13625 tg3_nvram_read(tp, offset + 8, &ver_offset))
13628 offset = offset + ver_offset - start;
13629 for (i = 0; i < 16; i += 4) {
13631 if (tg3_nvram_read_be32(tp, offset + i, &v))
13634 memcpy(tp->fw_ver + dst_off + i, &v, sizeof(v));
13639 if (tg3_nvram_read(tp, TG3_NVM_PTREV_BCVER, &ver_offset))
13642 major = (ver_offset & TG3_NVM_BCVER_MAJMSK) >>
13643 TG3_NVM_BCVER_MAJSFT;
13644 minor = ver_offset & TG3_NVM_BCVER_MINMSK;
13645 snprintf(&tp->fw_ver[dst_off], TG3_VER_SIZE - dst_off,
13646 "v%d.%02d", major, minor);
13650 static void __devinit tg3_read_hwsb_ver(struct tg3 *tp)
13652 u32 val, major, minor;
13654 /* Use native endian representation */
13655 if (tg3_nvram_read(tp, TG3_NVM_HWSB_CFG1, &val))
13658 major = (val & TG3_NVM_HWSB_CFG1_MAJMSK) >>
13659 TG3_NVM_HWSB_CFG1_MAJSFT;
13660 minor = (val & TG3_NVM_HWSB_CFG1_MINMSK) >>
13661 TG3_NVM_HWSB_CFG1_MINSFT;
13663 snprintf(&tp->fw_ver[0], 32, "sb v%d.%02d", major, minor);
13666 static void __devinit tg3_read_sb_ver(struct tg3 *tp, u32 val)
13668 u32 offset, major, minor, build;
13670 strncat(tp->fw_ver, "sb", TG3_VER_SIZE - strlen(tp->fw_ver) - 1);
13672 if ((val & TG3_EEPROM_SB_FORMAT_MASK) != TG3_EEPROM_SB_FORMAT_1)
13675 switch (val & TG3_EEPROM_SB_REVISION_MASK) {
13676 case TG3_EEPROM_SB_REVISION_0:
13677 offset = TG3_EEPROM_SB_F1R0_EDH_OFF;
13679 case TG3_EEPROM_SB_REVISION_2:
13680 offset = TG3_EEPROM_SB_F1R2_EDH_OFF;
13682 case TG3_EEPROM_SB_REVISION_3:
13683 offset = TG3_EEPROM_SB_F1R3_EDH_OFF;
13685 case TG3_EEPROM_SB_REVISION_4:
13686 offset = TG3_EEPROM_SB_F1R4_EDH_OFF;
13688 case TG3_EEPROM_SB_REVISION_5:
13689 offset = TG3_EEPROM_SB_F1R5_EDH_OFF;
13691 case TG3_EEPROM_SB_REVISION_6:
13692 offset = TG3_EEPROM_SB_F1R6_EDH_OFF;
13698 if (tg3_nvram_read(tp, offset, &val))
13701 build = (val & TG3_EEPROM_SB_EDH_BLD_MASK) >>
13702 TG3_EEPROM_SB_EDH_BLD_SHFT;
13703 major = (val & TG3_EEPROM_SB_EDH_MAJ_MASK) >>
13704 TG3_EEPROM_SB_EDH_MAJ_SHFT;
13705 minor = val & TG3_EEPROM_SB_EDH_MIN_MASK;
13707 if (minor > 99 || build > 26)
13710 offset = strlen(tp->fw_ver);
13711 snprintf(&tp->fw_ver[offset], TG3_VER_SIZE - offset,
13712 " v%d.%02d", major, minor);
13715 offset = strlen(tp->fw_ver);
13716 if (offset < TG3_VER_SIZE - 1)
13717 tp->fw_ver[offset] = 'a' + build - 1;
13721 static void __devinit tg3_read_mgmtfw_ver(struct tg3 *tp)
13723 u32 val, offset, start;
13726 for (offset = TG3_NVM_DIR_START;
13727 offset < TG3_NVM_DIR_END;
13728 offset += TG3_NVM_DIRENT_SIZE) {
13729 if (tg3_nvram_read(tp, offset, &val))
13732 if ((val >> TG3_NVM_DIRTYPE_SHIFT) == TG3_NVM_DIRTYPE_ASFINI)
13736 if (offset == TG3_NVM_DIR_END)
13739 if (!tg3_flag(tp, 5705_PLUS))
13740 start = 0x08000000;
13741 else if (tg3_nvram_read(tp, offset - 4, &start))
13744 if (tg3_nvram_read(tp, offset + 4, &offset) ||
13745 !tg3_fw_img_is_valid(tp, offset) ||
13746 tg3_nvram_read(tp, offset + 8, &val))
13749 offset += val - start;
13751 vlen = strlen(tp->fw_ver);
13753 tp->fw_ver[vlen++] = ',';
13754 tp->fw_ver[vlen++] = ' ';
13756 for (i = 0; i < 4; i++) {
13758 if (tg3_nvram_read_be32(tp, offset, &v))
13761 offset += sizeof(v);
13763 if (vlen > TG3_VER_SIZE - sizeof(v)) {
13764 memcpy(&tp->fw_ver[vlen], &v, TG3_VER_SIZE - vlen);
13768 memcpy(&tp->fw_ver[vlen], &v, sizeof(v));
13773 static void __devinit tg3_read_dash_ver(struct tg3 *tp)
13779 if (!tg3_flag(tp, ENABLE_APE) || !tg3_flag(tp, ENABLE_ASF))
13782 apedata = tg3_ape_read32(tp, TG3_APE_SEG_SIG);
13783 if (apedata != APE_SEG_SIG_MAGIC)
13786 apedata = tg3_ape_read32(tp, TG3_APE_FW_STATUS);
13787 if (!(apedata & APE_FW_STATUS_READY))
13790 apedata = tg3_ape_read32(tp, TG3_APE_FW_VERSION);
13792 if (tg3_ape_read32(tp, TG3_APE_FW_FEATURES) & TG3_APE_FW_FEATURE_NCSI) {
13793 tg3_flag_set(tp, APE_HAS_NCSI);
13799 vlen = strlen(tp->fw_ver);
13801 snprintf(&tp->fw_ver[vlen], TG3_VER_SIZE - vlen, " %s v%d.%d.%d.%d",
13803 (apedata & APE_FW_VERSION_MAJMSK) >> APE_FW_VERSION_MAJSFT,
13804 (apedata & APE_FW_VERSION_MINMSK) >> APE_FW_VERSION_MINSFT,
13805 (apedata & APE_FW_VERSION_REVMSK) >> APE_FW_VERSION_REVSFT,
13806 (apedata & APE_FW_VERSION_BLDMSK));
13809 static void __devinit tg3_read_fw_ver(struct tg3 *tp)
13812 bool vpd_vers = false;
13814 if (tp->fw_ver[0] != 0)
13817 if (tg3_flag(tp, NO_NVRAM)) {
13818 strcat(tp->fw_ver, "sb");
13822 if (tg3_nvram_read(tp, 0, &val))
13825 if (val == TG3_EEPROM_MAGIC)
13826 tg3_read_bc_ver(tp);
13827 else if ((val & TG3_EEPROM_MAGIC_FW_MSK) == TG3_EEPROM_MAGIC_FW)
13828 tg3_read_sb_ver(tp, val);
13829 else if ((val & TG3_EEPROM_MAGIC_HW_MSK) == TG3_EEPROM_MAGIC_HW)
13830 tg3_read_hwsb_ver(tp);
13837 if (tg3_flag(tp, ENABLE_APE)) {
13838 if (tg3_flag(tp, ENABLE_ASF))
13839 tg3_read_dash_ver(tp);
13840 } else if (tg3_flag(tp, ENABLE_ASF)) {
13841 tg3_read_mgmtfw_ver(tp);
13845 tp->fw_ver[TG3_VER_SIZE - 1] = 0;
13848 static inline u32 tg3_rx_ret_ring_size(struct tg3 *tp)
13850 if (tg3_flag(tp, LRG_PROD_RING_CAP))
13851 return TG3_RX_RET_MAX_SIZE_5717;
13852 else if (tg3_flag(tp, JUMBO_CAPABLE) && !tg3_flag(tp, 5780_CLASS))
13853 return TG3_RX_RET_MAX_SIZE_5700;
13855 return TG3_RX_RET_MAX_SIZE_5705;
13858 static DEFINE_PCI_DEVICE_TABLE(tg3_write_reorder_chipsets) = {
13859 { PCI_DEVICE(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_FE_GATE_700C) },
13860 { PCI_DEVICE(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_8131_BRIDGE) },
13861 { PCI_DEVICE(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8385_0) },
13865 static struct pci_dev * __devinit tg3_find_peer(struct tg3 *tp)
13867 struct pci_dev *peer;
13868 unsigned int func, devnr = tp->pdev->devfn & ~7;
13870 for (func = 0; func < 8; func++) {
13871 peer = pci_get_slot(tp->pdev->bus, devnr | func);
13872 if (peer && peer != tp->pdev)
13876 /* 5704 can be configured in single-port mode, set peer to
13877 * tp->pdev in that case.
13885 * We don't need to keep the refcount elevated; there's no way
13886 * to remove one half of this device without removing the other
13893 static int __devinit tg3_get_invariants(struct tg3 *tp)
13896 u32 pci_state_reg, grc_misc_cfg;
13901 /* Force memory write invalidate off. If we leave it on,
13902 * then on 5700_BX chips we have to enable a workaround.
13903 * The workaround is to set the TG3PCI_DMA_RW_CTRL boundary
13904 * to match the cacheline size. The Broadcom driver have this
13905 * workaround but turns MWI off all the times so never uses
13906 * it. This seems to suggest that the workaround is insufficient.
13908 pci_read_config_word(tp->pdev, PCI_COMMAND, &pci_cmd);
13909 pci_cmd &= ~PCI_COMMAND_INVALIDATE;
13910 pci_write_config_word(tp->pdev, PCI_COMMAND, pci_cmd);
13912 /* Important! -- Make sure register accesses are byteswapped
13913 * correctly. Also, for those chips that require it, make
13914 * sure that indirect register accesses are enabled before
13915 * the first operation.
13917 pci_read_config_dword(tp->pdev, TG3PCI_MISC_HOST_CTRL,
13919 tp->misc_host_ctrl |= (misc_ctrl_reg &
13920 MISC_HOST_CTRL_CHIPREV);
13921 pci_write_config_dword(tp->pdev, TG3PCI_MISC_HOST_CTRL,
13922 tp->misc_host_ctrl);
13924 tp->pci_chip_rev_id = (misc_ctrl_reg >>
13925 MISC_HOST_CTRL_CHIPREV_SHIFT);
13926 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_USE_PROD_ID_REG) {
13927 u32 prod_id_asic_rev;
13929 if (tp->pdev->device == TG3PCI_DEVICE_TIGON3_5717 ||
13930 tp->pdev->device == TG3PCI_DEVICE_TIGON3_5718 ||
13931 tp->pdev->device == TG3PCI_DEVICE_TIGON3_5719 ||
13932 tp->pdev->device == TG3PCI_DEVICE_TIGON3_5720)
13933 pci_read_config_dword(tp->pdev,
13934 TG3PCI_GEN2_PRODID_ASICREV,
13935 &prod_id_asic_rev);
13936 else if (tp->pdev->device == TG3PCI_DEVICE_TIGON3_57781 ||
13937 tp->pdev->device == TG3PCI_DEVICE_TIGON3_57785 ||
13938 tp->pdev->device == TG3PCI_DEVICE_TIGON3_57761 ||
13939 tp->pdev->device == TG3PCI_DEVICE_TIGON3_57765 ||
13940 tp->pdev->device == TG3PCI_DEVICE_TIGON3_57791 ||
13941 tp->pdev->device == TG3PCI_DEVICE_TIGON3_57795 ||
13942 tp->pdev->device == TG3PCI_DEVICE_TIGON3_57762 ||
13943 tp->pdev->device == TG3PCI_DEVICE_TIGON3_57766 ||
13944 tp->pdev->device == TG3PCI_DEVICE_TIGON3_57782 ||
13945 tp->pdev->device == TG3PCI_DEVICE_TIGON3_57786)
13946 pci_read_config_dword(tp->pdev,
13947 TG3PCI_GEN15_PRODID_ASICREV,
13948 &prod_id_asic_rev);
13950 pci_read_config_dword(tp->pdev, TG3PCI_PRODID_ASICREV,
13951 &prod_id_asic_rev);
13953 tp->pci_chip_rev_id = prod_id_asic_rev;
13956 /* Wrong chip ID in 5752 A0. This code can be removed later
13957 * as A0 is not in production.
13959 if (tp->pci_chip_rev_id == CHIPREV_ID_5752_A0_HW)
13960 tp->pci_chip_rev_id = CHIPREV_ID_5752_A0;
13962 /* If we have 5702/03 A1 or A2 on certain ICH chipsets,
13963 * we need to disable memory and use config. cycles
13964 * only to access all registers. The 5702/03 chips
13965 * can mistakenly decode the special cycles from the
13966 * ICH chipsets as memory write cycles, causing corruption
13967 * of register and memory space. Only certain ICH bridges
13968 * will drive special cycles with non-zero data during the
13969 * address phase which can fall within the 5703's address
13970 * range. This is not an ICH bug as the PCI spec allows
13971 * non-zero address during special cycles. However, only
13972 * these ICH bridges are known to drive non-zero addresses
13973 * during special cycles.
13975 * Since special cycles do not cross PCI bridges, we only
13976 * enable this workaround if the 5703 is on the secondary
13977 * bus of these ICH bridges.
13979 if ((tp->pci_chip_rev_id == CHIPREV_ID_5703_A1) ||
13980 (tp->pci_chip_rev_id == CHIPREV_ID_5703_A2)) {
13981 static struct tg3_dev_id {
13985 } ich_chipsets[] = {
13986 { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801AA_8,
13988 { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801AB_8,
13990 { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801BA_11,
13992 { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801BA_6,
13996 struct tg3_dev_id *pci_id = &ich_chipsets[0];
13997 struct pci_dev *bridge = NULL;
13999 while (pci_id->vendor != 0) {
14000 bridge = pci_get_device(pci_id->vendor, pci_id->device,
14006 if (pci_id->rev != PCI_ANY_ID) {
14007 if (bridge->revision > pci_id->rev)
14010 if (bridge->subordinate &&
14011 (bridge->subordinate->number ==
14012 tp->pdev->bus->number)) {
14013 tg3_flag_set(tp, ICH_WORKAROUND);
14014 pci_dev_put(bridge);
14020 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701) {
14021 static struct tg3_dev_id {
14024 } bridge_chipsets[] = {
14025 { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_PXH_0 },
14026 { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_PXH_1 },
14029 struct tg3_dev_id *pci_id = &bridge_chipsets[0];
14030 struct pci_dev *bridge = NULL;
14032 while (pci_id->vendor != 0) {
14033 bridge = pci_get_device(pci_id->vendor,
14040 if (bridge->subordinate &&
14041 (bridge->subordinate->number <=
14042 tp->pdev->bus->number) &&
14043 (bridge->subordinate->subordinate >=
14044 tp->pdev->bus->number)) {
14045 tg3_flag_set(tp, 5701_DMA_BUG);
14046 pci_dev_put(bridge);
14052 /* The EPB bridge inside 5714, 5715, and 5780 cannot support
14053 * DMA addresses > 40-bit. This bridge may have other additional
14054 * 57xx devices behind it in some 4-port NIC designs for example.
14055 * Any tg3 device found behind the bridge will also need the 40-bit
14058 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5780 ||
14059 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5714) {
14060 tg3_flag_set(tp, 5780_CLASS);
14061 tg3_flag_set(tp, 40BIT_DMA_BUG);
14062 tp->msi_cap = pci_find_capability(tp->pdev, PCI_CAP_ID_MSI);
14064 struct pci_dev *bridge = NULL;
14067 bridge = pci_get_device(PCI_VENDOR_ID_SERVERWORKS,
14068 PCI_DEVICE_ID_SERVERWORKS_EPB,
14070 if (bridge && bridge->subordinate &&
14071 (bridge->subordinate->number <=
14072 tp->pdev->bus->number) &&
14073 (bridge->subordinate->subordinate >=
14074 tp->pdev->bus->number)) {
14075 tg3_flag_set(tp, 40BIT_DMA_BUG);
14076 pci_dev_put(bridge);
14082 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704 ||
14083 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5714)
14084 tp->pdev_peer = tg3_find_peer(tp);
14086 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717 ||
14087 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5719 ||
14088 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5720)
14089 tg3_flag_set(tp, 5717_PLUS);
14091 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57765 ||
14092 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57766)
14093 tg3_flag_set(tp, 57765_CLASS);
14095 if (tg3_flag(tp, 57765_CLASS) || tg3_flag(tp, 5717_PLUS))
14096 tg3_flag_set(tp, 57765_PLUS);
14098 /* Intentionally exclude ASIC_REV_5906 */
14099 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5755 ||
14100 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5787 ||
14101 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5784 ||
14102 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5761 ||
14103 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785 ||
14104 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57780 ||
14105 tg3_flag(tp, 57765_PLUS))
14106 tg3_flag_set(tp, 5755_PLUS);
14108 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5750 ||
14109 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5752 ||
14110 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906 ||
14111 tg3_flag(tp, 5755_PLUS) ||
14112 tg3_flag(tp, 5780_CLASS))
14113 tg3_flag_set(tp, 5750_PLUS);
14115 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705 ||
14116 tg3_flag(tp, 5750_PLUS))
14117 tg3_flag_set(tp, 5705_PLUS);
14119 /* Determine TSO capabilities */
14120 if (tp->pci_chip_rev_id == CHIPREV_ID_5719_A0)
14121 ; /* Do nothing. HW bug. */
14122 else if (tg3_flag(tp, 57765_PLUS))
14123 tg3_flag_set(tp, HW_TSO_3);
14124 else if (tg3_flag(tp, 5755_PLUS) ||
14125 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906)
14126 tg3_flag_set(tp, HW_TSO_2);
14127 else if (tg3_flag(tp, 5750_PLUS)) {
14128 tg3_flag_set(tp, HW_TSO_1);
14129 tg3_flag_set(tp, TSO_BUG);
14130 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5750 &&
14131 tp->pci_chip_rev_id >= CHIPREV_ID_5750_C2)
14132 tg3_flag_clear(tp, TSO_BUG);
14133 } else if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5700 &&
14134 GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5701 &&
14135 tp->pci_chip_rev_id != CHIPREV_ID_5705_A0) {
14136 tg3_flag_set(tp, TSO_BUG);
14137 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705)
14138 tp->fw_needed = FIRMWARE_TG3TSO5;
14140 tp->fw_needed = FIRMWARE_TG3TSO;
14143 /* Selectively allow TSO based on operating conditions */
14144 if (tg3_flag(tp, HW_TSO_1) ||
14145 tg3_flag(tp, HW_TSO_2) ||
14146 tg3_flag(tp, HW_TSO_3) ||
14148 /* For firmware TSO, assume ASF is disabled.
14149 * We'll disable TSO later if we discover ASF
14150 * is enabled in tg3_get_eeprom_hw_cfg().
14152 tg3_flag_set(tp, TSO_CAPABLE);
14154 tg3_flag_clear(tp, TSO_CAPABLE);
14155 tg3_flag_clear(tp, TSO_BUG);
14156 tp->fw_needed = NULL;
14159 if (tp->pci_chip_rev_id == CHIPREV_ID_5701_A0)
14160 tp->fw_needed = FIRMWARE_TG3;
14164 if (tg3_flag(tp, 5750_PLUS)) {
14165 tg3_flag_set(tp, SUPPORT_MSI);
14166 if (GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5750_AX ||
14167 GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5750_BX ||
14168 (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5714 &&
14169 tp->pci_chip_rev_id <= CHIPREV_ID_5714_A2 &&
14170 tp->pdev_peer == tp->pdev))
14171 tg3_flag_clear(tp, SUPPORT_MSI);
14173 if (tg3_flag(tp, 5755_PLUS) ||
14174 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
14175 tg3_flag_set(tp, 1SHOT_MSI);
14178 if (tg3_flag(tp, 57765_PLUS)) {
14179 tg3_flag_set(tp, SUPPORT_MSIX);
14180 tp->irq_max = TG3_IRQ_MAX_VECS;
14181 tg3_rss_init_dflt_indir_tbl(tp);
14185 if (tg3_flag(tp, 5755_PLUS))
14186 tg3_flag_set(tp, SHORT_DMA_BUG);
14188 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5719)
14189 tp->dma_limit = TG3_TX_BD_DMA_MAX_4K;
14191 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717 ||
14192 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5719 ||
14193 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5720)
14194 tg3_flag_set(tp, LRG_PROD_RING_CAP);
14196 if (tg3_flag(tp, 57765_PLUS) &&
14197 tp->pci_chip_rev_id != CHIPREV_ID_5719_A0)
14198 tg3_flag_set(tp, USE_JUMBO_BDFLAG);
14200 if (!tg3_flag(tp, 5705_PLUS) ||
14201 tg3_flag(tp, 5780_CLASS) ||
14202 tg3_flag(tp, USE_JUMBO_BDFLAG))
14203 tg3_flag_set(tp, JUMBO_CAPABLE);
14205 pci_read_config_dword(tp->pdev, TG3PCI_PCISTATE,
14208 if (pci_is_pcie(tp->pdev)) {
14211 tg3_flag_set(tp, PCI_EXPRESS);
14213 if (tp->pci_chip_rev_id == CHIPREV_ID_5719_A0) {
14214 int readrq = pcie_get_readrq(tp->pdev);
14216 pcie_set_readrq(tp->pdev, 2048);
14219 pci_read_config_word(tp->pdev,
14220 pci_pcie_cap(tp->pdev) + PCI_EXP_LNKCTL,
14222 if (lnkctl & PCI_EXP_LNKCTL_CLKREQ_EN) {
14223 if (GET_ASIC_REV(tp->pci_chip_rev_id) ==
14225 tg3_flag_clear(tp, HW_TSO_2);
14226 tg3_flag_clear(tp, TSO_CAPABLE);
14228 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5784 ||
14229 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5761 ||
14230 tp->pci_chip_rev_id == CHIPREV_ID_57780_A0 ||
14231 tp->pci_chip_rev_id == CHIPREV_ID_57780_A1)
14232 tg3_flag_set(tp, CLKREQ_BUG);
14233 } else if (tp->pci_chip_rev_id == CHIPREV_ID_5717_A0) {
14234 tg3_flag_set(tp, L1PLLPD_EN);
14236 } else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785) {
14237 /* BCM5785 devices are effectively PCIe devices, and should
14238 * follow PCIe codepaths, but do not have a PCIe capabilities
14241 tg3_flag_set(tp, PCI_EXPRESS);
14242 } else if (!tg3_flag(tp, 5705_PLUS) ||
14243 tg3_flag(tp, 5780_CLASS)) {
14244 tp->pcix_cap = pci_find_capability(tp->pdev, PCI_CAP_ID_PCIX);
14245 if (!tp->pcix_cap) {
14246 dev_err(&tp->pdev->dev,
14247 "Cannot find PCI-X capability, aborting\n");
14251 if (!(pci_state_reg & PCISTATE_CONV_PCI_MODE))
14252 tg3_flag_set(tp, PCIX_MODE);
14255 /* If we have an AMD 762 or VIA K8T800 chipset, write
14256 * reordering to the mailbox registers done by the host
14257 * controller can cause major troubles. We read back from
14258 * every mailbox register write to force the writes to be
14259 * posted to the chip in order.
14261 if (pci_dev_present(tg3_write_reorder_chipsets) &&
14262 !tg3_flag(tp, PCI_EXPRESS))
14263 tg3_flag_set(tp, MBOX_WRITE_REORDER);
14265 pci_read_config_byte(tp->pdev, PCI_CACHE_LINE_SIZE,
14266 &tp->pci_cacheline_sz);
14267 pci_read_config_byte(tp->pdev, PCI_LATENCY_TIMER,
14268 &tp->pci_lat_timer);
14269 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703 &&
14270 tp->pci_lat_timer < 64) {
14271 tp->pci_lat_timer = 64;
14272 pci_write_config_byte(tp->pdev, PCI_LATENCY_TIMER,
14273 tp->pci_lat_timer);
14276 /* Important! -- It is critical that the PCI-X hw workaround
14277 * situation is decided before the first MMIO register access.
14279 if (GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5700_BX) {
14280 /* 5700 BX chips need to have their TX producer index
14281 * mailboxes written twice to workaround a bug.
14283 tg3_flag_set(tp, TXD_MBOX_HWBUG);
14285 /* If we are in PCI-X mode, enable register write workaround.
14287 * The workaround is to use indirect register accesses
14288 * for all chip writes not to mailbox registers.
14290 if (tg3_flag(tp, PCIX_MODE)) {
14293 tg3_flag_set(tp, PCIX_TARGET_HWBUG);
14295 /* The chip can have it's power management PCI config
14296 * space registers clobbered due to this bug.
14297 * So explicitly force the chip into D0 here.
14299 pci_read_config_dword(tp->pdev,
14300 tp->pm_cap + PCI_PM_CTRL,
14302 pm_reg &= ~PCI_PM_CTRL_STATE_MASK;
14303 pm_reg |= PCI_PM_CTRL_PME_ENABLE | 0 /* D0 */;
14304 pci_write_config_dword(tp->pdev,
14305 tp->pm_cap + PCI_PM_CTRL,
14308 /* Also, force SERR#/PERR# in PCI command. */
14309 pci_read_config_word(tp->pdev, PCI_COMMAND, &pci_cmd);
14310 pci_cmd |= PCI_COMMAND_PARITY | PCI_COMMAND_SERR;
14311 pci_write_config_word(tp->pdev, PCI_COMMAND, pci_cmd);
14315 if ((pci_state_reg & PCISTATE_BUS_SPEED_HIGH) != 0)
14316 tg3_flag_set(tp, PCI_HIGH_SPEED);
14317 if ((pci_state_reg & PCISTATE_BUS_32BIT) != 0)
14318 tg3_flag_set(tp, PCI_32BIT);
14320 /* Chip-specific fixup from Broadcom driver */
14321 if ((tp->pci_chip_rev_id == CHIPREV_ID_5704_A0) &&
14322 (!(pci_state_reg & PCISTATE_RETRY_SAME_DMA))) {
14323 pci_state_reg |= PCISTATE_RETRY_SAME_DMA;
14324 pci_write_config_dword(tp->pdev, TG3PCI_PCISTATE, pci_state_reg);
14327 /* Default fast path register access methods */
14328 tp->read32 = tg3_read32;
14329 tp->write32 = tg3_write32;
14330 tp->read32_mbox = tg3_read32;
14331 tp->write32_mbox = tg3_write32;
14332 tp->write32_tx_mbox = tg3_write32;
14333 tp->write32_rx_mbox = tg3_write32;
14335 /* Various workaround register access methods */
14336 if (tg3_flag(tp, PCIX_TARGET_HWBUG))
14337 tp->write32 = tg3_write_indirect_reg32;
14338 else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701 ||
14339 (tg3_flag(tp, PCI_EXPRESS) &&
14340 tp->pci_chip_rev_id == CHIPREV_ID_5750_A0)) {
14342 * Back to back register writes can cause problems on these
14343 * chips, the workaround is to read back all reg writes
14344 * except those to mailbox regs.
14346 * See tg3_write_indirect_reg32().
14348 tp->write32 = tg3_write_flush_reg32;
14351 if (tg3_flag(tp, TXD_MBOX_HWBUG) || tg3_flag(tp, MBOX_WRITE_REORDER)) {
14352 tp->write32_tx_mbox = tg3_write32_tx_mbox;
14353 if (tg3_flag(tp, MBOX_WRITE_REORDER))
14354 tp->write32_rx_mbox = tg3_write_flush_reg32;
14357 if (tg3_flag(tp, ICH_WORKAROUND)) {
14358 tp->read32 = tg3_read_indirect_reg32;
14359 tp->write32 = tg3_write_indirect_reg32;
14360 tp->read32_mbox = tg3_read_indirect_mbox;
14361 tp->write32_mbox = tg3_write_indirect_mbox;
14362 tp->write32_tx_mbox = tg3_write_indirect_mbox;
14363 tp->write32_rx_mbox = tg3_write_indirect_mbox;
14368 pci_read_config_word(tp->pdev, PCI_COMMAND, &pci_cmd);
14369 pci_cmd &= ~PCI_COMMAND_MEMORY;
14370 pci_write_config_word(tp->pdev, PCI_COMMAND, pci_cmd);
14372 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
14373 tp->read32_mbox = tg3_read32_mbox_5906;
14374 tp->write32_mbox = tg3_write32_mbox_5906;
14375 tp->write32_tx_mbox = tg3_write32_mbox_5906;
14376 tp->write32_rx_mbox = tg3_write32_mbox_5906;
14379 if (tp->write32 == tg3_write_indirect_reg32 ||
14380 (tg3_flag(tp, PCIX_MODE) &&
14381 (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
14382 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701)))
14383 tg3_flag_set(tp, SRAM_USE_CONFIG);
14385 /* The memory arbiter has to be enabled in order for SRAM accesses
14386 * to succeed. Normally on powerup the tg3 chip firmware will make
14387 * sure it is enabled, but other entities such as system netboot
14388 * code might disable it.
14390 val = tr32(MEMARB_MODE);
14391 tw32(MEMARB_MODE, val | MEMARB_MODE_ENABLE);
14393 tp->pci_fn = PCI_FUNC(tp->pdev->devfn) & 3;
14394 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704 ||
14395 tg3_flag(tp, 5780_CLASS)) {
14396 if (tg3_flag(tp, PCIX_MODE)) {
14397 pci_read_config_dword(tp->pdev,
14398 tp->pcix_cap + PCI_X_STATUS,
14400 tp->pci_fn = val & 0x7;
14402 } else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717) {
14403 tg3_read_mem(tp, NIC_SRAM_CPMU_STATUS, &val);
14404 if ((val & NIC_SRAM_CPMUSTAT_SIG_MSK) ==
14405 NIC_SRAM_CPMUSTAT_SIG) {
14406 tp->pci_fn = val & TG3_CPMU_STATUS_FMSK_5717;
14407 tp->pci_fn = tp->pci_fn ? 1 : 0;
14409 } else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5719 ||
14410 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5720) {
14411 tg3_read_mem(tp, NIC_SRAM_CPMU_STATUS, &val);
14412 if ((val & NIC_SRAM_CPMUSTAT_SIG_MSK) ==
14413 NIC_SRAM_CPMUSTAT_SIG) {
14414 tp->pci_fn = (val & TG3_CPMU_STATUS_FMSK_5719) >>
14415 TG3_CPMU_STATUS_FSHFT_5719;
14419 /* Get eeprom hw config before calling tg3_set_power_state().
14420 * In particular, the TG3_FLAG_IS_NIC flag must be
14421 * determined before calling tg3_set_power_state() so that
14422 * we know whether or not to switch out of Vaux power.
14423 * When the flag is set, it means that GPIO1 is used for eeprom
14424 * write protect and also implies that it is a LOM where GPIOs
14425 * are not used to switch power.
14427 tg3_get_eeprom_hw_cfg(tp);
14429 if (tp->fw_needed && tg3_flag(tp, ENABLE_ASF)) {
14430 tg3_flag_clear(tp, TSO_CAPABLE);
14431 tg3_flag_clear(tp, TSO_BUG);
14432 tp->fw_needed = NULL;
14435 if (tg3_flag(tp, ENABLE_APE)) {
14436 /* Allow reads and writes to the
14437 * APE register and memory space.
14439 pci_state_reg |= PCISTATE_ALLOW_APE_CTLSPC_WR |
14440 PCISTATE_ALLOW_APE_SHMEM_WR |
14441 PCISTATE_ALLOW_APE_PSPACE_WR;
14442 pci_write_config_dword(tp->pdev, TG3PCI_PCISTATE,
14445 tg3_ape_lock_init(tp);
14448 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5784 ||
14449 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5761 ||
14450 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785 ||
14451 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57780 ||
14452 tg3_flag(tp, 57765_PLUS))
14453 tg3_flag_set(tp, CPMU_PRESENT);
14455 /* Set up tp->grc_local_ctrl before calling
14456 * tg3_pwrsrc_switch_to_vmain(). GPIO1 driven high
14457 * will bring 5700's external PHY out of reset.
14458 * It is also used as eeprom write protect on LOMs.
14460 tp->grc_local_ctrl = GRC_LCLCTRL_INT_ON_ATTN | GRC_LCLCTRL_AUTO_SEEPROM;
14461 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
14462 tg3_flag(tp, EEPROM_WRITE_PROT))
14463 tp->grc_local_ctrl |= (GRC_LCLCTRL_GPIO_OE1 |
14464 GRC_LCLCTRL_GPIO_OUTPUT1);
14465 /* Unused GPIO3 must be driven as output on 5752 because there
14466 * are no pull-up resistors on unused GPIO pins.
14468 else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5752)
14469 tp->grc_local_ctrl |= GRC_LCLCTRL_GPIO_OE3;
14471 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5755 ||
14472 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57780 ||
14473 tg3_flag(tp, 57765_CLASS))
14474 tp->grc_local_ctrl |= GRC_LCLCTRL_GPIO_UART_SEL;
14476 if (tp->pdev->device == PCI_DEVICE_ID_TIGON3_5761 ||
14477 tp->pdev->device == TG3PCI_DEVICE_TIGON3_5761S) {
14478 /* Turn off the debug UART. */
14479 tp->grc_local_ctrl |= GRC_LCLCTRL_GPIO_UART_SEL;
14480 if (tg3_flag(tp, IS_NIC))
14481 /* Keep VMain power. */
14482 tp->grc_local_ctrl |= GRC_LCLCTRL_GPIO_OE0 |
14483 GRC_LCLCTRL_GPIO_OUTPUT0;
14486 /* Switch out of Vaux if it is a NIC */
14487 tg3_pwrsrc_switch_to_vmain(tp);
14489 /* Derive initial jumbo mode from MTU assigned in
14490 * ether_setup() via the alloc_etherdev() call
14492 if (tp->dev->mtu > ETH_DATA_LEN && !tg3_flag(tp, 5780_CLASS))
14493 tg3_flag_set(tp, JUMBO_RING_ENABLE);
14495 /* Determine WakeOnLan speed to use. */
14496 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
14497 tp->pci_chip_rev_id == CHIPREV_ID_5701_A0 ||
14498 tp->pci_chip_rev_id == CHIPREV_ID_5701_B0 ||
14499 tp->pci_chip_rev_id == CHIPREV_ID_5701_B2) {
14500 tg3_flag_clear(tp, WOL_SPEED_100MB);
14502 tg3_flag_set(tp, WOL_SPEED_100MB);
14505 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906)
14506 tp->phy_flags |= TG3_PHYFLG_IS_FET;
14508 /* A few boards don't want Ethernet@WireSpeed phy feature */
14509 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
14510 (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705 &&
14511 (tp->pci_chip_rev_id != CHIPREV_ID_5705_A0) &&
14512 (tp->pci_chip_rev_id != CHIPREV_ID_5705_A1)) ||
14513 (tp->phy_flags & TG3_PHYFLG_IS_FET) ||
14514 (tp->phy_flags & TG3_PHYFLG_ANY_SERDES))
14515 tp->phy_flags |= TG3_PHYFLG_NO_ETH_WIRE_SPEED;
14517 if (GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5703_AX ||
14518 GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5704_AX)
14519 tp->phy_flags |= TG3_PHYFLG_ADC_BUG;
14520 if (tp->pci_chip_rev_id == CHIPREV_ID_5704_A0)
14521 tp->phy_flags |= TG3_PHYFLG_5704_A0_BUG;
14523 if (tg3_flag(tp, 5705_PLUS) &&
14524 !(tp->phy_flags & TG3_PHYFLG_IS_FET) &&
14525 GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5785 &&
14526 GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_57780 &&
14527 !tg3_flag(tp, 57765_PLUS)) {
14528 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5755 ||
14529 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5787 ||
14530 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5784 ||
14531 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5761) {
14532 if (tp->pdev->device != PCI_DEVICE_ID_TIGON3_5756 &&
14533 tp->pdev->device != PCI_DEVICE_ID_TIGON3_5722)
14534 tp->phy_flags |= TG3_PHYFLG_JITTER_BUG;
14535 if (tp->pdev->device == PCI_DEVICE_ID_TIGON3_5755M)
14536 tp->phy_flags |= TG3_PHYFLG_ADJUST_TRIM;
14538 tp->phy_flags |= TG3_PHYFLG_BER_BUG;
14541 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5784 &&
14542 GET_CHIP_REV(tp->pci_chip_rev_id) != CHIPREV_5784_AX) {
14543 tp->phy_otp = tg3_read_otp_phycfg(tp);
14544 if (tp->phy_otp == 0)
14545 tp->phy_otp = TG3_OTP_DEFAULT;
14548 if (tg3_flag(tp, CPMU_PRESENT))
14549 tp->mi_mode = MAC_MI_MODE_500KHZ_CONST;
14551 tp->mi_mode = MAC_MI_MODE_BASE;
14553 tp->coalesce_mode = 0;
14554 if (GET_CHIP_REV(tp->pci_chip_rev_id) != CHIPREV_5700_AX &&
14555 GET_CHIP_REV(tp->pci_chip_rev_id) != CHIPREV_5700_BX)
14556 tp->coalesce_mode |= HOSTCC_MODE_32BYTE;
14558 /* Set these bits to enable statistics workaround. */
14559 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717 ||
14560 tp->pci_chip_rev_id == CHIPREV_ID_5719_A0 ||
14561 tp->pci_chip_rev_id == CHIPREV_ID_5720_A0) {
14562 tp->coalesce_mode |= HOSTCC_MODE_ATTN;
14563 tp->grc_mode |= GRC_MODE_IRQ_ON_FLOW_ATTN;
14566 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785 ||
14567 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57780)
14568 tg3_flag_set(tp, USE_PHYLIB);
14570 err = tg3_mdio_init(tp);
14574 /* Initialize data/descriptor byte/word swapping. */
14575 val = tr32(GRC_MODE);
14576 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5720)
14577 val &= (GRC_MODE_BYTE_SWAP_B2HRX_DATA |
14578 GRC_MODE_WORD_SWAP_B2HRX_DATA |
14579 GRC_MODE_B2HRX_ENABLE |
14580 GRC_MODE_HTX2B_ENABLE |
14581 GRC_MODE_HOST_STACKUP);
14583 val &= GRC_MODE_HOST_STACKUP;
14585 tw32(GRC_MODE, val | tp->grc_mode);
14587 tg3_switch_clocks(tp);
14589 /* Clear this out for sanity. */
14590 tw32(TG3PCI_MEM_WIN_BASE_ADDR, 0);
14592 pci_read_config_dword(tp->pdev, TG3PCI_PCISTATE,
14594 if ((pci_state_reg & PCISTATE_CONV_PCI_MODE) == 0 &&
14595 !tg3_flag(tp, PCIX_TARGET_HWBUG)) {
14596 u32 chiprevid = GET_CHIP_REV_ID(tp->misc_host_ctrl);
14598 if (chiprevid == CHIPREV_ID_5701_A0 ||
14599 chiprevid == CHIPREV_ID_5701_B0 ||
14600 chiprevid == CHIPREV_ID_5701_B2 ||
14601 chiprevid == CHIPREV_ID_5701_B5) {
14602 void __iomem *sram_base;
14604 /* Write some dummy words into the SRAM status block
14605 * area, see if it reads back correctly. If the return
14606 * value is bad, force enable the PCIX workaround.
14608 sram_base = tp->regs + NIC_SRAM_WIN_BASE + NIC_SRAM_STATS_BLK;
14610 writel(0x00000000, sram_base);
14611 writel(0x00000000, sram_base + 4);
14612 writel(0xffffffff, sram_base + 4);
14613 if (readl(sram_base) != 0x00000000)
14614 tg3_flag_set(tp, PCIX_TARGET_HWBUG);
14619 tg3_nvram_init(tp);
14621 grc_misc_cfg = tr32(GRC_MISC_CFG);
14622 grc_misc_cfg &= GRC_MISC_CFG_BOARD_ID_MASK;
14624 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705 &&
14625 (grc_misc_cfg == GRC_MISC_CFG_BOARD_ID_5788 ||
14626 grc_misc_cfg == GRC_MISC_CFG_BOARD_ID_5788M))
14627 tg3_flag_set(tp, IS_5788);
14629 if (!tg3_flag(tp, IS_5788) &&
14630 GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5700)
14631 tg3_flag_set(tp, TAGGED_STATUS);
14632 if (tg3_flag(tp, TAGGED_STATUS)) {
14633 tp->coalesce_mode |= (HOSTCC_MODE_CLRTICK_RXBD |
14634 HOSTCC_MODE_CLRTICK_TXBD);
14636 tp->misc_host_ctrl |= MISC_HOST_CTRL_TAGGED_STATUS;
14637 pci_write_config_dword(tp->pdev, TG3PCI_MISC_HOST_CTRL,
14638 tp->misc_host_ctrl);
14641 /* Preserve the APE MAC_MODE bits */
14642 if (tg3_flag(tp, ENABLE_APE))
14643 tp->mac_mode = MAC_MODE_APE_TX_EN | MAC_MODE_APE_RX_EN;
14647 /* these are limited to 10/100 only */
14648 if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703 &&
14649 (grc_misc_cfg == 0x8000 || grc_misc_cfg == 0x4000)) ||
14650 (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705 &&
14651 tp->pdev->vendor == PCI_VENDOR_ID_BROADCOM &&
14652 (tp->pdev->device == PCI_DEVICE_ID_TIGON3_5901 ||
14653 tp->pdev->device == PCI_DEVICE_ID_TIGON3_5901_2 ||
14654 tp->pdev->device == PCI_DEVICE_ID_TIGON3_5705F)) ||
14655 (tp->pdev->vendor == PCI_VENDOR_ID_BROADCOM &&
14656 (tp->pdev->device == PCI_DEVICE_ID_TIGON3_5751F ||
14657 tp->pdev->device == PCI_DEVICE_ID_TIGON3_5753F ||
14658 tp->pdev->device == PCI_DEVICE_ID_TIGON3_5787F)) ||
14659 tp->pdev->device == TG3PCI_DEVICE_TIGON3_57790 ||
14660 tp->pdev->device == TG3PCI_DEVICE_TIGON3_57791 ||
14661 tp->pdev->device == TG3PCI_DEVICE_TIGON3_57795 ||
14662 (tp->phy_flags & TG3_PHYFLG_IS_FET))
14663 tp->phy_flags |= TG3_PHYFLG_10_100_ONLY;
14665 err = tg3_phy_probe(tp);
14667 dev_err(&tp->pdev->dev, "phy probe failed, err %d\n", err);
14668 /* ... but do not return immediately ... */
14673 tg3_read_fw_ver(tp);
14675 if (tp->phy_flags & TG3_PHYFLG_PHY_SERDES) {
14676 tp->phy_flags &= ~TG3_PHYFLG_USE_MI_INTERRUPT;
14678 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700)
14679 tp->phy_flags |= TG3_PHYFLG_USE_MI_INTERRUPT;
14681 tp->phy_flags &= ~TG3_PHYFLG_USE_MI_INTERRUPT;
14684 /* 5700 {AX,BX} chips have a broken status block link
14685 * change bit implementation, so we must use the
14686 * status register in those cases.
14688 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700)
14689 tg3_flag_set(tp, USE_LINKCHG_REG);
14691 tg3_flag_clear(tp, USE_LINKCHG_REG);
14693 /* The led_ctrl is set during tg3_phy_probe, here we might
14694 * have to force the link status polling mechanism based
14695 * upon subsystem IDs.
14697 if (tp->pdev->subsystem_vendor == PCI_VENDOR_ID_DELL &&
14698 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701 &&
14699 !(tp->phy_flags & TG3_PHYFLG_PHY_SERDES)) {
14700 tp->phy_flags |= TG3_PHYFLG_USE_MI_INTERRUPT;
14701 tg3_flag_set(tp, USE_LINKCHG_REG);
14704 /* For all SERDES we poll the MAC status register. */
14705 if (tp->phy_flags & TG3_PHYFLG_PHY_SERDES)
14706 tg3_flag_set(tp, POLL_SERDES);
14708 tg3_flag_clear(tp, POLL_SERDES);
14710 tp->rx_offset = NET_SKB_PAD + NET_IP_ALIGN;
14711 tp->rx_copy_thresh = TG3_RX_COPY_THRESHOLD;
14712 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701 &&
14713 tg3_flag(tp, PCIX_MODE)) {
14714 tp->rx_offset = NET_SKB_PAD;
14715 #ifndef CONFIG_HAVE_EFFICIENT_UNALIGNED_ACCESS
14716 tp->rx_copy_thresh = ~(u16)0;
14720 tp->rx_std_ring_mask = TG3_RX_STD_RING_SIZE(tp) - 1;
14721 tp->rx_jmb_ring_mask = TG3_RX_JMB_RING_SIZE(tp) - 1;
14722 tp->rx_ret_ring_mask = tg3_rx_ret_ring_size(tp) - 1;
14724 tp->rx_std_max_post = tp->rx_std_ring_mask + 1;
14726 /* Increment the rx prod index on the rx std ring by at most
14727 * 8 for these chips to workaround hw errata.
14729 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5750 ||
14730 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5752 ||
14731 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5755)
14732 tp->rx_std_max_post = 8;
14734 if (tg3_flag(tp, ASPM_WORKAROUND))
14735 tp->pwrmgmt_thresh = tr32(PCIE_PWR_MGMT_THRESH) &
14736 PCIE_PWR_MGMT_L1_THRESH_MSK;
14741 #ifdef CONFIG_SPARC
14742 static int __devinit tg3_get_macaddr_sparc(struct tg3 *tp)
14744 struct net_device *dev = tp->dev;
14745 struct pci_dev *pdev = tp->pdev;
14746 struct device_node *dp = pci_device_to_OF_node(pdev);
14747 const unsigned char *addr;
14750 addr = of_get_property(dp, "local-mac-address", &len);
14751 if (addr && len == 6) {
14752 memcpy(dev->dev_addr, addr, 6);
14753 memcpy(dev->perm_addr, dev->dev_addr, 6);
14759 static int __devinit tg3_get_default_macaddr_sparc(struct tg3 *tp)
14761 struct net_device *dev = tp->dev;
14763 memcpy(dev->dev_addr, idprom->id_ethaddr, 6);
14764 memcpy(dev->perm_addr, idprom->id_ethaddr, 6);
14769 static int __devinit tg3_get_device_address(struct tg3 *tp)
14771 struct net_device *dev = tp->dev;
14772 u32 hi, lo, mac_offset;
14775 #ifdef CONFIG_SPARC
14776 if (!tg3_get_macaddr_sparc(tp))
14781 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704 ||
14782 tg3_flag(tp, 5780_CLASS)) {
14783 if (tr32(TG3PCI_DUAL_MAC_CTRL) & DUAL_MAC_CTRL_ID)
14785 if (tg3_nvram_lock(tp))
14786 tw32_f(NVRAM_CMD, NVRAM_CMD_RESET);
14788 tg3_nvram_unlock(tp);
14789 } else if (tg3_flag(tp, 5717_PLUS)) {
14790 if (tp->pci_fn & 1)
14792 if (tp->pci_fn > 1)
14793 mac_offset += 0x18c;
14794 } else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906)
14797 /* First try to get it from MAC address mailbox. */
14798 tg3_read_mem(tp, NIC_SRAM_MAC_ADDR_HIGH_MBOX, &hi);
14799 if ((hi >> 16) == 0x484b) {
14800 dev->dev_addr[0] = (hi >> 8) & 0xff;
14801 dev->dev_addr[1] = (hi >> 0) & 0xff;
14803 tg3_read_mem(tp, NIC_SRAM_MAC_ADDR_LOW_MBOX, &lo);
14804 dev->dev_addr[2] = (lo >> 24) & 0xff;
14805 dev->dev_addr[3] = (lo >> 16) & 0xff;
14806 dev->dev_addr[4] = (lo >> 8) & 0xff;
14807 dev->dev_addr[5] = (lo >> 0) & 0xff;
14809 /* Some old bootcode may report a 0 MAC address in SRAM */
14810 addr_ok = is_valid_ether_addr(&dev->dev_addr[0]);
14813 /* Next, try NVRAM. */
14814 if (!tg3_flag(tp, NO_NVRAM) &&
14815 !tg3_nvram_read_be32(tp, mac_offset + 0, &hi) &&
14816 !tg3_nvram_read_be32(tp, mac_offset + 4, &lo)) {
14817 memcpy(&dev->dev_addr[0], ((char *)&hi) + 2, 2);
14818 memcpy(&dev->dev_addr[2], (char *)&lo, sizeof(lo));
14820 /* Finally just fetch it out of the MAC control regs. */
14822 hi = tr32(MAC_ADDR_0_HIGH);
14823 lo = tr32(MAC_ADDR_0_LOW);
14825 dev->dev_addr[5] = lo & 0xff;
14826 dev->dev_addr[4] = (lo >> 8) & 0xff;
14827 dev->dev_addr[3] = (lo >> 16) & 0xff;
14828 dev->dev_addr[2] = (lo >> 24) & 0xff;
14829 dev->dev_addr[1] = hi & 0xff;
14830 dev->dev_addr[0] = (hi >> 8) & 0xff;
14834 if (!is_valid_ether_addr(&dev->dev_addr[0])) {
14835 #ifdef CONFIG_SPARC
14836 if (!tg3_get_default_macaddr_sparc(tp))
14841 memcpy(dev->perm_addr, dev->dev_addr, dev->addr_len);
14845 #define BOUNDARY_SINGLE_CACHELINE 1
14846 #define BOUNDARY_MULTI_CACHELINE 2
14848 static u32 __devinit tg3_calc_dma_bndry(struct tg3 *tp, u32 val)
14850 int cacheline_size;
14854 pci_read_config_byte(tp->pdev, PCI_CACHE_LINE_SIZE, &byte);
14856 cacheline_size = 1024;
14858 cacheline_size = (int) byte * 4;
14860 /* On 5703 and later chips, the boundary bits have no
14863 if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5700 &&
14864 GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5701 &&
14865 !tg3_flag(tp, PCI_EXPRESS))
14868 #if defined(CONFIG_PPC64) || defined(CONFIG_IA64) || defined(CONFIG_PARISC)
14869 goal = BOUNDARY_MULTI_CACHELINE;
14871 #if defined(CONFIG_SPARC64) || defined(CONFIG_ALPHA)
14872 goal = BOUNDARY_SINGLE_CACHELINE;
14878 if (tg3_flag(tp, 57765_PLUS)) {
14879 val = goal ? 0 : DMA_RWCTRL_DIS_CACHE_ALIGNMENT;
14886 /* PCI controllers on most RISC systems tend to disconnect
14887 * when a device tries to burst across a cache-line boundary.
14888 * Therefore, letting tg3 do so just wastes PCI bandwidth.
14890 * Unfortunately, for PCI-E there are only limited
14891 * write-side controls for this, and thus for reads
14892 * we will still get the disconnects. We'll also waste
14893 * these PCI cycles for both read and write for chips
14894 * other than 5700 and 5701 which do not implement the
14897 if (tg3_flag(tp, PCIX_MODE) && !tg3_flag(tp, PCI_EXPRESS)) {
14898 switch (cacheline_size) {
14903 if (goal == BOUNDARY_SINGLE_CACHELINE) {
14904 val |= (DMA_RWCTRL_READ_BNDRY_128_PCIX |
14905 DMA_RWCTRL_WRITE_BNDRY_128_PCIX);
14907 val |= (DMA_RWCTRL_READ_BNDRY_384_PCIX |
14908 DMA_RWCTRL_WRITE_BNDRY_384_PCIX);
14913 val |= (DMA_RWCTRL_READ_BNDRY_256_PCIX |
14914 DMA_RWCTRL_WRITE_BNDRY_256_PCIX);
14918 val |= (DMA_RWCTRL_READ_BNDRY_384_PCIX |
14919 DMA_RWCTRL_WRITE_BNDRY_384_PCIX);
14922 } else if (tg3_flag(tp, PCI_EXPRESS)) {
14923 switch (cacheline_size) {
14927 if (goal == BOUNDARY_SINGLE_CACHELINE) {
14928 val &= ~DMA_RWCTRL_WRITE_BNDRY_DISAB_PCIE;
14929 val |= DMA_RWCTRL_WRITE_BNDRY_64_PCIE;
14935 val &= ~DMA_RWCTRL_WRITE_BNDRY_DISAB_PCIE;
14936 val |= DMA_RWCTRL_WRITE_BNDRY_128_PCIE;
14940 switch (cacheline_size) {
14942 if (goal == BOUNDARY_SINGLE_CACHELINE) {
14943 val |= (DMA_RWCTRL_READ_BNDRY_16 |
14944 DMA_RWCTRL_WRITE_BNDRY_16);
14949 if (goal == BOUNDARY_SINGLE_CACHELINE) {
14950 val |= (DMA_RWCTRL_READ_BNDRY_32 |
14951 DMA_RWCTRL_WRITE_BNDRY_32);
14956 if (goal == BOUNDARY_SINGLE_CACHELINE) {
14957 val |= (DMA_RWCTRL_READ_BNDRY_64 |
14958 DMA_RWCTRL_WRITE_BNDRY_64);
14963 if (goal == BOUNDARY_SINGLE_CACHELINE) {
14964 val |= (DMA_RWCTRL_READ_BNDRY_128 |
14965 DMA_RWCTRL_WRITE_BNDRY_128);
14970 val |= (DMA_RWCTRL_READ_BNDRY_256 |
14971 DMA_RWCTRL_WRITE_BNDRY_256);
14974 val |= (DMA_RWCTRL_READ_BNDRY_512 |
14975 DMA_RWCTRL_WRITE_BNDRY_512);
14979 val |= (DMA_RWCTRL_READ_BNDRY_1024 |
14980 DMA_RWCTRL_WRITE_BNDRY_1024);
14989 static int __devinit tg3_do_test_dma(struct tg3 *tp, u32 *buf, dma_addr_t buf_dma, int size, int to_device)
14991 struct tg3_internal_buffer_desc test_desc;
14992 u32 sram_dma_descs;
14995 sram_dma_descs = NIC_SRAM_DMA_DESC_POOL_BASE;
14997 tw32(FTQ_RCVBD_COMP_FIFO_ENQDEQ, 0);
14998 tw32(FTQ_RCVDATA_COMP_FIFO_ENQDEQ, 0);
14999 tw32(RDMAC_STATUS, 0);
15000 tw32(WDMAC_STATUS, 0);
15002 tw32(BUFMGR_MODE, 0);
15003 tw32(FTQ_RESET, 0);
15005 test_desc.addr_hi = ((u64) buf_dma) >> 32;
15006 test_desc.addr_lo = buf_dma & 0xffffffff;
15007 test_desc.nic_mbuf = 0x00002100;
15008 test_desc.len = size;
15011 * HP ZX1 was seeing test failures for 5701 cards running at 33Mhz
15012 * the *second* time the tg3 driver was getting loaded after an
15015 * Broadcom tells me:
15016 * ...the DMA engine is connected to the GRC block and a DMA
15017 * reset may affect the GRC block in some unpredictable way...
15018 * The behavior of resets to individual blocks has not been tested.
15020 * Broadcom noted the GRC reset will also reset all sub-components.
15023 test_desc.cqid_sqid = (13 << 8) | 2;
15025 tw32_f(RDMAC_MODE, RDMAC_MODE_ENABLE);
15028 test_desc.cqid_sqid = (16 << 8) | 7;
15030 tw32_f(WDMAC_MODE, WDMAC_MODE_ENABLE);
15033 test_desc.flags = 0x00000005;
15035 for (i = 0; i < (sizeof(test_desc) / sizeof(u32)); i++) {
15038 val = *(((u32 *)&test_desc) + i);
15039 pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_BASE_ADDR,
15040 sram_dma_descs + (i * sizeof(u32)));
15041 pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_DATA, val);
15043 pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_BASE_ADDR, 0);
15046 tw32(FTQ_DMA_HIGH_READ_FIFO_ENQDEQ, sram_dma_descs);
15048 tw32(FTQ_DMA_HIGH_WRITE_FIFO_ENQDEQ, sram_dma_descs);
15051 for (i = 0; i < 40; i++) {
15055 val = tr32(FTQ_RCVBD_COMP_FIFO_ENQDEQ);
15057 val = tr32(FTQ_RCVDATA_COMP_FIFO_ENQDEQ);
15058 if ((val & 0xffff) == sram_dma_descs) {
15069 #define TEST_BUFFER_SIZE 0x2000
15071 static DEFINE_PCI_DEVICE_TABLE(tg3_dma_wait_state_chipsets) = {
15072 { PCI_DEVICE(PCI_VENDOR_ID_APPLE, PCI_DEVICE_ID_APPLE_UNI_N_PCI15) },
15076 static int __devinit tg3_test_dma(struct tg3 *tp)
15078 dma_addr_t buf_dma;
15079 u32 *buf, saved_dma_rwctrl;
15082 buf = dma_alloc_coherent(&tp->pdev->dev, TEST_BUFFER_SIZE,
15083 &buf_dma, GFP_KERNEL);
15089 tp->dma_rwctrl = ((0x7 << DMA_RWCTRL_PCI_WRITE_CMD_SHIFT) |
15090 (0x6 << DMA_RWCTRL_PCI_READ_CMD_SHIFT));
15092 tp->dma_rwctrl = tg3_calc_dma_bndry(tp, tp->dma_rwctrl);
15094 if (tg3_flag(tp, 57765_PLUS))
15097 if (tg3_flag(tp, PCI_EXPRESS)) {
15098 /* DMA read watermark not used on PCIE */
15099 tp->dma_rwctrl |= 0x00180000;
15100 } else if (!tg3_flag(tp, PCIX_MODE)) {
15101 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705 ||
15102 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5750)
15103 tp->dma_rwctrl |= 0x003f0000;
15105 tp->dma_rwctrl |= 0x003f000f;
15107 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703 ||
15108 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704) {
15109 u32 ccval = (tr32(TG3PCI_CLOCK_CTRL) & 0x1f);
15110 u32 read_water = 0x7;
15112 /* If the 5704 is behind the EPB bridge, we can
15113 * do the less restrictive ONE_DMA workaround for
15114 * better performance.
15116 if (tg3_flag(tp, 40BIT_DMA_BUG) &&
15117 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704)
15118 tp->dma_rwctrl |= 0x8000;
15119 else if (ccval == 0x6 || ccval == 0x7)
15120 tp->dma_rwctrl |= DMA_RWCTRL_ONE_DMA;
15122 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703)
15124 /* Set bit 23 to enable PCIX hw bug fix */
15126 (read_water << DMA_RWCTRL_READ_WATER_SHIFT) |
15127 (0x3 << DMA_RWCTRL_WRITE_WATER_SHIFT) |
15129 } else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5780) {
15130 /* 5780 always in PCIX mode */
15131 tp->dma_rwctrl |= 0x00144000;
15132 } else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5714) {
15133 /* 5714 always in PCIX mode */
15134 tp->dma_rwctrl |= 0x00148000;
15136 tp->dma_rwctrl |= 0x001b000f;
15140 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703 ||
15141 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704)
15142 tp->dma_rwctrl &= 0xfffffff0;
15144 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
15145 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701) {
15146 /* Remove this if it causes problems for some boards. */
15147 tp->dma_rwctrl |= DMA_RWCTRL_USE_MEM_READ_MULT;
15149 /* On 5700/5701 chips, we need to set this bit.
15150 * Otherwise the chip will issue cacheline transactions
15151 * to streamable DMA memory with not all the byte
15152 * enables turned on. This is an error on several
15153 * RISC PCI controllers, in particular sparc64.
15155 * On 5703/5704 chips, this bit has been reassigned
15156 * a different meaning. In particular, it is used
15157 * on those chips to enable a PCI-X workaround.
15159 tp->dma_rwctrl |= DMA_RWCTRL_ASSERT_ALL_BE;
15162 tw32(TG3PCI_DMA_RW_CTRL, tp->dma_rwctrl);
15165 /* Unneeded, already done by tg3_get_invariants. */
15166 tg3_switch_clocks(tp);
15169 if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5700 &&
15170 GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5701)
15173 /* It is best to perform DMA test with maximum write burst size
15174 * to expose the 5700/5701 write DMA bug.
15176 saved_dma_rwctrl = tp->dma_rwctrl;
15177 tp->dma_rwctrl &= ~DMA_RWCTRL_WRITE_BNDRY_MASK;
15178 tw32(TG3PCI_DMA_RW_CTRL, tp->dma_rwctrl);
15183 for (i = 0; i < TEST_BUFFER_SIZE / sizeof(u32); i++)
15186 /* Send the buffer to the chip. */
15187 ret = tg3_do_test_dma(tp, buf, buf_dma, TEST_BUFFER_SIZE, 1);
15189 dev_err(&tp->pdev->dev,
15190 "%s: Buffer write failed. err = %d\n",
15196 /* validate data reached card RAM correctly. */
15197 for (i = 0; i < TEST_BUFFER_SIZE / sizeof(u32); i++) {
15199 tg3_read_mem(tp, 0x2100 + (i*4), &val);
15200 if (le32_to_cpu(val) != p[i]) {
15201 dev_err(&tp->pdev->dev,
15202 "%s: Buffer corrupted on device! "
15203 "(%d != %d)\n", __func__, val, i);
15204 /* ret = -ENODEV here? */
15209 /* Now read it back. */
15210 ret = tg3_do_test_dma(tp, buf, buf_dma, TEST_BUFFER_SIZE, 0);
15212 dev_err(&tp->pdev->dev, "%s: Buffer read failed. "
15213 "err = %d\n", __func__, ret);
15218 for (i = 0; i < TEST_BUFFER_SIZE / sizeof(u32); i++) {
15222 if ((tp->dma_rwctrl & DMA_RWCTRL_WRITE_BNDRY_MASK) !=
15223 DMA_RWCTRL_WRITE_BNDRY_16) {
15224 tp->dma_rwctrl &= ~DMA_RWCTRL_WRITE_BNDRY_MASK;
15225 tp->dma_rwctrl |= DMA_RWCTRL_WRITE_BNDRY_16;
15226 tw32(TG3PCI_DMA_RW_CTRL, tp->dma_rwctrl);
15229 dev_err(&tp->pdev->dev,
15230 "%s: Buffer corrupted on read back! "
15231 "(%d != %d)\n", __func__, p[i], i);
15237 if (i == (TEST_BUFFER_SIZE / sizeof(u32))) {
15243 if ((tp->dma_rwctrl & DMA_RWCTRL_WRITE_BNDRY_MASK) !=
15244 DMA_RWCTRL_WRITE_BNDRY_16) {
15245 /* DMA test passed without adjusting DMA boundary,
15246 * now look for chipsets that are known to expose the
15247 * DMA bug without failing the test.
15249 if (pci_dev_present(tg3_dma_wait_state_chipsets)) {
15250 tp->dma_rwctrl &= ~DMA_RWCTRL_WRITE_BNDRY_MASK;
15251 tp->dma_rwctrl |= DMA_RWCTRL_WRITE_BNDRY_16;
15253 /* Safe to use the calculated DMA boundary. */
15254 tp->dma_rwctrl = saved_dma_rwctrl;
15257 tw32(TG3PCI_DMA_RW_CTRL, tp->dma_rwctrl);
15261 dma_free_coherent(&tp->pdev->dev, TEST_BUFFER_SIZE, buf, buf_dma);
15266 static void __devinit tg3_init_bufmgr_config(struct tg3 *tp)
15268 if (tg3_flag(tp, 57765_PLUS)) {
15269 tp->bufmgr_config.mbuf_read_dma_low_water =
15270 DEFAULT_MB_RDMA_LOW_WATER_5705;
15271 tp->bufmgr_config.mbuf_mac_rx_low_water =
15272 DEFAULT_MB_MACRX_LOW_WATER_57765;
15273 tp->bufmgr_config.mbuf_high_water =
15274 DEFAULT_MB_HIGH_WATER_57765;
15276 tp->bufmgr_config.mbuf_read_dma_low_water_jumbo =
15277 DEFAULT_MB_RDMA_LOW_WATER_5705;
15278 tp->bufmgr_config.mbuf_mac_rx_low_water_jumbo =
15279 DEFAULT_MB_MACRX_LOW_WATER_JUMBO_57765;
15280 tp->bufmgr_config.mbuf_high_water_jumbo =
15281 DEFAULT_MB_HIGH_WATER_JUMBO_57765;
15282 } else if (tg3_flag(tp, 5705_PLUS)) {
15283 tp->bufmgr_config.mbuf_read_dma_low_water =
15284 DEFAULT_MB_RDMA_LOW_WATER_5705;
15285 tp->bufmgr_config.mbuf_mac_rx_low_water =
15286 DEFAULT_MB_MACRX_LOW_WATER_5705;
15287 tp->bufmgr_config.mbuf_high_water =
15288 DEFAULT_MB_HIGH_WATER_5705;
15289 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
15290 tp->bufmgr_config.mbuf_mac_rx_low_water =
15291 DEFAULT_MB_MACRX_LOW_WATER_5906;
15292 tp->bufmgr_config.mbuf_high_water =
15293 DEFAULT_MB_HIGH_WATER_5906;
15296 tp->bufmgr_config.mbuf_read_dma_low_water_jumbo =
15297 DEFAULT_MB_RDMA_LOW_WATER_JUMBO_5780;
15298 tp->bufmgr_config.mbuf_mac_rx_low_water_jumbo =
15299 DEFAULT_MB_MACRX_LOW_WATER_JUMBO_5780;
15300 tp->bufmgr_config.mbuf_high_water_jumbo =
15301 DEFAULT_MB_HIGH_WATER_JUMBO_5780;
15303 tp->bufmgr_config.mbuf_read_dma_low_water =
15304 DEFAULT_MB_RDMA_LOW_WATER;
15305 tp->bufmgr_config.mbuf_mac_rx_low_water =
15306 DEFAULT_MB_MACRX_LOW_WATER;
15307 tp->bufmgr_config.mbuf_high_water =
15308 DEFAULT_MB_HIGH_WATER;
15310 tp->bufmgr_config.mbuf_read_dma_low_water_jumbo =
15311 DEFAULT_MB_RDMA_LOW_WATER_JUMBO;
15312 tp->bufmgr_config.mbuf_mac_rx_low_water_jumbo =
15313 DEFAULT_MB_MACRX_LOW_WATER_JUMBO;
15314 tp->bufmgr_config.mbuf_high_water_jumbo =
15315 DEFAULT_MB_HIGH_WATER_JUMBO;
15318 tp->bufmgr_config.dma_low_water = DEFAULT_DMA_LOW_WATER;
15319 tp->bufmgr_config.dma_high_water = DEFAULT_DMA_HIGH_WATER;
15322 static char * __devinit tg3_phy_string(struct tg3 *tp)
15324 switch (tp->phy_id & TG3_PHY_ID_MASK) {
15325 case TG3_PHY_ID_BCM5400: return "5400";
15326 case TG3_PHY_ID_BCM5401: return "5401";
15327 case TG3_PHY_ID_BCM5411: return "5411";
15328 case TG3_PHY_ID_BCM5701: return "5701";
15329 case TG3_PHY_ID_BCM5703: return "5703";
15330 case TG3_PHY_ID_BCM5704: return "5704";
15331 case TG3_PHY_ID_BCM5705: return "5705";
15332 case TG3_PHY_ID_BCM5750: return "5750";
15333 case TG3_PHY_ID_BCM5752: return "5752";
15334 case TG3_PHY_ID_BCM5714: return "5714";
15335 case TG3_PHY_ID_BCM5780: return "5780";
15336 case TG3_PHY_ID_BCM5755: return "5755";
15337 case TG3_PHY_ID_BCM5787: return "5787";
15338 case TG3_PHY_ID_BCM5784: return "5784";
15339 case TG3_PHY_ID_BCM5756: return "5722/5756";
15340 case TG3_PHY_ID_BCM5906: return "5906";
15341 case TG3_PHY_ID_BCM5761: return "5761";
15342 case TG3_PHY_ID_BCM5718C: return "5718C";
15343 case TG3_PHY_ID_BCM5718S: return "5718S";
15344 case TG3_PHY_ID_BCM57765: return "57765";
15345 case TG3_PHY_ID_BCM5719C: return "5719C";
15346 case TG3_PHY_ID_BCM5720C: return "5720C";
15347 case TG3_PHY_ID_BCM8002: return "8002/serdes";
15348 case 0: return "serdes";
15349 default: return "unknown";
15353 static char * __devinit tg3_bus_string(struct tg3 *tp, char *str)
15355 if (tg3_flag(tp, PCI_EXPRESS)) {
15356 strcpy(str, "PCI Express");
15358 } else if (tg3_flag(tp, PCIX_MODE)) {
15359 u32 clock_ctrl = tr32(TG3PCI_CLOCK_CTRL) & 0x1f;
15361 strcpy(str, "PCIX:");
15363 if ((clock_ctrl == 7) ||
15364 ((tr32(GRC_MISC_CFG) & GRC_MISC_CFG_BOARD_ID_MASK) ==
15365 GRC_MISC_CFG_BOARD_ID_5704CIOBE))
15366 strcat(str, "133MHz");
15367 else if (clock_ctrl == 0)
15368 strcat(str, "33MHz");
15369 else if (clock_ctrl == 2)
15370 strcat(str, "50MHz");
15371 else if (clock_ctrl == 4)
15372 strcat(str, "66MHz");
15373 else if (clock_ctrl == 6)
15374 strcat(str, "100MHz");
15376 strcpy(str, "PCI:");
15377 if (tg3_flag(tp, PCI_HIGH_SPEED))
15378 strcat(str, "66MHz");
15380 strcat(str, "33MHz");
15382 if (tg3_flag(tp, PCI_32BIT))
15383 strcat(str, ":32-bit");
15385 strcat(str, ":64-bit");
15389 static void __devinit tg3_init_coal(struct tg3 *tp)
15391 struct ethtool_coalesce *ec = &tp->coal;
15393 memset(ec, 0, sizeof(*ec));
15394 ec->cmd = ETHTOOL_GCOALESCE;
15395 ec->rx_coalesce_usecs = LOW_RXCOL_TICKS;
15396 ec->tx_coalesce_usecs = LOW_TXCOL_TICKS;
15397 ec->rx_max_coalesced_frames = LOW_RXMAX_FRAMES;
15398 ec->tx_max_coalesced_frames = LOW_TXMAX_FRAMES;
15399 ec->rx_coalesce_usecs_irq = DEFAULT_RXCOAL_TICK_INT;
15400 ec->tx_coalesce_usecs_irq = DEFAULT_TXCOAL_TICK_INT;
15401 ec->rx_max_coalesced_frames_irq = DEFAULT_RXCOAL_MAXF_INT;
15402 ec->tx_max_coalesced_frames_irq = DEFAULT_TXCOAL_MAXF_INT;
15403 ec->stats_block_coalesce_usecs = DEFAULT_STAT_COAL_TICKS;
15405 if (tp->coalesce_mode & (HOSTCC_MODE_CLRTICK_RXBD |
15406 HOSTCC_MODE_CLRTICK_TXBD)) {
15407 ec->rx_coalesce_usecs = LOW_RXCOL_TICKS_CLRTCKS;
15408 ec->rx_coalesce_usecs_irq = DEFAULT_RXCOAL_TICK_INT_CLRTCKS;
15409 ec->tx_coalesce_usecs = LOW_TXCOL_TICKS_CLRTCKS;
15410 ec->tx_coalesce_usecs_irq = DEFAULT_TXCOAL_TICK_INT_CLRTCKS;
15413 if (tg3_flag(tp, 5705_PLUS)) {
15414 ec->rx_coalesce_usecs_irq = 0;
15415 ec->tx_coalesce_usecs_irq = 0;
15416 ec->stats_block_coalesce_usecs = 0;
15420 static int __devinit tg3_init_one(struct pci_dev *pdev,
15421 const struct pci_device_id *ent)
15423 struct net_device *dev;
15425 int i, err, pm_cap;
15426 u32 sndmbx, rcvmbx, intmbx;
15428 u64 dma_mask, persist_dma_mask;
15429 netdev_features_t features = 0;
15431 printk_once(KERN_INFO "%s\n", version);
15433 err = pci_enable_device(pdev);
15435 dev_err(&pdev->dev, "Cannot enable PCI device, aborting\n");
15439 err = pci_request_regions(pdev, DRV_MODULE_NAME);
15441 dev_err(&pdev->dev, "Cannot obtain PCI resources, aborting\n");
15442 goto err_out_disable_pdev;
15445 pci_set_master(pdev);
15447 /* Find power-management capability. */
15448 pm_cap = pci_find_capability(pdev, PCI_CAP_ID_PM);
15450 dev_err(&pdev->dev,
15451 "Cannot find Power Management capability, aborting\n");
15453 goto err_out_free_res;
15456 err = pci_set_power_state(pdev, PCI_D0);
15458 dev_err(&pdev->dev, "Transition to D0 failed, aborting\n");
15459 goto err_out_free_res;
15462 dev = alloc_etherdev_mq(sizeof(*tp), TG3_IRQ_MAX_VECS);
15465 goto err_out_power_down;
15468 SET_NETDEV_DEV(dev, &pdev->dev);
15470 tp = netdev_priv(dev);
15473 tp->pm_cap = pm_cap;
15474 tp->rx_mode = TG3_DEF_RX_MODE;
15475 tp->tx_mode = TG3_DEF_TX_MODE;
15478 tp->msg_enable = tg3_debug;
15480 tp->msg_enable = TG3_DEF_MSG_ENABLE;
15482 /* The word/byte swap controls here control register access byte
15483 * swapping. DMA data byte swapping is controlled in the GRC_MODE
15486 tp->misc_host_ctrl =
15487 MISC_HOST_CTRL_MASK_PCI_INT |
15488 MISC_HOST_CTRL_WORD_SWAP |
15489 MISC_HOST_CTRL_INDIR_ACCESS |
15490 MISC_HOST_CTRL_PCISTATE_RW;
15492 /* The NONFRM (non-frame) byte/word swap controls take effect
15493 * on descriptor entries, anything which isn't packet data.
15495 * The StrongARM chips on the board (one for tx, one for rx)
15496 * are running in big-endian mode.
15498 tp->grc_mode = (GRC_MODE_WSWAP_DATA | GRC_MODE_BSWAP_DATA |
15499 GRC_MODE_WSWAP_NONFRM_DATA);
15500 #ifdef __BIG_ENDIAN
15501 tp->grc_mode |= GRC_MODE_BSWAP_NONFRM_DATA;
15503 spin_lock_init(&tp->lock);
15504 spin_lock_init(&tp->indirect_lock);
15505 INIT_WORK(&tp->reset_task, tg3_reset_task);
15507 tp->regs = pci_ioremap_bar(pdev, BAR_0);
15509 dev_err(&pdev->dev, "Cannot map device registers, aborting\n");
15511 goto err_out_free_dev;
15514 if (tp->pdev->device == PCI_DEVICE_ID_TIGON3_5761 ||
15515 tp->pdev->device == PCI_DEVICE_ID_TIGON3_5761E ||
15516 tp->pdev->device == TG3PCI_DEVICE_TIGON3_5761S ||
15517 tp->pdev->device == TG3PCI_DEVICE_TIGON3_5761SE ||
15518 tp->pdev->device == TG3PCI_DEVICE_TIGON3_5717 ||
15519 tp->pdev->device == TG3PCI_DEVICE_TIGON3_5718 ||
15520 tp->pdev->device == TG3PCI_DEVICE_TIGON3_5719 ||
15521 tp->pdev->device == TG3PCI_DEVICE_TIGON3_5720) {
15522 tg3_flag_set(tp, ENABLE_APE);
15523 tp->aperegs = pci_ioremap_bar(pdev, BAR_2);
15524 if (!tp->aperegs) {
15525 dev_err(&pdev->dev,
15526 "Cannot map APE registers, aborting\n");
15528 goto err_out_iounmap;
15532 tp->rx_pending = TG3_DEF_RX_RING_PENDING;
15533 tp->rx_jumbo_pending = TG3_DEF_RX_JUMBO_RING_PENDING;
15535 dev->ethtool_ops = &tg3_ethtool_ops;
15536 dev->watchdog_timeo = TG3_TX_TIMEOUT;
15537 dev->netdev_ops = &tg3_netdev_ops;
15538 dev->irq = pdev->irq;
15540 err = tg3_get_invariants(tp);
15542 dev_err(&pdev->dev,
15543 "Problem fetching invariants of chip, aborting\n");
15544 goto err_out_apeunmap;
15547 /* The EPB bridge inside 5714, 5715, and 5780 and any
15548 * device behind the EPB cannot support DMA addresses > 40-bit.
15549 * On 64-bit systems with IOMMU, use 40-bit dma_mask.
15550 * On 64-bit systems without IOMMU, use 64-bit dma_mask and
15551 * do DMA address check in tg3_start_xmit().
15553 if (tg3_flag(tp, IS_5788))
15554 persist_dma_mask = dma_mask = DMA_BIT_MASK(32);
15555 else if (tg3_flag(tp, 40BIT_DMA_BUG)) {
15556 persist_dma_mask = dma_mask = DMA_BIT_MASK(40);
15557 #ifdef CONFIG_HIGHMEM
15558 dma_mask = DMA_BIT_MASK(64);
15561 persist_dma_mask = dma_mask = DMA_BIT_MASK(64);
15563 /* Configure DMA attributes. */
15564 if (dma_mask > DMA_BIT_MASK(32)) {
15565 err = pci_set_dma_mask(pdev, dma_mask);
15567 features |= NETIF_F_HIGHDMA;
15568 err = pci_set_consistent_dma_mask(pdev,
15571 dev_err(&pdev->dev, "Unable to obtain 64 bit "
15572 "DMA for consistent allocations\n");
15573 goto err_out_apeunmap;
15577 if (err || dma_mask == DMA_BIT_MASK(32)) {
15578 err = pci_set_dma_mask(pdev, DMA_BIT_MASK(32));
15580 dev_err(&pdev->dev,
15581 "No usable DMA configuration, aborting\n");
15582 goto err_out_apeunmap;
15586 tg3_init_bufmgr_config(tp);
15588 features |= NETIF_F_HW_VLAN_TX | NETIF_F_HW_VLAN_RX;
15590 /* 5700 B0 chips do not support checksumming correctly due
15591 * to hardware bugs.
15593 if (tp->pci_chip_rev_id != CHIPREV_ID_5700_B0) {
15594 features |= NETIF_F_SG | NETIF_F_IP_CSUM | NETIF_F_RXCSUM;
15596 if (tg3_flag(tp, 5755_PLUS))
15597 features |= NETIF_F_IPV6_CSUM;
15600 /* TSO is on by default on chips that support hardware TSO.
15601 * Firmware TSO on older chips gives lower performance, so it
15602 * is off by default, but can be enabled using ethtool.
15604 if ((tg3_flag(tp, HW_TSO_1) ||
15605 tg3_flag(tp, HW_TSO_2) ||
15606 tg3_flag(tp, HW_TSO_3)) &&
15607 (features & NETIF_F_IP_CSUM))
15608 features |= NETIF_F_TSO;
15609 if (tg3_flag(tp, HW_TSO_2) || tg3_flag(tp, HW_TSO_3)) {
15610 if (features & NETIF_F_IPV6_CSUM)
15611 features |= NETIF_F_TSO6;
15612 if (tg3_flag(tp, HW_TSO_3) ||
15613 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5761 ||
15614 (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5784 &&
15615 GET_CHIP_REV(tp->pci_chip_rev_id) != CHIPREV_5784_AX) ||
15616 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785 ||
15617 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57780)
15618 features |= NETIF_F_TSO_ECN;
15621 dev->features |= features;
15622 dev->vlan_features |= features;
15625 * Add loopback capability only for a subset of devices that support
15626 * MAC-LOOPBACK. Eventually this need to be enhanced to allow INT-PHY
15627 * loopback for the remaining devices.
15629 if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5780 &&
15630 !tg3_flag(tp, CPMU_PRESENT))
15631 /* Add the loopback capability */
15632 features |= NETIF_F_LOOPBACK;
15634 dev->hw_features |= features;
15636 if (tp->pci_chip_rev_id == CHIPREV_ID_5705_A1 &&
15637 !tg3_flag(tp, TSO_CAPABLE) &&
15638 !(tr32(TG3PCI_PCISTATE) & PCISTATE_BUS_SPEED_HIGH)) {
15639 tg3_flag_set(tp, MAX_RXPEND_64);
15640 tp->rx_pending = 63;
15643 err = tg3_get_device_address(tp);
15645 dev_err(&pdev->dev,
15646 "Could not obtain valid ethernet address, aborting\n");
15647 goto err_out_apeunmap;
15651 * Reset chip in case UNDI or EFI driver did not shutdown
15652 * DMA self test will enable WDMAC and we'll see (spurious)
15653 * pending DMA on the PCI bus at that point.
15655 if ((tr32(HOSTCC_MODE) & HOSTCC_MODE_ENABLE) ||
15656 (tr32(WDMAC_MODE) & WDMAC_MODE_ENABLE)) {
15657 tw32(MEMARB_MODE, MEMARB_MODE_ENABLE);
15658 tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
15661 err = tg3_test_dma(tp);
15663 dev_err(&pdev->dev, "DMA engine test failed, aborting\n");
15664 goto err_out_apeunmap;
15667 intmbx = MAILBOX_INTERRUPT_0 + TG3_64BIT_REG_LOW;
15668 rcvmbx = MAILBOX_RCVRET_CON_IDX_0 + TG3_64BIT_REG_LOW;
15669 sndmbx = MAILBOX_SNDHOST_PROD_IDX_0 + TG3_64BIT_REG_LOW;
15670 for (i = 0; i < tp->irq_max; i++) {
15671 struct tg3_napi *tnapi = &tp->napi[i];
15674 tnapi->tx_pending = TG3_DEF_TX_RING_PENDING;
15676 tnapi->int_mbox = intmbx;
15682 tnapi->consmbox = rcvmbx;
15683 tnapi->prodmbox = sndmbx;
15686 tnapi->coal_now = HOSTCC_MODE_COAL_VEC1_NOW << (i - 1);
15688 tnapi->coal_now = HOSTCC_MODE_NOW;
15690 if (!tg3_flag(tp, SUPPORT_MSIX))
15694 * If we support MSIX, we'll be using RSS. If we're using
15695 * RSS, the first vector only handles link interrupts and the
15696 * remaining vectors handle rx and tx interrupts. Reuse the
15697 * mailbox values for the next iteration. The values we setup
15698 * above are still useful for the single vectored mode.
15713 pci_set_drvdata(pdev, dev);
15715 if (tg3_flag(tp, 5717_PLUS)) {
15716 /* Resume a low-power mode */
15717 tg3_frob_aux_power(tp, false);
15720 err = register_netdev(dev);
15722 dev_err(&pdev->dev, "Cannot register net device, aborting\n");
15723 goto err_out_apeunmap;
15726 netdev_info(dev, "Tigon3 [partno(%s) rev %04x] (%s) MAC address %pM\n",
15727 tp->board_part_number,
15728 tp->pci_chip_rev_id,
15729 tg3_bus_string(tp, str),
15732 if (tp->phy_flags & TG3_PHYFLG_IS_CONNECTED) {
15733 struct phy_device *phydev;
15734 phydev = tp->mdio_bus->phy_map[TG3_PHY_MII_ADDR];
15736 "attached PHY driver [%s] (mii_bus:phy_addr=%s)\n",
15737 phydev->drv->name, dev_name(&phydev->dev));
15741 if (tp->phy_flags & TG3_PHYFLG_10_100_ONLY)
15742 ethtype = "10/100Base-TX";
15743 else if (tp->phy_flags & TG3_PHYFLG_ANY_SERDES)
15744 ethtype = "1000Base-SX";
15746 ethtype = "10/100/1000Base-T";
15748 netdev_info(dev, "attached PHY is %s (%s Ethernet) "
15749 "(WireSpeed[%d], EEE[%d])\n",
15750 tg3_phy_string(tp), ethtype,
15751 (tp->phy_flags & TG3_PHYFLG_NO_ETH_WIRE_SPEED) == 0,
15752 (tp->phy_flags & TG3_PHYFLG_EEE_CAP) != 0);
15755 netdev_info(dev, "RXcsums[%d] LinkChgREG[%d] MIirq[%d] ASF[%d] TSOcap[%d]\n",
15756 (dev->features & NETIF_F_RXCSUM) != 0,
15757 tg3_flag(tp, USE_LINKCHG_REG) != 0,
15758 (tp->phy_flags & TG3_PHYFLG_USE_MI_INTERRUPT) != 0,
15759 tg3_flag(tp, ENABLE_ASF) != 0,
15760 tg3_flag(tp, TSO_CAPABLE) != 0);
15761 netdev_info(dev, "dma_rwctrl[%08x] dma_mask[%d-bit]\n",
15763 pdev->dma_mask == DMA_BIT_MASK(32) ? 32 :
15764 ((u64)pdev->dma_mask) == DMA_BIT_MASK(40) ? 40 : 64);
15766 pci_save_state(pdev);
15772 iounmap(tp->aperegs);
15773 tp->aperegs = NULL;
15785 err_out_power_down:
15786 pci_set_power_state(pdev, PCI_D3hot);
15789 pci_release_regions(pdev);
15791 err_out_disable_pdev:
15792 pci_disable_device(pdev);
15793 pci_set_drvdata(pdev, NULL);
15797 static void __devexit tg3_remove_one(struct pci_dev *pdev)
15799 struct net_device *dev = pci_get_drvdata(pdev);
15802 struct tg3 *tp = netdev_priv(dev);
15805 release_firmware(tp->fw);
15807 tg3_reset_task_cancel(tp);
15809 if (tg3_flag(tp, USE_PHYLIB)) {
15814 unregister_netdev(dev);
15816 iounmap(tp->aperegs);
15817 tp->aperegs = NULL;
15824 pci_release_regions(pdev);
15825 pci_disable_device(pdev);
15826 pci_set_drvdata(pdev, NULL);
15830 #ifdef CONFIG_PM_SLEEP
15831 static int tg3_suspend(struct device *device)
15833 struct pci_dev *pdev = to_pci_dev(device);
15834 struct net_device *dev = pci_get_drvdata(pdev);
15835 struct tg3 *tp = netdev_priv(dev);
15838 if (!netif_running(dev))
15841 tg3_reset_task_cancel(tp);
15843 tg3_netif_stop(tp);
15845 del_timer_sync(&tp->timer);
15847 tg3_full_lock(tp, 1);
15848 tg3_disable_ints(tp);
15849 tg3_full_unlock(tp);
15851 netif_device_detach(dev);
15853 tg3_full_lock(tp, 0);
15854 tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
15855 tg3_flag_clear(tp, INIT_COMPLETE);
15856 tg3_full_unlock(tp);
15858 err = tg3_power_down_prepare(tp);
15862 tg3_full_lock(tp, 0);
15864 tg3_flag_set(tp, INIT_COMPLETE);
15865 err2 = tg3_restart_hw(tp, 1);
15869 tp->timer.expires = jiffies + tp->timer_offset;
15870 add_timer(&tp->timer);
15872 netif_device_attach(dev);
15873 tg3_netif_start(tp);
15876 tg3_full_unlock(tp);
15885 static int tg3_resume(struct device *device)
15887 struct pci_dev *pdev = to_pci_dev(device);
15888 struct net_device *dev = pci_get_drvdata(pdev);
15889 struct tg3 *tp = netdev_priv(dev);
15892 if (!netif_running(dev))
15895 netif_device_attach(dev);
15897 tg3_full_lock(tp, 0);
15899 tg3_flag_set(tp, INIT_COMPLETE);
15900 err = tg3_restart_hw(tp, 1);
15904 tp->timer.expires = jiffies + tp->timer_offset;
15905 add_timer(&tp->timer);
15907 tg3_netif_start(tp);
15910 tg3_full_unlock(tp);
15918 static SIMPLE_DEV_PM_OPS(tg3_pm_ops, tg3_suspend, tg3_resume);
15919 #define TG3_PM_OPS (&tg3_pm_ops)
15923 #define TG3_PM_OPS NULL
15925 #endif /* CONFIG_PM_SLEEP */
15928 * tg3_io_error_detected - called when PCI error is detected
15929 * @pdev: Pointer to PCI device
15930 * @state: The current pci connection state
15932 * This function is called after a PCI bus error affecting
15933 * this device has been detected.
15935 static pci_ers_result_t tg3_io_error_detected(struct pci_dev *pdev,
15936 pci_channel_state_t state)
15938 struct net_device *netdev = pci_get_drvdata(pdev);
15939 struct tg3 *tp = netdev_priv(netdev);
15940 pci_ers_result_t err = PCI_ERS_RESULT_NEED_RESET;
15942 netdev_info(netdev, "PCI I/O error detected\n");
15946 if (!netif_running(netdev))
15951 tg3_netif_stop(tp);
15953 del_timer_sync(&tp->timer);
15955 /* Want to make sure that the reset task doesn't run */
15956 tg3_reset_task_cancel(tp);
15957 tg3_flag_clear(tp, TX_RECOVERY_PENDING);
15959 netif_device_detach(netdev);
15961 /* Clean up software state, even if MMIO is blocked */
15962 tg3_full_lock(tp, 0);
15963 tg3_halt(tp, RESET_KIND_SHUTDOWN, 0);
15964 tg3_full_unlock(tp);
15967 if (state == pci_channel_io_perm_failure)
15968 err = PCI_ERS_RESULT_DISCONNECT;
15970 pci_disable_device(pdev);
15978 * tg3_io_slot_reset - called after the pci bus has been reset.
15979 * @pdev: Pointer to PCI device
15981 * Restart the card from scratch, as if from a cold-boot.
15982 * At this point, the card has exprienced a hard reset,
15983 * followed by fixups by BIOS, and has its config space
15984 * set up identically to what it was at cold boot.
15986 static pci_ers_result_t tg3_io_slot_reset(struct pci_dev *pdev)
15988 struct net_device *netdev = pci_get_drvdata(pdev);
15989 struct tg3 *tp = netdev_priv(netdev);
15990 pci_ers_result_t rc = PCI_ERS_RESULT_DISCONNECT;
15995 if (pci_enable_device(pdev)) {
15996 netdev_err(netdev, "Cannot re-enable PCI device after reset.\n");
16000 pci_set_master(pdev);
16001 pci_restore_state(pdev);
16002 pci_save_state(pdev);
16004 if (!netif_running(netdev)) {
16005 rc = PCI_ERS_RESULT_RECOVERED;
16009 err = tg3_power_up(tp);
16013 rc = PCI_ERS_RESULT_RECOVERED;
16022 * tg3_io_resume - called when traffic can start flowing again.
16023 * @pdev: Pointer to PCI device
16025 * This callback is called when the error recovery driver tells
16026 * us that its OK to resume normal operation.
16028 static void tg3_io_resume(struct pci_dev *pdev)
16030 struct net_device *netdev = pci_get_drvdata(pdev);
16031 struct tg3 *tp = netdev_priv(netdev);
16036 if (!netif_running(netdev))
16039 tg3_full_lock(tp, 0);
16040 tg3_flag_set(tp, INIT_COMPLETE);
16041 err = tg3_restart_hw(tp, 1);
16042 tg3_full_unlock(tp);
16044 netdev_err(netdev, "Cannot restart hardware after reset.\n");
16048 netif_device_attach(netdev);
16050 tp->timer.expires = jiffies + tp->timer_offset;
16051 add_timer(&tp->timer);
16053 tg3_netif_start(tp);
16061 static struct pci_error_handlers tg3_err_handler = {
16062 .error_detected = tg3_io_error_detected,
16063 .slot_reset = tg3_io_slot_reset,
16064 .resume = tg3_io_resume
16067 static struct pci_driver tg3_driver = {
16068 .name = DRV_MODULE_NAME,
16069 .id_table = tg3_pci_tbl,
16070 .probe = tg3_init_one,
16071 .remove = __devexit_p(tg3_remove_one),
16072 .err_handler = &tg3_err_handler,
16073 .driver.pm = TG3_PM_OPS,
16076 static int __init tg3_init(void)
16078 return pci_register_driver(&tg3_driver);
16081 static void __exit tg3_cleanup(void)
16083 pci_unregister_driver(&tg3_driver);
16086 module_init(tg3_init);
16087 module_exit(tg3_cleanup);