2 * tg3.c: Broadcom Tigon3 ethernet driver.
4 * Copyright (C) 2001, 2002, 2003, 2004 David S. Miller (davem@redhat.com)
5 * Copyright (C) 2001, 2002, 2003 Jeff Garzik (jgarzik@pobox.com)
6 * Copyright (C) 2004 Sun Microsystems Inc.
7 * Copyright (C) 2005-2012 Broadcom Corporation.
10 * Derived from proprietary unpublished source code,
11 * Copyright (C) 2000-2003 Broadcom Corporation.
13 * Permission is hereby granted for the distribution of this firmware
14 * data in hexadecimal or equivalent format, provided this copyright
15 * notice is accompanying it.
19 #include <linux/module.h>
20 #include <linux/moduleparam.h>
21 #include <linux/stringify.h>
22 #include <linux/kernel.h>
23 #include <linux/types.h>
24 #include <linux/compiler.h>
25 #include <linux/slab.h>
26 #include <linux/delay.h>
28 #include <linux/init.h>
29 #include <linux/interrupt.h>
30 #include <linux/ioport.h>
31 #include <linux/pci.h>
32 #include <linux/netdevice.h>
33 #include <linux/etherdevice.h>
34 #include <linux/skbuff.h>
35 #include <linux/ethtool.h>
36 #include <linux/mdio.h>
37 #include <linux/mii.h>
38 #include <linux/phy.h>
39 #include <linux/brcmphy.h>
40 #include <linux/if_vlan.h>
42 #include <linux/tcp.h>
43 #include <linux/workqueue.h>
44 #include <linux/prefetch.h>
45 #include <linux/dma-mapping.h>
46 #include <linux/firmware.h>
48 #include <net/checksum.h>
51 #include <asm/system.h>
53 #include <asm/byteorder.h>
54 #include <linux/uaccess.h>
57 #include <asm/idprom.h>
66 /* Functions & macros to verify TG3_FLAGS types */
68 static inline int _tg3_flag(enum TG3_FLAGS flag, unsigned long *bits)
70 return test_bit(flag, bits);
73 static inline void _tg3_flag_set(enum TG3_FLAGS flag, unsigned long *bits)
78 static inline void _tg3_flag_clear(enum TG3_FLAGS flag, unsigned long *bits)
80 clear_bit(flag, bits);
83 #define tg3_flag(tp, flag) \
84 _tg3_flag(TG3_FLAG_##flag, (tp)->tg3_flags)
85 #define tg3_flag_set(tp, flag) \
86 _tg3_flag_set(TG3_FLAG_##flag, (tp)->tg3_flags)
87 #define tg3_flag_clear(tp, flag) \
88 _tg3_flag_clear(TG3_FLAG_##flag, (tp)->tg3_flags)
90 #define DRV_MODULE_NAME "tg3"
92 #define TG3_MIN_NUM 122
93 #define DRV_MODULE_VERSION \
94 __stringify(TG3_MAJ_NUM) "." __stringify(TG3_MIN_NUM)
95 #define DRV_MODULE_RELDATE "December 7, 2011"
97 #define RESET_KIND_SHUTDOWN 0
98 #define RESET_KIND_INIT 1
99 #define RESET_KIND_SUSPEND 2
101 #define TG3_DEF_RX_MODE 0
102 #define TG3_DEF_TX_MODE 0
103 #define TG3_DEF_MSG_ENABLE \
113 #define TG3_GRC_LCLCTL_PWRSW_DELAY 100
115 /* length of time before we decide the hardware is borked,
116 * and dev->tx_timeout() should be called to fix the problem
119 #define TG3_TX_TIMEOUT (5 * HZ)
121 /* hardware minimum and maximum for a single frame's data payload */
122 #define TG3_MIN_MTU 60
123 #define TG3_MAX_MTU(tp) \
124 (tg3_flag(tp, JUMBO_CAPABLE) ? 9000 : 1500)
126 /* These numbers seem to be hard coded in the NIC firmware somehow.
127 * You can't change the ring sizes, but you can change where you place
128 * them in the NIC onboard memory.
130 #define TG3_RX_STD_RING_SIZE(tp) \
131 (tg3_flag(tp, LRG_PROD_RING_CAP) ? \
132 TG3_RX_STD_MAX_SIZE_5717 : TG3_RX_STD_MAX_SIZE_5700)
133 #define TG3_DEF_RX_RING_PENDING 200
134 #define TG3_RX_JMB_RING_SIZE(tp) \
135 (tg3_flag(tp, LRG_PROD_RING_CAP) ? \
136 TG3_RX_JMB_MAX_SIZE_5717 : TG3_RX_JMB_MAX_SIZE_5700)
137 #define TG3_DEF_RX_JUMBO_RING_PENDING 100
139 /* Do not place this n-ring entries value into the tp struct itself,
140 * we really want to expose these constants to GCC so that modulo et
141 * al. operations are done with shifts and masks instead of with
142 * hw multiply/modulo instructions. Another solution would be to
143 * replace things like '% foo' with '& (foo - 1)'.
146 #define TG3_TX_RING_SIZE 512
147 #define TG3_DEF_TX_RING_PENDING (TG3_TX_RING_SIZE - 1)
149 #define TG3_RX_STD_RING_BYTES(tp) \
150 (sizeof(struct tg3_rx_buffer_desc) * TG3_RX_STD_RING_SIZE(tp))
151 #define TG3_RX_JMB_RING_BYTES(tp) \
152 (sizeof(struct tg3_ext_rx_buffer_desc) * TG3_RX_JMB_RING_SIZE(tp))
153 #define TG3_RX_RCB_RING_BYTES(tp) \
154 (sizeof(struct tg3_rx_buffer_desc) * (tp->rx_ret_ring_mask + 1))
155 #define TG3_TX_RING_BYTES (sizeof(struct tg3_tx_buffer_desc) * \
157 #define NEXT_TX(N) (((N) + 1) & (TG3_TX_RING_SIZE - 1))
159 #define TG3_DMA_BYTE_ENAB 64
161 #define TG3_RX_STD_DMA_SZ 1536
162 #define TG3_RX_JMB_DMA_SZ 9046
164 #define TG3_RX_DMA_TO_MAP_SZ(x) ((x) + TG3_DMA_BYTE_ENAB)
166 #define TG3_RX_STD_MAP_SZ TG3_RX_DMA_TO_MAP_SZ(TG3_RX_STD_DMA_SZ)
167 #define TG3_RX_JMB_MAP_SZ TG3_RX_DMA_TO_MAP_SZ(TG3_RX_JMB_DMA_SZ)
169 #define TG3_RX_STD_BUFF_RING_SIZE(tp) \
170 (sizeof(struct ring_info) * TG3_RX_STD_RING_SIZE(tp))
172 #define TG3_RX_JMB_BUFF_RING_SIZE(tp) \
173 (sizeof(struct ring_info) * TG3_RX_JMB_RING_SIZE(tp))
175 /* Due to a hardware bug, the 5701 can only DMA to memory addresses
176 * that are at least dword aligned when used in PCIX mode. The driver
177 * works around this bug by double copying the packet. This workaround
178 * is built into the normal double copy length check for efficiency.
180 * However, the double copy is only necessary on those architectures
181 * where unaligned memory accesses are inefficient. For those architectures
182 * where unaligned memory accesses incur little penalty, we can reintegrate
183 * the 5701 in the normal rx path. Doing so saves a device structure
184 * dereference by hardcoding the double copy threshold in place.
186 #define TG3_RX_COPY_THRESHOLD 256
187 #if NET_IP_ALIGN == 0 || defined(CONFIG_HAVE_EFFICIENT_UNALIGNED_ACCESS)
188 #define TG3_RX_COPY_THRESH(tp) TG3_RX_COPY_THRESHOLD
190 #define TG3_RX_COPY_THRESH(tp) ((tp)->rx_copy_thresh)
193 #if (NET_IP_ALIGN != 0)
194 #define TG3_RX_OFFSET(tp) ((tp)->rx_offset)
196 #define TG3_RX_OFFSET(tp) (NET_SKB_PAD)
199 /* minimum number of free TX descriptors required to wake up TX process */
200 #define TG3_TX_WAKEUP_THRESH(tnapi) ((tnapi)->tx_pending / 4)
201 #define TG3_TX_BD_DMA_MAX_2K 2048
202 #define TG3_TX_BD_DMA_MAX_4K 4096
204 #define TG3_RAW_IP_ALIGN 2
206 #define TG3_FW_UPDATE_TIMEOUT_SEC 5
208 #define FIRMWARE_TG3 "tigon/tg3.bin"
209 #define FIRMWARE_TG3TSO "tigon/tg3_tso.bin"
210 #define FIRMWARE_TG3TSO5 "tigon/tg3_tso5.bin"
212 static char version[] __devinitdata =
213 DRV_MODULE_NAME ".c:v" DRV_MODULE_VERSION " (" DRV_MODULE_RELDATE ")";
215 MODULE_AUTHOR("David S. Miller (davem@redhat.com) and Jeff Garzik (jgarzik@pobox.com)");
216 MODULE_DESCRIPTION("Broadcom Tigon3 ethernet driver");
217 MODULE_LICENSE("GPL");
218 MODULE_VERSION(DRV_MODULE_VERSION);
219 MODULE_FIRMWARE(FIRMWARE_TG3);
220 MODULE_FIRMWARE(FIRMWARE_TG3TSO);
221 MODULE_FIRMWARE(FIRMWARE_TG3TSO5);
223 static int tg3_debug = -1; /* -1 == use TG3_DEF_MSG_ENABLE as value */
224 module_param(tg3_debug, int, 0);
225 MODULE_PARM_DESC(tg3_debug, "Tigon3 bitmapped debugging message enable value");
227 static DEFINE_PCI_DEVICE_TABLE(tg3_pci_tbl) = {
228 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5700)},
229 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5701)},
230 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5702)},
231 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5703)},
232 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5704)},
233 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5702FE)},
234 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5705)},
235 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5705_2)},
236 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5705M)},
237 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5705M_2)},
238 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5702X)},
239 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5703X)},
240 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5704S)},
241 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5702A3)},
242 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5703A3)},
243 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5782)},
244 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5788)},
245 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5789)},
246 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5901)},
247 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5901_2)},
248 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5704S_2)},
249 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5705F)},
250 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5721)},
251 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5722)},
252 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5751)},
253 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5751M)},
254 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5751F)},
255 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5752)},
256 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5752M)},
257 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5753)},
258 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5753M)},
259 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5753F)},
260 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5754)},
261 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5754M)},
262 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5755)},
263 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5755M)},
264 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5756)},
265 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5786)},
266 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5787)},
267 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5787M)},
268 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5787F)},
269 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5714)},
270 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5714S)},
271 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5715)},
272 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5715S)},
273 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5780)},
274 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5780S)},
275 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5781)},
276 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5906)},
277 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5906M)},
278 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5784)},
279 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5764)},
280 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5723)},
281 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5761)},
282 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5761E)},
283 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_5761S)},
284 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_5761SE)},
285 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_5785_G)},
286 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_5785_F)},
287 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_57780)},
288 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_57760)},
289 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_57790)},
290 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_57788)},
291 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_5717)},
292 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_5718)},
293 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_57781)},
294 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_57785)},
295 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_57761)},
296 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_57765)},
297 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_57791)},
298 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_57795)},
299 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_5719)},
300 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_5720)},
301 {PCI_DEVICE(PCI_VENDOR_ID_SYSKONNECT, PCI_DEVICE_ID_SYSKONNECT_9DXX)},
302 {PCI_DEVICE(PCI_VENDOR_ID_SYSKONNECT, PCI_DEVICE_ID_SYSKONNECT_9MXX)},
303 {PCI_DEVICE(PCI_VENDOR_ID_ALTIMA, PCI_DEVICE_ID_ALTIMA_AC1000)},
304 {PCI_DEVICE(PCI_VENDOR_ID_ALTIMA, PCI_DEVICE_ID_ALTIMA_AC1001)},
305 {PCI_DEVICE(PCI_VENDOR_ID_ALTIMA, PCI_DEVICE_ID_ALTIMA_AC1003)},
306 {PCI_DEVICE(PCI_VENDOR_ID_ALTIMA, PCI_DEVICE_ID_ALTIMA_AC9100)},
307 {PCI_DEVICE(PCI_VENDOR_ID_APPLE, PCI_DEVICE_ID_APPLE_TIGON3)},
308 {PCI_DEVICE(0x10cf, 0x11a2)}, /* Fujitsu 1000base-SX with BCM5703SKHB */
312 MODULE_DEVICE_TABLE(pci, tg3_pci_tbl);
314 static const struct {
315 const char string[ETH_GSTRING_LEN];
316 } ethtool_stats_keys[] = {
319 { "rx_ucast_packets" },
320 { "rx_mcast_packets" },
321 { "rx_bcast_packets" },
323 { "rx_align_errors" },
324 { "rx_xon_pause_rcvd" },
325 { "rx_xoff_pause_rcvd" },
326 { "rx_mac_ctrl_rcvd" },
327 { "rx_xoff_entered" },
328 { "rx_frame_too_long_errors" },
330 { "rx_undersize_packets" },
331 { "rx_in_length_errors" },
332 { "rx_out_length_errors" },
333 { "rx_64_or_less_octet_packets" },
334 { "rx_65_to_127_octet_packets" },
335 { "rx_128_to_255_octet_packets" },
336 { "rx_256_to_511_octet_packets" },
337 { "rx_512_to_1023_octet_packets" },
338 { "rx_1024_to_1522_octet_packets" },
339 { "rx_1523_to_2047_octet_packets" },
340 { "rx_2048_to_4095_octet_packets" },
341 { "rx_4096_to_8191_octet_packets" },
342 { "rx_8192_to_9022_octet_packets" },
349 { "tx_flow_control" },
351 { "tx_single_collisions" },
352 { "tx_mult_collisions" },
354 { "tx_excessive_collisions" },
355 { "tx_late_collisions" },
356 { "tx_collide_2times" },
357 { "tx_collide_3times" },
358 { "tx_collide_4times" },
359 { "tx_collide_5times" },
360 { "tx_collide_6times" },
361 { "tx_collide_7times" },
362 { "tx_collide_8times" },
363 { "tx_collide_9times" },
364 { "tx_collide_10times" },
365 { "tx_collide_11times" },
366 { "tx_collide_12times" },
367 { "tx_collide_13times" },
368 { "tx_collide_14times" },
369 { "tx_collide_15times" },
370 { "tx_ucast_packets" },
371 { "tx_mcast_packets" },
372 { "tx_bcast_packets" },
373 { "tx_carrier_sense_errors" },
377 { "dma_writeq_full" },
378 { "dma_write_prioq_full" },
382 { "rx_threshold_hit" },
384 { "dma_readq_full" },
385 { "dma_read_prioq_full" },
386 { "tx_comp_queue_full" },
388 { "ring_set_send_prod_index" },
389 { "ring_status_update" },
391 { "nic_avoided_irqs" },
392 { "nic_tx_threshold_hit" },
394 { "mbuf_lwm_thresh_hit" },
397 #define TG3_NUM_STATS ARRAY_SIZE(ethtool_stats_keys)
400 static const struct {
401 const char string[ETH_GSTRING_LEN];
402 } ethtool_test_keys[] = {
403 { "nvram test (online) " },
404 { "link test (online) " },
405 { "register test (offline)" },
406 { "memory test (offline)" },
407 { "mac loopback test (offline)" },
408 { "phy loopback test (offline)" },
409 { "ext loopback test (offline)" },
410 { "interrupt test (offline)" },
413 #define TG3_NUM_TEST ARRAY_SIZE(ethtool_test_keys)
416 static void tg3_write32(struct tg3 *tp, u32 off, u32 val)
418 writel(val, tp->regs + off);
421 static u32 tg3_read32(struct tg3 *tp, u32 off)
423 return readl(tp->regs + off);
426 static void tg3_ape_write32(struct tg3 *tp, u32 off, u32 val)
428 writel(val, tp->aperegs + off);
431 static u32 tg3_ape_read32(struct tg3 *tp, u32 off)
433 return readl(tp->aperegs + off);
436 static void tg3_write_indirect_reg32(struct tg3 *tp, u32 off, u32 val)
440 spin_lock_irqsave(&tp->indirect_lock, flags);
441 pci_write_config_dword(tp->pdev, TG3PCI_REG_BASE_ADDR, off);
442 pci_write_config_dword(tp->pdev, TG3PCI_REG_DATA, val);
443 spin_unlock_irqrestore(&tp->indirect_lock, flags);
446 static void tg3_write_flush_reg32(struct tg3 *tp, u32 off, u32 val)
448 writel(val, tp->regs + off);
449 readl(tp->regs + off);
452 static u32 tg3_read_indirect_reg32(struct tg3 *tp, u32 off)
457 spin_lock_irqsave(&tp->indirect_lock, flags);
458 pci_write_config_dword(tp->pdev, TG3PCI_REG_BASE_ADDR, off);
459 pci_read_config_dword(tp->pdev, TG3PCI_REG_DATA, &val);
460 spin_unlock_irqrestore(&tp->indirect_lock, flags);
464 static void tg3_write_indirect_mbox(struct tg3 *tp, u32 off, u32 val)
468 if (off == (MAILBOX_RCVRET_CON_IDX_0 + TG3_64BIT_REG_LOW)) {
469 pci_write_config_dword(tp->pdev, TG3PCI_RCV_RET_RING_CON_IDX +
470 TG3_64BIT_REG_LOW, val);
473 if (off == TG3_RX_STD_PROD_IDX_REG) {
474 pci_write_config_dword(tp->pdev, TG3PCI_STD_RING_PROD_IDX +
475 TG3_64BIT_REG_LOW, val);
479 spin_lock_irqsave(&tp->indirect_lock, flags);
480 pci_write_config_dword(tp->pdev, TG3PCI_REG_BASE_ADDR, off + 0x5600);
481 pci_write_config_dword(tp->pdev, TG3PCI_REG_DATA, val);
482 spin_unlock_irqrestore(&tp->indirect_lock, flags);
484 /* In indirect mode when disabling interrupts, we also need
485 * to clear the interrupt bit in the GRC local ctrl register.
487 if ((off == (MAILBOX_INTERRUPT_0 + TG3_64BIT_REG_LOW)) &&
489 pci_write_config_dword(tp->pdev, TG3PCI_MISC_LOCAL_CTRL,
490 tp->grc_local_ctrl|GRC_LCLCTRL_CLEARINT);
494 static u32 tg3_read_indirect_mbox(struct tg3 *tp, u32 off)
499 spin_lock_irqsave(&tp->indirect_lock, flags);
500 pci_write_config_dword(tp->pdev, TG3PCI_REG_BASE_ADDR, off + 0x5600);
501 pci_read_config_dword(tp->pdev, TG3PCI_REG_DATA, &val);
502 spin_unlock_irqrestore(&tp->indirect_lock, flags);
506 /* usec_wait specifies the wait time in usec when writing to certain registers
507 * where it is unsafe to read back the register without some delay.
508 * GRC_LOCAL_CTRL is one example if the GPIOs are toggled to switch power.
509 * TG3PCI_CLOCK_CTRL is another example if the clock frequencies are changed.
511 static void _tw32_flush(struct tg3 *tp, u32 off, u32 val, u32 usec_wait)
513 if (tg3_flag(tp, PCIX_TARGET_HWBUG) || tg3_flag(tp, ICH_WORKAROUND))
514 /* Non-posted methods */
515 tp->write32(tp, off, val);
518 tg3_write32(tp, off, val);
523 /* Wait again after the read for the posted method to guarantee that
524 * the wait time is met.
530 static inline void tw32_mailbox_flush(struct tg3 *tp, u32 off, u32 val)
532 tp->write32_mbox(tp, off, val);
533 if (!tg3_flag(tp, MBOX_WRITE_REORDER) && !tg3_flag(tp, ICH_WORKAROUND))
534 tp->read32_mbox(tp, off);
537 static void tg3_write32_tx_mbox(struct tg3 *tp, u32 off, u32 val)
539 void __iomem *mbox = tp->regs + off;
541 if (tg3_flag(tp, TXD_MBOX_HWBUG))
543 if (tg3_flag(tp, MBOX_WRITE_REORDER))
547 static u32 tg3_read32_mbox_5906(struct tg3 *tp, u32 off)
549 return readl(tp->regs + off + GRCMBOX_BASE);
552 static void tg3_write32_mbox_5906(struct tg3 *tp, u32 off, u32 val)
554 writel(val, tp->regs + off + GRCMBOX_BASE);
557 #define tw32_mailbox(reg, val) tp->write32_mbox(tp, reg, val)
558 #define tw32_mailbox_f(reg, val) tw32_mailbox_flush(tp, (reg), (val))
559 #define tw32_rx_mbox(reg, val) tp->write32_rx_mbox(tp, reg, val)
560 #define tw32_tx_mbox(reg, val) tp->write32_tx_mbox(tp, reg, val)
561 #define tr32_mailbox(reg) tp->read32_mbox(tp, reg)
563 #define tw32(reg, val) tp->write32(tp, reg, val)
564 #define tw32_f(reg, val) _tw32_flush(tp, (reg), (val), 0)
565 #define tw32_wait_f(reg, val, us) _tw32_flush(tp, (reg), (val), (us))
566 #define tr32(reg) tp->read32(tp, reg)
568 static void tg3_write_mem(struct tg3 *tp, u32 off, u32 val)
572 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906 &&
573 (off >= NIC_SRAM_STATS_BLK) && (off < NIC_SRAM_TX_BUFFER_DESC))
576 spin_lock_irqsave(&tp->indirect_lock, flags);
577 if (tg3_flag(tp, SRAM_USE_CONFIG)) {
578 pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_BASE_ADDR, off);
579 pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_DATA, val);
581 /* Always leave this as zero. */
582 pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_BASE_ADDR, 0);
584 tw32_f(TG3PCI_MEM_WIN_BASE_ADDR, off);
585 tw32_f(TG3PCI_MEM_WIN_DATA, val);
587 /* Always leave this as zero. */
588 tw32_f(TG3PCI_MEM_WIN_BASE_ADDR, 0);
590 spin_unlock_irqrestore(&tp->indirect_lock, flags);
593 static void tg3_read_mem(struct tg3 *tp, u32 off, u32 *val)
597 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906 &&
598 (off >= NIC_SRAM_STATS_BLK) && (off < NIC_SRAM_TX_BUFFER_DESC)) {
603 spin_lock_irqsave(&tp->indirect_lock, flags);
604 if (tg3_flag(tp, SRAM_USE_CONFIG)) {
605 pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_BASE_ADDR, off);
606 pci_read_config_dword(tp->pdev, TG3PCI_MEM_WIN_DATA, val);
608 /* Always leave this as zero. */
609 pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_BASE_ADDR, 0);
611 tw32_f(TG3PCI_MEM_WIN_BASE_ADDR, off);
612 *val = tr32(TG3PCI_MEM_WIN_DATA);
614 /* Always leave this as zero. */
615 tw32_f(TG3PCI_MEM_WIN_BASE_ADDR, 0);
617 spin_unlock_irqrestore(&tp->indirect_lock, flags);
620 static void tg3_ape_lock_init(struct tg3 *tp)
625 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5761)
626 regbase = TG3_APE_LOCK_GRANT;
628 regbase = TG3_APE_PER_LOCK_GRANT;
630 /* Make sure the driver hasn't any stale locks. */
631 for (i = TG3_APE_LOCK_PHY0; i <= TG3_APE_LOCK_GPIO; i++) {
633 case TG3_APE_LOCK_PHY0:
634 case TG3_APE_LOCK_PHY1:
635 case TG3_APE_LOCK_PHY2:
636 case TG3_APE_LOCK_PHY3:
637 bit = APE_LOCK_GRANT_DRIVER;
641 bit = APE_LOCK_GRANT_DRIVER;
643 bit = 1 << tp->pci_fn;
645 tg3_ape_write32(tp, regbase + 4 * i, bit);
650 static int tg3_ape_lock(struct tg3 *tp, int locknum)
654 u32 status, req, gnt, bit;
656 if (!tg3_flag(tp, ENABLE_APE))
660 case TG3_APE_LOCK_GPIO:
661 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5761)
663 case TG3_APE_LOCK_GRC:
664 case TG3_APE_LOCK_MEM:
666 bit = APE_LOCK_REQ_DRIVER;
668 bit = 1 << tp->pci_fn;
674 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5761) {
675 req = TG3_APE_LOCK_REQ;
676 gnt = TG3_APE_LOCK_GRANT;
678 req = TG3_APE_PER_LOCK_REQ;
679 gnt = TG3_APE_PER_LOCK_GRANT;
684 tg3_ape_write32(tp, req + off, bit);
686 /* Wait for up to 1 millisecond to acquire lock. */
687 for (i = 0; i < 100; i++) {
688 status = tg3_ape_read32(tp, gnt + off);
695 /* Revoke the lock request. */
696 tg3_ape_write32(tp, gnt + off, bit);
703 static void tg3_ape_unlock(struct tg3 *tp, int locknum)
707 if (!tg3_flag(tp, ENABLE_APE))
711 case TG3_APE_LOCK_GPIO:
712 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5761)
714 case TG3_APE_LOCK_GRC:
715 case TG3_APE_LOCK_MEM:
717 bit = APE_LOCK_GRANT_DRIVER;
719 bit = 1 << tp->pci_fn;
725 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5761)
726 gnt = TG3_APE_LOCK_GRANT;
728 gnt = TG3_APE_PER_LOCK_GRANT;
730 tg3_ape_write32(tp, gnt + 4 * locknum, bit);
733 static void tg3_ape_send_event(struct tg3 *tp, u32 event)
738 /* NCSI does not support APE events */
739 if (tg3_flag(tp, APE_HAS_NCSI))
742 apedata = tg3_ape_read32(tp, TG3_APE_SEG_SIG);
743 if (apedata != APE_SEG_SIG_MAGIC)
746 apedata = tg3_ape_read32(tp, TG3_APE_FW_STATUS);
747 if (!(apedata & APE_FW_STATUS_READY))
750 /* Wait for up to 1 millisecond for APE to service previous event. */
751 for (i = 0; i < 10; i++) {
752 if (tg3_ape_lock(tp, TG3_APE_LOCK_MEM))
755 apedata = tg3_ape_read32(tp, TG3_APE_EVENT_STATUS);
757 if (!(apedata & APE_EVENT_STATUS_EVENT_PENDING))
758 tg3_ape_write32(tp, TG3_APE_EVENT_STATUS,
759 event | APE_EVENT_STATUS_EVENT_PENDING);
761 tg3_ape_unlock(tp, TG3_APE_LOCK_MEM);
763 if (!(apedata & APE_EVENT_STATUS_EVENT_PENDING))
769 if (!(apedata & APE_EVENT_STATUS_EVENT_PENDING))
770 tg3_ape_write32(tp, TG3_APE_EVENT, APE_EVENT_1);
773 static void tg3_ape_driver_state_change(struct tg3 *tp, int kind)
778 if (!tg3_flag(tp, ENABLE_APE))
782 case RESET_KIND_INIT:
783 tg3_ape_write32(tp, TG3_APE_HOST_SEG_SIG,
784 APE_HOST_SEG_SIG_MAGIC);
785 tg3_ape_write32(tp, TG3_APE_HOST_SEG_LEN,
786 APE_HOST_SEG_LEN_MAGIC);
787 apedata = tg3_ape_read32(tp, TG3_APE_HOST_INIT_COUNT);
788 tg3_ape_write32(tp, TG3_APE_HOST_INIT_COUNT, ++apedata);
789 tg3_ape_write32(tp, TG3_APE_HOST_DRIVER_ID,
790 APE_HOST_DRIVER_ID_MAGIC(TG3_MAJ_NUM, TG3_MIN_NUM));
791 tg3_ape_write32(tp, TG3_APE_HOST_BEHAVIOR,
792 APE_HOST_BEHAV_NO_PHYLOCK);
793 tg3_ape_write32(tp, TG3_APE_HOST_DRVR_STATE,
794 TG3_APE_HOST_DRVR_STATE_START);
796 event = APE_EVENT_STATUS_STATE_START;
798 case RESET_KIND_SHUTDOWN:
799 /* With the interface we are currently using,
800 * APE does not track driver state. Wiping
801 * out the HOST SEGMENT SIGNATURE forces
802 * the APE to assume OS absent status.
804 tg3_ape_write32(tp, TG3_APE_HOST_SEG_SIG, 0x0);
806 if (device_may_wakeup(&tp->pdev->dev) &&
807 tg3_flag(tp, WOL_ENABLE)) {
808 tg3_ape_write32(tp, TG3_APE_HOST_WOL_SPEED,
809 TG3_APE_HOST_WOL_SPEED_AUTO);
810 apedata = TG3_APE_HOST_DRVR_STATE_WOL;
812 apedata = TG3_APE_HOST_DRVR_STATE_UNLOAD;
814 tg3_ape_write32(tp, TG3_APE_HOST_DRVR_STATE, apedata);
816 event = APE_EVENT_STATUS_STATE_UNLOAD;
818 case RESET_KIND_SUSPEND:
819 event = APE_EVENT_STATUS_STATE_SUSPEND;
825 event |= APE_EVENT_STATUS_DRIVER_EVNT | APE_EVENT_STATUS_STATE_CHNGE;
827 tg3_ape_send_event(tp, event);
830 static void tg3_disable_ints(struct tg3 *tp)
834 tw32(TG3PCI_MISC_HOST_CTRL,
835 (tp->misc_host_ctrl | MISC_HOST_CTRL_MASK_PCI_INT));
836 for (i = 0; i < tp->irq_max; i++)
837 tw32_mailbox_f(tp->napi[i].int_mbox, 0x00000001);
840 static void tg3_enable_ints(struct tg3 *tp)
847 tw32(TG3PCI_MISC_HOST_CTRL,
848 (tp->misc_host_ctrl & ~MISC_HOST_CTRL_MASK_PCI_INT));
850 tp->coal_now = tp->coalesce_mode | HOSTCC_MODE_ENABLE;
851 for (i = 0; i < tp->irq_cnt; i++) {
852 struct tg3_napi *tnapi = &tp->napi[i];
854 tw32_mailbox_f(tnapi->int_mbox, tnapi->last_tag << 24);
855 if (tg3_flag(tp, 1SHOT_MSI))
856 tw32_mailbox_f(tnapi->int_mbox, tnapi->last_tag << 24);
858 tp->coal_now |= tnapi->coal_now;
861 /* Force an initial interrupt */
862 if (!tg3_flag(tp, TAGGED_STATUS) &&
863 (tp->napi[0].hw_status->status & SD_STATUS_UPDATED))
864 tw32(GRC_LOCAL_CTRL, tp->grc_local_ctrl | GRC_LCLCTRL_SETINT);
866 tw32(HOSTCC_MODE, tp->coal_now);
868 tp->coal_now &= ~(tp->napi[0].coal_now | tp->napi[1].coal_now);
871 static inline unsigned int tg3_has_work(struct tg3_napi *tnapi)
873 struct tg3 *tp = tnapi->tp;
874 struct tg3_hw_status *sblk = tnapi->hw_status;
875 unsigned int work_exists = 0;
877 /* check for phy events */
878 if (!(tg3_flag(tp, USE_LINKCHG_REG) || tg3_flag(tp, POLL_SERDES))) {
879 if (sblk->status & SD_STATUS_LINK_CHG)
882 /* check for RX/TX work to do */
883 if (sblk->idx[0].tx_consumer != tnapi->tx_cons ||
884 *(tnapi->rx_rcb_prod_idx) != tnapi->rx_rcb_ptr)
891 * similar to tg3_enable_ints, but it accurately determines whether there
892 * is new work pending and can return without flushing the PIO write
893 * which reenables interrupts
895 static void tg3_int_reenable(struct tg3_napi *tnapi)
897 struct tg3 *tp = tnapi->tp;
899 tw32_mailbox(tnapi->int_mbox, tnapi->last_tag << 24);
902 /* When doing tagged status, this work check is unnecessary.
903 * The last_tag we write above tells the chip which piece of
904 * work we've completed.
906 if (!tg3_flag(tp, TAGGED_STATUS) && tg3_has_work(tnapi))
907 tw32(HOSTCC_MODE, tp->coalesce_mode |
908 HOSTCC_MODE_ENABLE | tnapi->coal_now);
911 static void tg3_switch_clocks(struct tg3 *tp)
916 if (tg3_flag(tp, CPMU_PRESENT) || tg3_flag(tp, 5780_CLASS))
919 clock_ctrl = tr32(TG3PCI_CLOCK_CTRL);
921 orig_clock_ctrl = clock_ctrl;
922 clock_ctrl &= (CLOCK_CTRL_FORCE_CLKRUN |
923 CLOCK_CTRL_CLKRUN_OENABLE |
925 tp->pci_clock_ctrl = clock_ctrl;
927 if (tg3_flag(tp, 5705_PLUS)) {
928 if (orig_clock_ctrl & CLOCK_CTRL_625_CORE) {
929 tw32_wait_f(TG3PCI_CLOCK_CTRL,
930 clock_ctrl | CLOCK_CTRL_625_CORE, 40);
932 } else if ((orig_clock_ctrl & CLOCK_CTRL_44MHZ_CORE) != 0) {
933 tw32_wait_f(TG3PCI_CLOCK_CTRL,
935 (CLOCK_CTRL_44MHZ_CORE | CLOCK_CTRL_ALTCLK),
937 tw32_wait_f(TG3PCI_CLOCK_CTRL,
938 clock_ctrl | (CLOCK_CTRL_ALTCLK),
941 tw32_wait_f(TG3PCI_CLOCK_CTRL, clock_ctrl, 40);
944 #define PHY_BUSY_LOOPS 5000
946 static int tg3_readphy(struct tg3 *tp, int reg, u32 *val)
952 if ((tp->mi_mode & MAC_MI_MODE_AUTO_POLL) != 0) {
954 (tp->mi_mode & ~MAC_MI_MODE_AUTO_POLL));
960 frame_val = ((tp->phy_addr << MI_COM_PHY_ADDR_SHIFT) &
961 MI_COM_PHY_ADDR_MASK);
962 frame_val |= ((reg << MI_COM_REG_ADDR_SHIFT) &
963 MI_COM_REG_ADDR_MASK);
964 frame_val |= (MI_COM_CMD_READ | MI_COM_START);
966 tw32_f(MAC_MI_COM, frame_val);
968 loops = PHY_BUSY_LOOPS;
971 frame_val = tr32(MAC_MI_COM);
973 if ((frame_val & MI_COM_BUSY) == 0) {
975 frame_val = tr32(MAC_MI_COM);
983 *val = frame_val & MI_COM_DATA_MASK;
987 if ((tp->mi_mode & MAC_MI_MODE_AUTO_POLL) != 0) {
988 tw32_f(MAC_MI_MODE, tp->mi_mode);
995 static int tg3_writephy(struct tg3 *tp, int reg, u32 val)
1001 if ((tp->phy_flags & TG3_PHYFLG_IS_FET) &&
1002 (reg == MII_CTRL1000 || reg == MII_TG3_AUX_CTRL))
1005 if ((tp->mi_mode & MAC_MI_MODE_AUTO_POLL) != 0) {
1007 (tp->mi_mode & ~MAC_MI_MODE_AUTO_POLL));
1011 frame_val = ((tp->phy_addr << MI_COM_PHY_ADDR_SHIFT) &
1012 MI_COM_PHY_ADDR_MASK);
1013 frame_val |= ((reg << MI_COM_REG_ADDR_SHIFT) &
1014 MI_COM_REG_ADDR_MASK);
1015 frame_val |= (val & MI_COM_DATA_MASK);
1016 frame_val |= (MI_COM_CMD_WRITE | MI_COM_START);
1018 tw32_f(MAC_MI_COM, frame_val);
1020 loops = PHY_BUSY_LOOPS;
1021 while (loops != 0) {
1023 frame_val = tr32(MAC_MI_COM);
1024 if ((frame_val & MI_COM_BUSY) == 0) {
1026 frame_val = tr32(MAC_MI_COM);
1036 if ((tp->mi_mode & MAC_MI_MODE_AUTO_POLL) != 0) {
1037 tw32_f(MAC_MI_MODE, tp->mi_mode);
1044 static int tg3_phy_cl45_write(struct tg3 *tp, u32 devad, u32 addr, u32 val)
1048 err = tg3_writephy(tp, MII_TG3_MMD_CTRL, devad);
1052 err = tg3_writephy(tp, MII_TG3_MMD_ADDRESS, addr);
1056 err = tg3_writephy(tp, MII_TG3_MMD_CTRL,
1057 MII_TG3_MMD_CTRL_DATA_NOINC | devad);
1061 err = tg3_writephy(tp, MII_TG3_MMD_ADDRESS, val);
1067 static int tg3_phy_cl45_read(struct tg3 *tp, u32 devad, u32 addr, u32 *val)
1071 err = tg3_writephy(tp, MII_TG3_MMD_CTRL, devad);
1075 err = tg3_writephy(tp, MII_TG3_MMD_ADDRESS, addr);
1079 err = tg3_writephy(tp, MII_TG3_MMD_CTRL,
1080 MII_TG3_MMD_CTRL_DATA_NOINC | devad);
1084 err = tg3_readphy(tp, MII_TG3_MMD_ADDRESS, val);
1090 static int tg3_phydsp_read(struct tg3 *tp, u32 reg, u32 *val)
1094 err = tg3_writephy(tp, MII_TG3_DSP_ADDRESS, reg);
1096 err = tg3_readphy(tp, MII_TG3_DSP_RW_PORT, val);
1101 static int tg3_phydsp_write(struct tg3 *tp, u32 reg, u32 val)
1105 err = tg3_writephy(tp, MII_TG3_DSP_ADDRESS, reg);
1107 err = tg3_writephy(tp, MII_TG3_DSP_RW_PORT, val);
1112 static int tg3_phy_auxctl_read(struct tg3 *tp, int reg, u32 *val)
1116 err = tg3_writephy(tp, MII_TG3_AUX_CTRL,
1117 (reg << MII_TG3_AUXCTL_MISC_RDSEL_SHIFT) |
1118 MII_TG3_AUXCTL_SHDWSEL_MISC);
1120 err = tg3_readphy(tp, MII_TG3_AUX_CTRL, val);
1125 static int tg3_phy_auxctl_write(struct tg3 *tp, int reg, u32 set)
1127 if (reg == MII_TG3_AUXCTL_SHDWSEL_MISC)
1128 set |= MII_TG3_AUXCTL_MISC_WREN;
1130 return tg3_writephy(tp, MII_TG3_AUX_CTRL, set | reg);
1133 #define TG3_PHY_AUXCTL_SMDSP_ENABLE(tp) \
1134 tg3_phy_auxctl_write((tp), MII_TG3_AUXCTL_SHDWSEL_AUXCTL, \
1135 MII_TG3_AUXCTL_ACTL_SMDSP_ENA | \
1136 MII_TG3_AUXCTL_ACTL_TX_6DB)
1138 #define TG3_PHY_AUXCTL_SMDSP_DISABLE(tp) \
1139 tg3_phy_auxctl_write((tp), MII_TG3_AUXCTL_SHDWSEL_AUXCTL, \
1140 MII_TG3_AUXCTL_ACTL_TX_6DB);
1142 static int tg3_bmcr_reset(struct tg3 *tp)
1147 /* OK, reset it, and poll the BMCR_RESET bit until it
1148 * clears or we time out.
1150 phy_control = BMCR_RESET;
1151 err = tg3_writephy(tp, MII_BMCR, phy_control);
1157 err = tg3_readphy(tp, MII_BMCR, &phy_control);
1161 if ((phy_control & BMCR_RESET) == 0) {
1173 static int tg3_mdio_read(struct mii_bus *bp, int mii_id, int reg)
1175 struct tg3 *tp = bp->priv;
1178 spin_lock_bh(&tp->lock);
1180 if (tg3_readphy(tp, reg, &val))
1183 spin_unlock_bh(&tp->lock);
1188 static int tg3_mdio_write(struct mii_bus *bp, int mii_id, int reg, u16 val)
1190 struct tg3 *tp = bp->priv;
1193 spin_lock_bh(&tp->lock);
1195 if (tg3_writephy(tp, reg, val))
1198 spin_unlock_bh(&tp->lock);
1203 static int tg3_mdio_reset(struct mii_bus *bp)
1208 static void tg3_mdio_config_5785(struct tg3 *tp)
1211 struct phy_device *phydev;
1213 phydev = tp->mdio_bus->phy_map[TG3_PHY_MII_ADDR];
1214 switch (phydev->drv->phy_id & phydev->drv->phy_id_mask) {
1215 case PHY_ID_BCM50610:
1216 case PHY_ID_BCM50610M:
1217 val = MAC_PHYCFG2_50610_LED_MODES;
1219 case PHY_ID_BCMAC131:
1220 val = MAC_PHYCFG2_AC131_LED_MODES;
1222 case PHY_ID_RTL8211C:
1223 val = MAC_PHYCFG2_RTL8211C_LED_MODES;
1225 case PHY_ID_RTL8201E:
1226 val = MAC_PHYCFG2_RTL8201E_LED_MODES;
1232 if (phydev->interface != PHY_INTERFACE_MODE_RGMII) {
1233 tw32(MAC_PHYCFG2, val);
1235 val = tr32(MAC_PHYCFG1);
1236 val &= ~(MAC_PHYCFG1_RGMII_INT |
1237 MAC_PHYCFG1_RXCLK_TO_MASK | MAC_PHYCFG1_TXCLK_TO_MASK);
1238 val |= MAC_PHYCFG1_RXCLK_TIMEOUT | MAC_PHYCFG1_TXCLK_TIMEOUT;
1239 tw32(MAC_PHYCFG1, val);
1244 if (!tg3_flag(tp, RGMII_INBAND_DISABLE))
1245 val |= MAC_PHYCFG2_EMODE_MASK_MASK |
1246 MAC_PHYCFG2_FMODE_MASK_MASK |
1247 MAC_PHYCFG2_GMODE_MASK_MASK |
1248 MAC_PHYCFG2_ACT_MASK_MASK |
1249 MAC_PHYCFG2_QUAL_MASK_MASK |
1250 MAC_PHYCFG2_INBAND_ENABLE;
1252 tw32(MAC_PHYCFG2, val);
1254 val = tr32(MAC_PHYCFG1);
1255 val &= ~(MAC_PHYCFG1_RXCLK_TO_MASK | MAC_PHYCFG1_TXCLK_TO_MASK |
1256 MAC_PHYCFG1_RGMII_EXT_RX_DEC | MAC_PHYCFG1_RGMII_SND_STAT_EN);
1257 if (!tg3_flag(tp, RGMII_INBAND_DISABLE)) {
1258 if (tg3_flag(tp, RGMII_EXT_IBND_RX_EN))
1259 val |= MAC_PHYCFG1_RGMII_EXT_RX_DEC;
1260 if (tg3_flag(tp, RGMII_EXT_IBND_TX_EN))
1261 val |= MAC_PHYCFG1_RGMII_SND_STAT_EN;
1263 val |= MAC_PHYCFG1_RXCLK_TIMEOUT | MAC_PHYCFG1_TXCLK_TIMEOUT |
1264 MAC_PHYCFG1_RGMII_INT | MAC_PHYCFG1_TXC_DRV;
1265 tw32(MAC_PHYCFG1, val);
1267 val = tr32(MAC_EXT_RGMII_MODE);
1268 val &= ~(MAC_RGMII_MODE_RX_INT_B |
1269 MAC_RGMII_MODE_RX_QUALITY |
1270 MAC_RGMII_MODE_RX_ACTIVITY |
1271 MAC_RGMII_MODE_RX_ENG_DET |
1272 MAC_RGMII_MODE_TX_ENABLE |
1273 MAC_RGMII_MODE_TX_LOWPWR |
1274 MAC_RGMII_MODE_TX_RESET);
1275 if (!tg3_flag(tp, RGMII_INBAND_DISABLE)) {
1276 if (tg3_flag(tp, RGMII_EXT_IBND_RX_EN))
1277 val |= MAC_RGMII_MODE_RX_INT_B |
1278 MAC_RGMII_MODE_RX_QUALITY |
1279 MAC_RGMII_MODE_RX_ACTIVITY |
1280 MAC_RGMII_MODE_RX_ENG_DET;
1281 if (tg3_flag(tp, RGMII_EXT_IBND_TX_EN))
1282 val |= MAC_RGMII_MODE_TX_ENABLE |
1283 MAC_RGMII_MODE_TX_LOWPWR |
1284 MAC_RGMII_MODE_TX_RESET;
1286 tw32(MAC_EXT_RGMII_MODE, val);
1289 static void tg3_mdio_start(struct tg3 *tp)
1291 tp->mi_mode &= ~MAC_MI_MODE_AUTO_POLL;
1292 tw32_f(MAC_MI_MODE, tp->mi_mode);
1295 if (tg3_flag(tp, MDIOBUS_INITED) &&
1296 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785)
1297 tg3_mdio_config_5785(tp);
1300 static int tg3_mdio_init(struct tg3 *tp)
1304 struct phy_device *phydev;
1306 if (tg3_flag(tp, 5717_PLUS)) {
1309 tp->phy_addr = tp->pci_fn + 1;
1311 if (tp->pci_chip_rev_id != CHIPREV_ID_5717_A0)
1312 is_serdes = tr32(SG_DIG_STATUS) & SG_DIG_IS_SERDES;
1314 is_serdes = tr32(TG3_CPMU_PHY_STRAP) &
1315 TG3_CPMU_PHY_STRAP_IS_SERDES;
1319 tp->phy_addr = TG3_PHY_MII_ADDR;
1323 if (!tg3_flag(tp, USE_PHYLIB) || tg3_flag(tp, MDIOBUS_INITED))
1326 tp->mdio_bus = mdiobus_alloc();
1327 if (tp->mdio_bus == NULL)
1330 tp->mdio_bus->name = "tg3 mdio bus";
1331 snprintf(tp->mdio_bus->id, MII_BUS_ID_SIZE, "%x",
1332 (tp->pdev->bus->number << 8) | tp->pdev->devfn);
1333 tp->mdio_bus->priv = tp;
1334 tp->mdio_bus->parent = &tp->pdev->dev;
1335 tp->mdio_bus->read = &tg3_mdio_read;
1336 tp->mdio_bus->write = &tg3_mdio_write;
1337 tp->mdio_bus->reset = &tg3_mdio_reset;
1338 tp->mdio_bus->phy_mask = ~(1 << TG3_PHY_MII_ADDR);
1339 tp->mdio_bus->irq = &tp->mdio_irq[0];
1341 for (i = 0; i < PHY_MAX_ADDR; i++)
1342 tp->mdio_bus->irq[i] = PHY_POLL;
1344 /* The bus registration will look for all the PHYs on the mdio bus.
1345 * Unfortunately, it does not ensure the PHY is powered up before
1346 * accessing the PHY ID registers. A chip reset is the
1347 * quickest way to bring the device back to an operational state..
1349 if (tg3_readphy(tp, MII_BMCR, ®) || (reg & BMCR_PDOWN))
1352 i = mdiobus_register(tp->mdio_bus);
1354 dev_warn(&tp->pdev->dev, "mdiobus_reg failed (0x%x)\n", i);
1355 mdiobus_free(tp->mdio_bus);
1359 phydev = tp->mdio_bus->phy_map[TG3_PHY_MII_ADDR];
1361 if (!phydev || !phydev->drv) {
1362 dev_warn(&tp->pdev->dev, "No PHY devices\n");
1363 mdiobus_unregister(tp->mdio_bus);
1364 mdiobus_free(tp->mdio_bus);
1368 switch (phydev->drv->phy_id & phydev->drv->phy_id_mask) {
1369 case PHY_ID_BCM57780:
1370 phydev->interface = PHY_INTERFACE_MODE_GMII;
1371 phydev->dev_flags |= PHY_BRCM_AUTO_PWRDWN_ENABLE;
1373 case PHY_ID_BCM50610:
1374 case PHY_ID_BCM50610M:
1375 phydev->dev_flags |= PHY_BRCM_CLEAR_RGMII_MODE |
1376 PHY_BRCM_RX_REFCLK_UNUSED |
1377 PHY_BRCM_DIS_TXCRXC_NOENRGY |
1378 PHY_BRCM_AUTO_PWRDWN_ENABLE;
1379 if (tg3_flag(tp, RGMII_INBAND_DISABLE))
1380 phydev->dev_flags |= PHY_BRCM_STD_IBND_DISABLE;
1381 if (tg3_flag(tp, RGMII_EXT_IBND_RX_EN))
1382 phydev->dev_flags |= PHY_BRCM_EXT_IBND_RX_ENABLE;
1383 if (tg3_flag(tp, RGMII_EXT_IBND_TX_EN))
1384 phydev->dev_flags |= PHY_BRCM_EXT_IBND_TX_ENABLE;
1386 case PHY_ID_RTL8211C:
1387 phydev->interface = PHY_INTERFACE_MODE_RGMII;
1389 case PHY_ID_RTL8201E:
1390 case PHY_ID_BCMAC131:
1391 phydev->interface = PHY_INTERFACE_MODE_MII;
1392 phydev->dev_flags |= PHY_BRCM_AUTO_PWRDWN_ENABLE;
1393 tp->phy_flags |= TG3_PHYFLG_IS_FET;
1397 tg3_flag_set(tp, MDIOBUS_INITED);
1399 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785)
1400 tg3_mdio_config_5785(tp);
1405 static void tg3_mdio_fini(struct tg3 *tp)
1407 if (tg3_flag(tp, MDIOBUS_INITED)) {
1408 tg3_flag_clear(tp, MDIOBUS_INITED);
1409 mdiobus_unregister(tp->mdio_bus);
1410 mdiobus_free(tp->mdio_bus);
1414 /* tp->lock is held. */
1415 static inline void tg3_generate_fw_event(struct tg3 *tp)
1419 val = tr32(GRC_RX_CPU_EVENT);
1420 val |= GRC_RX_CPU_DRIVER_EVENT;
1421 tw32_f(GRC_RX_CPU_EVENT, val);
1423 tp->last_event_jiffies = jiffies;
1426 #define TG3_FW_EVENT_TIMEOUT_USEC 2500
1428 /* tp->lock is held. */
1429 static void tg3_wait_for_event_ack(struct tg3 *tp)
1432 unsigned int delay_cnt;
1435 /* If enough time has passed, no wait is necessary. */
1436 time_remain = (long)(tp->last_event_jiffies + 1 +
1437 usecs_to_jiffies(TG3_FW_EVENT_TIMEOUT_USEC)) -
1439 if (time_remain < 0)
1442 /* Check if we can shorten the wait time. */
1443 delay_cnt = jiffies_to_usecs(time_remain);
1444 if (delay_cnt > TG3_FW_EVENT_TIMEOUT_USEC)
1445 delay_cnt = TG3_FW_EVENT_TIMEOUT_USEC;
1446 delay_cnt = (delay_cnt >> 3) + 1;
1448 for (i = 0; i < delay_cnt; i++) {
1449 if (!(tr32(GRC_RX_CPU_EVENT) & GRC_RX_CPU_DRIVER_EVENT))
1455 /* tp->lock is held. */
1456 static void tg3_phy_gather_ump_data(struct tg3 *tp, u32 *data)
1461 if (!tg3_readphy(tp, MII_BMCR, ®))
1463 if (!tg3_readphy(tp, MII_BMSR, ®))
1464 val |= (reg & 0xffff);
1468 if (!tg3_readphy(tp, MII_ADVERTISE, ®))
1470 if (!tg3_readphy(tp, MII_LPA, ®))
1471 val |= (reg & 0xffff);
1475 if (!(tp->phy_flags & TG3_PHYFLG_MII_SERDES)) {
1476 if (!tg3_readphy(tp, MII_CTRL1000, ®))
1478 if (!tg3_readphy(tp, MII_STAT1000, ®))
1479 val |= (reg & 0xffff);
1483 if (!tg3_readphy(tp, MII_PHYADDR, ®))
1490 /* tp->lock is held. */
1491 static void tg3_ump_link_report(struct tg3 *tp)
1495 if (!tg3_flag(tp, 5780_CLASS) || !tg3_flag(tp, ENABLE_ASF))
1498 tg3_phy_gather_ump_data(tp, data);
1500 tg3_wait_for_event_ack(tp);
1502 tg3_write_mem(tp, NIC_SRAM_FW_CMD_MBOX, FWCMD_NICDRV_LINK_UPDATE);
1503 tg3_write_mem(tp, NIC_SRAM_FW_CMD_LEN_MBOX, 14);
1504 tg3_write_mem(tp, NIC_SRAM_FW_CMD_DATA_MBOX + 0x0, data[0]);
1505 tg3_write_mem(tp, NIC_SRAM_FW_CMD_DATA_MBOX + 0x4, data[1]);
1506 tg3_write_mem(tp, NIC_SRAM_FW_CMD_DATA_MBOX + 0x8, data[2]);
1507 tg3_write_mem(tp, NIC_SRAM_FW_CMD_DATA_MBOX + 0xc, data[3]);
1509 tg3_generate_fw_event(tp);
1512 /* tp->lock is held. */
1513 static void tg3_stop_fw(struct tg3 *tp)
1515 if (tg3_flag(tp, ENABLE_ASF) && !tg3_flag(tp, ENABLE_APE)) {
1516 /* Wait for RX cpu to ACK the previous event. */
1517 tg3_wait_for_event_ack(tp);
1519 tg3_write_mem(tp, NIC_SRAM_FW_CMD_MBOX, FWCMD_NICDRV_PAUSE_FW);
1521 tg3_generate_fw_event(tp);
1523 /* Wait for RX cpu to ACK this event. */
1524 tg3_wait_for_event_ack(tp);
1528 /* tp->lock is held. */
1529 static void tg3_write_sig_pre_reset(struct tg3 *tp, int kind)
1531 tg3_write_mem(tp, NIC_SRAM_FIRMWARE_MBOX,
1532 NIC_SRAM_FIRMWARE_MBOX_MAGIC1);
1534 if (tg3_flag(tp, ASF_NEW_HANDSHAKE)) {
1536 case RESET_KIND_INIT:
1537 tg3_write_mem(tp, NIC_SRAM_FW_DRV_STATE_MBOX,
1541 case RESET_KIND_SHUTDOWN:
1542 tg3_write_mem(tp, NIC_SRAM_FW_DRV_STATE_MBOX,
1546 case RESET_KIND_SUSPEND:
1547 tg3_write_mem(tp, NIC_SRAM_FW_DRV_STATE_MBOX,
1556 if (kind == RESET_KIND_INIT ||
1557 kind == RESET_KIND_SUSPEND)
1558 tg3_ape_driver_state_change(tp, kind);
1561 /* tp->lock is held. */
1562 static void tg3_write_sig_post_reset(struct tg3 *tp, int kind)
1564 if (tg3_flag(tp, ASF_NEW_HANDSHAKE)) {
1566 case RESET_KIND_INIT:
1567 tg3_write_mem(tp, NIC_SRAM_FW_DRV_STATE_MBOX,
1568 DRV_STATE_START_DONE);
1571 case RESET_KIND_SHUTDOWN:
1572 tg3_write_mem(tp, NIC_SRAM_FW_DRV_STATE_MBOX,
1573 DRV_STATE_UNLOAD_DONE);
1581 if (kind == RESET_KIND_SHUTDOWN)
1582 tg3_ape_driver_state_change(tp, kind);
1585 /* tp->lock is held. */
1586 static void tg3_write_sig_legacy(struct tg3 *tp, int kind)
1588 if (tg3_flag(tp, ENABLE_ASF)) {
1590 case RESET_KIND_INIT:
1591 tg3_write_mem(tp, NIC_SRAM_FW_DRV_STATE_MBOX,
1595 case RESET_KIND_SHUTDOWN:
1596 tg3_write_mem(tp, NIC_SRAM_FW_DRV_STATE_MBOX,
1600 case RESET_KIND_SUSPEND:
1601 tg3_write_mem(tp, NIC_SRAM_FW_DRV_STATE_MBOX,
1611 static int tg3_poll_fw(struct tg3 *tp)
1616 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
1617 /* Wait up to 20ms for init done. */
1618 for (i = 0; i < 200; i++) {
1619 if (tr32(VCPU_STATUS) & VCPU_STATUS_INIT_DONE)
1626 /* Wait for firmware initialization to complete. */
1627 for (i = 0; i < 100000; i++) {
1628 tg3_read_mem(tp, NIC_SRAM_FIRMWARE_MBOX, &val);
1629 if (val == ~NIC_SRAM_FIRMWARE_MBOX_MAGIC1)
1634 /* Chip might not be fitted with firmware. Some Sun onboard
1635 * parts are configured like that. So don't signal the timeout
1636 * of the above loop as an error, but do report the lack of
1637 * running firmware once.
1639 if (i >= 100000 && !tg3_flag(tp, NO_FWARE_REPORTED)) {
1640 tg3_flag_set(tp, NO_FWARE_REPORTED);
1642 netdev_info(tp->dev, "No firmware running\n");
1645 if (tp->pci_chip_rev_id == CHIPREV_ID_57765_A0) {
1646 /* The 57765 A0 needs a little more
1647 * time to do some important work.
1655 static void tg3_link_report(struct tg3 *tp)
1657 if (!netif_carrier_ok(tp->dev)) {
1658 netif_info(tp, link, tp->dev, "Link is down\n");
1659 tg3_ump_link_report(tp);
1660 } else if (netif_msg_link(tp)) {
1661 netdev_info(tp->dev, "Link is up at %d Mbps, %s duplex\n",
1662 (tp->link_config.active_speed == SPEED_1000 ?
1664 (tp->link_config.active_speed == SPEED_100 ?
1666 (tp->link_config.active_duplex == DUPLEX_FULL ?
1669 netdev_info(tp->dev, "Flow control is %s for TX and %s for RX\n",
1670 (tp->link_config.active_flowctrl & FLOW_CTRL_TX) ?
1672 (tp->link_config.active_flowctrl & FLOW_CTRL_RX) ?
1675 if (tp->phy_flags & TG3_PHYFLG_EEE_CAP)
1676 netdev_info(tp->dev, "EEE is %s\n",
1677 tp->setlpicnt ? "enabled" : "disabled");
1679 tg3_ump_link_report(tp);
1683 static u16 tg3_advert_flowctrl_1000X(u8 flow_ctrl)
1687 if ((flow_ctrl & FLOW_CTRL_TX) && (flow_ctrl & FLOW_CTRL_RX))
1688 miireg = ADVERTISE_1000XPAUSE;
1689 else if (flow_ctrl & FLOW_CTRL_TX)
1690 miireg = ADVERTISE_1000XPSE_ASYM;
1691 else if (flow_ctrl & FLOW_CTRL_RX)
1692 miireg = ADVERTISE_1000XPAUSE | ADVERTISE_1000XPSE_ASYM;
1699 static u8 tg3_resolve_flowctrl_1000X(u16 lcladv, u16 rmtadv)
1703 if (lcladv & rmtadv & ADVERTISE_1000XPAUSE) {
1704 cap = FLOW_CTRL_TX | FLOW_CTRL_RX;
1705 } else if (lcladv & rmtadv & ADVERTISE_1000XPSE_ASYM) {
1706 if (lcladv & ADVERTISE_1000XPAUSE)
1708 if (rmtadv & ADVERTISE_1000XPAUSE)
1715 static void tg3_setup_flow_control(struct tg3 *tp, u32 lcladv, u32 rmtadv)
1719 u32 old_rx_mode = tp->rx_mode;
1720 u32 old_tx_mode = tp->tx_mode;
1722 if (tg3_flag(tp, USE_PHYLIB))
1723 autoneg = tp->mdio_bus->phy_map[TG3_PHY_MII_ADDR]->autoneg;
1725 autoneg = tp->link_config.autoneg;
1727 if (autoneg == AUTONEG_ENABLE && tg3_flag(tp, PAUSE_AUTONEG)) {
1728 if (tp->phy_flags & TG3_PHYFLG_ANY_SERDES)
1729 flowctrl = tg3_resolve_flowctrl_1000X(lcladv, rmtadv);
1731 flowctrl = mii_resolve_flowctrl_fdx(lcladv, rmtadv);
1733 flowctrl = tp->link_config.flowctrl;
1735 tp->link_config.active_flowctrl = flowctrl;
1737 if (flowctrl & FLOW_CTRL_RX)
1738 tp->rx_mode |= RX_MODE_FLOW_CTRL_ENABLE;
1740 tp->rx_mode &= ~RX_MODE_FLOW_CTRL_ENABLE;
1742 if (old_rx_mode != tp->rx_mode)
1743 tw32_f(MAC_RX_MODE, tp->rx_mode);
1745 if (flowctrl & FLOW_CTRL_TX)
1746 tp->tx_mode |= TX_MODE_FLOW_CTRL_ENABLE;
1748 tp->tx_mode &= ~TX_MODE_FLOW_CTRL_ENABLE;
1750 if (old_tx_mode != tp->tx_mode)
1751 tw32_f(MAC_TX_MODE, tp->tx_mode);
1754 static void tg3_adjust_link(struct net_device *dev)
1756 u8 oldflowctrl, linkmesg = 0;
1757 u32 mac_mode, lcl_adv, rmt_adv;
1758 struct tg3 *tp = netdev_priv(dev);
1759 struct phy_device *phydev = tp->mdio_bus->phy_map[TG3_PHY_MII_ADDR];
1761 spin_lock_bh(&tp->lock);
1763 mac_mode = tp->mac_mode & ~(MAC_MODE_PORT_MODE_MASK |
1764 MAC_MODE_HALF_DUPLEX);
1766 oldflowctrl = tp->link_config.active_flowctrl;
1772 if (phydev->speed == SPEED_100 || phydev->speed == SPEED_10)
1773 mac_mode |= MAC_MODE_PORT_MODE_MII;
1774 else if (phydev->speed == SPEED_1000 ||
1775 GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5785)
1776 mac_mode |= MAC_MODE_PORT_MODE_GMII;
1778 mac_mode |= MAC_MODE_PORT_MODE_MII;
1780 if (phydev->duplex == DUPLEX_HALF)
1781 mac_mode |= MAC_MODE_HALF_DUPLEX;
1783 lcl_adv = mii_advertise_flowctrl(
1784 tp->link_config.flowctrl);
1787 rmt_adv = LPA_PAUSE_CAP;
1788 if (phydev->asym_pause)
1789 rmt_adv |= LPA_PAUSE_ASYM;
1792 tg3_setup_flow_control(tp, lcl_adv, rmt_adv);
1794 mac_mode |= MAC_MODE_PORT_MODE_GMII;
1796 if (mac_mode != tp->mac_mode) {
1797 tp->mac_mode = mac_mode;
1798 tw32_f(MAC_MODE, tp->mac_mode);
1802 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785) {
1803 if (phydev->speed == SPEED_10)
1805 MAC_MI_STAT_10MBPS_MODE |
1806 MAC_MI_STAT_LNKSTAT_ATTN_ENAB);
1808 tw32(MAC_MI_STAT, MAC_MI_STAT_LNKSTAT_ATTN_ENAB);
1811 if (phydev->speed == SPEED_1000 && phydev->duplex == DUPLEX_HALF)
1812 tw32(MAC_TX_LENGTHS,
1813 ((2 << TX_LENGTHS_IPG_CRS_SHIFT) |
1814 (6 << TX_LENGTHS_IPG_SHIFT) |
1815 (0xff << TX_LENGTHS_SLOT_TIME_SHIFT)));
1817 tw32(MAC_TX_LENGTHS,
1818 ((2 << TX_LENGTHS_IPG_CRS_SHIFT) |
1819 (6 << TX_LENGTHS_IPG_SHIFT) |
1820 (32 << TX_LENGTHS_SLOT_TIME_SHIFT)));
1822 if ((phydev->link && tp->link_config.active_speed == SPEED_UNKNOWN) ||
1823 (!phydev->link && tp->link_config.active_speed != SPEED_UNKNOWN) ||
1824 phydev->speed != tp->link_config.active_speed ||
1825 phydev->duplex != tp->link_config.active_duplex ||
1826 oldflowctrl != tp->link_config.active_flowctrl)
1829 tp->link_config.active_speed = phydev->speed;
1830 tp->link_config.active_duplex = phydev->duplex;
1832 spin_unlock_bh(&tp->lock);
1835 tg3_link_report(tp);
1838 static int tg3_phy_init(struct tg3 *tp)
1840 struct phy_device *phydev;
1842 if (tp->phy_flags & TG3_PHYFLG_IS_CONNECTED)
1845 /* Bring the PHY back to a known state. */
1848 phydev = tp->mdio_bus->phy_map[TG3_PHY_MII_ADDR];
1850 /* Attach the MAC to the PHY. */
1851 phydev = phy_connect(tp->dev, dev_name(&phydev->dev), tg3_adjust_link,
1852 phydev->dev_flags, phydev->interface);
1853 if (IS_ERR(phydev)) {
1854 dev_err(&tp->pdev->dev, "Could not attach to PHY\n");
1855 return PTR_ERR(phydev);
1858 /* Mask with MAC supported features. */
1859 switch (phydev->interface) {
1860 case PHY_INTERFACE_MODE_GMII:
1861 case PHY_INTERFACE_MODE_RGMII:
1862 if (!(tp->phy_flags & TG3_PHYFLG_10_100_ONLY)) {
1863 phydev->supported &= (PHY_GBIT_FEATURES |
1865 SUPPORTED_Asym_Pause);
1869 case PHY_INTERFACE_MODE_MII:
1870 phydev->supported &= (PHY_BASIC_FEATURES |
1872 SUPPORTED_Asym_Pause);
1875 phy_disconnect(tp->mdio_bus->phy_map[TG3_PHY_MII_ADDR]);
1879 tp->phy_flags |= TG3_PHYFLG_IS_CONNECTED;
1881 phydev->advertising = phydev->supported;
1886 static void tg3_phy_start(struct tg3 *tp)
1888 struct phy_device *phydev;
1890 if (!(tp->phy_flags & TG3_PHYFLG_IS_CONNECTED))
1893 phydev = tp->mdio_bus->phy_map[TG3_PHY_MII_ADDR];
1895 if (tp->phy_flags & TG3_PHYFLG_IS_LOW_POWER) {
1896 tp->phy_flags &= ~TG3_PHYFLG_IS_LOW_POWER;
1897 phydev->speed = tp->link_config.speed;
1898 phydev->duplex = tp->link_config.duplex;
1899 phydev->autoneg = tp->link_config.autoneg;
1900 phydev->advertising = tp->link_config.advertising;
1905 phy_start_aneg(phydev);
1908 static void tg3_phy_stop(struct tg3 *tp)
1910 if (!(tp->phy_flags & TG3_PHYFLG_IS_CONNECTED))
1913 phy_stop(tp->mdio_bus->phy_map[TG3_PHY_MII_ADDR]);
1916 static void tg3_phy_fini(struct tg3 *tp)
1918 if (tp->phy_flags & TG3_PHYFLG_IS_CONNECTED) {
1919 phy_disconnect(tp->mdio_bus->phy_map[TG3_PHY_MII_ADDR]);
1920 tp->phy_flags &= ~TG3_PHYFLG_IS_CONNECTED;
1924 static int tg3_phy_set_extloopbk(struct tg3 *tp)
1929 if (tp->phy_flags & TG3_PHYFLG_IS_FET)
1932 if ((tp->phy_id & TG3_PHY_ID_MASK) == TG3_PHY_ID_BCM5401) {
1933 /* Cannot do read-modify-write on 5401 */
1934 err = tg3_phy_auxctl_write(tp,
1935 MII_TG3_AUXCTL_SHDWSEL_AUXCTL,
1936 MII_TG3_AUXCTL_ACTL_EXTLOOPBK |
1941 err = tg3_phy_auxctl_read(tp,
1942 MII_TG3_AUXCTL_SHDWSEL_AUXCTL, &val);
1946 val |= MII_TG3_AUXCTL_ACTL_EXTLOOPBK;
1947 err = tg3_phy_auxctl_write(tp,
1948 MII_TG3_AUXCTL_SHDWSEL_AUXCTL, val);
1954 static void tg3_phy_fet_toggle_apd(struct tg3 *tp, bool enable)
1958 if (!tg3_readphy(tp, MII_TG3_FET_TEST, &phytest)) {
1961 tg3_writephy(tp, MII_TG3_FET_TEST,
1962 phytest | MII_TG3_FET_SHADOW_EN);
1963 if (!tg3_readphy(tp, MII_TG3_FET_SHDW_AUXSTAT2, &phy)) {
1965 phy |= MII_TG3_FET_SHDW_AUXSTAT2_APD;
1967 phy &= ~MII_TG3_FET_SHDW_AUXSTAT2_APD;
1968 tg3_writephy(tp, MII_TG3_FET_SHDW_AUXSTAT2, phy);
1970 tg3_writephy(tp, MII_TG3_FET_TEST, phytest);
1974 static void tg3_phy_toggle_apd(struct tg3 *tp, bool enable)
1978 if (!tg3_flag(tp, 5705_PLUS) ||
1979 (tg3_flag(tp, 5717_PLUS) &&
1980 (tp->phy_flags & TG3_PHYFLG_MII_SERDES)))
1983 if (tp->phy_flags & TG3_PHYFLG_IS_FET) {
1984 tg3_phy_fet_toggle_apd(tp, enable);
1988 reg = MII_TG3_MISC_SHDW_WREN |
1989 MII_TG3_MISC_SHDW_SCR5_SEL |
1990 MII_TG3_MISC_SHDW_SCR5_LPED |
1991 MII_TG3_MISC_SHDW_SCR5_DLPTLM |
1992 MII_TG3_MISC_SHDW_SCR5_SDTL |
1993 MII_TG3_MISC_SHDW_SCR5_C125OE;
1994 if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5784 || !enable)
1995 reg |= MII_TG3_MISC_SHDW_SCR5_DLLAPD;
1997 tg3_writephy(tp, MII_TG3_MISC_SHDW, reg);
2000 reg = MII_TG3_MISC_SHDW_WREN |
2001 MII_TG3_MISC_SHDW_APD_SEL |
2002 MII_TG3_MISC_SHDW_APD_WKTM_84MS;
2004 reg |= MII_TG3_MISC_SHDW_APD_ENABLE;
2006 tg3_writephy(tp, MII_TG3_MISC_SHDW, reg);
2009 static void tg3_phy_toggle_automdix(struct tg3 *tp, int enable)
2013 if (!tg3_flag(tp, 5705_PLUS) ||
2014 (tp->phy_flags & TG3_PHYFLG_ANY_SERDES))
2017 if (tp->phy_flags & TG3_PHYFLG_IS_FET) {
2020 if (!tg3_readphy(tp, MII_TG3_FET_TEST, &ephy)) {
2021 u32 reg = MII_TG3_FET_SHDW_MISCCTRL;
2023 tg3_writephy(tp, MII_TG3_FET_TEST,
2024 ephy | MII_TG3_FET_SHADOW_EN);
2025 if (!tg3_readphy(tp, reg, &phy)) {
2027 phy |= MII_TG3_FET_SHDW_MISCCTRL_MDIX;
2029 phy &= ~MII_TG3_FET_SHDW_MISCCTRL_MDIX;
2030 tg3_writephy(tp, reg, phy);
2032 tg3_writephy(tp, MII_TG3_FET_TEST, ephy);
2037 ret = tg3_phy_auxctl_read(tp,
2038 MII_TG3_AUXCTL_SHDWSEL_MISC, &phy);
2041 phy |= MII_TG3_AUXCTL_MISC_FORCE_AMDIX;
2043 phy &= ~MII_TG3_AUXCTL_MISC_FORCE_AMDIX;
2044 tg3_phy_auxctl_write(tp,
2045 MII_TG3_AUXCTL_SHDWSEL_MISC, phy);
2050 static void tg3_phy_set_wirespeed(struct tg3 *tp)
2055 if (tp->phy_flags & TG3_PHYFLG_NO_ETH_WIRE_SPEED)
2058 ret = tg3_phy_auxctl_read(tp, MII_TG3_AUXCTL_SHDWSEL_MISC, &val);
2060 tg3_phy_auxctl_write(tp, MII_TG3_AUXCTL_SHDWSEL_MISC,
2061 val | MII_TG3_AUXCTL_MISC_WIRESPD_EN);
2064 static void tg3_phy_apply_otp(struct tg3 *tp)
2073 if (TG3_PHY_AUXCTL_SMDSP_ENABLE(tp))
2076 phy = ((otp & TG3_OTP_AGCTGT_MASK) >> TG3_OTP_AGCTGT_SHIFT);
2077 phy |= MII_TG3_DSP_TAP1_AGCTGT_DFLT;
2078 tg3_phydsp_write(tp, MII_TG3_DSP_TAP1, phy);
2080 phy = ((otp & TG3_OTP_HPFFLTR_MASK) >> TG3_OTP_HPFFLTR_SHIFT) |
2081 ((otp & TG3_OTP_HPFOVER_MASK) >> TG3_OTP_HPFOVER_SHIFT);
2082 tg3_phydsp_write(tp, MII_TG3_DSP_AADJ1CH0, phy);
2084 phy = ((otp & TG3_OTP_LPFDIS_MASK) >> TG3_OTP_LPFDIS_SHIFT);
2085 phy |= MII_TG3_DSP_AADJ1CH3_ADCCKADJ;
2086 tg3_phydsp_write(tp, MII_TG3_DSP_AADJ1CH3, phy);
2088 phy = ((otp & TG3_OTP_VDAC_MASK) >> TG3_OTP_VDAC_SHIFT);
2089 tg3_phydsp_write(tp, MII_TG3_DSP_EXP75, phy);
2091 phy = ((otp & TG3_OTP_10BTAMP_MASK) >> TG3_OTP_10BTAMP_SHIFT);
2092 tg3_phydsp_write(tp, MII_TG3_DSP_EXP96, phy);
2094 phy = ((otp & TG3_OTP_ROFF_MASK) >> TG3_OTP_ROFF_SHIFT) |
2095 ((otp & TG3_OTP_RCOFF_MASK) >> TG3_OTP_RCOFF_SHIFT);
2096 tg3_phydsp_write(tp, MII_TG3_DSP_EXP97, phy);
2098 TG3_PHY_AUXCTL_SMDSP_DISABLE(tp);
2101 static void tg3_phy_eee_adjust(struct tg3 *tp, u32 current_link_up)
2105 if (!(tp->phy_flags & TG3_PHYFLG_EEE_CAP))
2110 if (tp->link_config.autoneg == AUTONEG_ENABLE &&
2111 current_link_up == 1 &&
2112 tp->link_config.active_duplex == DUPLEX_FULL &&
2113 (tp->link_config.active_speed == SPEED_100 ||
2114 tp->link_config.active_speed == SPEED_1000)) {
2117 if (tp->link_config.active_speed == SPEED_1000)
2118 eeectl = TG3_CPMU_EEE_CTRL_EXIT_16_5_US;
2120 eeectl = TG3_CPMU_EEE_CTRL_EXIT_36_US;
2122 tw32(TG3_CPMU_EEE_CTRL, eeectl);
2124 tg3_phy_cl45_read(tp, MDIO_MMD_AN,
2125 TG3_CL45_D7_EEERES_STAT, &val);
2127 if (val == TG3_CL45_D7_EEERES_STAT_LP_1000T ||
2128 val == TG3_CL45_D7_EEERES_STAT_LP_100TX)
2132 if (!tp->setlpicnt) {
2133 if (current_link_up == 1 &&
2134 !TG3_PHY_AUXCTL_SMDSP_ENABLE(tp)) {
2135 tg3_phydsp_write(tp, MII_TG3_DSP_TAP26, 0x0000);
2136 TG3_PHY_AUXCTL_SMDSP_DISABLE(tp);
2139 val = tr32(TG3_CPMU_EEE_MODE);
2140 tw32(TG3_CPMU_EEE_MODE, val & ~TG3_CPMU_EEEMD_LPI_ENABLE);
2144 static void tg3_phy_eee_enable(struct tg3 *tp)
2148 if (tp->link_config.active_speed == SPEED_1000 &&
2149 (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717 ||
2150 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5719 ||
2151 tg3_flag(tp, 57765_CLASS)) &&
2152 !TG3_PHY_AUXCTL_SMDSP_ENABLE(tp)) {
2153 val = MII_TG3_DSP_TAP26_ALNOKO |
2154 MII_TG3_DSP_TAP26_RMRXSTO;
2155 tg3_phydsp_write(tp, MII_TG3_DSP_TAP26, val);
2156 TG3_PHY_AUXCTL_SMDSP_DISABLE(tp);
2159 val = tr32(TG3_CPMU_EEE_MODE);
2160 tw32(TG3_CPMU_EEE_MODE, val | TG3_CPMU_EEEMD_LPI_ENABLE);
2163 static int tg3_wait_macro_done(struct tg3 *tp)
2170 if (!tg3_readphy(tp, MII_TG3_DSP_CONTROL, &tmp32)) {
2171 if ((tmp32 & 0x1000) == 0)
2181 static int tg3_phy_write_and_check_testpat(struct tg3 *tp, int *resetp)
2183 static const u32 test_pat[4][6] = {
2184 { 0x00005555, 0x00000005, 0x00002aaa, 0x0000000a, 0x00003456, 0x00000003 },
2185 { 0x00002aaa, 0x0000000a, 0x00003333, 0x00000003, 0x0000789a, 0x00000005 },
2186 { 0x00005a5a, 0x00000005, 0x00002a6a, 0x0000000a, 0x00001bcd, 0x00000003 },
2187 { 0x00002a5a, 0x0000000a, 0x000033c3, 0x00000003, 0x00002ef1, 0x00000005 }
2191 for (chan = 0; chan < 4; chan++) {
2194 tg3_writephy(tp, MII_TG3_DSP_ADDRESS,
2195 (chan * 0x2000) | 0x0200);
2196 tg3_writephy(tp, MII_TG3_DSP_CONTROL, 0x0002);
2198 for (i = 0; i < 6; i++)
2199 tg3_writephy(tp, MII_TG3_DSP_RW_PORT,
2202 tg3_writephy(tp, MII_TG3_DSP_CONTROL, 0x0202);
2203 if (tg3_wait_macro_done(tp)) {
2208 tg3_writephy(tp, MII_TG3_DSP_ADDRESS,
2209 (chan * 0x2000) | 0x0200);
2210 tg3_writephy(tp, MII_TG3_DSP_CONTROL, 0x0082);
2211 if (tg3_wait_macro_done(tp)) {
2216 tg3_writephy(tp, MII_TG3_DSP_CONTROL, 0x0802);
2217 if (tg3_wait_macro_done(tp)) {
2222 for (i = 0; i < 6; i += 2) {
2225 if (tg3_readphy(tp, MII_TG3_DSP_RW_PORT, &low) ||
2226 tg3_readphy(tp, MII_TG3_DSP_RW_PORT, &high) ||
2227 tg3_wait_macro_done(tp)) {
2233 if (low != test_pat[chan][i] ||
2234 high != test_pat[chan][i+1]) {
2235 tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x000b);
2236 tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x4001);
2237 tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x4005);
2247 static int tg3_phy_reset_chanpat(struct tg3 *tp)
2251 for (chan = 0; chan < 4; chan++) {
2254 tg3_writephy(tp, MII_TG3_DSP_ADDRESS,
2255 (chan * 0x2000) | 0x0200);
2256 tg3_writephy(tp, MII_TG3_DSP_CONTROL, 0x0002);
2257 for (i = 0; i < 6; i++)
2258 tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x000);
2259 tg3_writephy(tp, MII_TG3_DSP_CONTROL, 0x0202);
2260 if (tg3_wait_macro_done(tp))
2267 static int tg3_phy_reset_5703_4_5(struct tg3 *tp)
2269 u32 reg32, phy9_orig;
2270 int retries, do_phy_reset, err;
2276 err = tg3_bmcr_reset(tp);
2282 /* Disable transmitter and interrupt. */
2283 if (tg3_readphy(tp, MII_TG3_EXT_CTRL, ®32))
2287 tg3_writephy(tp, MII_TG3_EXT_CTRL, reg32);
2289 /* Set full-duplex, 1000 mbps. */
2290 tg3_writephy(tp, MII_BMCR,
2291 BMCR_FULLDPLX | BMCR_SPEED1000);
2293 /* Set to master mode. */
2294 if (tg3_readphy(tp, MII_CTRL1000, &phy9_orig))
2297 tg3_writephy(tp, MII_CTRL1000,
2298 CTL1000_AS_MASTER | CTL1000_ENABLE_MASTER);
2300 err = TG3_PHY_AUXCTL_SMDSP_ENABLE(tp);
2304 /* Block the PHY control access. */
2305 tg3_phydsp_write(tp, 0x8005, 0x0800);
2307 err = tg3_phy_write_and_check_testpat(tp, &do_phy_reset);
2310 } while (--retries);
2312 err = tg3_phy_reset_chanpat(tp);
2316 tg3_phydsp_write(tp, 0x8005, 0x0000);
2318 tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x8200);
2319 tg3_writephy(tp, MII_TG3_DSP_CONTROL, 0x0000);
2321 TG3_PHY_AUXCTL_SMDSP_DISABLE(tp);
2323 tg3_writephy(tp, MII_CTRL1000, phy9_orig);
2325 if (!tg3_readphy(tp, MII_TG3_EXT_CTRL, ®32)) {
2327 tg3_writephy(tp, MII_TG3_EXT_CTRL, reg32);
2334 /* This will reset the tigon3 PHY if there is no valid
2335 * link unless the FORCE argument is non-zero.
2337 static int tg3_phy_reset(struct tg3 *tp)
2342 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
2343 val = tr32(GRC_MISC_CFG);
2344 tw32_f(GRC_MISC_CFG, val & ~GRC_MISC_CFG_EPHY_IDDQ);
2347 err = tg3_readphy(tp, MII_BMSR, &val);
2348 err |= tg3_readphy(tp, MII_BMSR, &val);
2352 if (netif_running(tp->dev) && netif_carrier_ok(tp->dev)) {
2353 netif_carrier_off(tp->dev);
2354 tg3_link_report(tp);
2357 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703 ||
2358 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704 ||
2359 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705) {
2360 err = tg3_phy_reset_5703_4_5(tp);
2367 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5784 &&
2368 GET_CHIP_REV(tp->pci_chip_rev_id) != CHIPREV_5784_AX) {
2369 cpmuctrl = tr32(TG3_CPMU_CTRL);
2370 if (cpmuctrl & CPMU_CTRL_GPHY_10MB_RXONLY)
2372 cpmuctrl & ~CPMU_CTRL_GPHY_10MB_RXONLY);
2375 err = tg3_bmcr_reset(tp);
2379 if (cpmuctrl & CPMU_CTRL_GPHY_10MB_RXONLY) {
2380 val = MII_TG3_DSP_EXP8_AEDW | MII_TG3_DSP_EXP8_REJ2MHz;
2381 tg3_phydsp_write(tp, MII_TG3_DSP_EXP8, val);
2383 tw32(TG3_CPMU_CTRL, cpmuctrl);
2386 if (GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5784_AX ||
2387 GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5761_AX) {
2388 val = tr32(TG3_CPMU_LSPD_1000MB_CLK);
2389 if ((val & CPMU_LSPD_1000MB_MACCLK_MASK) ==
2390 CPMU_LSPD_1000MB_MACCLK_12_5) {
2391 val &= ~CPMU_LSPD_1000MB_MACCLK_MASK;
2393 tw32_f(TG3_CPMU_LSPD_1000MB_CLK, val);
2397 if (tg3_flag(tp, 5717_PLUS) &&
2398 (tp->phy_flags & TG3_PHYFLG_MII_SERDES))
2401 tg3_phy_apply_otp(tp);
2403 if (tp->phy_flags & TG3_PHYFLG_ENABLE_APD)
2404 tg3_phy_toggle_apd(tp, true);
2406 tg3_phy_toggle_apd(tp, false);
2409 if ((tp->phy_flags & TG3_PHYFLG_ADC_BUG) &&
2410 !TG3_PHY_AUXCTL_SMDSP_ENABLE(tp)) {
2411 tg3_phydsp_write(tp, 0x201f, 0x2aaa);
2412 tg3_phydsp_write(tp, 0x000a, 0x0323);
2413 TG3_PHY_AUXCTL_SMDSP_DISABLE(tp);
2416 if (tp->phy_flags & TG3_PHYFLG_5704_A0_BUG) {
2417 tg3_writephy(tp, MII_TG3_MISC_SHDW, 0x8d68);
2418 tg3_writephy(tp, MII_TG3_MISC_SHDW, 0x8d68);
2421 if (tp->phy_flags & TG3_PHYFLG_BER_BUG) {
2422 if (!TG3_PHY_AUXCTL_SMDSP_ENABLE(tp)) {
2423 tg3_phydsp_write(tp, 0x000a, 0x310b);
2424 tg3_phydsp_write(tp, 0x201f, 0x9506);
2425 tg3_phydsp_write(tp, 0x401f, 0x14e2);
2426 TG3_PHY_AUXCTL_SMDSP_DISABLE(tp);
2428 } else if (tp->phy_flags & TG3_PHYFLG_JITTER_BUG) {
2429 if (!TG3_PHY_AUXCTL_SMDSP_ENABLE(tp)) {
2430 tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x000a);
2431 if (tp->phy_flags & TG3_PHYFLG_ADJUST_TRIM) {
2432 tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x110b);
2433 tg3_writephy(tp, MII_TG3_TEST1,
2434 MII_TG3_TEST1_TRIM_EN | 0x4);
2436 tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x010b);
2438 TG3_PHY_AUXCTL_SMDSP_DISABLE(tp);
2442 /* Set Extended packet length bit (bit 14) on all chips that */
2443 /* support jumbo frames */
2444 if ((tp->phy_id & TG3_PHY_ID_MASK) == TG3_PHY_ID_BCM5401) {
2445 /* Cannot do read-modify-write on 5401 */
2446 tg3_phy_auxctl_write(tp, MII_TG3_AUXCTL_SHDWSEL_AUXCTL, 0x4c20);
2447 } else if (tg3_flag(tp, JUMBO_CAPABLE)) {
2448 /* Set bit 14 with read-modify-write to preserve other bits */
2449 err = tg3_phy_auxctl_read(tp,
2450 MII_TG3_AUXCTL_SHDWSEL_AUXCTL, &val);
2452 tg3_phy_auxctl_write(tp, MII_TG3_AUXCTL_SHDWSEL_AUXCTL,
2453 val | MII_TG3_AUXCTL_ACTL_EXTPKTLEN);
2456 /* Set phy register 0x10 bit 0 to high fifo elasticity to support
2457 * jumbo frames transmission.
2459 if (tg3_flag(tp, JUMBO_CAPABLE)) {
2460 if (!tg3_readphy(tp, MII_TG3_EXT_CTRL, &val))
2461 tg3_writephy(tp, MII_TG3_EXT_CTRL,
2462 val | MII_TG3_EXT_CTRL_FIFO_ELASTIC);
2465 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
2466 /* adjust output voltage */
2467 tg3_writephy(tp, MII_TG3_FET_PTEST, 0x12);
2470 tg3_phy_toggle_automdix(tp, 1);
2471 tg3_phy_set_wirespeed(tp);
2475 #define TG3_GPIO_MSG_DRVR_PRES 0x00000001
2476 #define TG3_GPIO_MSG_NEED_VAUX 0x00000002
2477 #define TG3_GPIO_MSG_MASK (TG3_GPIO_MSG_DRVR_PRES | \
2478 TG3_GPIO_MSG_NEED_VAUX)
2479 #define TG3_GPIO_MSG_ALL_DRVR_PRES_MASK \
2480 ((TG3_GPIO_MSG_DRVR_PRES << 0) | \
2481 (TG3_GPIO_MSG_DRVR_PRES << 4) | \
2482 (TG3_GPIO_MSG_DRVR_PRES << 8) | \
2483 (TG3_GPIO_MSG_DRVR_PRES << 12))
2485 #define TG3_GPIO_MSG_ALL_NEED_VAUX_MASK \
2486 ((TG3_GPIO_MSG_NEED_VAUX << 0) | \
2487 (TG3_GPIO_MSG_NEED_VAUX << 4) | \
2488 (TG3_GPIO_MSG_NEED_VAUX << 8) | \
2489 (TG3_GPIO_MSG_NEED_VAUX << 12))
2491 static inline u32 tg3_set_function_status(struct tg3 *tp, u32 newstat)
2495 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717 ||
2496 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5719)
2497 status = tg3_ape_read32(tp, TG3_APE_GPIO_MSG);
2499 status = tr32(TG3_CPMU_DRV_STATUS);
2501 shift = TG3_APE_GPIO_MSG_SHIFT + 4 * tp->pci_fn;
2502 status &= ~(TG3_GPIO_MSG_MASK << shift);
2503 status |= (newstat << shift);
2505 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717 ||
2506 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5719)
2507 tg3_ape_write32(tp, TG3_APE_GPIO_MSG, status);
2509 tw32(TG3_CPMU_DRV_STATUS, status);
2511 return status >> TG3_APE_GPIO_MSG_SHIFT;
2514 static inline int tg3_pwrsrc_switch_to_vmain(struct tg3 *tp)
2516 if (!tg3_flag(tp, IS_NIC))
2519 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717 ||
2520 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5719 ||
2521 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5720) {
2522 if (tg3_ape_lock(tp, TG3_APE_LOCK_GPIO))
2525 tg3_set_function_status(tp, TG3_GPIO_MSG_DRVR_PRES);
2527 tw32_wait_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl,
2528 TG3_GRC_LCLCTL_PWRSW_DELAY);
2530 tg3_ape_unlock(tp, TG3_APE_LOCK_GPIO);
2532 tw32_wait_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl,
2533 TG3_GRC_LCLCTL_PWRSW_DELAY);
2539 static void tg3_pwrsrc_die_with_vmain(struct tg3 *tp)
2543 if (!tg3_flag(tp, IS_NIC) ||
2544 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
2545 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701)
2548 grc_local_ctrl = tp->grc_local_ctrl | GRC_LCLCTRL_GPIO_OE1;
2550 tw32_wait_f(GRC_LOCAL_CTRL,
2551 grc_local_ctrl | GRC_LCLCTRL_GPIO_OUTPUT1,
2552 TG3_GRC_LCLCTL_PWRSW_DELAY);
2554 tw32_wait_f(GRC_LOCAL_CTRL,
2556 TG3_GRC_LCLCTL_PWRSW_DELAY);
2558 tw32_wait_f(GRC_LOCAL_CTRL,
2559 grc_local_ctrl | GRC_LCLCTRL_GPIO_OUTPUT1,
2560 TG3_GRC_LCLCTL_PWRSW_DELAY);
2563 static void tg3_pwrsrc_switch_to_vaux(struct tg3 *tp)
2565 if (!tg3_flag(tp, IS_NIC))
2568 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
2569 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701) {
2570 tw32_wait_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl |
2571 (GRC_LCLCTRL_GPIO_OE0 |
2572 GRC_LCLCTRL_GPIO_OE1 |
2573 GRC_LCLCTRL_GPIO_OE2 |
2574 GRC_LCLCTRL_GPIO_OUTPUT0 |
2575 GRC_LCLCTRL_GPIO_OUTPUT1),
2576 TG3_GRC_LCLCTL_PWRSW_DELAY);
2577 } else if (tp->pdev->device == PCI_DEVICE_ID_TIGON3_5761 ||
2578 tp->pdev->device == TG3PCI_DEVICE_TIGON3_5761S) {
2579 /* The 5761 non-e device swaps GPIO 0 and GPIO 2. */
2580 u32 grc_local_ctrl = GRC_LCLCTRL_GPIO_OE0 |
2581 GRC_LCLCTRL_GPIO_OE1 |
2582 GRC_LCLCTRL_GPIO_OE2 |
2583 GRC_LCLCTRL_GPIO_OUTPUT0 |
2584 GRC_LCLCTRL_GPIO_OUTPUT1 |
2586 tw32_wait_f(GRC_LOCAL_CTRL, grc_local_ctrl,
2587 TG3_GRC_LCLCTL_PWRSW_DELAY);
2589 grc_local_ctrl |= GRC_LCLCTRL_GPIO_OUTPUT2;
2590 tw32_wait_f(GRC_LOCAL_CTRL, grc_local_ctrl,
2591 TG3_GRC_LCLCTL_PWRSW_DELAY);
2593 grc_local_ctrl &= ~GRC_LCLCTRL_GPIO_OUTPUT0;
2594 tw32_wait_f(GRC_LOCAL_CTRL, grc_local_ctrl,
2595 TG3_GRC_LCLCTL_PWRSW_DELAY);
2598 u32 grc_local_ctrl = 0;
2600 /* Workaround to prevent overdrawing Amps. */
2601 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5714) {
2602 grc_local_ctrl |= GRC_LCLCTRL_GPIO_OE3;
2603 tw32_wait_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl |
2605 TG3_GRC_LCLCTL_PWRSW_DELAY);
2608 /* On 5753 and variants, GPIO2 cannot be used. */
2609 no_gpio2 = tp->nic_sram_data_cfg &
2610 NIC_SRAM_DATA_CFG_NO_GPIO2;
2612 grc_local_ctrl |= GRC_LCLCTRL_GPIO_OE0 |
2613 GRC_LCLCTRL_GPIO_OE1 |
2614 GRC_LCLCTRL_GPIO_OE2 |
2615 GRC_LCLCTRL_GPIO_OUTPUT1 |
2616 GRC_LCLCTRL_GPIO_OUTPUT2;
2618 grc_local_ctrl &= ~(GRC_LCLCTRL_GPIO_OE2 |
2619 GRC_LCLCTRL_GPIO_OUTPUT2);
2621 tw32_wait_f(GRC_LOCAL_CTRL,
2622 tp->grc_local_ctrl | grc_local_ctrl,
2623 TG3_GRC_LCLCTL_PWRSW_DELAY);
2625 grc_local_ctrl |= GRC_LCLCTRL_GPIO_OUTPUT0;
2627 tw32_wait_f(GRC_LOCAL_CTRL,
2628 tp->grc_local_ctrl | grc_local_ctrl,
2629 TG3_GRC_LCLCTL_PWRSW_DELAY);
2632 grc_local_ctrl &= ~GRC_LCLCTRL_GPIO_OUTPUT2;
2633 tw32_wait_f(GRC_LOCAL_CTRL,
2634 tp->grc_local_ctrl | grc_local_ctrl,
2635 TG3_GRC_LCLCTL_PWRSW_DELAY);
2640 static void tg3_frob_aux_power_5717(struct tg3 *tp, bool wol_enable)
2644 /* Serialize power state transitions */
2645 if (tg3_ape_lock(tp, TG3_APE_LOCK_GPIO))
2648 if (tg3_flag(tp, ENABLE_ASF) || tg3_flag(tp, ENABLE_APE) || wol_enable)
2649 msg = TG3_GPIO_MSG_NEED_VAUX;
2651 msg = tg3_set_function_status(tp, msg);
2653 if (msg & TG3_GPIO_MSG_ALL_DRVR_PRES_MASK)
2656 if (msg & TG3_GPIO_MSG_ALL_NEED_VAUX_MASK)
2657 tg3_pwrsrc_switch_to_vaux(tp);
2659 tg3_pwrsrc_die_with_vmain(tp);
2662 tg3_ape_unlock(tp, TG3_APE_LOCK_GPIO);
2665 static void tg3_frob_aux_power(struct tg3 *tp, bool include_wol)
2667 bool need_vaux = false;
2669 /* The GPIOs do something completely different on 57765. */
2670 if (!tg3_flag(tp, IS_NIC) || tg3_flag(tp, 57765_CLASS))
2673 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717 ||
2674 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5719 ||
2675 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5720) {
2676 tg3_frob_aux_power_5717(tp, include_wol ?
2677 tg3_flag(tp, WOL_ENABLE) != 0 : 0);
2681 if (tp->pdev_peer && tp->pdev_peer != tp->pdev) {
2682 struct net_device *dev_peer;
2684 dev_peer = pci_get_drvdata(tp->pdev_peer);
2686 /* remove_one() may have been run on the peer. */
2688 struct tg3 *tp_peer = netdev_priv(dev_peer);
2690 if (tg3_flag(tp_peer, INIT_COMPLETE))
2693 if ((include_wol && tg3_flag(tp_peer, WOL_ENABLE)) ||
2694 tg3_flag(tp_peer, ENABLE_ASF))
2699 if ((include_wol && tg3_flag(tp, WOL_ENABLE)) ||
2700 tg3_flag(tp, ENABLE_ASF))
2704 tg3_pwrsrc_switch_to_vaux(tp);
2706 tg3_pwrsrc_die_with_vmain(tp);
2709 static int tg3_5700_link_polarity(struct tg3 *tp, u32 speed)
2711 if (tp->led_ctrl == LED_CTRL_MODE_PHY_2)
2713 else if ((tp->phy_id & TG3_PHY_ID_MASK) == TG3_PHY_ID_BCM5411) {
2714 if (speed != SPEED_10)
2716 } else if (speed == SPEED_10)
2722 static void tg3_power_down_phy(struct tg3 *tp, bool do_low_power)
2726 if (tp->phy_flags & TG3_PHYFLG_PHY_SERDES) {
2727 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704) {
2728 u32 sg_dig_ctrl = tr32(SG_DIG_CTRL);
2729 u32 serdes_cfg = tr32(MAC_SERDES_CFG);
2732 SG_DIG_USING_HW_AUTONEG | SG_DIG_SOFT_RESET;
2733 tw32(SG_DIG_CTRL, sg_dig_ctrl);
2734 tw32(MAC_SERDES_CFG, serdes_cfg | (1 << 15));
2739 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
2741 val = tr32(GRC_MISC_CFG);
2742 tw32_f(GRC_MISC_CFG, val | GRC_MISC_CFG_EPHY_IDDQ);
2745 } else if (tp->phy_flags & TG3_PHYFLG_IS_FET) {
2747 if (!tg3_readphy(tp, MII_TG3_FET_TEST, &phytest)) {
2750 tg3_writephy(tp, MII_ADVERTISE, 0);
2751 tg3_writephy(tp, MII_BMCR,
2752 BMCR_ANENABLE | BMCR_ANRESTART);
2754 tg3_writephy(tp, MII_TG3_FET_TEST,
2755 phytest | MII_TG3_FET_SHADOW_EN);
2756 if (!tg3_readphy(tp, MII_TG3_FET_SHDW_AUXMODE4, &phy)) {
2757 phy |= MII_TG3_FET_SHDW_AUXMODE4_SBPD;
2759 MII_TG3_FET_SHDW_AUXMODE4,
2762 tg3_writephy(tp, MII_TG3_FET_TEST, phytest);
2765 } else if (do_low_power) {
2766 tg3_writephy(tp, MII_TG3_EXT_CTRL,
2767 MII_TG3_EXT_CTRL_FORCE_LED_OFF);
2769 val = MII_TG3_AUXCTL_PCTL_100TX_LPWR |
2770 MII_TG3_AUXCTL_PCTL_SPR_ISOLATE |
2771 MII_TG3_AUXCTL_PCTL_VREG_11V;
2772 tg3_phy_auxctl_write(tp, MII_TG3_AUXCTL_SHDWSEL_PWRCTL, val);
2775 /* The PHY should not be powered down on some chips because
2778 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
2779 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704 ||
2780 (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5780 &&
2781 (tp->phy_flags & TG3_PHYFLG_MII_SERDES)))
2784 if (GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5784_AX ||
2785 GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5761_AX) {
2786 val = tr32(TG3_CPMU_LSPD_1000MB_CLK);
2787 val &= ~CPMU_LSPD_1000MB_MACCLK_MASK;
2788 val |= CPMU_LSPD_1000MB_MACCLK_12_5;
2789 tw32_f(TG3_CPMU_LSPD_1000MB_CLK, val);
2792 tg3_writephy(tp, MII_BMCR, BMCR_PDOWN);
2795 /* tp->lock is held. */
2796 static int tg3_nvram_lock(struct tg3 *tp)
2798 if (tg3_flag(tp, NVRAM)) {
2801 if (tp->nvram_lock_cnt == 0) {
2802 tw32(NVRAM_SWARB, SWARB_REQ_SET1);
2803 for (i = 0; i < 8000; i++) {
2804 if (tr32(NVRAM_SWARB) & SWARB_GNT1)
2809 tw32(NVRAM_SWARB, SWARB_REQ_CLR1);
2813 tp->nvram_lock_cnt++;
2818 /* tp->lock is held. */
2819 static void tg3_nvram_unlock(struct tg3 *tp)
2821 if (tg3_flag(tp, NVRAM)) {
2822 if (tp->nvram_lock_cnt > 0)
2823 tp->nvram_lock_cnt--;
2824 if (tp->nvram_lock_cnt == 0)
2825 tw32_f(NVRAM_SWARB, SWARB_REQ_CLR1);
2829 /* tp->lock is held. */
2830 static void tg3_enable_nvram_access(struct tg3 *tp)
2832 if (tg3_flag(tp, 5750_PLUS) && !tg3_flag(tp, PROTECTED_NVRAM)) {
2833 u32 nvaccess = tr32(NVRAM_ACCESS);
2835 tw32(NVRAM_ACCESS, nvaccess | ACCESS_ENABLE);
2839 /* tp->lock is held. */
2840 static void tg3_disable_nvram_access(struct tg3 *tp)
2842 if (tg3_flag(tp, 5750_PLUS) && !tg3_flag(tp, PROTECTED_NVRAM)) {
2843 u32 nvaccess = tr32(NVRAM_ACCESS);
2845 tw32(NVRAM_ACCESS, nvaccess & ~ACCESS_ENABLE);
2849 static int tg3_nvram_read_using_eeprom(struct tg3 *tp,
2850 u32 offset, u32 *val)
2855 if (offset > EEPROM_ADDR_ADDR_MASK || (offset % 4) != 0)
2858 tmp = tr32(GRC_EEPROM_ADDR) & ~(EEPROM_ADDR_ADDR_MASK |
2859 EEPROM_ADDR_DEVID_MASK |
2861 tw32(GRC_EEPROM_ADDR,
2863 (0 << EEPROM_ADDR_DEVID_SHIFT) |
2864 ((offset << EEPROM_ADDR_ADDR_SHIFT) &
2865 EEPROM_ADDR_ADDR_MASK) |
2866 EEPROM_ADDR_READ | EEPROM_ADDR_START);
2868 for (i = 0; i < 1000; i++) {
2869 tmp = tr32(GRC_EEPROM_ADDR);
2871 if (tmp & EEPROM_ADDR_COMPLETE)
2875 if (!(tmp & EEPROM_ADDR_COMPLETE))
2878 tmp = tr32(GRC_EEPROM_DATA);
2881 * The data will always be opposite the native endian
2882 * format. Perform a blind byteswap to compensate.
2889 #define NVRAM_CMD_TIMEOUT 10000
2891 static int tg3_nvram_exec_cmd(struct tg3 *tp, u32 nvram_cmd)
2895 tw32(NVRAM_CMD, nvram_cmd);
2896 for (i = 0; i < NVRAM_CMD_TIMEOUT; i++) {
2898 if (tr32(NVRAM_CMD) & NVRAM_CMD_DONE) {
2904 if (i == NVRAM_CMD_TIMEOUT)
2910 static u32 tg3_nvram_phys_addr(struct tg3 *tp, u32 addr)
2912 if (tg3_flag(tp, NVRAM) &&
2913 tg3_flag(tp, NVRAM_BUFFERED) &&
2914 tg3_flag(tp, FLASH) &&
2915 !tg3_flag(tp, NO_NVRAM_ADDR_TRANS) &&
2916 (tp->nvram_jedecnum == JEDEC_ATMEL))
2918 addr = ((addr / tp->nvram_pagesize) <<
2919 ATMEL_AT45DB0X1B_PAGE_POS) +
2920 (addr % tp->nvram_pagesize);
2925 static u32 tg3_nvram_logical_addr(struct tg3 *tp, u32 addr)
2927 if (tg3_flag(tp, NVRAM) &&
2928 tg3_flag(tp, NVRAM_BUFFERED) &&
2929 tg3_flag(tp, FLASH) &&
2930 !tg3_flag(tp, NO_NVRAM_ADDR_TRANS) &&
2931 (tp->nvram_jedecnum == JEDEC_ATMEL))
2933 addr = ((addr >> ATMEL_AT45DB0X1B_PAGE_POS) *
2934 tp->nvram_pagesize) +
2935 (addr & ((1 << ATMEL_AT45DB0X1B_PAGE_POS) - 1));
2940 /* NOTE: Data read in from NVRAM is byteswapped according to
2941 * the byteswapping settings for all other register accesses.
2942 * tg3 devices are BE devices, so on a BE machine, the data
2943 * returned will be exactly as it is seen in NVRAM. On a LE
2944 * machine, the 32-bit value will be byteswapped.
2946 static int tg3_nvram_read(struct tg3 *tp, u32 offset, u32 *val)
2950 if (!tg3_flag(tp, NVRAM))
2951 return tg3_nvram_read_using_eeprom(tp, offset, val);
2953 offset = tg3_nvram_phys_addr(tp, offset);
2955 if (offset > NVRAM_ADDR_MSK)
2958 ret = tg3_nvram_lock(tp);
2962 tg3_enable_nvram_access(tp);
2964 tw32(NVRAM_ADDR, offset);
2965 ret = tg3_nvram_exec_cmd(tp, NVRAM_CMD_RD | NVRAM_CMD_GO |
2966 NVRAM_CMD_FIRST | NVRAM_CMD_LAST | NVRAM_CMD_DONE);
2969 *val = tr32(NVRAM_RDDATA);
2971 tg3_disable_nvram_access(tp);
2973 tg3_nvram_unlock(tp);
2978 /* Ensures NVRAM data is in bytestream format. */
2979 static int tg3_nvram_read_be32(struct tg3 *tp, u32 offset, __be32 *val)
2982 int res = tg3_nvram_read(tp, offset, &v);
2984 *val = cpu_to_be32(v);
2988 static int tg3_nvram_write_block_using_eeprom(struct tg3 *tp,
2989 u32 offset, u32 len, u8 *buf)
2994 for (i = 0; i < len; i += 4) {
3000 memcpy(&data, buf + i, 4);
3003 * The SEEPROM interface expects the data to always be opposite
3004 * the native endian format. We accomplish this by reversing
3005 * all the operations that would have been performed on the
3006 * data from a call to tg3_nvram_read_be32().
3008 tw32(GRC_EEPROM_DATA, swab32(be32_to_cpu(data)));
3010 val = tr32(GRC_EEPROM_ADDR);
3011 tw32(GRC_EEPROM_ADDR, val | EEPROM_ADDR_COMPLETE);
3013 val &= ~(EEPROM_ADDR_ADDR_MASK | EEPROM_ADDR_DEVID_MASK |
3015 tw32(GRC_EEPROM_ADDR, val |
3016 (0 << EEPROM_ADDR_DEVID_SHIFT) |
3017 (addr & EEPROM_ADDR_ADDR_MASK) |
3021 for (j = 0; j < 1000; j++) {
3022 val = tr32(GRC_EEPROM_ADDR);
3024 if (val & EEPROM_ADDR_COMPLETE)
3028 if (!(val & EEPROM_ADDR_COMPLETE)) {
3037 /* offset and length are dword aligned */
3038 static int tg3_nvram_write_block_unbuffered(struct tg3 *tp, u32 offset, u32 len,
3042 u32 pagesize = tp->nvram_pagesize;
3043 u32 pagemask = pagesize - 1;
3047 tmp = kmalloc(pagesize, GFP_KERNEL);
3053 u32 phy_addr, page_off, size;
3055 phy_addr = offset & ~pagemask;
3057 for (j = 0; j < pagesize; j += 4) {
3058 ret = tg3_nvram_read_be32(tp, phy_addr + j,
3059 (__be32 *) (tmp + j));
3066 page_off = offset & pagemask;
3073 memcpy(tmp + page_off, buf, size);
3075 offset = offset + (pagesize - page_off);
3077 tg3_enable_nvram_access(tp);
3080 * Before we can erase the flash page, we need
3081 * to issue a special "write enable" command.
3083 nvram_cmd = NVRAM_CMD_WREN | NVRAM_CMD_GO | NVRAM_CMD_DONE;
3085 if (tg3_nvram_exec_cmd(tp, nvram_cmd))
3088 /* Erase the target page */
3089 tw32(NVRAM_ADDR, phy_addr);
3091 nvram_cmd = NVRAM_CMD_GO | NVRAM_CMD_DONE | NVRAM_CMD_WR |
3092 NVRAM_CMD_FIRST | NVRAM_CMD_LAST | NVRAM_CMD_ERASE;
3094 if (tg3_nvram_exec_cmd(tp, nvram_cmd))
3097 /* Issue another write enable to start the write. */
3098 nvram_cmd = NVRAM_CMD_WREN | NVRAM_CMD_GO | NVRAM_CMD_DONE;
3100 if (tg3_nvram_exec_cmd(tp, nvram_cmd))
3103 for (j = 0; j < pagesize; j += 4) {
3106 data = *((__be32 *) (tmp + j));
3108 tw32(NVRAM_WRDATA, be32_to_cpu(data));
3110 tw32(NVRAM_ADDR, phy_addr + j);
3112 nvram_cmd = NVRAM_CMD_GO | NVRAM_CMD_DONE |
3116 nvram_cmd |= NVRAM_CMD_FIRST;
3117 else if (j == (pagesize - 4))
3118 nvram_cmd |= NVRAM_CMD_LAST;
3120 ret = tg3_nvram_exec_cmd(tp, nvram_cmd);
3128 nvram_cmd = NVRAM_CMD_WRDI | NVRAM_CMD_GO | NVRAM_CMD_DONE;
3129 tg3_nvram_exec_cmd(tp, nvram_cmd);
3136 /* offset and length are dword aligned */
3137 static int tg3_nvram_write_block_buffered(struct tg3 *tp, u32 offset, u32 len,
3142 for (i = 0; i < len; i += 4, offset += 4) {
3143 u32 page_off, phy_addr, nvram_cmd;
3146 memcpy(&data, buf + i, 4);
3147 tw32(NVRAM_WRDATA, be32_to_cpu(data));
3149 page_off = offset % tp->nvram_pagesize;
3151 phy_addr = tg3_nvram_phys_addr(tp, offset);
3153 nvram_cmd = NVRAM_CMD_GO | NVRAM_CMD_DONE | NVRAM_CMD_WR;
3155 if (page_off == 0 || i == 0)
3156 nvram_cmd |= NVRAM_CMD_FIRST;
3157 if (page_off == (tp->nvram_pagesize - 4))
3158 nvram_cmd |= NVRAM_CMD_LAST;
3161 nvram_cmd |= NVRAM_CMD_LAST;
3163 if ((nvram_cmd & NVRAM_CMD_FIRST) ||
3164 !tg3_flag(tp, FLASH) ||
3165 !tg3_flag(tp, 57765_PLUS))
3166 tw32(NVRAM_ADDR, phy_addr);
3168 if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5752 &&
3169 !tg3_flag(tp, 5755_PLUS) &&
3170 (tp->nvram_jedecnum == JEDEC_ST) &&
3171 (nvram_cmd & NVRAM_CMD_FIRST)) {
3174 cmd = NVRAM_CMD_WREN | NVRAM_CMD_GO | NVRAM_CMD_DONE;
3175 ret = tg3_nvram_exec_cmd(tp, cmd);
3179 if (!tg3_flag(tp, FLASH)) {
3180 /* We always do complete word writes to eeprom. */
3181 nvram_cmd |= (NVRAM_CMD_FIRST | NVRAM_CMD_LAST);
3184 ret = tg3_nvram_exec_cmd(tp, nvram_cmd);
3191 /* offset and length are dword aligned */
3192 static int tg3_nvram_write_block(struct tg3 *tp, u32 offset, u32 len, u8 *buf)
3196 if (tg3_flag(tp, EEPROM_WRITE_PROT)) {
3197 tw32_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl &
3198 ~GRC_LCLCTRL_GPIO_OUTPUT1);
3202 if (!tg3_flag(tp, NVRAM)) {
3203 ret = tg3_nvram_write_block_using_eeprom(tp, offset, len, buf);
3207 ret = tg3_nvram_lock(tp);
3211 tg3_enable_nvram_access(tp);
3212 if (tg3_flag(tp, 5750_PLUS) && !tg3_flag(tp, PROTECTED_NVRAM))
3213 tw32(NVRAM_WRITE1, 0x406);
3215 grc_mode = tr32(GRC_MODE);
3216 tw32(GRC_MODE, grc_mode | GRC_MODE_NVRAM_WR_ENABLE);
3218 if (tg3_flag(tp, NVRAM_BUFFERED) || !tg3_flag(tp, FLASH)) {
3219 ret = tg3_nvram_write_block_buffered(tp, offset, len,
3222 ret = tg3_nvram_write_block_unbuffered(tp, offset, len,
3226 grc_mode = tr32(GRC_MODE);
3227 tw32(GRC_MODE, grc_mode & ~GRC_MODE_NVRAM_WR_ENABLE);
3229 tg3_disable_nvram_access(tp);
3230 tg3_nvram_unlock(tp);
3233 if (tg3_flag(tp, EEPROM_WRITE_PROT)) {
3234 tw32_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl);
3241 #define RX_CPU_SCRATCH_BASE 0x30000
3242 #define RX_CPU_SCRATCH_SIZE 0x04000
3243 #define TX_CPU_SCRATCH_BASE 0x34000
3244 #define TX_CPU_SCRATCH_SIZE 0x04000
3246 /* tp->lock is held. */
3247 static int tg3_halt_cpu(struct tg3 *tp, u32 offset)
3251 BUG_ON(offset == TX_CPU_BASE && tg3_flag(tp, 5705_PLUS));
3253 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
3254 u32 val = tr32(GRC_VCPU_EXT_CTRL);
3256 tw32(GRC_VCPU_EXT_CTRL, val | GRC_VCPU_EXT_CTRL_HALT_CPU);
3259 if (offset == RX_CPU_BASE) {
3260 for (i = 0; i < 10000; i++) {
3261 tw32(offset + CPU_STATE, 0xffffffff);
3262 tw32(offset + CPU_MODE, CPU_MODE_HALT);
3263 if (tr32(offset + CPU_MODE) & CPU_MODE_HALT)
3267 tw32(offset + CPU_STATE, 0xffffffff);
3268 tw32_f(offset + CPU_MODE, CPU_MODE_HALT);
3271 for (i = 0; i < 10000; i++) {
3272 tw32(offset + CPU_STATE, 0xffffffff);
3273 tw32(offset + CPU_MODE, CPU_MODE_HALT);
3274 if (tr32(offset + CPU_MODE) & CPU_MODE_HALT)
3280 netdev_err(tp->dev, "%s timed out, %s CPU\n",
3281 __func__, offset == RX_CPU_BASE ? "RX" : "TX");
3285 /* Clear firmware's nvram arbitration. */
3286 if (tg3_flag(tp, NVRAM))
3287 tw32(NVRAM_SWARB, SWARB_REQ_CLR0);
3292 unsigned int fw_base;
3293 unsigned int fw_len;
3294 const __be32 *fw_data;
3297 /* tp->lock is held. */
3298 static int tg3_load_firmware_cpu(struct tg3 *tp, u32 cpu_base,
3299 u32 cpu_scratch_base, int cpu_scratch_size,
3300 struct fw_info *info)
3302 int err, lock_err, i;
3303 void (*write_op)(struct tg3 *, u32, u32);
3305 if (cpu_base == TX_CPU_BASE && tg3_flag(tp, 5705_PLUS)) {
3307 "%s: Trying to load TX cpu firmware which is 5705\n",
3312 if (tg3_flag(tp, 5705_PLUS))
3313 write_op = tg3_write_mem;
3315 write_op = tg3_write_indirect_reg32;
3317 /* It is possible that bootcode is still loading at this point.
3318 * Get the nvram lock first before halting the cpu.
3320 lock_err = tg3_nvram_lock(tp);
3321 err = tg3_halt_cpu(tp, cpu_base);
3323 tg3_nvram_unlock(tp);
3327 for (i = 0; i < cpu_scratch_size; i += sizeof(u32))
3328 write_op(tp, cpu_scratch_base + i, 0);
3329 tw32(cpu_base + CPU_STATE, 0xffffffff);
3330 tw32(cpu_base + CPU_MODE, tr32(cpu_base+CPU_MODE)|CPU_MODE_HALT);
3331 for (i = 0; i < (info->fw_len / sizeof(u32)); i++)
3332 write_op(tp, (cpu_scratch_base +
3333 (info->fw_base & 0xffff) +
3335 be32_to_cpu(info->fw_data[i]));
3343 /* tp->lock is held. */
3344 static int tg3_load_5701_a0_firmware_fix(struct tg3 *tp)
3346 struct fw_info info;
3347 const __be32 *fw_data;
3350 fw_data = (void *)tp->fw->data;
3352 /* Firmware blob starts with version numbers, followed by
3353 start address and length. We are setting complete length.
3354 length = end_address_of_bss - start_address_of_text.
3355 Remainder is the blob to be loaded contiguously
3356 from start address. */
3358 info.fw_base = be32_to_cpu(fw_data[1]);
3359 info.fw_len = tp->fw->size - 12;
3360 info.fw_data = &fw_data[3];
3362 err = tg3_load_firmware_cpu(tp, RX_CPU_BASE,
3363 RX_CPU_SCRATCH_BASE, RX_CPU_SCRATCH_SIZE,
3368 err = tg3_load_firmware_cpu(tp, TX_CPU_BASE,
3369 TX_CPU_SCRATCH_BASE, TX_CPU_SCRATCH_SIZE,
3374 /* Now startup only the RX cpu. */
3375 tw32(RX_CPU_BASE + CPU_STATE, 0xffffffff);
3376 tw32_f(RX_CPU_BASE + CPU_PC, info.fw_base);
3378 for (i = 0; i < 5; i++) {
3379 if (tr32(RX_CPU_BASE + CPU_PC) == info.fw_base)
3381 tw32(RX_CPU_BASE + CPU_STATE, 0xffffffff);
3382 tw32(RX_CPU_BASE + CPU_MODE, CPU_MODE_HALT);
3383 tw32_f(RX_CPU_BASE + CPU_PC, info.fw_base);
3387 netdev_err(tp->dev, "%s fails to set RX CPU PC, is %08x "
3388 "should be %08x\n", __func__,
3389 tr32(RX_CPU_BASE + CPU_PC), info.fw_base);
3392 tw32(RX_CPU_BASE + CPU_STATE, 0xffffffff);
3393 tw32_f(RX_CPU_BASE + CPU_MODE, 0x00000000);
3398 /* tp->lock is held. */
3399 static int tg3_load_tso_firmware(struct tg3 *tp)
3401 struct fw_info info;
3402 const __be32 *fw_data;
3403 unsigned long cpu_base, cpu_scratch_base, cpu_scratch_size;
3406 if (tg3_flag(tp, HW_TSO_1) ||
3407 tg3_flag(tp, HW_TSO_2) ||
3408 tg3_flag(tp, HW_TSO_3))
3411 fw_data = (void *)tp->fw->data;
3413 /* Firmware blob starts with version numbers, followed by
3414 start address and length. We are setting complete length.
3415 length = end_address_of_bss - start_address_of_text.
3416 Remainder is the blob to be loaded contiguously
3417 from start address. */
3419 info.fw_base = be32_to_cpu(fw_data[1]);
3420 cpu_scratch_size = tp->fw_len;
3421 info.fw_len = tp->fw->size - 12;
3422 info.fw_data = &fw_data[3];
3424 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705) {
3425 cpu_base = RX_CPU_BASE;
3426 cpu_scratch_base = NIC_SRAM_MBUF_POOL_BASE5705;
3428 cpu_base = TX_CPU_BASE;
3429 cpu_scratch_base = TX_CPU_SCRATCH_BASE;
3430 cpu_scratch_size = TX_CPU_SCRATCH_SIZE;
3433 err = tg3_load_firmware_cpu(tp, cpu_base,
3434 cpu_scratch_base, cpu_scratch_size,
3439 /* Now startup the cpu. */
3440 tw32(cpu_base + CPU_STATE, 0xffffffff);
3441 tw32_f(cpu_base + CPU_PC, info.fw_base);
3443 for (i = 0; i < 5; i++) {
3444 if (tr32(cpu_base + CPU_PC) == info.fw_base)
3446 tw32(cpu_base + CPU_STATE, 0xffffffff);
3447 tw32(cpu_base + CPU_MODE, CPU_MODE_HALT);
3448 tw32_f(cpu_base + CPU_PC, info.fw_base);
3453 "%s fails to set CPU PC, is %08x should be %08x\n",
3454 __func__, tr32(cpu_base + CPU_PC), info.fw_base);
3457 tw32(cpu_base + CPU_STATE, 0xffffffff);
3458 tw32_f(cpu_base + CPU_MODE, 0x00000000);
3463 /* tp->lock is held. */
3464 static void __tg3_set_mac_addr(struct tg3 *tp, int skip_mac_1)
3466 u32 addr_high, addr_low;
3469 addr_high = ((tp->dev->dev_addr[0] << 8) |
3470 tp->dev->dev_addr[1]);
3471 addr_low = ((tp->dev->dev_addr[2] << 24) |
3472 (tp->dev->dev_addr[3] << 16) |
3473 (tp->dev->dev_addr[4] << 8) |
3474 (tp->dev->dev_addr[5] << 0));
3475 for (i = 0; i < 4; i++) {
3476 if (i == 1 && skip_mac_1)
3478 tw32(MAC_ADDR_0_HIGH + (i * 8), addr_high);
3479 tw32(MAC_ADDR_0_LOW + (i * 8), addr_low);
3482 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703 ||
3483 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704) {
3484 for (i = 0; i < 12; i++) {
3485 tw32(MAC_EXTADDR_0_HIGH + (i * 8), addr_high);
3486 tw32(MAC_EXTADDR_0_LOW + (i * 8), addr_low);
3490 addr_high = (tp->dev->dev_addr[0] +
3491 tp->dev->dev_addr[1] +
3492 tp->dev->dev_addr[2] +
3493 tp->dev->dev_addr[3] +
3494 tp->dev->dev_addr[4] +
3495 tp->dev->dev_addr[5]) &
3496 TX_BACKOFF_SEED_MASK;
3497 tw32(MAC_TX_BACKOFF_SEED, addr_high);
3500 static void tg3_enable_register_access(struct tg3 *tp)
3503 * Make sure register accesses (indirect or otherwise) will function
3506 pci_write_config_dword(tp->pdev,
3507 TG3PCI_MISC_HOST_CTRL, tp->misc_host_ctrl);
3510 static int tg3_power_up(struct tg3 *tp)
3514 tg3_enable_register_access(tp);
3516 err = pci_set_power_state(tp->pdev, PCI_D0);
3518 /* Switch out of Vaux if it is a NIC */
3519 tg3_pwrsrc_switch_to_vmain(tp);
3521 netdev_err(tp->dev, "Transition to D0 failed\n");
3527 static int tg3_setup_phy(struct tg3 *, int);
3529 static int tg3_power_down_prepare(struct tg3 *tp)
3532 bool device_should_wake, do_low_power;
3534 tg3_enable_register_access(tp);
3536 /* Restore the CLKREQ setting. */
3537 if (tg3_flag(tp, CLKREQ_BUG)) {
3540 pci_read_config_word(tp->pdev,
3541 pci_pcie_cap(tp->pdev) + PCI_EXP_LNKCTL,
3543 lnkctl |= PCI_EXP_LNKCTL_CLKREQ_EN;
3544 pci_write_config_word(tp->pdev,
3545 pci_pcie_cap(tp->pdev) + PCI_EXP_LNKCTL,
3549 misc_host_ctrl = tr32(TG3PCI_MISC_HOST_CTRL);
3550 tw32(TG3PCI_MISC_HOST_CTRL,
3551 misc_host_ctrl | MISC_HOST_CTRL_MASK_PCI_INT);
3553 device_should_wake = device_may_wakeup(&tp->pdev->dev) &&
3554 tg3_flag(tp, WOL_ENABLE);
3556 if (tg3_flag(tp, USE_PHYLIB)) {
3557 do_low_power = false;
3558 if ((tp->phy_flags & TG3_PHYFLG_IS_CONNECTED) &&
3559 !(tp->phy_flags & TG3_PHYFLG_IS_LOW_POWER)) {
3560 struct phy_device *phydev;
3561 u32 phyid, advertising;
3563 phydev = tp->mdio_bus->phy_map[TG3_PHY_MII_ADDR];
3565 tp->phy_flags |= TG3_PHYFLG_IS_LOW_POWER;
3567 tp->link_config.speed = phydev->speed;
3568 tp->link_config.duplex = phydev->duplex;
3569 tp->link_config.autoneg = phydev->autoneg;
3570 tp->link_config.advertising = phydev->advertising;
3572 advertising = ADVERTISED_TP |
3574 ADVERTISED_Autoneg |
3575 ADVERTISED_10baseT_Half;
3577 if (tg3_flag(tp, ENABLE_ASF) || device_should_wake) {
3578 if (tg3_flag(tp, WOL_SPEED_100MB))
3580 ADVERTISED_100baseT_Half |
3581 ADVERTISED_100baseT_Full |
3582 ADVERTISED_10baseT_Full;
3584 advertising |= ADVERTISED_10baseT_Full;
3587 phydev->advertising = advertising;
3589 phy_start_aneg(phydev);
3591 phyid = phydev->drv->phy_id & phydev->drv->phy_id_mask;
3592 if (phyid != PHY_ID_BCMAC131) {
3593 phyid &= PHY_BCM_OUI_MASK;
3594 if (phyid == PHY_BCM_OUI_1 ||
3595 phyid == PHY_BCM_OUI_2 ||
3596 phyid == PHY_BCM_OUI_3)
3597 do_low_power = true;
3601 do_low_power = true;
3603 if (!(tp->phy_flags & TG3_PHYFLG_IS_LOW_POWER))
3604 tp->phy_flags |= TG3_PHYFLG_IS_LOW_POWER;
3606 if (!(tp->phy_flags & TG3_PHYFLG_ANY_SERDES))
3607 tg3_setup_phy(tp, 0);
3610 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
3613 val = tr32(GRC_VCPU_EXT_CTRL);
3614 tw32(GRC_VCPU_EXT_CTRL, val | GRC_VCPU_EXT_CTRL_DISABLE_WOL);
3615 } else if (!tg3_flag(tp, ENABLE_ASF)) {
3619 for (i = 0; i < 200; i++) {
3620 tg3_read_mem(tp, NIC_SRAM_FW_ASF_STATUS_MBOX, &val);
3621 if (val == ~NIC_SRAM_FIRMWARE_MBOX_MAGIC1)
3626 if (tg3_flag(tp, WOL_CAP))
3627 tg3_write_mem(tp, NIC_SRAM_WOL_MBOX, WOL_SIGNATURE |
3628 WOL_DRV_STATE_SHUTDOWN |
3632 if (device_should_wake) {
3635 if (!(tp->phy_flags & TG3_PHYFLG_PHY_SERDES)) {
3637 !(tp->phy_flags & TG3_PHYFLG_IS_FET)) {
3638 tg3_phy_auxctl_write(tp,
3639 MII_TG3_AUXCTL_SHDWSEL_PWRCTL,
3640 MII_TG3_AUXCTL_PCTL_WOL_EN |
3641 MII_TG3_AUXCTL_PCTL_100TX_LPWR |
3642 MII_TG3_AUXCTL_PCTL_CL_AB_TXDAC);
3646 if (tp->phy_flags & TG3_PHYFLG_MII_SERDES)
3647 mac_mode = MAC_MODE_PORT_MODE_GMII;
3649 mac_mode = MAC_MODE_PORT_MODE_MII;
3651 mac_mode |= tp->mac_mode & MAC_MODE_LINK_POLARITY;
3652 if (GET_ASIC_REV(tp->pci_chip_rev_id) ==
3654 u32 speed = tg3_flag(tp, WOL_SPEED_100MB) ?
3655 SPEED_100 : SPEED_10;
3656 if (tg3_5700_link_polarity(tp, speed))
3657 mac_mode |= MAC_MODE_LINK_POLARITY;
3659 mac_mode &= ~MAC_MODE_LINK_POLARITY;
3662 mac_mode = MAC_MODE_PORT_MODE_TBI;
3665 if (!tg3_flag(tp, 5750_PLUS))
3666 tw32(MAC_LED_CTRL, tp->led_ctrl);
3668 mac_mode |= MAC_MODE_MAGIC_PKT_ENABLE;
3669 if ((tg3_flag(tp, 5705_PLUS) && !tg3_flag(tp, 5780_CLASS)) &&
3670 (tg3_flag(tp, ENABLE_ASF) || tg3_flag(tp, ENABLE_APE)))
3671 mac_mode |= MAC_MODE_KEEP_FRAME_IN_WOL;
3673 if (tg3_flag(tp, ENABLE_APE))
3674 mac_mode |= MAC_MODE_APE_TX_EN |
3675 MAC_MODE_APE_RX_EN |
3676 MAC_MODE_TDE_ENABLE;
3678 tw32_f(MAC_MODE, mac_mode);
3681 tw32_f(MAC_RX_MODE, RX_MODE_ENABLE);
3685 if (!tg3_flag(tp, WOL_SPEED_100MB) &&
3686 (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
3687 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701)) {
3690 base_val = tp->pci_clock_ctrl;
3691 base_val |= (CLOCK_CTRL_RXCLK_DISABLE |
3692 CLOCK_CTRL_TXCLK_DISABLE);
3694 tw32_wait_f(TG3PCI_CLOCK_CTRL, base_val | CLOCK_CTRL_ALTCLK |
3695 CLOCK_CTRL_PWRDOWN_PLL133, 40);
3696 } else if (tg3_flag(tp, 5780_CLASS) ||
3697 tg3_flag(tp, CPMU_PRESENT) ||
3698 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
3700 } else if (!(tg3_flag(tp, 5750_PLUS) && tg3_flag(tp, ENABLE_ASF))) {
3701 u32 newbits1, newbits2;
3703 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
3704 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701) {
3705 newbits1 = (CLOCK_CTRL_RXCLK_DISABLE |
3706 CLOCK_CTRL_TXCLK_DISABLE |
3708 newbits2 = newbits1 | CLOCK_CTRL_44MHZ_CORE;
3709 } else if (tg3_flag(tp, 5705_PLUS)) {
3710 newbits1 = CLOCK_CTRL_625_CORE;
3711 newbits2 = newbits1 | CLOCK_CTRL_ALTCLK;
3713 newbits1 = CLOCK_CTRL_ALTCLK;
3714 newbits2 = newbits1 | CLOCK_CTRL_44MHZ_CORE;
3717 tw32_wait_f(TG3PCI_CLOCK_CTRL, tp->pci_clock_ctrl | newbits1,
3720 tw32_wait_f(TG3PCI_CLOCK_CTRL, tp->pci_clock_ctrl | newbits2,
3723 if (!tg3_flag(tp, 5705_PLUS)) {
3726 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
3727 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701) {
3728 newbits3 = (CLOCK_CTRL_RXCLK_DISABLE |
3729 CLOCK_CTRL_TXCLK_DISABLE |
3730 CLOCK_CTRL_44MHZ_CORE);
3732 newbits3 = CLOCK_CTRL_44MHZ_CORE;
3735 tw32_wait_f(TG3PCI_CLOCK_CTRL,
3736 tp->pci_clock_ctrl | newbits3, 40);
3740 if (!(device_should_wake) && !tg3_flag(tp, ENABLE_ASF))
3741 tg3_power_down_phy(tp, do_low_power);
3743 tg3_frob_aux_power(tp, true);
3745 /* Workaround for unstable PLL clock */
3746 if ((GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5750_AX) ||
3747 (GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5750_BX)) {
3748 u32 val = tr32(0x7d00);
3750 val &= ~((1 << 16) | (1 << 4) | (1 << 2) | (1 << 1) | 1);
3752 if (!tg3_flag(tp, ENABLE_ASF)) {
3755 err = tg3_nvram_lock(tp);
3756 tg3_halt_cpu(tp, RX_CPU_BASE);
3758 tg3_nvram_unlock(tp);
3762 tg3_write_sig_post_reset(tp, RESET_KIND_SHUTDOWN);
3767 static void tg3_power_down(struct tg3 *tp)
3769 tg3_power_down_prepare(tp);
3771 pci_wake_from_d3(tp->pdev, tg3_flag(tp, WOL_ENABLE));
3772 pci_set_power_state(tp->pdev, PCI_D3hot);
3775 static void tg3_aux_stat_to_speed_duplex(struct tg3 *tp, u32 val, u16 *speed, u8 *duplex)
3777 switch (val & MII_TG3_AUX_STAT_SPDMASK) {
3778 case MII_TG3_AUX_STAT_10HALF:
3780 *duplex = DUPLEX_HALF;
3783 case MII_TG3_AUX_STAT_10FULL:
3785 *duplex = DUPLEX_FULL;
3788 case MII_TG3_AUX_STAT_100HALF:
3790 *duplex = DUPLEX_HALF;
3793 case MII_TG3_AUX_STAT_100FULL:
3795 *duplex = DUPLEX_FULL;
3798 case MII_TG3_AUX_STAT_1000HALF:
3799 *speed = SPEED_1000;
3800 *duplex = DUPLEX_HALF;
3803 case MII_TG3_AUX_STAT_1000FULL:
3804 *speed = SPEED_1000;
3805 *duplex = DUPLEX_FULL;
3809 if (tp->phy_flags & TG3_PHYFLG_IS_FET) {
3810 *speed = (val & MII_TG3_AUX_STAT_100) ? SPEED_100 :
3812 *duplex = (val & MII_TG3_AUX_STAT_FULL) ? DUPLEX_FULL :
3816 *speed = SPEED_UNKNOWN;
3817 *duplex = DUPLEX_UNKNOWN;
3822 static int tg3_phy_autoneg_cfg(struct tg3 *tp, u32 advertise, u32 flowctrl)
3827 new_adv = ADVERTISE_CSMA;
3828 new_adv |= ethtool_adv_to_mii_adv_t(advertise) & ADVERTISE_ALL;
3829 new_adv |= mii_advertise_flowctrl(flowctrl);
3831 err = tg3_writephy(tp, MII_ADVERTISE, new_adv);
3835 if (!(tp->phy_flags & TG3_PHYFLG_10_100_ONLY)) {
3836 new_adv = ethtool_adv_to_mii_ctrl1000_t(advertise);
3838 if (tp->pci_chip_rev_id == CHIPREV_ID_5701_A0 ||
3839 tp->pci_chip_rev_id == CHIPREV_ID_5701_B0)
3840 new_adv |= CTL1000_AS_MASTER | CTL1000_ENABLE_MASTER;
3842 err = tg3_writephy(tp, MII_CTRL1000, new_adv);
3847 if (!(tp->phy_flags & TG3_PHYFLG_EEE_CAP))
3850 tw32(TG3_CPMU_EEE_MODE,
3851 tr32(TG3_CPMU_EEE_MODE) & ~TG3_CPMU_EEEMD_LPI_ENABLE);
3853 err = TG3_PHY_AUXCTL_SMDSP_ENABLE(tp);
3858 /* Advertise 100-BaseTX EEE ability */
3859 if (advertise & ADVERTISED_100baseT_Full)
3860 val |= MDIO_AN_EEE_ADV_100TX;
3861 /* Advertise 1000-BaseT EEE ability */
3862 if (advertise & ADVERTISED_1000baseT_Full)
3863 val |= MDIO_AN_EEE_ADV_1000T;
3864 err = tg3_phy_cl45_write(tp, MDIO_MMD_AN, MDIO_AN_EEE_ADV, val);
3868 switch (GET_ASIC_REV(tp->pci_chip_rev_id)) {
3870 case ASIC_REV_57765:
3871 case ASIC_REV_57766:
3873 /* If we advertised any eee advertisements above... */
3875 val = MII_TG3_DSP_TAP26_ALNOKO |
3876 MII_TG3_DSP_TAP26_RMRXSTO |
3877 MII_TG3_DSP_TAP26_OPCSINPT;
3878 tg3_phydsp_write(tp, MII_TG3_DSP_TAP26, val);
3881 if (!tg3_phydsp_read(tp, MII_TG3_DSP_CH34TP2, &val))
3882 tg3_phydsp_write(tp, MII_TG3_DSP_CH34TP2, val |
3883 MII_TG3_DSP_CH34TP2_HIBW01);
3886 err2 = TG3_PHY_AUXCTL_SMDSP_DISABLE(tp);
3895 static void tg3_phy_copper_begin(struct tg3 *tp)
3900 if (tp->phy_flags & TG3_PHYFLG_IS_LOW_POWER) {
3901 new_adv = ADVERTISED_10baseT_Half |
3902 ADVERTISED_10baseT_Full;
3903 if (tg3_flag(tp, WOL_SPEED_100MB))
3904 new_adv |= ADVERTISED_100baseT_Half |
3905 ADVERTISED_100baseT_Full;
3907 tg3_phy_autoneg_cfg(tp, new_adv,
3908 FLOW_CTRL_TX | FLOW_CTRL_RX);
3909 } else if (tp->link_config.speed == SPEED_UNKNOWN) {
3910 if (tp->phy_flags & TG3_PHYFLG_10_100_ONLY)
3911 tp->link_config.advertising &=
3912 ~(ADVERTISED_1000baseT_Half |
3913 ADVERTISED_1000baseT_Full);
3915 tg3_phy_autoneg_cfg(tp, tp->link_config.advertising,
3916 tp->link_config.flowctrl);
3918 /* Asking for a specific link mode. */
3919 if (tp->link_config.speed == SPEED_1000) {
3920 if (tp->link_config.duplex == DUPLEX_FULL)
3921 new_adv = ADVERTISED_1000baseT_Full;
3923 new_adv = ADVERTISED_1000baseT_Half;
3924 } else if (tp->link_config.speed == SPEED_100) {
3925 if (tp->link_config.duplex == DUPLEX_FULL)
3926 new_adv = ADVERTISED_100baseT_Full;
3928 new_adv = ADVERTISED_100baseT_Half;
3930 if (tp->link_config.duplex == DUPLEX_FULL)
3931 new_adv = ADVERTISED_10baseT_Full;
3933 new_adv = ADVERTISED_10baseT_Half;
3936 tg3_phy_autoneg_cfg(tp, new_adv,
3937 tp->link_config.flowctrl);
3940 if (tp->link_config.autoneg == AUTONEG_DISABLE &&
3941 tp->link_config.speed != SPEED_UNKNOWN) {
3942 u32 bmcr, orig_bmcr;
3944 tp->link_config.active_speed = tp->link_config.speed;
3945 tp->link_config.active_duplex = tp->link_config.duplex;
3948 switch (tp->link_config.speed) {
3954 bmcr |= BMCR_SPEED100;
3958 bmcr |= BMCR_SPEED1000;
3962 if (tp->link_config.duplex == DUPLEX_FULL)
3963 bmcr |= BMCR_FULLDPLX;
3965 if (!tg3_readphy(tp, MII_BMCR, &orig_bmcr) &&
3966 (bmcr != orig_bmcr)) {
3967 tg3_writephy(tp, MII_BMCR, BMCR_LOOPBACK);
3968 for (i = 0; i < 1500; i++) {
3972 if (tg3_readphy(tp, MII_BMSR, &tmp) ||
3973 tg3_readphy(tp, MII_BMSR, &tmp))
3975 if (!(tmp & BMSR_LSTATUS)) {
3980 tg3_writephy(tp, MII_BMCR, bmcr);
3984 tg3_writephy(tp, MII_BMCR,
3985 BMCR_ANENABLE | BMCR_ANRESTART);
3989 static int tg3_init_5401phy_dsp(struct tg3 *tp)
3993 /* Turn off tap power management. */
3994 /* Set Extended packet length bit */
3995 err = tg3_phy_auxctl_write(tp, MII_TG3_AUXCTL_SHDWSEL_AUXCTL, 0x4c20);
3997 err |= tg3_phydsp_write(tp, 0x0012, 0x1804);
3998 err |= tg3_phydsp_write(tp, 0x0013, 0x1204);
3999 err |= tg3_phydsp_write(tp, 0x8006, 0x0132);
4000 err |= tg3_phydsp_write(tp, 0x8006, 0x0232);
4001 err |= tg3_phydsp_write(tp, 0x201f, 0x0a20);
4008 static bool tg3_phy_copper_an_config_ok(struct tg3 *tp, u32 *lcladv)
4010 u32 advmsk, tgtadv, advertising;
4012 advertising = tp->link_config.advertising;
4013 tgtadv = ethtool_adv_to_mii_adv_t(advertising) & ADVERTISE_ALL;
4015 advmsk = ADVERTISE_ALL;
4016 if (tp->link_config.active_duplex == DUPLEX_FULL) {
4017 tgtadv |= mii_advertise_flowctrl(tp->link_config.flowctrl);
4018 advmsk |= ADVERTISE_PAUSE_CAP | ADVERTISE_PAUSE_ASYM;
4021 if (tg3_readphy(tp, MII_ADVERTISE, lcladv))
4024 if ((*lcladv & advmsk) != tgtadv)
4027 if (!(tp->phy_flags & TG3_PHYFLG_10_100_ONLY)) {
4030 tgtadv = ethtool_adv_to_mii_ctrl1000_t(advertising);
4032 if (tg3_readphy(tp, MII_CTRL1000, &tg3_ctrl))
4036 (tp->pci_chip_rev_id == CHIPREV_ID_5701_A0 ||
4037 tp->pci_chip_rev_id == CHIPREV_ID_5701_B0)) {
4038 tgtadv |= CTL1000_AS_MASTER | CTL1000_ENABLE_MASTER;
4039 tg3_ctrl &= (ADVERTISE_1000HALF | ADVERTISE_1000FULL |
4040 CTL1000_AS_MASTER | CTL1000_ENABLE_MASTER);
4042 tg3_ctrl &= (ADVERTISE_1000HALF | ADVERTISE_1000FULL);
4045 if (tg3_ctrl != tgtadv)
4052 static bool tg3_phy_copper_fetch_rmtadv(struct tg3 *tp, u32 *rmtadv)
4056 if (!(tp->phy_flags & TG3_PHYFLG_10_100_ONLY)) {
4059 if (tg3_readphy(tp, MII_STAT1000, &val))
4062 lpeth = mii_stat1000_to_ethtool_lpa_t(val);
4065 if (tg3_readphy(tp, MII_LPA, rmtadv))
4068 lpeth |= mii_lpa_to_ethtool_lpa_t(*rmtadv);
4069 tp->link_config.rmt_adv = lpeth;
4074 static int tg3_setup_copper_phy(struct tg3 *tp, int force_reset)
4076 int current_link_up;
4078 u32 lcl_adv, rmt_adv;
4086 (MAC_STATUS_SYNC_CHANGED |
4087 MAC_STATUS_CFG_CHANGED |
4088 MAC_STATUS_MI_COMPLETION |
4089 MAC_STATUS_LNKSTATE_CHANGED));
4092 if ((tp->mi_mode & MAC_MI_MODE_AUTO_POLL) != 0) {
4094 (tp->mi_mode & ~MAC_MI_MODE_AUTO_POLL));
4098 tg3_phy_auxctl_write(tp, MII_TG3_AUXCTL_SHDWSEL_PWRCTL, 0);
4100 /* Some third-party PHYs need to be reset on link going
4103 if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703 ||
4104 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704 ||
4105 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705) &&
4106 netif_carrier_ok(tp->dev)) {
4107 tg3_readphy(tp, MII_BMSR, &bmsr);
4108 if (!tg3_readphy(tp, MII_BMSR, &bmsr) &&
4109 !(bmsr & BMSR_LSTATUS))
4115 if ((tp->phy_id & TG3_PHY_ID_MASK) == TG3_PHY_ID_BCM5401) {
4116 tg3_readphy(tp, MII_BMSR, &bmsr);
4117 if (tg3_readphy(tp, MII_BMSR, &bmsr) ||
4118 !tg3_flag(tp, INIT_COMPLETE))
4121 if (!(bmsr & BMSR_LSTATUS)) {
4122 err = tg3_init_5401phy_dsp(tp);
4126 tg3_readphy(tp, MII_BMSR, &bmsr);
4127 for (i = 0; i < 1000; i++) {
4129 if (!tg3_readphy(tp, MII_BMSR, &bmsr) &&
4130 (bmsr & BMSR_LSTATUS)) {
4136 if ((tp->phy_id & TG3_PHY_ID_REV_MASK) ==
4137 TG3_PHY_REV_BCM5401_B0 &&
4138 !(bmsr & BMSR_LSTATUS) &&
4139 tp->link_config.active_speed == SPEED_1000) {
4140 err = tg3_phy_reset(tp);
4142 err = tg3_init_5401phy_dsp(tp);
4147 } else if (tp->pci_chip_rev_id == CHIPREV_ID_5701_A0 ||
4148 tp->pci_chip_rev_id == CHIPREV_ID_5701_B0) {
4149 /* 5701 {A0,B0} CRC bug workaround */
4150 tg3_writephy(tp, 0x15, 0x0a75);
4151 tg3_writephy(tp, MII_TG3_MISC_SHDW, 0x8c68);
4152 tg3_writephy(tp, MII_TG3_MISC_SHDW, 0x8d68);
4153 tg3_writephy(tp, MII_TG3_MISC_SHDW, 0x8c68);
4156 /* Clear pending interrupts... */
4157 tg3_readphy(tp, MII_TG3_ISTAT, &val);
4158 tg3_readphy(tp, MII_TG3_ISTAT, &val);
4160 if (tp->phy_flags & TG3_PHYFLG_USE_MI_INTERRUPT)
4161 tg3_writephy(tp, MII_TG3_IMASK, ~MII_TG3_INT_LINKCHG);
4162 else if (!(tp->phy_flags & TG3_PHYFLG_IS_FET))
4163 tg3_writephy(tp, MII_TG3_IMASK, ~0);
4165 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
4166 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701) {
4167 if (tp->led_ctrl == LED_CTRL_MODE_PHY_1)
4168 tg3_writephy(tp, MII_TG3_EXT_CTRL,
4169 MII_TG3_EXT_CTRL_LNK3_LED_MODE);
4171 tg3_writephy(tp, MII_TG3_EXT_CTRL, 0);
4174 current_link_up = 0;
4175 current_speed = SPEED_UNKNOWN;
4176 current_duplex = DUPLEX_UNKNOWN;
4177 tp->phy_flags &= ~TG3_PHYFLG_MDIX_STATE;
4178 tp->link_config.rmt_adv = 0;
4180 if (tp->phy_flags & TG3_PHYFLG_CAPACITIVE_COUPLING) {
4181 err = tg3_phy_auxctl_read(tp,
4182 MII_TG3_AUXCTL_SHDWSEL_MISCTEST,
4184 if (!err && !(val & (1 << 10))) {
4185 tg3_phy_auxctl_write(tp,
4186 MII_TG3_AUXCTL_SHDWSEL_MISCTEST,
4193 for (i = 0; i < 100; i++) {
4194 tg3_readphy(tp, MII_BMSR, &bmsr);
4195 if (!tg3_readphy(tp, MII_BMSR, &bmsr) &&
4196 (bmsr & BMSR_LSTATUS))
4201 if (bmsr & BMSR_LSTATUS) {
4204 tg3_readphy(tp, MII_TG3_AUX_STAT, &aux_stat);
4205 for (i = 0; i < 2000; i++) {
4207 if (!tg3_readphy(tp, MII_TG3_AUX_STAT, &aux_stat) &&
4212 tg3_aux_stat_to_speed_duplex(tp, aux_stat,
4217 for (i = 0; i < 200; i++) {
4218 tg3_readphy(tp, MII_BMCR, &bmcr);
4219 if (tg3_readphy(tp, MII_BMCR, &bmcr))
4221 if (bmcr && bmcr != 0x7fff)
4229 tp->link_config.active_speed = current_speed;
4230 tp->link_config.active_duplex = current_duplex;
4232 if (tp->link_config.autoneg == AUTONEG_ENABLE) {
4233 if ((bmcr & BMCR_ANENABLE) &&
4234 tg3_phy_copper_an_config_ok(tp, &lcl_adv) &&
4235 tg3_phy_copper_fetch_rmtadv(tp, &rmt_adv))
4236 current_link_up = 1;
4238 if (!(bmcr & BMCR_ANENABLE) &&
4239 tp->link_config.speed == current_speed &&
4240 tp->link_config.duplex == current_duplex &&
4241 tp->link_config.flowctrl ==
4242 tp->link_config.active_flowctrl) {
4243 current_link_up = 1;
4247 if (current_link_up == 1 &&
4248 tp->link_config.active_duplex == DUPLEX_FULL) {
4251 if (tp->phy_flags & TG3_PHYFLG_IS_FET) {
4252 reg = MII_TG3_FET_GEN_STAT;
4253 bit = MII_TG3_FET_GEN_STAT_MDIXSTAT;
4255 reg = MII_TG3_EXT_STAT;
4256 bit = MII_TG3_EXT_STAT_MDIX;
4259 if (!tg3_readphy(tp, reg, &val) && (val & bit))
4260 tp->phy_flags |= TG3_PHYFLG_MDIX_STATE;
4262 tg3_setup_flow_control(tp, lcl_adv, rmt_adv);
4267 if (current_link_up == 0 || (tp->phy_flags & TG3_PHYFLG_IS_LOW_POWER)) {
4268 tg3_phy_copper_begin(tp);
4270 tg3_readphy(tp, MII_BMSR, &bmsr);
4271 if ((!tg3_readphy(tp, MII_BMSR, &bmsr) && (bmsr & BMSR_LSTATUS)) ||
4272 (tp->mac_mode & MAC_MODE_PORT_INT_LPBACK))
4273 current_link_up = 1;
4276 tp->mac_mode &= ~MAC_MODE_PORT_MODE_MASK;
4277 if (current_link_up == 1) {
4278 if (tp->link_config.active_speed == SPEED_100 ||
4279 tp->link_config.active_speed == SPEED_10)
4280 tp->mac_mode |= MAC_MODE_PORT_MODE_MII;
4282 tp->mac_mode |= MAC_MODE_PORT_MODE_GMII;
4283 } else if (tp->phy_flags & TG3_PHYFLG_IS_FET)
4284 tp->mac_mode |= MAC_MODE_PORT_MODE_MII;
4286 tp->mac_mode |= MAC_MODE_PORT_MODE_GMII;
4288 tp->mac_mode &= ~MAC_MODE_HALF_DUPLEX;
4289 if (tp->link_config.active_duplex == DUPLEX_HALF)
4290 tp->mac_mode |= MAC_MODE_HALF_DUPLEX;
4292 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700) {
4293 if (current_link_up == 1 &&
4294 tg3_5700_link_polarity(tp, tp->link_config.active_speed))
4295 tp->mac_mode |= MAC_MODE_LINK_POLARITY;
4297 tp->mac_mode &= ~MAC_MODE_LINK_POLARITY;
4300 /* ??? Without this setting Netgear GA302T PHY does not
4301 * ??? send/receive packets...
4303 if ((tp->phy_id & TG3_PHY_ID_MASK) == TG3_PHY_ID_BCM5411 &&
4304 tp->pci_chip_rev_id == CHIPREV_ID_5700_ALTIMA) {
4305 tp->mi_mode |= MAC_MI_MODE_AUTO_POLL;
4306 tw32_f(MAC_MI_MODE, tp->mi_mode);
4310 tw32_f(MAC_MODE, tp->mac_mode);
4313 tg3_phy_eee_adjust(tp, current_link_up);
4315 if (tg3_flag(tp, USE_LINKCHG_REG)) {
4316 /* Polled via timer. */
4317 tw32_f(MAC_EVENT, 0);
4319 tw32_f(MAC_EVENT, MAC_EVENT_LNKSTATE_CHANGED);
4323 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 &&
4324 current_link_up == 1 &&
4325 tp->link_config.active_speed == SPEED_1000 &&
4326 (tg3_flag(tp, PCIX_MODE) || tg3_flag(tp, PCI_HIGH_SPEED))) {
4329 (MAC_STATUS_SYNC_CHANGED |
4330 MAC_STATUS_CFG_CHANGED));
4333 NIC_SRAM_FIRMWARE_MBOX,
4334 NIC_SRAM_FIRMWARE_MBOX_MAGIC2);
4337 /* Prevent send BD corruption. */
4338 if (tg3_flag(tp, CLKREQ_BUG)) {
4339 u16 oldlnkctl, newlnkctl;
4341 pci_read_config_word(tp->pdev,
4342 pci_pcie_cap(tp->pdev) + PCI_EXP_LNKCTL,
4344 if (tp->link_config.active_speed == SPEED_100 ||
4345 tp->link_config.active_speed == SPEED_10)
4346 newlnkctl = oldlnkctl & ~PCI_EXP_LNKCTL_CLKREQ_EN;
4348 newlnkctl = oldlnkctl | PCI_EXP_LNKCTL_CLKREQ_EN;
4349 if (newlnkctl != oldlnkctl)
4350 pci_write_config_word(tp->pdev,
4351 pci_pcie_cap(tp->pdev) +
4352 PCI_EXP_LNKCTL, newlnkctl);
4355 if (current_link_up != netif_carrier_ok(tp->dev)) {
4356 if (current_link_up)
4357 netif_carrier_on(tp->dev);
4359 netif_carrier_off(tp->dev);
4360 tg3_link_report(tp);
4366 struct tg3_fiber_aneginfo {
4368 #define ANEG_STATE_UNKNOWN 0
4369 #define ANEG_STATE_AN_ENABLE 1
4370 #define ANEG_STATE_RESTART_INIT 2
4371 #define ANEG_STATE_RESTART 3
4372 #define ANEG_STATE_DISABLE_LINK_OK 4
4373 #define ANEG_STATE_ABILITY_DETECT_INIT 5
4374 #define ANEG_STATE_ABILITY_DETECT 6
4375 #define ANEG_STATE_ACK_DETECT_INIT 7
4376 #define ANEG_STATE_ACK_DETECT 8
4377 #define ANEG_STATE_COMPLETE_ACK_INIT 9
4378 #define ANEG_STATE_COMPLETE_ACK 10
4379 #define ANEG_STATE_IDLE_DETECT_INIT 11
4380 #define ANEG_STATE_IDLE_DETECT 12
4381 #define ANEG_STATE_LINK_OK 13
4382 #define ANEG_STATE_NEXT_PAGE_WAIT_INIT 14
4383 #define ANEG_STATE_NEXT_PAGE_WAIT 15
4386 #define MR_AN_ENABLE 0x00000001
4387 #define MR_RESTART_AN 0x00000002
4388 #define MR_AN_COMPLETE 0x00000004
4389 #define MR_PAGE_RX 0x00000008
4390 #define MR_NP_LOADED 0x00000010
4391 #define MR_TOGGLE_TX 0x00000020
4392 #define MR_LP_ADV_FULL_DUPLEX 0x00000040
4393 #define MR_LP_ADV_HALF_DUPLEX 0x00000080
4394 #define MR_LP_ADV_SYM_PAUSE 0x00000100
4395 #define MR_LP_ADV_ASYM_PAUSE 0x00000200
4396 #define MR_LP_ADV_REMOTE_FAULT1 0x00000400
4397 #define MR_LP_ADV_REMOTE_FAULT2 0x00000800
4398 #define MR_LP_ADV_NEXT_PAGE 0x00001000
4399 #define MR_TOGGLE_RX 0x00002000
4400 #define MR_NP_RX 0x00004000
4402 #define MR_LINK_OK 0x80000000
4404 unsigned long link_time, cur_time;
4406 u32 ability_match_cfg;
4407 int ability_match_count;
4409 char ability_match, idle_match, ack_match;
4411 u32 txconfig, rxconfig;
4412 #define ANEG_CFG_NP 0x00000080
4413 #define ANEG_CFG_ACK 0x00000040
4414 #define ANEG_CFG_RF2 0x00000020
4415 #define ANEG_CFG_RF1 0x00000010
4416 #define ANEG_CFG_PS2 0x00000001
4417 #define ANEG_CFG_PS1 0x00008000
4418 #define ANEG_CFG_HD 0x00004000
4419 #define ANEG_CFG_FD 0x00002000
4420 #define ANEG_CFG_INVAL 0x00001f06
4425 #define ANEG_TIMER_ENAB 2
4426 #define ANEG_FAILED -1
4428 #define ANEG_STATE_SETTLE_TIME 10000
4430 static int tg3_fiber_aneg_smachine(struct tg3 *tp,
4431 struct tg3_fiber_aneginfo *ap)
4434 unsigned long delta;
4438 if (ap->state == ANEG_STATE_UNKNOWN) {
4442 ap->ability_match_cfg = 0;
4443 ap->ability_match_count = 0;
4444 ap->ability_match = 0;
4450 if (tr32(MAC_STATUS) & MAC_STATUS_RCVD_CFG) {
4451 rx_cfg_reg = tr32(MAC_RX_AUTO_NEG);
4453 if (rx_cfg_reg != ap->ability_match_cfg) {
4454 ap->ability_match_cfg = rx_cfg_reg;
4455 ap->ability_match = 0;
4456 ap->ability_match_count = 0;
4458 if (++ap->ability_match_count > 1) {
4459 ap->ability_match = 1;
4460 ap->ability_match_cfg = rx_cfg_reg;
4463 if (rx_cfg_reg & ANEG_CFG_ACK)
4471 ap->ability_match_cfg = 0;
4472 ap->ability_match_count = 0;
4473 ap->ability_match = 0;
4479 ap->rxconfig = rx_cfg_reg;
4482 switch (ap->state) {
4483 case ANEG_STATE_UNKNOWN:
4484 if (ap->flags & (MR_AN_ENABLE | MR_RESTART_AN))
4485 ap->state = ANEG_STATE_AN_ENABLE;
4488 case ANEG_STATE_AN_ENABLE:
4489 ap->flags &= ~(MR_AN_COMPLETE | MR_PAGE_RX);
4490 if (ap->flags & MR_AN_ENABLE) {
4493 ap->ability_match_cfg = 0;
4494 ap->ability_match_count = 0;
4495 ap->ability_match = 0;
4499 ap->state = ANEG_STATE_RESTART_INIT;
4501 ap->state = ANEG_STATE_DISABLE_LINK_OK;
4505 case ANEG_STATE_RESTART_INIT:
4506 ap->link_time = ap->cur_time;
4507 ap->flags &= ~(MR_NP_LOADED);
4509 tw32(MAC_TX_AUTO_NEG, 0);
4510 tp->mac_mode |= MAC_MODE_SEND_CONFIGS;
4511 tw32_f(MAC_MODE, tp->mac_mode);
4514 ret = ANEG_TIMER_ENAB;
4515 ap->state = ANEG_STATE_RESTART;
4518 case ANEG_STATE_RESTART:
4519 delta = ap->cur_time - ap->link_time;
4520 if (delta > ANEG_STATE_SETTLE_TIME)
4521 ap->state = ANEG_STATE_ABILITY_DETECT_INIT;
4523 ret = ANEG_TIMER_ENAB;
4526 case ANEG_STATE_DISABLE_LINK_OK:
4530 case ANEG_STATE_ABILITY_DETECT_INIT:
4531 ap->flags &= ~(MR_TOGGLE_TX);
4532 ap->txconfig = ANEG_CFG_FD;
4533 flowctrl = tg3_advert_flowctrl_1000X(tp->link_config.flowctrl);
4534 if (flowctrl & ADVERTISE_1000XPAUSE)
4535 ap->txconfig |= ANEG_CFG_PS1;
4536 if (flowctrl & ADVERTISE_1000XPSE_ASYM)
4537 ap->txconfig |= ANEG_CFG_PS2;
4538 tw32(MAC_TX_AUTO_NEG, ap->txconfig);
4539 tp->mac_mode |= MAC_MODE_SEND_CONFIGS;
4540 tw32_f(MAC_MODE, tp->mac_mode);
4543 ap->state = ANEG_STATE_ABILITY_DETECT;
4546 case ANEG_STATE_ABILITY_DETECT:
4547 if (ap->ability_match != 0 && ap->rxconfig != 0)
4548 ap->state = ANEG_STATE_ACK_DETECT_INIT;
4551 case ANEG_STATE_ACK_DETECT_INIT:
4552 ap->txconfig |= ANEG_CFG_ACK;
4553 tw32(MAC_TX_AUTO_NEG, ap->txconfig);
4554 tp->mac_mode |= MAC_MODE_SEND_CONFIGS;
4555 tw32_f(MAC_MODE, tp->mac_mode);
4558 ap->state = ANEG_STATE_ACK_DETECT;
4561 case ANEG_STATE_ACK_DETECT:
4562 if (ap->ack_match != 0) {
4563 if ((ap->rxconfig & ~ANEG_CFG_ACK) ==
4564 (ap->ability_match_cfg & ~ANEG_CFG_ACK)) {
4565 ap->state = ANEG_STATE_COMPLETE_ACK_INIT;
4567 ap->state = ANEG_STATE_AN_ENABLE;
4569 } else if (ap->ability_match != 0 &&
4570 ap->rxconfig == 0) {
4571 ap->state = ANEG_STATE_AN_ENABLE;
4575 case ANEG_STATE_COMPLETE_ACK_INIT:
4576 if (ap->rxconfig & ANEG_CFG_INVAL) {
4580 ap->flags &= ~(MR_LP_ADV_FULL_DUPLEX |
4581 MR_LP_ADV_HALF_DUPLEX |
4582 MR_LP_ADV_SYM_PAUSE |
4583 MR_LP_ADV_ASYM_PAUSE |
4584 MR_LP_ADV_REMOTE_FAULT1 |
4585 MR_LP_ADV_REMOTE_FAULT2 |
4586 MR_LP_ADV_NEXT_PAGE |
4589 if (ap->rxconfig & ANEG_CFG_FD)
4590 ap->flags |= MR_LP_ADV_FULL_DUPLEX;
4591 if (ap->rxconfig & ANEG_CFG_HD)
4592 ap->flags |= MR_LP_ADV_HALF_DUPLEX;
4593 if (ap->rxconfig & ANEG_CFG_PS1)
4594 ap->flags |= MR_LP_ADV_SYM_PAUSE;
4595 if (ap->rxconfig & ANEG_CFG_PS2)
4596 ap->flags |= MR_LP_ADV_ASYM_PAUSE;
4597 if (ap->rxconfig & ANEG_CFG_RF1)
4598 ap->flags |= MR_LP_ADV_REMOTE_FAULT1;
4599 if (ap->rxconfig & ANEG_CFG_RF2)
4600 ap->flags |= MR_LP_ADV_REMOTE_FAULT2;
4601 if (ap->rxconfig & ANEG_CFG_NP)
4602 ap->flags |= MR_LP_ADV_NEXT_PAGE;
4604 ap->link_time = ap->cur_time;
4606 ap->flags ^= (MR_TOGGLE_TX);
4607 if (ap->rxconfig & 0x0008)
4608 ap->flags |= MR_TOGGLE_RX;
4609 if (ap->rxconfig & ANEG_CFG_NP)
4610 ap->flags |= MR_NP_RX;
4611 ap->flags |= MR_PAGE_RX;
4613 ap->state = ANEG_STATE_COMPLETE_ACK;
4614 ret = ANEG_TIMER_ENAB;
4617 case ANEG_STATE_COMPLETE_ACK:
4618 if (ap->ability_match != 0 &&
4619 ap->rxconfig == 0) {
4620 ap->state = ANEG_STATE_AN_ENABLE;
4623 delta = ap->cur_time - ap->link_time;
4624 if (delta > ANEG_STATE_SETTLE_TIME) {
4625 if (!(ap->flags & (MR_LP_ADV_NEXT_PAGE))) {
4626 ap->state = ANEG_STATE_IDLE_DETECT_INIT;
4628 if ((ap->txconfig & ANEG_CFG_NP) == 0 &&
4629 !(ap->flags & MR_NP_RX)) {
4630 ap->state = ANEG_STATE_IDLE_DETECT_INIT;
4638 case ANEG_STATE_IDLE_DETECT_INIT:
4639 ap->link_time = ap->cur_time;
4640 tp->mac_mode &= ~MAC_MODE_SEND_CONFIGS;
4641 tw32_f(MAC_MODE, tp->mac_mode);
4644 ap->state = ANEG_STATE_IDLE_DETECT;
4645 ret = ANEG_TIMER_ENAB;
4648 case ANEG_STATE_IDLE_DETECT:
4649 if (ap->ability_match != 0 &&
4650 ap->rxconfig == 0) {
4651 ap->state = ANEG_STATE_AN_ENABLE;
4654 delta = ap->cur_time - ap->link_time;
4655 if (delta > ANEG_STATE_SETTLE_TIME) {
4656 /* XXX another gem from the Broadcom driver :( */
4657 ap->state = ANEG_STATE_LINK_OK;
4661 case ANEG_STATE_LINK_OK:
4662 ap->flags |= (MR_AN_COMPLETE | MR_LINK_OK);
4666 case ANEG_STATE_NEXT_PAGE_WAIT_INIT:
4667 /* ??? unimplemented */
4670 case ANEG_STATE_NEXT_PAGE_WAIT:
4671 /* ??? unimplemented */
4682 static int fiber_autoneg(struct tg3 *tp, u32 *txflags, u32 *rxflags)
4685 struct tg3_fiber_aneginfo aninfo;
4686 int status = ANEG_FAILED;
4690 tw32_f(MAC_TX_AUTO_NEG, 0);
4692 tmp = tp->mac_mode & ~MAC_MODE_PORT_MODE_MASK;
4693 tw32_f(MAC_MODE, tmp | MAC_MODE_PORT_MODE_GMII);
4696 tw32_f(MAC_MODE, tp->mac_mode | MAC_MODE_SEND_CONFIGS);
4699 memset(&aninfo, 0, sizeof(aninfo));
4700 aninfo.flags |= MR_AN_ENABLE;
4701 aninfo.state = ANEG_STATE_UNKNOWN;
4702 aninfo.cur_time = 0;
4704 while (++tick < 195000) {
4705 status = tg3_fiber_aneg_smachine(tp, &aninfo);
4706 if (status == ANEG_DONE || status == ANEG_FAILED)
4712 tp->mac_mode &= ~MAC_MODE_SEND_CONFIGS;
4713 tw32_f(MAC_MODE, tp->mac_mode);
4716 *txflags = aninfo.txconfig;
4717 *rxflags = aninfo.flags;
4719 if (status == ANEG_DONE &&
4720 (aninfo.flags & (MR_AN_COMPLETE | MR_LINK_OK |
4721 MR_LP_ADV_FULL_DUPLEX)))
4727 static void tg3_init_bcm8002(struct tg3 *tp)
4729 u32 mac_status = tr32(MAC_STATUS);
4732 /* Reset when initting first time or we have a link. */
4733 if (tg3_flag(tp, INIT_COMPLETE) &&
4734 !(mac_status & MAC_STATUS_PCS_SYNCED))
4737 /* Set PLL lock range. */
4738 tg3_writephy(tp, 0x16, 0x8007);
4741 tg3_writephy(tp, MII_BMCR, BMCR_RESET);
4743 /* Wait for reset to complete. */
4744 /* XXX schedule_timeout() ... */
4745 for (i = 0; i < 500; i++)
4748 /* Config mode; select PMA/Ch 1 regs. */
4749 tg3_writephy(tp, 0x10, 0x8411);
4751 /* Enable auto-lock and comdet, select txclk for tx. */
4752 tg3_writephy(tp, 0x11, 0x0a10);
4754 tg3_writephy(tp, 0x18, 0x00a0);
4755 tg3_writephy(tp, 0x16, 0x41ff);
4757 /* Assert and deassert POR. */
4758 tg3_writephy(tp, 0x13, 0x0400);
4760 tg3_writephy(tp, 0x13, 0x0000);
4762 tg3_writephy(tp, 0x11, 0x0a50);
4764 tg3_writephy(tp, 0x11, 0x0a10);
4766 /* Wait for signal to stabilize */
4767 /* XXX schedule_timeout() ... */
4768 for (i = 0; i < 15000; i++)
4771 /* Deselect the channel register so we can read the PHYID
4774 tg3_writephy(tp, 0x10, 0x8011);
4777 static int tg3_setup_fiber_hw_autoneg(struct tg3 *tp, u32 mac_status)
4780 u32 sg_dig_ctrl, sg_dig_status;
4781 u32 serdes_cfg, expected_sg_dig_ctrl;
4782 int workaround, port_a;
4783 int current_link_up;
4786 expected_sg_dig_ctrl = 0;
4789 current_link_up = 0;
4791 if (tp->pci_chip_rev_id != CHIPREV_ID_5704_A0 &&
4792 tp->pci_chip_rev_id != CHIPREV_ID_5704_A1) {
4794 if (tr32(TG3PCI_DUAL_MAC_CTRL) & DUAL_MAC_CTRL_ID)
4797 /* preserve bits 0-11,13,14 for signal pre-emphasis */
4798 /* preserve bits 20-23 for voltage regulator */
4799 serdes_cfg = tr32(MAC_SERDES_CFG) & 0x00f06fff;
4802 sg_dig_ctrl = tr32(SG_DIG_CTRL);
4804 if (tp->link_config.autoneg != AUTONEG_ENABLE) {
4805 if (sg_dig_ctrl & SG_DIG_USING_HW_AUTONEG) {
4807 u32 val = serdes_cfg;
4813 tw32_f(MAC_SERDES_CFG, val);
4816 tw32_f(SG_DIG_CTRL, SG_DIG_COMMON_SETUP);
4818 if (mac_status & MAC_STATUS_PCS_SYNCED) {
4819 tg3_setup_flow_control(tp, 0, 0);
4820 current_link_up = 1;
4825 /* Want auto-negotiation. */
4826 expected_sg_dig_ctrl = SG_DIG_USING_HW_AUTONEG | SG_DIG_COMMON_SETUP;
4828 flowctrl = tg3_advert_flowctrl_1000X(tp->link_config.flowctrl);
4829 if (flowctrl & ADVERTISE_1000XPAUSE)
4830 expected_sg_dig_ctrl |= SG_DIG_PAUSE_CAP;
4831 if (flowctrl & ADVERTISE_1000XPSE_ASYM)
4832 expected_sg_dig_ctrl |= SG_DIG_ASYM_PAUSE;
4834 if (sg_dig_ctrl != expected_sg_dig_ctrl) {
4835 if ((tp->phy_flags & TG3_PHYFLG_PARALLEL_DETECT) &&
4836 tp->serdes_counter &&
4837 ((mac_status & (MAC_STATUS_PCS_SYNCED |
4838 MAC_STATUS_RCVD_CFG)) ==
4839 MAC_STATUS_PCS_SYNCED)) {
4840 tp->serdes_counter--;
4841 current_link_up = 1;
4846 tw32_f(MAC_SERDES_CFG, serdes_cfg | 0xc011000);
4847 tw32_f(SG_DIG_CTRL, expected_sg_dig_ctrl | SG_DIG_SOFT_RESET);
4849 tw32_f(SG_DIG_CTRL, expected_sg_dig_ctrl);
4851 tp->serdes_counter = SERDES_AN_TIMEOUT_5704S;
4852 tp->phy_flags &= ~TG3_PHYFLG_PARALLEL_DETECT;
4853 } else if (mac_status & (MAC_STATUS_PCS_SYNCED |
4854 MAC_STATUS_SIGNAL_DET)) {
4855 sg_dig_status = tr32(SG_DIG_STATUS);
4856 mac_status = tr32(MAC_STATUS);
4858 if ((sg_dig_status & SG_DIG_AUTONEG_COMPLETE) &&
4859 (mac_status & MAC_STATUS_PCS_SYNCED)) {
4860 u32 local_adv = 0, remote_adv = 0;
4862 if (sg_dig_ctrl & SG_DIG_PAUSE_CAP)
4863 local_adv |= ADVERTISE_1000XPAUSE;
4864 if (sg_dig_ctrl & SG_DIG_ASYM_PAUSE)
4865 local_adv |= ADVERTISE_1000XPSE_ASYM;
4867 if (sg_dig_status & SG_DIG_PARTNER_PAUSE_CAPABLE)
4868 remote_adv |= LPA_1000XPAUSE;
4869 if (sg_dig_status & SG_DIG_PARTNER_ASYM_PAUSE)
4870 remote_adv |= LPA_1000XPAUSE_ASYM;
4872 tp->link_config.rmt_adv =
4873 mii_adv_to_ethtool_adv_x(remote_adv);
4875 tg3_setup_flow_control(tp, local_adv, remote_adv);
4876 current_link_up = 1;
4877 tp->serdes_counter = 0;
4878 tp->phy_flags &= ~TG3_PHYFLG_PARALLEL_DETECT;
4879 } else if (!(sg_dig_status & SG_DIG_AUTONEG_COMPLETE)) {
4880 if (tp->serdes_counter)
4881 tp->serdes_counter--;
4884 u32 val = serdes_cfg;
4891 tw32_f(MAC_SERDES_CFG, val);
4894 tw32_f(SG_DIG_CTRL, SG_DIG_COMMON_SETUP);
4897 /* Link parallel detection - link is up */
4898 /* only if we have PCS_SYNC and not */
4899 /* receiving config code words */
4900 mac_status = tr32(MAC_STATUS);
4901 if ((mac_status & MAC_STATUS_PCS_SYNCED) &&
4902 !(mac_status & MAC_STATUS_RCVD_CFG)) {
4903 tg3_setup_flow_control(tp, 0, 0);
4904 current_link_up = 1;
4906 TG3_PHYFLG_PARALLEL_DETECT;
4907 tp->serdes_counter =
4908 SERDES_PARALLEL_DET_TIMEOUT;
4910 goto restart_autoneg;
4914 tp->serdes_counter = SERDES_AN_TIMEOUT_5704S;
4915 tp->phy_flags &= ~TG3_PHYFLG_PARALLEL_DETECT;
4919 return current_link_up;
4922 static int tg3_setup_fiber_by_hand(struct tg3 *tp, u32 mac_status)
4924 int current_link_up = 0;
4926 if (!(mac_status & MAC_STATUS_PCS_SYNCED))
4929 if (tp->link_config.autoneg == AUTONEG_ENABLE) {
4930 u32 txflags, rxflags;
4933 if (fiber_autoneg(tp, &txflags, &rxflags)) {
4934 u32 local_adv = 0, remote_adv = 0;
4936 if (txflags & ANEG_CFG_PS1)
4937 local_adv |= ADVERTISE_1000XPAUSE;
4938 if (txflags & ANEG_CFG_PS2)
4939 local_adv |= ADVERTISE_1000XPSE_ASYM;
4941 if (rxflags & MR_LP_ADV_SYM_PAUSE)
4942 remote_adv |= LPA_1000XPAUSE;
4943 if (rxflags & MR_LP_ADV_ASYM_PAUSE)
4944 remote_adv |= LPA_1000XPAUSE_ASYM;
4946 tp->link_config.rmt_adv =
4947 mii_adv_to_ethtool_adv_x(remote_adv);
4949 tg3_setup_flow_control(tp, local_adv, remote_adv);
4951 current_link_up = 1;
4953 for (i = 0; i < 30; i++) {
4956 (MAC_STATUS_SYNC_CHANGED |
4957 MAC_STATUS_CFG_CHANGED));
4959 if ((tr32(MAC_STATUS) &
4960 (MAC_STATUS_SYNC_CHANGED |
4961 MAC_STATUS_CFG_CHANGED)) == 0)
4965 mac_status = tr32(MAC_STATUS);
4966 if (current_link_up == 0 &&
4967 (mac_status & MAC_STATUS_PCS_SYNCED) &&
4968 !(mac_status & MAC_STATUS_RCVD_CFG))
4969 current_link_up = 1;
4971 tg3_setup_flow_control(tp, 0, 0);
4973 /* Forcing 1000FD link up. */
4974 current_link_up = 1;
4976 tw32_f(MAC_MODE, (tp->mac_mode | MAC_MODE_SEND_CONFIGS));
4979 tw32_f(MAC_MODE, tp->mac_mode);
4984 return current_link_up;
4987 static int tg3_setup_fiber_phy(struct tg3 *tp, int force_reset)
4990 u16 orig_active_speed;
4991 u8 orig_active_duplex;
4993 int current_link_up;
4996 orig_pause_cfg = tp->link_config.active_flowctrl;
4997 orig_active_speed = tp->link_config.active_speed;
4998 orig_active_duplex = tp->link_config.active_duplex;
5000 if (!tg3_flag(tp, HW_AUTONEG) &&
5001 netif_carrier_ok(tp->dev) &&
5002 tg3_flag(tp, INIT_COMPLETE)) {
5003 mac_status = tr32(MAC_STATUS);
5004 mac_status &= (MAC_STATUS_PCS_SYNCED |
5005 MAC_STATUS_SIGNAL_DET |
5006 MAC_STATUS_CFG_CHANGED |
5007 MAC_STATUS_RCVD_CFG);
5008 if (mac_status == (MAC_STATUS_PCS_SYNCED |
5009 MAC_STATUS_SIGNAL_DET)) {
5010 tw32_f(MAC_STATUS, (MAC_STATUS_SYNC_CHANGED |
5011 MAC_STATUS_CFG_CHANGED));
5016 tw32_f(MAC_TX_AUTO_NEG, 0);
5018 tp->mac_mode &= ~(MAC_MODE_PORT_MODE_MASK | MAC_MODE_HALF_DUPLEX);
5019 tp->mac_mode |= MAC_MODE_PORT_MODE_TBI;
5020 tw32_f(MAC_MODE, tp->mac_mode);
5023 if (tp->phy_id == TG3_PHY_ID_BCM8002)
5024 tg3_init_bcm8002(tp);
5026 /* Enable link change event even when serdes polling. */
5027 tw32_f(MAC_EVENT, MAC_EVENT_LNKSTATE_CHANGED);
5030 current_link_up = 0;
5031 tp->link_config.rmt_adv = 0;
5032 mac_status = tr32(MAC_STATUS);
5034 if (tg3_flag(tp, HW_AUTONEG))
5035 current_link_up = tg3_setup_fiber_hw_autoneg(tp, mac_status);
5037 current_link_up = tg3_setup_fiber_by_hand(tp, mac_status);
5039 tp->napi[0].hw_status->status =
5040 (SD_STATUS_UPDATED |
5041 (tp->napi[0].hw_status->status & ~SD_STATUS_LINK_CHG));
5043 for (i = 0; i < 100; i++) {
5044 tw32_f(MAC_STATUS, (MAC_STATUS_SYNC_CHANGED |
5045 MAC_STATUS_CFG_CHANGED));
5047 if ((tr32(MAC_STATUS) & (MAC_STATUS_SYNC_CHANGED |
5048 MAC_STATUS_CFG_CHANGED |
5049 MAC_STATUS_LNKSTATE_CHANGED)) == 0)
5053 mac_status = tr32(MAC_STATUS);
5054 if ((mac_status & MAC_STATUS_PCS_SYNCED) == 0) {
5055 current_link_up = 0;
5056 if (tp->link_config.autoneg == AUTONEG_ENABLE &&
5057 tp->serdes_counter == 0) {
5058 tw32_f(MAC_MODE, (tp->mac_mode |
5059 MAC_MODE_SEND_CONFIGS));
5061 tw32_f(MAC_MODE, tp->mac_mode);
5065 if (current_link_up == 1) {
5066 tp->link_config.active_speed = SPEED_1000;
5067 tp->link_config.active_duplex = DUPLEX_FULL;
5068 tw32(MAC_LED_CTRL, (tp->led_ctrl |
5069 LED_CTRL_LNKLED_OVERRIDE |
5070 LED_CTRL_1000MBPS_ON));
5072 tp->link_config.active_speed = SPEED_UNKNOWN;
5073 tp->link_config.active_duplex = DUPLEX_UNKNOWN;
5074 tw32(MAC_LED_CTRL, (tp->led_ctrl |
5075 LED_CTRL_LNKLED_OVERRIDE |
5076 LED_CTRL_TRAFFIC_OVERRIDE));
5079 if (current_link_up != netif_carrier_ok(tp->dev)) {
5080 if (current_link_up)
5081 netif_carrier_on(tp->dev);
5083 netif_carrier_off(tp->dev);
5084 tg3_link_report(tp);
5086 u32 now_pause_cfg = tp->link_config.active_flowctrl;
5087 if (orig_pause_cfg != now_pause_cfg ||
5088 orig_active_speed != tp->link_config.active_speed ||
5089 orig_active_duplex != tp->link_config.active_duplex)
5090 tg3_link_report(tp);
5096 static int tg3_setup_fiber_mii_phy(struct tg3 *tp, int force_reset)
5098 int current_link_up, err = 0;
5102 u32 local_adv, remote_adv;
5104 tp->mac_mode |= MAC_MODE_PORT_MODE_GMII;
5105 tw32_f(MAC_MODE, tp->mac_mode);
5111 (MAC_STATUS_SYNC_CHANGED |
5112 MAC_STATUS_CFG_CHANGED |
5113 MAC_STATUS_MI_COMPLETION |
5114 MAC_STATUS_LNKSTATE_CHANGED));
5120 current_link_up = 0;
5121 current_speed = SPEED_UNKNOWN;
5122 current_duplex = DUPLEX_UNKNOWN;
5123 tp->link_config.rmt_adv = 0;
5125 err |= tg3_readphy(tp, MII_BMSR, &bmsr);
5126 err |= tg3_readphy(tp, MII_BMSR, &bmsr);
5127 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5714) {
5128 if (tr32(MAC_TX_STATUS) & TX_STATUS_LINK_UP)
5129 bmsr |= BMSR_LSTATUS;
5131 bmsr &= ~BMSR_LSTATUS;
5134 err |= tg3_readphy(tp, MII_BMCR, &bmcr);
5136 if ((tp->link_config.autoneg == AUTONEG_ENABLE) && !force_reset &&
5137 (tp->phy_flags & TG3_PHYFLG_PARALLEL_DETECT)) {
5138 /* do nothing, just check for link up at the end */
5139 } else if (tp->link_config.autoneg == AUTONEG_ENABLE) {
5142 err |= tg3_readphy(tp, MII_ADVERTISE, &adv);
5143 newadv = adv & ~(ADVERTISE_1000XFULL | ADVERTISE_1000XHALF |
5144 ADVERTISE_1000XPAUSE |
5145 ADVERTISE_1000XPSE_ASYM |
5148 newadv |= tg3_advert_flowctrl_1000X(tp->link_config.flowctrl);
5149 newadv |= ethtool_adv_to_mii_adv_x(tp->link_config.advertising);
5151 if ((newadv != adv) || !(bmcr & BMCR_ANENABLE)) {
5152 tg3_writephy(tp, MII_ADVERTISE, newadv);
5153 bmcr |= BMCR_ANENABLE | BMCR_ANRESTART;
5154 tg3_writephy(tp, MII_BMCR, bmcr);
5156 tw32_f(MAC_EVENT, MAC_EVENT_LNKSTATE_CHANGED);
5157 tp->serdes_counter = SERDES_AN_TIMEOUT_5714S;
5158 tp->phy_flags &= ~TG3_PHYFLG_PARALLEL_DETECT;
5165 bmcr &= ~BMCR_SPEED1000;
5166 new_bmcr = bmcr & ~(BMCR_ANENABLE | BMCR_FULLDPLX);
5168 if (tp->link_config.duplex == DUPLEX_FULL)
5169 new_bmcr |= BMCR_FULLDPLX;
5171 if (new_bmcr != bmcr) {
5172 /* BMCR_SPEED1000 is a reserved bit that needs
5173 * to be set on write.
5175 new_bmcr |= BMCR_SPEED1000;
5177 /* Force a linkdown */
5178 if (netif_carrier_ok(tp->dev)) {
5181 err |= tg3_readphy(tp, MII_ADVERTISE, &adv);
5182 adv &= ~(ADVERTISE_1000XFULL |
5183 ADVERTISE_1000XHALF |
5185 tg3_writephy(tp, MII_ADVERTISE, adv);
5186 tg3_writephy(tp, MII_BMCR, bmcr |
5190 netif_carrier_off(tp->dev);
5192 tg3_writephy(tp, MII_BMCR, new_bmcr);
5194 err |= tg3_readphy(tp, MII_BMSR, &bmsr);
5195 err |= tg3_readphy(tp, MII_BMSR, &bmsr);
5196 if (GET_ASIC_REV(tp->pci_chip_rev_id) ==
5198 if (tr32(MAC_TX_STATUS) & TX_STATUS_LINK_UP)
5199 bmsr |= BMSR_LSTATUS;
5201 bmsr &= ~BMSR_LSTATUS;
5203 tp->phy_flags &= ~TG3_PHYFLG_PARALLEL_DETECT;
5207 if (bmsr & BMSR_LSTATUS) {
5208 current_speed = SPEED_1000;
5209 current_link_up = 1;
5210 if (bmcr & BMCR_FULLDPLX)
5211 current_duplex = DUPLEX_FULL;
5213 current_duplex = DUPLEX_HALF;
5218 if (bmcr & BMCR_ANENABLE) {
5221 err |= tg3_readphy(tp, MII_ADVERTISE, &local_adv);
5222 err |= tg3_readphy(tp, MII_LPA, &remote_adv);
5223 common = local_adv & remote_adv;
5224 if (common & (ADVERTISE_1000XHALF |
5225 ADVERTISE_1000XFULL)) {
5226 if (common & ADVERTISE_1000XFULL)
5227 current_duplex = DUPLEX_FULL;
5229 current_duplex = DUPLEX_HALF;
5231 tp->link_config.rmt_adv =
5232 mii_adv_to_ethtool_adv_x(remote_adv);
5233 } else if (!tg3_flag(tp, 5780_CLASS)) {
5234 /* Link is up via parallel detect */
5236 current_link_up = 0;
5241 if (current_link_up == 1 && current_duplex == DUPLEX_FULL)
5242 tg3_setup_flow_control(tp, local_adv, remote_adv);
5244 tp->mac_mode &= ~MAC_MODE_HALF_DUPLEX;
5245 if (tp->link_config.active_duplex == DUPLEX_HALF)
5246 tp->mac_mode |= MAC_MODE_HALF_DUPLEX;
5248 tw32_f(MAC_MODE, tp->mac_mode);
5251 tw32_f(MAC_EVENT, MAC_EVENT_LNKSTATE_CHANGED);
5253 tp->link_config.active_speed = current_speed;
5254 tp->link_config.active_duplex = current_duplex;
5256 if (current_link_up != netif_carrier_ok(tp->dev)) {
5257 if (current_link_up)
5258 netif_carrier_on(tp->dev);
5260 netif_carrier_off(tp->dev);
5261 tp->phy_flags &= ~TG3_PHYFLG_PARALLEL_DETECT;
5263 tg3_link_report(tp);
5268 static void tg3_serdes_parallel_detect(struct tg3 *tp)
5270 if (tp->serdes_counter) {
5271 /* Give autoneg time to complete. */
5272 tp->serdes_counter--;
5276 if (!netif_carrier_ok(tp->dev) &&
5277 (tp->link_config.autoneg == AUTONEG_ENABLE)) {
5280 tg3_readphy(tp, MII_BMCR, &bmcr);
5281 if (bmcr & BMCR_ANENABLE) {
5284 /* Select shadow register 0x1f */
5285 tg3_writephy(tp, MII_TG3_MISC_SHDW, 0x7c00);
5286 tg3_readphy(tp, MII_TG3_MISC_SHDW, &phy1);
5288 /* Select expansion interrupt status register */
5289 tg3_writephy(tp, MII_TG3_DSP_ADDRESS,
5290 MII_TG3_DSP_EXP1_INT_STAT);
5291 tg3_readphy(tp, MII_TG3_DSP_RW_PORT, &phy2);
5292 tg3_readphy(tp, MII_TG3_DSP_RW_PORT, &phy2);
5294 if ((phy1 & 0x10) && !(phy2 & 0x20)) {
5295 /* We have signal detect and not receiving
5296 * config code words, link is up by parallel
5300 bmcr &= ~BMCR_ANENABLE;
5301 bmcr |= BMCR_SPEED1000 | BMCR_FULLDPLX;
5302 tg3_writephy(tp, MII_BMCR, bmcr);
5303 tp->phy_flags |= TG3_PHYFLG_PARALLEL_DETECT;
5306 } else if (netif_carrier_ok(tp->dev) &&
5307 (tp->link_config.autoneg == AUTONEG_ENABLE) &&
5308 (tp->phy_flags & TG3_PHYFLG_PARALLEL_DETECT)) {
5311 /* Select expansion interrupt status register */
5312 tg3_writephy(tp, MII_TG3_DSP_ADDRESS,
5313 MII_TG3_DSP_EXP1_INT_STAT);
5314 tg3_readphy(tp, MII_TG3_DSP_RW_PORT, &phy2);
5318 /* Config code words received, turn on autoneg. */
5319 tg3_readphy(tp, MII_BMCR, &bmcr);
5320 tg3_writephy(tp, MII_BMCR, bmcr | BMCR_ANENABLE);
5322 tp->phy_flags &= ~TG3_PHYFLG_PARALLEL_DETECT;
5328 static int tg3_setup_phy(struct tg3 *tp, int force_reset)
5333 if (tp->phy_flags & TG3_PHYFLG_PHY_SERDES)
5334 err = tg3_setup_fiber_phy(tp, force_reset);
5335 else if (tp->phy_flags & TG3_PHYFLG_MII_SERDES)
5336 err = tg3_setup_fiber_mii_phy(tp, force_reset);
5338 err = tg3_setup_copper_phy(tp, force_reset);
5340 if (GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5784_AX) {
5343 val = tr32(TG3_CPMU_CLCK_STAT) & CPMU_CLCK_STAT_MAC_CLCK_MASK;
5344 if (val == CPMU_CLCK_STAT_MAC_CLCK_62_5)
5346 else if (val == CPMU_CLCK_STAT_MAC_CLCK_6_25)
5351 val = tr32(GRC_MISC_CFG) & ~GRC_MISC_CFG_PRESCALAR_MASK;
5352 val |= (scale << GRC_MISC_CFG_PRESCALAR_SHIFT);
5353 tw32(GRC_MISC_CFG, val);
5356 val = (2 << TX_LENGTHS_IPG_CRS_SHIFT) |
5357 (6 << TX_LENGTHS_IPG_SHIFT);
5358 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5720)
5359 val |= tr32(MAC_TX_LENGTHS) &
5360 (TX_LENGTHS_JMB_FRM_LEN_MSK |
5361 TX_LENGTHS_CNT_DWN_VAL_MSK);
5363 if (tp->link_config.active_speed == SPEED_1000 &&
5364 tp->link_config.active_duplex == DUPLEX_HALF)
5365 tw32(MAC_TX_LENGTHS, val |
5366 (0xff << TX_LENGTHS_SLOT_TIME_SHIFT));
5368 tw32(MAC_TX_LENGTHS, val |
5369 (32 << TX_LENGTHS_SLOT_TIME_SHIFT));
5371 if (!tg3_flag(tp, 5705_PLUS)) {
5372 if (netif_carrier_ok(tp->dev)) {
5373 tw32(HOSTCC_STAT_COAL_TICKS,
5374 tp->coal.stats_block_coalesce_usecs);
5376 tw32(HOSTCC_STAT_COAL_TICKS, 0);
5380 if (tg3_flag(tp, ASPM_WORKAROUND)) {
5381 val = tr32(PCIE_PWR_MGMT_THRESH);
5382 if (!netif_carrier_ok(tp->dev))
5383 val = (val & ~PCIE_PWR_MGMT_L1_THRESH_MSK) |
5386 val |= PCIE_PWR_MGMT_L1_THRESH_MSK;
5387 tw32(PCIE_PWR_MGMT_THRESH, val);
5393 static inline int tg3_irq_sync(struct tg3 *tp)
5395 return tp->irq_sync;
5398 static inline void tg3_rd32_loop(struct tg3 *tp, u32 *dst, u32 off, u32 len)
5402 dst = (u32 *)((u8 *)dst + off);
5403 for (i = 0; i < len; i += sizeof(u32))
5404 *dst++ = tr32(off + i);
5407 static void tg3_dump_legacy_regs(struct tg3 *tp, u32 *regs)
5409 tg3_rd32_loop(tp, regs, TG3PCI_VENDOR, 0xb0);
5410 tg3_rd32_loop(tp, regs, MAILBOX_INTERRUPT_0, 0x200);
5411 tg3_rd32_loop(tp, regs, MAC_MODE, 0x4f0);
5412 tg3_rd32_loop(tp, regs, SNDDATAI_MODE, 0xe0);
5413 tg3_rd32_loop(tp, regs, SNDDATAC_MODE, 0x04);
5414 tg3_rd32_loop(tp, regs, SNDBDS_MODE, 0x80);
5415 tg3_rd32_loop(tp, regs, SNDBDI_MODE, 0x48);
5416 tg3_rd32_loop(tp, regs, SNDBDC_MODE, 0x04);
5417 tg3_rd32_loop(tp, regs, RCVLPC_MODE, 0x20);
5418 tg3_rd32_loop(tp, regs, RCVLPC_SELLST_BASE, 0x15c);
5419 tg3_rd32_loop(tp, regs, RCVDBDI_MODE, 0x0c);
5420 tg3_rd32_loop(tp, regs, RCVDBDI_JUMBO_BD, 0x3c);
5421 tg3_rd32_loop(tp, regs, RCVDBDI_BD_PROD_IDX_0, 0x44);
5422 tg3_rd32_loop(tp, regs, RCVDCC_MODE, 0x04);
5423 tg3_rd32_loop(tp, regs, RCVBDI_MODE, 0x20);
5424 tg3_rd32_loop(tp, regs, RCVCC_MODE, 0x14);
5425 tg3_rd32_loop(tp, regs, RCVLSC_MODE, 0x08);
5426 tg3_rd32_loop(tp, regs, MBFREE_MODE, 0x08);
5427 tg3_rd32_loop(tp, regs, HOSTCC_MODE, 0x100);
5429 if (tg3_flag(tp, SUPPORT_MSIX))
5430 tg3_rd32_loop(tp, regs, HOSTCC_RXCOL_TICKS_VEC1, 0x180);
5432 tg3_rd32_loop(tp, regs, MEMARB_MODE, 0x10);
5433 tg3_rd32_loop(tp, regs, BUFMGR_MODE, 0x58);
5434 tg3_rd32_loop(tp, regs, RDMAC_MODE, 0x08);
5435 tg3_rd32_loop(tp, regs, WDMAC_MODE, 0x08);
5436 tg3_rd32_loop(tp, regs, RX_CPU_MODE, 0x04);
5437 tg3_rd32_loop(tp, regs, RX_CPU_STATE, 0x04);
5438 tg3_rd32_loop(tp, regs, RX_CPU_PGMCTR, 0x04);
5439 tg3_rd32_loop(tp, regs, RX_CPU_HWBKPT, 0x04);
5441 if (!tg3_flag(tp, 5705_PLUS)) {
5442 tg3_rd32_loop(tp, regs, TX_CPU_MODE, 0x04);
5443 tg3_rd32_loop(tp, regs, TX_CPU_STATE, 0x04);
5444 tg3_rd32_loop(tp, regs, TX_CPU_PGMCTR, 0x04);
5447 tg3_rd32_loop(tp, regs, GRCMBOX_INTERRUPT_0, 0x110);
5448 tg3_rd32_loop(tp, regs, FTQ_RESET, 0x120);
5449 tg3_rd32_loop(tp, regs, MSGINT_MODE, 0x0c);
5450 tg3_rd32_loop(tp, regs, DMAC_MODE, 0x04);
5451 tg3_rd32_loop(tp, regs, GRC_MODE, 0x4c);
5453 if (tg3_flag(tp, NVRAM))
5454 tg3_rd32_loop(tp, regs, NVRAM_CMD, 0x24);
5457 static void tg3_dump_state(struct tg3 *tp)
5462 regs = kzalloc(TG3_REG_BLK_SIZE, GFP_ATOMIC);
5464 netdev_err(tp->dev, "Failed allocating register dump buffer\n");
5468 if (tg3_flag(tp, PCI_EXPRESS)) {
5469 /* Read up to but not including private PCI registers */
5470 for (i = 0; i < TG3_PCIE_TLDLPL_PORT; i += sizeof(u32))
5471 regs[i / sizeof(u32)] = tr32(i);
5473 tg3_dump_legacy_regs(tp, regs);
5475 for (i = 0; i < TG3_REG_BLK_SIZE / sizeof(u32); i += 4) {
5476 if (!regs[i + 0] && !regs[i + 1] &&
5477 !regs[i + 2] && !regs[i + 3])
5480 netdev_err(tp->dev, "0x%08x: 0x%08x, 0x%08x, 0x%08x, 0x%08x\n",
5482 regs[i + 0], regs[i + 1], regs[i + 2], regs[i + 3]);
5487 for (i = 0; i < tp->irq_cnt; i++) {
5488 struct tg3_napi *tnapi = &tp->napi[i];
5490 /* SW status block */
5492 "%d: Host status block [%08x:%08x:(%04x:%04x:%04x):(%04x:%04x)]\n",
5494 tnapi->hw_status->status,
5495 tnapi->hw_status->status_tag,
5496 tnapi->hw_status->rx_jumbo_consumer,
5497 tnapi->hw_status->rx_consumer,
5498 tnapi->hw_status->rx_mini_consumer,
5499 tnapi->hw_status->idx[0].rx_producer,
5500 tnapi->hw_status->idx[0].tx_consumer);
5503 "%d: NAPI info [%08x:%08x:(%04x:%04x:%04x):%04x:(%04x:%04x:%04x:%04x)]\n",
5505 tnapi->last_tag, tnapi->last_irq_tag,
5506 tnapi->tx_prod, tnapi->tx_cons, tnapi->tx_pending,
5508 tnapi->prodring.rx_std_prod_idx,
5509 tnapi->prodring.rx_std_cons_idx,
5510 tnapi->prodring.rx_jmb_prod_idx,
5511 tnapi->prodring.rx_jmb_cons_idx);
5515 /* This is called whenever we suspect that the system chipset is re-
5516 * ordering the sequence of MMIO to the tx send mailbox. The symptom
5517 * is bogus tx completions. We try to recover by setting the
5518 * TG3_FLAG_MBOX_WRITE_REORDER flag and resetting the chip later
5521 static void tg3_tx_recover(struct tg3 *tp)
5523 BUG_ON(tg3_flag(tp, MBOX_WRITE_REORDER) ||
5524 tp->write32_tx_mbox == tg3_write_indirect_mbox);
5526 netdev_warn(tp->dev,
5527 "The system may be re-ordering memory-mapped I/O "
5528 "cycles to the network device, attempting to recover. "
5529 "Please report the problem to the driver maintainer "
5530 "and include system chipset information.\n");
5532 spin_lock(&tp->lock);
5533 tg3_flag_set(tp, TX_RECOVERY_PENDING);
5534 spin_unlock(&tp->lock);
5537 static inline u32 tg3_tx_avail(struct tg3_napi *tnapi)
5539 /* Tell compiler to fetch tx indices from memory. */
5541 return tnapi->tx_pending -
5542 ((tnapi->tx_prod - tnapi->tx_cons) & (TG3_TX_RING_SIZE - 1));
5545 /* Tigon3 never reports partial packet sends. So we do not
5546 * need special logic to handle SKBs that have not had all
5547 * of their frags sent yet, like SunGEM does.
5549 static void tg3_tx(struct tg3_napi *tnapi)
5551 struct tg3 *tp = tnapi->tp;
5552 u32 hw_idx = tnapi->hw_status->idx[0].tx_consumer;
5553 u32 sw_idx = tnapi->tx_cons;
5554 struct netdev_queue *txq;
5555 int index = tnapi - tp->napi;
5556 unsigned int pkts_compl = 0, bytes_compl = 0;
5558 if (tg3_flag(tp, ENABLE_TSS))
5561 txq = netdev_get_tx_queue(tp->dev, index);
5563 while (sw_idx != hw_idx) {
5564 struct tg3_tx_ring_info *ri = &tnapi->tx_buffers[sw_idx];
5565 struct sk_buff *skb = ri->skb;
5568 if (unlikely(skb == NULL)) {
5573 pci_unmap_single(tp->pdev,
5574 dma_unmap_addr(ri, mapping),
5580 while (ri->fragmented) {
5581 ri->fragmented = false;
5582 sw_idx = NEXT_TX(sw_idx);
5583 ri = &tnapi->tx_buffers[sw_idx];
5586 sw_idx = NEXT_TX(sw_idx);
5588 for (i = 0; i < skb_shinfo(skb)->nr_frags; i++) {
5589 ri = &tnapi->tx_buffers[sw_idx];
5590 if (unlikely(ri->skb != NULL || sw_idx == hw_idx))
5593 pci_unmap_page(tp->pdev,
5594 dma_unmap_addr(ri, mapping),
5595 skb_frag_size(&skb_shinfo(skb)->frags[i]),
5598 while (ri->fragmented) {
5599 ri->fragmented = false;
5600 sw_idx = NEXT_TX(sw_idx);
5601 ri = &tnapi->tx_buffers[sw_idx];
5604 sw_idx = NEXT_TX(sw_idx);
5608 bytes_compl += skb->len;
5612 if (unlikely(tx_bug)) {
5618 netdev_completed_queue(tp->dev, pkts_compl, bytes_compl);
5620 tnapi->tx_cons = sw_idx;
5622 /* Need to make the tx_cons update visible to tg3_start_xmit()
5623 * before checking for netif_queue_stopped(). Without the
5624 * memory barrier, there is a small possibility that tg3_start_xmit()
5625 * will miss it and cause the queue to be stopped forever.
5629 if (unlikely(netif_tx_queue_stopped(txq) &&
5630 (tg3_tx_avail(tnapi) > TG3_TX_WAKEUP_THRESH(tnapi)))) {
5631 __netif_tx_lock(txq, smp_processor_id());
5632 if (netif_tx_queue_stopped(txq) &&
5633 (tg3_tx_avail(tnapi) > TG3_TX_WAKEUP_THRESH(tnapi)))
5634 netif_tx_wake_queue(txq);
5635 __netif_tx_unlock(txq);
5639 static void tg3_rx_data_free(struct tg3 *tp, struct ring_info *ri, u32 map_sz)
5644 pci_unmap_single(tp->pdev, dma_unmap_addr(ri, mapping),
5645 map_sz, PCI_DMA_FROMDEVICE);
5650 /* Returns size of skb allocated or < 0 on error.
5652 * We only need to fill in the address because the other members
5653 * of the RX descriptor are invariant, see tg3_init_rings.
5655 * Note the purposeful assymetry of cpu vs. chip accesses. For
5656 * posting buffers we only dirty the first cache line of the RX
5657 * descriptor (containing the address). Whereas for the RX status
5658 * buffers the cpu only reads the last cacheline of the RX descriptor
5659 * (to fetch the error flags, vlan tag, checksum, and opaque cookie).
5661 static int tg3_alloc_rx_data(struct tg3 *tp, struct tg3_rx_prodring_set *tpr,
5662 u32 opaque_key, u32 dest_idx_unmasked)
5664 struct tg3_rx_buffer_desc *desc;
5665 struct ring_info *map;
5668 int skb_size, data_size, dest_idx;
5670 switch (opaque_key) {
5671 case RXD_OPAQUE_RING_STD:
5672 dest_idx = dest_idx_unmasked & tp->rx_std_ring_mask;
5673 desc = &tpr->rx_std[dest_idx];
5674 map = &tpr->rx_std_buffers[dest_idx];
5675 data_size = tp->rx_pkt_map_sz;
5678 case RXD_OPAQUE_RING_JUMBO:
5679 dest_idx = dest_idx_unmasked & tp->rx_jmb_ring_mask;
5680 desc = &tpr->rx_jmb[dest_idx].std;
5681 map = &tpr->rx_jmb_buffers[dest_idx];
5682 data_size = TG3_RX_JMB_MAP_SZ;
5689 /* Do not overwrite any of the map or rp information
5690 * until we are sure we can commit to a new buffer.
5692 * Callers depend upon this behavior and assume that
5693 * we leave everything unchanged if we fail.
5695 skb_size = SKB_DATA_ALIGN(data_size + TG3_RX_OFFSET(tp)) +
5696 SKB_DATA_ALIGN(sizeof(struct skb_shared_info));
5697 data = kmalloc(skb_size, GFP_ATOMIC);
5701 mapping = pci_map_single(tp->pdev,
5702 data + TG3_RX_OFFSET(tp),
5704 PCI_DMA_FROMDEVICE);
5705 if (pci_dma_mapping_error(tp->pdev, mapping)) {
5711 dma_unmap_addr_set(map, mapping, mapping);
5713 desc->addr_hi = ((u64)mapping >> 32);
5714 desc->addr_lo = ((u64)mapping & 0xffffffff);
5719 /* We only need to move over in the address because the other
5720 * members of the RX descriptor are invariant. See notes above
5721 * tg3_alloc_rx_data for full details.
5723 static void tg3_recycle_rx(struct tg3_napi *tnapi,
5724 struct tg3_rx_prodring_set *dpr,
5725 u32 opaque_key, int src_idx,
5726 u32 dest_idx_unmasked)
5728 struct tg3 *tp = tnapi->tp;
5729 struct tg3_rx_buffer_desc *src_desc, *dest_desc;
5730 struct ring_info *src_map, *dest_map;
5731 struct tg3_rx_prodring_set *spr = &tp->napi[0].prodring;
5734 switch (opaque_key) {
5735 case RXD_OPAQUE_RING_STD:
5736 dest_idx = dest_idx_unmasked & tp->rx_std_ring_mask;
5737 dest_desc = &dpr->rx_std[dest_idx];
5738 dest_map = &dpr->rx_std_buffers[dest_idx];
5739 src_desc = &spr->rx_std[src_idx];
5740 src_map = &spr->rx_std_buffers[src_idx];
5743 case RXD_OPAQUE_RING_JUMBO:
5744 dest_idx = dest_idx_unmasked & tp->rx_jmb_ring_mask;
5745 dest_desc = &dpr->rx_jmb[dest_idx].std;
5746 dest_map = &dpr->rx_jmb_buffers[dest_idx];
5747 src_desc = &spr->rx_jmb[src_idx].std;
5748 src_map = &spr->rx_jmb_buffers[src_idx];
5755 dest_map->data = src_map->data;
5756 dma_unmap_addr_set(dest_map, mapping,
5757 dma_unmap_addr(src_map, mapping));
5758 dest_desc->addr_hi = src_desc->addr_hi;
5759 dest_desc->addr_lo = src_desc->addr_lo;
5761 /* Ensure that the update to the skb happens after the physical
5762 * addresses have been transferred to the new BD location.
5766 src_map->data = NULL;
5769 /* The RX ring scheme is composed of multiple rings which post fresh
5770 * buffers to the chip, and one special ring the chip uses to report
5771 * status back to the host.
5773 * The special ring reports the status of received packets to the
5774 * host. The chip does not write into the original descriptor the
5775 * RX buffer was obtained from. The chip simply takes the original
5776 * descriptor as provided by the host, updates the status and length
5777 * field, then writes this into the next status ring entry.
5779 * Each ring the host uses to post buffers to the chip is described
5780 * by a TG3_BDINFO entry in the chips SRAM area. When a packet arrives,
5781 * it is first placed into the on-chip ram. When the packet's length
5782 * is known, it walks down the TG3_BDINFO entries to select the ring.
5783 * Each TG3_BDINFO specifies a MAXLEN field and the first TG3_BDINFO
5784 * which is within the range of the new packet's length is chosen.
5786 * The "separate ring for rx status" scheme may sound queer, but it makes
5787 * sense from a cache coherency perspective. If only the host writes
5788 * to the buffer post rings, and only the chip writes to the rx status
5789 * rings, then cache lines never move beyond shared-modified state.
5790 * If both the host and chip were to write into the same ring, cache line
5791 * eviction could occur since both entities want it in an exclusive state.
5793 static int tg3_rx(struct tg3_napi *tnapi, int budget)
5795 struct tg3 *tp = tnapi->tp;
5796 u32 work_mask, rx_std_posted = 0;
5797 u32 std_prod_idx, jmb_prod_idx;
5798 u32 sw_idx = tnapi->rx_rcb_ptr;
5801 struct tg3_rx_prodring_set *tpr = &tnapi->prodring;
5803 hw_idx = *(tnapi->rx_rcb_prod_idx);
5805 * We need to order the read of hw_idx and the read of
5806 * the opaque cookie.
5811 std_prod_idx = tpr->rx_std_prod_idx;
5812 jmb_prod_idx = tpr->rx_jmb_prod_idx;
5813 while (sw_idx != hw_idx && budget > 0) {
5814 struct ring_info *ri;
5815 struct tg3_rx_buffer_desc *desc = &tnapi->rx_rcb[sw_idx];
5817 struct sk_buff *skb;
5818 dma_addr_t dma_addr;
5819 u32 opaque_key, desc_idx, *post_ptr;
5822 desc_idx = desc->opaque & RXD_OPAQUE_INDEX_MASK;
5823 opaque_key = desc->opaque & RXD_OPAQUE_RING_MASK;
5824 if (opaque_key == RXD_OPAQUE_RING_STD) {
5825 ri = &tp->napi[0].prodring.rx_std_buffers[desc_idx];
5826 dma_addr = dma_unmap_addr(ri, mapping);
5828 post_ptr = &std_prod_idx;
5830 } else if (opaque_key == RXD_OPAQUE_RING_JUMBO) {
5831 ri = &tp->napi[0].prodring.rx_jmb_buffers[desc_idx];
5832 dma_addr = dma_unmap_addr(ri, mapping);
5834 post_ptr = &jmb_prod_idx;
5836 goto next_pkt_nopost;
5838 work_mask |= opaque_key;
5840 if ((desc->err_vlan & RXD_ERR_MASK) != 0 &&
5841 (desc->err_vlan != RXD_ERR_ODD_NIBBLE_RCVD_MII)) {
5843 tg3_recycle_rx(tnapi, tpr, opaque_key,
5844 desc_idx, *post_ptr);
5846 /* Other statistics kept track of by card. */
5851 prefetch(data + TG3_RX_OFFSET(tp));
5852 len = ((desc->idx_len & RXD_LEN_MASK) >> RXD_LEN_SHIFT) -
5855 if (len > TG3_RX_COPY_THRESH(tp)) {
5858 skb_size = tg3_alloc_rx_data(tp, tpr, opaque_key,
5863 pci_unmap_single(tp->pdev, dma_addr, skb_size,
5864 PCI_DMA_FROMDEVICE);
5866 skb = build_skb(data);
5869 goto drop_it_no_recycle;
5871 skb_reserve(skb, TG3_RX_OFFSET(tp));
5872 /* Ensure that the update to the data happens
5873 * after the usage of the old DMA mapping.
5880 tg3_recycle_rx(tnapi, tpr, opaque_key,
5881 desc_idx, *post_ptr);
5883 skb = netdev_alloc_skb(tp->dev,
5884 len + TG3_RAW_IP_ALIGN);
5886 goto drop_it_no_recycle;
5888 skb_reserve(skb, TG3_RAW_IP_ALIGN);
5889 pci_dma_sync_single_for_cpu(tp->pdev, dma_addr, len, PCI_DMA_FROMDEVICE);
5891 data + TG3_RX_OFFSET(tp),
5893 pci_dma_sync_single_for_device(tp->pdev, dma_addr, len, PCI_DMA_FROMDEVICE);
5897 if ((tp->dev->features & NETIF_F_RXCSUM) &&
5898 (desc->type_flags & RXD_FLAG_TCPUDP_CSUM) &&
5899 (((desc->ip_tcp_csum & RXD_TCPCSUM_MASK)
5900 >> RXD_TCPCSUM_SHIFT) == 0xffff))
5901 skb->ip_summed = CHECKSUM_UNNECESSARY;
5903 skb_checksum_none_assert(skb);
5905 skb->protocol = eth_type_trans(skb, tp->dev);
5907 if (len > (tp->dev->mtu + ETH_HLEN) &&
5908 skb->protocol != htons(ETH_P_8021Q)) {
5910 goto drop_it_no_recycle;
5913 if (desc->type_flags & RXD_FLAG_VLAN &&
5914 !(tp->rx_mode & RX_MODE_KEEP_VLAN_TAG))
5915 __vlan_hwaccel_put_tag(skb,
5916 desc->err_vlan & RXD_VLAN_MASK);
5918 napi_gro_receive(&tnapi->napi, skb);
5926 if (unlikely(rx_std_posted >= tp->rx_std_max_post)) {
5927 tpr->rx_std_prod_idx = std_prod_idx &
5928 tp->rx_std_ring_mask;
5929 tw32_rx_mbox(TG3_RX_STD_PROD_IDX_REG,
5930 tpr->rx_std_prod_idx);
5931 work_mask &= ~RXD_OPAQUE_RING_STD;
5936 sw_idx &= tp->rx_ret_ring_mask;
5938 /* Refresh hw_idx to see if there is new work */
5939 if (sw_idx == hw_idx) {
5940 hw_idx = *(tnapi->rx_rcb_prod_idx);
5945 /* ACK the status ring. */
5946 tnapi->rx_rcb_ptr = sw_idx;
5947 tw32_rx_mbox(tnapi->consmbox, sw_idx);
5949 /* Refill RX ring(s). */
5950 if (!tg3_flag(tp, ENABLE_RSS)) {
5951 if (work_mask & RXD_OPAQUE_RING_STD) {
5952 tpr->rx_std_prod_idx = std_prod_idx &
5953 tp->rx_std_ring_mask;
5954 tw32_rx_mbox(TG3_RX_STD_PROD_IDX_REG,
5955 tpr->rx_std_prod_idx);
5957 if (work_mask & RXD_OPAQUE_RING_JUMBO) {
5958 tpr->rx_jmb_prod_idx = jmb_prod_idx &
5959 tp->rx_jmb_ring_mask;
5960 tw32_rx_mbox(TG3_RX_JMB_PROD_IDX_REG,
5961 tpr->rx_jmb_prod_idx);
5964 } else if (work_mask) {
5965 /* rx_std_buffers[] and rx_jmb_buffers[] entries must be
5966 * updated before the producer indices can be updated.
5970 tpr->rx_std_prod_idx = std_prod_idx & tp->rx_std_ring_mask;
5971 tpr->rx_jmb_prod_idx = jmb_prod_idx & tp->rx_jmb_ring_mask;
5973 if (tnapi != &tp->napi[1])
5974 napi_schedule(&tp->napi[1].napi);
5980 static void tg3_poll_link(struct tg3 *tp)
5982 /* handle link change and other phy events */
5983 if (!(tg3_flag(tp, USE_LINKCHG_REG) || tg3_flag(tp, POLL_SERDES))) {
5984 struct tg3_hw_status *sblk = tp->napi[0].hw_status;
5986 if (sblk->status & SD_STATUS_LINK_CHG) {
5987 sblk->status = SD_STATUS_UPDATED |
5988 (sblk->status & ~SD_STATUS_LINK_CHG);
5989 spin_lock(&tp->lock);
5990 if (tg3_flag(tp, USE_PHYLIB)) {
5992 (MAC_STATUS_SYNC_CHANGED |
5993 MAC_STATUS_CFG_CHANGED |
5994 MAC_STATUS_MI_COMPLETION |
5995 MAC_STATUS_LNKSTATE_CHANGED));
5998 tg3_setup_phy(tp, 0);
5999 spin_unlock(&tp->lock);
6004 static int tg3_rx_prodring_xfer(struct tg3 *tp,
6005 struct tg3_rx_prodring_set *dpr,
6006 struct tg3_rx_prodring_set *spr)
6008 u32 si, di, cpycnt, src_prod_idx;
6012 src_prod_idx = spr->rx_std_prod_idx;
6014 /* Make sure updates to the rx_std_buffers[] entries and the
6015 * standard producer index are seen in the correct order.
6019 if (spr->rx_std_cons_idx == src_prod_idx)
6022 if (spr->rx_std_cons_idx < src_prod_idx)
6023 cpycnt = src_prod_idx - spr->rx_std_cons_idx;
6025 cpycnt = tp->rx_std_ring_mask + 1 -
6026 spr->rx_std_cons_idx;
6028 cpycnt = min(cpycnt,
6029 tp->rx_std_ring_mask + 1 - dpr->rx_std_prod_idx);
6031 si = spr->rx_std_cons_idx;
6032 di = dpr->rx_std_prod_idx;
6034 for (i = di; i < di + cpycnt; i++) {
6035 if (dpr->rx_std_buffers[i].data) {
6045 /* Ensure that updates to the rx_std_buffers ring and the
6046 * shadowed hardware producer ring from tg3_recycle_skb() are
6047 * ordered correctly WRT the skb check above.
6051 memcpy(&dpr->rx_std_buffers[di],
6052 &spr->rx_std_buffers[si],
6053 cpycnt * sizeof(struct ring_info));
6055 for (i = 0; i < cpycnt; i++, di++, si++) {
6056 struct tg3_rx_buffer_desc *sbd, *dbd;
6057 sbd = &spr->rx_std[si];
6058 dbd = &dpr->rx_std[di];
6059 dbd->addr_hi = sbd->addr_hi;
6060 dbd->addr_lo = sbd->addr_lo;
6063 spr->rx_std_cons_idx = (spr->rx_std_cons_idx + cpycnt) &
6064 tp->rx_std_ring_mask;
6065 dpr->rx_std_prod_idx = (dpr->rx_std_prod_idx + cpycnt) &
6066 tp->rx_std_ring_mask;
6070 src_prod_idx = spr->rx_jmb_prod_idx;
6072 /* Make sure updates to the rx_jmb_buffers[] entries and
6073 * the jumbo producer index are seen in the correct order.
6077 if (spr->rx_jmb_cons_idx == src_prod_idx)
6080 if (spr->rx_jmb_cons_idx < src_prod_idx)
6081 cpycnt = src_prod_idx - spr->rx_jmb_cons_idx;
6083 cpycnt = tp->rx_jmb_ring_mask + 1 -
6084 spr->rx_jmb_cons_idx;
6086 cpycnt = min(cpycnt,
6087 tp->rx_jmb_ring_mask + 1 - dpr->rx_jmb_prod_idx);
6089 si = spr->rx_jmb_cons_idx;
6090 di = dpr->rx_jmb_prod_idx;
6092 for (i = di; i < di + cpycnt; i++) {
6093 if (dpr->rx_jmb_buffers[i].data) {
6103 /* Ensure that updates to the rx_jmb_buffers ring and the
6104 * shadowed hardware producer ring from tg3_recycle_skb() are
6105 * ordered correctly WRT the skb check above.
6109 memcpy(&dpr->rx_jmb_buffers[di],
6110 &spr->rx_jmb_buffers[si],
6111 cpycnt * sizeof(struct ring_info));
6113 for (i = 0; i < cpycnt; i++, di++, si++) {
6114 struct tg3_rx_buffer_desc *sbd, *dbd;
6115 sbd = &spr->rx_jmb[si].std;
6116 dbd = &dpr->rx_jmb[di].std;
6117 dbd->addr_hi = sbd->addr_hi;
6118 dbd->addr_lo = sbd->addr_lo;
6121 spr->rx_jmb_cons_idx = (spr->rx_jmb_cons_idx + cpycnt) &
6122 tp->rx_jmb_ring_mask;
6123 dpr->rx_jmb_prod_idx = (dpr->rx_jmb_prod_idx + cpycnt) &
6124 tp->rx_jmb_ring_mask;
6130 static int tg3_poll_work(struct tg3_napi *tnapi, int work_done, int budget)
6132 struct tg3 *tp = tnapi->tp;
6134 /* run TX completion thread */
6135 if (tnapi->hw_status->idx[0].tx_consumer != tnapi->tx_cons) {
6137 if (unlikely(tg3_flag(tp, TX_RECOVERY_PENDING)))
6141 /* run RX thread, within the bounds set by NAPI.
6142 * All RX "locking" is done by ensuring outside
6143 * code synchronizes with tg3->napi.poll()
6145 if (*(tnapi->rx_rcb_prod_idx) != tnapi->rx_rcb_ptr)
6146 work_done += tg3_rx(tnapi, budget - work_done);
6148 if (tg3_flag(tp, ENABLE_RSS) && tnapi == &tp->napi[1]) {
6149 struct tg3_rx_prodring_set *dpr = &tp->napi[0].prodring;
6151 u32 std_prod_idx = dpr->rx_std_prod_idx;
6152 u32 jmb_prod_idx = dpr->rx_jmb_prod_idx;
6154 for (i = 1; i < tp->irq_cnt; i++)
6155 err |= tg3_rx_prodring_xfer(tp, dpr,
6156 &tp->napi[i].prodring);
6160 if (std_prod_idx != dpr->rx_std_prod_idx)
6161 tw32_rx_mbox(TG3_RX_STD_PROD_IDX_REG,
6162 dpr->rx_std_prod_idx);
6164 if (jmb_prod_idx != dpr->rx_jmb_prod_idx)
6165 tw32_rx_mbox(TG3_RX_JMB_PROD_IDX_REG,
6166 dpr->rx_jmb_prod_idx);
6171 tw32_f(HOSTCC_MODE, tp->coal_now);
6177 static inline void tg3_reset_task_schedule(struct tg3 *tp)
6179 if (!test_and_set_bit(TG3_FLAG_RESET_TASK_PENDING, tp->tg3_flags))
6180 schedule_work(&tp->reset_task);
6183 static inline void tg3_reset_task_cancel(struct tg3 *tp)
6185 cancel_work_sync(&tp->reset_task);
6186 tg3_flag_clear(tp, RESET_TASK_PENDING);
6189 static int tg3_poll_msix(struct napi_struct *napi, int budget)
6191 struct tg3_napi *tnapi = container_of(napi, struct tg3_napi, napi);
6192 struct tg3 *tp = tnapi->tp;
6194 struct tg3_hw_status *sblk = tnapi->hw_status;
6197 work_done = tg3_poll_work(tnapi, work_done, budget);
6199 if (unlikely(tg3_flag(tp, TX_RECOVERY_PENDING)))
6202 if (unlikely(work_done >= budget))
6205 /* tp->last_tag is used in tg3_int_reenable() below
6206 * to tell the hw how much work has been processed,
6207 * so we must read it before checking for more work.
6209 tnapi->last_tag = sblk->status_tag;
6210 tnapi->last_irq_tag = tnapi->last_tag;
6213 /* check for RX/TX work to do */
6214 if (likely(sblk->idx[0].tx_consumer == tnapi->tx_cons &&
6215 *(tnapi->rx_rcb_prod_idx) == tnapi->rx_rcb_ptr)) {
6216 napi_complete(napi);
6217 /* Reenable interrupts. */
6218 tw32_mailbox(tnapi->int_mbox, tnapi->last_tag << 24);
6227 /* work_done is guaranteed to be less than budget. */
6228 napi_complete(napi);
6229 tg3_reset_task_schedule(tp);
6233 static void tg3_process_error(struct tg3 *tp)
6236 bool real_error = false;
6238 if (tg3_flag(tp, ERROR_PROCESSED))
6241 /* Check Flow Attention register */
6242 val = tr32(HOSTCC_FLOW_ATTN);
6243 if (val & ~HOSTCC_FLOW_ATTN_MBUF_LWM) {
6244 netdev_err(tp->dev, "FLOW Attention error. Resetting chip.\n");
6248 if (tr32(MSGINT_STATUS) & ~MSGINT_STATUS_MSI_REQ) {
6249 netdev_err(tp->dev, "MSI Status error. Resetting chip.\n");
6253 if (tr32(RDMAC_STATUS) || tr32(WDMAC_STATUS)) {
6254 netdev_err(tp->dev, "DMA Status error. Resetting chip.\n");
6263 tg3_flag_set(tp, ERROR_PROCESSED);
6264 tg3_reset_task_schedule(tp);
6267 static int tg3_poll(struct napi_struct *napi, int budget)
6269 struct tg3_napi *tnapi = container_of(napi, struct tg3_napi, napi);
6270 struct tg3 *tp = tnapi->tp;
6272 struct tg3_hw_status *sblk = tnapi->hw_status;
6275 if (sblk->status & SD_STATUS_ERROR)
6276 tg3_process_error(tp);
6280 work_done = tg3_poll_work(tnapi, work_done, budget);
6282 if (unlikely(tg3_flag(tp, TX_RECOVERY_PENDING)))
6285 if (unlikely(work_done >= budget))
6288 if (tg3_flag(tp, TAGGED_STATUS)) {
6289 /* tp->last_tag is used in tg3_int_reenable() below
6290 * to tell the hw how much work has been processed,
6291 * so we must read it before checking for more work.
6293 tnapi->last_tag = sblk->status_tag;
6294 tnapi->last_irq_tag = tnapi->last_tag;
6297 sblk->status &= ~SD_STATUS_UPDATED;
6299 if (likely(!tg3_has_work(tnapi))) {
6300 napi_complete(napi);
6301 tg3_int_reenable(tnapi);
6309 /* work_done is guaranteed to be less than budget. */
6310 napi_complete(napi);
6311 tg3_reset_task_schedule(tp);
6315 static void tg3_napi_disable(struct tg3 *tp)
6319 for (i = tp->irq_cnt - 1; i >= 0; i--)
6320 napi_disable(&tp->napi[i].napi);
6323 static void tg3_napi_enable(struct tg3 *tp)
6327 for (i = 0; i < tp->irq_cnt; i++)
6328 napi_enable(&tp->napi[i].napi);
6331 static void tg3_napi_init(struct tg3 *tp)
6335 netif_napi_add(tp->dev, &tp->napi[0].napi, tg3_poll, 64);
6336 for (i = 1; i < tp->irq_cnt; i++)
6337 netif_napi_add(tp->dev, &tp->napi[i].napi, tg3_poll_msix, 64);
6340 static void tg3_napi_fini(struct tg3 *tp)
6344 for (i = 0; i < tp->irq_cnt; i++)
6345 netif_napi_del(&tp->napi[i].napi);
6348 static inline void tg3_netif_stop(struct tg3 *tp)
6350 tp->dev->trans_start = jiffies; /* prevent tx timeout */
6351 tg3_napi_disable(tp);
6352 netif_tx_disable(tp->dev);
6355 static inline void tg3_netif_start(struct tg3 *tp)
6357 /* NOTE: unconditional netif_tx_wake_all_queues is only
6358 * appropriate so long as all callers are assured to
6359 * have free tx slots (such as after tg3_init_hw)
6361 netif_tx_wake_all_queues(tp->dev);
6363 tg3_napi_enable(tp);
6364 tp->napi[0].hw_status->status |= SD_STATUS_UPDATED;
6365 tg3_enable_ints(tp);
6368 static void tg3_irq_quiesce(struct tg3 *tp)
6372 BUG_ON(tp->irq_sync);
6377 for (i = 0; i < tp->irq_cnt; i++)
6378 synchronize_irq(tp->napi[i].irq_vec);
6381 /* Fully shutdown all tg3 driver activity elsewhere in the system.
6382 * If irq_sync is non-zero, then the IRQ handler must be synchronized
6383 * with as well. Most of the time, this is not necessary except when
6384 * shutting down the device.
6386 static inline void tg3_full_lock(struct tg3 *tp, int irq_sync)
6388 spin_lock_bh(&tp->lock);
6390 tg3_irq_quiesce(tp);
6393 static inline void tg3_full_unlock(struct tg3 *tp)
6395 spin_unlock_bh(&tp->lock);
6398 /* One-shot MSI handler - Chip automatically disables interrupt
6399 * after sending MSI so driver doesn't have to do it.
6401 static irqreturn_t tg3_msi_1shot(int irq, void *dev_id)
6403 struct tg3_napi *tnapi = dev_id;
6404 struct tg3 *tp = tnapi->tp;
6406 prefetch(tnapi->hw_status);
6408 prefetch(&tnapi->rx_rcb[tnapi->rx_rcb_ptr]);
6410 if (likely(!tg3_irq_sync(tp)))
6411 napi_schedule(&tnapi->napi);
6416 /* MSI ISR - No need to check for interrupt sharing and no need to
6417 * flush status block and interrupt mailbox. PCI ordering rules
6418 * guarantee that MSI will arrive after the status block.
6420 static irqreturn_t tg3_msi(int irq, void *dev_id)
6422 struct tg3_napi *tnapi = dev_id;
6423 struct tg3 *tp = tnapi->tp;
6425 prefetch(tnapi->hw_status);
6427 prefetch(&tnapi->rx_rcb[tnapi->rx_rcb_ptr]);
6429 * Writing any value to intr-mbox-0 clears PCI INTA# and
6430 * chip-internal interrupt pending events.
6431 * Writing non-zero to intr-mbox-0 additional tells the
6432 * NIC to stop sending us irqs, engaging "in-intr-handler"
6435 tw32_mailbox(tnapi->int_mbox, 0x00000001);
6436 if (likely(!tg3_irq_sync(tp)))
6437 napi_schedule(&tnapi->napi);
6439 return IRQ_RETVAL(1);
6442 static irqreturn_t tg3_interrupt(int irq, void *dev_id)
6444 struct tg3_napi *tnapi = dev_id;
6445 struct tg3 *tp = tnapi->tp;
6446 struct tg3_hw_status *sblk = tnapi->hw_status;
6447 unsigned int handled = 1;
6449 /* In INTx mode, it is possible for the interrupt to arrive at
6450 * the CPU before the status block posted prior to the interrupt.
6451 * Reading the PCI State register will confirm whether the
6452 * interrupt is ours and will flush the status block.
6454 if (unlikely(!(sblk->status & SD_STATUS_UPDATED))) {
6455 if (tg3_flag(tp, CHIP_RESETTING) ||
6456 (tr32(TG3PCI_PCISTATE) & PCISTATE_INT_NOT_ACTIVE)) {
6463 * Writing any value to intr-mbox-0 clears PCI INTA# and
6464 * chip-internal interrupt pending events.
6465 * Writing non-zero to intr-mbox-0 additional tells the
6466 * NIC to stop sending us irqs, engaging "in-intr-handler"
6469 * Flush the mailbox to de-assert the IRQ immediately to prevent
6470 * spurious interrupts. The flush impacts performance but
6471 * excessive spurious interrupts can be worse in some cases.
6473 tw32_mailbox_f(MAILBOX_INTERRUPT_0 + TG3_64BIT_REG_LOW, 0x00000001);
6474 if (tg3_irq_sync(tp))
6476 sblk->status &= ~SD_STATUS_UPDATED;
6477 if (likely(tg3_has_work(tnapi))) {
6478 prefetch(&tnapi->rx_rcb[tnapi->rx_rcb_ptr]);
6479 napi_schedule(&tnapi->napi);
6481 /* No work, shared interrupt perhaps? re-enable
6482 * interrupts, and flush that PCI write
6484 tw32_mailbox_f(MAILBOX_INTERRUPT_0 + TG3_64BIT_REG_LOW,
6488 return IRQ_RETVAL(handled);
6491 static irqreturn_t tg3_interrupt_tagged(int irq, void *dev_id)
6493 struct tg3_napi *tnapi = dev_id;
6494 struct tg3 *tp = tnapi->tp;
6495 struct tg3_hw_status *sblk = tnapi->hw_status;
6496 unsigned int handled = 1;
6498 /* In INTx mode, it is possible for the interrupt to arrive at
6499 * the CPU before the status block posted prior to the interrupt.
6500 * Reading the PCI State register will confirm whether the
6501 * interrupt is ours and will flush the status block.
6503 if (unlikely(sblk->status_tag == tnapi->last_irq_tag)) {
6504 if (tg3_flag(tp, CHIP_RESETTING) ||
6505 (tr32(TG3PCI_PCISTATE) & PCISTATE_INT_NOT_ACTIVE)) {
6512 * writing any value to intr-mbox-0 clears PCI INTA# and
6513 * chip-internal interrupt pending events.
6514 * writing non-zero to intr-mbox-0 additional tells the
6515 * NIC to stop sending us irqs, engaging "in-intr-handler"
6518 * Flush the mailbox to de-assert the IRQ immediately to prevent
6519 * spurious interrupts. The flush impacts performance but
6520 * excessive spurious interrupts can be worse in some cases.
6522 tw32_mailbox_f(MAILBOX_INTERRUPT_0 + TG3_64BIT_REG_LOW, 0x00000001);
6525 * In a shared interrupt configuration, sometimes other devices'
6526 * interrupts will scream. We record the current status tag here
6527 * so that the above check can report that the screaming interrupts
6528 * are unhandled. Eventually they will be silenced.
6530 tnapi->last_irq_tag = sblk->status_tag;
6532 if (tg3_irq_sync(tp))
6535 prefetch(&tnapi->rx_rcb[tnapi->rx_rcb_ptr]);
6537 napi_schedule(&tnapi->napi);
6540 return IRQ_RETVAL(handled);
6543 /* ISR for interrupt test */
6544 static irqreturn_t tg3_test_isr(int irq, void *dev_id)
6546 struct tg3_napi *tnapi = dev_id;
6547 struct tg3 *tp = tnapi->tp;
6548 struct tg3_hw_status *sblk = tnapi->hw_status;
6550 if ((sblk->status & SD_STATUS_UPDATED) ||
6551 !(tr32(TG3PCI_PCISTATE) & PCISTATE_INT_NOT_ACTIVE)) {
6552 tg3_disable_ints(tp);
6553 return IRQ_RETVAL(1);
6555 return IRQ_RETVAL(0);
6558 #ifdef CONFIG_NET_POLL_CONTROLLER
6559 static void tg3_poll_controller(struct net_device *dev)
6562 struct tg3 *tp = netdev_priv(dev);
6564 for (i = 0; i < tp->irq_cnt; i++)
6565 tg3_interrupt(tp->napi[i].irq_vec, &tp->napi[i]);
6569 static void tg3_tx_timeout(struct net_device *dev)
6571 struct tg3 *tp = netdev_priv(dev);
6573 if (netif_msg_tx_err(tp)) {
6574 netdev_err(dev, "transmit timed out, resetting\n");
6578 tg3_reset_task_schedule(tp);
6581 /* Test for DMA buffers crossing any 4GB boundaries: 4G, 8G, etc */
6582 static inline int tg3_4g_overflow_test(dma_addr_t mapping, int len)
6584 u32 base = (u32) mapping & 0xffffffff;
6586 return (base > 0xffffdcc0) && (base + len + 8 < base);
6589 /* Test for DMA addresses > 40-bit */
6590 static inline int tg3_40bit_overflow_test(struct tg3 *tp, dma_addr_t mapping,
6593 #if defined(CONFIG_HIGHMEM) && (BITS_PER_LONG == 64)
6594 if (tg3_flag(tp, 40BIT_DMA_BUG))
6595 return ((u64) mapping + len) > DMA_BIT_MASK(40);
6602 static inline void tg3_tx_set_bd(struct tg3_tx_buffer_desc *txbd,
6603 dma_addr_t mapping, u32 len, u32 flags,
6606 txbd->addr_hi = ((u64) mapping >> 32);
6607 txbd->addr_lo = ((u64) mapping & 0xffffffff);
6608 txbd->len_flags = (len << TXD_LEN_SHIFT) | (flags & 0x0000ffff);
6609 txbd->vlan_tag = (mss << TXD_MSS_SHIFT) | (vlan << TXD_VLAN_TAG_SHIFT);
6612 static bool tg3_tx_frag_set(struct tg3_napi *tnapi, u32 *entry, u32 *budget,
6613 dma_addr_t map, u32 len, u32 flags,
6616 struct tg3 *tp = tnapi->tp;
6619 if (tg3_flag(tp, SHORT_DMA_BUG) && len <= 8)
6622 if (tg3_4g_overflow_test(map, len))
6625 if (tg3_40bit_overflow_test(tp, map, len))
6628 if (tp->dma_limit) {
6629 u32 prvidx = *entry;
6630 u32 tmp_flag = flags & ~TXD_FLAG_END;
6631 while (len > tp->dma_limit && *budget) {
6632 u32 frag_len = tp->dma_limit;
6633 len -= tp->dma_limit;
6635 /* Avoid the 8byte DMA problem */
6637 len += tp->dma_limit / 2;
6638 frag_len = tp->dma_limit / 2;
6641 tnapi->tx_buffers[*entry].fragmented = true;
6643 tg3_tx_set_bd(&tnapi->tx_ring[*entry], map,
6644 frag_len, tmp_flag, mss, vlan);
6647 *entry = NEXT_TX(*entry);
6654 tg3_tx_set_bd(&tnapi->tx_ring[*entry], map,
6655 len, flags, mss, vlan);
6657 *entry = NEXT_TX(*entry);
6660 tnapi->tx_buffers[prvidx].fragmented = false;
6664 tg3_tx_set_bd(&tnapi->tx_ring[*entry], map,
6665 len, flags, mss, vlan);
6666 *entry = NEXT_TX(*entry);
6672 static void tg3_tx_skb_unmap(struct tg3_napi *tnapi, u32 entry, int last)
6675 struct sk_buff *skb;
6676 struct tg3_tx_ring_info *txb = &tnapi->tx_buffers[entry];
6681 pci_unmap_single(tnapi->tp->pdev,
6682 dma_unmap_addr(txb, mapping),
6686 while (txb->fragmented) {
6687 txb->fragmented = false;
6688 entry = NEXT_TX(entry);
6689 txb = &tnapi->tx_buffers[entry];
6692 for (i = 0; i <= last; i++) {
6693 const skb_frag_t *frag = &skb_shinfo(skb)->frags[i];
6695 entry = NEXT_TX(entry);
6696 txb = &tnapi->tx_buffers[entry];
6698 pci_unmap_page(tnapi->tp->pdev,
6699 dma_unmap_addr(txb, mapping),
6700 skb_frag_size(frag), PCI_DMA_TODEVICE);
6702 while (txb->fragmented) {
6703 txb->fragmented = false;
6704 entry = NEXT_TX(entry);
6705 txb = &tnapi->tx_buffers[entry];
6710 /* Workaround 4GB and 40-bit hardware DMA bugs. */
6711 static int tigon3_dma_hwbug_workaround(struct tg3_napi *tnapi,
6712 struct sk_buff **pskb,
6713 u32 *entry, u32 *budget,
6714 u32 base_flags, u32 mss, u32 vlan)
6716 struct tg3 *tp = tnapi->tp;
6717 struct sk_buff *new_skb, *skb = *pskb;
6718 dma_addr_t new_addr = 0;
6721 if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5701)
6722 new_skb = skb_copy(skb, GFP_ATOMIC);
6724 int more_headroom = 4 - ((unsigned long)skb->data & 3);
6726 new_skb = skb_copy_expand(skb,
6727 skb_headroom(skb) + more_headroom,
6728 skb_tailroom(skb), GFP_ATOMIC);
6734 /* New SKB is guaranteed to be linear. */
6735 new_addr = pci_map_single(tp->pdev, new_skb->data, new_skb->len,
6737 /* Make sure the mapping succeeded */
6738 if (pci_dma_mapping_error(tp->pdev, new_addr)) {
6739 dev_kfree_skb(new_skb);
6742 u32 save_entry = *entry;
6744 base_flags |= TXD_FLAG_END;
6746 tnapi->tx_buffers[*entry].skb = new_skb;
6747 dma_unmap_addr_set(&tnapi->tx_buffers[*entry],
6750 if (tg3_tx_frag_set(tnapi, entry, budget, new_addr,
6751 new_skb->len, base_flags,
6753 tg3_tx_skb_unmap(tnapi, save_entry, -1);
6754 dev_kfree_skb(new_skb);
6765 static netdev_tx_t tg3_start_xmit(struct sk_buff *, struct net_device *);
6767 /* Use GSO to workaround a rare TSO bug that may be triggered when the
6768 * TSO header is greater than 80 bytes.
6770 static int tg3_tso_bug(struct tg3 *tp, struct sk_buff *skb)
6772 struct sk_buff *segs, *nskb;
6773 u32 frag_cnt_est = skb_shinfo(skb)->gso_segs * 3;
6775 /* Estimate the number of fragments in the worst case */
6776 if (unlikely(tg3_tx_avail(&tp->napi[0]) <= frag_cnt_est)) {
6777 netif_stop_queue(tp->dev);
6779 /* netif_tx_stop_queue() must be done before checking
6780 * checking tx index in tg3_tx_avail() below, because in
6781 * tg3_tx(), we update tx index before checking for
6782 * netif_tx_queue_stopped().
6785 if (tg3_tx_avail(&tp->napi[0]) <= frag_cnt_est)
6786 return NETDEV_TX_BUSY;
6788 netif_wake_queue(tp->dev);
6791 segs = skb_gso_segment(skb, tp->dev->features & ~NETIF_F_TSO);
6793 goto tg3_tso_bug_end;
6799 tg3_start_xmit(nskb, tp->dev);
6805 return NETDEV_TX_OK;
6808 /* hard_start_xmit for devices that have the 4G bug and/or 40-bit bug and
6809 * support TG3_FLAG_HW_TSO_1 or firmware TSO only.
6811 static netdev_tx_t tg3_start_xmit(struct sk_buff *skb, struct net_device *dev)
6813 struct tg3 *tp = netdev_priv(dev);
6814 u32 len, entry, base_flags, mss, vlan = 0;
6816 int i = -1, would_hit_hwbug;
6818 struct tg3_napi *tnapi;
6819 struct netdev_queue *txq;
6822 txq = netdev_get_tx_queue(dev, skb_get_queue_mapping(skb));
6823 tnapi = &tp->napi[skb_get_queue_mapping(skb)];
6824 if (tg3_flag(tp, ENABLE_TSS))
6827 budget = tg3_tx_avail(tnapi);
6829 /* We are running in BH disabled context with netif_tx_lock
6830 * and TX reclaim runs via tp->napi.poll inside of a software
6831 * interrupt. Furthermore, IRQ processing runs lockless so we have
6832 * no IRQ context deadlocks to worry about either. Rejoice!
6834 if (unlikely(budget <= (skb_shinfo(skb)->nr_frags + 1))) {
6835 if (!netif_tx_queue_stopped(txq)) {
6836 netif_tx_stop_queue(txq);
6838 /* This is a hard error, log it. */
6840 "BUG! Tx Ring full when queue awake!\n");
6842 return NETDEV_TX_BUSY;
6845 entry = tnapi->tx_prod;
6847 if (skb->ip_summed == CHECKSUM_PARTIAL)
6848 base_flags |= TXD_FLAG_TCPUDP_CSUM;
6850 mss = skb_shinfo(skb)->gso_size;
6853 u32 tcp_opt_len, hdr_len;
6855 if (skb_header_cloned(skb) &&
6856 pskb_expand_head(skb, 0, 0, GFP_ATOMIC))
6860 tcp_opt_len = tcp_optlen(skb);
6862 hdr_len = skb_transport_offset(skb) + tcp_hdrlen(skb) - ETH_HLEN;
6864 if (!skb_is_gso_v6(skb)) {
6866 iph->tot_len = htons(mss + hdr_len);
6869 if (unlikely((ETH_HLEN + hdr_len) > 80) &&
6870 tg3_flag(tp, TSO_BUG))
6871 return tg3_tso_bug(tp, skb);
6873 base_flags |= (TXD_FLAG_CPU_PRE_DMA |
6874 TXD_FLAG_CPU_POST_DMA);
6876 if (tg3_flag(tp, HW_TSO_1) ||
6877 tg3_flag(tp, HW_TSO_2) ||
6878 tg3_flag(tp, HW_TSO_3)) {
6879 tcp_hdr(skb)->check = 0;
6880 base_flags &= ~TXD_FLAG_TCPUDP_CSUM;
6882 tcp_hdr(skb)->check = ~csum_tcpudp_magic(iph->saddr,
6887 if (tg3_flag(tp, HW_TSO_3)) {
6888 mss |= (hdr_len & 0xc) << 12;
6890 base_flags |= 0x00000010;
6891 base_flags |= (hdr_len & 0x3e0) << 5;
6892 } else if (tg3_flag(tp, HW_TSO_2))
6893 mss |= hdr_len << 9;
6894 else if (tg3_flag(tp, HW_TSO_1) ||
6895 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705) {
6896 if (tcp_opt_len || iph->ihl > 5) {
6899 tsflags = (iph->ihl - 5) + (tcp_opt_len >> 2);
6900 mss |= (tsflags << 11);
6903 if (tcp_opt_len || iph->ihl > 5) {
6906 tsflags = (iph->ihl - 5) + (tcp_opt_len >> 2);
6907 base_flags |= tsflags << 12;
6912 if (tg3_flag(tp, USE_JUMBO_BDFLAG) &&
6913 !mss && skb->len > VLAN_ETH_FRAME_LEN)
6914 base_flags |= TXD_FLAG_JMB_PKT;
6916 if (vlan_tx_tag_present(skb)) {
6917 base_flags |= TXD_FLAG_VLAN;
6918 vlan = vlan_tx_tag_get(skb);
6921 len = skb_headlen(skb);
6923 mapping = pci_map_single(tp->pdev, skb->data, len, PCI_DMA_TODEVICE);
6924 if (pci_dma_mapping_error(tp->pdev, mapping))
6928 tnapi->tx_buffers[entry].skb = skb;
6929 dma_unmap_addr_set(&tnapi->tx_buffers[entry], mapping, mapping);
6931 would_hit_hwbug = 0;
6933 if (tg3_flag(tp, 5701_DMA_BUG))
6934 would_hit_hwbug = 1;
6936 if (tg3_tx_frag_set(tnapi, &entry, &budget, mapping, len, base_flags |
6937 ((skb_shinfo(skb)->nr_frags == 0) ? TXD_FLAG_END : 0),
6939 would_hit_hwbug = 1;
6940 } else if (skb_shinfo(skb)->nr_frags > 0) {
6943 if (!tg3_flag(tp, HW_TSO_1) &&
6944 !tg3_flag(tp, HW_TSO_2) &&
6945 !tg3_flag(tp, HW_TSO_3))
6948 /* Now loop through additional data
6949 * fragments, and queue them.
6951 last = skb_shinfo(skb)->nr_frags - 1;
6952 for (i = 0; i <= last; i++) {
6953 skb_frag_t *frag = &skb_shinfo(skb)->frags[i];
6955 len = skb_frag_size(frag);
6956 mapping = skb_frag_dma_map(&tp->pdev->dev, frag, 0,
6957 len, DMA_TO_DEVICE);
6959 tnapi->tx_buffers[entry].skb = NULL;
6960 dma_unmap_addr_set(&tnapi->tx_buffers[entry], mapping,
6962 if (dma_mapping_error(&tp->pdev->dev, mapping))
6966 tg3_tx_frag_set(tnapi, &entry, &budget, mapping,
6968 ((i == last) ? TXD_FLAG_END : 0),
6970 would_hit_hwbug = 1;
6976 if (would_hit_hwbug) {
6977 tg3_tx_skb_unmap(tnapi, tnapi->tx_prod, i);
6979 /* If the workaround fails due to memory/mapping
6980 * failure, silently drop this packet.
6982 entry = tnapi->tx_prod;
6983 budget = tg3_tx_avail(tnapi);
6984 if (tigon3_dma_hwbug_workaround(tnapi, &skb, &entry, &budget,
6985 base_flags, mss, vlan))
6989 skb_tx_timestamp(skb);
6990 netdev_sent_queue(tp->dev, skb->len);
6992 /* Packets are ready, update Tx producer idx local and on card. */
6993 tw32_tx_mbox(tnapi->prodmbox, entry);
6995 tnapi->tx_prod = entry;
6996 if (unlikely(tg3_tx_avail(tnapi) <= (MAX_SKB_FRAGS + 1))) {
6997 netif_tx_stop_queue(txq);
6999 /* netif_tx_stop_queue() must be done before checking
7000 * checking tx index in tg3_tx_avail() below, because in
7001 * tg3_tx(), we update tx index before checking for
7002 * netif_tx_queue_stopped().
7005 if (tg3_tx_avail(tnapi) > TG3_TX_WAKEUP_THRESH(tnapi))
7006 netif_tx_wake_queue(txq);
7010 return NETDEV_TX_OK;
7013 tg3_tx_skb_unmap(tnapi, tnapi->tx_prod, --i);
7014 tnapi->tx_buffers[tnapi->tx_prod].skb = NULL;
7019 return NETDEV_TX_OK;
7022 static void tg3_mac_loopback(struct tg3 *tp, bool enable)
7025 tp->mac_mode &= ~(MAC_MODE_HALF_DUPLEX |
7026 MAC_MODE_PORT_MODE_MASK);
7028 tp->mac_mode |= MAC_MODE_PORT_INT_LPBACK;
7030 if (!tg3_flag(tp, 5705_PLUS))
7031 tp->mac_mode |= MAC_MODE_LINK_POLARITY;
7033 if (tp->phy_flags & TG3_PHYFLG_10_100_ONLY)
7034 tp->mac_mode |= MAC_MODE_PORT_MODE_MII;
7036 tp->mac_mode |= MAC_MODE_PORT_MODE_GMII;
7038 tp->mac_mode &= ~MAC_MODE_PORT_INT_LPBACK;
7040 if (tg3_flag(tp, 5705_PLUS) ||
7041 (tp->phy_flags & TG3_PHYFLG_PHY_SERDES) ||
7042 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700)
7043 tp->mac_mode &= ~MAC_MODE_LINK_POLARITY;
7046 tw32(MAC_MODE, tp->mac_mode);
7050 static int tg3_phy_lpbk_set(struct tg3 *tp, u32 speed, bool extlpbk)
7052 u32 val, bmcr, mac_mode, ptest = 0;
7054 tg3_phy_toggle_apd(tp, false);
7055 tg3_phy_toggle_automdix(tp, 0);
7057 if (extlpbk && tg3_phy_set_extloopbk(tp))
7060 bmcr = BMCR_FULLDPLX;
7065 bmcr |= BMCR_SPEED100;
7069 if (tp->phy_flags & TG3_PHYFLG_IS_FET) {
7071 bmcr |= BMCR_SPEED100;
7074 bmcr |= BMCR_SPEED1000;
7079 if (!(tp->phy_flags & TG3_PHYFLG_IS_FET)) {
7080 tg3_readphy(tp, MII_CTRL1000, &val);
7081 val |= CTL1000_AS_MASTER |
7082 CTL1000_ENABLE_MASTER;
7083 tg3_writephy(tp, MII_CTRL1000, val);
7085 ptest = MII_TG3_FET_PTEST_TRIM_SEL |
7086 MII_TG3_FET_PTEST_TRIM_2;
7087 tg3_writephy(tp, MII_TG3_FET_PTEST, ptest);
7090 bmcr |= BMCR_LOOPBACK;
7092 tg3_writephy(tp, MII_BMCR, bmcr);
7094 /* The write needs to be flushed for the FETs */
7095 if (tp->phy_flags & TG3_PHYFLG_IS_FET)
7096 tg3_readphy(tp, MII_BMCR, &bmcr);
7100 if ((tp->phy_flags & TG3_PHYFLG_IS_FET) &&
7101 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785) {
7102 tg3_writephy(tp, MII_TG3_FET_PTEST, ptest |
7103 MII_TG3_FET_PTEST_FRC_TX_LINK |
7104 MII_TG3_FET_PTEST_FRC_TX_LOCK);
7106 /* The write needs to be flushed for the AC131 */
7107 tg3_readphy(tp, MII_TG3_FET_PTEST, &val);
7110 /* Reset to prevent losing 1st rx packet intermittently */
7111 if ((tp->phy_flags & TG3_PHYFLG_MII_SERDES) &&
7112 tg3_flag(tp, 5780_CLASS)) {
7113 tw32_f(MAC_RX_MODE, RX_MODE_RESET);
7115 tw32_f(MAC_RX_MODE, tp->rx_mode);
7118 mac_mode = tp->mac_mode &
7119 ~(MAC_MODE_PORT_MODE_MASK | MAC_MODE_HALF_DUPLEX);
7120 if (speed == SPEED_1000)
7121 mac_mode |= MAC_MODE_PORT_MODE_GMII;
7123 mac_mode |= MAC_MODE_PORT_MODE_MII;
7125 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700) {
7126 u32 masked_phy_id = tp->phy_id & TG3_PHY_ID_MASK;
7128 if (masked_phy_id == TG3_PHY_ID_BCM5401)
7129 mac_mode &= ~MAC_MODE_LINK_POLARITY;
7130 else if (masked_phy_id == TG3_PHY_ID_BCM5411)
7131 mac_mode |= MAC_MODE_LINK_POLARITY;
7133 tg3_writephy(tp, MII_TG3_EXT_CTRL,
7134 MII_TG3_EXT_CTRL_LNK3_LED_MODE);
7137 tw32(MAC_MODE, mac_mode);
7143 static void tg3_set_loopback(struct net_device *dev, netdev_features_t features)
7145 struct tg3 *tp = netdev_priv(dev);
7147 if (features & NETIF_F_LOOPBACK) {
7148 if (tp->mac_mode & MAC_MODE_PORT_INT_LPBACK)
7151 spin_lock_bh(&tp->lock);
7152 tg3_mac_loopback(tp, true);
7153 netif_carrier_on(tp->dev);
7154 spin_unlock_bh(&tp->lock);
7155 netdev_info(dev, "Internal MAC loopback mode enabled.\n");
7157 if (!(tp->mac_mode & MAC_MODE_PORT_INT_LPBACK))
7160 spin_lock_bh(&tp->lock);
7161 tg3_mac_loopback(tp, false);
7162 /* Force link status check */
7163 tg3_setup_phy(tp, 1);
7164 spin_unlock_bh(&tp->lock);
7165 netdev_info(dev, "Internal MAC loopback mode disabled.\n");
7169 static netdev_features_t tg3_fix_features(struct net_device *dev,
7170 netdev_features_t features)
7172 struct tg3 *tp = netdev_priv(dev);
7174 if (dev->mtu > ETH_DATA_LEN && tg3_flag(tp, 5780_CLASS))
7175 features &= ~NETIF_F_ALL_TSO;
7180 static int tg3_set_features(struct net_device *dev, netdev_features_t features)
7182 netdev_features_t changed = dev->features ^ features;
7184 if ((changed & NETIF_F_LOOPBACK) && netif_running(dev))
7185 tg3_set_loopback(dev, features);
7190 static void tg3_rx_prodring_free(struct tg3 *tp,
7191 struct tg3_rx_prodring_set *tpr)
7195 if (tpr != &tp->napi[0].prodring) {
7196 for (i = tpr->rx_std_cons_idx; i != tpr->rx_std_prod_idx;
7197 i = (i + 1) & tp->rx_std_ring_mask)
7198 tg3_rx_data_free(tp, &tpr->rx_std_buffers[i],
7201 if (tg3_flag(tp, JUMBO_CAPABLE)) {
7202 for (i = tpr->rx_jmb_cons_idx;
7203 i != tpr->rx_jmb_prod_idx;
7204 i = (i + 1) & tp->rx_jmb_ring_mask) {
7205 tg3_rx_data_free(tp, &tpr->rx_jmb_buffers[i],
7213 for (i = 0; i <= tp->rx_std_ring_mask; i++)
7214 tg3_rx_data_free(tp, &tpr->rx_std_buffers[i],
7217 if (tg3_flag(tp, JUMBO_CAPABLE) && !tg3_flag(tp, 5780_CLASS)) {
7218 for (i = 0; i <= tp->rx_jmb_ring_mask; i++)
7219 tg3_rx_data_free(tp, &tpr->rx_jmb_buffers[i],
7224 /* Initialize rx rings for packet processing.
7226 * The chip has been shut down and the driver detached from
7227 * the networking, so no interrupts or new tx packets will
7228 * end up in the driver. tp->{tx,}lock are held and thus
7231 static int tg3_rx_prodring_alloc(struct tg3 *tp,
7232 struct tg3_rx_prodring_set *tpr)
7234 u32 i, rx_pkt_dma_sz;
7236 tpr->rx_std_cons_idx = 0;
7237 tpr->rx_std_prod_idx = 0;
7238 tpr->rx_jmb_cons_idx = 0;
7239 tpr->rx_jmb_prod_idx = 0;
7241 if (tpr != &tp->napi[0].prodring) {
7242 memset(&tpr->rx_std_buffers[0], 0,
7243 TG3_RX_STD_BUFF_RING_SIZE(tp));
7244 if (tpr->rx_jmb_buffers)
7245 memset(&tpr->rx_jmb_buffers[0], 0,
7246 TG3_RX_JMB_BUFF_RING_SIZE(tp));
7250 /* Zero out all descriptors. */
7251 memset(tpr->rx_std, 0, TG3_RX_STD_RING_BYTES(tp));
7253 rx_pkt_dma_sz = TG3_RX_STD_DMA_SZ;
7254 if (tg3_flag(tp, 5780_CLASS) &&
7255 tp->dev->mtu > ETH_DATA_LEN)
7256 rx_pkt_dma_sz = TG3_RX_JMB_DMA_SZ;
7257 tp->rx_pkt_map_sz = TG3_RX_DMA_TO_MAP_SZ(rx_pkt_dma_sz);
7259 /* Initialize invariants of the rings, we only set this
7260 * stuff once. This works because the card does not
7261 * write into the rx buffer posting rings.
7263 for (i = 0; i <= tp->rx_std_ring_mask; i++) {
7264 struct tg3_rx_buffer_desc *rxd;
7266 rxd = &tpr->rx_std[i];
7267 rxd->idx_len = rx_pkt_dma_sz << RXD_LEN_SHIFT;
7268 rxd->type_flags = (RXD_FLAG_END << RXD_FLAGS_SHIFT);
7269 rxd->opaque = (RXD_OPAQUE_RING_STD |
7270 (i << RXD_OPAQUE_INDEX_SHIFT));
7273 /* Now allocate fresh SKBs for each rx ring. */
7274 for (i = 0; i < tp->rx_pending; i++) {
7275 if (tg3_alloc_rx_data(tp, tpr, RXD_OPAQUE_RING_STD, i) < 0) {
7276 netdev_warn(tp->dev,
7277 "Using a smaller RX standard ring. Only "
7278 "%d out of %d buffers were allocated "
7279 "successfully\n", i, tp->rx_pending);
7287 if (!tg3_flag(tp, JUMBO_CAPABLE) || tg3_flag(tp, 5780_CLASS))
7290 memset(tpr->rx_jmb, 0, TG3_RX_JMB_RING_BYTES(tp));
7292 if (!tg3_flag(tp, JUMBO_RING_ENABLE))
7295 for (i = 0; i <= tp->rx_jmb_ring_mask; i++) {
7296 struct tg3_rx_buffer_desc *rxd;
7298 rxd = &tpr->rx_jmb[i].std;
7299 rxd->idx_len = TG3_RX_JMB_DMA_SZ << RXD_LEN_SHIFT;
7300 rxd->type_flags = (RXD_FLAG_END << RXD_FLAGS_SHIFT) |
7302 rxd->opaque = (RXD_OPAQUE_RING_JUMBO |
7303 (i << RXD_OPAQUE_INDEX_SHIFT));
7306 for (i = 0; i < tp->rx_jumbo_pending; i++) {
7307 if (tg3_alloc_rx_data(tp, tpr, RXD_OPAQUE_RING_JUMBO, i) < 0) {
7308 netdev_warn(tp->dev,
7309 "Using a smaller RX jumbo ring. Only %d "
7310 "out of %d buffers were allocated "
7311 "successfully\n", i, tp->rx_jumbo_pending);
7314 tp->rx_jumbo_pending = i;
7323 tg3_rx_prodring_free(tp, tpr);
7327 static void tg3_rx_prodring_fini(struct tg3 *tp,
7328 struct tg3_rx_prodring_set *tpr)
7330 kfree(tpr->rx_std_buffers);
7331 tpr->rx_std_buffers = NULL;
7332 kfree(tpr->rx_jmb_buffers);
7333 tpr->rx_jmb_buffers = NULL;
7335 dma_free_coherent(&tp->pdev->dev, TG3_RX_STD_RING_BYTES(tp),
7336 tpr->rx_std, tpr->rx_std_mapping);
7340 dma_free_coherent(&tp->pdev->dev, TG3_RX_JMB_RING_BYTES(tp),
7341 tpr->rx_jmb, tpr->rx_jmb_mapping);
7346 static int tg3_rx_prodring_init(struct tg3 *tp,
7347 struct tg3_rx_prodring_set *tpr)
7349 tpr->rx_std_buffers = kzalloc(TG3_RX_STD_BUFF_RING_SIZE(tp),
7351 if (!tpr->rx_std_buffers)
7354 tpr->rx_std = dma_alloc_coherent(&tp->pdev->dev,
7355 TG3_RX_STD_RING_BYTES(tp),
7356 &tpr->rx_std_mapping,
7361 if (tg3_flag(tp, JUMBO_CAPABLE) && !tg3_flag(tp, 5780_CLASS)) {
7362 tpr->rx_jmb_buffers = kzalloc(TG3_RX_JMB_BUFF_RING_SIZE(tp),
7364 if (!tpr->rx_jmb_buffers)
7367 tpr->rx_jmb = dma_alloc_coherent(&tp->pdev->dev,
7368 TG3_RX_JMB_RING_BYTES(tp),
7369 &tpr->rx_jmb_mapping,
7378 tg3_rx_prodring_fini(tp, tpr);
7382 /* Free up pending packets in all rx/tx rings.
7384 * The chip has been shut down and the driver detached from
7385 * the networking, so no interrupts or new tx packets will
7386 * end up in the driver. tp->{tx,}lock is not held and we are not
7387 * in an interrupt context and thus may sleep.
7389 static void tg3_free_rings(struct tg3 *tp)
7393 for (j = 0; j < tp->irq_cnt; j++) {
7394 struct tg3_napi *tnapi = &tp->napi[j];
7396 tg3_rx_prodring_free(tp, &tnapi->prodring);
7398 if (!tnapi->tx_buffers)
7401 for (i = 0; i < TG3_TX_RING_SIZE; i++) {
7402 struct sk_buff *skb = tnapi->tx_buffers[i].skb;
7407 tg3_tx_skb_unmap(tnapi, i,
7408 skb_shinfo(skb)->nr_frags - 1);
7410 dev_kfree_skb_any(skb);
7413 netdev_reset_queue(tp->dev);
7416 /* Initialize tx/rx rings for packet processing.
7418 * The chip has been shut down and the driver detached from
7419 * the networking, so no interrupts or new tx packets will
7420 * end up in the driver. tp->{tx,}lock are held and thus
7423 static int tg3_init_rings(struct tg3 *tp)
7427 /* Free up all the SKBs. */
7430 for (i = 0; i < tp->irq_cnt; i++) {
7431 struct tg3_napi *tnapi = &tp->napi[i];
7433 tnapi->last_tag = 0;
7434 tnapi->last_irq_tag = 0;
7435 tnapi->hw_status->status = 0;
7436 tnapi->hw_status->status_tag = 0;
7437 memset(tnapi->hw_status, 0, TG3_HW_STATUS_SIZE);
7442 memset(tnapi->tx_ring, 0, TG3_TX_RING_BYTES);
7444 tnapi->rx_rcb_ptr = 0;
7446 memset(tnapi->rx_rcb, 0, TG3_RX_RCB_RING_BYTES(tp));
7448 if (tg3_rx_prodring_alloc(tp, &tnapi->prodring)) {
7458 * Must not be invoked with interrupt sources disabled and
7459 * the hardware shutdown down.
7461 static void tg3_free_consistent(struct tg3 *tp)
7465 for (i = 0; i < tp->irq_cnt; i++) {
7466 struct tg3_napi *tnapi = &tp->napi[i];
7468 if (tnapi->tx_ring) {
7469 dma_free_coherent(&tp->pdev->dev, TG3_TX_RING_BYTES,
7470 tnapi->tx_ring, tnapi->tx_desc_mapping);
7471 tnapi->tx_ring = NULL;
7474 kfree(tnapi->tx_buffers);
7475 tnapi->tx_buffers = NULL;
7477 if (tnapi->rx_rcb) {
7478 dma_free_coherent(&tp->pdev->dev,
7479 TG3_RX_RCB_RING_BYTES(tp),
7481 tnapi->rx_rcb_mapping);
7482 tnapi->rx_rcb = NULL;
7485 tg3_rx_prodring_fini(tp, &tnapi->prodring);
7487 if (tnapi->hw_status) {
7488 dma_free_coherent(&tp->pdev->dev, TG3_HW_STATUS_SIZE,
7490 tnapi->status_mapping);
7491 tnapi->hw_status = NULL;
7496 dma_free_coherent(&tp->pdev->dev, sizeof(struct tg3_hw_stats),
7497 tp->hw_stats, tp->stats_mapping);
7498 tp->hw_stats = NULL;
7503 * Must not be invoked with interrupt sources disabled and
7504 * the hardware shutdown down. Can sleep.
7506 static int tg3_alloc_consistent(struct tg3 *tp)
7510 tp->hw_stats = dma_alloc_coherent(&tp->pdev->dev,
7511 sizeof(struct tg3_hw_stats),
7517 memset(tp->hw_stats, 0, sizeof(struct tg3_hw_stats));
7519 for (i = 0; i < tp->irq_cnt; i++) {
7520 struct tg3_napi *tnapi = &tp->napi[i];
7521 struct tg3_hw_status *sblk;
7523 tnapi->hw_status = dma_alloc_coherent(&tp->pdev->dev,
7525 &tnapi->status_mapping,
7527 if (!tnapi->hw_status)
7530 memset(tnapi->hw_status, 0, TG3_HW_STATUS_SIZE);
7531 sblk = tnapi->hw_status;
7533 if (tg3_rx_prodring_init(tp, &tnapi->prodring))
7536 /* If multivector TSS is enabled, vector 0 does not handle
7537 * tx interrupts. Don't allocate any resources for it.
7539 if ((!i && !tg3_flag(tp, ENABLE_TSS)) ||
7540 (i && tg3_flag(tp, ENABLE_TSS))) {
7541 tnapi->tx_buffers = kzalloc(
7542 sizeof(struct tg3_tx_ring_info) *
7543 TG3_TX_RING_SIZE, GFP_KERNEL);
7544 if (!tnapi->tx_buffers)
7547 tnapi->tx_ring = dma_alloc_coherent(&tp->pdev->dev,
7549 &tnapi->tx_desc_mapping,
7551 if (!tnapi->tx_ring)
7556 * When RSS is enabled, the status block format changes
7557 * slightly. The "rx_jumbo_consumer", "reserved",
7558 * and "rx_mini_consumer" members get mapped to the
7559 * other three rx return ring producer indexes.
7563 tnapi->rx_rcb_prod_idx = &sblk->idx[0].rx_producer;
7566 tnapi->rx_rcb_prod_idx = &sblk->rx_jumbo_consumer;
7569 tnapi->rx_rcb_prod_idx = &sblk->reserved;
7572 tnapi->rx_rcb_prod_idx = &sblk->rx_mini_consumer;
7577 * If multivector RSS is enabled, vector 0 does not handle
7578 * rx or tx interrupts. Don't allocate any resources for it.
7580 if (!i && tg3_flag(tp, ENABLE_RSS))
7583 tnapi->rx_rcb = dma_alloc_coherent(&tp->pdev->dev,
7584 TG3_RX_RCB_RING_BYTES(tp),
7585 &tnapi->rx_rcb_mapping,
7590 memset(tnapi->rx_rcb, 0, TG3_RX_RCB_RING_BYTES(tp));
7596 tg3_free_consistent(tp);
7600 #define MAX_WAIT_CNT 1000
7602 /* To stop a block, clear the enable bit and poll till it
7603 * clears. tp->lock is held.
7605 static int tg3_stop_block(struct tg3 *tp, unsigned long ofs, u32 enable_bit, int silent)
7610 if (tg3_flag(tp, 5705_PLUS)) {
7617 /* We can't enable/disable these bits of the
7618 * 5705/5750, just say success.
7631 for (i = 0; i < MAX_WAIT_CNT; i++) {
7634 if ((val & enable_bit) == 0)
7638 if (i == MAX_WAIT_CNT && !silent) {
7639 dev_err(&tp->pdev->dev,
7640 "tg3_stop_block timed out, ofs=%lx enable_bit=%x\n",
7648 /* tp->lock is held. */
7649 static int tg3_abort_hw(struct tg3 *tp, int silent)
7653 tg3_disable_ints(tp);
7655 tp->rx_mode &= ~RX_MODE_ENABLE;
7656 tw32_f(MAC_RX_MODE, tp->rx_mode);
7659 err = tg3_stop_block(tp, RCVBDI_MODE, RCVBDI_MODE_ENABLE, silent);
7660 err |= tg3_stop_block(tp, RCVLPC_MODE, RCVLPC_MODE_ENABLE, silent);
7661 err |= tg3_stop_block(tp, RCVLSC_MODE, RCVLSC_MODE_ENABLE, silent);
7662 err |= tg3_stop_block(tp, RCVDBDI_MODE, RCVDBDI_MODE_ENABLE, silent);
7663 err |= tg3_stop_block(tp, RCVDCC_MODE, RCVDCC_MODE_ENABLE, silent);
7664 err |= tg3_stop_block(tp, RCVCC_MODE, RCVCC_MODE_ENABLE, silent);
7666 err |= tg3_stop_block(tp, SNDBDS_MODE, SNDBDS_MODE_ENABLE, silent);
7667 err |= tg3_stop_block(tp, SNDBDI_MODE, SNDBDI_MODE_ENABLE, silent);
7668 err |= tg3_stop_block(tp, SNDDATAI_MODE, SNDDATAI_MODE_ENABLE, silent);
7669 err |= tg3_stop_block(tp, RDMAC_MODE, RDMAC_MODE_ENABLE, silent);
7670 err |= tg3_stop_block(tp, SNDDATAC_MODE, SNDDATAC_MODE_ENABLE, silent);
7671 err |= tg3_stop_block(tp, DMAC_MODE, DMAC_MODE_ENABLE, silent);
7672 err |= tg3_stop_block(tp, SNDBDC_MODE, SNDBDC_MODE_ENABLE, silent);
7674 tp->mac_mode &= ~MAC_MODE_TDE_ENABLE;
7675 tw32_f(MAC_MODE, tp->mac_mode);
7678 tp->tx_mode &= ~TX_MODE_ENABLE;
7679 tw32_f(MAC_TX_MODE, tp->tx_mode);
7681 for (i = 0; i < MAX_WAIT_CNT; i++) {
7683 if (!(tr32(MAC_TX_MODE) & TX_MODE_ENABLE))
7686 if (i >= MAX_WAIT_CNT) {
7687 dev_err(&tp->pdev->dev,
7688 "%s timed out, TX_MODE_ENABLE will not clear "
7689 "MAC_TX_MODE=%08x\n", __func__, tr32(MAC_TX_MODE));
7693 err |= tg3_stop_block(tp, HOSTCC_MODE, HOSTCC_MODE_ENABLE, silent);
7694 err |= tg3_stop_block(tp, WDMAC_MODE, WDMAC_MODE_ENABLE, silent);
7695 err |= tg3_stop_block(tp, MBFREE_MODE, MBFREE_MODE_ENABLE, silent);
7697 tw32(FTQ_RESET, 0xffffffff);
7698 tw32(FTQ_RESET, 0x00000000);
7700 err |= tg3_stop_block(tp, BUFMGR_MODE, BUFMGR_MODE_ENABLE, silent);
7701 err |= tg3_stop_block(tp, MEMARB_MODE, MEMARB_MODE_ENABLE, silent);
7703 for (i = 0; i < tp->irq_cnt; i++) {
7704 struct tg3_napi *tnapi = &tp->napi[i];
7705 if (tnapi->hw_status)
7706 memset(tnapi->hw_status, 0, TG3_HW_STATUS_SIZE);
7712 /* Save PCI command register before chip reset */
7713 static void tg3_save_pci_state(struct tg3 *tp)
7715 pci_read_config_word(tp->pdev, PCI_COMMAND, &tp->pci_cmd);
7718 /* Restore PCI state after chip reset */
7719 static void tg3_restore_pci_state(struct tg3 *tp)
7723 /* Re-enable indirect register accesses. */
7724 pci_write_config_dword(tp->pdev, TG3PCI_MISC_HOST_CTRL,
7725 tp->misc_host_ctrl);
7727 /* Set MAX PCI retry to zero. */
7728 val = (PCISTATE_ROM_ENABLE | PCISTATE_ROM_RETRY_ENABLE);
7729 if (tp->pci_chip_rev_id == CHIPREV_ID_5704_A0 &&
7730 tg3_flag(tp, PCIX_MODE))
7731 val |= PCISTATE_RETRY_SAME_DMA;
7732 /* Allow reads and writes to the APE register and memory space. */
7733 if (tg3_flag(tp, ENABLE_APE))
7734 val |= PCISTATE_ALLOW_APE_CTLSPC_WR |
7735 PCISTATE_ALLOW_APE_SHMEM_WR |
7736 PCISTATE_ALLOW_APE_PSPACE_WR;
7737 pci_write_config_dword(tp->pdev, TG3PCI_PCISTATE, val);
7739 pci_write_config_word(tp->pdev, PCI_COMMAND, tp->pci_cmd);
7741 if (!tg3_flag(tp, PCI_EXPRESS)) {
7742 pci_write_config_byte(tp->pdev, PCI_CACHE_LINE_SIZE,
7743 tp->pci_cacheline_sz);
7744 pci_write_config_byte(tp->pdev, PCI_LATENCY_TIMER,
7748 /* Make sure PCI-X relaxed ordering bit is clear. */
7749 if (tg3_flag(tp, PCIX_MODE)) {
7752 pci_read_config_word(tp->pdev, tp->pcix_cap + PCI_X_CMD,
7754 pcix_cmd &= ~PCI_X_CMD_ERO;
7755 pci_write_config_word(tp->pdev, tp->pcix_cap + PCI_X_CMD,
7759 if (tg3_flag(tp, 5780_CLASS)) {
7761 /* Chip reset on 5780 will reset MSI enable bit,
7762 * so need to restore it.
7764 if (tg3_flag(tp, USING_MSI)) {
7767 pci_read_config_word(tp->pdev,
7768 tp->msi_cap + PCI_MSI_FLAGS,
7770 pci_write_config_word(tp->pdev,
7771 tp->msi_cap + PCI_MSI_FLAGS,
7772 ctrl | PCI_MSI_FLAGS_ENABLE);
7773 val = tr32(MSGINT_MODE);
7774 tw32(MSGINT_MODE, val | MSGINT_MODE_ENABLE);
7779 /* tp->lock is held. */
7780 static int tg3_chip_reset(struct tg3 *tp)
7783 void (*write_op)(struct tg3 *, u32, u32);
7788 tg3_ape_lock(tp, TG3_APE_LOCK_GRC);
7790 /* No matching tg3_nvram_unlock() after this because
7791 * chip reset below will undo the nvram lock.
7793 tp->nvram_lock_cnt = 0;
7795 /* GRC_MISC_CFG core clock reset will clear the memory
7796 * enable bit in PCI register 4 and the MSI enable bit
7797 * on some chips, so we save relevant registers here.
7799 tg3_save_pci_state(tp);
7801 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5752 ||
7802 tg3_flag(tp, 5755_PLUS))
7803 tw32(GRC_FASTBOOT_PC, 0);
7806 * We must avoid the readl() that normally takes place.
7807 * It locks machines, causes machine checks, and other
7808 * fun things. So, temporarily disable the 5701
7809 * hardware workaround, while we do the reset.
7811 write_op = tp->write32;
7812 if (write_op == tg3_write_flush_reg32)
7813 tp->write32 = tg3_write32;
7815 /* Prevent the irq handler from reading or writing PCI registers
7816 * during chip reset when the memory enable bit in the PCI command
7817 * register may be cleared. The chip does not generate interrupt
7818 * at this time, but the irq handler may still be called due to irq
7819 * sharing or irqpoll.
7821 tg3_flag_set(tp, CHIP_RESETTING);
7822 for (i = 0; i < tp->irq_cnt; i++) {
7823 struct tg3_napi *tnapi = &tp->napi[i];
7824 if (tnapi->hw_status) {
7825 tnapi->hw_status->status = 0;
7826 tnapi->hw_status->status_tag = 0;
7828 tnapi->last_tag = 0;
7829 tnapi->last_irq_tag = 0;
7833 for (i = 0; i < tp->irq_cnt; i++)
7834 synchronize_irq(tp->napi[i].irq_vec);
7836 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57780) {
7837 val = tr32(TG3_PCIE_LNKCTL) & ~TG3_PCIE_LNKCTL_L1_PLL_PD_EN;
7838 tw32(TG3_PCIE_LNKCTL, val | TG3_PCIE_LNKCTL_L1_PLL_PD_DIS);
7842 val = GRC_MISC_CFG_CORECLK_RESET;
7844 if (tg3_flag(tp, PCI_EXPRESS)) {
7845 /* Force PCIe 1.0a mode */
7846 if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5785 &&
7847 !tg3_flag(tp, 57765_PLUS) &&
7848 tr32(TG3_PCIE_PHY_TSTCTL) ==
7849 (TG3_PCIE_PHY_TSTCTL_PCIE10 | TG3_PCIE_PHY_TSTCTL_PSCRAM))
7850 tw32(TG3_PCIE_PHY_TSTCTL, TG3_PCIE_PHY_TSTCTL_PSCRAM);
7852 if (tp->pci_chip_rev_id != CHIPREV_ID_5750_A0) {
7853 tw32(GRC_MISC_CFG, (1 << 29));
7858 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
7859 tw32(VCPU_STATUS, tr32(VCPU_STATUS) | VCPU_STATUS_DRV_RESET);
7860 tw32(GRC_VCPU_EXT_CTRL,
7861 tr32(GRC_VCPU_EXT_CTRL) & ~GRC_VCPU_EXT_CTRL_HALT_CPU);
7864 /* Manage gphy power for all CPMU absent PCIe devices. */
7865 if (tg3_flag(tp, 5705_PLUS) && !tg3_flag(tp, CPMU_PRESENT))
7866 val |= GRC_MISC_CFG_KEEP_GPHY_POWER;
7868 tw32(GRC_MISC_CFG, val);
7870 /* restore 5701 hardware bug workaround write method */
7871 tp->write32 = write_op;
7873 /* Unfortunately, we have to delay before the PCI read back.
7874 * Some 575X chips even will not respond to a PCI cfg access
7875 * when the reset command is given to the chip.
7877 * How do these hardware designers expect things to work
7878 * properly if the PCI write is posted for a long period
7879 * of time? It is always necessary to have some method by
7880 * which a register read back can occur to push the write
7881 * out which does the reset.
7883 * For most tg3 variants the trick below was working.
7888 /* Flush PCI posted writes. The normal MMIO registers
7889 * are inaccessible at this time so this is the only
7890 * way to make this reliably (actually, this is no longer
7891 * the case, see above). I tried to use indirect
7892 * register read/write but this upset some 5701 variants.
7894 pci_read_config_dword(tp->pdev, PCI_COMMAND, &val);
7898 if (tg3_flag(tp, PCI_EXPRESS) && pci_pcie_cap(tp->pdev)) {
7901 if (tp->pci_chip_rev_id == CHIPREV_ID_5750_A0) {
7905 /* Wait for link training to complete. */
7906 for (i = 0; i < 5000; i++)
7909 pci_read_config_dword(tp->pdev, 0xc4, &cfg_val);
7910 pci_write_config_dword(tp->pdev, 0xc4,
7911 cfg_val | (1 << 15));
7914 /* Clear the "no snoop" and "relaxed ordering" bits. */
7915 pci_read_config_word(tp->pdev,
7916 pci_pcie_cap(tp->pdev) + PCI_EXP_DEVCTL,
7918 val16 &= ~(PCI_EXP_DEVCTL_RELAX_EN |
7919 PCI_EXP_DEVCTL_NOSNOOP_EN);
7921 * Older PCIe devices only support the 128 byte
7922 * MPS setting. Enforce the restriction.
7924 if (!tg3_flag(tp, CPMU_PRESENT))
7925 val16 &= ~PCI_EXP_DEVCTL_PAYLOAD;
7926 pci_write_config_word(tp->pdev,
7927 pci_pcie_cap(tp->pdev) + PCI_EXP_DEVCTL,
7930 /* Clear error status */
7931 pci_write_config_word(tp->pdev,
7932 pci_pcie_cap(tp->pdev) + PCI_EXP_DEVSTA,
7933 PCI_EXP_DEVSTA_CED |
7934 PCI_EXP_DEVSTA_NFED |
7935 PCI_EXP_DEVSTA_FED |
7936 PCI_EXP_DEVSTA_URD);
7939 tg3_restore_pci_state(tp);
7941 tg3_flag_clear(tp, CHIP_RESETTING);
7942 tg3_flag_clear(tp, ERROR_PROCESSED);
7945 if (tg3_flag(tp, 5780_CLASS))
7946 val = tr32(MEMARB_MODE);
7947 tw32(MEMARB_MODE, val | MEMARB_MODE_ENABLE);
7949 if (tp->pci_chip_rev_id == CHIPREV_ID_5750_A3) {
7951 tw32(0x5000, 0x400);
7954 tw32(GRC_MODE, tp->grc_mode);
7956 if (tp->pci_chip_rev_id == CHIPREV_ID_5705_A0) {
7959 tw32(0xc4, val | (1 << 15));
7962 if ((tp->nic_sram_data_cfg & NIC_SRAM_DATA_CFG_MINI_PCI) != 0 &&
7963 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705) {
7964 tp->pci_clock_ctrl |= CLOCK_CTRL_CLKRUN_OENABLE;
7965 if (tp->pci_chip_rev_id == CHIPREV_ID_5705_A0)
7966 tp->pci_clock_ctrl |= CLOCK_CTRL_FORCE_CLKRUN;
7967 tw32(TG3PCI_CLOCK_CTRL, tp->pci_clock_ctrl);
7970 if (tp->phy_flags & TG3_PHYFLG_PHY_SERDES) {
7971 tp->mac_mode = MAC_MODE_PORT_MODE_TBI;
7973 } else if (tp->phy_flags & TG3_PHYFLG_MII_SERDES) {
7974 tp->mac_mode = MAC_MODE_PORT_MODE_GMII;
7979 tw32_f(MAC_MODE, val);
7982 tg3_ape_unlock(tp, TG3_APE_LOCK_GRC);
7984 err = tg3_poll_fw(tp);
7990 if (tg3_flag(tp, PCI_EXPRESS) &&
7991 tp->pci_chip_rev_id != CHIPREV_ID_5750_A0 &&
7992 GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5785 &&
7993 !tg3_flag(tp, 57765_PLUS)) {
7996 tw32(0x7c00, val | (1 << 25));
7999 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5720) {
8000 val = tr32(TG3_CPMU_CLCK_ORIDE);
8001 tw32(TG3_CPMU_CLCK_ORIDE, val & ~CPMU_CLCK_ORIDE_MAC_ORIDE_EN);
8004 /* Reprobe ASF enable state. */
8005 tg3_flag_clear(tp, ENABLE_ASF);
8006 tg3_flag_clear(tp, ASF_NEW_HANDSHAKE);
8007 tg3_read_mem(tp, NIC_SRAM_DATA_SIG, &val);
8008 if (val == NIC_SRAM_DATA_SIG_MAGIC) {
8011 tg3_read_mem(tp, NIC_SRAM_DATA_CFG, &nic_cfg);
8012 if (nic_cfg & NIC_SRAM_DATA_CFG_ASF_ENABLE) {
8013 tg3_flag_set(tp, ENABLE_ASF);
8014 tp->last_event_jiffies = jiffies;
8015 if (tg3_flag(tp, 5750_PLUS))
8016 tg3_flag_set(tp, ASF_NEW_HANDSHAKE);
8023 static struct rtnl_link_stats64 *tg3_get_stats64(struct net_device *,
8024 struct rtnl_link_stats64 *);
8025 static struct tg3_ethtool_stats *tg3_get_estats(struct tg3 *,
8026 struct tg3_ethtool_stats *);
8028 /* tp->lock is held. */
8029 static int tg3_halt(struct tg3 *tp, int kind, int silent)
8035 tg3_write_sig_pre_reset(tp, kind);
8037 tg3_abort_hw(tp, silent);
8038 err = tg3_chip_reset(tp);
8040 __tg3_set_mac_addr(tp, 0);
8042 tg3_write_sig_legacy(tp, kind);
8043 tg3_write_sig_post_reset(tp, kind);
8046 /* Save the stats across chip resets... */
8047 tg3_get_stats64(tp->dev, &tp->net_stats_prev),
8048 tg3_get_estats(tp, &tp->estats_prev);
8050 /* And make sure the next sample is new data */
8051 memset(tp->hw_stats, 0, sizeof(struct tg3_hw_stats));
8060 static int tg3_set_mac_addr(struct net_device *dev, void *p)
8062 struct tg3 *tp = netdev_priv(dev);
8063 struct sockaddr *addr = p;
8064 int err = 0, skip_mac_1 = 0;
8066 if (!is_valid_ether_addr(addr->sa_data))
8069 memcpy(dev->dev_addr, addr->sa_data, dev->addr_len);
8071 if (!netif_running(dev))
8074 if (tg3_flag(tp, ENABLE_ASF)) {
8075 u32 addr0_high, addr0_low, addr1_high, addr1_low;
8077 addr0_high = tr32(MAC_ADDR_0_HIGH);
8078 addr0_low = tr32(MAC_ADDR_0_LOW);
8079 addr1_high = tr32(MAC_ADDR_1_HIGH);
8080 addr1_low = tr32(MAC_ADDR_1_LOW);
8082 /* Skip MAC addr 1 if ASF is using it. */
8083 if ((addr0_high != addr1_high || addr0_low != addr1_low) &&
8084 !(addr1_high == 0 && addr1_low == 0))
8087 spin_lock_bh(&tp->lock);
8088 __tg3_set_mac_addr(tp, skip_mac_1);
8089 spin_unlock_bh(&tp->lock);
8094 /* tp->lock is held. */
8095 static void tg3_set_bdinfo(struct tg3 *tp, u32 bdinfo_addr,
8096 dma_addr_t mapping, u32 maxlen_flags,
8100 (bdinfo_addr + TG3_BDINFO_HOST_ADDR + TG3_64BIT_REG_HIGH),
8101 ((u64) mapping >> 32));
8103 (bdinfo_addr + TG3_BDINFO_HOST_ADDR + TG3_64BIT_REG_LOW),
8104 ((u64) mapping & 0xffffffff));
8106 (bdinfo_addr + TG3_BDINFO_MAXLEN_FLAGS),
8109 if (!tg3_flag(tp, 5705_PLUS))
8111 (bdinfo_addr + TG3_BDINFO_NIC_ADDR),
8115 static void __tg3_set_coalesce(struct tg3 *tp, struct ethtool_coalesce *ec)
8119 if (!tg3_flag(tp, ENABLE_TSS)) {
8120 tw32(HOSTCC_TXCOL_TICKS, ec->tx_coalesce_usecs);
8121 tw32(HOSTCC_TXMAX_FRAMES, ec->tx_max_coalesced_frames);
8122 tw32(HOSTCC_TXCOAL_MAXF_INT, ec->tx_max_coalesced_frames_irq);
8124 tw32(HOSTCC_TXCOL_TICKS, 0);
8125 tw32(HOSTCC_TXMAX_FRAMES, 0);
8126 tw32(HOSTCC_TXCOAL_MAXF_INT, 0);
8129 if (!tg3_flag(tp, ENABLE_RSS)) {
8130 tw32(HOSTCC_RXCOL_TICKS, ec->rx_coalesce_usecs);
8131 tw32(HOSTCC_RXMAX_FRAMES, ec->rx_max_coalesced_frames);
8132 tw32(HOSTCC_RXCOAL_MAXF_INT, ec->rx_max_coalesced_frames_irq);
8134 tw32(HOSTCC_RXCOL_TICKS, 0);
8135 tw32(HOSTCC_RXMAX_FRAMES, 0);
8136 tw32(HOSTCC_RXCOAL_MAXF_INT, 0);
8139 if (!tg3_flag(tp, 5705_PLUS)) {
8140 u32 val = ec->stats_block_coalesce_usecs;
8142 tw32(HOSTCC_RXCOAL_TICK_INT, ec->rx_coalesce_usecs_irq);
8143 tw32(HOSTCC_TXCOAL_TICK_INT, ec->tx_coalesce_usecs_irq);
8145 if (!netif_carrier_ok(tp->dev))
8148 tw32(HOSTCC_STAT_COAL_TICKS, val);
8151 for (i = 0; i < tp->irq_cnt - 1; i++) {
8154 reg = HOSTCC_RXCOL_TICKS_VEC1 + i * 0x18;
8155 tw32(reg, ec->rx_coalesce_usecs);
8156 reg = HOSTCC_RXMAX_FRAMES_VEC1 + i * 0x18;
8157 tw32(reg, ec->rx_max_coalesced_frames);
8158 reg = HOSTCC_RXCOAL_MAXF_INT_VEC1 + i * 0x18;
8159 tw32(reg, ec->rx_max_coalesced_frames_irq);
8161 if (tg3_flag(tp, ENABLE_TSS)) {
8162 reg = HOSTCC_TXCOL_TICKS_VEC1 + i * 0x18;
8163 tw32(reg, ec->tx_coalesce_usecs);
8164 reg = HOSTCC_TXMAX_FRAMES_VEC1 + i * 0x18;
8165 tw32(reg, ec->tx_max_coalesced_frames);
8166 reg = HOSTCC_TXCOAL_MAXF_INT_VEC1 + i * 0x18;
8167 tw32(reg, ec->tx_max_coalesced_frames_irq);
8171 for (; i < tp->irq_max - 1; i++) {
8172 tw32(HOSTCC_RXCOL_TICKS_VEC1 + i * 0x18, 0);
8173 tw32(HOSTCC_RXMAX_FRAMES_VEC1 + i * 0x18, 0);
8174 tw32(HOSTCC_RXCOAL_MAXF_INT_VEC1 + i * 0x18, 0);
8176 if (tg3_flag(tp, ENABLE_TSS)) {
8177 tw32(HOSTCC_TXCOL_TICKS_VEC1 + i * 0x18, 0);
8178 tw32(HOSTCC_TXMAX_FRAMES_VEC1 + i * 0x18, 0);
8179 tw32(HOSTCC_TXCOAL_MAXF_INT_VEC1 + i * 0x18, 0);
8184 /* tp->lock is held. */
8185 static void tg3_rings_reset(struct tg3 *tp)
8188 u32 stblk, txrcb, rxrcb, limit;
8189 struct tg3_napi *tnapi = &tp->napi[0];
8191 /* Disable all transmit rings but the first. */
8192 if (!tg3_flag(tp, 5705_PLUS))
8193 limit = NIC_SRAM_SEND_RCB + TG3_BDINFO_SIZE * 16;
8194 else if (tg3_flag(tp, 5717_PLUS))
8195 limit = NIC_SRAM_SEND_RCB + TG3_BDINFO_SIZE * 4;
8196 else if (tg3_flag(tp, 57765_CLASS))
8197 limit = NIC_SRAM_SEND_RCB + TG3_BDINFO_SIZE * 2;
8199 limit = NIC_SRAM_SEND_RCB + TG3_BDINFO_SIZE;
8201 for (txrcb = NIC_SRAM_SEND_RCB + TG3_BDINFO_SIZE;
8202 txrcb < limit; txrcb += TG3_BDINFO_SIZE)
8203 tg3_write_mem(tp, txrcb + TG3_BDINFO_MAXLEN_FLAGS,
8204 BDINFO_FLAGS_DISABLED);
8207 /* Disable all receive return rings but the first. */
8208 if (tg3_flag(tp, 5717_PLUS))
8209 limit = NIC_SRAM_RCV_RET_RCB + TG3_BDINFO_SIZE * 17;
8210 else if (!tg3_flag(tp, 5705_PLUS))
8211 limit = NIC_SRAM_RCV_RET_RCB + TG3_BDINFO_SIZE * 16;
8212 else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5755 ||
8213 tg3_flag(tp, 57765_CLASS))
8214 limit = NIC_SRAM_RCV_RET_RCB + TG3_BDINFO_SIZE * 4;
8216 limit = NIC_SRAM_RCV_RET_RCB + TG3_BDINFO_SIZE;
8218 for (rxrcb = NIC_SRAM_RCV_RET_RCB + TG3_BDINFO_SIZE;
8219 rxrcb < limit; rxrcb += TG3_BDINFO_SIZE)
8220 tg3_write_mem(tp, rxrcb + TG3_BDINFO_MAXLEN_FLAGS,
8221 BDINFO_FLAGS_DISABLED);
8223 /* Disable interrupts */
8224 tw32_mailbox_f(tp->napi[0].int_mbox, 1);
8225 tp->napi[0].chk_msi_cnt = 0;
8226 tp->napi[0].last_rx_cons = 0;
8227 tp->napi[0].last_tx_cons = 0;
8229 /* Zero mailbox registers. */
8230 if (tg3_flag(tp, SUPPORT_MSIX)) {
8231 for (i = 1; i < tp->irq_max; i++) {
8232 tp->napi[i].tx_prod = 0;
8233 tp->napi[i].tx_cons = 0;
8234 if (tg3_flag(tp, ENABLE_TSS))
8235 tw32_mailbox(tp->napi[i].prodmbox, 0);
8236 tw32_rx_mbox(tp->napi[i].consmbox, 0);
8237 tw32_mailbox_f(tp->napi[i].int_mbox, 1);
8238 tp->napi[i].chk_msi_cnt = 0;
8239 tp->napi[i].last_rx_cons = 0;
8240 tp->napi[i].last_tx_cons = 0;
8242 if (!tg3_flag(tp, ENABLE_TSS))
8243 tw32_mailbox(tp->napi[0].prodmbox, 0);
8245 tp->napi[0].tx_prod = 0;
8246 tp->napi[0].tx_cons = 0;
8247 tw32_mailbox(tp->napi[0].prodmbox, 0);
8248 tw32_rx_mbox(tp->napi[0].consmbox, 0);
8251 /* Make sure the NIC-based send BD rings are disabled. */
8252 if (!tg3_flag(tp, 5705_PLUS)) {
8253 u32 mbox = MAILBOX_SNDNIC_PROD_IDX_0 + TG3_64BIT_REG_LOW;
8254 for (i = 0; i < 16; i++)
8255 tw32_tx_mbox(mbox + i * 8, 0);
8258 txrcb = NIC_SRAM_SEND_RCB;
8259 rxrcb = NIC_SRAM_RCV_RET_RCB;
8261 /* Clear status block in ram. */
8262 memset(tnapi->hw_status, 0, TG3_HW_STATUS_SIZE);
8264 /* Set status block DMA address */
8265 tw32(HOSTCC_STATUS_BLK_HOST_ADDR + TG3_64BIT_REG_HIGH,
8266 ((u64) tnapi->status_mapping >> 32));
8267 tw32(HOSTCC_STATUS_BLK_HOST_ADDR + TG3_64BIT_REG_LOW,
8268 ((u64) tnapi->status_mapping & 0xffffffff));
8270 if (tnapi->tx_ring) {
8271 tg3_set_bdinfo(tp, txrcb, tnapi->tx_desc_mapping,
8272 (TG3_TX_RING_SIZE <<
8273 BDINFO_FLAGS_MAXLEN_SHIFT),
8274 NIC_SRAM_TX_BUFFER_DESC);
8275 txrcb += TG3_BDINFO_SIZE;
8278 if (tnapi->rx_rcb) {
8279 tg3_set_bdinfo(tp, rxrcb, tnapi->rx_rcb_mapping,
8280 (tp->rx_ret_ring_mask + 1) <<
8281 BDINFO_FLAGS_MAXLEN_SHIFT, 0);
8282 rxrcb += TG3_BDINFO_SIZE;
8285 stblk = HOSTCC_STATBLCK_RING1;
8287 for (i = 1, tnapi++; i < tp->irq_cnt; i++, tnapi++) {
8288 u64 mapping = (u64)tnapi->status_mapping;
8289 tw32(stblk + TG3_64BIT_REG_HIGH, mapping >> 32);
8290 tw32(stblk + TG3_64BIT_REG_LOW, mapping & 0xffffffff);
8292 /* Clear status block in ram. */
8293 memset(tnapi->hw_status, 0, TG3_HW_STATUS_SIZE);
8295 if (tnapi->tx_ring) {
8296 tg3_set_bdinfo(tp, txrcb, tnapi->tx_desc_mapping,
8297 (TG3_TX_RING_SIZE <<
8298 BDINFO_FLAGS_MAXLEN_SHIFT),
8299 NIC_SRAM_TX_BUFFER_DESC);
8300 txrcb += TG3_BDINFO_SIZE;
8303 tg3_set_bdinfo(tp, rxrcb, tnapi->rx_rcb_mapping,
8304 ((tp->rx_ret_ring_mask + 1) <<
8305 BDINFO_FLAGS_MAXLEN_SHIFT), 0);
8308 rxrcb += TG3_BDINFO_SIZE;
8312 static void tg3_setup_rxbd_thresholds(struct tg3 *tp)
8314 u32 val, bdcache_maxcnt, host_rep_thresh, nic_rep_thresh;
8316 if (!tg3_flag(tp, 5750_PLUS) ||
8317 tg3_flag(tp, 5780_CLASS) ||
8318 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5750 ||
8319 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5752 ||
8320 tg3_flag(tp, 57765_PLUS))
8321 bdcache_maxcnt = TG3_SRAM_RX_STD_BDCACHE_SIZE_5700;
8322 else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5755 ||
8323 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5787)
8324 bdcache_maxcnt = TG3_SRAM_RX_STD_BDCACHE_SIZE_5755;
8326 bdcache_maxcnt = TG3_SRAM_RX_STD_BDCACHE_SIZE_5906;
8328 nic_rep_thresh = min(bdcache_maxcnt / 2, tp->rx_std_max_post);
8329 host_rep_thresh = max_t(u32, tp->rx_pending / 8, 1);
8331 val = min(nic_rep_thresh, host_rep_thresh);
8332 tw32(RCVBDI_STD_THRESH, val);
8334 if (tg3_flag(tp, 57765_PLUS))
8335 tw32(STD_REPLENISH_LWM, bdcache_maxcnt);
8337 if (!tg3_flag(tp, JUMBO_CAPABLE) || tg3_flag(tp, 5780_CLASS))
8340 bdcache_maxcnt = TG3_SRAM_RX_JMB_BDCACHE_SIZE_5700;
8342 host_rep_thresh = max_t(u32, tp->rx_jumbo_pending / 8, 1);
8344 val = min(bdcache_maxcnt / 2, host_rep_thresh);
8345 tw32(RCVBDI_JUMBO_THRESH, val);
8347 if (tg3_flag(tp, 57765_PLUS))
8348 tw32(JMB_REPLENISH_LWM, bdcache_maxcnt);
8351 static inline u32 calc_crc(unsigned char *buf, int len)
8359 for (j = 0; j < len; j++) {
8362 for (k = 0; k < 8; k++) {
8375 static void tg3_set_multi(struct tg3 *tp, unsigned int accept_all)
8377 /* accept or reject all multicast frames */
8378 tw32(MAC_HASH_REG_0, accept_all ? 0xffffffff : 0);
8379 tw32(MAC_HASH_REG_1, accept_all ? 0xffffffff : 0);
8380 tw32(MAC_HASH_REG_2, accept_all ? 0xffffffff : 0);
8381 tw32(MAC_HASH_REG_3, accept_all ? 0xffffffff : 0);
8384 static void __tg3_set_rx_mode(struct net_device *dev)
8386 struct tg3 *tp = netdev_priv(dev);
8389 rx_mode = tp->rx_mode & ~(RX_MODE_PROMISC |
8390 RX_MODE_KEEP_VLAN_TAG);
8392 #if !defined(CONFIG_VLAN_8021Q) && !defined(CONFIG_VLAN_8021Q_MODULE)
8393 /* When ASF is in use, we always keep the RX_MODE_KEEP_VLAN_TAG
8396 if (!tg3_flag(tp, ENABLE_ASF))
8397 rx_mode |= RX_MODE_KEEP_VLAN_TAG;
8400 if (dev->flags & IFF_PROMISC) {
8401 /* Promiscuous mode. */
8402 rx_mode |= RX_MODE_PROMISC;
8403 } else if (dev->flags & IFF_ALLMULTI) {
8404 /* Accept all multicast. */
8405 tg3_set_multi(tp, 1);
8406 } else if (netdev_mc_empty(dev)) {
8407 /* Reject all multicast. */
8408 tg3_set_multi(tp, 0);
8410 /* Accept one or more multicast(s). */
8411 struct netdev_hw_addr *ha;
8412 u32 mc_filter[4] = { 0, };
8417 netdev_for_each_mc_addr(ha, dev) {
8418 crc = calc_crc(ha->addr, ETH_ALEN);
8420 regidx = (bit & 0x60) >> 5;
8422 mc_filter[regidx] |= (1 << bit);
8425 tw32(MAC_HASH_REG_0, mc_filter[0]);
8426 tw32(MAC_HASH_REG_1, mc_filter[1]);
8427 tw32(MAC_HASH_REG_2, mc_filter[2]);
8428 tw32(MAC_HASH_REG_3, mc_filter[3]);
8431 if (rx_mode != tp->rx_mode) {
8432 tp->rx_mode = rx_mode;
8433 tw32_f(MAC_RX_MODE, rx_mode);
8438 static void tg3_rss_init_dflt_indir_tbl(struct tg3 *tp)
8442 for (i = 0; i < TG3_RSS_INDIR_TBL_SIZE; i++)
8443 tp->rss_ind_tbl[i] =
8444 ethtool_rxfh_indir_default(i, tp->irq_cnt - 1);
8447 static void tg3_rss_check_indir_tbl(struct tg3 *tp)
8451 if (!tg3_flag(tp, SUPPORT_MSIX))
8454 if (tp->irq_cnt <= 2) {
8455 memset(&tp->rss_ind_tbl[0], 0, sizeof(tp->rss_ind_tbl));
8459 /* Validate table against current IRQ count */
8460 for (i = 0; i < TG3_RSS_INDIR_TBL_SIZE; i++) {
8461 if (tp->rss_ind_tbl[i] >= tp->irq_cnt - 1)
8465 if (i != TG3_RSS_INDIR_TBL_SIZE)
8466 tg3_rss_init_dflt_indir_tbl(tp);
8469 static void tg3_rss_write_indir_tbl(struct tg3 *tp)
8472 u32 reg = MAC_RSS_INDIR_TBL_0;
8474 while (i < TG3_RSS_INDIR_TBL_SIZE) {
8475 u32 val = tp->rss_ind_tbl[i];
8477 for (; i % 8; i++) {
8479 val |= tp->rss_ind_tbl[i];
8486 /* tp->lock is held. */
8487 static int tg3_reset_hw(struct tg3 *tp, int reset_phy)
8489 u32 val, rdmac_mode;
8491 struct tg3_rx_prodring_set *tpr = &tp->napi[0].prodring;
8493 tg3_disable_ints(tp);
8497 tg3_write_sig_pre_reset(tp, RESET_KIND_INIT);
8499 if (tg3_flag(tp, INIT_COMPLETE))
8500 tg3_abort_hw(tp, 1);
8502 /* Enable MAC control of LPI */
8503 if (tp->phy_flags & TG3_PHYFLG_EEE_CAP) {
8504 tw32_f(TG3_CPMU_EEE_LNKIDL_CTRL,
8505 TG3_CPMU_EEE_LNKIDL_PCIE_NL0 |
8506 TG3_CPMU_EEE_LNKIDL_UART_IDL);
8508 tw32_f(TG3_CPMU_EEE_CTRL,
8509 TG3_CPMU_EEE_CTRL_EXIT_20_1_US);
8511 val = TG3_CPMU_EEEMD_ERLY_L1_XIT_DET |
8512 TG3_CPMU_EEEMD_LPI_IN_TX |
8513 TG3_CPMU_EEEMD_LPI_IN_RX |
8514 TG3_CPMU_EEEMD_EEE_ENABLE;
8516 if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5717)
8517 val |= TG3_CPMU_EEEMD_SND_IDX_DET_EN;
8519 if (tg3_flag(tp, ENABLE_APE))
8520 val |= TG3_CPMU_EEEMD_APE_TX_DET_EN;
8522 tw32_f(TG3_CPMU_EEE_MODE, val);
8524 tw32_f(TG3_CPMU_EEE_DBTMR1,
8525 TG3_CPMU_DBTMR1_PCIEXIT_2047US |
8526 TG3_CPMU_DBTMR1_LNKIDLE_2047US);
8528 tw32_f(TG3_CPMU_EEE_DBTMR2,
8529 TG3_CPMU_DBTMR2_APE_TX_2047US |
8530 TG3_CPMU_DBTMR2_TXIDXEQ_2047US);
8536 err = tg3_chip_reset(tp);
8540 tg3_write_sig_legacy(tp, RESET_KIND_INIT);
8542 if (GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5784_AX) {
8543 val = tr32(TG3_CPMU_CTRL);
8544 val &= ~(CPMU_CTRL_LINK_AWARE_MODE | CPMU_CTRL_LINK_IDLE_MODE);
8545 tw32(TG3_CPMU_CTRL, val);
8547 val = tr32(TG3_CPMU_LSPD_10MB_CLK);
8548 val &= ~CPMU_LSPD_10MB_MACCLK_MASK;
8549 val |= CPMU_LSPD_10MB_MACCLK_6_25;
8550 tw32(TG3_CPMU_LSPD_10MB_CLK, val);
8552 val = tr32(TG3_CPMU_LNK_AWARE_PWRMD);
8553 val &= ~CPMU_LNK_AWARE_MACCLK_MASK;
8554 val |= CPMU_LNK_AWARE_MACCLK_6_25;
8555 tw32(TG3_CPMU_LNK_AWARE_PWRMD, val);
8557 val = tr32(TG3_CPMU_HST_ACC);
8558 val &= ~CPMU_HST_ACC_MACCLK_MASK;
8559 val |= CPMU_HST_ACC_MACCLK_6_25;
8560 tw32(TG3_CPMU_HST_ACC, val);
8563 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57780) {
8564 val = tr32(PCIE_PWR_MGMT_THRESH) & ~PCIE_PWR_MGMT_L1_THRESH_MSK;
8565 val |= PCIE_PWR_MGMT_EXT_ASPM_TMR_EN |
8566 PCIE_PWR_MGMT_L1_THRESH_4MS;
8567 tw32(PCIE_PWR_MGMT_THRESH, val);
8569 val = tr32(TG3_PCIE_EIDLE_DELAY) & ~TG3_PCIE_EIDLE_DELAY_MASK;
8570 tw32(TG3_PCIE_EIDLE_DELAY, val | TG3_PCIE_EIDLE_DELAY_13_CLKS);
8572 tw32(TG3_CORR_ERR_STAT, TG3_CORR_ERR_STAT_CLEAR);
8574 val = tr32(TG3_PCIE_LNKCTL) & ~TG3_PCIE_LNKCTL_L1_PLL_PD_EN;
8575 tw32(TG3_PCIE_LNKCTL, val | TG3_PCIE_LNKCTL_L1_PLL_PD_DIS);
8578 if (tg3_flag(tp, L1PLLPD_EN)) {
8579 u32 grc_mode = tr32(GRC_MODE);
8581 /* Access the lower 1K of PL PCIE block registers. */
8582 val = grc_mode & ~GRC_MODE_PCIE_PORT_MASK;
8583 tw32(GRC_MODE, val | GRC_MODE_PCIE_PL_SEL);
8585 val = tr32(TG3_PCIE_TLDLPL_PORT + TG3_PCIE_PL_LO_PHYCTL1);
8586 tw32(TG3_PCIE_TLDLPL_PORT + TG3_PCIE_PL_LO_PHYCTL1,
8587 val | TG3_PCIE_PL_LO_PHYCTL1_L1PLLPD_EN);
8589 tw32(GRC_MODE, grc_mode);
8592 if (tg3_flag(tp, 57765_CLASS)) {
8593 if (tp->pci_chip_rev_id == CHIPREV_ID_57765_A0) {
8594 u32 grc_mode = tr32(GRC_MODE);
8596 /* Access the lower 1K of PL PCIE block registers. */
8597 val = grc_mode & ~GRC_MODE_PCIE_PORT_MASK;
8598 tw32(GRC_MODE, val | GRC_MODE_PCIE_PL_SEL);
8600 val = tr32(TG3_PCIE_TLDLPL_PORT +
8601 TG3_PCIE_PL_LO_PHYCTL5);
8602 tw32(TG3_PCIE_TLDLPL_PORT + TG3_PCIE_PL_LO_PHYCTL5,
8603 val | TG3_PCIE_PL_LO_PHYCTL5_DIS_L2CLKREQ);
8605 tw32(GRC_MODE, grc_mode);
8608 if (GET_CHIP_REV(tp->pci_chip_rev_id) != CHIPREV_57765_AX) {
8609 u32 grc_mode = tr32(GRC_MODE);
8611 /* Access the lower 1K of DL PCIE block registers. */
8612 val = grc_mode & ~GRC_MODE_PCIE_PORT_MASK;
8613 tw32(GRC_MODE, val | GRC_MODE_PCIE_DL_SEL);
8615 val = tr32(TG3_PCIE_TLDLPL_PORT +
8616 TG3_PCIE_DL_LO_FTSMAX);
8617 val &= ~TG3_PCIE_DL_LO_FTSMAX_MSK;
8618 tw32(TG3_PCIE_TLDLPL_PORT + TG3_PCIE_DL_LO_FTSMAX,
8619 val | TG3_PCIE_DL_LO_FTSMAX_VAL);
8621 tw32(GRC_MODE, grc_mode);
8624 val = tr32(TG3_CPMU_LSPD_10MB_CLK);
8625 val &= ~CPMU_LSPD_10MB_MACCLK_MASK;
8626 val |= CPMU_LSPD_10MB_MACCLK_6_25;
8627 tw32(TG3_CPMU_LSPD_10MB_CLK, val);
8630 /* This works around an issue with Athlon chipsets on
8631 * B3 tigon3 silicon. This bit has no effect on any
8632 * other revision. But do not set this on PCI Express
8633 * chips and don't even touch the clocks if the CPMU is present.
8635 if (!tg3_flag(tp, CPMU_PRESENT)) {
8636 if (!tg3_flag(tp, PCI_EXPRESS))
8637 tp->pci_clock_ctrl |= CLOCK_CTRL_DELAY_PCI_GRANT;
8638 tw32_f(TG3PCI_CLOCK_CTRL, tp->pci_clock_ctrl);
8641 if (tp->pci_chip_rev_id == CHIPREV_ID_5704_A0 &&
8642 tg3_flag(tp, PCIX_MODE)) {
8643 val = tr32(TG3PCI_PCISTATE);
8644 val |= PCISTATE_RETRY_SAME_DMA;
8645 tw32(TG3PCI_PCISTATE, val);
8648 if (tg3_flag(tp, ENABLE_APE)) {
8649 /* Allow reads and writes to the
8650 * APE register and memory space.
8652 val = tr32(TG3PCI_PCISTATE);
8653 val |= PCISTATE_ALLOW_APE_CTLSPC_WR |
8654 PCISTATE_ALLOW_APE_SHMEM_WR |
8655 PCISTATE_ALLOW_APE_PSPACE_WR;
8656 tw32(TG3PCI_PCISTATE, val);
8659 if (GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5704_BX) {
8660 /* Enable some hw fixes. */
8661 val = tr32(TG3PCI_MSI_DATA);
8662 val |= (1 << 26) | (1 << 28) | (1 << 29);
8663 tw32(TG3PCI_MSI_DATA, val);
8666 /* Descriptor ring init may make accesses to the
8667 * NIC SRAM area to setup the TX descriptors, so we
8668 * can only do this after the hardware has been
8669 * successfully reset.
8671 err = tg3_init_rings(tp);
8675 if (tg3_flag(tp, 57765_PLUS)) {
8676 val = tr32(TG3PCI_DMA_RW_CTRL) &
8677 ~DMA_RWCTRL_DIS_CACHE_ALIGNMENT;
8678 if (tp->pci_chip_rev_id == CHIPREV_ID_57765_A0)
8679 val &= ~DMA_RWCTRL_CRDRDR_RDMA_MRRS_MSK;
8680 if (!tg3_flag(tp, 57765_CLASS) &&
8681 GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5717)
8682 val |= DMA_RWCTRL_TAGGED_STAT_WA;
8683 tw32(TG3PCI_DMA_RW_CTRL, val | tp->dma_rwctrl);
8684 } else if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5784 &&
8685 GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5761) {
8686 /* This value is determined during the probe time DMA
8687 * engine test, tg3_test_dma.
8689 tw32(TG3PCI_DMA_RW_CTRL, tp->dma_rwctrl);
8692 tp->grc_mode &= ~(GRC_MODE_HOST_SENDBDS |
8693 GRC_MODE_4X_NIC_SEND_RINGS |
8694 GRC_MODE_NO_TX_PHDR_CSUM |
8695 GRC_MODE_NO_RX_PHDR_CSUM);
8696 tp->grc_mode |= GRC_MODE_HOST_SENDBDS;
8698 /* Pseudo-header checksum is done by hardware logic and not
8699 * the offload processers, so make the chip do the pseudo-
8700 * header checksums on receive. For transmit it is more
8701 * convenient to do the pseudo-header checksum in software
8702 * as Linux does that on transmit for us in all cases.
8704 tp->grc_mode |= GRC_MODE_NO_TX_PHDR_CSUM;
8708 (GRC_MODE_IRQ_ON_MAC_ATTN | GRC_MODE_HOST_STACKUP));
8710 /* Setup the timer prescalar register. Clock is always 66Mhz. */
8711 val = tr32(GRC_MISC_CFG);
8713 val |= (65 << GRC_MISC_CFG_PRESCALAR_SHIFT);
8714 tw32(GRC_MISC_CFG, val);
8716 /* Initialize MBUF/DESC pool. */
8717 if (tg3_flag(tp, 5750_PLUS)) {
8719 } else if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5705) {
8720 tw32(BUFMGR_MB_POOL_ADDR, NIC_SRAM_MBUF_POOL_BASE);
8721 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704)
8722 tw32(BUFMGR_MB_POOL_SIZE, NIC_SRAM_MBUF_POOL_SIZE64);
8724 tw32(BUFMGR_MB_POOL_SIZE, NIC_SRAM_MBUF_POOL_SIZE96);
8725 tw32(BUFMGR_DMA_DESC_POOL_ADDR, NIC_SRAM_DMA_DESC_POOL_BASE);
8726 tw32(BUFMGR_DMA_DESC_POOL_SIZE, NIC_SRAM_DMA_DESC_POOL_SIZE);
8727 } else if (tg3_flag(tp, TSO_CAPABLE)) {
8730 fw_len = tp->fw_len;
8731 fw_len = (fw_len + (0x80 - 1)) & ~(0x80 - 1);
8732 tw32(BUFMGR_MB_POOL_ADDR,
8733 NIC_SRAM_MBUF_POOL_BASE5705 + fw_len);
8734 tw32(BUFMGR_MB_POOL_SIZE,
8735 NIC_SRAM_MBUF_POOL_SIZE5705 - fw_len - 0xa00);
8738 if (tp->dev->mtu <= ETH_DATA_LEN) {
8739 tw32(BUFMGR_MB_RDMA_LOW_WATER,
8740 tp->bufmgr_config.mbuf_read_dma_low_water);
8741 tw32(BUFMGR_MB_MACRX_LOW_WATER,
8742 tp->bufmgr_config.mbuf_mac_rx_low_water);
8743 tw32(BUFMGR_MB_HIGH_WATER,
8744 tp->bufmgr_config.mbuf_high_water);
8746 tw32(BUFMGR_MB_RDMA_LOW_WATER,
8747 tp->bufmgr_config.mbuf_read_dma_low_water_jumbo);
8748 tw32(BUFMGR_MB_MACRX_LOW_WATER,
8749 tp->bufmgr_config.mbuf_mac_rx_low_water_jumbo);
8750 tw32(BUFMGR_MB_HIGH_WATER,
8751 tp->bufmgr_config.mbuf_high_water_jumbo);
8753 tw32(BUFMGR_DMA_LOW_WATER,
8754 tp->bufmgr_config.dma_low_water);
8755 tw32(BUFMGR_DMA_HIGH_WATER,
8756 tp->bufmgr_config.dma_high_water);
8758 val = BUFMGR_MODE_ENABLE | BUFMGR_MODE_ATTN_ENABLE;
8759 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5719)
8760 val |= BUFMGR_MODE_NO_TX_UNDERRUN;
8761 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717 ||
8762 tp->pci_chip_rev_id == CHIPREV_ID_5719_A0 ||
8763 tp->pci_chip_rev_id == CHIPREV_ID_5720_A0)
8764 val |= BUFMGR_MODE_MBLOW_ATTN_ENAB;
8765 tw32(BUFMGR_MODE, val);
8766 for (i = 0; i < 2000; i++) {
8767 if (tr32(BUFMGR_MODE) & BUFMGR_MODE_ENABLE)
8772 netdev_err(tp->dev, "%s cannot enable BUFMGR\n", __func__);
8776 if (tp->pci_chip_rev_id == CHIPREV_ID_5906_A1)
8777 tw32(ISO_PKT_TX, (tr32(ISO_PKT_TX) & ~0x3) | 0x2);
8779 tg3_setup_rxbd_thresholds(tp);
8781 /* Initialize TG3_BDINFO's at:
8782 * RCVDBDI_STD_BD: standard eth size rx ring
8783 * RCVDBDI_JUMBO_BD: jumbo frame rx ring
8784 * RCVDBDI_MINI_BD: small frame rx ring (??? does not work)
8787 * TG3_BDINFO_HOST_ADDR: high/low parts of DMA address of ring
8788 * TG3_BDINFO_MAXLEN_FLAGS: (rx max buffer size << 16) |
8789 * ring attribute flags
8790 * TG3_BDINFO_NIC_ADDR: location of descriptors in nic SRAM
8792 * Standard receive ring @ NIC_SRAM_RX_BUFFER_DESC, 512 entries.
8793 * Jumbo receive ring @ NIC_SRAM_RX_JUMBO_BUFFER_DESC, 256 entries.
8795 * The size of each ring is fixed in the firmware, but the location is
8798 tw32(RCVDBDI_STD_BD + TG3_BDINFO_HOST_ADDR + TG3_64BIT_REG_HIGH,
8799 ((u64) tpr->rx_std_mapping >> 32));
8800 tw32(RCVDBDI_STD_BD + TG3_BDINFO_HOST_ADDR + TG3_64BIT_REG_LOW,
8801 ((u64) tpr->rx_std_mapping & 0xffffffff));
8802 if (!tg3_flag(tp, 5717_PLUS))
8803 tw32(RCVDBDI_STD_BD + TG3_BDINFO_NIC_ADDR,
8804 NIC_SRAM_RX_BUFFER_DESC);
8806 /* Disable the mini ring */
8807 if (!tg3_flag(tp, 5705_PLUS))
8808 tw32(RCVDBDI_MINI_BD + TG3_BDINFO_MAXLEN_FLAGS,
8809 BDINFO_FLAGS_DISABLED);
8811 /* Program the jumbo buffer descriptor ring control
8812 * blocks on those devices that have them.
8814 if (tp->pci_chip_rev_id == CHIPREV_ID_5719_A0 ||
8815 (tg3_flag(tp, JUMBO_CAPABLE) && !tg3_flag(tp, 5780_CLASS))) {
8817 if (tg3_flag(tp, JUMBO_RING_ENABLE)) {
8818 tw32(RCVDBDI_JUMBO_BD + TG3_BDINFO_HOST_ADDR + TG3_64BIT_REG_HIGH,
8819 ((u64) tpr->rx_jmb_mapping >> 32));
8820 tw32(RCVDBDI_JUMBO_BD + TG3_BDINFO_HOST_ADDR + TG3_64BIT_REG_LOW,
8821 ((u64) tpr->rx_jmb_mapping & 0xffffffff));
8822 val = TG3_RX_JMB_RING_SIZE(tp) <<
8823 BDINFO_FLAGS_MAXLEN_SHIFT;
8824 tw32(RCVDBDI_JUMBO_BD + TG3_BDINFO_MAXLEN_FLAGS,
8825 val | BDINFO_FLAGS_USE_EXT_RECV);
8826 if (!tg3_flag(tp, USE_JUMBO_BDFLAG) ||
8827 tg3_flag(tp, 57765_CLASS))
8828 tw32(RCVDBDI_JUMBO_BD + TG3_BDINFO_NIC_ADDR,
8829 NIC_SRAM_RX_JUMBO_BUFFER_DESC);
8831 tw32(RCVDBDI_JUMBO_BD + TG3_BDINFO_MAXLEN_FLAGS,
8832 BDINFO_FLAGS_DISABLED);
8835 if (tg3_flag(tp, 57765_PLUS)) {
8836 val = TG3_RX_STD_RING_SIZE(tp);
8837 val <<= BDINFO_FLAGS_MAXLEN_SHIFT;
8838 val |= (TG3_RX_STD_DMA_SZ << 2);
8840 val = TG3_RX_STD_DMA_SZ << BDINFO_FLAGS_MAXLEN_SHIFT;
8842 val = TG3_RX_STD_MAX_SIZE_5700 << BDINFO_FLAGS_MAXLEN_SHIFT;
8844 tw32(RCVDBDI_STD_BD + TG3_BDINFO_MAXLEN_FLAGS, val);
8846 tpr->rx_std_prod_idx = tp->rx_pending;
8847 tw32_rx_mbox(TG3_RX_STD_PROD_IDX_REG, tpr->rx_std_prod_idx);
8849 tpr->rx_jmb_prod_idx =
8850 tg3_flag(tp, JUMBO_RING_ENABLE) ? tp->rx_jumbo_pending : 0;
8851 tw32_rx_mbox(TG3_RX_JMB_PROD_IDX_REG, tpr->rx_jmb_prod_idx);
8853 tg3_rings_reset(tp);
8855 /* Initialize MAC address and backoff seed. */
8856 __tg3_set_mac_addr(tp, 0);
8858 /* MTU + ethernet header + FCS + optional VLAN tag */
8859 tw32(MAC_RX_MTU_SIZE,
8860 tp->dev->mtu + ETH_HLEN + ETH_FCS_LEN + VLAN_HLEN);
8862 /* The slot time is changed by tg3_setup_phy if we
8863 * run at gigabit with half duplex.
8865 val = (2 << TX_LENGTHS_IPG_CRS_SHIFT) |
8866 (6 << TX_LENGTHS_IPG_SHIFT) |
8867 (32 << TX_LENGTHS_SLOT_TIME_SHIFT);
8869 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5720)
8870 val |= tr32(MAC_TX_LENGTHS) &
8871 (TX_LENGTHS_JMB_FRM_LEN_MSK |
8872 TX_LENGTHS_CNT_DWN_VAL_MSK);
8874 tw32(MAC_TX_LENGTHS, val);
8876 /* Receive rules. */
8877 tw32(MAC_RCV_RULE_CFG, RCV_RULE_CFG_DEFAULT_CLASS);
8878 tw32(RCVLPC_CONFIG, 0x0181);
8880 /* Calculate RDMAC_MODE setting early, we need it to determine
8881 * the RCVLPC_STATE_ENABLE mask.
8883 rdmac_mode = (RDMAC_MODE_ENABLE | RDMAC_MODE_TGTABORT_ENAB |
8884 RDMAC_MODE_MSTABORT_ENAB | RDMAC_MODE_PARITYERR_ENAB |
8885 RDMAC_MODE_ADDROFLOW_ENAB | RDMAC_MODE_FIFOOFLOW_ENAB |
8886 RDMAC_MODE_FIFOURUN_ENAB | RDMAC_MODE_FIFOOREAD_ENAB |
8887 RDMAC_MODE_LNGREAD_ENAB);
8889 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717)
8890 rdmac_mode |= RDMAC_MODE_MULT_DMA_RD_DIS;
8892 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5784 ||
8893 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785 ||
8894 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57780)
8895 rdmac_mode |= RDMAC_MODE_BD_SBD_CRPT_ENAB |
8896 RDMAC_MODE_MBUF_RBD_CRPT_ENAB |
8897 RDMAC_MODE_MBUF_SBD_CRPT_ENAB;
8899 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705 &&
8900 tp->pci_chip_rev_id != CHIPREV_ID_5705_A0) {
8901 if (tg3_flag(tp, TSO_CAPABLE) &&
8902 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705) {
8903 rdmac_mode |= RDMAC_MODE_FIFO_SIZE_128;
8904 } else if (!(tr32(TG3PCI_PCISTATE) & PCISTATE_BUS_SPEED_HIGH) &&
8905 !tg3_flag(tp, IS_5788)) {
8906 rdmac_mode |= RDMAC_MODE_FIFO_LONG_BURST;
8910 if (tg3_flag(tp, PCI_EXPRESS))
8911 rdmac_mode |= RDMAC_MODE_FIFO_LONG_BURST;
8913 if (tg3_flag(tp, HW_TSO_1) ||
8914 tg3_flag(tp, HW_TSO_2) ||
8915 tg3_flag(tp, HW_TSO_3))
8916 rdmac_mode |= RDMAC_MODE_IPV4_LSO_EN;
8918 if (tg3_flag(tp, 57765_PLUS) ||
8919 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785 ||
8920 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57780)
8921 rdmac_mode |= RDMAC_MODE_IPV6_LSO_EN;
8923 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5720)
8924 rdmac_mode |= tr32(RDMAC_MODE) & RDMAC_MODE_H2BNC_VLAN_DET;
8926 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5761 ||
8927 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5784 ||
8928 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785 ||
8929 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57780 ||
8930 tg3_flag(tp, 57765_PLUS)) {
8931 val = tr32(TG3_RDMA_RSRVCTRL_REG);
8932 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5719 ||
8933 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5720) {
8934 val &= ~(TG3_RDMA_RSRVCTRL_TXMRGN_MASK |
8935 TG3_RDMA_RSRVCTRL_FIFO_LWM_MASK |
8936 TG3_RDMA_RSRVCTRL_FIFO_HWM_MASK);
8937 val |= TG3_RDMA_RSRVCTRL_TXMRGN_320B |
8938 TG3_RDMA_RSRVCTRL_FIFO_LWM_1_5K |
8939 TG3_RDMA_RSRVCTRL_FIFO_HWM_1_5K;
8941 tw32(TG3_RDMA_RSRVCTRL_REG,
8942 val | TG3_RDMA_RSRVCTRL_FIFO_OFLW_FIX);
8945 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5719 ||
8946 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5720) {
8947 val = tr32(TG3_LSO_RD_DMA_CRPTEN_CTRL);
8948 tw32(TG3_LSO_RD_DMA_CRPTEN_CTRL, val |
8949 TG3_LSO_RD_DMA_CRPTEN_CTRL_BLEN_BD_4K |
8950 TG3_LSO_RD_DMA_CRPTEN_CTRL_BLEN_LSO_4K);
8953 /* Receive/send statistics. */
8954 if (tg3_flag(tp, 5750_PLUS)) {
8955 val = tr32(RCVLPC_STATS_ENABLE);
8956 val &= ~RCVLPC_STATSENAB_DACK_FIX;
8957 tw32(RCVLPC_STATS_ENABLE, val);
8958 } else if ((rdmac_mode & RDMAC_MODE_FIFO_SIZE_128) &&
8959 tg3_flag(tp, TSO_CAPABLE)) {
8960 val = tr32(RCVLPC_STATS_ENABLE);
8961 val &= ~RCVLPC_STATSENAB_LNGBRST_RFIX;
8962 tw32(RCVLPC_STATS_ENABLE, val);
8964 tw32(RCVLPC_STATS_ENABLE, 0xffffff);
8966 tw32(RCVLPC_STATSCTRL, RCVLPC_STATSCTRL_ENABLE);
8967 tw32(SNDDATAI_STATSENAB, 0xffffff);
8968 tw32(SNDDATAI_STATSCTRL,
8969 (SNDDATAI_SCTRL_ENABLE |
8970 SNDDATAI_SCTRL_FASTUPD));
8972 /* Setup host coalescing engine. */
8973 tw32(HOSTCC_MODE, 0);
8974 for (i = 0; i < 2000; i++) {
8975 if (!(tr32(HOSTCC_MODE) & HOSTCC_MODE_ENABLE))
8980 __tg3_set_coalesce(tp, &tp->coal);
8982 if (!tg3_flag(tp, 5705_PLUS)) {
8983 /* Status/statistics block address. See tg3_timer,
8984 * the tg3_periodic_fetch_stats call there, and
8985 * tg3_get_stats to see how this works for 5705/5750 chips.
8987 tw32(HOSTCC_STATS_BLK_HOST_ADDR + TG3_64BIT_REG_HIGH,
8988 ((u64) tp->stats_mapping >> 32));
8989 tw32(HOSTCC_STATS_BLK_HOST_ADDR + TG3_64BIT_REG_LOW,
8990 ((u64) tp->stats_mapping & 0xffffffff));
8991 tw32(HOSTCC_STATS_BLK_NIC_ADDR, NIC_SRAM_STATS_BLK);
8993 tw32(HOSTCC_STATUS_BLK_NIC_ADDR, NIC_SRAM_STATUS_BLK);
8995 /* Clear statistics and status block memory areas */
8996 for (i = NIC_SRAM_STATS_BLK;
8997 i < NIC_SRAM_STATUS_BLK + TG3_HW_STATUS_SIZE;
8999 tg3_write_mem(tp, i, 0);
9004 tw32(HOSTCC_MODE, HOSTCC_MODE_ENABLE | tp->coalesce_mode);
9006 tw32(RCVCC_MODE, RCVCC_MODE_ENABLE | RCVCC_MODE_ATTN_ENABLE);
9007 tw32(RCVLPC_MODE, RCVLPC_MODE_ENABLE);
9008 if (!tg3_flag(tp, 5705_PLUS))
9009 tw32(RCVLSC_MODE, RCVLSC_MODE_ENABLE | RCVLSC_MODE_ATTN_ENABLE);
9011 if (tp->phy_flags & TG3_PHYFLG_MII_SERDES) {
9012 tp->phy_flags &= ~TG3_PHYFLG_PARALLEL_DETECT;
9013 /* reset to prevent losing 1st rx packet intermittently */
9014 tw32_f(MAC_RX_MODE, RX_MODE_RESET);
9018 tp->mac_mode |= MAC_MODE_TXSTAT_ENABLE | MAC_MODE_RXSTAT_ENABLE |
9019 MAC_MODE_TDE_ENABLE | MAC_MODE_RDE_ENABLE |
9020 MAC_MODE_FHDE_ENABLE;
9021 if (tg3_flag(tp, ENABLE_APE))
9022 tp->mac_mode |= MAC_MODE_APE_TX_EN | MAC_MODE_APE_RX_EN;
9023 if (!tg3_flag(tp, 5705_PLUS) &&
9024 !(tp->phy_flags & TG3_PHYFLG_PHY_SERDES) &&
9025 GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5700)
9026 tp->mac_mode |= MAC_MODE_LINK_POLARITY;
9027 tw32_f(MAC_MODE, tp->mac_mode | MAC_MODE_RXSTAT_CLEAR | MAC_MODE_TXSTAT_CLEAR);
9030 /* tp->grc_local_ctrl is partially set up during tg3_get_invariants().
9031 * If TG3_FLAG_IS_NIC is zero, we should read the
9032 * register to preserve the GPIO settings for LOMs. The GPIOs,
9033 * whether used as inputs or outputs, are set by boot code after
9036 if (!tg3_flag(tp, IS_NIC)) {
9039 gpio_mask = GRC_LCLCTRL_GPIO_OE0 | GRC_LCLCTRL_GPIO_OE1 |
9040 GRC_LCLCTRL_GPIO_OE2 | GRC_LCLCTRL_GPIO_OUTPUT0 |
9041 GRC_LCLCTRL_GPIO_OUTPUT1 | GRC_LCLCTRL_GPIO_OUTPUT2;
9043 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5752)
9044 gpio_mask |= GRC_LCLCTRL_GPIO_OE3 |
9045 GRC_LCLCTRL_GPIO_OUTPUT3;
9047 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5755)
9048 gpio_mask |= GRC_LCLCTRL_GPIO_UART_SEL;
9050 tp->grc_local_ctrl &= ~gpio_mask;
9051 tp->grc_local_ctrl |= tr32(GRC_LOCAL_CTRL) & gpio_mask;
9053 /* GPIO1 must be driven high for eeprom write protect */
9054 if (tg3_flag(tp, EEPROM_WRITE_PROT))
9055 tp->grc_local_ctrl |= (GRC_LCLCTRL_GPIO_OE1 |
9056 GRC_LCLCTRL_GPIO_OUTPUT1);
9058 tw32_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl);
9061 if (tg3_flag(tp, USING_MSIX)) {
9062 val = tr32(MSGINT_MODE);
9063 val |= MSGINT_MODE_ENABLE;
9064 if (tp->irq_cnt > 1)
9065 val |= MSGINT_MODE_MULTIVEC_EN;
9066 if (!tg3_flag(tp, 1SHOT_MSI))
9067 val |= MSGINT_MODE_ONE_SHOT_DISABLE;
9068 tw32(MSGINT_MODE, val);
9071 if (!tg3_flag(tp, 5705_PLUS)) {
9072 tw32_f(DMAC_MODE, DMAC_MODE_ENABLE);
9076 val = (WDMAC_MODE_ENABLE | WDMAC_MODE_TGTABORT_ENAB |
9077 WDMAC_MODE_MSTABORT_ENAB | WDMAC_MODE_PARITYERR_ENAB |
9078 WDMAC_MODE_ADDROFLOW_ENAB | WDMAC_MODE_FIFOOFLOW_ENAB |
9079 WDMAC_MODE_FIFOURUN_ENAB | WDMAC_MODE_FIFOOREAD_ENAB |
9080 WDMAC_MODE_LNGREAD_ENAB);
9082 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705 &&
9083 tp->pci_chip_rev_id != CHIPREV_ID_5705_A0) {
9084 if (tg3_flag(tp, TSO_CAPABLE) &&
9085 (tp->pci_chip_rev_id == CHIPREV_ID_5705_A1 ||
9086 tp->pci_chip_rev_id == CHIPREV_ID_5705_A2)) {
9088 } else if (!(tr32(TG3PCI_PCISTATE) & PCISTATE_BUS_SPEED_HIGH) &&
9089 !tg3_flag(tp, IS_5788)) {
9090 val |= WDMAC_MODE_RX_ACCEL;
9094 /* Enable host coalescing bug fix */
9095 if (tg3_flag(tp, 5755_PLUS))
9096 val |= WDMAC_MODE_STATUS_TAG_FIX;
9098 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785)
9099 val |= WDMAC_MODE_BURST_ALL_DATA;
9101 tw32_f(WDMAC_MODE, val);
9104 if (tg3_flag(tp, PCIX_MODE)) {
9107 pci_read_config_word(tp->pdev, tp->pcix_cap + PCI_X_CMD,
9109 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703) {
9110 pcix_cmd &= ~PCI_X_CMD_MAX_READ;
9111 pcix_cmd |= PCI_X_CMD_READ_2K;
9112 } else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704) {
9113 pcix_cmd &= ~(PCI_X_CMD_MAX_SPLIT | PCI_X_CMD_MAX_READ);
9114 pcix_cmd |= PCI_X_CMD_READ_2K;
9116 pci_write_config_word(tp->pdev, tp->pcix_cap + PCI_X_CMD,
9120 tw32_f(RDMAC_MODE, rdmac_mode);
9123 tw32(RCVDCC_MODE, RCVDCC_MODE_ENABLE | RCVDCC_MODE_ATTN_ENABLE);
9124 if (!tg3_flag(tp, 5705_PLUS))
9125 tw32(MBFREE_MODE, MBFREE_MODE_ENABLE);
9127 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5761)
9129 SNDDATAC_MODE_ENABLE | SNDDATAC_MODE_CDELAY);
9131 tw32(SNDDATAC_MODE, SNDDATAC_MODE_ENABLE);
9133 tw32(SNDBDC_MODE, SNDBDC_MODE_ENABLE | SNDBDC_MODE_ATTN_ENABLE);
9134 tw32(RCVBDI_MODE, RCVBDI_MODE_ENABLE | RCVBDI_MODE_RCB_ATTN_ENAB);
9135 val = RCVDBDI_MODE_ENABLE | RCVDBDI_MODE_INV_RING_SZ;
9136 if (tg3_flag(tp, LRG_PROD_RING_CAP))
9137 val |= RCVDBDI_MODE_LRG_RING_SZ;
9138 tw32(RCVDBDI_MODE, val);
9139 tw32(SNDDATAI_MODE, SNDDATAI_MODE_ENABLE);
9140 if (tg3_flag(tp, HW_TSO_1) ||
9141 tg3_flag(tp, HW_TSO_2) ||
9142 tg3_flag(tp, HW_TSO_3))
9143 tw32(SNDDATAI_MODE, SNDDATAI_MODE_ENABLE | 0x8);
9144 val = SNDBDI_MODE_ENABLE | SNDBDI_MODE_ATTN_ENABLE;
9145 if (tg3_flag(tp, ENABLE_TSS))
9146 val |= SNDBDI_MODE_MULTI_TXQ_EN;
9147 tw32(SNDBDI_MODE, val);
9148 tw32(SNDBDS_MODE, SNDBDS_MODE_ENABLE | SNDBDS_MODE_ATTN_ENABLE);
9150 if (tp->pci_chip_rev_id == CHIPREV_ID_5701_A0) {
9151 err = tg3_load_5701_a0_firmware_fix(tp);
9156 if (tg3_flag(tp, TSO_CAPABLE)) {
9157 err = tg3_load_tso_firmware(tp);
9162 tp->tx_mode = TX_MODE_ENABLE;
9164 if (tg3_flag(tp, 5755_PLUS) ||
9165 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906)
9166 tp->tx_mode |= TX_MODE_MBUF_LOCKUP_FIX;
9168 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5720) {
9169 val = TX_MODE_JMB_FRM_LEN | TX_MODE_CNT_DN_MODE;
9170 tp->tx_mode &= ~val;
9171 tp->tx_mode |= tr32(MAC_TX_MODE) & val;
9174 tw32_f(MAC_TX_MODE, tp->tx_mode);
9177 if (tg3_flag(tp, ENABLE_RSS)) {
9178 tg3_rss_write_indir_tbl(tp);
9180 /* Setup the "secret" hash key. */
9181 tw32(MAC_RSS_HASH_KEY_0, 0x5f865437);
9182 tw32(MAC_RSS_HASH_KEY_1, 0xe4ac62cc);
9183 tw32(MAC_RSS_HASH_KEY_2, 0x50103a45);
9184 tw32(MAC_RSS_HASH_KEY_3, 0x36621985);
9185 tw32(MAC_RSS_HASH_KEY_4, 0xbf14c0e8);
9186 tw32(MAC_RSS_HASH_KEY_5, 0x1bc27a1e);
9187 tw32(MAC_RSS_HASH_KEY_6, 0x84f4b556);
9188 tw32(MAC_RSS_HASH_KEY_7, 0x094ea6fe);
9189 tw32(MAC_RSS_HASH_KEY_8, 0x7dda01e7);
9190 tw32(MAC_RSS_HASH_KEY_9, 0xc04d7481);
9193 tp->rx_mode = RX_MODE_ENABLE;
9194 if (tg3_flag(tp, 5755_PLUS))
9195 tp->rx_mode |= RX_MODE_IPV6_CSUM_ENABLE;
9197 if (tg3_flag(tp, ENABLE_RSS))
9198 tp->rx_mode |= RX_MODE_RSS_ENABLE |
9199 RX_MODE_RSS_ITBL_HASH_BITS_7 |
9200 RX_MODE_RSS_IPV6_HASH_EN |
9201 RX_MODE_RSS_TCP_IPV6_HASH_EN |
9202 RX_MODE_RSS_IPV4_HASH_EN |
9203 RX_MODE_RSS_TCP_IPV4_HASH_EN;
9205 tw32_f(MAC_RX_MODE, tp->rx_mode);
9208 tw32(MAC_LED_CTRL, tp->led_ctrl);
9210 tw32(MAC_MI_STAT, MAC_MI_STAT_LNKSTAT_ATTN_ENAB);
9211 if (tp->phy_flags & TG3_PHYFLG_PHY_SERDES) {
9212 tw32_f(MAC_RX_MODE, RX_MODE_RESET);
9215 tw32_f(MAC_RX_MODE, tp->rx_mode);
9218 if (tp->phy_flags & TG3_PHYFLG_PHY_SERDES) {
9219 if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704) &&
9220 !(tp->phy_flags & TG3_PHYFLG_SERDES_PREEMPHASIS)) {
9221 /* Set drive transmission level to 1.2V */
9222 /* only if the signal pre-emphasis bit is not set */
9223 val = tr32(MAC_SERDES_CFG);
9226 tw32(MAC_SERDES_CFG, val);
9228 if (tp->pci_chip_rev_id == CHIPREV_ID_5703_A1)
9229 tw32(MAC_SERDES_CFG, 0x616000);
9232 /* Prevent chip from dropping frames when flow control
9235 if (tg3_flag(tp, 57765_CLASS))
9239 tw32_f(MAC_LOW_WMARK_MAX_RX_FRAME, val);
9241 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704 &&
9242 (tp->phy_flags & TG3_PHYFLG_PHY_SERDES)) {
9243 /* Use hardware link auto-negotiation */
9244 tg3_flag_set(tp, HW_AUTONEG);
9247 if ((tp->phy_flags & TG3_PHYFLG_MII_SERDES) &&
9248 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5714) {
9251 tmp = tr32(SERDES_RX_CTRL);
9252 tw32(SERDES_RX_CTRL, tmp | SERDES_RX_SIG_DETECT);
9253 tp->grc_local_ctrl &= ~GRC_LCLCTRL_USE_EXT_SIG_DETECT;
9254 tp->grc_local_ctrl |= GRC_LCLCTRL_USE_SIG_DETECT;
9255 tw32(GRC_LOCAL_CTRL, tp->grc_local_ctrl);
9258 if (!tg3_flag(tp, USE_PHYLIB)) {
9259 if (tp->phy_flags & TG3_PHYFLG_IS_LOW_POWER)
9260 tp->phy_flags &= ~TG3_PHYFLG_IS_LOW_POWER;
9262 err = tg3_setup_phy(tp, 0);
9266 if (!(tp->phy_flags & TG3_PHYFLG_PHY_SERDES) &&
9267 !(tp->phy_flags & TG3_PHYFLG_IS_FET)) {
9270 /* Clear CRC stats. */
9271 if (!tg3_readphy(tp, MII_TG3_TEST1, &tmp)) {
9272 tg3_writephy(tp, MII_TG3_TEST1,
9273 tmp | MII_TG3_TEST1_CRC_EN);
9274 tg3_readphy(tp, MII_TG3_RXR_COUNTERS, &tmp);
9279 __tg3_set_rx_mode(tp->dev);
9281 /* Initialize receive rules. */
9282 tw32(MAC_RCV_RULE_0, 0xc2000000 & RCV_RULE_DISABLE_MASK);
9283 tw32(MAC_RCV_VALUE_0, 0xffffffff & RCV_RULE_DISABLE_MASK);
9284 tw32(MAC_RCV_RULE_1, 0x86000004 & RCV_RULE_DISABLE_MASK);
9285 tw32(MAC_RCV_VALUE_1, 0xffffffff & RCV_RULE_DISABLE_MASK);
9287 if (tg3_flag(tp, 5705_PLUS) && !tg3_flag(tp, 5780_CLASS))
9291 if (tg3_flag(tp, ENABLE_ASF))
9295 tw32(MAC_RCV_RULE_15, 0); tw32(MAC_RCV_VALUE_15, 0);
9297 tw32(MAC_RCV_RULE_14, 0); tw32(MAC_RCV_VALUE_14, 0);
9299 tw32(MAC_RCV_RULE_13, 0); tw32(MAC_RCV_VALUE_13, 0);
9301 tw32(MAC_RCV_RULE_12, 0); tw32(MAC_RCV_VALUE_12, 0);
9303 tw32(MAC_RCV_RULE_11, 0); tw32(MAC_RCV_VALUE_11, 0);
9305 tw32(MAC_RCV_RULE_10, 0); tw32(MAC_RCV_VALUE_10, 0);
9307 tw32(MAC_RCV_RULE_9, 0); tw32(MAC_RCV_VALUE_9, 0);
9309 tw32(MAC_RCV_RULE_8, 0); tw32(MAC_RCV_VALUE_8, 0);
9311 tw32(MAC_RCV_RULE_7, 0); tw32(MAC_RCV_VALUE_7, 0);
9313 tw32(MAC_RCV_RULE_6, 0); tw32(MAC_RCV_VALUE_6, 0);
9315 tw32(MAC_RCV_RULE_5, 0); tw32(MAC_RCV_VALUE_5, 0);
9317 tw32(MAC_RCV_RULE_4, 0); tw32(MAC_RCV_VALUE_4, 0);
9319 /* tw32(MAC_RCV_RULE_3, 0); tw32(MAC_RCV_VALUE_3, 0); */
9321 /* tw32(MAC_RCV_RULE_2, 0); tw32(MAC_RCV_VALUE_2, 0); */
9329 if (tg3_flag(tp, ENABLE_APE))
9330 /* Write our heartbeat update interval to APE. */
9331 tg3_ape_write32(tp, TG3_APE_HOST_HEARTBEAT_INT_MS,
9332 APE_HOST_HEARTBEAT_INT_DISABLE);
9334 tg3_write_sig_post_reset(tp, RESET_KIND_INIT);
9339 /* Called at device open time to get the chip ready for
9340 * packet processing. Invoked with tp->lock held.
9342 static int tg3_init_hw(struct tg3 *tp, int reset_phy)
9344 tg3_switch_clocks(tp);
9346 tw32(TG3PCI_MEM_WIN_BASE_ADDR, 0);
9348 return tg3_reset_hw(tp, reset_phy);
9351 /* Restart hardware after configuration changes, self-test, etc.
9352 * Invoked with tp->lock held.
9354 static int tg3_restart_hw(struct tg3 *tp, int reset_phy)
9355 __releases(tp->lock)
9356 __acquires(tp->lock)
9360 err = tg3_init_hw(tp, reset_phy);
9363 "Failed to re-initialize device, aborting\n");
9364 tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
9365 tg3_full_unlock(tp);
9366 del_timer_sync(&tp->timer);
9368 tg3_napi_enable(tp);
9370 tg3_full_lock(tp, 0);
9375 static void tg3_reset_task(struct work_struct *work)
9377 struct tg3 *tp = container_of(work, struct tg3, reset_task);
9380 tg3_full_lock(tp, 0);
9382 if (!netif_running(tp->dev)) {
9383 tg3_flag_clear(tp, RESET_TASK_PENDING);
9384 tg3_full_unlock(tp);
9388 tg3_full_unlock(tp);
9394 tg3_full_lock(tp, 1);
9396 if (tg3_flag(tp, TX_RECOVERY_PENDING)) {
9397 tp->write32_tx_mbox = tg3_write32_tx_mbox;
9398 tp->write32_rx_mbox = tg3_write_flush_reg32;
9399 tg3_flag_set(tp, MBOX_WRITE_REORDER);
9400 tg3_flag_clear(tp, TX_RECOVERY_PENDING);
9403 tg3_halt(tp, RESET_KIND_SHUTDOWN, 0);
9404 err = tg3_init_hw(tp, 1);
9408 tg3_netif_start(tp);
9411 tg3_full_unlock(tp);
9416 tg3_flag_clear(tp, RESET_TASK_PENDING);
9419 #define TG3_STAT_ADD32(PSTAT, REG) \
9420 do { u32 __val = tr32(REG); \
9421 (PSTAT)->low += __val; \
9422 if ((PSTAT)->low < __val) \
9423 (PSTAT)->high += 1; \
9426 static void tg3_periodic_fetch_stats(struct tg3 *tp)
9428 struct tg3_hw_stats *sp = tp->hw_stats;
9430 if (!netif_carrier_ok(tp->dev))
9433 TG3_STAT_ADD32(&sp->tx_octets, MAC_TX_STATS_OCTETS);
9434 TG3_STAT_ADD32(&sp->tx_collisions, MAC_TX_STATS_COLLISIONS);
9435 TG3_STAT_ADD32(&sp->tx_xon_sent, MAC_TX_STATS_XON_SENT);
9436 TG3_STAT_ADD32(&sp->tx_xoff_sent, MAC_TX_STATS_XOFF_SENT);
9437 TG3_STAT_ADD32(&sp->tx_mac_errors, MAC_TX_STATS_MAC_ERRORS);
9438 TG3_STAT_ADD32(&sp->tx_single_collisions, MAC_TX_STATS_SINGLE_COLLISIONS);
9439 TG3_STAT_ADD32(&sp->tx_mult_collisions, MAC_TX_STATS_MULT_COLLISIONS);
9440 TG3_STAT_ADD32(&sp->tx_deferred, MAC_TX_STATS_DEFERRED);
9441 TG3_STAT_ADD32(&sp->tx_excessive_collisions, MAC_TX_STATS_EXCESSIVE_COL);
9442 TG3_STAT_ADD32(&sp->tx_late_collisions, MAC_TX_STATS_LATE_COL);
9443 TG3_STAT_ADD32(&sp->tx_ucast_packets, MAC_TX_STATS_UCAST);
9444 TG3_STAT_ADD32(&sp->tx_mcast_packets, MAC_TX_STATS_MCAST);
9445 TG3_STAT_ADD32(&sp->tx_bcast_packets, MAC_TX_STATS_BCAST);
9447 TG3_STAT_ADD32(&sp->rx_octets, MAC_RX_STATS_OCTETS);
9448 TG3_STAT_ADD32(&sp->rx_fragments, MAC_RX_STATS_FRAGMENTS);
9449 TG3_STAT_ADD32(&sp->rx_ucast_packets, MAC_RX_STATS_UCAST);
9450 TG3_STAT_ADD32(&sp->rx_mcast_packets, MAC_RX_STATS_MCAST);
9451 TG3_STAT_ADD32(&sp->rx_bcast_packets, MAC_RX_STATS_BCAST);
9452 TG3_STAT_ADD32(&sp->rx_fcs_errors, MAC_RX_STATS_FCS_ERRORS);
9453 TG3_STAT_ADD32(&sp->rx_align_errors, MAC_RX_STATS_ALIGN_ERRORS);
9454 TG3_STAT_ADD32(&sp->rx_xon_pause_rcvd, MAC_RX_STATS_XON_PAUSE_RECVD);
9455 TG3_STAT_ADD32(&sp->rx_xoff_pause_rcvd, MAC_RX_STATS_XOFF_PAUSE_RECVD);
9456 TG3_STAT_ADD32(&sp->rx_mac_ctrl_rcvd, MAC_RX_STATS_MAC_CTRL_RECVD);
9457 TG3_STAT_ADD32(&sp->rx_xoff_entered, MAC_RX_STATS_XOFF_ENTERED);
9458 TG3_STAT_ADD32(&sp->rx_frame_too_long_errors, MAC_RX_STATS_FRAME_TOO_LONG);
9459 TG3_STAT_ADD32(&sp->rx_jabbers, MAC_RX_STATS_JABBERS);
9460 TG3_STAT_ADD32(&sp->rx_undersize_packets, MAC_RX_STATS_UNDERSIZE);
9462 TG3_STAT_ADD32(&sp->rxbds_empty, RCVLPC_NO_RCV_BD_CNT);
9463 if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5717 &&
9464 tp->pci_chip_rev_id != CHIPREV_ID_5719_A0 &&
9465 tp->pci_chip_rev_id != CHIPREV_ID_5720_A0) {
9466 TG3_STAT_ADD32(&sp->rx_discards, RCVLPC_IN_DISCARDS_CNT);
9468 u32 val = tr32(HOSTCC_FLOW_ATTN);
9469 val = (val & HOSTCC_FLOW_ATTN_MBUF_LWM) ? 1 : 0;
9471 tw32(HOSTCC_FLOW_ATTN, HOSTCC_FLOW_ATTN_MBUF_LWM);
9472 sp->rx_discards.low += val;
9473 if (sp->rx_discards.low < val)
9474 sp->rx_discards.high += 1;
9476 sp->mbuf_lwm_thresh_hit = sp->rx_discards;
9478 TG3_STAT_ADD32(&sp->rx_errors, RCVLPC_IN_ERRORS_CNT);
9481 static void tg3_chk_missed_msi(struct tg3 *tp)
9485 for (i = 0; i < tp->irq_cnt; i++) {
9486 struct tg3_napi *tnapi = &tp->napi[i];
9488 if (tg3_has_work(tnapi)) {
9489 if (tnapi->last_rx_cons == tnapi->rx_rcb_ptr &&
9490 tnapi->last_tx_cons == tnapi->tx_cons) {
9491 if (tnapi->chk_msi_cnt < 1) {
9492 tnapi->chk_msi_cnt++;
9498 tnapi->chk_msi_cnt = 0;
9499 tnapi->last_rx_cons = tnapi->rx_rcb_ptr;
9500 tnapi->last_tx_cons = tnapi->tx_cons;
9504 static void tg3_timer(unsigned long __opaque)
9506 struct tg3 *tp = (struct tg3 *) __opaque;
9508 if (tp->irq_sync || tg3_flag(tp, RESET_TASK_PENDING))
9511 spin_lock(&tp->lock);
9513 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717 ||
9514 tg3_flag(tp, 57765_CLASS))
9515 tg3_chk_missed_msi(tp);
9517 if (!tg3_flag(tp, TAGGED_STATUS)) {
9518 /* All of this garbage is because when using non-tagged
9519 * IRQ status the mailbox/status_block protocol the chip
9520 * uses with the cpu is race prone.
9522 if (tp->napi[0].hw_status->status & SD_STATUS_UPDATED) {
9523 tw32(GRC_LOCAL_CTRL,
9524 tp->grc_local_ctrl | GRC_LCLCTRL_SETINT);
9526 tw32(HOSTCC_MODE, tp->coalesce_mode |
9527 HOSTCC_MODE_ENABLE | HOSTCC_MODE_NOW);
9530 if (!(tr32(WDMAC_MODE) & WDMAC_MODE_ENABLE)) {
9531 spin_unlock(&tp->lock);
9532 tg3_reset_task_schedule(tp);
9537 /* This part only runs once per second. */
9538 if (!--tp->timer_counter) {
9539 if (tg3_flag(tp, 5705_PLUS))
9540 tg3_periodic_fetch_stats(tp);
9542 if (tp->setlpicnt && !--tp->setlpicnt)
9543 tg3_phy_eee_enable(tp);
9545 if (tg3_flag(tp, USE_LINKCHG_REG)) {
9549 mac_stat = tr32(MAC_STATUS);
9552 if (tp->phy_flags & TG3_PHYFLG_USE_MI_INTERRUPT) {
9553 if (mac_stat & MAC_STATUS_MI_INTERRUPT)
9555 } else if (mac_stat & MAC_STATUS_LNKSTATE_CHANGED)
9559 tg3_setup_phy(tp, 0);
9560 } else if (tg3_flag(tp, POLL_SERDES)) {
9561 u32 mac_stat = tr32(MAC_STATUS);
9564 if (netif_carrier_ok(tp->dev) &&
9565 (mac_stat & MAC_STATUS_LNKSTATE_CHANGED)) {
9568 if (!netif_carrier_ok(tp->dev) &&
9569 (mac_stat & (MAC_STATUS_PCS_SYNCED |
9570 MAC_STATUS_SIGNAL_DET))) {
9574 if (!tp->serdes_counter) {
9577 ~MAC_MODE_PORT_MODE_MASK));
9579 tw32_f(MAC_MODE, tp->mac_mode);
9582 tg3_setup_phy(tp, 0);
9584 } else if ((tp->phy_flags & TG3_PHYFLG_MII_SERDES) &&
9585 tg3_flag(tp, 5780_CLASS)) {
9586 tg3_serdes_parallel_detect(tp);
9589 tp->timer_counter = tp->timer_multiplier;
9592 /* Heartbeat is only sent once every 2 seconds.
9594 * The heartbeat is to tell the ASF firmware that the host
9595 * driver is still alive. In the event that the OS crashes,
9596 * ASF needs to reset the hardware to free up the FIFO space
9597 * that may be filled with rx packets destined for the host.
9598 * If the FIFO is full, ASF will no longer function properly.
9600 * Unintended resets have been reported on real time kernels
9601 * where the timer doesn't run on time. Netpoll will also have
9604 * The new FWCMD_NICDRV_ALIVE3 command tells the ASF firmware
9605 * to check the ring condition when the heartbeat is expiring
9606 * before doing the reset. This will prevent most unintended
9609 if (!--tp->asf_counter) {
9610 if (tg3_flag(tp, ENABLE_ASF) && !tg3_flag(tp, ENABLE_APE)) {
9611 tg3_wait_for_event_ack(tp);
9613 tg3_write_mem(tp, NIC_SRAM_FW_CMD_MBOX,
9614 FWCMD_NICDRV_ALIVE3);
9615 tg3_write_mem(tp, NIC_SRAM_FW_CMD_LEN_MBOX, 4);
9616 tg3_write_mem(tp, NIC_SRAM_FW_CMD_DATA_MBOX,
9617 TG3_FW_UPDATE_TIMEOUT_SEC);
9619 tg3_generate_fw_event(tp);
9621 tp->asf_counter = tp->asf_multiplier;
9624 spin_unlock(&tp->lock);
9627 tp->timer.expires = jiffies + tp->timer_offset;
9628 add_timer(&tp->timer);
9631 static int tg3_request_irq(struct tg3 *tp, int irq_num)
9634 unsigned long flags;
9636 struct tg3_napi *tnapi = &tp->napi[irq_num];
9638 if (tp->irq_cnt == 1)
9639 name = tp->dev->name;
9641 name = &tnapi->irq_lbl[0];
9642 snprintf(name, IFNAMSIZ, "%s-%d", tp->dev->name, irq_num);
9643 name[IFNAMSIZ-1] = 0;
9646 if (tg3_flag(tp, USING_MSI) || tg3_flag(tp, USING_MSIX)) {
9648 if (tg3_flag(tp, 1SHOT_MSI))
9653 if (tg3_flag(tp, TAGGED_STATUS))
9654 fn = tg3_interrupt_tagged;
9655 flags = IRQF_SHARED;
9658 return request_irq(tnapi->irq_vec, fn, flags, name, tnapi);
9661 static int tg3_test_interrupt(struct tg3 *tp)
9663 struct tg3_napi *tnapi = &tp->napi[0];
9664 struct net_device *dev = tp->dev;
9665 int err, i, intr_ok = 0;
9668 if (!netif_running(dev))
9671 tg3_disable_ints(tp);
9673 free_irq(tnapi->irq_vec, tnapi);
9676 * Turn off MSI one shot mode. Otherwise this test has no
9677 * observable way to know whether the interrupt was delivered.
9679 if (tg3_flag(tp, 57765_PLUS)) {
9680 val = tr32(MSGINT_MODE) | MSGINT_MODE_ONE_SHOT_DISABLE;
9681 tw32(MSGINT_MODE, val);
9684 err = request_irq(tnapi->irq_vec, tg3_test_isr,
9685 IRQF_SHARED | IRQF_SAMPLE_RANDOM, dev->name, tnapi);
9689 tnapi->hw_status->status &= ~SD_STATUS_UPDATED;
9690 tg3_enable_ints(tp);
9692 tw32_f(HOSTCC_MODE, tp->coalesce_mode | HOSTCC_MODE_ENABLE |
9695 for (i = 0; i < 5; i++) {
9696 u32 int_mbox, misc_host_ctrl;
9698 int_mbox = tr32_mailbox(tnapi->int_mbox);
9699 misc_host_ctrl = tr32(TG3PCI_MISC_HOST_CTRL);
9701 if ((int_mbox != 0) ||
9702 (misc_host_ctrl & MISC_HOST_CTRL_MASK_PCI_INT)) {
9707 if (tg3_flag(tp, 57765_PLUS) &&
9708 tnapi->hw_status->status_tag != tnapi->last_tag)
9709 tw32_mailbox_f(tnapi->int_mbox, tnapi->last_tag << 24);
9714 tg3_disable_ints(tp);
9716 free_irq(tnapi->irq_vec, tnapi);
9718 err = tg3_request_irq(tp, 0);
9724 /* Reenable MSI one shot mode. */
9725 if (tg3_flag(tp, 57765_PLUS) && tg3_flag(tp, 1SHOT_MSI)) {
9726 val = tr32(MSGINT_MODE) & ~MSGINT_MODE_ONE_SHOT_DISABLE;
9727 tw32(MSGINT_MODE, val);
9735 /* Returns 0 if MSI test succeeds or MSI test fails and INTx mode is
9736 * successfully restored
9738 static int tg3_test_msi(struct tg3 *tp)
9743 if (!tg3_flag(tp, USING_MSI))
9746 /* Turn off SERR reporting in case MSI terminates with Master
9749 pci_read_config_word(tp->pdev, PCI_COMMAND, &pci_cmd);
9750 pci_write_config_word(tp->pdev, PCI_COMMAND,
9751 pci_cmd & ~PCI_COMMAND_SERR);
9753 err = tg3_test_interrupt(tp);
9755 pci_write_config_word(tp->pdev, PCI_COMMAND, pci_cmd);
9760 /* other failures */
9764 /* MSI test failed, go back to INTx mode */
9765 netdev_warn(tp->dev, "No interrupt was generated using MSI. Switching "
9766 "to INTx mode. Please report this failure to the PCI "
9767 "maintainer and include system chipset information\n");
9769 free_irq(tp->napi[0].irq_vec, &tp->napi[0]);
9771 pci_disable_msi(tp->pdev);
9773 tg3_flag_clear(tp, USING_MSI);
9774 tp->napi[0].irq_vec = tp->pdev->irq;
9776 err = tg3_request_irq(tp, 0);
9780 /* Need to reset the chip because the MSI cycle may have terminated
9781 * with Master Abort.
9783 tg3_full_lock(tp, 1);
9785 tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
9786 err = tg3_init_hw(tp, 1);
9788 tg3_full_unlock(tp);
9791 free_irq(tp->napi[0].irq_vec, &tp->napi[0]);
9796 static int tg3_request_firmware(struct tg3 *tp)
9798 const __be32 *fw_data;
9800 if (request_firmware(&tp->fw, tp->fw_needed, &tp->pdev->dev)) {
9801 netdev_err(tp->dev, "Failed to load firmware \"%s\"\n",
9806 fw_data = (void *)tp->fw->data;
9808 /* Firmware blob starts with version numbers, followed by
9809 * start address and _full_ length including BSS sections
9810 * (which must be longer than the actual data, of course
9813 tp->fw_len = be32_to_cpu(fw_data[2]); /* includes bss */
9814 if (tp->fw_len < (tp->fw->size - 12)) {
9815 netdev_err(tp->dev, "bogus length %d in \"%s\"\n",
9816 tp->fw_len, tp->fw_needed);
9817 release_firmware(tp->fw);
9822 /* We no longer need firmware; we have it. */
9823 tp->fw_needed = NULL;
9827 static bool tg3_enable_msix(struct tg3 *tp)
9830 struct msix_entry msix_ent[tp->irq_max];
9832 tp->irq_cnt = num_online_cpus();
9833 if (tp->irq_cnt > 1) {
9834 /* We want as many rx rings enabled as there are cpus.
9835 * In multiqueue MSI-X mode, the first MSI-X vector
9836 * only deals with link interrupts, etc, so we add
9837 * one to the number of vectors we are requesting.
9839 tp->irq_cnt = min_t(unsigned, tp->irq_cnt + 1, tp->irq_max);
9842 for (i = 0; i < tp->irq_max; i++) {
9843 msix_ent[i].entry = i;
9844 msix_ent[i].vector = 0;
9847 rc = pci_enable_msix(tp->pdev, msix_ent, tp->irq_cnt);
9850 } else if (rc != 0) {
9851 if (pci_enable_msix(tp->pdev, msix_ent, rc))
9853 netdev_notice(tp->dev, "Requested %d MSI-X vectors, received %d\n",
9858 for (i = 0; i < tp->irq_max; i++)
9859 tp->napi[i].irq_vec = msix_ent[i].vector;
9861 netif_set_real_num_tx_queues(tp->dev, 1);
9862 rc = tp->irq_cnt > 1 ? tp->irq_cnt - 1 : 1;
9863 if (netif_set_real_num_rx_queues(tp->dev, rc)) {
9864 pci_disable_msix(tp->pdev);
9868 if (tp->irq_cnt > 1) {
9869 tg3_flag_set(tp, ENABLE_RSS);
9871 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5719 ||
9872 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5720) {
9873 tg3_flag_set(tp, ENABLE_TSS);
9874 netif_set_real_num_tx_queues(tp->dev, tp->irq_cnt - 1);
9881 static void tg3_ints_init(struct tg3 *tp)
9883 if ((tg3_flag(tp, SUPPORT_MSI) || tg3_flag(tp, SUPPORT_MSIX)) &&
9884 !tg3_flag(tp, TAGGED_STATUS)) {
9885 /* All MSI supporting chips should support tagged
9886 * status. Assert that this is the case.
9888 netdev_warn(tp->dev,
9889 "MSI without TAGGED_STATUS? Not using MSI\n");
9893 if (tg3_flag(tp, SUPPORT_MSIX) && tg3_enable_msix(tp))
9894 tg3_flag_set(tp, USING_MSIX);
9895 else if (tg3_flag(tp, SUPPORT_MSI) && pci_enable_msi(tp->pdev) == 0)
9896 tg3_flag_set(tp, USING_MSI);
9898 if (tg3_flag(tp, USING_MSI) || tg3_flag(tp, USING_MSIX)) {
9899 u32 msi_mode = tr32(MSGINT_MODE);
9900 if (tg3_flag(tp, USING_MSIX) && tp->irq_cnt > 1)
9901 msi_mode |= MSGINT_MODE_MULTIVEC_EN;
9902 if (!tg3_flag(tp, 1SHOT_MSI))
9903 msi_mode |= MSGINT_MODE_ONE_SHOT_DISABLE;
9904 tw32(MSGINT_MODE, msi_mode | MSGINT_MODE_ENABLE);
9907 if (!tg3_flag(tp, USING_MSIX)) {
9909 tp->napi[0].irq_vec = tp->pdev->irq;
9910 netif_set_real_num_tx_queues(tp->dev, 1);
9911 netif_set_real_num_rx_queues(tp->dev, 1);
9915 static void tg3_ints_fini(struct tg3 *tp)
9917 if (tg3_flag(tp, USING_MSIX))
9918 pci_disable_msix(tp->pdev);
9919 else if (tg3_flag(tp, USING_MSI))
9920 pci_disable_msi(tp->pdev);
9921 tg3_flag_clear(tp, USING_MSI);
9922 tg3_flag_clear(tp, USING_MSIX);
9923 tg3_flag_clear(tp, ENABLE_RSS);
9924 tg3_flag_clear(tp, ENABLE_TSS);
9927 static int tg3_open(struct net_device *dev)
9929 struct tg3 *tp = netdev_priv(dev);
9932 if (tp->fw_needed) {
9933 err = tg3_request_firmware(tp);
9934 if (tp->pci_chip_rev_id == CHIPREV_ID_5701_A0) {
9938 netdev_warn(tp->dev, "TSO capability disabled\n");
9939 tg3_flag_clear(tp, TSO_CAPABLE);
9940 } else if (!tg3_flag(tp, TSO_CAPABLE)) {
9941 netdev_notice(tp->dev, "TSO capability restored\n");
9942 tg3_flag_set(tp, TSO_CAPABLE);
9946 netif_carrier_off(tp->dev);
9948 err = tg3_power_up(tp);
9952 tg3_full_lock(tp, 0);
9954 tg3_disable_ints(tp);
9955 tg3_flag_clear(tp, INIT_COMPLETE);
9957 tg3_full_unlock(tp);
9960 * Setup interrupts first so we know how
9961 * many NAPI resources to allocate
9965 tg3_rss_check_indir_tbl(tp);
9967 /* The placement of this call is tied
9968 * to the setup and use of Host TX descriptors.
9970 err = tg3_alloc_consistent(tp);
9976 tg3_napi_enable(tp);
9978 for (i = 0; i < tp->irq_cnt; i++) {
9979 struct tg3_napi *tnapi = &tp->napi[i];
9980 err = tg3_request_irq(tp, i);
9982 for (i--; i >= 0; i--) {
9983 tnapi = &tp->napi[i];
9984 free_irq(tnapi->irq_vec, tnapi);
9990 tg3_full_lock(tp, 0);
9992 err = tg3_init_hw(tp, 1);
9994 tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
9997 if (tg3_flag(tp, TAGGED_STATUS) &&
9998 GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5717 &&
9999 !tg3_flag(tp, 57765_CLASS))
10000 tp->timer_offset = HZ;
10002 tp->timer_offset = HZ / 10;
10004 BUG_ON(tp->timer_offset > HZ);
10005 tp->timer_counter = tp->timer_multiplier =
10006 (HZ / tp->timer_offset);
10007 tp->asf_counter = tp->asf_multiplier =
10008 ((HZ / tp->timer_offset) * 2);
10010 init_timer(&tp->timer);
10011 tp->timer.expires = jiffies + tp->timer_offset;
10012 tp->timer.data = (unsigned long) tp;
10013 tp->timer.function = tg3_timer;
10016 tg3_full_unlock(tp);
10021 if (tg3_flag(tp, USING_MSI)) {
10022 err = tg3_test_msi(tp);
10025 tg3_full_lock(tp, 0);
10026 tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
10027 tg3_free_rings(tp);
10028 tg3_full_unlock(tp);
10033 if (!tg3_flag(tp, 57765_PLUS) && tg3_flag(tp, USING_MSI)) {
10034 u32 val = tr32(PCIE_TRANSACTION_CFG);
10036 tw32(PCIE_TRANSACTION_CFG,
10037 val | PCIE_TRANS_CFG_1SHOT_MSI);
10043 tg3_full_lock(tp, 0);
10045 add_timer(&tp->timer);
10046 tg3_flag_set(tp, INIT_COMPLETE);
10047 tg3_enable_ints(tp);
10049 tg3_full_unlock(tp);
10051 netif_tx_start_all_queues(dev);
10054 * Reset loopback feature if it was turned on while the device was down
10055 * make sure that it's installed properly now.
10057 if (dev->features & NETIF_F_LOOPBACK)
10058 tg3_set_loopback(dev, dev->features);
10063 for (i = tp->irq_cnt - 1; i >= 0; i--) {
10064 struct tg3_napi *tnapi = &tp->napi[i];
10065 free_irq(tnapi->irq_vec, tnapi);
10069 tg3_napi_disable(tp);
10071 tg3_free_consistent(tp);
10075 tg3_frob_aux_power(tp, false);
10076 pci_set_power_state(tp->pdev, PCI_D3hot);
10080 static int tg3_close(struct net_device *dev)
10083 struct tg3 *tp = netdev_priv(dev);
10085 tg3_napi_disable(tp);
10086 tg3_reset_task_cancel(tp);
10088 netif_tx_stop_all_queues(dev);
10090 del_timer_sync(&tp->timer);
10094 tg3_full_lock(tp, 1);
10096 tg3_disable_ints(tp);
10098 tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
10099 tg3_free_rings(tp);
10100 tg3_flag_clear(tp, INIT_COMPLETE);
10102 tg3_full_unlock(tp);
10104 for (i = tp->irq_cnt - 1; i >= 0; i--) {
10105 struct tg3_napi *tnapi = &tp->napi[i];
10106 free_irq(tnapi->irq_vec, tnapi);
10111 /* Clear stats across close / open calls */
10112 memset(&tp->net_stats_prev, 0, sizeof(tp->net_stats_prev));
10113 memset(&tp->estats_prev, 0, sizeof(tp->estats_prev));
10117 tg3_free_consistent(tp);
10119 tg3_power_down(tp);
10121 netif_carrier_off(tp->dev);
10126 static inline u64 get_stat64(tg3_stat64_t *val)
10128 return ((u64)val->high << 32) | ((u64)val->low);
10131 static u64 calc_crc_errors(struct tg3 *tp)
10133 struct tg3_hw_stats *hw_stats = tp->hw_stats;
10135 if (!(tp->phy_flags & TG3_PHYFLG_PHY_SERDES) &&
10136 (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
10137 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701)) {
10140 spin_lock_bh(&tp->lock);
10141 if (!tg3_readphy(tp, MII_TG3_TEST1, &val)) {
10142 tg3_writephy(tp, MII_TG3_TEST1,
10143 val | MII_TG3_TEST1_CRC_EN);
10144 tg3_readphy(tp, MII_TG3_RXR_COUNTERS, &val);
10147 spin_unlock_bh(&tp->lock);
10149 tp->phy_crc_errors += val;
10151 return tp->phy_crc_errors;
10154 return get_stat64(&hw_stats->rx_fcs_errors);
10157 #define ESTAT_ADD(member) \
10158 estats->member = old_estats->member + \
10159 get_stat64(&hw_stats->member)
10161 static struct tg3_ethtool_stats *tg3_get_estats(struct tg3 *tp,
10162 struct tg3_ethtool_stats *estats)
10164 struct tg3_ethtool_stats *old_estats = &tp->estats_prev;
10165 struct tg3_hw_stats *hw_stats = tp->hw_stats;
10167 ESTAT_ADD(rx_octets);
10168 ESTAT_ADD(rx_fragments);
10169 ESTAT_ADD(rx_ucast_packets);
10170 ESTAT_ADD(rx_mcast_packets);
10171 ESTAT_ADD(rx_bcast_packets);
10172 ESTAT_ADD(rx_fcs_errors);
10173 ESTAT_ADD(rx_align_errors);
10174 ESTAT_ADD(rx_xon_pause_rcvd);
10175 ESTAT_ADD(rx_xoff_pause_rcvd);
10176 ESTAT_ADD(rx_mac_ctrl_rcvd);
10177 ESTAT_ADD(rx_xoff_entered);
10178 ESTAT_ADD(rx_frame_too_long_errors);
10179 ESTAT_ADD(rx_jabbers);
10180 ESTAT_ADD(rx_undersize_packets);
10181 ESTAT_ADD(rx_in_length_errors);
10182 ESTAT_ADD(rx_out_length_errors);
10183 ESTAT_ADD(rx_64_or_less_octet_packets);
10184 ESTAT_ADD(rx_65_to_127_octet_packets);
10185 ESTAT_ADD(rx_128_to_255_octet_packets);
10186 ESTAT_ADD(rx_256_to_511_octet_packets);
10187 ESTAT_ADD(rx_512_to_1023_octet_packets);
10188 ESTAT_ADD(rx_1024_to_1522_octet_packets);
10189 ESTAT_ADD(rx_1523_to_2047_octet_packets);
10190 ESTAT_ADD(rx_2048_to_4095_octet_packets);
10191 ESTAT_ADD(rx_4096_to_8191_octet_packets);
10192 ESTAT_ADD(rx_8192_to_9022_octet_packets);
10194 ESTAT_ADD(tx_octets);
10195 ESTAT_ADD(tx_collisions);
10196 ESTAT_ADD(tx_xon_sent);
10197 ESTAT_ADD(tx_xoff_sent);
10198 ESTAT_ADD(tx_flow_control);
10199 ESTAT_ADD(tx_mac_errors);
10200 ESTAT_ADD(tx_single_collisions);
10201 ESTAT_ADD(tx_mult_collisions);
10202 ESTAT_ADD(tx_deferred);
10203 ESTAT_ADD(tx_excessive_collisions);
10204 ESTAT_ADD(tx_late_collisions);
10205 ESTAT_ADD(tx_collide_2times);
10206 ESTAT_ADD(tx_collide_3times);
10207 ESTAT_ADD(tx_collide_4times);
10208 ESTAT_ADD(tx_collide_5times);
10209 ESTAT_ADD(tx_collide_6times);
10210 ESTAT_ADD(tx_collide_7times);
10211 ESTAT_ADD(tx_collide_8times);
10212 ESTAT_ADD(tx_collide_9times);
10213 ESTAT_ADD(tx_collide_10times);
10214 ESTAT_ADD(tx_collide_11times);
10215 ESTAT_ADD(tx_collide_12times);
10216 ESTAT_ADD(tx_collide_13times);
10217 ESTAT_ADD(tx_collide_14times);
10218 ESTAT_ADD(tx_collide_15times);
10219 ESTAT_ADD(tx_ucast_packets);
10220 ESTAT_ADD(tx_mcast_packets);
10221 ESTAT_ADD(tx_bcast_packets);
10222 ESTAT_ADD(tx_carrier_sense_errors);
10223 ESTAT_ADD(tx_discards);
10224 ESTAT_ADD(tx_errors);
10226 ESTAT_ADD(dma_writeq_full);
10227 ESTAT_ADD(dma_write_prioq_full);
10228 ESTAT_ADD(rxbds_empty);
10229 ESTAT_ADD(rx_discards);
10230 ESTAT_ADD(rx_errors);
10231 ESTAT_ADD(rx_threshold_hit);
10233 ESTAT_ADD(dma_readq_full);
10234 ESTAT_ADD(dma_read_prioq_full);
10235 ESTAT_ADD(tx_comp_queue_full);
10237 ESTAT_ADD(ring_set_send_prod_index);
10238 ESTAT_ADD(ring_status_update);
10239 ESTAT_ADD(nic_irqs);
10240 ESTAT_ADD(nic_avoided_irqs);
10241 ESTAT_ADD(nic_tx_threshold_hit);
10243 ESTAT_ADD(mbuf_lwm_thresh_hit);
10248 static struct rtnl_link_stats64 *tg3_get_stats64(struct net_device *dev,
10249 struct rtnl_link_stats64 *stats)
10251 struct tg3 *tp = netdev_priv(dev);
10252 struct rtnl_link_stats64 *old_stats = &tp->net_stats_prev;
10253 struct tg3_hw_stats *hw_stats = tp->hw_stats;
10258 stats->rx_packets = old_stats->rx_packets +
10259 get_stat64(&hw_stats->rx_ucast_packets) +
10260 get_stat64(&hw_stats->rx_mcast_packets) +
10261 get_stat64(&hw_stats->rx_bcast_packets);
10263 stats->tx_packets = old_stats->tx_packets +
10264 get_stat64(&hw_stats->tx_ucast_packets) +
10265 get_stat64(&hw_stats->tx_mcast_packets) +
10266 get_stat64(&hw_stats->tx_bcast_packets);
10268 stats->rx_bytes = old_stats->rx_bytes +
10269 get_stat64(&hw_stats->rx_octets);
10270 stats->tx_bytes = old_stats->tx_bytes +
10271 get_stat64(&hw_stats->tx_octets);
10273 stats->rx_errors = old_stats->rx_errors +
10274 get_stat64(&hw_stats->rx_errors);
10275 stats->tx_errors = old_stats->tx_errors +
10276 get_stat64(&hw_stats->tx_errors) +
10277 get_stat64(&hw_stats->tx_mac_errors) +
10278 get_stat64(&hw_stats->tx_carrier_sense_errors) +
10279 get_stat64(&hw_stats->tx_discards);
10281 stats->multicast = old_stats->multicast +
10282 get_stat64(&hw_stats->rx_mcast_packets);
10283 stats->collisions = old_stats->collisions +
10284 get_stat64(&hw_stats->tx_collisions);
10286 stats->rx_length_errors = old_stats->rx_length_errors +
10287 get_stat64(&hw_stats->rx_frame_too_long_errors) +
10288 get_stat64(&hw_stats->rx_undersize_packets);
10290 stats->rx_over_errors = old_stats->rx_over_errors +
10291 get_stat64(&hw_stats->rxbds_empty);
10292 stats->rx_frame_errors = old_stats->rx_frame_errors +
10293 get_stat64(&hw_stats->rx_align_errors);
10294 stats->tx_aborted_errors = old_stats->tx_aborted_errors +
10295 get_stat64(&hw_stats->tx_discards);
10296 stats->tx_carrier_errors = old_stats->tx_carrier_errors +
10297 get_stat64(&hw_stats->tx_carrier_sense_errors);
10299 stats->rx_crc_errors = old_stats->rx_crc_errors +
10300 calc_crc_errors(tp);
10302 stats->rx_missed_errors = old_stats->rx_missed_errors +
10303 get_stat64(&hw_stats->rx_discards);
10305 stats->rx_dropped = tp->rx_dropped;
10306 stats->tx_dropped = tp->tx_dropped;
10311 static int tg3_get_regs_len(struct net_device *dev)
10313 return TG3_REG_BLK_SIZE;
10316 static void tg3_get_regs(struct net_device *dev,
10317 struct ethtool_regs *regs, void *_p)
10319 struct tg3 *tp = netdev_priv(dev);
10323 memset(_p, 0, TG3_REG_BLK_SIZE);
10325 if (tp->phy_flags & TG3_PHYFLG_IS_LOW_POWER)
10328 tg3_full_lock(tp, 0);
10330 tg3_dump_legacy_regs(tp, (u32 *)_p);
10332 tg3_full_unlock(tp);
10335 static int tg3_get_eeprom_len(struct net_device *dev)
10337 struct tg3 *tp = netdev_priv(dev);
10339 return tp->nvram_size;
10342 static int tg3_get_eeprom(struct net_device *dev, struct ethtool_eeprom *eeprom, u8 *data)
10344 struct tg3 *tp = netdev_priv(dev);
10347 u32 i, offset, len, b_offset, b_count;
10350 if (tg3_flag(tp, NO_NVRAM))
10353 if (tp->phy_flags & TG3_PHYFLG_IS_LOW_POWER)
10356 offset = eeprom->offset;
10360 eeprom->magic = TG3_EEPROM_MAGIC;
10363 /* adjustments to start on required 4 byte boundary */
10364 b_offset = offset & 3;
10365 b_count = 4 - b_offset;
10366 if (b_count > len) {
10367 /* i.e. offset=1 len=2 */
10370 ret = tg3_nvram_read_be32(tp, offset-b_offset, &val);
10373 memcpy(data, ((char *)&val) + b_offset, b_count);
10376 eeprom->len += b_count;
10379 /* read bytes up to the last 4 byte boundary */
10380 pd = &data[eeprom->len];
10381 for (i = 0; i < (len - (len & 3)); i += 4) {
10382 ret = tg3_nvram_read_be32(tp, offset + i, &val);
10387 memcpy(pd + i, &val, 4);
10392 /* read last bytes not ending on 4 byte boundary */
10393 pd = &data[eeprom->len];
10395 b_offset = offset + len - b_count;
10396 ret = tg3_nvram_read_be32(tp, b_offset, &val);
10399 memcpy(pd, &val, b_count);
10400 eeprom->len += b_count;
10405 static int tg3_set_eeprom(struct net_device *dev, struct ethtool_eeprom *eeprom, u8 *data)
10407 struct tg3 *tp = netdev_priv(dev);
10409 u32 offset, len, b_offset, odd_len;
10413 if (tp->phy_flags & TG3_PHYFLG_IS_LOW_POWER)
10416 if (tg3_flag(tp, NO_NVRAM) ||
10417 eeprom->magic != TG3_EEPROM_MAGIC)
10420 offset = eeprom->offset;
10423 if ((b_offset = (offset & 3))) {
10424 /* adjustments to start on required 4 byte boundary */
10425 ret = tg3_nvram_read_be32(tp, offset-b_offset, &start);
10436 /* adjustments to end on required 4 byte boundary */
10438 len = (len + 3) & ~3;
10439 ret = tg3_nvram_read_be32(tp, offset+len-4, &end);
10445 if (b_offset || odd_len) {
10446 buf = kmalloc(len, GFP_KERNEL);
10450 memcpy(buf, &start, 4);
10452 memcpy(buf+len-4, &end, 4);
10453 memcpy(buf + b_offset, data, eeprom->len);
10456 ret = tg3_nvram_write_block(tp, offset, len, buf);
10464 static int tg3_get_settings(struct net_device *dev, struct ethtool_cmd *cmd)
10466 struct tg3 *tp = netdev_priv(dev);
10468 if (tg3_flag(tp, USE_PHYLIB)) {
10469 struct phy_device *phydev;
10470 if (!(tp->phy_flags & TG3_PHYFLG_IS_CONNECTED))
10472 phydev = tp->mdio_bus->phy_map[TG3_PHY_MII_ADDR];
10473 return phy_ethtool_gset(phydev, cmd);
10476 cmd->supported = (SUPPORTED_Autoneg);
10478 if (!(tp->phy_flags & TG3_PHYFLG_10_100_ONLY))
10479 cmd->supported |= (SUPPORTED_1000baseT_Half |
10480 SUPPORTED_1000baseT_Full);
10482 if (!(tp->phy_flags & TG3_PHYFLG_ANY_SERDES)) {
10483 cmd->supported |= (SUPPORTED_100baseT_Half |
10484 SUPPORTED_100baseT_Full |
10485 SUPPORTED_10baseT_Half |
10486 SUPPORTED_10baseT_Full |
10488 cmd->port = PORT_TP;
10490 cmd->supported |= SUPPORTED_FIBRE;
10491 cmd->port = PORT_FIBRE;
10494 cmd->advertising = tp->link_config.advertising;
10495 if (tg3_flag(tp, PAUSE_AUTONEG)) {
10496 if (tp->link_config.flowctrl & FLOW_CTRL_RX) {
10497 if (tp->link_config.flowctrl & FLOW_CTRL_TX) {
10498 cmd->advertising |= ADVERTISED_Pause;
10500 cmd->advertising |= ADVERTISED_Pause |
10501 ADVERTISED_Asym_Pause;
10503 } else if (tp->link_config.flowctrl & FLOW_CTRL_TX) {
10504 cmd->advertising |= ADVERTISED_Asym_Pause;
10507 if (netif_running(dev) && netif_carrier_ok(dev)) {
10508 ethtool_cmd_speed_set(cmd, tp->link_config.active_speed);
10509 cmd->duplex = tp->link_config.active_duplex;
10510 cmd->lp_advertising = tp->link_config.rmt_adv;
10511 if (!(tp->phy_flags & TG3_PHYFLG_ANY_SERDES)) {
10512 if (tp->phy_flags & TG3_PHYFLG_MDIX_STATE)
10513 cmd->eth_tp_mdix = ETH_TP_MDI_X;
10515 cmd->eth_tp_mdix = ETH_TP_MDI;
10518 ethtool_cmd_speed_set(cmd, SPEED_UNKNOWN);
10519 cmd->duplex = DUPLEX_UNKNOWN;
10520 cmd->eth_tp_mdix = ETH_TP_MDI_INVALID;
10522 cmd->phy_address = tp->phy_addr;
10523 cmd->transceiver = XCVR_INTERNAL;
10524 cmd->autoneg = tp->link_config.autoneg;
10530 static int tg3_set_settings(struct net_device *dev, struct ethtool_cmd *cmd)
10532 struct tg3 *tp = netdev_priv(dev);
10533 u32 speed = ethtool_cmd_speed(cmd);
10535 if (tg3_flag(tp, USE_PHYLIB)) {
10536 struct phy_device *phydev;
10537 if (!(tp->phy_flags & TG3_PHYFLG_IS_CONNECTED))
10539 phydev = tp->mdio_bus->phy_map[TG3_PHY_MII_ADDR];
10540 return phy_ethtool_sset(phydev, cmd);
10543 if (cmd->autoneg != AUTONEG_ENABLE &&
10544 cmd->autoneg != AUTONEG_DISABLE)
10547 if (cmd->autoneg == AUTONEG_DISABLE &&
10548 cmd->duplex != DUPLEX_FULL &&
10549 cmd->duplex != DUPLEX_HALF)
10552 if (cmd->autoneg == AUTONEG_ENABLE) {
10553 u32 mask = ADVERTISED_Autoneg |
10555 ADVERTISED_Asym_Pause;
10557 if (!(tp->phy_flags & TG3_PHYFLG_10_100_ONLY))
10558 mask |= ADVERTISED_1000baseT_Half |
10559 ADVERTISED_1000baseT_Full;
10561 if (!(tp->phy_flags & TG3_PHYFLG_ANY_SERDES))
10562 mask |= ADVERTISED_100baseT_Half |
10563 ADVERTISED_100baseT_Full |
10564 ADVERTISED_10baseT_Half |
10565 ADVERTISED_10baseT_Full |
10568 mask |= ADVERTISED_FIBRE;
10570 if (cmd->advertising & ~mask)
10573 mask &= (ADVERTISED_1000baseT_Half |
10574 ADVERTISED_1000baseT_Full |
10575 ADVERTISED_100baseT_Half |
10576 ADVERTISED_100baseT_Full |
10577 ADVERTISED_10baseT_Half |
10578 ADVERTISED_10baseT_Full);
10580 cmd->advertising &= mask;
10582 if (tp->phy_flags & TG3_PHYFLG_ANY_SERDES) {
10583 if (speed != SPEED_1000)
10586 if (cmd->duplex != DUPLEX_FULL)
10589 if (speed != SPEED_100 &&
10595 tg3_full_lock(tp, 0);
10597 tp->link_config.autoneg = cmd->autoneg;
10598 if (cmd->autoneg == AUTONEG_ENABLE) {
10599 tp->link_config.advertising = (cmd->advertising |
10600 ADVERTISED_Autoneg);
10601 tp->link_config.speed = SPEED_UNKNOWN;
10602 tp->link_config.duplex = DUPLEX_UNKNOWN;
10604 tp->link_config.advertising = 0;
10605 tp->link_config.speed = speed;
10606 tp->link_config.duplex = cmd->duplex;
10609 if (netif_running(dev))
10610 tg3_setup_phy(tp, 1);
10612 tg3_full_unlock(tp);
10617 static void tg3_get_drvinfo(struct net_device *dev, struct ethtool_drvinfo *info)
10619 struct tg3 *tp = netdev_priv(dev);
10621 strlcpy(info->driver, DRV_MODULE_NAME, sizeof(info->driver));
10622 strlcpy(info->version, DRV_MODULE_VERSION, sizeof(info->version));
10623 strlcpy(info->fw_version, tp->fw_ver, sizeof(info->fw_version));
10624 strlcpy(info->bus_info, pci_name(tp->pdev), sizeof(info->bus_info));
10627 static void tg3_get_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
10629 struct tg3 *tp = netdev_priv(dev);
10631 if (tg3_flag(tp, WOL_CAP) && device_can_wakeup(&tp->pdev->dev))
10632 wol->supported = WAKE_MAGIC;
10634 wol->supported = 0;
10636 if (tg3_flag(tp, WOL_ENABLE) && device_can_wakeup(&tp->pdev->dev))
10637 wol->wolopts = WAKE_MAGIC;
10638 memset(&wol->sopass, 0, sizeof(wol->sopass));
10641 static int tg3_set_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
10643 struct tg3 *tp = netdev_priv(dev);
10644 struct device *dp = &tp->pdev->dev;
10646 if (wol->wolopts & ~WAKE_MAGIC)
10648 if ((wol->wolopts & WAKE_MAGIC) &&
10649 !(tg3_flag(tp, WOL_CAP) && device_can_wakeup(dp)))
10652 device_set_wakeup_enable(dp, wol->wolopts & WAKE_MAGIC);
10654 spin_lock_bh(&tp->lock);
10655 if (device_may_wakeup(dp))
10656 tg3_flag_set(tp, WOL_ENABLE);
10658 tg3_flag_clear(tp, WOL_ENABLE);
10659 spin_unlock_bh(&tp->lock);
10664 static u32 tg3_get_msglevel(struct net_device *dev)
10666 struct tg3 *tp = netdev_priv(dev);
10667 return tp->msg_enable;
10670 static void tg3_set_msglevel(struct net_device *dev, u32 value)
10672 struct tg3 *tp = netdev_priv(dev);
10673 tp->msg_enable = value;
10676 static int tg3_nway_reset(struct net_device *dev)
10678 struct tg3 *tp = netdev_priv(dev);
10681 if (!netif_running(dev))
10684 if (tp->phy_flags & TG3_PHYFLG_PHY_SERDES)
10687 if (tg3_flag(tp, USE_PHYLIB)) {
10688 if (!(tp->phy_flags & TG3_PHYFLG_IS_CONNECTED))
10690 r = phy_start_aneg(tp->mdio_bus->phy_map[TG3_PHY_MII_ADDR]);
10694 spin_lock_bh(&tp->lock);
10696 tg3_readphy(tp, MII_BMCR, &bmcr);
10697 if (!tg3_readphy(tp, MII_BMCR, &bmcr) &&
10698 ((bmcr & BMCR_ANENABLE) ||
10699 (tp->phy_flags & TG3_PHYFLG_PARALLEL_DETECT))) {
10700 tg3_writephy(tp, MII_BMCR, bmcr | BMCR_ANRESTART |
10704 spin_unlock_bh(&tp->lock);
10710 static void tg3_get_ringparam(struct net_device *dev, struct ethtool_ringparam *ering)
10712 struct tg3 *tp = netdev_priv(dev);
10714 ering->rx_max_pending = tp->rx_std_ring_mask;
10715 if (tg3_flag(tp, JUMBO_RING_ENABLE))
10716 ering->rx_jumbo_max_pending = tp->rx_jmb_ring_mask;
10718 ering->rx_jumbo_max_pending = 0;
10720 ering->tx_max_pending = TG3_TX_RING_SIZE - 1;
10722 ering->rx_pending = tp->rx_pending;
10723 if (tg3_flag(tp, JUMBO_RING_ENABLE))
10724 ering->rx_jumbo_pending = tp->rx_jumbo_pending;
10726 ering->rx_jumbo_pending = 0;
10728 ering->tx_pending = tp->napi[0].tx_pending;
10731 static int tg3_set_ringparam(struct net_device *dev, struct ethtool_ringparam *ering)
10733 struct tg3 *tp = netdev_priv(dev);
10734 int i, irq_sync = 0, err = 0;
10736 if ((ering->rx_pending > tp->rx_std_ring_mask) ||
10737 (ering->rx_jumbo_pending > tp->rx_jmb_ring_mask) ||
10738 (ering->tx_pending > TG3_TX_RING_SIZE - 1) ||
10739 (ering->tx_pending <= MAX_SKB_FRAGS) ||
10740 (tg3_flag(tp, TSO_BUG) &&
10741 (ering->tx_pending <= (MAX_SKB_FRAGS * 3))))
10744 if (netif_running(dev)) {
10746 tg3_netif_stop(tp);
10750 tg3_full_lock(tp, irq_sync);
10752 tp->rx_pending = ering->rx_pending;
10754 if (tg3_flag(tp, MAX_RXPEND_64) &&
10755 tp->rx_pending > 63)
10756 tp->rx_pending = 63;
10757 tp->rx_jumbo_pending = ering->rx_jumbo_pending;
10759 for (i = 0; i < tp->irq_max; i++)
10760 tp->napi[i].tx_pending = ering->tx_pending;
10762 if (netif_running(dev)) {
10763 tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
10764 err = tg3_restart_hw(tp, 1);
10766 tg3_netif_start(tp);
10769 tg3_full_unlock(tp);
10771 if (irq_sync && !err)
10777 static void tg3_get_pauseparam(struct net_device *dev, struct ethtool_pauseparam *epause)
10779 struct tg3 *tp = netdev_priv(dev);
10781 epause->autoneg = !!tg3_flag(tp, PAUSE_AUTONEG);
10783 if (tp->link_config.flowctrl & FLOW_CTRL_RX)
10784 epause->rx_pause = 1;
10786 epause->rx_pause = 0;
10788 if (tp->link_config.flowctrl & FLOW_CTRL_TX)
10789 epause->tx_pause = 1;
10791 epause->tx_pause = 0;
10794 static int tg3_set_pauseparam(struct net_device *dev, struct ethtool_pauseparam *epause)
10796 struct tg3 *tp = netdev_priv(dev);
10799 if (tg3_flag(tp, USE_PHYLIB)) {
10801 struct phy_device *phydev;
10803 phydev = tp->mdio_bus->phy_map[TG3_PHY_MII_ADDR];
10805 if (!(phydev->supported & SUPPORTED_Pause) ||
10806 (!(phydev->supported & SUPPORTED_Asym_Pause) &&
10807 (epause->rx_pause != epause->tx_pause)))
10810 tp->link_config.flowctrl = 0;
10811 if (epause->rx_pause) {
10812 tp->link_config.flowctrl |= FLOW_CTRL_RX;
10814 if (epause->tx_pause) {
10815 tp->link_config.flowctrl |= FLOW_CTRL_TX;
10816 newadv = ADVERTISED_Pause;
10818 newadv = ADVERTISED_Pause |
10819 ADVERTISED_Asym_Pause;
10820 } else if (epause->tx_pause) {
10821 tp->link_config.flowctrl |= FLOW_CTRL_TX;
10822 newadv = ADVERTISED_Asym_Pause;
10826 if (epause->autoneg)
10827 tg3_flag_set(tp, PAUSE_AUTONEG);
10829 tg3_flag_clear(tp, PAUSE_AUTONEG);
10831 if (tp->phy_flags & TG3_PHYFLG_IS_CONNECTED) {
10832 u32 oldadv = phydev->advertising &
10833 (ADVERTISED_Pause | ADVERTISED_Asym_Pause);
10834 if (oldadv != newadv) {
10835 phydev->advertising &=
10836 ~(ADVERTISED_Pause |
10837 ADVERTISED_Asym_Pause);
10838 phydev->advertising |= newadv;
10839 if (phydev->autoneg) {
10841 * Always renegotiate the link to
10842 * inform our link partner of our
10843 * flow control settings, even if the
10844 * flow control is forced. Let
10845 * tg3_adjust_link() do the final
10846 * flow control setup.
10848 return phy_start_aneg(phydev);
10852 if (!epause->autoneg)
10853 tg3_setup_flow_control(tp, 0, 0);
10855 tp->link_config.advertising &=
10856 ~(ADVERTISED_Pause |
10857 ADVERTISED_Asym_Pause);
10858 tp->link_config.advertising |= newadv;
10863 if (netif_running(dev)) {
10864 tg3_netif_stop(tp);
10868 tg3_full_lock(tp, irq_sync);
10870 if (epause->autoneg)
10871 tg3_flag_set(tp, PAUSE_AUTONEG);
10873 tg3_flag_clear(tp, PAUSE_AUTONEG);
10874 if (epause->rx_pause)
10875 tp->link_config.flowctrl |= FLOW_CTRL_RX;
10877 tp->link_config.flowctrl &= ~FLOW_CTRL_RX;
10878 if (epause->tx_pause)
10879 tp->link_config.flowctrl |= FLOW_CTRL_TX;
10881 tp->link_config.flowctrl &= ~FLOW_CTRL_TX;
10883 if (netif_running(dev)) {
10884 tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
10885 err = tg3_restart_hw(tp, 1);
10887 tg3_netif_start(tp);
10890 tg3_full_unlock(tp);
10896 static int tg3_get_sset_count(struct net_device *dev, int sset)
10900 return TG3_NUM_TEST;
10902 return TG3_NUM_STATS;
10904 return -EOPNOTSUPP;
10908 static int tg3_get_rxnfc(struct net_device *dev, struct ethtool_rxnfc *info,
10909 u32 *rules __always_unused)
10911 struct tg3 *tp = netdev_priv(dev);
10913 if (!tg3_flag(tp, SUPPORT_MSIX))
10914 return -EOPNOTSUPP;
10916 switch (info->cmd) {
10917 case ETHTOOL_GRXRINGS:
10918 if (netif_running(tp->dev))
10919 info->data = tp->irq_cnt;
10921 info->data = num_online_cpus();
10922 if (info->data > TG3_IRQ_MAX_VECS_RSS)
10923 info->data = TG3_IRQ_MAX_VECS_RSS;
10926 /* The first interrupt vector only
10927 * handles link interrupts.
10933 return -EOPNOTSUPP;
10937 static u32 tg3_get_rxfh_indir_size(struct net_device *dev)
10940 struct tg3 *tp = netdev_priv(dev);
10942 if (tg3_flag(tp, SUPPORT_MSIX))
10943 size = TG3_RSS_INDIR_TBL_SIZE;
10948 static int tg3_get_rxfh_indir(struct net_device *dev, u32 *indir)
10950 struct tg3 *tp = netdev_priv(dev);
10953 for (i = 0; i < TG3_RSS_INDIR_TBL_SIZE; i++)
10954 indir[i] = tp->rss_ind_tbl[i];
10959 static int tg3_set_rxfh_indir(struct net_device *dev, const u32 *indir)
10961 struct tg3 *tp = netdev_priv(dev);
10964 for (i = 0; i < TG3_RSS_INDIR_TBL_SIZE; i++)
10965 tp->rss_ind_tbl[i] = indir[i];
10967 if (!netif_running(dev) || !tg3_flag(tp, ENABLE_RSS))
10970 /* It is legal to write the indirection
10971 * table while the device is running.
10973 tg3_full_lock(tp, 0);
10974 tg3_rss_write_indir_tbl(tp);
10975 tg3_full_unlock(tp);
10980 static void tg3_get_strings(struct net_device *dev, u32 stringset, u8 *buf)
10982 switch (stringset) {
10984 memcpy(buf, ðtool_stats_keys, sizeof(ethtool_stats_keys));
10987 memcpy(buf, ðtool_test_keys, sizeof(ethtool_test_keys));
10990 WARN_ON(1); /* we need a WARN() */
10995 static int tg3_set_phys_id(struct net_device *dev,
10996 enum ethtool_phys_id_state state)
10998 struct tg3 *tp = netdev_priv(dev);
11000 if (!netif_running(tp->dev))
11004 case ETHTOOL_ID_ACTIVE:
11005 return 1; /* cycle on/off once per second */
11007 case ETHTOOL_ID_ON:
11008 tw32(MAC_LED_CTRL, LED_CTRL_LNKLED_OVERRIDE |
11009 LED_CTRL_1000MBPS_ON |
11010 LED_CTRL_100MBPS_ON |
11011 LED_CTRL_10MBPS_ON |
11012 LED_CTRL_TRAFFIC_OVERRIDE |
11013 LED_CTRL_TRAFFIC_BLINK |
11014 LED_CTRL_TRAFFIC_LED);
11017 case ETHTOOL_ID_OFF:
11018 tw32(MAC_LED_CTRL, LED_CTRL_LNKLED_OVERRIDE |
11019 LED_CTRL_TRAFFIC_OVERRIDE);
11022 case ETHTOOL_ID_INACTIVE:
11023 tw32(MAC_LED_CTRL, tp->led_ctrl);
11030 static void tg3_get_ethtool_stats(struct net_device *dev,
11031 struct ethtool_stats *estats, u64 *tmp_stats)
11033 struct tg3 *tp = netdev_priv(dev);
11036 tg3_get_estats(tp, (struct tg3_ethtool_stats *)tmp_stats);
11038 memset(tmp_stats, 0, sizeof(struct tg3_ethtool_stats));
11041 static __be32 *tg3_vpd_readblock(struct tg3 *tp, u32 *vpdlen)
11045 u32 offset = 0, len = 0;
11048 if (tg3_flag(tp, NO_NVRAM) || tg3_nvram_read(tp, 0, &magic))
11051 if (magic == TG3_EEPROM_MAGIC) {
11052 for (offset = TG3_NVM_DIR_START;
11053 offset < TG3_NVM_DIR_END;
11054 offset += TG3_NVM_DIRENT_SIZE) {
11055 if (tg3_nvram_read(tp, offset, &val))
11058 if ((val >> TG3_NVM_DIRTYPE_SHIFT) ==
11059 TG3_NVM_DIRTYPE_EXTVPD)
11063 if (offset != TG3_NVM_DIR_END) {
11064 len = (val & TG3_NVM_DIRTYPE_LENMSK) * 4;
11065 if (tg3_nvram_read(tp, offset + 4, &offset))
11068 offset = tg3_nvram_logical_addr(tp, offset);
11072 if (!offset || !len) {
11073 offset = TG3_NVM_VPD_OFF;
11074 len = TG3_NVM_VPD_LEN;
11077 buf = kmalloc(len, GFP_KERNEL);
11081 if (magic == TG3_EEPROM_MAGIC) {
11082 for (i = 0; i < len; i += 4) {
11083 /* The data is in little-endian format in NVRAM.
11084 * Use the big-endian read routines to preserve
11085 * the byte order as it exists in NVRAM.
11087 if (tg3_nvram_read_be32(tp, offset + i, &buf[i/4]))
11093 unsigned int pos = 0;
11095 ptr = (u8 *)&buf[0];
11096 for (i = 0; pos < len && i < 3; i++, pos += cnt, ptr += cnt) {
11097 cnt = pci_read_vpd(tp->pdev, pos,
11099 if (cnt == -ETIMEDOUT || cnt == -EINTR)
11117 #define NVRAM_TEST_SIZE 0x100
11118 #define NVRAM_SELFBOOT_FORMAT1_0_SIZE 0x14
11119 #define NVRAM_SELFBOOT_FORMAT1_2_SIZE 0x18
11120 #define NVRAM_SELFBOOT_FORMAT1_3_SIZE 0x1c
11121 #define NVRAM_SELFBOOT_FORMAT1_4_SIZE 0x20
11122 #define NVRAM_SELFBOOT_FORMAT1_5_SIZE 0x24
11123 #define NVRAM_SELFBOOT_FORMAT1_6_SIZE 0x50
11124 #define NVRAM_SELFBOOT_HW_SIZE 0x20
11125 #define NVRAM_SELFBOOT_DATA_SIZE 0x1c
11127 static int tg3_test_nvram(struct tg3 *tp)
11129 u32 csum, magic, len;
11131 int i, j, k, err = 0, size;
11133 if (tg3_flag(tp, NO_NVRAM))
11136 if (tg3_nvram_read(tp, 0, &magic) != 0)
11139 if (magic == TG3_EEPROM_MAGIC)
11140 size = NVRAM_TEST_SIZE;
11141 else if ((magic & TG3_EEPROM_MAGIC_FW_MSK) == TG3_EEPROM_MAGIC_FW) {
11142 if ((magic & TG3_EEPROM_SB_FORMAT_MASK) ==
11143 TG3_EEPROM_SB_FORMAT_1) {
11144 switch (magic & TG3_EEPROM_SB_REVISION_MASK) {
11145 case TG3_EEPROM_SB_REVISION_0:
11146 size = NVRAM_SELFBOOT_FORMAT1_0_SIZE;
11148 case TG3_EEPROM_SB_REVISION_2:
11149 size = NVRAM_SELFBOOT_FORMAT1_2_SIZE;
11151 case TG3_EEPROM_SB_REVISION_3:
11152 size = NVRAM_SELFBOOT_FORMAT1_3_SIZE;
11154 case TG3_EEPROM_SB_REVISION_4:
11155 size = NVRAM_SELFBOOT_FORMAT1_4_SIZE;
11157 case TG3_EEPROM_SB_REVISION_5:
11158 size = NVRAM_SELFBOOT_FORMAT1_5_SIZE;
11160 case TG3_EEPROM_SB_REVISION_6:
11161 size = NVRAM_SELFBOOT_FORMAT1_6_SIZE;
11168 } else if ((magic & TG3_EEPROM_MAGIC_HW_MSK) == TG3_EEPROM_MAGIC_HW)
11169 size = NVRAM_SELFBOOT_HW_SIZE;
11173 buf = kmalloc(size, GFP_KERNEL);
11178 for (i = 0, j = 0; i < size; i += 4, j++) {
11179 err = tg3_nvram_read_be32(tp, i, &buf[j]);
11186 /* Selfboot format */
11187 magic = be32_to_cpu(buf[0]);
11188 if ((magic & TG3_EEPROM_MAGIC_FW_MSK) ==
11189 TG3_EEPROM_MAGIC_FW) {
11190 u8 *buf8 = (u8 *) buf, csum8 = 0;
11192 if ((magic & TG3_EEPROM_SB_REVISION_MASK) ==
11193 TG3_EEPROM_SB_REVISION_2) {
11194 /* For rev 2, the csum doesn't include the MBA. */
11195 for (i = 0; i < TG3_EEPROM_SB_F1R2_MBA_OFF; i++)
11197 for (i = TG3_EEPROM_SB_F1R2_MBA_OFF + 4; i < size; i++)
11200 for (i = 0; i < size; i++)
11213 if ((magic & TG3_EEPROM_MAGIC_HW_MSK) ==
11214 TG3_EEPROM_MAGIC_HW) {
11215 u8 data[NVRAM_SELFBOOT_DATA_SIZE];
11216 u8 parity[NVRAM_SELFBOOT_DATA_SIZE];
11217 u8 *buf8 = (u8 *) buf;
11219 /* Separate the parity bits and the data bytes. */
11220 for (i = 0, j = 0, k = 0; i < NVRAM_SELFBOOT_HW_SIZE; i++) {
11221 if ((i == 0) || (i == 8)) {
11225 for (l = 0, msk = 0x80; l < 7; l++, msk >>= 1)
11226 parity[k++] = buf8[i] & msk;
11228 } else if (i == 16) {
11232 for (l = 0, msk = 0x20; l < 6; l++, msk >>= 1)
11233 parity[k++] = buf8[i] & msk;
11236 for (l = 0, msk = 0x80; l < 8; l++, msk >>= 1)
11237 parity[k++] = buf8[i] & msk;
11240 data[j++] = buf8[i];
11244 for (i = 0; i < NVRAM_SELFBOOT_DATA_SIZE; i++) {
11245 u8 hw8 = hweight8(data[i]);
11247 if ((hw8 & 0x1) && parity[i])
11249 else if (!(hw8 & 0x1) && !parity[i])
11258 /* Bootstrap checksum at offset 0x10 */
11259 csum = calc_crc((unsigned char *) buf, 0x10);
11260 if (csum != le32_to_cpu(buf[0x10/4]))
11263 /* Manufacturing block starts at offset 0x74, checksum at 0xfc */
11264 csum = calc_crc((unsigned char *) &buf[0x74/4], 0x88);
11265 if (csum != le32_to_cpu(buf[0xfc/4]))
11270 buf = tg3_vpd_readblock(tp, &len);
11274 i = pci_vpd_find_tag((u8 *)buf, 0, len, PCI_VPD_LRDT_RO_DATA);
11276 j = pci_vpd_lrdt_size(&((u8 *)buf)[i]);
11280 if (i + PCI_VPD_LRDT_TAG_SIZE + j > len)
11283 i += PCI_VPD_LRDT_TAG_SIZE;
11284 j = pci_vpd_find_info_keyword((u8 *)buf, i, j,
11285 PCI_VPD_RO_KEYWORD_CHKSUM);
11289 j += PCI_VPD_INFO_FLD_HDR_SIZE;
11291 for (i = 0; i <= j; i++)
11292 csum8 += ((u8 *)buf)[i];
11306 #define TG3_SERDES_TIMEOUT_SEC 2
11307 #define TG3_COPPER_TIMEOUT_SEC 6
11309 static int tg3_test_link(struct tg3 *tp)
11313 if (!netif_running(tp->dev))
11316 if (tp->phy_flags & TG3_PHYFLG_ANY_SERDES)
11317 max = TG3_SERDES_TIMEOUT_SEC;
11319 max = TG3_COPPER_TIMEOUT_SEC;
11321 for (i = 0; i < max; i++) {
11322 if (netif_carrier_ok(tp->dev))
11325 if (msleep_interruptible(1000))
11332 /* Only test the commonly used registers */
11333 static int tg3_test_registers(struct tg3 *tp)
11335 int i, is_5705, is_5750;
11336 u32 offset, read_mask, write_mask, val, save_val, read_val;
11340 #define TG3_FL_5705 0x1
11341 #define TG3_FL_NOT_5705 0x2
11342 #define TG3_FL_NOT_5788 0x4
11343 #define TG3_FL_NOT_5750 0x8
11347 /* MAC Control Registers */
11348 { MAC_MODE, TG3_FL_NOT_5705,
11349 0x00000000, 0x00ef6f8c },
11350 { MAC_MODE, TG3_FL_5705,
11351 0x00000000, 0x01ef6b8c },
11352 { MAC_STATUS, TG3_FL_NOT_5705,
11353 0x03800107, 0x00000000 },
11354 { MAC_STATUS, TG3_FL_5705,
11355 0x03800100, 0x00000000 },
11356 { MAC_ADDR_0_HIGH, 0x0000,
11357 0x00000000, 0x0000ffff },
11358 { MAC_ADDR_0_LOW, 0x0000,
11359 0x00000000, 0xffffffff },
11360 { MAC_RX_MTU_SIZE, 0x0000,
11361 0x00000000, 0x0000ffff },
11362 { MAC_TX_MODE, 0x0000,
11363 0x00000000, 0x00000070 },
11364 { MAC_TX_LENGTHS, 0x0000,
11365 0x00000000, 0x00003fff },
11366 { MAC_RX_MODE, TG3_FL_NOT_5705,
11367 0x00000000, 0x000007fc },
11368 { MAC_RX_MODE, TG3_FL_5705,
11369 0x00000000, 0x000007dc },
11370 { MAC_HASH_REG_0, 0x0000,
11371 0x00000000, 0xffffffff },
11372 { MAC_HASH_REG_1, 0x0000,
11373 0x00000000, 0xffffffff },
11374 { MAC_HASH_REG_2, 0x0000,
11375 0x00000000, 0xffffffff },
11376 { MAC_HASH_REG_3, 0x0000,
11377 0x00000000, 0xffffffff },
11379 /* Receive Data and Receive BD Initiator Control Registers. */
11380 { RCVDBDI_JUMBO_BD+0, TG3_FL_NOT_5705,
11381 0x00000000, 0xffffffff },
11382 { RCVDBDI_JUMBO_BD+4, TG3_FL_NOT_5705,
11383 0x00000000, 0xffffffff },
11384 { RCVDBDI_JUMBO_BD+8, TG3_FL_NOT_5705,
11385 0x00000000, 0x00000003 },
11386 { RCVDBDI_JUMBO_BD+0xc, TG3_FL_NOT_5705,
11387 0x00000000, 0xffffffff },
11388 { RCVDBDI_STD_BD+0, 0x0000,
11389 0x00000000, 0xffffffff },
11390 { RCVDBDI_STD_BD+4, 0x0000,
11391 0x00000000, 0xffffffff },
11392 { RCVDBDI_STD_BD+8, 0x0000,
11393 0x00000000, 0xffff0002 },
11394 { RCVDBDI_STD_BD+0xc, 0x0000,
11395 0x00000000, 0xffffffff },
11397 /* Receive BD Initiator Control Registers. */
11398 { RCVBDI_STD_THRESH, TG3_FL_NOT_5705,
11399 0x00000000, 0xffffffff },
11400 { RCVBDI_STD_THRESH, TG3_FL_5705,
11401 0x00000000, 0x000003ff },
11402 { RCVBDI_JUMBO_THRESH, TG3_FL_NOT_5705,
11403 0x00000000, 0xffffffff },
11405 /* Host Coalescing Control Registers. */
11406 { HOSTCC_MODE, TG3_FL_NOT_5705,
11407 0x00000000, 0x00000004 },
11408 { HOSTCC_MODE, TG3_FL_5705,
11409 0x00000000, 0x000000f6 },
11410 { HOSTCC_RXCOL_TICKS, TG3_FL_NOT_5705,
11411 0x00000000, 0xffffffff },
11412 { HOSTCC_RXCOL_TICKS, TG3_FL_5705,
11413 0x00000000, 0x000003ff },
11414 { HOSTCC_TXCOL_TICKS, TG3_FL_NOT_5705,
11415 0x00000000, 0xffffffff },
11416 { HOSTCC_TXCOL_TICKS, TG3_FL_5705,
11417 0x00000000, 0x000003ff },
11418 { HOSTCC_RXMAX_FRAMES, TG3_FL_NOT_5705,
11419 0x00000000, 0xffffffff },
11420 { HOSTCC_RXMAX_FRAMES, TG3_FL_5705 | TG3_FL_NOT_5788,
11421 0x00000000, 0x000000ff },
11422 { HOSTCC_TXMAX_FRAMES, TG3_FL_NOT_5705,
11423 0x00000000, 0xffffffff },
11424 { HOSTCC_TXMAX_FRAMES, TG3_FL_5705 | TG3_FL_NOT_5788,
11425 0x00000000, 0x000000ff },
11426 { HOSTCC_RXCOAL_TICK_INT, TG3_FL_NOT_5705,
11427 0x00000000, 0xffffffff },
11428 { HOSTCC_TXCOAL_TICK_INT, TG3_FL_NOT_5705,
11429 0x00000000, 0xffffffff },
11430 { HOSTCC_RXCOAL_MAXF_INT, TG3_FL_NOT_5705,
11431 0x00000000, 0xffffffff },
11432 { HOSTCC_RXCOAL_MAXF_INT, TG3_FL_5705 | TG3_FL_NOT_5788,
11433 0x00000000, 0x000000ff },
11434 { HOSTCC_TXCOAL_MAXF_INT, TG3_FL_NOT_5705,
11435 0x00000000, 0xffffffff },
11436 { HOSTCC_TXCOAL_MAXF_INT, TG3_FL_5705 | TG3_FL_NOT_5788,
11437 0x00000000, 0x000000ff },
11438 { HOSTCC_STAT_COAL_TICKS, TG3_FL_NOT_5705,
11439 0x00000000, 0xffffffff },
11440 { HOSTCC_STATS_BLK_HOST_ADDR, TG3_FL_NOT_5705,
11441 0x00000000, 0xffffffff },
11442 { HOSTCC_STATS_BLK_HOST_ADDR+4, TG3_FL_NOT_5705,
11443 0x00000000, 0xffffffff },
11444 { HOSTCC_STATUS_BLK_HOST_ADDR, 0x0000,
11445 0x00000000, 0xffffffff },
11446 { HOSTCC_STATUS_BLK_HOST_ADDR+4, 0x0000,
11447 0x00000000, 0xffffffff },
11448 { HOSTCC_STATS_BLK_NIC_ADDR, 0x0000,
11449 0xffffffff, 0x00000000 },
11450 { HOSTCC_STATUS_BLK_NIC_ADDR, 0x0000,
11451 0xffffffff, 0x00000000 },
11453 /* Buffer Manager Control Registers. */
11454 { BUFMGR_MB_POOL_ADDR, TG3_FL_NOT_5750,
11455 0x00000000, 0x007fff80 },
11456 { BUFMGR_MB_POOL_SIZE, TG3_FL_NOT_5750,
11457 0x00000000, 0x007fffff },
11458 { BUFMGR_MB_RDMA_LOW_WATER, 0x0000,
11459 0x00000000, 0x0000003f },
11460 { BUFMGR_MB_MACRX_LOW_WATER, 0x0000,
11461 0x00000000, 0x000001ff },
11462 { BUFMGR_MB_HIGH_WATER, 0x0000,
11463 0x00000000, 0x000001ff },
11464 { BUFMGR_DMA_DESC_POOL_ADDR, TG3_FL_NOT_5705,
11465 0xffffffff, 0x00000000 },
11466 { BUFMGR_DMA_DESC_POOL_SIZE, TG3_FL_NOT_5705,
11467 0xffffffff, 0x00000000 },
11469 /* Mailbox Registers */
11470 { GRCMBOX_RCVSTD_PROD_IDX+4, 0x0000,
11471 0x00000000, 0x000001ff },
11472 { GRCMBOX_RCVJUMBO_PROD_IDX+4, TG3_FL_NOT_5705,
11473 0x00000000, 0x000001ff },
11474 { GRCMBOX_RCVRET_CON_IDX_0+4, 0x0000,
11475 0x00000000, 0x000007ff },
11476 { GRCMBOX_SNDHOST_PROD_IDX_0+4, 0x0000,
11477 0x00000000, 0x000001ff },
11479 { 0xffff, 0x0000, 0x00000000, 0x00000000 },
11482 is_5705 = is_5750 = 0;
11483 if (tg3_flag(tp, 5705_PLUS)) {
11485 if (tg3_flag(tp, 5750_PLUS))
11489 for (i = 0; reg_tbl[i].offset != 0xffff; i++) {
11490 if (is_5705 && (reg_tbl[i].flags & TG3_FL_NOT_5705))
11493 if (!is_5705 && (reg_tbl[i].flags & TG3_FL_5705))
11496 if (tg3_flag(tp, IS_5788) &&
11497 (reg_tbl[i].flags & TG3_FL_NOT_5788))
11500 if (is_5750 && (reg_tbl[i].flags & TG3_FL_NOT_5750))
11503 offset = (u32) reg_tbl[i].offset;
11504 read_mask = reg_tbl[i].read_mask;
11505 write_mask = reg_tbl[i].write_mask;
11507 /* Save the original register content */
11508 save_val = tr32(offset);
11510 /* Determine the read-only value. */
11511 read_val = save_val & read_mask;
11513 /* Write zero to the register, then make sure the read-only bits
11514 * are not changed and the read/write bits are all zeros.
11518 val = tr32(offset);
11520 /* Test the read-only and read/write bits. */
11521 if (((val & read_mask) != read_val) || (val & write_mask))
11524 /* Write ones to all the bits defined by RdMask and WrMask, then
11525 * make sure the read-only bits are not changed and the
11526 * read/write bits are all ones.
11528 tw32(offset, read_mask | write_mask);
11530 val = tr32(offset);
11532 /* Test the read-only bits. */
11533 if ((val & read_mask) != read_val)
11536 /* Test the read/write bits. */
11537 if ((val & write_mask) != write_mask)
11540 tw32(offset, save_val);
11546 if (netif_msg_hw(tp))
11547 netdev_err(tp->dev,
11548 "Register test failed at offset %x\n", offset);
11549 tw32(offset, save_val);
11553 static int tg3_do_mem_test(struct tg3 *tp, u32 offset, u32 len)
11555 static const u32 test_pattern[] = { 0x00000000, 0xffffffff, 0xaa55a55a };
11559 for (i = 0; i < ARRAY_SIZE(test_pattern); i++) {
11560 for (j = 0; j < len; j += 4) {
11563 tg3_write_mem(tp, offset + j, test_pattern[i]);
11564 tg3_read_mem(tp, offset + j, &val);
11565 if (val != test_pattern[i])
11572 static int tg3_test_memory(struct tg3 *tp)
11574 static struct mem_entry {
11577 } mem_tbl_570x[] = {
11578 { 0x00000000, 0x00b50},
11579 { 0x00002000, 0x1c000},
11580 { 0xffffffff, 0x00000}
11581 }, mem_tbl_5705[] = {
11582 { 0x00000100, 0x0000c},
11583 { 0x00000200, 0x00008},
11584 { 0x00004000, 0x00800},
11585 { 0x00006000, 0x01000},
11586 { 0x00008000, 0x02000},
11587 { 0x00010000, 0x0e000},
11588 { 0xffffffff, 0x00000}
11589 }, mem_tbl_5755[] = {
11590 { 0x00000200, 0x00008},
11591 { 0x00004000, 0x00800},
11592 { 0x00006000, 0x00800},
11593 { 0x00008000, 0x02000},
11594 { 0x00010000, 0x0c000},
11595 { 0xffffffff, 0x00000}
11596 }, mem_tbl_5906[] = {
11597 { 0x00000200, 0x00008},
11598 { 0x00004000, 0x00400},
11599 { 0x00006000, 0x00400},
11600 { 0x00008000, 0x01000},
11601 { 0x00010000, 0x01000},
11602 { 0xffffffff, 0x00000}
11603 }, mem_tbl_5717[] = {
11604 { 0x00000200, 0x00008},
11605 { 0x00010000, 0x0a000},
11606 { 0x00020000, 0x13c00},
11607 { 0xffffffff, 0x00000}
11608 }, mem_tbl_57765[] = {
11609 { 0x00000200, 0x00008},
11610 { 0x00004000, 0x00800},
11611 { 0x00006000, 0x09800},
11612 { 0x00010000, 0x0a000},
11613 { 0xffffffff, 0x00000}
11615 struct mem_entry *mem_tbl;
11619 if (tg3_flag(tp, 5717_PLUS))
11620 mem_tbl = mem_tbl_5717;
11621 else if (tg3_flag(tp, 57765_CLASS))
11622 mem_tbl = mem_tbl_57765;
11623 else if (tg3_flag(tp, 5755_PLUS))
11624 mem_tbl = mem_tbl_5755;
11625 else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906)
11626 mem_tbl = mem_tbl_5906;
11627 else if (tg3_flag(tp, 5705_PLUS))
11628 mem_tbl = mem_tbl_5705;
11630 mem_tbl = mem_tbl_570x;
11632 for (i = 0; mem_tbl[i].offset != 0xffffffff; i++) {
11633 err = tg3_do_mem_test(tp, mem_tbl[i].offset, mem_tbl[i].len);
11641 #define TG3_TSO_MSS 500
11643 #define TG3_TSO_IP_HDR_LEN 20
11644 #define TG3_TSO_TCP_HDR_LEN 20
11645 #define TG3_TSO_TCP_OPT_LEN 12
11647 static const u8 tg3_tso_header[] = {
11649 0x45, 0x00, 0x00, 0x00,
11650 0x00, 0x00, 0x40, 0x00,
11651 0x40, 0x06, 0x00, 0x00,
11652 0x0a, 0x00, 0x00, 0x01,
11653 0x0a, 0x00, 0x00, 0x02,
11654 0x0d, 0x00, 0xe0, 0x00,
11655 0x00, 0x00, 0x01, 0x00,
11656 0x00, 0x00, 0x02, 0x00,
11657 0x80, 0x10, 0x10, 0x00,
11658 0x14, 0x09, 0x00, 0x00,
11659 0x01, 0x01, 0x08, 0x0a,
11660 0x11, 0x11, 0x11, 0x11,
11661 0x11, 0x11, 0x11, 0x11,
11664 static int tg3_run_loopback(struct tg3 *tp, u32 pktsz, bool tso_loopback)
11666 u32 rx_start_idx, rx_idx, tx_idx, opaque_key;
11667 u32 base_flags = 0, mss = 0, desc_idx, coal_now, data_off, val;
11669 struct sk_buff *skb;
11670 u8 *tx_data, *rx_data;
11672 int num_pkts, tx_len, rx_len, i, err;
11673 struct tg3_rx_buffer_desc *desc;
11674 struct tg3_napi *tnapi, *rnapi;
11675 struct tg3_rx_prodring_set *tpr = &tp->napi[0].prodring;
11677 tnapi = &tp->napi[0];
11678 rnapi = &tp->napi[0];
11679 if (tp->irq_cnt > 1) {
11680 if (tg3_flag(tp, ENABLE_RSS))
11681 rnapi = &tp->napi[1];
11682 if (tg3_flag(tp, ENABLE_TSS))
11683 tnapi = &tp->napi[1];
11685 coal_now = tnapi->coal_now | rnapi->coal_now;
11690 skb = netdev_alloc_skb(tp->dev, tx_len);
11694 tx_data = skb_put(skb, tx_len);
11695 memcpy(tx_data, tp->dev->dev_addr, 6);
11696 memset(tx_data + 6, 0x0, 8);
11698 tw32(MAC_RX_MTU_SIZE, tx_len + ETH_FCS_LEN);
11700 if (tso_loopback) {
11701 struct iphdr *iph = (struct iphdr *)&tx_data[ETH_HLEN];
11703 u32 hdr_len = TG3_TSO_IP_HDR_LEN + TG3_TSO_TCP_HDR_LEN +
11704 TG3_TSO_TCP_OPT_LEN;
11706 memcpy(tx_data + ETH_ALEN * 2, tg3_tso_header,
11707 sizeof(tg3_tso_header));
11710 val = tx_len - ETH_ALEN * 2 - sizeof(tg3_tso_header);
11711 num_pkts = DIV_ROUND_UP(val, TG3_TSO_MSS);
11713 /* Set the total length field in the IP header */
11714 iph->tot_len = htons((u16)(mss + hdr_len));
11716 base_flags = (TXD_FLAG_CPU_PRE_DMA |
11717 TXD_FLAG_CPU_POST_DMA);
11719 if (tg3_flag(tp, HW_TSO_1) ||
11720 tg3_flag(tp, HW_TSO_2) ||
11721 tg3_flag(tp, HW_TSO_3)) {
11723 val = ETH_HLEN + TG3_TSO_IP_HDR_LEN;
11724 th = (struct tcphdr *)&tx_data[val];
11727 base_flags |= TXD_FLAG_TCPUDP_CSUM;
11729 if (tg3_flag(tp, HW_TSO_3)) {
11730 mss |= (hdr_len & 0xc) << 12;
11731 if (hdr_len & 0x10)
11732 base_flags |= 0x00000010;
11733 base_flags |= (hdr_len & 0x3e0) << 5;
11734 } else if (tg3_flag(tp, HW_TSO_2))
11735 mss |= hdr_len << 9;
11736 else if (tg3_flag(tp, HW_TSO_1) ||
11737 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705) {
11738 mss |= (TG3_TSO_TCP_OPT_LEN << 9);
11740 base_flags |= (TG3_TSO_TCP_OPT_LEN << 10);
11743 data_off = ETH_ALEN * 2 + sizeof(tg3_tso_header);
11746 data_off = ETH_HLEN;
11749 for (i = data_off; i < tx_len; i++)
11750 tx_data[i] = (u8) (i & 0xff);
11752 map = pci_map_single(tp->pdev, skb->data, tx_len, PCI_DMA_TODEVICE);
11753 if (pci_dma_mapping_error(tp->pdev, map)) {
11754 dev_kfree_skb(skb);
11758 val = tnapi->tx_prod;
11759 tnapi->tx_buffers[val].skb = skb;
11760 dma_unmap_addr_set(&tnapi->tx_buffers[val], mapping, map);
11762 tw32_f(HOSTCC_MODE, tp->coalesce_mode | HOSTCC_MODE_ENABLE |
11767 rx_start_idx = rnapi->hw_status->idx[0].rx_producer;
11769 budget = tg3_tx_avail(tnapi);
11770 if (tg3_tx_frag_set(tnapi, &val, &budget, map, tx_len,
11771 base_flags | TXD_FLAG_END, mss, 0)) {
11772 tnapi->tx_buffers[val].skb = NULL;
11773 dev_kfree_skb(skb);
11779 tw32_tx_mbox(tnapi->prodmbox, tnapi->tx_prod);
11780 tr32_mailbox(tnapi->prodmbox);
11784 /* 350 usec to allow enough time on some 10/100 Mbps devices. */
11785 for (i = 0; i < 35; i++) {
11786 tw32_f(HOSTCC_MODE, tp->coalesce_mode | HOSTCC_MODE_ENABLE |
11791 tx_idx = tnapi->hw_status->idx[0].tx_consumer;
11792 rx_idx = rnapi->hw_status->idx[0].rx_producer;
11793 if ((tx_idx == tnapi->tx_prod) &&
11794 (rx_idx == (rx_start_idx + num_pkts)))
11798 tg3_tx_skb_unmap(tnapi, tnapi->tx_prod - 1, -1);
11799 dev_kfree_skb(skb);
11801 if (tx_idx != tnapi->tx_prod)
11804 if (rx_idx != rx_start_idx + num_pkts)
11808 while (rx_idx != rx_start_idx) {
11809 desc = &rnapi->rx_rcb[rx_start_idx++];
11810 desc_idx = desc->opaque & RXD_OPAQUE_INDEX_MASK;
11811 opaque_key = desc->opaque & RXD_OPAQUE_RING_MASK;
11813 if ((desc->err_vlan & RXD_ERR_MASK) != 0 &&
11814 (desc->err_vlan != RXD_ERR_ODD_NIBBLE_RCVD_MII))
11817 rx_len = ((desc->idx_len & RXD_LEN_MASK) >> RXD_LEN_SHIFT)
11820 if (!tso_loopback) {
11821 if (rx_len != tx_len)
11824 if (pktsz <= TG3_RX_STD_DMA_SZ - ETH_FCS_LEN) {
11825 if (opaque_key != RXD_OPAQUE_RING_STD)
11828 if (opaque_key != RXD_OPAQUE_RING_JUMBO)
11831 } else if ((desc->type_flags & RXD_FLAG_TCPUDP_CSUM) &&
11832 (desc->ip_tcp_csum & RXD_TCPCSUM_MASK)
11833 >> RXD_TCPCSUM_SHIFT != 0xffff) {
11837 if (opaque_key == RXD_OPAQUE_RING_STD) {
11838 rx_data = tpr->rx_std_buffers[desc_idx].data;
11839 map = dma_unmap_addr(&tpr->rx_std_buffers[desc_idx],
11841 } else if (opaque_key == RXD_OPAQUE_RING_JUMBO) {
11842 rx_data = tpr->rx_jmb_buffers[desc_idx].data;
11843 map = dma_unmap_addr(&tpr->rx_jmb_buffers[desc_idx],
11848 pci_dma_sync_single_for_cpu(tp->pdev, map, rx_len,
11849 PCI_DMA_FROMDEVICE);
11851 rx_data += TG3_RX_OFFSET(tp);
11852 for (i = data_off; i < rx_len; i++, val++) {
11853 if (*(rx_data + i) != (u8) (val & 0xff))
11860 /* tg3_free_rings will unmap and free the rx_data */
11865 #define TG3_STD_LOOPBACK_FAILED 1
11866 #define TG3_JMB_LOOPBACK_FAILED 2
11867 #define TG3_TSO_LOOPBACK_FAILED 4
11868 #define TG3_LOOPBACK_FAILED \
11869 (TG3_STD_LOOPBACK_FAILED | \
11870 TG3_JMB_LOOPBACK_FAILED | \
11871 TG3_TSO_LOOPBACK_FAILED)
11873 static int tg3_test_loopback(struct tg3 *tp, u64 *data, bool do_extlpbk)
11878 eee_cap = tp->phy_flags & TG3_PHYFLG_EEE_CAP;
11879 tp->phy_flags &= ~TG3_PHYFLG_EEE_CAP;
11881 if (!netif_running(tp->dev)) {
11882 data[0] = TG3_LOOPBACK_FAILED;
11883 data[1] = TG3_LOOPBACK_FAILED;
11885 data[2] = TG3_LOOPBACK_FAILED;
11889 err = tg3_reset_hw(tp, 1);
11891 data[0] = TG3_LOOPBACK_FAILED;
11892 data[1] = TG3_LOOPBACK_FAILED;
11894 data[2] = TG3_LOOPBACK_FAILED;
11898 if (tg3_flag(tp, ENABLE_RSS)) {
11901 /* Reroute all rx packets to the 1st queue */
11902 for (i = MAC_RSS_INDIR_TBL_0;
11903 i < MAC_RSS_INDIR_TBL_0 + TG3_RSS_INDIR_TBL_SIZE; i += 4)
11907 /* HW errata - mac loopback fails in some cases on 5780.
11908 * Normal traffic and PHY loopback are not affected by
11909 * errata. Also, the MAC loopback test is deprecated for
11910 * all newer ASIC revisions.
11912 if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5780 &&
11913 !tg3_flag(tp, CPMU_PRESENT)) {
11914 tg3_mac_loopback(tp, true);
11916 if (tg3_run_loopback(tp, ETH_FRAME_LEN, false))
11917 data[0] |= TG3_STD_LOOPBACK_FAILED;
11919 if (tg3_flag(tp, JUMBO_RING_ENABLE) &&
11920 tg3_run_loopback(tp, 9000 + ETH_HLEN, false))
11921 data[0] |= TG3_JMB_LOOPBACK_FAILED;
11923 tg3_mac_loopback(tp, false);
11926 if (!(tp->phy_flags & TG3_PHYFLG_PHY_SERDES) &&
11927 !tg3_flag(tp, USE_PHYLIB)) {
11930 tg3_phy_lpbk_set(tp, 0, false);
11932 /* Wait for link */
11933 for (i = 0; i < 100; i++) {
11934 if (tr32(MAC_TX_STATUS) & TX_STATUS_LINK_UP)
11939 if (tg3_run_loopback(tp, ETH_FRAME_LEN, false))
11940 data[1] |= TG3_STD_LOOPBACK_FAILED;
11941 if (tg3_flag(tp, TSO_CAPABLE) &&
11942 tg3_run_loopback(tp, ETH_FRAME_LEN, true))
11943 data[1] |= TG3_TSO_LOOPBACK_FAILED;
11944 if (tg3_flag(tp, JUMBO_RING_ENABLE) &&
11945 tg3_run_loopback(tp, 9000 + ETH_HLEN, false))
11946 data[1] |= TG3_JMB_LOOPBACK_FAILED;
11949 tg3_phy_lpbk_set(tp, 0, true);
11951 /* All link indications report up, but the hardware
11952 * isn't really ready for about 20 msec. Double it
11957 if (tg3_run_loopback(tp, ETH_FRAME_LEN, false))
11958 data[2] |= TG3_STD_LOOPBACK_FAILED;
11959 if (tg3_flag(tp, TSO_CAPABLE) &&
11960 tg3_run_loopback(tp, ETH_FRAME_LEN, true))
11961 data[2] |= TG3_TSO_LOOPBACK_FAILED;
11962 if (tg3_flag(tp, JUMBO_RING_ENABLE) &&
11963 tg3_run_loopback(tp, 9000 + ETH_HLEN, false))
11964 data[2] |= TG3_JMB_LOOPBACK_FAILED;
11967 /* Re-enable gphy autopowerdown. */
11968 if (tp->phy_flags & TG3_PHYFLG_ENABLE_APD)
11969 tg3_phy_toggle_apd(tp, true);
11972 err = (data[0] | data[1] | data[2]) ? -EIO : 0;
11975 tp->phy_flags |= eee_cap;
11980 static void tg3_self_test(struct net_device *dev, struct ethtool_test *etest,
11983 struct tg3 *tp = netdev_priv(dev);
11984 bool doextlpbk = etest->flags & ETH_TEST_FL_EXTERNAL_LB;
11986 if ((tp->phy_flags & TG3_PHYFLG_IS_LOW_POWER) &&
11987 tg3_power_up(tp)) {
11988 etest->flags |= ETH_TEST_FL_FAILED;
11989 memset(data, 1, sizeof(u64) * TG3_NUM_TEST);
11993 memset(data, 0, sizeof(u64) * TG3_NUM_TEST);
11995 if (tg3_test_nvram(tp) != 0) {
11996 etest->flags |= ETH_TEST_FL_FAILED;
11999 if (!doextlpbk && tg3_test_link(tp)) {
12000 etest->flags |= ETH_TEST_FL_FAILED;
12003 if (etest->flags & ETH_TEST_FL_OFFLINE) {
12004 int err, err2 = 0, irq_sync = 0;
12006 if (netif_running(dev)) {
12008 tg3_netif_stop(tp);
12012 tg3_full_lock(tp, irq_sync);
12014 tg3_halt(tp, RESET_KIND_SUSPEND, 1);
12015 err = tg3_nvram_lock(tp);
12016 tg3_halt_cpu(tp, RX_CPU_BASE);
12017 if (!tg3_flag(tp, 5705_PLUS))
12018 tg3_halt_cpu(tp, TX_CPU_BASE);
12020 tg3_nvram_unlock(tp);
12022 if (tp->phy_flags & TG3_PHYFLG_MII_SERDES)
12025 if (tg3_test_registers(tp) != 0) {
12026 etest->flags |= ETH_TEST_FL_FAILED;
12030 if (tg3_test_memory(tp) != 0) {
12031 etest->flags |= ETH_TEST_FL_FAILED;
12036 etest->flags |= ETH_TEST_FL_EXTERNAL_LB_DONE;
12038 if (tg3_test_loopback(tp, &data[4], doextlpbk))
12039 etest->flags |= ETH_TEST_FL_FAILED;
12041 tg3_full_unlock(tp);
12043 if (tg3_test_interrupt(tp) != 0) {
12044 etest->flags |= ETH_TEST_FL_FAILED;
12048 tg3_full_lock(tp, 0);
12050 tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
12051 if (netif_running(dev)) {
12052 tg3_flag_set(tp, INIT_COMPLETE);
12053 err2 = tg3_restart_hw(tp, 1);
12055 tg3_netif_start(tp);
12058 tg3_full_unlock(tp);
12060 if (irq_sync && !err2)
12063 if (tp->phy_flags & TG3_PHYFLG_IS_LOW_POWER)
12064 tg3_power_down(tp);
12068 static int tg3_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd)
12070 struct mii_ioctl_data *data = if_mii(ifr);
12071 struct tg3 *tp = netdev_priv(dev);
12074 if (tg3_flag(tp, USE_PHYLIB)) {
12075 struct phy_device *phydev;
12076 if (!(tp->phy_flags & TG3_PHYFLG_IS_CONNECTED))
12078 phydev = tp->mdio_bus->phy_map[TG3_PHY_MII_ADDR];
12079 return phy_mii_ioctl(phydev, ifr, cmd);
12084 data->phy_id = tp->phy_addr;
12087 case SIOCGMIIREG: {
12090 if (tp->phy_flags & TG3_PHYFLG_PHY_SERDES)
12091 break; /* We have no PHY */
12093 if (!netif_running(dev))
12096 spin_lock_bh(&tp->lock);
12097 err = tg3_readphy(tp, data->reg_num & 0x1f, &mii_regval);
12098 spin_unlock_bh(&tp->lock);
12100 data->val_out = mii_regval;
12106 if (tp->phy_flags & TG3_PHYFLG_PHY_SERDES)
12107 break; /* We have no PHY */
12109 if (!netif_running(dev))
12112 spin_lock_bh(&tp->lock);
12113 err = tg3_writephy(tp, data->reg_num & 0x1f, data->val_in);
12114 spin_unlock_bh(&tp->lock);
12122 return -EOPNOTSUPP;
12125 static int tg3_get_coalesce(struct net_device *dev, struct ethtool_coalesce *ec)
12127 struct tg3 *tp = netdev_priv(dev);
12129 memcpy(ec, &tp->coal, sizeof(*ec));
12133 static int tg3_set_coalesce(struct net_device *dev, struct ethtool_coalesce *ec)
12135 struct tg3 *tp = netdev_priv(dev);
12136 u32 max_rxcoal_tick_int = 0, max_txcoal_tick_int = 0;
12137 u32 max_stat_coal_ticks = 0, min_stat_coal_ticks = 0;
12139 if (!tg3_flag(tp, 5705_PLUS)) {
12140 max_rxcoal_tick_int = MAX_RXCOAL_TICK_INT;
12141 max_txcoal_tick_int = MAX_TXCOAL_TICK_INT;
12142 max_stat_coal_ticks = MAX_STAT_COAL_TICKS;
12143 min_stat_coal_ticks = MIN_STAT_COAL_TICKS;
12146 if ((ec->rx_coalesce_usecs > MAX_RXCOL_TICKS) ||
12147 (ec->tx_coalesce_usecs > MAX_TXCOL_TICKS) ||
12148 (ec->rx_max_coalesced_frames > MAX_RXMAX_FRAMES) ||
12149 (ec->tx_max_coalesced_frames > MAX_TXMAX_FRAMES) ||
12150 (ec->rx_coalesce_usecs_irq > max_rxcoal_tick_int) ||
12151 (ec->tx_coalesce_usecs_irq > max_txcoal_tick_int) ||
12152 (ec->rx_max_coalesced_frames_irq > MAX_RXCOAL_MAXF_INT) ||
12153 (ec->tx_max_coalesced_frames_irq > MAX_TXCOAL_MAXF_INT) ||
12154 (ec->stats_block_coalesce_usecs > max_stat_coal_ticks) ||
12155 (ec->stats_block_coalesce_usecs < min_stat_coal_ticks))
12158 /* No rx interrupts will be generated if both are zero */
12159 if ((ec->rx_coalesce_usecs == 0) &&
12160 (ec->rx_max_coalesced_frames == 0))
12163 /* No tx interrupts will be generated if both are zero */
12164 if ((ec->tx_coalesce_usecs == 0) &&
12165 (ec->tx_max_coalesced_frames == 0))
12168 /* Only copy relevant parameters, ignore all others. */
12169 tp->coal.rx_coalesce_usecs = ec->rx_coalesce_usecs;
12170 tp->coal.tx_coalesce_usecs = ec->tx_coalesce_usecs;
12171 tp->coal.rx_max_coalesced_frames = ec->rx_max_coalesced_frames;
12172 tp->coal.tx_max_coalesced_frames = ec->tx_max_coalesced_frames;
12173 tp->coal.rx_coalesce_usecs_irq = ec->rx_coalesce_usecs_irq;
12174 tp->coal.tx_coalesce_usecs_irq = ec->tx_coalesce_usecs_irq;
12175 tp->coal.rx_max_coalesced_frames_irq = ec->rx_max_coalesced_frames_irq;
12176 tp->coal.tx_max_coalesced_frames_irq = ec->tx_max_coalesced_frames_irq;
12177 tp->coal.stats_block_coalesce_usecs = ec->stats_block_coalesce_usecs;
12179 if (netif_running(dev)) {
12180 tg3_full_lock(tp, 0);
12181 __tg3_set_coalesce(tp, &tp->coal);
12182 tg3_full_unlock(tp);
12187 static const struct ethtool_ops tg3_ethtool_ops = {
12188 .get_settings = tg3_get_settings,
12189 .set_settings = tg3_set_settings,
12190 .get_drvinfo = tg3_get_drvinfo,
12191 .get_regs_len = tg3_get_regs_len,
12192 .get_regs = tg3_get_regs,
12193 .get_wol = tg3_get_wol,
12194 .set_wol = tg3_set_wol,
12195 .get_msglevel = tg3_get_msglevel,
12196 .set_msglevel = tg3_set_msglevel,
12197 .nway_reset = tg3_nway_reset,
12198 .get_link = ethtool_op_get_link,
12199 .get_eeprom_len = tg3_get_eeprom_len,
12200 .get_eeprom = tg3_get_eeprom,
12201 .set_eeprom = tg3_set_eeprom,
12202 .get_ringparam = tg3_get_ringparam,
12203 .set_ringparam = tg3_set_ringparam,
12204 .get_pauseparam = tg3_get_pauseparam,
12205 .set_pauseparam = tg3_set_pauseparam,
12206 .self_test = tg3_self_test,
12207 .get_strings = tg3_get_strings,
12208 .set_phys_id = tg3_set_phys_id,
12209 .get_ethtool_stats = tg3_get_ethtool_stats,
12210 .get_coalesce = tg3_get_coalesce,
12211 .set_coalesce = tg3_set_coalesce,
12212 .get_sset_count = tg3_get_sset_count,
12213 .get_rxnfc = tg3_get_rxnfc,
12214 .get_rxfh_indir_size = tg3_get_rxfh_indir_size,
12215 .get_rxfh_indir = tg3_get_rxfh_indir,
12216 .set_rxfh_indir = tg3_set_rxfh_indir,
12219 static void tg3_set_rx_mode(struct net_device *dev)
12221 struct tg3 *tp = netdev_priv(dev);
12223 if (!netif_running(dev))
12226 tg3_full_lock(tp, 0);
12227 __tg3_set_rx_mode(dev);
12228 tg3_full_unlock(tp);
12231 static inline void tg3_set_mtu(struct net_device *dev, struct tg3 *tp,
12234 dev->mtu = new_mtu;
12236 if (new_mtu > ETH_DATA_LEN) {
12237 if (tg3_flag(tp, 5780_CLASS)) {
12238 netdev_update_features(dev);
12239 tg3_flag_clear(tp, TSO_CAPABLE);
12241 tg3_flag_set(tp, JUMBO_RING_ENABLE);
12244 if (tg3_flag(tp, 5780_CLASS)) {
12245 tg3_flag_set(tp, TSO_CAPABLE);
12246 netdev_update_features(dev);
12248 tg3_flag_clear(tp, JUMBO_RING_ENABLE);
12252 static int tg3_change_mtu(struct net_device *dev, int new_mtu)
12254 struct tg3 *tp = netdev_priv(dev);
12257 if (new_mtu < TG3_MIN_MTU || new_mtu > TG3_MAX_MTU(tp))
12260 if (!netif_running(dev)) {
12261 /* We'll just catch it later when the
12264 tg3_set_mtu(dev, tp, new_mtu);
12270 tg3_netif_stop(tp);
12272 tg3_full_lock(tp, 1);
12274 tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
12276 tg3_set_mtu(dev, tp, new_mtu);
12278 err = tg3_restart_hw(tp, 0);
12281 tg3_netif_start(tp);
12283 tg3_full_unlock(tp);
12291 static const struct net_device_ops tg3_netdev_ops = {
12292 .ndo_open = tg3_open,
12293 .ndo_stop = tg3_close,
12294 .ndo_start_xmit = tg3_start_xmit,
12295 .ndo_get_stats64 = tg3_get_stats64,
12296 .ndo_validate_addr = eth_validate_addr,
12297 .ndo_set_rx_mode = tg3_set_rx_mode,
12298 .ndo_set_mac_address = tg3_set_mac_addr,
12299 .ndo_do_ioctl = tg3_ioctl,
12300 .ndo_tx_timeout = tg3_tx_timeout,
12301 .ndo_change_mtu = tg3_change_mtu,
12302 .ndo_fix_features = tg3_fix_features,
12303 .ndo_set_features = tg3_set_features,
12304 #ifdef CONFIG_NET_POLL_CONTROLLER
12305 .ndo_poll_controller = tg3_poll_controller,
12309 static void __devinit tg3_get_eeprom_size(struct tg3 *tp)
12311 u32 cursize, val, magic;
12313 tp->nvram_size = EEPROM_CHIP_SIZE;
12315 if (tg3_nvram_read(tp, 0, &magic) != 0)
12318 if ((magic != TG3_EEPROM_MAGIC) &&
12319 ((magic & TG3_EEPROM_MAGIC_FW_MSK) != TG3_EEPROM_MAGIC_FW) &&
12320 ((magic & TG3_EEPROM_MAGIC_HW_MSK) != TG3_EEPROM_MAGIC_HW))
12324 * Size the chip by reading offsets at increasing powers of two.
12325 * When we encounter our validation signature, we know the addressing
12326 * has wrapped around, and thus have our chip size.
12330 while (cursize < tp->nvram_size) {
12331 if (tg3_nvram_read(tp, cursize, &val) != 0)
12340 tp->nvram_size = cursize;
12343 static void __devinit tg3_get_nvram_size(struct tg3 *tp)
12347 if (tg3_flag(tp, NO_NVRAM) || tg3_nvram_read(tp, 0, &val) != 0)
12350 /* Selfboot format */
12351 if (val != TG3_EEPROM_MAGIC) {
12352 tg3_get_eeprom_size(tp);
12356 if (tg3_nvram_read(tp, 0xf0, &val) == 0) {
12358 /* This is confusing. We want to operate on the
12359 * 16-bit value at offset 0xf2. The tg3_nvram_read()
12360 * call will read from NVRAM and byteswap the data
12361 * according to the byteswapping settings for all
12362 * other register accesses. This ensures the data we
12363 * want will always reside in the lower 16-bits.
12364 * However, the data in NVRAM is in LE format, which
12365 * means the data from the NVRAM read will always be
12366 * opposite the endianness of the CPU. The 16-bit
12367 * byteswap then brings the data to CPU endianness.
12369 tp->nvram_size = swab16((u16)(val & 0x0000ffff)) * 1024;
12373 tp->nvram_size = TG3_NVRAM_SIZE_512KB;
12376 static void __devinit tg3_get_nvram_info(struct tg3 *tp)
12380 nvcfg1 = tr32(NVRAM_CFG1);
12381 if (nvcfg1 & NVRAM_CFG1_FLASHIF_ENAB) {
12382 tg3_flag_set(tp, FLASH);
12384 nvcfg1 &= ~NVRAM_CFG1_COMPAT_BYPASS;
12385 tw32(NVRAM_CFG1, nvcfg1);
12388 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5750 ||
12389 tg3_flag(tp, 5780_CLASS)) {
12390 switch (nvcfg1 & NVRAM_CFG1_VENDOR_MASK) {
12391 case FLASH_VENDOR_ATMEL_FLASH_BUFFERED:
12392 tp->nvram_jedecnum = JEDEC_ATMEL;
12393 tp->nvram_pagesize = ATMEL_AT45DB0X1B_PAGE_SIZE;
12394 tg3_flag_set(tp, NVRAM_BUFFERED);
12396 case FLASH_VENDOR_ATMEL_FLASH_UNBUFFERED:
12397 tp->nvram_jedecnum = JEDEC_ATMEL;
12398 tp->nvram_pagesize = ATMEL_AT25F512_PAGE_SIZE;
12400 case FLASH_VENDOR_ATMEL_EEPROM:
12401 tp->nvram_jedecnum = JEDEC_ATMEL;
12402 tp->nvram_pagesize = ATMEL_AT24C512_CHIP_SIZE;
12403 tg3_flag_set(tp, NVRAM_BUFFERED);
12405 case FLASH_VENDOR_ST:
12406 tp->nvram_jedecnum = JEDEC_ST;
12407 tp->nvram_pagesize = ST_M45PEX0_PAGE_SIZE;
12408 tg3_flag_set(tp, NVRAM_BUFFERED);
12410 case FLASH_VENDOR_SAIFUN:
12411 tp->nvram_jedecnum = JEDEC_SAIFUN;
12412 tp->nvram_pagesize = SAIFUN_SA25F0XX_PAGE_SIZE;
12414 case FLASH_VENDOR_SST_SMALL:
12415 case FLASH_VENDOR_SST_LARGE:
12416 tp->nvram_jedecnum = JEDEC_SST;
12417 tp->nvram_pagesize = SST_25VF0X0_PAGE_SIZE;
12421 tp->nvram_jedecnum = JEDEC_ATMEL;
12422 tp->nvram_pagesize = ATMEL_AT45DB0X1B_PAGE_SIZE;
12423 tg3_flag_set(tp, NVRAM_BUFFERED);
12427 static void __devinit tg3_nvram_get_pagesize(struct tg3 *tp, u32 nvmcfg1)
12429 switch (nvmcfg1 & NVRAM_CFG1_5752PAGE_SIZE_MASK) {
12430 case FLASH_5752PAGE_SIZE_256:
12431 tp->nvram_pagesize = 256;
12433 case FLASH_5752PAGE_SIZE_512:
12434 tp->nvram_pagesize = 512;
12436 case FLASH_5752PAGE_SIZE_1K:
12437 tp->nvram_pagesize = 1024;
12439 case FLASH_5752PAGE_SIZE_2K:
12440 tp->nvram_pagesize = 2048;
12442 case FLASH_5752PAGE_SIZE_4K:
12443 tp->nvram_pagesize = 4096;
12445 case FLASH_5752PAGE_SIZE_264:
12446 tp->nvram_pagesize = 264;
12448 case FLASH_5752PAGE_SIZE_528:
12449 tp->nvram_pagesize = 528;
12454 static void __devinit tg3_get_5752_nvram_info(struct tg3 *tp)
12458 nvcfg1 = tr32(NVRAM_CFG1);
12460 /* NVRAM protection for TPM */
12461 if (nvcfg1 & (1 << 27))
12462 tg3_flag_set(tp, PROTECTED_NVRAM);
12464 switch (nvcfg1 & NVRAM_CFG1_5752VENDOR_MASK) {
12465 case FLASH_5752VENDOR_ATMEL_EEPROM_64KHZ:
12466 case FLASH_5752VENDOR_ATMEL_EEPROM_376KHZ:
12467 tp->nvram_jedecnum = JEDEC_ATMEL;
12468 tg3_flag_set(tp, NVRAM_BUFFERED);
12470 case FLASH_5752VENDOR_ATMEL_FLASH_BUFFERED:
12471 tp->nvram_jedecnum = JEDEC_ATMEL;
12472 tg3_flag_set(tp, NVRAM_BUFFERED);
12473 tg3_flag_set(tp, FLASH);
12475 case FLASH_5752VENDOR_ST_M45PE10:
12476 case FLASH_5752VENDOR_ST_M45PE20:
12477 case FLASH_5752VENDOR_ST_M45PE40:
12478 tp->nvram_jedecnum = JEDEC_ST;
12479 tg3_flag_set(tp, NVRAM_BUFFERED);
12480 tg3_flag_set(tp, FLASH);
12484 if (tg3_flag(tp, FLASH)) {
12485 tg3_nvram_get_pagesize(tp, nvcfg1);
12487 /* For eeprom, set pagesize to maximum eeprom size */
12488 tp->nvram_pagesize = ATMEL_AT24C512_CHIP_SIZE;
12490 nvcfg1 &= ~NVRAM_CFG1_COMPAT_BYPASS;
12491 tw32(NVRAM_CFG1, nvcfg1);
12495 static void __devinit tg3_get_5755_nvram_info(struct tg3 *tp)
12497 u32 nvcfg1, protect = 0;
12499 nvcfg1 = tr32(NVRAM_CFG1);
12501 /* NVRAM protection for TPM */
12502 if (nvcfg1 & (1 << 27)) {
12503 tg3_flag_set(tp, PROTECTED_NVRAM);
12507 nvcfg1 &= NVRAM_CFG1_5752VENDOR_MASK;
12509 case FLASH_5755VENDOR_ATMEL_FLASH_1:
12510 case FLASH_5755VENDOR_ATMEL_FLASH_2:
12511 case FLASH_5755VENDOR_ATMEL_FLASH_3:
12512 case FLASH_5755VENDOR_ATMEL_FLASH_5:
12513 tp->nvram_jedecnum = JEDEC_ATMEL;
12514 tg3_flag_set(tp, NVRAM_BUFFERED);
12515 tg3_flag_set(tp, FLASH);
12516 tp->nvram_pagesize = 264;
12517 if (nvcfg1 == FLASH_5755VENDOR_ATMEL_FLASH_1 ||
12518 nvcfg1 == FLASH_5755VENDOR_ATMEL_FLASH_5)
12519 tp->nvram_size = (protect ? 0x3e200 :
12520 TG3_NVRAM_SIZE_512KB);
12521 else if (nvcfg1 == FLASH_5755VENDOR_ATMEL_FLASH_2)
12522 tp->nvram_size = (protect ? 0x1f200 :
12523 TG3_NVRAM_SIZE_256KB);
12525 tp->nvram_size = (protect ? 0x1f200 :
12526 TG3_NVRAM_SIZE_128KB);
12528 case FLASH_5752VENDOR_ST_M45PE10:
12529 case FLASH_5752VENDOR_ST_M45PE20:
12530 case FLASH_5752VENDOR_ST_M45PE40:
12531 tp->nvram_jedecnum = JEDEC_ST;
12532 tg3_flag_set(tp, NVRAM_BUFFERED);
12533 tg3_flag_set(tp, FLASH);
12534 tp->nvram_pagesize = 256;
12535 if (nvcfg1 == FLASH_5752VENDOR_ST_M45PE10)
12536 tp->nvram_size = (protect ?
12537 TG3_NVRAM_SIZE_64KB :
12538 TG3_NVRAM_SIZE_128KB);
12539 else if (nvcfg1 == FLASH_5752VENDOR_ST_M45PE20)
12540 tp->nvram_size = (protect ?
12541 TG3_NVRAM_SIZE_64KB :
12542 TG3_NVRAM_SIZE_256KB);
12544 tp->nvram_size = (protect ?
12545 TG3_NVRAM_SIZE_128KB :
12546 TG3_NVRAM_SIZE_512KB);
12551 static void __devinit tg3_get_5787_nvram_info(struct tg3 *tp)
12555 nvcfg1 = tr32(NVRAM_CFG1);
12557 switch (nvcfg1 & NVRAM_CFG1_5752VENDOR_MASK) {
12558 case FLASH_5787VENDOR_ATMEL_EEPROM_64KHZ:
12559 case FLASH_5787VENDOR_ATMEL_EEPROM_376KHZ:
12560 case FLASH_5787VENDOR_MICRO_EEPROM_64KHZ:
12561 case FLASH_5787VENDOR_MICRO_EEPROM_376KHZ:
12562 tp->nvram_jedecnum = JEDEC_ATMEL;
12563 tg3_flag_set(tp, NVRAM_BUFFERED);
12564 tp->nvram_pagesize = ATMEL_AT24C512_CHIP_SIZE;
12566 nvcfg1 &= ~NVRAM_CFG1_COMPAT_BYPASS;
12567 tw32(NVRAM_CFG1, nvcfg1);
12569 case FLASH_5752VENDOR_ATMEL_FLASH_BUFFERED:
12570 case FLASH_5755VENDOR_ATMEL_FLASH_1:
12571 case FLASH_5755VENDOR_ATMEL_FLASH_2:
12572 case FLASH_5755VENDOR_ATMEL_FLASH_3:
12573 tp->nvram_jedecnum = JEDEC_ATMEL;
12574 tg3_flag_set(tp, NVRAM_BUFFERED);
12575 tg3_flag_set(tp, FLASH);
12576 tp->nvram_pagesize = 264;
12578 case FLASH_5752VENDOR_ST_M45PE10:
12579 case FLASH_5752VENDOR_ST_M45PE20:
12580 case FLASH_5752VENDOR_ST_M45PE40:
12581 tp->nvram_jedecnum = JEDEC_ST;
12582 tg3_flag_set(tp, NVRAM_BUFFERED);
12583 tg3_flag_set(tp, FLASH);
12584 tp->nvram_pagesize = 256;
12589 static void __devinit tg3_get_5761_nvram_info(struct tg3 *tp)
12591 u32 nvcfg1, protect = 0;
12593 nvcfg1 = tr32(NVRAM_CFG1);
12595 /* NVRAM protection for TPM */
12596 if (nvcfg1 & (1 << 27)) {
12597 tg3_flag_set(tp, PROTECTED_NVRAM);
12601 nvcfg1 &= NVRAM_CFG1_5752VENDOR_MASK;
12603 case FLASH_5761VENDOR_ATMEL_ADB021D:
12604 case FLASH_5761VENDOR_ATMEL_ADB041D:
12605 case FLASH_5761VENDOR_ATMEL_ADB081D:
12606 case FLASH_5761VENDOR_ATMEL_ADB161D:
12607 case FLASH_5761VENDOR_ATMEL_MDB021D:
12608 case FLASH_5761VENDOR_ATMEL_MDB041D:
12609 case FLASH_5761VENDOR_ATMEL_MDB081D:
12610 case FLASH_5761VENDOR_ATMEL_MDB161D:
12611 tp->nvram_jedecnum = JEDEC_ATMEL;
12612 tg3_flag_set(tp, NVRAM_BUFFERED);
12613 tg3_flag_set(tp, FLASH);
12614 tg3_flag_set(tp, NO_NVRAM_ADDR_TRANS);
12615 tp->nvram_pagesize = 256;
12617 case FLASH_5761VENDOR_ST_A_M45PE20:
12618 case FLASH_5761VENDOR_ST_A_M45PE40:
12619 case FLASH_5761VENDOR_ST_A_M45PE80:
12620 case FLASH_5761VENDOR_ST_A_M45PE16:
12621 case FLASH_5761VENDOR_ST_M_M45PE20:
12622 case FLASH_5761VENDOR_ST_M_M45PE40:
12623 case FLASH_5761VENDOR_ST_M_M45PE80:
12624 case FLASH_5761VENDOR_ST_M_M45PE16:
12625 tp->nvram_jedecnum = JEDEC_ST;
12626 tg3_flag_set(tp, NVRAM_BUFFERED);
12627 tg3_flag_set(tp, FLASH);
12628 tp->nvram_pagesize = 256;
12633 tp->nvram_size = tr32(NVRAM_ADDR_LOCKOUT);
12636 case FLASH_5761VENDOR_ATMEL_ADB161D:
12637 case FLASH_5761VENDOR_ATMEL_MDB161D:
12638 case FLASH_5761VENDOR_ST_A_M45PE16:
12639 case FLASH_5761VENDOR_ST_M_M45PE16:
12640 tp->nvram_size = TG3_NVRAM_SIZE_2MB;
12642 case FLASH_5761VENDOR_ATMEL_ADB081D:
12643 case FLASH_5761VENDOR_ATMEL_MDB081D:
12644 case FLASH_5761VENDOR_ST_A_M45PE80:
12645 case FLASH_5761VENDOR_ST_M_M45PE80:
12646 tp->nvram_size = TG3_NVRAM_SIZE_1MB;
12648 case FLASH_5761VENDOR_ATMEL_ADB041D:
12649 case FLASH_5761VENDOR_ATMEL_MDB041D:
12650 case FLASH_5761VENDOR_ST_A_M45PE40:
12651 case FLASH_5761VENDOR_ST_M_M45PE40:
12652 tp->nvram_size = TG3_NVRAM_SIZE_512KB;
12654 case FLASH_5761VENDOR_ATMEL_ADB021D:
12655 case FLASH_5761VENDOR_ATMEL_MDB021D:
12656 case FLASH_5761VENDOR_ST_A_M45PE20:
12657 case FLASH_5761VENDOR_ST_M_M45PE20:
12658 tp->nvram_size = TG3_NVRAM_SIZE_256KB;
12664 static void __devinit tg3_get_5906_nvram_info(struct tg3 *tp)
12666 tp->nvram_jedecnum = JEDEC_ATMEL;
12667 tg3_flag_set(tp, NVRAM_BUFFERED);
12668 tp->nvram_pagesize = ATMEL_AT24C512_CHIP_SIZE;
12671 static void __devinit tg3_get_57780_nvram_info(struct tg3 *tp)
12675 nvcfg1 = tr32(NVRAM_CFG1);
12677 switch (nvcfg1 & NVRAM_CFG1_5752VENDOR_MASK) {
12678 case FLASH_5787VENDOR_ATMEL_EEPROM_376KHZ:
12679 case FLASH_5787VENDOR_MICRO_EEPROM_376KHZ:
12680 tp->nvram_jedecnum = JEDEC_ATMEL;
12681 tg3_flag_set(tp, NVRAM_BUFFERED);
12682 tp->nvram_pagesize = ATMEL_AT24C512_CHIP_SIZE;
12684 nvcfg1 &= ~NVRAM_CFG1_COMPAT_BYPASS;
12685 tw32(NVRAM_CFG1, nvcfg1);
12687 case FLASH_5752VENDOR_ATMEL_FLASH_BUFFERED:
12688 case FLASH_57780VENDOR_ATMEL_AT45DB011D:
12689 case FLASH_57780VENDOR_ATMEL_AT45DB011B:
12690 case FLASH_57780VENDOR_ATMEL_AT45DB021D:
12691 case FLASH_57780VENDOR_ATMEL_AT45DB021B:
12692 case FLASH_57780VENDOR_ATMEL_AT45DB041D:
12693 case FLASH_57780VENDOR_ATMEL_AT45DB041B:
12694 tp->nvram_jedecnum = JEDEC_ATMEL;
12695 tg3_flag_set(tp, NVRAM_BUFFERED);
12696 tg3_flag_set(tp, FLASH);
12698 switch (nvcfg1 & NVRAM_CFG1_5752VENDOR_MASK) {
12699 case FLASH_5752VENDOR_ATMEL_FLASH_BUFFERED:
12700 case FLASH_57780VENDOR_ATMEL_AT45DB011D:
12701 case FLASH_57780VENDOR_ATMEL_AT45DB011B:
12702 tp->nvram_size = TG3_NVRAM_SIZE_128KB;
12704 case FLASH_57780VENDOR_ATMEL_AT45DB021D:
12705 case FLASH_57780VENDOR_ATMEL_AT45DB021B:
12706 tp->nvram_size = TG3_NVRAM_SIZE_256KB;
12708 case FLASH_57780VENDOR_ATMEL_AT45DB041D:
12709 case FLASH_57780VENDOR_ATMEL_AT45DB041B:
12710 tp->nvram_size = TG3_NVRAM_SIZE_512KB;
12714 case FLASH_5752VENDOR_ST_M45PE10:
12715 case FLASH_5752VENDOR_ST_M45PE20:
12716 case FLASH_5752VENDOR_ST_M45PE40:
12717 tp->nvram_jedecnum = JEDEC_ST;
12718 tg3_flag_set(tp, NVRAM_BUFFERED);
12719 tg3_flag_set(tp, FLASH);
12721 switch (nvcfg1 & NVRAM_CFG1_5752VENDOR_MASK) {
12722 case FLASH_5752VENDOR_ST_M45PE10:
12723 tp->nvram_size = TG3_NVRAM_SIZE_128KB;
12725 case FLASH_5752VENDOR_ST_M45PE20:
12726 tp->nvram_size = TG3_NVRAM_SIZE_256KB;
12728 case FLASH_5752VENDOR_ST_M45PE40:
12729 tp->nvram_size = TG3_NVRAM_SIZE_512KB;
12734 tg3_flag_set(tp, NO_NVRAM);
12738 tg3_nvram_get_pagesize(tp, nvcfg1);
12739 if (tp->nvram_pagesize != 264 && tp->nvram_pagesize != 528)
12740 tg3_flag_set(tp, NO_NVRAM_ADDR_TRANS);
12744 static void __devinit tg3_get_5717_nvram_info(struct tg3 *tp)
12748 nvcfg1 = tr32(NVRAM_CFG1);
12750 switch (nvcfg1 & NVRAM_CFG1_5752VENDOR_MASK) {
12751 case FLASH_5717VENDOR_ATMEL_EEPROM:
12752 case FLASH_5717VENDOR_MICRO_EEPROM:
12753 tp->nvram_jedecnum = JEDEC_ATMEL;
12754 tg3_flag_set(tp, NVRAM_BUFFERED);
12755 tp->nvram_pagesize = ATMEL_AT24C512_CHIP_SIZE;
12757 nvcfg1 &= ~NVRAM_CFG1_COMPAT_BYPASS;
12758 tw32(NVRAM_CFG1, nvcfg1);
12760 case FLASH_5717VENDOR_ATMEL_MDB011D:
12761 case FLASH_5717VENDOR_ATMEL_ADB011B:
12762 case FLASH_5717VENDOR_ATMEL_ADB011D:
12763 case FLASH_5717VENDOR_ATMEL_MDB021D:
12764 case FLASH_5717VENDOR_ATMEL_ADB021B:
12765 case FLASH_5717VENDOR_ATMEL_ADB021D:
12766 case FLASH_5717VENDOR_ATMEL_45USPT:
12767 tp->nvram_jedecnum = JEDEC_ATMEL;
12768 tg3_flag_set(tp, NVRAM_BUFFERED);
12769 tg3_flag_set(tp, FLASH);
12771 switch (nvcfg1 & NVRAM_CFG1_5752VENDOR_MASK) {
12772 case FLASH_5717VENDOR_ATMEL_MDB021D:
12773 /* Detect size with tg3_nvram_get_size() */
12775 case FLASH_5717VENDOR_ATMEL_ADB021B:
12776 case FLASH_5717VENDOR_ATMEL_ADB021D:
12777 tp->nvram_size = TG3_NVRAM_SIZE_256KB;
12780 tp->nvram_size = TG3_NVRAM_SIZE_128KB;
12784 case FLASH_5717VENDOR_ST_M_M25PE10:
12785 case FLASH_5717VENDOR_ST_A_M25PE10:
12786 case FLASH_5717VENDOR_ST_M_M45PE10:
12787 case FLASH_5717VENDOR_ST_A_M45PE10:
12788 case FLASH_5717VENDOR_ST_M_M25PE20:
12789 case FLASH_5717VENDOR_ST_A_M25PE20:
12790 case FLASH_5717VENDOR_ST_M_M45PE20:
12791 case FLASH_5717VENDOR_ST_A_M45PE20:
12792 case FLASH_5717VENDOR_ST_25USPT:
12793 case FLASH_5717VENDOR_ST_45USPT:
12794 tp->nvram_jedecnum = JEDEC_ST;
12795 tg3_flag_set(tp, NVRAM_BUFFERED);
12796 tg3_flag_set(tp, FLASH);
12798 switch (nvcfg1 & NVRAM_CFG1_5752VENDOR_MASK) {
12799 case FLASH_5717VENDOR_ST_M_M25PE20:
12800 case FLASH_5717VENDOR_ST_M_M45PE20:
12801 /* Detect size with tg3_nvram_get_size() */
12803 case FLASH_5717VENDOR_ST_A_M25PE20:
12804 case FLASH_5717VENDOR_ST_A_M45PE20:
12805 tp->nvram_size = TG3_NVRAM_SIZE_256KB;
12808 tp->nvram_size = TG3_NVRAM_SIZE_128KB;
12813 tg3_flag_set(tp, NO_NVRAM);
12817 tg3_nvram_get_pagesize(tp, nvcfg1);
12818 if (tp->nvram_pagesize != 264 && tp->nvram_pagesize != 528)
12819 tg3_flag_set(tp, NO_NVRAM_ADDR_TRANS);
12822 static void __devinit tg3_get_5720_nvram_info(struct tg3 *tp)
12824 u32 nvcfg1, nvmpinstrp;
12826 nvcfg1 = tr32(NVRAM_CFG1);
12827 nvmpinstrp = nvcfg1 & NVRAM_CFG1_5752VENDOR_MASK;
12829 switch (nvmpinstrp) {
12830 case FLASH_5720_EEPROM_HD:
12831 case FLASH_5720_EEPROM_LD:
12832 tp->nvram_jedecnum = JEDEC_ATMEL;
12833 tg3_flag_set(tp, NVRAM_BUFFERED);
12835 nvcfg1 &= ~NVRAM_CFG1_COMPAT_BYPASS;
12836 tw32(NVRAM_CFG1, nvcfg1);
12837 if (nvmpinstrp == FLASH_5720_EEPROM_HD)
12838 tp->nvram_pagesize = ATMEL_AT24C512_CHIP_SIZE;
12840 tp->nvram_pagesize = ATMEL_AT24C02_CHIP_SIZE;
12842 case FLASH_5720VENDOR_M_ATMEL_DB011D:
12843 case FLASH_5720VENDOR_A_ATMEL_DB011B:
12844 case FLASH_5720VENDOR_A_ATMEL_DB011D:
12845 case FLASH_5720VENDOR_M_ATMEL_DB021D:
12846 case FLASH_5720VENDOR_A_ATMEL_DB021B:
12847 case FLASH_5720VENDOR_A_ATMEL_DB021D:
12848 case FLASH_5720VENDOR_M_ATMEL_DB041D:
12849 case FLASH_5720VENDOR_A_ATMEL_DB041B:
12850 case FLASH_5720VENDOR_A_ATMEL_DB041D:
12851 case FLASH_5720VENDOR_M_ATMEL_DB081D:
12852 case FLASH_5720VENDOR_A_ATMEL_DB081D:
12853 case FLASH_5720VENDOR_ATMEL_45USPT:
12854 tp->nvram_jedecnum = JEDEC_ATMEL;
12855 tg3_flag_set(tp, NVRAM_BUFFERED);
12856 tg3_flag_set(tp, FLASH);
12858 switch (nvmpinstrp) {
12859 case FLASH_5720VENDOR_M_ATMEL_DB021D:
12860 case FLASH_5720VENDOR_A_ATMEL_DB021B:
12861 case FLASH_5720VENDOR_A_ATMEL_DB021D:
12862 tp->nvram_size = TG3_NVRAM_SIZE_256KB;
12864 case FLASH_5720VENDOR_M_ATMEL_DB041D:
12865 case FLASH_5720VENDOR_A_ATMEL_DB041B:
12866 case FLASH_5720VENDOR_A_ATMEL_DB041D:
12867 tp->nvram_size = TG3_NVRAM_SIZE_512KB;
12869 case FLASH_5720VENDOR_M_ATMEL_DB081D:
12870 case FLASH_5720VENDOR_A_ATMEL_DB081D:
12871 tp->nvram_size = TG3_NVRAM_SIZE_1MB;
12874 tp->nvram_size = TG3_NVRAM_SIZE_128KB;
12878 case FLASH_5720VENDOR_M_ST_M25PE10:
12879 case FLASH_5720VENDOR_M_ST_M45PE10:
12880 case FLASH_5720VENDOR_A_ST_M25PE10:
12881 case FLASH_5720VENDOR_A_ST_M45PE10:
12882 case FLASH_5720VENDOR_M_ST_M25PE20:
12883 case FLASH_5720VENDOR_M_ST_M45PE20:
12884 case FLASH_5720VENDOR_A_ST_M25PE20:
12885 case FLASH_5720VENDOR_A_ST_M45PE20:
12886 case FLASH_5720VENDOR_M_ST_M25PE40:
12887 case FLASH_5720VENDOR_M_ST_M45PE40:
12888 case FLASH_5720VENDOR_A_ST_M25PE40:
12889 case FLASH_5720VENDOR_A_ST_M45PE40:
12890 case FLASH_5720VENDOR_M_ST_M25PE80:
12891 case FLASH_5720VENDOR_M_ST_M45PE80:
12892 case FLASH_5720VENDOR_A_ST_M25PE80:
12893 case FLASH_5720VENDOR_A_ST_M45PE80:
12894 case FLASH_5720VENDOR_ST_25USPT:
12895 case FLASH_5720VENDOR_ST_45USPT:
12896 tp->nvram_jedecnum = JEDEC_ST;
12897 tg3_flag_set(tp, NVRAM_BUFFERED);
12898 tg3_flag_set(tp, FLASH);
12900 switch (nvmpinstrp) {
12901 case FLASH_5720VENDOR_M_ST_M25PE20:
12902 case FLASH_5720VENDOR_M_ST_M45PE20:
12903 case FLASH_5720VENDOR_A_ST_M25PE20:
12904 case FLASH_5720VENDOR_A_ST_M45PE20:
12905 tp->nvram_size = TG3_NVRAM_SIZE_256KB;
12907 case FLASH_5720VENDOR_M_ST_M25PE40:
12908 case FLASH_5720VENDOR_M_ST_M45PE40:
12909 case FLASH_5720VENDOR_A_ST_M25PE40:
12910 case FLASH_5720VENDOR_A_ST_M45PE40:
12911 tp->nvram_size = TG3_NVRAM_SIZE_512KB;
12913 case FLASH_5720VENDOR_M_ST_M25PE80:
12914 case FLASH_5720VENDOR_M_ST_M45PE80:
12915 case FLASH_5720VENDOR_A_ST_M25PE80:
12916 case FLASH_5720VENDOR_A_ST_M45PE80:
12917 tp->nvram_size = TG3_NVRAM_SIZE_1MB;
12920 tp->nvram_size = TG3_NVRAM_SIZE_128KB;
12925 tg3_flag_set(tp, NO_NVRAM);
12929 tg3_nvram_get_pagesize(tp, nvcfg1);
12930 if (tp->nvram_pagesize != 264 && tp->nvram_pagesize != 528)
12931 tg3_flag_set(tp, NO_NVRAM_ADDR_TRANS);
12934 /* Chips other than 5700/5701 use the NVRAM for fetching info. */
12935 static void __devinit tg3_nvram_init(struct tg3 *tp)
12937 tw32_f(GRC_EEPROM_ADDR,
12938 (EEPROM_ADDR_FSM_RESET |
12939 (EEPROM_DEFAULT_CLOCK_PERIOD <<
12940 EEPROM_ADDR_CLKPERD_SHIFT)));
12944 /* Enable seeprom accesses. */
12945 tw32_f(GRC_LOCAL_CTRL,
12946 tr32(GRC_LOCAL_CTRL) | GRC_LCLCTRL_AUTO_SEEPROM);
12949 if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5700 &&
12950 GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5701) {
12951 tg3_flag_set(tp, NVRAM);
12953 if (tg3_nvram_lock(tp)) {
12954 netdev_warn(tp->dev,
12955 "Cannot get nvram lock, %s failed\n",
12959 tg3_enable_nvram_access(tp);
12961 tp->nvram_size = 0;
12963 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5752)
12964 tg3_get_5752_nvram_info(tp);
12965 else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5755)
12966 tg3_get_5755_nvram_info(tp);
12967 else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5787 ||
12968 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5784 ||
12969 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785)
12970 tg3_get_5787_nvram_info(tp);
12971 else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5761)
12972 tg3_get_5761_nvram_info(tp);
12973 else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906)
12974 tg3_get_5906_nvram_info(tp);
12975 else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57780 ||
12976 tg3_flag(tp, 57765_CLASS))
12977 tg3_get_57780_nvram_info(tp);
12978 else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717 ||
12979 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5719)
12980 tg3_get_5717_nvram_info(tp);
12981 else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5720)
12982 tg3_get_5720_nvram_info(tp);
12984 tg3_get_nvram_info(tp);
12986 if (tp->nvram_size == 0)
12987 tg3_get_nvram_size(tp);
12989 tg3_disable_nvram_access(tp);
12990 tg3_nvram_unlock(tp);
12993 tg3_flag_clear(tp, NVRAM);
12994 tg3_flag_clear(tp, NVRAM_BUFFERED);
12996 tg3_get_eeprom_size(tp);
13000 struct subsys_tbl_ent {
13001 u16 subsys_vendor, subsys_devid;
13005 static struct subsys_tbl_ent subsys_id_to_phy_id[] __devinitdata = {
13006 /* Broadcom boards. */
13007 { TG3PCI_SUBVENDOR_ID_BROADCOM,
13008 TG3PCI_SUBDEVICE_ID_BROADCOM_95700A6, TG3_PHY_ID_BCM5401 },
13009 { TG3PCI_SUBVENDOR_ID_BROADCOM,
13010 TG3PCI_SUBDEVICE_ID_BROADCOM_95701A5, TG3_PHY_ID_BCM5701 },
13011 { TG3PCI_SUBVENDOR_ID_BROADCOM,
13012 TG3PCI_SUBDEVICE_ID_BROADCOM_95700T6, TG3_PHY_ID_BCM8002 },
13013 { TG3PCI_SUBVENDOR_ID_BROADCOM,
13014 TG3PCI_SUBDEVICE_ID_BROADCOM_95700A9, 0 },
13015 { TG3PCI_SUBVENDOR_ID_BROADCOM,
13016 TG3PCI_SUBDEVICE_ID_BROADCOM_95701T1, TG3_PHY_ID_BCM5701 },
13017 { TG3PCI_SUBVENDOR_ID_BROADCOM,
13018 TG3PCI_SUBDEVICE_ID_BROADCOM_95701T8, TG3_PHY_ID_BCM5701 },
13019 { TG3PCI_SUBVENDOR_ID_BROADCOM,
13020 TG3PCI_SUBDEVICE_ID_BROADCOM_95701A7, 0 },
13021 { TG3PCI_SUBVENDOR_ID_BROADCOM,
13022 TG3PCI_SUBDEVICE_ID_BROADCOM_95701A10, TG3_PHY_ID_BCM5701 },
13023 { TG3PCI_SUBVENDOR_ID_BROADCOM,
13024 TG3PCI_SUBDEVICE_ID_BROADCOM_95701A12, TG3_PHY_ID_BCM5701 },
13025 { TG3PCI_SUBVENDOR_ID_BROADCOM,
13026 TG3PCI_SUBDEVICE_ID_BROADCOM_95703AX1, TG3_PHY_ID_BCM5703 },
13027 { TG3PCI_SUBVENDOR_ID_BROADCOM,
13028 TG3PCI_SUBDEVICE_ID_BROADCOM_95703AX2, TG3_PHY_ID_BCM5703 },
13031 { TG3PCI_SUBVENDOR_ID_3COM,
13032 TG3PCI_SUBDEVICE_ID_3COM_3C996T, TG3_PHY_ID_BCM5401 },
13033 { TG3PCI_SUBVENDOR_ID_3COM,
13034 TG3PCI_SUBDEVICE_ID_3COM_3C996BT, TG3_PHY_ID_BCM5701 },
13035 { TG3PCI_SUBVENDOR_ID_3COM,
13036 TG3PCI_SUBDEVICE_ID_3COM_3C996SX, 0 },
13037 { TG3PCI_SUBVENDOR_ID_3COM,
13038 TG3PCI_SUBDEVICE_ID_3COM_3C1000T, TG3_PHY_ID_BCM5701 },
13039 { TG3PCI_SUBVENDOR_ID_3COM,
13040 TG3PCI_SUBDEVICE_ID_3COM_3C940BR01, TG3_PHY_ID_BCM5701 },
13043 { TG3PCI_SUBVENDOR_ID_DELL,
13044 TG3PCI_SUBDEVICE_ID_DELL_VIPER, TG3_PHY_ID_BCM5401 },
13045 { TG3PCI_SUBVENDOR_ID_DELL,
13046 TG3PCI_SUBDEVICE_ID_DELL_JAGUAR, TG3_PHY_ID_BCM5401 },
13047 { TG3PCI_SUBVENDOR_ID_DELL,
13048 TG3PCI_SUBDEVICE_ID_DELL_MERLOT, TG3_PHY_ID_BCM5411 },
13049 { TG3PCI_SUBVENDOR_ID_DELL,
13050 TG3PCI_SUBDEVICE_ID_DELL_SLIM_MERLOT, TG3_PHY_ID_BCM5411 },
13052 /* Compaq boards. */
13053 { TG3PCI_SUBVENDOR_ID_COMPAQ,
13054 TG3PCI_SUBDEVICE_ID_COMPAQ_BANSHEE, TG3_PHY_ID_BCM5701 },
13055 { TG3PCI_SUBVENDOR_ID_COMPAQ,
13056 TG3PCI_SUBDEVICE_ID_COMPAQ_BANSHEE_2, TG3_PHY_ID_BCM5701 },
13057 { TG3PCI_SUBVENDOR_ID_COMPAQ,
13058 TG3PCI_SUBDEVICE_ID_COMPAQ_CHANGELING, 0 },
13059 { TG3PCI_SUBVENDOR_ID_COMPAQ,
13060 TG3PCI_SUBDEVICE_ID_COMPAQ_NC7780, TG3_PHY_ID_BCM5701 },
13061 { TG3PCI_SUBVENDOR_ID_COMPAQ,
13062 TG3PCI_SUBDEVICE_ID_COMPAQ_NC7780_2, TG3_PHY_ID_BCM5701 },
13065 { TG3PCI_SUBVENDOR_ID_IBM,
13066 TG3PCI_SUBDEVICE_ID_IBM_5703SAX2, 0 }
13069 static struct subsys_tbl_ent * __devinit tg3_lookup_by_subsys(struct tg3 *tp)
13073 for (i = 0; i < ARRAY_SIZE(subsys_id_to_phy_id); i++) {
13074 if ((subsys_id_to_phy_id[i].subsys_vendor ==
13075 tp->pdev->subsystem_vendor) &&
13076 (subsys_id_to_phy_id[i].subsys_devid ==
13077 tp->pdev->subsystem_device))
13078 return &subsys_id_to_phy_id[i];
13083 static void __devinit tg3_get_eeprom_hw_cfg(struct tg3 *tp)
13087 tp->phy_id = TG3_PHY_ID_INVALID;
13088 tp->led_ctrl = LED_CTRL_MODE_PHY_1;
13090 /* Assume an onboard device and WOL capable by default. */
13091 tg3_flag_set(tp, EEPROM_WRITE_PROT);
13092 tg3_flag_set(tp, WOL_CAP);
13094 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
13095 if (!(tr32(PCIE_TRANSACTION_CFG) & PCIE_TRANS_CFG_LOM)) {
13096 tg3_flag_clear(tp, EEPROM_WRITE_PROT);
13097 tg3_flag_set(tp, IS_NIC);
13099 val = tr32(VCPU_CFGSHDW);
13100 if (val & VCPU_CFGSHDW_ASPM_DBNC)
13101 tg3_flag_set(tp, ASPM_WORKAROUND);
13102 if ((val & VCPU_CFGSHDW_WOL_ENABLE) &&
13103 (val & VCPU_CFGSHDW_WOL_MAGPKT)) {
13104 tg3_flag_set(tp, WOL_ENABLE);
13105 device_set_wakeup_enable(&tp->pdev->dev, true);
13110 tg3_read_mem(tp, NIC_SRAM_DATA_SIG, &val);
13111 if (val == NIC_SRAM_DATA_SIG_MAGIC) {
13112 u32 nic_cfg, led_cfg;
13113 u32 nic_phy_id, ver, cfg2 = 0, cfg4 = 0, eeprom_phy_id;
13114 int eeprom_phy_serdes = 0;
13116 tg3_read_mem(tp, NIC_SRAM_DATA_CFG, &nic_cfg);
13117 tp->nic_sram_data_cfg = nic_cfg;
13119 tg3_read_mem(tp, NIC_SRAM_DATA_VER, &ver);
13120 ver >>= NIC_SRAM_DATA_VER_SHIFT;
13121 if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5700 &&
13122 GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5701 &&
13123 GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5703 &&
13124 (ver > 0) && (ver < 0x100))
13125 tg3_read_mem(tp, NIC_SRAM_DATA_CFG_2, &cfg2);
13127 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785)
13128 tg3_read_mem(tp, NIC_SRAM_DATA_CFG_4, &cfg4);
13130 if ((nic_cfg & NIC_SRAM_DATA_CFG_PHY_TYPE_MASK) ==
13131 NIC_SRAM_DATA_CFG_PHY_TYPE_FIBER)
13132 eeprom_phy_serdes = 1;
13134 tg3_read_mem(tp, NIC_SRAM_DATA_PHY_ID, &nic_phy_id);
13135 if (nic_phy_id != 0) {
13136 u32 id1 = nic_phy_id & NIC_SRAM_DATA_PHY_ID1_MASK;
13137 u32 id2 = nic_phy_id & NIC_SRAM_DATA_PHY_ID2_MASK;
13139 eeprom_phy_id = (id1 >> 16) << 10;
13140 eeprom_phy_id |= (id2 & 0xfc00) << 16;
13141 eeprom_phy_id |= (id2 & 0x03ff) << 0;
13145 tp->phy_id = eeprom_phy_id;
13146 if (eeprom_phy_serdes) {
13147 if (!tg3_flag(tp, 5705_PLUS))
13148 tp->phy_flags |= TG3_PHYFLG_PHY_SERDES;
13150 tp->phy_flags |= TG3_PHYFLG_MII_SERDES;
13153 if (tg3_flag(tp, 5750_PLUS))
13154 led_cfg = cfg2 & (NIC_SRAM_DATA_CFG_LED_MODE_MASK |
13155 SHASTA_EXT_LED_MODE_MASK);
13157 led_cfg = nic_cfg & NIC_SRAM_DATA_CFG_LED_MODE_MASK;
13161 case NIC_SRAM_DATA_CFG_LED_MODE_PHY_1:
13162 tp->led_ctrl = LED_CTRL_MODE_PHY_1;
13165 case NIC_SRAM_DATA_CFG_LED_MODE_PHY_2:
13166 tp->led_ctrl = LED_CTRL_MODE_PHY_2;
13169 case NIC_SRAM_DATA_CFG_LED_MODE_MAC:
13170 tp->led_ctrl = LED_CTRL_MODE_MAC;
13172 /* Default to PHY_1_MODE if 0 (MAC_MODE) is
13173 * read on some older 5700/5701 bootcode.
13175 if (GET_ASIC_REV(tp->pci_chip_rev_id) ==
13177 GET_ASIC_REV(tp->pci_chip_rev_id) ==
13179 tp->led_ctrl = LED_CTRL_MODE_PHY_1;
13183 case SHASTA_EXT_LED_SHARED:
13184 tp->led_ctrl = LED_CTRL_MODE_SHARED;
13185 if (tp->pci_chip_rev_id != CHIPREV_ID_5750_A0 &&
13186 tp->pci_chip_rev_id != CHIPREV_ID_5750_A1)
13187 tp->led_ctrl |= (LED_CTRL_MODE_PHY_1 |
13188 LED_CTRL_MODE_PHY_2);
13191 case SHASTA_EXT_LED_MAC:
13192 tp->led_ctrl = LED_CTRL_MODE_SHASTA_MAC;
13195 case SHASTA_EXT_LED_COMBO:
13196 tp->led_ctrl = LED_CTRL_MODE_COMBO;
13197 if (tp->pci_chip_rev_id != CHIPREV_ID_5750_A0)
13198 tp->led_ctrl |= (LED_CTRL_MODE_PHY_1 |
13199 LED_CTRL_MODE_PHY_2);
13204 if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
13205 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701) &&
13206 tp->pdev->subsystem_vendor == PCI_VENDOR_ID_DELL)
13207 tp->led_ctrl = LED_CTRL_MODE_PHY_2;
13209 if (GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5784_AX)
13210 tp->led_ctrl = LED_CTRL_MODE_PHY_1;
13212 if (nic_cfg & NIC_SRAM_DATA_CFG_EEPROM_WP) {
13213 tg3_flag_set(tp, EEPROM_WRITE_PROT);
13214 if ((tp->pdev->subsystem_vendor ==
13215 PCI_VENDOR_ID_ARIMA) &&
13216 (tp->pdev->subsystem_device == 0x205a ||
13217 tp->pdev->subsystem_device == 0x2063))
13218 tg3_flag_clear(tp, EEPROM_WRITE_PROT);
13220 tg3_flag_clear(tp, EEPROM_WRITE_PROT);
13221 tg3_flag_set(tp, IS_NIC);
13224 if (nic_cfg & NIC_SRAM_DATA_CFG_ASF_ENABLE) {
13225 tg3_flag_set(tp, ENABLE_ASF);
13226 if (tg3_flag(tp, 5750_PLUS))
13227 tg3_flag_set(tp, ASF_NEW_HANDSHAKE);
13230 if ((nic_cfg & NIC_SRAM_DATA_CFG_APE_ENABLE) &&
13231 tg3_flag(tp, 5750_PLUS))
13232 tg3_flag_set(tp, ENABLE_APE);
13234 if (tp->phy_flags & TG3_PHYFLG_ANY_SERDES &&
13235 !(nic_cfg & NIC_SRAM_DATA_CFG_FIBER_WOL))
13236 tg3_flag_clear(tp, WOL_CAP);
13238 if (tg3_flag(tp, WOL_CAP) &&
13239 (nic_cfg & NIC_SRAM_DATA_CFG_WOL_ENABLE)) {
13240 tg3_flag_set(tp, WOL_ENABLE);
13241 device_set_wakeup_enable(&tp->pdev->dev, true);
13244 if (cfg2 & (1 << 17))
13245 tp->phy_flags |= TG3_PHYFLG_CAPACITIVE_COUPLING;
13247 /* serdes signal pre-emphasis in register 0x590 set by */
13248 /* bootcode if bit 18 is set */
13249 if (cfg2 & (1 << 18))
13250 tp->phy_flags |= TG3_PHYFLG_SERDES_PREEMPHASIS;
13252 if ((tg3_flag(tp, 57765_PLUS) ||
13253 (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5784 &&
13254 GET_CHIP_REV(tp->pci_chip_rev_id) != CHIPREV_5784_AX)) &&
13255 (cfg2 & NIC_SRAM_DATA_CFG_2_APD_EN))
13256 tp->phy_flags |= TG3_PHYFLG_ENABLE_APD;
13258 if (tg3_flag(tp, PCI_EXPRESS) &&
13259 GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5785 &&
13260 !tg3_flag(tp, 57765_PLUS)) {
13263 tg3_read_mem(tp, NIC_SRAM_DATA_CFG_3, &cfg3);
13264 if (cfg3 & NIC_SRAM_ASPM_DEBOUNCE)
13265 tg3_flag_set(tp, ASPM_WORKAROUND);
13268 if (cfg4 & NIC_SRAM_RGMII_INBAND_DISABLE)
13269 tg3_flag_set(tp, RGMII_INBAND_DISABLE);
13270 if (cfg4 & NIC_SRAM_RGMII_EXT_IBND_RX_EN)
13271 tg3_flag_set(tp, RGMII_EXT_IBND_RX_EN);
13272 if (cfg4 & NIC_SRAM_RGMII_EXT_IBND_TX_EN)
13273 tg3_flag_set(tp, RGMII_EXT_IBND_TX_EN);
13276 if (tg3_flag(tp, WOL_CAP))
13277 device_set_wakeup_enable(&tp->pdev->dev,
13278 tg3_flag(tp, WOL_ENABLE));
13280 device_set_wakeup_capable(&tp->pdev->dev, false);
13283 static int __devinit tg3_issue_otp_command(struct tg3 *tp, u32 cmd)
13288 tw32(OTP_CTRL, cmd | OTP_CTRL_OTP_CMD_START);
13289 tw32(OTP_CTRL, cmd);
13291 /* Wait for up to 1 ms for command to execute. */
13292 for (i = 0; i < 100; i++) {
13293 val = tr32(OTP_STATUS);
13294 if (val & OTP_STATUS_CMD_DONE)
13299 return (val & OTP_STATUS_CMD_DONE) ? 0 : -EBUSY;
13302 /* Read the gphy configuration from the OTP region of the chip. The gphy
13303 * configuration is a 32-bit value that straddles the alignment boundary.
13304 * We do two 32-bit reads and then shift and merge the results.
13306 static u32 __devinit tg3_read_otp_phycfg(struct tg3 *tp)
13308 u32 bhalf_otp, thalf_otp;
13310 tw32(OTP_MODE, OTP_MODE_OTP_THRU_GRC);
13312 if (tg3_issue_otp_command(tp, OTP_CTRL_OTP_CMD_INIT))
13315 tw32(OTP_ADDRESS, OTP_ADDRESS_MAGIC1);
13317 if (tg3_issue_otp_command(tp, OTP_CTRL_OTP_CMD_READ))
13320 thalf_otp = tr32(OTP_READ_DATA);
13322 tw32(OTP_ADDRESS, OTP_ADDRESS_MAGIC2);
13324 if (tg3_issue_otp_command(tp, OTP_CTRL_OTP_CMD_READ))
13327 bhalf_otp = tr32(OTP_READ_DATA);
13329 return ((thalf_otp & 0x0000ffff) << 16) | (bhalf_otp >> 16);
13332 static void __devinit tg3_phy_init_link_config(struct tg3 *tp)
13334 u32 adv = ADVERTISED_Autoneg;
13336 if (!(tp->phy_flags & TG3_PHYFLG_10_100_ONLY))
13337 adv |= ADVERTISED_1000baseT_Half |
13338 ADVERTISED_1000baseT_Full;
13340 if (!(tp->phy_flags & TG3_PHYFLG_ANY_SERDES))
13341 adv |= ADVERTISED_100baseT_Half |
13342 ADVERTISED_100baseT_Full |
13343 ADVERTISED_10baseT_Half |
13344 ADVERTISED_10baseT_Full |
13347 adv |= ADVERTISED_FIBRE;
13349 tp->link_config.advertising = adv;
13350 tp->link_config.speed = SPEED_UNKNOWN;
13351 tp->link_config.duplex = DUPLEX_UNKNOWN;
13352 tp->link_config.autoneg = AUTONEG_ENABLE;
13353 tp->link_config.active_speed = SPEED_UNKNOWN;
13354 tp->link_config.active_duplex = DUPLEX_UNKNOWN;
13357 static int __devinit tg3_phy_probe(struct tg3 *tp)
13359 u32 hw_phy_id_1, hw_phy_id_2;
13360 u32 hw_phy_id, hw_phy_id_masked;
13363 /* flow control autonegotiation is default behavior */
13364 tg3_flag_set(tp, PAUSE_AUTONEG);
13365 tp->link_config.flowctrl = FLOW_CTRL_TX | FLOW_CTRL_RX;
13367 if (tg3_flag(tp, USE_PHYLIB))
13368 return tg3_phy_init(tp);
13370 /* Reading the PHY ID register can conflict with ASF
13371 * firmware access to the PHY hardware.
13374 if (tg3_flag(tp, ENABLE_ASF) || tg3_flag(tp, ENABLE_APE)) {
13375 hw_phy_id = hw_phy_id_masked = TG3_PHY_ID_INVALID;
13377 /* Now read the physical PHY_ID from the chip and verify
13378 * that it is sane. If it doesn't look good, we fall back
13379 * to either the hard-coded table based PHY_ID and failing
13380 * that the value found in the eeprom area.
13382 err |= tg3_readphy(tp, MII_PHYSID1, &hw_phy_id_1);
13383 err |= tg3_readphy(tp, MII_PHYSID2, &hw_phy_id_2);
13385 hw_phy_id = (hw_phy_id_1 & 0xffff) << 10;
13386 hw_phy_id |= (hw_phy_id_2 & 0xfc00) << 16;
13387 hw_phy_id |= (hw_phy_id_2 & 0x03ff) << 0;
13389 hw_phy_id_masked = hw_phy_id & TG3_PHY_ID_MASK;
13392 if (!err && TG3_KNOWN_PHY_ID(hw_phy_id_masked)) {
13393 tp->phy_id = hw_phy_id;
13394 if (hw_phy_id_masked == TG3_PHY_ID_BCM8002)
13395 tp->phy_flags |= TG3_PHYFLG_PHY_SERDES;
13397 tp->phy_flags &= ~TG3_PHYFLG_PHY_SERDES;
13399 if (tp->phy_id != TG3_PHY_ID_INVALID) {
13400 /* Do nothing, phy ID already set up in
13401 * tg3_get_eeprom_hw_cfg().
13404 struct subsys_tbl_ent *p;
13406 /* No eeprom signature? Try the hardcoded
13407 * subsys device table.
13409 p = tg3_lookup_by_subsys(tp);
13413 tp->phy_id = p->phy_id;
13415 tp->phy_id == TG3_PHY_ID_BCM8002)
13416 tp->phy_flags |= TG3_PHYFLG_PHY_SERDES;
13420 if (!(tp->phy_flags & TG3_PHYFLG_ANY_SERDES) &&
13421 (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5719 ||
13422 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5720 ||
13423 (tp->pdev->device == TG3PCI_DEVICE_TIGON3_5718 &&
13424 tp->pci_chip_rev_id != CHIPREV_ID_5717_A0) ||
13425 (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57765 &&
13426 tp->pci_chip_rev_id != CHIPREV_ID_57765_A0)))
13427 tp->phy_flags |= TG3_PHYFLG_EEE_CAP;
13429 tg3_phy_init_link_config(tp);
13431 if (!(tp->phy_flags & TG3_PHYFLG_ANY_SERDES) &&
13432 !tg3_flag(tp, ENABLE_APE) &&
13433 !tg3_flag(tp, ENABLE_ASF)) {
13436 tg3_readphy(tp, MII_BMSR, &bmsr);
13437 if (!tg3_readphy(tp, MII_BMSR, &bmsr) &&
13438 (bmsr & BMSR_LSTATUS))
13439 goto skip_phy_reset;
13441 err = tg3_phy_reset(tp);
13445 tg3_phy_set_wirespeed(tp);
13447 if (!tg3_phy_copper_an_config_ok(tp, &dummy)) {
13448 tg3_phy_autoneg_cfg(tp, tp->link_config.advertising,
13449 tp->link_config.flowctrl);
13451 tg3_writephy(tp, MII_BMCR,
13452 BMCR_ANENABLE | BMCR_ANRESTART);
13457 if ((tp->phy_id & TG3_PHY_ID_MASK) == TG3_PHY_ID_BCM5401) {
13458 err = tg3_init_5401phy_dsp(tp);
13462 err = tg3_init_5401phy_dsp(tp);
13468 static void __devinit tg3_read_vpd(struct tg3 *tp)
13471 unsigned int block_end, rosize, len;
13475 vpd_data = (u8 *)tg3_vpd_readblock(tp, &vpdlen);
13479 i = pci_vpd_find_tag(vpd_data, 0, vpdlen, PCI_VPD_LRDT_RO_DATA);
13481 goto out_not_found;
13483 rosize = pci_vpd_lrdt_size(&vpd_data[i]);
13484 block_end = i + PCI_VPD_LRDT_TAG_SIZE + rosize;
13485 i += PCI_VPD_LRDT_TAG_SIZE;
13487 if (block_end > vpdlen)
13488 goto out_not_found;
13490 j = pci_vpd_find_info_keyword(vpd_data, i, rosize,
13491 PCI_VPD_RO_KEYWORD_MFR_ID);
13493 len = pci_vpd_info_field_size(&vpd_data[j]);
13495 j += PCI_VPD_INFO_FLD_HDR_SIZE;
13496 if (j + len > block_end || len != 4 ||
13497 memcmp(&vpd_data[j], "1028", 4))
13500 j = pci_vpd_find_info_keyword(vpd_data, i, rosize,
13501 PCI_VPD_RO_KEYWORD_VENDOR0);
13505 len = pci_vpd_info_field_size(&vpd_data[j]);
13507 j += PCI_VPD_INFO_FLD_HDR_SIZE;
13508 if (j + len > block_end)
13511 memcpy(tp->fw_ver, &vpd_data[j], len);
13512 strncat(tp->fw_ver, " bc ", vpdlen - len - 1);
13516 i = pci_vpd_find_info_keyword(vpd_data, i, rosize,
13517 PCI_VPD_RO_KEYWORD_PARTNO);
13519 goto out_not_found;
13521 len = pci_vpd_info_field_size(&vpd_data[i]);
13523 i += PCI_VPD_INFO_FLD_HDR_SIZE;
13524 if (len > TG3_BPN_SIZE ||
13525 (len + i) > vpdlen)
13526 goto out_not_found;
13528 memcpy(tp->board_part_number, &vpd_data[i], len);
13532 if (tp->board_part_number[0])
13536 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717) {
13537 if (tp->pdev->device == TG3PCI_DEVICE_TIGON3_5717)
13538 strcpy(tp->board_part_number, "BCM5717");
13539 else if (tp->pdev->device == TG3PCI_DEVICE_TIGON3_5718)
13540 strcpy(tp->board_part_number, "BCM5718");
13543 } else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57780) {
13544 if (tp->pdev->device == TG3PCI_DEVICE_TIGON3_57780)
13545 strcpy(tp->board_part_number, "BCM57780");
13546 else if (tp->pdev->device == TG3PCI_DEVICE_TIGON3_57760)
13547 strcpy(tp->board_part_number, "BCM57760");
13548 else if (tp->pdev->device == TG3PCI_DEVICE_TIGON3_57790)
13549 strcpy(tp->board_part_number, "BCM57790");
13550 else if (tp->pdev->device == TG3PCI_DEVICE_TIGON3_57788)
13551 strcpy(tp->board_part_number, "BCM57788");
13554 } else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57765) {
13555 if (tp->pdev->device == TG3PCI_DEVICE_TIGON3_57761)
13556 strcpy(tp->board_part_number, "BCM57761");
13557 else if (tp->pdev->device == TG3PCI_DEVICE_TIGON3_57765)
13558 strcpy(tp->board_part_number, "BCM57765");
13559 else if (tp->pdev->device == TG3PCI_DEVICE_TIGON3_57781)
13560 strcpy(tp->board_part_number, "BCM57781");
13561 else if (tp->pdev->device == TG3PCI_DEVICE_TIGON3_57785)
13562 strcpy(tp->board_part_number, "BCM57785");
13563 else if (tp->pdev->device == TG3PCI_DEVICE_TIGON3_57791)
13564 strcpy(tp->board_part_number, "BCM57791");
13565 else if (tp->pdev->device == TG3PCI_DEVICE_TIGON3_57795)
13566 strcpy(tp->board_part_number, "BCM57795");
13569 } else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57766) {
13570 if (tp->pdev->device == TG3PCI_DEVICE_TIGON3_57762)
13571 strcpy(tp->board_part_number, "BCM57762");
13572 else if (tp->pdev->device == TG3PCI_DEVICE_TIGON3_57766)
13573 strcpy(tp->board_part_number, "BCM57766");
13574 else if (tp->pdev->device == TG3PCI_DEVICE_TIGON3_57782)
13575 strcpy(tp->board_part_number, "BCM57782");
13576 else if (tp->pdev->device == TG3PCI_DEVICE_TIGON3_57786)
13577 strcpy(tp->board_part_number, "BCM57786");
13580 } else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
13581 strcpy(tp->board_part_number, "BCM95906");
13584 strcpy(tp->board_part_number, "none");
13588 static int __devinit tg3_fw_img_is_valid(struct tg3 *tp, u32 offset)
13592 if (tg3_nvram_read(tp, offset, &val) ||
13593 (val & 0xfc000000) != 0x0c000000 ||
13594 tg3_nvram_read(tp, offset + 4, &val) ||
13601 static void __devinit tg3_read_bc_ver(struct tg3 *tp)
13603 u32 val, offset, start, ver_offset;
13605 bool newver = false;
13607 if (tg3_nvram_read(tp, 0xc, &offset) ||
13608 tg3_nvram_read(tp, 0x4, &start))
13611 offset = tg3_nvram_logical_addr(tp, offset);
13613 if (tg3_nvram_read(tp, offset, &val))
13616 if ((val & 0xfc000000) == 0x0c000000) {
13617 if (tg3_nvram_read(tp, offset + 4, &val))
13624 dst_off = strlen(tp->fw_ver);
13627 if (TG3_VER_SIZE - dst_off < 16 ||
13628 tg3_nvram_read(tp, offset + 8, &ver_offset))
13631 offset = offset + ver_offset - start;
13632 for (i = 0; i < 16; i += 4) {
13634 if (tg3_nvram_read_be32(tp, offset + i, &v))
13637 memcpy(tp->fw_ver + dst_off + i, &v, sizeof(v));
13642 if (tg3_nvram_read(tp, TG3_NVM_PTREV_BCVER, &ver_offset))
13645 major = (ver_offset & TG3_NVM_BCVER_MAJMSK) >>
13646 TG3_NVM_BCVER_MAJSFT;
13647 minor = ver_offset & TG3_NVM_BCVER_MINMSK;
13648 snprintf(&tp->fw_ver[dst_off], TG3_VER_SIZE - dst_off,
13649 "v%d.%02d", major, minor);
13653 static void __devinit tg3_read_hwsb_ver(struct tg3 *tp)
13655 u32 val, major, minor;
13657 /* Use native endian representation */
13658 if (tg3_nvram_read(tp, TG3_NVM_HWSB_CFG1, &val))
13661 major = (val & TG3_NVM_HWSB_CFG1_MAJMSK) >>
13662 TG3_NVM_HWSB_CFG1_MAJSFT;
13663 minor = (val & TG3_NVM_HWSB_CFG1_MINMSK) >>
13664 TG3_NVM_HWSB_CFG1_MINSFT;
13666 snprintf(&tp->fw_ver[0], 32, "sb v%d.%02d", major, minor);
13669 static void __devinit tg3_read_sb_ver(struct tg3 *tp, u32 val)
13671 u32 offset, major, minor, build;
13673 strncat(tp->fw_ver, "sb", TG3_VER_SIZE - strlen(tp->fw_ver) - 1);
13675 if ((val & TG3_EEPROM_SB_FORMAT_MASK) != TG3_EEPROM_SB_FORMAT_1)
13678 switch (val & TG3_EEPROM_SB_REVISION_MASK) {
13679 case TG3_EEPROM_SB_REVISION_0:
13680 offset = TG3_EEPROM_SB_F1R0_EDH_OFF;
13682 case TG3_EEPROM_SB_REVISION_2:
13683 offset = TG3_EEPROM_SB_F1R2_EDH_OFF;
13685 case TG3_EEPROM_SB_REVISION_3:
13686 offset = TG3_EEPROM_SB_F1R3_EDH_OFF;
13688 case TG3_EEPROM_SB_REVISION_4:
13689 offset = TG3_EEPROM_SB_F1R4_EDH_OFF;
13691 case TG3_EEPROM_SB_REVISION_5:
13692 offset = TG3_EEPROM_SB_F1R5_EDH_OFF;
13694 case TG3_EEPROM_SB_REVISION_6:
13695 offset = TG3_EEPROM_SB_F1R6_EDH_OFF;
13701 if (tg3_nvram_read(tp, offset, &val))
13704 build = (val & TG3_EEPROM_SB_EDH_BLD_MASK) >>
13705 TG3_EEPROM_SB_EDH_BLD_SHFT;
13706 major = (val & TG3_EEPROM_SB_EDH_MAJ_MASK) >>
13707 TG3_EEPROM_SB_EDH_MAJ_SHFT;
13708 minor = val & TG3_EEPROM_SB_EDH_MIN_MASK;
13710 if (minor > 99 || build > 26)
13713 offset = strlen(tp->fw_ver);
13714 snprintf(&tp->fw_ver[offset], TG3_VER_SIZE - offset,
13715 " v%d.%02d", major, minor);
13718 offset = strlen(tp->fw_ver);
13719 if (offset < TG3_VER_SIZE - 1)
13720 tp->fw_ver[offset] = 'a' + build - 1;
13724 static void __devinit tg3_read_mgmtfw_ver(struct tg3 *tp)
13726 u32 val, offset, start;
13729 for (offset = TG3_NVM_DIR_START;
13730 offset < TG3_NVM_DIR_END;
13731 offset += TG3_NVM_DIRENT_SIZE) {
13732 if (tg3_nvram_read(tp, offset, &val))
13735 if ((val >> TG3_NVM_DIRTYPE_SHIFT) == TG3_NVM_DIRTYPE_ASFINI)
13739 if (offset == TG3_NVM_DIR_END)
13742 if (!tg3_flag(tp, 5705_PLUS))
13743 start = 0x08000000;
13744 else if (tg3_nvram_read(tp, offset - 4, &start))
13747 if (tg3_nvram_read(tp, offset + 4, &offset) ||
13748 !tg3_fw_img_is_valid(tp, offset) ||
13749 tg3_nvram_read(tp, offset + 8, &val))
13752 offset += val - start;
13754 vlen = strlen(tp->fw_ver);
13756 tp->fw_ver[vlen++] = ',';
13757 tp->fw_ver[vlen++] = ' ';
13759 for (i = 0; i < 4; i++) {
13761 if (tg3_nvram_read_be32(tp, offset, &v))
13764 offset += sizeof(v);
13766 if (vlen > TG3_VER_SIZE - sizeof(v)) {
13767 memcpy(&tp->fw_ver[vlen], &v, TG3_VER_SIZE - vlen);
13771 memcpy(&tp->fw_ver[vlen], &v, sizeof(v));
13776 static void __devinit tg3_read_dash_ver(struct tg3 *tp)
13782 if (!tg3_flag(tp, ENABLE_APE) || !tg3_flag(tp, ENABLE_ASF))
13785 apedata = tg3_ape_read32(tp, TG3_APE_SEG_SIG);
13786 if (apedata != APE_SEG_SIG_MAGIC)
13789 apedata = tg3_ape_read32(tp, TG3_APE_FW_STATUS);
13790 if (!(apedata & APE_FW_STATUS_READY))
13793 apedata = tg3_ape_read32(tp, TG3_APE_FW_VERSION);
13795 if (tg3_ape_read32(tp, TG3_APE_FW_FEATURES) & TG3_APE_FW_FEATURE_NCSI) {
13796 tg3_flag_set(tp, APE_HAS_NCSI);
13802 vlen = strlen(tp->fw_ver);
13804 snprintf(&tp->fw_ver[vlen], TG3_VER_SIZE - vlen, " %s v%d.%d.%d.%d",
13806 (apedata & APE_FW_VERSION_MAJMSK) >> APE_FW_VERSION_MAJSFT,
13807 (apedata & APE_FW_VERSION_MINMSK) >> APE_FW_VERSION_MINSFT,
13808 (apedata & APE_FW_VERSION_REVMSK) >> APE_FW_VERSION_REVSFT,
13809 (apedata & APE_FW_VERSION_BLDMSK));
13812 static void __devinit tg3_read_fw_ver(struct tg3 *tp)
13815 bool vpd_vers = false;
13817 if (tp->fw_ver[0] != 0)
13820 if (tg3_flag(tp, NO_NVRAM)) {
13821 strcat(tp->fw_ver, "sb");
13825 if (tg3_nvram_read(tp, 0, &val))
13828 if (val == TG3_EEPROM_MAGIC)
13829 tg3_read_bc_ver(tp);
13830 else if ((val & TG3_EEPROM_MAGIC_FW_MSK) == TG3_EEPROM_MAGIC_FW)
13831 tg3_read_sb_ver(tp, val);
13832 else if ((val & TG3_EEPROM_MAGIC_HW_MSK) == TG3_EEPROM_MAGIC_HW)
13833 tg3_read_hwsb_ver(tp);
13840 if (tg3_flag(tp, ENABLE_APE)) {
13841 if (tg3_flag(tp, ENABLE_ASF))
13842 tg3_read_dash_ver(tp);
13843 } else if (tg3_flag(tp, ENABLE_ASF)) {
13844 tg3_read_mgmtfw_ver(tp);
13848 tp->fw_ver[TG3_VER_SIZE - 1] = 0;
13851 static inline u32 tg3_rx_ret_ring_size(struct tg3 *tp)
13853 if (tg3_flag(tp, LRG_PROD_RING_CAP))
13854 return TG3_RX_RET_MAX_SIZE_5717;
13855 else if (tg3_flag(tp, JUMBO_CAPABLE) && !tg3_flag(tp, 5780_CLASS))
13856 return TG3_RX_RET_MAX_SIZE_5700;
13858 return TG3_RX_RET_MAX_SIZE_5705;
13861 static DEFINE_PCI_DEVICE_TABLE(tg3_write_reorder_chipsets) = {
13862 { PCI_DEVICE(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_FE_GATE_700C) },
13863 { PCI_DEVICE(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_8131_BRIDGE) },
13864 { PCI_DEVICE(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8385_0) },
13868 static struct pci_dev * __devinit tg3_find_peer(struct tg3 *tp)
13870 struct pci_dev *peer;
13871 unsigned int func, devnr = tp->pdev->devfn & ~7;
13873 for (func = 0; func < 8; func++) {
13874 peer = pci_get_slot(tp->pdev->bus, devnr | func);
13875 if (peer && peer != tp->pdev)
13879 /* 5704 can be configured in single-port mode, set peer to
13880 * tp->pdev in that case.
13888 * We don't need to keep the refcount elevated; there's no way
13889 * to remove one half of this device without removing the other
13896 static void __devinit tg3_detect_asic_rev(struct tg3 *tp, u32 misc_ctrl_reg)
13898 tp->pci_chip_rev_id = misc_ctrl_reg >> MISC_HOST_CTRL_CHIPREV_SHIFT;
13899 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_USE_PROD_ID_REG) {
13902 /* All devices that use the alternate
13903 * ASIC REV location have a CPMU.
13905 tg3_flag_set(tp, CPMU_PRESENT);
13907 if (tp->pdev->device == TG3PCI_DEVICE_TIGON3_5717 ||
13908 tp->pdev->device == TG3PCI_DEVICE_TIGON3_5718 ||
13909 tp->pdev->device == TG3PCI_DEVICE_TIGON3_5719 ||
13910 tp->pdev->device == TG3PCI_DEVICE_TIGON3_5720)
13911 reg = TG3PCI_GEN2_PRODID_ASICREV;
13912 else if (tp->pdev->device == TG3PCI_DEVICE_TIGON3_57781 ||
13913 tp->pdev->device == TG3PCI_DEVICE_TIGON3_57785 ||
13914 tp->pdev->device == TG3PCI_DEVICE_TIGON3_57761 ||
13915 tp->pdev->device == TG3PCI_DEVICE_TIGON3_57765 ||
13916 tp->pdev->device == TG3PCI_DEVICE_TIGON3_57791 ||
13917 tp->pdev->device == TG3PCI_DEVICE_TIGON3_57795 ||
13918 tp->pdev->device == TG3PCI_DEVICE_TIGON3_57762 ||
13919 tp->pdev->device == TG3PCI_DEVICE_TIGON3_57766 ||
13920 tp->pdev->device == TG3PCI_DEVICE_TIGON3_57782 ||
13921 tp->pdev->device == TG3PCI_DEVICE_TIGON3_57786)
13922 reg = TG3PCI_GEN15_PRODID_ASICREV;
13924 reg = TG3PCI_PRODID_ASICREV;
13926 pci_read_config_dword(tp->pdev, reg, &tp->pci_chip_rev_id);
13929 /* Wrong chip ID in 5752 A0. This code can be removed later
13930 * as A0 is not in production.
13932 if (tp->pci_chip_rev_id == CHIPREV_ID_5752_A0_HW)
13933 tp->pci_chip_rev_id = CHIPREV_ID_5752_A0;
13935 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717 ||
13936 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5719 ||
13937 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5720)
13938 tg3_flag_set(tp, 5717_PLUS);
13940 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57765 ||
13941 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57766)
13942 tg3_flag_set(tp, 57765_CLASS);
13944 if (tg3_flag(tp, 57765_CLASS) || tg3_flag(tp, 5717_PLUS))
13945 tg3_flag_set(tp, 57765_PLUS);
13947 /* Intentionally exclude ASIC_REV_5906 */
13948 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5755 ||
13949 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5787 ||
13950 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5784 ||
13951 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5761 ||
13952 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785 ||
13953 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57780 ||
13954 tg3_flag(tp, 57765_PLUS))
13955 tg3_flag_set(tp, 5755_PLUS);
13957 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5780 ||
13958 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5714)
13959 tg3_flag_set(tp, 5780_CLASS);
13961 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5750 ||
13962 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5752 ||
13963 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906 ||
13964 tg3_flag(tp, 5755_PLUS) ||
13965 tg3_flag(tp, 5780_CLASS))
13966 tg3_flag_set(tp, 5750_PLUS);
13968 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705 ||
13969 tg3_flag(tp, 5750_PLUS))
13970 tg3_flag_set(tp, 5705_PLUS);
13973 static int __devinit tg3_get_invariants(struct tg3 *tp)
13976 u32 pci_state_reg, grc_misc_cfg;
13981 /* Force memory write invalidate off. If we leave it on,
13982 * then on 5700_BX chips we have to enable a workaround.
13983 * The workaround is to set the TG3PCI_DMA_RW_CTRL boundary
13984 * to match the cacheline size. The Broadcom driver have this
13985 * workaround but turns MWI off all the times so never uses
13986 * it. This seems to suggest that the workaround is insufficient.
13988 pci_read_config_word(tp->pdev, PCI_COMMAND, &pci_cmd);
13989 pci_cmd &= ~PCI_COMMAND_INVALIDATE;
13990 pci_write_config_word(tp->pdev, PCI_COMMAND, pci_cmd);
13992 /* Important! -- Make sure register accesses are byteswapped
13993 * correctly. Also, for those chips that require it, make
13994 * sure that indirect register accesses are enabled before
13995 * the first operation.
13997 pci_read_config_dword(tp->pdev, TG3PCI_MISC_HOST_CTRL,
13999 tp->misc_host_ctrl |= (misc_ctrl_reg &
14000 MISC_HOST_CTRL_CHIPREV);
14001 pci_write_config_dword(tp->pdev, TG3PCI_MISC_HOST_CTRL,
14002 tp->misc_host_ctrl);
14004 tg3_detect_asic_rev(tp, misc_ctrl_reg);
14006 /* If we have 5702/03 A1 or A2 on certain ICH chipsets,
14007 * we need to disable memory and use config. cycles
14008 * only to access all registers. The 5702/03 chips
14009 * can mistakenly decode the special cycles from the
14010 * ICH chipsets as memory write cycles, causing corruption
14011 * of register and memory space. Only certain ICH bridges
14012 * will drive special cycles with non-zero data during the
14013 * address phase which can fall within the 5703's address
14014 * range. This is not an ICH bug as the PCI spec allows
14015 * non-zero address during special cycles. However, only
14016 * these ICH bridges are known to drive non-zero addresses
14017 * during special cycles.
14019 * Since special cycles do not cross PCI bridges, we only
14020 * enable this workaround if the 5703 is on the secondary
14021 * bus of these ICH bridges.
14023 if ((tp->pci_chip_rev_id == CHIPREV_ID_5703_A1) ||
14024 (tp->pci_chip_rev_id == CHIPREV_ID_5703_A2)) {
14025 static struct tg3_dev_id {
14029 } ich_chipsets[] = {
14030 { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801AA_8,
14032 { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801AB_8,
14034 { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801BA_11,
14036 { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801BA_6,
14040 struct tg3_dev_id *pci_id = &ich_chipsets[0];
14041 struct pci_dev *bridge = NULL;
14043 while (pci_id->vendor != 0) {
14044 bridge = pci_get_device(pci_id->vendor, pci_id->device,
14050 if (pci_id->rev != PCI_ANY_ID) {
14051 if (bridge->revision > pci_id->rev)
14054 if (bridge->subordinate &&
14055 (bridge->subordinate->number ==
14056 tp->pdev->bus->number)) {
14057 tg3_flag_set(tp, ICH_WORKAROUND);
14058 pci_dev_put(bridge);
14064 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701) {
14065 static struct tg3_dev_id {
14068 } bridge_chipsets[] = {
14069 { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_PXH_0 },
14070 { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_PXH_1 },
14073 struct tg3_dev_id *pci_id = &bridge_chipsets[0];
14074 struct pci_dev *bridge = NULL;
14076 while (pci_id->vendor != 0) {
14077 bridge = pci_get_device(pci_id->vendor,
14084 if (bridge->subordinate &&
14085 (bridge->subordinate->number <=
14086 tp->pdev->bus->number) &&
14087 (bridge->subordinate->subordinate >=
14088 tp->pdev->bus->number)) {
14089 tg3_flag_set(tp, 5701_DMA_BUG);
14090 pci_dev_put(bridge);
14096 /* The EPB bridge inside 5714, 5715, and 5780 cannot support
14097 * DMA addresses > 40-bit. This bridge may have other additional
14098 * 57xx devices behind it in some 4-port NIC designs for example.
14099 * Any tg3 device found behind the bridge will also need the 40-bit
14102 if (tg3_flag(tp, 5780_CLASS)) {
14103 tg3_flag_set(tp, 40BIT_DMA_BUG);
14104 tp->msi_cap = pci_find_capability(tp->pdev, PCI_CAP_ID_MSI);
14106 struct pci_dev *bridge = NULL;
14109 bridge = pci_get_device(PCI_VENDOR_ID_SERVERWORKS,
14110 PCI_DEVICE_ID_SERVERWORKS_EPB,
14112 if (bridge && bridge->subordinate &&
14113 (bridge->subordinate->number <=
14114 tp->pdev->bus->number) &&
14115 (bridge->subordinate->subordinate >=
14116 tp->pdev->bus->number)) {
14117 tg3_flag_set(tp, 40BIT_DMA_BUG);
14118 pci_dev_put(bridge);
14124 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704 ||
14125 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5714)
14126 tp->pdev_peer = tg3_find_peer(tp);
14128 /* Determine TSO capabilities */
14129 if (tp->pci_chip_rev_id == CHIPREV_ID_5719_A0)
14130 ; /* Do nothing. HW bug. */
14131 else if (tg3_flag(tp, 57765_PLUS))
14132 tg3_flag_set(tp, HW_TSO_3);
14133 else if (tg3_flag(tp, 5755_PLUS) ||
14134 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906)
14135 tg3_flag_set(tp, HW_TSO_2);
14136 else if (tg3_flag(tp, 5750_PLUS)) {
14137 tg3_flag_set(tp, HW_TSO_1);
14138 tg3_flag_set(tp, TSO_BUG);
14139 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5750 &&
14140 tp->pci_chip_rev_id >= CHIPREV_ID_5750_C2)
14141 tg3_flag_clear(tp, TSO_BUG);
14142 } else if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5700 &&
14143 GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5701 &&
14144 tp->pci_chip_rev_id != CHIPREV_ID_5705_A0) {
14145 tg3_flag_set(tp, TSO_BUG);
14146 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705)
14147 tp->fw_needed = FIRMWARE_TG3TSO5;
14149 tp->fw_needed = FIRMWARE_TG3TSO;
14152 /* Selectively allow TSO based on operating conditions */
14153 if (tg3_flag(tp, HW_TSO_1) ||
14154 tg3_flag(tp, HW_TSO_2) ||
14155 tg3_flag(tp, HW_TSO_3) ||
14157 /* For firmware TSO, assume ASF is disabled.
14158 * We'll disable TSO later if we discover ASF
14159 * is enabled in tg3_get_eeprom_hw_cfg().
14161 tg3_flag_set(tp, TSO_CAPABLE);
14163 tg3_flag_clear(tp, TSO_CAPABLE);
14164 tg3_flag_clear(tp, TSO_BUG);
14165 tp->fw_needed = NULL;
14168 if (tp->pci_chip_rev_id == CHIPREV_ID_5701_A0)
14169 tp->fw_needed = FIRMWARE_TG3;
14173 if (tg3_flag(tp, 5750_PLUS)) {
14174 tg3_flag_set(tp, SUPPORT_MSI);
14175 if (GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5750_AX ||
14176 GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5750_BX ||
14177 (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5714 &&
14178 tp->pci_chip_rev_id <= CHIPREV_ID_5714_A2 &&
14179 tp->pdev_peer == tp->pdev))
14180 tg3_flag_clear(tp, SUPPORT_MSI);
14182 if (tg3_flag(tp, 5755_PLUS) ||
14183 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
14184 tg3_flag_set(tp, 1SHOT_MSI);
14187 if (tg3_flag(tp, 57765_PLUS)) {
14188 tg3_flag_set(tp, SUPPORT_MSIX);
14189 tp->irq_max = TG3_IRQ_MAX_VECS;
14190 tg3_rss_init_dflt_indir_tbl(tp);
14194 if (tg3_flag(tp, 5755_PLUS))
14195 tg3_flag_set(tp, SHORT_DMA_BUG);
14197 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5719)
14198 tp->dma_limit = TG3_TX_BD_DMA_MAX_4K;
14200 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717 ||
14201 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5719 ||
14202 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5720)
14203 tg3_flag_set(tp, LRG_PROD_RING_CAP);
14205 if (tg3_flag(tp, 57765_PLUS) &&
14206 tp->pci_chip_rev_id != CHIPREV_ID_5719_A0)
14207 tg3_flag_set(tp, USE_JUMBO_BDFLAG);
14209 if (!tg3_flag(tp, 5705_PLUS) ||
14210 tg3_flag(tp, 5780_CLASS) ||
14211 tg3_flag(tp, USE_JUMBO_BDFLAG))
14212 tg3_flag_set(tp, JUMBO_CAPABLE);
14214 pci_read_config_dword(tp->pdev, TG3PCI_PCISTATE,
14217 if (pci_is_pcie(tp->pdev)) {
14220 tg3_flag_set(tp, PCI_EXPRESS);
14222 if (tp->pci_chip_rev_id == CHIPREV_ID_5719_A0) {
14223 int readrq = pcie_get_readrq(tp->pdev);
14225 pcie_set_readrq(tp->pdev, 2048);
14228 pci_read_config_word(tp->pdev,
14229 pci_pcie_cap(tp->pdev) + PCI_EXP_LNKCTL,
14231 if (lnkctl & PCI_EXP_LNKCTL_CLKREQ_EN) {
14232 if (GET_ASIC_REV(tp->pci_chip_rev_id) ==
14234 tg3_flag_clear(tp, HW_TSO_2);
14235 tg3_flag_clear(tp, TSO_CAPABLE);
14237 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5784 ||
14238 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5761 ||
14239 tp->pci_chip_rev_id == CHIPREV_ID_57780_A0 ||
14240 tp->pci_chip_rev_id == CHIPREV_ID_57780_A1)
14241 tg3_flag_set(tp, CLKREQ_BUG);
14242 } else if (tp->pci_chip_rev_id == CHIPREV_ID_5717_A0) {
14243 tg3_flag_set(tp, L1PLLPD_EN);
14245 } else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785) {
14246 /* BCM5785 devices are effectively PCIe devices, and should
14247 * follow PCIe codepaths, but do not have a PCIe capabilities
14250 tg3_flag_set(tp, PCI_EXPRESS);
14251 } else if (!tg3_flag(tp, 5705_PLUS) ||
14252 tg3_flag(tp, 5780_CLASS)) {
14253 tp->pcix_cap = pci_find_capability(tp->pdev, PCI_CAP_ID_PCIX);
14254 if (!tp->pcix_cap) {
14255 dev_err(&tp->pdev->dev,
14256 "Cannot find PCI-X capability, aborting\n");
14260 if (!(pci_state_reg & PCISTATE_CONV_PCI_MODE))
14261 tg3_flag_set(tp, PCIX_MODE);
14264 /* If we have an AMD 762 or VIA K8T800 chipset, write
14265 * reordering to the mailbox registers done by the host
14266 * controller can cause major troubles. We read back from
14267 * every mailbox register write to force the writes to be
14268 * posted to the chip in order.
14270 if (pci_dev_present(tg3_write_reorder_chipsets) &&
14271 !tg3_flag(tp, PCI_EXPRESS))
14272 tg3_flag_set(tp, MBOX_WRITE_REORDER);
14274 pci_read_config_byte(tp->pdev, PCI_CACHE_LINE_SIZE,
14275 &tp->pci_cacheline_sz);
14276 pci_read_config_byte(tp->pdev, PCI_LATENCY_TIMER,
14277 &tp->pci_lat_timer);
14278 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703 &&
14279 tp->pci_lat_timer < 64) {
14280 tp->pci_lat_timer = 64;
14281 pci_write_config_byte(tp->pdev, PCI_LATENCY_TIMER,
14282 tp->pci_lat_timer);
14285 /* Important! -- It is critical that the PCI-X hw workaround
14286 * situation is decided before the first MMIO register access.
14288 if (GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5700_BX) {
14289 /* 5700 BX chips need to have their TX producer index
14290 * mailboxes written twice to workaround a bug.
14292 tg3_flag_set(tp, TXD_MBOX_HWBUG);
14294 /* If we are in PCI-X mode, enable register write workaround.
14296 * The workaround is to use indirect register accesses
14297 * for all chip writes not to mailbox registers.
14299 if (tg3_flag(tp, PCIX_MODE)) {
14302 tg3_flag_set(tp, PCIX_TARGET_HWBUG);
14304 /* The chip can have it's power management PCI config
14305 * space registers clobbered due to this bug.
14306 * So explicitly force the chip into D0 here.
14308 pci_read_config_dword(tp->pdev,
14309 tp->pm_cap + PCI_PM_CTRL,
14311 pm_reg &= ~PCI_PM_CTRL_STATE_MASK;
14312 pm_reg |= PCI_PM_CTRL_PME_ENABLE | 0 /* D0 */;
14313 pci_write_config_dword(tp->pdev,
14314 tp->pm_cap + PCI_PM_CTRL,
14317 /* Also, force SERR#/PERR# in PCI command. */
14318 pci_read_config_word(tp->pdev, PCI_COMMAND, &pci_cmd);
14319 pci_cmd |= PCI_COMMAND_PARITY | PCI_COMMAND_SERR;
14320 pci_write_config_word(tp->pdev, PCI_COMMAND, pci_cmd);
14324 if ((pci_state_reg & PCISTATE_BUS_SPEED_HIGH) != 0)
14325 tg3_flag_set(tp, PCI_HIGH_SPEED);
14326 if ((pci_state_reg & PCISTATE_BUS_32BIT) != 0)
14327 tg3_flag_set(tp, PCI_32BIT);
14329 /* Chip-specific fixup from Broadcom driver */
14330 if ((tp->pci_chip_rev_id == CHIPREV_ID_5704_A0) &&
14331 (!(pci_state_reg & PCISTATE_RETRY_SAME_DMA))) {
14332 pci_state_reg |= PCISTATE_RETRY_SAME_DMA;
14333 pci_write_config_dword(tp->pdev, TG3PCI_PCISTATE, pci_state_reg);
14336 /* Default fast path register access methods */
14337 tp->read32 = tg3_read32;
14338 tp->write32 = tg3_write32;
14339 tp->read32_mbox = tg3_read32;
14340 tp->write32_mbox = tg3_write32;
14341 tp->write32_tx_mbox = tg3_write32;
14342 tp->write32_rx_mbox = tg3_write32;
14344 /* Various workaround register access methods */
14345 if (tg3_flag(tp, PCIX_TARGET_HWBUG))
14346 tp->write32 = tg3_write_indirect_reg32;
14347 else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701 ||
14348 (tg3_flag(tp, PCI_EXPRESS) &&
14349 tp->pci_chip_rev_id == CHIPREV_ID_5750_A0)) {
14351 * Back to back register writes can cause problems on these
14352 * chips, the workaround is to read back all reg writes
14353 * except those to mailbox regs.
14355 * See tg3_write_indirect_reg32().
14357 tp->write32 = tg3_write_flush_reg32;
14360 if (tg3_flag(tp, TXD_MBOX_HWBUG) || tg3_flag(tp, MBOX_WRITE_REORDER)) {
14361 tp->write32_tx_mbox = tg3_write32_tx_mbox;
14362 if (tg3_flag(tp, MBOX_WRITE_REORDER))
14363 tp->write32_rx_mbox = tg3_write_flush_reg32;
14366 if (tg3_flag(tp, ICH_WORKAROUND)) {
14367 tp->read32 = tg3_read_indirect_reg32;
14368 tp->write32 = tg3_write_indirect_reg32;
14369 tp->read32_mbox = tg3_read_indirect_mbox;
14370 tp->write32_mbox = tg3_write_indirect_mbox;
14371 tp->write32_tx_mbox = tg3_write_indirect_mbox;
14372 tp->write32_rx_mbox = tg3_write_indirect_mbox;
14377 pci_read_config_word(tp->pdev, PCI_COMMAND, &pci_cmd);
14378 pci_cmd &= ~PCI_COMMAND_MEMORY;
14379 pci_write_config_word(tp->pdev, PCI_COMMAND, pci_cmd);
14381 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
14382 tp->read32_mbox = tg3_read32_mbox_5906;
14383 tp->write32_mbox = tg3_write32_mbox_5906;
14384 tp->write32_tx_mbox = tg3_write32_mbox_5906;
14385 tp->write32_rx_mbox = tg3_write32_mbox_5906;
14388 if (tp->write32 == tg3_write_indirect_reg32 ||
14389 (tg3_flag(tp, PCIX_MODE) &&
14390 (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
14391 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701)))
14392 tg3_flag_set(tp, SRAM_USE_CONFIG);
14394 /* The memory arbiter has to be enabled in order for SRAM accesses
14395 * to succeed. Normally on powerup the tg3 chip firmware will make
14396 * sure it is enabled, but other entities such as system netboot
14397 * code might disable it.
14399 val = tr32(MEMARB_MODE);
14400 tw32(MEMARB_MODE, val | MEMARB_MODE_ENABLE);
14402 tp->pci_fn = PCI_FUNC(tp->pdev->devfn) & 3;
14403 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704 ||
14404 tg3_flag(tp, 5780_CLASS)) {
14405 if (tg3_flag(tp, PCIX_MODE)) {
14406 pci_read_config_dword(tp->pdev,
14407 tp->pcix_cap + PCI_X_STATUS,
14409 tp->pci_fn = val & 0x7;
14411 } else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717) {
14412 tg3_read_mem(tp, NIC_SRAM_CPMU_STATUS, &val);
14413 if ((val & NIC_SRAM_CPMUSTAT_SIG_MSK) ==
14414 NIC_SRAM_CPMUSTAT_SIG) {
14415 tp->pci_fn = val & TG3_CPMU_STATUS_FMSK_5717;
14416 tp->pci_fn = tp->pci_fn ? 1 : 0;
14418 } else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5719 ||
14419 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5720) {
14420 tg3_read_mem(tp, NIC_SRAM_CPMU_STATUS, &val);
14421 if ((val & NIC_SRAM_CPMUSTAT_SIG_MSK) ==
14422 NIC_SRAM_CPMUSTAT_SIG) {
14423 tp->pci_fn = (val & TG3_CPMU_STATUS_FMSK_5719) >>
14424 TG3_CPMU_STATUS_FSHFT_5719;
14428 /* Get eeprom hw config before calling tg3_set_power_state().
14429 * In particular, the TG3_FLAG_IS_NIC flag must be
14430 * determined before calling tg3_set_power_state() so that
14431 * we know whether or not to switch out of Vaux power.
14432 * When the flag is set, it means that GPIO1 is used for eeprom
14433 * write protect and also implies that it is a LOM where GPIOs
14434 * are not used to switch power.
14436 tg3_get_eeprom_hw_cfg(tp);
14438 if (tp->fw_needed && tg3_flag(tp, ENABLE_ASF)) {
14439 tg3_flag_clear(tp, TSO_CAPABLE);
14440 tg3_flag_clear(tp, TSO_BUG);
14441 tp->fw_needed = NULL;
14444 if (tg3_flag(tp, ENABLE_APE)) {
14445 /* Allow reads and writes to the
14446 * APE register and memory space.
14448 pci_state_reg |= PCISTATE_ALLOW_APE_CTLSPC_WR |
14449 PCISTATE_ALLOW_APE_SHMEM_WR |
14450 PCISTATE_ALLOW_APE_PSPACE_WR;
14451 pci_write_config_dword(tp->pdev, TG3PCI_PCISTATE,
14454 tg3_ape_lock_init(tp);
14457 /* Set up tp->grc_local_ctrl before calling
14458 * tg3_pwrsrc_switch_to_vmain(). GPIO1 driven high
14459 * will bring 5700's external PHY out of reset.
14460 * It is also used as eeprom write protect on LOMs.
14462 tp->grc_local_ctrl = GRC_LCLCTRL_INT_ON_ATTN | GRC_LCLCTRL_AUTO_SEEPROM;
14463 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
14464 tg3_flag(tp, EEPROM_WRITE_PROT))
14465 tp->grc_local_ctrl |= (GRC_LCLCTRL_GPIO_OE1 |
14466 GRC_LCLCTRL_GPIO_OUTPUT1);
14467 /* Unused GPIO3 must be driven as output on 5752 because there
14468 * are no pull-up resistors on unused GPIO pins.
14470 else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5752)
14471 tp->grc_local_ctrl |= GRC_LCLCTRL_GPIO_OE3;
14473 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5755 ||
14474 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57780 ||
14475 tg3_flag(tp, 57765_CLASS))
14476 tp->grc_local_ctrl |= GRC_LCLCTRL_GPIO_UART_SEL;
14478 if (tp->pdev->device == PCI_DEVICE_ID_TIGON3_5761 ||
14479 tp->pdev->device == TG3PCI_DEVICE_TIGON3_5761S) {
14480 /* Turn off the debug UART. */
14481 tp->grc_local_ctrl |= GRC_LCLCTRL_GPIO_UART_SEL;
14482 if (tg3_flag(tp, IS_NIC))
14483 /* Keep VMain power. */
14484 tp->grc_local_ctrl |= GRC_LCLCTRL_GPIO_OE0 |
14485 GRC_LCLCTRL_GPIO_OUTPUT0;
14488 /* Switch out of Vaux if it is a NIC */
14489 tg3_pwrsrc_switch_to_vmain(tp);
14491 /* Derive initial jumbo mode from MTU assigned in
14492 * ether_setup() via the alloc_etherdev() call
14494 if (tp->dev->mtu > ETH_DATA_LEN && !tg3_flag(tp, 5780_CLASS))
14495 tg3_flag_set(tp, JUMBO_RING_ENABLE);
14497 /* Determine WakeOnLan speed to use. */
14498 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
14499 tp->pci_chip_rev_id == CHIPREV_ID_5701_A0 ||
14500 tp->pci_chip_rev_id == CHIPREV_ID_5701_B0 ||
14501 tp->pci_chip_rev_id == CHIPREV_ID_5701_B2) {
14502 tg3_flag_clear(tp, WOL_SPEED_100MB);
14504 tg3_flag_set(tp, WOL_SPEED_100MB);
14507 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906)
14508 tp->phy_flags |= TG3_PHYFLG_IS_FET;
14510 /* A few boards don't want Ethernet@WireSpeed phy feature */
14511 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
14512 (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705 &&
14513 (tp->pci_chip_rev_id != CHIPREV_ID_5705_A0) &&
14514 (tp->pci_chip_rev_id != CHIPREV_ID_5705_A1)) ||
14515 (tp->phy_flags & TG3_PHYFLG_IS_FET) ||
14516 (tp->phy_flags & TG3_PHYFLG_ANY_SERDES))
14517 tp->phy_flags |= TG3_PHYFLG_NO_ETH_WIRE_SPEED;
14519 if (GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5703_AX ||
14520 GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5704_AX)
14521 tp->phy_flags |= TG3_PHYFLG_ADC_BUG;
14522 if (tp->pci_chip_rev_id == CHIPREV_ID_5704_A0)
14523 tp->phy_flags |= TG3_PHYFLG_5704_A0_BUG;
14525 if (tg3_flag(tp, 5705_PLUS) &&
14526 !(tp->phy_flags & TG3_PHYFLG_IS_FET) &&
14527 GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5785 &&
14528 GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_57780 &&
14529 !tg3_flag(tp, 57765_PLUS)) {
14530 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5755 ||
14531 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5787 ||
14532 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5784 ||
14533 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5761) {
14534 if (tp->pdev->device != PCI_DEVICE_ID_TIGON3_5756 &&
14535 tp->pdev->device != PCI_DEVICE_ID_TIGON3_5722)
14536 tp->phy_flags |= TG3_PHYFLG_JITTER_BUG;
14537 if (tp->pdev->device == PCI_DEVICE_ID_TIGON3_5755M)
14538 tp->phy_flags |= TG3_PHYFLG_ADJUST_TRIM;
14540 tp->phy_flags |= TG3_PHYFLG_BER_BUG;
14543 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5784 &&
14544 GET_CHIP_REV(tp->pci_chip_rev_id) != CHIPREV_5784_AX) {
14545 tp->phy_otp = tg3_read_otp_phycfg(tp);
14546 if (tp->phy_otp == 0)
14547 tp->phy_otp = TG3_OTP_DEFAULT;
14550 if (tg3_flag(tp, CPMU_PRESENT))
14551 tp->mi_mode = MAC_MI_MODE_500KHZ_CONST;
14553 tp->mi_mode = MAC_MI_MODE_BASE;
14555 tp->coalesce_mode = 0;
14556 if (GET_CHIP_REV(tp->pci_chip_rev_id) != CHIPREV_5700_AX &&
14557 GET_CHIP_REV(tp->pci_chip_rev_id) != CHIPREV_5700_BX)
14558 tp->coalesce_mode |= HOSTCC_MODE_32BYTE;
14560 /* Set these bits to enable statistics workaround. */
14561 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717 ||
14562 tp->pci_chip_rev_id == CHIPREV_ID_5719_A0 ||
14563 tp->pci_chip_rev_id == CHIPREV_ID_5720_A0) {
14564 tp->coalesce_mode |= HOSTCC_MODE_ATTN;
14565 tp->grc_mode |= GRC_MODE_IRQ_ON_FLOW_ATTN;
14568 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785 ||
14569 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57780)
14570 tg3_flag_set(tp, USE_PHYLIB);
14572 err = tg3_mdio_init(tp);
14576 /* Initialize data/descriptor byte/word swapping. */
14577 val = tr32(GRC_MODE);
14578 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5720)
14579 val &= (GRC_MODE_BYTE_SWAP_B2HRX_DATA |
14580 GRC_MODE_WORD_SWAP_B2HRX_DATA |
14581 GRC_MODE_B2HRX_ENABLE |
14582 GRC_MODE_HTX2B_ENABLE |
14583 GRC_MODE_HOST_STACKUP);
14585 val &= GRC_MODE_HOST_STACKUP;
14587 tw32(GRC_MODE, val | tp->grc_mode);
14589 tg3_switch_clocks(tp);
14591 /* Clear this out for sanity. */
14592 tw32(TG3PCI_MEM_WIN_BASE_ADDR, 0);
14594 pci_read_config_dword(tp->pdev, TG3PCI_PCISTATE,
14596 if ((pci_state_reg & PCISTATE_CONV_PCI_MODE) == 0 &&
14597 !tg3_flag(tp, PCIX_TARGET_HWBUG)) {
14598 u32 chiprevid = GET_CHIP_REV_ID(tp->misc_host_ctrl);
14600 if (chiprevid == CHIPREV_ID_5701_A0 ||
14601 chiprevid == CHIPREV_ID_5701_B0 ||
14602 chiprevid == CHIPREV_ID_5701_B2 ||
14603 chiprevid == CHIPREV_ID_5701_B5) {
14604 void __iomem *sram_base;
14606 /* Write some dummy words into the SRAM status block
14607 * area, see if it reads back correctly. If the return
14608 * value is bad, force enable the PCIX workaround.
14610 sram_base = tp->regs + NIC_SRAM_WIN_BASE + NIC_SRAM_STATS_BLK;
14612 writel(0x00000000, sram_base);
14613 writel(0x00000000, sram_base + 4);
14614 writel(0xffffffff, sram_base + 4);
14615 if (readl(sram_base) != 0x00000000)
14616 tg3_flag_set(tp, PCIX_TARGET_HWBUG);
14621 tg3_nvram_init(tp);
14623 grc_misc_cfg = tr32(GRC_MISC_CFG);
14624 grc_misc_cfg &= GRC_MISC_CFG_BOARD_ID_MASK;
14626 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705 &&
14627 (grc_misc_cfg == GRC_MISC_CFG_BOARD_ID_5788 ||
14628 grc_misc_cfg == GRC_MISC_CFG_BOARD_ID_5788M))
14629 tg3_flag_set(tp, IS_5788);
14631 if (!tg3_flag(tp, IS_5788) &&
14632 GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5700)
14633 tg3_flag_set(tp, TAGGED_STATUS);
14634 if (tg3_flag(tp, TAGGED_STATUS)) {
14635 tp->coalesce_mode |= (HOSTCC_MODE_CLRTICK_RXBD |
14636 HOSTCC_MODE_CLRTICK_TXBD);
14638 tp->misc_host_ctrl |= MISC_HOST_CTRL_TAGGED_STATUS;
14639 pci_write_config_dword(tp->pdev, TG3PCI_MISC_HOST_CTRL,
14640 tp->misc_host_ctrl);
14643 /* Preserve the APE MAC_MODE bits */
14644 if (tg3_flag(tp, ENABLE_APE))
14645 tp->mac_mode = MAC_MODE_APE_TX_EN | MAC_MODE_APE_RX_EN;
14649 /* these are limited to 10/100 only */
14650 if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703 &&
14651 (grc_misc_cfg == 0x8000 || grc_misc_cfg == 0x4000)) ||
14652 (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705 &&
14653 tp->pdev->vendor == PCI_VENDOR_ID_BROADCOM &&
14654 (tp->pdev->device == PCI_DEVICE_ID_TIGON3_5901 ||
14655 tp->pdev->device == PCI_DEVICE_ID_TIGON3_5901_2 ||
14656 tp->pdev->device == PCI_DEVICE_ID_TIGON3_5705F)) ||
14657 (tp->pdev->vendor == PCI_VENDOR_ID_BROADCOM &&
14658 (tp->pdev->device == PCI_DEVICE_ID_TIGON3_5751F ||
14659 tp->pdev->device == PCI_DEVICE_ID_TIGON3_5753F ||
14660 tp->pdev->device == PCI_DEVICE_ID_TIGON3_5787F)) ||
14661 tp->pdev->device == TG3PCI_DEVICE_TIGON3_57790 ||
14662 tp->pdev->device == TG3PCI_DEVICE_TIGON3_57791 ||
14663 tp->pdev->device == TG3PCI_DEVICE_TIGON3_57795 ||
14664 (tp->phy_flags & TG3_PHYFLG_IS_FET))
14665 tp->phy_flags |= TG3_PHYFLG_10_100_ONLY;
14667 err = tg3_phy_probe(tp);
14669 dev_err(&tp->pdev->dev, "phy probe failed, err %d\n", err);
14670 /* ... but do not return immediately ... */
14675 tg3_read_fw_ver(tp);
14677 if (tp->phy_flags & TG3_PHYFLG_PHY_SERDES) {
14678 tp->phy_flags &= ~TG3_PHYFLG_USE_MI_INTERRUPT;
14680 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700)
14681 tp->phy_flags |= TG3_PHYFLG_USE_MI_INTERRUPT;
14683 tp->phy_flags &= ~TG3_PHYFLG_USE_MI_INTERRUPT;
14686 /* 5700 {AX,BX} chips have a broken status block link
14687 * change bit implementation, so we must use the
14688 * status register in those cases.
14690 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700)
14691 tg3_flag_set(tp, USE_LINKCHG_REG);
14693 tg3_flag_clear(tp, USE_LINKCHG_REG);
14695 /* The led_ctrl is set during tg3_phy_probe, here we might
14696 * have to force the link status polling mechanism based
14697 * upon subsystem IDs.
14699 if (tp->pdev->subsystem_vendor == PCI_VENDOR_ID_DELL &&
14700 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701 &&
14701 !(tp->phy_flags & TG3_PHYFLG_PHY_SERDES)) {
14702 tp->phy_flags |= TG3_PHYFLG_USE_MI_INTERRUPT;
14703 tg3_flag_set(tp, USE_LINKCHG_REG);
14706 /* For all SERDES we poll the MAC status register. */
14707 if (tp->phy_flags & TG3_PHYFLG_PHY_SERDES)
14708 tg3_flag_set(tp, POLL_SERDES);
14710 tg3_flag_clear(tp, POLL_SERDES);
14712 tp->rx_offset = NET_SKB_PAD + NET_IP_ALIGN;
14713 tp->rx_copy_thresh = TG3_RX_COPY_THRESHOLD;
14714 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701 &&
14715 tg3_flag(tp, PCIX_MODE)) {
14716 tp->rx_offset = NET_SKB_PAD;
14717 #ifndef CONFIG_HAVE_EFFICIENT_UNALIGNED_ACCESS
14718 tp->rx_copy_thresh = ~(u16)0;
14722 tp->rx_std_ring_mask = TG3_RX_STD_RING_SIZE(tp) - 1;
14723 tp->rx_jmb_ring_mask = TG3_RX_JMB_RING_SIZE(tp) - 1;
14724 tp->rx_ret_ring_mask = tg3_rx_ret_ring_size(tp) - 1;
14726 tp->rx_std_max_post = tp->rx_std_ring_mask + 1;
14728 /* Increment the rx prod index on the rx std ring by at most
14729 * 8 for these chips to workaround hw errata.
14731 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5750 ||
14732 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5752 ||
14733 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5755)
14734 tp->rx_std_max_post = 8;
14736 if (tg3_flag(tp, ASPM_WORKAROUND))
14737 tp->pwrmgmt_thresh = tr32(PCIE_PWR_MGMT_THRESH) &
14738 PCIE_PWR_MGMT_L1_THRESH_MSK;
14743 #ifdef CONFIG_SPARC
14744 static int __devinit tg3_get_macaddr_sparc(struct tg3 *tp)
14746 struct net_device *dev = tp->dev;
14747 struct pci_dev *pdev = tp->pdev;
14748 struct device_node *dp = pci_device_to_OF_node(pdev);
14749 const unsigned char *addr;
14752 addr = of_get_property(dp, "local-mac-address", &len);
14753 if (addr && len == 6) {
14754 memcpy(dev->dev_addr, addr, 6);
14755 memcpy(dev->perm_addr, dev->dev_addr, 6);
14761 static int __devinit tg3_get_default_macaddr_sparc(struct tg3 *tp)
14763 struct net_device *dev = tp->dev;
14765 memcpy(dev->dev_addr, idprom->id_ethaddr, 6);
14766 memcpy(dev->perm_addr, idprom->id_ethaddr, 6);
14771 static int __devinit tg3_get_device_address(struct tg3 *tp)
14773 struct net_device *dev = tp->dev;
14774 u32 hi, lo, mac_offset;
14777 #ifdef CONFIG_SPARC
14778 if (!tg3_get_macaddr_sparc(tp))
14783 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704 ||
14784 tg3_flag(tp, 5780_CLASS)) {
14785 if (tr32(TG3PCI_DUAL_MAC_CTRL) & DUAL_MAC_CTRL_ID)
14787 if (tg3_nvram_lock(tp))
14788 tw32_f(NVRAM_CMD, NVRAM_CMD_RESET);
14790 tg3_nvram_unlock(tp);
14791 } else if (tg3_flag(tp, 5717_PLUS)) {
14792 if (tp->pci_fn & 1)
14794 if (tp->pci_fn > 1)
14795 mac_offset += 0x18c;
14796 } else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906)
14799 /* First try to get it from MAC address mailbox. */
14800 tg3_read_mem(tp, NIC_SRAM_MAC_ADDR_HIGH_MBOX, &hi);
14801 if ((hi >> 16) == 0x484b) {
14802 dev->dev_addr[0] = (hi >> 8) & 0xff;
14803 dev->dev_addr[1] = (hi >> 0) & 0xff;
14805 tg3_read_mem(tp, NIC_SRAM_MAC_ADDR_LOW_MBOX, &lo);
14806 dev->dev_addr[2] = (lo >> 24) & 0xff;
14807 dev->dev_addr[3] = (lo >> 16) & 0xff;
14808 dev->dev_addr[4] = (lo >> 8) & 0xff;
14809 dev->dev_addr[5] = (lo >> 0) & 0xff;
14811 /* Some old bootcode may report a 0 MAC address in SRAM */
14812 addr_ok = is_valid_ether_addr(&dev->dev_addr[0]);
14815 /* Next, try NVRAM. */
14816 if (!tg3_flag(tp, NO_NVRAM) &&
14817 !tg3_nvram_read_be32(tp, mac_offset + 0, &hi) &&
14818 !tg3_nvram_read_be32(tp, mac_offset + 4, &lo)) {
14819 memcpy(&dev->dev_addr[0], ((char *)&hi) + 2, 2);
14820 memcpy(&dev->dev_addr[2], (char *)&lo, sizeof(lo));
14822 /* Finally just fetch it out of the MAC control regs. */
14824 hi = tr32(MAC_ADDR_0_HIGH);
14825 lo = tr32(MAC_ADDR_0_LOW);
14827 dev->dev_addr[5] = lo & 0xff;
14828 dev->dev_addr[4] = (lo >> 8) & 0xff;
14829 dev->dev_addr[3] = (lo >> 16) & 0xff;
14830 dev->dev_addr[2] = (lo >> 24) & 0xff;
14831 dev->dev_addr[1] = hi & 0xff;
14832 dev->dev_addr[0] = (hi >> 8) & 0xff;
14836 if (!is_valid_ether_addr(&dev->dev_addr[0])) {
14837 #ifdef CONFIG_SPARC
14838 if (!tg3_get_default_macaddr_sparc(tp))
14843 memcpy(dev->perm_addr, dev->dev_addr, dev->addr_len);
14847 #define BOUNDARY_SINGLE_CACHELINE 1
14848 #define BOUNDARY_MULTI_CACHELINE 2
14850 static u32 __devinit tg3_calc_dma_bndry(struct tg3 *tp, u32 val)
14852 int cacheline_size;
14856 pci_read_config_byte(tp->pdev, PCI_CACHE_LINE_SIZE, &byte);
14858 cacheline_size = 1024;
14860 cacheline_size = (int) byte * 4;
14862 /* On 5703 and later chips, the boundary bits have no
14865 if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5700 &&
14866 GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5701 &&
14867 !tg3_flag(tp, PCI_EXPRESS))
14870 #if defined(CONFIG_PPC64) || defined(CONFIG_IA64) || defined(CONFIG_PARISC)
14871 goal = BOUNDARY_MULTI_CACHELINE;
14873 #if defined(CONFIG_SPARC64) || defined(CONFIG_ALPHA)
14874 goal = BOUNDARY_SINGLE_CACHELINE;
14880 if (tg3_flag(tp, 57765_PLUS)) {
14881 val = goal ? 0 : DMA_RWCTRL_DIS_CACHE_ALIGNMENT;
14888 /* PCI controllers on most RISC systems tend to disconnect
14889 * when a device tries to burst across a cache-line boundary.
14890 * Therefore, letting tg3 do so just wastes PCI bandwidth.
14892 * Unfortunately, for PCI-E there are only limited
14893 * write-side controls for this, and thus for reads
14894 * we will still get the disconnects. We'll also waste
14895 * these PCI cycles for both read and write for chips
14896 * other than 5700 and 5701 which do not implement the
14899 if (tg3_flag(tp, PCIX_MODE) && !tg3_flag(tp, PCI_EXPRESS)) {
14900 switch (cacheline_size) {
14905 if (goal == BOUNDARY_SINGLE_CACHELINE) {
14906 val |= (DMA_RWCTRL_READ_BNDRY_128_PCIX |
14907 DMA_RWCTRL_WRITE_BNDRY_128_PCIX);
14909 val |= (DMA_RWCTRL_READ_BNDRY_384_PCIX |
14910 DMA_RWCTRL_WRITE_BNDRY_384_PCIX);
14915 val |= (DMA_RWCTRL_READ_BNDRY_256_PCIX |
14916 DMA_RWCTRL_WRITE_BNDRY_256_PCIX);
14920 val |= (DMA_RWCTRL_READ_BNDRY_384_PCIX |
14921 DMA_RWCTRL_WRITE_BNDRY_384_PCIX);
14924 } else if (tg3_flag(tp, PCI_EXPRESS)) {
14925 switch (cacheline_size) {
14929 if (goal == BOUNDARY_SINGLE_CACHELINE) {
14930 val &= ~DMA_RWCTRL_WRITE_BNDRY_DISAB_PCIE;
14931 val |= DMA_RWCTRL_WRITE_BNDRY_64_PCIE;
14937 val &= ~DMA_RWCTRL_WRITE_BNDRY_DISAB_PCIE;
14938 val |= DMA_RWCTRL_WRITE_BNDRY_128_PCIE;
14942 switch (cacheline_size) {
14944 if (goal == BOUNDARY_SINGLE_CACHELINE) {
14945 val |= (DMA_RWCTRL_READ_BNDRY_16 |
14946 DMA_RWCTRL_WRITE_BNDRY_16);
14951 if (goal == BOUNDARY_SINGLE_CACHELINE) {
14952 val |= (DMA_RWCTRL_READ_BNDRY_32 |
14953 DMA_RWCTRL_WRITE_BNDRY_32);
14958 if (goal == BOUNDARY_SINGLE_CACHELINE) {
14959 val |= (DMA_RWCTRL_READ_BNDRY_64 |
14960 DMA_RWCTRL_WRITE_BNDRY_64);
14965 if (goal == BOUNDARY_SINGLE_CACHELINE) {
14966 val |= (DMA_RWCTRL_READ_BNDRY_128 |
14967 DMA_RWCTRL_WRITE_BNDRY_128);
14972 val |= (DMA_RWCTRL_READ_BNDRY_256 |
14973 DMA_RWCTRL_WRITE_BNDRY_256);
14976 val |= (DMA_RWCTRL_READ_BNDRY_512 |
14977 DMA_RWCTRL_WRITE_BNDRY_512);
14981 val |= (DMA_RWCTRL_READ_BNDRY_1024 |
14982 DMA_RWCTRL_WRITE_BNDRY_1024);
14991 static int __devinit tg3_do_test_dma(struct tg3 *tp, u32 *buf, dma_addr_t buf_dma, int size, int to_device)
14993 struct tg3_internal_buffer_desc test_desc;
14994 u32 sram_dma_descs;
14997 sram_dma_descs = NIC_SRAM_DMA_DESC_POOL_BASE;
14999 tw32(FTQ_RCVBD_COMP_FIFO_ENQDEQ, 0);
15000 tw32(FTQ_RCVDATA_COMP_FIFO_ENQDEQ, 0);
15001 tw32(RDMAC_STATUS, 0);
15002 tw32(WDMAC_STATUS, 0);
15004 tw32(BUFMGR_MODE, 0);
15005 tw32(FTQ_RESET, 0);
15007 test_desc.addr_hi = ((u64) buf_dma) >> 32;
15008 test_desc.addr_lo = buf_dma & 0xffffffff;
15009 test_desc.nic_mbuf = 0x00002100;
15010 test_desc.len = size;
15013 * HP ZX1 was seeing test failures for 5701 cards running at 33Mhz
15014 * the *second* time the tg3 driver was getting loaded after an
15017 * Broadcom tells me:
15018 * ...the DMA engine is connected to the GRC block and a DMA
15019 * reset may affect the GRC block in some unpredictable way...
15020 * The behavior of resets to individual blocks has not been tested.
15022 * Broadcom noted the GRC reset will also reset all sub-components.
15025 test_desc.cqid_sqid = (13 << 8) | 2;
15027 tw32_f(RDMAC_MODE, RDMAC_MODE_ENABLE);
15030 test_desc.cqid_sqid = (16 << 8) | 7;
15032 tw32_f(WDMAC_MODE, WDMAC_MODE_ENABLE);
15035 test_desc.flags = 0x00000005;
15037 for (i = 0; i < (sizeof(test_desc) / sizeof(u32)); i++) {
15040 val = *(((u32 *)&test_desc) + i);
15041 pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_BASE_ADDR,
15042 sram_dma_descs + (i * sizeof(u32)));
15043 pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_DATA, val);
15045 pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_BASE_ADDR, 0);
15048 tw32(FTQ_DMA_HIGH_READ_FIFO_ENQDEQ, sram_dma_descs);
15050 tw32(FTQ_DMA_HIGH_WRITE_FIFO_ENQDEQ, sram_dma_descs);
15053 for (i = 0; i < 40; i++) {
15057 val = tr32(FTQ_RCVBD_COMP_FIFO_ENQDEQ);
15059 val = tr32(FTQ_RCVDATA_COMP_FIFO_ENQDEQ);
15060 if ((val & 0xffff) == sram_dma_descs) {
15071 #define TEST_BUFFER_SIZE 0x2000
15073 static DEFINE_PCI_DEVICE_TABLE(tg3_dma_wait_state_chipsets) = {
15074 { PCI_DEVICE(PCI_VENDOR_ID_APPLE, PCI_DEVICE_ID_APPLE_UNI_N_PCI15) },
15078 static int __devinit tg3_test_dma(struct tg3 *tp)
15080 dma_addr_t buf_dma;
15081 u32 *buf, saved_dma_rwctrl;
15084 buf = dma_alloc_coherent(&tp->pdev->dev, TEST_BUFFER_SIZE,
15085 &buf_dma, GFP_KERNEL);
15091 tp->dma_rwctrl = ((0x7 << DMA_RWCTRL_PCI_WRITE_CMD_SHIFT) |
15092 (0x6 << DMA_RWCTRL_PCI_READ_CMD_SHIFT));
15094 tp->dma_rwctrl = tg3_calc_dma_bndry(tp, tp->dma_rwctrl);
15096 if (tg3_flag(tp, 57765_PLUS))
15099 if (tg3_flag(tp, PCI_EXPRESS)) {
15100 /* DMA read watermark not used on PCIE */
15101 tp->dma_rwctrl |= 0x00180000;
15102 } else if (!tg3_flag(tp, PCIX_MODE)) {
15103 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705 ||
15104 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5750)
15105 tp->dma_rwctrl |= 0x003f0000;
15107 tp->dma_rwctrl |= 0x003f000f;
15109 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703 ||
15110 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704) {
15111 u32 ccval = (tr32(TG3PCI_CLOCK_CTRL) & 0x1f);
15112 u32 read_water = 0x7;
15114 /* If the 5704 is behind the EPB bridge, we can
15115 * do the less restrictive ONE_DMA workaround for
15116 * better performance.
15118 if (tg3_flag(tp, 40BIT_DMA_BUG) &&
15119 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704)
15120 tp->dma_rwctrl |= 0x8000;
15121 else if (ccval == 0x6 || ccval == 0x7)
15122 tp->dma_rwctrl |= DMA_RWCTRL_ONE_DMA;
15124 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703)
15126 /* Set bit 23 to enable PCIX hw bug fix */
15128 (read_water << DMA_RWCTRL_READ_WATER_SHIFT) |
15129 (0x3 << DMA_RWCTRL_WRITE_WATER_SHIFT) |
15131 } else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5780) {
15132 /* 5780 always in PCIX mode */
15133 tp->dma_rwctrl |= 0x00144000;
15134 } else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5714) {
15135 /* 5714 always in PCIX mode */
15136 tp->dma_rwctrl |= 0x00148000;
15138 tp->dma_rwctrl |= 0x001b000f;
15142 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703 ||
15143 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704)
15144 tp->dma_rwctrl &= 0xfffffff0;
15146 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
15147 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701) {
15148 /* Remove this if it causes problems for some boards. */
15149 tp->dma_rwctrl |= DMA_RWCTRL_USE_MEM_READ_MULT;
15151 /* On 5700/5701 chips, we need to set this bit.
15152 * Otherwise the chip will issue cacheline transactions
15153 * to streamable DMA memory with not all the byte
15154 * enables turned on. This is an error on several
15155 * RISC PCI controllers, in particular sparc64.
15157 * On 5703/5704 chips, this bit has been reassigned
15158 * a different meaning. In particular, it is used
15159 * on those chips to enable a PCI-X workaround.
15161 tp->dma_rwctrl |= DMA_RWCTRL_ASSERT_ALL_BE;
15164 tw32(TG3PCI_DMA_RW_CTRL, tp->dma_rwctrl);
15167 /* Unneeded, already done by tg3_get_invariants. */
15168 tg3_switch_clocks(tp);
15171 if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5700 &&
15172 GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5701)
15175 /* It is best to perform DMA test with maximum write burst size
15176 * to expose the 5700/5701 write DMA bug.
15178 saved_dma_rwctrl = tp->dma_rwctrl;
15179 tp->dma_rwctrl &= ~DMA_RWCTRL_WRITE_BNDRY_MASK;
15180 tw32(TG3PCI_DMA_RW_CTRL, tp->dma_rwctrl);
15185 for (i = 0; i < TEST_BUFFER_SIZE / sizeof(u32); i++)
15188 /* Send the buffer to the chip. */
15189 ret = tg3_do_test_dma(tp, buf, buf_dma, TEST_BUFFER_SIZE, 1);
15191 dev_err(&tp->pdev->dev,
15192 "%s: Buffer write failed. err = %d\n",
15198 /* validate data reached card RAM correctly. */
15199 for (i = 0; i < TEST_BUFFER_SIZE / sizeof(u32); i++) {
15201 tg3_read_mem(tp, 0x2100 + (i*4), &val);
15202 if (le32_to_cpu(val) != p[i]) {
15203 dev_err(&tp->pdev->dev,
15204 "%s: Buffer corrupted on device! "
15205 "(%d != %d)\n", __func__, val, i);
15206 /* ret = -ENODEV here? */
15211 /* Now read it back. */
15212 ret = tg3_do_test_dma(tp, buf, buf_dma, TEST_BUFFER_SIZE, 0);
15214 dev_err(&tp->pdev->dev, "%s: Buffer read failed. "
15215 "err = %d\n", __func__, ret);
15220 for (i = 0; i < TEST_BUFFER_SIZE / sizeof(u32); i++) {
15224 if ((tp->dma_rwctrl & DMA_RWCTRL_WRITE_BNDRY_MASK) !=
15225 DMA_RWCTRL_WRITE_BNDRY_16) {
15226 tp->dma_rwctrl &= ~DMA_RWCTRL_WRITE_BNDRY_MASK;
15227 tp->dma_rwctrl |= DMA_RWCTRL_WRITE_BNDRY_16;
15228 tw32(TG3PCI_DMA_RW_CTRL, tp->dma_rwctrl);
15231 dev_err(&tp->pdev->dev,
15232 "%s: Buffer corrupted on read back! "
15233 "(%d != %d)\n", __func__, p[i], i);
15239 if (i == (TEST_BUFFER_SIZE / sizeof(u32))) {
15245 if ((tp->dma_rwctrl & DMA_RWCTRL_WRITE_BNDRY_MASK) !=
15246 DMA_RWCTRL_WRITE_BNDRY_16) {
15247 /* DMA test passed without adjusting DMA boundary,
15248 * now look for chipsets that are known to expose the
15249 * DMA bug without failing the test.
15251 if (pci_dev_present(tg3_dma_wait_state_chipsets)) {
15252 tp->dma_rwctrl &= ~DMA_RWCTRL_WRITE_BNDRY_MASK;
15253 tp->dma_rwctrl |= DMA_RWCTRL_WRITE_BNDRY_16;
15255 /* Safe to use the calculated DMA boundary. */
15256 tp->dma_rwctrl = saved_dma_rwctrl;
15259 tw32(TG3PCI_DMA_RW_CTRL, tp->dma_rwctrl);
15263 dma_free_coherent(&tp->pdev->dev, TEST_BUFFER_SIZE, buf, buf_dma);
15268 static void __devinit tg3_init_bufmgr_config(struct tg3 *tp)
15270 if (tg3_flag(tp, 57765_PLUS)) {
15271 tp->bufmgr_config.mbuf_read_dma_low_water =
15272 DEFAULT_MB_RDMA_LOW_WATER_5705;
15273 tp->bufmgr_config.mbuf_mac_rx_low_water =
15274 DEFAULT_MB_MACRX_LOW_WATER_57765;
15275 tp->bufmgr_config.mbuf_high_water =
15276 DEFAULT_MB_HIGH_WATER_57765;
15278 tp->bufmgr_config.mbuf_read_dma_low_water_jumbo =
15279 DEFAULT_MB_RDMA_LOW_WATER_5705;
15280 tp->bufmgr_config.mbuf_mac_rx_low_water_jumbo =
15281 DEFAULT_MB_MACRX_LOW_WATER_JUMBO_57765;
15282 tp->bufmgr_config.mbuf_high_water_jumbo =
15283 DEFAULT_MB_HIGH_WATER_JUMBO_57765;
15284 } else if (tg3_flag(tp, 5705_PLUS)) {
15285 tp->bufmgr_config.mbuf_read_dma_low_water =
15286 DEFAULT_MB_RDMA_LOW_WATER_5705;
15287 tp->bufmgr_config.mbuf_mac_rx_low_water =
15288 DEFAULT_MB_MACRX_LOW_WATER_5705;
15289 tp->bufmgr_config.mbuf_high_water =
15290 DEFAULT_MB_HIGH_WATER_5705;
15291 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
15292 tp->bufmgr_config.mbuf_mac_rx_low_water =
15293 DEFAULT_MB_MACRX_LOW_WATER_5906;
15294 tp->bufmgr_config.mbuf_high_water =
15295 DEFAULT_MB_HIGH_WATER_5906;
15298 tp->bufmgr_config.mbuf_read_dma_low_water_jumbo =
15299 DEFAULT_MB_RDMA_LOW_WATER_JUMBO_5780;
15300 tp->bufmgr_config.mbuf_mac_rx_low_water_jumbo =
15301 DEFAULT_MB_MACRX_LOW_WATER_JUMBO_5780;
15302 tp->bufmgr_config.mbuf_high_water_jumbo =
15303 DEFAULT_MB_HIGH_WATER_JUMBO_5780;
15305 tp->bufmgr_config.mbuf_read_dma_low_water =
15306 DEFAULT_MB_RDMA_LOW_WATER;
15307 tp->bufmgr_config.mbuf_mac_rx_low_water =
15308 DEFAULT_MB_MACRX_LOW_WATER;
15309 tp->bufmgr_config.mbuf_high_water =
15310 DEFAULT_MB_HIGH_WATER;
15312 tp->bufmgr_config.mbuf_read_dma_low_water_jumbo =
15313 DEFAULT_MB_RDMA_LOW_WATER_JUMBO;
15314 tp->bufmgr_config.mbuf_mac_rx_low_water_jumbo =
15315 DEFAULT_MB_MACRX_LOW_WATER_JUMBO;
15316 tp->bufmgr_config.mbuf_high_water_jumbo =
15317 DEFAULT_MB_HIGH_WATER_JUMBO;
15320 tp->bufmgr_config.dma_low_water = DEFAULT_DMA_LOW_WATER;
15321 tp->bufmgr_config.dma_high_water = DEFAULT_DMA_HIGH_WATER;
15324 static char * __devinit tg3_phy_string(struct tg3 *tp)
15326 switch (tp->phy_id & TG3_PHY_ID_MASK) {
15327 case TG3_PHY_ID_BCM5400: return "5400";
15328 case TG3_PHY_ID_BCM5401: return "5401";
15329 case TG3_PHY_ID_BCM5411: return "5411";
15330 case TG3_PHY_ID_BCM5701: return "5701";
15331 case TG3_PHY_ID_BCM5703: return "5703";
15332 case TG3_PHY_ID_BCM5704: return "5704";
15333 case TG3_PHY_ID_BCM5705: return "5705";
15334 case TG3_PHY_ID_BCM5750: return "5750";
15335 case TG3_PHY_ID_BCM5752: return "5752";
15336 case TG3_PHY_ID_BCM5714: return "5714";
15337 case TG3_PHY_ID_BCM5780: return "5780";
15338 case TG3_PHY_ID_BCM5755: return "5755";
15339 case TG3_PHY_ID_BCM5787: return "5787";
15340 case TG3_PHY_ID_BCM5784: return "5784";
15341 case TG3_PHY_ID_BCM5756: return "5722/5756";
15342 case TG3_PHY_ID_BCM5906: return "5906";
15343 case TG3_PHY_ID_BCM5761: return "5761";
15344 case TG3_PHY_ID_BCM5718C: return "5718C";
15345 case TG3_PHY_ID_BCM5718S: return "5718S";
15346 case TG3_PHY_ID_BCM57765: return "57765";
15347 case TG3_PHY_ID_BCM5719C: return "5719C";
15348 case TG3_PHY_ID_BCM5720C: return "5720C";
15349 case TG3_PHY_ID_BCM8002: return "8002/serdes";
15350 case 0: return "serdes";
15351 default: return "unknown";
15355 static char * __devinit tg3_bus_string(struct tg3 *tp, char *str)
15357 if (tg3_flag(tp, PCI_EXPRESS)) {
15358 strcpy(str, "PCI Express");
15360 } else if (tg3_flag(tp, PCIX_MODE)) {
15361 u32 clock_ctrl = tr32(TG3PCI_CLOCK_CTRL) & 0x1f;
15363 strcpy(str, "PCIX:");
15365 if ((clock_ctrl == 7) ||
15366 ((tr32(GRC_MISC_CFG) & GRC_MISC_CFG_BOARD_ID_MASK) ==
15367 GRC_MISC_CFG_BOARD_ID_5704CIOBE))
15368 strcat(str, "133MHz");
15369 else if (clock_ctrl == 0)
15370 strcat(str, "33MHz");
15371 else if (clock_ctrl == 2)
15372 strcat(str, "50MHz");
15373 else if (clock_ctrl == 4)
15374 strcat(str, "66MHz");
15375 else if (clock_ctrl == 6)
15376 strcat(str, "100MHz");
15378 strcpy(str, "PCI:");
15379 if (tg3_flag(tp, PCI_HIGH_SPEED))
15380 strcat(str, "66MHz");
15382 strcat(str, "33MHz");
15384 if (tg3_flag(tp, PCI_32BIT))
15385 strcat(str, ":32-bit");
15387 strcat(str, ":64-bit");
15391 static void __devinit tg3_init_coal(struct tg3 *tp)
15393 struct ethtool_coalesce *ec = &tp->coal;
15395 memset(ec, 0, sizeof(*ec));
15396 ec->cmd = ETHTOOL_GCOALESCE;
15397 ec->rx_coalesce_usecs = LOW_RXCOL_TICKS;
15398 ec->tx_coalesce_usecs = LOW_TXCOL_TICKS;
15399 ec->rx_max_coalesced_frames = LOW_RXMAX_FRAMES;
15400 ec->tx_max_coalesced_frames = LOW_TXMAX_FRAMES;
15401 ec->rx_coalesce_usecs_irq = DEFAULT_RXCOAL_TICK_INT;
15402 ec->tx_coalesce_usecs_irq = DEFAULT_TXCOAL_TICK_INT;
15403 ec->rx_max_coalesced_frames_irq = DEFAULT_RXCOAL_MAXF_INT;
15404 ec->tx_max_coalesced_frames_irq = DEFAULT_TXCOAL_MAXF_INT;
15405 ec->stats_block_coalesce_usecs = DEFAULT_STAT_COAL_TICKS;
15407 if (tp->coalesce_mode & (HOSTCC_MODE_CLRTICK_RXBD |
15408 HOSTCC_MODE_CLRTICK_TXBD)) {
15409 ec->rx_coalesce_usecs = LOW_RXCOL_TICKS_CLRTCKS;
15410 ec->rx_coalesce_usecs_irq = DEFAULT_RXCOAL_TICK_INT_CLRTCKS;
15411 ec->tx_coalesce_usecs = LOW_TXCOL_TICKS_CLRTCKS;
15412 ec->tx_coalesce_usecs_irq = DEFAULT_TXCOAL_TICK_INT_CLRTCKS;
15415 if (tg3_flag(tp, 5705_PLUS)) {
15416 ec->rx_coalesce_usecs_irq = 0;
15417 ec->tx_coalesce_usecs_irq = 0;
15418 ec->stats_block_coalesce_usecs = 0;
15422 static int __devinit tg3_init_one(struct pci_dev *pdev,
15423 const struct pci_device_id *ent)
15425 struct net_device *dev;
15427 int i, err, pm_cap;
15428 u32 sndmbx, rcvmbx, intmbx;
15430 u64 dma_mask, persist_dma_mask;
15431 netdev_features_t features = 0;
15433 printk_once(KERN_INFO "%s\n", version);
15435 err = pci_enable_device(pdev);
15437 dev_err(&pdev->dev, "Cannot enable PCI device, aborting\n");
15441 err = pci_request_regions(pdev, DRV_MODULE_NAME);
15443 dev_err(&pdev->dev, "Cannot obtain PCI resources, aborting\n");
15444 goto err_out_disable_pdev;
15447 pci_set_master(pdev);
15449 /* Find power-management capability. */
15450 pm_cap = pci_find_capability(pdev, PCI_CAP_ID_PM);
15452 dev_err(&pdev->dev,
15453 "Cannot find Power Management capability, aborting\n");
15455 goto err_out_free_res;
15458 err = pci_set_power_state(pdev, PCI_D0);
15460 dev_err(&pdev->dev, "Transition to D0 failed, aborting\n");
15461 goto err_out_free_res;
15464 dev = alloc_etherdev_mq(sizeof(*tp), TG3_IRQ_MAX_VECS);
15467 goto err_out_power_down;
15470 SET_NETDEV_DEV(dev, &pdev->dev);
15472 tp = netdev_priv(dev);
15475 tp->pm_cap = pm_cap;
15476 tp->rx_mode = TG3_DEF_RX_MODE;
15477 tp->tx_mode = TG3_DEF_TX_MODE;
15480 tp->msg_enable = tg3_debug;
15482 tp->msg_enable = TG3_DEF_MSG_ENABLE;
15484 /* The word/byte swap controls here control register access byte
15485 * swapping. DMA data byte swapping is controlled in the GRC_MODE
15488 tp->misc_host_ctrl =
15489 MISC_HOST_CTRL_MASK_PCI_INT |
15490 MISC_HOST_CTRL_WORD_SWAP |
15491 MISC_HOST_CTRL_INDIR_ACCESS |
15492 MISC_HOST_CTRL_PCISTATE_RW;
15494 /* The NONFRM (non-frame) byte/word swap controls take effect
15495 * on descriptor entries, anything which isn't packet data.
15497 * The StrongARM chips on the board (one for tx, one for rx)
15498 * are running in big-endian mode.
15500 tp->grc_mode = (GRC_MODE_WSWAP_DATA | GRC_MODE_BSWAP_DATA |
15501 GRC_MODE_WSWAP_NONFRM_DATA);
15502 #ifdef __BIG_ENDIAN
15503 tp->grc_mode |= GRC_MODE_BSWAP_NONFRM_DATA;
15505 spin_lock_init(&tp->lock);
15506 spin_lock_init(&tp->indirect_lock);
15507 INIT_WORK(&tp->reset_task, tg3_reset_task);
15509 tp->regs = pci_ioremap_bar(pdev, BAR_0);
15511 dev_err(&pdev->dev, "Cannot map device registers, aborting\n");
15513 goto err_out_free_dev;
15516 if (tp->pdev->device == PCI_DEVICE_ID_TIGON3_5761 ||
15517 tp->pdev->device == PCI_DEVICE_ID_TIGON3_5761E ||
15518 tp->pdev->device == TG3PCI_DEVICE_TIGON3_5761S ||
15519 tp->pdev->device == TG3PCI_DEVICE_TIGON3_5761SE ||
15520 tp->pdev->device == TG3PCI_DEVICE_TIGON3_5717 ||
15521 tp->pdev->device == TG3PCI_DEVICE_TIGON3_5718 ||
15522 tp->pdev->device == TG3PCI_DEVICE_TIGON3_5719 ||
15523 tp->pdev->device == TG3PCI_DEVICE_TIGON3_5720) {
15524 tg3_flag_set(tp, ENABLE_APE);
15525 tp->aperegs = pci_ioremap_bar(pdev, BAR_2);
15526 if (!tp->aperegs) {
15527 dev_err(&pdev->dev,
15528 "Cannot map APE registers, aborting\n");
15530 goto err_out_iounmap;
15534 tp->rx_pending = TG3_DEF_RX_RING_PENDING;
15535 tp->rx_jumbo_pending = TG3_DEF_RX_JUMBO_RING_PENDING;
15537 dev->ethtool_ops = &tg3_ethtool_ops;
15538 dev->watchdog_timeo = TG3_TX_TIMEOUT;
15539 dev->netdev_ops = &tg3_netdev_ops;
15540 dev->irq = pdev->irq;
15542 err = tg3_get_invariants(tp);
15544 dev_err(&pdev->dev,
15545 "Problem fetching invariants of chip, aborting\n");
15546 goto err_out_apeunmap;
15549 /* The EPB bridge inside 5714, 5715, and 5780 and any
15550 * device behind the EPB cannot support DMA addresses > 40-bit.
15551 * On 64-bit systems with IOMMU, use 40-bit dma_mask.
15552 * On 64-bit systems without IOMMU, use 64-bit dma_mask and
15553 * do DMA address check in tg3_start_xmit().
15555 if (tg3_flag(tp, IS_5788))
15556 persist_dma_mask = dma_mask = DMA_BIT_MASK(32);
15557 else if (tg3_flag(tp, 40BIT_DMA_BUG)) {
15558 persist_dma_mask = dma_mask = DMA_BIT_MASK(40);
15559 #ifdef CONFIG_HIGHMEM
15560 dma_mask = DMA_BIT_MASK(64);
15563 persist_dma_mask = dma_mask = DMA_BIT_MASK(64);
15565 /* Configure DMA attributes. */
15566 if (dma_mask > DMA_BIT_MASK(32)) {
15567 err = pci_set_dma_mask(pdev, dma_mask);
15569 features |= NETIF_F_HIGHDMA;
15570 err = pci_set_consistent_dma_mask(pdev,
15573 dev_err(&pdev->dev, "Unable to obtain 64 bit "
15574 "DMA for consistent allocations\n");
15575 goto err_out_apeunmap;
15579 if (err || dma_mask == DMA_BIT_MASK(32)) {
15580 err = pci_set_dma_mask(pdev, DMA_BIT_MASK(32));
15582 dev_err(&pdev->dev,
15583 "No usable DMA configuration, aborting\n");
15584 goto err_out_apeunmap;
15588 tg3_init_bufmgr_config(tp);
15590 features |= NETIF_F_HW_VLAN_TX | NETIF_F_HW_VLAN_RX;
15592 /* 5700 B0 chips do not support checksumming correctly due
15593 * to hardware bugs.
15595 if (tp->pci_chip_rev_id != CHIPREV_ID_5700_B0) {
15596 features |= NETIF_F_SG | NETIF_F_IP_CSUM | NETIF_F_RXCSUM;
15598 if (tg3_flag(tp, 5755_PLUS))
15599 features |= NETIF_F_IPV6_CSUM;
15602 /* TSO is on by default on chips that support hardware TSO.
15603 * Firmware TSO on older chips gives lower performance, so it
15604 * is off by default, but can be enabled using ethtool.
15606 if ((tg3_flag(tp, HW_TSO_1) ||
15607 tg3_flag(tp, HW_TSO_2) ||
15608 tg3_flag(tp, HW_TSO_3)) &&
15609 (features & NETIF_F_IP_CSUM))
15610 features |= NETIF_F_TSO;
15611 if (tg3_flag(tp, HW_TSO_2) || tg3_flag(tp, HW_TSO_3)) {
15612 if (features & NETIF_F_IPV6_CSUM)
15613 features |= NETIF_F_TSO6;
15614 if (tg3_flag(tp, HW_TSO_3) ||
15615 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5761 ||
15616 (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5784 &&
15617 GET_CHIP_REV(tp->pci_chip_rev_id) != CHIPREV_5784_AX) ||
15618 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785 ||
15619 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57780)
15620 features |= NETIF_F_TSO_ECN;
15623 dev->features |= features;
15624 dev->vlan_features |= features;
15627 * Add loopback capability only for a subset of devices that support
15628 * MAC-LOOPBACK. Eventually this need to be enhanced to allow INT-PHY
15629 * loopback for the remaining devices.
15631 if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5780 &&
15632 !tg3_flag(tp, CPMU_PRESENT))
15633 /* Add the loopback capability */
15634 features |= NETIF_F_LOOPBACK;
15636 dev->hw_features |= features;
15638 if (tp->pci_chip_rev_id == CHIPREV_ID_5705_A1 &&
15639 !tg3_flag(tp, TSO_CAPABLE) &&
15640 !(tr32(TG3PCI_PCISTATE) & PCISTATE_BUS_SPEED_HIGH)) {
15641 tg3_flag_set(tp, MAX_RXPEND_64);
15642 tp->rx_pending = 63;
15645 err = tg3_get_device_address(tp);
15647 dev_err(&pdev->dev,
15648 "Could not obtain valid ethernet address, aborting\n");
15649 goto err_out_apeunmap;
15653 * Reset chip in case UNDI or EFI driver did not shutdown
15654 * DMA self test will enable WDMAC and we'll see (spurious)
15655 * pending DMA on the PCI bus at that point.
15657 if ((tr32(HOSTCC_MODE) & HOSTCC_MODE_ENABLE) ||
15658 (tr32(WDMAC_MODE) & WDMAC_MODE_ENABLE)) {
15659 tw32(MEMARB_MODE, MEMARB_MODE_ENABLE);
15660 tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
15663 err = tg3_test_dma(tp);
15665 dev_err(&pdev->dev, "DMA engine test failed, aborting\n");
15666 goto err_out_apeunmap;
15669 intmbx = MAILBOX_INTERRUPT_0 + TG3_64BIT_REG_LOW;
15670 rcvmbx = MAILBOX_RCVRET_CON_IDX_0 + TG3_64BIT_REG_LOW;
15671 sndmbx = MAILBOX_SNDHOST_PROD_IDX_0 + TG3_64BIT_REG_LOW;
15672 for (i = 0; i < tp->irq_max; i++) {
15673 struct tg3_napi *tnapi = &tp->napi[i];
15676 tnapi->tx_pending = TG3_DEF_TX_RING_PENDING;
15678 tnapi->int_mbox = intmbx;
15684 tnapi->consmbox = rcvmbx;
15685 tnapi->prodmbox = sndmbx;
15688 tnapi->coal_now = HOSTCC_MODE_COAL_VEC1_NOW << (i - 1);
15690 tnapi->coal_now = HOSTCC_MODE_NOW;
15692 if (!tg3_flag(tp, SUPPORT_MSIX))
15696 * If we support MSIX, we'll be using RSS. If we're using
15697 * RSS, the first vector only handles link interrupts and the
15698 * remaining vectors handle rx and tx interrupts. Reuse the
15699 * mailbox values for the next iteration. The values we setup
15700 * above are still useful for the single vectored mode.
15715 pci_set_drvdata(pdev, dev);
15717 if (tg3_flag(tp, 5717_PLUS)) {
15718 /* Resume a low-power mode */
15719 tg3_frob_aux_power(tp, false);
15722 err = register_netdev(dev);
15724 dev_err(&pdev->dev, "Cannot register net device, aborting\n");
15725 goto err_out_apeunmap;
15728 netdev_info(dev, "Tigon3 [partno(%s) rev %04x] (%s) MAC address %pM\n",
15729 tp->board_part_number,
15730 tp->pci_chip_rev_id,
15731 tg3_bus_string(tp, str),
15734 if (tp->phy_flags & TG3_PHYFLG_IS_CONNECTED) {
15735 struct phy_device *phydev;
15736 phydev = tp->mdio_bus->phy_map[TG3_PHY_MII_ADDR];
15738 "attached PHY driver [%s] (mii_bus:phy_addr=%s)\n",
15739 phydev->drv->name, dev_name(&phydev->dev));
15743 if (tp->phy_flags & TG3_PHYFLG_10_100_ONLY)
15744 ethtype = "10/100Base-TX";
15745 else if (tp->phy_flags & TG3_PHYFLG_ANY_SERDES)
15746 ethtype = "1000Base-SX";
15748 ethtype = "10/100/1000Base-T";
15750 netdev_info(dev, "attached PHY is %s (%s Ethernet) "
15751 "(WireSpeed[%d], EEE[%d])\n",
15752 tg3_phy_string(tp), ethtype,
15753 (tp->phy_flags & TG3_PHYFLG_NO_ETH_WIRE_SPEED) == 0,
15754 (tp->phy_flags & TG3_PHYFLG_EEE_CAP) != 0);
15757 netdev_info(dev, "RXcsums[%d] LinkChgREG[%d] MIirq[%d] ASF[%d] TSOcap[%d]\n",
15758 (dev->features & NETIF_F_RXCSUM) != 0,
15759 tg3_flag(tp, USE_LINKCHG_REG) != 0,
15760 (tp->phy_flags & TG3_PHYFLG_USE_MI_INTERRUPT) != 0,
15761 tg3_flag(tp, ENABLE_ASF) != 0,
15762 tg3_flag(tp, TSO_CAPABLE) != 0);
15763 netdev_info(dev, "dma_rwctrl[%08x] dma_mask[%d-bit]\n",
15765 pdev->dma_mask == DMA_BIT_MASK(32) ? 32 :
15766 ((u64)pdev->dma_mask) == DMA_BIT_MASK(40) ? 40 : 64);
15768 pci_save_state(pdev);
15774 iounmap(tp->aperegs);
15775 tp->aperegs = NULL;
15787 err_out_power_down:
15788 pci_set_power_state(pdev, PCI_D3hot);
15791 pci_release_regions(pdev);
15793 err_out_disable_pdev:
15794 pci_disable_device(pdev);
15795 pci_set_drvdata(pdev, NULL);
15799 static void __devexit tg3_remove_one(struct pci_dev *pdev)
15801 struct net_device *dev = pci_get_drvdata(pdev);
15804 struct tg3 *tp = netdev_priv(dev);
15807 release_firmware(tp->fw);
15809 tg3_reset_task_cancel(tp);
15811 if (tg3_flag(tp, USE_PHYLIB)) {
15816 unregister_netdev(dev);
15818 iounmap(tp->aperegs);
15819 tp->aperegs = NULL;
15826 pci_release_regions(pdev);
15827 pci_disable_device(pdev);
15828 pci_set_drvdata(pdev, NULL);
15832 #ifdef CONFIG_PM_SLEEP
15833 static int tg3_suspend(struct device *device)
15835 struct pci_dev *pdev = to_pci_dev(device);
15836 struct net_device *dev = pci_get_drvdata(pdev);
15837 struct tg3 *tp = netdev_priv(dev);
15840 if (!netif_running(dev))
15843 tg3_reset_task_cancel(tp);
15845 tg3_netif_stop(tp);
15847 del_timer_sync(&tp->timer);
15849 tg3_full_lock(tp, 1);
15850 tg3_disable_ints(tp);
15851 tg3_full_unlock(tp);
15853 netif_device_detach(dev);
15855 tg3_full_lock(tp, 0);
15856 tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
15857 tg3_flag_clear(tp, INIT_COMPLETE);
15858 tg3_full_unlock(tp);
15860 err = tg3_power_down_prepare(tp);
15864 tg3_full_lock(tp, 0);
15866 tg3_flag_set(tp, INIT_COMPLETE);
15867 err2 = tg3_restart_hw(tp, 1);
15871 tp->timer.expires = jiffies + tp->timer_offset;
15872 add_timer(&tp->timer);
15874 netif_device_attach(dev);
15875 tg3_netif_start(tp);
15878 tg3_full_unlock(tp);
15887 static int tg3_resume(struct device *device)
15889 struct pci_dev *pdev = to_pci_dev(device);
15890 struct net_device *dev = pci_get_drvdata(pdev);
15891 struct tg3 *tp = netdev_priv(dev);
15894 if (!netif_running(dev))
15897 netif_device_attach(dev);
15899 tg3_full_lock(tp, 0);
15901 tg3_flag_set(tp, INIT_COMPLETE);
15902 err = tg3_restart_hw(tp, 1);
15906 tp->timer.expires = jiffies + tp->timer_offset;
15907 add_timer(&tp->timer);
15909 tg3_netif_start(tp);
15912 tg3_full_unlock(tp);
15920 static SIMPLE_DEV_PM_OPS(tg3_pm_ops, tg3_suspend, tg3_resume);
15921 #define TG3_PM_OPS (&tg3_pm_ops)
15925 #define TG3_PM_OPS NULL
15927 #endif /* CONFIG_PM_SLEEP */
15930 * tg3_io_error_detected - called when PCI error is detected
15931 * @pdev: Pointer to PCI device
15932 * @state: The current pci connection state
15934 * This function is called after a PCI bus error affecting
15935 * this device has been detected.
15937 static pci_ers_result_t tg3_io_error_detected(struct pci_dev *pdev,
15938 pci_channel_state_t state)
15940 struct net_device *netdev = pci_get_drvdata(pdev);
15941 struct tg3 *tp = netdev_priv(netdev);
15942 pci_ers_result_t err = PCI_ERS_RESULT_NEED_RESET;
15944 netdev_info(netdev, "PCI I/O error detected\n");
15948 if (!netif_running(netdev))
15953 tg3_netif_stop(tp);
15955 del_timer_sync(&tp->timer);
15957 /* Want to make sure that the reset task doesn't run */
15958 tg3_reset_task_cancel(tp);
15959 tg3_flag_clear(tp, TX_RECOVERY_PENDING);
15961 netif_device_detach(netdev);
15963 /* Clean up software state, even if MMIO is blocked */
15964 tg3_full_lock(tp, 0);
15965 tg3_halt(tp, RESET_KIND_SHUTDOWN, 0);
15966 tg3_full_unlock(tp);
15969 if (state == pci_channel_io_perm_failure)
15970 err = PCI_ERS_RESULT_DISCONNECT;
15972 pci_disable_device(pdev);
15980 * tg3_io_slot_reset - called after the pci bus has been reset.
15981 * @pdev: Pointer to PCI device
15983 * Restart the card from scratch, as if from a cold-boot.
15984 * At this point, the card has exprienced a hard reset,
15985 * followed by fixups by BIOS, and has its config space
15986 * set up identically to what it was at cold boot.
15988 static pci_ers_result_t tg3_io_slot_reset(struct pci_dev *pdev)
15990 struct net_device *netdev = pci_get_drvdata(pdev);
15991 struct tg3 *tp = netdev_priv(netdev);
15992 pci_ers_result_t rc = PCI_ERS_RESULT_DISCONNECT;
15997 if (pci_enable_device(pdev)) {
15998 netdev_err(netdev, "Cannot re-enable PCI device after reset.\n");
16002 pci_set_master(pdev);
16003 pci_restore_state(pdev);
16004 pci_save_state(pdev);
16006 if (!netif_running(netdev)) {
16007 rc = PCI_ERS_RESULT_RECOVERED;
16011 err = tg3_power_up(tp);
16015 rc = PCI_ERS_RESULT_RECOVERED;
16024 * tg3_io_resume - called when traffic can start flowing again.
16025 * @pdev: Pointer to PCI device
16027 * This callback is called when the error recovery driver tells
16028 * us that its OK to resume normal operation.
16030 static void tg3_io_resume(struct pci_dev *pdev)
16032 struct net_device *netdev = pci_get_drvdata(pdev);
16033 struct tg3 *tp = netdev_priv(netdev);
16038 if (!netif_running(netdev))
16041 tg3_full_lock(tp, 0);
16042 tg3_flag_set(tp, INIT_COMPLETE);
16043 err = tg3_restart_hw(tp, 1);
16044 tg3_full_unlock(tp);
16046 netdev_err(netdev, "Cannot restart hardware after reset.\n");
16050 netif_device_attach(netdev);
16052 tp->timer.expires = jiffies + tp->timer_offset;
16053 add_timer(&tp->timer);
16055 tg3_netif_start(tp);
16063 static struct pci_error_handlers tg3_err_handler = {
16064 .error_detected = tg3_io_error_detected,
16065 .slot_reset = tg3_io_slot_reset,
16066 .resume = tg3_io_resume
16069 static struct pci_driver tg3_driver = {
16070 .name = DRV_MODULE_NAME,
16071 .id_table = tg3_pci_tbl,
16072 .probe = tg3_init_one,
16073 .remove = __devexit_p(tg3_remove_one),
16074 .err_handler = &tg3_err_handler,
16075 .driver.pm = TG3_PM_OPS,
16078 static int __init tg3_init(void)
16080 return pci_register_driver(&tg3_driver);
16083 static void __exit tg3_cleanup(void)
16085 pci_unregister_driver(&tg3_driver);
16088 module_init(tg3_init);
16089 module_exit(tg3_cleanup);