2 * tg3.c: Broadcom Tigon3 ethernet driver.
4 * Copyright (C) 2001, 2002, 2003, 2004 David S. Miller (davem@redhat.com)
5 * Copyright (C) 2001, 2002, 2003 Jeff Garzik (jgarzik@pobox.com)
6 * Copyright (C) 2004 Sun Microsystems Inc.
7 * Copyright (C) 2005-2011 Broadcom Corporation.
10 * Derived from proprietary unpublished source code,
11 * Copyright (C) 2000-2003 Broadcom Corporation.
13 * Permission is hereby granted for the distribution of this firmware
14 * data in hexadecimal or equivalent format, provided this copyright
15 * notice is accompanying it.
19 #include <linux/module.h>
20 #include <linux/moduleparam.h>
21 #include <linux/stringify.h>
22 #include <linux/kernel.h>
23 #include <linux/types.h>
24 #include <linux/compiler.h>
25 #include <linux/slab.h>
26 #include <linux/delay.h>
28 #include <linux/init.h>
29 #include <linux/interrupt.h>
30 #include <linux/ioport.h>
31 #include <linux/pci.h>
32 #include <linux/netdevice.h>
33 #include <linux/etherdevice.h>
34 #include <linux/skbuff.h>
35 #include <linux/ethtool.h>
36 #include <linux/mdio.h>
37 #include <linux/mii.h>
38 #include <linux/phy.h>
39 #include <linux/brcmphy.h>
40 #include <linux/if_vlan.h>
42 #include <linux/tcp.h>
43 #include <linux/workqueue.h>
44 #include <linux/prefetch.h>
45 #include <linux/dma-mapping.h>
46 #include <linux/firmware.h>
48 #include <net/checksum.h>
51 #include <asm/system.h>
53 #include <asm/byteorder.h>
54 #include <linux/uaccess.h>
57 #include <asm/idprom.h>
66 /* Functions & macros to verify TG3_FLAGS types */
68 static inline int _tg3_flag(enum TG3_FLAGS flag, unsigned long *bits)
70 return test_bit(flag, bits);
73 static inline void _tg3_flag_set(enum TG3_FLAGS flag, unsigned long *bits)
78 static inline void _tg3_flag_clear(enum TG3_FLAGS flag, unsigned long *bits)
80 clear_bit(flag, bits);
83 #define tg3_flag(tp, flag) \
84 _tg3_flag(TG3_FLAG_##flag, (tp)->tg3_flags)
85 #define tg3_flag_set(tp, flag) \
86 _tg3_flag_set(TG3_FLAG_##flag, (tp)->tg3_flags)
87 #define tg3_flag_clear(tp, flag) \
88 _tg3_flag_clear(TG3_FLAG_##flag, (tp)->tg3_flags)
90 #define DRV_MODULE_NAME "tg3"
92 #define TG3_MIN_NUM 122
93 #define DRV_MODULE_VERSION \
94 __stringify(TG3_MAJ_NUM) "." __stringify(TG3_MIN_NUM)
95 #define DRV_MODULE_RELDATE "December 7, 2011"
97 #define RESET_KIND_SHUTDOWN 0
98 #define RESET_KIND_INIT 1
99 #define RESET_KIND_SUSPEND 2
101 #define TG3_DEF_RX_MODE 0
102 #define TG3_DEF_TX_MODE 0
103 #define TG3_DEF_MSG_ENABLE \
113 #define TG3_GRC_LCLCTL_PWRSW_DELAY 100
115 /* length of time before we decide the hardware is borked,
116 * and dev->tx_timeout() should be called to fix the problem
119 #define TG3_TX_TIMEOUT (5 * HZ)
121 /* hardware minimum and maximum for a single frame's data payload */
122 #define TG3_MIN_MTU 60
123 #define TG3_MAX_MTU(tp) \
124 (tg3_flag(tp, JUMBO_CAPABLE) ? 9000 : 1500)
126 /* These numbers seem to be hard coded in the NIC firmware somehow.
127 * You can't change the ring sizes, but you can change where you place
128 * them in the NIC onboard memory.
130 #define TG3_RX_STD_RING_SIZE(tp) \
131 (tg3_flag(tp, LRG_PROD_RING_CAP) ? \
132 TG3_RX_STD_MAX_SIZE_5717 : TG3_RX_STD_MAX_SIZE_5700)
133 #define TG3_DEF_RX_RING_PENDING 200
134 #define TG3_RX_JMB_RING_SIZE(tp) \
135 (tg3_flag(tp, LRG_PROD_RING_CAP) ? \
136 TG3_RX_JMB_MAX_SIZE_5717 : TG3_RX_JMB_MAX_SIZE_5700)
137 #define TG3_DEF_RX_JUMBO_RING_PENDING 100
139 /* Do not place this n-ring entries value into the tp struct itself,
140 * we really want to expose these constants to GCC so that modulo et
141 * al. operations are done with shifts and masks instead of with
142 * hw multiply/modulo instructions. Another solution would be to
143 * replace things like '% foo' with '& (foo - 1)'.
146 #define TG3_TX_RING_SIZE 512
147 #define TG3_DEF_TX_RING_PENDING (TG3_TX_RING_SIZE - 1)
149 #define TG3_RX_STD_RING_BYTES(tp) \
150 (sizeof(struct tg3_rx_buffer_desc) * TG3_RX_STD_RING_SIZE(tp))
151 #define TG3_RX_JMB_RING_BYTES(tp) \
152 (sizeof(struct tg3_ext_rx_buffer_desc) * TG3_RX_JMB_RING_SIZE(tp))
153 #define TG3_RX_RCB_RING_BYTES(tp) \
154 (sizeof(struct tg3_rx_buffer_desc) * (tp->rx_ret_ring_mask + 1))
155 #define TG3_TX_RING_BYTES (sizeof(struct tg3_tx_buffer_desc) * \
157 #define NEXT_TX(N) (((N) + 1) & (TG3_TX_RING_SIZE - 1))
159 #define TG3_DMA_BYTE_ENAB 64
161 #define TG3_RX_STD_DMA_SZ 1536
162 #define TG3_RX_JMB_DMA_SZ 9046
164 #define TG3_RX_DMA_TO_MAP_SZ(x) ((x) + TG3_DMA_BYTE_ENAB)
166 #define TG3_RX_STD_MAP_SZ TG3_RX_DMA_TO_MAP_SZ(TG3_RX_STD_DMA_SZ)
167 #define TG3_RX_JMB_MAP_SZ TG3_RX_DMA_TO_MAP_SZ(TG3_RX_JMB_DMA_SZ)
169 #define TG3_RX_STD_BUFF_RING_SIZE(tp) \
170 (sizeof(struct ring_info) * TG3_RX_STD_RING_SIZE(tp))
172 #define TG3_RX_JMB_BUFF_RING_SIZE(tp) \
173 (sizeof(struct ring_info) * TG3_RX_JMB_RING_SIZE(tp))
175 /* Due to a hardware bug, the 5701 can only DMA to memory addresses
176 * that are at least dword aligned when used in PCIX mode. The driver
177 * works around this bug by double copying the packet. This workaround
178 * is built into the normal double copy length check for efficiency.
180 * However, the double copy is only necessary on those architectures
181 * where unaligned memory accesses are inefficient. For those architectures
182 * where unaligned memory accesses incur little penalty, we can reintegrate
183 * the 5701 in the normal rx path. Doing so saves a device structure
184 * dereference by hardcoding the double copy threshold in place.
186 #define TG3_RX_COPY_THRESHOLD 256
187 #if NET_IP_ALIGN == 0 || defined(CONFIG_HAVE_EFFICIENT_UNALIGNED_ACCESS)
188 #define TG3_RX_COPY_THRESH(tp) TG3_RX_COPY_THRESHOLD
190 #define TG3_RX_COPY_THRESH(tp) ((tp)->rx_copy_thresh)
193 #if (NET_IP_ALIGN != 0)
194 #define TG3_RX_OFFSET(tp) ((tp)->rx_offset)
196 #define TG3_RX_OFFSET(tp) (NET_SKB_PAD)
199 /* minimum number of free TX descriptors required to wake up TX process */
200 #define TG3_TX_WAKEUP_THRESH(tnapi) ((tnapi)->tx_pending / 4)
201 #define TG3_TX_BD_DMA_MAX_2K 2048
202 #define TG3_TX_BD_DMA_MAX_4K 4096
204 #define TG3_RAW_IP_ALIGN 2
206 #define TG3_FW_UPDATE_TIMEOUT_SEC 5
208 #define FIRMWARE_TG3 "tigon/tg3.bin"
209 #define FIRMWARE_TG3TSO "tigon/tg3_tso.bin"
210 #define FIRMWARE_TG3TSO5 "tigon/tg3_tso5.bin"
212 static char version[] __devinitdata =
213 DRV_MODULE_NAME ".c:v" DRV_MODULE_VERSION " (" DRV_MODULE_RELDATE ")";
215 MODULE_AUTHOR("David S. Miller (davem@redhat.com) and Jeff Garzik (jgarzik@pobox.com)");
216 MODULE_DESCRIPTION("Broadcom Tigon3 ethernet driver");
217 MODULE_LICENSE("GPL");
218 MODULE_VERSION(DRV_MODULE_VERSION);
219 MODULE_FIRMWARE(FIRMWARE_TG3);
220 MODULE_FIRMWARE(FIRMWARE_TG3TSO);
221 MODULE_FIRMWARE(FIRMWARE_TG3TSO5);
223 static int tg3_debug = -1; /* -1 == use TG3_DEF_MSG_ENABLE as value */
224 module_param(tg3_debug, int, 0);
225 MODULE_PARM_DESC(tg3_debug, "Tigon3 bitmapped debugging message enable value");
227 static DEFINE_PCI_DEVICE_TABLE(tg3_pci_tbl) = {
228 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5700)},
229 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5701)},
230 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5702)},
231 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5703)},
232 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5704)},
233 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5702FE)},
234 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5705)},
235 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5705_2)},
236 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5705M)},
237 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5705M_2)},
238 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5702X)},
239 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5703X)},
240 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5704S)},
241 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5702A3)},
242 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5703A3)},
243 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5782)},
244 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5788)},
245 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5789)},
246 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5901)},
247 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5901_2)},
248 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5704S_2)},
249 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5705F)},
250 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5721)},
251 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5722)},
252 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5751)},
253 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5751M)},
254 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5751F)},
255 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5752)},
256 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5752M)},
257 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5753)},
258 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5753M)},
259 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5753F)},
260 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5754)},
261 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5754M)},
262 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5755)},
263 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5755M)},
264 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5756)},
265 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5786)},
266 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5787)},
267 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5787M)},
268 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5787F)},
269 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5714)},
270 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5714S)},
271 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5715)},
272 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5715S)},
273 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5780)},
274 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5780S)},
275 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5781)},
276 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5906)},
277 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5906M)},
278 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5784)},
279 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5764)},
280 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5723)},
281 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5761)},
282 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5761E)},
283 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_5761S)},
284 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_5761SE)},
285 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_5785_G)},
286 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_5785_F)},
287 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_57780)},
288 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_57760)},
289 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_57790)},
290 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_57788)},
291 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_5717)},
292 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_5718)},
293 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_57781)},
294 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_57785)},
295 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_57761)},
296 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_57765)},
297 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_57791)},
298 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_57795)},
299 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_5719)},
300 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_5720)},
301 {PCI_DEVICE(PCI_VENDOR_ID_SYSKONNECT, PCI_DEVICE_ID_SYSKONNECT_9DXX)},
302 {PCI_DEVICE(PCI_VENDOR_ID_SYSKONNECT, PCI_DEVICE_ID_SYSKONNECT_9MXX)},
303 {PCI_DEVICE(PCI_VENDOR_ID_ALTIMA, PCI_DEVICE_ID_ALTIMA_AC1000)},
304 {PCI_DEVICE(PCI_VENDOR_ID_ALTIMA, PCI_DEVICE_ID_ALTIMA_AC1001)},
305 {PCI_DEVICE(PCI_VENDOR_ID_ALTIMA, PCI_DEVICE_ID_ALTIMA_AC1003)},
306 {PCI_DEVICE(PCI_VENDOR_ID_ALTIMA, PCI_DEVICE_ID_ALTIMA_AC9100)},
307 {PCI_DEVICE(PCI_VENDOR_ID_APPLE, PCI_DEVICE_ID_APPLE_TIGON3)},
308 {PCI_DEVICE(0x10cf, 0x11a2)}, /* Fujitsu 1000base-SX with BCM5703SKHB */
312 MODULE_DEVICE_TABLE(pci, tg3_pci_tbl);
314 static const struct {
315 const char string[ETH_GSTRING_LEN];
316 } ethtool_stats_keys[] = {
319 { "rx_ucast_packets" },
320 { "rx_mcast_packets" },
321 { "rx_bcast_packets" },
323 { "rx_align_errors" },
324 { "rx_xon_pause_rcvd" },
325 { "rx_xoff_pause_rcvd" },
326 { "rx_mac_ctrl_rcvd" },
327 { "rx_xoff_entered" },
328 { "rx_frame_too_long_errors" },
330 { "rx_undersize_packets" },
331 { "rx_in_length_errors" },
332 { "rx_out_length_errors" },
333 { "rx_64_or_less_octet_packets" },
334 { "rx_65_to_127_octet_packets" },
335 { "rx_128_to_255_octet_packets" },
336 { "rx_256_to_511_octet_packets" },
337 { "rx_512_to_1023_octet_packets" },
338 { "rx_1024_to_1522_octet_packets" },
339 { "rx_1523_to_2047_octet_packets" },
340 { "rx_2048_to_4095_octet_packets" },
341 { "rx_4096_to_8191_octet_packets" },
342 { "rx_8192_to_9022_octet_packets" },
349 { "tx_flow_control" },
351 { "tx_single_collisions" },
352 { "tx_mult_collisions" },
354 { "tx_excessive_collisions" },
355 { "tx_late_collisions" },
356 { "tx_collide_2times" },
357 { "tx_collide_3times" },
358 { "tx_collide_4times" },
359 { "tx_collide_5times" },
360 { "tx_collide_6times" },
361 { "tx_collide_7times" },
362 { "tx_collide_8times" },
363 { "tx_collide_9times" },
364 { "tx_collide_10times" },
365 { "tx_collide_11times" },
366 { "tx_collide_12times" },
367 { "tx_collide_13times" },
368 { "tx_collide_14times" },
369 { "tx_collide_15times" },
370 { "tx_ucast_packets" },
371 { "tx_mcast_packets" },
372 { "tx_bcast_packets" },
373 { "tx_carrier_sense_errors" },
377 { "dma_writeq_full" },
378 { "dma_write_prioq_full" },
382 { "rx_threshold_hit" },
384 { "dma_readq_full" },
385 { "dma_read_prioq_full" },
386 { "tx_comp_queue_full" },
388 { "ring_set_send_prod_index" },
389 { "ring_status_update" },
391 { "nic_avoided_irqs" },
392 { "nic_tx_threshold_hit" },
394 { "mbuf_lwm_thresh_hit" },
397 #define TG3_NUM_STATS ARRAY_SIZE(ethtool_stats_keys)
400 static const struct {
401 const char string[ETH_GSTRING_LEN];
402 } ethtool_test_keys[] = {
403 { "nvram test (online) " },
404 { "link test (online) " },
405 { "register test (offline)" },
406 { "memory test (offline)" },
407 { "mac loopback test (offline)" },
408 { "phy loopback test (offline)" },
409 { "ext loopback test (offline)" },
410 { "interrupt test (offline)" },
413 #define TG3_NUM_TEST ARRAY_SIZE(ethtool_test_keys)
416 static void tg3_write32(struct tg3 *tp, u32 off, u32 val)
418 writel(val, tp->regs + off);
421 static u32 tg3_read32(struct tg3 *tp, u32 off)
423 return readl(tp->regs + off);
426 static void tg3_ape_write32(struct tg3 *tp, u32 off, u32 val)
428 writel(val, tp->aperegs + off);
431 static u32 tg3_ape_read32(struct tg3 *tp, u32 off)
433 return readl(tp->aperegs + off);
436 static void tg3_write_indirect_reg32(struct tg3 *tp, u32 off, u32 val)
440 spin_lock_irqsave(&tp->indirect_lock, flags);
441 pci_write_config_dword(tp->pdev, TG3PCI_REG_BASE_ADDR, off);
442 pci_write_config_dword(tp->pdev, TG3PCI_REG_DATA, val);
443 spin_unlock_irqrestore(&tp->indirect_lock, flags);
446 static void tg3_write_flush_reg32(struct tg3 *tp, u32 off, u32 val)
448 writel(val, tp->regs + off);
449 readl(tp->regs + off);
452 static u32 tg3_read_indirect_reg32(struct tg3 *tp, u32 off)
457 spin_lock_irqsave(&tp->indirect_lock, flags);
458 pci_write_config_dword(tp->pdev, TG3PCI_REG_BASE_ADDR, off);
459 pci_read_config_dword(tp->pdev, TG3PCI_REG_DATA, &val);
460 spin_unlock_irqrestore(&tp->indirect_lock, flags);
464 static void tg3_write_indirect_mbox(struct tg3 *tp, u32 off, u32 val)
468 if (off == (MAILBOX_RCVRET_CON_IDX_0 + TG3_64BIT_REG_LOW)) {
469 pci_write_config_dword(tp->pdev, TG3PCI_RCV_RET_RING_CON_IDX +
470 TG3_64BIT_REG_LOW, val);
473 if (off == TG3_RX_STD_PROD_IDX_REG) {
474 pci_write_config_dword(tp->pdev, TG3PCI_STD_RING_PROD_IDX +
475 TG3_64BIT_REG_LOW, val);
479 spin_lock_irqsave(&tp->indirect_lock, flags);
480 pci_write_config_dword(tp->pdev, TG3PCI_REG_BASE_ADDR, off + 0x5600);
481 pci_write_config_dword(tp->pdev, TG3PCI_REG_DATA, val);
482 spin_unlock_irqrestore(&tp->indirect_lock, flags);
484 /* In indirect mode when disabling interrupts, we also need
485 * to clear the interrupt bit in the GRC local ctrl register.
487 if ((off == (MAILBOX_INTERRUPT_0 + TG3_64BIT_REG_LOW)) &&
489 pci_write_config_dword(tp->pdev, TG3PCI_MISC_LOCAL_CTRL,
490 tp->grc_local_ctrl|GRC_LCLCTRL_CLEARINT);
494 static u32 tg3_read_indirect_mbox(struct tg3 *tp, u32 off)
499 spin_lock_irqsave(&tp->indirect_lock, flags);
500 pci_write_config_dword(tp->pdev, TG3PCI_REG_BASE_ADDR, off + 0x5600);
501 pci_read_config_dword(tp->pdev, TG3PCI_REG_DATA, &val);
502 spin_unlock_irqrestore(&tp->indirect_lock, flags);
506 /* usec_wait specifies the wait time in usec when writing to certain registers
507 * where it is unsafe to read back the register without some delay.
508 * GRC_LOCAL_CTRL is one example if the GPIOs are toggled to switch power.
509 * TG3PCI_CLOCK_CTRL is another example if the clock frequencies are changed.
511 static void _tw32_flush(struct tg3 *tp, u32 off, u32 val, u32 usec_wait)
513 if (tg3_flag(tp, PCIX_TARGET_HWBUG) || tg3_flag(tp, ICH_WORKAROUND))
514 /* Non-posted methods */
515 tp->write32(tp, off, val);
518 tg3_write32(tp, off, val);
523 /* Wait again after the read for the posted method to guarantee that
524 * the wait time is met.
530 static inline void tw32_mailbox_flush(struct tg3 *tp, u32 off, u32 val)
532 tp->write32_mbox(tp, off, val);
533 if (!tg3_flag(tp, MBOX_WRITE_REORDER) && !tg3_flag(tp, ICH_WORKAROUND))
534 tp->read32_mbox(tp, off);
537 static void tg3_write32_tx_mbox(struct tg3 *tp, u32 off, u32 val)
539 void __iomem *mbox = tp->regs + off;
541 if (tg3_flag(tp, TXD_MBOX_HWBUG))
543 if (tg3_flag(tp, MBOX_WRITE_REORDER))
547 static u32 tg3_read32_mbox_5906(struct tg3 *tp, u32 off)
549 return readl(tp->regs + off + GRCMBOX_BASE);
552 static void tg3_write32_mbox_5906(struct tg3 *tp, u32 off, u32 val)
554 writel(val, tp->regs + off + GRCMBOX_BASE);
557 #define tw32_mailbox(reg, val) tp->write32_mbox(tp, reg, val)
558 #define tw32_mailbox_f(reg, val) tw32_mailbox_flush(tp, (reg), (val))
559 #define tw32_rx_mbox(reg, val) tp->write32_rx_mbox(tp, reg, val)
560 #define tw32_tx_mbox(reg, val) tp->write32_tx_mbox(tp, reg, val)
561 #define tr32_mailbox(reg) tp->read32_mbox(tp, reg)
563 #define tw32(reg, val) tp->write32(tp, reg, val)
564 #define tw32_f(reg, val) _tw32_flush(tp, (reg), (val), 0)
565 #define tw32_wait_f(reg, val, us) _tw32_flush(tp, (reg), (val), (us))
566 #define tr32(reg) tp->read32(tp, reg)
568 static void tg3_write_mem(struct tg3 *tp, u32 off, u32 val)
572 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906 &&
573 (off >= NIC_SRAM_STATS_BLK) && (off < NIC_SRAM_TX_BUFFER_DESC))
576 spin_lock_irqsave(&tp->indirect_lock, flags);
577 if (tg3_flag(tp, SRAM_USE_CONFIG)) {
578 pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_BASE_ADDR, off);
579 pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_DATA, val);
581 /* Always leave this as zero. */
582 pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_BASE_ADDR, 0);
584 tw32_f(TG3PCI_MEM_WIN_BASE_ADDR, off);
585 tw32_f(TG3PCI_MEM_WIN_DATA, val);
587 /* Always leave this as zero. */
588 tw32_f(TG3PCI_MEM_WIN_BASE_ADDR, 0);
590 spin_unlock_irqrestore(&tp->indirect_lock, flags);
593 static void tg3_read_mem(struct tg3 *tp, u32 off, u32 *val)
597 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906 &&
598 (off >= NIC_SRAM_STATS_BLK) && (off < NIC_SRAM_TX_BUFFER_DESC)) {
603 spin_lock_irqsave(&tp->indirect_lock, flags);
604 if (tg3_flag(tp, SRAM_USE_CONFIG)) {
605 pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_BASE_ADDR, off);
606 pci_read_config_dword(tp->pdev, TG3PCI_MEM_WIN_DATA, val);
608 /* Always leave this as zero. */
609 pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_BASE_ADDR, 0);
611 tw32_f(TG3PCI_MEM_WIN_BASE_ADDR, off);
612 *val = tr32(TG3PCI_MEM_WIN_DATA);
614 /* Always leave this as zero. */
615 tw32_f(TG3PCI_MEM_WIN_BASE_ADDR, 0);
617 spin_unlock_irqrestore(&tp->indirect_lock, flags);
620 static void tg3_ape_lock_init(struct tg3 *tp)
625 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5761)
626 regbase = TG3_APE_LOCK_GRANT;
628 regbase = TG3_APE_PER_LOCK_GRANT;
630 /* Make sure the driver hasn't any stale locks. */
631 for (i = TG3_APE_LOCK_PHY0; i <= TG3_APE_LOCK_GPIO; i++) {
633 case TG3_APE_LOCK_PHY0:
634 case TG3_APE_LOCK_PHY1:
635 case TG3_APE_LOCK_PHY2:
636 case TG3_APE_LOCK_PHY3:
637 bit = APE_LOCK_GRANT_DRIVER;
641 bit = APE_LOCK_GRANT_DRIVER;
643 bit = 1 << tp->pci_fn;
645 tg3_ape_write32(tp, regbase + 4 * i, bit);
650 static int tg3_ape_lock(struct tg3 *tp, int locknum)
654 u32 status, req, gnt, bit;
656 if (!tg3_flag(tp, ENABLE_APE))
660 case TG3_APE_LOCK_GPIO:
661 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5761)
663 case TG3_APE_LOCK_GRC:
664 case TG3_APE_LOCK_MEM:
666 bit = APE_LOCK_REQ_DRIVER;
668 bit = 1 << tp->pci_fn;
674 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5761) {
675 req = TG3_APE_LOCK_REQ;
676 gnt = TG3_APE_LOCK_GRANT;
678 req = TG3_APE_PER_LOCK_REQ;
679 gnt = TG3_APE_PER_LOCK_GRANT;
684 tg3_ape_write32(tp, req + off, bit);
686 /* Wait for up to 1 millisecond to acquire lock. */
687 for (i = 0; i < 100; i++) {
688 status = tg3_ape_read32(tp, gnt + off);
695 /* Revoke the lock request. */
696 tg3_ape_write32(tp, gnt + off, bit);
703 static void tg3_ape_unlock(struct tg3 *tp, int locknum)
707 if (!tg3_flag(tp, ENABLE_APE))
711 case TG3_APE_LOCK_GPIO:
712 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5761)
714 case TG3_APE_LOCK_GRC:
715 case TG3_APE_LOCK_MEM:
717 bit = APE_LOCK_GRANT_DRIVER;
719 bit = 1 << tp->pci_fn;
725 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5761)
726 gnt = TG3_APE_LOCK_GRANT;
728 gnt = TG3_APE_PER_LOCK_GRANT;
730 tg3_ape_write32(tp, gnt + 4 * locknum, bit);
733 static void tg3_ape_send_event(struct tg3 *tp, u32 event)
738 /* NCSI does not support APE events */
739 if (tg3_flag(tp, APE_HAS_NCSI))
742 apedata = tg3_ape_read32(tp, TG3_APE_SEG_SIG);
743 if (apedata != APE_SEG_SIG_MAGIC)
746 apedata = tg3_ape_read32(tp, TG3_APE_FW_STATUS);
747 if (!(apedata & APE_FW_STATUS_READY))
750 /* Wait for up to 1 millisecond for APE to service previous event. */
751 for (i = 0; i < 10; i++) {
752 if (tg3_ape_lock(tp, TG3_APE_LOCK_MEM))
755 apedata = tg3_ape_read32(tp, TG3_APE_EVENT_STATUS);
757 if (!(apedata & APE_EVENT_STATUS_EVENT_PENDING))
758 tg3_ape_write32(tp, TG3_APE_EVENT_STATUS,
759 event | APE_EVENT_STATUS_EVENT_PENDING);
761 tg3_ape_unlock(tp, TG3_APE_LOCK_MEM);
763 if (!(apedata & APE_EVENT_STATUS_EVENT_PENDING))
769 if (!(apedata & APE_EVENT_STATUS_EVENT_PENDING))
770 tg3_ape_write32(tp, TG3_APE_EVENT, APE_EVENT_1);
773 static void tg3_ape_driver_state_change(struct tg3 *tp, int kind)
778 if (!tg3_flag(tp, ENABLE_APE))
782 case RESET_KIND_INIT:
783 tg3_ape_write32(tp, TG3_APE_HOST_SEG_SIG,
784 APE_HOST_SEG_SIG_MAGIC);
785 tg3_ape_write32(tp, TG3_APE_HOST_SEG_LEN,
786 APE_HOST_SEG_LEN_MAGIC);
787 apedata = tg3_ape_read32(tp, TG3_APE_HOST_INIT_COUNT);
788 tg3_ape_write32(tp, TG3_APE_HOST_INIT_COUNT, ++apedata);
789 tg3_ape_write32(tp, TG3_APE_HOST_DRIVER_ID,
790 APE_HOST_DRIVER_ID_MAGIC(TG3_MAJ_NUM, TG3_MIN_NUM));
791 tg3_ape_write32(tp, TG3_APE_HOST_BEHAVIOR,
792 APE_HOST_BEHAV_NO_PHYLOCK);
793 tg3_ape_write32(tp, TG3_APE_HOST_DRVR_STATE,
794 TG3_APE_HOST_DRVR_STATE_START);
796 event = APE_EVENT_STATUS_STATE_START;
798 case RESET_KIND_SHUTDOWN:
799 /* With the interface we are currently using,
800 * APE does not track driver state. Wiping
801 * out the HOST SEGMENT SIGNATURE forces
802 * the APE to assume OS absent status.
804 tg3_ape_write32(tp, TG3_APE_HOST_SEG_SIG, 0x0);
806 if (device_may_wakeup(&tp->pdev->dev) &&
807 tg3_flag(tp, WOL_ENABLE)) {
808 tg3_ape_write32(tp, TG3_APE_HOST_WOL_SPEED,
809 TG3_APE_HOST_WOL_SPEED_AUTO);
810 apedata = TG3_APE_HOST_DRVR_STATE_WOL;
812 apedata = TG3_APE_HOST_DRVR_STATE_UNLOAD;
814 tg3_ape_write32(tp, TG3_APE_HOST_DRVR_STATE, apedata);
816 event = APE_EVENT_STATUS_STATE_UNLOAD;
818 case RESET_KIND_SUSPEND:
819 event = APE_EVENT_STATUS_STATE_SUSPEND;
825 event |= APE_EVENT_STATUS_DRIVER_EVNT | APE_EVENT_STATUS_STATE_CHNGE;
827 tg3_ape_send_event(tp, event);
830 static void tg3_disable_ints(struct tg3 *tp)
834 tw32(TG3PCI_MISC_HOST_CTRL,
835 (tp->misc_host_ctrl | MISC_HOST_CTRL_MASK_PCI_INT));
836 for (i = 0; i < tp->irq_max; i++)
837 tw32_mailbox_f(tp->napi[i].int_mbox, 0x00000001);
840 static void tg3_enable_ints(struct tg3 *tp)
847 tw32(TG3PCI_MISC_HOST_CTRL,
848 (tp->misc_host_ctrl & ~MISC_HOST_CTRL_MASK_PCI_INT));
850 tp->coal_now = tp->coalesce_mode | HOSTCC_MODE_ENABLE;
851 for (i = 0; i < tp->irq_cnt; i++) {
852 struct tg3_napi *tnapi = &tp->napi[i];
854 tw32_mailbox_f(tnapi->int_mbox, tnapi->last_tag << 24);
855 if (tg3_flag(tp, 1SHOT_MSI))
856 tw32_mailbox_f(tnapi->int_mbox, tnapi->last_tag << 24);
858 tp->coal_now |= tnapi->coal_now;
861 /* Force an initial interrupt */
862 if (!tg3_flag(tp, TAGGED_STATUS) &&
863 (tp->napi[0].hw_status->status & SD_STATUS_UPDATED))
864 tw32(GRC_LOCAL_CTRL, tp->grc_local_ctrl | GRC_LCLCTRL_SETINT);
866 tw32(HOSTCC_MODE, tp->coal_now);
868 tp->coal_now &= ~(tp->napi[0].coal_now | tp->napi[1].coal_now);
871 static inline unsigned int tg3_has_work(struct tg3_napi *tnapi)
873 struct tg3 *tp = tnapi->tp;
874 struct tg3_hw_status *sblk = tnapi->hw_status;
875 unsigned int work_exists = 0;
877 /* check for phy events */
878 if (!(tg3_flag(tp, USE_LINKCHG_REG) || tg3_flag(tp, POLL_SERDES))) {
879 if (sblk->status & SD_STATUS_LINK_CHG)
882 /* check for RX/TX work to do */
883 if (sblk->idx[0].tx_consumer != tnapi->tx_cons ||
884 *(tnapi->rx_rcb_prod_idx) != tnapi->rx_rcb_ptr)
891 * similar to tg3_enable_ints, but it accurately determines whether there
892 * is new work pending and can return without flushing the PIO write
893 * which reenables interrupts
895 static void tg3_int_reenable(struct tg3_napi *tnapi)
897 struct tg3 *tp = tnapi->tp;
899 tw32_mailbox(tnapi->int_mbox, tnapi->last_tag << 24);
902 /* When doing tagged status, this work check is unnecessary.
903 * The last_tag we write above tells the chip which piece of
904 * work we've completed.
906 if (!tg3_flag(tp, TAGGED_STATUS) && tg3_has_work(tnapi))
907 tw32(HOSTCC_MODE, tp->coalesce_mode |
908 HOSTCC_MODE_ENABLE | tnapi->coal_now);
911 static void tg3_switch_clocks(struct tg3 *tp)
916 if (tg3_flag(tp, CPMU_PRESENT) || tg3_flag(tp, 5780_CLASS))
919 clock_ctrl = tr32(TG3PCI_CLOCK_CTRL);
921 orig_clock_ctrl = clock_ctrl;
922 clock_ctrl &= (CLOCK_CTRL_FORCE_CLKRUN |
923 CLOCK_CTRL_CLKRUN_OENABLE |
925 tp->pci_clock_ctrl = clock_ctrl;
927 if (tg3_flag(tp, 5705_PLUS)) {
928 if (orig_clock_ctrl & CLOCK_CTRL_625_CORE) {
929 tw32_wait_f(TG3PCI_CLOCK_CTRL,
930 clock_ctrl | CLOCK_CTRL_625_CORE, 40);
932 } else if ((orig_clock_ctrl & CLOCK_CTRL_44MHZ_CORE) != 0) {
933 tw32_wait_f(TG3PCI_CLOCK_CTRL,
935 (CLOCK_CTRL_44MHZ_CORE | CLOCK_CTRL_ALTCLK),
937 tw32_wait_f(TG3PCI_CLOCK_CTRL,
938 clock_ctrl | (CLOCK_CTRL_ALTCLK),
941 tw32_wait_f(TG3PCI_CLOCK_CTRL, clock_ctrl, 40);
944 #define PHY_BUSY_LOOPS 5000
946 static int tg3_readphy(struct tg3 *tp, int reg, u32 *val)
952 if ((tp->mi_mode & MAC_MI_MODE_AUTO_POLL) != 0) {
954 (tp->mi_mode & ~MAC_MI_MODE_AUTO_POLL));
960 frame_val = ((tp->phy_addr << MI_COM_PHY_ADDR_SHIFT) &
961 MI_COM_PHY_ADDR_MASK);
962 frame_val |= ((reg << MI_COM_REG_ADDR_SHIFT) &
963 MI_COM_REG_ADDR_MASK);
964 frame_val |= (MI_COM_CMD_READ | MI_COM_START);
966 tw32_f(MAC_MI_COM, frame_val);
968 loops = PHY_BUSY_LOOPS;
971 frame_val = tr32(MAC_MI_COM);
973 if ((frame_val & MI_COM_BUSY) == 0) {
975 frame_val = tr32(MAC_MI_COM);
983 *val = frame_val & MI_COM_DATA_MASK;
987 if ((tp->mi_mode & MAC_MI_MODE_AUTO_POLL) != 0) {
988 tw32_f(MAC_MI_MODE, tp->mi_mode);
995 static int tg3_writephy(struct tg3 *tp, int reg, u32 val)
1001 if ((tp->phy_flags & TG3_PHYFLG_IS_FET) &&
1002 (reg == MII_CTRL1000 || reg == MII_TG3_AUX_CTRL))
1005 if ((tp->mi_mode & MAC_MI_MODE_AUTO_POLL) != 0) {
1007 (tp->mi_mode & ~MAC_MI_MODE_AUTO_POLL));
1011 frame_val = ((tp->phy_addr << MI_COM_PHY_ADDR_SHIFT) &
1012 MI_COM_PHY_ADDR_MASK);
1013 frame_val |= ((reg << MI_COM_REG_ADDR_SHIFT) &
1014 MI_COM_REG_ADDR_MASK);
1015 frame_val |= (val & MI_COM_DATA_MASK);
1016 frame_val |= (MI_COM_CMD_WRITE | MI_COM_START);
1018 tw32_f(MAC_MI_COM, frame_val);
1020 loops = PHY_BUSY_LOOPS;
1021 while (loops != 0) {
1023 frame_val = tr32(MAC_MI_COM);
1024 if ((frame_val & MI_COM_BUSY) == 0) {
1026 frame_val = tr32(MAC_MI_COM);
1036 if ((tp->mi_mode & MAC_MI_MODE_AUTO_POLL) != 0) {
1037 tw32_f(MAC_MI_MODE, tp->mi_mode);
1044 static int tg3_phy_cl45_write(struct tg3 *tp, u32 devad, u32 addr, u32 val)
1048 err = tg3_writephy(tp, MII_TG3_MMD_CTRL, devad);
1052 err = tg3_writephy(tp, MII_TG3_MMD_ADDRESS, addr);
1056 err = tg3_writephy(tp, MII_TG3_MMD_CTRL,
1057 MII_TG3_MMD_CTRL_DATA_NOINC | devad);
1061 err = tg3_writephy(tp, MII_TG3_MMD_ADDRESS, val);
1067 static int tg3_phy_cl45_read(struct tg3 *tp, u32 devad, u32 addr, u32 *val)
1071 err = tg3_writephy(tp, MII_TG3_MMD_CTRL, devad);
1075 err = tg3_writephy(tp, MII_TG3_MMD_ADDRESS, addr);
1079 err = tg3_writephy(tp, MII_TG3_MMD_CTRL,
1080 MII_TG3_MMD_CTRL_DATA_NOINC | devad);
1084 err = tg3_readphy(tp, MII_TG3_MMD_ADDRESS, val);
1090 static int tg3_phydsp_read(struct tg3 *tp, u32 reg, u32 *val)
1094 err = tg3_writephy(tp, MII_TG3_DSP_ADDRESS, reg);
1096 err = tg3_readphy(tp, MII_TG3_DSP_RW_PORT, val);
1101 static int tg3_phydsp_write(struct tg3 *tp, u32 reg, u32 val)
1105 err = tg3_writephy(tp, MII_TG3_DSP_ADDRESS, reg);
1107 err = tg3_writephy(tp, MII_TG3_DSP_RW_PORT, val);
1112 static int tg3_phy_auxctl_read(struct tg3 *tp, int reg, u32 *val)
1116 err = tg3_writephy(tp, MII_TG3_AUX_CTRL,
1117 (reg << MII_TG3_AUXCTL_MISC_RDSEL_SHIFT) |
1118 MII_TG3_AUXCTL_SHDWSEL_MISC);
1120 err = tg3_readphy(tp, MII_TG3_AUX_CTRL, val);
1125 static int tg3_phy_auxctl_write(struct tg3 *tp, int reg, u32 set)
1127 if (reg == MII_TG3_AUXCTL_SHDWSEL_MISC)
1128 set |= MII_TG3_AUXCTL_MISC_WREN;
1130 return tg3_writephy(tp, MII_TG3_AUX_CTRL, set | reg);
1133 #define TG3_PHY_AUXCTL_SMDSP_ENABLE(tp) \
1134 tg3_phy_auxctl_write((tp), MII_TG3_AUXCTL_SHDWSEL_AUXCTL, \
1135 MII_TG3_AUXCTL_ACTL_SMDSP_ENA | \
1136 MII_TG3_AUXCTL_ACTL_TX_6DB)
1138 #define TG3_PHY_AUXCTL_SMDSP_DISABLE(tp) \
1139 tg3_phy_auxctl_write((tp), MII_TG3_AUXCTL_SHDWSEL_AUXCTL, \
1140 MII_TG3_AUXCTL_ACTL_TX_6DB);
1142 static int tg3_bmcr_reset(struct tg3 *tp)
1147 /* OK, reset it, and poll the BMCR_RESET bit until it
1148 * clears or we time out.
1150 phy_control = BMCR_RESET;
1151 err = tg3_writephy(tp, MII_BMCR, phy_control);
1157 err = tg3_readphy(tp, MII_BMCR, &phy_control);
1161 if ((phy_control & BMCR_RESET) == 0) {
1173 static int tg3_mdio_read(struct mii_bus *bp, int mii_id, int reg)
1175 struct tg3 *tp = bp->priv;
1178 spin_lock_bh(&tp->lock);
1180 if (tg3_readphy(tp, reg, &val))
1183 spin_unlock_bh(&tp->lock);
1188 static int tg3_mdio_write(struct mii_bus *bp, int mii_id, int reg, u16 val)
1190 struct tg3 *tp = bp->priv;
1193 spin_lock_bh(&tp->lock);
1195 if (tg3_writephy(tp, reg, val))
1198 spin_unlock_bh(&tp->lock);
1203 static int tg3_mdio_reset(struct mii_bus *bp)
1208 static void tg3_mdio_config_5785(struct tg3 *tp)
1211 struct phy_device *phydev;
1213 phydev = tp->mdio_bus->phy_map[TG3_PHY_MII_ADDR];
1214 switch (phydev->drv->phy_id & phydev->drv->phy_id_mask) {
1215 case PHY_ID_BCM50610:
1216 case PHY_ID_BCM50610M:
1217 val = MAC_PHYCFG2_50610_LED_MODES;
1219 case PHY_ID_BCMAC131:
1220 val = MAC_PHYCFG2_AC131_LED_MODES;
1222 case PHY_ID_RTL8211C:
1223 val = MAC_PHYCFG2_RTL8211C_LED_MODES;
1225 case PHY_ID_RTL8201E:
1226 val = MAC_PHYCFG2_RTL8201E_LED_MODES;
1232 if (phydev->interface != PHY_INTERFACE_MODE_RGMII) {
1233 tw32(MAC_PHYCFG2, val);
1235 val = tr32(MAC_PHYCFG1);
1236 val &= ~(MAC_PHYCFG1_RGMII_INT |
1237 MAC_PHYCFG1_RXCLK_TO_MASK | MAC_PHYCFG1_TXCLK_TO_MASK);
1238 val |= MAC_PHYCFG1_RXCLK_TIMEOUT | MAC_PHYCFG1_TXCLK_TIMEOUT;
1239 tw32(MAC_PHYCFG1, val);
1244 if (!tg3_flag(tp, RGMII_INBAND_DISABLE))
1245 val |= MAC_PHYCFG2_EMODE_MASK_MASK |
1246 MAC_PHYCFG2_FMODE_MASK_MASK |
1247 MAC_PHYCFG2_GMODE_MASK_MASK |
1248 MAC_PHYCFG2_ACT_MASK_MASK |
1249 MAC_PHYCFG2_QUAL_MASK_MASK |
1250 MAC_PHYCFG2_INBAND_ENABLE;
1252 tw32(MAC_PHYCFG2, val);
1254 val = tr32(MAC_PHYCFG1);
1255 val &= ~(MAC_PHYCFG1_RXCLK_TO_MASK | MAC_PHYCFG1_TXCLK_TO_MASK |
1256 MAC_PHYCFG1_RGMII_EXT_RX_DEC | MAC_PHYCFG1_RGMII_SND_STAT_EN);
1257 if (!tg3_flag(tp, RGMII_INBAND_DISABLE)) {
1258 if (tg3_flag(tp, RGMII_EXT_IBND_RX_EN))
1259 val |= MAC_PHYCFG1_RGMII_EXT_RX_DEC;
1260 if (tg3_flag(tp, RGMII_EXT_IBND_TX_EN))
1261 val |= MAC_PHYCFG1_RGMII_SND_STAT_EN;
1263 val |= MAC_PHYCFG1_RXCLK_TIMEOUT | MAC_PHYCFG1_TXCLK_TIMEOUT |
1264 MAC_PHYCFG1_RGMII_INT | MAC_PHYCFG1_TXC_DRV;
1265 tw32(MAC_PHYCFG1, val);
1267 val = tr32(MAC_EXT_RGMII_MODE);
1268 val &= ~(MAC_RGMII_MODE_RX_INT_B |
1269 MAC_RGMII_MODE_RX_QUALITY |
1270 MAC_RGMII_MODE_RX_ACTIVITY |
1271 MAC_RGMII_MODE_RX_ENG_DET |
1272 MAC_RGMII_MODE_TX_ENABLE |
1273 MAC_RGMII_MODE_TX_LOWPWR |
1274 MAC_RGMII_MODE_TX_RESET);
1275 if (!tg3_flag(tp, RGMII_INBAND_DISABLE)) {
1276 if (tg3_flag(tp, RGMII_EXT_IBND_RX_EN))
1277 val |= MAC_RGMII_MODE_RX_INT_B |
1278 MAC_RGMII_MODE_RX_QUALITY |
1279 MAC_RGMII_MODE_RX_ACTIVITY |
1280 MAC_RGMII_MODE_RX_ENG_DET;
1281 if (tg3_flag(tp, RGMII_EXT_IBND_TX_EN))
1282 val |= MAC_RGMII_MODE_TX_ENABLE |
1283 MAC_RGMII_MODE_TX_LOWPWR |
1284 MAC_RGMII_MODE_TX_RESET;
1286 tw32(MAC_EXT_RGMII_MODE, val);
1289 static void tg3_mdio_start(struct tg3 *tp)
1291 tp->mi_mode &= ~MAC_MI_MODE_AUTO_POLL;
1292 tw32_f(MAC_MI_MODE, tp->mi_mode);
1295 if (tg3_flag(tp, MDIOBUS_INITED) &&
1296 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785)
1297 tg3_mdio_config_5785(tp);
1300 static int tg3_mdio_init(struct tg3 *tp)
1304 struct phy_device *phydev;
1306 if (tg3_flag(tp, 5717_PLUS)) {
1309 tp->phy_addr = tp->pci_fn + 1;
1311 if (tp->pci_chip_rev_id != CHIPREV_ID_5717_A0)
1312 is_serdes = tr32(SG_DIG_STATUS) & SG_DIG_IS_SERDES;
1314 is_serdes = tr32(TG3_CPMU_PHY_STRAP) &
1315 TG3_CPMU_PHY_STRAP_IS_SERDES;
1319 tp->phy_addr = TG3_PHY_MII_ADDR;
1323 if (!tg3_flag(tp, USE_PHYLIB) || tg3_flag(tp, MDIOBUS_INITED))
1326 tp->mdio_bus = mdiobus_alloc();
1327 if (tp->mdio_bus == NULL)
1330 tp->mdio_bus->name = "tg3 mdio bus";
1331 snprintf(tp->mdio_bus->id, MII_BUS_ID_SIZE, "%x",
1332 (tp->pdev->bus->number << 8) | tp->pdev->devfn);
1333 tp->mdio_bus->priv = tp;
1334 tp->mdio_bus->parent = &tp->pdev->dev;
1335 tp->mdio_bus->read = &tg3_mdio_read;
1336 tp->mdio_bus->write = &tg3_mdio_write;
1337 tp->mdio_bus->reset = &tg3_mdio_reset;
1338 tp->mdio_bus->phy_mask = ~(1 << TG3_PHY_MII_ADDR);
1339 tp->mdio_bus->irq = &tp->mdio_irq[0];
1341 for (i = 0; i < PHY_MAX_ADDR; i++)
1342 tp->mdio_bus->irq[i] = PHY_POLL;
1344 /* The bus registration will look for all the PHYs on the mdio bus.
1345 * Unfortunately, it does not ensure the PHY is powered up before
1346 * accessing the PHY ID registers. A chip reset is the
1347 * quickest way to bring the device back to an operational state..
1349 if (tg3_readphy(tp, MII_BMCR, ®) || (reg & BMCR_PDOWN))
1352 i = mdiobus_register(tp->mdio_bus);
1354 dev_warn(&tp->pdev->dev, "mdiobus_reg failed (0x%x)\n", i);
1355 mdiobus_free(tp->mdio_bus);
1359 phydev = tp->mdio_bus->phy_map[TG3_PHY_MII_ADDR];
1361 if (!phydev || !phydev->drv) {
1362 dev_warn(&tp->pdev->dev, "No PHY devices\n");
1363 mdiobus_unregister(tp->mdio_bus);
1364 mdiobus_free(tp->mdio_bus);
1368 switch (phydev->drv->phy_id & phydev->drv->phy_id_mask) {
1369 case PHY_ID_BCM57780:
1370 phydev->interface = PHY_INTERFACE_MODE_GMII;
1371 phydev->dev_flags |= PHY_BRCM_AUTO_PWRDWN_ENABLE;
1373 case PHY_ID_BCM50610:
1374 case PHY_ID_BCM50610M:
1375 phydev->dev_flags |= PHY_BRCM_CLEAR_RGMII_MODE |
1376 PHY_BRCM_RX_REFCLK_UNUSED |
1377 PHY_BRCM_DIS_TXCRXC_NOENRGY |
1378 PHY_BRCM_AUTO_PWRDWN_ENABLE;
1379 if (tg3_flag(tp, RGMII_INBAND_DISABLE))
1380 phydev->dev_flags |= PHY_BRCM_STD_IBND_DISABLE;
1381 if (tg3_flag(tp, RGMII_EXT_IBND_RX_EN))
1382 phydev->dev_flags |= PHY_BRCM_EXT_IBND_RX_ENABLE;
1383 if (tg3_flag(tp, RGMII_EXT_IBND_TX_EN))
1384 phydev->dev_flags |= PHY_BRCM_EXT_IBND_TX_ENABLE;
1386 case PHY_ID_RTL8211C:
1387 phydev->interface = PHY_INTERFACE_MODE_RGMII;
1389 case PHY_ID_RTL8201E:
1390 case PHY_ID_BCMAC131:
1391 phydev->interface = PHY_INTERFACE_MODE_MII;
1392 phydev->dev_flags |= PHY_BRCM_AUTO_PWRDWN_ENABLE;
1393 tp->phy_flags |= TG3_PHYFLG_IS_FET;
1397 tg3_flag_set(tp, MDIOBUS_INITED);
1399 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785)
1400 tg3_mdio_config_5785(tp);
1405 static void tg3_mdio_fini(struct tg3 *tp)
1407 if (tg3_flag(tp, MDIOBUS_INITED)) {
1408 tg3_flag_clear(tp, MDIOBUS_INITED);
1409 mdiobus_unregister(tp->mdio_bus);
1410 mdiobus_free(tp->mdio_bus);
1414 /* tp->lock is held. */
1415 static inline void tg3_generate_fw_event(struct tg3 *tp)
1419 val = tr32(GRC_RX_CPU_EVENT);
1420 val |= GRC_RX_CPU_DRIVER_EVENT;
1421 tw32_f(GRC_RX_CPU_EVENT, val);
1423 tp->last_event_jiffies = jiffies;
1426 #define TG3_FW_EVENT_TIMEOUT_USEC 2500
1428 /* tp->lock is held. */
1429 static void tg3_wait_for_event_ack(struct tg3 *tp)
1432 unsigned int delay_cnt;
1435 /* If enough time has passed, no wait is necessary. */
1436 time_remain = (long)(tp->last_event_jiffies + 1 +
1437 usecs_to_jiffies(TG3_FW_EVENT_TIMEOUT_USEC)) -
1439 if (time_remain < 0)
1442 /* Check if we can shorten the wait time. */
1443 delay_cnt = jiffies_to_usecs(time_remain);
1444 if (delay_cnt > TG3_FW_EVENT_TIMEOUT_USEC)
1445 delay_cnt = TG3_FW_EVENT_TIMEOUT_USEC;
1446 delay_cnt = (delay_cnt >> 3) + 1;
1448 for (i = 0; i < delay_cnt; i++) {
1449 if (!(tr32(GRC_RX_CPU_EVENT) & GRC_RX_CPU_DRIVER_EVENT))
1455 /* tp->lock is held. */
1456 static void tg3_ump_link_report(struct tg3 *tp)
1461 if (!tg3_flag(tp, 5780_CLASS) || !tg3_flag(tp, ENABLE_ASF))
1464 tg3_wait_for_event_ack(tp);
1466 tg3_write_mem(tp, NIC_SRAM_FW_CMD_MBOX, FWCMD_NICDRV_LINK_UPDATE);
1468 tg3_write_mem(tp, NIC_SRAM_FW_CMD_LEN_MBOX, 14);
1471 if (!tg3_readphy(tp, MII_BMCR, ®))
1473 if (!tg3_readphy(tp, MII_BMSR, ®))
1474 val |= (reg & 0xffff);
1475 tg3_write_mem(tp, NIC_SRAM_FW_CMD_DATA_MBOX, val);
1478 if (!tg3_readphy(tp, MII_ADVERTISE, ®))
1480 if (!tg3_readphy(tp, MII_LPA, ®))
1481 val |= (reg & 0xffff);
1482 tg3_write_mem(tp, NIC_SRAM_FW_CMD_DATA_MBOX + 4, val);
1485 if (!(tp->phy_flags & TG3_PHYFLG_MII_SERDES)) {
1486 if (!tg3_readphy(tp, MII_CTRL1000, ®))
1488 if (!tg3_readphy(tp, MII_STAT1000, ®))
1489 val |= (reg & 0xffff);
1491 tg3_write_mem(tp, NIC_SRAM_FW_CMD_DATA_MBOX + 8, val);
1493 if (!tg3_readphy(tp, MII_PHYADDR, ®))
1497 tg3_write_mem(tp, NIC_SRAM_FW_CMD_DATA_MBOX + 12, val);
1499 tg3_generate_fw_event(tp);
1502 /* tp->lock is held. */
1503 static void tg3_stop_fw(struct tg3 *tp)
1505 if (tg3_flag(tp, ENABLE_ASF) && !tg3_flag(tp, ENABLE_APE)) {
1506 /* Wait for RX cpu to ACK the previous event. */
1507 tg3_wait_for_event_ack(tp);
1509 tg3_write_mem(tp, NIC_SRAM_FW_CMD_MBOX, FWCMD_NICDRV_PAUSE_FW);
1511 tg3_generate_fw_event(tp);
1513 /* Wait for RX cpu to ACK this event. */
1514 tg3_wait_for_event_ack(tp);
1518 /* tp->lock is held. */
1519 static void tg3_write_sig_pre_reset(struct tg3 *tp, int kind)
1521 tg3_write_mem(tp, NIC_SRAM_FIRMWARE_MBOX,
1522 NIC_SRAM_FIRMWARE_MBOX_MAGIC1);
1524 if (tg3_flag(tp, ASF_NEW_HANDSHAKE)) {
1526 case RESET_KIND_INIT:
1527 tg3_write_mem(tp, NIC_SRAM_FW_DRV_STATE_MBOX,
1531 case RESET_KIND_SHUTDOWN:
1532 tg3_write_mem(tp, NIC_SRAM_FW_DRV_STATE_MBOX,
1536 case RESET_KIND_SUSPEND:
1537 tg3_write_mem(tp, NIC_SRAM_FW_DRV_STATE_MBOX,
1546 if (kind == RESET_KIND_INIT ||
1547 kind == RESET_KIND_SUSPEND)
1548 tg3_ape_driver_state_change(tp, kind);
1551 /* tp->lock is held. */
1552 static void tg3_write_sig_post_reset(struct tg3 *tp, int kind)
1554 if (tg3_flag(tp, ASF_NEW_HANDSHAKE)) {
1556 case RESET_KIND_INIT:
1557 tg3_write_mem(tp, NIC_SRAM_FW_DRV_STATE_MBOX,
1558 DRV_STATE_START_DONE);
1561 case RESET_KIND_SHUTDOWN:
1562 tg3_write_mem(tp, NIC_SRAM_FW_DRV_STATE_MBOX,
1563 DRV_STATE_UNLOAD_DONE);
1571 if (kind == RESET_KIND_SHUTDOWN)
1572 tg3_ape_driver_state_change(tp, kind);
1575 /* tp->lock is held. */
1576 static void tg3_write_sig_legacy(struct tg3 *tp, int kind)
1578 if (tg3_flag(tp, ENABLE_ASF)) {
1580 case RESET_KIND_INIT:
1581 tg3_write_mem(tp, NIC_SRAM_FW_DRV_STATE_MBOX,
1585 case RESET_KIND_SHUTDOWN:
1586 tg3_write_mem(tp, NIC_SRAM_FW_DRV_STATE_MBOX,
1590 case RESET_KIND_SUSPEND:
1591 tg3_write_mem(tp, NIC_SRAM_FW_DRV_STATE_MBOX,
1601 static int tg3_poll_fw(struct tg3 *tp)
1606 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
1607 /* Wait up to 20ms for init done. */
1608 for (i = 0; i < 200; i++) {
1609 if (tr32(VCPU_STATUS) & VCPU_STATUS_INIT_DONE)
1616 /* Wait for firmware initialization to complete. */
1617 for (i = 0; i < 100000; i++) {
1618 tg3_read_mem(tp, NIC_SRAM_FIRMWARE_MBOX, &val);
1619 if (val == ~NIC_SRAM_FIRMWARE_MBOX_MAGIC1)
1624 /* Chip might not be fitted with firmware. Some Sun onboard
1625 * parts are configured like that. So don't signal the timeout
1626 * of the above loop as an error, but do report the lack of
1627 * running firmware once.
1629 if (i >= 100000 && !tg3_flag(tp, NO_FWARE_REPORTED)) {
1630 tg3_flag_set(tp, NO_FWARE_REPORTED);
1632 netdev_info(tp->dev, "No firmware running\n");
1635 if (tp->pci_chip_rev_id == CHIPREV_ID_57765_A0) {
1636 /* The 57765 A0 needs a little more
1637 * time to do some important work.
1645 static void tg3_link_report(struct tg3 *tp)
1647 if (!netif_carrier_ok(tp->dev)) {
1648 netif_info(tp, link, tp->dev, "Link is down\n");
1649 tg3_ump_link_report(tp);
1650 } else if (netif_msg_link(tp)) {
1651 netdev_info(tp->dev, "Link is up at %d Mbps, %s duplex\n",
1652 (tp->link_config.active_speed == SPEED_1000 ?
1654 (tp->link_config.active_speed == SPEED_100 ?
1656 (tp->link_config.active_duplex == DUPLEX_FULL ?
1659 netdev_info(tp->dev, "Flow control is %s for TX and %s for RX\n",
1660 (tp->link_config.active_flowctrl & FLOW_CTRL_TX) ?
1662 (tp->link_config.active_flowctrl & FLOW_CTRL_RX) ?
1665 if (tp->phy_flags & TG3_PHYFLG_EEE_CAP)
1666 netdev_info(tp->dev, "EEE is %s\n",
1667 tp->setlpicnt ? "enabled" : "disabled");
1669 tg3_ump_link_report(tp);
1673 static u16 tg3_advert_flowctrl_1000X(u8 flow_ctrl)
1677 if ((flow_ctrl & FLOW_CTRL_TX) && (flow_ctrl & FLOW_CTRL_RX))
1678 miireg = ADVERTISE_1000XPAUSE;
1679 else if (flow_ctrl & FLOW_CTRL_TX)
1680 miireg = ADVERTISE_1000XPSE_ASYM;
1681 else if (flow_ctrl & FLOW_CTRL_RX)
1682 miireg = ADVERTISE_1000XPAUSE | ADVERTISE_1000XPSE_ASYM;
1689 static u8 tg3_resolve_flowctrl_1000X(u16 lcladv, u16 rmtadv)
1693 if (lcladv & rmtadv & ADVERTISE_1000XPAUSE) {
1694 cap = FLOW_CTRL_TX | FLOW_CTRL_RX;
1695 } else if (lcladv & rmtadv & ADVERTISE_1000XPSE_ASYM) {
1696 if (lcladv & ADVERTISE_1000XPAUSE)
1698 if (rmtadv & ADVERTISE_1000XPAUSE)
1705 static void tg3_setup_flow_control(struct tg3 *tp, u32 lcladv, u32 rmtadv)
1709 u32 old_rx_mode = tp->rx_mode;
1710 u32 old_tx_mode = tp->tx_mode;
1712 if (tg3_flag(tp, USE_PHYLIB))
1713 autoneg = tp->mdio_bus->phy_map[TG3_PHY_MII_ADDR]->autoneg;
1715 autoneg = tp->link_config.autoneg;
1717 if (autoneg == AUTONEG_ENABLE && tg3_flag(tp, PAUSE_AUTONEG)) {
1718 if (tp->phy_flags & TG3_PHYFLG_ANY_SERDES)
1719 flowctrl = tg3_resolve_flowctrl_1000X(lcladv, rmtadv);
1721 flowctrl = mii_resolve_flowctrl_fdx(lcladv, rmtadv);
1723 flowctrl = tp->link_config.flowctrl;
1725 tp->link_config.active_flowctrl = flowctrl;
1727 if (flowctrl & FLOW_CTRL_RX)
1728 tp->rx_mode |= RX_MODE_FLOW_CTRL_ENABLE;
1730 tp->rx_mode &= ~RX_MODE_FLOW_CTRL_ENABLE;
1732 if (old_rx_mode != tp->rx_mode)
1733 tw32_f(MAC_RX_MODE, tp->rx_mode);
1735 if (flowctrl & FLOW_CTRL_TX)
1736 tp->tx_mode |= TX_MODE_FLOW_CTRL_ENABLE;
1738 tp->tx_mode &= ~TX_MODE_FLOW_CTRL_ENABLE;
1740 if (old_tx_mode != tp->tx_mode)
1741 tw32_f(MAC_TX_MODE, tp->tx_mode);
1744 static void tg3_adjust_link(struct net_device *dev)
1746 u8 oldflowctrl, linkmesg = 0;
1747 u32 mac_mode, lcl_adv, rmt_adv;
1748 struct tg3 *tp = netdev_priv(dev);
1749 struct phy_device *phydev = tp->mdio_bus->phy_map[TG3_PHY_MII_ADDR];
1751 spin_lock_bh(&tp->lock);
1753 mac_mode = tp->mac_mode & ~(MAC_MODE_PORT_MODE_MASK |
1754 MAC_MODE_HALF_DUPLEX);
1756 oldflowctrl = tp->link_config.active_flowctrl;
1762 if (phydev->speed == SPEED_100 || phydev->speed == SPEED_10)
1763 mac_mode |= MAC_MODE_PORT_MODE_MII;
1764 else if (phydev->speed == SPEED_1000 ||
1765 GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5785)
1766 mac_mode |= MAC_MODE_PORT_MODE_GMII;
1768 mac_mode |= MAC_MODE_PORT_MODE_MII;
1770 if (phydev->duplex == DUPLEX_HALF)
1771 mac_mode |= MAC_MODE_HALF_DUPLEX;
1773 lcl_adv = mii_advertise_flowctrl(
1774 tp->link_config.flowctrl);
1777 rmt_adv = LPA_PAUSE_CAP;
1778 if (phydev->asym_pause)
1779 rmt_adv |= LPA_PAUSE_ASYM;
1782 tg3_setup_flow_control(tp, lcl_adv, rmt_adv);
1784 mac_mode |= MAC_MODE_PORT_MODE_GMII;
1786 if (mac_mode != tp->mac_mode) {
1787 tp->mac_mode = mac_mode;
1788 tw32_f(MAC_MODE, tp->mac_mode);
1792 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785) {
1793 if (phydev->speed == SPEED_10)
1795 MAC_MI_STAT_10MBPS_MODE |
1796 MAC_MI_STAT_LNKSTAT_ATTN_ENAB);
1798 tw32(MAC_MI_STAT, MAC_MI_STAT_LNKSTAT_ATTN_ENAB);
1801 if (phydev->speed == SPEED_1000 && phydev->duplex == DUPLEX_HALF)
1802 tw32(MAC_TX_LENGTHS,
1803 ((2 << TX_LENGTHS_IPG_CRS_SHIFT) |
1804 (6 << TX_LENGTHS_IPG_SHIFT) |
1805 (0xff << TX_LENGTHS_SLOT_TIME_SHIFT)));
1807 tw32(MAC_TX_LENGTHS,
1808 ((2 << TX_LENGTHS_IPG_CRS_SHIFT) |
1809 (6 << TX_LENGTHS_IPG_SHIFT) |
1810 (32 << TX_LENGTHS_SLOT_TIME_SHIFT)));
1812 if ((phydev->link && tp->link_config.active_speed == SPEED_INVALID) ||
1813 (!phydev->link && tp->link_config.active_speed != SPEED_INVALID) ||
1814 phydev->speed != tp->link_config.active_speed ||
1815 phydev->duplex != tp->link_config.active_duplex ||
1816 oldflowctrl != tp->link_config.active_flowctrl)
1819 tp->link_config.active_speed = phydev->speed;
1820 tp->link_config.active_duplex = phydev->duplex;
1822 spin_unlock_bh(&tp->lock);
1825 tg3_link_report(tp);
1828 static int tg3_phy_init(struct tg3 *tp)
1830 struct phy_device *phydev;
1832 if (tp->phy_flags & TG3_PHYFLG_IS_CONNECTED)
1835 /* Bring the PHY back to a known state. */
1838 phydev = tp->mdio_bus->phy_map[TG3_PHY_MII_ADDR];
1840 /* Attach the MAC to the PHY. */
1841 phydev = phy_connect(tp->dev, dev_name(&phydev->dev), tg3_adjust_link,
1842 phydev->dev_flags, phydev->interface);
1843 if (IS_ERR(phydev)) {
1844 dev_err(&tp->pdev->dev, "Could not attach to PHY\n");
1845 return PTR_ERR(phydev);
1848 /* Mask with MAC supported features. */
1849 switch (phydev->interface) {
1850 case PHY_INTERFACE_MODE_GMII:
1851 case PHY_INTERFACE_MODE_RGMII:
1852 if (!(tp->phy_flags & TG3_PHYFLG_10_100_ONLY)) {
1853 phydev->supported &= (PHY_GBIT_FEATURES |
1855 SUPPORTED_Asym_Pause);
1859 case PHY_INTERFACE_MODE_MII:
1860 phydev->supported &= (PHY_BASIC_FEATURES |
1862 SUPPORTED_Asym_Pause);
1865 phy_disconnect(tp->mdio_bus->phy_map[TG3_PHY_MII_ADDR]);
1869 tp->phy_flags |= TG3_PHYFLG_IS_CONNECTED;
1871 phydev->advertising = phydev->supported;
1876 static void tg3_phy_start(struct tg3 *tp)
1878 struct phy_device *phydev;
1880 if (!(tp->phy_flags & TG3_PHYFLG_IS_CONNECTED))
1883 phydev = tp->mdio_bus->phy_map[TG3_PHY_MII_ADDR];
1885 if (tp->phy_flags & TG3_PHYFLG_IS_LOW_POWER) {
1886 tp->phy_flags &= ~TG3_PHYFLG_IS_LOW_POWER;
1887 phydev->speed = tp->link_config.orig_speed;
1888 phydev->duplex = tp->link_config.orig_duplex;
1889 phydev->autoneg = tp->link_config.orig_autoneg;
1890 phydev->advertising = tp->link_config.orig_advertising;
1895 phy_start_aneg(phydev);
1898 static void tg3_phy_stop(struct tg3 *tp)
1900 if (!(tp->phy_flags & TG3_PHYFLG_IS_CONNECTED))
1903 phy_stop(tp->mdio_bus->phy_map[TG3_PHY_MII_ADDR]);
1906 static void tg3_phy_fini(struct tg3 *tp)
1908 if (tp->phy_flags & TG3_PHYFLG_IS_CONNECTED) {
1909 phy_disconnect(tp->mdio_bus->phy_map[TG3_PHY_MII_ADDR]);
1910 tp->phy_flags &= ~TG3_PHYFLG_IS_CONNECTED;
1914 static int tg3_phy_set_extloopbk(struct tg3 *tp)
1919 if (tp->phy_flags & TG3_PHYFLG_IS_FET)
1922 if ((tp->phy_id & TG3_PHY_ID_MASK) == TG3_PHY_ID_BCM5401) {
1923 /* Cannot do read-modify-write on 5401 */
1924 err = tg3_phy_auxctl_write(tp,
1925 MII_TG3_AUXCTL_SHDWSEL_AUXCTL,
1926 MII_TG3_AUXCTL_ACTL_EXTLOOPBK |
1931 err = tg3_phy_auxctl_read(tp,
1932 MII_TG3_AUXCTL_SHDWSEL_AUXCTL, &val);
1936 val |= MII_TG3_AUXCTL_ACTL_EXTLOOPBK;
1937 err = tg3_phy_auxctl_write(tp,
1938 MII_TG3_AUXCTL_SHDWSEL_AUXCTL, val);
1944 static void tg3_phy_fet_toggle_apd(struct tg3 *tp, bool enable)
1948 if (!tg3_readphy(tp, MII_TG3_FET_TEST, &phytest)) {
1951 tg3_writephy(tp, MII_TG3_FET_TEST,
1952 phytest | MII_TG3_FET_SHADOW_EN);
1953 if (!tg3_readphy(tp, MII_TG3_FET_SHDW_AUXSTAT2, &phy)) {
1955 phy |= MII_TG3_FET_SHDW_AUXSTAT2_APD;
1957 phy &= ~MII_TG3_FET_SHDW_AUXSTAT2_APD;
1958 tg3_writephy(tp, MII_TG3_FET_SHDW_AUXSTAT2, phy);
1960 tg3_writephy(tp, MII_TG3_FET_TEST, phytest);
1964 static void tg3_phy_toggle_apd(struct tg3 *tp, bool enable)
1968 if (!tg3_flag(tp, 5705_PLUS) ||
1969 (tg3_flag(tp, 5717_PLUS) &&
1970 (tp->phy_flags & TG3_PHYFLG_MII_SERDES)))
1973 if (tp->phy_flags & TG3_PHYFLG_IS_FET) {
1974 tg3_phy_fet_toggle_apd(tp, enable);
1978 reg = MII_TG3_MISC_SHDW_WREN |
1979 MII_TG3_MISC_SHDW_SCR5_SEL |
1980 MII_TG3_MISC_SHDW_SCR5_LPED |
1981 MII_TG3_MISC_SHDW_SCR5_DLPTLM |
1982 MII_TG3_MISC_SHDW_SCR5_SDTL |
1983 MII_TG3_MISC_SHDW_SCR5_C125OE;
1984 if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5784 || !enable)
1985 reg |= MII_TG3_MISC_SHDW_SCR5_DLLAPD;
1987 tg3_writephy(tp, MII_TG3_MISC_SHDW, reg);
1990 reg = MII_TG3_MISC_SHDW_WREN |
1991 MII_TG3_MISC_SHDW_APD_SEL |
1992 MII_TG3_MISC_SHDW_APD_WKTM_84MS;
1994 reg |= MII_TG3_MISC_SHDW_APD_ENABLE;
1996 tg3_writephy(tp, MII_TG3_MISC_SHDW, reg);
1999 static void tg3_phy_toggle_automdix(struct tg3 *tp, int enable)
2003 if (!tg3_flag(tp, 5705_PLUS) ||
2004 (tp->phy_flags & TG3_PHYFLG_ANY_SERDES))
2007 if (tp->phy_flags & TG3_PHYFLG_IS_FET) {
2010 if (!tg3_readphy(tp, MII_TG3_FET_TEST, &ephy)) {
2011 u32 reg = MII_TG3_FET_SHDW_MISCCTRL;
2013 tg3_writephy(tp, MII_TG3_FET_TEST,
2014 ephy | MII_TG3_FET_SHADOW_EN);
2015 if (!tg3_readphy(tp, reg, &phy)) {
2017 phy |= MII_TG3_FET_SHDW_MISCCTRL_MDIX;
2019 phy &= ~MII_TG3_FET_SHDW_MISCCTRL_MDIX;
2020 tg3_writephy(tp, reg, phy);
2022 tg3_writephy(tp, MII_TG3_FET_TEST, ephy);
2027 ret = tg3_phy_auxctl_read(tp,
2028 MII_TG3_AUXCTL_SHDWSEL_MISC, &phy);
2031 phy |= MII_TG3_AUXCTL_MISC_FORCE_AMDIX;
2033 phy &= ~MII_TG3_AUXCTL_MISC_FORCE_AMDIX;
2034 tg3_phy_auxctl_write(tp,
2035 MII_TG3_AUXCTL_SHDWSEL_MISC, phy);
2040 static void tg3_phy_set_wirespeed(struct tg3 *tp)
2045 if (tp->phy_flags & TG3_PHYFLG_NO_ETH_WIRE_SPEED)
2048 ret = tg3_phy_auxctl_read(tp, MII_TG3_AUXCTL_SHDWSEL_MISC, &val);
2050 tg3_phy_auxctl_write(tp, MII_TG3_AUXCTL_SHDWSEL_MISC,
2051 val | MII_TG3_AUXCTL_MISC_WIRESPD_EN);
2054 static void tg3_phy_apply_otp(struct tg3 *tp)
2063 if (TG3_PHY_AUXCTL_SMDSP_ENABLE(tp))
2066 phy = ((otp & TG3_OTP_AGCTGT_MASK) >> TG3_OTP_AGCTGT_SHIFT);
2067 phy |= MII_TG3_DSP_TAP1_AGCTGT_DFLT;
2068 tg3_phydsp_write(tp, MII_TG3_DSP_TAP1, phy);
2070 phy = ((otp & TG3_OTP_HPFFLTR_MASK) >> TG3_OTP_HPFFLTR_SHIFT) |
2071 ((otp & TG3_OTP_HPFOVER_MASK) >> TG3_OTP_HPFOVER_SHIFT);
2072 tg3_phydsp_write(tp, MII_TG3_DSP_AADJ1CH0, phy);
2074 phy = ((otp & TG3_OTP_LPFDIS_MASK) >> TG3_OTP_LPFDIS_SHIFT);
2075 phy |= MII_TG3_DSP_AADJ1CH3_ADCCKADJ;
2076 tg3_phydsp_write(tp, MII_TG3_DSP_AADJ1CH3, phy);
2078 phy = ((otp & TG3_OTP_VDAC_MASK) >> TG3_OTP_VDAC_SHIFT);
2079 tg3_phydsp_write(tp, MII_TG3_DSP_EXP75, phy);
2081 phy = ((otp & TG3_OTP_10BTAMP_MASK) >> TG3_OTP_10BTAMP_SHIFT);
2082 tg3_phydsp_write(tp, MII_TG3_DSP_EXP96, phy);
2084 phy = ((otp & TG3_OTP_ROFF_MASK) >> TG3_OTP_ROFF_SHIFT) |
2085 ((otp & TG3_OTP_RCOFF_MASK) >> TG3_OTP_RCOFF_SHIFT);
2086 tg3_phydsp_write(tp, MII_TG3_DSP_EXP97, phy);
2088 TG3_PHY_AUXCTL_SMDSP_DISABLE(tp);
2091 static void tg3_phy_eee_adjust(struct tg3 *tp, u32 current_link_up)
2095 if (!(tp->phy_flags & TG3_PHYFLG_EEE_CAP))
2100 if (tp->link_config.autoneg == AUTONEG_ENABLE &&
2101 current_link_up == 1 &&
2102 tp->link_config.active_duplex == DUPLEX_FULL &&
2103 (tp->link_config.active_speed == SPEED_100 ||
2104 tp->link_config.active_speed == SPEED_1000)) {
2107 if (tp->link_config.active_speed == SPEED_1000)
2108 eeectl = TG3_CPMU_EEE_CTRL_EXIT_16_5_US;
2110 eeectl = TG3_CPMU_EEE_CTRL_EXIT_36_US;
2112 tw32(TG3_CPMU_EEE_CTRL, eeectl);
2114 tg3_phy_cl45_read(tp, MDIO_MMD_AN,
2115 TG3_CL45_D7_EEERES_STAT, &val);
2117 if (val == TG3_CL45_D7_EEERES_STAT_LP_1000T ||
2118 val == TG3_CL45_D7_EEERES_STAT_LP_100TX)
2122 if (!tp->setlpicnt) {
2123 if (current_link_up == 1 &&
2124 !TG3_PHY_AUXCTL_SMDSP_ENABLE(tp)) {
2125 tg3_phydsp_write(tp, MII_TG3_DSP_TAP26, 0x0000);
2126 TG3_PHY_AUXCTL_SMDSP_DISABLE(tp);
2129 val = tr32(TG3_CPMU_EEE_MODE);
2130 tw32(TG3_CPMU_EEE_MODE, val & ~TG3_CPMU_EEEMD_LPI_ENABLE);
2134 static void tg3_phy_eee_enable(struct tg3 *tp)
2138 if (tp->link_config.active_speed == SPEED_1000 &&
2139 (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717 ||
2140 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5719 ||
2141 tg3_flag(tp, 57765_CLASS)) &&
2142 !TG3_PHY_AUXCTL_SMDSP_ENABLE(tp)) {
2143 val = MII_TG3_DSP_TAP26_ALNOKO |
2144 MII_TG3_DSP_TAP26_RMRXSTO;
2145 tg3_phydsp_write(tp, MII_TG3_DSP_TAP26, val);
2146 TG3_PHY_AUXCTL_SMDSP_DISABLE(tp);
2149 val = tr32(TG3_CPMU_EEE_MODE);
2150 tw32(TG3_CPMU_EEE_MODE, val | TG3_CPMU_EEEMD_LPI_ENABLE);
2153 static int tg3_wait_macro_done(struct tg3 *tp)
2160 if (!tg3_readphy(tp, MII_TG3_DSP_CONTROL, &tmp32)) {
2161 if ((tmp32 & 0x1000) == 0)
2171 static int tg3_phy_write_and_check_testpat(struct tg3 *tp, int *resetp)
2173 static const u32 test_pat[4][6] = {
2174 { 0x00005555, 0x00000005, 0x00002aaa, 0x0000000a, 0x00003456, 0x00000003 },
2175 { 0x00002aaa, 0x0000000a, 0x00003333, 0x00000003, 0x0000789a, 0x00000005 },
2176 { 0x00005a5a, 0x00000005, 0x00002a6a, 0x0000000a, 0x00001bcd, 0x00000003 },
2177 { 0x00002a5a, 0x0000000a, 0x000033c3, 0x00000003, 0x00002ef1, 0x00000005 }
2181 for (chan = 0; chan < 4; chan++) {
2184 tg3_writephy(tp, MII_TG3_DSP_ADDRESS,
2185 (chan * 0x2000) | 0x0200);
2186 tg3_writephy(tp, MII_TG3_DSP_CONTROL, 0x0002);
2188 for (i = 0; i < 6; i++)
2189 tg3_writephy(tp, MII_TG3_DSP_RW_PORT,
2192 tg3_writephy(tp, MII_TG3_DSP_CONTROL, 0x0202);
2193 if (tg3_wait_macro_done(tp)) {
2198 tg3_writephy(tp, MII_TG3_DSP_ADDRESS,
2199 (chan * 0x2000) | 0x0200);
2200 tg3_writephy(tp, MII_TG3_DSP_CONTROL, 0x0082);
2201 if (tg3_wait_macro_done(tp)) {
2206 tg3_writephy(tp, MII_TG3_DSP_CONTROL, 0x0802);
2207 if (tg3_wait_macro_done(tp)) {
2212 for (i = 0; i < 6; i += 2) {
2215 if (tg3_readphy(tp, MII_TG3_DSP_RW_PORT, &low) ||
2216 tg3_readphy(tp, MII_TG3_DSP_RW_PORT, &high) ||
2217 tg3_wait_macro_done(tp)) {
2223 if (low != test_pat[chan][i] ||
2224 high != test_pat[chan][i+1]) {
2225 tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x000b);
2226 tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x4001);
2227 tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x4005);
2237 static int tg3_phy_reset_chanpat(struct tg3 *tp)
2241 for (chan = 0; chan < 4; chan++) {
2244 tg3_writephy(tp, MII_TG3_DSP_ADDRESS,
2245 (chan * 0x2000) | 0x0200);
2246 tg3_writephy(tp, MII_TG3_DSP_CONTROL, 0x0002);
2247 for (i = 0; i < 6; i++)
2248 tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x000);
2249 tg3_writephy(tp, MII_TG3_DSP_CONTROL, 0x0202);
2250 if (tg3_wait_macro_done(tp))
2257 static int tg3_phy_reset_5703_4_5(struct tg3 *tp)
2259 u32 reg32, phy9_orig;
2260 int retries, do_phy_reset, err;
2266 err = tg3_bmcr_reset(tp);
2272 /* Disable transmitter and interrupt. */
2273 if (tg3_readphy(tp, MII_TG3_EXT_CTRL, ®32))
2277 tg3_writephy(tp, MII_TG3_EXT_CTRL, reg32);
2279 /* Set full-duplex, 1000 mbps. */
2280 tg3_writephy(tp, MII_BMCR,
2281 BMCR_FULLDPLX | BMCR_SPEED1000);
2283 /* Set to master mode. */
2284 if (tg3_readphy(tp, MII_CTRL1000, &phy9_orig))
2287 tg3_writephy(tp, MII_CTRL1000,
2288 CTL1000_AS_MASTER | CTL1000_ENABLE_MASTER);
2290 err = TG3_PHY_AUXCTL_SMDSP_ENABLE(tp);
2294 /* Block the PHY control access. */
2295 tg3_phydsp_write(tp, 0x8005, 0x0800);
2297 err = tg3_phy_write_and_check_testpat(tp, &do_phy_reset);
2300 } while (--retries);
2302 err = tg3_phy_reset_chanpat(tp);
2306 tg3_phydsp_write(tp, 0x8005, 0x0000);
2308 tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x8200);
2309 tg3_writephy(tp, MII_TG3_DSP_CONTROL, 0x0000);
2311 TG3_PHY_AUXCTL_SMDSP_DISABLE(tp);
2313 tg3_writephy(tp, MII_CTRL1000, phy9_orig);
2315 if (!tg3_readphy(tp, MII_TG3_EXT_CTRL, ®32)) {
2317 tg3_writephy(tp, MII_TG3_EXT_CTRL, reg32);
2324 /* This will reset the tigon3 PHY if there is no valid
2325 * link unless the FORCE argument is non-zero.
2327 static int tg3_phy_reset(struct tg3 *tp)
2332 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
2333 val = tr32(GRC_MISC_CFG);
2334 tw32_f(GRC_MISC_CFG, val & ~GRC_MISC_CFG_EPHY_IDDQ);
2337 err = tg3_readphy(tp, MII_BMSR, &val);
2338 err |= tg3_readphy(tp, MII_BMSR, &val);
2342 if (netif_running(tp->dev) && netif_carrier_ok(tp->dev)) {
2343 netif_carrier_off(tp->dev);
2344 tg3_link_report(tp);
2347 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703 ||
2348 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704 ||
2349 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705) {
2350 err = tg3_phy_reset_5703_4_5(tp);
2357 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5784 &&
2358 GET_CHIP_REV(tp->pci_chip_rev_id) != CHIPREV_5784_AX) {
2359 cpmuctrl = tr32(TG3_CPMU_CTRL);
2360 if (cpmuctrl & CPMU_CTRL_GPHY_10MB_RXONLY)
2362 cpmuctrl & ~CPMU_CTRL_GPHY_10MB_RXONLY);
2365 err = tg3_bmcr_reset(tp);
2369 if (cpmuctrl & CPMU_CTRL_GPHY_10MB_RXONLY) {
2370 val = MII_TG3_DSP_EXP8_AEDW | MII_TG3_DSP_EXP8_REJ2MHz;
2371 tg3_phydsp_write(tp, MII_TG3_DSP_EXP8, val);
2373 tw32(TG3_CPMU_CTRL, cpmuctrl);
2376 if (GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5784_AX ||
2377 GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5761_AX) {
2378 val = tr32(TG3_CPMU_LSPD_1000MB_CLK);
2379 if ((val & CPMU_LSPD_1000MB_MACCLK_MASK) ==
2380 CPMU_LSPD_1000MB_MACCLK_12_5) {
2381 val &= ~CPMU_LSPD_1000MB_MACCLK_MASK;
2383 tw32_f(TG3_CPMU_LSPD_1000MB_CLK, val);
2387 if (tg3_flag(tp, 5717_PLUS) &&
2388 (tp->phy_flags & TG3_PHYFLG_MII_SERDES))
2391 tg3_phy_apply_otp(tp);
2393 if (tp->phy_flags & TG3_PHYFLG_ENABLE_APD)
2394 tg3_phy_toggle_apd(tp, true);
2396 tg3_phy_toggle_apd(tp, false);
2399 if ((tp->phy_flags & TG3_PHYFLG_ADC_BUG) &&
2400 !TG3_PHY_AUXCTL_SMDSP_ENABLE(tp)) {
2401 tg3_phydsp_write(tp, 0x201f, 0x2aaa);
2402 tg3_phydsp_write(tp, 0x000a, 0x0323);
2403 TG3_PHY_AUXCTL_SMDSP_DISABLE(tp);
2406 if (tp->phy_flags & TG3_PHYFLG_5704_A0_BUG) {
2407 tg3_writephy(tp, MII_TG3_MISC_SHDW, 0x8d68);
2408 tg3_writephy(tp, MII_TG3_MISC_SHDW, 0x8d68);
2411 if (tp->phy_flags & TG3_PHYFLG_BER_BUG) {
2412 if (!TG3_PHY_AUXCTL_SMDSP_ENABLE(tp)) {
2413 tg3_phydsp_write(tp, 0x000a, 0x310b);
2414 tg3_phydsp_write(tp, 0x201f, 0x9506);
2415 tg3_phydsp_write(tp, 0x401f, 0x14e2);
2416 TG3_PHY_AUXCTL_SMDSP_DISABLE(tp);
2418 } else if (tp->phy_flags & TG3_PHYFLG_JITTER_BUG) {
2419 if (!TG3_PHY_AUXCTL_SMDSP_ENABLE(tp)) {
2420 tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x000a);
2421 if (tp->phy_flags & TG3_PHYFLG_ADJUST_TRIM) {
2422 tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x110b);
2423 tg3_writephy(tp, MII_TG3_TEST1,
2424 MII_TG3_TEST1_TRIM_EN | 0x4);
2426 tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x010b);
2428 TG3_PHY_AUXCTL_SMDSP_DISABLE(tp);
2432 /* Set Extended packet length bit (bit 14) on all chips that */
2433 /* support jumbo frames */
2434 if ((tp->phy_id & TG3_PHY_ID_MASK) == TG3_PHY_ID_BCM5401) {
2435 /* Cannot do read-modify-write on 5401 */
2436 tg3_phy_auxctl_write(tp, MII_TG3_AUXCTL_SHDWSEL_AUXCTL, 0x4c20);
2437 } else if (tg3_flag(tp, JUMBO_CAPABLE)) {
2438 /* Set bit 14 with read-modify-write to preserve other bits */
2439 err = tg3_phy_auxctl_read(tp,
2440 MII_TG3_AUXCTL_SHDWSEL_AUXCTL, &val);
2442 tg3_phy_auxctl_write(tp, MII_TG3_AUXCTL_SHDWSEL_AUXCTL,
2443 val | MII_TG3_AUXCTL_ACTL_EXTPKTLEN);
2446 /* Set phy register 0x10 bit 0 to high fifo elasticity to support
2447 * jumbo frames transmission.
2449 if (tg3_flag(tp, JUMBO_CAPABLE)) {
2450 if (!tg3_readphy(tp, MII_TG3_EXT_CTRL, &val))
2451 tg3_writephy(tp, MII_TG3_EXT_CTRL,
2452 val | MII_TG3_EXT_CTRL_FIFO_ELASTIC);
2455 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
2456 /* adjust output voltage */
2457 tg3_writephy(tp, MII_TG3_FET_PTEST, 0x12);
2460 tg3_phy_toggle_automdix(tp, 1);
2461 tg3_phy_set_wirespeed(tp);
2465 #define TG3_GPIO_MSG_DRVR_PRES 0x00000001
2466 #define TG3_GPIO_MSG_NEED_VAUX 0x00000002
2467 #define TG3_GPIO_MSG_MASK (TG3_GPIO_MSG_DRVR_PRES | \
2468 TG3_GPIO_MSG_NEED_VAUX)
2469 #define TG3_GPIO_MSG_ALL_DRVR_PRES_MASK \
2470 ((TG3_GPIO_MSG_DRVR_PRES << 0) | \
2471 (TG3_GPIO_MSG_DRVR_PRES << 4) | \
2472 (TG3_GPIO_MSG_DRVR_PRES << 8) | \
2473 (TG3_GPIO_MSG_DRVR_PRES << 12))
2475 #define TG3_GPIO_MSG_ALL_NEED_VAUX_MASK \
2476 ((TG3_GPIO_MSG_NEED_VAUX << 0) | \
2477 (TG3_GPIO_MSG_NEED_VAUX << 4) | \
2478 (TG3_GPIO_MSG_NEED_VAUX << 8) | \
2479 (TG3_GPIO_MSG_NEED_VAUX << 12))
2481 static inline u32 tg3_set_function_status(struct tg3 *tp, u32 newstat)
2485 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717 ||
2486 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5719)
2487 status = tg3_ape_read32(tp, TG3_APE_GPIO_MSG);
2489 status = tr32(TG3_CPMU_DRV_STATUS);
2491 shift = TG3_APE_GPIO_MSG_SHIFT + 4 * tp->pci_fn;
2492 status &= ~(TG3_GPIO_MSG_MASK << shift);
2493 status |= (newstat << shift);
2495 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717 ||
2496 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5719)
2497 tg3_ape_write32(tp, TG3_APE_GPIO_MSG, status);
2499 tw32(TG3_CPMU_DRV_STATUS, status);
2501 return status >> TG3_APE_GPIO_MSG_SHIFT;
2504 static inline int tg3_pwrsrc_switch_to_vmain(struct tg3 *tp)
2506 if (!tg3_flag(tp, IS_NIC))
2509 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717 ||
2510 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5719 ||
2511 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5720) {
2512 if (tg3_ape_lock(tp, TG3_APE_LOCK_GPIO))
2515 tg3_set_function_status(tp, TG3_GPIO_MSG_DRVR_PRES);
2517 tw32_wait_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl,
2518 TG3_GRC_LCLCTL_PWRSW_DELAY);
2520 tg3_ape_unlock(tp, TG3_APE_LOCK_GPIO);
2522 tw32_wait_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl,
2523 TG3_GRC_LCLCTL_PWRSW_DELAY);
2529 static void tg3_pwrsrc_die_with_vmain(struct tg3 *tp)
2533 if (!tg3_flag(tp, IS_NIC) ||
2534 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
2535 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701)
2538 grc_local_ctrl = tp->grc_local_ctrl | GRC_LCLCTRL_GPIO_OE1;
2540 tw32_wait_f(GRC_LOCAL_CTRL,
2541 grc_local_ctrl | GRC_LCLCTRL_GPIO_OUTPUT1,
2542 TG3_GRC_LCLCTL_PWRSW_DELAY);
2544 tw32_wait_f(GRC_LOCAL_CTRL,
2546 TG3_GRC_LCLCTL_PWRSW_DELAY);
2548 tw32_wait_f(GRC_LOCAL_CTRL,
2549 grc_local_ctrl | GRC_LCLCTRL_GPIO_OUTPUT1,
2550 TG3_GRC_LCLCTL_PWRSW_DELAY);
2553 static void tg3_pwrsrc_switch_to_vaux(struct tg3 *tp)
2555 if (!tg3_flag(tp, IS_NIC))
2558 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
2559 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701) {
2560 tw32_wait_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl |
2561 (GRC_LCLCTRL_GPIO_OE0 |
2562 GRC_LCLCTRL_GPIO_OE1 |
2563 GRC_LCLCTRL_GPIO_OE2 |
2564 GRC_LCLCTRL_GPIO_OUTPUT0 |
2565 GRC_LCLCTRL_GPIO_OUTPUT1),
2566 TG3_GRC_LCLCTL_PWRSW_DELAY);
2567 } else if (tp->pdev->device == PCI_DEVICE_ID_TIGON3_5761 ||
2568 tp->pdev->device == TG3PCI_DEVICE_TIGON3_5761S) {
2569 /* The 5761 non-e device swaps GPIO 0 and GPIO 2. */
2570 u32 grc_local_ctrl = GRC_LCLCTRL_GPIO_OE0 |
2571 GRC_LCLCTRL_GPIO_OE1 |
2572 GRC_LCLCTRL_GPIO_OE2 |
2573 GRC_LCLCTRL_GPIO_OUTPUT0 |
2574 GRC_LCLCTRL_GPIO_OUTPUT1 |
2576 tw32_wait_f(GRC_LOCAL_CTRL, grc_local_ctrl,
2577 TG3_GRC_LCLCTL_PWRSW_DELAY);
2579 grc_local_ctrl |= GRC_LCLCTRL_GPIO_OUTPUT2;
2580 tw32_wait_f(GRC_LOCAL_CTRL, grc_local_ctrl,
2581 TG3_GRC_LCLCTL_PWRSW_DELAY);
2583 grc_local_ctrl &= ~GRC_LCLCTRL_GPIO_OUTPUT0;
2584 tw32_wait_f(GRC_LOCAL_CTRL, grc_local_ctrl,
2585 TG3_GRC_LCLCTL_PWRSW_DELAY);
2588 u32 grc_local_ctrl = 0;
2590 /* Workaround to prevent overdrawing Amps. */
2591 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5714) {
2592 grc_local_ctrl |= GRC_LCLCTRL_GPIO_OE3;
2593 tw32_wait_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl |
2595 TG3_GRC_LCLCTL_PWRSW_DELAY);
2598 /* On 5753 and variants, GPIO2 cannot be used. */
2599 no_gpio2 = tp->nic_sram_data_cfg &
2600 NIC_SRAM_DATA_CFG_NO_GPIO2;
2602 grc_local_ctrl |= GRC_LCLCTRL_GPIO_OE0 |
2603 GRC_LCLCTRL_GPIO_OE1 |
2604 GRC_LCLCTRL_GPIO_OE2 |
2605 GRC_LCLCTRL_GPIO_OUTPUT1 |
2606 GRC_LCLCTRL_GPIO_OUTPUT2;
2608 grc_local_ctrl &= ~(GRC_LCLCTRL_GPIO_OE2 |
2609 GRC_LCLCTRL_GPIO_OUTPUT2);
2611 tw32_wait_f(GRC_LOCAL_CTRL,
2612 tp->grc_local_ctrl | grc_local_ctrl,
2613 TG3_GRC_LCLCTL_PWRSW_DELAY);
2615 grc_local_ctrl |= GRC_LCLCTRL_GPIO_OUTPUT0;
2617 tw32_wait_f(GRC_LOCAL_CTRL,
2618 tp->grc_local_ctrl | grc_local_ctrl,
2619 TG3_GRC_LCLCTL_PWRSW_DELAY);
2622 grc_local_ctrl &= ~GRC_LCLCTRL_GPIO_OUTPUT2;
2623 tw32_wait_f(GRC_LOCAL_CTRL,
2624 tp->grc_local_ctrl | grc_local_ctrl,
2625 TG3_GRC_LCLCTL_PWRSW_DELAY);
2630 static void tg3_frob_aux_power_5717(struct tg3 *tp, bool wol_enable)
2634 /* Serialize power state transitions */
2635 if (tg3_ape_lock(tp, TG3_APE_LOCK_GPIO))
2638 if (tg3_flag(tp, ENABLE_ASF) || tg3_flag(tp, ENABLE_APE) || wol_enable)
2639 msg = TG3_GPIO_MSG_NEED_VAUX;
2641 msg = tg3_set_function_status(tp, msg);
2643 if (msg & TG3_GPIO_MSG_ALL_DRVR_PRES_MASK)
2646 if (msg & TG3_GPIO_MSG_ALL_NEED_VAUX_MASK)
2647 tg3_pwrsrc_switch_to_vaux(tp);
2649 tg3_pwrsrc_die_with_vmain(tp);
2652 tg3_ape_unlock(tp, TG3_APE_LOCK_GPIO);
2655 static void tg3_frob_aux_power(struct tg3 *tp, bool include_wol)
2657 bool need_vaux = false;
2659 /* The GPIOs do something completely different on 57765. */
2660 if (!tg3_flag(tp, IS_NIC) || tg3_flag(tp, 57765_CLASS))
2663 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717 ||
2664 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5719 ||
2665 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5720) {
2666 tg3_frob_aux_power_5717(tp, include_wol ?
2667 tg3_flag(tp, WOL_ENABLE) != 0 : 0);
2671 if (tp->pdev_peer && tp->pdev_peer != tp->pdev) {
2672 struct net_device *dev_peer;
2674 dev_peer = pci_get_drvdata(tp->pdev_peer);
2676 /* remove_one() may have been run on the peer. */
2678 struct tg3 *tp_peer = netdev_priv(dev_peer);
2680 if (tg3_flag(tp_peer, INIT_COMPLETE))
2683 if ((include_wol && tg3_flag(tp_peer, WOL_ENABLE)) ||
2684 tg3_flag(tp_peer, ENABLE_ASF))
2689 if ((include_wol && tg3_flag(tp, WOL_ENABLE)) ||
2690 tg3_flag(tp, ENABLE_ASF))
2694 tg3_pwrsrc_switch_to_vaux(tp);
2696 tg3_pwrsrc_die_with_vmain(tp);
2699 static int tg3_5700_link_polarity(struct tg3 *tp, u32 speed)
2701 if (tp->led_ctrl == LED_CTRL_MODE_PHY_2)
2703 else if ((tp->phy_id & TG3_PHY_ID_MASK) == TG3_PHY_ID_BCM5411) {
2704 if (speed != SPEED_10)
2706 } else if (speed == SPEED_10)
2712 static int tg3_setup_phy(struct tg3 *, int);
2713 static int tg3_halt_cpu(struct tg3 *, u32);
2715 static void tg3_power_down_phy(struct tg3 *tp, bool do_low_power)
2719 if (tp->phy_flags & TG3_PHYFLG_PHY_SERDES) {
2720 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704) {
2721 u32 sg_dig_ctrl = tr32(SG_DIG_CTRL);
2722 u32 serdes_cfg = tr32(MAC_SERDES_CFG);
2725 SG_DIG_USING_HW_AUTONEG | SG_DIG_SOFT_RESET;
2726 tw32(SG_DIG_CTRL, sg_dig_ctrl);
2727 tw32(MAC_SERDES_CFG, serdes_cfg | (1 << 15));
2732 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
2734 val = tr32(GRC_MISC_CFG);
2735 tw32_f(GRC_MISC_CFG, val | GRC_MISC_CFG_EPHY_IDDQ);
2738 } else if (tp->phy_flags & TG3_PHYFLG_IS_FET) {
2740 if (!tg3_readphy(tp, MII_TG3_FET_TEST, &phytest)) {
2743 tg3_writephy(tp, MII_ADVERTISE, 0);
2744 tg3_writephy(tp, MII_BMCR,
2745 BMCR_ANENABLE | BMCR_ANRESTART);
2747 tg3_writephy(tp, MII_TG3_FET_TEST,
2748 phytest | MII_TG3_FET_SHADOW_EN);
2749 if (!tg3_readphy(tp, MII_TG3_FET_SHDW_AUXMODE4, &phy)) {
2750 phy |= MII_TG3_FET_SHDW_AUXMODE4_SBPD;
2752 MII_TG3_FET_SHDW_AUXMODE4,
2755 tg3_writephy(tp, MII_TG3_FET_TEST, phytest);
2758 } else if (do_low_power) {
2759 tg3_writephy(tp, MII_TG3_EXT_CTRL,
2760 MII_TG3_EXT_CTRL_FORCE_LED_OFF);
2762 val = MII_TG3_AUXCTL_PCTL_100TX_LPWR |
2763 MII_TG3_AUXCTL_PCTL_SPR_ISOLATE |
2764 MII_TG3_AUXCTL_PCTL_VREG_11V;
2765 tg3_phy_auxctl_write(tp, MII_TG3_AUXCTL_SHDWSEL_PWRCTL, val);
2768 /* The PHY should not be powered down on some chips because
2771 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
2772 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704 ||
2773 (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5780 &&
2774 (tp->phy_flags & TG3_PHYFLG_MII_SERDES)))
2777 if (GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5784_AX ||
2778 GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5761_AX) {
2779 val = tr32(TG3_CPMU_LSPD_1000MB_CLK);
2780 val &= ~CPMU_LSPD_1000MB_MACCLK_MASK;
2781 val |= CPMU_LSPD_1000MB_MACCLK_12_5;
2782 tw32_f(TG3_CPMU_LSPD_1000MB_CLK, val);
2785 tg3_writephy(tp, MII_BMCR, BMCR_PDOWN);
2788 /* tp->lock is held. */
2789 static int tg3_nvram_lock(struct tg3 *tp)
2791 if (tg3_flag(tp, NVRAM)) {
2794 if (tp->nvram_lock_cnt == 0) {
2795 tw32(NVRAM_SWARB, SWARB_REQ_SET1);
2796 for (i = 0; i < 8000; i++) {
2797 if (tr32(NVRAM_SWARB) & SWARB_GNT1)
2802 tw32(NVRAM_SWARB, SWARB_REQ_CLR1);
2806 tp->nvram_lock_cnt++;
2811 /* tp->lock is held. */
2812 static void tg3_nvram_unlock(struct tg3 *tp)
2814 if (tg3_flag(tp, NVRAM)) {
2815 if (tp->nvram_lock_cnt > 0)
2816 tp->nvram_lock_cnt--;
2817 if (tp->nvram_lock_cnt == 0)
2818 tw32_f(NVRAM_SWARB, SWARB_REQ_CLR1);
2822 /* tp->lock is held. */
2823 static void tg3_enable_nvram_access(struct tg3 *tp)
2825 if (tg3_flag(tp, 5750_PLUS) && !tg3_flag(tp, PROTECTED_NVRAM)) {
2826 u32 nvaccess = tr32(NVRAM_ACCESS);
2828 tw32(NVRAM_ACCESS, nvaccess | ACCESS_ENABLE);
2832 /* tp->lock is held. */
2833 static void tg3_disable_nvram_access(struct tg3 *tp)
2835 if (tg3_flag(tp, 5750_PLUS) && !tg3_flag(tp, PROTECTED_NVRAM)) {
2836 u32 nvaccess = tr32(NVRAM_ACCESS);
2838 tw32(NVRAM_ACCESS, nvaccess & ~ACCESS_ENABLE);
2842 static int tg3_nvram_read_using_eeprom(struct tg3 *tp,
2843 u32 offset, u32 *val)
2848 if (offset > EEPROM_ADDR_ADDR_MASK || (offset % 4) != 0)
2851 tmp = tr32(GRC_EEPROM_ADDR) & ~(EEPROM_ADDR_ADDR_MASK |
2852 EEPROM_ADDR_DEVID_MASK |
2854 tw32(GRC_EEPROM_ADDR,
2856 (0 << EEPROM_ADDR_DEVID_SHIFT) |
2857 ((offset << EEPROM_ADDR_ADDR_SHIFT) &
2858 EEPROM_ADDR_ADDR_MASK) |
2859 EEPROM_ADDR_READ | EEPROM_ADDR_START);
2861 for (i = 0; i < 1000; i++) {
2862 tmp = tr32(GRC_EEPROM_ADDR);
2864 if (tmp & EEPROM_ADDR_COMPLETE)
2868 if (!(tmp & EEPROM_ADDR_COMPLETE))
2871 tmp = tr32(GRC_EEPROM_DATA);
2874 * The data will always be opposite the native endian
2875 * format. Perform a blind byteswap to compensate.
2882 #define NVRAM_CMD_TIMEOUT 10000
2884 static int tg3_nvram_exec_cmd(struct tg3 *tp, u32 nvram_cmd)
2888 tw32(NVRAM_CMD, nvram_cmd);
2889 for (i = 0; i < NVRAM_CMD_TIMEOUT; i++) {
2891 if (tr32(NVRAM_CMD) & NVRAM_CMD_DONE) {
2897 if (i == NVRAM_CMD_TIMEOUT)
2903 static u32 tg3_nvram_phys_addr(struct tg3 *tp, u32 addr)
2905 if (tg3_flag(tp, NVRAM) &&
2906 tg3_flag(tp, NVRAM_BUFFERED) &&
2907 tg3_flag(tp, FLASH) &&
2908 !tg3_flag(tp, NO_NVRAM_ADDR_TRANS) &&
2909 (tp->nvram_jedecnum == JEDEC_ATMEL))
2911 addr = ((addr / tp->nvram_pagesize) <<
2912 ATMEL_AT45DB0X1B_PAGE_POS) +
2913 (addr % tp->nvram_pagesize);
2918 static u32 tg3_nvram_logical_addr(struct tg3 *tp, u32 addr)
2920 if (tg3_flag(tp, NVRAM) &&
2921 tg3_flag(tp, NVRAM_BUFFERED) &&
2922 tg3_flag(tp, FLASH) &&
2923 !tg3_flag(tp, NO_NVRAM_ADDR_TRANS) &&
2924 (tp->nvram_jedecnum == JEDEC_ATMEL))
2926 addr = ((addr >> ATMEL_AT45DB0X1B_PAGE_POS) *
2927 tp->nvram_pagesize) +
2928 (addr & ((1 << ATMEL_AT45DB0X1B_PAGE_POS) - 1));
2933 /* NOTE: Data read in from NVRAM is byteswapped according to
2934 * the byteswapping settings for all other register accesses.
2935 * tg3 devices are BE devices, so on a BE machine, the data
2936 * returned will be exactly as it is seen in NVRAM. On a LE
2937 * machine, the 32-bit value will be byteswapped.
2939 static int tg3_nvram_read(struct tg3 *tp, u32 offset, u32 *val)
2943 if (!tg3_flag(tp, NVRAM))
2944 return tg3_nvram_read_using_eeprom(tp, offset, val);
2946 offset = tg3_nvram_phys_addr(tp, offset);
2948 if (offset > NVRAM_ADDR_MSK)
2951 ret = tg3_nvram_lock(tp);
2955 tg3_enable_nvram_access(tp);
2957 tw32(NVRAM_ADDR, offset);
2958 ret = tg3_nvram_exec_cmd(tp, NVRAM_CMD_RD | NVRAM_CMD_GO |
2959 NVRAM_CMD_FIRST | NVRAM_CMD_LAST | NVRAM_CMD_DONE);
2962 *val = tr32(NVRAM_RDDATA);
2964 tg3_disable_nvram_access(tp);
2966 tg3_nvram_unlock(tp);
2971 /* Ensures NVRAM data is in bytestream format. */
2972 static int tg3_nvram_read_be32(struct tg3 *tp, u32 offset, __be32 *val)
2975 int res = tg3_nvram_read(tp, offset, &v);
2977 *val = cpu_to_be32(v);
2981 #define RX_CPU_SCRATCH_BASE 0x30000
2982 #define RX_CPU_SCRATCH_SIZE 0x04000
2983 #define TX_CPU_SCRATCH_BASE 0x34000
2984 #define TX_CPU_SCRATCH_SIZE 0x04000
2986 /* tp->lock is held. */
2987 static int tg3_halt_cpu(struct tg3 *tp, u32 offset)
2991 BUG_ON(offset == TX_CPU_BASE && tg3_flag(tp, 5705_PLUS));
2993 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
2994 u32 val = tr32(GRC_VCPU_EXT_CTRL);
2996 tw32(GRC_VCPU_EXT_CTRL, val | GRC_VCPU_EXT_CTRL_HALT_CPU);
2999 if (offset == RX_CPU_BASE) {
3000 for (i = 0; i < 10000; i++) {
3001 tw32(offset + CPU_STATE, 0xffffffff);
3002 tw32(offset + CPU_MODE, CPU_MODE_HALT);
3003 if (tr32(offset + CPU_MODE) & CPU_MODE_HALT)
3007 tw32(offset + CPU_STATE, 0xffffffff);
3008 tw32_f(offset + CPU_MODE, CPU_MODE_HALT);
3011 for (i = 0; i < 10000; i++) {
3012 tw32(offset + CPU_STATE, 0xffffffff);
3013 tw32(offset + CPU_MODE, CPU_MODE_HALT);
3014 if (tr32(offset + CPU_MODE) & CPU_MODE_HALT)
3020 netdev_err(tp->dev, "%s timed out, %s CPU\n",
3021 __func__, offset == RX_CPU_BASE ? "RX" : "TX");
3025 /* Clear firmware's nvram arbitration. */
3026 if (tg3_flag(tp, NVRAM))
3027 tw32(NVRAM_SWARB, SWARB_REQ_CLR0);
3032 unsigned int fw_base;
3033 unsigned int fw_len;
3034 const __be32 *fw_data;
3037 /* tp->lock is held. */
3038 static int tg3_load_firmware_cpu(struct tg3 *tp, u32 cpu_base,
3039 u32 cpu_scratch_base, int cpu_scratch_size,
3040 struct fw_info *info)
3042 int err, lock_err, i;
3043 void (*write_op)(struct tg3 *, u32, u32);
3045 if (cpu_base == TX_CPU_BASE && tg3_flag(tp, 5705_PLUS)) {
3047 "%s: Trying to load TX cpu firmware which is 5705\n",
3052 if (tg3_flag(tp, 5705_PLUS))
3053 write_op = tg3_write_mem;
3055 write_op = tg3_write_indirect_reg32;
3057 /* It is possible that bootcode is still loading at this point.
3058 * Get the nvram lock first before halting the cpu.
3060 lock_err = tg3_nvram_lock(tp);
3061 err = tg3_halt_cpu(tp, cpu_base);
3063 tg3_nvram_unlock(tp);
3067 for (i = 0; i < cpu_scratch_size; i += sizeof(u32))
3068 write_op(tp, cpu_scratch_base + i, 0);
3069 tw32(cpu_base + CPU_STATE, 0xffffffff);
3070 tw32(cpu_base + CPU_MODE, tr32(cpu_base+CPU_MODE)|CPU_MODE_HALT);
3071 for (i = 0; i < (info->fw_len / sizeof(u32)); i++)
3072 write_op(tp, (cpu_scratch_base +
3073 (info->fw_base & 0xffff) +
3075 be32_to_cpu(info->fw_data[i]));
3083 /* tp->lock is held. */
3084 static int tg3_load_5701_a0_firmware_fix(struct tg3 *tp)
3086 struct fw_info info;
3087 const __be32 *fw_data;
3090 fw_data = (void *)tp->fw->data;
3092 /* Firmware blob starts with version numbers, followed by
3093 start address and length. We are setting complete length.
3094 length = end_address_of_bss - start_address_of_text.
3095 Remainder is the blob to be loaded contiguously
3096 from start address. */
3098 info.fw_base = be32_to_cpu(fw_data[1]);
3099 info.fw_len = tp->fw->size - 12;
3100 info.fw_data = &fw_data[3];
3102 err = tg3_load_firmware_cpu(tp, RX_CPU_BASE,
3103 RX_CPU_SCRATCH_BASE, RX_CPU_SCRATCH_SIZE,
3108 err = tg3_load_firmware_cpu(tp, TX_CPU_BASE,
3109 TX_CPU_SCRATCH_BASE, TX_CPU_SCRATCH_SIZE,
3114 /* Now startup only the RX cpu. */
3115 tw32(RX_CPU_BASE + CPU_STATE, 0xffffffff);
3116 tw32_f(RX_CPU_BASE + CPU_PC, info.fw_base);
3118 for (i = 0; i < 5; i++) {
3119 if (tr32(RX_CPU_BASE + CPU_PC) == info.fw_base)
3121 tw32(RX_CPU_BASE + CPU_STATE, 0xffffffff);
3122 tw32(RX_CPU_BASE + CPU_MODE, CPU_MODE_HALT);
3123 tw32_f(RX_CPU_BASE + CPU_PC, info.fw_base);
3127 netdev_err(tp->dev, "%s fails to set RX CPU PC, is %08x "
3128 "should be %08x\n", __func__,
3129 tr32(RX_CPU_BASE + CPU_PC), info.fw_base);
3132 tw32(RX_CPU_BASE + CPU_STATE, 0xffffffff);
3133 tw32_f(RX_CPU_BASE + CPU_MODE, 0x00000000);
3138 /* tp->lock is held. */
3139 static int tg3_load_tso_firmware(struct tg3 *tp)
3141 struct fw_info info;
3142 const __be32 *fw_data;
3143 unsigned long cpu_base, cpu_scratch_base, cpu_scratch_size;
3146 if (tg3_flag(tp, HW_TSO_1) ||
3147 tg3_flag(tp, HW_TSO_2) ||
3148 tg3_flag(tp, HW_TSO_3))
3151 fw_data = (void *)tp->fw->data;
3153 /* Firmware blob starts with version numbers, followed by
3154 start address and length. We are setting complete length.
3155 length = end_address_of_bss - start_address_of_text.
3156 Remainder is the blob to be loaded contiguously
3157 from start address. */
3159 info.fw_base = be32_to_cpu(fw_data[1]);
3160 cpu_scratch_size = tp->fw_len;
3161 info.fw_len = tp->fw->size - 12;
3162 info.fw_data = &fw_data[3];
3164 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705) {
3165 cpu_base = RX_CPU_BASE;
3166 cpu_scratch_base = NIC_SRAM_MBUF_POOL_BASE5705;
3168 cpu_base = TX_CPU_BASE;
3169 cpu_scratch_base = TX_CPU_SCRATCH_BASE;
3170 cpu_scratch_size = TX_CPU_SCRATCH_SIZE;
3173 err = tg3_load_firmware_cpu(tp, cpu_base,
3174 cpu_scratch_base, cpu_scratch_size,
3179 /* Now startup the cpu. */
3180 tw32(cpu_base + CPU_STATE, 0xffffffff);
3181 tw32_f(cpu_base + CPU_PC, info.fw_base);
3183 for (i = 0; i < 5; i++) {
3184 if (tr32(cpu_base + CPU_PC) == info.fw_base)
3186 tw32(cpu_base + CPU_STATE, 0xffffffff);
3187 tw32(cpu_base + CPU_MODE, CPU_MODE_HALT);
3188 tw32_f(cpu_base + CPU_PC, info.fw_base);
3193 "%s fails to set CPU PC, is %08x should be %08x\n",
3194 __func__, tr32(cpu_base + CPU_PC), info.fw_base);
3197 tw32(cpu_base + CPU_STATE, 0xffffffff);
3198 tw32_f(cpu_base + CPU_MODE, 0x00000000);
3203 /* tp->lock is held. */
3204 static void __tg3_set_mac_addr(struct tg3 *tp, int skip_mac_1)
3206 u32 addr_high, addr_low;
3209 addr_high = ((tp->dev->dev_addr[0] << 8) |
3210 tp->dev->dev_addr[1]);
3211 addr_low = ((tp->dev->dev_addr[2] << 24) |
3212 (tp->dev->dev_addr[3] << 16) |
3213 (tp->dev->dev_addr[4] << 8) |
3214 (tp->dev->dev_addr[5] << 0));
3215 for (i = 0; i < 4; i++) {
3216 if (i == 1 && skip_mac_1)
3218 tw32(MAC_ADDR_0_HIGH + (i * 8), addr_high);
3219 tw32(MAC_ADDR_0_LOW + (i * 8), addr_low);
3222 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703 ||
3223 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704) {
3224 for (i = 0; i < 12; i++) {
3225 tw32(MAC_EXTADDR_0_HIGH + (i * 8), addr_high);
3226 tw32(MAC_EXTADDR_0_LOW + (i * 8), addr_low);
3230 addr_high = (tp->dev->dev_addr[0] +
3231 tp->dev->dev_addr[1] +
3232 tp->dev->dev_addr[2] +
3233 tp->dev->dev_addr[3] +
3234 tp->dev->dev_addr[4] +
3235 tp->dev->dev_addr[5]) &
3236 TX_BACKOFF_SEED_MASK;
3237 tw32(MAC_TX_BACKOFF_SEED, addr_high);
3240 static void tg3_enable_register_access(struct tg3 *tp)
3243 * Make sure register accesses (indirect or otherwise) will function
3246 pci_write_config_dword(tp->pdev,
3247 TG3PCI_MISC_HOST_CTRL, tp->misc_host_ctrl);
3250 static int tg3_power_up(struct tg3 *tp)
3254 tg3_enable_register_access(tp);
3256 err = pci_set_power_state(tp->pdev, PCI_D0);
3258 /* Switch out of Vaux if it is a NIC */
3259 tg3_pwrsrc_switch_to_vmain(tp);
3261 netdev_err(tp->dev, "Transition to D0 failed\n");
3267 static int tg3_power_down_prepare(struct tg3 *tp)
3270 bool device_should_wake, do_low_power;
3272 tg3_enable_register_access(tp);
3274 /* Restore the CLKREQ setting. */
3275 if (tg3_flag(tp, CLKREQ_BUG)) {
3278 pci_read_config_word(tp->pdev,
3279 pci_pcie_cap(tp->pdev) + PCI_EXP_LNKCTL,
3281 lnkctl |= PCI_EXP_LNKCTL_CLKREQ_EN;
3282 pci_write_config_word(tp->pdev,
3283 pci_pcie_cap(tp->pdev) + PCI_EXP_LNKCTL,
3287 misc_host_ctrl = tr32(TG3PCI_MISC_HOST_CTRL);
3288 tw32(TG3PCI_MISC_HOST_CTRL,
3289 misc_host_ctrl | MISC_HOST_CTRL_MASK_PCI_INT);
3291 device_should_wake = device_may_wakeup(&tp->pdev->dev) &&
3292 tg3_flag(tp, WOL_ENABLE);
3294 if (tg3_flag(tp, USE_PHYLIB)) {
3295 do_low_power = false;
3296 if ((tp->phy_flags & TG3_PHYFLG_IS_CONNECTED) &&
3297 !(tp->phy_flags & TG3_PHYFLG_IS_LOW_POWER)) {
3298 struct phy_device *phydev;
3299 u32 phyid, advertising;
3301 phydev = tp->mdio_bus->phy_map[TG3_PHY_MII_ADDR];
3303 tp->phy_flags |= TG3_PHYFLG_IS_LOW_POWER;
3305 tp->link_config.orig_speed = phydev->speed;
3306 tp->link_config.orig_duplex = phydev->duplex;
3307 tp->link_config.orig_autoneg = phydev->autoneg;
3308 tp->link_config.orig_advertising = phydev->advertising;
3310 advertising = ADVERTISED_TP |
3312 ADVERTISED_Autoneg |
3313 ADVERTISED_10baseT_Half;
3315 if (tg3_flag(tp, ENABLE_ASF) || device_should_wake) {
3316 if (tg3_flag(tp, WOL_SPEED_100MB))
3318 ADVERTISED_100baseT_Half |
3319 ADVERTISED_100baseT_Full |
3320 ADVERTISED_10baseT_Full;
3322 advertising |= ADVERTISED_10baseT_Full;
3325 phydev->advertising = advertising;
3327 phy_start_aneg(phydev);
3329 phyid = phydev->drv->phy_id & phydev->drv->phy_id_mask;
3330 if (phyid != PHY_ID_BCMAC131) {
3331 phyid &= PHY_BCM_OUI_MASK;
3332 if (phyid == PHY_BCM_OUI_1 ||
3333 phyid == PHY_BCM_OUI_2 ||
3334 phyid == PHY_BCM_OUI_3)
3335 do_low_power = true;
3339 do_low_power = true;
3341 if (!(tp->phy_flags & TG3_PHYFLG_IS_LOW_POWER)) {
3342 tp->phy_flags |= TG3_PHYFLG_IS_LOW_POWER;
3343 tp->link_config.orig_speed = tp->link_config.speed;
3344 tp->link_config.orig_duplex = tp->link_config.duplex;
3345 tp->link_config.orig_autoneg = tp->link_config.autoneg;
3348 if (!(tp->phy_flags & TG3_PHYFLG_ANY_SERDES)) {
3349 tp->link_config.speed = SPEED_10;
3350 tp->link_config.duplex = DUPLEX_HALF;
3351 tp->link_config.autoneg = AUTONEG_ENABLE;
3352 tg3_setup_phy(tp, 0);
3356 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
3359 val = tr32(GRC_VCPU_EXT_CTRL);
3360 tw32(GRC_VCPU_EXT_CTRL, val | GRC_VCPU_EXT_CTRL_DISABLE_WOL);
3361 } else if (!tg3_flag(tp, ENABLE_ASF)) {
3365 for (i = 0; i < 200; i++) {
3366 tg3_read_mem(tp, NIC_SRAM_FW_ASF_STATUS_MBOX, &val);
3367 if (val == ~NIC_SRAM_FIRMWARE_MBOX_MAGIC1)
3372 if (tg3_flag(tp, WOL_CAP))
3373 tg3_write_mem(tp, NIC_SRAM_WOL_MBOX, WOL_SIGNATURE |
3374 WOL_DRV_STATE_SHUTDOWN |
3378 if (device_should_wake) {
3381 if (!(tp->phy_flags & TG3_PHYFLG_PHY_SERDES)) {
3383 !(tp->phy_flags & TG3_PHYFLG_IS_FET)) {
3384 tg3_phy_auxctl_write(tp,
3385 MII_TG3_AUXCTL_SHDWSEL_PWRCTL,
3386 MII_TG3_AUXCTL_PCTL_WOL_EN |
3387 MII_TG3_AUXCTL_PCTL_100TX_LPWR |
3388 MII_TG3_AUXCTL_PCTL_CL_AB_TXDAC);
3392 if (tp->phy_flags & TG3_PHYFLG_MII_SERDES)
3393 mac_mode = MAC_MODE_PORT_MODE_GMII;
3395 mac_mode = MAC_MODE_PORT_MODE_MII;
3397 mac_mode |= tp->mac_mode & MAC_MODE_LINK_POLARITY;
3398 if (GET_ASIC_REV(tp->pci_chip_rev_id) ==
3400 u32 speed = tg3_flag(tp, WOL_SPEED_100MB) ?
3401 SPEED_100 : SPEED_10;
3402 if (tg3_5700_link_polarity(tp, speed))
3403 mac_mode |= MAC_MODE_LINK_POLARITY;
3405 mac_mode &= ~MAC_MODE_LINK_POLARITY;
3408 mac_mode = MAC_MODE_PORT_MODE_TBI;
3411 if (!tg3_flag(tp, 5750_PLUS))
3412 tw32(MAC_LED_CTRL, tp->led_ctrl);
3414 mac_mode |= MAC_MODE_MAGIC_PKT_ENABLE;
3415 if ((tg3_flag(tp, 5705_PLUS) && !tg3_flag(tp, 5780_CLASS)) &&
3416 (tg3_flag(tp, ENABLE_ASF) || tg3_flag(tp, ENABLE_APE)))
3417 mac_mode |= MAC_MODE_KEEP_FRAME_IN_WOL;
3419 if (tg3_flag(tp, ENABLE_APE))
3420 mac_mode |= MAC_MODE_APE_TX_EN |
3421 MAC_MODE_APE_RX_EN |
3422 MAC_MODE_TDE_ENABLE;
3424 tw32_f(MAC_MODE, mac_mode);
3427 tw32_f(MAC_RX_MODE, RX_MODE_ENABLE);
3431 if (!tg3_flag(tp, WOL_SPEED_100MB) &&
3432 (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
3433 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701)) {
3436 base_val = tp->pci_clock_ctrl;
3437 base_val |= (CLOCK_CTRL_RXCLK_DISABLE |
3438 CLOCK_CTRL_TXCLK_DISABLE);
3440 tw32_wait_f(TG3PCI_CLOCK_CTRL, base_val | CLOCK_CTRL_ALTCLK |
3441 CLOCK_CTRL_PWRDOWN_PLL133, 40);
3442 } else if (tg3_flag(tp, 5780_CLASS) ||
3443 tg3_flag(tp, CPMU_PRESENT) ||
3444 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
3446 } else if (!(tg3_flag(tp, 5750_PLUS) && tg3_flag(tp, ENABLE_ASF))) {
3447 u32 newbits1, newbits2;
3449 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
3450 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701) {
3451 newbits1 = (CLOCK_CTRL_RXCLK_DISABLE |
3452 CLOCK_CTRL_TXCLK_DISABLE |
3454 newbits2 = newbits1 | CLOCK_CTRL_44MHZ_CORE;
3455 } else if (tg3_flag(tp, 5705_PLUS)) {
3456 newbits1 = CLOCK_CTRL_625_CORE;
3457 newbits2 = newbits1 | CLOCK_CTRL_ALTCLK;
3459 newbits1 = CLOCK_CTRL_ALTCLK;
3460 newbits2 = newbits1 | CLOCK_CTRL_44MHZ_CORE;
3463 tw32_wait_f(TG3PCI_CLOCK_CTRL, tp->pci_clock_ctrl | newbits1,
3466 tw32_wait_f(TG3PCI_CLOCK_CTRL, tp->pci_clock_ctrl | newbits2,
3469 if (!tg3_flag(tp, 5705_PLUS)) {
3472 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
3473 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701) {
3474 newbits3 = (CLOCK_CTRL_RXCLK_DISABLE |
3475 CLOCK_CTRL_TXCLK_DISABLE |
3476 CLOCK_CTRL_44MHZ_CORE);
3478 newbits3 = CLOCK_CTRL_44MHZ_CORE;
3481 tw32_wait_f(TG3PCI_CLOCK_CTRL,
3482 tp->pci_clock_ctrl | newbits3, 40);
3486 if (!(device_should_wake) && !tg3_flag(tp, ENABLE_ASF))
3487 tg3_power_down_phy(tp, do_low_power);
3489 tg3_frob_aux_power(tp, true);
3491 /* Workaround for unstable PLL clock */
3492 if ((GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5750_AX) ||
3493 (GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5750_BX)) {
3494 u32 val = tr32(0x7d00);
3496 val &= ~((1 << 16) | (1 << 4) | (1 << 2) | (1 << 1) | 1);
3498 if (!tg3_flag(tp, ENABLE_ASF)) {
3501 err = tg3_nvram_lock(tp);
3502 tg3_halt_cpu(tp, RX_CPU_BASE);
3504 tg3_nvram_unlock(tp);
3508 tg3_write_sig_post_reset(tp, RESET_KIND_SHUTDOWN);
3513 static void tg3_power_down(struct tg3 *tp)
3515 tg3_power_down_prepare(tp);
3517 pci_wake_from_d3(tp->pdev, tg3_flag(tp, WOL_ENABLE));
3518 pci_set_power_state(tp->pdev, PCI_D3hot);
3521 static void tg3_aux_stat_to_speed_duplex(struct tg3 *tp, u32 val, u16 *speed, u8 *duplex)
3523 switch (val & MII_TG3_AUX_STAT_SPDMASK) {
3524 case MII_TG3_AUX_STAT_10HALF:
3526 *duplex = DUPLEX_HALF;
3529 case MII_TG3_AUX_STAT_10FULL:
3531 *duplex = DUPLEX_FULL;
3534 case MII_TG3_AUX_STAT_100HALF:
3536 *duplex = DUPLEX_HALF;
3539 case MII_TG3_AUX_STAT_100FULL:
3541 *duplex = DUPLEX_FULL;
3544 case MII_TG3_AUX_STAT_1000HALF:
3545 *speed = SPEED_1000;
3546 *duplex = DUPLEX_HALF;
3549 case MII_TG3_AUX_STAT_1000FULL:
3550 *speed = SPEED_1000;
3551 *duplex = DUPLEX_FULL;
3555 if (tp->phy_flags & TG3_PHYFLG_IS_FET) {
3556 *speed = (val & MII_TG3_AUX_STAT_100) ? SPEED_100 :
3558 *duplex = (val & MII_TG3_AUX_STAT_FULL) ? DUPLEX_FULL :
3562 *speed = SPEED_INVALID;
3563 *duplex = DUPLEX_INVALID;
3568 static int tg3_phy_autoneg_cfg(struct tg3 *tp, u32 advertise, u32 flowctrl)
3573 new_adv = ADVERTISE_CSMA;
3574 new_adv |= ethtool_adv_to_mii_adv_t(advertise) & ADVERTISE_ALL;
3575 new_adv |= mii_advertise_flowctrl(flowctrl);
3577 err = tg3_writephy(tp, MII_ADVERTISE, new_adv);
3581 if (!(tp->phy_flags & TG3_PHYFLG_10_100_ONLY)) {
3582 new_adv = ethtool_adv_to_mii_ctrl1000_t(advertise);
3584 if (tp->pci_chip_rev_id == CHIPREV_ID_5701_A0 ||
3585 tp->pci_chip_rev_id == CHIPREV_ID_5701_B0)
3586 new_adv |= CTL1000_AS_MASTER | CTL1000_ENABLE_MASTER;
3588 err = tg3_writephy(tp, MII_CTRL1000, new_adv);
3593 if (!(tp->phy_flags & TG3_PHYFLG_EEE_CAP))
3596 tw32(TG3_CPMU_EEE_MODE,
3597 tr32(TG3_CPMU_EEE_MODE) & ~TG3_CPMU_EEEMD_LPI_ENABLE);
3599 err = TG3_PHY_AUXCTL_SMDSP_ENABLE(tp);
3604 /* Advertise 100-BaseTX EEE ability */
3605 if (advertise & ADVERTISED_100baseT_Full)
3606 val |= MDIO_AN_EEE_ADV_100TX;
3607 /* Advertise 1000-BaseT EEE ability */
3608 if (advertise & ADVERTISED_1000baseT_Full)
3609 val |= MDIO_AN_EEE_ADV_1000T;
3610 err = tg3_phy_cl45_write(tp, MDIO_MMD_AN, MDIO_AN_EEE_ADV, val);
3614 switch (GET_ASIC_REV(tp->pci_chip_rev_id)) {
3616 case ASIC_REV_57765:
3617 case ASIC_REV_57766:
3619 /* If we advertised any eee advertisements above... */
3621 val = MII_TG3_DSP_TAP26_ALNOKO |
3622 MII_TG3_DSP_TAP26_RMRXSTO |
3623 MII_TG3_DSP_TAP26_OPCSINPT;
3624 tg3_phydsp_write(tp, MII_TG3_DSP_TAP26, val);
3627 if (!tg3_phydsp_read(tp, MII_TG3_DSP_CH34TP2, &val))
3628 tg3_phydsp_write(tp, MII_TG3_DSP_CH34TP2, val |
3629 MII_TG3_DSP_CH34TP2_HIBW01);
3632 err2 = TG3_PHY_AUXCTL_SMDSP_DISABLE(tp);
3641 static void tg3_phy_copper_begin(struct tg3 *tp)
3646 if (tp->phy_flags & TG3_PHYFLG_IS_LOW_POWER) {
3647 new_adv = ADVERTISED_10baseT_Half |
3648 ADVERTISED_10baseT_Full;
3649 if (tg3_flag(tp, WOL_SPEED_100MB))
3650 new_adv |= ADVERTISED_100baseT_Half |
3651 ADVERTISED_100baseT_Full;
3653 tg3_phy_autoneg_cfg(tp, new_adv,
3654 FLOW_CTRL_TX | FLOW_CTRL_RX);
3655 } else if (tp->link_config.speed == SPEED_INVALID) {
3656 if (tp->phy_flags & TG3_PHYFLG_10_100_ONLY)
3657 tp->link_config.advertising &=
3658 ~(ADVERTISED_1000baseT_Half |
3659 ADVERTISED_1000baseT_Full);
3661 tg3_phy_autoneg_cfg(tp, tp->link_config.advertising,
3662 tp->link_config.flowctrl);
3664 /* Asking for a specific link mode. */
3665 if (tp->link_config.speed == SPEED_1000) {
3666 if (tp->link_config.duplex == DUPLEX_FULL)
3667 new_adv = ADVERTISED_1000baseT_Full;
3669 new_adv = ADVERTISED_1000baseT_Half;
3670 } else if (tp->link_config.speed == SPEED_100) {
3671 if (tp->link_config.duplex == DUPLEX_FULL)
3672 new_adv = ADVERTISED_100baseT_Full;
3674 new_adv = ADVERTISED_100baseT_Half;
3676 if (tp->link_config.duplex == DUPLEX_FULL)
3677 new_adv = ADVERTISED_10baseT_Full;
3679 new_adv = ADVERTISED_10baseT_Half;
3682 tg3_phy_autoneg_cfg(tp, new_adv,
3683 tp->link_config.flowctrl);
3686 if (tp->link_config.autoneg == AUTONEG_DISABLE &&
3687 tp->link_config.speed != SPEED_INVALID) {
3688 u32 bmcr, orig_bmcr;
3690 tp->link_config.active_speed = tp->link_config.speed;
3691 tp->link_config.active_duplex = tp->link_config.duplex;
3694 switch (tp->link_config.speed) {
3700 bmcr |= BMCR_SPEED100;
3704 bmcr |= BMCR_SPEED1000;
3708 if (tp->link_config.duplex == DUPLEX_FULL)
3709 bmcr |= BMCR_FULLDPLX;
3711 if (!tg3_readphy(tp, MII_BMCR, &orig_bmcr) &&
3712 (bmcr != orig_bmcr)) {
3713 tg3_writephy(tp, MII_BMCR, BMCR_LOOPBACK);
3714 for (i = 0; i < 1500; i++) {
3718 if (tg3_readphy(tp, MII_BMSR, &tmp) ||
3719 tg3_readphy(tp, MII_BMSR, &tmp))
3721 if (!(tmp & BMSR_LSTATUS)) {
3726 tg3_writephy(tp, MII_BMCR, bmcr);
3730 tg3_writephy(tp, MII_BMCR,
3731 BMCR_ANENABLE | BMCR_ANRESTART);
3735 static int tg3_init_5401phy_dsp(struct tg3 *tp)
3739 /* Turn off tap power management. */
3740 /* Set Extended packet length bit */
3741 err = tg3_phy_auxctl_write(tp, MII_TG3_AUXCTL_SHDWSEL_AUXCTL, 0x4c20);
3743 err |= tg3_phydsp_write(tp, 0x0012, 0x1804);
3744 err |= tg3_phydsp_write(tp, 0x0013, 0x1204);
3745 err |= tg3_phydsp_write(tp, 0x8006, 0x0132);
3746 err |= tg3_phydsp_write(tp, 0x8006, 0x0232);
3747 err |= tg3_phydsp_write(tp, 0x201f, 0x0a20);
3754 static bool tg3_phy_copper_an_config_ok(struct tg3 *tp, u32 *lcladv)
3756 u32 advmsk, tgtadv, advertising;
3758 advertising = tp->link_config.advertising;
3759 tgtadv = ethtool_adv_to_mii_adv_t(advertising) & ADVERTISE_ALL;
3761 advmsk = ADVERTISE_ALL;
3762 if (tp->link_config.active_duplex == DUPLEX_FULL) {
3763 tgtadv |= mii_advertise_flowctrl(tp->link_config.flowctrl);
3764 advmsk |= ADVERTISE_PAUSE_CAP | ADVERTISE_PAUSE_ASYM;
3767 if (tg3_readphy(tp, MII_ADVERTISE, lcladv))
3770 if ((*lcladv & advmsk) != tgtadv)
3773 if (!(tp->phy_flags & TG3_PHYFLG_10_100_ONLY)) {
3776 tgtadv = ethtool_adv_to_mii_ctrl1000_t(advertising);
3778 if (tg3_readphy(tp, MII_CTRL1000, &tg3_ctrl))
3781 tg3_ctrl &= (ADVERTISE_1000HALF | ADVERTISE_1000FULL);
3782 if (tg3_ctrl != tgtadv)
3789 static bool tg3_phy_copper_fetch_rmtadv(struct tg3 *tp, u32 *rmtadv)
3793 if (!(tp->phy_flags & TG3_PHYFLG_10_100_ONLY)) {
3796 if (tg3_readphy(tp, MII_STAT1000, &val))
3799 lpeth = mii_stat1000_to_ethtool_lpa_t(val);
3802 if (tg3_readphy(tp, MII_LPA, rmtadv))
3805 lpeth |= mii_lpa_to_ethtool_lpa_t(*rmtadv);
3806 tp->link_config.rmt_adv = lpeth;
3811 static int tg3_setup_copper_phy(struct tg3 *tp, int force_reset)
3813 int current_link_up;
3815 u32 lcl_adv, rmt_adv;
3823 (MAC_STATUS_SYNC_CHANGED |
3824 MAC_STATUS_CFG_CHANGED |
3825 MAC_STATUS_MI_COMPLETION |
3826 MAC_STATUS_LNKSTATE_CHANGED));
3829 if ((tp->mi_mode & MAC_MI_MODE_AUTO_POLL) != 0) {
3831 (tp->mi_mode & ~MAC_MI_MODE_AUTO_POLL));
3835 tg3_phy_auxctl_write(tp, MII_TG3_AUXCTL_SHDWSEL_PWRCTL, 0);
3837 /* Some third-party PHYs need to be reset on link going
3840 if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703 ||
3841 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704 ||
3842 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705) &&
3843 netif_carrier_ok(tp->dev)) {
3844 tg3_readphy(tp, MII_BMSR, &bmsr);
3845 if (!tg3_readphy(tp, MII_BMSR, &bmsr) &&
3846 !(bmsr & BMSR_LSTATUS))
3852 if ((tp->phy_id & TG3_PHY_ID_MASK) == TG3_PHY_ID_BCM5401) {
3853 tg3_readphy(tp, MII_BMSR, &bmsr);
3854 if (tg3_readphy(tp, MII_BMSR, &bmsr) ||
3855 !tg3_flag(tp, INIT_COMPLETE))
3858 if (!(bmsr & BMSR_LSTATUS)) {
3859 err = tg3_init_5401phy_dsp(tp);
3863 tg3_readphy(tp, MII_BMSR, &bmsr);
3864 for (i = 0; i < 1000; i++) {
3866 if (!tg3_readphy(tp, MII_BMSR, &bmsr) &&
3867 (bmsr & BMSR_LSTATUS)) {
3873 if ((tp->phy_id & TG3_PHY_ID_REV_MASK) ==
3874 TG3_PHY_REV_BCM5401_B0 &&
3875 !(bmsr & BMSR_LSTATUS) &&
3876 tp->link_config.active_speed == SPEED_1000) {
3877 err = tg3_phy_reset(tp);
3879 err = tg3_init_5401phy_dsp(tp);
3884 } else if (tp->pci_chip_rev_id == CHIPREV_ID_5701_A0 ||
3885 tp->pci_chip_rev_id == CHIPREV_ID_5701_B0) {
3886 /* 5701 {A0,B0} CRC bug workaround */
3887 tg3_writephy(tp, 0x15, 0x0a75);
3888 tg3_writephy(tp, MII_TG3_MISC_SHDW, 0x8c68);
3889 tg3_writephy(tp, MII_TG3_MISC_SHDW, 0x8d68);
3890 tg3_writephy(tp, MII_TG3_MISC_SHDW, 0x8c68);
3893 /* Clear pending interrupts... */
3894 tg3_readphy(tp, MII_TG3_ISTAT, &val);
3895 tg3_readphy(tp, MII_TG3_ISTAT, &val);
3897 if (tp->phy_flags & TG3_PHYFLG_USE_MI_INTERRUPT)
3898 tg3_writephy(tp, MII_TG3_IMASK, ~MII_TG3_INT_LINKCHG);
3899 else if (!(tp->phy_flags & TG3_PHYFLG_IS_FET))
3900 tg3_writephy(tp, MII_TG3_IMASK, ~0);
3902 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
3903 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701) {
3904 if (tp->led_ctrl == LED_CTRL_MODE_PHY_1)
3905 tg3_writephy(tp, MII_TG3_EXT_CTRL,
3906 MII_TG3_EXT_CTRL_LNK3_LED_MODE);
3908 tg3_writephy(tp, MII_TG3_EXT_CTRL, 0);
3911 current_link_up = 0;
3912 current_speed = SPEED_INVALID;
3913 current_duplex = DUPLEX_INVALID;
3914 tp->phy_flags &= ~TG3_PHYFLG_MDIX_STATE;
3915 tp->link_config.rmt_adv = 0;
3917 if (tp->phy_flags & TG3_PHYFLG_CAPACITIVE_COUPLING) {
3918 err = tg3_phy_auxctl_read(tp,
3919 MII_TG3_AUXCTL_SHDWSEL_MISCTEST,
3921 if (!err && !(val & (1 << 10))) {
3922 tg3_phy_auxctl_write(tp,
3923 MII_TG3_AUXCTL_SHDWSEL_MISCTEST,
3930 for (i = 0; i < 100; i++) {
3931 tg3_readphy(tp, MII_BMSR, &bmsr);
3932 if (!tg3_readphy(tp, MII_BMSR, &bmsr) &&
3933 (bmsr & BMSR_LSTATUS))
3938 if (bmsr & BMSR_LSTATUS) {
3941 tg3_readphy(tp, MII_TG3_AUX_STAT, &aux_stat);
3942 for (i = 0; i < 2000; i++) {
3944 if (!tg3_readphy(tp, MII_TG3_AUX_STAT, &aux_stat) &&
3949 tg3_aux_stat_to_speed_duplex(tp, aux_stat,
3954 for (i = 0; i < 200; i++) {
3955 tg3_readphy(tp, MII_BMCR, &bmcr);
3956 if (tg3_readphy(tp, MII_BMCR, &bmcr))
3958 if (bmcr && bmcr != 0x7fff)
3966 tp->link_config.active_speed = current_speed;
3967 tp->link_config.active_duplex = current_duplex;
3969 if (tp->link_config.autoneg == AUTONEG_ENABLE) {
3970 if ((bmcr & BMCR_ANENABLE) &&
3971 tg3_phy_copper_an_config_ok(tp, &lcl_adv) &&
3972 tg3_phy_copper_fetch_rmtadv(tp, &rmt_adv))
3973 current_link_up = 1;
3975 if (!(bmcr & BMCR_ANENABLE) &&
3976 tp->link_config.speed == current_speed &&
3977 tp->link_config.duplex == current_duplex &&
3978 tp->link_config.flowctrl ==
3979 tp->link_config.active_flowctrl) {
3980 current_link_up = 1;
3984 if (current_link_up == 1 &&
3985 tp->link_config.active_duplex == DUPLEX_FULL) {
3988 if (tp->phy_flags & TG3_PHYFLG_IS_FET) {
3989 reg = MII_TG3_FET_GEN_STAT;
3990 bit = MII_TG3_FET_GEN_STAT_MDIXSTAT;
3992 reg = MII_TG3_EXT_STAT;
3993 bit = MII_TG3_EXT_STAT_MDIX;
3996 if (!tg3_readphy(tp, reg, &val) && (val & bit))
3997 tp->phy_flags |= TG3_PHYFLG_MDIX_STATE;
3999 tg3_setup_flow_control(tp, lcl_adv, rmt_adv);
4004 if (current_link_up == 0 || (tp->phy_flags & TG3_PHYFLG_IS_LOW_POWER)) {
4005 tg3_phy_copper_begin(tp);
4007 tg3_readphy(tp, MII_BMSR, &bmsr);
4008 if ((!tg3_readphy(tp, MII_BMSR, &bmsr) && (bmsr & BMSR_LSTATUS)) ||
4009 (tp->mac_mode & MAC_MODE_PORT_INT_LPBACK))
4010 current_link_up = 1;
4013 tp->mac_mode &= ~MAC_MODE_PORT_MODE_MASK;
4014 if (current_link_up == 1) {
4015 if (tp->link_config.active_speed == SPEED_100 ||
4016 tp->link_config.active_speed == SPEED_10)
4017 tp->mac_mode |= MAC_MODE_PORT_MODE_MII;
4019 tp->mac_mode |= MAC_MODE_PORT_MODE_GMII;
4020 } else if (tp->phy_flags & TG3_PHYFLG_IS_FET)
4021 tp->mac_mode |= MAC_MODE_PORT_MODE_MII;
4023 tp->mac_mode |= MAC_MODE_PORT_MODE_GMII;
4025 tp->mac_mode &= ~MAC_MODE_HALF_DUPLEX;
4026 if (tp->link_config.active_duplex == DUPLEX_HALF)
4027 tp->mac_mode |= MAC_MODE_HALF_DUPLEX;
4029 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700) {
4030 if (current_link_up == 1 &&
4031 tg3_5700_link_polarity(tp, tp->link_config.active_speed))
4032 tp->mac_mode |= MAC_MODE_LINK_POLARITY;
4034 tp->mac_mode &= ~MAC_MODE_LINK_POLARITY;
4037 /* ??? Without this setting Netgear GA302T PHY does not
4038 * ??? send/receive packets...
4040 if ((tp->phy_id & TG3_PHY_ID_MASK) == TG3_PHY_ID_BCM5411 &&
4041 tp->pci_chip_rev_id == CHIPREV_ID_5700_ALTIMA) {
4042 tp->mi_mode |= MAC_MI_MODE_AUTO_POLL;
4043 tw32_f(MAC_MI_MODE, tp->mi_mode);
4047 tw32_f(MAC_MODE, tp->mac_mode);
4050 tg3_phy_eee_adjust(tp, current_link_up);
4052 if (tg3_flag(tp, USE_LINKCHG_REG)) {
4053 /* Polled via timer. */
4054 tw32_f(MAC_EVENT, 0);
4056 tw32_f(MAC_EVENT, MAC_EVENT_LNKSTATE_CHANGED);
4060 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 &&
4061 current_link_up == 1 &&
4062 tp->link_config.active_speed == SPEED_1000 &&
4063 (tg3_flag(tp, PCIX_MODE) || tg3_flag(tp, PCI_HIGH_SPEED))) {
4066 (MAC_STATUS_SYNC_CHANGED |
4067 MAC_STATUS_CFG_CHANGED));
4070 NIC_SRAM_FIRMWARE_MBOX,
4071 NIC_SRAM_FIRMWARE_MBOX_MAGIC2);
4074 /* Prevent send BD corruption. */
4075 if (tg3_flag(tp, CLKREQ_BUG)) {
4076 u16 oldlnkctl, newlnkctl;
4078 pci_read_config_word(tp->pdev,
4079 pci_pcie_cap(tp->pdev) + PCI_EXP_LNKCTL,
4081 if (tp->link_config.active_speed == SPEED_100 ||
4082 tp->link_config.active_speed == SPEED_10)
4083 newlnkctl = oldlnkctl & ~PCI_EXP_LNKCTL_CLKREQ_EN;
4085 newlnkctl = oldlnkctl | PCI_EXP_LNKCTL_CLKREQ_EN;
4086 if (newlnkctl != oldlnkctl)
4087 pci_write_config_word(tp->pdev,
4088 pci_pcie_cap(tp->pdev) +
4089 PCI_EXP_LNKCTL, newlnkctl);
4092 if (current_link_up != netif_carrier_ok(tp->dev)) {
4093 if (current_link_up)
4094 netif_carrier_on(tp->dev);
4096 netif_carrier_off(tp->dev);
4097 tg3_link_report(tp);
4103 struct tg3_fiber_aneginfo {
4105 #define ANEG_STATE_UNKNOWN 0
4106 #define ANEG_STATE_AN_ENABLE 1
4107 #define ANEG_STATE_RESTART_INIT 2
4108 #define ANEG_STATE_RESTART 3
4109 #define ANEG_STATE_DISABLE_LINK_OK 4
4110 #define ANEG_STATE_ABILITY_DETECT_INIT 5
4111 #define ANEG_STATE_ABILITY_DETECT 6
4112 #define ANEG_STATE_ACK_DETECT_INIT 7
4113 #define ANEG_STATE_ACK_DETECT 8
4114 #define ANEG_STATE_COMPLETE_ACK_INIT 9
4115 #define ANEG_STATE_COMPLETE_ACK 10
4116 #define ANEG_STATE_IDLE_DETECT_INIT 11
4117 #define ANEG_STATE_IDLE_DETECT 12
4118 #define ANEG_STATE_LINK_OK 13
4119 #define ANEG_STATE_NEXT_PAGE_WAIT_INIT 14
4120 #define ANEG_STATE_NEXT_PAGE_WAIT 15
4123 #define MR_AN_ENABLE 0x00000001
4124 #define MR_RESTART_AN 0x00000002
4125 #define MR_AN_COMPLETE 0x00000004
4126 #define MR_PAGE_RX 0x00000008
4127 #define MR_NP_LOADED 0x00000010
4128 #define MR_TOGGLE_TX 0x00000020
4129 #define MR_LP_ADV_FULL_DUPLEX 0x00000040
4130 #define MR_LP_ADV_HALF_DUPLEX 0x00000080
4131 #define MR_LP_ADV_SYM_PAUSE 0x00000100
4132 #define MR_LP_ADV_ASYM_PAUSE 0x00000200
4133 #define MR_LP_ADV_REMOTE_FAULT1 0x00000400
4134 #define MR_LP_ADV_REMOTE_FAULT2 0x00000800
4135 #define MR_LP_ADV_NEXT_PAGE 0x00001000
4136 #define MR_TOGGLE_RX 0x00002000
4137 #define MR_NP_RX 0x00004000
4139 #define MR_LINK_OK 0x80000000
4141 unsigned long link_time, cur_time;
4143 u32 ability_match_cfg;
4144 int ability_match_count;
4146 char ability_match, idle_match, ack_match;
4148 u32 txconfig, rxconfig;
4149 #define ANEG_CFG_NP 0x00000080
4150 #define ANEG_CFG_ACK 0x00000040
4151 #define ANEG_CFG_RF2 0x00000020
4152 #define ANEG_CFG_RF1 0x00000010
4153 #define ANEG_CFG_PS2 0x00000001
4154 #define ANEG_CFG_PS1 0x00008000
4155 #define ANEG_CFG_HD 0x00004000
4156 #define ANEG_CFG_FD 0x00002000
4157 #define ANEG_CFG_INVAL 0x00001f06
4162 #define ANEG_TIMER_ENAB 2
4163 #define ANEG_FAILED -1
4165 #define ANEG_STATE_SETTLE_TIME 10000
4167 static int tg3_fiber_aneg_smachine(struct tg3 *tp,
4168 struct tg3_fiber_aneginfo *ap)
4171 unsigned long delta;
4175 if (ap->state == ANEG_STATE_UNKNOWN) {
4179 ap->ability_match_cfg = 0;
4180 ap->ability_match_count = 0;
4181 ap->ability_match = 0;
4187 if (tr32(MAC_STATUS) & MAC_STATUS_RCVD_CFG) {
4188 rx_cfg_reg = tr32(MAC_RX_AUTO_NEG);
4190 if (rx_cfg_reg != ap->ability_match_cfg) {
4191 ap->ability_match_cfg = rx_cfg_reg;
4192 ap->ability_match = 0;
4193 ap->ability_match_count = 0;
4195 if (++ap->ability_match_count > 1) {
4196 ap->ability_match = 1;
4197 ap->ability_match_cfg = rx_cfg_reg;
4200 if (rx_cfg_reg & ANEG_CFG_ACK)
4208 ap->ability_match_cfg = 0;
4209 ap->ability_match_count = 0;
4210 ap->ability_match = 0;
4216 ap->rxconfig = rx_cfg_reg;
4219 switch (ap->state) {
4220 case ANEG_STATE_UNKNOWN:
4221 if (ap->flags & (MR_AN_ENABLE | MR_RESTART_AN))
4222 ap->state = ANEG_STATE_AN_ENABLE;
4225 case ANEG_STATE_AN_ENABLE:
4226 ap->flags &= ~(MR_AN_COMPLETE | MR_PAGE_RX);
4227 if (ap->flags & MR_AN_ENABLE) {
4230 ap->ability_match_cfg = 0;
4231 ap->ability_match_count = 0;
4232 ap->ability_match = 0;
4236 ap->state = ANEG_STATE_RESTART_INIT;
4238 ap->state = ANEG_STATE_DISABLE_LINK_OK;
4242 case ANEG_STATE_RESTART_INIT:
4243 ap->link_time = ap->cur_time;
4244 ap->flags &= ~(MR_NP_LOADED);
4246 tw32(MAC_TX_AUTO_NEG, 0);
4247 tp->mac_mode |= MAC_MODE_SEND_CONFIGS;
4248 tw32_f(MAC_MODE, tp->mac_mode);
4251 ret = ANEG_TIMER_ENAB;
4252 ap->state = ANEG_STATE_RESTART;
4255 case ANEG_STATE_RESTART:
4256 delta = ap->cur_time - ap->link_time;
4257 if (delta > ANEG_STATE_SETTLE_TIME)
4258 ap->state = ANEG_STATE_ABILITY_DETECT_INIT;
4260 ret = ANEG_TIMER_ENAB;
4263 case ANEG_STATE_DISABLE_LINK_OK:
4267 case ANEG_STATE_ABILITY_DETECT_INIT:
4268 ap->flags &= ~(MR_TOGGLE_TX);
4269 ap->txconfig = ANEG_CFG_FD;
4270 flowctrl = tg3_advert_flowctrl_1000X(tp->link_config.flowctrl);
4271 if (flowctrl & ADVERTISE_1000XPAUSE)
4272 ap->txconfig |= ANEG_CFG_PS1;
4273 if (flowctrl & ADVERTISE_1000XPSE_ASYM)
4274 ap->txconfig |= ANEG_CFG_PS2;
4275 tw32(MAC_TX_AUTO_NEG, ap->txconfig);
4276 tp->mac_mode |= MAC_MODE_SEND_CONFIGS;
4277 tw32_f(MAC_MODE, tp->mac_mode);
4280 ap->state = ANEG_STATE_ABILITY_DETECT;
4283 case ANEG_STATE_ABILITY_DETECT:
4284 if (ap->ability_match != 0 && ap->rxconfig != 0)
4285 ap->state = ANEG_STATE_ACK_DETECT_INIT;
4288 case ANEG_STATE_ACK_DETECT_INIT:
4289 ap->txconfig |= ANEG_CFG_ACK;
4290 tw32(MAC_TX_AUTO_NEG, ap->txconfig);
4291 tp->mac_mode |= MAC_MODE_SEND_CONFIGS;
4292 tw32_f(MAC_MODE, tp->mac_mode);
4295 ap->state = ANEG_STATE_ACK_DETECT;
4298 case ANEG_STATE_ACK_DETECT:
4299 if (ap->ack_match != 0) {
4300 if ((ap->rxconfig & ~ANEG_CFG_ACK) ==
4301 (ap->ability_match_cfg & ~ANEG_CFG_ACK)) {
4302 ap->state = ANEG_STATE_COMPLETE_ACK_INIT;
4304 ap->state = ANEG_STATE_AN_ENABLE;
4306 } else if (ap->ability_match != 0 &&
4307 ap->rxconfig == 0) {
4308 ap->state = ANEG_STATE_AN_ENABLE;
4312 case ANEG_STATE_COMPLETE_ACK_INIT:
4313 if (ap->rxconfig & ANEG_CFG_INVAL) {
4317 ap->flags &= ~(MR_LP_ADV_FULL_DUPLEX |
4318 MR_LP_ADV_HALF_DUPLEX |
4319 MR_LP_ADV_SYM_PAUSE |
4320 MR_LP_ADV_ASYM_PAUSE |
4321 MR_LP_ADV_REMOTE_FAULT1 |
4322 MR_LP_ADV_REMOTE_FAULT2 |
4323 MR_LP_ADV_NEXT_PAGE |
4326 if (ap->rxconfig & ANEG_CFG_FD)
4327 ap->flags |= MR_LP_ADV_FULL_DUPLEX;
4328 if (ap->rxconfig & ANEG_CFG_HD)
4329 ap->flags |= MR_LP_ADV_HALF_DUPLEX;
4330 if (ap->rxconfig & ANEG_CFG_PS1)
4331 ap->flags |= MR_LP_ADV_SYM_PAUSE;
4332 if (ap->rxconfig & ANEG_CFG_PS2)
4333 ap->flags |= MR_LP_ADV_ASYM_PAUSE;
4334 if (ap->rxconfig & ANEG_CFG_RF1)
4335 ap->flags |= MR_LP_ADV_REMOTE_FAULT1;
4336 if (ap->rxconfig & ANEG_CFG_RF2)
4337 ap->flags |= MR_LP_ADV_REMOTE_FAULT2;
4338 if (ap->rxconfig & ANEG_CFG_NP)
4339 ap->flags |= MR_LP_ADV_NEXT_PAGE;
4341 ap->link_time = ap->cur_time;
4343 ap->flags ^= (MR_TOGGLE_TX);
4344 if (ap->rxconfig & 0x0008)
4345 ap->flags |= MR_TOGGLE_RX;
4346 if (ap->rxconfig & ANEG_CFG_NP)
4347 ap->flags |= MR_NP_RX;
4348 ap->flags |= MR_PAGE_RX;
4350 ap->state = ANEG_STATE_COMPLETE_ACK;
4351 ret = ANEG_TIMER_ENAB;
4354 case ANEG_STATE_COMPLETE_ACK:
4355 if (ap->ability_match != 0 &&
4356 ap->rxconfig == 0) {
4357 ap->state = ANEG_STATE_AN_ENABLE;
4360 delta = ap->cur_time - ap->link_time;
4361 if (delta > ANEG_STATE_SETTLE_TIME) {
4362 if (!(ap->flags & (MR_LP_ADV_NEXT_PAGE))) {
4363 ap->state = ANEG_STATE_IDLE_DETECT_INIT;
4365 if ((ap->txconfig & ANEG_CFG_NP) == 0 &&
4366 !(ap->flags & MR_NP_RX)) {
4367 ap->state = ANEG_STATE_IDLE_DETECT_INIT;
4375 case ANEG_STATE_IDLE_DETECT_INIT:
4376 ap->link_time = ap->cur_time;
4377 tp->mac_mode &= ~MAC_MODE_SEND_CONFIGS;
4378 tw32_f(MAC_MODE, tp->mac_mode);
4381 ap->state = ANEG_STATE_IDLE_DETECT;
4382 ret = ANEG_TIMER_ENAB;
4385 case ANEG_STATE_IDLE_DETECT:
4386 if (ap->ability_match != 0 &&
4387 ap->rxconfig == 0) {
4388 ap->state = ANEG_STATE_AN_ENABLE;
4391 delta = ap->cur_time - ap->link_time;
4392 if (delta > ANEG_STATE_SETTLE_TIME) {
4393 /* XXX another gem from the Broadcom driver :( */
4394 ap->state = ANEG_STATE_LINK_OK;
4398 case ANEG_STATE_LINK_OK:
4399 ap->flags |= (MR_AN_COMPLETE | MR_LINK_OK);
4403 case ANEG_STATE_NEXT_PAGE_WAIT_INIT:
4404 /* ??? unimplemented */
4407 case ANEG_STATE_NEXT_PAGE_WAIT:
4408 /* ??? unimplemented */
4419 static int fiber_autoneg(struct tg3 *tp, u32 *txflags, u32 *rxflags)
4422 struct tg3_fiber_aneginfo aninfo;
4423 int status = ANEG_FAILED;
4427 tw32_f(MAC_TX_AUTO_NEG, 0);
4429 tmp = tp->mac_mode & ~MAC_MODE_PORT_MODE_MASK;
4430 tw32_f(MAC_MODE, tmp | MAC_MODE_PORT_MODE_GMII);
4433 tw32_f(MAC_MODE, tp->mac_mode | MAC_MODE_SEND_CONFIGS);
4436 memset(&aninfo, 0, sizeof(aninfo));
4437 aninfo.flags |= MR_AN_ENABLE;
4438 aninfo.state = ANEG_STATE_UNKNOWN;
4439 aninfo.cur_time = 0;
4441 while (++tick < 195000) {
4442 status = tg3_fiber_aneg_smachine(tp, &aninfo);
4443 if (status == ANEG_DONE || status == ANEG_FAILED)
4449 tp->mac_mode &= ~MAC_MODE_SEND_CONFIGS;
4450 tw32_f(MAC_MODE, tp->mac_mode);
4453 *txflags = aninfo.txconfig;
4454 *rxflags = aninfo.flags;
4456 if (status == ANEG_DONE &&
4457 (aninfo.flags & (MR_AN_COMPLETE | MR_LINK_OK |
4458 MR_LP_ADV_FULL_DUPLEX)))
4464 static void tg3_init_bcm8002(struct tg3 *tp)
4466 u32 mac_status = tr32(MAC_STATUS);
4469 /* Reset when initting first time or we have a link. */
4470 if (tg3_flag(tp, INIT_COMPLETE) &&
4471 !(mac_status & MAC_STATUS_PCS_SYNCED))
4474 /* Set PLL lock range. */
4475 tg3_writephy(tp, 0x16, 0x8007);
4478 tg3_writephy(tp, MII_BMCR, BMCR_RESET);
4480 /* Wait for reset to complete. */
4481 /* XXX schedule_timeout() ... */
4482 for (i = 0; i < 500; i++)
4485 /* Config mode; select PMA/Ch 1 regs. */
4486 tg3_writephy(tp, 0x10, 0x8411);
4488 /* Enable auto-lock and comdet, select txclk for tx. */
4489 tg3_writephy(tp, 0x11, 0x0a10);
4491 tg3_writephy(tp, 0x18, 0x00a0);
4492 tg3_writephy(tp, 0x16, 0x41ff);
4494 /* Assert and deassert POR. */
4495 tg3_writephy(tp, 0x13, 0x0400);
4497 tg3_writephy(tp, 0x13, 0x0000);
4499 tg3_writephy(tp, 0x11, 0x0a50);
4501 tg3_writephy(tp, 0x11, 0x0a10);
4503 /* Wait for signal to stabilize */
4504 /* XXX schedule_timeout() ... */
4505 for (i = 0; i < 15000; i++)
4508 /* Deselect the channel register so we can read the PHYID
4511 tg3_writephy(tp, 0x10, 0x8011);
4514 static int tg3_setup_fiber_hw_autoneg(struct tg3 *tp, u32 mac_status)
4517 u32 sg_dig_ctrl, sg_dig_status;
4518 u32 serdes_cfg, expected_sg_dig_ctrl;
4519 int workaround, port_a;
4520 int current_link_up;
4523 expected_sg_dig_ctrl = 0;
4526 current_link_up = 0;
4528 if (tp->pci_chip_rev_id != CHIPREV_ID_5704_A0 &&
4529 tp->pci_chip_rev_id != CHIPREV_ID_5704_A1) {
4531 if (tr32(TG3PCI_DUAL_MAC_CTRL) & DUAL_MAC_CTRL_ID)
4534 /* preserve bits 0-11,13,14 for signal pre-emphasis */
4535 /* preserve bits 20-23 for voltage regulator */
4536 serdes_cfg = tr32(MAC_SERDES_CFG) & 0x00f06fff;
4539 sg_dig_ctrl = tr32(SG_DIG_CTRL);
4541 if (tp->link_config.autoneg != AUTONEG_ENABLE) {
4542 if (sg_dig_ctrl & SG_DIG_USING_HW_AUTONEG) {
4544 u32 val = serdes_cfg;
4550 tw32_f(MAC_SERDES_CFG, val);
4553 tw32_f(SG_DIG_CTRL, SG_DIG_COMMON_SETUP);
4555 if (mac_status & MAC_STATUS_PCS_SYNCED) {
4556 tg3_setup_flow_control(tp, 0, 0);
4557 current_link_up = 1;
4562 /* Want auto-negotiation. */
4563 expected_sg_dig_ctrl = SG_DIG_USING_HW_AUTONEG | SG_DIG_COMMON_SETUP;
4565 flowctrl = tg3_advert_flowctrl_1000X(tp->link_config.flowctrl);
4566 if (flowctrl & ADVERTISE_1000XPAUSE)
4567 expected_sg_dig_ctrl |= SG_DIG_PAUSE_CAP;
4568 if (flowctrl & ADVERTISE_1000XPSE_ASYM)
4569 expected_sg_dig_ctrl |= SG_DIG_ASYM_PAUSE;
4571 if (sg_dig_ctrl != expected_sg_dig_ctrl) {
4572 if ((tp->phy_flags & TG3_PHYFLG_PARALLEL_DETECT) &&
4573 tp->serdes_counter &&
4574 ((mac_status & (MAC_STATUS_PCS_SYNCED |
4575 MAC_STATUS_RCVD_CFG)) ==
4576 MAC_STATUS_PCS_SYNCED)) {
4577 tp->serdes_counter--;
4578 current_link_up = 1;
4583 tw32_f(MAC_SERDES_CFG, serdes_cfg | 0xc011000);
4584 tw32_f(SG_DIG_CTRL, expected_sg_dig_ctrl | SG_DIG_SOFT_RESET);
4586 tw32_f(SG_DIG_CTRL, expected_sg_dig_ctrl);
4588 tp->serdes_counter = SERDES_AN_TIMEOUT_5704S;
4589 tp->phy_flags &= ~TG3_PHYFLG_PARALLEL_DETECT;
4590 } else if (mac_status & (MAC_STATUS_PCS_SYNCED |
4591 MAC_STATUS_SIGNAL_DET)) {
4592 sg_dig_status = tr32(SG_DIG_STATUS);
4593 mac_status = tr32(MAC_STATUS);
4595 if ((sg_dig_status & SG_DIG_AUTONEG_COMPLETE) &&
4596 (mac_status & MAC_STATUS_PCS_SYNCED)) {
4597 u32 local_adv = 0, remote_adv = 0;
4599 if (sg_dig_ctrl & SG_DIG_PAUSE_CAP)
4600 local_adv |= ADVERTISE_1000XPAUSE;
4601 if (sg_dig_ctrl & SG_DIG_ASYM_PAUSE)
4602 local_adv |= ADVERTISE_1000XPSE_ASYM;
4604 if (sg_dig_status & SG_DIG_PARTNER_PAUSE_CAPABLE)
4605 remote_adv |= LPA_1000XPAUSE;
4606 if (sg_dig_status & SG_DIG_PARTNER_ASYM_PAUSE)
4607 remote_adv |= LPA_1000XPAUSE_ASYM;
4609 tp->link_config.rmt_adv =
4610 mii_adv_to_ethtool_adv_x(remote_adv);
4612 tg3_setup_flow_control(tp, local_adv, remote_adv);
4613 current_link_up = 1;
4614 tp->serdes_counter = 0;
4615 tp->phy_flags &= ~TG3_PHYFLG_PARALLEL_DETECT;
4616 } else if (!(sg_dig_status & SG_DIG_AUTONEG_COMPLETE)) {
4617 if (tp->serdes_counter)
4618 tp->serdes_counter--;
4621 u32 val = serdes_cfg;
4628 tw32_f(MAC_SERDES_CFG, val);
4631 tw32_f(SG_DIG_CTRL, SG_DIG_COMMON_SETUP);
4634 /* Link parallel detection - link is up */
4635 /* only if we have PCS_SYNC and not */
4636 /* receiving config code words */
4637 mac_status = tr32(MAC_STATUS);
4638 if ((mac_status & MAC_STATUS_PCS_SYNCED) &&
4639 !(mac_status & MAC_STATUS_RCVD_CFG)) {
4640 tg3_setup_flow_control(tp, 0, 0);
4641 current_link_up = 1;
4643 TG3_PHYFLG_PARALLEL_DETECT;
4644 tp->serdes_counter =
4645 SERDES_PARALLEL_DET_TIMEOUT;
4647 goto restart_autoneg;
4651 tp->serdes_counter = SERDES_AN_TIMEOUT_5704S;
4652 tp->phy_flags &= ~TG3_PHYFLG_PARALLEL_DETECT;
4656 return current_link_up;
4659 static int tg3_setup_fiber_by_hand(struct tg3 *tp, u32 mac_status)
4661 int current_link_up = 0;
4663 if (!(mac_status & MAC_STATUS_PCS_SYNCED))
4666 if (tp->link_config.autoneg == AUTONEG_ENABLE) {
4667 u32 txflags, rxflags;
4670 if (fiber_autoneg(tp, &txflags, &rxflags)) {
4671 u32 local_adv = 0, remote_adv = 0;
4673 if (txflags & ANEG_CFG_PS1)
4674 local_adv |= ADVERTISE_1000XPAUSE;
4675 if (txflags & ANEG_CFG_PS2)
4676 local_adv |= ADVERTISE_1000XPSE_ASYM;
4678 if (rxflags & MR_LP_ADV_SYM_PAUSE)
4679 remote_adv |= LPA_1000XPAUSE;
4680 if (rxflags & MR_LP_ADV_ASYM_PAUSE)
4681 remote_adv |= LPA_1000XPAUSE_ASYM;
4683 tp->link_config.rmt_adv =
4684 mii_adv_to_ethtool_adv_x(remote_adv);
4686 tg3_setup_flow_control(tp, local_adv, remote_adv);
4688 current_link_up = 1;
4690 for (i = 0; i < 30; i++) {
4693 (MAC_STATUS_SYNC_CHANGED |
4694 MAC_STATUS_CFG_CHANGED));
4696 if ((tr32(MAC_STATUS) &
4697 (MAC_STATUS_SYNC_CHANGED |
4698 MAC_STATUS_CFG_CHANGED)) == 0)
4702 mac_status = tr32(MAC_STATUS);
4703 if (current_link_up == 0 &&
4704 (mac_status & MAC_STATUS_PCS_SYNCED) &&
4705 !(mac_status & MAC_STATUS_RCVD_CFG))
4706 current_link_up = 1;
4708 tg3_setup_flow_control(tp, 0, 0);
4710 /* Forcing 1000FD link up. */
4711 current_link_up = 1;
4713 tw32_f(MAC_MODE, (tp->mac_mode | MAC_MODE_SEND_CONFIGS));
4716 tw32_f(MAC_MODE, tp->mac_mode);
4721 return current_link_up;
4724 static int tg3_setup_fiber_phy(struct tg3 *tp, int force_reset)
4727 u16 orig_active_speed;
4728 u8 orig_active_duplex;
4730 int current_link_up;
4733 orig_pause_cfg = tp->link_config.active_flowctrl;
4734 orig_active_speed = tp->link_config.active_speed;
4735 orig_active_duplex = tp->link_config.active_duplex;
4737 if (!tg3_flag(tp, HW_AUTONEG) &&
4738 netif_carrier_ok(tp->dev) &&
4739 tg3_flag(tp, INIT_COMPLETE)) {
4740 mac_status = tr32(MAC_STATUS);
4741 mac_status &= (MAC_STATUS_PCS_SYNCED |
4742 MAC_STATUS_SIGNAL_DET |
4743 MAC_STATUS_CFG_CHANGED |
4744 MAC_STATUS_RCVD_CFG);
4745 if (mac_status == (MAC_STATUS_PCS_SYNCED |
4746 MAC_STATUS_SIGNAL_DET)) {
4747 tw32_f(MAC_STATUS, (MAC_STATUS_SYNC_CHANGED |
4748 MAC_STATUS_CFG_CHANGED));
4753 tw32_f(MAC_TX_AUTO_NEG, 0);
4755 tp->mac_mode &= ~(MAC_MODE_PORT_MODE_MASK | MAC_MODE_HALF_DUPLEX);
4756 tp->mac_mode |= MAC_MODE_PORT_MODE_TBI;
4757 tw32_f(MAC_MODE, tp->mac_mode);
4760 if (tp->phy_id == TG3_PHY_ID_BCM8002)
4761 tg3_init_bcm8002(tp);
4763 /* Enable link change event even when serdes polling. */
4764 tw32_f(MAC_EVENT, MAC_EVENT_LNKSTATE_CHANGED);
4767 current_link_up = 0;
4768 tp->link_config.rmt_adv = 0;
4769 mac_status = tr32(MAC_STATUS);
4771 if (tg3_flag(tp, HW_AUTONEG))
4772 current_link_up = tg3_setup_fiber_hw_autoneg(tp, mac_status);
4774 current_link_up = tg3_setup_fiber_by_hand(tp, mac_status);
4776 tp->napi[0].hw_status->status =
4777 (SD_STATUS_UPDATED |
4778 (tp->napi[0].hw_status->status & ~SD_STATUS_LINK_CHG));
4780 for (i = 0; i < 100; i++) {
4781 tw32_f(MAC_STATUS, (MAC_STATUS_SYNC_CHANGED |
4782 MAC_STATUS_CFG_CHANGED));
4784 if ((tr32(MAC_STATUS) & (MAC_STATUS_SYNC_CHANGED |
4785 MAC_STATUS_CFG_CHANGED |
4786 MAC_STATUS_LNKSTATE_CHANGED)) == 0)
4790 mac_status = tr32(MAC_STATUS);
4791 if ((mac_status & MAC_STATUS_PCS_SYNCED) == 0) {
4792 current_link_up = 0;
4793 if (tp->link_config.autoneg == AUTONEG_ENABLE &&
4794 tp->serdes_counter == 0) {
4795 tw32_f(MAC_MODE, (tp->mac_mode |
4796 MAC_MODE_SEND_CONFIGS));
4798 tw32_f(MAC_MODE, tp->mac_mode);
4802 if (current_link_up == 1) {
4803 tp->link_config.active_speed = SPEED_1000;
4804 tp->link_config.active_duplex = DUPLEX_FULL;
4805 tw32(MAC_LED_CTRL, (tp->led_ctrl |
4806 LED_CTRL_LNKLED_OVERRIDE |
4807 LED_CTRL_1000MBPS_ON));
4809 tp->link_config.active_speed = SPEED_INVALID;
4810 tp->link_config.active_duplex = DUPLEX_INVALID;
4811 tw32(MAC_LED_CTRL, (tp->led_ctrl |
4812 LED_CTRL_LNKLED_OVERRIDE |
4813 LED_CTRL_TRAFFIC_OVERRIDE));
4816 if (current_link_up != netif_carrier_ok(tp->dev)) {
4817 if (current_link_up)
4818 netif_carrier_on(tp->dev);
4820 netif_carrier_off(tp->dev);
4821 tg3_link_report(tp);
4823 u32 now_pause_cfg = tp->link_config.active_flowctrl;
4824 if (orig_pause_cfg != now_pause_cfg ||
4825 orig_active_speed != tp->link_config.active_speed ||
4826 orig_active_duplex != tp->link_config.active_duplex)
4827 tg3_link_report(tp);
4833 static int tg3_setup_fiber_mii_phy(struct tg3 *tp, int force_reset)
4835 int current_link_up, err = 0;
4839 u32 local_adv, remote_adv;
4841 tp->mac_mode |= MAC_MODE_PORT_MODE_GMII;
4842 tw32_f(MAC_MODE, tp->mac_mode);
4848 (MAC_STATUS_SYNC_CHANGED |
4849 MAC_STATUS_CFG_CHANGED |
4850 MAC_STATUS_MI_COMPLETION |
4851 MAC_STATUS_LNKSTATE_CHANGED));
4857 current_link_up = 0;
4858 current_speed = SPEED_INVALID;
4859 current_duplex = DUPLEX_INVALID;
4860 tp->link_config.rmt_adv = 0;
4862 err |= tg3_readphy(tp, MII_BMSR, &bmsr);
4863 err |= tg3_readphy(tp, MII_BMSR, &bmsr);
4864 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5714) {
4865 if (tr32(MAC_TX_STATUS) & TX_STATUS_LINK_UP)
4866 bmsr |= BMSR_LSTATUS;
4868 bmsr &= ~BMSR_LSTATUS;
4871 err |= tg3_readphy(tp, MII_BMCR, &bmcr);
4873 if ((tp->link_config.autoneg == AUTONEG_ENABLE) && !force_reset &&
4874 (tp->phy_flags & TG3_PHYFLG_PARALLEL_DETECT)) {
4875 /* do nothing, just check for link up at the end */
4876 } else if (tp->link_config.autoneg == AUTONEG_ENABLE) {
4879 err |= tg3_readphy(tp, MII_ADVERTISE, &adv);
4880 newadv = adv & ~(ADVERTISE_1000XFULL | ADVERTISE_1000XHALF |
4881 ADVERTISE_1000XPAUSE |
4882 ADVERTISE_1000XPSE_ASYM |
4885 newadv |= tg3_advert_flowctrl_1000X(tp->link_config.flowctrl);
4886 newadv |= ethtool_adv_to_mii_adv_x(tp->link_config.advertising);
4888 if ((newadv != adv) || !(bmcr & BMCR_ANENABLE)) {
4889 tg3_writephy(tp, MII_ADVERTISE, newadv);
4890 bmcr |= BMCR_ANENABLE | BMCR_ANRESTART;
4891 tg3_writephy(tp, MII_BMCR, bmcr);
4893 tw32_f(MAC_EVENT, MAC_EVENT_LNKSTATE_CHANGED);
4894 tp->serdes_counter = SERDES_AN_TIMEOUT_5714S;
4895 tp->phy_flags &= ~TG3_PHYFLG_PARALLEL_DETECT;
4902 bmcr &= ~BMCR_SPEED1000;
4903 new_bmcr = bmcr & ~(BMCR_ANENABLE | BMCR_FULLDPLX);
4905 if (tp->link_config.duplex == DUPLEX_FULL)
4906 new_bmcr |= BMCR_FULLDPLX;
4908 if (new_bmcr != bmcr) {
4909 /* BMCR_SPEED1000 is a reserved bit that needs
4910 * to be set on write.
4912 new_bmcr |= BMCR_SPEED1000;
4914 /* Force a linkdown */
4915 if (netif_carrier_ok(tp->dev)) {
4918 err |= tg3_readphy(tp, MII_ADVERTISE, &adv);
4919 adv &= ~(ADVERTISE_1000XFULL |
4920 ADVERTISE_1000XHALF |
4922 tg3_writephy(tp, MII_ADVERTISE, adv);
4923 tg3_writephy(tp, MII_BMCR, bmcr |
4927 netif_carrier_off(tp->dev);
4929 tg3_writephy(tp, MII_BMCR, new_bmcr);
4931 err |= tg3_readphy(tp, MII_BMSR, &bmsr);
4932 err |= tg3_readphy(tp, MII_BMSR, &bmsr);
4933 if (GET_ASIC_REV(tp->pci_chip_rev_id) ==
4935 if (tr32(MAC_TX_STATUS) & TX_STATUS_LINK_UP)
4936 bmsr |= BMSR_LSTATUS;
4938 bmsr &= ~BMSR_LSTATUS;
4940 tp->phy_flags &= ~TG3_PHYFLG_PARALLEL_DETECT;
4944 if (bmsr & BMSR_LSTATUS) {
4945 current_speed = SPEED_1000;
4946 current_link_up = 1;
4947 if (bmcr & BMCR_FULLDPLX)
4948 current_duplex = DUPLEX_FULL;
4950 current_duplex = DUPLEX_HALF;
4955 if (bmcr & BMCR_ANENABLE) {
4958 err |= tg3_readphy(tp, MII_ADVERTISE, &local_adv);
4959 err |= tg3_readphy(tp, MII_LPA, &remote_adv);
4960 common = local_adv & remote_adv;
4961 if (common & (ADVERTISE_1000XHALF |
4962 ADVERTISE_1000XFULL)) {
4963 if (common & ADVERTISE_1000XFULL)
4964 current_duplex = DUPLEX_FULL;
4966 current_duplex = DUPLEX_HALF;
4968 tp->link_config.rmt_adv =
4969 mii_adv_to_ethtool_adv_x(remote_adv);
4970 } else if (!tg3_flag(tp, 5780_CLASS)) {
4971 /* Link is up via parallel detect */
4973 current_link_up = 0;
4978 if (current_link_up == 1 && current_duplex == DUPLEX_FULL)
4979 tg3_setup_flow_control(tp, local_adv, remote_adv);
4981 tp->mac_mode &= ~MAC_MODE_HALF_DUPLEX;
4982 if (tp->link_config.active_duplex == DUPLEX_HALF)
4983 tp->mac_mode |= MAC_MODE_HALF_DUPLEX;
4985 tw32_f(MAC_MODE, tp->mac_mode);
4988 tw32_f(MAC_EVENT, MAC_EVENT_LNKSTATE_CHANGED);
4990 tp->link_config.active_speed = current_speed;
4991 tp->link_config.active_duplex = current_duplex;
4993 if (current_link_up != netif_carrier_ok(tp->dev)) {
4994 if (current_link_up)
4995 netif_carrier_on(tp->dev);
4997 netif_carrier_off(tp->dev);
4998 tp->phy_flags &= ~TG3_PHYFLG_PARALLEL_DETECT;
5000 tg3_link_report(tp);
5005 static void tg3_serdes_parallel_detect(struct tg3 *tp)
5007 if (tp->serdes_counter) {
5008 /* Give autoneg time to complete. */
5009 tp->serdes_counter--;
5013 if (!netif_carrier_ok(tp->dev) &&
5014 (tp->link_config.autoneg == AUTONEG_ENABLE)) {
5017 tg3_readphy(tp, MII_BMCR, &bmcr);
5018 if (bmcr & BMCR_ANENABLE) {
5021 /* Select shadow register 0x1f */
5022 tg3_writephy(tp, MII_TG3_MISC_SHDW, 0x7c00);
5023 tg3_readphy(tp, MII_TG3_MISC_SHDW, &phy1);
5025 /* Select expansion interrupt status register */
5026 tg3_writephy(tp, MII_TG3_DSP_ADDRESS,
5027 MII_TG3_DSP_EXP1_INT_STAT);
5028 tg3_readphy(tp, MII_TG3_DSP_RW_PORT, &phy2);
5029 tg3_readphy(tp, MII_TG3_DSP_RW_PORT, &phy2);
5031 if ((phy1 & 0x10) && !(phy2 & 0x20)) {
5032 /* We have signal detect and not receiving
5033 * config code words, link is up by parallel
5037 bmcr &= ~BMCR_ANENABLE;
5038 bmcr |= BMCR_SPEED1000 | BMCR_FULLDPLX;
5039 tg3_writephy(tp, MII_BMCR, bmcr);
5040 tp->phy_flags |= TG3_PHYFLG_PARALLEL_DETECT;
5043 } else if (netif_carrier_ok(tp->dev) &&
5044 (tp->link_config.autoneg == AUTONEG_ENABLE) &&
5045 (tp->phy_flags & TG3_PHYFLG_PARALLEL_DETECT)) {
5048 /* Select expansion interrupt status register */
5049 tg3_writephy(tp, MII_TG3_DSP_ADDRESS,
5050 MII_TG3_DSP_EXP1_INT_STAT);
5051 tg3_readphy(tp, MII_TG3_DSP_RW_PORT, &phy2);
5055 /* Config code words received, turn on autoneg. */
5056 tg3_readphy(tp, MII_BMCR, &bmcr);
5057 tg3_writephy(tp, MII_BMCR, bmcr | BMCR_ANENABLE);
5059 tp->phy_flags &= ~TG3_PHYFLG_PARALLEL_DETECT;
5065 static int tg3_setup_phy(struct tg3 *tp, int force_reset)
5070 if (tp->phy_flags & TG3_PHYFLG_PHY_SERDES)
5071 err = tg3_setup_fiber_phy(tp, force_reset);
5072 else if (tp->phy_flags & TG3_PHYFLG_MII_SERDES)
5073 err = tg3_setup_fiber_mii_phy(tp, force_reset);
5075 err = tg3_setup_copper_phy(tp, force_reset);
5077 if (GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5784_AX) {
5080 val = tr32(TG3_CPMU_CLCK_STAT) & CPMU_CLCK_STAT_MAC_CLCK_MASK;
5081 if (val == CPMU_CLCK_STAT_MAC_CLCK_62_5)
5083 else if (val == CPMU_CLCK_STAT_MAC_CLCK_6_25)
5088 val = tr32(GRC_MISC_CFG) & ~GRC_MISC_CFG_PRESCALAR_MASK;
5089 val |= (scale << GRC_MISC_CFG_PRESCALAR_SHIFT);
5090 tw32(GRC_MISC_CFG, val);
5093 val = (2 << TX_LENGTHS_IPG_CRS_SHIFT) |
5094 (6 << TX_LENGTHS_IPG_SHIFT);
5095 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5720)
5096 val |= tr32(MAC_TX_LENGTHS) &
5097 (TX_LENGTHS_JMB_FRM_LEN_MSK |
5098 TX_LENGTHS_CNT_DWN_VAL_MSK);
5100 if (tp->link_config.active_speed == SPEED_1000 &&
5101 tp->link_config.active_duplex == DUPLEX_HALF)
5102 tw32(MAC_TX_LENGTHS, val |
5103 (0xff << TX_LENGTHS_SLOT_TIME_SHIFT));
5105 tw32(MAC_TX_LENGTHS, val |
5106 (32 << TX_LENGTHS_SLOT_TIME_SHIFT));
5108 if (!tg3_flag(tp, 5705_PLUS)) {
5109 if (netif_carrier_ok(tp->dev)) {
5110 tw32(HOSTCC_STAT_COAL_TICKS,
5111 tp->coal.stats_block_coalesce_usecs);
5113 tw32(HOSTCC_STAT_COAL_TICKS, 0);
5117 if (tg3_flag(tp, ASPM_WORKAROUND)) {
5118 val = tr32(PCIE_PWR_MGMT_THRESH);
5119 if (!netif_carrier_ok(tp->dev))
5120 val = (val & ~PCIE_PWR_MGMT_L1_THRESH_MSK) |
5123 val |= PCIE_PWR_MGMT_L1_THRESH_MSK;
5124 tw32(PCIE_PWR_MGMT_THRESH, val);
5130 static inline int tg3_irq_sync(struct tg3 *tp)
5132 return tp->irq_sync;
5135 static inline void tg3_rd32_loop(struct tg3 *tp, u32 *dst, u32 off, u32 len)
5139 dst = (u32 *)((u8 *)dst + off);
5140 for (i = 0; i < len; i += sizeof(u32))
5141 *dst++ = tr32(off + i);
5144 static void tg3_dump_legacy_regs(struct tg3 *tp, u32 *regs)
5146 tg3_rd32_loop(tp, regs, TG3PCI_VENDOR, 0xb0);
5147 tg3_rd32_loop(tp, regs, MAILBOX_INTERRUPT_0, 0x200);
5148 tg3_rd32_loop(tp, regs, MAC_MODE, 0x4f0);
5149 tg3_rd32_loop(tp, regs, SNDDATAI_MODE, 0xe0);
5150 tg3_rd32_loop(tp, regs, SNDDATAC_MODE, 0x04);
5151 tg3_rd32_loop(tp, regs, SNDBDS_MODE, 0x80);
5152 tg3_rd32_loop(tp, regs, SNDBDI_MODE, 0x48);
5153 tg3_rd32_loop(tp, regs, SNDBDC_MODE, 0x04);
5154 tg3_rd32_loop(tp, regs, RCVLPC_MODE, 0x20);
5155 tg3_rd32_loop(tp, regs, RCVLPC_SELLST_BASE, 0x15c);
5156 tg3_rd32_loop(tp, regs, RCVDBDI_MODE, 0x0c);
5157 tg3_rd32_loop(tp, regs, RCVDBDI_JUMBO_BD, 0x3c);
5158 tg3_rd32_loop(tp, regs, RCVDBDI_BD_PROD_IDX_0, 0x44);
5159 tg3_rd32_loop(tp, regs, RCVDCC_MODE, 0x04);
5160 tg3_rd32_loop(tp, regs, RCVBDI_MODE, 0x20);
5161 tg3_rd32_loop(tp, regs, RCVCC_MODE, 0x14);
5162 tg3_rd32_loop(tp, regs, RCVLSC_MODE, 0x08);
5163 tg3_rd32_loop(tp, regs, MBFREE_MODE, 0x08);
5164 tg3_rd32_loop(tp, regs, HOSTCC_MODE, 0x100);
5166 if (tg3_flag(tp, SUPPORT_MSIX))
5167 tg3_rd32_loop(tp, regs, HOSTCC_RXCOL_TICKS_VEC1, 0x180);
5169 tg3_rd32_loop(tp, regs, MEMARB_MODE, 0x10);
5170 tg3_rd32_loop(tp, regs, BUFMGR_MODE, 0x58);
5171 tg3_rd32_loop(tp, regs, RDMAC_MODE, 0x08);
5172 tg3_rd32_loop(tp, regs, WDMAC_MODE, 0x08);
5173 tg3_rd32_loop(tp, regs, RX_CPU_MODE, 0x04);
5174 tg3_rd32_loop(tp, regs, RX_CPU_STATE, 0x04);
5175 tg3_rd32_loop(tp, regs, RX_CPU_PGMCTR, 0x04);
5176 tg3_rd32_loop(tp, regs, RX_CPU_HWBKPT, 0x04);
5178 if (!tg3_flag(tp, 5705_PLUS)) {
5179 tg3_rd32_loop(tp, regs, TX_CPU_MODE, 0x04);
5180 tg3_rd32_loop(tp, regs, TX_CPU_STATE, 0x04);
5181 tg3_rd32_loop(tp, regs, TX_CPU_PGMCTR, 0x04);
5184 tg3_rd32_loop(tp, regs, GRCMBOX_INTERRUPT_0, 0x110);
5185 tg3_rd32_loop(tp, regs, FTQ_RESET, 0x120);
5186 tg3_rd32_loop(tp, regs, MSGINT_MODE, 0x0c);
5187 tg3_rd32_loop(tp, regs, DMAC_MODE, 0x04);
5188 tg3_rd32_loop(tp, regs, GRC_MODE, 0x4c);
5190 if (tg3_flag(tp, NVRAM))
5191 tg3_rd32_loop(tp, regs, NVRAM_CMD, 0x24);
5194 static void tg3_dump_state(struct tg3 *tp)
5199 regs = kzalloc(TG3_REG_BLK_SIZE, GFP_ATOMIC);
5201 netdev_err(tp->dev, "Failed allocating register dump buffer\n");
5205 if (tg3_flag(tp, PCI_EXPRESS)) {
5206 /* Read up to but not including private PCI registers */
5207 for (i = 0; i < TG3_PCIE_TLDLPL_PORT; i += sizeof(u32))
5208 regs[i / sizeof(u32)] = tr32(i);
5210 tg3_dump_legacy_regs(tp, regs);
5212 for (i = 0; i < TG3_REG_BLK_SIZE / sizeof(u32); i += 4) {
5213 if (!regs[i + 0] && !regs[i + 1] &&
5214 !regs[i + 2] && !regs[i + 3])
5217 netdev_err(tp->dev, "0x%08x: 0x%08x, 0x%08x, 0x%08x, 0x%08x\n",
5219 regs[i + 0], regs[i + 1], regs[i + 2], regs[i + 3]);
5224 for (i = 0; i < tp->irq_cnt; i++) {
5225 struct tg3_napi *tnapi = &tp->napi[i];
5227 /* SW status block */
5229 "%d: Host status block [%08x:%08x:(%04x:%04x:%04x):(%04x:%04x)]\n",
5231 tnapi->hw_status->status,
5232 tnapi->hw_status->status_tag,
5233 tnapi->hw_status->rx_jumbo_consumer,
5234 tnapi->hw_status->rx_consumer,
5235 tnapi->hw_status->rx_mini_consumer,
5236 tnapi->hw_status->idx[0].rx_producer,
5237 tnapi->hw_status->idx[0].tx_consumer);
5240 "%d: NAPI info [%08x:%08x:(%04x:%04x:%04x):%04x:(%04x:%04x:%04x:%04x)]\n",
5242 tnapi->last_tag, tnapi->last_irq_tag,
5243 tnapi->tx_prod, tnapi->tx_cons, tnapi->tx_pending,
5245 tnapi->prodring.rx_std_prod_idx,
5246 tnapi->prodring.rx_std_cons_idx,
5247 tnapi->prodring.rx_jmb_prod_idx,
5248 tnapi->prodring.rx_jmb_cons_idx);
5252 /* This is called whenever we suspect that the system chipset is re-
5253 * ordering the sequence of MMIO to the tx send mailbox. The symptom
5254 * is bogus tx completions. We try to recover by setting the
5255 * TG3_FLAG_MBOX_WRITE_REORDER flag and resetting the chip later
5258 static void tg3_tx_recover(struct tg3 *tp)
5260 BUG_ON(tg3_flag(tp, MBOX_WRITE_REORDER) ||
5261 tp->write32_tx_mbox == tg3_write_indirect_mbox);
5263 netdev_warn(tp->dev,
5264 "The system may be re-ordering memory-mapped I/O "
5265 "cycles to the network device, attempting to recover. "
5266 "Please report the problem to the driver maintainer "
5267 "and include system chipset information.\n");
5269 spin_lock(&tp->lock);
5270 tg3_flag_set(tp, TX_RECOVERY_PENDING);
5271 spin_unlock(&tp->lock);
5274 static inline u32 tg3_tx_avail(struct tg3_napi *tnapi)
5276 /* Tell compiler to fetch tx indices from memory. */
5278 return tnapi->tx_pending -
5279 ((tnapi->tx_prod - tnapi->tx_cons) & (TG3_TX_RING_SIZE - 1));
5282 /* Tigon3 never reports partial packet sends. So we do not
5283 * need special logic to handle SKBs that have not had all
5284 * of their frags sent yet, like SunGEM does.
5286 static void tg3_tx(struct tg3_napi *tnapi)
5288 struct tg3 *tp = tnapi->tp;
5289 u32 hw_idx = tnapi->hw_status->idx[0].tx_consumer;
5290 u32 sw_idx = tnapi->tx_cons;
5291 struct netdev_queue *txq;
5292 int index = tnapi - tp->napi;
5293 unsigned int pkts_compl = 0, bytes_compl = 0;
5295 if (tg3_flag(tp, ENABLE_TSS))
5298 txq = netdev_get_tx_queue(tp->dev, index);
5300 while (sw_idx != hw_idx) {
5301 struct tg3_tx_ring_info *ri = &tnapi->tx_buffers[sw_idx];
5302 struct sk_buff *skb = ri->skb;
5305 if (unlikely(skb == NULL)) {
5310 pci_unmap_single(tp->pdev,
5311 dma_unmap_addr(ri, mapping),
5317 while (ri->fragmented) {
5318 ri->fragmented = false;
5319 sw_idx = NEXT_TX(sw_idx);
5320 ri = &tnapi->tx_buffers[sw_idx];
5323 sw_idx = NEXT_TX(sw_idx);
5325 for (i = 0; i < skb_shinfo(skb)->nr_frags; i++) {
5326 ri = &tnapi->tx_buffers[sw_idx];
5327 if (unlikely(ri->skb != NULL || sw_idx == hw_idx))
5330 pci_unmap_page(tp->pdev,
5331 dma_unmap_addr(ri, mapping),
5332 skb_frag_size(&skb_shinfo(skb)->frags[i]),
5335 while (ri->fragmented) {
5336 ri->fragmented = false;
5337 sw_idx = NEXT_TX(sw_idx);
5338 ri = &tnapi->tx_buffers[sw_idx];
5341 sw_idx = NEXT_TX(sw_idx);
5345 bytes_compl += skb->len;
5349 if (unlikely(tx_bug)) {
5355 netdev_completed_queue(tp->dev, pkts_compl, bytes_compl);
5357 tnapi->tx_cons = sw_idx;
5359 /* Need to make the tx_cons update visible to tg3_start_xmit()
5360 * before checking for netif_queue_stopped(). Without the
5361 * memory barrier, there is a small possibility that tg3_start_xmit()
5362 * will miss it and cause the queue to be stopped forever.
5366 if (unlikely(netif_tx_queue_stopped(txq) &&
5367 (tg3_tx_avail(tnapi) > TG3_TX_WAKEUP_THRESH(tnapi)))) {
5368 __netif_tx_lock(txq, smp_processor_id());
5369 if (netif_tx_queue_stopped(txq) &&
5370 (tg3_tx_avail(tnapi) > TG3_TX_WAKEUP_THRESH(tnapi)))
5371 netif_tx_wake_queue(txq);
5372 __netif_tx_unlock(txq);
5376 static void tg3_rx_data_free(struct tg3 *tp, struct ring_info *ri, u32 map_sz)
5381 pci_unmap_single(tp->pdev, dma_unmap_addr(ri, mapping),
5382 map_sz, PCI_DMA_FROMDEVICE);
5387 /* Returns size of skb allocated or < 0 on error.
5389 * We only need to fill in the address because the other members
5390 * of the RX descriptor are invariant, see tg3_init_rings.
5392 * Note the purposeful assymetry of cpu vs. chip accesses. For
5393 * posting buffers we only dirty the first cache line of the RX
5394 * descriptor (containing the address). Whereas for the RX status
5395 * buffers the cpu only reads the last cacheline of the RX descriptor
5396 * (to fetch the error flags, vlan tag, checksum, and opaque cookie).
5398 static int tg3_alloc_rx_data(struct tg3 *tp, struct tg3_rx_prodring_set *tpr,
5399 u32 opaque_key, u32 dest_idx_unmasked)
5401 struct tg3_rx_buffer_desc *desc;
5402 struct ring_info *map;
5405 int skb_size, data_size, dest_idx;
5407 switch (opaque_key) {
5408 case RXD_OPAQUE_RING_STD:
5409 dest_idx = dest_idx_unmasked & tp->rx_std_ring_mask;
5410 desc = &tpr->rx_std[dest_idx];
5411 map = &tpr->rx_std_buffers[dest_idx];
5412 data_size = tp->rx_pkt_map_sz;
5415 case RXD_OPAQUE_RING_JUMBO:
5416 dest_idx = dest_idx_unmasked & tp->rx_jmb_ring_mask;
5417 desc = &tpr->rx_jmb[dest_idx].std;
5418 map = &tpr->rx_jmb_buffers[dest_idx];
5419 data_size = TG3_RX_JMB_MAP_SZ;
5426 /* Do not overwrite any of the map or rp information
5427 * until we are sure we can commit to a new buffer.
5429 * Callers depend upon this behavior and assume that
5430 * we leave everything unchanged if we fail.
5432 skb_size = SKB_DATA_ALIGN(data_size + TG3_RX_OFFSET(tp)) +
5433 SKB_DATA_ALIGN(sizeof(struct skb_shared_info));
5434 data = kmalloc(skb_size, GFP_ATOMIC);
5438 mapping = pci_map_single(tp->pdev,
5439 data + TG3_RX_OFFSET(tp),
5441 PCI_DMA_FROMDEVICE);
5442 if (pci_dma_mapping_error(tp->pdev, mapping)) {
5448 dma_unmap_addr_set(map, mapping, mapping);
5450 desc->addr_hi = ((u64)mapping >> 32);
5451 desc->addr_lo = ((u64)mapping & 0xffffffff);
5456 /* We only need to move over in the address because the other
5457 * members of the RX descriptor are invariant. See notes above
5458 * tg3_alloc_rx_data for full details.
5460 static void tg3_recycle_rx(struct tg3_napi *tnapi,
5461 struct tg3_rx_prodring_set *dpr,
5462 u32 opaque_key, int src_idx,
5463 u32 dest_idx_unmasked)
5465 struct tg3 *tp = tnapi->tp;
5466 struct tg3_rx_buffer_desc *src_desc, *dest_desc;
5467 struct ring_info *src_map, *dest_map;
5468 struct tg3_rx_prodring_set *spr = &tp->napi[0].prodring;
5471 switch (opaque_key) {
5472 case RXD_OPAQUE_RING_STD:
5473 dest_idx = dest_idx_unmasked & tp->rx_std_ring_mask;
5474 dest_desc = &dpr->rx_std[dest_idx];
5475 dest_map = &dpr->rx_std_buffers[dest_idx];
5476 src_desc = &spr->rx_std[src_idx];
5477 src_map = &spr->rx_std_buffers[src_idx];
5480 case RXD_OPAQUE_RING_JUMBO:
5481 dest_idx = dest_idx_unmasked & tp->rx_jmb_ring_mask;
5482 dest_desc = &dpr->rx_jmb[dest_idx].std;
5483 dest_map = &dpr->rx_jmb_buffers[dest_idx];
5484 src_desc = &spr->rx_jmb[src_idx].std;
5485 src_map = &spr->rx_jmb_buffers[src_idx];
5492 dest_map->data = src_map->data;
5493 dma_unmap_addr_set(dest_map, mapping,
5494 dma_unmap_addr(src_map, mapping));
5495 dest_desc->addr_hi = src_desc->addr_hi;
5496 dest_desc->addr_lo = src_desc->addr_lo;
5498 /* Ensure that the update to the skb happens after the physical
5499 * addresses have been transferred to the new BD location.
5503 src_map->data = NULL;
5506 /* The RX ring scheme is composed of multiple rings which post fresh
5507 * buffers to the chip, and one special ring the chip uses to report
5508 * status back to the host.
5510 * The special ring reports the status of received packets to the
5511 * host. The chip does not write into the original descriptor the
5512 * RX buffer was obtained from. The chip simply takes the original
5513 * descriptor as provided by the host, updates the status and length
5514 * field, then writes this into the next status ring entry.
5516 * Each ring the host uses to post buffers to the chip is described
5517 * by a TG3_BDINFO entry in the chips SRAM area. When a packet arrives,
5518 * it is first placed into the on-chip ram. When the packet's length
5519 * is known, it walks down the TG3_BDINFO entries to select the ring.
5520 * Each TG3_BDINFO specifies a MAXLEN field and the first TG3_BDINFO
5521 * which is within the range of the new packet's length is chosen.
5523 * The "separate ring for rx status" scheme may sound queer, but it makes
5524 * sense from a cache coherency perspective. If only the host writes
5525 * to the buffer post rings, and only the chip writes to the rx status
5526 * rings, then cache lines never move beyond shared-modified state.
5527 * If both the host and chip were to write into the same ring, cache line
5528 * eviction could occur since both entities want it in an exclusive state.
5530 static int tg3_rx(struct tg3_napi *tnapi, int budget)
5532 struct tg3 *tp = tnapi->tp;
5533 u32 work_mask, rx_std_posted = 0;
5534 u32 std_prod_idx, jmb_prod_idx;
5535 u32 sw_idx = tnapi->rx_rcb_ptr;
5538 struct tg3_rx_prodring_set *tpr = &tnapi->prodring;
5540 hw_idx = *(tnapi->rx_rcb_prod_idx);
5542 * We need to order the read of hw_idx and the read of
5543 * the opaque cookie.
5548 std_prod_idx = tpr->rx_std_prod_idx;
5549 jmb_prod_idx = tpr->rx_jmb_prod_idx;
5550 while (sw_idx != hw_idx && budget > 0) {
5551 struct ring_info *ri;
5552 struct tg3_rx_buffer_desc *desc = &tnapi->rx_rcb[sw_idx];
5554 struct sk_buff *skb;
5555 dma_addr_t dma_addr;
5556 u32 opaque_key, desc_idx, *post_ptr;
5559 desc_idx = desc->opaque & RXD_OPAQUE_INDEX_MASK;
5560 opaque_key = desc->opaque & RXD_OPAQUE_RING_MASK;
5561 if (opaque_key == RXD_OPAQUE_RING_STD) {
5562 ri = &tp->napi[0].prodring.rx_std_buffers[desc_idx];
5563 dma_addr = dma_unmap_addr(ri, mapping);
5565 post_ptr = &std_prod_idx;
5567 } else if (opaque_key == RXD_OPAQUE_RING_JUMBO) {
5568 ri = &tp->napi[0].prodring.rx_jmb_buffers[desc_idx];
5569 dma_addr = dma_unmap_addr(ri, mapping);
5571 post_ptr = &jmb_prod_idx;
5573 goto next_pkt_nopost;
5575 work_mask |= opaque_key;
5577 if ((desc->err_vlan & RXD_ERR_MASK) != 0 &&
5578 (desc->err_vlan != RXD_ERR_ODD_NIBBLE_RCVD_MII)) {
5580 tg3_recycle_rx(tnapi, tpr, opaque_key,
5581 desc_idx, *post_ptr);
5583 /* Other statistics kept track of by card. */
5588 prefetch(data + TG3_RX_OFFSET(tp));
5589 len = ((desc->idx_len & RXD_LEN_MASK) >> RXD_LEN_SHIFT) -
5592 if (len > TG3_RX_COPY_THRESH(tp)) {
5595 skb_size = tg3_alloc_rx_data(tp, tpr, opaque_key,
5600 pci_unmap_single(tp->pdev, dma_addr, skb_size,
5601 PCI_DMA_FROMDEVICE);
5603 skb = build_skb(data);
5606 goto drop_it_no_recycle;
5608 skb_reserve(skb, TG3_RX_OFFSET(tp));
5609 /* Ensure that the update to the data happens
5610 * after the usage of the old DMA mapping.
5617 tg3_recycle_rx(tnapi, tpr, opaque_key,
5618 desc_idx, *post_ptr);
5620 skb = netdev_alloc_skb(tp->dev,
5621 len + TG3_RAW_IP_ALIGN);
5623 goto drop_it_no_recycle;
5625 skb_reserve(skb, TG3_RAW_IP_ALIGN);
5626 pci_dma_sync_single_for_cpu(tp->pdev, dma_addr, len, PCI_DMA_FROMDEVICE);
5628 data + TG3_RX_OFFSET(tp),
5630 pci_dma_sync_single_for_device(tp->pdev, dma_addr, len, PCI_DMA_FROMDEVICE);
5634 if ((tp->dev->features & NETIF_F_RXCSUM) &&
5635 (desc->type_flags & RXD_FLAG_TCPUDP_CSUM) &&
5636 (((desc->ip_tcp_csum & RXD_TCPCSUM_MASK)
5637 >> RXD_TCPCSUM_SHIFT) == 0xffff))
5638 skb->ip_summed = CHECKSUM_UNNECESSARY;
5640 skb_checksum_none_assert(skb);
5642 skb->protocol = eth_type_trans(skb, tp->dev);
5644 if (len > (tp->dev->mtu + ETH_HLEN) &&
5645 skb->protocol != htons(ETH_P_8021Q)) {
5647 goto drop_it_no_recycle;
5650 if (desc->type_flags & RXD_FLAG_VLAN &&
5651 !(tp->rx_mode & RX_MODE_KEEP_VLAN_TAG))
5652 __vlan_hwaccel_put_tag(skb,
5653 desc->err_vlan & RXD_VLAN_MASK);
5655 napi_gro_receive(&tnapi->napi, skb);
5663 if (unlikely(rx_std_posted >= tp->rx_std_max_post)) {
5664 tpr->rx_std_prod_idx = std_prod_idx &
5665 tp->rx_std_ring_mask;
5666 tw32_rx_mbox(TG3_RX_STD_PROD_IDX_REG,
5667 tpr->rx_std_prod_idx);
5668 work_mask &= ~RXD_OPAQUE_RING_STD;
5673 sw_idx &= tp->rx_ret_ring_mask;
5675 /* Refresh hw_idx to see if there is new work */
5676 if (sw_idx == hw_idx) {
5677 hw_idx = *(tnapi->rx_rcb_prod_idx);
5682 /* ACK the status ring. */
5683 tnapi->rx_rcb_ptr = sw_idx;
5684 tw32_rx_mbox(tnapi->consmbox, sw_idx);
5686 /* Refill RX ring(s). */
5687 if (!tg3_flag(tp, ENABLE_RSS)) {
5688 if (work_mask & RXD_OPAQUE_RING_STD) {
5689 tpr->rx_std_prod_idx = std_prod_idx &
5690 tp->rx_std_ring_mask;
5691 tw32_rx_mbox(TG3_RX_STD_PROD_IDX_REG,
5692 tpr->rx_std_prod_idx);
5694 if (work_mask & RXD_OPAQUE_RING_JUMBO) {
5695 tpr->rx_jmb_prod_idx = jmb_prod_idx &
5696 tp->rx_jmb_ring_mask;
5697 tw32_rx_mbox(TG3_RX_JMB_PROD_IDX_REG,
5698 tpr->rx_jmb_prod_idx);
5701 } else if (work_mask) {
5702 /* rx_std_buffers[] and rx_jmb_buffers[] entries must be
5703 * updated before the producer indices can be updated.
5707 tpr->rx_std_prod_idx = std_prod_idx & tp->rx_std_ring_mask;
5708 tpr->rx_jmb_prod_idx = jmb_prod_idx & tp->rx_jmb_ring_mask;
5710 if (tnapi != &tp->napi[1])
5711 napi_schedule(&tp->napi[1].napi);
5717 static void tg3_poll_link(struct tg3 *tp)
5719 /* handle link change and other phy events */
5720 if (!(tg3_flag(tp, USE_LINKCHG_REG) || tg3_flag(tp, POLL_SERDES))) {
5721 struct tg3_hw_status *sblk = tp->napi[0].hw_status;
5723 if (sblk->status & SD_STATUS_LINK_CHG) {
5724 sblk->status = SD_STATUS_UPDATED |
5725 (sblk->status & ~SD_STATUS_LINK_CHG);
5726 spin_lock(&tp->lock);
5727 if (tg3_flag(tp, USE_PHYLIB)) {
5729 (MAC_STATUS_SYNC_CHANGED |
5730 MAC_STATUS_CFG_CHANGED |
5731 MAC_STATUS_MI_COMPLETION |
5732 MAC_STATUS_LNKSTATE_CHANGED));
5735 tg3_setup_phy(tp, 0);
5736 spin_unlock(&tp->lock);
5741 static int tg3_rx_prodring_xfer(struct tg3 *tp,
5742 struct tg3_rx_prodring_set *dpr,
5743 struct tg3_rx_prodring_set *spr)
5745 u32 si, di, cpycnt, src_prod_idx;
5749 src_prod_idx = spr->rx_std_prod_idx;
5751 /* Make sure updates to the rx_std_buffers[] entries and the
5752 * standard producer index are seen in the correct order.
5756 if (spr->rx_std_cons_idx == src_prod_idx)
5759 if (spr->rx_std_cons_idx < src_prod_idx)
5760 cpycnt = src_prod_idx - spr->rx_std_cons_idx;
5762 cpycnt = tp->rx_std_ring_mask + 1 -
5763 spr->rx_std_cons_idx;
5765 cpycnt = min(cpycnt,
5766 tp->rx_std_ring_mask + 1 - dpr->rx_std_prod_idx);
5768 si = spr->rx_std_cons_idx;
5769 di = dpr->rx_std_prod_idx;
5771 for (i = di; i < di + cpycnt; i++) {
5772 if (dpr->rx_std_buffers[i].data) {
5782 /* Ensure that updates to the rx_std_buffers ring and the
5783 * shadowed hardware producer ring from tg3_recycle_skb() are
5784 * ordered correctly WRT the skb check above.
5788 memcpy(&dpr->rx_std_buffers[di],
5789 &spr->rx_std_buffers[si],
5790 cpycnt * sizeof(struct ring_info));
5792 for (i = 0; i < cpycnt; i++, di++, si++) {
5793 struct tg3_rx_buffer_desc *sbd, *dbd;
5794 sbd = &spr->rx_std[si];
5795 dbd = &dpr->rx_std[di];
5796 dbd->addr_hi = sbd->addr_hi;
5797 dbd->addr_lo = sbd->addr_lo;
5800 spr->rx_std_cons_idx = (spr->rx_std_cons_idx + cpycnt) &
5801 tp->rx_std_ring_mask;
5802 dpr->rx_std_prod_idx = (dpr->rx_std_prod_idx + cpycnt) &
5803 tp->rx_std_ring_mask;
5807 src_prod_idx = spr->rx_jmb_prod_idx;
5809 /* Make sure updates to the rx_jmb_buffers[] entries and
5810 * the jumbo producer index are seen in the correct order.
5814 if (spr->rx_jmb_cons_idx == src_prod_idx)
5817 if (spr->rx_jmb_cons_idx < src_prod_idx)
5818 cpycnt = src_prod_idx - spr->rx_jmb_cons_idx;
5820 cpycnt = tp->rx_jmb_ring_mask + 1 -
5821 spr->rx_jmb_cons_idx;
5823 cpycnt = min(cpycnt,
5824 tp->rx_jmb_ring_mask + 1 - dpr->rx_jmb_prod_idx);
5826 si = spr->rx_jmb_cons_idx;
5827 di = dpr->rx_jmb_prod_idx;
5829 for (i = di; i < di + cpycnt; i++) {
5830 if (dpr->rx_jmb_buffers[i].data) {
5840 /* Ensure that updates to the rx_jmb_buffers ring and the
5841 * shadowed hardware producer ring from tg3_recycle_skb() are
5842 * ordered correctly WRT the skb check above.
5846 memcpy(&dpr->rx_jmb_buffers[di],
5847 &spr->rx_jmb_buffers[si],
5848 cpycnt * sizeof(struct ring_info));
5850 for (i = 0; i < cpycnt; i++, di++, si++) {
5851 struct tg3_rx_buffer_desc *sbd, *dbd;
5852 sbd = &spr->rx_jmb[si].std;
5853 dbd = &dpr->rx_jmb[di].std;
5854 dbd->addr_hi = sbd->addr_hi;
5855 dbd->addr_lo = sbd->addr_lo;
5858 spr->rx_jmb_cons_idx = (spr->rx_jmb_cons_idx + cpycnt) &
5859 tp->rx_jmb_ring_mask;
5860 dpr->rx_jmb_prod_idx = (dpr->rx_jmb_prod_idx + cpycnt) &
5861 tp->rx_jmb_ring_mask;
5867 static int tg3_poll_work(struct tg3_napi *tnapi, int work_done, int budget)
5869 struct tg3 *tp = tnapi->tp;
5871 /* run TX completion thread */
5872 if (tnapi->hw_status->idx[0].tx_consumer != tnapi->tx_cons) {
5874 if (unlikely(tg3_flag(tp, TX_RECOVERY_PENDING)))
5878 /* run RX thread, within the bounds set by NAPI.
5879 * All RX "locking" is done by ensuring outside
5880 * code synchronizes with tg3->napi.poll()
5882 if (*(tnapi->rx_rcb_prod_idx) != tnapi->rx_rcb_ptr)
5883 work_done += tg3_rx(tnapi, budget - work_done);
5885 if (tg3_flag(tp, ENABLE_RSS) && tnapi == &tp->napi[1]) {
5886 struct tg3_rx_prodring_set *dpr = &tp->napi[0].prodring;
5888 u32 std_prod_idx = dpr->rx_std_prod_idx;
5889 u32 jmb_prod_idx = dpr->rx_jmb_prod_idx;
5891 for (i = 1; i < tp->irq_cnt; i++)
5892 err |= tg3_rx_prodring_xfer(tp, dpr,
5893 &tp->napi[i].prodring);
5897 if (std_prod_idx != dpr->rx_std_prod_idx)
5898 tw32_rx_mbox(TG3_RX_STD_PROD_IDX_REG,
5899 dpr->rx_std_prod_idx);
5901 if (jmb_prod_idx != dpr->rx_jmb_prod_idx)
5902 tw32_rx_mbox(TG3_RX_JMB_PROD_IDX_REG,
5903 dpr->rx_jmb_prod_idx);
5908 tw32_f(HOSTCC_MODE, tp->coal_now);
5914 static inline void tg3_reset_task_schedule(struct tg3 *tp)
5916 if (!test_and_set_bit(TG3_FLAG_RESET_TASK_PENDING, tp->tg3_flags))
5917 schedule_work(&tp->reset_task);
5920 static inline void tg3_reset_task_cancel(struct tg3 *tp)
5922 cancel_work_sync(&tp->reset_task);
5923 tg3_flag_clear(tp, RESET_TASK_PENDING);
5926 static int tg3_poll_msix(struct napi_struct *napi, int budget)
5928 struct tg3_napi *tnapi = container_of(napi, struct tg3_napi, napi);
5929 struct tg3 *tp = tnapi->tp;
5931 struct tg3_hw_status *sblk = tnapi->hw_status;
5934 work_done = tg3_poll_work(tnapi, work_done, budget);
5936 if (unlikely(tg3_flag(tp, TX_RECOVERY_PENDING)))
5939 if (unlikely(work_done >= budget))
5942 /* tp->last_tag is used in tg3_int_reenable() below
5943 * to tell the hw how much work has been processed,
5944 * so we must read it before checking for more work.
5946 tnapi->last_tag = sblk->status_tag;
5947 tnapi->last_irq_tag = tnapi->last_tag;
5950 /* check for RX/TX work to do */
5951 if (likely(sblk->idx[0].tx_consumer == tnapi->tx_cons &&
5952 *(tnapi->rx_rcb_prod_idx) == tnapi->rx_rcb_ptr)) {
5953 napi_complete(napi);
5954 /* Reenable interrupts. */
5955 tw32_mailbox(tnapi->int_mbox, tnapi->last_tag << 24);
5964 /* work_done is guaranteed to be less than budget. */
5965 napi_complete(napi);
5966 tg3_reset_task_schedule(tp);
5970 static void tg3_process_error(struct tg3 *tp)
5973 bool real_error = false;
5975 if (tg3_flag(tp, ERROR_PROCESSED))
5978 /* Check Flow Attention register */
5979 val = tr32(HOSTCC_FLOW_ATTN);
5980 if (val & ~HOSTCC_FLOW_ATTN_MBUF_LWM) {
5981 netdev_err(tp->dev, "FLOW Attention error. Resetting chip.\n");
5985 if (tr32(MSGINT_STATUS) & ~MSGINT_STATUS_MSI_REQ) {
5986 netdev_err(tp->dev, "MSI Status error. Resetting chip.\n");
5990 if (tr32(RDMAC_STATUS) || tr32(WDMAC_STATUS)) {
5991 netdev_err(tp->dev, "DMA Status error. Resetting chip.\n");
6000 tg3_flag_set(tp, ERROR_PROCESSED);
6001 tg3_reset_task_schedule(tp);
6004 static int tg3_poll(struct napi_struct *napi, int budget)
6006 struct tg3_napi *tnapi = container_of(napi, struct tg3_napi, napi);
6007 struct tg3 *tp = tnapi->tp;
6009 struct tg3_hw_status *sblk = tnapi->hw_status;
6012 if (sblk->status & SD_STATUS_ERROR)
6013 tg3_process_error(tp);
6017 work_done = tg3_poll_work(tnapi, work_done, budget);
6019 if (unlikely(tg3_flag(tp, TX_RECOVERY_PENDING)))
6022 if (unlikely(work_done >= budget))
6025 if (tg3_flag(tp, TAGGED_STATUS)) {
6026 /* tp->last_tag is used in tg3_int_reenable() below
6027 * to tell the hw how much work has been processed,
6028 * so we must read it before checking for more work.
6030 tnapi->last_tag = sblk->status_tag;
6031 tnapi->last_irq_tag = tnapi->last_tag;
6034 sblk->status &= ~SD_STATUS_UPDATED;
6036 if (likely(!tg3_has_work(tnapi))) {
6037 napi_complete(napi);
6038 tg3_int_reenable(tnapi);
6046 /* work_done is guaranteed to be less than budget. */
6047 napi_complete(napi);
6048 tg3_reset_task_schedule(tp);
6052 static void tg3_napi_disable(struct tg3 *tp)
6056 for (i = tp->irq_cnt - 1; i >= 0; i--)
6057 napi_disable(&tp->napi[i].napi);
6060 static void tg3_napi_enable(struct tg3 *tp)
6064 for (i = 0; i < tp->irq_cnt; i++)
6065 napi_enable(&tp->napi[i].napi);
6068 static void tg3_napi_init(struct tg3 *tp)
6072 netif_napi_add(tp->dev, &tp->napi[0].napi, tg3_poll, 64);
6073 for (i = 1; i < tp->irq_cnt; i++)
6074 netif_napi_add(tp->dev, &tp->napi[i].napi, tg3_poll_msix, 64);
6077 static void tg3_napi_fini(struct tg3 *tp)
6081 for (i = 0; i < tp->irq_cnt; i++)
6082 netif_napi_del(&tp->napi[i].napi);
6085 static inline void tg3_netif_stop(struct tg3 *tp)
6087 tp->dev->trans_start = jiffies; /* prevent tx timeout */
6088 tg3_napi_disable(tp);
6089 netif_tx_disable(tp->dev);
6092 static inline void tg3_netif_start(struct tg3 *tp)
6094 /* NOTE: unconditional netif_tx_wake_all_queues is only
6095 * appropriate so long as all callers are assured to
6096 * have free tx slots (such as after tg3_init_hw)
6098 netif_tx_wake_all_queues(tp->dev);
6100 tg3_napi_enable(tp);
6101 tp->napi[0].hw_status->status |= SD_STATUS_UPDATED;
6102 tg3_enable_ints(tp);
6105 static void tg3_irq_quiesce(struct tg3 *tp)
6109 BUG_ON(tp->irq_sync);
6114 for (i = 0; i < tp->irq_cnt; i++)
6115 synchronize_irq(tp->napi[i].irq_vec);
6118 /* Fully shutdown all tg3 driver activity elsewhere in the system.
6119 * If irq_sync is non-zero, then the IRQ handler must be synchronized
6120 * with as well. Most of the time, this is not necessary except when
6121 * shutting down the device.
6123 static inline void tg3_full_lock(struct tg3 *tp, int irq_sync)
6125 spin_lock_bh(&tp->lock);
6127 tg3_irq_quiesce(tp);
6130 static inline void tg3_full_unlock(struct tg3 *tp)
6132 spin_unlock_bh(&tp->lock);
6135 /* One-shot MSI handler - Chip automatically disables interrupt
6136 * after sending MSI so driver doesn't have to do it.
6138 static irqreturn_t tg3_msi_1shot(int irq, void *dev_id)
6140 struct tg3_napi *tnapi = dev_id;
6141 struct tg3 *tp = tnapi->tp;
6143 prefetch(tnapi->hw_status);
6145 prefetch(&tnapi->rx_rcb[tnapi->rx_rcb_ptr]);
6147 if (likely(!tg3_irq_sync(tp)))
6148 napi_schedule(&tnapi->napi);
6153 /* MSI ISR - No need to check for interrupt sharing and no need to
6154 * flush status block and interrupt mailbox. PCI ordering rules
6155 * guarantee that MSI will arrive after the status block.
6157 static irqreturn_t tg3_msi(int irq, void *dev_id)
6159 struct tg3_napi *tnapi = dev_id;
6160 struct tg3 *tp = tnapi->tp;
6162 prefetch(tnapi->hw_status);
6164 prefetch(&tnapi->rx_rcb[tnapi->rx_rcb_ptr]);
6166 * Writing any value to intr-mbox-0 clears PCI INTA# and
6167 * chip-internal interrupt pending events.
6168 * Writing non-zero to intr-mbox-0 additional tells the
6169 * NIC to stop sending us irqs, engaging "in-intr-handler"
6172 tw32_mailbox(tnapi->int_mbox, 0x00000001);
6173 if (likely(!tg3_irq_sync(tp)))
6174 napi_schedule(&tnapi->napi);
6176 return IRQ_RETVAL(1);
6179 static irqreturn_t tg3_interrupt(int irq, void *dev_id)
6181 struct tg3_napi *tnapi = dev_id;
6182 struct tg3 *tp = tnapi->tp;
6183 struct tg3_hw_status *sblk = tnapi->hw_status;
6184 unsigned int handled = 1;
6186 /* In INTx mode, it is possible for the interrupt to arrive at
6187 * the CPU before the status block posted prior to the interrupt.
6188 * Reading the PCI State register will confirm whether the
6189 * interrupt is ours and will flush the status block.
6191 if (unlikely(!(sblk->status & SD_STATUS_UPDATED))) {
6192 if (tg3_flag(tp, CHIP_RESETTING) ||
6193 (tr32(TG3PCI_PCISTATE) & PCISTATE_INT_NOT_ACTIVE)) {
6200 * Writing any value to intr-mbox-0 clears PCI INTA# and
6201 * chip-internal interrupt pending events.
6202 * Writing non-zero to intr-mbox-0 additional tells the
6203 * NIC to stop sending us irqs, engaging "in-intr-handler"
6206 * Flush the mailbox to de-assert the IRQ immediately to prevent
6207 * spurious interrupts. The flush impacts performance but
6208 * excessive spurious interrupts can be worse in some cases.
6210 tw32_mailbox_f(MAILBOX_INTERRUPT_0 + TG3_64BIT_REG_LOW, 0x00000001);
6211 if (tg3_irq_sync(tp))
6213 sblk->status &= ~SD_STATUS_UPDATED;
6214 if (likely(tg3_has_work(tnapi))) {
6215 prefetch(&tnapi->rx_rcb[tnapi->rx_rcb_ptr]);
6216 napi_schedule(&tnapi->napi);
6218 /* No work, shared interrupt perhaps? re-enable
6219 * interrupts, and flush that PCI write
6221 tw32_mailbox_f(MAILBOX_INTERRUPT_0 + TG3_64BIT_REG_LOW,
6225 return IRQ_RETVAL(handled);
6228 static irqreturn_t tg3_interrupt_tagged(int irq, void *dev_id)
6230 struct tg3_napi *tnapi = dev_id;
6231 struct tg3 *tp = tnapi->tp;
6232 struct tg3_hw_status *sblk = tnapi->hw_status;
6233 unsigned int handled = 1;
6235 /* In INTx mode, it is possible for the interrupt to arrive at
6236 * the CPU before the status block posted prior to the interrupt.
6237 * Reading the PCI State register will confirm whether the
6238 * interrupt is ours and will flush the status block.
6240 if (unlikely(sblk->status_tag == tnapi->last_irq_tag)) {
6241 if (tg3_flag(tp, CHIP_RESETTING) ||
6242 (tr32(TG3PCI_PCISTATE) & PCISTATE_INT_NOT_ACTIVE)) {
6249 * writing any value to intr-mbox-0 clears PCI INTA# and
6250 * chip-internal interrupt pending events.
6251 * writing non-zero to intr-mbox-0 additional tells the
6252 * NIC to stop sending us irqs, engaging "in-intr-handler"
6255 * Flush the mailbox to de-assert the IRQ immediately to prevent
6256 * spurious interrupts. The flush impacts performance but
6257 * excessive spurious interrupts can be worse in some cases.
6259 tw32_mailbox_f(MAILBOX_INTERRUPT_0 + TG3_64BIT_REG_LOW, 0x00000001);
6262 * In a shared interrupt configuration, sometimes other devices'
6263 * interrupts will scream. We record the current status tag here
6264 * so that the above check can report that the screaming interrupts
6265 * are unhandled. Eventually they will be silenced.
6267 tnapi->last_irq_tag = sblk->status_tag;
6269 if (tg3_irq_sync(tp))
6272 prefetch(&tnapi->rx_rcb[tnapi->rx_rcb_ptr]);
6274 napi_schedule(&tnapi->napi);
6277 return IRQ_RETVAL(handled);
6280 /* ISR for interrupt test */
6281 static irqreturn_t tg3_test_isr(int irq, void *dev_id)
6283 struct tg3_napi *tnapi = dev_id;
6284 struct tg3 *tp = tnapi->tp;
6285 struct tg3_hw_status *sblk = tnapi->hw_status;
6287 if ((sblk->status & SD_STATUS_UPDATED) ||
6288 !(tr32(TG3PCI_PCISTATE) & PCISTATE_INT_NOT_ACTIVE)) {
6289 tg3_disable_ints(tp);
6290 return IRQ_RETVAL(1);
6292 return IRQ_RETVAL(0);
6295 #ifdef CONFIG_NET_POLL_CONTROLLER
6296 static void tg3_poll_controller(struct net_device *dev)
6299 struct tg3 *tp = netdev_priv(dev);
6301 for (i = 0; i < tp->irq_cnt; i++)
6302 tg3_interrupt(tp->napi[i].irq_vec, &tp->napi[i]);
6306 static void tg3_tx_timeout(struct net_device *dev)
6308 struct tg3 *tp = netdev_priv(dev);
6310 if (netif_msg_tx_err(tp)) {
6311 netdev_err(dev, "transmit timed out, resetting\n");
6315 tg3_reset_task_schedule(tp);
6318 /* Test for DMA buffers crossing any 4GB boundaries: 4G, 8G, etc */
6319 static inline int tg3_4g_overflow_test(dma_addr_t mapping, int len)
6321 u32 base = (u32) mapping & 0xffffffff;
6323 return (base > 0xffffdcc0) && (base + len + 8 < base);
6326 /* Test for DMA addresses > 40-bit */
6327 static inline int tg3_40bit_overflow_test(struct tg3 *tp, dma_addr_t mapping,
6330 #if defined(CONFIG_HIGHMEM) && (BITS_PER_LONG == 64)
6331 if (tg3_flag(tp, 40BIT_DMA_BUG))
6332 return ((u64) mapping + len) > DMA_BIT_MASK(40);
6339 static inline void tg3_tx_set_bd(struct tg3_tx_buffer_desc *txbd,
6340 dma_addr_t mapping, u32 len, u32 flags,
6343 txbd->addr_hi = ((u64) mapping >> 32);
6344 txbd->addr_lo = ((u64) mapping & 0xffffffff);
6345 txbd->len_flags = (len << TXD_LEN_SHIFT) | (flags & 0x0000ffff);
6346 txbd->vlan_tag = (mss << TXD_MSS_SHIFT) | (vlan << TXD_VLAN_TAG_SHIFT);
6349 static bool tg3_tx_frag_set(struct tg3_napi *tnapi, u32 *entry, u32 *budget,
6350 dma_addr_t map, u32 len, u32 flags,
6353 struct tg3 *tp = tnapi->tp;
6356 if (tg3_flag(tp, SHORT_DMA_BUG) && len <= 8)
6359 if (tg3_4g_overflow_test(map, len))
6362 if (tg3_40bit_overflow_test(tp, map, len))
6365 if (tp->dma_limit) {
6366 u32 prvidx = *entry;
6367 u32 tmp_flag = flags & ~TXD_FLAG_END;
6368 while (len > tp->dma_limit && *budget) {
6369 u32 frag_len = tp->dma_limit;
6370 len -= tp->dma_limit;
6372 /* Avoid the 8byte DMA problem */
6374 len += tp->dma_limit / 2;
6375 frag_len = tp->dma_limit / 2;
6378 tnapi->tx_buffers[*entry].fragmented = true;
6380 tg3_tx_set_bd(&tnapi->tx_ring[*entry], map,
6381 frag_len, tmp_flag, mss, vlan);
6384 *entry = NEXT_TX(*entry);
6391 tg3_tx_set_bd(&tnapi->tx_ring[*entry], map,
6392 len, flags, mss, vlan);
6394 *entry = NEXT_TX(*entry);
6397 tnapi->tx_buffers[prvidx].fragmented = false;
6401 tg3_tx_set_bd(&tnapi->tx_ring[*entry], map,
6402 len, flags, mss, vlan);
6403 *entry = NEXT_TX(*entry);
6409 static void tg3_tx_skb_unmap(struct tg3_napi *tnapi, u32 entry, int last)
6412 struct sk_buff *skb;
6413 struct tg3_tx_ring_info *txb = &tnapi->tx_buffers[entry];
6418 pci_unmap_single(tnapi->tp->pdev,
6419 dma_unmap_addr(txb, mapping),
6423 while (txb->fragmented) {
6424 txb->fragmented = false;
6425 entry = NEXT_TX(entry);
6426 txb = &tnapi->tx_buffers[entry];
6429 for (i = 0; i <= last; i++) {
6430 const skb_frag_t *frag = &skb_shinfo(skb)->frags[i];
6432 entry = NEXT_TX(entry);
6433 txb = &tnapi->tx_buffers[entry];
6435 pci_unmap_page(tnapi->tp->pdev,
6436 dma_unmap_addr(txb, mapping),
6437 skb_frag_size(frag), PCI_DMA_TODEVICE);
6439 while (txb->fragmented) {
6440 txb->fragmented = false;
6441 entry = NEXT_TX(entry);
6442 txb = &tnapi->tx_buffers[entry];
6447 /* Workaround 4GB and 40-bit hardware DMA bugs. */
6448 static int tigon3_dma_hwbug_workaround(struct tg3_napi *tnapi,
6449 struct sk_buff **pskb,
6450 u32 *entry, u32 *budget,
6451 u32 base_flags, u32 mss, u32 vlan)
6453 struct tg3 *tp = tnapi->tp;
6454 struct sk_buff *new_skb, *skb = *pskb;
6455 dma_addr_t new_addr = 0;
6458 if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5701)
6459 new_skb = skb_copy(skb, GFP_ATOMIC);
6461 int more_headroom = 4 - ((unsigned long)skb->data & 3);
6463 new_skb = skb_copy_expand(skb,
6464 skb_headroom(skb) + more_headroom,
6465 skb_tailroom(skb), GFP_ATOMIC);
6471 /* New SKB is guaranteed to be linear. */
6472 new_addr = pci_map_single(tp->pdev, new_skb->data, new_skb->len,
6474 /* Make sure the mapping succeeded */
6475 if (pci_dma_mapping_error(tp->pdev, new_addr)) {
6476 dev_kfree_skb(new_skb);
6479 u32 save_entry = *entry;
6481 base_flags |= TXD_FLAG_END;
6483 tnapi->tx_buffers[*entry].skb = new_skb;
6484 dma_unmap_addr_set(&tnapi->tx_buffers[*entry],
6487 if (tg3_tx_frag_set(tnapi, entry, budget, new_addr,
6488 new_skb->len, base_flags,
6490 tg3_tx_skb_unmap(tnapi, save_entry, -1);
6491 dev_kfree_skb(new_skb);
6502 static netdev_tx_t tg3_start_xmit(struct sk_buff *, struct net_device *);
6504 /* Use GSO to workaround a rare TSO bug that may be triggered when the
6505 * TSO header is greater than 80 bytes.
6507 static int tg3_tso_bug(struct tg3 *tp, struct sk_buff *skb)
6509 struct sk_buff *segs, *nskb;
6510 u32 frag_cnt_est = skb_shinfo(skb)->gso_segs * 3;
6512 /* Estimate the number of fragments in the worst case */
6513 if (unlikely(tg3_tx_avail(&tp->napi[0]) <= frag_cnt_est)) {
6514 netif_stop_queue(tp->dev);
6516 /* netif_tx_stop_queue() must be done before checking
6517 * checking tx index in tg3_tx_avail() below, because in
6518 * tg3_tx(), we update tx index before checking for
6519 * netif_tx_queue_stopped().
6522 if (tg3_tx_avail(&tp->napi[0]) <= frag_cnt_est)
6523 return NETDEV_TX_BUSY;
6525 netif_wake_queue(tp->dev);
6528 segs = skb_gso_segment(skb, tp->dev->features & ~NETIF_F_TSO);
6530 goto tg3_tso_bug_end;
6536 tg3_start_xmit(nskb, tp->dev);
6542 return NETDEV_TX_OK;
6545 /* hard_start_xmit for devices that have the 4G bug and/or 40-bit bug and
6546 * support TG3_FLAG_HW_TSO_1 or firmware TSO only.
6548 static netdev_tx_t tg3_start_xmit(struct sk_buff *skb, struct net_device *dev)
6550 struct tg3 *tp = netdev_priv(dev);
6551 u32 len, entry, base_flags, mss, vlan = 0;
6553 int i = -1, would_hit_hwbug;
6555 struct tg3_napi *tnapi;
6556 struct netdev_queue *txq;
6559 txq = netdev_get_tx_queue(dev, skb_get_queue_mapping(skb));
6560 tnapi = &tp->napi[skb_get_queue_mapping(skb)];
6561 if (tg3_flag(tp, ENABLE_TSS))
6564 budget = tg3_tx_avail(tnapi);
6566 /* We are running in BH disabled context with netif_tx_lock
6567 * and TX reclaim runs via tp->napi.poll inside of a software
6568 * interrupt. Furthermore, IRQ processing runs lockless so we have
6569 * no IRQ context deadlocks to worry about either. Rejoice!
6571 if (unlikely(budget <= (skb_shinfo(skb)->nr_frags + 1))) {
6572 if (!netif_tx_queue_stopped(txq)) {
6573 netif_tx_stop_queue(txq);
6575 /* This is a hard error, log it. */
6577 "BUG! Tx Ring full when queue awake!\n");
6579 return NETDEV_TX_BUSY;
6582 entry = tnapi->tx_prod;
6584 if (skb->ip_summed == CHECKSUM_PARTIAL)
6585 base_flags |= TXD_FLAG_TCPUDP_CSUM;
6587 mss = skb_shinfo(skb)->gso_size;
6590 u32 tcp_opt_len, hdr_len;
6592 if (skb_header_cloned(skb) &&
6593 pskb_expand_head(skb, 0, 0, GFP_ATOMIC))
6597 tcp_opt_len = tcp_optlen(skb);
6599 hdr_len = skb_transport_offset(skb) + tcp_hdrlen(skb) - ETH_HLEN;
6601 if (!skb_is_gso_v6(skb)) {
6603 iph->tot_len = htons(mss + hdr_len);
6606 if (unlikely((ETH_HLEN + hdr_len) > 80) &&
6607 tg3_flag(tp, TSO_BUG))
6608 return tg3_tso_bug(tp, skb);
6610 base_flags |= (TXD_FLAG_CPU_PRE_DMA |
6611 TXD_FLAG_CPU_POST_DMA);
6613 if (tg3_flag(tp, HW_TSO_1) ||
6614 tg3_flag(tp, HW_TSO_2) ||
6615 tg3_flag(tp, HW_TSO_3)) {
6616 tcp_hdr(skb)->check = 0;
6617 base_flags &= ~TXD_FLAG_TCPUDP_CSUM;
6619 tcp_hdr(skb)->check = ~csum_tcpudp_magic(iph->saddr,
6624 if (tg3_flag(tp, HW_TSO_3)) {
6625 mss |= (hdr_len & 0xc) << 12;
6627 base_flags |= 0x00000010;
6628 base_flags |= (hdr_len & 0x3e0) << 5;
6629 } else if (tg3_flag(tp, HW_TSO_2))
6630 mss |= hdr_len << 9;
6631 else if (tg3_flag(tp, HW_TSO_1) ||
6632 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705) {
6633 if (tcp_opt_len || iph->ihl > 5) {
6636 tsflags = (iph->ihl - 5) + (tcp_opt_len >> 2);
6637 mss |= (tsflags << 11);
6640 if (tcp_opt_len || iph->ihl > 5) {
6643 tsflags = (iph->ihl - 5) + (tcp_opt_len >> 2);
6644 base_flags |= tsflags << 12;
6649 if (tg3_flag(tp, USE_JUMBO_BDFLAG) &&
6650 !mss && skb->len > VLAN_ETH_FRAME_LEN)
6651 base_flags |= TXD_FLAG_JMB_PKT;
6653 if (vlan_tx_tag_present(skb)) {
6654 base_flags |= TXD_FLAG_VLAN;
6655 vlan = vlan_tx_tag_get(skb);
6658 len = skb_headlen(skb);
6660 mapping = pci_map_single(tp->pdev, skb->data, len, PCI_DMA_TODEVICE);
6661 if (pci_dma_mapping_error(tp->pdev, mapping))
6665 tnapi->tx_buffers[entry].skb = skb;
6666 dma_unmap_addr_set(&tnapi->tx_buffers[entry], mapping, mapping);
6668 would_hit_hwbug = 0;
6670 if (tg3_flag(tp, 5701_DMA_BUG))
6671 would_hit_hwbug = 1;
6673 if (tg3_tx_frag_set(tnapi, &entry, &budget, mapping, len, base_flags |
6674 ((skb_shinfo(skb)->nr_frags == 0) ? TXD_FLAG_END : 0),
6676 would_hit_hwbug = 1;
6677 /* Now loop through additional data fragments, and queue them. */
6678 } else if (skb_shinfo(skb)->nr_frags > 0) {
6681 if (!tg3_flag(tp, HW_TSO_1) &&
6682 !tg3_flag(tp, HW_TSO_2) &&
6683 !tg3_flag(tp, HW_TSO_3))
6686 last = skb_shinfo(skb)->nr_frags - 1;
6687 for (i = 0; i <= last; i++) {
6688 skb_frag_t *frag = &skb_shinfo(skb)->frags[i];
6690 len = skb_frag_size(frag);
6691 mapping = skb_frag_dma_map(&tp->pdev->dev, frag, 0,
6692 len, DMA_TO_DEVICE);
6694 tnapi->tx_buffers[entry].skb = NULL;
6695 dma_unmap_addr_set(&tnapi->tx_buffers[entry], mapping,
6697 if (dma_mapping_error(&tp->pdev->dev, mapping))
6701 tg3_tx_frag_set(tnapi, &entry, &budget, mapping,
6703 ((i == last) ? TXD_FLAG_END : 0),
6705 would_hit_hwbug = 1;
6711 if (would_hit_hwbug) {
6712 tg3_tx_skb_unmap(tnapi, tnapi->tx_prod, i);
6714 /* If the workaround fails due to memory/mapping
6715 * failure, silently drop this packet.
6717 entry = tnapi->tx_prod;
6718 budget = tg3_tx_avail(tnapi);
6719 if (tigon3_dma_hwbug_workaround(tnapi, &skb, &entry, &budget,
6720 base_flags, mss, vlan))
6724 skb_tx_timestamp(skb);
6725 netdev_sent_queue(tp->dev, skb->len);
6727 /* Packets are ready, update Tx producer idx local and on card. */
6728 tw32_tx_mbox(tnapi->prodmbox, entry);
6730 tnapi->tx_prod = entry;
6731 if (unlikely(tg3_tx_avail(tnapi) <= (MAX_SKB_FRAGS + 1))) {
6732 netif_tx_stop_queue(txq);
6734 /* netif_tx_stop_queue() must be done before checking
6735 * checking tx index in tg3_tx_avail() below, because in
6736 * tg3_tx(), we update tx index before checking for
6737 * netif_tx_queue_stopped().
6740 if (tg3_tx_avail(tnapi) > TG3_TX_WAKEUP_THRESH(tnapi))
6741 netif_tx_wake_queue(txq);
6745 return NETDEV_TX_OK;
6748 tg3_tx_skb_unmap(tnapi, tnapi->tx_prod, --i);
6749 tnapi->tx_buffers[tnapi->tx_prod].skb = NULL;
6754 return NETDEV_TX_OK;
6757 static void tg3_mac_loopback(struct tg3 *tp, bool enable)
6760 tp->mac_mode &= ~(MAC_MODE_HALF_DUPLEX |
6761 MAC_MODE_PORT_MODE_MASK);
6763 tp->mac_mode |= MAC_MODE_PORT_INT_LPBACK;
6765 if (!tg3_flag(tp, 5705_PLUS))
6766 tp->mac_mode |= MAC_MODE_LINK_POLARITY;
6768 if (tp->phy_flags & TG3_PHYFLG_10_100_ONLY)
6769 tp->mac_mode |= MAC_MODE_PORT_MODE_MII;
6771 tp->mac_mode |= MAC_MODE_PORT_MODE_GMII;
6773 tp->mac_mode &= ~MAC_MODE_PORT_INT_LPBACK;
6775 if (tg3_flag(tp, 5705_PLUS) ||
6776 (tp->phy_flags & TG3_PHYFLG_PHY_SERDES) ||
6777 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700)
6778 tp->mac_mode &= ~MAC_MODE_LINK_POLARITY;
6781 tw32(MAC_MODE, tp->mac_mode);
6785 static int tg3_phy_lpbk_set(struct tg3 *tp, u32 speed, bool extlpbk)
6787 u32 val, bmcr, mac_mode, ptest = 0;
6789 tg3_phy_toggle_apd(tp, false);
6790 tg3_phy_toggle_automdix(tp, 0);
6792 if (extlpbk && tg3_phy_set_extloopbk(tp))
6795 bmcr = BMCR_FULLDPLX;
6800 bmcr |= BMCR_SPEED100;
6804 if (tp->phy_flags & TG3_PHYFLG_IS_FET) {
6806 bmcr |= BMCR_SPEED100;
6809 bmcr |= BMCR_SPEED1000;
6814 if (!(tp->phy_flags & TG3_PHYFLG_IS_FET)) {
6815 tg3_readphy(tp, MII_CTRL1000, &val);
6816 val |= CTL1000_AS_MASTER |
6817 CTL1000_ENABLE_MASTER;
6818 tg3_writephy(tp, MII_CTRL1000, val);
6820 ptest = MII_TG3_FET_PTEST_TRIM_SEL |
6821 MII_TG3_FET_PTEST_TRIM_2;
6822 tg3_writephy(tp, MII_TG3_FET_PTEST, ptest);
6825 bmcr |= BMCR_LOOPBACK;
6827 tg3_writephy(tp, MII_BMCR, bmcr);
6829 /* The write needs to be flushed for the FETs */
6830 if (tp->phy_flags & TG3_PHYFLG_IS_FET)
6831 tg3_readphy(tp, MII_BMCR, &bmcr);
6835 if ((tp->phy_flags & TG3_PHYFLG_IS_FET) &&
6836 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785) {
6837 tg3_writephy(tp, MII_TG3_FET_PTEST, ptest |
6838 MII_TG3_FET_PTEST_FRC_TX_LINK |
6839 MII_TG3_FET_PTEST_FRC_TX_LOCK);
6841 /* The write needs to be flushed for the AC131 */
6842 tg3_readphy(tp, MII_TG3_FET_PTEST, &val);
6845 /* Reset to prevent losing 1st rx packet intermittently */
6846 if ((tp->phy_flags & TG3_PHYFLG_MII_SERDES) &&
6847 tg3_flag(tp, 5780_CLASS)) {
6848 tw32_f(MAC_RX_MODE, RX_MODE_RESET);
6850 tw32_f(MAC_RX_MODE, tp->rx_mode);
6853 mac_mode = tp->mac_mode &
6854 ~(MAC_MODE_PORT_MODE_MASK | MAC_MODE_HALF_DUPLEX);
6855 if (speed == SPEED_1000)
6856 mac_mode |= MAC_MODE_PORT_MODE_GMII;
6858 mac_mode |= MAC_MODE_PORT_MODE_MII;
6860 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700) {
6861 u32 masked_phy_id = tp->phy_id & TG3_PHY_ID_MASK;
6863 if (masked_phy_id == TG3_PHY_ID_BCM5401)
6864 mac_mode &= ~MAC_MODE_LINK_POLARITY;
6865 else if (masked_phy_id == TG3_PHY_ID_BCM5411)
6866 mac_mode |= MAC_MODE_LINK_POLARITY;
6868 tg3_writephy(tp, MII_TG3_EXT_CTRL,
6869 MII_TG3_EXT_CTRL_LNK3_LED_MODE);
6872 tw32(MAC_MODE, mac_mode);
6878 static void tg3_set_loopback(struct net_device *dev, netdev_features_t features)
6880 struct tg3 *tp = netdev_priv(dev);
6882 if (features & NETIF_F_LOOPBACK) {
6883 if (tp->mac_mode & MAC_MODE_PORT_INT_LPBACK)
6886 spin_lock_bh(&tp->lock);
6887 tg3_mac_loopback(tp, true);
6888 netif_carrier_on(tp->dev);
6889 spin_unlock_bh(&tp->lock);
6890 netdev_info(dev, "Internal MAC loopback mode enabled.\n");
6892 if (!(tp->mac_mode & MAC_MODE_PORT_INT_LPBACK))
6895 spin_lock_bh(&tp->lock);
6896 tg3_mac_loopback(tp, false);
6897 /* Force link status check */
6898 tg3_setup_phy(tp, 1);
6899 spin_unlock_bh(&tp->lock);
6900 netdev_info(dev, "Internal MAC loopback mode disabled.\n");
6904 static netdev_features_t tg3_fix_features(struct net_device *dev,
6905 netdev_features_t features)
6907 struct tg3 *tp = netdev_priv(dev);
6909 if (dev->mtu > ETH_DATA_LEN && tg3_flag(tp, 5780_CLASS))
6910 features &= ~NETIF_F_ALL_TSO;
6915 static int tg3_set_features(struct net_device *dev, netdev_features_t features)
6917 netdev_features_t changed = dev->features ^ features;
6919 if ((changed & NETIF_F_LOOPBACK) && netif_running(dev))
6920 tg3_set_loopback(dev, features);
6925 static void tg3_rx_prodring_free(struct tg3 *tp,
6926 struct tg3_rx_prodring_set *tpr)
6930 if (tpr != &tp->napi[0].prodring) {
6931 for (i = tpr->rx_std_cons_idx; i != tpr->rx_std_prod_idx;
6932 i = (i + 1) & tp->rx_std_ring_mask)
6933 tg3_rx_data_free(tp, &tpr->rx_std_buffers[i],
6936 if (tg3_flag(tp, JUMBO_CAPABLE)) {
6937 for (i = tpr->rx_jmb_cons_idx;
6938 i != tpr->rx_jmb_prod_idx;
6939 i = (i + 1) & tp->rx_jmb_ring_mask) {
6940 tg3_rx_data_free(tp, &tpr->rx_jmb_buffers[i],
6948 for (i = 0; i <= tp->rx_std_ring_mask; i++)
6949 tg3_rx_data_free(tp, &tpr->rx_std_buffers[i],
6952 if (tg3_flag(tp, JUMBO_CAPABLE) && !tg3_flag(tp, 5780_CLASS)) {
6953 for (i = 0; i <= tp->rx_jmb_ring_mask; i++)
6954 tg3_rx_data_free(tp, &tpr->rx_jmb_buffers[i],
6959 /* Initialize rx rings for packet processing.
6961 * The chip has been shut down and the driver detached from
6962 * the networking, so no interrupts or new tx packets will
6963 * end up in the driver. tp->{tx,}lock are held and thus
6966 static int tg3_rx_prodring_alloc(struct tg3 *tp,
6967 struct tg3_rx_prodring_set *tpr)
6969 u32 i, rx_pkt_dma_sz;
6971 tpr->rx_std_cons_idx = 0;
6972 tpr->rx_std_prod_idx = 0;
6973 tpr->rx_jmb_cons_idx = 0;
6974 tpr->rx_jmb_prod_idx = 0;
6976 if (tpr != &tp->napi[0].prodring) {
6977 memset(&tpr->rx_std_buffers[0], 0,
6978 TG3_RX_STD_BUFF_RING_SIZE(tp));
6979 if (tpr->rx_jmb_buffers)
6980 memset(&tpr->rx_jmb_buffers[0], 0,
6981 TG3_RX_JMB_BUFF_RING_SIZE(tp));
6985 /* Zero out all descriptors. */
6986 memset(tpr->rx_std, 0, TG3_RX_STD_RING_BYTES(tp));
6988 rx_pkt_dma_sz = TG3_RX_STD_DMA_SZ;
6989 if (tg3_flag(tp, 5780_CLASS) &&
6990 tp->dev->mtu > ETH_DATA_LEN)
6991 rx_pkt_dma_sz = TG3_RX_JMB_DMA_SZ;
6992 tp->rx_pkt_map_sz = TG3_RX_DMA_TO_MAP_SZ(rx_pkt_dma_sz);
6994 /* Initialize invariants of the rings, we only set this
6995 * stuff once. This works because the card does not
6996 * write into the rx buffer posting rings.
6998 for (i = 0; i <= tp->rx_std_ring_mask; i++) {
6999 struct tg3_rx_buffer_desc *rxd;
7001 rxd = &tpr->rx_std[i];
7002 rxd->idx_len = rx_pkt_dma_sz << RXD_LEN_SHIFT;
7003 rxd->type_flags = (RXD_FLAG_END << RXD_FLAGS_SHIFT);
7004 rxd->opaque = (RXD_OPAQUE_RING_STD |
7005 (i << RXD_OPAQUE_INDEX_SHIFT));
7008 /* Now allocate fresh SKBs for each rx ring. */
7009 for (i = 0; i < tp->rx_pending; i++) {
7010 if (tg3_alloc_rx_data(tp, tpr, RXD_OPAQUE_RING_STD, i) < 0) {
7011 netdev_warn(tp->dev,
7012 "Using a smaller RX standard ring. Only "
7013 "%d out of %d buffers were allocated "
7014 "successfully\n", i, tp->rx_pending);
7022 if (!tg3_flag(tp, JUMBO_CAPABLE) || tg3_flag(tp, 5780_CLASS))
7025 memset(tpr->rx_jmb, 0, TG3_RX_JMB_RING_BYTES(tp));
7027 if (!tg3_flag(tp, JUMBO_RING_ENABLE))
7030 for (i = 0; i <= tp->rx_jmb_ring_mask; i++) {
7031 struct tg3_rx_buffer_desc *rxd;
7033 rxd = &tpr->rx_jmb[i].std;
7034 rxd->idx_len = TG3_RX_JMB_DMA_SZ << RXD_LEN_SHIFT;
7035 rxd->type_flags = (RXD_FLAG_END << RXD_FLAGS_SHIFT) |
7037 rxd->opaque = (RXD_OPAQUE_RING_JUMBO |
7038 (i << RXD_OPAQUE_INDEX_SHIFT));
7041 for (i = 0; i < tp->rx_jumbo_pending; i++) {
7042 if (tg3_alloc_rx_data(tp, tpr, RXD_OPAQUE_RING_JUMBO, i) < 0) {
7043 netdev_warn(tp->dev,
7044 "Using a smaller RX jumbo ring. Only %d "
7045 "out of %d buffers were allocated "
7046 "successfully\n", i, tp->rx_jumbo_pending);
7049 tp->rx_jumbo_pending = i;
7058 tg3_rx_prodring_free(tp, tpr);
7062 static void tg3_rx_prodring_fini(struct tg3 *tp,
7063 struct tg3_rx_prodring_set *tpr)
7065 kfree(tpr->rx_std_buffers);
7066 tpr->rx_std_buffers = NULL;
7067 kfree(tpr->rx_jmb_buffers);
7068 tpr->rx_jmb_buffers = NULL;
7070 dma_free_coherent(&tp->pdev->dev, TG3_RX_STD_RING_BYTES(tp),
7071 tpr->rx_std, tpr->rx_std_mapping);
7075 dma_free_coherent(&tp->pdev->dev, TG3_RX_JMB_RING_BYTES(tp),
7076 tpr->rx_jmb, tpr->rx_jmb_mapping);
7081 static int tg3_rx_prodring_init(struct tg3 *tp,
7082 struct tg3_rx_prodring_set *tpr)
7084 tpr->rx_std_buffers = kzalloc(TG3_RX_STD_BUFF_RING_SIZE(tp),
7086 if (!tpr->rx_std_buffers)
7089 tpr->rx_std = dma_alloc_coherent(&tp->pdev->dev,
7090 TG3_RX_STD_RING_BYTES(tp),
7091 &tpr->rx_std_mapping,
7096 if (tg3_flag(tp, JUMBO_CAPABLE) && !tg3_flag(tp, 5780_CLASS)) {
7097 tpr->rx_jmb_buffers = kzalloc(TG3_RX_JMB_BUFF_RING_SIZE(tp),
7099 if (!tpr->rx_jmb_buffers)
7102 tpr->rx_jmb = dma_alloc_coherent(&tp->pdev->dev,
7103 TG3_RX_JMB_RING_BYTES(tp),
7104 &tpr->rx_jmb_mapping,
7113 tg3_rx_prodring_fini(tp, tpr);
7117 /* Free up pending packets in all rx/tx rings.
7119 * The chip has been shut down and the driver detached from
7120 * the networking, so no interrupts or new tx packets will
7121 * end up in the driver. tp->{tx,}lock is not held and we are not
7122 * in an interrupt context and thus may sleep.
7124 static void tg3_free_rings(struct tg3 *tp)
7128 for (j = 0; j < tp->irq_cnt; j++) {
7129 struct tg3_napi *tnapi = &tp->napi[j];
7131 tg3_rx_prodring_free(tp, &tnapi->prodring);
7133 if (!tnapi->tx_buffers)
7136 for (i = 0; i < TG3_TX_RING_SIZE; i++) {
7137 struct sk_buff *skb = tnapi->tx_buffers[i].skb;
7142 tg3_tx_skb_unmap(tnapi, i,
7143 skb_shinfo(skb)->nr_frags - 1);
7145 dev_kfree_skb_any(skb);
7148 netdev_reset_queue(tp->dev);
7151 /* Initialize tx/rx rings for packet processing.
7153 * The chip has been shut down and the driver detached from
7154 * the networking, so no interrupts or new tx packets will
7155 * end up in the driver. tp->{tx,}lock are held and thus
7158 static int tg3_init_rings(struct tg3 *tp)
7162 /* Free up all the SKBs. */
7165 for (i = 0; i < tp->irq_cnt; i++) {
7166 struct tg3_napi *tnapi = &tp->napi[i];
7168 tnapi->last_tag = 0;
7169 tnapi->last_irq_tag = 0;
7170 tnapi->hw_status->status = 0;
7171 tnapi->hw_status->status_tag = 0;
7172 memset(tnapi->hw_status, 0, TG3_HW_STATUS_SIZE);
7177 memset(tnapi->tx_ring, 0, TG3_TX_RING_BYTES);
7179 tnapi->rx_rcb_ptr = 0;
7181 memset(tnapi->rx_rcb, 0, TG3_RX_RCB_RING_BYTES(tp));
7183 if (tg3_rx_prodring_alloc(tp, &tnapi->prodring)) {
7193 * Must not be invoked with interrupt sources disabled and
7194 * the hardware shutdown down.
7196 static void tg3_free_consistent(struct tg3 *tp)
7200 for (i = 0; i < tp->irq_cnt; i++) {
7201 struct tg3_napi *tnapi = &tp->napi[i];
7203 if (tnapi->tx_ring) {
7204 dma_free_coherent(&tp->pdev->dev, TG3_TX_RING_BYTES,
7205 tnapi->tx_ring, tnapi->tx_desc_mapping);
7206 tnapi->tx_ring = NULL;
7209 kfree(tnapi->tx_buffers);
7210 tnapi->tx_buffers = NULL;
7212 if (tnapi->rx_rcb) {
7213 dma_free_coherent(&tp->pdev->dev,
7214 TG3_RX_RCB_RING_BYTES(tp),
7216 tnapi->rx_rcb_mapping);
7217 tnapi->rx_rcb = NULL;
7220 tg3_rx_prodring_fini(tp, &tnapi->prodring);
7222 if (tnapi->hw_status) {
7223 dma_free_coherent(&tp->pdev->dev, TG3_HW_STATUS_SIZE,
7225 tnapi->status_mapping);
7226 tnapi->hw_status = NULL;
7231 dma_free_coherent(&tp->pdev->dev, sizeof(struct tg3_hw_stats),
7232 tp->hw_stats, tp->stats_mapping);
7233 tp->hw_stats = NULL;
7238 * Must not be invoked with interrupt sources disabled and
7239 * the hardware shutdown down. Can sleep.
7241 static int tg3_alloc_consistent(struct tg3 *tp)
7245 tp->hw_stats = dma_alloc_coherent(&tp->pdev->dev,
7246 sizeof(struct tg3_hw_stats),
7252 memset(tp->hw_stats, 0, sizeof(struct tg3_hw_stats));
7254 for (i = 0; i < tp->irq_cnt; i++) {
7255 struct tg3_napi *tnapi = &tp->napi[i];
7256 struct tg3_hw_status *sblk;
7258 tnapi->hw_status = dma_alloc_coherent(&tp->pdev->dev,
7260 &tnapi->status_mapping,
7262 if (!tnapi->hw_status)
7265 memset(tnapi->hw_status, 0, TG3_HW_STATUS_SIZE);
7266 sblk = tnapi->hw_status;
7268 if (tg3_rx_prodring_init(tp, &tnapi->prodring))
7271 /* If multivector TSS is enabled, vector 0 does not handle
7272 * tx interrupts. Don't allocate any resources for it.
7274 if ((!i && !tg3_flag(tp, ENABLE_TSS)) ||
7275 (i && tg3_flag(tp, ENABLE_TSS))) {
7276 tnapi->tx_buffers = kzalloc(
7277 sizeof(struct tg3_tx_ring_info) *
7278 TG3_TX_RING_SIZE, GFP_KERNEL);
7279 if (!tnapi->tx_buffers)
7282 tnapi->tx_ring = dma_alloc_coherent(&tp->pdev->dev,
7284 &tnapi->tx_desc_mapping,
7286 if (!tnapi->tx_ring)
7291 * When RSS is enabled, the status block format changes
7292 * slightly. The "rx_jumbo_consumer", "reserved",
7293 * and "rx_mini_consumer" members get mapped to the
7294 * other three rx return ring producer indexes.
7298 tnapi->rx_rcb_prod_idx = &sblk->idx[0].rx_producer;
7301 tnapi->rx_rcb_prod_idx = &sblk->rx_jumbo_consumer;
7304 tnapi->rx_rcb_prod_idx = &sblk->reserved;
7307 tnapi->rx_rcb_prod_idx = &sblk->rx_mini_consumer;
7312 * If multivector RSS is enabled, vector 0 does not handle
7313 * rx or tx interrupts. Don't allocate any resources for it.
7315 if (!i && tg3_flag(tp, ENABLE_RSS))
7318 tnapi->rx_rcb = dma_alloc_coherent(&tp->pdev->dev,
7319 TG3_RX_RCB_RING_BYTES(tp),
7320 &tnapi->rx_rcb_mapping,
7325 memset(tnapi->rx_rcb, 0, TG3_RX_RCB_RING_BYTES(tp));
7331 tg3_free_consistent(tp);
7335 #define MAX_WAIT_CNT 1000
7337 /* To stop a block, clear the enable bit and poll till it
7338 * clears. tp->lock is held.
7340 static int tg3_stop_block(struct tg3 *tp, unsigned long ofs, u32 enable_bit, int silent)
7345 if (tg3_flag(tp, 5705_PLUS)) {
7352 /* We can't enable/disable these bits of the
7353 * 5705/5750, just say success.
7366 for (i = 0; i < MAX_WAIT_CNT; i++) {
7369 if ((val & enable_bit) == 0)
7373 if (i == MAX_WAIT_CNT && !silent) {
7374 dev_err(&tp->pdev->dev,
7375 "tg3_stop_block timed out, ofs=%lx enable_bit=%x\n",
7383 /* tp->lock is held. */
7384 static int tg3_abort_hw(struct tg3 *tp, int silent)
7388 tg3_disable_ints(tp);
7390 tp->rx_mode &= ~RX_MODE_ENABLE;
7391 tw32_f(MAC_RX_MODE, tp->rx_mode);
7394 err = tg3_stop_block(tp, RCVBDI_MODE, RCVBDI_MODE_ENABLE, silent);
7395 err |= tg3_stop_block(tp, RCVLPC_MODE, RCVLPC_MODE_ENABLE, silent);
7396 err |= tg3_stop_block(tp, RCVLSC_MODE, RCVLSC_MODE_ENABLE, silent);
7397 err |= tg3_stop_block(tp, RCVDBDI_MODE, RCVDBDI_MODE_ENABLE, silent);
7398 err |= tg3_stop_block(tp, RCVDCC_MODE, RCVDCC_MODE_ENABLE, silent);
7399 err |= tg3_stop_block(tp, RCVCC_MODE, RCVCC_MODE_ENABLE, silent);
7401 err |= tg3_stop_block(tp, SNDBDS_MODE, SNDBDS_MODE_ENABLE, silent);
7402 err |= tg3_stop_block(tp, SNDBDI_MODE, SNDBDI_MODE_ENABLE, silent);
7403 err |= tg3_stop_block(tp, SNDDATAI_MODE, SNDDATAI_MODE_ENABLE, silent);
7404 err |= tg3_stop_block(tp, RDMAC_MODE, RDMAC_MODE_ENABLE, silent);
7405 err |= tg3_stop_block(tp, SNDDATAC_MODE, SNDDATAC_MODE_ENABLE, silent);
7406 err |= tg3_stop_block(tp, DMAC_MODE, DMAC_MODE_ENABLE, silent);
7407 err |= tg3_stop_block(tp, SNDBDC_MODE, SNDBDC_MODE_ENABLE, silent);
7409 tp->mac_mode &= ~MAC_MODE_TDE_ENABLE;
7410 tw32_f(MAC_MODE, tp->mac_mode);
7413 tp->tx_mode &= ~TX_MODE_ENABLE;
7414 tw32_f(MAC_TX_MODE, tp->tx_mode);
7416 for (i = 0; i < MAX_WAIT_CNT; i++) {
7418 if (!(tr32(MAC_TX_MODE) & TX_MODE_ENABLE))
7421 if (i >= MAX_WAIT_CNT) {
7422 dev_err(&tp->pdev->dev,
7423 "%s timed out, TX_MODE_ENABLE will not clear "
7424 "MAC_TX_MODE=%08x\n", __func__, tr32(MAC_TX_MODE));
7428 err |= tg3_stop_block(tp, HOSTCC_MODE, HOSTCC_MODE_ENABLE, silent);
7429 err |= tg3_stop_block(tp, WDMAC_MODE, WDMAC_MODE_ENABLE, silent);
7430 err |= tg3_stop_block(tp, MBFREE_MODE, MBFREE_MODE_ENABLE, silent);
7432 tw32(FTQ_RESET, 0xffffffff);
7433 tw32(FTQ_RESET, 0x00000000);
7435 err |= tg3_stop_block(tp, BUFMGR_MODE, BUFMGR_MODE_ENABLE, silent);
7436 err |= tg3_stop_block(tp, MEMARB_MODE, MEMARB_MODE_ENABLE, silent);
7438 for (i = 0; i < tp->irq_cnt; i++) {
7439 struct tg3_napi *tnapi = &tp->napi[i];
7440 if (tnapi->hw_status)
7441 memset(tnapi->hw_status, 0, TG3_HW_STATUS_SIZE);
7447 /* Save PCI command register before chip reset */
7448 static void tg3_save_pci_state(struct tg3 *tp)
7450 pci_read_config_word(tp->pdev, PCI_COMMAND, &tp->pci_cmd);
7453 /* Restore PCI state after chip reset */
7454 static void tg3_restore_pci_state(struct tg3 *tp)
7458 /* Re-enable indirect register accesses. */
7459 pci_write_config_dword(tp->pdev, TG3PCI_MISC_HOST_CTRL,
7460 tp->misc_host_ctrl);
7462 /* Set MAX PCI retry to zero. */
7463 val = (PCISTATE_ROM_ENABLE | PCISTATE_ROM_RETRY_ENABLE);
7464 if (tp->pci_chip_rev_id == CHIPREV_ID_5704_A0 &&
7465 tg3_flag(tp, PCIX_MODE))
7466 val |= PCISTATE_RETRY_SAME_DMA;
7467 /* Allow reads and writes to the APE register and memory space. */
7468 if (tg3_flag(tp, ENABLE_APE))
7469 val |= PCISTATE_ALLOW_APE_CTLSPC_WR |
7470 PCISTATE_ALLOW_APE_SHMEM_WR |
7471 PCISTATE_ALLOW_APE_PSPACE_WR;
7472 pci_write_config_dword(tp->pdev, TG3PCI_PCISTATE, val);
7474 pci_write_config_word(tp->pdev, PCI_COMMAND, tp->pci_cmd);
7476 if (!tg3_flag(tp, PCI_EXPRESS)) {
7477 pci_write_config_byte(tp->pdev, PCI_CACHE_LINE_SIZE,
7478 tp->pci_cacheline_sz);
7479 pci_write_config_byte(tp->pdev, PCI_LATENCY_TIMER,
7483 /* Make sure PCI-X relaxed ordering bit is clear. */
7484 if (tg3_flag(tp, PCIX_MODE)) {
7487 pci_read_config_word(tp->pdev, tp->pcix_cap + PCI_X_CMD,
7489 pcix_cmd &= ~PCI_X_CMD_ERO;
7490 pci_write_config_word(tp->pdev, tp->pcix_cap + PCI_X_CMD,
7494 if (tg3_flag(tp, 5780_CLASS)) {
7496 /* Chip reset on 5780 will reset MSI enable bit,
7497 * so need to restore it.
7499 if (tg3_flag(tp, USING_MSI)) {
7502 pci_read_config_word(tp->pdev,
7503 tp->msi_cap + PCI_MSI_FLAGS,
7505 pci_write_config_word(tp->pdev,
7506 tp->msi_cap + PCI_MSI_FLAGS,
7507 ctrl | PCI_MSI_FLAGS_ENABLE);
7508 val = tr32(MSGINT_MODE);
7509 tw32(MSGINT_MODE, val | MSGINT_MODE_ENABLE);
7514 /* tp->lock is held. */
7515 static int tg3_chip_reset(struct tg3 *tp)
7518 void (*write_op)(struct tg3 *, u32, u32);
7523 tg3_ape_lock(tp, TG3_APE_LOCK_GRC);
7525 /* No matching tg3_nvram_unlock() after this because
7526 * chip reset below will undo the nvram lock.
7528 tp->nvram_lock_cnt = 0;
7530 /* GRC_MISC_CFG core clock reset will clear the memory
7531 * enable bit in PCI register 4 and the MSI enable bit
7532 * on some chips, so we save relevant registers here.
7534 tg3_save_pci_state(tp);
7536 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5752 ||
7537 tg3_flag(tp, 5755_PLUS))
7538 tw32(GRC_FASTBOOT_PC, 0);
7541 * We must avoid the readl() that normally takes place.
7542 * It locks machines, causes machine checks, and other
7543 * fun things. So, temporarily disable the 5701
7544 * hardware workaround, while we do the reset.
7546 write_op = tp->write32;
7547 if (write_op == tg3_write_flush_reg32)
7548 tp->write32 = tg3_write32;
7550 /* Prevent the irq handler from reading or writing PCI registers
7551 * during chip reset when the memory enable bit in the PCI command
7552 * register may be cleared. The chip does not generate interrupt
7553 * at this time, but the irq handler may still be called due to irq
7554 * sharing or irqpoll.
7556 tg3_flag_set(tp, CHIP_RESETTING);
7557 for (i = 0; i < tp->irq_cnt; i++) {
7558 struct tg3_napi *tnapi = &tp->napi[i];
7559 if (tnapi->hw_status) {
7560 tnapi->hw_status->status = 0;
7561 tnapi->hw_status->status_tag = 0;
7563 tnapi->last_tag = 0;
7564 tnapi->last_irq_tag = 0;
7568 for (i = 0; i < tp->irq_cnt; i++)
7569 synchronize_irq(tp->napi[i].irq_vec);
7571 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57780) {
7572 val = tr32(TG3_PCIE_LNKCTL) & ~TG3_PCIE_LNKCTL_L1_PLL_PD_EN;
7573 tw32(TG3_PCIE_LNKCTL, val | TG3_PCIE_LNKCTL_L1_PLL_PD_DIS);
7577 val = GRC_MISC_CFG_CORECLK_RESET;
7579 if (tg3_flag(tp, PCI_EXPRESS)) {
7580 /* Force PCIe 1.0a mode */
7581 if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5785 &&
7582 !tg3_flag(tp, 57765_PLUS) &&
7583 tr32(TG3_PCIE_PHY_TSTCTL) ==
7584 (TG3_PCIE_PHY_TSTCTL_PCIE10 | TG3_PCIE_PHY_TSTCTL_PSCRAM))
7585 tw32(TG3_PCIE_PHY_TSTCTL, TG3_PCIE_PHY_TSTCTL_PSCRAM);
7587 if (tp->pci_chip_rev_id != CHIPREV_ID_5750_A0) {
7588 tw32(GRC_MISC_CFG, (1 << 29));
7593 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
7594 tw32(VCPU_STATUS, tr32(VCPU_STATUS) | VCPU_STATUS_DRV_RESET);
7595 tw32(GRC_VCPU_EXT_CTRL,
7596 tr32(GRC_VCPU_EXT_CTRL) & ~GRC_VCPU_EXT_CTRL_HALT_CPU);
7599 /* Manage gphy power for all CPMU absent PCIe devices. */
7600 if (tg3_flag(tp, 5705_PLUS) && !tg3_flag(tp, CPMU_PRESENT))
7601 val |= GRC_MISC_CFG_KEEP_GPHY_POWER;
7603 tw32(GRC_MISC_CFG, val);
7605 /* restore 5701 hardware bug workaround write method */
7606 tp->write32 = write_op;
7608 /* Unfortunately, we have to delay before the PCI read back.
7609 * Some 575X chips even will not respond to a PCI cfg access
7610 * when the reset command is given to the chip.
7612 * How do these hardware designers expect things to work
7613 * properly if the PCI write is posted for a long period
7614 * of time? It is always necessary to have some method by
7615 * which a register read back can occur to push the write
7616 * out which does the reset.
7618 * For most tg3 variants the trick below was working.
7623 /* Flush PCI posted writes. The normal MMIO registers
7624 * are inaccessible at this time so this is the only
7625 * way to make this reliably (actually, this is no longer
7626 * the case, see above). I tried to use indirect
7627 * register read/write but this upset some 5701 variants.
7629 pci_read_config_dword(tp->pdev, PCI_COMMAND, &val);
7633 if (tg3_flag(tp, PCI_EXPRESS) && pci_pcie_cap(tp->pdev)) {
7636 if (tp->pci_chip_rev_id == CHIPREV_ID_5750_A0) {
7640 /* Wait for link training to complete. */
7641 for (i = 0; i < 5000; i++)
7644 pci_read_config_dword(tp->pdev, 0xc4, &cfg_val);
7645 pci_write_config_dword(tp->pdev, 0xc4,
7646 cfg_val | (1 << 15));
7649 /* Clear the "no snoop" and "relaxed ordering" bits. */
7650 pci_read_config_word(tp->pdev,
7651 pci_pcie_cap(tp->pdev) + PCI_EXP_DEVCTL,
7653 val16 &= ~(PCI_EXP_DEVCTL_RELAX_EN |
7654 PCI_EXP_DEVCTL_NOSNOOP_EN);
7656 * Older PCIe devices only support the 128 byte
7657 * MPS setting. Enforce the restriction.
7659 if (!tg3_flag(tp, CPMU_PRESENT))
7660 val16 &= ~PCI_EXP_DEVCTL_PAYLOAD;
7661 pci_write_config_word(tp->pdev,
7662 pci_pcie_cap(tp->pdev) + PCI_EXP_DEVCTL,
7665 /* Clear error status */
7666 pci_write_config_word(tp->pdev,
7667 pci_pcie_cap(tp->pdev) + PCI_EXP_DEVSTA,
7668 PCI_EXP_DEVSTA_CED |
7669 PCI_EXP_DEVSTA_NFED |
7670 PCI_EXP_DEVSTA_FED |
7671 PCI_EXP_DEVSTA_URD);
7674 tg3_restore_pci_state(tp);
7676 tg3_flag_clear(tp, CHIP_RESETTING);
7677 tg3_flag_clear(tp, ERROR_PROCESSED);
7680 if (tg3_flag(tp, 5780_CLASS))
7681 val = tr32(MEMARB_MODE);
7682 tw32(MEMARB_MODE, val | MEMARB_MODE_ENABLE);
7684 if (tp->pci_chip_rev_id == CHIPREV_ID_5750_A3) {
7686 tw32(0x5000, 0x400);
7689 tw32(GRC_MODE, tp->grc_mode);
7691 if (tp->pci_chip_rev_id == CHIPREV_ID_5705_A0) {
7694 tw32(0xc4, val | (1 << 15));
7697 if ((tp->nic_sram_data_cfg & NIC_SRAM_DATA_CFG_MINI_PCI) != 0 &&
7698 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705) {
7699 tp->pci_clock_ctrl |= CLOCK_CTRL_CLKRUN_OENABLE;
7700 if (tp->pci_chip_rev_id == CHIPREV_ID_5705_A0)
7701 tp->pci_clock_ctrl |= CLOCK_CTRL_FORCE_CLKRUN;
7702 tw32(TG3PCI_CLOCK_CTRL, tp->pci_clock_ctrl);
7705 if (tp->phy_flags & TG3_PHYFLG_PHY_SERDES) {
7706 tp->mac_mode = MAC_MODE_PORT_MODE_TBI;
7708 } else if (tp->phy_flags & TG3_PHYFLG_MII_SERDES) {
7709 tp->mac_mode = MAC_MODE_PORT_MODE_GMII;
7714 tw32_f(MAC_MODE, val);
7717 tg3_ape_unlock(tp, TG3_APE_LOCK_GRC);
7719 err = tg3_poll_fw(tp);
7725 if (tg3_flag(tp, PCI_EXPRESS) &&
7726 tp->pci_chip_rev_id != CHIPREV_ID_5750_A0 &&
7727 GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5785 &&
7728 !tg3_flag(tp, 57765_PLUS)) {
7731 tw32(0x7c00, val | (1 << 25));
7734 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5720) {
7735 val = tr32(TG3_CPMU_CLCK_ORIDE);
7736 tw32(TG3_CPMU_CLCK_ORIDE, val & ~CPMU_CLCK_ORIDE_MAC_ORIDE_EN);
7739 /* Reprobe ASF enable state. */
7740 tg3_flag_clear(tp, ENABLE_ASF);
7741 tg3_flag_clear(tp, ASF_NEW_HANDSHAKE);
7742 tg3_read_mem(tp, NIC_SRAM_DATA_SIG, &val);
7743 if (val == NIC_SRAM_DATA_SIG_MAGIC) {
7746 tg3_read_mem(tp, NIC_SRAM_DATA_CFG, &nic_cfg);
7747 if (nic_cfg & NIC_SRAM_DATA_CFG_ASF_ENABLE) {
7748 tg3_flag_set(tp, ENABLE_ASF);
7749 tp->last_event_jiffies = jiffies;
7750 if (tg3_flag(tp, 5750_PLUS))
7751 tg3_flag_set(tp, ASF_NEW_HANDSHAKE);
7758 static struct rtnl_link_stats64 *tg3_get_stats64(struct net_device *,
7759 struct rtnl_link_stats64 *);
7760 static struct tg3_ethtool_stats *tg3_get_estats(struct tg3 *,
7761 struct tg3_ethtool_stats *);
7763 /* tp->lock is held. */
7764 static int tg3_halt(struct tg3 *tp, int kind, int silent)
7770 tg3_write_sig_pre_reset(tp, kind);
7772 tg3_abort_hw(tp, silent);
7773 err = tg3_chip_reset(tp);
7775 __tg3_set_mac_addr(tp, 0);
7777 tg3_write_sig_legacy(tp, kind);
7778 tg3_write_sig_post_reset(tp, kind);
7781 /* Save the stats across chip resets... */
7782 tg3_get_stats64(tp->dev, &tp->net_stats_prev),
7783 tg3_get_estats(tp, &tp->estats_prev);
7785 /* And make sure the next sample is new data */
7786 memset(tp->hw_stats, 0, sizeof(struct tg3_hw_stats));
7795 static int tg3_set_mac_addr(struct net_device *dev, void *p)
7797 struct tg3 *tp = netdev_priv(dev);
7798 struct sockaddr *addr = p;
7799 int err = 0, skip_mac_1 = 0;
7801 if (!is_valid_ether_addr(addr->sa_data))
7804 memcpy(dev->dev_addr, addr->sa_data, dev->addr_len);
7806 if (!netif_running(dev))
7809 if (tg3_flag(tp, ENABLE_ASF)) {
7810 u32 addr0_high, addr0_low, addr1_high, addr1_low;
7812 addr0_high = tr32(MAC_ADDR_0_HIGH);
7813 addr0_low = tr32(MAC_ADDR_0_LOW);
7814 addr1_high = tr32(MAC_ADDR_1_HIGH);
7815 addr1_low = tr32(MAC_ADDR_1_LOW);
7817 /* Skip MAC addr 1 if ASF is using it. */
7818 if ((addr0_high != addr1_high || addr0_low != addr1_low) &&
7819 !(addr1_high == 0 && addr1_low == 0))
7822 spin_lock_bh(&tp->lock);
7823 __tg3_set_mac_addr(tp, skip_mac_1);
7824 spin_unlock_bh(&tp->lock);
7829 /* tp->lock is held. */
7830 static void tg3_set_bdinfo(struct tg3 *tp, u32 bdinfo_addr,
7831 dma_addr_t mapping, u32 maxlen_flags,
7835 (bdinfo_addr + TG3_BDINFO_HOST_ADDR + TG3_64BIT_REG_HIGH),
7836 ((u64) mapping >> 32));
7838 (bdinfo_addr + TG3_BDINFO_HOST_ADDR + TG3_64BIT_REG_LOW),
7839 ((u64) mapping & 0xffffffff));
7841 (bdinfo_addr + TG3_BDINFO_MAXLEN_FLAGS),
7844 if (!tg3_flag(tp, 5705_PLUS))
7846 (bdinfo_addr + TG3_BDINFO_NIC_ADDR),
7850 static void __tg3_set_coalesce(struct tg3 *tp, struct ethtool_coalesce *ec)
7854 if (!tg3_flag(tp, ENABLE_TSS)) {
7855 tw32(HOSTCC_TXCOL_TICKS, ec->tx_coalesce_usecs);
7856 tw32(HOSTCC_TXMAX_FRAMES, ec->tx_max_coalesced_frames);
7857 tw32(HOSTCC_TXCOAL_MAXF_INT, ec->tx_max_coalesced_frames_irq);
7859 tw32(HOSTCC_TXCOL_TICKS, 0);
7860 tw32(HOSTCC_TXMAX_FRAMES, 0);
7861 tw32(HOSTCC_TXCOAL_MAXF_INT, 0);
7864 if (!tg3_flag(tp, ENABLE_RSS)) {
7865 tw32(HOSTCC_RXCOL_TICKS, ec->rx_coalesce_usecs);
7866 tw32(HOSTCC_RXMAX_FRAMES, ec->rx_max_coalesced_frames);
7867 tw32(HOSTCC_RXCOAL_MAXF_INT, ec->rx_max_coalesced_frames_irq);
7869 tw32(HOSTCC_RXCOL_TICKS, 0);
7870 tw32(HOSTCC_RXMAX_FRAMES, 0);
7871 tw32(HOSTCC_RXCOAL_MAXF_INT, 0);
7874 if (!tg3_flag(tp, 5705_PLUS)) {
7875 u32 val = ec->stats_block_coalesce_usecs;
7877 tw32(HOSTCC_RXCOAL_TICK_INT, ec->rx_coalesce_usecs_irq);
7878 tw32(HOSTCC_TXCOAL_TICK_INT, ec->tx_coalesce_usecs_irq);
7880 if (!netif_carrier_ok(tp->dev))
7883 tw32(HOSTCC_STAT_COAL_TICKS, val);
7886 for (i = 0; i < tp->irq_cnt - 1; i++) {
7889 reg = HOSTCC_RXCOL_TICKS_VEC1 + i * 0x18;
7890 tw32(reg, ec->rx_coalesce_usecs);
7891 reg = HOSTCC_RXMAX_FRAMES_VEC1 + i * 0x18;
7892 tw32(reg, ec->rx_max_coalesced_frames);
7893 reg = HOSTCC_RXCOAL_MAXF_INT_VEC1 + i * 0x18;
7894 tw32(reg, ec->rx_max_coalesced_frames_irq);
7896 if (tg3_flag(tp, ENABLE_TSS)) {
7897 reg = HOSTCC_TXCOL_TICKS_VEC1 + i * 0x18;
7898 tw32(reg, ec->tx_coalesce_usecs);
7899 reg = HOSTCC_TXMAX_FRAMES_VEC1 + i * 0x18;
7900 tw32(reg, ec->tx_max_coalesced_frames);
7901 reg = HOSTCC_TXCOAL_MAXF_INT_VEC1 + i * 0x18;
7902 tw32(reg, ec->tx_max_coalesced_frames_irq);
7906 for (; i < tp->irq_max - 1; i++) {
7907 tw32(HOSTCC_RXCOL_TICKS_VEC1 + i * 0x18, 0);
7908 tw32(HOSTCC_RXMAX_FRAMES_VEC1 + i * 0x18, 0);
7909 tw32(HOSTCC_RXCOAL_MAXF_INT_VEC1 + i * 0x18, 0);
7911 if (tg3_flag(tp, ENABLE_TSS)) {
7912 tw32(HOSTCC_TXCOL_TICKS_VEC1 + i * 0x18, 0);
7913 tw32(HOSTCC_TXMAX_FRAMES_VEC1 + i * 0x18, 0);
7914 tw32(HOSTCC_TXCOAL_MAXF_INT_VEC1 + i * 0x18, 0);
7919 /* tp->lock is held. */
7920 static void tg3_rings_reset(struct tg3 *tp)
7923 u32 stblk, txrcb, rxrcb, limit;
7924 struct tg3_napi *tnapi = &tp->napi[0];
7926 /* Disable all transmit rings but the first. */
7927 if (!tg3_flag(tp, 5705_PLUS))
7928 limit = NIC_SRAM_SEND_RCB + TG3_BDINFO_SIZE * 16;
7929 else if (tg3_flag(tp, 5717_PLUS))
7930 limit = NIC_SRAM_SEND_RCB + TG3_BDINFO_SIZE * 4;
7931 else if (tg3_flag(tp, 57765_CLASS))
7932 limit = NIC_SRAM_SEND_RCB + TG3_BDINFO_SIZE * 2;
7934 limit = NIC_SRAM_SEND_RCB + TG3_BDINFO_SIZE;
7936 for (txrcb = NIC_SRAM_SEND_RCB + TG3_BDINFO_SIZE;
7937 txrcb < limit; txrcb += TG3_BDINFO_SIZE)
7938 tg3_write_mem(tp, txrcb + TG3_BDINFO_MAXLEN_FLAGS,
7939 BDINFO_FLAGS_DISABLED);
7942 /* Disable all receive return rings but the first. */
7943 if (tg3_flag(tp, 5717_PLUS))
7944 limit = NIC_SRAM_RCV_RET_RCB + TG3_BDINFO_SIZE * 17;
7945 else if (!tg3_flag(tp, 5705_PLUS))
7946 limit = NIC_SRAM_RCV_RET_RCB + TG3_BDINFO_SIZE * 16;
7947 else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5755 ||
7948 tg3_flag(tp, 57765_CLASS))
7949 limit = NIC_SRAM_RCV_RET_RCB + TG3_BDINFO_SIZE * 4;
7951 limit = NIC_SRAM_RCV_RET_RCB + TG3_BDINFO_SIZE;
7953 for (rxrcb = NIC_SRAM_RCV_RET_RCB + TG3_BDINFO_SIZE;
7954 rxrcb < limit; rxrcb += TG3_BDINFO_SIZE)
7955 tg3_write_mem(tp, rxrcb + TG3_BDINFO_MAXLEN_FLAGS,
7956 BDINFO_FLAGS_DISABLED);
7958 /* Disable interrupts */
7959 tw32_mailbox_f(tp->napi[0].int_mbox, 1);
7960 tp->napi[0].chk_msi_cnt = 0;
7961 tp->napi[0].last_rx_cons = 0;
7962 tp->napi[0].last_tx_cons = 0;
7964 /* Zero mailbox registers. */
7965 if (tg3_flag(tp, SUPPORT_MSIX)) {
7966 for (i = 1; i < tp->irq_max; i++) {
7967 tp->napi[i].tx_prod = 0;
7968 tp->napi[i].tx_cons = 0;
7969 if (tg3_flag(tp, ENABLE_TSS))
7970 tw32_mailbox(tp->napi[i].prodmbox, 0);
7971 tw32_rx_mbox(tp->napi[i].consmbox, 0);
7972 tw32_mailbox_f(tp->napi[i].int_mbox, 1);
7973 tp->napi[i].chk_msi_cnt = 0;
7974 tp->napi[i].last_rx_cons = 0;
7975 tp->napi[i].last_tx_cons = 0;
7977 if (!tg3_flag(tp, ENABLE_TSS))
7978 tw32_mailbox(tp->napi[0].prodmbox, 0);
7980 tp->napi[0].tx_prod = 0;
7981 tp->napi[0].tx_cons = 0;
7982 tw32_mailbox(tp->napi[0].prodmbox, 0);
7983 tw32_rx_mbox(tp->napi[0].consmbox, 0);
7986 /* Make sure the NIC-based send BD rings are disabled. */
7987 if (!tg3_flag(tp, 5705_PLUS)) {
7988 u32 mbox = MAILBOX_SNDNIC_PROD_IDX_0 + TG3_64BIT_REG_LOW;
7989 for (i = 0; i < 16; i++)
7990 tw32_tx_mbox(mbox + i * 8, 0);
7993 txrcb = NIC_SRAM_SEND_RCB;
7994 rxrcb = NIC_SRAM_RCV_RET_RCB;
7996 /* Clear status block in ram. */
7997 memset(tnapi->hw_status, 0, TG3_HW_STATUS_SIZE);
7999 /* Set status block DMA address */
8000 tw32(HOSTCC_STATUS_BLK_HOST_ADDR + TG3_64BIT_REG_HIGH,
8001 ((u64) tnapi->status_mapping >> 32));
8002 tw32(HOSTCC_STATUS_BLK_HOST_ADDR + TG3_64BIT_REG_LOW,
8003 ((u64) tnapi->status_mapping & 0xffffffff));
8005 if (tnapi->tx_ring) {
8006 tg3_set_bdinfo(tp, txrcb, tnapi->tx_desc_mapping,
8007 (TG3_TX_RING_SIZE <<
8008 BDINFO_FLAGS_MAXLEN_SHIFT),
8009 NIC_SRAM_TX_BUFFER_DESC);
8010 txrcb += TG3_BDINFO_SIZE;
8013 if (tnapi->rx_rcb) {
8014 tg3_set_bdinfo(tp, rxrcb, tnapi->rx_rcb_mapping,
8015 (tp->rx_ret_ring_mask + 1) <<
8016 BDINFO_FLAGS_MAXLEN_SHIFT, 0);
8017 rxrcb += TG3_BDINFO_SIZE;
8020 stblk = HOSTCC_STATBLCK_RING1;
8022 for (i = 1, tnapi++; i < tp->irq_cnt; i++, tnapi++) {
8023 u64 mapping = (u64)tnapi->status_mapping;
8024 tw32(stblk + TG3_64BIT_REG_HIGH, mapping >> 32);
8025 tw32(stblk + TG3_64BIT_REG_LOW, mapping & 0xffffffff);
8027 /* Clear status block in ram. */
8028 memset(tnapi->hw_status, 0, TG3_HW_STATUS_SIZE);
8030 if (tnapi->tx_ring) {
8031 tg3_set_bdinfo(tp, txrcb, tnapi->tx_desc_mapping,
8032 (TG3_TX_RING_SIZE <<
8033 BDINFO_FLAGS_MAXLEN_SHIFT),
8034 NIC_SRAM_TX_BUFFER_DESC);
8035 txrcb += TG3_BDINFO_SIZE;
8038 tg3_set_bdinfo(tp, rxrcb, tnapi->rx_rcb_mapping,
8039 ((tp->rx_ret_ring_mask + 1) <<
8040 BDINFO_FLAGS_MAXLEN_SHIFT), 0);
8043 rxrcb += TG3_BDINFO_SIZE;
8047 static void tg3_setup_rxbd_thresholds(struct tg3 *tp)
8049 u32 val, bdcache_maxcnt, host_rep_thresh, nic_rep_thresh;
8051 if (!tg3_flag(tp, 5750_PLUS) ||
8052 tg3_flag(tp, 5780_CLASS) ||
8053 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5750 ||
8054 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5752 ||
8055 tg3_flag(tp, 57765_PLUS))
8056 bdcache_maxcnt = TG3_SRAM_RX_STD_BDCACHE_SIZE_5700;
8057 else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5755 ||
8058 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5787)
8059 bdcache_maxcnt = TG3_SRAM_RX_STD_BDCACHE_SIZE_5755;
8061 bdcache_maxcnt = TG3_SRAM_RX_STD_BDCACHE_SIZE_5906;
8063 nic_rep_thresh = min(bdcache_maxcnt / 2, tp->rx_std_max_post);
8064 host_rep_thresh = max_t(u32, tp->rx_pending / 8, 1);
8066 val = min(nic_rep_thresh, host_rep_thresh);
8067 tw32(RCVBDI_STD_THRESH, val);
8069 if (tg3_flag(tp, 57765_PLUS))
8070 tw32(STD_REPLENISH_LWM, bdcache_maxcnt);
8072 if (!tg3_flag(tp, JUMBO_CAPABLE) || tg3_flag(tp, 5780_CLASS))
8075 bdcache_maxcnt = TG3_SRAM_RX_JMB_BDCACHE_SIZE_5700;
8077 host_rep_thresh = max_t(u32, tp->rx_jumbo_pending / 8, 1);
8079 val = min(bdcache_maxcnt / 2, host_rep_thresh);
8080 tw32(RCVBDI_JUMBO_THRESH, val);
8082 if (tg3_flag(tp, 57765_PLUS))
8083 tw32(JMB_REPLENISH_LWM, bdcache_maxcnt);
8086 static inline u32 calc_crc(unsigned char *buf, int len)
8094 for (j = 0; j < len; j++) {
8097 for (k = 0; k < 8; k++) {
8110 static void tg3_set_multi(struct tg3 *tp, unsigned int accept_all)
8112 /* accept or reject all multicast frames */
8113 tw32(MAC_HASH_REG_0, accept_all ? 0xffffffff : 0);
8114 tw32(MAC_HASH_REG_1, accept_all ? 0xffffffff : 0);
8115 tw32(MAC_HASH_REG_2, accept_all ? 0xffffffff : 0);
8116 tw32(MAC_HASH_REG_3, accept_all ? 0xffffffff : 0);
8119 static void __tg3_set_rx_mode(struct net_device *dev)
8121 struct tg3 *tp = netdev_priv(dev);
8124 rx_mode = tp->rx_mode & ~(RX_MODE_PROMISC |
8125 RX_MODE_KEEP_VLAN_TAG);
8127 #if !defined(CONFIG_VLAN_8021Q) && !defined(CONFIG_VLAN_8021Q_MODULE)
8128 /* When ASF is in use, we always keep the RX_MODE_KEEP_VLAN_TAG
8131 if (!tg3_flag(tp, ENABLE_ASF))
8132 rx_mode |= RX_MODE_KEEP_VLAN_TAG;
8135 if (dev->flags & IFF_PROMISC) {
8136 /* Promiscuous mode. */
8137 rx_mode |= RX_MODE_PROMISC;
8138 } else if (dev->flags & IFF_ALLMULTI) {
8139 /* Accept all multicast. */
8140 tg3_set_multi(tp, 1);
8141 } else if (netdev_mc_empty(dev)) {
8142 /* Reject all multicast. */
8143 tg3_set_multi(tp, 0);
8145 /* Accept one or more multicast(s). */
8146 struct netdev_hw_addr *ha;
8147 u32 mc_filter[4] = { 0, };
8152 netdev_for_each_mc_addr(ha, dev) {
8153 crc = calc_crc(ha->addr, ETH_ALEN);
8155 regidx = (bit & 0x60) >> 5;
8157 mc_filter[regidx] |= (1 << bit);
8160 tw32(MAC_HASH_REG_0, mc_filter[0]);
8161 tw32(MAC_HASH_REG_1, mc_filter[1]);
8162 tw32(MAC_HASH_REG_2, mc_filter[2]);
8163 tw32(MAC_HASH_REG_3, mc_filter[3]);
8166 if (rx_mode != tp->rx_mode) {
8167 tp->rx_mode = rx_mode;
8168 tw32_f(MAC_RX_MODE, rx_mode);
8173 static void tg3_rss_init_dflt_indir_tbl(struct tg3 *tp)
8177 for (i = 0; i < TG3_RSS_INDIR_TBL_SIZE; i++)
8178 tp->rss_ind_tbl[i] =
8179 ethtool_rxfh_indir_default(i, tp->irq_cnt - 1);
8182 static void tg3_rss_check_indir_tbl(struct tg3 *tp)
8186 if (!tg3_flag(tp, SUPPORT_MSIX))
8189 if (tp->irq_cnt <= 2) {
8190 memset(&tp->rss_ind_tbl[0], 0, sizeof(tp->rss_ind_tbl));
8194 /* Validate table against current IRQ count */
8195 for (i = 0; i < TG3_RSS_INDIR_TBL_SIZE; i++) {
8196 if (tp->rss_ind_tbl[i] >= tp->irq_cnt - 1)
8200 if (i != TG3_RSS_INDIR_TBL_SIZE)
8201 tg3_rss_init_dflt_indir_tbl(tp);
8204 static void tg3_rss_write_indir_tbl(struct tg3 *tp)
8207 u32 reg = MAC_RSS_INDIR_TBL_0;
8209 while (i < TG3_RSS_INDIR_TBL_SIZE) {
8210 u32 val = tp->rss_ind_tbl[i];
8212 for (; i % 8; i++) {
8214 val |= tp->rss_ind_tbl[i];
8221 /* tp->lock is held. */
8222 static int tg3_reset_hw(struct tg3 *tp, int reset_phy)
8224 u32 val, rdmac_mode;
8226 struct tg3_rx_prodring_set *tpr = &tp->napi[0].prodring;
8228 tg3_disable_ints(tp);
8232 tg3_write_sig_pre_reset(tp, RESET_KIND_INIT);
8234 if (tg3_flag(tp, INIT_COMPLETE))
8235 tg3_abort_hw(tp, 1);
8237 /* Enable MAC control of LPI */
8238 if (tp->phy_flags & TG3_PHYFLG_EEE_CAP) {
8239 tw32_f(TG3_CPMU_EEE_LNKIDL_CTRL,
8240 TG3_CPMU_EEE_LNKIDL_PCIE_NL0 |
8241 TG3_CPMU_EEE_LNKIDL_UART_IDL);
8243 tw32_f(TG3_CPMU_EEE_CTRL,
8244 TG3_CPMU_EEE_CTRL_EXIT_20_1_US);
8246 val = TG3_CPMU_EEEMD_ERLY_L1_XIT_DET |
8247 TG3_CPMU_EEEMD_LPI_IN_TX |
8248 TG3_CPMU_EEEMD_LPI_IN_RX |
8249 TG3_CPMU_EEEMD_EEE_ENABLE;
8251 if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5717)
8252 val |= TG3_CPMU_EEEMD_SND_IDX_DET_EN;
8254 if (tg3_flag(tp, ENABLE_APE))
8255 val |= TG3_CPMU_EEEMD_APE_TX_DET_EN;
8257 tw32_f(TG3_CPMU_EEE_MODE, val);
8259 tw32_f(TG3_CPMU_EEE_DBTMR1,
8260 TG3_CPMU_DBTMR1_PCIEXIT_2047US |
8261 TG3_CPMU_DBTMR1_LNKIDLE_2047US);
8263 tw32_f(TG3_CPMU_EEE_DBTMR2,
8264 TG3_CPMU_DBTMR2_APE_TX_2047US |
8265 TG3_CPMU_DBTMR2_TXIDXEQ_2047US);
8271 err = tg3_chip_reset(tp);
8275 tg3_write_sig_legacy(tp, RESET_KIND_INIT);
8277 if (GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5784_AX) {
8278 val = tr32(TG3_CPMU_CTRL);
8279 val &= ~(CPMU_CTRL_LINK_AWARE_MODE | CPMU_CTRL_LINK_IDLE_MODE);
8280 tw32(TG3_CPMU_CTRL, val);
8282 val = tr32(TG3_CPMU_LSPD_10MB_CLK);
8283 val &= ~CPMU_LSPD_10MB_MACCLK_MASK;
8284 val |= CPMU_LSPD_10MB_MACCLK_6_25;
8285 tw32(TG3_CPMU_LSPD_10MB_CLK, val);
8287 val = tr32(TG3_CPMU_LNK_AWARE_PWRMD);
8288 val &= ~CPMU_LNK_AWARE_MACCLK_MASK;
8289 val |= CPMU_LNK_AWARE_MACCLK_6_25;
8290 tw32(TG3_CPMU_LNK_AWARE_PWRMD, val);
8292 val = tr32(TG3_CPMU_HST_ACC);
8293 val &= ~CPMU_HST_ACC_MACCLK_MASK;
8294 val |= CPMU_HST_ACC_MACCLK_6_25;
8295 tw32(TG3_CPMU_HST_ACC, val);
8298 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57780) {
8299 val = tr32(PCIE_PWR_MGMT_THRESH) & ~PCIE_PWR_MGMT_L1_THRESH_MSK;
8300 val |= PCIE_PWR_MGMT_EXT_ASPM_TMR_EN |
8301 PCIE_PWR_MGMT_L1_THRESH_4MS;
8302 tw32(PCIE_PWR_MGMT_THRESH, val);
8304 val = tr32(TG3_PCIE_EIDLE_DELAY) & ~TG3_PCIE_EIDLE_DELAY_MASK;
8305 tw32(TG3_PCIE_EIDLE_DELAY, val | TG3_PCIE_EIDLE_DELAY_13_CLKS);
8307 tw32(TG3_CORR_ERR_STAT, TG3_CORR_ERR_STAT_CLEAR);
8309 val = tr32(TG3_PCIE_LNKCTL) & ~TG3_PCIE_LNKCTL_L1_PLL_PD_EN;
8310 tw32(TG3_PCIE_LNKCTL, val | TG3_PCIE_LNKCTL_L1_PLL_PD_DIS);
8313 if (tg3_flag(tp, L1PLLPD_EN)) {
8314 u32 grc_mode = tr32(GRC_MODE);
8316 /* Access the lower 1K of PL PCIE block registers. */
8317 val = grc_mode & ~GRC_MODE_PCIE_PORT_MASK;
8318 tw32(GRC_MODE, val | GRC_MODE_PCIE_PL_SEL);
8320 val = tr32(TG3_PCIE_TLDLPL_PORT + TG3_PCIE_PL_LO_PHYCTL1);
8321 tw32(TG3_PCIE_TLDLPL_PORT + TG3_PCIE_PL_LO_PHYCTL1,
8322 val | TG3_PCIE_PL_LO_PHYCTL1_L1PLLPD_EN);
8324 tw32(GRC_MODE, grc_mode);
8327 if (tg3_flag(tp, 57765_CLASS)) {
8328 if (tp->pci_chip_rev_id == CHIPREV_ID_57765_A0) {
8329 u32 grc_mode = tr32(GRC_MODE);
8331 /* Access the lower 1K of PL PCIE block registers. */
8332 val = grc_mode & ~GRC_MODE_PCIE_PORT_MASK;
8333 tw32(GRC_MODE, val | GRC_MODE_PCIE_PL_SEL);
8335 val = tr32(TG3_PCIE_TLDLPL_PORT +
8336 TG3_PCIE_PL_LO_PHYCTL5);
8337 tw32(TG3_PCIE_TLDLPL_PORT + TG3_PCIE_PL_LO_PHYCTL5,
8338 val | TG3_PCIE_PL_LO_PHYCTL5_DIS_L2CLKREQ);
8340 tw32(GRC_MODE, grc_mode);
8343 if (GET_CHIP_REV(tp->pci_chip_rev_id) != CHIPREV_57765_AX) {
8344 u32 grc_mode = tr32(GRC_MODE);
8346 /* Access the lower 1K of DL PCIE block registers. */
8347 val = grc_mode & ~GRC_MODE_PCIE_PORT_MASK;
8348 tw32(GRC_MODE, val | GRC_MODE_PCIE_DL_SEL);
8350 val = tr32(TG3_PCIE_TLDLPL_PORT +
8351 TG3_PCIE_DL_LO_FTSMAX);
8352 val &= ~TG3_PCIE_DL_LO_FTSMAX_MSK;
8353 tw32(TG3_PCIE_TLDLPL_PORT + TG3_PCIE_DL_LO_FTSMAX,
8354 val | TG3_PCIE_DL_LO_FTSMAX_VAL);
8356 tw32(GRC_MODE, grc_mode);
8359 val = tr32(TG3_CPMU_LSPD_10MB_CLK);
8360 val &= ~CPMU_LSPD_10MB_MACCLK_MASK;
8361 val |= CPMU_LSPD_10MB_MACCLK_6_25;
8362 tw32(TG3_CPMU_LSPD_10MB_CLK, val);
8365 /* This works around an issue with Athlon chipsets on
8366 * B3 tigon3 silicon. This bit has no effect on any
8367 * other revision. But do not set this on PCI Express
8368 * chips and don't even touch the clocks if the CPMU is present.
8370 if (!tg3_flag(tp, CPMU_PRESENT)) {
8371 if (!tg3_flag(tp, PCI_EXPRESS))
8372 tp->pci_clock_ctrl |= CLOCK_CTRL_DELAY_PCI_GRANT;
8373 tw32_f(TG3PCI_CLOCK_CTRL, tp->pci_clock_ctrl);
8376 if (tp->pci_chip_rev_id == CHIPREV_ID_5704_A0 &&
8377 tg3_flag(tp, PCIX_MODE)) {
8378 val = tr32(TG3PCI_PCISTATE);
8379 val |= PCISTATE_RETRY_SAME_DMA;
8380 tw32(TG3PCI_PCISTATE, val);
8383 if (tg3_flag(tp, ENABLE_APE)) {
8384 /* Allow reads and writes to the
8385 * APE register and memory space.
8387 val = tr32(TG3PCI_PCISTATE);
8388 val |= PCISTATE_ALLOW_APE_CTLSPC_WR |
8389 PCISTATE_ALLOW_APE_SHMEM_WR |
8390 PCISTATE_ALLOW_APE_PSPACE_WR;
8391 tw32(TG3PCI_PCISTATE, val);
8394 if (GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5704_BX) {
8395 /* Enable some hw fixes. */
8396 val = tr32(TG3PCI_MSI_DATA);
8397 val |= (1 << 26) | (1 << 28) | (1 << 29);
8398 tw32(TG3PCI_MSI_DATA, val);
8401 /* Descriptor ring init may make accesses to the
8402 * NIC SRAM area to setup the TX descriptors, so we
8403 * can only do this after the hardware has been
8404 * successfully reset.
8406 err = tg3_init_rings(tp);
8410 if (tg3_flag(tp, 57765_PLUS)) {
8411 val = tr32(TG3PCI_DMA_RW_CTRL) &
8412 ~DMA_RWCTRL_DIS_CACHE_ALIGNMENT;
8413 if (tp->pci_chip_rev_id == CHIPREV_ID_57765_A0)
8414 val &= ~DMA_RWCTRL_CRDRDR_RDMA_MRRS_MSK;
8415 if (!tg3_flag(tp, 57765_CLASS) &&
8416 GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5717)
8417 val |= DMA_RWCTRL_TAGGED_STAT_WA;
8418 tw32(TG3PCI_DMA_RW_CTRL, val | tp->dma_rwctrl);
8419 } else if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5784 &&
8420 GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5761) {
8421 /* This value is determined during the probe time DMA
8422 * engine test, tg3_test_dma.
8424 tw32(TG3PCI_DMA_RW_CTRL, tp->dma_rwctrl);
8427 tp->grc_mode &= ~(GRC_MODE_HOST_SENDBDS |
8428 GRC_MODE_4X_NIC_SEND_RINGS |
8429 GRC_MODE_NO_TX_PHDR_CSUM |
8430 GRC_MODE_NO_RX_PHDR_CSUM);
8431 tp->grc_mode |= GRC_MODE_HOST_SENDBDS;
8433 /* Pseudo-header checksum is done by hardware logic and not
8434 * the offload processers, so make the chip do the pseudo-
8435 * header checksums on receive. For transmit it is more
8436 * convenient to do the pseudo-header checksum in software
8437 * as Linux does that on transmit for us in all cases.
8439 tp->grc_mode |= GRC_MODE_NO_TX_PHDR_CSUM;
8443 (GRC_MODE_IRQ_ON_MAC_ATTN | GRC_MODE_HOST_STACKUP));
8445 /* Setup the timer prescalar register. Clock is always 66Mhz. */
8446 val = tr32(GRC_MISC_CFG);
8448 val |= (65 << GRC_MISC_CFG_PRESCALAR_SHIFT);
8449 tw32(GRC_MISC_CFG, val);
8451 /* Initialize MBUF/DESC pool. */
8452 if (tg3_flag(tp, 5750_PLUS)) {
8454 } else if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5705) {
8455 tw32(BUFMGR_MB_POOL_ADDR, NIC_SRAM_MBUF_POOL_BASE);
8456 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704)
8457 tw32(BUFMGR_MB_POOL_SIZE, NIC_SRAM_MBUF_POOL_SIZE64);
8459 tw32(BUFMGR_MB_POOL_SIZE, NIC_SRAM_MBUF_POOL_SIZE96);
8460 tw32(BUFMGR_DMA_DESC_POOL_ADDR, NIC_SRAM_DMA_DESC_POOL_BASE);
8461 tw32(BUFMGR_DMA_DESC_POOL_SIZE, NIC_SRAM_DMA_DESC_POOL_SIZE);
8462 } else if (tg3_flag(tp, TSO_CAPABLE)) {
8465 fw_len = tp->fw_len;
8466 fw_len = (fw_len + (0x80 - 1)) & ~(0x80 - 1);
8467 tw32(BUFMGR_MB_POOL_ADDR,
8468 NIC_SRAM_MBUF_POOL_BASE5705 + fw_len);
8469 tw32(BUFMGR_MB_POOL_SIZE,
8470 NIC_SRAM_MBUF_POOL_SIZE5705 - fw_len - 0xa00);
8473 if (tp->dev->mtu <= ETH_DATA_LEN) {
8474 tw32(BUFMGR_MB_RDMA_LOW_WATER,
8475 tp->bufmgr_config.mbuf_read_dma_low_water);
8476 tw32(BUFMGR_MB_MACRX_LOW_WATER,
8477 tp->bufmgr_config.mbuf_mac_rx_low_water);
8478 tw32(BUFMGR_MB_HIGH_WATER,
8479 tp->bufmgr_config.mbuf_high_water);
8481 tw32(BUFMGR_MB_RDMA_LOW_WATER,
8482 tp->bufmgr_config.mbuf_read_dma_low_water_jumbo);
8483 tw32(BUFMGR_MB_MACRX_LOW_WATER,
8484 tp->bufmgr_config.mbuf_mac_rx_low_water_jumbo);
8485 tw32(BUFMGR_MB_HIGH_WATER,
8486 tp->bufmgr_config.mbuf_high_water_jumbo);
8488 tw32(BUFMGR_DMA_LOW_WATER,
8489 tp->bufmgr_config.dma_low_water);
8490 tw32(BUFMGR_DMA_HIGH_WATER,
8491 tp->bufmgr_config.dma_high_water);
8493 val = BUFMGR_MODE_ENABLE | BUFMGR_MODE_ATTN_ENABLE;
8494 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5719)
8495 val |= BUFMGR_MODE_NO_TX_UNDERRUN;
8496 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717 ||
8497 tp->pci_chip_rev_id == CHIPREV_ID_5719_A0 ||
8498 tp->pci_chip_rev_id == CHIPREV_ID_5720_A0)
8499 val |= BUFMGR_MODE_MBLOW_ATTN_ENAB;
8500 tw32(BUFMGR_MODE, val);
8501 for (i = 0; i < 2000; i++) {
8502 if (tr32(BUFMGR_MODE) & BUFMGR_MODE_ENABLE)
8507 netdev_err(tp->dev, "%s cannot enable BUFMGR\n", __func__);
8511 if (tp->pci_chip_rev_id == CHIPREV_ID_5906_A1)
8512 tw32(ISO_PKT_TX, (tr32(ISO_PKT_TX) & ~0x3) | 0x2);
8514 tg3_setup_rxbd_thresholds(tp);
8516 /* Initialize TG3_BDINFO's at:
8517 * RCVDBDI_STD_BD: standard eth size rx ring
8518 * RCVDBDI_JUMBO_BD: jumbo frame rx ring
8519 * RCVDBDI_MINI_BD: small frame rx ring (??? does not work)
8522 * TG3_BDINFO_HOST_ADDR: high/low parts of DMA address of ring
8523 * TG3_BDINFO_MAXLEN_FLAGS: (rx max buffer size << 16) |
8524 * ring attribute flags
8525 * TG3_BDINFO_NIC_ADDR: location of descriptors in nic SRAM
8527 * Standard receive ring @ NIC_SRAM_RX_BUFFER_DESC, 512 entries.
8528 * Jumbo receive ring @ NIC_SRAM_RX_JUMBO_BUFFER_DESC, 256 entries.
8530 * The size of each ring is fixed in the firmware, but the location is
8533 tw32(RCVDBDI_STD_BD + TG3_BDINFO_HOST_ADDR + TG3_64BIT_REG_HIGH,
8534 ((u64) tpr->rx_std_mapping >> 32));
8535 tw32(RCVDBDI_STD_BD + TG3_BDINFO_HOST_ADDR + TG3_64BIT_REG_LOW,
8536 ((u64) tpr->rx_std_mapping & 0xffffffff));
8537 if (!tg3_flag(tp, 5717_PLUS))
8538 tw32(RCVDBDI_STD_BD + TG3_BDINFO_NIC_ADDR,
8539 NIC_SRAM_RX_BUFFER_DESC);
8541 /* Disable the mini ring */
8542 if (!tg3_flag(tp, 5705_PLUS))
8543 tw32(RCVDBDI_MINI_BD + TG3_BDINFO_MAXLEN_FLAGS,
8544 BDINFO_FLAGS_DISABLED);
8546 /* Program the jumbo buffer descriptor ring control
8547 * blocks on those devices that have them.
8549 if (tp->pci_chip_rev_id == CHIPREV_ID_5719_A0 ||
8550 (tg3_flag(tp, JUMBO_CAPABLE) && !tg3_flag(tp, 5780_CLASS))) {
8552 if (tg3_flag(tp, JUMBO_RING_ENABLE)) {
8553 tw32(RCVDBDI_JUMBO_BD + TG3_BDINFO_HOST_ADDR + TG3_64BIT_REG_HIGH,
8554 ((u64) tpr->rx_jmb_mapping >> 32));
8555 tw32(RCVDBDI_JUMBO_BD + TG3_BDINFO_HOST_ADDR + TG3_64BIT_REG_LOW,
8556 ((u64) tpr->rx_jmb_mapping & 0xffffffff));
8557 val = TG3_RX_JMB_RING_SIZE(tp) <<
8558 BDINFO_FLAGS_MAXLEN_SHIFT;
8559 tw32(RCVDBDI_JUMBO_BD + TG3_BDINFO_MAXLEN_FLAGS,
8560 val | BDINFO_FLAGS_USE_EXT_RECV);
8561 if (!tg3_flag(tp, USE_JUMBO_BDFLAG) ||
8562 tg3_flag(tp, 57765_CLASS))
8563 tw32(RCVDBDI_JUMBO_BD + TG3_BDINFO_NIC_ADDR,
8564 NIC_SRAM_RX_JUMBO_BUFFER_DESC);
8566 tw32(RCVDBDI_JUMBO_BD + TG3_BDINFO_MAXLEN_FLAGS,
8567 BDINFO_FLAGS_DISABLED);
8570 if (tg3_flag(tp, 57765_PLUS)) {
8571 val = TG3_RX_STD_RING_SIZE(tp);
8572 val <<= BDINFO_FLAGS_MAXLEN_SHIFT;
8573 val |= (TG3_RX_STD_DMA_SZ << 2);
8575 val = TG3_RX_STD_DMA_SZ << BDINFO_FLAGS_MAXLEN_SHIFT;
8577 val = TG3_RX_STD_MAX_SIZE_5700 << BDINFO_FLAGS_MAXLEN_SHIFT;
8579 tw32(RCVDBDI_STD_BD + TG3_BDINFO_MAXLEN_FLAGS, val);
8581 tpr->rx_std_prod_idx = tp->rx_pending;
8582 tw32_rx_mbox(TG3_RX_STD_PROD_IDX_REG, tpr->rx_std_prod_idx);
8584 tpr->rx_jmb_prod_idx =
8585 tg3_flag(tp, JUMBO_RING_ENABLE) ? tp->rx_jumbo_pending : 0;
8586 tw32_rx_mbox(TG3_RX_JMB_PROD_IDX_REG, tpr->rx_jmb_prod_idx);
8588 tg3_rings_reset(tp);
8590 /* Initialize MAC address and backoff seed. */
8591 __tg3_set_mac_addr(tp, 0);
8593 /* MTU + ethernet header + FCS + optional VLAN tag */
8594 tw32(MAC_RX_MTU_SIZE,
8595 tp->dev->mtu + ETH_HLEN + ETH_FCS_LEN + VLAN_HLEN);
8597 /* The slot time is changed by tg3_setup_phy if we
8598 * run at gigabit with half duplex.
8600 val = (2 << TX_LENGTHS_IPG_CRS_SHIFT) |
8601 (6 << TX_LENGTHS_IPG_SHIFT) |
8602 (32 << TX_LENGTHS_SLOT_TIME_SHIFT);
8604 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5720)
8605 val |= tr32(MAC_TX_LENGTHS) &
8606 (TX_LENGTHS_JMB_FRM_LEN_MSK |
8607 TX_LENGTHS_CNT_DWN_VAL_MSK);
8609 tw32(MAC_TX_LENGTHS, val);
8611 /* Receive rules. */
8612 tw32(MAC_RCV_RULE_CFG, RCV_RULE_CFG_DEFAULT_CLASS);
8613 tw32(RCVLPC_CONFIG, 0x0181);
8615 /* Calculate RDMAC_MODE setting early, we need it to determine
8616 * the RCVLPC_STATE_ENABLE mask.
8618 rdmac_mode = (RDMAC_MODE_ENABLE | RDMAC_MODE_TGTABORT_ENAB |
8619 RDMAC_MODE_MSTABORT_ENAB | RDMAC_MODE_PARITYERR_ENAB |
8620 RDMAC_MODE_ADDROFLOW_ENAB | RDMAC_MODE_FIFOOFLOW_ENAB |
8621 RDMAC_MODE_FIFOURUN_ENAB | RDMAC_MODE_FIFOOREAD_ENAB |
8622 RDMAC_MODE_LNGREAD_ENAB);
8624 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717)
8625 rdmac_mode |= RDMAC_MODE_MULT_DMA_RD_DIS;
8627 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5784 ||
8628 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785 ||
8629 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57780)
8630 rdmac_mode |= RDMAC_MODE_BD_SBD_CRPT_ENAB |
8631 RDMAC_MODE_MBUF_RBD_CRPT_ENAB |
8632 RDMAC_MODE_MBUF_SBD_CRPT_ENAB;
8634 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705 &&
8635 tp->pci_chip_rev_id != CHIPREV_ID_5705_A0) {
8636 if (tg3_flag(tp, TSO_CAPABLE) &&
8637 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705) {
8638 rdmac_mode |= RDMAC_MODE_FIFO_SIZE_128;
8639 } else if (!(tr32(TG3PCI_PCISTATE) & PCISTATE_BUS_SPEED_HIGH) &&
8640 !tg3_flag(tp, IS_5788)) {
8641 rdmac_mode |= RDMAC_MODE_FIFO_LONG_BURST;
8645 if (tg3_flag(tp, PCI_EXPRESS))
8646 rdmac_mode |= RDMAC_MODE_FIFO_LONG_BURST;
8648 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57766)
8649 rdmac_mode |= RDMAC_MODE_JMB_2K_MMRR;
8651 if (tg3_flag(tp, HW_TSO_1) ||
8652 tg3_flag(tp, HW_TSO_2) ||
8653 tg3_flag(tp, HW_TSO_3))
8654 rdmac_mode |= RDMAC_MODE_IPV4_LSO_EN;
8656 if (tg3_flag(tp, 57765_PLUS) ||
8657 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785 ||
8658 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57780)
8659 rdmac_mode |= RDMAC_MODE_IPV6_LSO_EN;
8661 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5720)
8662 rdmac_mode |= tr32(RDMAC_MODE) & RDMAC_MODE_H2BNC_VLAN_DET;
8664 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5761 ||
8665 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5784 ||
8666 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785 ||
8667 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57780 ||
8668 tg3_flag(tp, 57765_PLUS)) {
8669 val = tr32(TG3_RDMA_RSRVCTRL_REG);
8670 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5719 ||
8671 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5720) {
8672 val &= ~(TG3_RDMA_RSRVCTRL_TXMRGN_MASK |
8673 TG3_RDMA_RSRVCTRL_FIFO_LWM_MASK |
8674 TG3_RDMA_RSRVCTRL_FIFO_HWM_MASK);
8675 val |= TG3_RDMA_RSRVCTRL_TXMRGN_320B |
8676 TG3_RDMA_RSRVCTRL_FIFO_LWM_1_5K |
8677 TG3_RDMA_RSRVCTRL_FIFO_HWM_1_5K;
8679 tw32(TG3_RDMA_RSRVCTRL_REG,
8680 val | TG3_RDMA_RSRVCTRL_FIFO_OFLW_FIX);
8683 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5719 ||
8684 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5720) {
8685 val = tr32(TG3_LSO_RD_DMA_CRPTEN_CTRL);
8686 tw32(TG3_LSO_RD_DMA_CRPTEN_CTRL, val |
8687 TG3_LSO_RD_DMA_CRPTEN_CTRL_BLEN_BD_4K |
8688 TG3_LSO_RD_DMA_CRPTEN_CTRL_BLEN_LSO_4K);
8691 /* Receive/send statistics. */
8692 if (tg3_flag(tp, 5750_PLUS)) {
8693 val = tr32(RCVLPC_STATS_ENABLE);
8694 val &= ~RCVLPC_STATSENAB_DACK_FIX;
8695 tw32(RCVLPC_STATS_ENABLE, val);
8696 } else if ((rdmac_mode & RDMAC_MODE_FIFO_SIZE_128) &&
8697 tg3_flag(tp, TSO_CAPABLE)) {
8698 val = tr32(RCVLPC_STATS_ENABLE);
8699 val &= ~RCVLPC_STATSENAB_LNGBRST_RFIX;
8700 tw32(RCVLPC_STATS_ENABLE, val);
8702 tw32(RCVLPC_STATS_ENABLE, 0xffffff);
8704 tw32(RCVLPC_STATSCTRL, RCVLPC_STATSCTRL_ENABLE);
8705 tw32(SNDDATAI_STATSENAB, 0xffffff);
8706 tw32(SNDDATAI_STATSCTRL,
8707 (SNDDATAI_SCTRL_ENABLE |
8708 SNDDATAI_SCTRL_FASTUPD));
8710 /* Setup host coalescing engine. */
8711 tw32(HOSTCC_MODE, 0);
8712 for (i = 0; i < 2000; i++) {
8713 if (!(tr32(HOSTCC_MODE) & HOSTCC_MODE_ENABLE))
8718 __tg3_set_coalesce(tp, &tp->coal);
8720 if (!tg3_flag(tp, 5705_PLUS)) {
8721 /* Status/statistics block address. See tg3_timer,
8722 * the tg3_periodic_fetch_stats call there, and
8723 * tg3_get_stats to see how this works for 5705/5750 chips.
8725 tw32(HOSTCC_STATS_BLK_HOST_ADDR + TG3_64BIT_REG_HIGH,
8726 ((u64) tp->stats_mapping >> 32));
8727 tw32(HOSTCC_STATS_BLK_HOST_ADDR + TG3_64BIT_REG_LOW,
8728 ((u64) tp->stats_mapping & 0xffffffff));
8729 tw32(HOSTCC_STATS_BLK_NIC_ADDR, NIC_SRAM_STATS_BLK);
8731 tw32(HOSTCC_STATUS_BLK_NIC_ADDR, NIC_SRAM_STATUS_BLK);
8733 /* Clear statistics and status block memory areas */
8734 for (i = NIC_SRAM_STATS_BLK;
8735 i < NIC_SRAM_STATUS_BLK + TG3_HW_STATUS_SIZE;
8737 tg3_write_mem(tp, i, 0);
8742 tw32(HOSTCC_MODE, HOSTCC_MODE_ENABLE | tp->coalesce_mode);
8744 tw32(RCVCC_MODE, RCVCC_MODE_ENABLE | RCVCC_MODE_ATTN_ENABLE);
8745 tw32(RCVLPC_MODE, RCVLPC_MODE_ENABLE);
8746 if (!tg3_flag(tp, 5705_PLUS))
8747 tw32(RCVLSC_MODE, RCVLSC_MODE_ENABLE | RCVLSC_MODE_ATTN_ENABLE);
8749 if (tp->phy_flags & TG3_PHYFLG_MII_SERDES) {
8750 tp->phy_flags &= ~TG3_PHYFLG_PARALLEL_DETECT;
8751 /* reset to prevent losing 1st rx packet intermittently */
8752 tw32_f(MAC_RX_MODE, RX_MODE_RESET);
8756 tp->mac_mode |= MAC_MODE_TXSTAT_ENABLE | MAC_MODE_RXSTAT_ENABLE |
8757 MAC_MODE_TDE_ENABLE | MAC_MODE_RDE_ENABLE |
8758 MAC_MODE_FHDE_ENABLE;
8759 if (tg3_flag(tp, ENABLE_APE))
8760 tp->mac_mode |= MAC_MODE_APE_TX_EN | MAC_MODE_APE_RX_EN;
8761 if (!tg3_flag(tp, 5705_PLUS) &&
8762 !(tp->phy_flags & TG3_PHYFLG_PHY_SERDES) &&
8763 GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5700)
8764 tp->mac_mode |= MAC_MODE_LINK_POLARITY;
8765 tw32_f(MAC_MODE, tp->mac_mode | MAC_MODE_RXSTAT_CLEAR | MAC_MODE_TXSTAT_CLEAR);
8768 /* tp->grc_local_ctrl is partially set up during tg3_get_invariants().
8769 * If TG3_FLAG_IS_NIC is zero, we should read the
8770 * register to preserve the GPIO settings for LOMs. The GPIOs,
8771 * whether used as inputs or outputs, are set by boot code after
8774 if (!tg3_flag(tp, IS_NIC)) {
8777 gpio_mask = GRC_LCLCTRL_GPIO_OE0 | GRC_LCLCTRL_GPIO_OE1 |
8778 GRC_LCLCTRL_GPIO_OE2 | GRC_LCLCTRL_GPIO_OUTPUT0 |
8779 GRC_LCLCTRL_GPIO_OUTPUT1 | GRC_LCLCTRL_GPIO_OUTPUT2;
8781 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5752)
8782 gpio_mask |= GRC_LCLCTRL_GPIO_OE3 |
8783 GRC_LCLCTRL_GPIO_OUTPUT3;
8785 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5755)
8786 gpio_mask |= GRC_LCLCTRL_GPIO_UART_SEL;
8788 tp->grc_local_ctrl &= ~gpio_mask;
8789 tp->grc_local_ctrl |= tr32(GRC_LOCAL_CTRL) & gpio_mask;
8791 /* GPIO1 must be driven high for eeprom write protect */
8792 if (tg3_flag(tp, EEPROM_WRITE_PROT))
8793 tp->grc_local_ctrl |= (GRC_LCLCTRL_GPIO_OE1 |
8794 GRC_LCLCTRL_GPIO_OUTPUT1);
8796 tw32_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl);
8799 if (tg3_flag(tp, USING_MSIX)) {
8800 val = tr32(MSGINT_MODE);
8801 val |= MSGINT_MODE_ENABLE;
8802 if (tp->irq_cnt > 1)
8803 val |= MSGINT_MODE_MULTIVEC_EN;
8804 if (!tg3_flag(tp, 1SHOT_MSI))
8805 val |= MSGINT_MODE_ONE_SHOT_DISABLE;
8806 tw32(MSGINT_MODE, val);
8809 if (!tg3_flag(tp, 5705_PLUS)) {
8810 tw32_f(DMAC_MODE, DMAC_MODE_ENABLE);
8814 val = (WDMAC_MODE_ENABLE | WDMAC_MODE_TGTABORT_ENAB |
8815 WDMAC_MODE_MSTABORT_ENAB | WDMAC_MODE_PARITYERR_ENAB |
8816 WDMAC_MODE_ADDROFLOW_ENAB | WDMAC_MODE_FIFOOFLOW_ENAB |
8817 WDMAC_MODE_FIFOURUN_ENAB | WDMAC_MODE_FIFOOREAD_ENAB |
8818 WDMAC_MODE_LNGREAD_ENAB);
8820 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705 &&
8821 tp->pci_chip_rev_id != CHIPREV_ID_5705_A0) {
8822 if (tg3_flag(tp, TSO_CAPABLE) &&
8823 (tp->pci_chip_rev_id == CHIPREV_ID_5705_A1 ||
8824 tp->pci_chip_rev_id == CHIPREV_ID_5705_A2)) {
8826 } else if (!(tr32(TG3PCI_PCISTATE) & PCISTATE_BUS_SPEED_HIGH) &&
8827 !tg3_flag(tp, IS_5788)) {
8828 val |= WDMAC_MODE_RX_ACCEL;
8832 /* Enable host coalescing bug fix */
8833 if (tg3_flag(tp, 5755_PLUS))
8834 val |= WDMAC_MODE_STATUS_TAG_FIX;
8836 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785)
8837 val |= WDMAC_MODE_BURST_ALL_DATA;
8839 tw32_f(WDMAC_MODE, val);
8842 if (tg3_flag(tp, PCIX_MODE)) {
8845 pci_read_config_word(tp->pdev, tp->pcix_cap + PCI_X_CMD,
8847 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703) {
8848 pcix_cmd &= ~PCI_X_CMD_MAX_READ;
8849 pcix_cmd |= PCI_X_CMD_READ_2K;
8850 } else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704) {
8851 pcix_cmd &= ~(PCI_X_CMD_MAX_SPLIT | PCI_X_CMD_MAX_READ);
8852 pcix_cmd |= PCI_X_CMD_READ_2K;
8854 pci_write_config_word(tp->pdev, tp->pcix_cap + PCI_X_CMD,
8858 tw32_f(RDMAC_MODE, rdmac_mode);
8861 tw32(RCVDCC_MODE, RCVDCC_MODE_ENABLE | RCVDCC_MODE_ATTN_ENABLE);
8862 if (!tg3_flag(tp, 5705_PLUS))
8863 tw32(MBFREE_MODE, MBFREE_MODE_ENABLE);
8865 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5761)
8867 SNDDATAC_MODE_ENABLE | SNDDATAC_MODE_CDELAY);
8869 tw32(SNDDATAC_MODE, SNDDATAC_MODE_ENABLE);
8871 tw32(SNDBDC_MODE, SNDBDC_MODE_ENABLE | SNDBDC_MODE_ATTN_ENABLE);
8872 tw32(RCVBDI_MODE, RCVBDI_MODE_ENABLE | RCVBDI_MODE_RCB_ATTN_ENAB);
8873 val = RCVDBDI_MODE_ENABLE | RCVDBDI_MODE_INV_RING_SZ;
8874 if (tg3_flag(tp, LRG_PROD_RING_CAP))
8875 val |= RCVDBDI_MODE_LRG_RING_SZ;
8876 tw32(RCVDBDI_MODE, val);
8877 tw32(SNDDATAI_MODE, SNDDATAI_MODE_ENABLE);
8878 if (tg3_flag(tp, HW_TSO_1) ||
8879 tg3_flag(tp, HW_TSO_2) ||
8880 tg3_flag(tp, HW_TSO_3))
8881 tw32(SNDDATAI_MODE, SNDDATAI_MODE_ENABLE | 0x8);
8882 val = SNDBDI_MODE_ENABLE | SNDBDI_MODE_ATTN_ENABLE;
8883 if (tg3_flag(tp, ENABLE_TSS))
8884 val |= SNDBDI_MODE_MULTI_TXQ_EN;
8885 tw32(SNDBDI_MODE, val);
8886 tw32(SNDBDS_MODE, SNDBDS_MODE_ENABLE | SNDBDS_MODE_ATTN_ENABLE);
8888 if (tp->pci_chip_rev_id == CHIPREV_ID_5701_A0) {
8889 err = tg3_load_5701_a0_firmware_fix(tp);
8894 if (tg3_flag(tp, TSO_CAPABLE)) {
8895 err = tg3_load_tso_firmware(tp);
8900 tp->tx_mode = TX_MODE_ENABLE;
8902 if (tg3_flag(tp, 5755_PLUS) ||
8903 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906)
8904 tp->tx_mode |= TX_MODE_MBUF_LOCKUP_FIX;
8906 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5720) {
8907 val = TX_MODE_JMB_FRM_LEN | TX_MODE_CNT_DN_MODE;
8908 tp->tx_mode &= ~val;
8909 tp->tx_mode |= tr32(MAC_TX_MODE) & val;
8912 tw32_f(MAC_TX_MODE, tp->tx_mode);
8915 if (tg3_flag(tp, ENABLE_RSS)) {
8916 tg3_rss_write_indir_tbl(tp);
8918 /* Setup the "secret" hash key. */
8919 tw32(MAC_RSS_HASH_KEY_0, 0x5f865437);
8920 tw32(MAC_RSS_HASH_KEY_1, 0xe4ac62cc);
8921 tw32(MAC_RSS_HASH_KEY_2, 0x50103a45);
8922 tw32(MAC_RSS_HASH_KEY_3, 0x36621985);
8923 tw32(MAC_RSS_HASH_KEY_4, 0xbf14c0e8);
8924 tw32(MAC_RSS_HASH_KEY_5, 0x1bc27a1e);
8925 tw32(MAC_RSS_HASH_KEY_6, 0x84f4b556);
8926 tw32(MAC_RSS_HASH_KEY_7, 0x094ea6fe);
8927 tw32(MAC_RSS_HASH_KEY_8, 0x7dda01e7);
8928 tw32(MAC_RSS_HASH_KEY_9, 0xc04d7481);
8931 tp->rx_mode = RX_MODE_ENABLE;
8932 if (tg3_flag(tp, 5755_PLUS))
8933 tp->rx_mode |= RX_MODE_IPV6_CSUM_ENABLE;
8935 if (tg3_flag(tp, ENABLE_RSS))
8936 tp->rx_mode |= RX_MODE_RSS_ENABLE |
8937 RX_MODE_RSS_ITBL_HASH_BITS_7 |
8938 RX_MODE_RSS_IPV6_HASH_EN |
8939 RX_MODE_RSS_TCP_IPV6_HASH_EN |
8940 RX_MODE_RSS_IPV4_HASH_EN |
8941 RX_MODE_RSS_TCP_IPV4_HASH_EN;
8943 tw32_f(MAC_RX_MODE, tp->rx_mode);
8946 tw32(MAC_LED_CTRL, tp->led_ctrl);
8948 tw32(MAC_MI_STAT, MAC_MI_STAT_LNKSTAT_ATTN_ENAB);
8949 if (tp->phy_flags & TG3_PHYFLG_PHY_SERDES) {
8950 tw32_f(MAC_RX_MODE, RX_MODE_RESET);
8953 tw32_f(MAC_RX_MODE, tp->rx_mode);
8956 if (tp->phy_flags & TG3_PHYFLG_PHY_SERDES) {
8957 if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704) &&
8958 !(tp->phy_flags & TG3_PHYFLG_SERDES_PREEMPHASIS)) {
8959 /* Set drive transmission level to 1.2V */
8960 /* only if the signal pre-emphasis bit is not set */
8961 val = tr32(MAC_SERDES_CFG);
8964 tw32(MAC_SERDES_CFG, val);
8966 if (tp->pci_chip_rev_id == CHIPREV_ID_5703_A1)
8967 tw32(MAC_SERDES_CFG, 0x616000);
8970 /* Prevent chip from dropping frames when flow control
8973 if (tg3_flag(tp, 57765_CLASS))
8977 tw32_f(MAC_LOW_WMARK_MAX_RX_FRAME, val);
8979 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704 &&
8980 (tp->phy_flags & TG3_PHYFLG_PHY_SERDES)) {
8981 /* Use hardware link auto-negotiation */
8982 tg3_flag_set(tp, HW_AUTONEG);
8985 if ((tp->phy_flags & TG3_PHYFLG_MII_SERDES) &&
8986 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5714) {
8989 tmp = tr32(SERDES_RX_CTRL);
8990 tw32(SERDES_RX_CTRL, tmp | SERDES_RX_SIG_DETECT);
8991 tp->grc_local_ctrl &= ~GRC_LCLCTRL_USE_EXT_SIG_DETECT;
8992 tp->grc_local_ctrl |= GRC_LCLCTRL_USE_SIG_DETECT;
8993 tw32(GRC_LOCAL_CTRL, tp->grc_local_ctrl);
8996 if (!tg3_flag(tp, USE_PHYLIB)) {
8997 if (tp->phy_flags & TG3_PHYFLG_IS_LOW_POWER) {
8998 tp->phy_flags &= ~TG3_PHYFLG_IS_LOW_POWER;
8999 tp->link_config.speed = tp->link_config.orig_speed;
9000 tp->link_config.duplex = tp->link_config.orig_duplex;
9001 tp->link_config.autoneg = tp->link_config.orig_autoneg;
9004 err = tg3_setup_phy(tp, 0);
9008 if (!(tp->phy_flags & TG3_PHYFLG_PHY_SERDES) &&
9009 !(tp->phy_flags & TG3_PHYFLG_IS_FET)) {
9012 /* Clear CRC stats. */
9013 if (!tg3_readphy(tp, MII_TG3_TEST1, &tmp)) {
9014 tg3_writephy(tp, MII_TG3_TEST1,
9015 tmp | MII_TG3_TEST1_CRC_EN);
9016 tg3_readphy(tp, MII_TG3_RXR_COUNTERS, &tmp);
9021 __tg3_set_rx_mode(tp->dev);
9023 /* Initialize receive rules. */
9024 tw32(MAC_RCV_RULE_0, 0xc2000000 & RCV_RULE_DISABLE_MASK);
9025 tw32(MAC_RCV_VALUE_0, 0xffffffff & RCV_RULE_DISABLE_MASK);
9026 tw32(MAC_RCV_RULE_1, 0x86000004 & RCV_RULE_DISABLE_MASK);
9027 tw32(MAC_RCV_VALUE_1, 0xffffffff & RCV_RULE_DISABLE_MASK);
9029 if (tg3_flag(tp, 5705_PLUS) && !tg3_flag(tp, 5780_CLASS))
9033 if (tg3_flag(tp, ENABLE_ASF))
9037 tw32(MAC_RCV_RULE_15, 0); tw32(MAC_RCV_VALUE_15, 0);
9039 tw32(MAC_RCV_RULE_14, 0); tw32(MAC_RCV_VALUE_14, 0);
9041 tw32(MAC_RCV_RULE_13, 0); tw32(MAC_RCV_VALUE_13, 0);
9043 tw32(MAC_RCV_RULE_12, 0); tw32(MAC_RCV_VALUE_12, 0);
9045 tw32(MAC_RCV_RULE_11, 0); tw32(MAC_RCV_VALUE_11, 0);
9047 tw32(MAC_RCV_RULE_10, 0); tw32(MAC_RCV_VALUE_10, 0);
9049 tw32(MAC_RCV_RULE_9, 0); tw32(MAC_RCV_VALUE_9, 0);
9051 tw32(MAC_RCV_RULE_8, 0); tw32(MAC_RCV_VALUE_8, 0);
9053 tw32(MAC_RCV_RULE_7, 0); tw32(MAC_RCV_VALUE_7, 0);
9055 tw32(MAC_RCV_RULE_6, 0); tw32(MAC_RCV_VALUE_6, 0);
9057 tw32(MAC_RCV_RULE_5, 0); tw32(MAC_RCV_VALUE_5, 0);
9059 tw32(MAC_RCV_RULE_4, 0); tw32(MAC_RCV_VALUE_4, 0);
9061 /* tw32(MAC_RCV_RULE_3, 0); tw32(MAC_RCV_VALUE_3, 0); */
9063 /* tw32(MAC_RCV_RULE_2, 0); tw32(MAC_RCV_VALUE_2, 0); */
9071 if (tg3_flag(tp, ENABLE_APE))
9072 /* Write our heartbeat update interval to APE. */
9073 tg3_ape_write32(tp, TG3_APE_HOST_HEARTBEAT_INT_MS,
9074 APE_HOST_HEARTBEAT_INT_DISABLE);
9076 tg3_write_sig_post_reset(tp, RESET_KIND_INIT);
9081 /* Called at device open time to get the chip ready for
9082 * packet processing. Invoked with tp->lock held.
9084 static int tg3_init_hw(struct tg3 *tp, int reset_phy)
9086 tg3_switch_clocks(tp);
9088 tw32(TG3PCI_MEM_WIN_BASE_ADDR, 0);
9090 return tg3_reset_hw(tp, reset_phy);
9093 /* Restart hardware after configuration changes, self-test, etc.
9094 * Invoked with tp->lock held.
9096 static int tg3_restart_hw(struct tg3 *tp, int reset_phy)
9097 __releases(tp->lock)
9098 __acquires(tp->lock)
9102 err = tg3_init_hw(tp, reset_phy);
9105 "Failed to re-initialize device, aborting\n");
9106 tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
9107 tg3_full_unlock(tp);
9108 del_timer_sync(&tp->timer);
9110 tg3_napi_enable(tp);
9112 tg3_full_lock(tp, 0);
9117 static void tg3_reset_task(struct work_struct *work)
9119 struct tg3 *tp = container_of(work, struct tg3, reset_task);
9122 tg3_full_lock(tp, 0);
9124 if (!netif_running(tp->dev)) {
9125 tg3_flag_clear(tp, RESET_TASK_PENDING);
9126 tg3_full_unlock(tp);
9130 tg3_full_unlock(tp);
9136 tg3_full_lock(tp, 1);
9138 if (tg3_flag(tp, TX_RECOVERY_PENDING)) {
9139 tp->write32_tx_mbox = tg3_write32_tx_mbox;
9140 tp->write32_rx_mbox = tg3_write_flush_reg32;
9141 tg3_flag_set(tp, MBOX_WRITE_REORDER);
9142 tg3_flag_clear(tp, TX_RECOVERY_PENDING);
9145 tg3_halt(tp, RESET_KIND_SHUTDOWN, 0);
9146 err = tg3_init_hw(tp, 1);
9150 tg3_netif_start(tp);
9153 tg3_full_unlock(tp);
9158 tg3_flag_clear(tp, RESET_TASK_PENDING);
9161 #define TG3_STAT_ADD32(PSTAT, REG) \
9162 do { u32 __val = tr32(REG); \
9163 (PSTAT)->low += __val; \
9164 if ((PSTAT)->low < __val) \
9165 (PSTAT)->high += 1; \
9168 static void tg3_periodic_fetch_stats(struct tg3 *tp)
9170 struct tg3_hw_stats *sp = tp->hw_stats;
9172 if (!netif_carrier_ok(tp->dev))
9175 TG3_STAT_ADD32(&sp->tx_octets, MAC_TX_STATS_OCTETS);
9176 TG3_STAT_ADD32(&sp->tx_collisions, MAC_TX_STATS_COLLISIONS);
9177 TG3_STAT_ADD32(&sp->tx_xon_sent, MAC_TX_STATS_XON_SENT);
9178 TG3_STAT_ADD32(&sp->tx_xoff_sent, MAC_TX_STATS_XOFF_SENT);
9179 TG3_STAT_ADD32(&sp->tx_mac_errors, MAC_TX_STATS_MAC_ERRORS);
9180 TG3_STAT_ADD32(&sp->tx_single_collisions, MAC_TX_STATS_SINGLE_COLLISIONS);
9181 TG3_STAT_ADD32(&sp->tx_mult_collisions, MAC_TX_STATS_MULT_COLLISIONS);
9182 TG3_STAT_ADD32(&sp->tx_deferred, MAC_TX_STATS_DEFERRED);
9183 TG3_STAT_ADD32(&sp->tx_excessive_collisions, MAC_TX_STATS_EXCESSIVE_COL);
9184 TG3_STAT_ADD32(&sp->tx_late_collisions, MAC_TX_STATS_LATE_COL);
9185 TG3_STAT_ADD32(&sp->tx_ucast_packets, MAC_TX_STATS_UCAST);
9186 TG3_STAT_ADD32(&sp->tx_mcast_packets, MAC_TX_STATS_MCAST);
9187 TG3_STAT_ADD32(&sp->tx_bcast_packets, MAC_TX_STATS_BCAST);
9189 TG3_STAT_ADD32(&sp->rx_octets, MAC_RX_STATS_OCTETS);
9190 TG3_STAT_ADD32(&sp->rx_fragments, MAC_RX_STATS_FRAGMENTS);
9191 TG3_STAT_ADD32(&sp->rx_ucast_packets, MAC_RX_STATS_UCAST);
9192 TG3_STAT_ADD32(&sp->rx_mcast_packets, MAC_RX_STATS_MCAST);
9193 TG3_STAT_ADD32(&sp->rx_bcast_packets, MAC_RX_STATS_BCAST);
9194 TG3_STAT_ADD32(&sp->rx_fcs_errors, MAC_RX_STATS_FCS_ERRORS);
9195 TG3_STAT_ADD32(&sp->rx_align_errors, MAC_RX_STATS_ALIGN_ERRORS);
9196 TG3_STAT_ADD32(&sp->rx_xon_pause_rcvd, MAC_RX_STATS_XON_PAUSE_RECVD);
9197 TG3_STAT_ADD32(&sp->rx_xoff_pause_rcvd, MAC_RX_STATS_XOFF_PAUSE_RECVD);
9198 TG3_STAT_ADD32(&sp->rx_mac_ctrl_rcvd, MAC_RX_STATS_MAC_CTRL_RECVD);
9199 TG3_STAT_ADD32(&sp->rx_xoff_entered, MAC_RX_STATS_XOFF_ENTERED);
9200 TG3_STAT_ADD32(&sp->rx_frame_too_long_errors, MAC_RX_STATS_FRAME_TOO_LONG);
9201 TG3_STAT_ADD32(&sp->rx_jabbers, MAC_RX_STATS_JABBERS);
9202 TG3_STAT_ADD32(&sp->rx_undersize_packets, MAC_RX_STATS_UNDERSIZE);
9204 TG3_STAT_ADD32(&sp->rxbds_empty, RCVLPC_NO_RCV_BD_CNT);
9205 if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5717 &&
9206 tp->pci_chip_rev_id != CHIPREV_ID_5719_A0 &&
9207 tp->pci_chip_rev_id != CHIPREV_ID_5720_A0) {
9208 TG3_STAT_ADD32(&sp->rx_discards, RCVLPC_IN_DISCARDS_CNT);
9210 u32 val = tr32(HOSTCC_FLOW_ATTN);
9211 val = (val & HOSTCC_FLOW_ATTN_MBUF_LWM) ? 1 : 0;
9213 tw32(HOSTCC_FLOW_ATTN, HOSTCC_FLOW_ATTN_MBUF_LWM);
9214 sp->rx_discards.low += val;
9215 if (sp->rx_discards.low < val)
9216 sp->rx_discards.high += 1;
9218 sp->mbuf_lwm_thresh_hit = sp->rx_discards;
9220 TG3_STAT_ADD32(&sp->rx_errors, RCVLPC_IN_ERRORS_CNT);
9223 static void tg3_chk_missed_msi(struct tg3 *tp)
9227 for (i = 0; i < tp->irq_cnt; i++) {
9228 struct tg3_napi *tnapi = &tp->napi[i];
9230 if (tg3_has_work(tnapi)) {
9231 if (tnapi->last_rx_cons == tnapi->rx_rcb_ptr &&
9232 tnapi->last_tx_cons == tnapi->tx_cons) {
9233 if (tnapi->chk_msi_cnt < 1) {
9234 tnapi->chk_msi_cnt++;
9240 tnapi->chk_msi_cnt = 0;
9241 tnapi->last_rx_cons = tnapi->rx_rcb_ptr;
9242 tnapi->last_tx_cons = tnapi->tx_cons;
9246 static void tg3_timer(unsigned long __opaque)
9248 struct tg3 *tp = (struct tg3 *) __opaque;
9250 if (tp->irq_sync || tg3_flag(tp, RESET_TASK_PENDING))
9253 spin_lock(&tp->lock);
9255 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717 ||
9256 tg3_flag(tp, 57765_CLASS))
9257 tg3_chk_missed_msi(tp);
9259 if (!tg3_flag(tp, TAGGED_STATUS)) {
9260 /* All of this garbage is because when using non-tagged
9261 * IRQ status the mailbox/status_block protocol the chip
9262 * uses with the cpu is race prone.
9264 if (tp->napi[0].hw_status->status & SD_STATUS_UPDATED) {
9265 tw32(GRC_LOCAL_CTRL,
9266 tp->grc_local_ctrl | GRC_LCLCTRL_SETINT);
9268 tw32(HOSTCC_MODE, tp->coalesce_mode |
9269 HOSTCC_MODE_ENABLE | HOSTCC_MODE_NOW);
9272 if (!(tr32(WDMAC_MODE) & WDMAC_MODE_ENABLE)) {
9273 spin_unlock(&tp->lock);
9274 tg3_reset_task_schedule(tp);
9279 /* This part only runs once per second. */
9280 if (!--tp->timer_counter) {
9281 if (tg3_flag(tp, 5705_PLUS))
9282 tg3_periodic_fetch_stats(tp);
9284 if (tp->setlpicnt && !--tp->setlpicnt)
9285 tg3_phy_eee_enable(tp);
9287 if (tg3_flag(tp, USE_LINKCHG_REG)) {
9291 mac_stat = tr32(MAC_STATUS);
9294 if (tp->phy_flags & TG3_PHYFLG_USE_MI_INTERRUPT) {
9295 if (mac_stat & MAC_STATUS_MI_INTERRUPT)
9297 } else if (mac_stat & MAC_STATUS_LNKSTATE_CHANGED)
9301 tg3_setup_phy(tp, 0);
9302 } else if (tg3_flag(tp, POLL_SERDES)) {
9303 u32 mac_stat = tr32(MAC_STATUS);
9306 if (netif_carrier_ok(tp->dev) &&
9307 (mac_stat & MAC_STATUS_LNKSTATE_CHANGED)) {
9310 if (!netif_carrier_ok(tp->dev) &&
9311 (mac_stat & (MAC_STATUS_PCS_SYNCED |
9312 MAC_STATUS_SIGNAL_DET))) {
9316 if (!tp->serdes_counter) {
9319 ~MAC_MODE_PORT_MODE_MASK));
9321 tw32_f(MAC_MODE, tp->mac_mode);
9324 tg3_setup_phy(tp, 0);
9326 } else if ((tp->phy_flags & TG3_PHYFLG_MII_SERDES) &&
9327 tg3_flag(tp, 5780_CLASS)) {
9328 tg3_serdes_parallel_detect(tp);
9331 tp->timer_counter = tp->timer_multiplier;
9334 /* Heartbeat is only sent once every 2 seconds.
9336 * The heartbeat is to tell the ASF firmware that the host
9337 * driver is still alive. In the event that the OS crashes,
9338 * ASF needs to reset the hardware to free up the FIFO space
9339 * that may be filled with rx packets destined for the host.
9340 * If the FIFO is full, ASF will no longer function properly.
9342 * Unintended resets have been reported on real time kernels
9343 * where the timer doesn't run on time. Netpoll will also have
9346 * The new FWCMD_NICDRV_ALIVE3 command tells the ASF firmware
9347 * to check the ring condition when the heartbeat is expiring
9348 * before doing the reset. This will prevent most unintended
9351 if (!--tp->asf_counter) {
9352 if (tg3_flag(tp, ENABLE_ASF) && !tg3_flag(tp, ENABLE_APE)) {
9353 tg3_wait_for_event_ack(tp);
9355 tg3_write_mem(tp, NIC_SRAM_FW_CMD_MBOX,
9356 FWCMD_NICDRV_ALIVE3);
9357 tg3_write_mem(tp, NIC_SRAM_FW_CMD_LEN_MBOX, 4);
9358 tg3_write_mem(tp, NIC_SRAM_FW_CMD_DATA_MBOX,
9359 TG3_FW_UPDATE_TIMEOUT_SEC);
9361 tg3_generate_fw_event(tp);
9363 tp->asf_counter = tp->asf_multiplier;
9366 spin_unlock(&tp->lock);
9369 tp->timer.expires = jiffies + tp->timer_offset;
9370 add_timer(&tp->timer);
9373 static int tg3_request_irq(struct tg3 *tp, int irq_num)
9376 unsigned long flags;
9378 struct tg3_napi *tnapi = &tp->napi[irq_num];
9380 if (tp->irq_cnt == 1)
9381 name = tp->dev->name;
9383 name = &tnapi->irq_lbl[0];
9384 snprintf(name, IFNAMSIZ, "%s-%d", tp->dev->name, irq_num);
9385 name[IFNAMSIZ-1] = 0;
9388 if (tg3_flag(tp, USING_MSI) || tg3_flag(tp, USING_MSIX)) {
9390 if (tg3_flag(tp, 1SHOT_MSI))
9395 if (tg3_flag(tp, TAGGED_STATUS))
9396 fn = tg3_interrupt_tagged;
9397 flags = IRQF_SHARED;
9400 return request_irq(tnapi->irq_vec, fn, flags, name, tnapi);
9403 static int tg3_test_interrupt(struct tg3 *tp)
9405 struct tg3_napi *tnapi = &tp->napi[0];
9406 struct net_device *dev = tp->dev;
9407 int err, i, intr_ok = 0;
9410 if (!netif_running(dev))
9413 tg3_disable_ints(tp);
9415 free_irq(tnapi->irq_vec, tnapi);
9418 * Turn off MSI one shot mode. Otherwise this test has no
9419 * observable way to know whether the interrupt was delivered.
9421 if (tg3_flag(tp, 57765_PLUS)) {
9422 val = tr32(MSGINT_MODE) | MSGINT_MODE_ONE_SHOT_DISABLE;
9423 tw32(MSGINT_MODE, val);
9426 err = request_irq(tnapi->irq_vec, tg3_test_isr,
9427 IRQF_SHARED | IRQF_SAMPLE_RANDOM, dev->name, tnapi);
9431 tnapi->hw_status->status &= ~SD_STATUS_UPDATED;
9432 tg3_enable_ints(tp);
9434 tw32_f(HOSTCC_MODE, tp->coalesce_mode | HOSTCC_MODE_ENABLE |
9437 for (i = 0; i < 5; i++) {
9438 u32 int_mbox, misc_host_ctrl;
9440 int_mbox = tr32_mailbox(tnapi->int_mbox);
9441 misc_host_ctrl = tr32(TG3PCI_MISC_HOST_CTRL);
9443 if ((int_mbox != 0) ||
9444 (misc_host_ctrl & MISC_HOST_CTRL_MASK_PCI_INT)) {
9449 if (tg3_flag(tp, 57765_PLUS) &&
9450 tnapi->hw_status->status_tag != tnapi->last_tag)
9451 tw32_mailbox_f(tnapi->int_mbox, tnapi->last_tag << 24);
9456 tg3_disable_ints(tp);
9458 free_irq(tnapi->irq_vec, tnapi);
9460 err = tg3_request_irq(tp, 0);
9466 /* Reenable MSI one shot mode. */
9467 if (tg3_flag(tp, 57765_PLUS) && tg3_flag(tp, 1SHOT_MSI)) {
9468 val = tr32(MSGINT_MODE) & ~MSGINT_MODE_ONE_SHOT_DISABLE;
9469 tw32(MSGINT_MODE, val);
9477 /* Returns 0 if MSI test succeeds or MSI test fails and INTx mode is
9478 * successfully restored
9480 static int tg3_test_msi(struct tg3 *tp)
9485 if (!tg3_flag(tp, USING_MSI))
9488 /* Turn off SERR reporting in case MSI terminates with Master
9491 pci_read_config_word(tp->pdev, PCI_COMMAND, &pci_cmd);
9492 pci_write_config_word(tp->pdev, PCI_COMMAND,
9493 pci_cmd & ~PCI_COMMAND_SERR);
9495 err = tg3_test_interrupt(tp);
9497 pci_write_config_word(tp->pdev, PCI_COMMAND, pci_cmd);
9502 /* other failures */
9506 /* MSI test failed, go back to INTx mode */
9507 netdev_warn(tp->dev, "No interrupt was generated using MSI. Switching "
9508 "to INTx mode. Please report this failure to the PCI "
9509 "maintainer and include system chipset information\n");
9511 free_irq(tp->napi[0].irq_vec, &tp->napi[0]);
9513 pci_disable_msi(tp->pdev);
9515 tg3_flag_clear(tp, USING_MSI);
9516 tp->napi[0].irq_vec = tp->pdev->irq;
9518 err = tg3_request_irq(tp, 0);
9522 /* Need to reset the chip because the MSI cycle may have terminated
9523 * with Master Abort.
9525 tg3_full_lock(tp, 1);
9527 tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
9528 err = tg3_init_hw(tp, 1);
9530 tg3_full_unlock(tp);
9533 free_irq(tp->napi[0].irq_vec, &tp->napi[0]);
9538 static int tg3_request_firmware(struct tg3 *tp)
9540 const __be32 *fw_data;
9542 if (request_firmware(&tp->fw, tp->fw_needed, &tp->pdev->dev)) {
9543 netdev_err(tp->dev, "Failed to load firmware \"%s\"\n",
9548 fw_data = (void *)tp->fw->data;
9550 /* Firmware blob starts with version numbers, followed by
9551 * start address and _full_ length including BSS sections
9552 * (which must be longer than the actual data, of course
9555 tp->fw_len = be32_to_cpu(fw_data[2]); /* includes bss */
9556 if (tp->fw_len < (tp->fw->size - 12)) {
9557 netdev_err(tp->dev, "bogus length %d in \"%s\"\n",
9558 tp->fw_len, tp->fw_needed);
9559 release_firmware(tp->fw);
9564 /* We no longer need firmware; we have it. */
9565 tp->fw_needed = NULL;
9569 static bool tg3_enable_msix(struct tg3 *tp)
9572 struct msix_entry msix_ent[tp->irq_max];
9574 tp->irq_cnt = num_online_cpus();
9575 if (tp->irq_cnt > 1) {
9576 /* We want as many rx rings enabled as there are cpus.
9577 * In multiqueue MSI-X mode, the first MSI-X vector
9578 * only deals with link interrupts, etc, so we add
9579 * one to the number of vectors we are requesting.
9581 tp->irq_cnt = min_t(unsigned, tp->irq_cnt + 1, tp->irq_max);
9584 for (i = 0; i < tp->irq_max; i++) {
9585 msix_ent[i].entry = i;
9586 msix_ent[i].vector = 0;
9589 rc = pci_enable_msix(tp->pdev, msix_ent, tp->irq_cnt);
9592 } else if (rc != 0) {
9593 if (pci_enable_msix(tp->pdev, msix_ent, rc))
9595 netdev_notice(tp->dev, "Requested %d MSI-X vectors, received %d\n",
9600 for (i = 0; i < tp->irq_max; i++)
9601 tp->napi[i].irq_vec = msix_ent[i].vector;
9603 netif_set_real_num_tx_queues(tp->dev, 1);
9604 rc = tp->irq_cnt > 1 ? tp->irq_cnt - 1 : 1;
9605 if (netif_set_real_num_rx_queues(tp->dev, rc)) {
9606 pci_disable_msix(tp->pdev);
9610 if (tp->irq_cnt > 1) {
9611 tg3_flag_set(tp, ENABLE_RSS);
9613 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5719 ||
9614 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5720) {
9615 tg3_flag_set(tp, ENABLE_TSS);
9616 netif_set_real_num_tx_queues(tp->dev, tp->irq_cnt - 1);
9623 static void tg3_ints_init(struct tg3 *tp)
9625 if ((tg3_flag(tp, SUPPORT_MSI) || tg3_flag(tp, SUPPORT_MSIX)) &&
9626 !tg3_flag(tp, TAGGED_STATUS)) {
9627 /* All MSI supporting chips should support tagged
9628 * status. Assert that this is the case.
9630 netdev_warn(tp->dev,
9631 "MSI without TAGGED_STATUS? Not using MSI\n");
9635 if (tg3_flag(tp, SUPPORT_MSIX) && tg3_enable_msix(tp))
9636 tg3_flag_set(tp, USING_MSIX);
9637 else if (tg3_flag(tp, SUPPORT_MSI) && pci_enable_msi(tp->pdev) == 0)
9638 tg3_flag_set(tp, USING_MSI);
9640 if (tg3_flag(tp, USING_MSI) || tg3_flag(tp, USING_MSIX)) {
9641 u32 msi_mode = tr32(MSGINT_MODE);
9642 if (tg3_flag(tp, USING_MSIX) && tp->irq_cnt > 1)
9643 msi_mode |= MSGINT_MODE_MULTIVEC_EN;
9644 if (!tg3_flag(tp, 1SHOT_MSI))
9645 msi_mode |= MSGINT_MODE_ONE_SHOT_DISABLE;
9646 tw32(MSGINT_MODE, msi_mode | MSGINT_MODE_ENABLE);
9649 if (!tg3_flag(tp, USING_MSIX)) {
9651 tp->napi[0].irq_vec = tp->pdev->irq;
9652 netif_set_real_num_tx_queues(tp->dev, 1);
9653 netif_set_real_num_rx_queues(tp->dev, 1);
9657 static void tg3_ints_fini(struct tg3 *tp)
9659 if (tg3_flag(tp, USING_MSIX))
9660 pci_disable_msix(tp->pdev);
9661 else if (tg3_flag(tp, USING_MSI))
9662 pci_disable_msi(tp->pdev);
9663 tg3_flag_clear(tp, USING_MSI);
9664 tg3_flag_clear(tp, USING_MSIX);
9665 tg3_flag_clear(tp, ENABLE_RSS);
9666 tg3_flag_clear(tp, ENABLE_TSS);
9669 static int tg3_open(struct net_device *dev)
9671 struct tg3 *tp = netdev_priv(dev);
9674 if (tp->fw_needed) {
9675 err = tg3_request_firmware(tp);
9676 if (tp->pci_chip_rev_id == CHIPREV_ID_5701_A0) {
9680 netdev_warn(tp->dev, "TSO capability disabled\n");
9681 tg3_flag_clear(tp, TSO_CAPABLE);
9682 } else if (!tg3_flag(tp, TSO_CAPABLE)) {
9683 netdev_notice(tp->dev, "TSO capability restored\n");
9684 tg3_flag_set(tp, TSO_CAPABLE);
9688 netif_carrier_off(tp->dev);
9690 err = tg3_power_up(tp);
9694 tg3_full_lock(tp, 0);
9696 tg3_disable_ints(tp);
9697 tg3_flag_clear(tp, INIT_COMPLETE);
9699 tg3_full_unlock(tp);
9702 * Setup interrupts first so we know how
9703 * many NAPI resources to allocate
9707 tg3_rss_check_indir_tbl(tp);
9709 /* The placement of this call is tied
9710 * to the setup and use of Host TX descriptors.
9712 err = tg3_alloc_consistent(tp);
9718 tg3_napi_enable(tp);
9720 for (i = 0; i < tp->irq_cnt; i++) {
9721 struct tg3_napi *tnapi = &tp->napi[i];
9722 err = tg3_request_irq(tp, i);
9724 for (i--; i >= 0; i--) {
9725 tnapi = &tp->napi[i];
9726 free_irq(tnapi->irq_vec, tnapi);
9732 tg3_full_lock(tp, 0);
9734 err = tg3_init_hw(tp, 1);
9736 tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
9739 if (tg3_flag(tp, TAGGED_STATUS) &&
9740 GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5717 &&
9741 !tg3_flag(tp, 57765_CLASS))
9742 tp->timer_offset = HZ;
9744 tp->timer_offset = HZ / 10;
9746 BUG_ON(tp->timer_offset > HZ);
9747 tp->timer_counter = tp->timer_multiplier =
9748 (HZ / tp->timer_offset);
9749 tp->asf_counter = tp->asf_multiplier =
9750 ((HZ / tp->timer_offset) * 2);
9752 init_timer(&tp->timer);
9753 tp->timer.expires = jiffies + tp->timer_offset;
9754 tp->timer.data = (unsigned long) tp;
9755 tp->timer.function = tg3_timer;
9758 tg3_full_unlock(tp);
9763 if (tg3_flag(tp, USING_MSI)) {
9764 err = tg3_test_msi(tp);
9767 tg3_full_lock(tp, 0);
9768 tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
9770 tg3_full_unlock(tp);
9775 if (!tg3_flag(tp, 57765_PLUS) && tg3_flag(tp, USING_MSI)) {
9776 u32 val = tr32(PCIE_TRANSACTION_CFG);
9778 tw32(PCIE_TRANSACTION_CFG,
9779 val | PCIE_TRANS_CFG_1SHOT_MSI);
9785 tg3_full_lock(tp, 0);
9787 add_timer(&tp->timer);
9788 tg3_flag_set(tp, INIT_COMPLETE);
9789 tg3_enable_ints(tp);
9791 tg3_full_unlock(tp);
9793 netif_tx_start_all_queues(dev);
9796 * Reset loopback feature if it was turned on while the device was down
9797 * make sure that it's installed properly now.
9799 if (dev->features & NETIF_F_LOOPBACK)
9800 tg3_set_loopback(dev, dev->features);
9805 for (i = tp->irq_cnt - 1; i >= 0; i--) {
9806 struct tg3_napi *tnapi = &tp->napi[i];
9807 free_irq(tnapi->irq_vec, tnapi);
9811 tg3_napi_disable(tp);
9813 tg3_free_consistent(tp);
9817 tg3_frob_aux_power(tp, false);
9818 pci_set_power_state(tp->pdev, PCI_D3hot);
9822 static int tg3_close(struct net_device *dev)
9825 struct tg3 *tp = netdev_priv(dev);
9827 tg3_napi_disable(tp);
9828 tg3_reset_task_cancel(tp);
9830 netif_tx_stop_all_queues(dev);
9832 del_timer_sync(&tp->timer);
9836 tg3_full_lock(tp, 1);
9838 tg3_disable_ints(tp);
9840 tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
9842 tg3_flag_clear(tp, INIT_COMPLETE);
9844 tg3_full_unlock(tp);
9846 for (i = tp->irq_cnt - 1; i >= 0; i--) {
9847 struct tg3_napi *tnapi = &tp->napi[i];
9848 free_irq(tnapi->irq_vec, tnapi);
9853 /* Clear stats across close / open calls */
9854 memset(&tp->net_stats_prev, 0, sizeof(tp->net_stats_prev));
9855 memset(&tp->estats_prev, 0, sizeof(tp->estats_prev));
9859 tg3_free_consistent(tp);
9863 netif_carrier_off(tp->dev);
9868 static inline u64 get_stat64(tg3_stat64_t *val)
9870 return ((u64)val->high << 32) | ((u64)val->low);
9873 static u64 calc_crc_errors(struct tg3 *tp)
9875 struct tg3_hw_stats *hw_stats = tp->hw_stats;
9877 if (!(tp->phy_flags & TG3_PHYFLG_PHY_SERDES) &&
9878 (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
9879 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701)) {
9882 spin_lock_bh(&tp->lock);
9883 if (!tg3_readphy(tp, MII_TG3_TEST1, &val)) {
9884 tg3_writephy(tp, MII_TG3_TEST1,
9885 val | MII_TG3_TEST1_CRC_EN);
9886 tg3_readphy(tp, MII_TG3_RXR_COUNTERS, &val);
9889 spin_unlock_bh(&tp->lock);
9891 tp->phy_crc_errors += val;
9893 return tp->phy_crc_errors;
9896 return get_stat64(&hw_stats->rx_fcs_errors);
9899 #define ESTAT_ADD(member) \
9900 estats->member = old_estats->member + \
9901 get_stat64(&hw_stats->member)
9903 static struct tg3_ethtool_stats *tg3_get_estats(struct tg3 *tp,
9904 struct tg3_ethtool_stats *estats)
9906 struct tg3_ethtool_stats *old_estats = &tp->estats_prev;
9907 struct tg3_hw_stats *hw_stats = tp->hw_stats;
9912 ESTAT_ADD(rx_octets);
9913 ESTAT_ADD(rx_fragments);
9914 ESTAT_ADD(rx_ucast_packets);
9915 ESTAT_ADD(rx_mcast_packets);
9916 ESTAT_ADD(rx_bcast_packets);
9917 ESTAT_ADD(rx_fcs_errors);
9918 ESTAT_ADD(rx_align_errors);
9919 ESTAT_ADD(rx_xon_pause_rcvd);
9920 ESTAT_ADD(rx_xoff_pause_rcvd);
9921 ESTAT_ADD(rx_mac_ctrl_rcvd);
9922 ESTAT_ADD(rx_xoff_entered);
9923 ESTAT_ADD(rx_frame_too_long_errors);
9924 ESTAT_ADD(rx_jabbers);
9925 ESTAT_ADD(rx_undersize_packets);
9926 ESTAT_ADD(rx_in_length_errors);
9927 ESTAT_ADD(rx_out_length_errors);
9928 ESTAT_ADD(rx_64_or_less_octet_packets);
9929 ESTAT_ADD(rx_65_to_127_octet_packets);
9930 ESTAT_ADD(rx_128_to_255_octet_packets);
9931 ESTAT_ADD(rx_256_to_511_octet_packets);
9932 ESTAT_ADD(rx_512_to_1023_octet_packets);
9933 ESTAT_ADD(rx_1024_to_1522_octet_packets);
9934 ESTAT_ADD(rx_1523_to_2047_octet_packets);
9935 ESTAT_ADD(rx_2048_to_4095_octet_packets);
9936 ESTAT_ADD(rx_4096_to_8191_octet_packets);
9937 ESTAT_ADD(rx_8192_to_9022_octet_packets);
9939 ESTAT_ADD(tx_octets);
9940 ESTAT_ADD(tx_collisions);
9941 ESTAT_ADD(tx_xon_sent);
9942 ESTAT_ADD(tx_xoff_sent);
9943 ESTAT_ADD(tx_flow_control);
9944 ESTAT_ADD(tx_mac_errors);
9945 ESTAT_ADD(tx_single_collisions);
9946 ESTAT_ADD(tx_mult_collisions);
9947 ESTAT_ADD(tx_deferred);
9948 ESTAT_ADD(tx_excessive_collisions);
9949 ESTAT_ADD(tx_late_collisions);
9950 ESTAT_ADD(tx_collide_2times);
9951 ESTAT_ADD(tx_collide_3times);
9952 ESTAT_ADD(tx_collide_4times);
9953 ESTAT_ADD(tx_collide_5times);
9954 ESTAT_ADD(tx_collide_6times);
9955 ESTAT_ADD(tx_collide_7times);
9956 ESTAT_ADD(tx_collide_8times);
9957 ESTAT_ADD(tx_collide_9times);
9958 ESTAT_ADD(tx_collide_10times);
9959 ESTAT_ADD(tx_collide_11times);
9960 ESTAT_ADD(tx_collide_12times);
9961 ESTAT_ADD(tx_collide_13times);
9962 ESTAT_ADD(tx_collide_14times);
9963 ESTAT_ADD(tx_collide_15times);
9964 ESTAT_ADD(tx_ucast_packets);
9965 ESTAT_ADD(tx_mcast_packets);
9966 ESTAT_ADD(tx_bcast_packets);
9967 ESTAT_ADD(tx_carrier_sense_errors);
9968 ESTAT_ADD(tx_discards);
9969 ESTAT_ADD(tx_errors);
9971 ESTAT_ADD(dma_writeq_full);
9972 ESTAT_ADD(dma_write_prioq_full);
9973 ESTAT_ADD(rxbds_empty);
9974 ESTAT_ADD(rx_discards);
9975 ESTAT_ADD(rx_errors);
9976 ESTAT_ADD(rx_threshold_hit);
9978 ESTAT_ADD(dma_readq_full);
9979 ESTAT_ADD(dma_read_prioq_full);
9980 ESTAT_ADD(tx_comp_queue_full);
9982 ESTAT_ADD(ring_set_send_prod_index);
9983 ESTAT_ADD(ring_status_update);
9984 ESTAT_ADD(nic_irqs);
9985 ESTAT_ADD(nic_avoided_irqs);
9986 ESTAT_ADD(nic_tx_threshold_hit);
9988 ESTAT_ADD(mbuf_lwm_thresh_hit);
9993 static struct rtnl_link_stats64 *tg3_get_stats64(struct net_device *dev,
9994 struct rtnl_link_stats64 *stats)
9996 struct tg3 *tp = netdev_priv(dev);
9997 struct rtnl_link_stats64 *old_stats = &tp->net_stats_prev;
9998 struct tg3_hw_stats *hw_stats = tp->hw_stats;
10003 stats->rx_packets = old_stats->rx_packets +
10004 get_stat64(&hw_stats->rx_ucast_packets) +
10005 get_stat64(&hw_stats->rx_mcast_packets) +
10006 get_stat64(&hw_stats->rx_bcast_packets);
10008 stats->tx_packets = old_stats->tx_packets +
10009 get_stat64(&hw_stats->tx_ucast_packets) +
10010 get_stat64(&hw_stats->tx_mcast_packets) +
10011 get_stat64(&hw_stats->tx_bcast_packets);
10013 stats->rx_bytes = old_stats->rx_bytes +
10014 get_stat64(&hw_stats->rx_octets);
10015 stats->tx_bytes = old_stats->tx_bytes +
10016 get_stat64(&hw_stats->tx_octets);
10018 stats->rx_errors = old_stats->rx_errors +
10019 get_stat64(&hw_stats->rx_errors);
10020 stats->tx_errors = old_stats->tx_errors +
10021 get_stat64(&hw_stats->tx_errors) +
10022 get_stat64(&hw_stats->tx_mac_errors) +
10023 get_stat64(&hw_stats->tx_carrier_sense_errors) +
10024 get_stat64(&hw_stats->tx_discards);
10026 stats->multicast = old_stats->multicast +
10027 get_stat64(&hw_stats->rx_mcast_packets);
10028 stats->collisions = old_stats->collisions +
10029 get_stat64(&hw_stats->tx_collisions);
10031 stats->rx_length_errors = old_stats->rx_length_errors +
10032 get_stat64(&hw_stats->rx_frame_too_long_errors) +
10033 get_stat64(&hw_stats->rx_undersize_packets);
10035 stats->rx_over_errors = old_stats->rx_over_errors +
10036 get_stat64(&hw_stats->rxbds_empty);
10037 stats->rx_frame_errors = old_stats->rx_frame_errors +
10038 get_stat64(&hw_stats->rx_align_errors);
10039 stats->tx_aborted_errors = old_stats->tx_aborted_errors +
10040 get_stat64(&hw_stats->tx_discards);
10041 stats->tx_carrier_errors = old_stats->tx_carrier_errors +
10042 get_stat64(&hw_stats->tx_carrier_sense_errors);
10044 stats->rx_crc_errors = old_stats->rx_crc_errors +
10045 calc_crc_errors(tp);
10047 stats->rx_missed_errors = old_stats->rx_missed_errors +
10048 get_stat64(&hw_stats->rx_discards);
10050 stats->rx_dropped = tp->rx_dropped;
10051 stats->tx_dropped = tp->tx_dropped;
10056 static int tg3_get_regs_len(struct net_device *dev)
10058 return TG3_REG_BLK_SIZE;
10061 static void tg3_get_regs(struct net_device *dev,
10062 struct ethtool_regs *regs, void *_p)
10064 struct tg3 *tp = netdev_priv(dev);
10068 memset(_p, 0, TG3_REG_BLK_SIZE);
10070 if (tp->phy_flags & TG3_PHYFLG_IS_LOW_POWER)
10073 tg3_full_lock(tp, 0);
10075 tg3_dump_legacy_regs(tp, (u32 *)_p);
10077 tg3_full_unlock(tp);
10080 static int tg3_get_eeprom_len(struct net_device *dev)
10082 struct tg3 *tp = netdev_priv(dev);
10084 return tp->nvram_size;
10087 static int tg3_get_eeprom(struct net_device *dev, struct ethtool_eeprom *eeprom, u8 *data)
10089 struct tg3 *tp = netdev_priv(dev);
10092 u32 i, offset, len, b_offset, b_count;
10095 if (tg3_flag(tp, NO_NVRAM))
10098 if (tp->phy_flags & TG3_PHYFLG_IS_LOW_POWER)
10101 offset = eeprom->offset;
10105 eeprom->magic = TG3_EEPROM_MAGIC;
10108 /* adjustments to start on required 4 byte boundary */
10109 b_offset = offset & 3;
10110 b_count = 4 - b_offset;
10111 if (b_count > len) {
10112 /* i.e. offset=1 len=2 */
10115 ret = tg3_nvram_read_be32(tp, offset-b_offset, &val);
10118 memcpy(data, ((char *)&val) + b_offset, b_count);
10121 eeprom->len += b_count;
10124 /* read bytes up to the last 4 byte boundary */
10125 pd = &data[eeprom->len];
10126 for (i = 0; i < (len - (len & 3)); i += 4) {
10127 ret = tg3_nvram_read_be32(tp, offset + i, &val);
10132 memcpy(pd + i, &val, 4);
10137 /* read last bytes not ending on 4 byte boundary */
10138 pd = &data[eeprom->len];
10140 b_offset = offset + len - b_count;
10141 ret = tg3_nvram_read_be32(tp, b_offset, &val);
10144 memcpy(pd, &val, b_count);
10145 eeprom->len += b_count;
10150 static int tg3_nvram_write_block(struct tg3 *tp, u32 offset, u32 len, u8 *buf);
10152 static int tg3_set_eeprom(struct net_device *dev, struct ethtool_eeprom *eeprom, u8 *data)
10154 struct tg3 *tp = netdev_priv(dev);
10156 u32 offset, len, b_offset, odd_len;
10160 if (tp->phy_flags & TG3_PHYFLG_IS_LOW_POWER)
10163 if (tg3_flag(tp, NO_NVRAM) ||
10164 eeprom->magic != TG3_EEPROM_MAGIC)
10167 offset = eeprom->offset;
10170 if ((b_offset = (offset & 3))) {
10171 /* adjustments to start on required 4 byte boundary */
10172 ret = tg3_nvram_read_be32(tp, offset-b_offset, &start);
10183 /* adjustments to end on required 4 byte boundary */
10185 len = (len + 3) & ~3;
10186 ret = tg3_nvram_read_be32(tp, offset+len-4, &end);
10192 if (b_offset || odd_len) {
10193 buf = kmalloc(len, GFP_KERNEL);
10197 memcpy(buf, &start, 4);
10199 memcpy(buf+len-4, &end, 4);
10200 memcpy(buf + b_offset, data, eeprom->len);
10203 ret = tg3_nvram_write_block(tp, offset, len, buf);
10211 static int tg3_get_settings(struct net_device *dev, struct ethtool_cmd *cmd)
10213 struct tg3 *tp = netdev_priv(dev);
10215 if (tg3_flag(tp, USE_PHYLIB)) {
10216 struct phy_device *phydev;
10217 if (!(tp->phy_flags & TG3_PHYFLG_IS_CONNECTED))
10219 phydev = tp->mdio_bus->phy_map[TG3_PHY_MII_ADDR];
10220 return phy_ethtool_gset(phydev, cmd);
10223 cmd->supported = (SUPPORTED_Autoneg);
10225 if (!(tp->phy_flags & TG3_PHYFLG_10_100_ONLY))
10226 cmd->supported |= (SUPPORTED_1000baseT_Half |
10227 SUPPORTED_1000baseT_Full);
10229 if (!(tp->phy_flags & TG3_PHYFLG_ANY_SERDES)) {
10230 cmd->supported |= (SUPPORTED_100baseT_Half |
10231 SUPPORTED_100baseT_Full |
10232 SUPPORTED_10baseT_Half |
10233 SUPPORTED_10baseT_Full |
10235 cmd->port = PORT_TP;
10237 cmd->supported |= SUPPORTED_FIBRE;
10238 cmd->port = PORT_FIBRE;
10241 cmd->advertising = tp->link_config.advertising;
10242 if (tg3_flag(tp, PAUSE_AUTONEG)) {
10243 if (tp->link_config.flowctrl & FLOW_CTRL_RX) {
10244 if (tp->link_config.flowctrl & FLOW_CTRL_TX) {
10245 cmd->advertising |= ADVERTISED_Pause;
10247 cmd->advertising |= ADVERTISED_Pause |
10248 ADVERTISED_Asym_Pause;
10250 } else if (tp->link_config.flowctrl & FLOW_CTRL_TX) {
10251 cmd->advertising |= ADVERTISED_Asym_Pause;
10254 if (netif_running(dev) && netif_carrier_ok(dev)) {
10255 ethtool_cmd_speed_set(cmd, tp->link_config.active_speed);
10256 cmd->duplex = tp->link_config.active_duplex;
10257 cmd->lp_advertising = tp->link_config.rmt_adv;
10258 if (!(tp->phy_flags & TG3_PHYFLG_ANY_SERDES)) {
10259 if (tp->phy_flags & TG3_PHYFLG_MDIX_STATE)
10260 cmd->eth_tp_mdix = ETH_TP_MDI_X;
10262 cmd->eth_tp_mdix = ETH_TP_MDI;
10265 ethtool_cmd_speed_set(cmd, SPEED_INVALID);
10266 cmd->duplex = DUPLEX_INVALID;
10267 cmd->eth_tp_mdix = ETH_TP_MDI_INVALID;
10269 cmd->phy_address = tp->phy_addr;
10270 cmd->transceiver = XCVR_INTERNAL;
10271 cmd->autoneg = tp->link_config.autoneg;
10277 static int tg3_set_settings(struct net_device *dev, struct ethtool_cmd *cmd)
10279 struct tg3 *tp = netdev_priv(dev);
10280 u32 speed = ethtool_cmd_speed(cmd);
10282 if (tg3_flag(tp, USE_PHYLIB)) {
10283 struct phy_device *phydev;
10284 if (!(tp->phy_flags & TG3_PHYFLG_IS_CONNECTED))
10286 phydev = tp->mdio_bus->phy_map[TG3_PHY_MII_ADDR];
10287 return phy_ethtool_sset(phydev, cmd);
10290 if (cmd->autoneg != AUTONEG_ENABLE &&
10291 cmd->autoneg != AUTONEG_DISABLE)
10294 if (cmd->autoneg == AUTONEG_DISABLE &&
10295 cmd->duplex != DUPLEX_FULL &&
10296 cmd->duplex != DUPLEX_HALF)
10299 if (cmd->autoneg == AUTONEG_ENABLE) {
10300 u32 mask = ADVERTISED_Autoneg |
10302 ADVERTISED_Asym_Pause;
10304 if (!(tp->phy_flags & TG3_PHYFLG_10_100_ONLY))
10305 mask |= ADVERTISED_1000baseT_Half |
10306 ADVERTISED_1000baseT_Full;
10308 if (!(tp->phy_flags & TG3_PHYFLG_ANY_SERDES))
10309 mask |= ADVERTISED_100baseT_Half |
10310 ADVERTISED_100baseT_Full |
10311 ADVERTISED_10baseT_Half |
10312 ADVERTISED_10baseT_Full |
10315 mask |= ADVERTISED_FIBRE;
10317 if (cmd->advertising & ~mask)
10320 mask &= (ADVERTISED_1000baseT_Half |
10321 ADVERTISED_1000baseT_Full |
10322 ADVERTISED_100baseT_Half |
10323 ADVERTISED_100baseT_Full |
10324 ADVERTISED_10baseT_Half |
10325 ADVERTISED_10baseT_Full);
10327 cmd->advertising &= mask;
10329 if (tp->phy_flags & TG3_PHYFLG_ANY_SERDES) {
10330 if (speed != SPEED_1000)
10333 if (cmd->duplex != DUPLEX_FULL)
10336 if (speed != SPEED_100 &&
10342 tg3_full_lock(tp, 0);
10344 tp->link_config.autoneg = cmd->autoneg;
10345 if (cmd->autoneg == AUTONEG_ENABLE) {
10346 tp->link_config.advertising = (cmd->advertising |
10347 ADVERTISED_Autoneg);
10348 tp->link_config.speed = SPEED_INVALID;
10349 tp->link_config.duplex = DUPLEX_INVALID;
10351 tp->link_config.advertising = 0;
10352 tp->link_config.speed = speed;
10353 tp->link_config.duplex = cmd->duplex;
10356 tp->link_config.orig_speed = tp->link_config.speed;
10357 tp->link_config.orig_duplex = tp->link_config.duplex;
10358 tp->link_config.orig_autoneg = tp->link_config.autoneg;
10360 if (netif_running(dev))
10361 tg3_setup_phy(tp, 1);
10363 tg3_full_unlock(tp);
10368 static void tg3_get_drvinfo(struct net_device *dev, struct ethtool_drvinfo *info)
10370 struct tg3 *tp = netdev_priv(dev);
10372 strlcpy(info->driver, DRV_MODULE_NAME, sizeof(info->driver));
10373 strlcpy(info->version, DRV_MODULE_VERSION, sizeof(info->version));
10374 strlcpy(info->fw_version, tp->fw_ver, sizeof(info->fw_version));
10375 strlcpy(info->bus_info, pci_name(tp->pdev), sizeof(info->bus_info));
10378 static void tg3_get_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
10380 struct tg3 *tp = netdev_priv(dev);
10382 if (tg3_flag(tp, WOL_CAP) && device_can_wakeup(&tp->pdev->dev))
10383 wol->supported = WAKE_MAGIC;
10385 wol->supported = 0;
10387 if (tg3_flag(tp, WOL_ENABLE) && device_can_wakeup(&tp->pdev->dev))
10388 wol->wolopts = WAKE_MAGIC;
10389 memset(&wol->sopass, 0, sizeof(wol->sopass));
10392 static int tg3_set_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
10394 struct tg3 *tp = netdev_priv(dev);
10395 struct device *dp = &tp->pdev->dev;
10397 if (wol->wolopts & ~WAKE_MAGIC)
10399 if ((wol->wolopts & WAKE_MAGIC) &&
10400 !(tg3_flag(tp, WOL_CAP) && device_can_wakeup(dp)))
10403 device_set_wakeup_enable(dp, wol->wolopts & WAKE_MAGIC);
10405 spin_lock_bh(&tp->lock);
10406 if (device_may_wakeup(dp))
10407 tg3_flag_set(tp, WOL_ENABLE);
10409 tg3_flag_clear(tp, WOL_ENABLE);
10410 spin_unlock_bh(&tp->lock);
10415 static u32 tg3_get_msglevel(struct net_device *dev)
10417 struct tg3 *tp = netdev_priv(dev);
10418 return tp->msg_enable;
10421 static void tg3_set_msglevel(struct net_device *dev, u32 value)
10423 struct tg3 *tp = netdev_priv(dev);
10424 tp->msg_enable = value;
10427 static int tg3_nway_reset(struct net_device *dev)
10429 struct tg3 *tp = netdev_priv(dev);
10432 if (!netif_running(dev))
10435 if (tp->phy_flags & TG3_PHYFLG_PHY_SERDES)
10438 if (tg3_flag(tp, USE_PHYLIB)) {
10439 if (!(tp->phy_flags & TG3_PHYFLG_IS_CONNECTED))
10441 r = phy_start_aneg(tp->mdio_bus->phy_map[TG3_PHY_MII_ADDR]);
10445 spin_lock_bh(&tp->lock);
10447 tg3_readphy(tp, MII_BMCR, &bmcr);
10448 if (!tg3_readphy(tp, MII_BMCR, &bmcr) &&
10449 ((bmcr & BMCR_ANENABLE) ||
10450 (tp->phy_flags & TG3_PHYFLG_PARALLEL_DETECT))) {
10451 tg3_writephy(tp, MII_BMCR, bmcr | BMCR_ANRESTART |
10455 spin_unlock_bh(&tp->lock);
10461 static void tg3_get_ringparam(struct net_device *dev, struct ethtool_ringparam *ering)
10463 struct tg3 *tp = netdev_priv(dev);
10465 ering->rx_max_pending = tp->rx_std_ring_mask;
10466 if (tg3_flag(tp, JUMBO_RING_ENABLE))
10467 ering->rx_jumbo_max_pending = tp->rx_jmb_ring_mask;
10469 ering->rx_jumbo_max_pending = 0;
10471 ering->tx_max_pending = TG3_TX_RING_SIZE - 1;
10473 ering->rx_pending = tp->rx_pending;
10474 if (tg3_flag(tp, JUMBO_RING_ENABLE))
10475 ering->rx_jumbo_pending = tp->rx_jumbo_pending;
10477 ering->rx_jumbo_pending = 0;
10479 ering->tx_pending = tp->napi[0].tx_pending;
10482 static int tg3_set_ringparam(struct net_device *dev, struct ethtool_ringparam *ering)
10484 struct tg3 *tp = netdev_priv(dev);
10485 int i, irq_sync = 0, err = 0;
10487 if ((ering->rx_pending > tp->rx_std_ring_mask) ||
10488 (ering->rx_jumbo_pending > tp->rx_jmb_ring_mask) ||
10489 (ering->tx_pending > TG3_TX_RING_SIZE - 1) ||
10490 (ering->tx_pending <= MAX_SKB_FRAGS) ||
10491 (tg3_flag(tp, TSO_BUG) &&
10492 (ering->tx_pending <= (MAX_SKB_FRAGS * 3))))
10495 if (netif_running(dev)) {
10497 tg3_netif_stop(tp);
10501 tg3_full_lock(tp, irq_sync);
10503 tp->rx_pending = ering->rx_pending;
10505 if (tg3_flag(tp, MAX_RXPEND_64) &&
10506 tp->rx_pending > 63)
10507 tp->rx_pending = 63;
10508 tp->rx_jumbo_pending = ering->rx_jumbo_pending;
10510 for (i = 0; i < tp->irq_max; i++)
10511 tp->napi[i].tx_pending = ering->tx_pending;
10513 if (netif_running(dev)) {
10514 tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
10515 err = tg3_restart_hw(tp, 1);
10517 tg3_netif_start(tp);
10520 tg3_full_unlock(tp);
10522 if (irq_sync && !err)
10528 static void tg3_get_pauseparam(struct net_device *dev, struct ethtool_pauseparam *epause)
10530 struct tg3 *tp = netdev_priv(dev);
10532 epause->autoneg = !!tg3_flag(tp, PAUSE_AUTONEG);
10534 if (tp->link_config.flowctrl & FLOW_CTRL_RX)
10535 epause->rx_pause = 1;
10537 epause->rx_pause = 0;
10539 if (tp->link_config.flowctrl & FLOW_CTRL_TX)
10540 epause->tx_pause = 1;
10542 epause->tx_pause = 0;
10545 static int tg3_set_pauseparam(struct net_device *dev, struct ethtool_pauseparam *epause)
10547 struct tg3 *tp = netdev_priv(dev);
10550 if (tg3_flag(tp, USE_PHYLIB)) {
10552 struct phy_device *phydev;
10554 phydev = tp->mdio_bus->phy_map[TG3_PHY_MII_ADDR];
10556 if (!(phydev->supported & SUPPORTED_Pause) ||
10557 (!(phydev->supported & SUPPORTED_Asym_Pause) &&
10558 (epause->rx_pause != epause->tx_pause)))
10561 tp->link_config.flowctrl = 0;
10562 if (epause->rx_pause) {
10563 tp->link_config.flowctrl |= FLOW_CTRL_RX;
10565 if (epause->tx_pause) {
10566 tp->link_config.flowctrl |= FLOW_CTRL_TX;
10567 newadv = ADVERTISED_Pause;
10569 newadv = ADVERTISED_Pause |
10570 ADVERTISED_Asym_Pause;
10571 } else if (epause->tx_pause) {
10572 tp->link_config.flowctrl |= FLOW_CTRL_TX;
10573 newadv = ADVERTISED_Asym_Pause;
10577 if (epause->autoneg)
10578 tg3_flag_set(tp, PAUSE_AUTONEG);
10580 tg3_flag_clear(tp, PAUSE_AUTONEG);
10582 if (tp->phy_flags & TG3_PHYFLG_IS_CONNECTED) {
10583 u32 oldadv = phydev->advertising &
10584 (ADVERTISED_Pause | ADVERTISED_Asym_Pause);
10585 if (oldadv != newadv) {
10586 phydev->advertising &=
10587 ~(ADVERTISED_Pause |
10588 ADVERTISED_Asym_Pause);
10589 phydev->advertising |= newadv;
10590 if (phydev->autoneg) {
10592 * Always renegotiate the link to
10593 * inform our link partner of our
10594 * flow control settings, even if the
10595 * flow control is forced. Let
10596 * tg3_adjust_link() do the final
10597 * flow control setup.
10599 return phy_start_aneg(phydev);
10603 if (!epause->autoneg)
10604 tg3_setup_flow_control(tp, 0, 0);
10606 tp->link_config.orig_advertising &=
10607 ~(ADVERTISED_Pause |
10608 ADVERTISED_Asym_Pause);
10609 tp->link_config.orig_advertising |= newadv;
10614 if (netif_running(dev)) {
10615 tg3_netif_stop(tp);
10619 tg3_full_lock(tp, irq_sync);
10621 if (epause->autoneg)
10622 tg3_flag_set(tp, PAUSE_AUTONEG);
10624 tg3_flag_clear(tp, PAUSE_AUTONEG);
10625 if (epause->rx_pause)
10626 tp->link_config.flowctrl |= FLOW_CTRL_RX;
10628 tp->link_config.flowctrl &= ~FLOW_CTRL_RX;
10629 if (epause->tx_pause)
10630 tp->link_config.flowctrl |= FLOW_CTRL_TX;
10632 tp->link_config.flowctrl &= ~FLOW_CTRL_TX;
10634 if (netif_running(dev)) {
10635 tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
10636 err = tg3_restart_hw(tp, 1);
10638 tg3_netif_start(tp);
10641 tg3_full_unlock(tp);
10647 static int tg3_get_sset_count(struct net_device *dev, int sset)
10651 return TG3_NUM_TEST;
10653 return TG3_NUM_STATS;
10655 return -EOPNOTSUPP;
10659 static int tg3_get_rxnfc(struct net_device *dev, struct ethtool_rxnfc *info,
10660 u32 *rules __always_unused)
10662 struct tg3 *tp = netdev_priv(dev);
10664 if (!tg3_flag(tp, SUPPORT_MSIX))
10665 return -EOPNOTSUPP;
10667 switch (info->cmd) {
10668 case ETHTOOL_GRXRINGS:
10669 if (netif_running(tp->dev))
10670 info->data = tp->irq_cnt;
10672 info->data = num_online_cpus();
10673 if (info->data > TG3_IRQ_MAX_VECS_RSS)
10674 info->data = TG3_IRQ_MAX_VECS_RSS;
10677 /* The first interrupt vector only
10678 * handles link interrupts.
10684 return -EOPNOTSUPP;
10688 static u32 tg3_get_rxfh_indir_size(struct net_device *dev)
10691 struct tg3 *tp = netdev_priv(dev);
10693 if (tg3_flag(tp, SUPPORT_MSIX))
10694 size = TG3_RSS_INDIR_TBL_SIZE;
10699 static int tg3_get_rxfh_indir(struct net_device *dev, u32 *indir)
10701 struct tg3 *tp = netdev_priv(dev);
10704 for (i = 0; i < TG3_RSS_INDIR_TBL_SIZE; i++)
10705 indir[i] = tp->rss_ind_tbl[i];
10710 static int tg3_set_rxfh_indir(struct net_device *dev, const u32 *indir)
10712 struct tg3 *tp = netdev_priv(dev);
10715 for (i = 0; i < TG3_RSS_INDIR_TBL_SIZE; i++)
10716 tp->rss_ind_tbl[i] = indir[i];
10718 if (!netif_running(dev) || !tg3_flag(tp, ENABLE_RSS))
10721 /* It is legal to write the indirection
10722 * table while the device is running.
10724 tg3_full_lock(tp, 0);
10725 tg3_rss_write_indir_tbl(tp);
10726 tg3_full_unlock(tp);
10731 static void tg3_get_strings(struct net_device *dev, u32 stringset, u8 *buf)
10733 switch (stringset) {
10735 memcpy(buf, ðtool_stats_keys, sizeof(ethtool_stats_keys));
10738 memcpy(buf, ðtool_test_keys, sizeof(ethtool_test_keys));
10741 WARN_ON(1); /* we need a WARN() */
10746 static int tg3_set_phys_id(struct net_device *dev,
10747 enum ethtool_phys_id_state state)
10749 struct tg3 *tp = netdev_priv(dev);
10751 if (!netif_running(tp->dev))
10755 case ETHTOOL_ID_ACTIVE:
10756 return 1; /* cycle on/off once per second */
10758 case ETHTOOL_ID_ON:
10759 tw32(MAC_LED_CTRL, LED_CTRL_LNKLED_OVERRIDE |
10760 LED_CTRL_1000MBPS_ON |
10761 LED_CTRL_100MBPS_ON |
10762 LED_CTRL_10MBPS_ON |
10763 LED_CTRL_TRAFFIC_OVERRIDE |
10764 LED_CTRL_TRAFFIC_BLINK |
10765 LED_CTRL_TRAFFIC_LED);
10768 case ETHTOOL_ID_OFF:
10769 tw32(MAC_LED_CTRL, LED_CTRL_LNKLED_OVERRIDE |
10770 LED_CTRL_TRAFFIC_OVERRIDE);
10773 case ETHTOOL_ID_INACTIVE:
10774 tw32(MAC_LED_CTRL, tp->led_ctrl);
10781 static void tg3_get_ethtool_stats(struct net_device *dev,
10782 struct ethtool_stats *estats, u64 *tmp_stats)
10784 struct tg3 *tp = netdev_priv(dev);
10786 tg3_get_estats(tp, (struct tg3_ethtool_stats *)tmp_stats);
10789 static __be32 *tg3_vpd_readblock(struct tg3 *tp, u32 *vpdlen)
10793 u32 offset = 0, len = 0;
10796 if (tg3_flag(tp, NO_NVRAM) || tg3_nvram_read(tp, 0, &magic))
10799 if (magic == TG3_EEPROM_MAGIC) {
10800 for (offset = TG3_NVM_DIR_START;
10801 offset < TG3_NVM_DIR_END;
10802 offset += TG3_NVM_DIRENT_SIZE) {
10803 if (tg3_nvram_read(tp, offset, &val))
10806 if ((val >> TG3_NVM_DIRTYPE_SHIFT) ==
10807 TG3_NVM_DIRTYPE_EXTVPD)
10811 if (offset != TG3_NVM_DIR_END) {
10812 len = (val & TG3_NVM_DIRTYPE_LENMSK) * 4;
10813 if (tg3_nvram_read(tp, offset + 4, &offset))
10816 offset = tg3_nvram_logical_addr(tp, offset);
10820 if (!offset || !len) {
10821 offset = TG3_NVM_VPD_OFF;
10822 len = TG3_NVM_VPD_LEN;
10825 buf = kmalloc(len, GFP_KERNEL);
10829 if (magic == TG3_EEPROM_MAGIC) {
10830 for (i = 0; i < len; i += 4) {
10831 /* The data is in little-endian format in NVRAM.
10832 * Use the big-endian read routines to preserve
10833 * the byte order as it exists in NVRAM.
10835 if (tg3_nvram_read_be32(tp, offset + i, &buf[i/4]))
10841 unsigned int pos = 0;
10843 ptr = (u8 *)&buf[0];
10844 for (i = 0; pos < len && i < 3; i++, pos += cnt, ptr += cnt) {
10845 cnt = pci_read_vpd(tp->pdev, pos,
10847 if (cnt == -ETIMEDOUT || cnt == -EINTR)
10865 #define NVRAM_TEST_SIZE 0x100
10866 #define NVRAM_SELFBOOT_FORMAT1_0_SIZE 0x14
10867 #define NVRAM_SELFBOOT_FORMAT1_2_SIZE 0x18
10868 #define NVRAM_SELFBOOT_FORMAT1_3_SIZE 0x1c
10869 #define NVRAM_SELFBOOT_FORMAT1_4_SIZE 0x20
10870 #define NVRAM_SELFBOOT_FORMAT1_5_SIZE 0x24
10871 #define NVRAM_SELFBOOT_FORMAT1_6_SIZE 0x50
10872 #define NVRAM_SELFBOOT_HW_SIZE 0x20
10873 #define NVRAM_SELFBOOT_DATA_SIZE 0x1c
10875 static int tg3_test_nvram(struct tg3 *tp)
10877 u32 csum, magic, len;
10879 int i, j, k, err = 0, size;
10881 if (tg3_flag(tp, NO_NVRAM))
10884 if (tg3_nvram_read(tp, 0, &magic) != 0)
10887 if (magic == TG3_EEPROM_MAGIC)
10888 size = NVRAM_TEST_SIZE;
10889 else if ((magic & TG3_EEPROM_MAGIC_FW_MSK) == TG3_EEPROM_MAGIC_FW) {
10890 if ((magic & TG3_EEPROM_SB_FORMAT_MASK) ==
10891 TG3_EEPROM_SB_FORMAT_1) {
10892 switch (magic & TG3_EEPROM_SB_REVISION_MASK) {
10893 case TG3_EEPROM_SB_REVISION_0:
10894 size = NVRAM_SELFBOOT_FORMAT1_0_SIZE;
10896 case TG3_EEPROM_SB_REVISION_2:
10897 size = NVRAM_SELFBOOT_FORMAT1_2_SIZE;
10899 case TG3_EEPROM_SB_REVISION_3:
10900 size = NVRAM_SELFBOOT_FORMAT1_3_SIZE;
10902 case TG3_EEPROM_SB_REVISION_4:
10903 size = NVRAM_SELFBOOT_FORMAT1_4_SIZE;
10905 case TG3_EEPROM_SB_REVISION_5:
10906 size = NVRAM_SELFBOOT_FORMAT1_5_SIZE;
10908 case TG3_EEPROM_SB_REVISION_6:
10909 size = NVRAM_SELFBOOT_FORMAT1_6_SIZE;
10916 } else if ((magic & TG3_EEPROM_MAGIC_HW_MSK) == TG3_EEPROM_MAGIC_HW)
10917 size = NVRAM_SELFBOOT_HW_SIZE;
10921 buf = kmalloc(size, GFP_KERNEL);
10926 for (i = 0, j = 0; i < size; i += 4, j++) {
10927 err = tg3_nvram_read_be32(tp, i, &buf[j]);
10934 /* Selfboot format */
10935 magic = be32_to_cpu(buf[0]);
10936 if ((magic & TG3_EEPROM_MAGIC_FW_MSK) ==
10937 TG3_EEPROM_MAGIC_FW) {
10938 u8 *buf8 = (u8 *) buf, csum8 = 0;
10940 if ((magic & TG3_EEPROM_SB_REVISION_MASK) ==
10941 TG3_EEPROM_SB_REVISION_2) {
10942 /* For rev 2, the csum doesn't include the MBA. */
10943 for (i = 0; i < TG3_EEPROM_SB_F1R2_MBA_OFF; i++)
10945 for (i = TG3_EEPROM_SB_F1R2_MBA_OFF + 4; i < size; i++)
10948 for (i = 0; i < size; i++)
10961 if ((magic & TG3_EEPROM_MAGIC_HW_MSK) ==
10962 TG3_EEPROM_MAGIC_HW) {
10963 u8 data[NVRAM_SELFBOOT_DATA_SIZE];
10964 u8 parity[NVRAM_SELFBOOT_DATA_SIZE];
10965 u8 *buf8 = (u8 *) buf;
10967 /* Separate the parity bits and the data bytes. */
10968 for (i = 0, j = 0, k = 0; i < NVRAM_SELFBOOT_HW_SIZE; i++) {
10969 if ((i == 0) || (i == 8)) {
10973 for (l = 0, msk = 0x80; l < 7; l++, msk >>= 1)
10974 parity[k++] = buf8[i] & msk;
10976 } else if (i == 16) {
10980 for (l = 0, msk = 0x20; l < 6; l++, msk >>= 1)
10981 parity[k++] = buf8[i] & msk;
10984 for (l = 0, msk = 0x80; l < 8; l++, msk >>= 1)
10985 parity[k++] = buf8[i] & msk;
10988 data[j++] = buf8[i];
10992 for (i = 0; i < NVRAM_SELFBOOT_DATA_SIZE; i++) {
10993 u8 hw8 = hweight8(data[i]);
10995 if ((hw8 & 0x1) && parity[i])
10997 else if (!(hw8 & 0x1) && !parity[i])
11006 /* Bootstrap checksum at offset 0x10 */
11007 csum = calc_crc((unsigned char *) buf, 0x10);
11008 if (csum != le32_to_cpu(buf[0x10/4]))
11011 /* Manufacturing block starts at offset 0x74, checksum at 0xfc */
11012 csum = calc_crc((unsigned char *) &buf[0x74/4], 0x88);
11013 if (csum != le32_to_cpu(buf[0xfc/4]))
11018 buf = tg3_vpd_readblock(tp, &len);
11022 i = pci_vpd_find_tag((u8 *)buf, 0, len, PCI_VPD_LRDT_RO_DATA);
11024 j = pci_vpd_lrdt_size(&((u8 *)buf)[i]);
11028 if (i + PCI_VPD_LRDT_TAG_SIZE + j > len)
11031 i += PCI_VPD_LRDT_TAG_SIZE;
11032 j = pci_vpd_find_info_keyword((u8 *)buf, i, j,
11033 PCI_VPD_RO_KEYWORD_CHKSUM);
11037 j += PCI_VPD_INFO_FLD_HDR_SIZE;
11039 for (i = 0; i <= j; i++)
11040 csum8 += ((u8 *)buf)[i];
11054 #define TG3_SERDES_TIMEOUT_SEC 2
11055 #define TG3_COPPER_TIMEOUT_SEC 6
11057 static int tg3_test_link(struct tg3 *tp)
11061 if (!netif_running(tp->dev))
11064 if (tp->phy_flags & TG3_PHYFLG_ANY_SERDES)
11065 max = TG3_SERDES_TIMEOUT_SEC;
11067 max = TG3_COPPER_TIMEOUT_SEC;
11069 for (i = 0; i < max; i++) {
11070 if (netif_carrier_ok(tp->dev))
11073 if (msleep_interruptible(1000))
11080 /* Only test the commonly used registers */
11081 static int tg3_test_registers(struct tg3 *tp)
11083 int i, is_5705, is_5750;
11084 u32 offset, read_mask, write_mask, val, save_val, read_val;
11088 #define TG3_FL_5705 0x1
11089 #define TG3_FL_NOT_5705 0x2
11090 #define TG3_FL_NOT_5788 0x4
11091 #define TG3_FL_NOT_5750 0x8
11095 /* MAC Control Registers */
11096 { MAC_MODE, TG3_FL_NOT_5705,
11097 0x00000000, 0x00ef6f8c },
11098 { MAC_MODE, TG3_FL_5705,
11099 0x00000000, 0x01ef6b8c },
11100 { MAC_STATUS, TG3_FL_NOT_5705,
11101 0x03800107, 0x00000000 },
11102 { MAC_STATUS, TG3_FL_5705,
11103 0x03800100, 0x00000000 },
11104 { MAC_ADDR_0_HIGH, 0x0000,
11105 0x00000000, 0x0000ffff },
11106 { MAC_ADDR_0_LOW, 0x0000,
11107 0x00000000, 0xffffffff },
11108 { MAC_RX_MTU_SIZE, 0x0000,
11109 0x00000000, 0x0000ffff },
11110 { MAC_TX_MODE, 0x0000,
11111 0x00000000, 0x00000070 },
11112 { MAC_TX_LENGTHS, 0x0000,
11113 0x00000000, 0x00003fff },
11114 { MAC_RX_MODE, TG3_FL_NOT_5705,
11115 0x00000000, 0x000007fc },
11116 { MAC_RX_MODE, TG3_FL_5705,
11117 0x00000000, 0x000007dc },
11118 { MAC_HASH_REG_0, 0x0000,
11119 0x00000000, 0xffffffff },
11120 { MAC_HASH_REG_1, 0x0000,
11121 0x00000000, 0xffffffff },
11122 { MAC_HASH_REG_2, 0x0000,
11123 0x00000000, 0xffffffff },
11124 { MAC_HASH_REG_3, 0x0000,
11125 0x00000000, 0xffffffff },
11127 /* Receive Data and Receive BD Initiator Control Registers. */
11128 { RCVDBDI_JUMBO_BD+0, TG3_FL_NOT_5705,
11129 0x00000000, 0xffffffff },
11130 { RCVDBDI_JUMBO_BD+4, TG3_FL_NOT_5705,
11131 0x00000000, 0xffffffff },
11132 { RCVDBDI_JUMBO_BD+8, TG3_FL_NOT_5705,
11133 0x00000000, 0x00000003 },
11134 { RCVDBDI_JUMBO_BD+0xc, TG3_FL_NOT_5705,
11135 0x00000000, 0xffffffff },
11136 { RCVDBDI_STD_BD+0, 0x0000,
11137 0x00000000, 0xffffffff },
11138 { RCVDBDI_STD_BD+4, 0x0000,
11139 0x00000000, 0xffffffff },
11140 { RCVDBDI_STD_BD+8, 0x0000,
11141 0x00000000, 0xffff0002 },
11142 { RCVDBDI_STD_BD+0xc, 0x0000,
11143 0x00000000, 0xffffffff },
11145 /* Receive BD Initiator Control Registers. */
11146 { RCVBDI_STD_THRESH, TG3_FL_NOT_5705,
11147 0x00000000, 0xffffffff },
11148 { RCVBDI_STD_THRESH, TG3_FL_5705,
11149 0x00000000, 0x000003ff },
11150 { RCVBDI_JUMBO_THRESH, TG3_FL_NOT_5705,
11151 0x00000000, 0xffffffff },
11153 /* Host Coalescing Control Registers. */
11154 { HOSTCC_MODE, TG3_FL_NOT_5705,
11155 0x00000000, 0x00000004 },
11156 { HOSTCC_MODE, TG3_FL_5705,
11157 0x00000000, 0x000000f6 },
11158 { HOSTCC_RXCOL_TICKS, TG3_FL_NOT_5705,
11159 0x00000000, 0xffffffff },
11160 { HOSTCC_RXCOL_TICKS, TG3_FL_5705,
11161 0x00000000, 0x000003ff },
11162 { HOSTCC_TXCOL_TICKS, TG3_FL_NOT_5705,
11163 0x00000000, 0xffffffff },
11164 { HOSTCC_TXCOL_TICKS, TG3_FL_5705,
11165 0x00000000, 0x000003ff },
11166 { HOSTCC_RXMAX_FRAMES, TG3_FL_NOT_5705,
11167 0x00000000, 0xffffffff },
11168 { HOSTCC_RXMAX_FRAMES, TG3_FL_5705 | TG3_FL_NOT_5788,
11169 0x00000000, 0x000000ff },
11170 { HOSTCC_TXMAX_FRAMES, TG3_FL_NOT_5705,
11171 0x00000000, 0xffffffff },
11172 { HOSTCC_TXMAX_FRAMES, TG3_FL_5705 | TG3_FL_NOT_5788,
11173 0x00000000, 0x000000ff },
11174 { HOSTCC_RXCOAL_TICK_INT, TG3_FL_NOT_5705,
11175 0x00000000, 0xffffffff },
11176 { HOSTCC_TXCOAL_TICK_INT, TG3_FL_NOT_5705,
11177 0x00000000, 0xffffffff },
11178 { HOSTCC_RXCOAL_MAXF_INT, TG3_FL_NOT_5705,
11179 0x00000000, 0xffffffff },
11180 { HOSTCC_RXCOAL_MAXF_INT, TG3_FL_5705 | TG3_FL_NOT_5788,
11181 0x00000000, 0x000000ff },
11182 { HOSTCC_TXCOAL_MAXF_INT, TG3_FL_NOT_5705,
11183 0x00000000, 0xffffffff },
11184 { HOSTCC_TXCOAL_MAXF_INT, TG3_FL_5705 | TG3_FL_NOT_5788,
11185 0x00000000, 0x000000ff },
11186 { HOSTCC_STAT_COAL_TICKS, TG3_FL_NOT_5705,
11187 0x00000000, 0xffffffff },
11188 { HOSTCC_STATS_BLK_HOST_ADDR, TG3_FL_NOT_5705,
11189 0x00000000, 0xffffffff },
11190 { HOSTCC_STATS_BLK_HOST_ADDR+4, TG3_FL_NOT_5705,
11191 0x00000000, 0xffffffff },
11192 { HOSTCC_STATUS_BLK_HOST_ADDR, 0x0000,
11193 0x00000000, 0xffffffff },
11194 { HOSTCC_STATUS_BLK_HOST_ADDR+4, 0x0000,
11195 0x00000000, 0xffffffff },
11196 { HOSTCC_STATS_BLK_NIC_ADDR, 0x0000,
11197 0xffffffff, 0x00000000 },
11198 { HOSTCC_STATUS_BLK_NIC_ADDR, 0x0000,
11199 0xffffffff, 0x00000000 },
11201 /* Buffer Manager Control Registers. */
11202 { BUFMGR_MB_POOL_ADDR, TG3_FL_NOT_5750,
11203 0x00000000, 0x007fff80 },
11204 { BUFMGR_MB_POOL_SIZE, TG3_FL_NOT_5750,
11205 0x00000000, 0x007fffff },
11206 { BUFMGR_MB_RDMA_LOW_WATER, 0x0000,
11207 0x00000000, 0x0000003f },
11208 { BUFMGR_MB_MACRX_LOW_WATER, 0x0000,
11209 0x00000000, 0x000001ff },
11210 { BUFMGR_MB_HIGH_WATER, 0x0000,
11211 0x00000000, 0x000001ff },
11212 { BUFMGR_DMA_DESC_POOL_ADDR, TG3_FL_NOT_5705,
11213 0xffffffff, 0x00000000 },
11214 { BUFMGR_DMA_DESC_POOL_SIZE, TG3_FL_NOT_5705,
11215 0xffffffff, 0x00000000 },
11217 /* Mailbox Registers */
11218 { GRCMBOX_RCVSTD_PROD_IDX+4, 0x0000,
11219 0x00000000, 0x000001ff },
11220 { GRCMBOX_RCVJUMBO_PROD_IDX+4, TG3_FL_NOT_5705,
11221 0x00000000, 0x000001ff },
11222 { GRCMBOX_RCVRET_CON_IDX_0+4, 0x0000,
11223 0x00000000, 0x000007ff },
11224 { GRCMBOX_SNDHOST_PROD_IDX_0+4, 0x0000,
11225 0x00000000, 0x000001ff },
11227 { 0xffff, 0x0000, 0x00000000, 0x00000000 },
11230 is_5705 = is_5750 = 0;
11231 if (tg3_flag(tp, 5705_PLUS)) {
11233 if (tg3_flag(tp, 5750_PLUS))
11237 for (i = 0; reg_tbl[i].offset != 0xffff; i++) {
11238 if (is_5705 && (reg_tbl[i].flags & TG3_FL_NOT_5705))
11241 if (!is_5705 && (reg_tbl[i].flags & TG3_FL_5705))
11244 if (tg3_flag(tp, IS_5788) &&
11245 (reg_tbl[i].flags & TG3_FL_NOT_5788))
11248 if (is_5750 && (reg_tbl[i].flags & TG3_FL_NOT_5750))
11251 offset = (u32) reg_tbl[i].offset;
11252 read_mask = reg_tbl[i].read_mask;
11253 write_mask = reg_tbl[i].write_mask;
11255 /* Save the original register content */
11256 save_val = tr32(offset);
11258 /* Determine the read-only value. */
11259 read_val = save_val & read_mask;
11261 /* Write zero to the register, then make sure the read-only bits
11262 * are not changed and the read/write bits are all zeros.
11266 val = tr32(offset);
11268 /* Test the read-only and read/write bits. */
11269 if (((val & read_mask) != read_val) || (val & write_mask))
11272 /* Write ones to all the bits defined by RdMask and WrMask, then
11273 * make sure the read-only bits are not changed and the
11274 * read/write bits are all ones.
11276 tw32(offset, read_mask | write_mask);
11278 val = tr32(offset);
11280 /* Test the read-only bits. */
11281 if ((val & read_mask) != read_val)
11284 /* Test the read/write bits. */
11285 if ((val & write_mask) != write_mask)
11288 tw32(offset, save_val);
11294 if (netif_msg_hw(tp))
11295 netdev_err(tp->dev,
11296 "Register test failed at offset %x\n", offset);
11297 tw32(offset, save_val);
11301 static int tg3_do_mem_test(struct tg3 *tp, u32 offset, u32 len)
11303 static const u32 test_pattern[] = { 0x00000000, 0xffffffff, 0xaa55a55a };
11307 for (i = 0; i < ARRAY_SIZE(test_pattern); i++) {
11308 for (j = 0; j < len; j += 4) {
11311 tg3_write_mem(tp, offset + j, test_pattern[i]);
11312 tg3_read_mem(tp, offset + j, &val);
11313 if (val != test_pattern[i])
11320 static int tg3_test_memory(struct tg3 *tp)
11322 static struct mem_entry {
11325 } mem_tbl_570x[] = {
11326 { 0x00000000, 0x00b50},
11327 { 0x00002000, 0x1c000},
11328 { 0xffffffff, 0x00000}
11329 }, mem_tbl_5705[] = {
11330 { 0x00000100, 0x0000c},
11331 { 0x00000200, 0x00008},
11332 { 0x00004000, 0x00800},
11333 { 0x00006000, 0x01000},
11334 { 0x00008000, 0x02000},
11335 { 0x00010000, 0x0e000},
11336 { 0xffffffff, 0x00000}
11337 }, mem_tbl_5755[] = {
11338 { 0x00000200, 0x00008},
11339 { 0x00004000, 0x00800},
11340 { 0x00006000, 0x00800},
11341 { 0x00008000, 0x02000},
11342 { 0x00010000, 0x0c000},
11343 { 0xffffffff, 0x00000}
11344 }, mem_tbl_5906[] = {
11345 { 0x00000200, 0x00008},
11346 { 0x00004000, 0x00400},
11347 { 0x00006000, 0x00400},
11348 { 0x00008000, 0x01000},
11349 { 0x00010000, 0x01000},
11350 { 0xffffffff, 0x00000}
11351 }, mem_tbl_5717[] = {
11352 { 0x00000200, 0x00008},
11353 { 0x00010000, 0x0a000},
11354 { 0x00020000, 0x13c00},
11355 { 0xffffffff, 0x00000}
11356 }, mem_tbl_57765[] = {
11357 { 0x00000200, 0x00008},
11358 { 0x00004000, 0x00800},
11359 { 0x00006000, 0x09800},
11360 { 0x00010000, 0x0a000},
11361 { 0xffffffff, 0x00000}
11363 struct mem_entry *mem_tbl;
11367 if (tg3_flag(tp, 5717_PLUS))
11368 mem_tbl = mem_tbl_5717;
11369 else if (tg3_flag(tp, 57765_CLASS))
11370 mem_tbl = mem_tbl_57765;
11371 else if (tg3_flag(tp, 5755_PLUS))
11372 mem_tbl = mem_tbl_5755;
11373 else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906)
11374 mem_tbl = mem_tbl_5906;
11375 else if (tg3_flag(tp, 5705_PLUS))
11376 mem_tbl = mem_tbl_5705;
11378 mem_tbl = mem_tbl_570x;
11380 for (i = 0; mem_tbl[i].offset != 0xffffffff; i++) {
11381 err = tg3_do_mem_test(tp, mem_tbl[i].offset, mem_tbl[i].len);
11389 #define TG3_TSO_MSS 500
11391 #define TG3_TSO_IP_HDR_LEN 20
11392 #define TG3_TSO_TCP_HDR_LEN 20
11393 #define TG3_TSO_TCP_OPT_LEN 12
11395 static const u8 tg3_tso_header[] = {
11397 0x45, 0x00, 0x00, 0x00,
11398 0x00, 0x00, 0x40, 0x00,
11399 0x40, 0x06, 0x00, 0x00,
11400 0x0a, 0x00, 0x00, 0x01,
11401 0x0a, 0x00, 0x00, 0x02,
11402 0x0d, 0x00, 0xe0, 0x00,
11403 0x00, 0x00, 0x01, 0x00,
11404 0x00, 0x00, 0x02, 0x00,
11405 0x80, 0x10, 0x10, 0x00,
11406 0x14, 0x09, 0x00, 0x00,
11407 0x01, 0x01, 0x08, 0x0a,
11408 0x11, 0x11, 0x11, 0x11,
11409 0x11, 0x11, 0x11, 0x11,
11412 static int tg3_run_loopback(struct tg3 *tp, u32 pktsz, bool tso_loopback)
11414 u32 rx_start_idx, rx_idx, tx_idx, opaque_key;
11415 u32 base_flags = 0, mss = 0, desc_idx, coal_now, data_off, val;
11417 struct sk_buff *skb;
11418 u8 *tx_data, *rx_data;
11420 int num_pkts, tx_len, rx_len, i, err;
11421 struct tg3_rx_buffer_desc *desc;
11422 struct tg3_napi *tnapi, *rnapi;
11423 struct tg3_rx_prodring_set *tpr = &tp->napi[0].prodring;
11425 tnapi = &tp->napi[0];
11426 rnapi = &tp->napi[0];
11427 if (tp->irq_cnt > 1) {
11428 if (tg3_flag(tp, ENABLE_RSS))
11429 rnapi = &tp->napi[1];
11430 if (tg3_flag(tp, ENABLE_TSS))
11431 tnapi = &tp->napi[1];
11433 coal_now = tnapi->coal_now | rnapi->coal_now;
11438 skb = netdev_alloc_skb(tp->dev, tx_len);
11442 tx_data = skb_put(skb, tx_len);
11443 memcpy(tx_data, tp->dev->dev_addr, 6);
11444 memset(tx_data + 6, 0x0, 8);
11446 tw32(MAC_RX_MTU_SIZE, tx_len + ETH_FCS_LEN);
11448 if (tso_loopback) {
11449 struct iphdr *iph = (struct iphdr *)&tx_data[ETH_HLEN];
11451 u32 hdr_len = TG3_TSO_IP_HDR_LEN + TG3_TSO_TCP_HDR_LEN +
11452 TG3_TSO_TCP_OPT_LEN;
11454 memcpy(tx_data + ETH_ALEN * 2, tg3_tso_header,
11455 sizeof(tg3_tso_header));
11458 val = tx_len - ETH_ALEN * 2 - sizeof(tg3_tso_header);
11459 num_pkts = DIV_ROUND_UP(val, TG3_TSO_MSS);
11461 /* Set the total length field in the IP header */
11462 iph->tot_len = htons((u16)(mss + hdr_len));
11464 base_flags = (TXD_FLAG_CPU_PRE_DMA |
11465 TXD_FLAG_CPU_POST_DMA);
11467 if (tg3_flag(tp, HW_TSO_1) ||
11468 tg3_flag(tp, HW_TSO_2) ||
11469 tg3_flag(tp, HW_TSO_3)) {
11471 val = ETH_HLEN + TG3_TSO_IP_HDR_LEN;
11472 th = (struct tcphdr *)&tx_data[val];
11475 base_flags |= TXD_FLAG_TCPUDP_CSUM;
11477 if (tg3_flag(tp, HW_TSO_3)) {
11478 mss |= (hdr_len & 0xc) << 12;
11479 if (hdr_len & 0x10)
11480 base_flags |= 0x00000010;
11481 base_flags |= (hdr_len & 0x3e0) << 5;
11482 } else if (tg3_flag(tp, HW_TSO_2))
11483 mss |= hdr_len << 9;
11484 else if (tg3_flag(tp, HW_TSO_1) ||
11485 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705) {
11486 mss |= (TG3_TSO_TCP_OPT_LEN << 9);
11488 base_flags |= (TG3_TSO_TCP_OPT_LEN << 10);
11491 data_off = ETH_ALEN * 2 + sizeof(tg3_tso_header);
11494 data_off = ETH_HLEN;
11497 for (i = data_off; i < tx_len; i++)
11498 tx_data[i] = (u8) (i & 0xff);
11500 map = pci_map_single(tp->pdev, skb->data, tx_len, PCI_DMA_TODEVICE);
11501 if (pci_dma_mapping_error(tp->pdev, map)) {
11502 dev_kfree_skb(skb);
11506 val = tnapi->tx_prod;
11507 tnapi->tx_buffers[val].skb = skb;
11508 dma_unmap_addr_set(&tnapi->tx_buffers[val], mapping, map);
11510 tw32_f(HOSTCC_MODE, tp->coalesce_mode | HOSTCC_MODE_ENABLE |
11515 rx_start_idx = rnapi->hw_status->idx[0].rx_producer;
11517 budget = tg3_tx_avail(tnapi);
11518 if (tg3_tx_frag_set(tnapi, &val, &budget, map, tx_len,
11519 base_flags | TXD_FLAG_END, mss, 0)) {
11520 tnapi->tx_buffers[val].skb = NULL;
11521 dev_kfree_skb(skb);
11527 tw32_tx_mbox(tnapi->prodmbox, tnapi->tx_prod);
11528 tr32_mailbox(tnapi->prodmbox);
11532 /* 350 usec to allow enough time on some 10/100 Mbps devices. */
11533 for (i = 0; i < 35; i++) {
11534 tw32_f(HOSTCC_MODE, tp->coalesce_mode | HOSTCC_MODE_ENABLE |
11539 tx_idx = tnapi->hw_status->idx[0].tx_consumer;
11540 rx_idx = rnapi->hw_status->idx[0].rx_producer;
11541 if ((tx_idx == tnapi->tx_prod) &&
11542 (rx_idx == (rx_start_idx + num_pkts)))
11546 tg3_tx_skb_unmap(tnapi, tnapi->tx_prod - 1, -1);
11547 dev_kfree_skb(skb);
11549 if (tx_idx != tnapi->tx_prod)
11552 if (rx_idx != rx_start_idx + num_pkts)
11556 while (rx_idx != rx_start_idx) {
11557 desc = &rnapi->rx_rcb[rx_start_idx++];
11558 desc_idx = desc->opaque & RXD_OPAQUE_INDEX_MASK;
11559 opaque_key = desc->opaque & RXD_OPAQUE_RING_MASK;
11561 if ((desc->err_vlan & RXD_ERR_MASK) != 0 &&
11562 (desc->err_vlan != RXD_ERR_ODD_NIBBLE_RCVD_MII))
11565 rx_len = ((desc->idx_len & RXD_LEN_MASK) >> RXD_LEN_SHIFT)
11568 if (!tso_loopback) {
11569 if (rx_len != tx_len)
11572 if (pktsz <= TG3_RX_STD_DMA_SZ - ETH_FCS_LEN) {
11573 if (opaque_key != RXD_OPAQUE_RING_STD)
11576 if (opaque_key != RXD_OPAQUE_RING_JUMBO)
11579 } else if ((desc->type_flags & RXD_FLAG_TCPUDP_CSUM) &&
11580 (desc->ip_tcp_csum & RXD_TCPCSUM_MASK)
11581 >> RXD_TCPCSUM_SHIFT != 0xffff) {
11585 if (opaque_key == RXD_OPAQUE_RING_STD) {
11586 rx_data = tpr->rx_std_buffers[desc_idx].data;
11587 map = dma_unmap_addr(&tpr->rx_std_buffers[desc_idx],
11589 } else if (opaque_key == RXD_OPAQUE_RING_JUMBO) {
11590 rx_data = tpr->rx_jmb_buffers[desc_idx].data;
11591 map = dma_unmap_addr(&tpr->rx_jmb_buffers[desc_idx],
11596 pci_dma_sync_single_for_cpu(tp->pdev, map, rx_len,
11597 PCI_DMA_FROMDEVICE);
11599 rx_data += TG3_RX_OFFSET(tp);
11600 for (i = data_off; i < rx_len; i++, val++) {
11601 if (*(rx_data + i) != (u8) (val & 0xff))
11608 /* tg3_free_rings will unmap and free the rx_data */
11613 #define TG3_STD_LOOPBACK_FAILED 1
11614 #define TG3_JMB_LOOPBACK_FAILED 2
11615 #define TG3_TSO_LOOPBACK_FAILED 4
11616 #define TG3_LOOPBACK_FAILED \
11617 (TG3_STD_LOOPBACK_FAILED | \
11618 TG3_JMB_LOOPBACK_FAILED | \
11619 TG3_TSO_LOOPBACK_FAILED)
11621 static int tg3_test_loopback(struct tg3 *tp, u64 *data, bool do_extlpbk)
11626 eee_cap = tp->phy_flags & TG3_PHYFLG_EEE_CAP;
11627 tp->phy_flags &= ~TG3_PHYFLG_EEE_CAP;
11629 if (!netif_running(tp->dev)) {
11630 data[0] = TG3_LOOPBACK_FAILED;
11631 data[1] = TG3_LOOPBACK_FAILED;
11633 data[2] = TG3_LOOPBACK_FAILED;
11637 err = tg3_reset_hw(tp, 1);
11639 data[0] = TG3_LOOPBACK_FAILED;
11640 data[1] = TG3_LOOPBACK_FAILED;
11642 data[2] = TG3_LOOPBACK_FAILED;
11646 if (tg3_flag(tp, ENABLE_RSS)) {
11649 /* Reroute all rx packets to the 1st queue */
11650 for (i = MAC_RSS_INDIR_TBL_0;
11651 i < MAC_RSS_INDIR_TBL_0 + TG3_RSS_INDIR_TBL_SIZE; i += 4)
11655 /* HW errata - mac loopback fails in some cases on 5780.
11656 * Normal traffic and PHY loopback are not affected by
11657 * errata. Also, the MAC loopback test is deprecated for
11658 * all newer ASIC revisions.
11660 if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5780 &&
11661 !tg3_flag(tp, CPMU_PRESENT)) {
11662 tg3_mac_loopback(tp, true);
11664 if (tg3_run_loopback(tp, ETH_FRAME_LEN, false))
11665 data[0] |= TG3_STD_LOOPBACK_FAILED;
11667 if (tg3_flag(tp, JUMBO_RING_ENABLE) &&
11668 tg3_run_loopback(tp, 9000 + ETH_HLEN, false))
11669 data[0] |= TG3_JMB_LOOPBACK_FAILED;
11671 tg3_mac_loopback(tp, false);
11674 if (!(tp->phy_flags & TG3_PHYFLG_PHY_SERDES) &&
11675 !tg3_flag(tp, USE_PHYLIB)) {
11678 tg3_phy_lpbk_set(tp, 0, false);
11680 /* Wait for link */
11681 for (i = 0; i < 100; i++) {
11682 if (tr32(MAC_TX_STATUS) & TX_STATUS_LINK_UP)
11687 if (tg3_run_loopback(tp, ETH_FRAME_LEN, false))
11688 data[1] |= TG3_STD_LOOPBACK_FAILED;
11689 if (tg3_flag(tp, TSO_CAPABLE) &&
11690 tg3_run_loopback(tp, ETH_FRAME_LEN, true))
11691 data[1] |= TG3_TSO_LOOPBACK_FAILED;
11692 if (tg3_flag(tp, JUMBO_RING_ENABLE) &&
11693 tg3_run_loopback(tp, 9000 + ETH_HLEN, false))
11694 data[1] |= TG3_JMB_LOOPBACK_FAILED;
11697 tg3_phy_lpbk_set(tp, 0, true);
11699 /* All link indications report up, but the hardware
11700 * isn't really ready for about 20 msec. Double it
11705 if (tg3_run_loopback(tp, ETH_FRAME_LEN, false))
11706 data[2] |= TG3_STD_LOOPBACK_FAILED;
11707 if (tg3_flag(tp, TSO_CAPABLE) &&
11708 tg3_run_loopback(tp, ETH_FRAME_LEN, true))
11709 data[2] |= TG3_TSO_LOOPBACK_FAILED;
11710 if (tg3_flag(tp, JUMBO_RING_ENABLE) &&
11711 tg3_run_loopback(tp, 9000 + ETH_HLEN, false))
11712 data[2] |= TG3_JMB_LOOPBACK_FAILED;
11715 /* Re-enable gphy autopowerdown. */
11716 if (tp->phy_flags & TG3_PHYFLG_ENABLE_APD)
11717 tg3_phy_toggle_apd(tp, true);
11720 err = (data[0] | data[1] | data[2]) ? -EIO : 0;
11723 tp->phy_flags |= eee_cap;
11728 static void tg3_self_test(struct net_device *dev, struct ethtool_test *etest,
11731 struct tg3 *tp = netdev_priv(dev);
11732 bool doextlpbk = etest->flags & ETH_TEST_FL_EXTERNAL_LB;
11734 if ((tp->phy_flags & TG3_PHYFLG_IS_LOW_POWER) &&
11735 tg3_power_up(tp)) {
11736 etest->flags |= ETH_TEST_FL_FAILED;
11737 memset(data, 1, sizeof(u64) * TG3_NUM_TEST);
11741 memset(data, 0, sizeof(u64) * TG3_NUM_TEST);
11743 if (tg3_test_nvram(tp) != 0) {
11744 etest->flags |= ETH_TEST_FL_FAILED;
11747 if (!doextlpbk && tg3_test_link(tp)) {
11748 etest->flags |= ETH_TEST_FL_FAILED;
11751 if (etest->flags & ETH_TEST_FL_OFFLINE) {
11752 int err, err2 = 0, irq_sync = 0;
11754 if (netif_running(dev)) {
11756 tg3_netif_stop(tp);
11760 tg3_full_lock(tp, irq_sync);
11762 tg3_halt(tp, RESET_KIND_SUSPEND, 1);
11763 err = tg3_nvram_lock(tp);
11764 tg3_halt_cpu(tp, RX_CPU_BASE);
11765 if (!tg3_flag(tp, 5705_PLUS))
11766 tg3_halt_cpu(tp, TX_CPU_BASE);
11768 tg3_nvram_unlock(tp);
11770 if (tp->phy_flags & TG3_PHYFLG_MII_SERDES)
11773 if (tg3_test_registers(tp) != 0) {
11774 etest->flags |= ETH_TEST_FL_FAILED;
11778 if (tg3_test_memory(tp) != 0) {
11779 etest->flags |= ETH_TEST_FL_FAILED;
11784 etest->flags |= ETH_TEST_FL_EXTERNAL_LB_DONE;
11786 if (tg3_test_loopback(tp, &data[4], doextlpbk))
11787 etest->flags |= ETH_TEST_FL_FAILED;
11789 tg3_full_unlock(tp);
11791 if (tg3_test_interrupt(tp) != 0) {
11792 etest->flags |= ETH_TEST_FL_FAILED;
11796 tg3_full_lock(tp, 0);
11798 tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
11799 if (netif_running(dev)) {
11800 tg3_flag_set(tp, INIT_COMPLETE);
11801 err2 = tg3_restart_hw(tp, 1);
11803 tg3_netif_start(tp);
11806 tg3_full_unlock(tp);
11808 if (irq_sync && !err2)
11811 if (tp->phy_flags & TG3_PHYFLG_IS_LOW_POWER)
11812 tg3_power_down(tp);
11816 static int tg3_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd)
11818 struct mii_ioctl_data *data = if_mii(ifr);
11819 struct tg3 *tp = netdev_priv(dev);
11822 if (tg3_flag(tp, USE_PHYLIB)) {
11823 struct phy_device *phydev;
11824 if (!(tp->phy_flags & TG3_PHYFLG_IS_CONNECTED))
11826 phydev = tp->mdio_bus->phy_map[TG3_PHY_MII_ADDR];
11827 return phy_mii_ioctl(phydev, ifr, cmd);
11832 data->phy_id = tp->phy_addr;
11835 case SIOCGMIIREG: {
11838 if (tp->phy_flags & TG3_PHYFLG_PHY_SERDES)
11839 break; /* We have no PHY */
11841 if (!netif_running(dev))
11844 spin_lock_bh(&tp->lock);
11845 err = tg3_readphy(tp, data->reg_num & 0x1f, &mii_regval);
11846 spin_unlock_bh(&tp->lock);
11848 data->val_out = mii_regval;
11854 if (tp->phy_flags & TG3_PHYFLG_PHY_SERDES)
11855 break; /* We have no PHY */
11857 if (!netif_running(dev))
11860 spin_lock_bh(&tp->lock);
11861 err = tg3_writephy(tp, data->reg_num & 0x1f, data->val_in);
11862 spin_unlock_bh(&tp->lock);
11870 return -EOPNOTSUPP;
11873 static int tg3_get_coalesce(struct net_device *dev, struct ethtool_coalesce *ec)
11875 struct tg3 *tp = netdev_priv(dev);
11877 memcpy(ec, &tp->coal, sizeof(*ec));
11881 static int tg3_set_coalesce(struct net_device *dev, struct ethtool_coalesce *ec)
11883 struct tg3 *tp = netdev_priv(dev);
11884 u32 max_rxcoal_tick_int = 0, max_txcoal_tick_int = 0;
11885 u32 max_stat_coal_ticks = 0, min_stat_coal_ticks = 0;
11887 if (!tg3_flag(tp, 5705_PLUS)) {
11888 max_rxcoal_tick_int = MAX_RXCOAL_TICK_INT;
11889 max_txcoal_tick_int = MAX_TXCOAL_TICK_INT;
11890 max_stat_coal_ticks = MAX_STAT_COAL_TICKS;
11891 min_stat_coal_ticks = MIN_STAT_COAL_TICKS;
11894 if ((ec->rx_coalesce_usecs > MAX_RXCOL_TICKS) ||
11895 (ec->tx_coalesce_usecs > MAX_TXCOL_TICKS) ||
11896 (ec->rx_max_coalesced_frames > MAX_RXMAX_FRAMES) ||
11897 (ec->tx_max_coalesced_frames > MAX_TXMAX_FRAMES) ||
11898 (ec->rx_coalesce_usecs_irq > max_rxcoal_tick_int) ||
11899 (ec->tx_coalesce_usecs_irq > max_txcoal_tick_int) ||
11900 (ec->rx_max_coalesced_frames_irq > MAX_RXCOAL_MAXF_INT) ||
11901 (ec->tx_max_coalesced_frames_irq > MAX_TXCOAL_MAXF_INT) ||
11902 (ec->stats_block_coalesce_usecs > max_stat_coal_ticks) ||
11903 (ec->stats_block_coalesce_usecs < min_stat_coal_ticks))
11906 /* No rx interrupts will be generated if both are zero */
11907 if ((ec->rx_coalesce_usecs == 0) &&
11908 (ec->rx_max_coalesced_frames == 0))
11911 /* No tx interrupts will be generated if both are zero */
11912 if ((ec->tx_coalesce_usecs == 0) &&
11913 (ec->tx_max_coalesced_frames == 0))
11916 /* Only copy relevant parameters, ignore all others. */
11917 tp->coal.rx_coalesce_usecs = ec->rx_coalesce_usecs;
11918 tp->coal.tx_coalesce_usecs = ec->tx_coalesce_usecs;
11919 tp->coal.rx_max_coalesced_frames = ec->rx_max_coalesced_frames;
11920 tp->coal.tx_max_coalesced_frames = ec->tx_max_coalesced_frames;
11921 tp->coal.rx_coalesce_usecs_irq = ec->rx_coalesce_usecs_irq;
11922 tp->coal.tx_coalesce_usecs_irq = ec->tx_coalesce_usecs_irq;
11923 tp->coal.rx_max_coalesced_frames_irq = ec->rx_max_coalesced_frames_irq;
11924 tp->coal.tx_max_coalesced_frames_irq = ec->tx_max_coalesced_frames_irq;
11925 tp->coal.stats_block_coalesce_usecs = ec->stats_block_coalesce_usecs;
11927 if (netif_running(dev)) {
11928 tg3_full_lock(tp, 0);
11929 __tg3_set_coalesce(tp, &tp->coal);
11930 tg3_full_unlock(tp);
11935 static const struct ethtool_ops tg3_ethtool_ops = {
11936 .get_settings = tg3_get_settings,
11937 .set_settings = tg3_set_settings,
11938 .get_drvinfo = tg3_get_drvinfo,
11939 .get_regs_len = tg3_get_regs_len,
11940 .get_regs = tg3_get_regs,
11941 .get_wol = tg3_get_wol,
11942 .set_wol = tg3_set_wol,
11943 .get_msglevel = tg3_get_msglevel,
11944 .set_msglevel = tg3_set_msglevel,
11945 .nway_reset = tg3_nway_reset,
11946 .get_link = ethtool_op_get_link,
11947 .get_eeprom_len = tg3_get_eeprom_len,
11948 .get_eeprom = tg3_get_eeprom,
11949 .set_eeprom = tg3_set_eeprom,
11950 .get_ringparam = tg3_get_ringparam,
11951 .set_ringparam = tg3_set_ringparam,
11952 .get_pauseparam = tg3_get_pauseparam,
11953 .set_pauseparam = tg3_set_pauseparam,
11954 .self_test = tg3_self_test,
11955 .get_strings = tg3_get_strings,
11956 .set_phys_id = tg3_set_phys_id,
11957 .get_ethtool_stats = tg3_get_ethtool_stats,
11958 .get_coalesce = tg3_get_coalesce,
11959 .set_coalesce = tg3_set_coalesce,
11960 .get_sset_count = tg3_get_sset_count,
11961 .get_rxnfc = tg3_get_rxnfc,
11962 .get_rxfh_indir_size = tg3_get_rxfh_indir_size,
11963 .get_rxfh_indir = tg3_get_rxfh_indir,
11964 .set_rxfh_indir = tg3_set_rxfh_indir,
11967 static void tg3_set_rx_mode(struct net_device *dev)
11969 struct tg3 *tp = netdev_priv(dev);
11971 if (!netif_running(dev))
11974 tg3_full_lock(tp, 0);
11975 __tg3_set_rx_mode(dev);
11976 tg3_full_unlock(tp);
11979 static inline void tg3_set_mtu(struct net_device *dev, struct tg3 *tp,
11982 dev->mtu = new_mtu;
11984 if (new_mtu > ETH_DATA_LEN) {
11985 if (tg3_flag(tp, 5780_CLASS)) {
11986 netdev_update_features(dev);
11987 tg3_flag_clear(tp, TSO_CAPABLE);
11989 tg3_flag_set(tp, JUMBO_RING_ENABLE);
11992 if (tg3_flag(tp, 5780_CLASS)) {
11993 tg3_flag_set(tp, TSO_CAPABLE);
11994 netdev_update_features(dev);
11996 tg3_flag_clear(tp, JUMBO_RING_ENABLE);
12000 static int tg3_change_mtu(struct net_device *dev, int new_mtu)
12002 struct tg3 *tp = netdev_priv(dev);
12005 if (new_mtu < TG3_MIN_MTU || new_mtu > TG3_MAX_MTU(tp))
12008 if (!netif_running(dev)) {
12009 /* We'll just catch it later when the
12012 tg3_set_mtu(dev, tp, new_mtu);
12018 tg3_netif_stop(tp);
12020 tg3_full_lock(tp, 1);
12022 tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
12024 tg3_set_mtu(dev, tp, new_mtu);
12026 err = tg3_restart_hw(tp, 0);
12029 tg3_netif_start(tp);
12031 tg3_full_unlock(tp);
12039 static const struct net_device_ops tg3_netdev_ops = {
12040 .ndo_open = tg3_open,
12041 .ndo_stop = tg3_close,
12042 .ndo_start_xmit = tg3_start_xmit,
12043 .ndo_get_stats64 = tg3_get_stats64,
12044 .ndo_validate_addr = eth_validate_addr,
12045 .ndo_set_rx_mode = tg3_set_rx_mode,
12046 .ndo_set_mac_address = tg3_set_mac_addr,
12047 .ndo_do_ioctl = tg3_ioctl,
12048 .ndo_tx_timeout = tg3_tx_timeout,
12049 .ndo_change_mtu = tg3_change_mtu,
12050 .ndo_fix_features = tg3_fix_features,
12051 .ndo_set_features = tg3_set_features,
12052 #ifdef CONFIG_NET_POLL_CONTROLLER
12053 .ndo_poll_controller = tg3_poll_controller,
12057 static void __devinit tg3_get_eeprom_size(struct tg3 *tp)
12059 u32 cursize, val, magic;
12061 tp->nvram_size = EEPROM_CHIP_SIZE;
12063 if (tg3_nvram_read(tp, 0, &magic) != 0)
12066 if ((magic != TG3_EEPROM_MAGIC) &&
12067 ((magic & TG3_EEPROM_MAGIC_FW_MSK) != TG3_EEPROM_MAGIC_FW) &&
12068 ((magic & TG3_EEPROM_MAGIC_HW_MSK) != TG3_EEPROM_MAGIC_HW))
12072 * Size the chip by reading offsets at increasing powers of two.
12073 * When we encounter our validation signature, we know the addressing
12074 * has wrapped around, and thus have our chip size.
12078 while (cursize < tp->nvram_size) {
12079 if (tg3_nvram_read(tp, cursize, &val) != 0)
12088 tp->nvram_size = cursize;
12091 static void __devinit tg3_get_nvram_size(struct tg3 *tp)
12095 if (tg3_flag(tp, NO_NVRAM) || tg3_nvram_read(tp, 0, &val) != 0)
12098 /* Selfboot format */
12099 if (val != TG3_EEPROM_MAGIC) {
12100 tg3_get_eeprom_size(tp);
12104 if (tg3_nvram_read(tp, 0xf0, &val) == 0) {
12106 /* This is confusing. We want to operate on the
12107 * 16-bit value at offset 0xf2. The tg3_nvram_read()
12108 * call will read from NVRAM and byteswap the data
12109 * according to the byteswapping settings for all
12110 * other register accesses. This ensures the data we
12111 * want will always reside in the lower 16-bits.
12112 * However, the data in NVRAM is in LE format, which
12113 * means the data from the NVRAM read will always be
12114 * opposite the endianness of the CPU. The 16-bit
12115 * byteswap then brings the data to CPU endianness.
12117 tp->nvram_size = swab16((u16)(val & 0x0000ffff)) * 1024;
12121 tp->nvram_size = TG3_NVRAM_SIZE_512KB;
12124 static void __devinit tg3_get_nvram_info(struct tg3 *tp)
12128 nvcfg1 = tr32(NVRAM_CFG1);
12129 if (nvcfg1 & NVRAM_CFG1_FLASHIF_ENAB) {
12130 tg3_flag_set(tp, FLASH);
12132 nvcfg1 &= ~NVRAM_CFG1_COMPAT_BYPASS;
12133 tw32(NVRAM_CFG1, nvcfg1);
12136 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5750 ||
12137 tg3_flag(tp, 5780_CLASS)) {
12138 switch (nvcfg1 & NVRAM_CFG1_VENDOR_MASK) {
12139 case FLASH_VENDOR_ATMEL_FLASH_BUFFERED:
12140 tp->nvram_jedecnum = JEDEC_ATMEL;
12141 tp->nvram_pagesize = ATMEL_AT45DB0X1B_PAGE_SIZE;
12142 tg3_flag_set(tp, NVRAM_BUFFERED);
12144 case FLASH_VENDOR_ATMEL_FLASH_UNBUFFERED:
12145 tp->nvram_jedecnum = JEDEC_ATMEL;
12146 tp->nvram_pagesize = ATMEL_AT25F512_PAGE_SIZE;
12148 case FLASH_VENDOR_ATMEL_EEPROM:
12149 tp->nvram_jedecnum = JEDEC_ATMEL;
12150 tp->nvram_pagesize = ATMEL_AT24C512_CHIP_SIZE;
12151 tg3_flag_set(tp, NVRAM_BUFFERED);
12153 case FLASH_VENDOR_ST:
12154 tp->nvram_jedecnum = JEDEC_ST;
12155 tp->nvram_pagesize = ST_M45PEX0_PAGE_SIZE;
12156 tg3_flag_set(tp, NVRAM_BUFFERED);
12158 case FLASH_VENDOR_SAIFUN:
12159 tp->nvram_jedecnum = JEDEC_SAIFUN;
12160 tp->nvram_pagesize = SAIFUN_SA25F0XX_PAGE_SIZE;
12162 case FLASH_VENDOR_SST_SMALL:
12163 case FLASH_VENDOR_SST_LARGE:
12164 tp->nvram_jedecnum = JEDEC_SST;
12165 tp->nvram_pagesize = SST_25VF0X0_PAGE_SIZE;
12169 tp->nvram_jedecnum = JEDEC_ATMEL;
12170 tp->nvram_pagesize = ATMEL_AT45DB0X1B_PAGE_SIZE;
12171 tg3_flag_set(tp, NVRAM_BUFFERED);
12175 static void __devinit tg3_nvram_get_pagesize(struct tg3 *tp, u32 nvmcfg1)
12177 switch (nvmcfg1 & NVRAM_CFG1_5752PAGE_SIZE_MASK) {
12178 case FLASH_5752PAGE_SIZE_256:
12179 tp->nvram_pagesize = 256;
12181 case FLASH_5752PAGE_SIZE_512:
12182 tp->nvram_pagesize = 512;
12184 case FLASH_5752PAGE_SIZE_1K:
12185 tp->nvram_pagesize = 1024;
12187 case FLASH_5752PAGE_SIZE_2K:
12188 tp->nvram_pagesize = 2048;
12190 case FLASH_5752PAGE_SIZE_4K:
12191 tp->nvram_pagesize = 4096;
12193 case FLASH_5752PAGE_SIZE_264:
12194 tp->nvram_pagesize = 264;
12196 case FLASH_5752PAGE_SIZE_528:
12197 tp->nvram_pagesize = 528;
12202 static void __devinit tg3_get_5752_nvram_info(struct tg3 *tp)
12206 nvcfg1 = tr32(NVRAM_CFG1);
12208 /* NVRAM protection for TPM */
12209 if (nvcfg1 & (1 << 27))
12210 tg3_flag_set(tp, PROTECTED_NVRAM);
12212 switch (nvcfg1 & NVRAM_CFG1_5752VENDOR_MASK) {
12213 case FLASH_5752VENDOR_ATMEL_EEPROM_64KHZ:
12214 case FLASH_5752VENDOR_ATMEL_EEPROM_376KHZ:
12215 tp->nvram_jedecnum = JEDEC_ATMEL;
12216 tg3_flag_set(tp, NVRAM_BUFFERED);
12218 case FLASH_5752VENDOR_ATMEL_FLASH_BUFFERED:
12219 tp->nvram_jedecnum = JEDEC_ATMEL;
12220 tg3_flag_set(tp, NVRAM_BUFFERED);
12221 tg3_flag_set(tp, FLASH);
12223 case FLASH_5752VENDOR_ST_M45PE10:
12224 case FLASH_5752VENDOR_ST_M45PE20:
12225 case FLASH_5752VENDOR_ST_M45PE40:
12226 tp->nvram_jedecnum = JEDEC_ST;
12227 tg3_flag_set(tp, NVRAM_BUFFERED);
12228 tg3_flag_set(tp, FLASH);
12232 if (tg3_flag(tp, FLASH)) {
12233 tg3_nvram_get_pagesize(tp, nvcfg1);
12235 /* For eeprom, set pagesize to maximum eeprom size */
12236 tp->nvram_pagesize = ATMEL_AT24C512_CHIP_SIZE;
12238 nvcfg1 &= ~NVRAM_CFG1_COMPAT_BYPASS;
12239 tw32(NVRAM_CFG1, nvcfg1);
12243 static void __devinit tg3_get_5755_nvram_info(struct tg3 *tp)
12245 u32 nvcfg1, protect = 0;
12247 nvcfg1 = tr32(NVRAM_CFG1);
12249 /* NVRAM protection for TPM */
12250 if (nvcfg1 & (1 << 27)) {
12251 tg3_flag_set(tp, PROTECTED_NVRAM);
12255 nvcfg1 &= NVRAM_CFG1_5752VENDOR_MASK;
12257 case FLASH_5755VENDOR_ATMEL_FLASH_1:
12258 case FLASH_5755VENDOR_ATMEL_FLASH_2:
12259 case FLASH_5755VENDOR_ATMEL_FLASH_3:
12260 case FLASH_5755VENDOR_ATMEL_FLASH_5:
12261 tp->nvram_jedecnum = JEDEC_ATMEL;
12262 tg3_flag_set(tp, NVRAM_BUFFERED);
12263 tg3_flag_set(tp, FLASH);
12264 tp->nvram_pagesize = 264;
12265 if (nvcfg1 == FLASH_5755VENDOR_ATMEL_FLASH_1 ||
12266 nvcfg1 == FLASH_5755VENDOR_ATMEL_FLASH_5)
12267 tp->nvram_size = (protect ? 0x3e200 :
12268 TG3_NVRAM_SIZE_512KB);
12269 else if (nvcfg1 == FLASH_5755VENDOR_ATMEL_FLASH_2)
12270 tp->nvram_size = (protect ? 0x1f200 :
12271 TG3_NVRAM_SIZE_256KB);
12273 tp->nvram_size = (protect ? 0x1f200 :
12274 TG3_NVRAM_SIZE_128KB);
12276 case FLASH_5752VENDOR_ST_M45PE10:
12277 case FLASH_5752VENDOR_ST_M45PE20:
12278 case FLASH_5752VENDOR_ST_M45PE40:
12279 tp->nvram_jedecnum = JEDEC_ST;
12280 tg3_flag_set(tp, NVRAM_BUFFERED);
12281 tg3_flag_set(tp, FLASH);
12282 tp->nvram_pagesize = 256;
12283 if (nvcfg1 == FLASH_5752VENDOR_ST_M45PE10)
12284 tp->nvram_size = (protect ?
12285 TG3_NVRAM_SIZE_64KB :
12286 TG3_NVRAM_SIZE_128KB);
12287 else if (nvcfg1 == FLASH_5752VENDOR_ST_M45PE20)
12288 tp->nvram_size = (protect ?
12289 TG3_NVRAM_SIZE_64KB :
12290 TG3_NVRAM_SIZE_256KB);
12292 tp->nvram_size = (protect ?
12293 TG3_NVRAM_SIZE_128KB :
12294 TG3_NVRAM_SIZE_512KB);
12299 static void __devinit tg3_get_5787_nvram_info(struct tg3 *tp)
12303 nvcfg1 = tr32(NVRAM_CFG1);
12305 switch (nvcfg1 & NVRAM_CFG1_5752VENDOR_MASK) {
12306 case FLASH_5787VENDOR_ATMEL_EEPROM_64KHZ:
12307 case FLASH_5787VENDOR_ATMEL_EEPROM_376KHZ:
12308 case FLASH_5787VENDOR_MICRO_EEPROM_64KHZ:
12309 case FLASH_5787VENDOR_MICRO_EEPROM_376KHZ:
12310 tp->nvram_jedecnum = JEDEC_ATMEL;
12311 tg3_flag_set(tp, NVRAM_BUFFERED);
12312 tp->nvram_pagesize = ATMEL_AT24C512_CHIP_SIZE;
12314 nvcfg1 &= ~NVRAM_CFG1_COMPAT_BYPASS;
12315 tw32(NVRAM_CFG1, nvcfg1);
12317 case FLASH_5752VENDOR_ATMEL_FLASH_BUFFERED:
12318 case FLASH_5755VENDOR_ATMEL_FLASH_1:
12319 case FLASH_5755VENDOR_ATMEL_FLASH_2:
12320 case FLASH_5755VENDOR_ATMEL_FLASH_3:
12321 tp->nvram_jedecnum = JEDEC_ATMEL;
12322 tg3_flag_set(tp, NVRAM_BUFFERED);
12323 tg3_flag_set(tp, FLASH);
12324 tp->nvram_pagesize = 264;
12326 case FLASH_5752VENDOR_ST_M45PE10:
12327 case FLASH_5752VENDOR_ST_M45PE20:
12328 case FLASH_5752VENDOR_ST_M45PE40:
12329 tp->nvram_jedecnum = JEDEC_ST;
12330 tg3_flag_set(tp, NVRAM_BUFFERED);
12331 tg3_flag_set(tp, FLASH);
12332 tp->nvram_pagesize = 256;
12337 static void __devinit tg3_get_5761_nvram_info(struct tg3 *tp)
12339 u32 nvcfg1, protect = 0;
12341 nvcfg1 = tr32(NVRAM_CFG1);
12343 /* NVRAM protection for TPM */
12344 if (nvcfg1 & (1 << 27)) {
12345 tg3_flag_set(tp, PROTECTED_NVRAM);
12349 nvcfg1 &= NVRAM_CFG1_5752VENDOR_MASK;
12351 case FLASH_5761VENDOR_ATMEL_ADB021D:
12352 case FLASH_5761VENDOR_ATMEL_ADB041D:
12353 case FLASH_5761VENDOR_ATMEL_ADB081D:
12354 case FLASH_5761VENDOR_ATMEL_ADB161D:
12355 case FLASH_5761VENDOR_ATMEL_MDB021D:
12356 case FLASH_5761VENDOR_ATMEL_MDB041D:
12357 case FLASH_5761VENDOR_ATMEL_MDB081D:
12358 case FLASH_5761VENDOR_ATMEL_MDB161D:
12359 tp->nvram_jedecnum = JEDEC_ATMEL;
12360 tg3_flag_set(tp, NVRAM_BUFFERED);
12361 tg3_flag_set(tp, FLASH);
12362 tg3_flag_set(tp, NO_NVRAM_ADDR_TRANS);
12363 tp->nvram_pagesize = 256;
12365 case FLASH_5761VENDOR_ST_A_M45PE20:
12366 case FLASH_5761VENDOR_ST_A_M45PE40:
12367 case FLASH_5761VENDOR_ST_A_M45PE80:
12368 case FLASH_5761VENDOR_ST_A_M45PE16:
12369 case FLASH_5761VENDOR_ST_M_M45PE20:
12370 case FLASH_5761VENDOR_ST_M_M45PE40:
12371 case FLASH_5761VENDOR_ST_M_M45PE80:
12372 case FLASH_5761VENDOR_ST_M_M45PE16:
12373 tp->nvram_jedecnum = JEDEC_ST;
12374 tg3_flag_set(tp, NVRAM_BUFFERED);
12375 tg3_flag_set(tp, FLASH);
12376 tp->nvram_pagesize = 256;
12381 tp->nvram_size = tr32(NVRAM_ADDR_LOCKOUT);
12384 case FLASH_5761VENDOR_ATMEL_ADB161D:
12385 case FLASH_5761VENDOR_ATMEL_MDB161D:
12386 case FLASH_5761VENDOR_ST_A_M45PE16:
12387 case FLASH_5761VENDOR_ST_M_M45PE16:
12388 tp->nvram_size = TG3_NVRAM_SIZE_2MB;
12390 case FLASH_5761VENDOR_ATMEL_ADB081D:
12391 case FLASH_5761VENDOR_ATMEL_MDB081D:
12392 case FLASH_5761VENDOR_ST_A_M45PE80:
12393 case FLASH_5761VENDOR_ST_M_M45PE80:
12394 tp->nvram_size = TG3_NVRAM_SIZE_1MB;
12396 case FLASH_5761VENDOR_ATMEL_ADB041D:
12397 case FLASH_5761VENDOR_ATMEL_MDB041D:
12398 case FLASH_5761VENDOR_ST_A_M45PE40:
12399 case FLASH_5761VENDOR_ST_M_M45PE40:
12400 tp->nvram_size = TG3_NVRAM_SIZE_512KB;
12402 case FLASH_5761VENDOR_ATMEL_ADB021D:
12403 case FLASH_5761VENDOR_ATMEL_MDB021D:
12404 case FLASH_5761VENDOR_ST_A_M45PE20:
12405 case FLASH_5761VENDOR_ST_M_M45PE20:
12406 tp->nvram_size = TG3_NVRAM_SIZE_256KB;
12412 static void __devinit tg3_get_5906_nvram_info(struct tg3 *tp)
12414 tp->nvram_jedecnum = JEDEC_ATMEL;
12415 tg3_flag_set(tp, NVRAM_BUFFERED);
12416 tp->nvram_pagesize = ATMEL_AT24C512_CHIP_SIZE;
12419 static void __devinit tg3_get_57780_nvram_info(struct tg3 *tp)
12423 nvcfg1 = tr32(NVRAM_CFG1);
12425 switch (nvcfg1 & NVRAM_CFG1_5752VENDOR_MASK) {
12426 case FLASH_5787VENDOR_ATMEL_EEPROM_376KHZ:
12427 case FLASH_5787VENDOR_MICRO_EEPROM_376KHZ:
12428 tp->nvram_jedecnum = JEDEC_ATMEL;
12429 tg3_flag_set(tp, NVRAM_BUFFERED);
12430 tp->nvram_pagesize = ATMEL_AT24C512_CHIP_SIZE;
12432 nvcfg1 &= ~NVRAM_CFG1_COMPAT_BYPASS;
12433 tw32(NVRAM_CFG1, nvcfg1);
12435 case FLASH_5752VENDOR_ATMEL_FLASH_BUFFERED:
12436 case FLASH_57780VENDOR_ATMEL_AT45DB011D:
12437 case FLASH_57780VENDOR_ATMEL_AT45DB011B:
12438 case FLASH_57780VENDOR_ATMEL_AT45DB021D:
12439 case FLASH_57780VENDOR_ATMEL_AT45DB021B:
12440 case FLASH_57780VENDOR_ATMEL_AT45DB041D:
12441 case FLASH_57780VENDOR_ATMEL_AT45DB041B:
12442 tp->nvram_jedecnum = JEDEC_ATMEL;
12443 tg3_flag_set(tp, NVRAM_BUFFERED);
12444 tg3_flag_set(tp, FLASH);
12446 switch (nvcfg1 & NVRAM_CFG1_5752VENDOR_MASK) {
12447 case FLASH_5752VENDOR_ATMEL_FLASH_BUFFERED:
12448 case FLASH_57780VENDOR_ATMEL_AT45DB011D:
12449 case FLASH_57780VENDOR_ATMEL_AT45DB011B:
12450 tp->nvram_size = TG3_NVRAM_SIZE_128KB;
12452 case FLASH_57780VENDOR_ATMEL_AT45DB021D:
12453 case FLASH_57780VENDOR_ATMEL_AT45DB021B:
12454 tp->nvram_size = TG3_NVRAM_SIZE_256KB;
12456 case FLASH_57780VENDOR_ATMEL_AT45DB041D:
12457 case FLASH_57780VENDOR_ATMEL_AT45DB041B:
12458 tp->nvram_size = TG3_NVRAM_SIZE_512KB;
12462 case FLASH_5752VENDOR_ST_M45PE10:
12463 case FLASH_5752VENDOR_ST_M45PE20:
12464 case FLASH_5752VENDOR_ST_M45PE40:
12465 tp->nvram_jedecnum = JEDEC_ST;
12466 tg3_flag_set(tp, NVRAM_BUFFERED);
12467 tg3_flag_set(tp, FLASH);
12469 switch (nvcfg1 & NVRAM_CFG1_5752VENDOR_MASK) {
12470 case FLASH_5752VENDOR_ST_M45PE10:
12471 tp->nvram_size = TG3_NVRAM_SIZE_128KB;
12473 case FLASH_5752VENDOR_ST_M45PE20:
12474 tp->nvram_size = TG3_NVRAM_SIZE_256KB;
12476 case FLASH_5752VENDOR_ST_M45PE40:
12477 tp->nvram_size = TG3_NVRAM_SIZE_512KB;
12482 tg3_flag_set(tp, NO_NVRAM);
12486 tg3_nvram_get_pagesize(tp, nvcfg1);
12487 if (tp->nvram_pagesize != 264 && tp->nvram_pagesize != 528)
12488 tg3_flag_set(tp, NO_NVRAM_ADDR_TRANS);
12492 static void __devinit tg3_get_5717_nvram_info(struct tg3 *tp)
12496 nvcfg1 = tr32(NVRAM_CFG1);
12498 switch (nvcfg1 & NVRAM_CFG1_5752VENDOR_MASK) {
12499 case FLASH_5717VENDOR_ATMEL_EEPROM:
12500 case FLASH_5717VENDOR_MICRO_EEPROM:
12501 tp->nvram_jedecnum = JEDEC_ATMEL;
12502 tg3_flag_set(tp, NVRAM_BUFFERED);
12503 tp->nvram_pagesize = ATMEL_AT24C512_CHIP_SIZE;
12505 nvcfg1 &= ~NVRAM_CFG1_COMPAT_BYPASS;
12506 tw32(NVRAM_CFG1, nvcfg1);
12508 case FLASH_5717VENDOR_ATMEL_MDB011D:
12509 case FLASH_5717VENDOR_ATMEL_ADB011B:
12510 case FLASH_5717VENDOR_ATMEL_ADB011D:
12511 case FLASH_5717VENDOR_ATMEL_MDB021D:
12512 case FLASH_5717VENDOR_ATMEL_ADB021B:
12513 case FLASH_5717VENDOR_ATMEL_ADB021D:
12514 case FLASH_5717VENDOR_ATMEL_45USPT:
12515 tp->nvram_jedecnum = JEDEC_ATMEL;
12516 tg3_flag_set(tp, NVRAM_BUFFERED);
12517 tg3_flag_set(tp, FLASH);
12519 switch (nvcfg1 & NVRAM_CFG1_5752VENDOR_MASK) {
12520 case FLASH_5717VENDOR_ATMEL_MDB021D:
12521 /* Detect size with tg3_nvram_get_size() */
12523 case FLASH_5717VENDOR_ATMEL_ADB021B:
12524 case FLASH_5717VENDOR_ATMEL_ADB021D:
12525 tp->nvram_size = TG3_NVRAM_SIZE_256KB;
12528 tp->nvram_size = TG3_NVRAM_SIZE_128KB;
12532 case FLASH_5717VENDOR_ST_M_M25PE10:
12533 case FLASH_5717VENDOR_ST_A_M25PE10:
12534 case FLASH_5717VENDOR_ST_M_M45PE10:
12535 case FLASH_5717VENDOR_ST_A_M45PE10:
12536 case FLASH_5717VENDOR_ST_M_M25PE20:
12537 case FLASH_5717VENDOR_ST_A_M25PE20:
12538 case FLASH_5717VENDOR_ST_M_M45PE20:
12539 case FLASH_5717VENDOR_ST_A_M45PE20:
12540 case FLASH_5717VENDOR_ST_25USPT:
12541 case FLASH_5717VENDOR_ST_45USPT:
12542 tp->nvram_jedecnum = JEDEC_ST;
12543 tg3_flag_set(tp, NVRAM_BUFFERED);
12544 tg3_flag_set(tp, FLASH);
12546 switch (nvcfg1 & NVRAM_CFG1_5752VENDOR_MASK) {
12547 case FLASH_5717VENDOR_ST_M_M25PE20:
12548 case FLASH_5717VENDOR_ST_M_M45PE20:
12549 /* Detect size with tg3_nvram_get_size() */
12551 case FLASH_5717VENDOR_ST_A_M25PE20:
12552 case FLASH_5717VENDOR_ST_A_M45PE20:
12553 tp->nvram_size = TG3_NVRAM_SIZE_256KB;
12556 tp->nvram_size = TG3_NVRAM_SIZE_128KB;
12561 tg3_flag_set(tp, NO_NVRAM);
12565 tg3_nvram_get_pagesize(tp, nvcfg1);
12566 if (tp->nvram_pagesize != 264 && tp->nvram_pagesize != 528)
12567 tg3_flag_set(tp, NO_NVRAM_ADDR_TRANS);
12570 static void __devinit tg3_get_5720_nvram_info(struct tg3 *tp)
12572 u32 nvcfg1, nvmpinstrp;
12574 nvcfg1 = tr32(NVRAM_CFG1);
12575 nvmpinstrp = nvcfg1 & NVRAM_CFG1_5752VENDOR_MASK;
12577 switch (nvmpinstrp) {
12578 case FLASH_5720_EEPROM_HD:
12579 case FLASH_5720_EEPROM_LD:
12580 tp->nvram_jedecnum = JEDEC_ATMEL;
12581 tg3_flag_set(tp, NVRAM_BUFFERED);
12583 nvcfg1 &= ~NVRAM_CFG1_COMPAT_BYPASS;
12584 tw32(NVRAM_CFG1, nvcfg1);
12585 if (nvmpinstrp == FLASH_5720_EEPROM_HD)
12586 tp->nvram_pagesize = ATMEL_AT24C512_CHIP_SIZE;
12588 tp->nvram_pagesize = ATMEL_AT24C02_CHIP_SIZE;
12590 case FLASH_5720VENDOR_M_ATMEL_DB011D:
12591 case FLASH_5720VENDOR_A_ATMEL_DB011B:
12592 case FLASH_5720VENDOR_A_ATMEL_DB011D:
12593 case FLASH_5720VENDOR_M_ATMEL_DB021D:
12594 case FLASH_5720VENDOR_A_ATMEL_DB021B:
12595 case FLASH_5720VENDOR_A_ATMEL_DB021D:
12596 case FLASH_5720VENDOR_M_ATMEL_DB041D:
12597 case FLASH_5720VENDOR_A_ATMEL_DB041B:
12598 case FLASH_5720VENDOR_A_ATMEL_DB041D:
12599 case FLASH_5720VENDOR_M_ATMEL_DB081D:
12600 case FLASH_5720VENDOR_A_ATMEL_DB081D:
12601 case FLASH_5720VENDOR_ATMEL_45USPT:
12602 tp->nvram_jedecnum = JEDEC_ATMEL;
12603 tg3_flag_set(tp, NVRAM_BUFFERED);
12604 tg3_flag_set(tp, FLASH);
12606 switch (nvmpinstrp) {
12607 case FLASH_5720VENDOR_M_ATMEL_DB021D:
12608 case FLASH_5720VENDOR_A_ATMEL_DB021B:
12609 case FLASH_5720VENDOR_A_ATMEL_DB021D:
12610 tp->nvram_size = TG3_NVRAM_SIZE_256KB;
12612 case FLASH_5720VENDOR_M_ATMEL_DB041D:
12613 case FLASH_5720VENDOR_A_ATMEL_DB041B:
12614 case FLASH_5720VENDOR_A_ATMEL_DB041D:
12615 tp->nvram_size = TG3_NVRAM_SIZE_512KB;
12617 case FLASH_5720VENDOR_M_ATMEL_DB081D:
12618 case FLASH_5720VENDOR_A_ATMEL_DB081D:
12619 tp->nvram_size = TG3_NVRAM_SIZE_1MB;
12622 tp->nvram_size = TG3_NVRAM_SIZE_128KB;
12626 case FLASH_5720VENDOR_M_ST_M25PE10:
12627 case FLASH_5720VENDOR_M_ST_M45PE10:
12628 case FLASH_5720VENDOR_A_ST_M25PE10:
12629 case FLASH_5720VENDOR_A_ST_M45PE10:
12630 case FLASH_5720VENDOR_M_ST_M25PE20:
12631 case FLASH_5720VENDOR_M_ST_M45PE20:
12632 case FLASH_5720VENDOR_A_ST_M25PE20:
12633 case FLASH_5720VENDOR_A_ST_M45PE20:
12634 case FLASH_5720VENDOR_M_ST_M25PE40:
12635 case FLASH_5720VENDOR_M_ST_M45PE40:
12636 case FLASH_5720VENDOR_A_ST_M25PE40:
12637 case FLASH_5720VENDOR_A_ST_M45PE40:
12638 case FLASH_5720VENDOR_M_ST_M25PE80:
12639 case FLASH_5720VENDOR_M_ST_M45PE80:
12640 case FLASH_5720VENDOR_A_ST_M25PE80:
12641 case FLASH_5720VENDOR_A_ST_M45PE80:
12642 case FLASH_5720VENDOR_ST_25USPT:
12643 case FLASH_5720VENDOR_ST_45USPT:
12644 tp->nvram_jedecnum = JEDEC_ST;
12645 tg3_flag_set(tp, NVRAM_BUFFERED);
12646 tg3_flag_set(tp, FLASH);
12648 switch (nvmpinstrp) {
12649 case FLASH_5720VENDOR_M_ST_M25PE20:
12650 case FLASH_5720VENDOR_M_ST_M45PE20:
12651 case FLASH_5720VENDOR_A_ST_M25PE20:
12652 case FLASH_5720VENDOR_A_ST_M45PE20:
12653 tp->nvram_size = TG3_NVRAM_SIZE_256KB;
12655 case FLASH_5720VENDOR_M_ST_M25PE40:
12656 case FLASH_5720VENDOR_M_ST_M45PE40:
12657 case FLASH_5720VENDOR_A_ST_M25PE40:
12658 case FLASH_5720VENDOR_A_ST_M45PE40:
12659 tp->nvram_size = TG3_NVRAM_SIZE_512KB;
12661 case FLASH_5720VENDOR_M_ST_M25PE80:
12662 case FLASH_5720VENDOR_M_ST_M45PE80:
12663 case FLASH_5720VENDOR_A_ST_M25PE80:
12664 case FLASH_5720VENDOR_A_ST_M45PE80:
12665 tp->nvram_size = TG3_NVRAM_SIZE_1MB;
12668 tp->nvram_size = TG3_NVRAM_SIZE_128KB;
12673 tg3_flag_set(tp, NO_NVRAM);
12677 tg3_nvram_get_pagesize(tp, nvcfg1);
12678 if (tp->nvram_pagesize != 264 && tp->nvram_pagesize != 528)
12679 tg3_flag_set(tp, NO_NVRAM_ADDR_TRANS);
12682 /* Chips other than 5700/5701 use the NVRAM for fetching info. */
12683 static void __devinit tg3_nvram_init(struct tg3 *tp)
12685 tw32_f(GRC_EEPROM_ADDR,
12686 (EEPROM_ADDR_FSM_RESET |
12687 (EEPROM_DEFAULT_CLOCK_PERIOD <<
12688 EEPROM_ADDR_CLKPERD_SHIFT)));
12692 /* Enable seeprom accesses. */
12693 tw32_f(GRC_LOCAL_CTRL,
12694 tr32(GRC_LOCAL_CTRL) | GRC_LCLCTRL_AUTO_SEEPROM);
12697 if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5700 &&
12698 GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5701) {
12699 tg3_flag_set(tp, NVRAM);
12701 if (tg3_nvram_lock(tp)) {
12702 netdev_warn(tp->dev,
12703 "Cannot get nvram lock, %s failed\n",
12707 tg3_enable_nvram_access(tp);
12709 tp->nvram_size = 0;
12711 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5752)
12712 tg3_get_5752_nvram_info(tp);
12713 else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5755)
12714 tg3_get_5755_nvram_info(tp);
12715 else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5787 ||
12716 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5784 ||
12717 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785)
12718 tg3_get_5787_nvram_info(tp);
12719 else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5761)
12720 tg3_get_5761_nvram_info(tp);
12721 else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906)
12722 tg3_get_5906_nvram_info(tp);
12723 else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57780 ||
12724 tg3_flag(tp, 57765_CLASS))
12725 tg3_get_57780_nvram_info(tp);
12726 else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717 ||
12727 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5719)
12728 tg3_get_5717_nvram_info(tp);
12729 else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5720)
12730 tg3_get_5720_nvram_info(tp);
12732 tg3_get_nvram_info(tp);
12734 if (tp->nvram_size == 0)
12735 tg3_get_nvram_size(tp);
12737 tg3_disable_nvram_access(tp);
12738 tg3_nvram_unlock(tp);
12741 tg3_flag_clear(tp, NVRAM);
12742 tg3_flag_clear(tp, NVRAM_BUFFERED);
12744 tg3_get_eeprom_size(tp);
12748 static int tg3_nvram_write_block_using_eeprom(struct tg3 *tp,
12749 u32 offset, u32 len, u8 *buf)
12754 for (i = 0; i < len; i += 4) {
12760 memcpy(&data, buf + i, 4);
12763 * The SEEPROM interface expects the data to always be opposite
12764 * the native endian format. We accomplish this by reversing
12765 * all the operations that would have been performed on the
12766 * data from a call to tg3_nvram_read_be32().
12768 tw32(GRC_EEPROM_DATA, swab32(be32_to_cpu(data)));
12770 val = tr32(GRC_EEPROM_ADDR);
12771 tw32(GRC_EEPROM_ADDR, val | EEPROM_ADDR_COMPLETE);
12773 val &= ~(EEPROM_ADDR_ADDR_MASK | EEPROM_ADDR_DEVID_MASK |
12775 tw32(GRC_EEPROM_ADDR, val |
12776 (0 << EEPROM_ADDR_DEVID_SHIFT) |
12777 (addr & EEPROM_ADDR_ADDR_MASK) |
12778 EEPROM_ADDR_START |
12779 EEPROM_ADDR_WRITE);
12781 for (j = 0; j < 1000; j++) {
12782 val = tr32(GRC_EEPROM_ADDR);
12784 if (val & EEPROM_ADDR_COMPLETE)
12788 if (!(val & EEPROM_ADDR_COMPLETE)) {
12797 /* offset and length are dword aligned */
12798 static int tg3_nvram_write_block_unbuffered(struct tg3 *tp, u32 offset, u32 len,
12802 u32 pagesize = tp->nvram_pagesize;
12803 u32 pagemask = pagesize - 1;
12807 tmp = kmalloc(pagesize, GFP_KERNEL);
12813 u32 phy_addr, page_off, size;
12815 phy_addr = offset & ~pagemask;
12817 for (j = 0; j < pagesize; j += 4) {
12818 ret = tg3_nvram_read_be32(tp, phy_addr + j,
12819 (__be32 *) (tmp + j));
12826 page_off = offset & pagemask;
12833 memcpy(tmp + page_off, buf, size);
12835 offset = offset + (pagesize - page_off);
12837 tg3_enable_nvram_access(tp);
12840 * Before we can erase the flash page, we need
12841 * to issue a special "write enable" command.
12843 nvram_cmd = NVRAM_CMD_WREN | NVRAM_CMD_GO | NVRAM_CMD_DONE;
12845 if (tg3_nvram_exec_cmd(tp, nvram_cmd))
12848 /* Erase the target page */
12849 tw32(NVRAM_ADDR, phy_addr);
12851 nvram_cmd = NVRAM_CMD_GO | NVRAM_CMD_DONE | NVRAM_CMD_WR |
12852 NVRAM_CMD_FIRST | NVRAM_CMD_LAST | NVRAM_CMD_ERASE;
12854 if (tg3_nvram_exec_cmd(tp, nvram_cmd))
12857 /* Issue another write enable to start the write. */
12858 nvram_cmd = NVRAM_CMD_WREN | NVRAM_CMD_GO | NVRAM_CMD_DONE;
12860 if (tg3_nvram_exec_cmd(tp, nvram_cmd))
12863 for (j = 0; j < pagesize; j += 4) {
12866 data = *((__be32 *) (tmp + j));
12868 tw32(NVRAM_WRDATA, be32_to_cpu(data));
12870 tw32(NVRAM_ADDR, phy_addr + j);
12872 nvram_cmd = NVRAM_CMD_GO | NVRAM_CMD_DONE |
12876 nvram_cmd |= NVRAM_CMD_FIRST;
12877 else if (j == (pagesize - 4))
12878 nvram_cmd |= NVRAM_CMD_LAST;
12880 if ((ret = tg3_nvram_exec_cmd(tp, nvram_cmd)))
12887 nvram_cmd = NVRAM_CMD_WRDI | NVRAM_CMD_GO | NVRAM_CMD_DONE;
12888 tg3_nvram_exec_cmd(tp, nvram_cmd);
12895 /* offset and length are dword aligned */
12896 static int tg3_nvram_write_block_buffered(struct tg3 *tp, u32 offset, u32 len,
12901 for (i = 0; i < len; i += 4, offset += 4) {
12902 u32 page_off, phy_addr, nvram_cmd;
12905 memcpy(&data, buf + i, 4);
12906 tw32(NVRAM_WRDATA, be32_to_cpu(data));
12908 page_off = offset % tp->nvram_pagesize;
12910 phy_addr = tg3_nvram_phys_addr(tp, offset);
12912 tw32(NVRAM_ADDR, phy_addr);
12914 nvram_cmd = NVRAM_CMD_GO | NVRAM_CMD_DONE | NVRAM_CMD_WR;
12916 if (page_off == 0 || i == 0)
12917 nvram_cmd |= NVRAM_CMD_FIRST;
12918 if (page_off == (tp->nvram_pagesize - 4))
12919 nvram_cmd |= NVRAM_CMD_LAST;
12921 if (i == (len - 4))
12922 nvram_cmd |= NVRAM_CMD_LAST;
12924 if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5752 &&
12925 !tg3_flag(tp, 5755_PLUS) &&
12926 (tp->nvram_jedecnum == JEDEC_ST) &&
12927 (nvram_cmd & NVRAM_CMD_FIRST)) {
12929 if ((ret = tg3_nvram_exec_cmd(tp,
12930 NVRAM_CMD_WREN | NVRAM_CMD_GO |
12935 if (!tg3_flag(tp, FLASH)) {
12936 /* We always do complete word writes to eeprom. */
12937 nvram_cmd |= (NVRAM_CMD_FIRST | NVRAM_CMD_LAST);
12940 if ((ret = tg3_nvram_exec_cmd(tp, nvram_cmd)))
12946 /* offset and length are dword aligned */
12947 static int tg3_nvram_write_block(struct tg3 *tp, u32 offset, u32 len, u8 *buf)
12951 if (tg3_flag(tp, EEPROM_WRITE_PROT)) {
12952 tw32_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl &
12953 ~GRC_LCLCTRL_GPIO_OUTPUT1);
12957 if (!tg3_flag(tp, NVRAM)) {
12958 ret = tg3_nvram_write_block_using_eeprom(tp, offset, len, buf);
12962 ret = tg3_nvram_lock(tp);
12966 tg3_enable_nvram_access(tp);
12967 if (tg3_flag(tp, 5750_PLUS) && !tg3_flag(tp, PROTECTED_NVRAM))
12968 tw32(NVRAM_WRITE1, 0x406);
12970 grc_mode = tr32(GRC_MODE);
12971 tw32(GRC_MODE, grc_mode | GRC_MODE_NVRAM_WR_ENABLE);
12973 if (tg3_flag(tp, NVRAM_BUFFERED) || !tg3_flag(tp, FLASH)) {
12974 ret = tg3_nvram_write_block_buffered(tp, offset, len,
12977 ret = tg3_nvram_write_block_unbuffered(tp, offset, len,
12981 grc_mode = tr32(GRC_MODE);
12982 tw32(GRC_MODE, grc_mode & ~GRC_MODE_NVRAM_WR_ENABLE);
12984 tg3_disable_nvram_access(tp);
12985 tg3_nvram_unlock(tp);
12988 if (tg3_flag(tp, EEPROM_WRITE_PROT)) {
12989 tw32_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl);
12996 struct subsys_tbl_ent {
12997 u16 subsys_vendor, subsys_devid;
13001 static struct subsys_tbl_ent subsys_id_to_phy_id[] __devinitdata = {
13002 /* Broadcom boards. */
13003 { TG3PCI_SUBVENDOR_ID_BROADCOM,
13004 TG3PCI_SUBDEVICE_ID_BROADCOM_95700A6, TG3_PHY_ID_BCM5401 },
13005 { TG3PCI_SUBVENDOR_ID_BROADCOM,
13006 TG3PCI_SUBDEVICE_ID_BROADCOM_95701A5, TG3_PHY_ID_BCM5701 },
13007 { TG3PCI_SUBVENDOR_ID_BROADCOM,
13008 TG3PCI_SUBDEVICE_ID_BROADCOM_95700T6, TG3_PHY_ID_BCM8002 },
13009 { TG3PCI_SUBVENDOR_ID_BROADCOM,
13010 TG3PCI_SUBDEVICE_ID_BROADCOM_95700A9, 0 },
13011 { TG3PCI_SUBVENDOR_ID_BROADCOM,
13012 TG3PCI_SUBDEVICE_ID_BROADCOM_95701T1, TG3_PHY_ID_BCM5701 },
13013 { TG3PCI_SUBVENDOR_ID_BROADCOM,
13014 TG3PCI_SUBDEVICE_ID_BROADCOM_95701T8, TG3_PHY_ID_BCM5701 },
13015 { TG3PCI_SUBVENDOR_ID_BROADCOM,
13016 TG3PCI_SUBDEVICE_ID_BROADCOM_95701A7, 0 },
13017 { TG3PCI_SUBVENDOR_ID_BROADCOM,
13018 TG3PCI_SUBDEVICE_ID_BROADCOM_95701A10, TG3_PHY_ID_BCM5701 },
13019 { TG3PCI_SUBVENDOR_ID_BROADCOM,
13020 TG3PCI_SUBDEVICE_ID_BROADCOM_95701A12, TG3_PHY_ID_BCM5701 },
13021 { TG3PCI_SUBVENDOR_ID_BROADCOM,
13022 TG3PCI_SUBDEVICE_ID_BROADCOM_95703AX1, TG3_PHY_ID_BCM5703 },
13023 { TG3PCI_SUBVENDOR_ID_BROADCOM,
13024 TG3PCI_SUBDEVICE_ID_BROADCOM_95703AX2, TG3_PHY_ID_BCM5703 },
13027 { TG3PCI_SUBVENDOR_ID_3COM,
13028 TG3PCI_SUBDEVICE_ID_3COM_3C996T, TG3_PHY_ID_BCM5401 },
13029 { TG3PCI_SUBVENDOR_ID_3COM,
13030 TG3PCI_SUBDEVICE_ID_3COM_3C996BT, TG3_PHY_ID_BCM5701 },
13031 { TG3PCI_SUBVENDOR_ID_3COM,
13032 TG3PCI_SUBDEVICE_ID_3COM_3C996SX, 0 },
13033 { TG3PCI_SUBVENDOR_ID_3COM,
13034 TG3PCI_SUBDEVICE_ID_3COM_3C1000T, TG3_PHY_ID_BCM5701 },
13035 { TG3PCI_SUBVENDOR_ID_3COM,
13036 TG3PCI_SUBDEVICE_ID_3COM_3C940BR01, TG3_PHY_ID_BCM5701 },
13039 { TG3PCI_SUBVENDOR_ID_DELL,
13040 TG3PCI_SUBDEVICE_ID_DELL_VIPER, TG3_PHY_ID_BCM5401 },
13041 { TG3PCI_SUBVENDOR_ID_DELL,
13042 TG3PCI_SUBDEVICE_ID_DELL_JAGUAR, TG3_PHY_ID_BCM5401 },
13043 { TG3PCI_SUBVENDOR_ID_DELL,
13044 TG3PCI_SUBDEVICE_ID_DELL_MERLOT, TG3_PHY_ID_BCM5411 },
13045 { TG3PCI_SUBVENDOR_ID_DELL,
13046 TG3PCI_SUBDEVICE_ID_DELL_SLIM_MERLOT, TG3_PHY_ID_BCM5411 },
13048 /* Compaq boards. */
13049 { TG3PCI_SUBVENDOR_ID_COMPAQ,
13050 TG3PCI_SUBDEVICE_ID_COMPAQ_BANSHEE, TG3_PHY_ID_BCM5701 },
13051 { TG3PCI_SUBVENDOR_ID_COMPAQ,
13052 TG3PCI_SUBDEVICE_ID_COMPAQ_BANSHEE_2, TG3_PHY_ID_BCM5701 },
13053 { TG3PCI_SUBVENDOR_ID_COMPAQ,
13054 TG3PCI_SUBDEVICE_ID_COMPAQ_CHANGELING, 0 },
13055 { TG3PCI_SUBVENDOR_ID_COMPAQ,
13056 TG3PCI_SUBDEVICE_ID_COMPAQ_NC7780, TG3_PHY_ID_BCM5701 },
13057 { TG3PCI_SUBVENDOR_ID_COMPAQ,
13058 TG3PCI_SUBDEVICE_ID_COMPAQ_NC7780_2, TG3_PHY_ID_BCM5701 },
13061 { TG3PCI_SUBVENDOR_ID_IBM,
13062 TG3PCI_SUBDEVICE_ID_IBM_5703SAX2, 0 }
13065 static struct subsys_tbl_ent * __devinit tg3_lookup_by_subsys(struct tg3 *tp)
13069 for (i = 0; i < ARRAY_SIZE(subsys_id_to_phy_id); i++) {
13070 if ((subsys_id_to_phy_id[i].subsys_vendor ==
13071 tp->pdev->subsystem_vendor) &&
13072 (subsys_id_to_phy_id[i].subsys_devid ==
13073 tp->pdev->subsystem_device))
13074 return &subsys_id_to_phy_id[i];
13079 static void __devinit tg3_get_eeprom_hw_cfg(struct tg3 *tp)
13083 tp->phy_id = TG3_PHY_ID_INVALID;
13084 tp->led_ctrl = LED_CTRL_MODE_PHY_1;
13086 /* Assume an onboard device and WOL capable by default. */
13087 tg3_flag_set(tp, EEPROM_WRITE_PROT);
13088 tg3_flag_set(tp, WOL_CAP);
13090 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
13091 if (!(tr32(PCIE_TRANSACTION_CFG) & PCIE_TRANS_CFG_LOM)) {
13092 tg3_flag_clear(tp, EEPROM_WRITE_PROT);
13093 tg3_flag_set(tp, IS_NIC);
13095 val = tr32(VCPU_CFGSHDW);
13096 if (val & VCPU_CFGSHDW_ASPM_DBNC)
13097 tg3_flag_set(tp, ASPM_WORKAROUND);
13098 if ((val & VCPU_CFGSHDW_WOL_ENABLE) &&
13099 (val & VCPU_CFGSHDW_WOL_MAGPKT)) {
13100 tg3_flag_set(tp, WOL_ENABLE);
13101 device_set_wakeup_enable(&tp->pdev->dev, true);
13106 tg3_read_mem(tp, NIC_SRAM_DATA_SIG, &val);
13107 if (val == NIC_SRAM_DATA_SIG_MAGIC) {
13108 u32 nic_cfg, led_cfg;
13109 u32 nic_phy_id, ver, cfg2 = 0, cfg4 = 0, eeprom_phy_id;
13110 int eeprom_phy_serdes = 0;
13112 tg3_read_mem(tp, NIC_SRAM_DATA_CFG, &nic_cfg);
13113 tp->nic_sram_data_cfg = nic_cfg;
13115 tg3_read_mem(tp, NIC_SRAM_DATA_VER, &ver);
13116 ver >>= NIC_SRAM_DATA_VER_SHIFT;
13117 if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5700 &&
13118 GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5701 &&
13119 GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5703 &&
13120 (ver > 0) && (ver < 0x100))
13121 tg3_read_mem(tp, NIC_SRAM_DATA_CFG_2, &cfg2);
13123 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785)
13124 tg3_read_mem(tp, NIC_SRAM_DATA_CFG_4, &cfg4);
13126 if ((nic_cfg & NIC_SRAM_DATA_CFG_PHY_TYPE_MASK) ==
13127 NIC_SRAM_DATA_CFG_PHY_TYPE_FIBER)
13128 eeprom_phy_serdes = 1;
13130 tg3_read_mem(tp, NIC_SRAM_DATA_PHY_ID, &nic_phy_id);
13131 if (nic_phy_id != 0) {
13132 u32 id1 = nic_phy_id & NIC_SRAM_DATA_PHY_ID1_MASK;
13133 u32 id2 = nic_phy_id & NIC_SRAM_DATA_PHY_ID2_MASK;
13135 eeprom_phy_id = (id1 >> 16) << 10;
13136 eeprom_phy_id |= (id2 & 0xfc00) << 16;
13137 eeprom_phy_id |= (id2 & 0x03ff) << 0;
13141 tp->phy_id = eeprom_phy_id;
13142 if (eeprom_phy_serdes) {
13143 if (!tg3_flag(tp, 5705_PLUS))
13144 tp->phy_flags |= TG3_PHYFLG_PHY_SERDES;
13146 tp->phy_flags |= TG3_PHYFLG_MII_SERDES;
13149 if (tg3_flag(tp, 5750_PLUS))
13150 led_cfg = cfg2 & (NIC_SRAM_DATA_CFG_LED_MODE_MASK |
13151 SHASTA_EXT_LED_MODE_MASK);
13153 led_cfg = nic_cfg & NIC_SRAM_DATA_CFG_LED_MODE_MASK;
13157 case NIC_SRAM_DATA_CFG_LED_MODE_PHY_1:
13158 tp->led_ctrl = LED_CTRL_MODE_PHY_1;
13161 case NIC_SRAM_DATA_CFG_LED_MODE_PHY_2:
13162 tp->led_ctrl = LED_CTRL_MODE_PHY_2;
13165 case NIC_SRAM_DATA_CFG_LED_MODE_MAC:
13166 tp->led_ctrl = LED_CTRL_MODE_MAC;
13168 /* Default to PHY_1_MODE if 0 (MAC_MODE) is
13169 * read on some older 5700/5701 bootcode.
13171 if (GET_ASIC_REV(tp->pci_chip_rev_id) ==
13173 GET_ASIC_REV(tp->pci_chip_rev_id) ==
13175 tp->led_ctrl = LED_CTRL_MODE_PHY_1;
13179 case SHASTA_EXT_LED_SHARED:
13180 tp->led_ctrl = LED_CTRL_MODE_SHARED;
13181 if (tp->pci_chip_rev_id != CHIPREV_ID_5750_A0 &&
13182 tp->pci_chip_rev_id != CHIPREV_ID_5750_A1)
13183 tp->led_ctrl |= (LED_CTRL_MODE_PHY_1 |
13184 LED_CTRL_MODE_PHY_2);
13187 case SHASTA_EXT_LED_MAC:
13188 tp->led_ctrl = LED_CTRL_MODE_SHASTA_MAC;
13191 case SHASTA_EXT_LED_COMBO:
13192 tp->led_ctrl = LED_CTRL_MODE_COMBO;
13193 if (tp->pci_chip_rev_id != CHIPREV_ID_5750_A0)
13194 tp->led_ctrl |= (LED_CTRL_MODE_PHY_1 |
13195 LED_CTRL_MODE_PHY_2);
13200 if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
13201 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701) &&
13202 tp->pdev->subsystem_vendor == PCI_VENDOR_ID_DELL)
13203 tp->led_ctrl = LED_CTRL_MODE_PHY_2;
13205 if (GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5784_AX)
13206 tp->led_ctrl = LED_CTRL_MODE_PHY_1;
13208 if (nic_cfg & NIC_SRAM_DATA_CFG_EEPROM_WP) {
13209 tg3_flag_set(tp, EEPROM_WRITE_PROT);
13210 if ((tp->pdev->subsystem_vendor ==
13211 PCI_VENDOR_ID_ARIMA) &&
13212 (tp->pdev->subsystem_device == 0x205a ||
13213 tp->pdev->subsystem_device == 0x2063))
13214 tg3_flag_clear(tp, EEPROM_WRITE_PROT);
13216 tg3_flag_clear(tp, EEPROM_WRITE_PROT);
13217 tg3_flag_set(tp, IS_NIC);
13220 if (nic_cfg & NIC_SRAM_DATA_CFG_ASF_ENABLE) {
13221 tg3_flag_set(tp, ENABLE_ASF);
13222 if (tg3_flag(tp, 5750_PLUS))
13223 tg3_flag_set(tp, ASF_NEW_HANDSHAKE);
13226 if ((nic_cfg & NIC_SRAM_DATA_CFG_APE_ENABLE) &&
13227 tg3_flag(tp, 5750_PLUS))
13228 tg3_flag_set(tp, ENABLE_APE);
13230 if (tp->phy_flags & TG3_PHYFLG_ANY_SERDES &&
13231 !(nic_cfg & NIC_SRAM_DATA_CFG_FIBER_WOL))
13232 tg3_flag_clear(tp, WOL_CAP);
13234 if (tg3_flag(tp, WOL_CAP) &&
13235 (nic_cfg & NIC_SRAM_DATA_CFG_WOL_ENABLE)) {
13236 tg3_flag_set(tp, WOL_ENABLE);
13237 device_set_wakeup_enable(&tp->pdev->dev, true);
13240 if (cfg2 & (1 << 17))
13241 tp->phy_flags |= TG3_PHYFLG_CAPACITIVE_COUPLING;
13243 /* serdes signal pre-emphasis in register 0x590 set by */
13244 /* bootcode if bit 18 is set */
13245 if (cfg2 & (1 << 18))
13246 tp->phy_flags |= TG3_PHYFLG_SERDES_PREEMPHASIS;
13248 if ((tg3_flag(tp, 57765_PLUS) ||
13249 (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5784 &&
13250 GET_CHIP_REV(tp->pci_chip_rev_id) != CHIPREV_5784_AX)) &&
13251 (cfg2 & NIC_SRAM_DATA_CFG_2_APD_EN))
13252 tp->phy_flags |= TG3_PHYFLG_ENABLE_APD;
13254 if (tg3_flag(tp, PCI_EXPRESS) &&
13255 GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5785 &&
13256 !tg3_flag(tp, 57765_PLUS)) {
13259 tg3_read_mem(tp, NIC_SRAM_DATA_CFG_3, &cfg3);
13260 if (cfg3 & NIC_SRAM_ASPM_DEBOUNCE)
13261 tg3_flag_set(tp, ASPM_WORKAROUND);
13264 if (cfg4 & NIC_SRAM_RGMII_INBAND_DISABLE)
13265 tg3_flag_set(tp, RGMII_INBAND_DISABLE);
13266 if (cfg4 & NIC_SRAM_RGMII_EXT_IBND_RX_EN)
13267 tg3_flag_set(tp, RGMII_EXT_IBND_RX_EN);
13268 if (cfg4 & NIC_SRAM_RGMII_EXT_IBND_TX_EN)
13269 tg3_flag_set(tp, RGMII_EXT_IBND_TX_EN);
13272 if (tg3_flag(tp, WOL_CAP))
13273 device_set_wakeup_enable(&tp->pdev->dev,
13274 tg3_flag(tp, WOL_ENABLE));
13276 device_set_wakeup_capable(&tp->pdev->dev, false);
13279 static int __devinit tg3_issue_otp_command(struct tg3 *tp, u32 cmd)
13284 tw32(OTP_CTRL, cmd | OTP_CTRL_OTP_CMD_START);
13285 tw32(OTP_CTRL, cmd);
13287 /* Wait for up to 1 ms for command to execute. */
13288 for (i = 0; i < 100; i++) {
13289 val = tr32(OTP_STATUS);
13290 if (val & OTP_STATUS_CMD_DONE)
13295 return (val & OTP_STATUS_CMD_DONE) ? 0 : -EBUSY;
13298 /* Read the gphy configuration from the OTP region of the chip. The gphy
13299 * configuration is a 32-bit value that straddles the alignment boundary.
13300 * We do two 32-bit reads and then shift and merge the results.
13302 static u32 __devinit tg3_read_otp_phycfg(struct tg3 *tp)
13304 u32 bhalf_otp, thalf_otp;
13306 tw32(OTP_MODE, OTP_MODE_OTP_THRU_GRC);
13308 if (tg3_issue_otp_command(tp, OTP_CTRL_OTP_CMD_INIT))
13311 tw32(OTP_ADDRESS, OTP_ADDRESS_MAGIC1);
13313 if (tg3_issue_otp_command(tp, OTP_CTRL_OTP_CMD_READ))
13316 thalf_otp = tr32(OTP_READ_DATA);
13318 tw32(OTP_ADDRESS, OTP_ADDRESS_MAGIC2);
13320 if (tg3_issue_otp_command(tp, OTP_CTRL_OTP_CMD_READ))
13323 bhalf_otp = tr32(OTP_READ_DATA);
13325 return ((thalf_otp & 0x0000ffff) << 16) | (bhalf_otp >> 16);
13328 static void __devinit tg3_phy_init_link_config(struct tg3 *tp)
13330 u32 adv = ADVERTISED_Autoneg;
13332 if (!(tp->phy_flags & TG3_PHYFLG_10_100_ONLY))
13333 adv |= ADVERTISED_1000baseT_Half |
13334 ADVERTISED_1000baseT_Full;
13336 if (!(tp->phy_flags & TG3_PHYFLG_ANY_SERDES))
13337 adv |= ADVERTISED_100baseT_Half |
13338 ADVERTISED_100baseT_Full |
13339 ADVERTISED_10baseT_Half |
13340 ADVERTISED_10baseT_Full |
13343 adv |= ADVERTISED_FIBRE;
13345 tp->link_config.advertising = adv;
13346 tp->link_config.speed = SPEED_INVALID;
13347 tp->link_config.duplex = DUPLEX_INVALID;
13348 tp->link_config.autoneg = AUTONEG_ENABLE;
13349 tp->link_config.active_speed = SPEED_INVALID;
13350 tp->link_config.active_duplex = DUPLEX_INVALID;
13351 tp->link_config.orig_speed = SPEED_INVALID;
13352 tp->link_config.orig_duplex = DUPLEX_INVALID;
13353 tp->link_config.orig_autoneg = AUTONEG_INVALID;
13356 static int __devinit tg3_phy_probe(struct tg3 *tp)
13358 u32 hw_phy_id_1, hw_phy_id_2;
13359 u32 hw_phy_id, hw_phy_id_masked;
13362 /* flow control autonegotiation is default behavior */
13363 tg3_flag_set(tp, PAUSE_AUTONEG);
13364 tp->link_config.flowctrl = FLOW_CTRL_TX | FLOW_CTRL_RX;
13366 if (tg3_flag(tp, USE_PHYLIB))
13367 return tg3_phy_init(tp);
13369 /* Reading the PHY ID register can conflict with ASF
13370 * firmware access to the PHY hardware.
13373 if (tg3_flag(tp, ENABLE_ASF) || tg3_flag(tp, ENABLE_APE)) {
13374 hw_phy_id = hw_phy_id_masked = TG3_PHY_ID_INVALID;
13376 /* Now read the physical PHY_ID from the chip and verify
13377 * that it is sane. If it doesn't look good, we fall back
13378 * to either the hard-coded table based PHY_ID and failing
13379 * that the value found in the eeprom area.
13381 err |= tg3_readphy(tp, MII_PHYSID1, &hw_phy_id_1);
13382 err |= tg3_readphy(tp, MII_PHYSID2, &hw_phy_id_2);
13384 hw_phy_id = (hw_phy_id_1 & 0xffff) << 10;
13385 hw_phy_id |= (hw_phy_id_2 & 0xfc00) << 16;
13386 hw_phy_id |= (hw_phy_id_2 & 0x03ff) << 0;
13388 hw_phy_id_masked = hw_phy_id & TG3_PHY_ID_MASK;
13391 if (!err && TG3_KNOWN_PHY_ID(hw_phy_id_masked)) {
13392 tp->phy_id = hw_phy_id;
13393 if (hw_phy_id_masked == TG3_PHY_ID_BCM8002)
13394 tp->phy_flags |= TG3_PHYFLG_PHY_SERDES;
13396 tp->phy_flags &= ~TG3_PHYFLG_PHY_SERDES;
13398 if (tp->phy_id != TG3_PHY_ID_INVALID) {
13399 /* Do nothing, phy ID already set up in
13400 * tg3_get_eeprom_hw_cfg().
13403 struct subsys_tbl_ent *p;
13405 /* No eeprom signature? Try the hardcoded
13406 * subsys device table.
13408 p = tg3_lookup_by_subsys(tp);
13412 tp->phy_id = p->phy_id;
13414 tp->phy_id == TG3_PHY_ID_BCM8002)
13415 tp->phy_flags |= TG3_PHYFLG_PHY_SERDES;
13419 if (!(tp->phy_flags & TG3_PHYFLG_ANY_SERDES) &&
13420 (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5719 ||
13421 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5720 ||
13422 (tp->pdev->device == TG3PCI_DEVICE_TIGON3_5718 &&
13423 tp->pci_chip_rev_id != CHIPREV_ID_5717_A0) ||
13424 (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57765 &&
13425 tp->pci_chip_rev_id != CHIPREV_ID_57765_A0)))
13426 tp->phy_flags |= TG3_PHYFLG_EEE_CAP;
13428 tg3_phy_init_link_config(tp);
13430 if (!(tp->phy_flags & TG3_PHYFLG_ANY_SERDES) &&
13431 !tg3_flag(tp, ENABLE_APE) &&
13432 !tg3_flag(tp, ENABLE_ASF)) {
13435 tg3_readphy(tp, MII_BMSR, &bmsr);
13436 if (!tg3_readphy(tp, MII_BMSR, &bmsr) &&
13437 (bmsr & BMSR_LSTATUS))
13438 goto skip_phy_reset;
13440 err = tg3_phy_reset(tp);
13444 tg3_phy_set_wirespeed(tp);
13446 if (!tg3_phy_copper_an_config_ok(tp, &dummy)) {
13447 tg3_phy_autoneg_cfg(tp, tp->link_config.advertising,
13448 tp->link_config.flowctrl);
13450 tg3_writephy(tp, MII_BMCR,
13451 BMCR_ANENABLE | BMCR_ANRESTART);
13456 if ((tp->phy_id & TG3_PHY_ID_MASK) == TG3_PHY_ID_BCM5401) {
13457 err = tg3_init_5401phy_dsp(tp);
13461 err = tg3_init_5401phy_dsp(tp);
13467 static void __devinit tg3_read_vpd(struct tg3 *tp)
13470 unsigned int block_end, rosize, len;
13474 vpd_data = (u8 *)tg3_vpd_readblock(tp, &vpdlen);
13478 i = pci_vpd_find_tag(vpd_data, 0, vpdlen, PCI_VPD_LRDT_RO_DATA);
13480 goto out_not_found;
13482 rosize = pci_vpd_lrdt_size(&vpd_data[i]);
13483 block_end = i + PCI_VPD_LRDT_TAG_SIZE + rosize;
13484 i += PCI_VPD_LRDT_TAG_SIZE;
13486 if (block_end > vpdlen)
13487 goto out_not_found;
13489 j = pci_vpd_find_info_keyword(vpd_data, i, rosize,
13490 PCI_VPD_RO_KEYWORD_MFR_ID);
13492 len = pci_vpd_info_field_size(&vpd_data[j]);
13494 j += PCI_VPD_INFO_FLD_HDR_SIZE;
13495 if (j + len > block_end || len != 4 ||
13496 memcmp(&vpd_data[j], "1028", 4))
13499 j = pci_vpd_find_info_keyword(vpd_data, i, rosize,
13500 PCI_VPD_RO_KEYWORD_VENDOR0);
13504 len = pci_vpd_info_field_size(&vpd_data[j]);
13506 j += PCI_VPD_INFO_FLD_HDR_SIZE;
13507 if (j + len > block_end)
13510 memcpy(tp->fw_ver, &vpd_data[j], len);
13511 strncat(tp->fw_ver, " bc ", vpdlen - len - 1);
13515 i = pci_vpd_find_info_keyword(vpd_data, i, rosize,
13516 PCI_VPD_RO_KEYWORD_PARTNO);
13518 goto out_not_found;
13520 len = pci_vpd_info_field_size(&vpd_data[i]);
13522 i += PCI_VPD_INFO_FLD_HDR_SIZE;
13523 if (len > TG3_BPN_SIZE ||
13524 (len + i) > vpdlen)
13525 goto out_not_found;
13527 memcpy(tp->board_part_number, &vpd_data[i], len);
13531 if (tp->board_part_number[0])
13535 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717) {
13536 if (tp->pdev->device == TG3PCI_DEVICE_TIGON3_5717)
13537 strcpy(tp->board_part_number, "BCM5717");
13538 else if (tp->pdev->device == TG3PCI_DEVICE_TIGON3_5718)
13539 strcpy(tp->board_part_number, "BCM5718");
13542 } else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57780) {
13543 if (tp->pdev->device == TG3PCI_DEVICE_TIGON3_57780)
13544 strcpy(tp->board_part_number, "BCM57780");
13545 else if (tp->pdev->device == TG3PCI_DEVICE_TIGON3_57760)
13546 strcpy(tp->board_part_number, "BCM57760");
13547 else if (tp->pdev->device == TG3PCI_DEVICE_TIGON3_57790)
13548 strcpy(tp->board_part_number, "BCM57790");
13549 else if (tp->pdev->device == TG3PCI_DEVICE_TIGON3_57788)
13550 strcpy(tp->board_part_number, "BCM57788");
13553 } else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57765) {
13554 if (tp->pdev->device == TG3PCI_DEVICE_TIGON3_57761)
13555 strcpy(tp->board_part_number, "BCM57761");
13556 else if (tp->pdev->device == TG3PCI_DEVICE_TIGON3_57765)
13557 strcpy(tp->board_part_number, "BCM57765");
13558 else if (tp->pdev->device == TG3PCI_DEVICE_TIGON3_57781)
13559 strcpy(tp->board_part_number, "BCM57781");
13560 else if (tp->pdev->device == TG3PCI_DEVICE_TIGON3_57785)
13561 strcpy(tp->board_part_number, "BCM57785");
13562 else if (tp->pdev->device == TG3PCI_DEVICE_TIGON3_57791)
13563 strcpy(tp->board_part_number, "BCM57791");
13564 else if (tp->pdev->device == TG3PCI_DEVICE_TIGON3_57795)
13565 strcpy(tp->board_part_number, "BCM57795");
13568 } else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57766) {
13569 if (tp->pdev->device == TG3PCI_DEVICE_TIGON3_57762)
13570 strcpy(tp->board_part_number, "BCM57762");
13571 else if (tp->pdev->device == TG3PCI_DEVICE_TIGON3_57766)
13572 strcpy(tp->board_part_number, "BCM57766");
13573 else if (tp->pdev->device == TG3PCI_DEVICE_TIGON3_57782)
13574 strcpy(tp->board_part_number, "BCM57782");
13575 else if (tp->pdev->device == TG3PCI_DEVICE_TIGON3_57786)
13576 strcpy(tp->board_part_number, "BCM57786");
13579 } else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
13580 strcpy(tp->board_part_number, "BCM95906");
13583 strcpy(tp->board_part_number, "none");
13587 static int __devinit tg3_fw_img_is_valid(struct tg3 *tp, u32 offset)
13591 if (tg3_nvram_read(tp, offset, &val) ||
13592 (val & 0xfc000000) != 0x0c000000 ||
13593 tg3_nvram_read(tp, offset + 4, &val) ||
13600 static void __devinit tg3_read_bc_ver(struct tg3 *tp)
13602 u32 val, offset, start, ver_offset;
13604 bool newver = false;
13606 if (tg3_nvram_read(tp, 0xc, &offset) ||
13607 tg3_nvram_read(tp, 0x4, &start))
13610 offset = tg3_nvram_logical_addr(tp, offset);
13612 if (tg3_nvram_read(tp, offset, &val))
13615 if ((val & 0xfc000000) == 0x0c000000) {
13616 if (tg3_nvram_read(tp, offset + 4, &val))
13623 dst_off = strlen(tp->fw_ver);
13626 if (TG3_VER_SIZE - dst_off < 16 ||
13627 tg3_nvram_read(tp, offset + 8, &ver_offset))
13630 offset = offset + ver_offset - start;
13631 for (i = 0; i < 16; i += 4) {
13633 if (tg3_nvram_read_be32(tp, offset + i, &v))
13636 memcpy(tp->fw_ver + dst_off + i, &v, sizeof(v));
13641 if (tg3_nvram_read(tp, TG3_NVM_PTREV_BCVER, &ver_offset))
13644 major = (ver_offset & TG3_NVM_BCVER_MAJMSK) >>
13645 TG3_NVM_BCVER_MAJSFT;
13646 minor = ver_offset & TG3_NVM_BCVER_MINMSK;
13647 snprintf(&tp->fw_ver[dst_off], TG3_VER_SIZE - dst_off,
13648 "v%d.%02d", major, minor);
13652 static void __devinit tg3_read_hwsb_ver(struct tg3 *tp)
13654 u32 val, major, minor;
13656 /* Use native endian representation */
13657 if (tg3_nvram_read(tp, TG3_NVM_HWSB_CFG1, &val))
13660 major = (val & TG3_NVM_HWSB_CFG1_MAJMSK) >>
13661 TG3_NVM_HWSB_CFG1_MAJSFT;
13662 minor = (val & TG3_NVM_HWSB_CFG1_MINMSK) >>
13663 TG3_NVM_HWSB_CFG1_MINSFT;
13665 snprintf(&tp->fw_ver[0], 32, "sb v%d.%02d", major, minor);
13668 static void __devinit tg3_read_sb_ver(struct tg3 *tp, u32 val)
13670 u32 offset, major, minor, build;
13672 strncat(tp->fw_ver, "sb", TG3_VER_SIZE - strlen(tp->fw_ver) - 1);
13674 if ((val & TG3_EEPROM_SB_FORMAT_MASK) != TG3_EEPROM_SB_FORMAT_1)
13677 switch (val & TG3_EEPROM_SB_REVISION_MASK) {
13678 case TG3_EEPROM_SB_REVISION_0:
13679 offset = TG3_EEPROM_SB_F1R0_EDH_OFF;
13681 case TG3_EEPROM_SB_REVISION_2:
13682 offset = TG3_EEPROM_SB_F1R2_EDH_OFF;
13684 case TG3_EEPROM_SB_REVISION_3:
13685 offset = TG3_EEPROM_SB_F1R3_EDH_OFF;
13687 case TG3_EEPROM_SB_REVISION_4:
13688 offset = TG3_EEPROM_SB_F1R4_EDH_OFF;
13690 case TG3_EEPROM_SB_REVISION_5:
13691 offset = TG3_EEPROM_SB_F1R5_EDH_OFF;
13693 case TG3_EEPROM_SB_REVISION_6:
13694 offset = TG3_EEPROM_SB_F1R6_EDH_OFF;
13700 if (tg3_nvram_read(tp, offset, &val))
13703 build = (val & TG3_EEPROM_SB_EDH_BLD_MASK) >>
13704 TG3_EEPROM_SB_EDH_BLD_SHFT;
13705 major = (val & TG3_EEPROM_SB_EDH_MAJ_MASK) >>
13706 TG3_EEPROM_SB_EDH_MAJ_SHFT;
13707 minor = val & TG3_EEPROM_SB_EDH_MIN_MASK;
13709 if (minor > 99 || build > 26)
13712 offset = strlen(tp->fw_ver);
13713 snprintf(&tp->fw_ver[offset], TG3_VER_SIZE - offset,
13714 " v%d.%02d", major, minor);
13717 offset = strlen(tp->fw_ver);
13718 if (offset < TG3_VER_SIZE - 1)
13719 tp->fw_ver[offset] = 'a' + build - 1;
13723 static void __devinit tg3_read_mgmtfw_ver(struct tg3 *tp)
13725 u32 val, offset, start;
13728 for (offset = TG3_NVM_DIR_START;
13729 offset < TG3_NVM_DIR_END;
13730 offset += TG3_NVM_DIRENT_SIZE) {
13731 if (tg3_nvram_read(tp, offset, &val))
13734 if ((val >> TG3_NVM_DIRTYPE_SHIFT) == TG3_NVM_DIRTYPE_ASFINI)
13738 if (offset == TG3_NVM_DIR_END)
13741 if (!tg3_flag(tp, 5705_PLUS))
13742 start = 0x08000000;
13743 else if (tg3_nvram_read(tp, offset - 4, &start))
13746 if (tg3_nvram_read(tp, offset + 4, &offset) ||
13747 !tg3_fw_img_is_valid(tp, offset) ||
13748 tg3_nvram_read(tp, offset + 8, &val))
13751 offset += val - start;
13753 vlen = strlen(tp->fw_ver);
13755 tp->fw_ver[vlen++] = ',';
13756 tp->fw_ver[vlen++] = ' ';
13758 for (i = 0; i < 4; i++) {
13760 if (tg3_nvram_read_be32(tp, offset, &v))
13763 offset += sizeof(v);
13765 if (vlen > TG3_VER_SIZE - sizeof(v)) {
13766 memcpy(&tp->fw_ver[vlen], &v, TG3_VER_SIZE - vlen);
13770 memcpy(&tp->fw_ver[vlen], &v, sizeof(v));
13775 static void __devinit tg3_read_dash_ver(struct tg3 *tp)
13781 if (!tg3_flag(tp, ENABLE_APE) || !tg3_flag(tp, ENABLE_ASF))
13784 apedata = tg3_ape_read32(tp, TG3_APE_SEG_SIG);
13785 if (apedata != APE_SEG_SIG_MAGIC)
13788 apedata = tg3_ape_read32(tp, TG3_APE_FW_STATUS);
13789 if (!(apedata & APE_FW_STATUS_READY))
13792 apedata = tg3_ape_read32(tp, TG3_APE_FW_VERSION);
13794 if (tg3_ape_read32(tp, TG3_APE_FW_FEATURES) & TG3_APE_FW_FEATURE_NCSI) {
13795 tg3_flag_set(tp, APE_HAS_NCSI);
13801 vlen = strlen(tp->fw_ver);
13803 snprintf(&tp->fw_ver[vlen], TG3_VER_SIZE - vlen, " %s v%d.%d.%d.%d",
13805 (apedata & APE_FW_VERSION_MAJMSK) >> APE_FW_VERSION_MAJSFT,
13806 (apedata & APE_FW_VERSION_MINMSK) >> APE_FW_VERSION_MINSFT,
13807 (apedata & APE_FW_VERSION_REVMSK) >> APE_FW_VERSION_REVSFT,
13808 (apedata & APE_FW_VERSION_BLDMSK));
13811 static void __devinit tg3_read_fw_ver(struct tg3 *tp)
13814 bool vpd_vers = false;
13816 if (tp->fw_ver[0] != 0)
13819 if (tg3_flag(tp, NO_NVRAM)) {
13820 strcat(tp->fw_ver, "sb");
13824 if (tg3_nvram_read(tp, 0, &val))
13827 if (val == TG3_EEPROM_MAGIC)
13828 tg3_read_bc_ver(tp);
13829 else if ((val & TG3_EEPROM_MAGIC_FW_MSK) == TG3_EEPROM_MAGIC_FW)
13830 tg3_read_sb_ver(tp, val);
13831 else if ((val & TG3_EEPROM_MAGIC_HW_MSK) == TG3_EEPROM_MAGIC_HW)
13832 tg3_read_hwsb_ver(tp);
13839 if (tg3_flag(tp, ENABLE_APE)) {
13840 if (tg3_flag(tp, ENABLE_ASF))
13841 tg3_read_dash_ver(tp);
13842 } else if (tg3_flag(tp, ENABLE_ASF)) {
13843 tg3_read_mgmtfw_ver(tp);
13847 tp->fw_ver[TG3_VER_SIZE - 1] = 0;
13850 static struct pci_dev * __devinit tg3_find_peer(struct tg3 *);
13852 static inline u32 tg3_rx_ret_ring_size(struct tg3 *tp)
13854 if (tg3_flag(tp, LRG_PROD_RING_CAP))
13855 return TG3_RX_RET_MAX_SIZE_5717;
13856 else if (tg3_flag(tp, JUMBO_CAPABLE) && !tg3_flag(tp, 5780_CLASS))
13857 return TG3_RX_RET_MAX_SIZE_5700;
13859 return TG3_RX_RET_MAX_SIZE_5705;
13862 static DEFINE_PCI_DEVICE_TABLE(tg3_write_reorder_chipsets) = {
13863 { PCI_DEVICE(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_FE_GATE_700C) },
13864 { PCI_DEVICE(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_8131_BRIDGE) },
13865 { PCI_DEVICE(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8385_0) },
13869 static int __devinit tg3_get_invariants(struct tg3 *tp)
13872 u32 pci_state_reg, grc_misc_cfg;
13877 /* Force memory write invalidate off. If we leave it on,
13878 * then on 5700_BX chips we have to enable a workaround.
13879 * The workaround is to set the TG3PCI_DMA_RW_CTRL boundary
13880 * to match the cacheline size. The Broadcom driver have this
13881 * workaround but turns MWI off all the times so never uses
13882 * it. This seems to suggest that the workaround is insufficient.
13884 pci_read_config_word(tp->pdev, PCI_COMMAND, &pci_cmd);
13885 pci_cmd &= ~PCI_COMMAND_INVALIDATE;
13886 pci_write_config_word(tp->pdev, PCI_COMMAND, pci_cmd);
13888 /* Important! -- Make sure register accesses are byteswapped
13889 * correctly. Also, for those chips that require it, make
13890 * sure that indirect register accesses are enabled before
13891 * the first operation.
13893 pci_read_config_dword(tp->pdev, TG3PCI_MISC_HOST_CTRL,
13895 tp->misc_host_ctrl |= (misc_ctrl_reg &
13896 MISC_HOST_CTRL_CHIPREV);
13897 pci_write_config_dword(tp->pdev, TG3PCI_MISC_HOST_CTRL,
13898 tp->misc_host_ctrl);
13900 tp->pci_chip_rev_id = (misc_ctrl_reg >>
13901 MISC_HOST_CTRL_CHIPREV_SHIFT);
13902 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_USE_PROD_ID_REG) {
13903 u32 prod_id_asic_rev;
13905 if (tp->pdev->device == TG3PCI_DEVICE_TIGON3_5717 ||
13906 tp->pdev->device == TG3PCI_DEVICE_TIGON3_5718 ||
13907 tp->pdev->device == TG3PCI_DEVICE_TIGON3_5719 ||
13908 tp->pdev->device == TG3PCI_DEVICE_TIGON3_5720)
13909 pci_read_config_dword(tp->pdev,
13910 TG3PCI_GEN2_PRODID_ASICREV,
13911 &prod_id_asic_rev);
13912 else if (tp->pdev->device == TG3PCI_DEVICE_TIGON3_57781 ||
13913 tp->pdev->device == TG3PCI_DEVICE_TIGON3_57785 ||
13914 tp->pdev->device == TG3PCI_DEVICE_TIGON3_57761 ||
13915 tp->pdev->device == TG3PCI_DEVICE_TIGON3_57765 ||
13916 tp->pdev->device == TG3PCI_DEVICE_TIGON3_57791 ||
13917 tp->pdev->device == TG3PCI_DEVICE_TIGON3_57795 ||
13918 tp->pdev->device == TG3PCI_DEVICE_TIGON3_57762 ||
13919 tp->pdev->device == TG3PCI_DEVICE_TIGON3_57766 ||
13920 tp->pdev->device == TG3PCI_DEVICE_TIGON3_57782 ||
13921 tp->pdev->device == TG3PCI_DEVICE_TIGON3_57786)
13922 pci_read_config_dword(tp->pdev,
13923 TG3PCI_GEN15_PRODID_ASICREV,
13924 &prod_id_asic_rev);
13926 pci_read_config_dword(tp->pdev, TG3PCI_PRODID_ASICREV,
13927 &prod_id_asic_rev);
13929 tp->pci_chip_rev_id = prod_id_asic_rev;
13932 /* Wrong chip ID in 5752 A0. This code can be removed later
13933 * as A0 is not in production.
13935 if (tp->pci_chip_rev_id == CHIPREV_ID_5752_A0_HW)
13936 tp->pci_chip_rev_id = CHIPREV_ID_5752_A0;
13938 /* If we have 5702/03 A1 or A2 on certain ICH chipsets,
13939 * we need to disable memory and use config. cycles
13940 * only to access all registers. The 5702/03 chips
13941 * can mistakenly decode the special cycles from the
13942 * ICH chipsets as memory write cycles, causing corruption
13943 * of register and memory space. Only certain ICH bridges
13944 * will drive special cycles with non-zero data during the
13945 * address phase which can fall within the 5703's address
13946 * range. This is not an ICH bug as the PCI spec allows
13947 * non-zero address during special cycles. However, only
13948 * these ICH bridges are known to drive non-zero addresses
13949 * during special cycles.
13951 * Since special cycles do not cross PCI bridges, we only
13952 * enable this workaround if the 5703 is on the secondary
13953 * bus of these ICH bridges.
13955 if ((tp->pci_chip_rev_id == CHIPREV_ID_5703_A1) ||
13956 (tp->pci_chip_rev_id == CHIPREV_ID_5703_A2)) {
13957 static struct tg3_dev_id {
13961 } ich_chipsets[] = {
13962 { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801AA_8,
13964 { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801AB_8,
13966 { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801BA_11,
13968 { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801BA_6,
13972 struct tg3_dev_id *pci_id = &ich_chipsets[0];
13973 struct pci_dev *bridge = NULL;
13975 while (pci_id->vendor != 0) {
13976 bridge = pci_get_device(pci_id->vendor, pci_id->device,
13982 if (pci_id->rev != PCI_ANY_ID) {
13983 if (bridge->revision > pci_id->rev)
13986 if (bridge->subordinate &&
13987 (bridge->subordinate->number ==
13988 tp->pdev->bus->number)) {
13989 tg3_flag_set(tp, ICH_WORKAROUND);
13990 pci_dev_put(bridge);
13996 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701) {
13997 static struct tg3_dev_id {
14000 } bridge_chipsets[] = {
14001 { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_PXH_0 },
14002 { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_PXH_1 },
14005 struct tg3_dev_id *pci_id = &bridge_chipsets[0];
14006 struct pci_dev *bridge = NULL;
14008 while (pci_id->vendor != 0) {
14009 bridge = pci_get_device(pci_id->vendor,
14016 if (bridge->subordinate &&
14017 (bridge->subordinate->number <=
14018 tp->pdev->bus->number) &&
14019 (bridge->subordinate->subordinate >=
14020 tp->pdev->bus->number)) {
14021 tg3_flag_set(tp, 5701_DMA_BUG);
14022 pci_dev_put(bridge);
14028 /* The EPB bridge inside 5714, 5715, and 5780 cannot support
14029 * DMA addresses > 40-bit. This bridge may have other additional
14030 * 57xx devices behind it in some 4-port NIC designs for example.
14031 * Any tg3 device found behind the bridge will also need the 40-bit
14034 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5780 ||
14035 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5714) {
14036 tg3_flag_set(tp, 5780_CLASS);
14037 tg3_flag_set(tp, 40BIT_DMA_BUG);
14038 tp->msi_cap = pci_find_capability(tp->pdev, PCI_CAP_ID_MSI);
14040 struct pci_dev *bridge = NULL;
14043 bridge = pci_get_device(PCI_VENDOR_ID_SERVERWORKS,
14044 PCI_DEVICE_ID_SERVERWORKS_EPB,
14046 if (bridge && bridge->subordinate &&
14047 (bridge->subordinate->number <=
14048 tp->pdev->bus->number) &&
14049 (bridge->subordinate->subordinate >=
14050 tp->pdev->bus->number)) {
14051 tg3_flag_set(tp, 40BIT_DMA_BUG);
14052 pci_dev_put(bridge);
14058 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704 ||
14059 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5714)
14060 tp->pdev_peer = tg3_find_peer(tp);
14062 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717 ||
14063 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5719 ||
14064 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5720)
14065 tg3_flag_set(tp, 5717_PLUS);
14067 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57765 ||
14068 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57766)
14069 tg3_flag_set(tp, 57765_CLASS);
14071 if (tg3_flag(tp, 57765_CLASS) || tg3_flag(tp, 5717_PLUS))
14072 tg3_flag_set(tp, 57765_PLUS);
14074 /* Intentionally exclude ASIC_REV_5906 */
14075 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5755 ||
14076 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5787 ||
14077 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5784 ||
14078 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5761 ||
14079 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785 ||
14080 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57780 ||
14081 tg3_flag(tp, 57765_PLUS))
14082 tg3_flag_set(tp, 5755_PLUS);
14084 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5750 ||
14085 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5752 ||
14086 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906 ||
14087 tg3_flag(tp, 5755_PLUS) ||
14088 tg3_flag(tp, 5780_CLASS))
14089 tg3_flag_set(tp, 5750_PLUS);
14091 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705 ||
14092 tg3_flag(tp, 5750_PLUS))
14093 tg3_flag_set(tp, 5705_PLUS);
14095 /* Determine TSO capabilities */
14096 if (tp->pci_chip_rev_id == CHIPREV_ID_5719_A0)
14097 ; /* Do nothing. HW bug. */
14098 else if (tg3_flag(tp, 57765_PLUS))
14099 tg3_flag_set(tp, HW_TSO_3);
14100 else if (tg3_flag(tp, 5755_PLUS) ||
14101 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906)
14102 tg3_flag_set(tp, HW_TSO_2);
14103 else if (tg3_flag(tp, 5750_PLUS)) {
14104 tg3_flag_set(tp, HW_TSO_1);
14105 tg3_flag_set(tp, TSO_BUG);
14106 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5750 &&
14107 tp->pci_chip_rev_id >= CHIPREV_ID_5750_C2)
14108 tg3_flag_clear(tp, TSO_BUG);
14109 } else if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5700 &&
14110 GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5701 &&
14111 tp->pci_chip_rev_id != CHIPREV_ID_5705_A0) {
14112 tg3_flag_set(tp, TSO_BUG);
14113 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705)
14114 tp->fw_needed = FIRMWARE_TG3TSO5;
14116 tp->fw_needed = FIRMWARE_TG3TSO;
14119 /* Selectively allow TSO based on operating conditions */
14120 if (tg3_flag(tp, HW_TSO_1) ||
14121 tg3_flag(tp, HW_TSO_2) ||
14122 tg3_flag(tp, HW_TSO_3) ||
14124 /* For firmware TSO, assume ASF is disabled.
14125 * We'll disable TSO later if we discover ASF
14126 * is enabled in tg3_get_eeprom_hw_cfg().
14128 tg3_flag_set(tp, TSO_CAPABLE);
14130 tg3_flag_clear(tp, TSO_CAPABLE);
14131 tg3_flag_clear(tp, TSO_BUG);
14132 tp->fw_needed = NULL;
14135 if (tp->pci_chip_rev_id == CHIPREV_ID_5701_A0)
14136 tp->fw_needed = FIRMWARE_TG3;
14140 if (tg3_flag(tp, 5750_PLUS)) {
14141 tg3_flag_set(tp, SUPPORT_MSI);
14142 if (GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5750_AX ||
14143 GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5750_BX ||
14144 (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5714 &&
14145 tp->pci_chip_rev_id <= CHIPREV_ID_5714_A2 &&
14146 tp->pdev_peer == tp->pdev))
14147 tg3_flag_clear(tp, SUPPORT_MSI);
14149 if (tg3_flag(tp, 5755_PLUS) ||
14150 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
14151 tg3_flag_set(tp, 1SHOT_MSI);
14154 if (tg3_flag(tp, 57765_PLUS)) {
14155 tg3_flag_set(tp, SUPPORT_MSIX);
14156 tp->irq_max = TG3_IRQ_MAX_VECS;
14157 tg3_rss_init_dflt_indir_tbl(tp);
14161 if (tg3_flag(tp, 5755_PLUS))
14162 tg3_flag_set(tp, SHORT_DMA_BUG);
14164 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5719)
14165 tp->dma_limit = TG3_TX_BD_DMA_MAX_4K;
14166 else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57766)
14167 tp->dma_limit = TG3_TX_BD_DMA_MAX_2K;
14169 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717 ||
14170 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5719 ||
14171 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5720)
14172 tg3_flag_set(tp, LRG_PROD_RING_CAP);
14174 if (tg3_flag(tp, 57765_PLUS) &&
14175 tp->pci_chip_rev_id != CHIPREV_ID_5719_A0)
14176 tg3_flag_set(tp, USE_JUMBO_BDFLAG);
14178 if (!tg3_flag(tp, 5705_PLUS) ||
14179 tg3_flag(tp, 5780_CLASS) ||
14180 tg3_flag(tp, USE_JUMBO_BDFLAG))
14181 tg3_flag_set(tp, JUMBO_CAPABLE);
14183 pci_read_config_dword(tp->pdev, TG3PCI_PCISTATE,
14186 if (pci_is_pcie(tp->pdev)) {
14189 tg3_flag_set(tp, PCI_EXPRESS);
14191 if (tp->pci_chip_rev_id == CHIPREV_ID_5719_A0) {
14192 int readrq = pcie_get_readrq(tp->pdev);
14194 pcie_set_readrq(tp->pdev, 2048);
14197 pci_read_config_word(tp->pdev,
14198 pci_pcie_cap(tp->pdev) + PCI_EXP_LNKCTL,
14200 if (lnkctl & PCI_EXP_LNKCTL_CLKREQ_EN) {
14201 if (GET_ASIC_REV(tp->pci_chip_rev_id) ==
14203 tg3_flag_clear(tp, HW_TSO_2);
14204 tg3_flag_clear(tp, TSO_CAPABLE);
14206 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5784 ||
14207 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5761 ||
14208 tp->pci_chip_rev_id == CHIPREV_ID_57780_A0 ||
14209 tp->pci_chip_rev_id == CHIPREV_ID_57780_A1)
14210 tg3_flag_set(tp, CLKREQ_BUG);
14211 } else if (tp->pci_chip_rev_id == CHIPREV_ID_5717_A0) {
14212 tg3_flag_set(tp, L1PLLPD_EN);
14214 } else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785) {
14215 /* BCM5785 devices are effectively PCIe devices, and should
14216 * follow PCIe codepaths, but do not have a PCIe capabilities
14219 tg3_flag_set(tp, PCI_EXPRESS);
14220 } else if (!tg3_flag(tp, 5705_PLUS) ||
14221 tg3_flag(tp, 5780_CLASS)) {
14222 tp->pcix_cap = pci_find_capability(tp->pdev, PCI_CAP_ID_PCIX);
14223 if (!tp->pcix_cap) {
14224 dev_err(&tp->pdev->dev,
14225 "Cannot find PCI-X capability, aborting\n");
14229 if (!(pci_state_reg & PCISTATE_CONV_PCI_MODE))
14230 tg3_flag_set(tp, PCIX_MODE);
14233 /* If we have an AMD 762 or VIA K8T800 chipset, write
14234 * reordering to the mailbox registers done by the host
14235 * controller can cause major troubles. We read back from
14236 * every mailbox register write to force the writes to be
14237 * posted to the chip in order.
14239 if (pci_dev_present(tg3_write_reorder_chipsets) &&
14240 !tg3_flag(tp, PCI_EXPRESS))
14241 tg3_flag_set(tp, MBOX_WRITE_REORDER);
14243 pci_read_config_byte(tp->pdev, PCI_CACHE_LINE_SIZE,
14244 &tp->pci_cacheline_sz);
14245 pci_read_config_byte(tp->pdev, PCI_LATENCY_TIMER,
14246 &tp->pci_lat_timer);
14247 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703 &&
14248 tp->pci_lat_timer < 64) {
14249 tp->pci_lat_timer = 64;
14250 pci_write_config_byte(tp->pdev, PCI_LATENCY_TIMER,
14251 tp->pci_lat_timer);
14254 /* Important! -- It is critical that the PCI-X hw workaround
14255 * situation is decided before the first MMIO register access.
14257 if (GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5700_BX) {
14258 /* 5700 BX chips need to have their TX producer index
14259 * mailboxes written twice to workaround a bug.
14261 tg3_flag_set(tp, TXD_MBOX_HWBUG);
14263 /* If we are in PCI-X mode, enable register write workaround.
14265 * The workaround is to use indirect register accesses
14266 * for all chip writes not to mailbox registers.
14268 if (tg3_flag(tp, PCIX_MODE)) {
14271 tg3_flag_set(tp, PCIX_TARGET_HWBUG);
14273 /* The chip can have it's power management PCI config
14274 * space registers clobbered due to this bug.
14275 * So explicitly force the chip into D0 here.
14277 pci_read_config_dword(tp->pdev,
14278 tp->pm_cap + PCI_PM_CTRL,
14280 pm_reg &= ~PCI_PM_CTRL_STATE_MASK;
14281 pm_reg |= PCI_PM_CTRL_PME_ENABLE | 0 /* D0 */;
14282 pci_write_config_dword(tp->pdev,
14283 tp->pm_cap + PCI_PM_CTRL,
14286 /* Also, force SERR#/PERR# in PCI command. */
14287 pci_read_config_word(tp->pdev, PCI_COMMAND, &pci_cmd);
14288 pci_cmd |= PCI_COMMAND_PARITY | PCI_COMMAND_SERR;
14289 pci_write_config_word(tp->pdev, PCI_COMMAND, pci_cmd);
14293 if ((pci_state_reg & PCISTATE_BUS_SPEED_HIGH) != 0)
14294 tg3_flag_set(tp, PCI_HIGH_SPEED);
14295 if ((pci_state_reg & PCISTATE_BUS_32BIT) != 0)
14296 tg3_flag_set(tp, PCI_32BIT);
14298 /* Chip-specific fixup from Broadcom driver */
14299 if ((tp->pci_chip_rev_id == CHIPREV_ID_5704_A0) &&
14300 (!(pci_state_reg & PCISTATE_RETRY_SAME_DMA))) {
14301 pci_state_reg |= PCISTATE_RETRY_SAME_DMA;
14302 pci_write_config_dword(tp->pdev, TG3PCI_PCISTATE, pci_state_reg);
14305 /* Default fast path register access methods */
14306 tp->read32 = tg3_read32;
14307 tp->write32 = tg3_write32;
14308 tp->read32_mbox = tg3_read32;
14309 tp->write32_mbox = tg3_write32;
14310 tp->write32_tx_mbox = tg3_write32;
14311 tp->write32_rx_mbox = tg3_write32;
14313 /* Various workaround register access methods */
14314 if (tg3_flag(tp, PCIX_TARGET_HWBUG))
14315 tp->write32 = tg3_write_indirect_reg32;
14316 else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701 ||
14317 (tg3_flag(tp, PCI_EXPRESS) &&
14318 tp->pci_chip_rev_id == CHIPREV_ID_5750_A0)) {
14320 * Back to back register writes can cause problems on these
14321 * chips, the workaround is to read back all reg writes
14322 * except those to mailbox regs.
14324 * See tg3_write_indirect_reg32().
14326 tp->write32 = tg3_write_flush_reg32;
14329 if (tg3_flag(tp, TXD_MBOX_HWBUG) || tg3_flag(tp, MBOX_WRITE_REORDER)) {
14330 tp->write32_tx_mbox = tg3_write32_tx_mbox;
14331 if (tg3_flag(tp, MBOX_WRITE_REORDER))
14332 tp->write32_rx_mbox = tg3_write_flush_reg32;
14335 if (tg3_flag(tp, ICH_WORKAROUND)) {
14336 tp->read32 = tg3_read_indirect_reg32;
14337 tp->write32 = tg3_write_indirect_reg32;
14338 tp->read32_mbox = tg3_read_indirect_mbox;
14339 tp->write32_mbox = tg3_write_indirect_mbox;
14340 tp->write32_tx_mbox = tg3_write_indirect_mbox;
14341 tp->write32_rx_mbox = tg3_write_indirect_mbox;
14346 pci_read_config_word(tp->pdev, PCI_COMMAND, &pci_cmd);
14347 pci_cmd &= ~PCI_COMMAND_MEMORY;
14348 pci_write_config_word(tp->pdev, PCI_COMMAND, pci_cmd);
14350 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
14351 tp->read32_mbox = tg3_read32_mbox_5906;
14352 tp->write32_mbox = tg3_write32_mbox_5906;
14353 tp->write32_tx_mbox = tg3_write32_mbox_5906;
14354 tp->write32_rx_mbox = tg3_write32_mbox_5906;
14357 if (tp->write32 == tg3_write_indirect_reg32 ||
14358 (tg3_flag(tp, PCIX_MODE) &&
14359 (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
14360 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701)))
14361 tg3_flag_set(tp, SRAM_USE_CONFIG);
14363 /* The memory arbiter has to be enabled in order for SRAM accesses
14364 * to succeed. Normally on powerup the tg3 chip firmware will make
14365 * sure it is enabled, but other entities such as system netboot
14366 * code might disable it.
14368 val = tr32(MEMARB_MODE);
14369 tw32(MEMARB_MODE, val | MEMARB_MODE_ENABLE);
14371 tp->pci_fn = PCI_FUNC(tp->pdev->devfn) & 3;
14372 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704 ||
14373 tg3_flag(tp, 5780_CLASS)) {
14374 if (tg3_flag(tp, PCIX_MODE)) {
14375 pci_read_config_dword(tp->pdev,
14376 tp->pcix_cap + PCI_X_STATUS,
14378 tp->pci_fn = val & 0x7;
14380 } else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717) {
14381 tg3_read_mem(tp, NIC_SRAM_CPMU_STATUS, &val);
14382 if ((val & NIC_SRAM_CPMUSTAT_SIG_MSK) ==
14383 NIC_SRAM_CPMUSTAT_SIG) {
14384 tp->pci_fn = val & TG3_CPMU_STATUS_FMSK_5717;
14385 tp->pci_fn = tp->pci_fn ? 1 : 0;
14387 } else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5719 ||
14388 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5720) {
14389 tg3_read_mem(tp, NIC_SRAM_CPMU_STATUS, &val);
14390 if ((val & NIC_SRAM_CPMUSTAT_SIG_MSK) ==
14391 NIC_SRAM_CPMUSTAT_SIG) {
14392 tp->pci_fn = (val & TG3_CPMU_STATUS_FMSK_5719) >>
14393 TG3_CPMU_STATUS_FSHFT_5719;
14397 /* Get eeprom hw config before calling tg3_set_power_state().
14398 * In particular, the TG3_FLAG_IS_NIC flag must be
14399 * determined before calling tg3_set_power_state() so that
14400 * we know whether or not to switch out of Vaux power.
14401 * When the flag is set, it means that GPIO1 is used for eeprom
14402 * write protect and also implies that it is a LOM where GPIOs
14403 * are not used to switch power.
14405 tg3_get_eeprom_hw_cfg(tp);
14407 if (tp->fw_needed && tg3_flag(tp, ENABLE_ASF)) {
14408 tg3_flag_clear(tp, TSO_CAPABLE);
14409 tg3_flag_clear(tp, TSO_BUG);
14410 tp->fw_needed = NULL;
14413 if (tg3_flag(tp, ENABLE_APE)) {
14414 /* Allow reads and writes to the
14415 * APE register and memory space.
14417 pci_state_reg |= PCISTATE_ALLOW_APE_CTLSPC_WR |
14418 PCISTATE_ALLOW_APE_SHMEM_WR |
14419 PCISTATE_ALLOW_APE_PSPACE_WR;
14420 pci_write_config_dword(tp->pdev, TG3PCI_PCISTATE,
14423 tg3_ape_lock_init(tp);
14426 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5784 ||
14427 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5761 ||
14428 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785 ||
14429 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57780 ||
14430 tg3_flag(tp, 57765_PLUS))
14431 tg3_flag_set(tp, CPMU_PRESENT);
14433 /* Set up tp->grc_local_ctrl before calling
14434 * tg3_pwrsrc_switch_to_vmain(). GPIO1 driven high
14435 * will bring 5700's external PHY out of reset.
14436 * It is also used as eeprom write protect on LOMs.
14438 tp->grc_local_ctrl = GRC_LCLCTRL_INT_ON_ATTN | GRC_LCLCTRL_AUTO_SEEPROM;
14439 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
14440 tg3_flag(tp, EEPROM_WRITE_PROT))
14441 tp->grc_local_ctrl |= (GRC_LCLCTRL_GPIO_OE1 |
14442 GRC_LCLCTRL_GPIO_OUTPUT1);
14443 /* Unused GPIO3 must be driven as output on 5752 because there
14444 * are no pull-up resistors on unused GPIO pins.
14446 else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5752)
14447 tp->grc_local_ctrl |= GRC_LCLCTRL_GPIO_OE3;
14449 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5755 ||
14450 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57780 ||
14451 tg3_flag(tp, 57765_CLASS))
14452 tp->grc_local_ctrl |= GRC_LCLCTRL_GPIO_UART_SEL;
14454 if (tp->pdev->device == PCI_DEVICE_ID_TIGON3_5761 ||
14455 tp->pdev->device == TG3PCI_DEVICE_TIGON3_5761S) {
14456 /* Turn off the debug UART. */
14457 tp->grc_local_ctrl |= GRC_LCLCTRL_GPIO_UART_SEL;
14458 if (tg3_flag(tp, IS_NIC))
14459 /* Keep VMain power. */
14460 tp->grc_local_ctrl |= GRC_LCLCTRL_GPIO_OE0 |
14461 GRC_LCLCTRL_GPIO_OUTPUT0;
14464 /* Switch out of Vaux if it is a NIC */
14465 tg3_pwrsrc_switch_to_vmain(tp);
14467 /* Derive initial jumbo mode from MTU assigned in
14468 * ether_setup() via the alloc_etherdev() call
14470 if (tp->dev->mtu > ETH_DATA_LEN && !tg3_flag(tp, 5780_CLASS))
14471 tg3_flag_set(tp, JUMBO_RING_ENABLE);
14473 /* Determine WakeOnLan speed to use. */
14474 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
14475 tp->pci_chip_rev_id == CHIPREV_ID_5701_A0 ||
14476 tp->pci_chip_rev_id == CHIPREV_ID_5701_B0 ||
14477 tp->pci_chip_rev_id == CHIPREV_ID_5701_B2) {
14478 tg3_flag_clear(tp, WOL_SPEED_100MB);
14480 tg3_flag_set(tp, WOL_SPEED_100MB);
14483 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906)
14484 tp->phy_flags |= TG3_PHYFLG_IS_FET;
14486 /* A few boards don't want Ethernet@WireSpeed phy feature */
14487 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
14488 (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705 &&
14489 (tp->pci_chip_rev_id != CHIPREV_ID_5705_A0) &&
14490 (tp->pci_chip_rev_id != CHIPREV_ID_5705_A1)) ||
14491 (tp->phy_flags & TG3_PHYFLG_IS_FET) ||
14492 (tp->phy_flags & TG3_PHYFLG_ANY_SERDES))
14493 tp->phy_flags |= TG3_PHYFLG_NO_ETH_WIRE_SPEED;
14495 if (GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5703_AX ||
14496 GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5704_AX)
14497 tp->phy_flags |= TG3_PHYFLG_ADC_BUG;
14498 if (tp->pci_chip_rev_id == CHIPREV_ID_5704_A0)
14499 tp->phy_flags |= TG3_PHYFLG_5704_A0_BUG;
14501 if (tg3_flag(tp, 5705_PLUS) &&
14502 !(tp->phy_flags & TG3_PHYFLG_IS_FET) &&
14503 GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5785 &&
14504 GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_57780 &&
14505 !tg3_flag(tp, 57765_PLUS)) {
14506 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5755 ||
14507 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5787 ||
14508 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5784 ||
14509 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5761) {
14510 if (tp->pdev->device != PCI_DEVICE_ID_TIGON3_5756 &&
14511 tp->pdev->device != PCI_DEVICE_ID_TIGON3_5722)
14512 tp->phy_flags |= TG3_PHYFLG_JITTER_BUG;
14513 if (tp->pdev->device == PCI_DEVICE_ID_TIGON3_5755M)
14514 tp->phy_flags |= TG3_PHYFLG_ADJUST_TRIM;
14516 tp->phy_flags |= TG3_PHYFLG_BER_BUG;
14519 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5784 &&
14520 GET_CHIP_REV(tp->pci_chip_rev_id) != CHIPREV_5784_AX) {
14521 tp->phy_otp = tg3_read_otp_phycfg(tp);
14522 if (tp->phy_otp == 0)
14523 tp->phy_otp = TG3_OTP_DEFAULT;
14526 if (tg3_flag(tp, CPMU_PRESENT))
14527 tp->mi_mode = MAC_MI_MODE_500KHZ_CONST;
14529 tp->mi_mode = MAC_MI_MODE_BASE;
14531 tp->coalesce_mode = 0;
14532 if (GET_CHIP_REV(tp->pci_chip_rev_id) != CHIPREV_5700_AX &&
14533 GET_CHIP_REV(tp->pci_chip_rev_id) != CHIPREV_5700_BX)
14534 tp->coalesce_mode |= HOSTCC_MODE_32BYTE;
14536 /* Set these bits to enable statistics workaround. */
14537 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717 ||
14538 tp->pci_chip_rev_id == CHIPREV_ID_5719_A0 ||
14539 tp->pci_chip_rev_id == CHIPREV_ID_5720_A0) {
14540 tp->coalesce_mode |= HOSTCC_MODE_ATTN;
14541 tp->grc_mode |= GRC_MODE_IRQ_ON_FLOW_ATTN;
14544 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785 ||
14545 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57780)
14546 tg3_flag_set(tp, USE_PHYLIB);
14548 err = tg3_mdio_init(tp);
14552 /* Initialize data/descriptor byte/word swapping. */
14553 val = tr32(GRC_MODE);
14554 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5720)
14555 val &= (GRC_MODE_BYTE_SWAP_B2HRX_DATA |
14556 GRC_MODE_WORD_SWAP_B2HRX_DATA |
14557 GRC_MODE_B2HRX_ENABLE |
14558 GRC_MODE_HTX2B_ENABLE |
14559 GRC_MODE_HOST_STACKUP);
14561 val &= GRC_MODE_HOST_STACKUP;
14563 tw32(GRC_MODE, val | tp->grc_mode);
14565 tg3_switch_clocks(tp);
14567 /* Clear this out for sanity. */
14568 tw32(TG3PCI_MEM_WIN_BASE_ADDR, 0);
14570 pci_read_config_dword(tp->pdev, TG3PCI_PCISTATE,
14572 if ((pci_state_reg & PCISTATE_CONV_PCI_MODE) == 0 &&
14573 !tg3_flag(tp, PCIX_TARGET_HWBUG)) {
14574 u32 chiprevid = GET_CHIP_REV_ID(tp->misc_host_ctrl);
14576 if (chiprevid == CHIPREV_ID_5701_A0 ||
14577 chiprevid == CHIPREV_ID_5701_B0 ||
14578 chiprevid == CHIPREV_ID_5701_B2 ||
14579 chiprevid == CHIPREV_ID_5701_B5) {
14580 void __iomem *sram_base;
14582 /* Write some dummy words into the SRAM status block
14583 * area, see if it reads back correctly. If the return
14584 * value is bad, force enable the PCIX workaround.
14586 sram_base = tp->regs + NIC_SRAM_WIN_BASE + NIC_SRAM_STATS_BLK;
14588 writel(0x00000000, sram_base);
14589 writel(0x00000000, sram_base + 4);
14590 writel(0xffffffff, sram_base + 4);
14591 if (readl(sram_base) != 0x00000000)
14592 tg3_flag_set(tp, PCIX_TARGET_HWBUG);
14597 tg3_nvram_init(tp);
14599 grc_misc_cfg = tr32(GRC_MISC_CFG);
14600 grc_misc_cfg &= GRC_MISC_CFG_BOARD_ID_MASK;
14602 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705 &&
14603 (grc_misc_cfg == GRC_MISC_CFG_BOARD_ID_5788 ||
14604 grc_misc_cfg == GRC_MISC_CFG_BOARD_ID_5788M))
14605 tg3_flag_set(tp, IS_5788);
14607 if (!tg3_flag(tp, IS_5788) &&
14608 GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5700)
14609 tg3_flag_set(tp, TAGGED_STATUS);
14610 if (tg3_flag(tp, TAGGED_STATUS)) {
14611 tp->coalesce_mode |= (HOSTCC_MODE_CLRTICK_RXBD |
14612 HOSTCC_MODE_CLRTICK_TXBD);
14614 tp->misc_host_ctrl |= MISC_HOST_CTRL_TAGGED_STATUS;
14615 pci_write_config_dword(tp->pdev, TG3PCI_MISC_HOST_CTRL,
14616 tp->misc_host_ctrl);
14619 /* Preserve the APE MAC_MODE bits */
14620 if (tg3_flag(tp, ENABLE_APE))
14621 tp->mac_mode = MAC_MODE_APE_TX_EN | MAC_MODE_APE_RX_EN;
14625 /* these are limited to 10/100 only */
14626 if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703 &&
14627 (grc_misc_cfg == 0x8000 || grc_misc_cfg == 0x4000)) ||
14628 (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705 &&
14629 tp->pdev->vendor == PCI_VENDOR_ID_BROADCOM &&
14630 (tp->pdev->device == PCI_DEVICE_ID_TIGON3_5901 ||
14631 tp->pdev->device == PCI_DEVICE_ID_TIGON3_5901_2 ||
14632 tp->pdev->device == PCI_DEVICE_ID_TIGON3_5705F)) ||
14633 (tp->pdev->vendor == PCI_VENDOR_ID_BROADCOM &&
14634 (tp->pdev->device == PCI_DEVICE_ID_TIGON3_5751F ||
14635 tp->pdev->device == PCI_DEVICE_ID_TIGON3_5753F ||
14636 tp->pdev->device == PCI_DEVICE_ID_TIGON3_5787F)) ||
14637 tp->pdev->device == TG3PCI_DEVICE_TIGON3_57790 ||
14638 tp->pdev->device == TG3PCI_DEVICE_TIGON3_57791 ||
14639 tp->pdev->device == TG3PCI_DEVICE_TIGON3_57795 ||
14640 (tp->phy_flags & TG3_PHYFLG_IS_FET))
14641 tp->phy_flags |= TG3_PHYFLG_10_100_ONLY;
14643 err = tg3_phy_probe(tp);
14645 dev_err(&tp->pdev->dev, "phy probe failed, err %d\n", err);
14646 /* ... but do not return immediately ... */
14651 tg3_read_fw_ver(tp);
14653 if (tp->phy_flags & TG3_PHYFLG_PHY_SERDES) {
14654 tp->phy_flags &= ~TG3_PHYFLG_USE_MI_INTERRUPT;
14656 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700)
14657 tp->phy_flags |= TG3_PHYFLG_USE_MI_INTERRUPT;
14659 tp->phy_flags &= ~TG3_PHYFLG_USE_MI_INTERRUPT;
14662 /* 5700 {AX,BX} chips have a broken status block link
14663 * change bit implementation, so we must use the
14664 * status register in those cases.
14666 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700)
14667 tg3_flag_set(tp, USE_LINKCHG_REG);
14669 tg3_flag_clear(tp, USE_LINKCHG_REG);
14671 /* The led_ctrl is set during tg3_phy_probe, here we might
14672 * have to force the link status polling mechanism based
14673 * upon subsystem IDs.
14675 if (tp->pdev->subsystem_vendor == PCI_VENDOR_ID_DELL &&
14676 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701 &&
14677 !(tp->phy_flags & TG3_PHYFLG_PHY_SERDES)) {
14678 tp->phy_flags |= TG3_PHYFLG_USE_MI_INTERRUPT;
14679 tg3_flag_set(tp, USE_LINKCHG_REG);
14682 /* For all SERDES we poll the MAC status register. */
14683 if (tp->phy_flags & TG3_PHYFLG_PHY_SERDES)
14684 tg3_flag_set(tp, POLL_SERDES);
14686 tg3_flag_clear(tp, POLL_SERDES);
14688 tp->rx_offset = NET_SKB_PAD + NET_IP_ALIGN;
14689 tp->rx_copy_thresh = TG3_RX_COPY_THRESHOLD;
14690 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701 &&
14691 tg3_flag(tp, PCIX_MODE)) {
14692 tp->rx_offset = NET_SKB_PAD;
14693 #ifndef CONFIG_HAVE_EFFICIENT_UNALIGNED_ACCESS
14694 tp->rx_copy_thresh = ~(u16)0;
14698 tp->rx_std_ring_mask = TG3_RX_STD_RING_SIZE(tp) - 1;
14699 tp->rx_jmb_ring_mask = TG3_RX_JMB_RING_SIZE(tp) - 1;
14700 tp->rx_ret_ring_mask = tg3_rx_ret_ring_size(tp) - 1;
14702 tp->rx_std_max_post = tp->rx_std_ring_mask + 1;
14704 /* Increment the rx prod index on the rx std ring by at most
14705 * 8 for these chips to workaround hw errata.
14707 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5750 ||
14708 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5752 ||
14709 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5755)
14710 tp->rx_std_max_post = 8;
14712 if (tg3_flag(tp, ASPM_WORKAROUND))
14713 tp->pwrmgmt_thresh = tr32(PCIE_PWR_MGMT_THRESH) &
14714 PCIE_PWR_MGMT_L1_THRESH_MSK;
14719 #ifdef CONFIG_SPARC
14720 static int __devinit tg3_get_macaddr_sparc(struct tg3 *tp)
14722 struct net_device *dev = tp->dev;
14723 struct pci_dev *pdev = tp->pdev;
14724 struct device_node *dp = pci_device_to_OF_node(pdev);
14725 const unsigned char *addr;
14728 addr = of_get_property(dp, "local-mac-address", &len);
14729 if (addr && len == 6) {
14730 memcpy(dev->dev_addr, addr, 6);
14731 memcpy(dev->perm_addr, dev->dev_addr, 6);
14737 static int __devinit tg3_get_default_macaddr_sparc(struct tg3 *tp)
14739 struct net_device *dev = tp->dev;
14741 memcpy(dev->dev_addr, idprom->id_ethaddr, 6);
14742 memcpy(dev->perm_addr, idprom->id_ethaddr, 6);
14747 static int __devinit tg3_get_device_address(struct tg3 *tp)
14749 struct net_device *dev = tp->dev;
14750 u32 hi, lo, mac_offset;
14753 #ifdef CONFIG_SPARC
14754 if (!tg3_get_macaddr_sparc(tp))
14759 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704 ||
14760 tg3_flag(tp, 5780_CLASS)) {
14761 if (tr32(TG3PCI_DUAL_MAC_CTRL) & DUAL_MAC_CTRL_ID)
14763 if (tg3_nvram_lock(tp))
14764 tw32_f(NVRAM_CMD, NVRAM_CMD_RESET);
14766 tg3_nvram_unlock(tp);
14767 } else if (tg3_flag(tp, 5717_PLUS)) {
14768 if (tp->pci_fn & 1)
14770 if (tp->pci_fn > 1)
14771 mac_offset += 0x18c;
14772 } else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906)
14775 /* First try to get it from MAC address mailbox. */
14776 tg3_read_mem(tp, NIC_SRAM_MAC_ADDR_HIGH_MBOX, &hi);
14777 if ((hi >> 16) == 0x484b) {
14778 dev->dev_addr[0] = (hi >> 8) & 0xff;
14779 dev->dev_addr[1] = (hi >> 0) & 0xff;
14781 tg3_read_mem(tp, NIC_SRAM_MAC_ADDR_LOW_MBOX, &lo);
14782 dev->dev_addr[2] = (lo >> 24) & 0xff;
14783 dev->dev_addr[3] = (lo >> 16) & 0xff;
14784 dev->dev_addr[4] = (lo >> 8) & 0xff;
14785 dev->dev_addr[5] = (lo >> 0) & 0xff;
14787 /* Some old bootcode may report a 0 MAC address in SRAM */
14788 addr_ok = is_valid_ether_addr(&dev->dev_addr[0]);
14791 /* Next, try NVRAM. */
14792 if (!tg3_flag(tp, NO_NVRAM) &&
14793 !tg3_nvram_read_be32(tp, mac_offset + 0, &hi) &&
14794 !tg3_nvram_read_be32(tp, mac_offset + 4, &lo)) {
14795 memcpy(&dev->dev_addr[0], ((char *)&hi) + 2, 2);
14796 memcpy(&dev->dev_addr[2], (char *)&lo, sizeof(lo));
14798 /* Finally just fetch it out of the MAC control regs. */
14800 hi = tr32(MAC_ADDR_0_HIGH);
14801 lo = tr32(MAC_ADDR_0_LOW);
14803 dev->dev_addr[5] = lo & 0xff;
14804 dev->dev_addr[4] = (lo >> 8) & 0xff;
14805 dev->dev_addr[3] = (lo >> 16) & 0xff;
14806 dev->dev_addr[2] = (lo >> 24) & 0xff;
14807 dev->dev_addr[1] = hi & 0xff;
14808 dev->dev_addr[0] = (hi >> 8) & 0xff;
14812 if (!is_valid_ether_addr(&dev->dev_addr[0])) {
14813 #ifdef CONFIG_SPARC
14814 if (!tg3_get_default_macaddr_sparc(tp))
14819 memcpy(dev->perm_addr, dev->dev_addr, dev->addr_len);
14823 #define BOUNDARY_SINGLE_CACHELINE 1
14824 #define BOUNDARY_MULTI_CACHELINE 2
14826 static u32 __devinit tg3_calc_dma_bndry(struct tg3 *tp, u32 val)
14828 int cacheline_size;
14832 pci_read_config_byte(tp->pdev, PCI_CACHE_LINE_SIZE, &byte);
14834 cacheline_size = 1024;
14836 cacheline_size = (int) byte * 4;
14838 /* On 5703 and later chips, the boundary bits have no
14841 if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5700 &&
14842 GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5701 &&
14843 !tg3_flag(tp, PCI_EXPRESS))
14846 #if defined(CONFIG_PPC64) || defined(CONFIG_IA64) || defined(CONFIG_PARISC)
14847 goal = BOUNDARY_MULTI_CACHELINE;
14849 #if defined(CONFIG_SPARC64) || defined(CONFIG_ALPHA)
14850 goal = BOUNDARY_SINGLE_CACHELINE;
14856 if (tg3_flag(tp, 57765_PLUS)) {
14857 val = goal ? 0 : DMA_RWCTRL_DIS_CACHE_ALIGNMENT;
14864 /* PCI controllers on most RISC systems tend to disconnect
14865 * when a device tries to burst across a cache-line boundary.
14866 * Therefore, letting tg3 do so just wastes PCI bandwidth.
14868 * Unfortunately, for PCI-E there are only limited
14869 * write-side controls for this, and thus for reads
14870 * we will still get the disconnects. We'll also waste
14871 * these PCI cycles for both read and write for chips
14872 * other than 5700 and 5701 which do not implement the
14875 if (tg3_flag(tp, PCIX_MODE) && !tg3_flag(tp, PCI_EXPRESS)) {
14876 switch (cacheline_size) {
14881 if (goal == BOUNDARY_SINGLE_CACHELINE) {
14882 val |= (DMA_RWCTRL_READ_BNDRY_128_PCIX |
14883 DMA_RWCTRL_WRITE_BNDRY_128_PCIX);
14885 val |= (DMA_RWCTRL_READ_BNDRY_384_PCIX |
14886 DMA_RWCTRL_WRITE_BNDRY_384_PCIX);
14891 val |= (DMA_RWCTRL_READ_BNDRY_256_PCIX |
14892 DMA_RWCTRL_WRITE_BNDRY_256_PCIX);
14896 val |= (DMA_RWCTRL_READ_BNDRY_384_PCIX |
14897 DMA_RWCTRL_WRITE_BNDRY_384_PCIX);
14900 } else if (tg3_flag(tp, PCI_EXPRESS)) {
14901 switch (cacheline_size) {
14905 if (goal == BOUNDARY_SINGLE_CACHELINE) {
14906 val &= ~DMA_RWCTRL_WRITE_BNDRY_DISAB_PCIE;
14907 val |= DMA_RWCTRL_WRITE_BNDRY_64_PCIE;
14913 val &= ~DMA_RWCTRL_WRITE_BNDRY_DISAB_PCIE;
14914 val |= DMA_RWCTRL_WRITE_BNDRY_128_PCIE;
14918 switch (cacheline_size) {
14920 if (goal == BOUNDARY_SINGLE_CACHELINE) {
14921 val |= (DMA_RWCTRL_READ_BNDRY_16 |
14922 DMA_RWCTRL_WRITE_BNDRY_16);
14927 if (goal == BOUNDARY_SINGLE_CACHELINE) {
14928 val |= (DMA_RWCTRL_READ_BNDRY_32 |
14929 DMA_RWCTRL_WRITE_BNDRY_32);
14934 if (goal == BOUNDARY_SINGLE_CACHELINE) {
14935 val |= (DMA_RWCTRL_READ_BNDRY_64 |
14936 DMA_RWCTRL_WRITE_BNDRY_64);
14941 if (goal == BOUNDARY_SINGLE_CACHELINE) {
14942 val |= (DMA_RWCTRL_READ_BNDRY_128 |
14943 DMA_RWCTRL_WRITE_BNDRY_128);
14948 val |= (DMA_RWCTRL_READ_BNDRY_256 |
14949 DMA_RWCTRL_WRITE_BNDRY_256);
14952 val |= (DMA_RWCTRL_READ_BNDRY_512 |
14953 DMA_RWCTRL_WRITE_BNDRY_512);
14957 val |= (DMA_RWCTRL_READ_BNDRY_1024 |
14958 DMA_RWCTRL_WRITE_BNDRY_1024);
14967 static int __devinit tg3_do_test_dma(struct tg3 *tp, u32 *buf, dma_addr_t buf_dma, int size, int to_device)
14969 struct tg3_internal_buffer_desc test_desc;
14970 u32 sram_dma_descs;
14973 sram_dma_descs = NIC_SRAM_DMA_DESC_POOL_BASE;
14975 tw32(FTQ_RCVBD_COMP_FIFO_ENQDEQ, 0);
14976 tw32(FTQ_RCVDATA_COMP_FIFO_ENQDEQ, 0);
14977 tw32(RDMAC_STATUS, 0);
14978 tw32(WDMAC_STATUS, 0);
14980 tw32(BUFMGR_MODE, 0);
14981 tw32(FTQ_RESET, 0);
14983 test_desc.addr_hi = ((u64) buf_dma) >> 32;
14984 test_desc.addr_lo = buf_dma & 0xffffffff;
14985 test_desc.nic_mbuf = 0x00002100;
14986 test_desc.len = size;
14989 * HP ZX1 was seeing test failures for 5701 cards running at 33Mhz
14990 * the *second* time the tg3 driver was getting loaded after an
14993 * Broadcom tells me:
14994 * ...the DMA engine is connected to the GRC block and a DMA
14995 * reset may affect the GRC block in some unpredictable way...
14996 * The behavior of resets to individual blocks has not been tested.
14998 * Broadcom noted the GRC reset will also reset all sub-components.
15001 test_desc.cqid_sqid = (13 << 8) | 2;
15003 tw32_f(RDMAC_MODE, RDMAC_MODE_ENABLE);
15006 test_desc.cqid_sqid = (16 << 8) | 7;
15008 tw32_f(WDMAC_MODE, WDMAC_MODE_ENABLE);
15011 test_desc.flags = 0x00000005;
15013 for (i = 0; i < (sizeof(test_desc) / sizeof(u32)); i++) {
15016 val = *(((u32 *)&test_desc) + i);
15017 pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_BASE_ADDR,
15018 sram_dma_descs + (i * sizeof(u32)));
15019 pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_DATA, val);
15021 pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_BASE_ADDR, 0);
15024 tw32(FTQ_DMA_HIGH_READ_FIFO_ENQDEQ, sram_dma_descs);
15026 tw32(FTQ_DMA_HIGH_WRITE_FIFO_ENQDEQ, sram_dma_descs);
15029 for (i = 0; i < 40; i++) {
15033 val = tr32(FTQ_RCVBD_COMP_FIFO_ENQDEQ);
15035 val = tr32(FTQ_RCVDATA_COMP_FIFO_ENQDEQ);
15036 if ((val & 0xffff) == sram_dma_descs) {
15047 #define TEST_BUFFER_SIZE 0x2000
15049 static DEFINE_PCI_DEVICE_TABLE(tg3_dma_wait_state_chipsets) = {
15050 { PCI_DEVICE(PCI_VENDOR_ID_APPLE, PCI_DEVICE_ID_APPLE_UNI_N_PCI15) },
15054 static int __devinit tg3_test_dma(struct tg3 *tp)
15056 dma_addr_t buf_dma;
15057 u32 *buf, saved_dma_rwctrl;
15060 buf = dma_alloc_coherent(&tp->pdev->dev, TEST_BUFFER_SIZE,
15061 &buf_dma, GFP_KERNEL);
15067 tp->dma_rwctrl = ((0x7 << DMA_RWCTRL_PCI_WRITE_CMD_SHIFT) |
15068 (0x6 << DMA_RWCTRL_PCI_READ_CMD_SHIFT));
15070 tp->dma_rwctrl = tg3_calc_dma_bndry(tp, tp->dma_rwctrl);
15072 if (tg3_flag(tp, 57765_PLUS))
15075 if (tg3_flag(tp, PCI_EXPRESS)) {
15076 /* DMA read watermark not used on PCIE */
15077 tp->dma_rwctrl |= 0x00180000;
15078 } else if (!tg3_flag(tp, PCIX_MODE)) {
15079 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705 ||
15080 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5750)
15081 tp->dma_rwctrl |= 0x003f0000;
15083 tp->dma_rwctrl |= 0x003f000f;
15085 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703 ||
15086 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704) {
15087 u32 ccval = (tr32(TG3PCI_CLOCK_CTRL) & 0x1f);
15088 u32 read_water = 0x7;
15090 /* If the 5704 is behind the EPB bridge, we can
15091 * do the less restrictive ONE_DMA workaround for
15092 * better performance.
15094 if (tg3_flag(tp, 40BIT_DMA_BUG) &&
15095 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704)
15096 tp->dma_rwctrl |= 0x8000;
15097 else if (ccval == 0x6 || ccval == 0x7)
15098 tp->dma_rwctrl |= DMA_RWCTRL_ONE_DMA;
15100 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703)
15102 /* Set bit 23 to enable PCIX hw bug fix */
15104 (read_water << DMA_RWCTRL_READ_WATER_SHIFT) |
15105 (0x3 << DMA_RWCTRL_WRITE_WATER_SHIFT) |
15107 } else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5780) {
15108 /* 5780 always in PCIX mode */
15109 tp->dma_rwctrl |= 0x00144000;
15110 } else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5714) {
15111 /* 5714 always in PCIX mode */
15112 tp->dma_rwctrl |= 0x00148000;
15114 tp->dma_rwctrl |= 0x001b000f;
15118 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703 ||
15119 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704)
15120 tp->dma_rwctrl &= 0xfffffff0;
15122 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
15123 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701) {
15124 /* Remove this if it causes problems for some boards. */
15125 tp->dma_rwctrl |= DMA_RWCTRL_USE_MEM_READ_MULT;
15127 /* On 5700/5701 chips, we need to set this bit.
15128 * Otherwise the chip will issue cacheline transactions
15129 * to streamable DMA memory with not all the byte
15130 * enables turned on. This is an error on several
15131 * RISC PCI controllers, in particular sparc64.
15133 * On 5703/5704 chips, this bit has been reassigned
15134 * a different meaning. In particular, it is used
15135 * on those chips to enable a PCI-X workaround.
15137 tp->dma_rwctrl |= DMA_RWCTRL_ASSERT_ALL_BE;
15140 tw32(TG3PCI_DMA_RW_CTRL, tp->dma_rwctrl);
15143 /* Unneeded, already done by tg3_get_invariants. */
15144 tg3_switch_clocks(tp);
15147 if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5700 &&
15148 GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5701)
15151 /* It is best to perform DMA test with maximum write burst size
15152 * to expose the 5700/5701 write DMA bug.
15154 saved_dma_rwctrl = tp->dma_rwctrl;
15155 tp->dma_rwctrl &= ~DMA_RWCTRL_WRITE_BNDRY_MASK;
15156 tw32(TG3PCI_DMA_RW_CTRL, tp->dma_rwctrl);
15161 for (i = 0; i < TEST_BUFFER_SIZE / sizeof(u32); i++)
15164 /* Send the buffer to the chip. */
15165 ret = tg3_do_test_dma(tp, buf, buf_dma, TEST_BUFFER_SIZE, 1);
15167 dev_err(&tp->pdev->dev,
15168 "%s: Buffer write failed. err = %d\n",
15174 /* validate data reached card RAM correctly. */
15175 for (i = 0; i < TEST_BUFFER_SIZE / sizeof(u32); i++) {
15177 tg3_read_mem(tp, 0x2100 + (i*4), &val);
15178 if (le32_to_cpu(val) != p[i]) {
15179 dev_err(&tp->pdev->dev,
15180 "%s: Buffer corrupted on device! "
15181 "(%d != %d)\n", __func__, val, i);
15182 /* ret = -ENODEV here? */
15187 /* Now read it back. */
15188 ret = tg3_do_test_dma(tp, buf, buf_dma, TEST_BUFFER_SIZE, 0);
15190 dev_err(&tp->pdev->dev, "%s: Buffer read failed. "
15191 "err = %d\n", __func__, ret);
15196 for (i = 0; i < TEST_BUFFER_SIZE / sizeof(u32); i++) {
15200 if ((tp->dma_rwctrl & DMA_RWCTRL_WRITE_BNDRY_MASK) !=
15201 DMA_RWCTRL_WRITE_BNDRY_16) {
15202 tp->dma_rwctrl &= ~DMA_RWCTRL_WRITE_BNDRY_MASK;
15203 tp->dma_rwctrl |= DMA_RWCTRL_WRITE_BNDRY_16;
15204 tw32(TG3PCI_DMA_RW_CTRL, tp->dma_rwctrl);
15207 dev_err(&tp->pdev->dev,
15208 "%s: Buffer corrupted on read back! "
15209 "(%d != %d)\n", __func__, p[i], i);
15215 if (i == (TEST_BUFFER_SIZE / sizeof(u32))) {
15221 if ((tp->dma_rwctrl & DMA_RWCTRL_WRITE_BNDRY_MASK) !=
15222 DMA_RWCTRL_WRITE_BNDRY_16) {
15223 /* DMA test passed without adjusting DMA boundary,
15224 * now look for chipsets that are known to expose the
15225 * DMA bug without failing the test.
15227 if (pci_dev_present(tg3_dma_wait_state_chipsets)) {
15228 tp->dma_rwctrl &= ~DMA_RWCTRL_WRITE_BNDRY_MASK;
15229 tp->dma_rwctrl |= DMA_RWCTRL_WRITE_BNDRY_16;
15231 /* Safe to use the calculated DMA boundary. */
15232 tp->dma_rwctrl = saved_dma_rwctrl;
15235 tw32(TG3PCI_DMA_RW_CTRL, tp->dma_rwctrl);
15239 dma_free_coherent(&tp->pdev->dev, TEST_BUFFER_SIZE, buf, buf_dma);
15244 static void __devinit tg3_init_bufmgr_config(struct tg3 *tp)
15246 if (tg3_flag(tp, 57765_PLUS)) {
15247 tp->bufmgr_config.mbuf_read_dma_low_water =
15248 DEFAULT_MB_RDMA_LOW_WATER_5705;
15249 tp->bufmgr_config.mbuf_mac_rx_low_water =
15250 DEFAULT_MB_MACRX_LOW_WATER_57765;
15251 tp->bufmgr_config.mbuf_high_water =
15252 DEFAULT_MB_HIGH_WATER_57765;
15254 tp->bufmgr_config.mbuf_read_dma_low_water_jumbo =
15255 DEFAULT_MB_RDMA_LOW_WATER_5705;
15256 tp->bufmgr_config.mbuf_mac_rx_low_water_jumbo =
15257 DEFAULT_MB_MACRX_LOW_WATER_JUMBO_57765;
15258 tp->bufmgr_config.mbuf_high_water_jumbo =
15259 DEFAULT_MB_HIGH_WATER_JUMBO_57765;
15260 } else if (tg3_flag(tp, 5705_PLUS)) {
15261 tp->bufmgr_config.mbuf_read_dma_low_water =
15262 DEFAULT_MB_RDMA_LOW_WATER_5705;
15263 tp->bufmgr_config.mbuf_mac_rx_low_water =
15264 DEFAULT_MB_MACRX_LOW_WATER_5705;
15265 tp->bufmgr_config.mbuf_high_water =
15266 DEFAULT_MB_HIGH_WATER_5705;
15267 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
15268 tp->bufmgr_config.mbuf_mac_rx_low_water =
15269 DEFAULT_MB_MACRX_LOW_WATER_5906;
15270 tp->bufmgr_config.mbuf_high_water =
15271 DEFAULT_MB_HIGH_WATER_5906;
15274 tp->bufmgr_config.mbuf_read_dma_low_water_jumbo =
15275 DEFAULT_MB_RDMA_LOW_WATER_JUMBO_5780;
15276 tp->bufmgr_config.mbuf_mac_rx_low_water_jumbo =
15277 DEFAULT_MB_MACRX_LOW_WATER_JUMBO_5780;
15278 tp->bufmgr_config.mbuf_high_water_jumbo =
15279 DEFAULT_MB_HIGH_WATER_JUMBO_5780;
15281 tp->bufmgr_config.mbuf_read_dma_low_water =
15282 DEFAULT_MB_RDMA_LOW_WATER;
15283 tp->bufmgr_config.mbuf_mac_rx_low_water =
15284 DEFAULT_MB_MACRX_LOW_WATER;
15285 tp->bufmgr_config.mbuf_high_water =
15286 DEFAULT_MB_HIGH_WATER;
15288 tp->bufmgr_config.mbuf_read_dma_low_water_jumbo =
15289 DEFAULT_MB_RDMA_LOW_WATER_JUMBO;
15290 tp->bufmgr_config.mbuf_mac_rx_low_water_jumbo =
15291 DEFAULT_MB_MACRX_LOW_WATER_JUMBO;
15292 tp->bufmgr_config.mbuf_high_water_jumbo =
15293 DEFAULT_MB_HIGH_WATER_JUMBO;
15296 tp->bufmgr_config.dma_low_water = DEFAULT_DMA_LOW_WATER;
15297 tp->bufmgr_config.dma_high_water = DEFAULT_DMA_HIGH_WATER;
15300 static char * __devinit tg3_phy_string(struct tg3 *tp)
15302 switch (tp->phy_id & TG3_PHY_ID_MASK) {
15303 case TG3_PHY_ID_BCM5400: return "5400";
15304 case TG3_PHY_ID_BCM5401: return "5401";
15305 case TG3_PHY_ID_BCM5411: return "5411";
15306 case TG3_PHY_ID_BCM5701: return "5701";
15307 case TG3_PHY_ID_BCM5703: return "5703";
15308 case TG3_PHY_ID_BCM5704: return "5704";
15309 case TG3_PHY_ID_BCM5705: return "5705";
15310 case TG3_PHY_ID_BCM5750: return "5750";
15311 case TG3_PHY_ID_BCM5752: return "5752";
15312 case TG3_PHY_ID_BCM5714: return "5714";
15313 case TG3_PHY_ID_BCM5780: return "5780";
15314 case TG3_PHY_ID_BCM5755: return "5755";
15315 case TG3_PHY_ID_BCM5787: return "5787";
15316 case TG3_PHY_ID_BCM5784: return "5784";
15317 case TG3_PHY_ID_BCM5756: return "5722/5756";
15318 case TG3_PHY_ID_BCM5906: return "5906";
15319 case TG3_PHY_ID_BCM5761: return "5761";
15320 case TG3_PHY_ID_BCM5718C: return "5718C";
15321 case TG3_PHY_ID_BCM5718S: return "5718S";
15322 case TG3_PHY_ID_BCM57765: return "57765";
15323 case TG3_PHY_ID_BCM5719C: return "5719C";
15324 case TG3_PHY_ID_BCM5720C: return "5720C";
15325 case TG3_PHY_ID_BCM8002: return "8002/serdes";
15326 case 0: return "serdes";
15327 default: return "unknown";
15331 static char * __devinit tg3_bus_string(struct tg3 *tp, char *str)
15333 if (tg3_flag(tp, PCI_EXPRESS)) {
15334 strcpy(str, "PCI Express");
15336 } else if (tg3_flag(tp, PCIX_MODE)) {
15337 u32 clock_ctrl = tr32(TG3PCI_CLOCK_CTRL) & 0x1f;
15339 strcpy(str, "PCIX:");
15341 if ((clock_ctrl == 7) ||
15342 ((tr32(GRC_MISC_CFG) & GRC_MISC_CFG_BOARD_ID_MASK) ==
15343 GRC_MISC_CFG_BOARD_ID_5704CIOBE))
15344 strcat(str, "133MHz");
15345 else if (clock_ctrl == 0)
15346 strcat(str, "33MHz");
15347 else if (clock_ctrl == 2)
15348 strcat(str, "50MHz");
15349 else if (clock_ctrl == 4)
15350 strcat(str, "66MHz");
15351 else if (clock_ctrl == 6)
15352 strcat(str, "100MHz");
15354 strcpy(str, "PCI:");
15355 if (tg3_flag(tp, PCI_HIGH_SPEED))
15356 strcat(str, "66MHz");
15358 strcat(str, "33MHz");
15360 if (tg3_flag(tp, PCI_32BIT))
15361 strcat(str, ":32-bit");
15363 strcat(str, ":64-bit");
15367 static struct pci_dev * __devinit tg3_find_peer(struct tg3 *tp)
15369 struct pci_dev *peer;
15370 unsigned int func, devnr = tp->pdev->devfn & ~7;
15372 for (func = 0; func < 8; func++) {
15373 peer = pci_get_slot(tp->pdev->bus, devnr | func);
15374 if (peer && peer != tp->pdev)
15378 /* 5704 can be configured in single-port mode, set peer to
15379 * tp->pdev in that case.
15387 * We don't need to keep the refcount elevated; there's no way
15388 * to remove one half of this device without removing the other
15395 static void __devinit tg3_init_coal(struct tg3 *tp)
15397 struct ethtool_coalesce *ec = &tp->coal;
15399 memset(ec, 0, sizeof(*ec));
15400 ec->cmd = ETHTOOL_GCOALESCE;
15401 ec->rx_coalesce_usecs = LOW_RXCOL_TICKS;
15402 ec->tx_coalesce_usecs = LOW_TXCOL_TICKS;
15403 ec->rx_max_coalesced_frames = LOW_RXMAX_FRAMES;
15404 ec->tx_max_coalesced_frames = LOW_TXMAX_FRAMES;
15405 ec->rx_coalesce_usecs_irq = DEFAULT_RXCOAL_TICK_INT;
15406 ec->tx_coalesce_usecs_irq = DEFAULT_TXCOAL_TICK_INT;
15407 ec->rx_max_coalesced_frames_irq = DEFAULT_RXCOAL_MAXF_INT;
15408 ec->tx_max_coalesced_frames_irq = DEFAULT_TXCOAL_MAXF_INT;
15409 ec->stats_block_coalesce_usecs = DEFAULT_STAT_COAL_TICKS;
15411 if (tp->coalesce_mode & (HOSTCC_MODE_CLRTICK_RXBD |
15412 HOSTCC_MODE_CLRTICK_TXBD)) {
15413 ec->rx_coalesce_usecs = LOW_RXCOL_TICKS_CLRTCKS;
15414 ec->rx_coalesce_usecs_irq = DEFAULT_RXCOAL_TICK_INT_CLRTCKS;
15415 ec->tx_coalesce_usecs = LOW_TXCOL_TICKS_CLRTCKS;
15416 ec->tx_coalesce_usecs_irq = DEFAULT_TXCOAL_TICK_INT_CLRTCKS;
15419 if (tg3_flag(tp, 5705_PLUS)) {
15420 ec->rx_coalesce_usecs_irq = 0;
15421 ec->tx_coalesce_usecs_irq = 0;
15422 ec->stats_block_coalesce_usecs = 0;
15426 static int __devinit tg3_init_one(struct pci_dev *pdev,
15427 const struct pci_device_id *ent)
15429 struct net_device *dev;
15431 int i, err, pm_cap;
15432 u32 sndmbx, rcvmbx, intmbx;
15434 u64 dma_mask, persist_dma_mask;
15435 netdev_features_t features = 0;
15437 printk_once(KERN_INFO "%s\n", version);
15439 err = pci_enable_device(pdev);
15441 dev_err(&pdev->dev, "Cannot enable PCI device, aborting\n");
15445 err = pci_request_regions(pdev, DRV_MODULE_NAME);
15447 dev_err(&pdev->dev, "Cannot obtain PCI resources, aborting\n");
15448 goto err_out_disable_pdev;
15451 pci_set_master(pdev);
15453 /* Find power-management capability. */
15454 pm_cap = pci_find_capability(pdev, PCI_CAP_ID_PM);
15456 dev_err(&pdev->dev,
15457 "Cannot find Power Management capability, aborting\n");
15459 goto err_out_free_res;
15462 err = pci_set_power_state(pdev, PCI_D0);
15464 dev_err(&pdev->dev, "Transition to D0 failed, aborting\n");
15465 goto err_out_free_res;
15468 dev = alloc_etherdev_mq(sizeof(*tp), TG3_IRQ_MAX_VECS);
15471 goto err_out_power_down;
15474 SET_NETDEV_DEV(dev, &pdev->dev);
15476 tp = netdev_priv(dev);
15479 tp->pm_cap = pm_cap;
15480 tp->rx_mode = TG3_DEF_RX_MODE;
15481 tp->tx_mode = TG3_DEF_TX_MODE;
15484 tp->msg_enable = tg3_debug;
15486 tp->msg_enable = TG3_DEF_MSG_ENABLE;
15488 /* The word/byte swap controls here control register access byte
15489 * swapping. DMA data byte swapping is controlled in the GRC_MODE
15492 tp->misc_host_ctrl =
15493 MISC_HOST_CTRL_MASK_PCI_INT |
15494 MISC_HOST_CTRL_WORD_SWAP |
15495 MISC_HOST_CTRL_INDIR_ACCESS |
15496 MISC_HOST_CTRL_PCISTATE_RW;
15498 /* The NONFRM (non-frame) byte/word swap controls take effect
15499 * on descriptor entries, anything which isn't packet data.
15501 * The StrongARM chips on the board (one for tx, one for rx)
15502 * are running in big-endian mode.
15504 tp->grc_mode = (GRC_MODE_WSWAP_DATA | GRC_MODE_BSWAP_DATA |
15505 GRC_MODE_WSWAP_NONFRM_DATA);
15506 #ifdef __BIG_ENDIAN
15507 tp->grc_mode |= GRC_MODE_BSWAP_NONFRM_DATA;
15509 spin_lock_init(&tp->lock);
15510 spin_lock_init(&tp->indirect_lock);
15511 INIT_WORK(&tp->reset_task, tg3_reset_task);
15513 tp->regs = pci_ioremap_bar(pdev, BAR_0);
15515 dev_err(&pdev->dev, "Cannot map device registers, aborting\n");
15517 goto err_out_free_dev;
15520 if (tp->pdev->device == PCI_DEVICE_ID_TIGON3_5761 ||
15521 tp->pdev->device == PCI_DEVICE_ID_TIGON3_5761E ||
15522 tp->pdev->device == TG3PCI_DEVICE_TIGON3_5761S ||
15523 tp->pdev->device == TG3PCI_DEVICE_TIGON3_5761SE ||
15524 tp->pdev->device == TG3PCI_DEVICE_TIGON3_5717 ||
15525 tp->pdev->device == TG3PCI_DEVICE_TIGON3_5718 ||
15526 tp->pdev->device == TG3PCI_DEVICE_TIGON3_5719 ||
15527 tp->pdev->device == TG3PCI_DEVICE_TIGON3_5720) {
15528 tg3_flag_set(tp, ENABLE_APE);
15529 tp->aperegs = pci_ioremap_bar(pdev, BAR_2);
15530 if (!tp->aperegs) {
15531 dev_err(&pdev->dev,
15532 "Cannot map APE registers, aborting\n");
15534 goto err_out_iounmap;
15538 tp->rx_pending = TG3_DEF_RX_RING_PENDING;
15539 tp->rx_jumbo_pending = TG3_DEF_RX_JUMBO_RING_PENDING;
15541 dev->ethtool_ops = &tg3_ethtool_ops;
15542 dev->watchdog_timeo = TG3_TX_TIMEOUT;
15543 dev->netdev_ops = &tg3_netdev_ops;
15544 dev->irq = pdev->irq;
15546 err = tg3_get_invariants(tp);
15548 dev_err(&pdev->dev,
15549 "Problem fetching invariants of chip, aborting\n");
15550 goto err_out_apeunmap;
15553 /* The EPB bridge inside 5714, 5715, and 5780 and any
15554 * device behind the EPB cannot support DMA addresses > 40-bit.
15555 * On 64-bit systems with IOMMU, use 40-bit dma_mask.
15556 * On 64-bit systems without IOMMU, use 64-bit dma_mask and
15557 * do DMA address check in tg3_start_xmit().
15559 if (tg3_flag(tp, IS_5788))
15560 persist_dma_mask = dma_mask = DMA_BIT_MASK(32);
15561 else if (tg3_flag(tp, 40BIT_DMA_BUG)) {
15562 persist_dma_mask = dma_mask = DMA_BIT_MASK(40);
15563 #ifdef CONFIG_HIGHMEM
15564 dma_mask = DMA_BIT_MASK(64);
15567 persist_dma_mask = dma_mask = DMA_BIT_MASK(64);
15569 /* Configure DMA attributes. */
15570 if (dma_mask > DMA_BIT_MASK(32)) {
15571 err = pci_set_dma_mask(pdev, dma_mask);
15573 features |= NETIF_F_HIGHDMA;
15574 err = pci_set_consistent_dma_mask(pdev,
15577 dev_err(&pdev->dev, "Unable to obtain 64 bit "
15578 "DMA for consistent allocations\n");
15579 goto err_out_apeunmap;
15583 if (err || dma_mask == DMA_BIT_MASK(32)) {
15584 err = pci_set_dma_mask(pdev, DMA_BIT_MASK(32));
15586 dev_err(&pdev->dev,
15587 "No usable DMA configuration, aborting\n");
15588 goto err_out_apeunmap;
15592 tg3_init_bufmgr_config(tp);
15594 features |= NETIF_F_HW_VLAN_TX | NETIF_F_HW_VLAN_RX;
15596 /* 5700 B0 chips do not support checksumming correctly due
15597 * to hardware bugs.
15599 if (tp->pci_chip_rev_id != CHIPREV_ID_5700_B0) {
15600 features |= NETIF_F_SG | NETIF_F_IP_CSUM | NETIF_F_RXCSUM;
15602 if (tg3_flag(tp, 5755_PLUS))
15603 features |= NETIF_F_IPV6_CSUM;
15606 /* TSO is on by default on chips that support hardware TSO.
15607 * Firmware TSO on older chips gives lower performance, so it
15608 * is off by default, but can be enabled using ethtool.
15610 if ((tg3_flag(tp, HW_TSO_1) ||
15611 tg3_flag(tp, HW_TSO_2) ||
15612 tg3_flag(tp, HW_TSO_3)) &&
15613 (features & NETIF_F_IP_CSUM))
15614 features |= NETIF_F_TSO;
15615 if (tg3_flag(tp, HW_TSO_2) || tg3_flag(tp, HW_TSO_3)) {
15616 if (features & NETIF_F_IPV6_CSUM)
15617 features |= NETIF_F_TSO6;
15618 if (tg3_flag(tp, HW_TSO_3) ||
15619 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5761 ||
15620 (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5784 &&
15621 GET_CHIP_REV(tp->pci_chip_rev_id) != CHIPREV_5784_AX) ||
15622 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785 ||
15623 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57780)
15624 features |= NETIF_F_TSO_ECN;
15627 dev->features |= features;
15628 dev->vlan_features |= features;
15631 * Add loopback capability only for a subset of devices that support
15632 * MAC-LOOPBACK. Eventually this need to be enhanced to allow INT-PHY
15633 * loopback for the remaining devices.
15635 if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5780 &&
15636 !tg3_flag(tp, CPMU_PRESENT))
15637 /* Add the loopback capability */
15638 features |= NETIF_F_LOOPBACK;
15640 dev->hw_features |= features;
15642 if (tp->pci_chip_rev_id == CHIPREV_ID_5705_A1 &&
15643 !tg3_flag(tp, TSO_CAPABLE) &&
15644 !(tr32(TG3PCI_PCISTATE) & PCISTATE_BUS_SPEED_HIGH)) {
15645 tg3_flag_set(tp, MAX_RXPEND_64);
15646 tp->rx_pending = 63;
15649 err = tg3_get_device_address(tp);
15651 dev_err(&pdev->dev,
15652 "Could not obtain valid ethernet address, aborting\n");
15653 goto err_out_apeunmap;
15657 * Reset chip in case UNDI or EFI driver did not shutdown
15658 * DMA self test will enable WDMAC and we'll see (spurious)
15659 * pending DMA on the PCI bus at that point.
15661 if ((tr32(HOSTCC_MODE) & HOSTCC_MODE_ENABLE) ||
15662 (tr32(WDMAC_MODE) & WDMAC_MODE_ENABLE)) {
15663 tw32(MEMARB_MODE, MEMARB_MODE_ENABLE);
15664 tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
15667 err = tg3_test_dma(tp);
15669 dev_err(&pdev->dev, "DMA engine test failed, aborting\n");
15670 goto err_out_apeunmap;
15673 intmbx = MAILBOX_INTERRUPT_0 + TG3_64BIT_REG_LOW;
15674 rcvmbx = MAILBOX_RCVRET_CON_IDX_0 + TG3_64BIT_REG_LOW;
15675 sndmbx = MAILBOX_SNDHOST_PROD_IDX_0 + TG3_64BIT_REG_LOW;
15676 for (i = 0; i < tp->irq_max; i++) {
15677 struct tg3_napi *tnapi = &tp->napi[i];
15680 tnapi->tx_pending = TG3_DEF_TX_RING_PENDING;
15682 tnapi->int_mbox = intmbx;
15688 tnapi->consmbox = rcvmbx;
15689 tnapi->prodmbox = sndmbx;
15692 tnapi->coal_now = HOSTCC_MODE_COAL_VEC1_NOW << (i - 1);
15694 tnapi->coal_now = HOSTCC_MODE_NOW;
15696 if (!tg3_flag(tp, SUPPORT_MSIX))
15700 * If we support MSIX, we'll be using RSS. If we're using
15701 * RSS, the first vector only handles link interrupts and the
15702 * remaining vectors handle rx and tx interrupts. Reuse the
15703 * mailbox values for the next iteration. The values we setup
15704 * above are still useful for the single vectored mode.
15719 pci_set_drvdata(pdev, dev);
15721 if (tg3_flag(tp, 5717_PLUS)) {
15722 /* Resume a low-power mode */
15723 tg3_frob_aux_power(tp, false);
15726 err = register_netdev(dev);
15728 dev_err(&pdev->dev, "Cannot register net device, aborting\n");
15729 goto err_out_apeunmap;
15732 netdev_info(dev, "Tigon3 [partno(%s) rev %04x] (%s) MAC address %pM\n",
15733 tp->board_part_number,
15734 tp->pci_chip_rev_id,
15735 tg3_bus_string(tp, str),
15738 if (tp->phy_flags & TG3_PHYFLG_IS_CONNECTED) {
15739 struct phy_device *phydev;
15740 phydev = tp->mdio_bus->phy_map[TG3_PHY_MII_ADDR];
15742 "attached PHY driver [%s] (mii_bus:phy_addr=%s)\n",
15743 phydev->drv->name, dev_name(&phydev->dev));
15747 if (tp->phy_flags & TG3_PHYFLG_10_100_ONLY)
15748 ethtype = "10/100Base-TX";
15749 else if (tp->phy_flags & TG3_PHYFLG_ANY_SERDES)
15750 ethtype = "1000Base-SX";
15752 ethtype = "10/100/1000Base-T";
15754 netdev_info(dev, "attached PHY is %s (%s Ethernet) "
15755 "(WireSpeed[%d], EEE[%d])\n",
15756 tg3_phy_string(tp), ethtype,
15757 (tp->phy_flags & TG3_PHYFLG_NO_ETH_WIRE_SPEED) == 0,
15758 (tp->phy_flags & TG3_PHYFLG_EEE_CAP) != 0);
15761 netdev_info(dev, "RXcsums[%d] LinkChgREG[%d] MIirq[%d] ASF[%d] TSOcap[%d]\n",
15762 (dev->features & NETIF_F_RXCSUM) != 0,
15763 tg3_flag(tp, USE_LINKCHG_REG) != 0,
15764 (tp->phy_flags & TG3_PHYFLG_USE_MI_INTERRUPT) != 0,
15765 tg3_flag(tp, ENABLE_ASF) != 0,
15766 tg3_flag(tp, TSO_CAPABLE) != 0);
15767 netdev_info(dev, "dma_rwctrl[%08x] dma_mask[%d-bit]\n",
15769 pdev->dma_mask == DMA_BIT_MASK(32) ? 32 :
15770 ((u64)pdev->dma_mask) == DMA_BIT_MASK(40) ? 40 : 64);
15772 pci_save_state(pdev);
15778 iounmap(tp->aperegs);
15779 tp->aperegs = NULL;
15791 err_out_power_down:
15792 pci_set_power_state(pdev, PCI_D3hot);
15795 pci_release_regions(pdev);
15797 err_out_disable_pdev:
15798 pci_disable_device(pdev);
15799 pci_set_drvdata(pdev, NULL);
15803 static void __devexit tg3_remove_one(struct pci_dev *pdev)
15805 struct net_device *dev = pci_get_drvdata(pdev);
15808 struct tg3 *tp = netdev_priv(dev);
15811 release_firmware(tp->fw);
15813 tg3_reset_task_cancel(tp);
15815 if (tg3_flag(tp, USE_PHYLIB)) {
15820 unregister_netdev(dev);
15822 iounmap(tp->aperegs);
15823 tp->aperegs = NULL;
15830 pci_release_regions(pdev);
15831 pci_disable_device(pdev);
15832 pci_set_drvdata(pdev, NULL);
15836 #ifdef CONFIG_PM_SLEEP
15837 static int tg3_suspend(struct device *device)
15839 struct pci_dev *pdev = to_pci_dev(device);
15840 struct net_device *dev = pci_get_drvdata(pdev);
15841 struct tg3 *tp = netdev_priv(dev);
15844 if (!netif_running(dev))
15847 tg3_reset_task_cancel(tp);
15849 tg3_netif_stop(tp);
15851 del_timer_sync(&tp->timer);
15853 tg3_full_lock(tp, 1);
15854 tg3_disable_ints(tp);
15855 tg3_full_unlock(tp);
15857 netif_device_detach(dev);
15859 tg3_full_lock(tp, 0);
15860 tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
15861 tg3_flag_clear(tp, INIT_COMPLETE);
15862 tg3_full_unlock(tp);
15864 err = tg3_power_down_prepare(tp);
15868 tg3_full_lock(tp, 0);
15870 tg3_flag_set(tp, INIT_COMPLETE);
15871 err2 = tg3_restart_hw(tp, 1);
15875 tp->timer.expires = jiffies + tp->timer_offset;
15876 add_timer(&tp->timer);
15878 netif_device_attach(dev);
15879 tg3_netif_start(tp);
15882 tg3_full_unlock(tp);
15891 static int tg3_resume(struct device *device)
15893 struct pci_dev *pdev = to_pci_dev(device);
15894 struct net_device *dev = pci_get_drvdata(pdev);
15895 struct tg3 *tp = netdev_priv(dev);
15898 if (!netif_running(dev))
15901 netif_device_attach(dev);
15903 tg3_full_lock(tp, 0);
15905 tg3_flag_set(tp, INIT_COMPLETE);
15906 err = tg3_restart_hw(tp, 1);
15910 tp->timer.expires = jiffies + tp->timer_offset;
15911 add_timer(&tp->timer);
15913 tg3_netif_start(tp);
15916 tg3_full_unlock(tp);
15924 static SIMPLE_DEV_PM_OPS(tg3_pm_ops, tg3_suspend, tg3_resume);
15925 #define TG3_PM_OPS (&tg3_pm_ops)
15929 #define TG3_PM_OPS NULL
15931 #endif /* CONFIG_PM_SLEEP */
15934 * tg3_io_error_detected - called when PCI error is detected
15935 * @pdev: Pointer to PCI device
15936 * @state: The current pci connection state
15938 * This function is called after a PCI bus error affecting
15939 * this device has been detected.
15941 static pci_ers_result_t tg3_io_error_detected(struct pci_dev *pdev,
15942 pci_channel_state_t state)
15944 struct net_device *netdev = pci_get_drvdata(pdev);
15945 struct tg3 *tp = netdev_priv(netdev);
15946 pci_ers_result_t err = PCI_ERS_RESULT_NEED_RESET;
15948 netdev_info(netdev, "PCI I/O error detected\n");
15952 if (!netif_running(netdev))
15957 tg3_netif_stop(tp);
15959 del_timer_sync(&tp->timer);
15961 /* Want to make sure that the reset task doesn't run */
15962 tg3_reset_task_cancel(tp);
15963 tg3_flag_clear(tp, TX_RECOVERY_PENDING);
15965 netif_device_detach(netdev);
15967 /* Clean up software state, even if MMIO is blocked */
15968 tg3_full_lock(tp, 0);
15969 tg3_halt(tp, RESET_KIND_SHUTDOWN, 0);
15970 tg3_full_unlock(tp);
15973 if (state == pci_channel_io_perm_failure)
15974 err = PCI_ERS_RESULT_DISCONNECT;
15976 pci_disable_device(pdev);
15984 * tg3_io_slot_reset - called after the pci bus has been reset.
15985 * @pdev: Pointer to PCI device
15987 * Restart the card from scratch, as if from a cold-boot.
15988 * At this point, the card has exprienced a hard reset,
15989 * followed by fixups by BIOS, and has its config space
15990 * set up identically to what it was at cold boot.
15992 static pci_ers_result_t tg3_io_slot_reset(struct pci_dev *pdev)
15994 struct net_device *netdev = pci_get_drvdata(pdev);
15995 struct tg3 *tp = netdev_priv(netdev);
15996 pci_ers_result_t rc = PCI_ERS_RESULT_DISCONNECT;
16001 if (pci_enable_device(pdev)) {
16002 netdev_err(netdev, "Cannot re-enable PCI device after reset.\n");
16006 pci_set_master(pdev);
16007 pci_restore_state(pdev);
16008 pci_save_state(pdev);
16010 if (!netif_running(netdev)) {
16011 rc = PCI_ERS_RESULT_RECOVERED;
16015 err = tg3_power_up(tp);
16019 rc = PCI_ERS_RESULT_RECOVERED;
16028 * tg3_io_resume - called when traffic can start flowing again.
16029 * @pdev: Pointer to PCI device
16031 * This callback is called when the error recovery driver tells
16032 * us that its OK to resume normal operation.
16034 static void tg3_io_resume(struct pci_dev *pdev)
16036 struct net_device *netdev = pci_get_drvdata(pdev);
16037 struct tg3 *tp = netdev_priv(netdev);
16042 if (!netif_running(netdev))
16045 tg3_full_lock(tp, 0);
16046 tg3_flag_set(tp, INIT_COMPLETE);
16047 err = tg3_restart_hw(tp, 1);
16048 tg3_full_unlock(tp);
16050 netdev_err(netdev, "Cannot restart hardware after reset.\n");
16054 netif_device_attach(netdev);
16056 tp->timer.expires = jiffies + tp->timer_offset;
16057 add_timer(&tp->timer);
16059 tg3_netif_start(tp);
16067 static struct pci_error_handlers tg3_err_handler = {
16068 .error_detected = tg3_io_error_detected,
16069 .slot_reset = tg3_io_slot_reset,
16070 .resume = tg3_io_resume
16073 static struct pci_driver tg3_driver = {
16074 .name = DRV_MODULE_NAME,
16075 .id_table = tg3_pci_tbl,
16076 .probe = tg3_init_one,
16077 .remove = __devexit_p(tg3_remove_one),
16078 .err_handler = &tg3_err_handler,
16079 .driver.pm = TG3_PM_OPS,
16082 static int __init tg3_init(void)
16084 return pci_register_driver(&tg3_driver);
16087 static void __exit tg3_cleanup(void)
16089 pci_unregister_driver(&tg3_driver);
16092 module_init(tg3_init);
16093 module_exit(tg3_cleanup);