drivers/net/ethernet/brocade/bna/bna_hw_defs.h

   1 /*
   2  * Linux network driver for Brocade Converged Network Adapter.
   3  *
   4  * This program is free software; you can redistribute it and/or modify it
   5  * under the terms of the GNU General Public License (GPL) Version 2 as
   6  * published by the Free Software Foundation
   7  *
   8  * This program is distributed in the hope that it will be useful, but
   9  * WITHOUT ANY WARRANTY; without even the implied warranty of
  10  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
  11  * General Public License for more details.
  12  */
  13 /*
  14  * Copyright (c) 2005-2011 Brocade Communications Systems, Inc.
  15  * All rights reserved
  16  * www.brocade.com
  17  */
  18
  19 /**
  20  * File for interrupt macros and functions
  21  */
  22
  23 #ifndef __BNA_HW_DEFS_H__
  24 #define __BNA_HW_DEFS_H__
  25
  26 #include "bfi_reg.h"
  27
  28 /**
  29  *
  30  * SW imposed limits
  31  *
  32  */
  33
  34 #define BFI_ENET_MAX_MCAM               256
  35
  36 #define BFI_INVALID_RID                 -1
  37
  38 #define BFI_IBIDX_SIZE                  4
  39
  40 #define BFI_VLAN_WORD_SHIFT             5       /* 32 bits */
  41 #define BFI_VLAN_WORD_MASK              0x1F
  42 #define BFI_VLAN_BLOCK_SHIFT            9       /* 512 bits */
  43 #define BFI_VLAN_BMASK_ALL              0xFF
  44
  45 #define BFI_COALESCING_TIMER_UNIT       5       /* 5us */
  46 #define BFI_MAX_COALESCING_TIMEO        0xFF    /* in 5us units */
  47 #define BFI_MAX_INTERPKT_COUNT          0xFF
  48 #define BFI_MAX_INTERPKT_TIMEO          0xF     /* in 0.5us units */
  49 #define BFI_TX_COALESCING_TIMEO         20      /* 20 * 5 = 100us */
  50 #define BFI_TX_INTERPKT_COUNT           32
  51 #define BFI_RX_COALESCING_TIMEO         12      /* 12 * 5 = 60us */
  52 #define BFI_RX_INTERPKT_COUNT           6       /* Pkt Cnt = 6 */
  53 #define BFI_RX_INTERPKT_TIMEO           3       /* 3 * 0.5 = 1.5us */
  54
  55 #define BFI_TXQ_WI_SIZE                 64      /* bytes */
  56 #define BFI_RXQ_WI_SIZE                 8       /* bytes */
  57 #define BFI_CQ_WI_SIZE                  16      /* bytes */
  58 #define BFI_TX_MAX_WRR_QUOTA            0xFFF
  59
  60 #define BFI_TX_MAX_VECTORS_PER_WI       4
  61 #define BFI_TX_MAX_VECTORS_PER_PKT      0xFF
  62 #define BFI_TX_MAX_DATA_PER_VECTOR      0xFFFF
  63 #define BFI_TX_MAX_DATA_PER_PKT         0xFFFFFF
  64
  65 /* Small Q buffer size */
  66 #define BFI_SMALL_RXBUF_SIZE            128
  67
  68 #define BFI_TX_MAX_PRIO                 8
  69 #define BFI_TX_PRIO_MAP_ALL             0xFF
  70
  71 /*
  72  *
  73  * Register definitions and macros
  74  *
  75  */
  76
  77 #define BNA_PCI_REG_CT_ADDRSZ           (0x40000)
  78
  79 #define ct_reg_addr_init(_bna, _pcidev)                                 \
  80 {                                                                       \
  81         struct bna_reg_offset reg_offset[] =                            \
  82         {{HOSTFN0_INT_STATUS, HOSTFN0_INT_MSK},                         \
  83          {HOSTFN1_INT_STATUS, HOSTFN1_INT_MSK},                         \
  84          {HOSTFN2_INT_STATUS, HOSTFN2_INT_MSK},                         \
  85          {HOSTFN3_INT_STATUS, HOSTFN3_INT_MSK} };                       \
  86                                                                         \
  87         (_bna)->regs.fn_int_status = (_pcidev)->pci_bar_kva +           \
  88                                 reg_offset[(_pcidev)->pci_func].fn_int_status;\
  89         (_bna)->regs.fn_int_mask = (_pcidev)->pci_bar_kva +             \
  90                                 reg_offset[(_pcidev)->pci_func].fn_int_mask;\
  91 }
  92
  93 #define ct_bit_defn_init(_bna, _pcidev)                                 \
  94 {                                                                       \
  95         (_bna)->bits.mbox_status_bits = (__HFN_INT_MBOX_LPU0 |          \
  96                                         __HFN_INT_MBOX_LPU1);           \
  97         (_bna)->bits.mbox_mask_bits = (__HFN_INT_MBOX_LPU0 |            \
  98                                         __HFN_INT_MBOX_LPU1);           \
  99         (_bna)->bits.error_status_bits = (__HFN_INT_ERR_MASK);          \
 100         (_bna)->bits.error_mask_bits = (__HFN_INT_ERR_MASK);            \
 101         (_bna)->bits.halt_status_bits = __HFN_INT_LL_HALT;              \
 102 }
 103
 104 #define ct2_reg_addr_init(_bna, _pcidev)                                \
 105 {                                                                       \
 106         (_bna)->regs.fn_int_status = (_pcidev)->pci_bar_kva +           \
 107                                 CT2_HOSTFN_INT_STATUS;                  \
 108         (_bna)->regs.fn_int_mask = (_pcidev)->pci_bar_kva +             \
 109                                 CT2_HOSTFN_INTR_MASK;                   \
 110 }
 111
 112 #define ct2_bit_defn_init(_bna, _pcidev)                                \
 113 {                                                                       \
 114         (_bna)->bits.mbox_status_bits = (__HFN_INT_MBOX_LPU0_CT2 |      \
 115                                         __HFN_INT_MBOX_LPU1_CT2);       \
 116         (_bna)->bits.mbox_mask_bits = (__HFN_INT_MBOX_LPU0_CT2 |        \
 117                                         __HFN_INT_MBOX_LPU1_CT2);       \
 118         (_bna)->bits.error_status_bits = (__HFN_INT_ERR_MASK_CT2);      \
 119         (_bna)->bits.error_mask_bits = (__HFN_INT_ERR_MASK_CT2);        \
 120         (_bna)->bits.halt_status_bits = __HFN_INT_CPQ_HALT_CT2;         \
 121         (_bna)->bits.halt_mask_bits = __HFN_INT_CPQ_HALT_CT2;           \
 122 }
 123
 124 #define bna_reg_addr_init(_bna, _pcidev)                                \
 125 {                                                                       \
 126         switch ((_pcidev)->device_id) {                                 \
 127         case PCI_DEVICE_ID_BROCADE_CT:                                  \
 128                 ct_reg_addr_init((_bna), (_pcidev));                    \
 129                 ct_bit_defn_init((_bna), (_pcidev));                    \
 130                 break;                                                  \
 131         }                                                               \
 132 }
 133
 134 #define bna_port_id_get(_bna) ((_bna)->ioceth.ioc.port_id)
 135 /**
 136  *
 137  *  Interrupt related bits, flags and macros
 138  *
 139  */
 140
 141 #define IB_STATUS_BITS          0x0000ffff
 142
 143 #define BNA_IS_MBOX_INTR(_bna, _intr_status)                            \
 144         ((_intr_status) & (_bna)->bits.mbox_status_bits)
 145
 146 #define BNA_IS_HALT_INTR(_bna, _intr_status)                            \
 147         ((_intr_status) & (_bna)->bits.halt_status_bits)
 148
 149 #define BNA_IS_ERR_INTR(_bna, _intr_status)     \
 150         ((_intr_status) & (_bna)->bits.error_status_bits)
 151
 152 #define BNA_IS_MBOX_ERR_INTR(_bna, _intr_status)        \
 153         (BNA_IS_MBOX_INTR(_bna, _intr_status) |         \
 154         BNA_IS_ERR_INTR(_bna, _intr_status))
 155
 156 #define BNA_IS_INTX_DATA_INTR(_intr_status)             \
 157                 ((_intr_status) & IB_STATUS_BITS)
 158
 159 #define bna_halt_clear(_bna)                                            \
 160 do {                                                                    \
 161         u32 init_halt;                                          \
 162         init_halt = readl((_bna)->ioceth.ioc.ioc_regs.ll_halt); \
 163         init_halt &= ~__FW_INIT_HALT_P;                                 \
 164         writel(init_halt, (_bna)->ioceth.ioc.ioc_regs.ll_halt); \
 165         init_halt = readl((_bna)->ioceth.ioc.ioc_regs.ll_halt); \
 166 } while (0)
 167
 168 #define bna_intx_disable(_bna, _cur_mask)                               \
 169 {                                                                       \
 170         (_cur_mask) = readl((_bna)->regs.fn_int_mask);          \
 171         writel(0xffffffff, (_bna)->regs.fn_int_mask);           \
 172 }
 173
 174 #define bna_intx_enable(bna, new_mask)                                  \
 175         writel((new_mask), (bna)->regs.fn_int_mask)
 176 #define bna_mbox_intr_disable(bna)                                      \
 177 do {                                                                    \
 178         u32 mask;                                                       \
 179         mask = readl((bna)->regs.fn_int_mask);                          \
 180         writel((mask | (bna)->bits.mbox_mask_bits |                     \
 181                 (bna)->bits.error_mask_bits), (bna)->regs.fn_int_mask); \
 182         mask = readl((bna)->regs.fn_int_mask);                          \
 183 } while (0)
 184
 185 #define bna_mbox_intr_enable(bna)                                       \
 186 do {                                                                    \
 187         u32 mask;                                                       \
 188         mask = readl((bna)->regs.fn_int_mask);                          \
 189         writel((mask & ~((bna)->bits.mbox_mask_bits |                   \
 190                 (bna)->bits.error_mask_bits)), (bna)->regs.fn_int_mask);\
 191         mask = readl((bna)->regs.fn_int_mask);                          \
 192 } while (0)
 193
 194 #define bna_intr_status_get(_bna, _status)                              \
 195 {                                                                       \
 196         (_status) = readl((_bna)->regs.fn_int_status);                  \
 197         if (_status) {                                                  \
 198                 writel(((_status) & ~(_bna)->bits.mbox_status_bits),    \
 199                         (_bna)->regs.fn_int_status);                    \
 200         }                                                               \
 201 }
 202
 203 /*
 204  * MAX ACK EVENTS : No. of acks that can be accumulated in driver,
 205  * before acking to h/w. The no. of bits is 16 in the doorbell register,
 206  * however we keep this limited to 15 bits.
 207  * This is because around the edge of 64K boundary (16 bits), one
 208  * single poll can make the accumulated ACK counter cross the 64K boundary,
 209  * causing problems, when we try to ack with a value greater than 64K.
 210  * 15 bits (32K) should  be large enough to accumulate, anyways, and the max.
 211  * acked events to h/w can be (32K + max poll weight) (currently 64).
 212  */
 213 #define BNA_IB_MAX_ACK_EVENTS           (1 << 15)
 214
 215 /* These macros build the data portion of the TxQ/RxQ doorbell */
 216 #define BNA_DOORBELL_Q_PRD_IDX(_pi)     (0x80000000 | (_pi))
 217 #define BNA_DOORBELL_Q_STOP             (0x40000000)
 218
 219 /* These macros build the data portion of the IB doorbell */
 220 #define BNA_DOORBELL_IB_INT_ACK(_timeout, _events)                      \
 221         (0x80000000 | ((_timeout) << 16) | (_events))
 222 #define BNA_DOORBELL_IB_INT_DISABLE     (0x40000000)
 223
 224 /* Set the coalescing timer for the given ib */
 225 #define bna_ib_coalescing_timer_set(_i_dbell, _cls_timer)               \
 226         ((_i_dbell)->doorbell_ack = BNA_DOORBELL_IB_INT_ACK((_cls_timer), 0));
 227
 228 /* Acks 'events' # of events for a given ib while disabling interrupts */
 229 #define bna_ib_ack_disable_irq(_i_dbell, _events)                       \
 230         (writel(BNA_DOORBELL_IB_INT_ACK(0, (_events)), \
 231                 (_i_dbell)->doorbell_addr));
 232
 233 /* Acks 'events' # of events for a given ib */
 234 #define bna_ib_ack(_i_dbell, _events)                                   \
 235         (writel(((_i_dbell)->doorbell_ack | (_events)), \
 236                 (_i_dbell)->doorbell_addr));
 237
 238 #define bna_ib_start(_bna, _ib, _is_regular)                            \
 239 {                                                                       \
 240         u32 intx_mask;                                          \
 241         struct bna_ib *ib = _ib;                                        \
 242         if ((ib->intr_type == BNA_INTR_T_INTX)) {                       \
 243                 bna_intx_disable((_bna), intx_mask);                    \
 244                 intx_mask &= ~(ib->intr_vector);                        \
 245                 bna_intx_enable((_bna), intx_mask);                     \
 246         }                                                               \
 247         bna_ib_coalescing_timer_set(&ib->door_bell,                     \
 248                         ib->coalescing_timeo);                          \
 249         if (_is_regular)                                                \
 250                 bna_ib_ack(&ib->door_bell, 0);                          \
 251 }
 252
 253 #define bna_ib_stop(_bna, _ib)                                          \
 254 {                                                                       \
 255         u32 intx_mask;                                          \
 256         struct bna_ib *ib = _ib;                                        \
 257         writel(BNA_DOORBELL_IB_INT_DISABLE,                             \
 258                 ib->door_bell.doorbell_addr);                           \
 259         if (ib->intr_type == BNA_INTR_T_INTX) {                         \
 260                 bna_intx_disable((_bna), intx_mask);                    \
 261                 intx_mask |= ib->intr_vector;                           \
 262                 bna_intx_enable((_bna), intx_mask);                     \
 263         }                                                               \
 264 }
 265
 266 #define bna_txq_prod_indx_doorbell(_tcb)                                \
 267         (writel(BNA_DOORBELL_Q_PRD_IDX((_tcb)->producer_index), \
 268                 (_tcb)->q_dbell));
 269
 270 #define bna_rxq_prod_indx_doorbell(_rcb)                                \
 271         (writel(BNA_DOORBELL_Q_PRD_IDX((_rcb)->producer_index), \
 272                 (_rcb)->q_dbell));
 273
 274 /**
 275  *
 276  * TxQ, RxQ, CQ related bits, offsets, macros
 277  *
 278  */
 279
 280 /* TxQ Entry Opcodes */
 281 #define BNA_TXQ_WI_SEND                 (0x402) /* Single Frame Transmission */
 282 #define BNA_TXQ_WI_SEND_LSO             (0x403) /* Multi-Frame Transmission */
 283 #define BNA_TXQ_WI_EXTENSION            (0x104) /* Extension WI */
 284
 285 /* TxQ Entry Control Flags */
 286 #define BNA_TXQ_WI_CF_FCOE_CRC          (1 << 8)
 287 #define BNA_TXQ_WI_CF_IPID_MODE         (1 << 5)
 288 #define BNA_TXQ_WI_CF_INS_PRIO          (1 << 4)
 289 #define BNA_TXQ_WI_CF_INS_VLAN          (1 << 3)
 290 #define BNA_TXQ_WI_CF_UDP_CKSUM         (1 << 2)
 291 #define BNA_TXQ_WI_CF_TCP_CKSUM         (1 << 1)
 292 #define BNA_TXQ_WI_CF_IP_CKSUM          (1 << 0)
 293
 294 #define BNA_TXQ_WI_L4_HDR_N_OFFSET(_hdr_size, _offset) \
 295                 (((_hdr_size) << 10) | ((_offset) & 0x3FF))
 296
 297 /*
 298  * Completion Q defines
 299  */
 300 /* CQ Entry Flags */
 301 #define BNA_CQ_EF_MAC_ERROR     (1 <<  0)
 302 #define BNA_CQ_EF_FCS_ERROR     (1 <<  1)
 303 #define BNA_CQ_EF_TOO_LONG      (1 <<  2)
 304 #define BNA_CQ_EF_FC_CRC_OK     (1 <<  3)
 305
 306 #define BNA_CQ_EF_RSVD1         (1 <<  4)
 307 #define BNA_CQ_EF_L4_CKSUM_OK   (1 <<  5)
 308 #define BNA_CQ_EF_L3_CKSUM_OK   (1 <<  6)
 309 #define BNA_CQ_EF_HDS_HEADER    (1 <<  7)
 310
 311 #define BNA_CQ_EF_UDP           (1 <<  8)
 312 #define BNA_CQ_EF_TCP           (1 <<  9)
 313 #define BNA_CQ_EF_IP_OPTIONS    (1 << 10)
 314 #define BNA_CQ_EF_IPV6          (1 << 11)
 315
 316 #define BNA_CQ_EF_IPV4          (1 << 12)
 317 #define BNA_CQ_EF_VLAN          (1 << 13)
 318 #define BNA_CQ_EF_RSS           (1 << 14)
 319 #define BNA_CQ_EF_RSVD2         (1 << 15)
 320
 321 #define BNA_CQ_EF_MCAST_MATCH   (1 << 16)
 322 #define BNA_CQ_EF_MCAST         (1 << 17)
 323 #define BNA_CQ_EF_BCAST         (1 << 18)
 324 #define BNA_CQ_EF_REMOTE        (1 << 19)
 325
 326 #define BNA_CQ_EF_LOCAL         (1 << 20)
 327
 328 /**
 329  *
 330  * Data structures
 331  *
 332  */
 333
 334 struct bna_reg_offset {
 335         u32 fn_int_status;
 336         u32 fn_int_mask;
 337 };
 338
 339 struct bna_bit_defn {
 340         u32 mbox_status_bits;
 341         u32 mbox_mask_bits;
 342         u32 error_status_bits;
 343         u32 error_mask_bits;
 344         u32 halt_status_bits;
 345         u32 halt_mask_bits;
 346 };
 347
 348 struct bna_reg {
 349         void __iomem *fn_int_status;
 350         void __iomem *fn_int_mask;
 351 };
 352
 353 /* TxQ Vector (a.k.a. Tx-Buffer Descriptor) */
 354 struct bna_dma_addr {
 355         u32             msb;
 356         u32             lsb;
 357 };
 358
 359 struct bna_txq_wi_vector {
 360         u16             reserved;
 361         u16             length;         /* Only 14 LSB are valid */
 362         struct bna_dma_addr host_addr; /* Tx-Buf DMA addr */
 363 };
 364
 365 /**
 366  *  TxQ Entry Structure
 367  *
 368  *  BEWARE:  Load values into this structure with correct endianess.
 369  */
 370 struct bna_txq_entry {
 371         union {
 372                 struct {
 373                         u8 reserved;
 374                         u8 num_vectors; /* number of vectors present */
 375                         u16 opcode; /* Either */
 376                                                     /* BNA_TXQ_WI_SEND or */
 377                                                     /* BNA_TXQ_WI_SEND_LSO */
 378                         u16 flags; /* OR of all the flags */
 379                         u16 l4_hdr_size_n_offset;
 380                         u16 vlan_tag;
 381                         u16 lso_mss;    /* Only 14 LSB are valid */
 382                         u32 frame_length;       /* Only 24 LSB are valid */
 383                 } wi;
 384
 385                 struct {
 386                         u16 reserved;
 387                         u16 opcode; /* Must be */
 388                                                     /* BNA_TXQ_WI_EXTENSION */
 389                         u32 reserved2[3];       /* Place holder for */
 390                                                 /* removed vector (12 bytes) */
 391                 } wi_ext;
 392         } hdr;
 393         struct bna_txq_wi_vector vector[4];
 394 };
 395
 396 /* RxQ Entry Structure */
 397 struct bna_rxq_entry {          /* Rx-Buffer */
 398         struct bna_dma_addr host_addr; /* Rx-Buffer DMA address */
 399 };
 400
 401 /* CQ Entry Structure */
 402 struct bna_cq_entry {
 403         u32 flags;
 404         u16 vlan_tag;
 405         u16 length;
 406         u32 rss_hash;
 407         u8 valid;
 408         u8 reserved1;
 409         u8 reserved2;
 410         u8 rxq_id;
 411 };
 412
 413 #endif /* __BNA_HW_DEFS_H__ */