2 * This file is part of the Chelsio T4 Ethernet driver for Linux.
4 * Copyright (c) 2003-2014 Chelsio Communications, Inc. All rights reserved.
6 * This software is available to you under a choice of one of two
7 * licenses. You may choose to be licensed under the terms of the GNU
8 * General Public License (GPL) Version 2, available from the file
9 * COPYING in the main directory of this source tree, or the
10 * OpenIB.org BSD license below:
12 * Redistribution and use in source and binary forms, with or
13 * without modification, are permitted provided that the following
16 * - Redistributions of source code must retain the above
17 * copyright notice, this list of conditions and the following
20 * - Redistributions in binary form must reproduce the above
21 * copyright notice, this list of conditions and the following
22 * disclaimer in the documentation and/or other materials
23 * provided with the distribution.
25 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
26 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
27 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
28 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
29 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
30 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
31 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
40 #include <linux/bitops.h>
41 #include <linux/cache.h>
42 #include <linux/interrupt.h>
43 #include <linux/list.h>
44 #include <linux/netdevice.h>
45 #include <linux/pci.h>
46 #include <linux/spinlock.h>
47 #include <linux/timer.h>
48 #include <linux/vmalloc.h>
49 #include <linux/etherdevice.h>
51 #include "cxgb4_uld.h"
53 #define CH_WARN(adap, fmt, ...) dev_warn(adap->pdev_dev, fmt, ## __VA_ARGS__)
56 MAX_NPORTS = 4, /* max # of ports */
57 SERNUM_LEN = 24, /* Serial # length */
58 EC_LEN = 16, /* E/C length */
59 ID_LEN = 16, /* ID length */
60 PN_LEN = 16, /* Part Number length */
61 MACADDR_LEN = 12, /* MAC Address length */
65 T4_REGMAP_SIZE = (160 * 1024),
66 T5_REGMAP_SIZE = (332 * 1024),
78 MEMWIN0_APERTURE = 2048,
79 MEMWIN0_BASE = 0x1b800,
80 MEMWIN1_APERTURE = 32768,
81 MEMWIN1_BASE = 0x28000,
82 MEMWIN1_BASE_T5 = 0x52000,
83 MEMWIN2_APERTURE = 65536,
84 MEMWIN2_BASE = 0x30000,
85 MEMWIN2_APERTURE_T5 = 131072,
86 MEMWIN2_BASE_T5 = 0x60000,
104 PAUSE_AUTONEG = 1 << 2
108 u64 tx_octets; /* total # of octets in good frames */
109 u64 tx_frames; /* all good frames */
110 u64 tx_bcast_frames; /* all broadcast frames */
111 u64 tx_mcast_frames; /* all multicast frames */
112 u64 tx_ucast_frames; /* all unicast frames */
113 u64 tx_error_frames; /* all error frames */
115 u64 tx_frames_64; /* # of Tx frames in a particular range */
116 u64 tx_frames_65_127;
117 u64 tx_frames_128_255;
118 u64 tx_frames_256_511;
119 u64 tx_frames_512_1023;
120 u64 tx_frames_1024_1518;
121 u64 tx_frames_1519_max;
123 u64 tx_drop; /* # of dropped Tx frames */
124 u64 tx_pause; /* # of transmitted pause frames */
125 u64 tx_ppp0; /* # of transmitted PPP prio 0 frames */
126 u64 tx_ppp1; /* # of transmitted PPP prio 1 frames */
127 u64 tx_ppp2; /* # of transmitted PPP prio 2 frames */
128 u64 tx_ppp3; /* # of transmitted PPP prio 3 frames */
129 u64 tx_ppp4; /* # of transmitted PPP prio 4 frames */
130 u64 tx_ppp5; /* # of transmitted PPP prio 5 frames */
131 u64 tx_ppp6; /* # of transmitted PPP prio 6 frames */
132 u64 tx_ppp7; /* # of transmitted PPP prio 7 frames */
134 u64 rx_octets; /* total # of octets in good frames */
135 u64 rx_frames; /* all good frames */
136 u64 rx_bcast_frames; /* all broadcast frames */
137 u64 rx_mcast_frames; /* all multicast frames */
138 u64 rx_ucast_frames; /* all unicast frames */
139 u64 rx_too_long; /* # of frames exceeding MTU */
140 u64 rx_jabber; /* # of jabber frames */
141 u64 rx_fcs_err; /* # of received frames with bad FCS */
142 u64 rx_len_err; /* # of received frames with length error */
143 u64 rx_symbol_err; /* symbol errors */
144 u64 rx_runt; /* # of short frames */
146 u64 rx_frames_64; /* # of Rx frames in a particular range */
147 u64 rx_frames_65_127;
148 u64 rx_frames_128_255;
149 u64 rx_frames_256_511;
150 u64 rx_frames_512_1023;
151 u64 rx_frames_1024_1518;
152 u64 rx_frames_1519_max;
154 u64 rx_pause; /* # of received pause frames */
155 u64 rx_ppp0; /* # of received PPP prio 0 frames */
156 u64 rx_ppp1; /* # of received PPP prio 1 frames */
157 u64 rx_ppp2; /* # of received PPP prio 2 frames */
158 u64 rx_ppp3; /* # of received PPP prio 3 frames */
159 u64 rx_ppp4; /* # of received PPP prio 4 frames */
160 u64 rx_ppp5; /* # of received PPP prio 5 frames */
161 u64 rx_ppp6; /* # of received PPP prio 6 frames */
162 u64 rx_ppp7; /* # of received PPP prio 7 frames */
164 u64 rx_ovflow0; /* drops due to buffer-group 0 overflows */
165 u64 rx_ovflow1; /* drops due to buffer-group 1 overflows */
166 u64 rx_ovflow2; /* drops due to buffer-group 2 overflows */
167 u64 rx_ovflow3; /* drops due to buffer-group 3 overflows */
168 u64 rx_trunc0; /* buffer-group 0 truncated packets */
169 u64 rx_trunc1; /* buffer-group 1 truncated packets */
170 u64 rx_trunc2; /* buffer-group 2 truncated packets */
171 u64 rx_trunc3; /* buffer-group 3 truncated packets */
174 struct lb_port_stats {
187 u64 frames_1024_1518;
202 struct tp_tcp_stats {
206 u64 tcp_retrans_segs;
209 struct tp_usm_stats {
215 struct tp_fcoe_stats {
221 struct tp_err_stats {
225 u32 tnl_cong_drops[4];
226 u32 ofld_chan_drops[4];
228 u32 ofld_vlan_drops[4];
234 struct tp_cpl_stats {
239 struct tp_rdma_stats {
245 u32 hps; /* host page size for our PF/VF */
246 u32 eq_qpp; /* egress queues/page for our PF/VF */
247 u32 iq_qpp; /* egress queues/page for our PF/VF */
251 unsigned int tre; /* log2 of core clocks per TP tick */
252 unsigned int la_mask; /* what events are recorded by TP LA */
253 unsigned short tx_modq_map; /* TX modulation scheduler queue to */
256 uint32_t dack_re; /* DACK timer resolution */
257 unsigned short tx_modq[NCHAN]; /* channel to modulation queue map */
259 u32 vlan_pri_map; /* cached TP_VLAN_PRI_MAP */
260 u32 ingress_config; /* cached TP_INGRESS_CONFIG */
262 /* TP_VLAN_PRI_MAP Compressed Filter Tuple field offsets. This is a
263 * subset of the set of fields which may be present in the Compressed
264 * Filter Tuple portion of filters and TCP TCB connections. The
265 * fields which are present are controlled by the TP_VLAN_PRI_MAP.
266 * Since a variable number of fields may or may not be present, their
267 * shifted field positions within the Compressed Filter Tuple may
268 * vary, or not even be present if the field isn't selected in
269 * TP_VLAN_PRI_MAP. Since some of these fields are needed in various
270 * places we store their offsets here, or a -1 if the field isn't
282 u8 sn[SERNUM_LEN + 1];
285 u8 na[MACADDR_LEN + 1];
293 #define CHELSIO_CHIP_CODE(version, revision) (((version) << 4) | (revision))
294 #define CHELSIO_CHIP_FPGA 0x100
295 #define CHELSIO_CHIP_VERSION(code) (((code) >> 4) & 0xf)
296 #define CHELSIO_CHIP_RELEASE(code) ((code) & 0xf)
298 #define CHELSIO_T4 0x4
299 #define CHELSIO_T5 0x5
300 #define CHELSIO_T6 0x6
303 T4_A1 = CHELSIO_CHIP_CODE(CHELSIO_T4, 1),
304 T4_A2 = CHELSIO_CHIP_CODE(CHELSIO_T4, 2),
305 T4_FIRST_REV = T4_A1,
308 T5_A0 = CHELSIO_CHIP_CODE(CHELSIO_T5, 0),
309 T5_A1 = CHELSIO_CHIP_CODE(CHELSIO_T5, 1),
310 T5_FIRST_REV = T5_A0,
313 T6_A0 = CHELSIO_CHIP_CODE(CHELSIO_T6, 0),
314 T6_FIRST_REV = T6_A0,
318 struct devlog_params {
319 u32 memtype; /* which memory (EDC0, EDC1, MC) */
320 u32 start; /* start of log in firmware memory */
321 u32 size; /* size of log */
324 /* Stores chip specific parameters */
325 struct arch_specific_params {
333 struct adapter_params {
334 struct sge_params sge;
336 struct vpd_params vpd;
337 struct pci_params pci;
338 struct devlog_params devlog;
339 enum pcie_memwin drv_memwin;
341 unsigned int cim_la_size;
343 unsigned int sf_size; /* serial flash size in bytes */
344 unsigned int sf_nsec; /* # of flash sectors */
345 unsigned int sf_fw_start; /* start of FW image in flash */
347 unsigned int fw_vers;
348 unsigned int tp_vers;
351 unsigned short mtus[NMTUS];
352 unsigned short a_wnd[NCCTRL_WIN];
353 unsigned short b_wnd[NCCTRL_WIN];
355 unsigned char nports; /* # of ethernet ports */
356 unsigned char portvec;
357 enum chip_type chip; /* chip code */
358 struct arch_specific_params arch; /* chip specific params */
359 unsigned char offload;
361 unsigned char bypass;
363 unsigned int ofldq_wr_cred;
364 bool ulptx_memwrite_dsgl; /* use of T5 DSGL allowed */
366 unsigned int max_ordird_qp; /* Max read depth per RDMA QP */
367 unsigned int max_ird_adapter; /* Max read depth per adapter */
370 /* State needed to monitor the forward progress of SGE Ingress DMA activities
371 * and possible hangs.
373 struct sge_idma_monitor_state {
374 unsigned int idma_1s_thresh; /* 1s threshold in Core Clock ticks */
375 unsigned int idma_stalled[2]; /* synthesized stalled timers in HZ */
376 unsigned int idma_state[2]; /* IDMA Hang detect state */
377 unsigned int idma_qid[2]; /* IDMA Hung Ingress Queue ID */
378 unsigned int idma_warn[2]; /* time to warning in HZ */
381 #include "t4fw_api.h"
383 #define FW_VERSION(chip) ( \
384 FW_HDR_FW_VER_MAJOR_G(chip##FW_VERSION_MAJOR) | \
385 FW_HDR_FW_VER_MINOR_G(chip##FW_VERSION_MINOR) | \
386 FW_HDR_FW_VER_MICRO_G(chip##FW_VERSION_MICRO) | \
387 FW_HDR_FW_VER_BUILD_G(chip##FW_VERSION_BUILD))
388 #define FW_INTFVER(chip, intf) (FW_HDR_INTFVER_##intf)
394 struct fw_hdr fw_hdr;
398 struct trace_params {
399 u32 data[TRACE_LEN / 4];
400 u32 mask[TRACE_LEN / 4];
401 unsigned short snap_len;
402 unsigned short min_len;
403 unsigned char skip_ofst;
404 unsigned char skip_len;
405 unsigned char invert;
410 unsigned short supported; /* link capabilities */
411 unsigned short advertising; /* advertised capabilities */
412 unsigned short requested_speed; /* speed user has requested */
413 unsigned short speed; /* actual link speed */
414 unsigned char requested_fc; /* flow control user has requested */
415 unsigned char fc; /* actual link flow control */
416 unsigned char autoneg; /* autonegotiating? */
417 unsigned char link_ok; /* link up? */
420 #define FW_LEN16(fw_struct) FW_CMD_LEN16_V(sizeof(fw_struct) / 16)
423 MAX_ETH_QSETS = 32, /* # of Ethernet Tx/Rx queue sets */
424 MAX_OFLD_QSETS = 16, /* # of offload Tx/Rx queue sets */
425 MAX_CTRL_QUEUES = NCHAN, /* # of control Tx queues */
426 MAX_RDMA_QUEUES = NCHAN, /* # of streaming RDMA Rx queues */
427 MAX_RDMA_CIQS = 32, /* # of RDMA concentrator IQs */
428 MAX_ISCSI_QUEUES = NCHAN, /* # of streaming iSCSI Rx queues */
432 MAX_TXQ_ENTRIES = 16384,
433 MAX_CTRL_TXQ_ENTRIES = 1024,
434 MAX_RSPQ_ENTRIES = 16384,
435 MAX_RX_BUFFERS = 16384,
436 MIN_TXQ_ENTRIES = 32,
437 MIN_CTRL_TXQ_ENTRIES = 32,
438 MIN_RSPQ_ENTRIES = 128,
443 INGQ_EXTRAS = 2, /* firmware event queue and */
444 /* forwarded interrupts */
445 MAX_INGQ = MAX_ETH_QSETS + MAX_OFLD_QSETS + MAX_RDMA_QUEUES
446 + MAX_RDMA_CIQS + MAX_ISCSI_QUEUES + INGQ_EXTRAS,
452 #include "cxgb4_dcb.h"
454 #ifdef CONFIG_CHELSIO_T4_FCOE
455 #include "cxgb4_fcoe.h"
456 #endif /* CONFIG_CHELSIO_T4_FCOE */
459 struct adapter *adapter;
461 s16 xact_addr_filt; /* index of exact MAC address filter */
462 u16 rss_size; /* size of VI's RSS table slice */
464 enum fw_port_type port_type;
468 u8 lport; /* associated offload logical port */
469 u8 nqsets; /* # of qsets */
470 u8 first_qset; /* index of first qset */
472 struct link_config link_cfg;
474 struct port_stats stats_base;
475 #ifdef CONFIG_CHELSIO_T4_DCB
476 struct port_dcb_info dcb; /* Data Center Bridging support */
478 #ifdef CONFIG_CHELSIO_T4_FCOE
479 struct cxgb_fcoe fcoe;
480 #endif /* CONFIG_CHELSIO_T4_FCOE */
486 enum { /* adapter flags */
487 FULL_INIT_DONE = (1 << 0),
488 DEV_ENABLED = (1 << 1),
489 USING_MSI = (1 << 2),
490 USING_MSIX = (1 << 3),
492 RSS_TNLALLLOOKUP = (1 << 5),
493 USING_SOFT_PARAMS = (1 << 6),
494 MASTER_PF = (1 << 7),
495 FW_OFLD_CONN = (1 << 9),
500 struct sge_fl { /* SGE free-buffer queue state */
501 unsigned int avail; /* # of available Rx buffers */
502 unsigned int pend_cred; /* new buffers since last FL DB ring */
503 unsigned int cidx; /* consumer index */
504 unsigned int pidx; /* producer index */
505 unsigned long alloc_failed; /* # of times buffer allocation failed */
506 unsigned long large_alloc_failed;
507 unsigned long starving;
509 unsigned int cntxt_id; /* SGE context id for the free list */
510 unsigned int size; /* capacity of free list */
511 struct rx_sw_desc *sdesc; /* address of SW Rx descriptor ring */
512 __be64 *desc; /* address of HW Rx descriptor ring */
513 dma_addr_t addr; /* bus address of HW ring start */
514 void __iomem *bar2_addr; /* address of BAR2 Queue registers */
515 unsigned int bar2_qid; /* Queue ID for BAR2 Queue registers */
518 /* A packet gather list */
520 struct page_frag frags[MAX_SKB_FRAGS];
521 void *va; /* virtual address of first byte */
522 unsigned int nfrags; /* # of fragments */
523 unsigned int tot_len; /* total length of fragments */
526 typedef int (*rspq_handler_t)(struct sge_rspq *q, const __be64 *rsp,
527 const struct pkt_gl *gl);
529 struct sge_rspq { /* state for an SGE response queue */
530 struct napi_struct napi;
531 const __be64 *cur_desc; /* current descriptor in queue */
532 unsigned int cidx; /* consumer index */
533 u8 gen; /* current generation bit */
534 u8 intr_params; /* interrupt holdoff parameters */
535 u8 next_intr_params; /* holdoff params for next interrupt */
537 u8 pktcnt_idx; /* interrupt packet threshold */
538 u8 uld; /* ULD handling this queue */
539 u8 idx; /* queue index within its group */
540 int offset; /* offset into current Rx buffer */
541 u16 cntxt_id; /* SGE context id for the response q */
542 u16 abs_id; /* absolute SGE id for the response q */
543 __be64 *desc; /* address of HW response ring */
544 dma_addr_t phys_addr; /* physical address of the ring */
545 void __iomem *bar2_addr; /* address of BAR2 Queue registers */
546 unsigned int bar2_qid; /* Queue ID for BAR2 Queue registers */
547 unsigned int iqe_len; /* entry size */
548 unsigned int size; /* capacity of response queue */
549 struct adapter *adap;
550 struct net_device *netdev; /* associated net device */
551 rspq_handler_t handler;
552 #ifdef CONFIG_NET_RX_BUSY_POLL
553 #define CXGB_POLL_STATE_IDLE 0
554 #define CXGB_POLL_STATE_NAPI BIT(0) /* NAPI owns this poll */
555 #define CXGB_POLL_STATE_POLL BIT(1) /* poll owns this poll */
556 #define CXGB_POLL_STATE_NAPI_YIELD BIT(2) /* NAPI yielded this poll */
557 #define CXGB_POLL_STATE_POLL_YIELD BIT(3) /* poll yielded this poll */
558 #define CXGB_POLL_YIELD (CXGB_POLL_STATE_NAPI_YIELD | \
559 CXGB_POLL_STATE_POLL_YIELD)
560 #define CXGB_POLL_LOCKED (CXGB_POLL_STATE_NAPI | \
561 CXGB_POLL_STATE_POLL)
562 #define CXGB_POLL_USER_PEND (CXGB_POLL_STATE_POLL | \
563 CXGB_POLL_STATE_POLL_YIELD)
564 unsigned int bpoll_state;
565 spinlock_t bpoll_lock; /* lock for busy poll */
566 #endif /* CONFIG_NET_RX_BUSY_POLL */
570 struct sge_eth_stats { /* Ethernet queue statistics */
571 unsigned long pkts; /* # of ethernet packets */
572 unsigned long lro_pkts; /* # of LRO super packets */
573 unsigned long lro_merged; /* # of wire packets merged by LRO */
574 unsigned long rx_cso; /* # of Rx checksum offloads */
575 unsigned long vlan_ex; /* # of Rx VLAN extractions */
576 unsigned long rx_drops; /* # of packets dropped due to no mem */
579 struct sge_eth_rxq { /* SW Ethernet Rx queue */
580 struct sge_rspq rspq;
582 struct sge_eth_stats stats;
583 } ____cacheline_aligned_in_smp;
585 struct sge_ofld_stats { /* offload queue statistics */
586 unsigned long pkts; /* # of packets */
587 unsigned long imm; /* # of immediate-data packets */
588 unsigned long an; /* # of asynchronous notifications */
589 unsigned long nomem; /* # of responses deferred due to no mem */
592 struct sge_ofld_rxq { /* SW offload Rx queue */
593 struct sge_rspq rspq;
595 struct sge_ofld_stats stats;
596 } ____cacheline_aligned_in_smp;
605 unsigned int in_use; /* # of in-use Tx descriptors */
606 unsigned int size; /* # of descriptors */
607 unsigned int cidx; /* SW consumer index */
608 unsigned int pidx; /* producer index */
609 unsigned long stops; /* # of times q has been stopped */
610 unsigned long restarts; /* # of queue restarts */
611 unsigned int cntxt_id; /* SGE context id for the Tx q */
612 struct tx_desc *desc; /* address of HW Tx descriptor ring */
613 struct tx_sw_desc *sdesc; /* address of SW Tx descriptor ring */
614 struct sge_qstat *stat; /* queue status entry */
615 dma_addr_t phys_addr; /* physical address of the ring */
618 unsigned short db_pidx;
619 unsigned short db_pidx_inc;
620 void __iomem *bar2_addr; /* address of BAR2 Queue registers */
621 unsigned int bar2_qid; /* Queue ID for BAR2 Queue registers */
624 struct sge_eth_txq { /* state for an SGE Ethernet Tx queue */
626 struct netdev_queue *txq; /* associated netdev TX queue */
627 #ifdef CONFIG_CHELSIO_T4_DCB
628 u8 dcb_prio; /* DCB Priority bound to queue */
630 unsigned long tso; /* # of TSO requests */
631 unsigned long tx_cso; /* # of Tx checksum offloads */
632 unsigned long vlan_ins; /* # of Tx VLAN insertions */
633 unsigned long mapping_err; /* # of I/O MMU packet mapping errors */
634 } ____cacheline_aligned_in_smp;
636 struct sge_ofld_txq { /* state for an SGE offload Tx queue */
638 struct adapter *adap;
639 struct sk_buff_head sendq; /* list of backpressured packets */
640 struct tasklet_struct qresume_tsk; /* restarts the queue */
641 u8 full; /* the Tx ring is full */
642 unsigned long mapping_err; /* # of I/O MMU packet mapping errors */
643 } ____cacheline_aligned_in_smp;
645 struct sge_ctrl_txq { /* state for an SGE control Tx queue */
647 struct adapter *adap;
648 struct sk_buff_head sendq; /* list of backpressured packets */
649 struct tasklet_struct qresume_tsk; /* restarts the queue */
650 u8 full; /* the Tx ring is full */
651 } ____cacheline_aligned_in_smp;
654 struct sge_eth_txq ethtxq[MAX_ETH_QSETS];
655 struct sge_ofld_txq ofldtxq[MAX_OFLD_QSETS];
656 struct sge_ctrl_txq ctrlq[MAX_CTRL_QUEUES];
658 struct sge_eth_rxq ethrxq[MAX_ETH_QSETS];
659 struct sge_ofld_rxq ofldrxq[MAX_OFLD_QSETS];
660 struct sge_ofld_rxq rdmarxq[MAX_RDMA_QUEUES];
661 struct sge_ofld_rxq rdmaciq[MAX_RDMA_CIQS];
662 struct sge_rspq fw_evtq ____cacheline_aligned_in_smp;
664 struct sge_rspq intrq ____cacheline_aligned_in_smp;
665 spinlock_t intrq_lock;
667 u16 max_ethqsets; /* # of available Ethernet queue sets */
668 u16 ethqsets; /* # of active Ethernet queue sets */
669 u16 ethtxq_rover; /* Tx queue to clean up next */
670 u16 ofldqsets; /* # of active offload queue sets */
671 u16 rdmaqs; /* # of available RDMA Rx queues */
672 u16 rdmaciqs; /* # of available RDMA concentrator IQs */
673 u16 ofld_rxq[MAX_OFLD_QSETS];
674 u16 rdma_rxq[MAX_RDMA_QUEUES];
675 u16 rdma_ciq[MAX_RDMA_CIQS];
676 u16 timer_val[SGE_NTIMERS];
677 u8 counter_val[SGE_NCOUNTERS];
678 u32 fl_pg_order; /* large page allocation size */
679 u32 stat_len; /* length of status page at ring end */
680 u32 pktshift; /* padding between CPL & packet data */
681 u32 fl_align; /* response queue message alignment */
682 u32 fl_starve_thres; /* Free List starvation threshold */
684 struct sge_idma_monitor_state idma_monitor;
685 unsigned int egr_start;
687 unsigned int ingr_start;
688 unsigned int ingr_sz;
689 void **egr_map; /* qid->queue egress queue map */
690 struct sge_rspq **ingr_map; /* qid->queue ingress queue map */
691 unsigned long *starving_fl;
692 unsigned long *txq_maperr;
693 unsigned long *blocked_fl;
694 struct timer_list rx_timer; /* refills starving FLs */
695 struct timer_list tx_timer; /* checks Tx queues */
698 #define for_each_ethrxq(sge, i) for (i = 0; i < (sge)->ethqsets; i++)
699 #define for_each_ofldrxq(sge, i) for (i = 0; i < (sge)->ofldqsets; i++)
700 #define for_each_rdmarxq(sge, i) for (i = 0; i < (sge)->rdmaqs; i++)
701 #define for_each_rdmaciq(sge, i) for (i = 0; i < (sge)->rdmaciqs; i++)
705 #ifdef CONFIG_PCI_IOV
707 /* T4 supports SRIOV on PF0-3 and T5 on PF0-7. However, the Serial
708 * Configuration initialization for T5 only has SR-IOV functionality enabled
709 * on PF0-3 in order to simplify everything.
711 #define NUM_OF_PF_WITH_SRIOV 4
715 struct doorbell_stats {
725 struct pci_dev *pdev;
726 struct device *pdev_dev;
734 struct adapter_params params;
735 struct cxgb4_virt_res vres;
740 char desc[IFNAMSIZ + 10];
741 } msix_info[MAX_INGQ + 1];
743 struct doorbell_stats db_stats;
746 struct net_device *port[MAX_NPORTS];
747 u8 chan_map[NCHAN]; /* channel -> port map */
750 unsigned int l2t_start;
751 unsigned int l2t_end;
752 struct l2t_data *l2t;
753 unsigned int clipt_start;
754 unsigned int clipt_end;
755 struct clip_tbl *clipt;
756 void *uld_handle[CXGB4_ULD_MAX];
757 struct list_head list_node;
758 struct list_head rcu_node;
760 struct tid_info tids;
761 void **tid_release_head;
762 spinlock_t tid_release_lock;
763 struct workqueue_struct *workq;
764 struct work_struct tid_release_task;
765 struct work_struct db_full_task;
766 struct work_struct db_drop_task;
767 bool tid_release_task_busy;
769 struct dentry *debugfs_root;
771 spinlock_t stats_lock;
772 spinlock_t win0_lock ____cacheline_aligned_in_smp;
775 /* Defined bit width of user definable filter tuples
777 #define ETHTYPE_BITWIDTH 16
778 #define FRAG_BITWIDTH 1
779 #define MACIDX_BITWIDTH 9
780 #define FCOE_BITWIDTH 1
781 #define IPORT_BITWIDTH 3
782 #define MATCHTYPE_BITWIDTH 3
783 #define PROTO_BITWIDTH 8
784 #define TOS_BITWIDTH 8
785 #define PF_BITWIDTH 8
786 #define VF_BITWIDTH 8
787 #define IVLAN_BITWIDTH 16
788 #define OVLAN_BITWIDTH 16
790 /* Filter matching rules. These consist of a set of ingress packet field
791 * (value, mask) tuples. The associated ingress packet field matches the
792 * tuple when ((field & mask) == value). (Thus a wildcard "don't care" field
793 * rule can be constructed by specifying a tuple of (0, 0).) A filter rule
794 * matches an ingress packet when all of the individual individual field
795 * matching rules are true.
797 * Partial field masks are always valid, however, while it may be easy to
798 * understand their meanings for some fields (e.g. IP address to match a
799 * subnet), for others making sensible partial masks is less intuitive (e.g.
800 * MPS match type) ...
802 * Most of the following data structures are modeled on T4 capabilities.
803 * Drivers for earlier chips use the subsets which make sense for those chips.
804 * We really need to come up with a hardware-independent mechanism to
805 * represent hardware filter capabilities ...
807 struct ch_filter_tuple {
808 /* Compressed header matching field rules. The TP_VLAN_PRI_MAP
809 * register selects which of these fields will participate in the
810 * filter match rules -- up to a maximum of 36 bits. Because
811 * TP_VLAN_PRI_MAP is a global register, all filters must use the same
814 uint32_t ethtype:ETHTYPE_BITWIDTH; /* Ethernet type */
815 uint32_t frag:FRAG_BITWIDTH; /* IP fragmentation header */
816 uint32_t ivlan_vld:1; /* inner VLAN valid */
817 uint32_t ovlan_vld:1; /* outer VLAN valid */
818 uint32_t pfvf_vld:1; /* PF/VF valid */
819 uint32_t macidx:MACIDX_BITWIDTH; /* exact match MAC index */
820 uint32_t fcoe:FCOE_BITWIDTH; /* FCoE packet */
821 uint32_t iport:IPORT_BITWIDTH; /* ingress port */
822 uint32_t matchtype:MATCHTYPE_BITWIDTH; /* MPS match type */
823 uint32_t proto:PROTO_BITWIDTH; /* protocol type */
824 uint32_t tos:TOS_BITWIDTH; /* TOS/Traffic Type */
825 uint32_t pf:PF_BITWIDTH; /* PCI-E PF ID */
826 uint32_t vf:VF_BITWIDTH; /* PCI-E VF ID */
827 uint32_t ivlan:IVLAN_BITWIDTH; /* inner VLAN */
828 uint32_t ovlan:OVLAN_BITWIDTH; /* outer VLAN */
830 /* Uncompressed header matching field rules. These are always
831 * available for field rules.
833 uint8_t lip[16]; /* local IP address (IPv4 in [3:0]) */
834 uint8_t fip[16]; /* foreign IP address (IPv4 in [3:0]) */
835 uint16_t lport; /* local port */
836 uint16_t fport; /* foreign port */
839 /* A filter ioctl command.
841 struct ch_filter_specification {
842 /* Administrative fields for filter.
844 uint32_t hitcnts:1; /* count filter hits in TCB */
845 uint32_t prio:1; /* filter has priority over active/server */
847 /* Fundamental filter typing. This is the one element of filter
848 * matching that doesn't exist as a (value, mask) tuple.
850 uint32_t type:1; /* 0 => IPv4, 1 => IPv6 */
852 /* Packet dispatch information. Ingress packets which match the
853 * filter rules will be dropped, passed to the host or switched back
854 * out as egress packets.
856 uint32_t action:2; /* drop, pass, switch */
858 uint32_t rpttid:1; /* report TID in RSS hash field */
860 uint32_t dirsteer:1; /* 0 => RSS, 1 => steer to iq */
861 uint32_t iq:10; /* ingress queue */
863 uint32_t maskhash:1; /* dirsteer=0: store RSS hash in TCB */
864 uint32_t dirsteerhash:1;/* dirsteer=1: 0 => TCB contains RSS hash */
865 /* 1 => TCB contains IQ ID */
867 /* Switch proxy/rewrite fields. An ingress packet which matches a
868 * filter with "switch" set will be looped back out as an egress
869 * packet -- potentially with some Ethernet header rewriting.
871 uint32_t eport:2; /* egress port to switch packet out */
872 uint32_t newdmac:1; /* rewrite destination MAC address */
873 uint32_t newsmac:1; /* rewrite source MAC address */
874 uint32_t newvlan:2; /* rewrite VLAN Tag */
875 uint8_t dmac[ETH_ALEN]; /* new destination MAC address */
876 uint8_t smac[ETH_ALEN]; /* new source MAC address */
877 uint16_t vlan; /* VLAN Tag to insert */
879 /* Filter rule value/mask pairs.
881 struct ch_filter_tuple val;
882 struct ch_filter_tuple mask;
886 FILTER_PASS = 0, /* default */
892 VLAN_NOCHANGE = 0, /* default */
898 static inline int is_offload(const struct adapter *adap)
900 return adap->params.offload;
903 static inline int is_t6(enum chip_type chip)
905 return CHELSIO_CHIP_VERSION(chip) == CHELSIO_T6;
908 static inline int is_t5(enum chip_type chip)
910 return CHELSIO_CHIP_VERSION(chip) == CHELSIO_T5;
913 static inline int is_t4(enum chip_type chip)
915 return CHELSIO_CHIP_VERSION(chip) == CHELSIO_T4;
918 static inline u32 t4_read_reg(struct adapter *adap, u32 reg_addr)
920 return readl(adap->regs + reg_addr);
923 static inline void t4_write_reg(struct adapter *adap, u32 reg_addr, u32 val)
925 writel(val, adap->regs + reg_addr);
929 static inline u64 readq(const volatile void __iomem *addr)
931 return readl(addr) + ((u64)readl(addr + 4) << 32);
934 static inline void writeq(u64 val, volatile void __iomem *addr)
937 writel(val >> 32, addr + 4);
941 static inline u64 t4_read_reg64(struct adapter *adap, u32 reg_addr)
943 return readq(adap->regs + reg_addr);
946 static inline void t4_write_reg64(struct adapter *adap, u32 reg_addr, u64 val)
948 writeq(val, adap->regs + reg_addr);
952 * t4_set_hw_addr - store a port's MAC address in SW
953 * @adapter: the adapter
954 * @port_idx: the port index
955 * @hw_addr: the Ethernet address
957 * Store the Ethernet address of the given port in SW. Called by the common
958 * code when it retrieves a port's Ethernet address from EEPROM.
960 static inline void t4_set_hw_addr(struct adapter *adapter, int port_idx,
963 ether_addr_copy(adapter->port[port_idx]->dev_addr, hw_addr);
964 ether_addr_copy(adapter->port[port_idx]->perm_addr, hw_addr);
968 * netdev2pinfo - return the port_info structure associated with a net_device
971 * Return the struct port_info associated with a net_device
973 static inline struct port_info *netdev2pinfo(const struct net_device *dev)
975 return netdev_priv(dev);
979 * adap2pinfo - return the port_info of a port
981 * @idx: the port index
983 * Return the port_info structure for the port of the given index.
985 static inline struct port_info *adap2pinfo(struct adapter *adap, int idx)
987 return netdev_priv(adap->port[idx]);
991 * netdev2adap - return the adapter structure associated with a net_device
994 * Return the struct adapter associated with a net_device
996 static inline struct adapter *netdev2adap(const struct net_device *dev)
998 return netdev2pinfo(dev)->adapter;
1001 #ifdef CONFIG_NET_RX_BUSY_POLL
1002 static inline void cxgb_busy_poll_init_lock(struct sge_rspq *q)
1004 spin_lock_init(&q->bpoll_lock);
1005 q->bpoll_state = CXGB_POLL_STATE_IDLE;
1008 static inline bool cxgb_poll_lock_napi(struct sge_rspq *q)
1012 spin_lock(&q->bpoll_lock);
1013 if (q->bpoll_state & CXGB_POLL_LOCKED) {
1014 q->bpoll_state |= CXGB_POLL_STATE_NAPI_YIELD;
1017 q->bpoll_state = CXGB_POLL_STATE_NAPI;
1019 spin_unlock(&q->bpoll_lock);
1023 static inline bool cxgb_poll_unlock_napi(struct sge_rspq *q)
1027 spin_lock(&q->bpoll_lock);
1028 if (q->bpoll_state & CXGB_POLL_STATE_POLL_YIELD)
1030 q->bpoll_state = CXGB_POLL_STATE_IDLE;
1031 spin_unlock(&q->bpoll_lock);
1035 static inline bool cxgb_poll_lock_poll(struct sge_rspq *q)
1039 spin_lock_bh(&q->bpoll_lock);
1040 if (q->bpoll_state & CXGB_POLL_LOCKED) {
1041 q->bpoll_state |= CXGB_POLL_STATE_POLL_YIELD;
1044 q->bpoll_state |= CXGB_POLL_STATE_POLL;
1046 spin_unlock_bh(&q->bpoll_lock);
1050 static inline bool cxgb_poll_unlock_poll(struct sge_rspq *q)
1054 spin_lock_bh(&q->bpoll_lock);
1055 if (q->bpoll_state & CXGB_POLL_STATE_POLL_YIELD)
1057 q->bpoll_state = CXGB_POLL_STATE_IDLE;
1058 spin_unlock_bh(&q->bpoll_lock);
1062 static inline bool cxgb_poll_busy_polling(struct sge_rspq *q)
1064 return q->bpoll_state & CXGB_POLL_USER_PEND;
1067 static inline void cxgb_busy_poll_init_lock(struct sge_rspq *q)
1071 static inline bool cxgb_poll_lock_napi(struct sge_rspq *q)
1076 static inline bool cxgb_poll_unlock_napi(struct sge_rspq *q)
1081 static inline bool cxgb_poll_lock_poll(struct sge_rspq *q)
1086 static inline bool cxgb_poll_unlock_poll(struct sge_rspq *q)
1091 static inline bool cxgb_poll_busy_polling(struct sge_rspq *q)
1095 #endif /* CONFIG_NET_RX_BUSY_POLL */
1097 /* Return a version number to identify the type of adapter. The scheme is:
1098 * - bits 0..9: chip version
1099 * - bits 10..15: chip revision
1100 * - bits 16..23: register dump version
1102 static inline unsigned int mk_adap_vers(struct adapter *ap)
1104 return CHELSIO_CHIP_VERSION(ap->params.chip) |
1105 (CHELSIO_CHIP_RELEASE(ap->params.chip) << 10) | (1 << 16);
1108 /* Return a queue's interrupt hold-off time in us. 0 means no timer. */
1109 static inline unsigned int qtimer_val(const struct adapter *adap,
1110 const struct sge_rspq *q)
1112 unsigned int idx = q->intr_params >> 1;
1114 return idx < SGE_NTIMERS ? adap->sge.timer_val[idx] : 0;
1117 /* driver version & name used for ethtool_drvinfo */
1118 extern char cxgb4_driver_name[];
1119 extern const char cxgb4_driver_version[];
1121 void t4_os_portmod_changed(const struct adapter *adap, int port_id);
1122 void t4_os_link_changed(struct adapter *adap, int port_id, int link_stat);
1124 void *t4_alloc_mem(size_t size);
1126 void t4_free_sge_resources(struct adapter *adap);
1127 void t4_free_ofld_rxqs(struct adapter *adap, int n, struct sge_ofld_rxq *q);
1128 irq_handler_t t4_intr_handler(struct adapter *adap);
1129 netdev_tx_t t4_eth_xmit(struct sk_buff *skb, struct net_device *dev);
1130 int t4_ethrx_handler(struct sge_rspq *q, const __be64 *rsp,
1131 const struct pkt_gl *gl);
1132 int t4_mgmt_tx(struct adapter *adap, struct sk_buff *skb);
1133 int t4_ofld_send(struct adapter *adap, struct sk_buff *skb);
1134 int t4_sge_alloc_rxq(struct adapter *adap, struct sge_rspq *iq, bool fwevtq,
1135 struct net_device *dev, int intr_idx,
1136 struct sge_fl *fl, rspq_handler_t hnd, int cong);
1137 int t4_sge_alloc_eth_txq(struct adapter *adap, struct sge_eth_txq *txq,
1138 struct net_device *dev, struct netdev_queue *netdevq,
1140 int t4_sge_alloc_ctrl_txq(struct adapter *adap, struct sge_ctrl_txq *txq,
1141 struct net_device *dev, unsigned int iqid,
1142 unsigned int cmplqid);
1143 int t4_sge_alloc_ofld_txq(struct adapter *adap, struct sge_ofld_txq *txq,
1144 struct net_device *dev, unsigned int iqid);
1145 irqreturn_t t4_sge_intr_msix(int irq, void *cookie);
1146 int t4_sge_init(struct adapter *adap);
1147 void t4_sge_start(struct adapter *adap);
1148 void t4_sge_stop(struct adapter *adap);
1149 int cxgb_busy_poll(struct napi_struct *napi);
1150 int cxgb4_set_rspq_intr_params(struct sge_rspq *q, unsigned int us,
1152 void cxgb4_set_ethtool_ops(struct net_device *netdev);
1153 int cxgb4_write_rss(const struct port_info *pi, const u16 *queues);
1154 extern int dbfifo_int_thresh;
1156 #define for_each_port(adapter, iter) \
1157 for (iter = 0; iter < (adapter)->params.nports; ++iter)
1159 static inline int is_bypass(struct adapter *adap)
1161 return adap->params.bypass;
1164 static inline int is_bypass_device(int device)
1166 /* this should be set based upon device capabilities */
1176 static inline int is_10gbt_device(int device)
1178 /* this should be set based upon device capabilities */
1189 static inline unsigned int core_ticks_per_usec(const struct adapter *adap)
1191 return adap->params.vpd.cclk / 1000;
1194 static inline unsigned int us_to_core_ticks(const struct adapter *adap,
1197 return (us * adap->params.vpd.cclk) / 1000;
1200 static inline unsigned int core_ticks_to_us(const struct adapter *adapter,
1203 /* add Core Clock / 2 to round ticks to nearest uS */
1204 return ((ticks * 1000 + adapter->params.vpd.cclk/2) /
1205 adapter->params.vpd.cclk);
1208 void t4_set_reg_field(struct adapter *adap, unsigned int addr, u32 mask,
1211 int t4_wr_mbox_meat_timeout(struct adapter *adap, int mbox, const void *cmd,
1212 int size, void *rpl, bool sleep_ok, int timeout);
1213 int t4_wr_mbox_meat(struct adapter *adap, int mbox, const void *cmd, int size,
1214 void *rpl, bool sleep_ok);
1216 static inline int t4_wr_mbox_timeout(struct adapter *adap, int mbox,
1217 const void *cmd, int size, void *rpl,
1220 return t4_wr_mbox_meat_timeout(adap, mbox, cmd, size, rpl, true,
1224 static inline int t4_wr_mbox(struct adapter *adap, int mbox, const void *cmd,
1225 int size, void *rpl)
1227 return t4_wr_mbox_meat(adap, mbox, cmd, size, rpl, true);
1230 static inline int t4_wr_mbox_ns(struct adapter *adap, int mbox, const void *cmd,
1231 int size, void *rpl)
1233 return t4_wr_mbox_meat(adap, mbox, cmd, size, rpl, false);
1236 void t4_write_indirect(struct adapter *adap, unsigned int addr_reg,
1237 unsigned int data_reg, const u32 *vals,
1238 unsigned int nregs, unsigned int start_idx);
1239 void t4_read_indirect(struct adapter *adap, unsigned int addr_reg,
1240 unsigned int data_reg, u32 *vals, unsigned int nregs,
1241 unsigned int start_idx);
1242 void t4_hw_pci_read_cfg4(struct adapter *adapter, int reg, u32 *val);
1244 struct fw_filter_wr;
1246 void t4_intr_enable(struct adapter *adapter);
1247 void t4_intr_disable(struct adapter *adapter);
1248 int t4_slow_intr_handler(struct adapter *adapter);
1250 int t4_wait_dev_ready(void __iomem *regs);
1251 int t4_link_l1cfg(struct adapter *adap, unsigned int mbox, unsigned int port,
1252 struct link_config *lc);
1253 int t4_restart_aneg(struct adapter *adap, unsigned int mbox, unsigned int port);
1255 u32 t4_read_pcie_cfg4(struct adapter *adap, int reg);
1256 u32 t4_get_util_window(struct adapter *adap);
1257 void t4_setup_memwin(struct adapter *adap, u32 memwin_base, u32 window);
1259 #define T4_MEMORY_WRITE 0
1260 #define T4_MEMORY_READ 1
1261 int t4_memory_rw(struct adapter *adap, int win, int mtype, u32 addr, u32 len,
1262 void *buf, int dir);
1263 static inline int t4_memory_write(struct adapter *adap, int mtype, u32 addr,
1264 u32 len, __be32 *buf)
1266 return t4_memory_rw(adap, 0, mtype, addr, len, buf, 0);
1269 unsigned int t4_get_regs_len(struct adapter *adapter);
1270 void t4_get_regs(struct adapter *adap, void *buf, size_t buf_size);
1272 int t4_seeprom_wp(struct adapter *adapter, bool enable);
1273 int t4_get_raw_vpd_params(struct adapter *adapter, struct vpd_params *p);
1274 int t4_get_vpd_params(struct adapter *adapter, struct vpd_params *p);
1275 int t4_read_flash(struct adapter *adapter, unsigned int addr,
1276 unsigned int nwords, u32 *data, int byte_oriented);
1277 int t4_load_fw(struct adapter *adapter, const u8 *fw_data, unsigned int size);
1278 int t4_load_phy_fw(struct adapter *adap,
1279 int win, spinlock_t *lock,
1280 int (*phy_fw_version)(const u8 *, size_t),
1281 const u8 *phy_fw_data, size_t phy_fw_size);
1282 int t4_phy_fw_ver(struct adapter *adap, int *phy_fw_ver);
1283 int t4_fwcache(struct adapter *adap, enum fw_params_param_dev_fwcache op);
1284 int t4_fw_upgrade(struct adapter *adap, unsigned int mbox,
1285 const u8 *fw_data, unsigned int size, int force);
1286 unsigned int t4_flash_cfg_addr(struct adapter *adapter);
1287 int t4_get_fw_version(struct adapter *adapter, u32 *vers);
1288 int t4_get_tp_version(struct adapter *adapter, u32 *vers);
1289 int t4_get_exprom_version(struct adapter *adapter, u32 *vers);
1290 int t4_prep_fw(struct adapter *adap, struct fw_info *fw_info,
1291 const u8 *fw_data, unsigned int fw_size,
1292 struct fw_hdr *card_fw, enum dev_state state, int *reset);
1293 int t4_prep_adapter(struct adapter *adapter);
1295 enum t4_bar2_qtype { T4_BAR2_QTYPE_EGRESS, T4_BAR2_QTYPE_INGRESS };
1296 int t4_bar2_sge_qregs(struct adapter *adapter,
1298 enum t4_bar2_qtype qtype,
1301 unsigned int *pbar2_qid);
1303 unsigned int qtimer_val(const struct adapter *adap,
1304 const struct sge_rspq *q);
1306 int t4_init_devlog_params(struct adapter *adapter);
1307 int t4_init_sge_params(struct adapter *adapter);
1308 int t4_init_tp_params(struct adapter *adap);
1309 int t4_filter_field_shift(const struct adapter *adap, int filter_sel);
1310 int t4_init_rss_mode(struct adapter *adap, int mbox);
1311 int t4_port_init(struct adapter *adap, int mbox, int pf, int vf);
1312 void t4_fatal_err(struct adapter *adapter);
1313 int t4_config_rss_range(struct adapter *adapter, int mbox, unsigned int viid,
1314 int start, int n, const u16 *rspq, unsigned int nrspq);
1315 int t4_config_glbl_rss(struct adapter *adapter, int mbox, unsigned int mode,
1316 unsigned int flags);
1317 int t4_config_vi_rss(struct adapter *adapter, int mbox, unsigned int viid,
1318 unsigned int flags, unsigned int defq);
1319 int t4_read_rss(struct adapter *adapter, u16 *entries);
1320 void t4_read_rss_key(struct adapter *adapter, u32 *key);
1321 void t4_write_rss_key(struct adapter *adap, const u32 *key, int idx);
1322 void t4_read_rss_pf_config(struct adapter *adapter, unsigned int index,
1324 void t4_read_rss_vf_config(struct adapter *adapter, unsigned int index,
1325 u32 *vfl, u32 *vfh);
1326 u32 t4_read_rss_pf_map(struct adapter *adapter);
1327 u32 t4_read_rss_pf_mask(struct adapter *adapter);
1329 unsigned int t4_get_mps_bg_map(struct adapter *adapter, int idx);
1330 void t4_pmtx_get_stats(struct adapter *adap, u32 cnt[], u64 cycles[]);
1331 void t4_pmrx_get_stats(struct adapter *adap, u32 cnt[], u64 cycles[]);
1332 int t4_read_cim_ibq(struct adapter *adap, unsigned int qid, u32 *data,
1334 int t4_read_cim_obq(struct adapter *adap, unsigned int qid, u32 *data,
1336 int t4_cim_read(struct adapter *adap, unsigned int addr, unsigned int n,
1337 unsigned int *valp);
1338 int t4_cim_write(struct adapter *adap, unsigned int addr, unsigned int n,
1339 const unsigned int *valp);
1340 int t4_cim_read_la(struct adapter *adap, u32 *la_buf, unsigned int *wrptr);
1341 void t4_cim_read_pif_la(struct adapter *adap, u32 *pif_req, u32 *pif_rsp,
1342 unsigned int *pif_req_wrptr,
1343 unsigned int *pif_rsp_wrptr);
1344 void t4_cim_read_ma_la(struct adapter *adap, u32 *ma_req, u32 *ma_rsp);
1345 void t4_read_cimq_cfg(struct adapter *adap, u16 *base, u16 *size, u16 *thres);
1346 const char *t4_get_port_type_description(enum fw_port_type port_type);
1347 void t4_get_port_stats(struct adapter *adap, int idx, struct port_stats *p);
1348 void t4_get_port_stats_offset(struct adapter *adap, int idx,
1349 struct port_stats *stats,
1350 struct port_stats *offset);
1351 void t4_get_lb_stats(struct adapter *adap, int idx, struct lb_port_stats *p);
1352 void t4_read_mtu_tbl(struct adapter *adap, u16 *mtus, u8 *mtu_log);
1353 void t4_read_cong_tbl(struct adapter *adap, u16 incr[NMTUS][NCCTRL_WIN]);
1354 void t4_tp_wr_bits_indirect(struct adapter *adap, unsigned int addr,
1355 unsigned int mask, unsigned int val);
1356 void t4_tp_read_la(struct adapter *adap, u64 *la_buf, unsigned int *wrptr);
1357 void t4_tp_get_err_stats(struct adapter *adap, struct tp_err_stats *st);
1358 void t4_tp_get_cpl_stats(struct adapter *adap, struct tp_cpl_stats *st);
1359 void t4_tp_get_rdma_stats(struct adapter *adap, struct tp_rdma_stats *st);
1360 void t4_get_usm_stats(struct adapter *adap, struct tp_usm_stats *st);
1361 void t4_tp_get_tcp_stats(struct adapter *adap, struct tp_tcp_stats *v4,
1362 struct tp_tcp_stats *v6);
1363 void t4_get_fcoe_stats(struct adapter *adap, unsigned int idx,
1364 struct tp_fcoe_stats *st);
1365 void t4_load_mtus(struct adapter *adap, const unsigned short *mtus,
1366 const unsigned short *alpha, const unsigned short *beta);
1368 void t4_ulprx_read_la(struct adapter *adap, u32 *la_buf);
1370 void t4_get_chan_txrate(struct adapter *adap, u64 *nic_rate, u64 *ofld_rate);
1371 void t4_mk_filtdelwr(unsigned int ftid, struct fw_filter_wr *wr, int qid);
1373 void t4_wol_magic_enable(struct adapter *adap, unsigned int port,
1375 int t4_wol_pat_enable(struct adapter *adap, unsigned int port, unsigned int map,
1376 u64 mask0, u64 mask1, unsigned int crc, bool enable);
1378 int t4_fw_hello(struct adapter *adap, unsigned int mbox, unsigned int evt_mbox,
1379 enum dev_master master, enum dev_state *state);
1380 int t4_fw_bye(struct adapter *adap, unsigned int mbox);
1381 int t4_early_init(struct adapter *adap, unsigned int mbox);
1382 int t4_fw_reset(struct adapter *adap, unsigned int mbox, int reset);
1383 int t4_fixup_host_params(struct adapter *adap, unsigned int page_size,
1384 unsigned int cache_line_size);
1385 int t4_fw_initialize(struct adapter *adap, unsigned int mbox);
1386 int t4_query_params(struct adapter *adap, unsigned int mbox, unsigned int pf,
1387 unsigned int vf, unsigned int nparams, const u32 *params,
1389 int t4_query_params_rw(struct adapter *adap, unsigned int mbox, unsigned int pf,
1390 unsigned int vf, unsigned int nparams, const u32 *params,
1392 int t4_set_params_timeout(struct adapter *adap, unsigned int mbox,
1393 unsigned int pf, unsigned int vf,
1394 unsigned int nparams, const u32 *params,
1395 const u32 *val, int timeout);
1396 int t4_set_params(struct adapter *adap, unsigned int mbox, unsigned int pf,
1397 unsigned int vf, unsigned int nparams, const u32 *params,
1399 int t4_cfg_pfvf(struct adapter *adap, unsigned int mbox, unsigned int pf,
1400 unsigned int vf, unsigned int txq, unsigned int txq_eth_ctrl,
1401 unsigned int rxqi, unsigned int rxq, unsigned int tc,
1402 unsigned int vi, unsigned int cmask, unsigned int pmask,
1403 unsigned int nexact, unsigned int rcaps, unsigned int wxcaps);
1404 int t4_alloc_vi(struct adapter *adap, unsigned int mbox, unsigned int port,
1405 unsigned int pf, unsigned int vf, unsigned int nmac, u8 *mac,
1406 unsigned int *rss_size);
1407 int t4_free_vi(struct adapter *adap, unsigned int mbox,
1408 unsigned int pf, unsigned int vf,
1410 int t4_set_rxmode(struct adapter *adap, unsigned int mbox, unsigned int viid,
1411 int mtu, int promisc, int all_multi, int bcast, int vlanex,
1413 int t4_alloc_mac_filt(struct adapter *adap, unsigned int mbox,
1414 unsigned int viid, bool free, unsigned int naddr,
1415 const u8 **addr, u16 *idx, u64 *hash, bool sleep_ok);
1416 int t4_change_mac(struct adapter *adap, unsigned int mbox, unsigned int viid,
1417 int idx, const u8 *addr, bool persist, bool add_smt);
1418 int t4_set_addr_hash(struct adapter *adap, unsigned int mbox, unsigned int viid,
1419 bool ucast, u64 vec, bool sleep_ok);
1420 int t4_enable_vi_params(struct adapter *adap, unsigned int mbox,
1421 unsigned int viid, bool rx_en, bool tx_en, bool dcb_en);
1422 int t4_enable_vi(struct adapter *adap, unsigned int mbox, unsigned int viid,
1423 bool rx_en, bool tx_en);
1424 int t4_identify_port(struct adapter *adap, unsigned int mbox, unsigned int viid,
1425 unsigned int nblinks);
1426 int t4_mdio_rd(struct adapter *adap, unsigned int mbox, unsigned int phy_addr,
1427 unsigned int mmd, unsigned int reg, u16 *valp);
1428 int t4_mdio_wr(struct adapter *adap, unsigned int mbox, unsigned int phy_addr,
1429 unsigned int mmd, unsigned int reg, u16 val);
1430 int t4_iq_free(struct adapter *adap, unsigned int mbox, unsigned int pf,
1431 unsigned int vf, unsigned int iqtype, unsigned int iqid,
1432 unsigned int fl0id, unsigned int fl1id);
1433 int t4_eth_eq_free(struct adapter *adap, unsigned int mbox, unsigned int pf,
1434 unsigned int vf, unsigned int eqid);
1435 int t4_ctrl_eq_free(struct adapter *adap, unsigned int mbox, unsigned int pf,
1436 unsigned int vf, unsigned int eqid);
1437 int t4_ofld_eq_free(struct adapter *adap, unsigned int mbox, unsigned int pf,
1438 unsigned int vf, unsigned int eqid);
1439 int t4_sge_ctxt_flush(struct adapter *adap, unsigned int mbox);
1440 int t4_handle_fw_rpl(struct adapter *adap, const __be64 *rpl);
1441 void t4_db_full(struct adapter *adapter);
1442 void t4_db_dropped(struct adapter *adapter);
1443 int t4_fwaddrspace_write(struct adapter *adap, unsigned int mbox,
1445 void t4_sge_decode_idma_state(struct adapter *adapter, int state);
1446 void t4_free_mem(void *addr);
1447 void t4_idma_monitor_init(struct adapter *adapter,
1448 struct sge_idma_monitor_state *idma);
1449 void t4_idma_monitor(struct adapter *adapter,
1450 struct sge_idma_monitor_state *idma,
1452 #endif /* __CXGB4_H__ */