2 * This file is part of the Chelsio T4 Ethernet driver for Linux.
4 * Copyright (c) 2003-2014 Chelsio Communications, Inc. All rights reserved.
6 * This software is available to you under a choice of one of two
7 * licenses. You may choose to be licensed under the terms of the GNU
8 * General Public License (GPL) Version 2, available from the file
9 * COPYING in the main directory of this source tree, or the
10 * OpenIB.org BSD license below:
12 * Redistribution and use in source and binary forms, with or
13 * without modification, are permitted provided that the following
16 * - Redistributions of source code must retain the above
17 * copyright notice, this list of conditions and the following
20 * - Redistributions in binary form must reproduce the above
21 * copyright notice, this list of conditions and the following
22 * disclaimer in the documentation and/or other materials
23 * provided with the distribution.
25 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
26 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
27 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
28 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
29 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
30 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
31 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
35 #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
37 #include <linux/bitmap.h>
38 #include <linux/crc32.h>
39 #include <linux/ctype.h>
40 #include <linux/debugfs.h>
41 #include <linux/err.h>
42 #include <linux/etherdevice.h>
43 #include <linux/firmware.h>
45 #include <linux/if_vlan.h>
46 #include <linux/init.h>
47 #include <linux/log2.h>
48 #include <linux/mdio.h>
49 #include <linux/module.h>
50 #include <linux/moduleparam.h>
51 #include <linux/mutex.h>
52 #include <linux/netdevice.h>
53 #include <linux/pci.h>
54 #include <linux/aer.h>
55 #include <linux/rtnetlink.h>
56 #include <linux/sched.h>
57 #include <linux/seq_file.h>
58 #include <linux/sockios.h>
59 #include <linux/vmalloc.h>
60 #include <linux/workqueue.h>
61 #include <net/neighbour.h>
62 #include <net/netevent.h>
63 #include <net/addrconf.h>
64 #include <net/bonding.h>
65 #include <net/addrconf.h>
66 #include <asm/uaccess.h>
70 #include "t4_values.h"
73 #include "t4fw_version.h"
74 #include "cxgb4_dcb.h"
75 #include "cxgb4_debugfs.h"
79 char cxgb4_driver_name[] = KBUILD_MODNAME;
84 #define DRV_VERSION "2.0.0-ko"
85 const char cxgb4_driver_version[] = DRV_VERSION;
86 #define DRV_DESC "Chelsio T4/T5 Network Driver"
88 /* Host shadow copy of ingress filter entry. This is in host native format
89 * and doesn't match the ordering or bit order, etc. of the hardware of the
90 * firmware command. The use of bit-field structure elements is purely to
91 * remind ourselves of the field size limitations and save memory in the case
92 * where the filter table is large.
95 /* Administrative fields for filter.
97 u32 valid:1; /* filter allocated and valid */
98 u32 locked:1; /* filter is administratively locked */
100 u32 pending:1; /* filter action is pending firmware reply */
101 u32 smtidx:8; /* Source MAC Table index for smac */
102 struct l2t_entry *l2t; /* Layer Two Table entry for dmac */
104 /* The filter itself. Most of this is a straight copy of information
105 * provided by the extended ioctl(). Some fields are translated to
106 * internal forms -- for instance the Ingress Queue ID passed in from
107 * the ioctl() is translated into the Absolute Ingress Queue ID.
109 struct ch_filter_specification fs;
112 #define DFLT_MSG_ENABLE (NETIF_MSG_DRV | NETIF_MSG_PROBE | NETIF_MSG_LINK | \
113 NETIF_MSG_TIMER | NETIF_MSG_IFDOWN | NETIF_MSG_IFUP |\
114 NETIF_MSG_RX_ERR | NETIF_MSG_TX_ERR)
116 /* Macros needed to support the PCI Device ID Table ...
118 #define CH_PCI_DEVICE_ID_TABLE_DEFINE_BEGIN \
119 static const struct pci_device_id cxgb4_pci_tbl[] = {
120 #define CH_PCI_DEVICE_ID_FUNCTION 0x4
122 /* Include PCI Device IDs for both PF4 and PF0-3 so our PCI probe() routine is
125 #define CH_PCI_DEVICE_ID_FUNCTION2 0x0
127 #define CH_PCI_ID_TABLE_ENTRY(devid) \
128 {PCI_VDEVICE(CHELSIO, (devid)), 4}
130 #define CH_PCI_DEVICE_ID_TABLE_DEFINE_END \
134 #include "t4_pci_id_tbl.h"
136 #define FW4_FNAME "cxgb4/t4fw.bin"
137 #define FW5_FNAME "cxgb4/t5fw.bin"
138 #define FW6_FNAME "cxgb4/t6fw.bin"
139 #define FW4_CFNAME "cxgb4/t4-config.txt"
140 #define FW5_CFNAME "cxgb4/t5-config.txt"
141 #define FW6_CFNAME "cxgb4/t6-config.txt"
142 #define PHY_AQ1202_FIRMWARE "cxgb4/aq1202_fw.cld"
143 #define PHY_BCM84834_FIRMWARE "cxgb4/bcm8483.bin"
144 #define PHY_AQ1202_DEVICEID 0x4409
145 #define PHY_BCM84834_DEVICEID 0x4486
147 MODULE_DESCRIPTION(DRV_DESC);
148 MODULE_AUTHOR("Chelsio Communications");
149 MODULE_LICENSE("Dual BSD/GPL");
150 MODULE_VERSION(DRV_VERSION);
151 MODULE_DEVICE_TABLE(pci, cxgb4_pci_tbl);
152 MODULE_FIRMWARE(FW4_FNAME);
153 MODULE_FIRMWARE(FW5_FNAME);
156 * Normally we're willing to become the firmware's Master PF but will be happy
157 * if another PF has already become the Master and initialized the adapter.
158 * Setting "force_init" will cause this driver to forcibly establish itself as
159 * the Master PF and initialize the adapter.
161 static uint force_init;
163 module_param(force_init, uint, 0644);
164 MODULE_PARM_DESC(force_init, "Forcibly become Master PF and initialize adapter");
167 * Normally if the firmware we connect to has Configuration File support, we
168 * use that and only fall back to the old Driver-based initialization if the
169 * Configuration File fails for some reason. If force_old_init is set, then
170 * we'll always use the old Driver-based initialization sequence.
172 static uint force_old_init;
174 module_param(force_old_init, uint, 0644);
175 MODULE_PARM_DESC(force_old_init, "Force old initialization sequence, deprecated"
178 static int dflt_msg_enable = DFLT_MSG_ENABLE;
180 module_param(dflt_msg_enable, int, 0644);
181 MODULE_PARM_DESC(dflt_msg_enable, "Chelsio T4 default message enable bitmap");
184 * The driver uses the best interrupt scheme available on a platform in the
185 * order MSI-X, MSI, legacy INTx interrupts. This parameter determines which
186 * of these schemes the driver may consider as follows:
188 * msi = 2: choose from among all three options
189 * msi = 1: only consider MSI and INTx interrupts
190 * msi = 0: force INTx interrupts
194 module_param(msi, int, 0644);
195 MODULE_PARM_DESC(msi, "whether to use INTx (0), MSI (1) or MSI-X (2)");
198 * Queue interrupt hold-off timer values. Queues default to the first of these
201 static unsigned int intr_holdoff[SGE_NTIMERS - 1] = { 5, 10, 20, 50, 100 };
203 module_param_array(intr_holdoff, uint, NULL, 0644);
204 MODULE_PARM_DESC(intr_holdoff, "values for queue interrupt hold-off timers "
205 "0..4 in microseconds, deprecated parameter");
207 static unsigned int intr_cnt[SGE_NCOUNTERS - 1] = { 4, 8, 16 };
209 module_param_array(intr_cnt, uint, NULL, 0644);
210 MODULE_PARM_DESC(intr_cnt,
211 "thresholds 1..3 for queue interrupt packet counters, "
212 "deprecated parameter");
215 * Normally we tell the chip to deliver Ingress Packets into our DMA buffers
216 * offset by 2 bytes in order to have the IP headers line up on 4-byte
217 * boundaries. This is a requirement for many architectures which will throw
218 * a machine check fault if an attempt is made to access one of the 4-byte IP
219 * header fields on a non-4-byte boundary. And it's a major performance issue
220 * even on some architectures which allow it like some implementations of the
221 * x86 ISA. However, some architectures don't mind this and for some very
222 * edge-case performance sensitive applications (like forwarding large volumes
223 * of small packets), setting this DMA offset to 0 will decrease the number of
224 * PCI-E Bus transfers enough to measurably affect performance.
226 static int rx_dma_offset = 2;
230 #ifdef CONFIG_PCI_IOV
231 module_param(vf_acls, bool, 0644);
232 MODULE_PARM_DESC(vf_acls, "if set enable virtualization L2 ACL enforcement, "
233 "deprecated parameter");
235 /* Configure the number of PCI-E Virtual Function which are to be instantiated
236 * on SR-IOV Capable Physical Functions.
238 static unsigned int num_vf[NUM_OF_PF_WITH_SRIOV];
240 module_param_array(num_vf, uint, NULL, 0644);
241 MODULE_PARM_DESC(num_vf, "number of VFs for each of PFs 0-3");
244 /* TX Queue select used to determine what algorithm to use for selecting TX
245 * queue. Select between the kernel provided function (select_queue=0) or user
246 * cxgb_select_queue function (select_queue=1)
248 * Default: select_queue=0
250 static int select_queue;
251 module_param(select_queue, int, 0644);
252 MODULE_PARM_DESC(select_queue,
253 "Select between kernel provided method of selecting or driver method of selecting TX queue. Default is kernel method.");
255 static unsigned int tp_vlan_pri_map = HW_TPL_FR_MT_PR_IV_P_FC;
257 module_param(tp_vlan_pri_map, uint, 0644);
258 MODULE_PARM_DESC(tp_vlan_pri_map, "global compressed filter configuration, "
259 "deprecated parameter");
261 static struct dentry *cxgb4_debugfs_root;
263 static LIST_HEAD(adapter_list);
264 static DEFINE_MUTEX(uld_mutex);
265 /* Adapter list to be accessed from atomic context */
266 static LIST_HEAD(adap_rcu_list);
267 static DEFINE_SPINLOCK(adap_rcu_lock);
268 static struct cxgb4_uld_info ulds[CXGB4_ULD_MAX];
269 static const char *uld_str[] = { "RDMA", "iSCSI" };
271 static void link_report(struct net_device *dev)
273 if (!netif_carrier_ok(dev))
274 netdev_info(dev, "link down\n");
276 static const char *fc[] = { "no", "Rx", "Tx", "Tx/Rx" };
279 const struct port_info *p = netdev_priv(dev);
281 switch (p->link_cfg.speed) {
295 pr_info("%s: unsupported speed: %d\n",
296 dev->name, p->link_cfg.speed);
300 netdev_info(dev, "link up, %s, full-duplex, %s PAUSE\n", s,
305 #ifdef CONFIG_CHELSIO_T4_DCB
306 /* Set up/tear down Data Center Bridging Priority mapping for a net device. */
307 static void dcb_tx_queue_prio_enable(struct net_device *dev, int enable)
309 struct port_info *pi = netdev_priv(dev);
310 struct adapter *adap = pi->adapter;
311 struct sge_eth_txq *txq = &adap->sge.ethtxq[pi->first_qset];
314 /* We use a simple mapping of Port TX Queue Index to DCB
315 * Priority when we're enabling DCB.
317 for (i = 0; i < pi->nqsets; i++, txq++) {
321 name = (FW_PARAMS_MNEM_V(FW_PARAMS_MNEM_DMAQ) |
323 FW_PARAMS_PARAM_DMAQ_EQ_DCBPRIO_ETH) |
324 FW_PARAMS_PARAM_YZ_V(txq->q.cntxt_id));
325 value = enable ? i : 0xffffffff;
327 /* Since we can be called while atomic (from "interrupt
328 * level") we need to issue the Set Parameters Commannd
329 * without sleeping (timeout < 0).
331 err = t4_set_params_timeout(adap, adap->mbox, adap->pf, 0, 1,
333 -FW_CMD_MAX_TIMEOUT);
336 dev_err(adap->pdev_dev,
337 "Can't %s DCB Priority on port %d, TX Queue %d: err=%d\n",
338 enable ? "set" : "unset", pi->port_id, i, -err);
340 txq->dcb_prio = value;
343 #endif /* CONFIG_CHELSIO_T4_DCB */
345 void t4_os_link_changed(struct adapter *adapter, int port_id, int link_stat)
347 struct net_device *dev = adapter->port[port_id];
349 /* Skip changes from disabled ports. */
350 if (netif_running(dev) && link_stat != netif_carrier_ok(dev)) {
352 netif_carrier_on(dev);
354 #ifdef CONFIG_CHELSIO_T4_DCB
355 cxgb4_dcb_state_init(dev);
356 dcb_tx_queue_prio_enable(dev, false);
357 #endif /* CONFIG_CHELSIO_T4_DCB */
358 netif_carrier_off(dev);
365 void t4_os_portmod_changed(const struct adapter *adap, int port_id)
367 static const char *mod_str[] = {
368 NULL, "LR", "SR", "ER", "passive DA", "active DA", "LRM"
371 const struct net_device *dev = adap->port[port_id];
372 const struct port_info *pi = netdev_priv(dev);
374 if (pi->mod_type == FW_PORT_MOD_TYPE_NONE)
375 netdev_info(dev, "port module unplugged\n");
376 else if (pi->mod_type < ARRAY_SIZE(mod_str))
377 netdev_info(dev, "%s module inserted\n", mod_str[pi->mod_type]);
381 * Configure the exact and hash address filters to handle a port's multicast
382 * and secondary unicast MAC addresses.
384 static int set_addr_filters(const struct net_device *dev, bool sleep)
392 const struct netdev_hw_addr *ha;
393 int uc_cnt = netdev_uc_count(dev);
394 int mc_cnt = netdev_mc_count(dev);
395 const struct port_info *pi = netdev_priv(dev);
396 unsigned int mb = pi->adapter->pf;
398 /* first do the secondary unicast addresses */
399 netdev_for_each_uc_addr(ha, dev) {
400 addr[naddr++] = ha->addr;
401 if (--uc_cnt == 0 || naddr >= ARRAY_SIZE(addr)) {
402 ret = t4_alloc_mac_filt(pi->adapter, mb, pi->viid, free,
403 naddr, addr, filt_idx, &uhash, sleep);
412 /* next set up the multicast addresses */
413 netdev_for_each_mc_addr(ha, dev) {
414 addr[naddr++] = ha->addr;
415 if (--mc_cnt == 0 || naddr >= ARRAY_SIZE(addr)) {
416 ret = t4_alloc_mac_filt(pi->adapter, mb, pi->viid, free,
417 naddr, addr, filt_idx, &mhash, sleep);
426 return t4_set_addr_hash(pi->adapter, mb, pi->viid, uhash != 0,
427 uhash | mhash, sleep);
430 int dbfifo_int_thresh = 10; /* 10 == 640 entry threshold */
431 module_param(dbfifo_int_thresh, int, 0644);
432 MODULE_PARM_DESC(dbfifo_int_thresh, "doorbell fifo interrupt threshold");
435 * usecs to sleep while draining the dbfifo
437 static int dbfifo_drain_delay = 1000;
438 module_param(dbfifo_drain_delay, int, 0644);
439 MODULE_PARM_DESC(dbfifo_drain_delay,
440 "usecs to sleep while draining the dbfifo");
443 * Set Rx properties of a port, such as promiscruity, address filters, and MTU.
444 * If @mtu is -1 it is left unchanged.
446 static int set_rxmode(struct net_device *dev, int mtu, bool sleep_ok)
449 struct port_info *pi = netdev_priv(dev);
451 ret = set_addr_filters(dev, sleep_ok);
453 ret = t4_set_rxmode(pi->adapter, pi->adapter->pf, pi->viid, mtu,
454 (dev->flags & IFF_PROMISC) ? 1 : 0,
455 (dev->flags & IFF_ALLMULTI) ? 1 : 0, 1, -1,
461 * link_start - enable a port
462 * @dev: the port to enable
464 * Performs the MAC and PHY actions needed to enable a port.
466 static int link_start(struct net_device *dev)
469 struct port_info *pi = netdev_priv(dev);
470 unsigned int mb = pi->adapter->pf;
473 * We do not set address filters and promiscuity here, the stack does
474 * that step explicitly.
476 ret = t4_set_rxmode(pi->adapter, mb, pi->viid, dev->mtu, -1, -1, -1,
477 !!(dev->features & NETIF_F_HW_VLAN_CTAG_RX), true);
479 ret = t4_change_mac(pi->adapter, mb, pi->viid,
480 pi->xact_addr_filt, dev->dev_addr, true,
483 pi->xact_addr_filt = ret;
488 ret = t4_link_l1cfg(pi->adapter, mb, pi->tx_chan,
492 ret = t4_enable_vi_params(pi->adapter, mb, pi->viid, true,
493 true, CXGB4_DCB_ENABLED);
500 int cxgb4_dcb_enabled(const struct net_device *dev)
502 #ifdef CONFIG_CHELSIO_T4_DCB
503 struct port_info *pi = netdev_priv(dev);
505 if (!pi->dcb.enabled)
508 return ((pi->dcb.state == CXGB4_DCB_STATE_FW_ALLSYNCED) ||
509 (pi->dcb.state == CXGB4_DCB_STATE_HOST));
514 EXPORT_SYMBOL(cxgb4_dcb_enabled);
516 #ifdef CONFIG_CHELSIO_T4_DCB
517 /* Handle a Data Center Bridging update message from the firmware. */
518 static void dcb_rpl(struct adapter *adap, const struct fw_port_cmd *pcmd)
520 int port = FW_PORT_CMD_PORTID_G(ntohl(pcmd->op_to_portid));
521 struct net_device *dev = adap->port[port];
522 int old_dcb_enabled = cxgb4_dcb_enabled(dev);
525 cxgb4_dcb_handle_fw_update(adap, pcmd);
526 new_dcb_enabled = cxgb4_dcb_enabled(dev);
528 /* If the DCB has become enabled or disabled on the port then we're
529 * going to need to set up/tear down DCB Priority parameters for the
530 * TX Queues associated with the port.
532 if (new_dcb_enabled != old_dcb_enabled)
533 dcb_tx_queue_prio_enable(dev, new_dcb_enabled);
535 #endif /* CONFIG_CHELSIO_T4_DCB */
537 /* Clear a filter and release any of its resources that we own. This also
538 * clears the filter's "pending" status.
540 static void clear_filter(struct adapter *adap, struct filter_entry *f)
542 /* If the new or old filter have loopback rewriteing rules then we'll
543 * need to free any existing Layer Two Table (L2T) entries of the old
544 * filter rule. The firmware will handle freeing up any Source MAC
545 * Table (SMT) entries used for rewriting Source MAC Addresses in
549 cxgb4_l2t_release(f->l2t);
551 /* The zeroing of the filter rule below clears the filter valid,
552 * pending, locked flags, l2t pointer, etc. so it's all we need for
555 memset(f, 0, sizeof(*f));
558 /* Handle a filter write/deletion reply.
560 static void filter_rpl(struct adapter *adap, const struct cpl_set_tcb_rpl *rpl)
562 unsigned int idx = GET_TID(rpl);
563 unsigned int nidx = idx - adap->tids.ftid_base;
565 struct filter_entry *f;
567 if (idx >= adap->tids.ftid_base && nidx <
568 (adap->tids.nftids + adap->tids.nsftids)) {
570 ret = TCB_COOKIE_G(rpl->cookie);
571 f = &adap->tids.ftid_tab[idx];
573 if (ret == FW_FILTER_WR_FLT_DELETED) {
574 /* Clear the filter when we get confirmation from the
575 * hardware that the filter has been deleted.
577 clear_filter(adap, f);
578 } else if (ret == FW_FILTER_WR_SMT_TBL_FULL) {
579 dev_err(adap->pdev_dev, "filter %u setup failed due to full SMT\n",
581 clear_filter(adap, f);
582 } else if (ret == FW_FILTER_WR_FLT_ADDED) {
583 f->smtidx = (be64_to_cpu(rpl->oldval) >> 24) & 0xff;
584 f->pending = 0; /* asynchronous setup completed */
587 /* Something went wrong. Issue a warning about the
588 * problem and clear everything out.
590 dev_err(adap->pdev_dev, "filter %u setup failed with error %u\n",
592 clear_filter(adap, f);
597 /* Response queue handler for the FW event queue.
599 static int fwevtq_handler(struct sge_rspq *q, const __be64 *rsp,
600 const struct pkt_gl *gl)
602 u8 opcode = ((const struct rss_header *)rsp)->opcode;
604 rsp++; /* skip RSS header */
606 /* FW can send EGR_UPDATEs encapsulated in a CPL_FW4_MSG.
608 if (unlikely(opcode == CPL_FW4_MSG &&
609 ((const struct cpl_fw4_msg *)rsp)->type == FW_TYPE_RSSCPL)) {
611 opcode = ((const struct rss_header *)rsp)->opcode;
613 if (opcode != CPL_SGE_EGR_UPDATE) {
614 dev_err(q->adap->pdev_dev, "unexpected FW4/CPL %#x on FW event queue\n"
620 if (likely(opcode == CPL_SGE_EGR_UPDATE)) {
621 const struct cpl_sge_egr_update *p = (void *)rsp;
622 unsigned int qid = EGR_QID_G(ntohl(p->opcode_qid));
625 txq = q->adap->sge.egr_map[qid - q->adap->sge.egr_start];
627 if ((u8 *)txq < (u8 *)q->adap->sge.ofldtxq) {
628 struct sge_eth_txq *eq;
630 eq = container_of(txq, struct sge_eth_txq, q);
631 netif_tx_wake_queue(eq->txq);
633 struct sge_ofld_txq *oq;
635 oq = container_of(txq, struct sge_ofld_txq, q);
636 tasklet_schedule(&oq->qresume_tsk);
638 } else if (opcode == CPL_FW6_MSG || opcode == CPL_FW4_MSG) {
639 const struct cpl_fw6_msg *p = (void *)rsp;
641 #ifdef CONFIG_CHELSIO_T4_DCB
642 const struct fw_port_cmd *pcmd = (const void *)p->data;
643 unsigned int cmd = FW_CMD_OP_G(ntohl(pcmd->op_to_portid));
644 unsigned int action =
645 FW_PORT_CMD_ACTION_G(ntohl(pcmd->action_to_len16));
647 if (cmd == FW_PORT_CMD &&
648 action == FW_PORT_ACTION_GET_PORT_INFO) {
649 int port = FW_PORT_CMD_PORTID_G(
650 be32_to_cpu(pcmd->op_to_portid));
651 struct net_device *dev = q->adap->port[port];
652 int state_input = ((pcmd->u.info.dcbxdis_pkd &
653 FW_PORT_CMD_DCBXDIS_F)
654 ? CXGB4_DCB_INPUT_FW_DISABLED
655 : CXGB4_DCB_INPUT_FW_ENABLED);
657 cxgb4_dcb_state_fsm(dev, state_input);
660 if (cmd == FW_PORT_CMD &&
661 action == FW_PORT_ACTION_L2_DCB_CFG)
662 dcb_rpl(q->adap, pcmd);
666 t4_handle_fw_rpl(q->adap, p->data);
667 } else if (opcode == CPL_L2T_WRITE_RPL) {
668 const struct cpl_l2t_write_rpl *p = (void *)rsp;
670 do_l2t_write_rpl(q->adap, p);
671 } else if (opcode == CPL_SET_TCB_RPL) {
672 const struct cpl_set_tcb_rpl *p = (void *)rsp;
674 filter_rpl(q->adap, p);
676 dev_err(q->adap->pdev_dev,
677 "unexpected CPL %#x on FW event queue\n", opcode);
683 * uldrx_handler - response queue handler for ULD queues
684 * @q: the response queue that received the packet
685 * @rsp: the response queue descriptor holding the offload message
686 * @gl: the gather list of packet fragments
688 * Deliver an ingress offload packet to a ULD. All processing is done by
689 * the ULD, we just maintain statistics.
691 static int uldrx_handler(struct sge_rspq *q, const __be64 *rsp,
692 const struct pkt_gl *gl)
694 struct sge_ofld_rxq *rxq = container_of(q, struct sge_ofld_rxq, rspq);
696 /* FW can send CPLs encapsulated in a CPL_FW4_MSG.
698 if (((const struct rss_header *)rsp)->opcode == CPL_FW4_MSG &&
699 ((const struct cpl_fw4_msg *)(rsp + 1))->type == FW_TYPE_RSSCPL)
702 if (ulds[q->uld].rx_handler(q->adap->uld_handle[q->uld], rsp, gl)) {
708 else if (gl == CXGB4_MSG_AN)
715 static void disable_msi(struct adapter *adapter)
717 if (adapter->flags & USING_MSIX) {
718 pci_disable_msix(adapter->pdev);
719 adapter->flags &= ~USING_MSIX;
720 } else if (adapter->flags & USING_MSI) {
721 pci_disable_msi(adapter->pdev);
722 adapter->flags &= ~USING_MSI;
727 * Interrupt handler for non-data events used with MSI-X.
729 static irqreturn_t t4_nondata_intr(int irq, void *cookie)
731 struct adapter *adap = cookie;
732 u32 v = t4_read_reg(adap, MYPF_REG(PL_PF_INT_CAUSE_A));
736 t4_write_reg(adap, MYPF_REG(PL_PF_INT_CAUSE_A), v);
738 if (adap->flags & MASTER_PF)
739 t4_slow_intr_handler(adap);
744 * Name the MSI-X interrupts.
746 static void name_msix_vecs(struct adapter *adap)
748 int i, j, msi_idx = 2, n = sizeof(adap->msix_info[0].desc);
750 /* non-data interrupts */
751 snprintf(adap->msix_info[0].desc, n, "%s", adap->port[0]->name);
754 snprintf(adap->msix_info[1].desc, n, "%s-FWeventq",
755 adap->port[0]->name);
757 /* Ethernet queues */
758 for_each_port(adap, j) {
759 struct net_device *d = adap->port[j];
760 const struct port_info *pi = netdev_priv(d);
762 for (i = 0; i < pi->nqsets; i++, msi_idx++)
763 snprintf(adap->msix_info[msi_idx].desc, n, "%s-Rx%d",
768 for_each_ofldrxq(&adap->sge, i)
769 snprintf(adap->msix_info[msi_idx++].desc, n, "%s-ofld%d",
770 adap->port[0]->name, i);
772 for_each_rdmarxq(&adap->sge, i)
773 snprintf(adap->msix_info[msi_idx++].desc, n, "%s-rdma%d",
774 adap->port[0]->name, i);
776 for_each_rdmaciq(&adap->sge, i)
777 snprintf(adap->msix_info[msi_idx++].desc, n, "%s-rdma-ciq%d",
778 adap->port[0]->name, i);
781 static int request_msix_queue_irqs(struct adapter *adap)
783 struct sge *s = &adap->sge;
784 int err, ethqidx, ofldqidx = 0, rdmaqidx = 0, rdmaciqqidx = 0;
787 err = request_irq(adap->msix_info[1].vec, t4_sge_intr_msix, 0,
788 adap->msix_info[1].desc, &s->fw_evtq);
792 for_each_ethrxq(s, ethqidx) {
793 err = request_irq(adap->msix_info[msi_index].vec,
795 adap->msix_info[msi_index].desc,
796 &s->ethrxq[ethqidx].rspq);
801 for_each_ofldrxq(s, ofldqidx) {
802 err = request_irq(adap->msix_info[msi_index].vec,
804 adap->msix_info[msi_index].desc,
805 &s->ofldrxq[ofldqidx].rspq);
810 for_each_rdmarxq(s, rdmaqidx) {
811 err = request_irq(adap->msix_info[msi_index].vec,
813 adap->msix_info[msi_index].desc,
814 &s->rdmarxq[rdmaqidx].rspq);
819 for_each_rdmaciq(s, rdmaciqqidx) {
820 err = request_irq(adap->msix_info[msi_index].vec,
822 adap->msix_info[msi_index].desc,
823 &s->rdmaciq[rdmaciqqidx].rspq);
831 while (--rdmaciqqidx >= 0)
832 free_irq(adap->msix_info[--msi_index].vec,
833 &s->rdmaciq[rdmaciqqidx].rspq);
834 while (--rdmaqidx >= 0)
835 free_irq(adap->msix_info[--msi_index].vec,
836 &s->rdmarxq[rdmaqidx].rspq);
837 while (--ofldqidx >= 0)
838 free_irq(adap->msix_info[--msi_index].vec,
839 &s->ofldrxq[ofldqidx].rspq);
840 while (--ethqidx >= 0)
841 free_irq(adap->msix_info[--msi_index].vec,
842 &s->ethrxq[ethqidx].rspq);
843 free_irq(adap->msix_info[1].vec, &s->fw_evtq);
847 static void free_msix_queue_irqs(struct adapter *adap)
849 int i, msi_index = 2;
850 struct sge *s = &adap->sge;
852 free_irq(adap->msix_info[1].vec, &s->fw_evtq);
853 for_each_ethrxq(s, i)
854 free_irq(adap->msix_info[msi_index++].vec, &s->ethrxq[i].rspq);
855 for_each_ofldrxq(s, i)
856 free_irq(adap->msix_info[msi_index++].vec, &s->ofldrxq[i].rspq);
857 for_each_rdmarxq(s, i)
858 free_irq(adap->msix_info[msi_index++].vec, &s->rdmarxq[i].rspq);
859 for_each_rdmaciq(s, i)
860 free_irq(adap->msix_info[msi_index++].vec, &s->rdmaciq[i].rspq);
864 * cxgb4_write_rss - write the RSS table for a given port
866 * @queues: array of queue indices for RSS
868 * Sets up the portion of the HW RSS table for the port's VI to distribute
869 * packets to the Rx queues in @queues.
870 * Should never be called before setting up sge eth rx queues
872 int cxgb4_write_rss(const struct port_info *pi, const u16 *queues)
876 struct adapter *adapter = pi->adapter;
877 const struct sge_eth_rxq *rxq;
879 rxq = &adapter->sge.ethrxq[pi->first_qset];
880 rss = kmalloc(pi->rss_size * sizeof(u16), GFP_KERNEL);
884 /* map the queue indices to queue ids */
885 for (i = 0; i < pi->rss_size; i++, queues++)
886 rss[i] = rxq[*queues].rspq.abs_id;
888 err = t4_config_rss_range(adapter, adapter->pf, pi->viid, 0,
889 pi->rss_size, rss, pi->rss_size);
890 /* If Tunnel All Lookup isn't specified in the global RSS
891 * Configuration, then we need to specify a default Ingress
892 * Queue for any ingress packets which aren't hashed. We'll
893 * use our first ingress queue ...
896 err = t4_config_vi_rss(adapter, adapter->mbox, pi->viid,
897 FW_RSS_VI_CONFIG_CMD_IP6FOURTUPEN_F |
898 FW_RSS_VI_CONFIG_CMD_IP6TWOTUPEN_F |
899 FW_RSS_VI_CONFIG_CMD_IP4FOURTUPEN_F |
900 FW_RSS_VI_CONFIG_CMD_IP4TWOTUPEN_F |
901 FW_RSS_VI_CONFIG_CMD_UDPEN_F,
908 * setup_rss - configure RSS
911 * Sets up RSS for each port.
913 static int setup_rss(struct adapter *adap)
917 for_each_port(adap, i) {
918 const struct port_info *pi = adap2pinfo(adap, i);
920 /* Fill default values with equal distribution */
921 for (j = 0; j < pi->rss_size; j++)
922 pi->rss[j] = j % pi->nqsets;
924 err = cxgb4_write_rss(pi, pi->rss);
932 * Return the channel of the ingress queue with the given qid.
934 static unsigned int rxq_to_chan(const struct sge *p, unsigned int qid)
936 qid -= p->ingr_start;
937 return netdev2pinfo(p->ingr_map[qid]->netdev)->tx_chan;
941 * Wait until all NAPI handlers are descheduled.
943 static void quiesce_rx(struct adapter *adap)
947 for (i = 0; i < adap->sge.ingr_sz; i++) {
948 struct sge_rspq *q = adap->sge.ingr_map[i];
950 if (q && q->handler) {
951 napi_disable(&q->napi);
953 while (!cxgb_poll_lock_napi(q))
961 /* Disable interrupt and napi handler */
962 static void disable_interrupts(struct adapter *adap)
964 if (adap->flags & FULL_INIT_DONE) {
965 t4_intr_disable(adap);
966 if (adap->flags & USING_MSIX) {
967 free_msix_queue_irqs(adap);
968 free_irq(adap->msix_info[0].vec, adap);
970 free_irq(adap->pdev->irq, adap);
977 * Enable NAPI scheduling and interrupt generation for all Rx queues.
979 static void enable_rx(struct adapter *adap)
983 for (i = 0; i < adap->sge.ingr_sz; i++) {
984 struct sge_rspq *q = adap->sge.ingr_map[i];
989 cxgb_busy_poll_init_lock(q);
990 napi_enable(&q->napi);
992 /* 0-increment GTS to start the timer and enable interrupts */
993 t4_write_reg(adap, MYPF_REG(SGE_PF_GTS_A),
994 SEINTARM_V(q->intr_params) |
995 INGRESSQID_V(q->cntxt_id));
999 static int alloc_ofld_rxqs(struct adapter *adap, struct sge_ofld_rxq *q,
1000 unsigned int nq, unsigned int per_chan, int msi_idx,
1005 for (i = 0; i < nq; i++, q++) {
1008 err = t4_sge_alloc_rxq(adap, &q->rspq, false,
1009 adap->port[i / per_chan],
1010 msi_idx, q->fl.size ? &q->fl : NULL,
1014 memset(&q->stats, 0, sizeof(q->stats));
1016 ids[i] = q->rspq.abs_id;
1022 * setup_sge_queues - configure SGE Tx/Rx/response queues
1023 * @adap: the adapter
1025 * Determines how many sets of SGE queues to use and initializes them.
1026 * We support multiple queue sets per port if we have MSI-X, otherwise
1027 * just one queue set per port.
1029 static int setup_sge_queues(struct adapter *adap)
1031 int err, msi_idx, i, j;
1032 struct sge *s = &adap->sge;
1034 bitmap_zero(s->starving_fl, s->egr_sz);
1035 bitmap_zero(s->txq_maperr, s->egr_sz);
1037 if (adap->flags & USING_MSIX)
1038 msi_idx = 1; /* vector 0 is for non-queue interrupts */
1040 err = t4_sge_alloc_rxq(adap, &s->intrq, false, adap->port[0], 0,
1044 msi_idx = -((int)s->intrq.abs_id + 1);
1047 /* NOTE: If you add/delete any Ingress/Egress Queue allocations in here,
1048 * don't forget to update the following which need to be
1049 * synchronized to and changes here.
1051 * 1. The calculations of MAX_INGQ in cxgb4.h.
1053 * 2. Update enable_msix/name_msix_vecs/request_msix_queue_irqs
1054 * to accommodate any new/deleted Ingress Queues
1055 * which need MSI-X Vectors.
1057 * 3. Update sge_qinfo_show() to include information on the
1058 * new/deleted queues.
1060 err = t4_sge_alloc_rxq(adap, &s->fw_evtq, true, adap->port[0],
1061 msi_idx, NULL, fwevtq_handler, -1);
1063 freeout: t4_free_sge_resources(adap);
1067 for_each_port(adap, i) {
1068 struct net_device *dev = adap->port[i];
1069 struct port_info *pi = netdev_priv(dev);
1070 struct sge_eth_rxq *q = &s->ethrxq[pi->first_qset];
1071 struct sge_eth_txq *t = &s->ethtxq[pi->first_qset];
1073 for (j = 0; j < pi->nqsets; j++, q++) {
1076 err = t4_sge_alloc_rxq(adap, &q->rspq, false, dev,
1079 t4_get_mps_bg_map(adap,
1084 memset(&q->stats, 0, sizeof(q->stats));
1086 for (j = 0; j < pi->nqsets; j++, t++) {
1087 err = t4_sge_alloc_eth_txq(adap, t, dev,
1088 netdev_get_tx_queue(dev, j),
1089 s->fw_evtq.cntxt_id);
1095 j = s->ofldqsets / adap->params.nports; /* ofld queues per channel */
1096 for_each_ofldrxq(s, i) {
1097 err = t4_sge_alloc_ofld_txq(adap, &s->ofldtxq[i],
1099 s->fw_evtq.cntxt_id);
1104 #define ALLOC_OFLD_RXQS(firstq, nq, per_chan, ids) do { \
1105 err = alloc_ofld_rxqs(adap, firstq, nq, per_chan, msi_idx, ids); \
1112 ALLOC_OFLD_RXQS(s->ofldrxq, s->ofldqsets, j, s->ofld_rxq);
1113 ALLOC_OFLD_RXQS(s->rdmarxq, s->rdmaqs, 1, s->rdma_rxq);
1114 j = s->rdmaciqs / adap->params.nports; /* rdmaq queues per channel */
1115 ALLOC_OFLD_RXQS(s->rdmaciq, s->rdmaciqs, j, s->rdma_ciq);
1117 #undef ALLOC_OFLD_RXQS
1119 for_each_port(adap, i) {
1121 * Note that ->rdmarxq[i].rspq.cntxt_id below is 0 if we don't
1122 * have RDMA queues, and that's the right value.
1124 err = t4_sge_alloc_ctrl_txq(adap, &s->ctrlq[i], adap->port[i],
1125 s->fw_evtq.cntxt_id,
1126 s->rdmarxq[i].rspq.cntxt_id);
1131 t4_write_reg(adap, is_t4(adap->params.chip) ?
1132 MPS_TRC_RSS_CONTROL_A :
1133 MPS_T5_TRC_RSS_CONTROL_A,
1134 RSSCONTROL_V(netdev2pinfo(adap->port[0])->tx_chan) |
1135 QUEUENUMBER_V(s->ethrxq[0].rspq.abs_id));
1140 * Allocate a chunk of memory using kmalloc or, if that fails, vmalloc.
1141 * The allocated memory is cleared.
1143 void *t4_alloc_mem(size_t size)
1145 void *p = kzalloc(size, GFP_KERNEL | __GFP_NOWARN);
1153 * Free memory allocated through alloc_mem().
1155 void t4_free_mem(void *addr)
1160 /* Send a Work Request to write the filter at a specified index. We construct
1161 * a Firmware Filter Work Request to have the work done and put the indicated
1162 * filter into "pending" mode which will prevent any further actions against
1163 * it till we get a reply from the firmware on the completion status of the
1166 static int set_filter_wr(struct adapter *adapter, int fidx)
1168 struct filter_entry *f = &adapter->tids.ftid_tab[fidx];
1169 struct sk_buff *skb;
1170 struct fw_filter_wr *fwr;
1173 skb = alloc_skb(sizeof(*fwr), GFP_KERNEL);
1177 /* If the new filter requires loopback Destination MAC and/or VLAN
1178 * rewriting then we need to allocate a Layer 2 Table (L2T) entry for
1181 if (f->fs.newdmac || f->fs.newvlan) {
1182 /* allocate L2T entry for new filter */
1183 f->l2t = t4_l2t_alloc_switching(adapter->l2t);
1184 if (f->l2t == NULL) {
1188 if (t4_l2t_set_switching(adapter, f->l2t, f->fs.vlan,
1189 f->fs.eport, f->fs.dmac)) {
1190 cxgb4_l2t_release(f->l2t);
1197 ftid = adapter->tids.ftid_base + fidx;
1199 fwr = (struct fw_filter_wr *)__skb_put(skb, sizeof(*fwr));
1200 memset(fwr, 0, sizeof(*fwr));
1202 /* It would be nice to put most of the following in t4_hw.c but most
1203 * of the work is translating the cxgbtool ch_filter_specification
1204 * into the Work Request and the definition of that structure is
1205 * currently in cxgbtool.h which isn't appropriate to pull into the
1206 * common code. We may eventually try to come up with a more neutral
1207 * filter specification structure but for now it's easiest to simply
1208 * put this fairly direct code in line ...
1210 fwr->op_pkd = htonl(FW_WR_OP_V(FW_FILTER_WR));
1211 fwr->len16_pkd = htonl(FW_WR_LEN16_V(sizeof(*fwr)/16));
1213 htonl(FW_FILTER_WR_TID_V(ftid) |
1214 FW_FILTER_WR_RQTYPE_V(f->fs.type) |
1215 FW_FILTER_WR_NOREPLY_V(0) |
1216 FW_FILTER_WR_IQ_V(f->fs.iq));
1217 fwr->del_filter_to_l2tix =
1218 htonl(FW_FILTER_WR_RPTTID_V(f->fs.rpttid) |
1219 FW_FILTER_WR_DROP_V(f->fs.action == FILTER_DROP) |
1220 FW_FILTER_WR_DIRSTEER_V(f->fs.dirsteer) |
1221 FW_FILTER_WR_MASKHASH_V(f->fs.maskhash) |
1222 FW_FILTER_WR_DIRSTEERHASH_V(f->fs.dirsteerhash) |
1223 FW_FILTER_WR_LPBK_V(f->fs.action == FILTER_SWITCH) |
1224 FW_FILTER_WR_DMAC_V(f->fs.newdmac) |
1225 FW_FILTER_WR_SMAC_V(f->fs.newsmac) |
1226 FW_FILTER_WR_INSVLAN_V(f->fs.newvlan == VLAN_INSERT ||
1227 f->fs.newvlan == VLAN_REWRITE) |
1228 FW_FILTER_WR_RMVLAN_V(f->fs.newvlan == VLAN_REMOVE ||
1229 f->fs.newvlan == VLAN_REWRITE) |
1230 FW_FILTER_WR_HITCNTS_V(f->fs.hitcnts) |
1231 FW_FILTER_WR_TXCHAN_V(f->fs.eport) |
1232 FW_FILTER_WR_PRIO_V(f->fs.prio) |
1233 FW_FILTER_WR_L2TIX_V(f->l2t ? f->l2t->idx : 0));
1234 fwr->ethtype = htons(f->fs.val.ethtype);
1235 fwr->ethtypem = htons(f->fs.mask.ethtype);
1236 fwr->frag_to_ovlan_vldm =
1237 (FW_FILTER_WR_FRAG_V(f->fs.val.frag) |
1238 FW_FILTER_WR_FRAGM_V(f->fs.mask.frag) |
1239 FW_FILTER_WR_IVLAN_VLD_V(f->fs.val.ivlan_vld) |
1240 FW_FILTER_WR_OVLAN_VLD_V(f->fs.val.ovlan_vld) |
1241 FW_FILTER_WR_IVLAN_VLDM_V(f->fs.mask.ivlan_vld) |
1242 FW_FILTER_WR_OVLAN_VLDM_V(f->fs.mask.ovlan_vld));
1244 fwr->rx_chan_rx_rpl_iq =
1245 htons(FW_FILTER_WR_RX_CHAN_V(0) |
1246 FW_FILTER_WR_RX_RPL_IQ_V(adapter->sge.fw_evtq.abs_id));
1247 fwr->maci_to_matchtypem =
1248 htonl(FW_FILTER_WR_MACI_V(f->fs.val.macidx) |
1249 FW_FILTER_WR_MACIM_V(f->fs.mask.macidx) |
1250 FW_FILTER_WR_FCOE_V(f->fs.val.fcoe) |
1251 FW_FILTER_WR_FCOEM_V(f->fs.mask.fcoe) |
1252 FW_FILTER_WR_PORT_V(f->fs.val.iport) |
1253 FW_FILTER_WR_PORTM_V(f->fs.mask.iport) |
1254 FW_FILTER_WR_MATCHTYPE_V(f->fs.val.matchtype) |
1255 FW_FILTER_WR_MATCHTYPEM_V(f->fs.mask.matchtype));
1256 fwr->ptcl = f->fs.val.proto;
1257 fwr->ptclm = f->fs.mask.proto;
1258 fwr->ttyp = f->fs.val.tos;
1259 fwr->ttypm = f->fs.mask.tos;
1260 fwr->ivlan = htons(f->fs.val.ivlan);
1261 fwr->ivlanm = htons(f->fs.mask.ivlan);
1262 fwr->ovlan = htons(f->fs.val.ovlan);
1263 fwr->ovlanm = htons(f->fs.mask.ovlan);
1264 memcpy(fwr->lip, f->fs.val.lip, sizeof(fwr->lip));
1265 memcpy(fwr->lipm, f->fs.mask.lip, sizeof(fwr->lipm));
1266 memcpy(fwr->fip, f->fs.val.fip, sizeof(fwr->fip));
1267 memcpy(fwr->fipm, f->fs.mask.fip, sizeof(fwr->fipm));
1268 fwr->lp = htons(f->fs.val.lport);
1269 fwr->lpm = htons(f->fs.mask.lport);
1270 fwr->fp = htons(f->fs.val.fport);
1271 fwr->fpm = htons(f->fs.mask.fport);
1273 memcpy(fwr->sma, f->fs.smac, sizeof(fwr->sma));
1275 /* Mark the filter as "pending" and ship off the Filter Work Request.
1276 * When we get the Work Request Reply we'll clear the pending status.
1279 set_wr_txq(skb, CPL_PRIORITY_CONTROL, f->fs.val.iport & 0x3);
1280 t4_ofld_send(adapter, skb);
1284 /* Delete the filter at a specified index.
1286 static int del_filter_wr(struct adapter *adapter, int fidx)
1288 struct filter_entry *f = &adapter->tids.ftid_tab[fidx];
1289 struct sk_buff *skb;
1290 struct fw_filter_wr *fwr;
1291 unsigned int len, ftid;
1294 ftid = adapter->tids.ftid_base + fidx;
1296 skb = alloc_skb(len, GFP_KERNEL);
1300 fwr = (struct fw_filter_wr *)__skb_put(skb, len);
1301 t4_mk_filtdelwr(ftid, fwr, adapter->sge.fw_evtq.abs_id);
1303 /* Mark the filter as "pending" and ship off the Filter Work Request.
1304 * When we get the Work Request Reply we'll clear the pending status.
1307 t4_mgmt_tx(adapter, skb);
1311 static u16 cxgb_select_queue(struct net_device *dev, struct sk_buff *skb,
1312 void *accel_priv, select_queue_fallback_t fallback)
1316 #ifdef CONFIG_CHELSIO_T4_DCB
1317 /* If a Data Center Bridging has been successfully negotiated on this
1318 * link then we'll use the skb's priority to map it to a TX Queue.
1319 * The skb's priority is determined via the VLAN Tag Priority Code
1322 if (cxgb4_dcb_enabled(dev)) {
1326 err = vlan_get_tag(skb, &vlan_tci);
1327 if (unlikely(err)) {
1328 if (net_ratelimit())
1330 "TX Packet without VLAN Tag on DCB Link\n");
1333 txq = (vlan_tci & VLAN_PRIO_MASK) >> VLAN_PRIO_SHIFT;
1334 #ifdef CONFIG_CHELSIO_T4_FCOE
1335 if (skb->protocol == htons(ETH_P_FCOE))
1336 txq = skb->priority & 0x7;
1337 #endif /* CONFIG_CHELSIO_T4_FCOE */
1341 #endif /* CONFIG_CHELSIO_T4_DCB */
1344 txq = (skb_rx_queue_recorded(skb)
1345 ? skb_get_rx_queue(skb)
1346 : smp_processor_id());
1348 while (unlikely(txq >= dev->real_num_tx_queues))
1349 txq -= dev->real_num_tx_queues;
1354 return fallback(dev, skb) % dev->real_num_tx_queues;
1357 static int closest_timer(const struct sge *s, int time)
1359 int i, delta, match = 0, min_delta = INT_MAX;
1361 for (i = 0; i < ARRAY_SIZE(s->timer_val); i++) {
1362 delta = time - s->timer_val[i];
1365 if (delta < min_delta) {
1373 static int closest_thres(const struct sge *s, int thres)
1375 int i, delta, match = 0, min_delta = INT_MAX;
1377 for (i = 0; i < ARRAY_SIZE(s->counter_val); i++) {
1378 delta = thres - s->counter_val[i];
1381 if (delta < min_delta) {
1390 * cxgb4_set_rspq_intr_params - set a queue's interrupt holdoff parameters
1392 * @us: the hold-off time in us, or 0 to disable timer
1393 * @cnt: the hold-off packet count, or 0 to disable counter
1395 * Sets an Rx queue's interrupt hold-off time and packet count. At least
1396 * one of the two needs to be enabled for the queue to generate interrupts.
1398 int cxgb4_set_rspq_intr_params(struct sge_rspq *q,
1399 unsigned int us, unsigned int cnt)
1401 struct adapter *adap = q->adap;
1403 if ((us | cnt) == 0)
1410 new_idx = closest_thres(&adap->sge, cnt);
1411 if (q->desc && q->pktcnt_idx != new_idx) {
1412 /* the queue has already been created, update it */
1413 v = FW_PARAMS_MNEM_V(FW_PARAMS_MNEM_DMAQ) |
1414 FW_PARAMS_PARAM_X_V(
1415 FW_PARAMS_PARAM_DMAQ_IQ_INTCNTTHRESH) |
1416 FW_PARAMS_PARAM_YZ_V(q->cntxt_id);
1417 err = t4_set_params(adap, adap->mbox, adap->pf, 0, 1,
1422 q->pktcnt_idx = new_idx;
1425 us = us == 0 ? 6 : closest_timer(&adap->sge, us);
1426 q->intr_params = QINTR_TIMER_IDX_V(us) | QINTR_CNT_EN_V(cnt > 0);
1430 static int cxgb_set_features(struct net_device *dev, netdev_features_t features)
1432 const struct port_info *pi = netdev_priv(dev);
1433 netdev_features_t changed = dev->features ^ features;
1436 if (!(changed & NETIF_F_HW_VLAN_CTAG_RX))
1439 err = t4_set_rxmode(pi->adapter, pi->adapter->pf, pi->viid, -1,
1441 !!(features & NETIF_F_HW_VLAN_CTAG_RX), true);
1443 dev->features = features ^ NETIF_F_HW_VLAN_CTAG_RX;
1447 static int setup_debugfs(struct adapter *adap)
1449 if (IS_ERR_OR_NULL(adap->debugfs_root))
1452 #ifdef CONFIG_DEBUG_FS
1453 t4_setup_debugfs(adap);
1459 * upper-layer driver support
1463 * Allocate an active-open TID and set it to the supplied value.
1465 int cxgb4_alloc_atid(struct tid_info *t, void *data)
1469 spin_lock_bh(&t->atid_lock);
1471 union aopen_entry *p = t->afree;
1473 atid = (p - t->atid_tab) + t->atid_base;
1478 spin_unlock_bh(&t->atid_lock);
1481 EXPORT_SYMBOL(cxgb4_alloc_atid);
1484 * Release an active-open TID.
1486 void cxgb4_free_atid(struct tid_info *t, unsigned int atid)
1488 union aopen_entry *p = &t->atid_tab[atid - t->atid_base];
1490 spin_lock_bh(&t->atid_lock);
1494 spin_unlock_bh(&t->atid_lock);
1496 EXPORT_SYMBOL(cxgb4_free_atid);
1499 * Allocate a server TID and set it to the supplied value.
1501 int cxgb4_alloc_stid(struct tid_info *t, int family, void *data)
1505 spin_lock_bh(&t->stid_lock);
1506 if (family == PF_INET) {
1507 stid = find_first_zero_bit(t->stid_bmap, t->nstids);
1508 if (stid < t->nstids)
1509 __set_bit(stid, t->stid_bmap);
1513 stid = bitmap_find_free_region(t->stid_bmap, t->nstids, 2);
1518 t->stid_tab[stid].data = data;
1519 stid += t->stid_base;
1520 /* IPv6 requires max of 520 bits or 16 cells in TCAM
1521 * This is equivalent to 4 TIDs. With CLIP enabled it
1524 if (family == PF_INET)
1527 t->stids_in_use += 4;
1529 spin_unlock_bh(&t->stid_lock);
1532 EXPORT_SYMBOL(cxgb4_alloc_stid);
1534 /* Allocate a server filter TID and set it to the supplied value.
1536 int cxgb4_alloc_sftid(struct tid_info *t, int family, void *data)
1540 spin_lock_bh(&t->stid_lock);
1541 if (family == PF_INET) {
1542 stid = find_next_zero_bit(t->stid_bmap,
1543 t->nstids + t->nsftids, t->nstids);
1544 if (stid < (t->nstids + t->nsftids))
1545 __set_bit(stid, t->stid_bmap);
1552 t->stid_tab[stid].data = data;
1554 stid += t->sftid_base;
1557 spin_unlock_bh(&t->stid_lock);
1560 EXPORT_SYMBOL(cxgb4_alloc_sftid);
1562 /* Release a server TID.
1564 void cxgb4_free_stid(struct tid_info *t, unsigned int stid, int family)
1566 /* Is it a server filter TID? */
1567 if (t->nsftids && (stid >= t->sftid_base)) {
1568 stid -= t->sftid_base;
1571 stid -= t->stid_base;
1574 spin_lock_bh(&t->stid_lock);
1575 if (family == PF_INET)
1576 __clear_bit(stid, t->stid_bmap);
1578 bitmap_release_region(t->stid_bmap, stid, 2);
1579 t->stid_tab[stid].data = NULL;
1580 if (stid < t->nstids) {
1581 if (family == PF_INET)
1584 t->stids_in_use -= 4;
1588 spin_unlock_bh(&t->stid_lock);
1590 EXPORT_SYMBOL(cxgb4_free_stid);
1593 * Populate a TID_RELEASE WR. Caller must properly size the skb.
1595 static void mk_tid_release(struct sk_buff *skb, unsigned int chan,
1598 struct cpl_tid_release *req;
1600 set_wr_txq(skb, CPL_PRIORITY_SETUP, chan);
1601 req = (struct cpl_tid_release *)__skb_put(skb, sizeof(*req));
1602 INIT_TP_WR(req, tid);
1603 OPCODE_TID(req) = htonl(MK_OPCODE_TID(CPL_TID_RELEASE, tid));
1607 * Queue a TID release request and if necessary schedule a work queue to
1610 static void cxgb4_queue_tid_release(struct tid_info *t, unsigned int chan,
1613 void **p = &t->tid_tab[tid];
1614 struct adapter *adap = container_of(t, struct adapter, tids);
1616 spin_lock_bh(&adap->tid_release_lock);
1617 *p = adap->tid_release_head;
1618 /* Low 2 bits encode the Tx channel number */
1619 adap->tid_release_head = (void **)((uintptr_t)p | chan);
1620 if (!adap->tid_release_task_busy) {
1621 adap->tid_release_task_busy = true;
1622 queue_work(adap->workq, &adap->tid_release_task);
1624 spin_unlock_bh(&adap->tid_release_lock);
1628 * Process the list of pending TID release requests.
1630 static void process_tid_release_list(struct work_struct *work)
1632 struct sk_buff *skb;
1633 struct adapter *adap;
1635 adap = container_of(work, struct adapter, tid_release_task);
1637 spin_lock_bh(&adap->tid_release_lock);
1638 while (adap->tid_release_head) {
1639 void **p = adap->tid_release_head;
1640 unsigned int chan = (uintptr_t)p & 3;
1641 p = (void *)p - chan;
1643 adap->tid_release_head = *p;
1645 spin_unlock_bh(&adap->tid_release_lock);
1647 while (!(skb = alloc_skb(sizeof(struct cpl_tid_release),
1649 schedule_timeout_uninterruptible(1);
1651 mk_tid_release(skb, chan, p - adap->tids.tid_tab);
1652 t4_ofld_send(adap, skb);
1653 spin_lock_bh(&adap->tid_release_lock);
1655 adap->tid_release_task_busy = false;
1656 spin_unlock_bh(&adap->tid_release_lock);
1660 * Release a TID and inform HW. If we are unable to allocate the release
1661 * message we defer to a work queue.
1663 void cxgb4_remove_tid(struct tid_info *t, unsigned int chan, unsigned int tid)
1665 struct sk_buff *skb;
1666 struct adapter *adap = container_of(t, struct adapter, tids);
1668 WARN_ON(tid >= t->ntids);
1670 if (t->tid_tab[tid]) {
1671 t->tid_tab[tid] = NULL;
1672 if (t->hash_base && (tid >= t->hash_base))
1673 atomic_dec(&t->hash_tids_in_use);
1675 atomic_dec(&t->tids_in_use);
1678 skb = alloc_skb(sizeof(struct cpl_tid_release), GFP_ATOMIC);
1680 mk_tid_release(skb, chan, tid);
1681 t4_ofld_send(adap, skb);
1683 cxgb4_queue_tid_release(t, chan, tid);
1685 EXPORT_SYMBOL(cxgb4_remove_tid);
1688 * Allocate and initialize the TID tables. Returns 0 on success.
1690 static int tid_init(struct tid_info *t)
1693 unsigned int stid_bmap_size;
1694 unsigned int natids = t->natids;
1695 struct adapter *adap = container_of(t, struct adapter, tids);
1697 stid_bmap_size = BITS_TO_LONGS(t->nstids + t->nsftids);
1698 size = t->ntids * sizeof(*t->tid_tab) +
1699 natids * sizeof(*t->atid_tab) +
1700 t->nstids * sizeof(*t->stid_tab) +
1701 t->nsftids * sizeof(*t->stid_tab) +
1702 stid_bmap_size * sizeof(long) +
1703 t->nftids * sizeof(*t->ftid_tab) +
1704 t->nsftids * sizeof(*t->ftid_tab);
1706 t->tid_tab = t4_alloc_mem(size);
1710 t->atid_tab = (union aopen_entry *)&t->tid_tab[t->ntids];
1711 t->stid_tab = (struct serv_entry *)&t->atid_tab[natids];
1712 t->stid_bmap = (unsigned long *)&t->stid_tab[t->nstids + t->nsftids];
1713 t->ftid_tab = (struct filter_entry *)&t->stid_bmap[stid_bmap_size];
1714 spin_lock_init(&t->stid_lock);
1715 spin_lock_init(&t->atid_lock);
1717 t->stids_in_use = 0;
1718 t->sftids_in_use = 0;
1720 t->atids_in_use = 0;
1721 atomic_set(&t->tids_in_use, 0);
1722 atomic_set(&t->hash_tids_in_use, 0);
1724 /* Setup the free list for atid_tab and clear the stid bitmap. */
1727 t->atid_tab[natids - 1].next = &t->atid_tab[natids];
1728 t->afree = t->atid_tab;
1730 bitmap_zero(t->stid_bmap, t->nstids + t->nsftids);
1731 /* Reserve stid 0 for T4/T5 adapters */
1732 if (!t->stid_base &&
1733 (CHELSIO_CHIP_VERSION(adap->params.chip) <= CHELSIO_T5))
1734 __set_bit(0, t->stid_bmap);
1740 * cxgb4_create_server - create an IP server
1742 * @stid: the server TID
1743 * @sip: local IP address to bind server to
1744 * @sport: the server's TCP port
1745 * @queue: queue to direct messages from this server to
1747 * Create an IP server for the given port and address.
1748 * Returns <0 on error and one of the %NET_XMIT_* values on success.
1750 int cxgb4_create_server(const struct net_device *dev, unsigned int stid,
1751 __be32 sip, __be16 sport, __be16 vlan,
1755 struct sk_buff *skb;
1756 struct adapter *adap;
1757 struct cpl_pass_open_req *req;
1760 skb = alloc_skb(sizeof(*req), GFP_KERNEL);
1764 adap = netdev2adap(dev);
1765 req = (struct cpl_pass_open_req *)__skb_put(skb, sizeof(*req));
1767 OPCODE_TID(req) = htonl(MK_OPCODE_TID(CPL_PASS_OPEN_REQ, stid));
1768 req->local_port = sport;
1769 req->peer_port = htons(0);
1770 req->local_ip = sip;
1771 req->peer_ip = htonl(0);
1772 chan = rxq_to_chan(&adap->sge, queue);
1773 req->opt0 = cpu_to_be64(TX_CHAN_V(chan));
1774 req->opt1 = cpu_to_be64(CONN_POLICY_V(CPL_CONN_POLICY_ASK) |
1775 SYN_RSS_ENABLE_F | SYN_RSS_QUEUE_V(queue));
1776 ret = t4_mgmt_tx(adap, skb);
1777 return net_xmit_eval(ret);
1779 EXPORT_SYMBOL(cxgb4_create_server);
1781 /* cxgb4_create_server6 - create an IPv6 server
1783 * @stid: the server TID
1784 * @sip: local IPv6 address to bind server to
1785 * @sport: the server's TCP port
1786 * @queue: queue to direct messages from this server to
1788 * Create an IPv6 server for the given port and address.
1789 * Returns <0 on error and one of the %NET_XMIT_* values on success.
1791 int cxgb4_create_server6(const struct net_device *dev, unsigned int stid,
1792 const struct in6_addr *sip, __be16 sport,
1796 struct sk_buff *skb;
1797 struct adapter *adap;
1798 struct cpl_pass_open_req6 *req;
1801 skb = alloc_skb(sizeof(*req), GFP_KERNEL);
1805 adap = netdev2adap(dev);
1806 req = (struct cpl_pass_open_req6 *)__skb_put(skb, sizeof(*req));
1808 OPCODE_TID(req) = htonl(MK_OPCODE_TID(CPL_PASS_OPEN_REQ6, stid));
1809 req->local_port = sport;
1810 req->peer_port = htons(0);
1811 req->local_ip_hi = *(__be64 *)(sip->s6_addr);
1812 req->local_ip_lo = *(__be64 *)(sip->s6_addr + 8);
1813 req->peer_ip_hi = cpu_to_be64(0);
1814 req->peer_ip_lo = cpu_to_be64(0);
1815 chan = rxq_to_chan(&adap->sge, queue);
1816 req->opt0 = cpu_to_be64(TX_CHAN_V(chan));
1817 req->opt1 = cpu_to_be64(CONN_POLICY_V(CPL_CONN_POLICY_ASK) |
1818 SYN_RSS_ENABLE_F | SYN_RSS_QUEUE_V(queue));
1819 ret = t4_mgmt_tx(adap, skb);
1820 return net_xmit_eval(ret);
1822 EXPORT_SYMBOL(cxgb4_create_server6);
1824 int cxgb4_remove_server(const struct net_device *dev, unsigned int stid,
1825 unsigned int queue, bool ipv6)
1827 struct sk_buff *skb;
1828 struct adapter *adap;
1829 struct cpl_close_listsvr_req *req;
1832 adap = netdev2adap(dev);
1834 skb = alloc_skb(sizeof(*req), GFP_KERNEL);
1838 req = (struct cpl_close_listsvr_req *)__skb_put(skb, sizeof(*req));
1840 OPCODE_TID(req) = htonl(MK_OPCODE_TID(CPL_CLOSE_LISTSRV_REQ, stid));
1841 req->reply_ctrl = htons(NO_REPLY_V(0) | (ipv6 ? LISTSVR_IPV6_V(1) :
1842 LISTSVR_IPV6_V(0)) | QUEUENO_V(queue));
1843 ret = t4_mgmt_tx(adap, skb);
1844 return net_xmit_eval(ret);
1846 EXPORT_SYMBOL(cxgb4_remove_server);
1849 * cxgb4_best_mtu - find the entry in the MTU table closest to an MTU
1850 * @mtus: the HW MTU table
1851 * @mtu: the target MTU
1852 * @idx: index of selected entry in the MTU table
1854 * Returns the index and the value in the HW MTU table that is closest to
1855 * but does not exceed @mtu, unless @mtu is smaller than any value in the
1856 * table, in which case that smallest available value is selected.
1858 unsigned int cxgb4_best_mtu(const unsigned short *mtus, unsigned short mtu,
1863 while (i < NMTUS - 1 && mtus[i + 1] <= mtu)
1869 EXPORT_SYMBOL(cxgb4_best_mtu);
1872 * cxgb4_best_aligned_mtu - find best MTU, [hopefully] data size aligned
1873 * @mtus: the HW MTU table
1874 * @header_size: Header Size
1875 * @data_size_max: maximum Data Segment Size
1876 * @data_size_align: desired Data Segment Size Alignment (2^N)
1877 * @mtu_idxp: HW MTU Table Index return value pointer (possibly NULL)
1879 * Similar to cxgb4_best_mtu() but instead of searching the Hardware
1880 * MTU Table based solely on a Maximum MTU parameter, we break that
1881 * parameter up into a Header Size and Maximum Data Segment Size, and
1882 * provide a desired Data Segment Size Alignment. If we find an MTU in
1883 * the Hardware MTU Table which will result in a Data Segment Size with
1884 * the requested alignment _and_ that MTU isn't "too far" from the
1885 * closest MTU, then we'll return that rather than the closest MTU.
1887 unsigned int cxgb4_best_aligned_mtu(const unsigned short *mtus,
1888 unsigned short header_size,
1889 unsigned short data_size_max,
1890 unsigned short data_size_align,
1891 unsigned int *mtu_idxp)
1893 unsigned short max_mtu = header_size + data_size_max;
1894 unsigned short data_size_align_mask = data_size_align - 1;
1895 int mtu_idx, aligned_mtu_idx;
1897 /* Scan the MTU Table till we find an MTU which is larger than our
1898 * Maximum MTU or we reach the end of the table. Along the way,
1899 * record the last MTU found, if any, which will result in a Data
1900 * Segment Length matching the requested alignment.
1902 for (mtu_idx = 0, aligned_mtu_idx = -1; mtu_idx < NMTUS; mtu_idx++) {
1903 unsigned short data_size = mtus[mtu_idx] - header_size;
1905 /* If this MTU minus the Header Size would result in a
1906 * Data Segment Size of the desired alignment, remember it.
1908 if ((data_size & data_size_align_mask) == 0)
1909 aligned_mtu_idx = mtu_idx;
1911 /* If we're not at the end of the Hardware MTU Table and the
1912 * next element is larger than our Maximum MTU, drop out of
1915 if (mtu_idx+1 < NMTUS && mtus[mtu_idx+1] > max_mtu)
1919 /* If we fell out of the loop because we ran to the end of the table,
1920 * then we just have to use the last [largest] entry.
1922 if (mtu_idx == NMTUS)
1925 /* If we found an MTU which resulted in the requested Data Segment
1926 * Length alignment and that's "not far" from the largest MTU which is
1927 * less than or equal to the maximum MTU, then use that.
1929 if (aligned_mtu_idx >= 0 &&
1930 mtu_idx - aligned_mtu_idx <= 1)
1931 mtu_idx = aligned_mtu_idx;
1933 /* If the caller has passed in an MTU Index pointer, pass the
1934 * MTU Index back. Return the MTU value.
1937 *mtu_idxp = mtu_idx;
1938 return mtus[mtu_idx];
1940 EXPORT_SYMBOL(cxgb4_best_aligned_mtu);
1943 * cxgb4_port_chan - get the HW channel of a port
1944 * @dev: the net device for the port
1946 * Return the HW Tx channel of the given port.
1948 unsigned int cxgb4_port_chan(const struct net_device *dev)
1950 return netdev2pinfo(dev)->tx_chan;
1952 EXPORT_SYMBOL(cxgb4_port_chan);
1954 unsigned int cxgb4_dbfifo_count(const struct net_device *dev, int lpfifo)
1956 struct adapter *adap = netdev2adap(dev);
1957 u32 v1, v2, lp_count, hp_count;
1959 v1 = t4_read_reg(adap, SGE_DBFIFO_STATUS_A);
1960 v2 = t4_read_reg(adap, SGE_DBFIFO_STATUS2_A);
1961 if (is_t4(adap->params.chip)) {
1962 lp_count = LP_COUNT_G(v1);
1963 hp_count = HP_COUNT_G(v1);
1965 lp_count = LP_COUNT_T5_G(v1);
1966 hp_count = HP_COUNT_T5_G(v2);
1968 return lpfifo ? lp_count : hp_count;
1970 EXPORT_SYMBOL(cxgb4_dbfifo_count);
1973 * cxgb4_port_viid - get the VI id of a port
1974 * @dev: the net device for the port
1976 * Return the VI id of the given port.
1978 unsigned int cxgb4_port_viid(const struct net_device *dev)
1980 return netdev2pinfo(dev)->viid;
1982 EXPORT_SYMBOL(cxgb4_port_viid);
1985 * cxgb4_port_idx - get the index of a port
1986 * @dev: the net device for the port
1988 * Return the index of the given port.
1990 unsigned int cxgb4_port_idx(const struct net_device *dev)
1992 return netdev2pinfo(dev)->port_id;
1994 EXPORT_SYMBOL(cxgb4_port_idx);
1996 void cxgb4_get_tcp_stats(struct pci_dev *pdev, struct tp_tcp_stats *v4,
1997 struct tp_tcp_stats *v6)
1999 struct adapter *adap = pci_get_drvdata(pdev);
2001 spin_lock(&adap->stats_lock);
2002 t4_tp_get_tcp_stats(adap, v4, v6);
2003 spin_unlock(&adap->stats_lock);
2005 EXPORT_SYMBOL(cxgb4_get_tcp_stats);
2007 void cxgb4_iscsi_init(struct net_device *dev, unsigned int tag_mask,
2008 const unsigned int *pgsz_order)
2010 struct adapter *adap = netdev2adap(dev);
2012 t4_write_reg(adap, ULP_RX_ISCSI_TAGMASK_A, tag_mask);
2013 t4_write_reg(adap, ULP_RX_ISCSI_PSZ_A, HPZ0_V(pgsz_order[0]) |
2014 HPZ1_V(pgsz_order[1]) | HPZ2_V(pgsz_order[2]) |
2015 HPZ3_V(pgsz_order[3]));
2017 EXPORT_SYMBOL(cxgb4_iscsi_init);
2019 int cxgb4_flush_eq_cache(struct net_device *dev)
2021 struct adapter *adap = netdev2adap(dev);
2023 return t4_sge_ctxt_flush(adap, adap->mbox);
2025 EXPORT_SYMBOL(cxgb4_flush_eq_cache);
2027 static int read_eq_indices(struct adapter *adap, u16 qid, u16 *pidx, u16 *cidx)
2029 u32 addr = t4_read_reg(adap, SGE_DBQ_CTXT_BADDR_A) + 24 * qid + 8;
2033 spin_lock(&adap->win0_lock);
2034 ret = t4_memory_rw(adap, 0, MEM_EDC0, addr,
2035 sizeof(indices), (__be32 *)&indices,
2037 spin_unlock(&adap->win0_lock);
2039 *cidx = (be64_to_cpu(indices) >> 25) & 0xffff;
2040 *pidx = (be64_to_cpu(indices) >> 9) & 0xffff;
2045 int cxgb4_sync_txq_pidx(struct net_device *dev, u16 qid, u16 pidx,
2048 struct adapter *adap = netdev2adap(dev);
2049 u16 hw_pidx, hw_cidx;
2052 ret = read_eq_indices(adap, qid, &hw_pidx, &hw_cidx);
2056 if (pidx != hw_pidx) {
2060 if (pidx >= hw_pidx)
2061 delta = pidx - hw_pidx;
2063 delta = size - hw_pidx + pidx;
2065 if (is_t4(adap->params.chip))
2066 val = PIDX_V(delta);
2068 val = PIDX_T5_V(delta);
2070 t4_write_reg(adap, MYPF_REG(SGE_PF_KDOORBELL_A),
2076 EXPORT_SYMBOL(cxgb4_sync_txq_pidx);
2078 int cxgb4_read_tpte(struct net_device *dev, u32 stag, __be32 *tpte)
2080 struct adapter *adap;
2081 u32 offset, memtype, memaddr;
2082 u32 edc0_size, edc1_size, mc0_size, mc1_size, size;
2083 u32 edc0_end, edc1_end, mc0_end, mc1_end;
2086 adap = netdev2adap(dev);
2088 offset = ((stag >> 8) * 32) + adap->vres.stag.start;
2090 /* Figure out where the offset lands in the Memory Type/Address scheme.
2091 * This code assumes that the memory is laid out starting at offset 0
2092 * with no breaks as: EDC0, EDC1, MC0, MC1. All cards have both EDC0
2093 * and EDC1. Some cards will have neither MC0 nor MC1, most cards have
2094 * MC0, and some have both MC0 and MC1.
2096 size = t4_read_reg(adap, MA_EDRAM0_BAR_A);
2097 edc0_size = EDRAM0_SIZE_G(size) << 20;
2098 size = t4_read_reg(adap, MA_EDRAM1_BAR_A);
2099 edc1_size = EDRAM1_SIZE_G(size) << 20;
2100 size = t4_read_reg(adap, MA_EXT_MEMORY0_BAR_A);
2101 mc0_size = EXT_MEM0_SIZE_G(size) << 20;
2103 edc0_end = edc0_size;
2104 edc1_end = edc0_end + edc1_size;
2105 mc0_end = edc1_end + mc0_size;
2107 if (offset < edc0_end) {
2110 } else if (offset < edc1_end) {
2112 memaddr = offset - edc0_end;
2114 if (offset < mc0_end) {
2116 memaddr = offset - edc1_end;
2117 } else if (is_t5(adap->params.chip)) {
2118 size = t4_read_reg(adap, MA_EXT_MEMORY1_BAR_A);
2119 mc1_size = EXT_MEM1_SIZE_G(size) << 20;
2120 mc1_end = mc0_end + mc1_size;
2121 if (offset < mc1_end) {
2123 memaddr = offset - mc0_end;
2125 /* offset beyond the end of any memory */
2129 /* T4/T6 only has a single memory channel */
2134 spin_lock(&adap->win0_lock);
2135 ret = t4_memory_rw(adap, 0, memtype, memaddr, 32, tpte, T4_MEMORY_READ);
2136 spin_unlock(&adap->win0_lock);
2140 dev_err(adap->pdev_dev, "stag %#x, offset %#x out of range\n",
2144 EXPORT_SYMBOL(cxgb4_read_tpte);
2146 u64 cxgb4_read_sge_timestamp(struct net_device *dev)
2149 struct adapter *adap;
2151 adap = netdev2adap(dev);
2152 lo = t4_read_reg(adap, SGE_TIMESTAMP_LO_A);
2153 hi = TSVAL_G(t4_read_reg(adap, SGE_TIMESTAMP_HI_A));
2155 return ((u64)hi << 32) | (u64)lo;
2157 EXPORT_SYMBOL(cxgb4_read_sge_timestamp);
2159 int cxgb4_bar2_sge_qregs(struct net_device *dev,
2161 enum cxgb4_bar2_qtype qtype,
2164 unsigned int *pbar2_qid)
2166 return t4_bar2_sge_qregs(netdev2adap(dev),
2168 (qtype == CXGB4_BAR2_QTYPE_EGRESS
2169 ? T4_BAR2_QTYPE_EGRESS
2170 : T4_BAR2_QTYPE_INGRESS),
2175 EXPORT_SYMBOL(cxgb4_bar2_sge_qregs);
2177 static struct pci_driver cxgb4_driver;
2179 static void check_neigh_update(struct neighbour *neigh)
2181 const struct device *parent;
2182 const struct net_device *netdev = neigh->dev;
2184 if (netdev->priv_flags & IFF_802_1Q_VLAN)
2185 netdev = vlan_dev_real_dev(netdev);
2186 parent = netdev->dev.parent;
2187 if (parent && parent->driver == &cxgb4_driver.driver)
2188 t4_l2t_update(dev_get_drvdata(parent), neigh);
2191 static int netevent_cb(struct notifier_block *nb, unsigned long event,
2195 case NETEVENT_NEIGH_UPDATE:
2196 check_neigh_update(data);
2198 case NETEVENT_REDIRECT:
2205 static bool netevent_registered;
2206 static struct notifier_block cxgb4_netevent_nb = {
2207 .notifier_call = netevent_cb
2210 static void drain_db_fifo(struct adapter *adap, int usecs)
2212 u32 v1, v2, lp_count, hp_count;
2215 v1 = t4_read_reg(adap, SGE_DBFIFO_STATUS_A);
2216 v2 = t4_read_reg(adap, SGE_DBFIFO_STATUS2_A);
2217 if (is_t4(adap->params.chip)) {
2218 lp_count = LP_COUNT_G(v1);
2219 hp_count = HP_COUNT_G(v1);
2221 lp_count = LP_COUNT_T5_G(v1);
2222 hp_count = HP_COUNT_T5_G(v2);
2225 if (lp_count == 0 && hp_count == 0)
2227 set_current_state(TASK_UNINTERRUPTIBLE);
2228 schedule_timeout(usecs_to_jiffies(usecs));
2232 static void disable_txq_db(struct sge_txq *q)
2234 unsigned long flags;
2236 spin_lock_irqsave(&q->db_lock, flags);
2238 spin_unlock_irqrestore(&q->db_lock, flags);
2241 static void enable_txq_db(struct adapter *adap, struct sge_txq *q)
2243 spin_lock_irq(&q->db_lock);
2244 if (q->db_pidx_inc) {
2245 /* Make sure that all writes to the TX descriptors
2246 * are committed before we tell HW about them.
2249 t4_write_reg(adap, MYPF_REG(SGE_PF_KDOORBELL_A),
2250 QID_V(q->cntxt_id) | PIDX_V(q->db_pidx_inc));
2254 spin_unlock_irq(&q->db_lock);
2257 static void disable_dbs(struct adapter *adap)
2261 for_each_ethrxq(&adap->sge, i)
2262 disable_txq_db(&adap->sge.ethtxq[i].q);
2263 for_each_ofldrxq(&adap->sge, i)
2264 disable_txq_db(&adap->sge.ofldtxq[i].q);
2265 for_each_port(adap, i)
2266 disable_txq_db(&adap->sge.ctrlq[i].q);
2269 static void enable_dbs(struct adapter *adap)
2273 for_each_ethrxq(&adap->sge, i)
2274 enable_txq_db(adap, &adap->sge.ethtxq[i].q);
2275 for_each_ofldrxq(&adap->sge, i)
2276 enable_txq_db(adap, &adap->sge.ofldtxq[i].q);
2277 for_each_port(adap, i)
2278 enable_txq_db(adap, &adap->sge.ctrlq[i].q);
2281 static void notify_rdma_uld(struct adapter *adap, enum cxgb4_control cmd)
2283 if (adap->uld_handle[CXGB4_ULD_RDMA])
2284 ulds[CXGB4_ULD_RDMA].control(adap->uld_handle[CXGB4_ULD_RDMA],
2288 static void process_db_full(struct work_struct *work)
2290 struct adapter *adap;
2292 adap = container_of(work, struct adapter, db_full_task);
2294 drain_db_fifo(adap, dbfifo_drain_delay);
2296 notify_rdma_uld(adap, CXGB4_CONTROL_DB_EMPTY);
2297 if (CHELSIO_CHIP_VERSION(adap->params.chip) <= CHELSIO_T5)
2298 t4_set_reg_field(adap, SGE_INT_ENABLE3_A,
2299 DBFIFO_HP_INT_F | DBFIFO_LP_INT_F,
2300 DBFIFO_HP_INT_F | DBFIFO_LP_INT_F);
2302 t4_set_reg_field(adap, SGE_INT_ENABLE3_A,
2303 DBFIFO_LP_INT_F, DBFIFO_LP_INT_F);
2306 static void sync_txq_pidx(struct adapter *adap, struct sge_txq *q)
2308 u16 hw_pidx, hw_cidx;
2311 spin_lock_irq(&q->db_lock);
2312 ret = read_eq_indices(adap, (u16)q->cntxt_id, &hw_pidx, &hw_cidx);
2315 if (q->db_pidx != hw_pidx) {
2319 if (q->db_pidx >= hw_pidx)
2320 delta = q->db_pidx - hw_pidx;
2322 delta = q->size - hw_pidx + q->db_pidx;
2324 if (is_t4(adap->params.chip))
2325 val = PIDX_V(delta);
2327 val = PIDX_T5_V(delta);
2329 t4_write_reg(adap, MYPF_REG(SGE_PF_KDOORBELL_A),
2330 QID_V(q->cntxt_id) | val);
2335 spin_unlock_irq(&q->db_lock);
2337 CH_WARN(adap, "DB drop recovery failed.\n");
2339 static void recover_all_queues(struct adapter *adap)
2343 for_each_ethrxq(&adap->sge, i)
2344 sync_txq_pidx(adap, &adap->sge.ethtxq[i].q);
2345 for_each_ofldrxq(&adap->sge, i)
2346 sync_txq_pidx(adap, &adap->sge.ofldtxq[i].q);
2347 for_each_port(adap, i)
2348 sync_txq_pidx(adap, &adap->sge.ctrlq[i].q);
2351 static void process_db_drop(struct work_struct *work)
2353 struct adapter *adap;
2355 adap = container_of(work, struct adapter, db_drop_task);
2357 if (is_t4(adap->params.chip)) {
2358 drain_db_fifo(adap, dbfifo_drain_delay);
2359 notify_rdma_uld(adap, CXGB4_CONTROL_DB_DROP);
2360 drain_db_fifo(adap, dbfifo_drain_delay);
2361 recover_all_queues(adap);
2362 drain_db_fifo(adap, dbfifo_drain_delay);
2364 notify_rdma_uld(adap, CXGB4_CONTROL_DB_EMPTY);
2365 } else if (is_t5(adap->params.chip)) {
2366 u32 dropped_db = t4_read_reg(adap, 0x010ac);
2367 u16 qid = (dropped_db >> 15) & 0x1ffff;
2368 u16 pidx_inc = dropped_db & 0x1fff;
2370 unsigned int bar2_qid;
2373 ret = t4_bar2_sge_qregs(adap, qid, T4_BAR2_QTYPE_EGRESS,
2374 0, &bar2_qoffset, &bar2_qid);
2376 dev_err(adap->pdev_dev, "doorbell drop recovery: "
2377 "qid=%d, pidx_inc=%d\n", qid, pidx_inc);
2379 writel(PIDX_T5_V(pidx_inc) | QID_V(bar2_qid),
2380 adap->bar2 + bar2_qoffset + SGE_UDB_KDOORBELL);
2382 /* Re-enable BAR2 WC */
2383 t4_set_reg_field(adap, 0x10b0, 1<<15, 1<<15);
2386 if (CHELSIO_CHIP_VERSION(adap->params.chip) <= CHELSIO_T5)
2387 t4_set_reg_field(adap, SGE_DOORBELL_CONTROL_A, DROPPED_DB_F, 0);
2390 void t4_db_full(struct adapter *adap)
2392 if (is_t4(adap->params.chip)) {
2394 notify_rdma_uld(adap, CXGB4_CONTROL_DB_FULL);
2395 t4_set_reg_field(adap, SGE_INT_ENABLE3_A,
2396 DBFIFO_HP_INT_F | DBFIFO_LP_INT_F, 0);
2397 queue_work(adap->workq, &adap->db_full_task);
2401 void t4_db_dropped(struct adapter *adap)
2403 if (is_t4(adap->params.chip)) {
2405 notify_rdma_uld(adap, CXGB4_CONTROL_DB_FULL);
2407 queue_work(adap->workq, &adap->db_drop_task);
2410 static void uld_attach(struct adapter *adap, unsigned int uld)
2413 struct cxgb4_lld_info lli;
2416 lli.pdev = adap->pdev;
2418 lli.l2t = adap->l2t;
2419 lli.tids = &adap->tids;
2420 lli.ports = adap->port;
2421 lli.vr = &adap->vres;
2422 lli.mtus = adap->params.mtus;
2423 if (uld == CXGB4_ULD_RDMA) {
2424 lli.rxq_ids = adap->sge.rdma_rxq;
2425 lli.ciq_ids = adap->sge.rdma_ciq;
2426 lli.nrxq = adap->sge.rdmaqs;
2427 lli.nciq = adap->sge.rdmaciqs;
2428 } else if (uld == CXGB4_ULD_ISCSI) {
2429 lli.rxq_ids = adap->sge.ofld_rxq;
2430 lli.nrxq = adap->sge.ofldqsets;
2432 lli.ntxq = adap->sge.ofldqsets;
2433 lli.nchan = adap->params.nports;
2434 lli.nports = adap->params.nports;
2435 lli.wr_cred = adap->params.ofldq_wr_cred;
2436 lli.adapter_type = adap->params.chip;
2437 lli.iscsi_iolen = MAXRXDATA_G(t4_read_reg(adap, TP_PARA_REG2_A));
2438 lli.cclk_ps = 1000000000 / adap->params.vpd.cclk;
2439 lli.udb_density = 1 << adap->params.sge.eq_qpp;
2440 lli.ucq_density = 1 << adap->params.sge.iq_qpp;
2441 lli.filt_mode = adap->params.tp.vlan_pri_map;
2442 /* MODQ_REQ_MAP sets queues 0-3 to chan 0-3 */
2443 for (i = 0; i < NCHAN; i++)
2445 lli.gts_reg = adap->regs + MYPF_REG(SGE_PF_GTS_A);
2446 lli.db_reg = adap->regs + MYPF_REG(SGE_PF_KDOORBELL_A);
2447 lli.fw_vers = adap->params.fw_vers;
2448 lli.dbfifo_int_thresh = dbfifo_int_thresh;
2449 lli.sge_ingpadboundary = adap->sge.fl_align;
2450 lli.sge_egrstatuspagesize = adap->sge.stat_len;
2451 lli.sge_pktshift = adap->sge.pktshift;
2452 lli.enable_fw_ofld_conn = adap->flags & FW_OFLD_CONN;
2453 lli.max_ordird_qp = adap->params.max_ordird_qp;
2454 lli.max_ird_adapter = adap->params.max_ird_adapter;
2455 lli.ulptx_memwrite_dsgl = adap->params.ulptx_memwrite_dsgl;
2456 lli.nodeid = dev_to_node(adap->pdev_dev);
2458 handle = ulds[uld].add(&lli);
2459 if (IS_ERR(handle)) {
2460 dev_warn(adap->pdev_dev,
2461 "could not attach to the %s driver, error %ld\n",
2462 uld_str[uld], PTR_ERR(handle));
2466 adap->uld_handle[uld] = handle;
2468 if (!netevent_registered) {
2469 register_netevent_notifier(&cxgb4_netevent_nb);
2470 netevent_registered = true;
2473 if (adap->flags & FULL_INIT_DONE)
2474 ulds[uld].state_change(handle, CXGB4_STATE_UP);
2477 static void attach_ulds(struct adapter *adap)
2481 spin_lock(&adap_rcu_lock);
2482 list_add_tail_rcu(&adap->rcu_node, &adap_rcu_list);
2483 spin_unlock(&adap_rcu_lock);
2485 mutex_lock(&uld_mutex);
2486 list_add_tail(&adap->list_node, &adapter_list);
2487 for (i = 0; i < CXGB4_ULD_MAX; i++)
2489 uld_attach(adap, i);
2490 mutex_unlock(&uld_mutex);
2493 static void detach_ulds(struct adapter *adap)
2497 mutex_lock(&uld_mutex);
2498 list_del(&adap->list_node);
2499 for (i = 0; i < CXGB4_ULD_MAX; i++)
2500 if (adap->uld_handle[i]) {
2501 ulds[i].state_change(adap->uld_handle[i],
2502 CXGB4_STATE_DETACH);
2503 adap->uld_handle[i] = NULL;
2505 if (netevent_registered && list_empty(&adapter_list)) {
2506 unregister_netevent_notifier(&cxgb4_netevent_nb);
2507 netevent_registered = false;
2509 mutex_unlock(&uld_mutex);
2511 spin_lock(&adap_rcu_lock);
2512 list_del_rcu(&adap->rcu_node);
2513 spin_unlock(&adap_rcu_lock);
2516 static void notify_ulds(struct adapter *adap, enum cxgb4_state new_state)
2520 mutex_lock(&uld_mutex);
2521 for (i = 0; i < CXGB4_ULD_MAX; i++)
2522 if (adap->uld_handle[i])
2523 ulds[i].state_change(adap->uld_handle[i], new_state);
2524 mutex_unlock(&uld_mutex);
2528 * cxgb4_register_uld - register an upper-layer driver
2529 * @type: the ULD type
2530 * @p: the ULD methods
2532 * Registers an upper-layer driver with this driver and notifies the ULD
2533 * about any presently available devices that support its type. Returns
2534 * %-EBUSY if a ULD of the same type is already registered.
2536 int cxgb4_register_uld(enum cxgb4_uld type, const struct cxgb4_uld_info *p)
2539 struct adapter *adap;
2541 if (type >= CXGB4_ULD_MAX)
2543 mutex_lock(&uld_mutex);
2544 if (ulds[type].add) {
2549 list_for_each_entry(adap, &adapter_list, list_node)
2550 uld_attach(adap, type);
2551 out: mutex_unlock(&uld_mutex);
2554 EXPORT_SYMBOL(cxgb4_register_uld);
2557 * cxgb4_unregister_uld - unregister an upper-layer driver
2558 * @type: the ULD type
2560 * Unregisters an existing upper-layer driver.
2562 int cxgb4_unregister_uld(enum cxgb4_uld type)
2564 struct adapter *adap;
2566 if (type >= CXGB4_ULD_MAX)
2568 mutex_lock(&uld_mutex);
2569 list_for_each_entry(adap, &adapter_list, list_node)
2570 adap->uld_handle[type] = NULL;
2571 ulds[type].add = NULL;
2572 mutex_unlock(&uld_mutex);
2575 EXPORT_SYMBOL(cxgb4_unregister_uld);
2577 #if IS_ENABLED(CONFIG_IPV6)
2578 static int cxgb4_inet6addr_handler(struct notifier_block *this,
2579 unsigned long event, void *data)
2581 struct inet6_ifaddr *ifa = data;
2582 struct net_device *event_dev = ifa->idev->dev;
2583 const struct device *parent = NULL;
2584 #if IS_ENABLED(CONFIG_BONDING)
2585 struct adapter *adap;
2587 if (event_dev->priv_flags & IFF_802_1Q_VLAN)
2588 event_dev = vlan_dev_real_dev(event_dev);
2589 #if IS_ENABLED(CONFIG_BONDING)
2590 if (event_dev->flags & IFF_MASTER) {
2591 list_for_each_entry(adap, &adapter_list, list_node) {
2594 cxgb4_clip_get(adap->port[0],
2595 (const u32 *)ifa, 1);
2598 cxgb4_clip_release(adap->port[0],
2599 (const u32 *)ifa, 1);
2610 parent = event_dev->dev.parent;
2612 if (parent && parent->driver == &cxgb4_driver.driver) {
2615 cxgb4_clip_get(event_dev, (const u32 *)ifa, 1);
2618 cxgb4_clip_release(event_dev, (const u32 *)ifa, 1);
2627 static bool inet6addr_registered;
2628 static struct notifier_block cxgb4_inet6addr_notifier = {
2629 .notifier_call = cxgb4_inet6addr_handler
2632 static void update_clip(const struct adapter *adap)
2635 struct net_device *dev;
2640 for (i = 0; i < MAX_NPORTS; i++) {
2641 dev = adap->port[i];
2645 ret = cxgb4_update_root_dev_clip(dev);
2652 #endif /* IS_ENABLED(CONFIG_IPV6) */
2655 * cxgb_up - enable the adapter
2656 * @adap: adapter being enabled
2658 * Called when the first port is enabled, this function performs the
2659 * actions necessary to make an adapter operational, such as completing
2660 * the initialization of HW modules, and enabling interrupts.
2662 * Must be called with the rtnl lock held.
2664 static int cxgb_up(struct adapter *adap)
2668 err = setup_sge_queues(adap);
2671 err = setup_rss(adap);
2675 if (adap->flags & USING_MSIX) {
2676 name_msix_vecs(adap);
2677 err = request_irq(adap->msix_info[0].vec, t4_nondata_intr, 0,
2678 adap->msix_info[0].desc, adap);
2682 err = request_msix_queue_irqs(adap);
2684 free_irq(adap->msix_info[0].vec, adap);
2688 err = request_irq(adap->pdev->irq, t4_intr_handler(adap),
2689 (adap->flags & USING_MSI) ? 0 : IRQF_SHARED,
2690 adap->port[0]->name, adap);
2696 t4_intr_enable(adap);
2697 adap->flags |= FULL_INIT_DONE;
2698 notify_ulds(adap, CXGB4_STATE_UP);
2699 #if IS_ENABLED(CONFIG_IPV6)
2705 dev_err(adap->pdev_dev, "request_irq failed, err %d\n", err);
2707 t4_free_sge_resources(adap);
2711 static void cxgb_down(struct adapter *adapter)
2713 cancel_work_sync(&adapter->tid_release_task);
2714 cancel_work_sync(&adapter->db_full_task);
2715 cancel_work_sync(&adapter->db_drop_task);
2716 adapter->tid_release_task_busy = false;
2717 adapter->tid_release_head = NULL;
2719 t4_sge_stop(adapter);
2720 t4_free_sge_resources(adapter);
2721 adapter->flags &= ~FULL_INIT_DONE;
2725 * net_device operations
2727 static int cxgb_open(struct net_device *dev)
2730 struct port_info *pi = netdev_priv(dev);
2731 struct adapter *adapter = pi->adapter;
2733 netif_carrier_off(dev);
2735 if (!(adapter->flags & FULL_INIT_DONE)) {
2736 err = cxgb_up(adapter);
2741 err = link_start(dev);
2743 netif_tx_start_all_queues(dev);
2747 static int cxgb_close(struct net_device *dev)
2749 struct port_info *pi = netdev_priv(dev);
2750 struct adapter *adapter = pi->adapter;
2752 netif_tx_stop_all_queues(dev);
2753 netif_carrier_off(dev);
2754 return t4_enable_vi(adapter, adapter->pf, pi->viid, false, false);
2757 /* Return an error number if the indicated filter isn't writable ...
2759 static int writable_filter(struct filter_entry *f)
2769 /* Delete the filter at the specified index (if valid). The checks for all
2770 * the common problems with doing this like the filter being locked, currently
2771 * pending in another operation, etc.
2773 static int delete_filter(struct adapter *adapter, unsigned int fidx)
2775 struct filter_entry *f;
2778 if (fidx >= adapter->tids.nftids + adapter->tids.nsftids)
2781 f = &adapter->tids.ftid_tab[fidx];
2782 ret = writable_filter(f);
2786 return del_filter_wr(adapter, fidx);
2791 int cxgb4_create_server_filter(const struct net_device *dev, unsigned int stid,
2792 __be32 sip, __be16 sport, __be16 vlan,
2793 unsigned int queue, unsigned char port, unsigned char mask)
2796 struct filter_entry *f;
2797 struct adapter *adap;
2801 adap = netdev2adap(dev);
2803 /* Adjust stid to correct filter index */
2804 stid -= adap->tids.sftid_base;
2805 stid += adap->tids.nftids;
2807 /* Check to make sure the filter requested is writable ...
2809 f = &adap->tids.ftid_tab[stid];
2810 ret = writable_filter(f);
2814 /* Clear out any old resources being used by the filter before
2815 * we start constructing the new filter.
2818 clear_filter(adap, f);
2820 /* Clear out filter specifications */
2821 memset(&f->fs, 0, sizeof(struct ch_filter_specification));
2822 f->fs.val.lport = cpu_to_be16(sport);
2823 f->fs.mask.lport = ~0;
2825 if ((val[0] | val[1] | val[2] | val[3]) != 0) {
2826 for (i = 0; i < 4; i++) {
2827 f->fs.val.lip[i] = val[i];
2828 f->fs.mask.lip[i] = ~0;
2830 if (adap->params.tp.vlan_pri_map & PORT_F) {
2831 f->fs.val.iport = port;
2832 f->fs.mask.iport = mask;
2836 if (adap->params.tp.vlan_pri_map & PROTOCOL_F) {
2837 f->fs.val.proto = IPPROTO_TCP;
2838 f->fs.mask.proto = ~0;
2843 /* Mark filter as locked */
2847 ret = set_filter_wr(adap, stid);
2849 clear_filter(adap, f);
2855 EXPORT_SYMBOL(cxgb4_create_server_filter);
2857 int cxgb4_remove_server_filter(const struct net_device *dev, unsigned int stid,
2858 unsigned int queue, bool ipv6)
2861 struct filter_entry *f;
2862 struct adapter *adap;
2864 adap = netdev2adap(dev);
2866 /* Adjust stid to correct filter index */
2867 stid -= adap->tids.sftid_base;
2868 stid += adap->tids.nftids;
2870 f = &adap->tids.ftid_tab[stid];
2871 /* Unlock the filter */
2874 ret = delete_filter(adap, stid);
2880 EXPORT_SYMBOL(cxgb4_remove_server_filter);
2882 static struct rtnl_link_stats64 *cxgb_get_stats(struct net_device *dev,
2883 struct rtnl_link_stats64 *ns)
2885 struct port_stats stats;
2886 struct port_info *p = netdev_priv(dev);
2887 struct adapter *adapter = p->adapter;
2889 /* Block retrieving statistics during EEH error
2890 * recovery. Otherwise, the recovery might fail
2891 * and the PCI device will be removed permanently
2893 spin_lock(&adapter->stats_lock);
2894 if (!netif_device_present(dev)) {
2895 spin_unlock(&adapter->stats_lock);
2898 t4_get_port_stats_offset(adapter, p->tx_chan, &stats,
2900 spin_unlock(&adapter->stats_lock);
2902 ns->tx_bytes = stats.tx_octets;
2903 ns->tx_packets = stats.tx_frames;
2904 ns->rx_bytes = stats.rx_octets;
2905 ns->rx_packets = stats.rx_frames;
2906 ns->multicast = stats.rx_mcast_frames;
2908 /* detailed rx_errors */
2909 ns->rx_length_errors = stats.rx_jabber + stats.rx_too_long +
2911 ns->rx_over_errors = 0;
2912 ns->rx_crc_errors = stats.rx_fcs_err;
2913 ns->rx_frame_errors = stats.rx_symbol_err;
2914 ns->rx_fifo_errors = stats.rx_ovflow0 + stats.rx_ovflow1 +
2915 stats.rx_ovflow2 + stats.rx_ovflow3 +
2916 stats.rx_trunc0 + stats.rx_trunc1 +
2917 stats.rx_trunc2 + stats.rx_trunc3;
2918 ns->rx_missed_errors = 0;
2920 /* detailed tx_errors */
2921 ns->tx_aborted_errors = 0;
2922 ns->tx_carrier_errors = 0;
2923 ns->tx_fifo_errors = 0;
2924 ns->tx_heartbeat_errors = 0;
2925 ns->tx_window_errors = 0;
2927 ns->tx_errors = stats.tx_error_frames;
2928 ns->rx_errors = stats.rx_symbol_err + stats.rx_fcs_err +
2929 ns->rx_length_errors + stats.rx_len_err + ns->rx_fifo_errors;
2933 static int cxgb_ioctl(struct net_device *dev, struct ifreq *req, int cmd)
2936 int ret = 0, prtad, devad;
2937 struct port_info *pi = netdev_priv(dev);
2938 struct mii_ioctl_data *data = (struct mii_ioctl_data *)&req->ifr_data;
2942 if (pi->mdio_addr < 0)
2944 data->phy_id = pi->mdio_addr;
2948 if (mdio_phy_id_is_c45(data->phy_id)) {
2949 prtad = mdio_phy_id_prtad(data->phy_id);
2950 devad = mdio_phy_id_devad(data->phy_id);
2951 } else if (data->phy_id < 32) {
2952 prtad = data->phy_id;
2954 data->reg_num &= 0x1f;
2958 mbox = pi->adapter->pf;
2959 if (cmd == SIOCGMIIREG)
2960 ret = t4_mdio_rd(pi->adapter, mbox, prtad, devad,
2961 data->reg_num, &data->val_out);
2963 ret = t4_mdio_wr(pi->adapter, mbox, prtad, devad,
2964 data->reg_num, data->val_in);
2967 return copy_to_user(req->ifr_data, &pi->tstamp_config,
2968 sizeof(pi->tstamp_config)) ?
2971 if (copy_from_user(&pi->tstamp_config, req->ifr_data,
2972 sizeof(pi->tstamp_config)))
2975 switch (pi->tstamp_config.rx_filter) {
2976 case HWTSTAMP_FILTER_NONE:
2977 pi->rxtstamp = false;
2979 case HWTSTAMP_FILTER_ALL:
2980 pi->rxtstamp = true;
2983 pi->tstamp_config.rx_filter = HWTSTAMP_FILTER_NONE;
2987 return copy_to_user(req->ifr_data, &pi->tstamp_config,
2988 sizeof(pi->tstamp_config)) ?
2996 static void cxgb_set_rxmode(struct net_device *dev)
2998 /* unfortunately we can't return errors to the stack */
2999 set_rxmode(dev, -1, false);
3002 static int cxgb_change_mtu(struct net_device *dev, int new_mtu)
3005 struct port_info *pi = netdev_priv(dev);
3007 if (new_mtu < 81 || new_mtu > MAX_MTU) /* accommodate SACK */
3009 ret = t4_set_rxmode(pi->adapter, pi->adapter->pf, pi->viid, new_mtu, -1,
3016 static int cxgb_set_mac_addr(struct net_device *dev, void *p)
3019 struct sockaddr *addr = p;
3020 struct port_info *pi = netdev_priv(dev);
3022 if (!is_valid_ether_addr(addr->sa_data))
3023 return -EADDRNOTAVAIL;
3025 ret = t4_change_mac(pi->adapter, pi->adapter->pf, pi->viid,
3026 pi->xact_addr_filt, addr->sa_data, true, true);
3030 memcpy(dev->dev_addr, addr->sa_data, dev->addr_len);
3031 pi->xact_addr_filt = ret;
3035 #ifdef CONFIG_NET_POLL_CONTROLLER
3036 static void cxgb_netpoll(struct net_device *dev)
3038 struct port_info *pi = netdev_priv(dev);
3039 struct adapter *adap = pi->adapter;
3041 if (adap->flags & USING_MSIX) {
3043 struct sge_eth_rxq *rx = &adap->sge.ethrxq[pi->first_qset];
3045 for (i = pi->nqsets; i; i--, rx++)
3046 t4_sge_intr_msix(0, &rx->rspq);
3048 t4_intr_handler(adap)(0, adap);
3052 static const struct net_device_ops cxgb4_netdev_ops = {
3053 .ndo_open = cxgb_open,
3054 .ndo_stop = cxgb_close,
3055 .ndo_start_xmit = t4_eth_xmit,
3056 .ndo_select_queue = cxgb_select_queue,
3057 .ndo_get_stats64 = cxgb_get_stats,
3058 .ndo_set_rx_mode = cxgb_set_rxmode,
3059 .ndo_set_mac_address = cxgb_set_mac_addr,
3060 .ndo_set_features = cxgb_set_features,
3061 .ndo_validate_addr = eth_validate_addr,
3062 .ndo_do_ioctl = cxgb_ioctl,
3063 .ndo_change_mtu = cxgb_change_mtu,
3064 #ifdef CONFIG_NET_POLL_CONTROLLER
3065 .ndo_poll_controller = cxgb_netpoll,
3067 #ifdef CONFIG_CHELSIO_T4_FCOE
3068 .ndo_fcoe_enable = cxgb_fcoe_enable,
3069 .ndo_fcoe_disable = cxgb_fcoe_disable,
3070 #endif /* CONFIG_CHELSIO_T4_FCOE */
3071 #ifdef CONFIG_NET_RX_BUSY_POLL
3072 .ndo_busy_poll = cxgb_busy_poll,
3077 void t4_fatal_err(struct adapter *adap)
3079 t4_set_reg_field(adap, SGE_CONTROL_A, GLOBALENABLE_F, 0);
3080 t4_intr_disable(adap);
3081 dev_alert(adap->pdev_dev, "encountered fatal error, adapter stopped\n");
3084 static void setup_memwin(struct adapter *adap)
3086 u32 nic_win_base = t4_get_util_window(adap);
3088 t4_setup_memwin(adap, nic_win_base, MEMWIN_NIC);
3091 static void setup_memwin_rdma(struct adapter *adap)
3093 if (adap->vres.ocq.size) {
3097 start = t4_read_pcie_cfg4(adap, PCI_BASE_ADDRESS_2);
3098 start &= PCI_BASE_ADDRESS_MEM_MASK;
3099 start += OCQ_WIN_OFFSET(adap->pdev, &adap->vres);
3100 sz_kb = roundup_pow_of_two(adap->vres.ocq.size) >> 10;
3102 PCIE_MEM_ACCESS_REG(PCIE_MEM_ACCESS_BASE_WIN_A, 3),
3103 start | BIR_V(1) | WINDOW_V(ilog2(sz_kb)));
3105 PCIE_MEM_ACCESS_REG(PCIE_MEM_ACCESS_OFFSET_A, 3),
3106 adap->vres.ocq.start);
3108 PCIE_MEM_ACCESS_REG(PCIE_MEM_ACCESS_OFFSET_A, 3));
3112 static int adap_init1(struct adapter *adap, struct fw_caps_config_cmd *c)
3117 /* get device capabilities */
3118 memset(c, 0, sizeof(*c));
3119 c->op_to_write = htonl(FW_CMD_OP_V(FW_CAPS_CONFIG_CMD) |
3120 FW_CMD_REQUEST_F | FW_CMD_READ_F);
3121 c->cfvalid_to_len16 = htonl(FW_LEN16(*c));
3122 ret = t4_wr_mbox(adap, adap->mbox, c, sizeof(*c), c);
3126 /* select capabilities we'll be using */
3127 if (c->niccaps & htons(FW_CAPS_CONFIG_NIC_VM)) {
3129 c->niccaps ^= htons(FW_CAPS_CONFIG_NIC_VM);
3131 c->niccaps = htons(FW_CAPS_CONFIG_NIC_VM);
3132 } else if (vf_acls) {
3133 dev_err(adap->pdev_dev, "virtualization ACLs not supported");
3136 c->op_to_write = htonl(FW_CMD_OP_V(FW_CAPS_CONFIG_CMD) |
3137 FW_CMD_REQUEST_F | FW_CMD_WRITE_F);
3138 ret = t4_wr_mbox(adap, adap->mbox, c, sizeof(*c), NULL);
3142 ret = t4_config_glbl_rss(adap, adap->pf,
3143 FW_RSS_GLB_CONFIG_CMD_MODE_BASICVIRTUAL,
3144 FW_RSS_GLB_CONFIG_CMD_TNLMAPEN_F |
3145 FW_RSS_GLB_CONFIG_CMD_TNLALLLKP_F);
3149 ret = t4_cfg_pfvf(adap, adap->mbox, adap->pf, 0, adap->sge.egr_sz, 64,
3150 MAX_INGQ, 0, 0, 4, 0xf, 0xf, 16, FW_CMD_CAP_PF,
3157 /* tweak some settings */
3158 t4_write_reg(adap, TP_SHIFT_CNT_A, 0x64f8849);
3159 t4_write_reg(adap, ULP_RX_TDDP_PSZ_A, HPZ0_V(PAGE_SHIFT - 12));
3160 t4_write_reg(adap, TP_PIO_ADDR_A, TP_INGRESS_CONFIG_A);
3161 v = t4_read_reg(adap, TP_PIO_DATA_A);
3162 t4_write_reg(adap, TP_PIO_DATA_A, v & ~CSUM_HAS_PSEUDO_HDR_F);
3164 /* first 4 Tx modulation queues point to consecutive Tx channels */
3165 adap->params.tp.tx_modq_map = 0xE4;
3166 t4_write_reg(adap, TP_TX_MOD_QUEUE_REQ_MAP_A,
3167 TX_MOD_QUEUE_REQ_MAP_V(adap->params.tp.tx_modq_map));
3169 /* associate each Tx modulation queue with consecutive Tx channels */
3171 t4_write_indirect(adap, TP_PIO_ADDR_A, TP_PIO_DATA_A,
3172 &v, 1, TP_TX_SCHED_HDR_A);
3173 t4_write_indirect(adap, TP_PIO_ADDR_A, TP_PIO_DATA_A,
3174 &v, 1, TP_TX_SCHED_FIFO_A);
3175 t4_write_indirect(adap, TP_PIO_ADDR_A, TP_PIO_DATA_A,
3176 &v, 1, TP_TX_SCHED_PCMD_A);
3178 #define T4_TX_MODQ_10G_WEIGHT_DEFAULT 16 /* in KB units */
3179 if (is_offload(adap)) {
3180 t4_write_reg(adap, TP_TX_MOD_QUEUE_WEIGHT0_A,
3181 TX_MODQ_WEIGHT0_V(T4_TX_MODQ_10G_WEIGHT_DEFAULT) |
3182 TX_MODQ_WEIGHT1_V(T4_TX_MODQ_10G_WEIGHT_DEFAULT) |
3183 TX_MODQ_WEIGHT2_V(T4_TX_MODQ_10G_WEIGHT_DEFAULT) |
3184 TX_MODQ_WEIGHT3_V(T4_TX_MODQ_10G_WEIGHT_DEFAULT));
3185 t4_write_reg(adap, TP_TX_MOD_CHANNEL_WEIGHT_A,
3186 TX_MODQ_WEIGHT0_V(T4_TX_MODQ_10G_WEIGHT_DEFAULT) |
3187 TX_MODQ_WEIGHT1_V(T4_TX_MODQ_10G_WEIGHT_DEFAULT) |
3188 TX_MODQ_WEIGHT2_V(T4_TX_MODQ_10G_WEIGHT_DEFAULT) |
3189 TX_MODQ_WEIGHT3_V(T4_TX_MODQ_10G_WEIGHT_DEFAULT));
3192 /* get basic stuff going */
3193 return t4_early_init(adap, adap->pf);
3197 * Max # of ATIDs. The absolute HW max is 16K but we keep it lower.
3199 #define MAX_ATIDS 8192U
3202 * Phase 0 of initialization: contact FW, obtain config, perform basic init.
3204 * If the firmware we're dealing with has Configuration File support, then
3205 * we use that to perform all configuration
3209 * Tweak configuration based on module parameters, etc. Most of these have
3210 * defaults assigned to them by Firmware Configuration Files (if we're using
3211 * them) but need to be explicitly set if we're using hard-coded
3212 * initialization. But even in the case of using Firmware Configuration
3213 * Files, we'd like to expose the ability to change these via module
3214 * parameters so these are essentially common tweaks/settings for
3215 * Configuration Files and hard-coded initialization ...
3217 static int adap_init0_tweaks(struct adapter *adapter)
3220 * Fix up various Host-Dependent Parameters like Page Size, Cache
3221 * Line Size, etc. The firmware default is for a 4KB Page Size and
3222 * 64B Cache Line Size ...
3224 t4_fixup_host_params(adapter, PAGE_SIZE, L1_CACHE_BYTES);
3227 * Process module parameters which affect early initialization.
3229 if (rx_dma_offset != 2 && rx_dma_offset != 0) {
3230 dev_err(&adapter->pdev->dev,
3231 "Ignoring illegal rx_dma_offset=%d, using 2\n",
3235 t4_set_reg_field(adapter, SGE_CONTROL_A,
3236 PKTSHIFT_V(PKTSHIFT_M),
3237 PKTSHIFT_V(rx_dma_offset));
3240 * Don't include the "IP Pseudo Header" in CPL_RX_PKT checksums: Linux
3241 * adds the pseudo header itself.
3243 t4_tp_wr_bits_indirect(adapter, TP_INGRESS_CONFIG_A,
3244 CSUM_HAS_PSEUDO_HDR_F, 0);
3249 /* 10Gb/s-BT PHY Support. chip-external 10Gb/s-BT PHYs are complex chips
3250 * unto themselves and they contain their own firmware to perform their
3253 static int phy_aq1202_version(const u8 *phy_fw_data,
3258 /* At offset 0x8 you're looking for the primary image's
3259 * starting offset which is 3 Bytes wide
3261 * At offset 0xa of the primary image, you look for the offset
3262 * of the DRAM segment which is 3 Bytes wide.
3264 * The FW version is at offset 0x27e of the DRAM and is 2 Bytes
3267 #define be16(__p) (((__p)[0] << 8) | (__p)[1])
3268 #define le16(__p) ((__p)[0] | ((__p)[1] << 8))
3269 #define le24(__p) (le16(__p) | ((__p)[2] << 16))
3271 offset = le24(phy_fw_data + 0x8) << 12;
3272 offset = le24(phy_fw_data + offset + 0xa);
3273 return be16(phy_fw_data + offset + 0x27e);
3280 static struct info_10gbt_phy_fw {
3281 unsigned int phy_fw_id; /* PCI Device ID */
3282 char *phy_fw_file; /* /lib/firmware/ PHY Firmware file */
3283 int (*phy_fw_version)(const u8 *phy_fw_data, size_t phy_fw_size);
3284 int phy_flash; /* Has FLASH for PHY Firmware */
3285 } phy_info_array[] = {
3287 PHY_AQ1202_DEVICEID,
3288 PHY_AQ1202_FIRMWARE,
3293 PHY_BCM84834_DEVICEID,
3294 PHY_BCM84834_FIRMWARE,
3301 static struct info_10gbt_phy_fw *find_phy_info(int devid)
3305 for (i = 0; i < ARRAY_SIZE(phy_info_array); i++) {
3306 if (phy_info_array[i].phy_fw_id == devid)
3307 return &phy_info_array[i];
3312 /* Handle updating of chip-external 10Gb/s-BT PHY firmware. This needs to
3313 * happen after the FW_RESET_CMD but before the FW_INITIALIZE_CMD. On error
3314 * we return a negative error number. If we transfer new firmware we return 1
3315 * (from t4_load_phy_fw()). If we don't do anything we return 0.
3317 static int adap_init0_phy(struct adapter *adap)
3319 const struct firmware *phyf;
3321 struct info_10gbt_phy_fw *phy_info;
3323 /* Use the device ID to determine which PHY file to flash.
3325 phy_info = find_phy_info(adap->pdev->device);
3327 dev_warn(adap->pdev_dev,
3328 "No PHY Firmware file found for this PHY\n");
3332 /* If we have a T4 PHY firmware file under /lib/firmware/cxgb4/, then
3333 * use that. The adapter firmware provides us with a memory buffer
3334 * where we can load a PHY firmware file from the host if we want to
3335 * override the PHY firmware File in flash.
3337 ret = request_firmware_direct(&phyf, phy_info->phy_fw_file,
3340 /* For adapters without FLASH attached to PHY for their
3341 * firmware, it's obviously a fatal error if we can't get the
3342 * firmware to the adapter. For adapters with PHY firmware
3343 * FLASH storage, it's worth a warning if we can't find the
3344 * PHY Firmware but we'll neuter the error ...
3346 dev_err(adap->pdev_dev, "unable to find PHY Firmware image "
3347 "/lib/firmware/%s, error %d\n",
3348 phy_info->phy_fw_file, -ret);
3349 if (phy_info->phy_flash) {
3350 int cur_phy_fw_ver = 0;
3352 t4_phy_fw_ver(adap, &cur_phy_fw_ver);
3353 dev_warn(adap->pdev_dev, "continuing with, on-adapter "
3354 "FLASH copy, version %#x\n", cur_phy_fw_ver);
3361 /* Load PHY Firmware onto adapter.
3363 ret = t4_load_phy_fw(adap, MEMWIN_NIC, &adap->win0_lock,
3364 phy_info->phy_fw_version,
3365 (u8 *)phyf->data, phyf->size);
3367 dev_err(adap->pdev_dev, "PHY Firmware transfer error %d\n",
3370 int new_phy_fw_ver = 0;
3372 if (phy_info->phy_fw_version)
3373 new_phy_fw_ver = phy_info->phy_fw_version(phyf->data,
3375 dev_info(adap->pdev_dev, "Successfully transferred PHY "
3376 "Firmware /lib/firmware/%s, version %#x\n",
3377 phy_info->phy_fw_file, new_phy_fw_ver);
3380 release_firmware(phyf);
3386 * Attempt to initialize the adapter via a Firmware Configuration File.
3388 static int adap_init0_config(struct adapter *adapter, int reset)
3390 struct fw_caps_config_cmd caps_cmd;
3391 const struct firmware *cf;
3392 unsigned long mtype = 0, maddr = 0;
3393 u32 finiver, finicsum, cfcsum;
3395 int config_issued = 0;
3396 char *fw_config_file, fw_config_file_path[256];
3397 char *config_name = NULL;
3400 * Reset device if necessary.
3403 ret = t4_fw_reset(adapter, adapter->mbox,
3404 PIORSTMODE_F | PIORST_F);
3409 /* If this is a 10Gb/s-BT adapter make sure the chip-external
3410 * 10Gb/s-BT PHYs have up-to-date firmware. Note that this step needs
3411 * to be performed after any global adapter RESET above since some
3412 * PHYs only have local RAM copies of the PHY firmware.
3414 if (is_10gbt_device(adapter->pdev->device)) {
3415 ret = adap_init0_phy(adapter);
3420 * If we have a T4 configuration file under /lib/firmware/cxgb4/,
3421 * then use that. Otherwise, use the configuration file stored
3422 * in the adapter flash ...
3424 switch (CHELSIO_CHIP_VERSION(adapter->params.chip)) {
3426 fw_config_file = FW4_CFNAME;
3429 fw_config_file = FW5_CFNAME;
3432 fw_config_file = FW6_CFNAME;
3435 dev_err(adapter->pdev_dev, "Device %d is not supported\n",
3436 adapter->pdev->device);
3441 ret = request_firmware(&cf, fw_config_file, adapter->pdev_dev);
3443 config_name = "On FLASH";
3444 mtype = FW_MEMTYPE_CF_FLASH;
3445 maddr = t4_flash_cfg_addr(adapter);
3447 u32 params[7], val[7];
3449 sprintf(fw_config_file_path,
3450 "/lib/firmware/%s", fw_config_file);
3451 config_name = fw_config_file_path;
3453 if (cf->size >= FLASH_CFG_MAX_SIZE)
3456 params[0] = (FW_PARAMS_MNEM_V(FW_PARAMS_MNEM_DEV) |
3457 FW_PARAMS_PARAM_X_V(FW_PARAMS_PARAM_DEV_CF));
3458 ret = t4_query_params(adapter, adapter->mbox,
3459 adapter->pf, 0, 1, params, val);
3462 * For t4_memory_rw() below addresses and
3463 * sizes have to be in terms of multiples of 4
3464 * bytes. So, if the Configuration File isn't
3465 * a multiple of 4 bytes in length we'll have
3466 * to write that out separately since we can't
3467 * guarantee that the bytes following the
3468 * residual byte in the buffer returned by
3469 * request_firmware() are zeroed out ...
3471 size_t resid = cf->size & 0x3;
3472 size_t size = cf->size & ~0x3;
3473 __be32 *data = (__be32 *)cf->data;
3475 mtype = FW_PARAMS_PARAM_Y_G(val[0]);
3476 maddr = FW_PARAMS_PARAM_Z_G(val[0]) << 16;
3478 spin_lock(&adapter->win0_lock);
3479 ret = t4_memory_rw(adapter, 0, mtype, maddr,
3480 size, data, T4_MEMORY_WRITE);
3481 if (ret == 0 && resid != 0) {
3488 last.word = data[size >> 2];
3489 for (i = resid; i < 4; i++)
3491 ret = t4_memory_rw(adapter, 0, mtype,
3496 spin_unlock(&adapter->win0_lock);
3500 release_firmware(cf);
3506 * Issue a Capability Configuration command to the firmware to get it
3507 * to parse the Configuration File. We don't use t4_fw_config_file()
3508 * because we want the ability to modify various features after we've
3509 * processed the configuration file ...
3511 memset(&caps_cmd, 0, sizeof(caps_cmd));
3512 caps_cmd.op_to_write =
3513 htonl(FW_CMD_OP_V(FW_CAPS_CONFIG_CMD) |
3516 caps_cmd.cfvalid_to_len16 =
3517 htonl(FW_CAPS_CONFIG_CMD_CFVALID_F |
3518 FW_CAPS_CONFIG_CMD_MEMTYPE_CF_V(mtype) |
3519 FW_CAPS_CONFIG_CMD_MEMADDR64K_CF_V(maddr >> 16) |
3520 FW_LEN16(caps_cmd));
3521 ret = t4_wr_mbox(adapter, adapter->mbox, &caps_cmd, sizeof(caps_cmd),
3524 /* If the CAPS_CONFIG failed with an ENOENT (for a Firmware
3525 * Configuration File in FLASH), our last gasp effort is to use the
3526 * Firmware Configuration File which is embedded in the firmware. A
3527 * very few early versions of the firmware didn't have one embedded
3528 * but we can ignore those.
3530 if (ret == -ENOENT) {
3531 memset(&caps_cmd, 0, sizeof(caps_cmd));
3532 caps_cmd.op_to_write =
3533 htonl(FW_CMD_OP_V(FW_CAPS_CONFIG_CMD) |
3536 caps_cmd.cfvalid_to_len16 = htonl(FW_LEN16(caps_cmd));
3537 ret = t4_wr_mbox(adapter, adapter->mbox, &caps_cmd,
3538 sizeof(caps_cmd), &caps_cmd);
3539 config_name = "Firmware Default";
3546 finiver = ntohl(caps_cmd.finiver);
3547 finicsum = ntohl(caps_cmd.finicsum);
3548 cfcsum = ntohl(caps_cmd.cfcsum);
3549 if (finicsum != cfcsum)
3550 dev_warn(adapter->pdev_dev, "Configuration File checksum "\
3551 "mismatch: [fini] csum=%#x, computed csum=%#x\n",
3555 * And now tell the firmware to use the configuration we just loaded.
3557 caps_cmd.op_to_write =
3558 htonl(FW_CMD_OP_V(FW_CAPS_CONFIG_CMD) |
3561 caps_cmd.cfvalid_to_len16 = htonl(FW_LEN16(caps_cmd));
3562 ret = t4_wr_mbox(adapter, adapter->mbox, &caps_cmd, sizeof(caps_cmd),
3568 * Tweak configuration based on system architecture, module
3571 ret = adap_init0_tweaks(adapter);
3576 * And finally tell the firmware to initialize itself using the
3577 * parameters from the Configuration File.
3579 ret = t4_fw_initialize(adapter, adapter->mbox);
3583 /* Emit Firmware Configuration File information and return
3586 dev_info(adapter->pdev_dev, "Successfully configured using Firmware "\
3587 "Configuration File \"%s\", version %#x, computed checksum %#x\n",
3588 config_name, finiver, cfcsum);
3592 * Something bad happened. Return the error ... (If the "error"
3593 * is that there's no Configuration File on the adapter we don't
3594 * want to issue a warning since this is fairly common.)
3597 if (config_issued && ret != -ENOENT)
3598 dev_warn(adapter->pdev_dev, "\"%s\" configuration file error %d\n",
3603 static struct fw_info fw_info_array[] = {
3606 .fs_name = FW4_CFNAME,
3607 .fw_mod_name = FW4_FNAME,
3609 .chip = FW_HDR_CHIP_T4,
3610 .fw_ver = __cpu_to_be32(FW_VERSION(T4)),
3611 .intfver_nic = FW_INTFVER(T4, NIC),
3612 .intfver_vnic = FW_INTFVER(T4, VNIC),
3613 .intfver_ri = FW_INTFVER(T4, RI),
3614 .intfver_iscsi = FW_INTFVER(T4, ISCSI),
3615 .intfver_fcoe = FW_INTFVER(T4, FCOE),
3619 .fs_name = FW5_CFNAME,
3620 .fw_mod_name = FW5_FNAME,
3622 .chip = FW_HDR_CHIP_T5,
3623 .fw_ver = __cpu_to_be32(FW_VERSION(T5)),
3624 .intfver_nic = FW_INTFVER(T5, NIC),
3625 .intfver_vnic = FW_INTFVER(T5, VNIC),
3626 .intfver_ri = FW_INTFVER(T5, RI),
3627 .intfver_iscsi = FW_INTFVER(T5, ISCSI),
3628 .intfver_fcoe = FW_INTFVER(T5, FCOE),
3632 .fs_name = FW6_CFNAME,
3633 .fw_mod_name = FW6_FNAME,
3635 .chip = FW_HDR_CHIP_T6,
3636 .fw_ver = __cpu_to_be32(FW_VERSION(T6)),
3637 .intfver_nic = FW_INTFVER(T6, NIC),
3638 .intfver_vnic = FW_INTFVER(T6, VNIC),
3639 .intfver_ofld = FW_INTFVER(T6, OFLD),
3640 .intfver_ri = FW_INTFVER(T6, RI),
3641 .intfver_iscsipdu = FW_INTFVER(T6, ISCSIPDU),
3642 .intfver_iscsi = FW_INTFVER(T6, ISCSI),
3643 .intfver_fcoepdu = FW_INTFVER(T6, FCOEPDU),
3644 .intfver_fcoe = FW_INTFVER(T6, FCOE),
3650 static struct fw_info *find_fw_info(int chip)
3654 for (i = 0; i < ARRAY_SIZE(fw_info_array); i++) {
3655 if (fw_info_array[i].chip == chip)
3656 return &fw_info_array[i];
3662 * Phase 0 of initialization: contact FW, obtain config, perform basic init.
3664 static int adap_init0(struct adapter *adap)
3668 enum dev_state state;
3669 u32 params[7], val[7];
3670 struct fw_caps_config_cmd caps_cmd;
3673 /* Grab Firmware Device Log parameters as early as possible so we have
3674 * access to it for debugging, etc.
3676 ret = t4_init_devlog_params(adap);
3680 /* Contact FW, advertising Master capability */
3681 ret = t4_fw_hello(adap, adap->mbox, adap->mbox, MASTER_MAY, &state);
3683 dev_err(adap->pdev_dev, "could not connect to FW, error %d\n",
3687 if (ret == adap->mbox)
3688 adap->flags |= MASTER_PF;
3691 * If we're the Master PF Driver and the device is uninitialized,
3692 * then let's consider upgrading the firmware ... (We always want
3693 * to check the firmware version number in order to A. get it for
3694 * later reporting and B. to warn if the currently loaded firmware
3695 * is excessively mismatched relative to the driver.)
3697 t4_get_fw_version(adap, &adap->params.fw_vers);
3698 t4_get_tp_version(adap, &adap->params.tp_vers);
3699 ret = t4_check_fw_version(adap);
3700 /* If firmware is too old (not supported by driver) force an update. */
3702 state = DEV_STATE_UNINIT;
3703 if ((adap->flags & MASTER_PF) && state != DEV_STATE_INIT) {
3704 struct fw_info *fw_info;
3705 struct fw_hdr *card_fw;
3706 const struct firmware *fw;
3707 const u8 *fw_data = NULL;
3708 unsigned int fw_size = 0;
3710 /* This is the firmware whose headers the driver was compiled
3713 fw_info = find_fw_info(CHELSIO_CHIP_VERSION(adap->params.chip));
3714 if (fw_info == NULL) {
3715 dev_err(adap->pdev_dev,
3716 "unable to get firmware info for chip %d.\n",
3717 CHELSIO_CHIP_VERSION(adap->params.chip));
3721 /* allocate memory to read the header of the firmware on the
3724 card_fw = t4_alloc_mem(sizeof(*card_fw));
3726 /* Get FW from from /lib/firmware/ */
3727 ret = request_firmware(&fw, fw_info->fw_mod_name,
3730 dev_err(adap->pdev_dev,
3731 "unable to load firmware image %s, error %d\n",
3732 fw_info->fw_mod_name, ret);
3738 /* upgrade FW logic */
3739 ret = t4_prep_fw(adap, fw_info, fw_data, fw_size, card_fw,
3743 release_firmware(fw);
3744 t4_free_mem(card_fw);
3751 * Grab VPD parameters. This should be done after we establish a
3752 * connection to the firmware since some of the VPD parameters
3753 * (notably the Core Clock frequency) are retrieved via requests to
3754 * the firmware. On the other hand, we need these fairly early on
3755 * so we do this right after getting ahold of the firmware.
3757 ret = t4_get_vpd_params(adap, &adap->params.vpd);
3762 * Find out what ports are available to us. Note that we need to do
3763 * this before calling adap_init0_no_config() since it needs nports
3767 FW_PARAMS_MNEM_V(FW_PARAMS_MNEM_DEV) |
3768 FW_PARAMS_PARAM_X_V(FW_PARAMS_PARAM_DEV_PORTVEC);
3769 ret = t4_query_params(adap, adap->mbox, adap->pf, 0, 1, &v, &port_vec);
3773 adap->params.nports = hweight32(port_vec);
3774 adap->params.portvec = port_vec;
3776 /* If the firmware is initialized already, emit a simply note to that
3777 * effect. Otherwise, it's time to try initializing the adapter.
3779 if (state == DEV_STATE_INIT) {
3780 dev_info(adap->pdev_dev, "Coming up as %s: "\
3781 "Adapter already initialized\n",
3782 adap->flags & MASTER_PF ? "MASTER" : "SLAVE");
3784 dev_info(adap->pdev_dev, "Coming up as MASTER: "\
3785 "Initializing adapter\n");
3787 /* Find out whether we're dealing with a version of the
3788 * firmware which has configuration file support.
3790 params[0] = (FW_PARAMS_MNEM_V(FW_PARAMS_MNEM_DEV) |
3791 FW_PARAMS_PARAM_X_V(FW_PARAMS_PARAM_DEV_CF));
3792 ret = t4_query_params(adap, adap->mbox, adap->pf, 0, 1,
3795 /* If the firmware doesn't support Configuration Files,
3799 dev_err(adap->pdev_dev, "firmware doesn't support "
3800 "Firmware Configuration Files\n");
3804 /* The firmware provides us with a memory buffer where we can
3805 * load a Configuration File from the host if we want to
3806 * override the Configuration File in flash.
3808 ret = adap_init0_config(adap, reset);
3809 if (ret == -ENOENT) {
3810 dev_err(adap->pdev_dev, "no Configuration File "
3811 "present on adapter.\n");
3815 dev_err(adap->pdev_dev, "could not initialize "
3816 "adapter, error %d\n", -ret);
3821 /* Give the SGE code a chance to pull in anything that it needs ...
3822 * Note that this must be called after we retrieve our VPD parameters
3823 * in order to know how to convert core ticks to seconds, etc.
3825 ret = t4_sge_init(adap);
3829 if (is_bypass_device(adap->pdev->device))
3830 adap->params.bypass = 1;
3833 * Grab some of our basic fundamental operating parameters.
3835 #define FW_PARAM_DEV(param) \
3836 (FW_PARAMS_MNEM_V(FW_PARAMS_MNEM_DEV) | \
3837 FW_PARAMS_PARAM_X_V(FW_PARAMS_PARAM_DEV_##param))
3839 #define FW_PARAM_PFVF(param) \
3840 FW_PARAMS_MNEM_V(FW_PARAMS_MNEM_PFVF) | \
3841 FW_PARAMS_PARAM_X_V(FW_PARAMS_PARAM_PFVF_##param)| \
3842 FW_PARAMS_PARAM_Y_V(0) | \
3843 FW_PARAMS_PARAM_Z_V(0)
3845 params[0] = FW_PARAM_PFVF(EQ_START);
3846 params[1] = FW_PARAM_PFVF(L2T_START);
3847 params[2] = FW_PARAM_PFVF(L2T_END);
3848 params[3] = FW_PARAM_PFVF(FILTER_START);
3849 params[4] = FW_PARAM_PFVF(FILTER_END);
3850 params[5] = FW_PARAM_PFVF(IQFLINT_START);
3851 ret = t4_query_params(adap, adap->mbox, adap->pf, 0, 6, params, val);
3854 adap->sge.egr_start = val[0];
3855 adap->l2t_start = val[1];
3856 adap->l2t_end = val[2];
3857 adap->tids.ftid_base = val[3];
3858 adap->tids.nftids = val[4] - val[3] + 1;
3859 adap->sge.ingr_start = val[5];
3861 /* qids (ingress/egress) returned from firmware can be anywhere
3862 * in the range from EQ(IQFLINT)_START to EQ(IQFLINT)_END.
3863 * Hence driver needs to allocate memory for this range to
3864 * store the queue info. Get the highest IQFLINT/EQ index returned
3865 * in FW_EQ_*_CMD.alloc command.
3867 params[0] = FW_PARAM_PFVF(EQ_END);
3868 params[1] = FW_PARAM_PFVF(IQFLINT_END);
3869 ret = t4_query_params(adap, adap->mbox, adap->pf, 0, 2, params, val);
3872 adap->sge.egr_sz = val[0] - adap->sge.egr_start + 1;
3873 adap->sge.ingr_sz = val[1] - adap->sge.ingr_start + 1;
3875 adap->sge.egr_map = kcalloc(adap->sge.egr_sz,
3876 sizeof(*adap->sge.egr_map), GFP_KERNEL);
3877 if (!adap->sge.egr_map) {
3882 adap->sge.ingr_map = kcalloc(adap->sge.ingr_sz,
3883 sizeof(*adap->sge.ingr_map), GFP_KERNEL);
3884 if (!adap->sge.ingr_map) {
3889 /* Allocate the memory for the vaious egress queue bitmaps
3890 * ie starving_fl, txq_maperr and blocked_fl.
3892 adap->sge.starving_fl = kcalloc(BITS_TO_LONGS(adap->sge.egr_sz),
3893 sizeof(long), GFP_KERNEL);
3894 if (!adap->sge.starving_fl) {
3899 adap->sge.txq_maperr = kcalloc(BITS_TO_LONGS(adap->sge.egr_sz),
3900 sizeof(long), GFP_KERNEL);
3901 if (!adap->sge.txq_maperr) {
3906 #ifdef CONFIG_DEBUG_FS
3907 adap->sge.blocked_fl = kcalloc(BITS_TO_LONGS(adap->sge.egr_sz),
3908 sizeof(long), GFP_KERNEL);
3909 if (!adap->sge.blocked_fl) {
3915 params[0] = FW_PARAM_PFVF(CLIP_START);
3916 params[1] = FW_PARAM_PFVF(CLIP_END);
3917 ret = t4_query_params(adap, adap->mbox, adap->pf, 0, 2, params, val);
3920 adap->clipt_start = val[0];
3921 adap->clipt_end = val[1];
3923 /* query params related to active filter region */
3924 params[0] = FW_PARAM_PFVF(ACTIVE_FILTER_START);
3925 params[1] = FW_PARAM_PFVF(ACTIVE_FILTER_END);
3926 ret = t4_query_params(adap, adap->mbox, adap->pf, 0, 2, params, val);
3927 /* If Active filter size is set we enable establishing
3928 * offload connection through firmware work request
3930 if ((val[0] != val[1]) && (ret >= 0)) {
3931 adap->flags |= FW_OFLD_CONN;
3932 adap->tids.aftid_base = val[0];
3933 adap->tids.aftid_end = val[1];
3936 /* If we're running on newer firmware, let it know that we're
3937 * prepared to deal with encapsulated CPL messages. Older
3938 * firmware won't understand this and we'll just get
3939 * unencapsulated messages ...
3941 params[0] = FW_PARAM_PFVF(CPLFW4MSG_ENCAP);
3943 (void)t4_set_params(adap, adap->mbox, adap->pf, 0, 1, params, val);
3946 * Find out whether we're allowed to use the T5+ ULPTX MEMWRITE DSGL
3947 * capability. Earlier versions of the firmware didn't have the
3948 * ULPTX_MEMWRITE_DSGL so we'll interpret a query failure as no
3949 * permission to use ULPTX MEMWRITE DSGL.
3951 if (is_t4(adap->params.chip)) {
3952 adap->params.ulptx_memwrite_dsgl = false;
3954 params[0] = FW_PARAM_DEV(ULPTX_MEMWRITE_DSGL);
3955 ret = t4_query_params(adap, adap->mbox, adap->pf, 0,
3957 adap->params.ulptx_memwrite_dsgl = (ret == 0 && val[0] != 0);
3961 * Get device capabilities so we can determine what resources we need
3964 memset(&caps_cmd, 0, sizeof(caps_cmd));
3965 caps_cmd.op_to_write = htonl(FW_CMD_OP_V(FW_CAPS_CONFIG_CMD) |
3966 FW_CMD_REQUEST_F | FW_CMD_READ_F);
3967 caps_cmd.cfvalid_to_len16 = htonl(FW_LEN16(caps_cmd));
3968 ret = t4_wr_mbox(adap, adap->mbox, &caps_cmd, sizeof(caps_cmd),
3973 if (caps_cmd.ofldcaps) {
3974 /* query offload-related parameters */
3975 params[0] = FW_PARAM_DEV(NTID);
3976 params[1] = FW_PARAM_PFVF(SERVER_START);
3977 params[2] = FW_PARAM_PFVF(SERVER_END);
3978 params[3] = FW_PARAM_PFVF(TDDP_START);
3979 params[4] = FW_PARAM_PFVF(TDDP_END);
3980 params[5] = FW_PARAM_DEV(FLOWC_BUFFIFO_SZ);
3981 ret = t4_query_params(adap, adap->mbox, adap->pf, 0, 6,
3985 adap->tids.ntids = val[0];
3986 adap->tids.natids = min(adap->tids.ntids / 2, MAX_ATIDS);
3987 adap->tids.stid_base = val[1];
3988 adap->tids.nstids = val[2] - val[1] + 1;
3990 * Setup server filter region. Divide the available filter
3991 * region into two parts. Regular filters get 1/3rd and server
3992 * filters get 2/3rd part. This is only enabled if workarond
3994 * 1. For regular filters.
3995 * 2. Server filter: This are special filters which are used
3996 * to redirect SYN packets to offload queue.
3998 if (adap->flags & FW_OFLD_CONN && !is_bypass(adap)) {
3999 adap->tids.sftid_base = adap->tids.ftid_base +
4000 DIV_ROUND_UP(adap->tids.nftids, 3);
4001 adap->tids.nsftids = adap->tids.nftids -
4002 DIV_ROUND_UP(adap->tids.nftids, 3);
4003 adap->tids.nftids = adap->tids.sftid_base -
4004 adap->tids.ftid_base;
4006 adap->vres.ddp.start = val[3];
4007 adap->vres.ddp.size = val[4] - val[3] + 1;
4008 adap->params.ofldq_wr_cred = val[5];
4010 adap->params.offload = 1;
4012 if (caps_cmd.rdmacaps) {
4013 params[0] = FW_PARAM_PFVF(STAG_START);
4014 params[1] = FW_PARAM_PFVF(STAG_END);
4015 params[2] = FW_PARAM_PFVF(RQ_START);
4016 params[3] = FW_PARAM_PFVF(RQ_END);
4017 params[4] = FW_PARAM_PFVF(PBL_START);
4018 params[5] = FW_PARAM_PFVF(PBL_END);
4019 ret = t4_query_params(adap, adap->mbox, adap->pf, 0, 6,
4023 adap->vres.stag.start = val[0];
4024 adap->vres.stag.size = val[1] - val[0] + 1;
4025 adap->vres.rq.start = val[2];
4026 adap->vres.rq.size = val[3] - val[2] + 1;
4027 adap->vres.pbl.start = val[4];
4028 adap->vres.pbl.size = val[5] - val[4] + 1;
4030 params[0] = FW_PARAM_PFVF(SQRQ_START);
4031 params[1] = FW_PARAM_PFVF(SQRQ_END);
4032 params[2] = FW_PARAM_PFVF(CQ_START);
4033 params[3] = FW_PARAM_PFVF(CQ_END);
4034 params[4] = FW_PARAM_PFVF(OCQ_START);
4035 params[5] = FW_PARAM_PFVF(OCQ_END);
4036 ret = t4_query_params(adap, adap->mbox, adap->pf, 0, 6, params,
4040 adap->vres.qp.start = val[0];
4041 adap->vres.qp.size = val[1] - val[0] + 1;
4042 adap->vres.cq.start = val[2];
4043 adap->vres.cq.size = val[3] - val[2] + 1;
4044 adap->vres.ocq.start = val[4];
4045 adap->vres.ocq.size = val[5] - val[4] + 1;
4047 params[0] = FW_PARAM_DEV(MAXORDIRD_QP);
4048 params[1] = FW_PARAM_DEV(MAXIRD_ADAPTER);
4049 ret = t4_query_params(adap, adap->mbox, adap->pf, 0, 2, params,
4052 adap->params.max_ordird_qp = 8;
4053 adap->params.max_ird_adapter = 32 * adap->tids.ntids;
4056 adap->params.max_ordird_qp = val[0];
4057 adap->params.max_ird_adapter = val[1];
4059 dev_info(adap->pdev_dev,
4060 "max_ordird_qp %d max_ird_adapter %d\n",
4061 adap->params.max_ordird_qp,
4062 adap->params.max_ird_adapter);
4064 if (caps_cmd.iscsicaps) {
4065 params[0] = FW_PARAM_PFVF(ISCSI_START);
4066 params[1] = FW_PARAM_PFVF(ISCSI_END);
4067 ret = t4_query_params(adap, adap->mbox, adap->pf, 0, 2,
4071 adap->vres.iscsi.start = val[0];
4072 adap->vres.iscsi.size = val[1] - val[0] + 1;
4074 #undef FW_PARAM_PFVF
4077 /* The MTU/MSS Table is initialized by now, so load their values. If
4078 * we're initializing the adapter, then we'll make any modifications
4079 * we want to the MTU/MSS Table and also initialize the congestion
4082 t4_read_mtu_tbl(adap, adap->params.mtus, NULL);
4083 if (state != DEV_STATE_INIT) {
4086 /* The default MTU Table contains values 1492 and 1500.
4087 * However, for TCP, it's better to have two values which are
4088 * a multiple of 8 +/- 4 bytes apart near this popular MTU.
4089 * This allows us to have a TCP Data Payload which is a
4090 * multiple of 8 regardless of what combination of TCP Options
4091 * are in use (always a multiple of 4 bytes) which is
4092 * important for performance reasons. For instance, if no
4093 * options are in use, then we have a 20-byte IP header and a
4094 * 20-byte TCP header. In this case, a 1500-byte MSS would
4095 * result in a TCP Data Payload of 1500 - 40 == 1460 bytes
4096 * which is not a multiple of 8. So using an MSS of 1488 in
4097 * this case results in a TCP Data Payload of 1448 bytes which
4098 * is a multiple of 8. On the other hand, if 12-byte TCP Time
4099 * Stamps have been negotiated, then an MTU of 1500 bytes
4100 * results in a TCP Data Payload of 1448 bytes which, as
4101 * above, is a multiple of 8 bytes ...
4103 for (i = 0; i < NMTUS; i++)
4104 if (adap->params.mtus[i] == 1492) {
4105 adap->params.mtus[i] = 1488;
4109 t4_load_mtus(adap, adap->params.mtus, adap->params.a_wnd,
4110 adap->params.b_wnd);
4112 t4_init_sge_params(adap);
4113 adap->flags |= FW_OK;
4114 t4_init_tp_params(adap);
4118 * Something bad happened. If a command timed out or failed with EIO
4119 * FW does not operate within its spec or something catastrophic
4120 * happened to HW/FW, stop issuing commands.
4123 kfree(adap->sge.egr_map);
4124 kfree(adap->sge.ingr_map);
4125 kfree(adap->sge.starving_fl);
4126 kfree(adap->sge.txq_maperr);
4127 #ifdef CONFIG_DEBUG_FS
4128 kfree(adap->sge.blocked_fl);
4130 if (ret != -ETIMEDOUT && ret != -EIO)
4131 t4_fw_bye(adap, adap->mbox);
4137 static pci_ers_result_t eeh_err_detected(struct pci_dev *pdev,
4138 pci_channel_state_t state)
4141 struct adapter *adap = pci_get_drvdata(pdev);
4147 adap->flags &= ~FW_OK;
4148 notify_ulds(adap, CXGB4_STATE_START_RECOVERY);
4149 spin_lock(&adap->stats_lock);
4150 for_each_port(adap, i) {
4151 struct net_device *dev = adap->port[i];
4153 netif_device_detach(dev);
4154 netif_carrier_off(dev);
4156 spin_unlock(&adap->stats_lock);
4157 disable_interrupts(adap);
4158 if (adap->flags & FULL_INIT_DONE)
4161 if ((adap->flags & DEV_ENABLED)) {
4162 pci_disable_device(pdev);
4163 adap->flags &= ~DEV_ENABLED;
4165 out: return state == pci_channel_io_perm_failure ?
4166 PCI_ERS_RESULT_DISCONNECT : PCI_ERS_RESULT_NEED_RESET;
4169 static pci_ers_result_t eeh_slot_reset(struct pci_dev *pdev)
4172 struct fw_caps_config_cmd c;
4173 struct adapter *adap = pci_get_drvdata(pdev);
4176 pci_restore_state(pdev);
4177 pci_save_state(pdev);
4178 return PCI_ERS_RESULT_RECOVERED;
4181 if (!(adap->flags & DEV_ENABLED)) {
4182 if (pci_enable_device(pdev)) {
4183 dev_err(&pdev->dev, "Cannot reenable PCI "
4184 "device after reset\n");
4185 return PCI_ERS_RESULT_DISCONNECT;
4187 adap->flags |= DEV_ENABLED;
4190 pci_set_master(pdev);
4191 pci_restore_state(pdev);
4192 pci_save_state(pdev);
4193 pci_cleanup_aer_uncorrect_error_status(pdev);
4195 if (t4_wait_dev_ready(adap->regs) < 0)
4196 return PCI_ERS_RESULT_DISCONNECT;
4197 if (t4_fw_hello(adap, adap->mbox, adap->pf, MASTER_MUST, NULL) < 0)
4198 return PCI_ERS_RESULT_DISCONNECT;
4199 adap->flags |= FW_OK;
4200 if (adap_init1(adap, &c))
4201 return PCI_ERS_RESULT_DISCONNECT;
4203 for_each_port(adap, i) {
4204 struct port_info *p = adap2pinfo(adap, i);
4206 ret = t4_alloc_vi(adap, adap->mbox, p->tx_chan, adap->pf, 0, 1,
4209 return PCI_ERS_RESULT_DISCONNECT;
4211 p->xact_addr_filt = -1;
4214 t4_load_mtus(adap, adap->params.mtus, adap->params.a_wnd,
4215 adap->params.b_wnd);
4218 return PCI_ERS_RESULT_DISCONNECT;
4219 return PCI_ERS_RESULT_RECOVERED;
4222 static void eeh_resume(struct pci_dev *pdev)
4225 struct adapter *adap = pci_get_drvdata(pdev);
4231 for_each_port(adap, i) {
4232 struct net_device *dev = adap->port[i];
4234 if (netif_running(dev)) {
4236 cxgb_set_rxmode(dev);
4238 netif_device_attach(dev);
4243 static const struct pci_error_handlers cxgb4_eeh = {
4244 .error_detected = eeh_err_detected,
4245 .slot_reset = eeh_slot_reset,
4246 .resume = eeh_resume,
4249 static inline bool is_x_10g_port(const struct link_config *lc)
4251 return (lc->supported & FW_PORT_CAP_SPEED_10G) != 0 ||
4252 (lc->supported & FW_PORT_CAP_SPEED_40G) != 0;
4255 static inline void init_rspq(struct adapter *adap, struct sge_rspq *q,
4256 unsigned int us, unsigned int cnt,
4257 unsigned int size, unsigned int iqe_size)
4260 cxgb4_set_rspq_intr_params(q, us, cnt);
4261 q->iqe_len = iqe_size;
4266 * Perform default configuration of DMA queues depending on the number and type
4267 * of ports we found and the number of available CPUs. Most settings can be
4268 * modified by the admin prior to actual use.
4270 static void cfg_queues(struct adapter *adap)
4272 struct sge *s = &adap->sge;
4273 int i, n10g = 0, qidx = 0;
4274 #ifndef CONFIG_CHELSIO_T4_DCB
4279 for_each_port(adap, i)
4280 n10g += is_x_10g_port(&adap2pinfo(adap, i)->link_cfg);
4281 #ifdef CONFIG_CHELSIO_T4_DCB
4282 /* For Data Center Bridging support we need to be able to support up
4283 * to 8 Traffic Priorities; each of which will be assigned to its
4284 * own TX Queue in order to prevent Head-Of-Line Blocking.
4286 if (adap->params.nports * 8 > MAX_ETH_QSETS) {
4287 dev_err(adap->pdev_dev, "MAX_ETH_QSETS=%d < %d!\n",
4288 MAX_ETH_QSETS, adap->params.nports * 8);
4292 for_each_port(adap, i) {
4293 struct port_info *pi = adap2pinfo(adap, i);
4295 pi->first_qset = qidx;
4299 #else /* !CONFIG_CHELSIO_T4_DCB */
4301 * We default to 1 queue per non-10G port and up to # of cores queues
4305 q10g = (MAX_ETH_QSETS - (adap->params.nports - n10g)) / n10g;
4306 if (q10g > netif_get_num_default_rss_queues())
4307 q10g = netif_get_num_default_rss_queues();
4309 for_each_port(adap, i) {
4310 struct port_info *pi = adap2pinfo(adap, i);
4312 pi->first_qset = qidx;
4313 pi->nqsets = is_x_10g_port(&pi->link_cfg) ? q10g : 1;
4316 #endif /* !CONFIG_CHELSIO_T4_DCB */
4319 s->max_ethqsets = qidx; /* MSI-X may lower it later */
4321 if (is_offload(adap)) {
4323 * For offload we use 1 queue/channel if all ports are up to 1G,
4324 * otherwise we divide all available queues amongst the channels
4325 * capped by the number of available cores.
4328 i = min_t(int, ARRAY_SIZE(s->ofldrxq),
4330 s->ofldqsets = roundup(i, adap->params.nports);
4332 s->ofldqsets = adap->params.nports;
4333 /* For RDMA one Rx queue per channel suffices */
4334 s->rdmaqs = adap->params.nports;
4335 /* Try and allow at least 1 CIQ per cpu rounding down
4336 * to the number of ports, with a minimum of 1 per port.
4337 * A 2 port card in a 6 cpu system: 6 CIQs, 3 / port.
4338 * A 4 port card in a 6 cpu system: 4 CIQs, 1 / port.
4339 * A 4 port card in a 2 cpu system: 4 CIQs, 1 / port.
4341 s->rdmaciqs = min_t(int, MAX_RDMA_CIQS, num_online_cpus());
4342 s->rdmaciqs = (s->rdmaciqs / adap->params.nports) *
4343 adap->params.nports;
4344 s->rdmaciqs = max_t(int, s->rdmaciqs, adap->params.nports);
4347 for (i = 0; i < ARRAY_SIZE(s->ethrxq); i++) {
4348 struct sge_eth_rxq *r = &s->ethrxq[i];
4350 init_rspq(adap, &r->rspq, 5, 10, 1024, 64);
4354 for (i = 0; i < ARRAY_SIZE(s->ethtxq); i++)
4355 s->ethtxq[i].q.size = 1024;
4357 for (i = 0; i < ARRAY_SIZE(s->ctrlq); i++)
4358 s->ctrlq[i].q.size = 512;
4360 for (i = 0; i < ARRAY_SIZE(s->ofldtxq); i++)
4361 s->ofldtxq[i].q.size = 1024;
4363 for (i = 0; i < ARRAY_SIZE(s->ofldrxq); i++) {
4364 struct sge_ofld_rxq *r = &s->ofldrxq[i];
4366 init_rspq(adap, &r->rspq, 5, 1, 1024, 64);
4367 r->rspq.uld = CXGB4_ULD_ISCSI;
4371 for (i = 0; i < ARRAY_SIZE(s->rdmarxq); i++) {
4372 struct sge_ofld_rxq *r = &s->rdmarxq[i];
4374 init_rspq(adap, &r->rspq, 5, 1, 511, 64);
4375 r->rspq.uld = CXGB4_ULD_RDMA;
4379 ciq_size = 64 + adap->vres.cq.size + adap->tids.nftids;
4380 if (ciq_size > SGE_MAX_IQ_SIZE) {
4381 CH_WARN(adap, "CIQ size too small for available IQs\n");
4382 ciq_size = SGE_MAX_IQ_SIZE;
4385 for (i = 0; i < ARRAY_SIZE(s->rdmaciq); i++) {
4386 struct sge_ofld_rxq *r = &s->rdmaciq[i];
4388 init_rspq(adap, &r->rspq, 5, 1, ciq_size, 64);
4389 r->rspq.uld = CXGB4_ULD_RDMA;
4392 init_rspq(adap, &s->fw_evtq, 0, 1, 1024, 64);
4393 init_rspq(adap, &s->intrq, 0, 1, 2 * MAX_INGQ, 64);
4397 * Reduce the number of Ethernet queues across all ports to at most n.
4398 * n provides at least one queue per port.
4400 static void reduce_ethqs(struct adapter *adap, int n)
4403 struct port_info *pi;
4405 while (n < adap->sge.ethqsets)
4406 for_each_port(adap, i) {
4407 pi = adap2pinfo(adap, i);
4408 if (pi->nqsets > 1) {
4410 adap->sge.ethqsets--;
4411 if (adap->sge.ethqsets <= n)
4417 for_each_port(adap, i) {
4418 pi = adap2pinfo(adap, i);
4424 /* 2 MSI-X vectors needed for the FW queue and non-data interrupts */
4425 #define EXTRA_VECS 2
4427 static int enable_msix(struct adapter *adap)
4430 int i, want, need, allocated;
4431 struct sge *s = &adap->sge;
4432 unsigned int nchan = adap->params.nports;
4433 struct msix_entry *entries;
4435 entries = kmalloc(sizeof(*entries) * (MAX_INGQ + 1),
4440 for (i = 0; i < MAX_INGQ + 1; ++i)
4441 entries[i].entry = i;
4443 want = s->max_ethqsets + EXTRA_VECS;
4444 if (is_offload(adap)) {
4445 want += s->rdmaqs + s->rdmaciqs + s->ofldqsets;
4446 /* need nchan for each possible ULD */
4447 ofld_need = 3 * nchan;
4449 #ifdef CONFIG_CHELSIO_T4_DCB
4450 /* For Data Center Bridging we need 8 Ethernet TX Priority Queues for
4453 need = 8 * adap->params.nports + EXTRA_VECS + ofld_need;
4455 need = adap->params.nports + EXTRA_VECS + ofld_need;
4457 allocated = pci_enable_msix_range(adap->pdev, entries, need, want);
4458 if (allocated < 0) {
4459 dev_info(adap->pdev_dev, "not enough MSI-X vectors left,"
4460 " not using MSI-X\n");
4465 /* Distribute available vectors to the various queue groups.
4466 * Every group gets its minimum requirement and NIC gets top
4467 * priority for leftovers.
4469 i = allocated - EXTRA_VECS - ofld_need;
4470 if (i < s->max_ethqsets) {
4471 s->max_ethqsets = i;
4472 if (i < s->ethqsets)
4473 reduce_ethqs(adap, i);
4475 if (is_offload(adap)) {
4476 if (allocated < want) {
4478 s->rdmaciqs = nchan;
4481 /* leftovers go to OFLD */
4482 i = allocated - EXTRA_VECS - s->max_ethqsets -
4483 s->rdmaqs - s->rdmaciqs;
4484 s->ofldqsets = (i / nchan) * nchan; /* round down */
4486 for (i = 0; i < allocated; ++i)
4487 adap->msix_info[i].vec = entries[i].vector;
4495 static int init_rss(struct adapter *adap)
4500 err = t4_init_rss_mode(adap, adap->mbox);
4504 for_each_port(adap, i) {
4505 struct port_info *pi = adap2pinfo(adap, i);
4507 pi->rss = kcalloc(pi->rss_size, sizeof(u16), GFP_KERNEL);
4514 static void print_port_info(const struct net_device *dev)
4518 const char *spd = "";
4519 const struct port_info *pi = netdev_priv(dev);
4520 const struct adapter *adap = pi->adapter;
4522 if (adap->params.pci.speed == PCI_EXP_LNKSTA_CLS_2_5GB)
4524 else if (adap->params.pci.speed == PCI_EXP_LNKSTA_CLS_5_0GB)
4526 else if (adap->params.pci.speed == PCI_EXP_LNKSTA_CLS_8_0GB)
4529 if (pi->link_cfg.supported & FW_PORT_CAP_SPEED_100M)
4530 bufp += sprintf(bufp, "100/");
4531 if (pi->link_cfg.supported & FW_PORT_CAP_SPEED_1G)
4532 bufp += sprintf(bufp, "1000/");
4533 if (pi->link_cfg.supported & FW_PORT_CAP_SPEED_10G)
4534 bufp += sprintf(bufp, "10G/");
4535 if (pi->link_cfg.supported & FW_PORT_CAP_SPEED_40G)
4536 bufp += sprintf(bufp, "40G/");
4539 sprintf(bufp, "BASE-%s", t4_get_port_type_description(pi->port_type));
4541 netdev_info(dev, "Chelsio %s rev %d %s %sNIC PCIe x%d%s%s\n",
4542 adap->params.vpd.id,
4543 CHELSIO_CHIP_RELEASE(adap->params.chip), buf,
4544 is_offload(adap) ? "R" : "", adap->params.pci.width, spd,
4545 (adap->flags & USING_MSIX) ? " MSI-X" :
4546 (adap->flags & USING_MSI) ? " MSI" : "");
4547 netdev_info(dev, "S/N: %s, P/N: %s\n",
4548 adap->params.vpd.sn, adap->params.vpd.pn);
4551 static void enable_pcie_relaxed_ordering(struct pci_dev *dev)
4553 pcie_capability_set_word(dev, PCI_EXP_DEVCTL, PCI_EXP_DEVCTL_RELAX_EN);
4557 * Free the following resources:
4558 * - memory used for tables
4561 * - resources FW is holding for us
4563 static void free_some_resources(struct adapter *adapter)
4567 t4_free_mem(adapter->l2t);
4568 t4_free_mem(adapter->tids.tid_tab);
4569 kfree(adapter->sge.egr_map);
4570 kfree(adapter->sge.ingr_map);
4571 kfree(adapter->sge.starving_fl);
4572 kfree(adapter->sge.txq_maperr);
4573 #ifdef CONFIG_DEBUG_FS
4574 kfree(adapter->sge.blocked_fl);
4576 disable_msi(adapter);
4578 for_each_port(adapter, i)
4579 if (adapter->port[i]) {
4580 struct port_info *pi = adap2pinfo(adapter, i);
4583 t4_free_vi(adapter, adapter->mbox, adapter->pf,
4585 kfree(adap2pinfo(adapter, i)->rss);
4586 free_netdev(adapter->port[i]);
4588 if (adapter->flags & FW_OK)
4589 t4_fw_bye(adapter, adapter->pf);
4592 #define TSO_FLAGS (NETIF_F_TSO | NETIF_F_TSO6 | NETIF_F_TSO_ECN)
4593 #define VLAN_FEAT (NETIF_F_SG | NETIF_F_IP_CSUM | TSO_FLAGS | \
4594 NETIF_F_IPV6_CSUM | NETIF_F_HIGHDMA)
4595 #define SEGMENT_SIZE 128
4597 static int get_chip_type(struct pci_dev *pdev, u32 pl_rev)
4601 /* Retrieve adapter's device ID */
4602 pci_read_config_word(pdev, PCI_DEVICE_ID, &device_id);
4604 switch (device_id >> 12) {
4606 return CHELSIO_CHIP_CODE(CHELSIO_T4, pl_rev);
4608 return CHELSIO_CHIP_CODE(CHELSIO_T5, pl_rev);
4610 return CHELSIO_CHIP_CODE(CHELSIO_T6, pl_rev);
4612 dev_err(&pdev->dev, "Device %d is not supported\n",
4618 static int init_one(struct pci_dev *pdev, const struct pci_device_id *ent)
4620 int func, i, err, s_qpp, qpp, num_seg;
4621 struct port_info *pi;
4622 bool highdma = false;
4623 struct adapter *adapter = NULL;
4626 enum chip_type chip;
4628 printk_once(KERN_INFO "%s - version %s\n", DRV_DESC, DRV_VERSION);
4630 err = pci_request_regions(pdev, KBUILD_MODNAME);
4632 /* Just info, some other driver may have claimed the device. */
4633 dev_info(&pdev->dev, "cannot obtain PCI resources\n");
4637 err = pci_enable_device(pdev);
4639 dev_err(&pdev->dev, "cannot enable PCI device\n");
4640 goto out_release_regions;
4643 regs = pci_ioremap_bar(pdev, 0);
4645 dev_err(&pdev->dev, "cannot map device registers\n");
4647 goto out_disable_device;
4650 err = t4_wait_dev_ready(regs);
4652 goto out_unmap_bar0;
4654 /* We control everything through one PF */
4655 whoami = readl(regs + PL_WHOAMI_A);
4656 pl_rev = REV_G(readl(regs + PL_REV_A));
4657 chip = get_chip_type(pdev, pl_rev);
4658 func = CHELSIO_CHIP_VERSION(chip) <= CHELSIO_T5 ?
4659 SOURCEPF_G(whoami) : T6_SOURCEPF_G(whoami);
4660 if (func != ent->driver_data) {
4662 pci_disable_device(pdev);
4663 pci_save_state(pdev); /* to restore SR-IOV later */
4667 if (!pci_set_dma_mask(pdev, DMA_BIT_MASK(64))) {
4669 err = pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(64));
4671 dev_err(&pdev->dev, "unable to obtain 64-bit DMA for "
4672 "coherent allocations\n");
4673 goto out_unmap_bar0;
4676 err = pci_set_dma_mask(pdev, DMA_BIT_MASK(32));
4678 dev_err(&pdev->dev, "no usable DMA configuration\n");
4679 goto out_unmap_bar0;
4683 pci_enable_pcie_error_reporting(pdev);
4684 enable_pcie_relaxed_ordering(pdev);
4685 pci_set_master(pdev);
4686 pci_save_state(pdev);
4688 adapter = kzalloc(sizeof(*adapter), GFP_KERNEL);
4691 goto out_unmap_bar0;
4694 adapter->workq = create_singlethread_workqueue("cxgb4");
4695 if (!adapter->workq) {
4697 goto out_free_adapter;
4700 /* PCI device has been enabled */
4701 adapter->flags |= DEV_ENABLED;
4703 adapter->regs = regs;
4704 adapter->pdev = pdev;
4705 adapter->pdev_dev = &pdev->dev;
4706 adapter->mbox = func;
4708 adapter->msg_enable = dflt_msg_enable;
4709 memset(adapter->chan_map, 0xff, sizeof(adapter->chan_map));
4711 spin_lock_init(&adapter->stats_lock);
4712 spin_lock_init(&adapter->tid_release_lock);
4713 spin_lock_init(&adapter->win0_lock);
4715 INIT_WORK(&adapter->tid_release_task, process_tid_release_list);
4716 INIT_WORK(&adapter->db_full_task, process_db_full);
4717 INIT_WORK(&adapter->db_drop_task, process_db_drop);
4719 err = t4_prep_adapter(adapter);
4721 goto out_free_adapter;
4724 if (!is_t4(adapter->params.chip)) {
4725 s_qpp = (QUEUESPERPAGEPF0_S +
4726 (QUEUESPERPAGEPF1_S - QUEUESPERPAGEPF0_S) *
4728 qpp = 1 << QUEUESPERPAGEPF0_G(t4_read_reg(adapter,
4729 SGE_EGRESS_QUEUES_PER_PAGE_PF_A) >> s_qpp);
4730 num_seg = PAGE_SIZE / SEGMENT_SIZE;
4732 /* Each segment size is 128B. Write coalescing is enabled only
4733 * when SGE_EGRESS_QUEUES_PER_PAGE_PF reg value for the
4734 * queue is less no of segments that can be accommodated in
4737 if (qpp > num_seg) {
4739 "Incorrect number of egress queues per page\n");
4741 goto out_free_adapter;
4743 adapter->bar2 = ioremap_wc(pci_resource_start(pdev, 2),
4744 pci_resource_len(pdev, 2));
4745 if (!adapter->bar2) {
4746 dev_err(&pdev->dev, "cannot map device bar2 region\n");
4748 goto out_free_adapter;
4752 setup_memwin(adapter);
4753 err = adap_init0(adapter);
4754 #ifdef CONFIG_DEBUG_FS
4755 bitmap_zero(adapter->sge.blocked_fl, adapter->sge.egr_sz);
4757 setup_memwin_rdma(adapter);
4761 /* configure SGE_STAT_CFG_A to read WC stats */
4762 if (!is_t4(adapter->params.chip))
4763 t4_write_reg(adapter, SGE_STAT_CFG_A,
4764 STATSOURCE_T5_V(7) | STATMODE_V(0));
4766 for_each_port(adapter, i) {
4767 struct net_device *netdev;
4769 netdev = alloc_etherdev_mq(sizeof(struct port_info),
4776 SET_NETDEV_DEV(netdev, &pdev->dev);
4778 adapter->port[i] = netdev;
4779 pi = netdev_priv(netdev);
4780 pi->adapter = adapter;
4781 pi->xact_addr_filt = -1;
4783 netdev->irq = pdev->irq;
4785 netdev->hw_features = NETIF_F_SG | TSO_FLAGS |
4786 NETIF_F_IP_CSUM | NETIF_F_IPV6_CSUM |
4787 NETIF_F_RXCSUM | NETIF_F_RXHASH |
4788 NETIF_F_HW_VLAN_CTAG_TX | NETIF_F_HW_VLAN_CTAG_RX;
4790 netdev->hw_features |= NETIF_F_HIGHDMA;
4791 netdev->features |= netdev->hw_features;
4792 netdev->vlan_features = netdev->features & VLAN_FEAT;
4794 netdev->priv_flags |= IFF_UNICAST_FLT;
4796 netdev->netdev_ops = &cxgb4_netdev_ops;
4797 #ifdef CONFIG_CHELSIO_T4_DCB
4798 netdev->dcbnl_ops = &cxgb4_dcb_ops;
4799 cxgb4_dcb_state_init(netdev);
4801 cxgb4_set_ethtool_ops(netdev);
4804 pci_set_drvdata(pdev, adapter);
4806 if (adapter->flags & FW_OK) {
4807 err = t4_port_init(adapter, func, func, 0);
4810 } else if (adapter->params.nports == 1) {
4811 /* If we don't have a connection to the firmware -- possibly
4812 * because of an error -- grab the raw VPD parameters so we
4813 * can set the proper MAC Address on the debug network
4814 * interface that we've created.
4816 u8 hw_addr[ETH_ALEN];
4817 u8 *na = adapter->params.vpd.na;
4819 err = t4_get_raw_vpd_params(adapter, &adapter->params.vpd);
4821 for (i = 0; i < ETH_ALEN; i++)
4822 hw_addr[i] = (hex2val(na[2 * i + 0]) * 16 +
4823 hex2val(na[2 * i + 1]));
4824 t4_set_hw_addr(adapter, 0, hw_addr);
4828 /* Configure queues and allocate tables now, they can be needed as
4829 * soon as the first register_netdev completes.
4831 cfg_queues(adapter);
4833 adapter->l2t = t4_init_l2t(adapter->l2t_start, adapter->l2t_end);
4834 if (!adapter->l2t) {
4835 /* We tolerate a lack of L2T, giving up some functionality */
4836 dev_warn(&pdev->dev, "could not allocate L2T, continuing\n");
4837 adapter->params.offload = 0;
4840 #if IS_ENABLED(CONFIG_IPV6)
4841 adapter->clipt = t4_init_clip_tbl(adapter->clipt_start,
4842 adapter->clipt_end);
4843 if (!adapter->clipt) {
4844 /* We tolerate a lack of clip_table, giving up
4845 * some functionality
4847 dev_warn(&pdev->dev,
4848 "could not allocate Clip table, continuing\n");
4849 adapter->params.offload = 0;
4852 if (is_offload(adapter) && tid_init(&adapter->tids) < 0) {
4853 dev_warn(&pdev->dev, "could not allocate TID table, "
4855 adapter->params.offload = 0;
4858 if (is_offload(adapter)) {
4859 if (t4_read_reg(adapter, LE_DB_CONFIG_A) & HASHEN_F) {
4860 u32 hash_base, hash_reg;
4862 if (chip <= CHELSIO_T5) {
4863 hash_reg = LE_DB_TID_HASHBASE_A;
4864 hash_base = t4_read_reg(adapter, hash_reg);
4865 adapter->tids.hash_base = hash_base / 4;
4867 hash_reg = T6_LE_DB_HASH_TID_BASE_A;
4868 hash_base = t4_read_reg(adapter, hash_reg);
4869 adapter->tids.hash_base = hash_base;
4874 /* See what interrupts we'll be using */
4875 if (msi > 1 && enable_msix(adapter) == 0)
4876 adapter->flags |= USING_MSIX;
4877 else if (msi > 0 && pci_enable_msi(pdev) == 0)
4878 adapter->flags |= USING_MSI;
4880 err = init_rss(adapter);
4885 * The card is now ready to go. If any errors occur during device
4886 * registration we do not fail the whole card but rather proceed only
4887 * with the ports we manage to register successfully. However we must
4888 * register at least one net device.
4890 for_each_port(adapter, i) {
4891 pi = adap2pinfo(adapter, i);
4892 netif_set_real_num_tx_queues(adapter->port[i], pi->nqsets);
4893 netif_set_real_num_rx_queues(adapter->port[i], pi->nqsets);
4895 err = register_netdev(adapter->port[i]);
4898 adapter->chan_map[pi->tx_chan] = i;
4899 print_port_info(adapter->port[i]);
4902 dev_err(&pdev->dev, "could not register any net devices\n");
4906 dev_warn(&pdev->dev, "only %d net devices registered\n", i);
4910 if (cxgb4_debugfs_root) {
4911 adapter->debugfs_root = debugfs_create_dir(pci_name(pdev),
4912 cxgb4_debugfs_root);
4913 setup_debugfs(adapter);
4916 /* PCIe EEH recovery on powerpc platforms needs fundamental reset */
4917 pdev->needs_freset = 1;
4919 if (is_offload(adapter))
4920 attach_ulds(adapter);
4923 #ifdef CONFIG_PCI_IOV
4924 if (func < ARRAY_SIZE(num_vf) && num_vf[func] > 0)
4925 if (pci_enable_sriov(pdev, num_vf[func]) == 0)
4926 dev_info(&pdev->dev,
4927 "instantiated %u virtual functions\n",
4933 free_some_resources(adapter);
4935 if (!is_t4(adapter->params.chip))
4936 iounmap(adapter->bar2);
4939 destroy_workqueue(adapter->workq);
4945 pci_disable_pcie_error_reporting(pdev);
4946 pci_disable_device(pdev);
4947 out_release_regions:
4948 pci_release_regions(pdev);
4952 static void remove_one(struct pci_dev *pdev)
4954 struct adapter *adapter = pci_get_drvdata(pdev);
4956 #ifdef CONFIG_PCI_IOV
4957 pci_disable_sriov(pdev);
4964 /* Tear down per-adapter Work Queue first since it can contain
4965 * references to our adapter data structure.
4967 destroy_workqueue(adapter->workq);
4969 if (is_offload(adapter))
4970 detach_ulds(adapter);
4972 disable_interrupts(adapter);
4974 for_each_port(adapter, i)
4975 if (adapter->port[i]->reg_state == NETREG_REGISTERED)
4976 unregister_netdev(adapter->port[i]);
4978 debugfs_remove_recursive(adapter->debugfs_root);
4980 /* If we allocated filters, free up state associated with any
4983 if (adapter->tids.ftid_tab) {
4984 struct filter_entry *f = &adapter->tids.ftid_tab[0];
4985 for (i = 0; i < (adapter->tids.nftids +
4986 adapter->tids.nsftids); i++, f++)
4988 clear_filter(adapter, f);
4991 if (adapter->flags & FULL_INIT_DONE)
4994 free_some_resources(adapter);
4995 #if IS_ENABLED(CONFIG_IPV6)
4996 t4_cleanup_clip_tbl(adapter);
4998 iounmap(adapter->regs);
4999 if (!is_t4(adapter->params.chip))
5000 iounmap(adapter->bar2);
5001 pci_disable_pcie_error_reporting(pdev);
5002 if ((adapter->flags & DEV_ENABLED)) {
5003 pci_disable_device(pdev);
5004 adapter->flags &= ~DEV_ENABLED;
5006 pci_release_regions(pdev);
5010 pci_release_regions(pdev);
5013 static struct pci_driver cxgb4_driver = {
5014 .name = KBUILD_MODNAME,
5015 .id_table = cxgb4_pci_tbl,
5017 .remove = remove_one,
5018 .shutdown = remove_one,
5019 .err_handler = &cxgb4_eeh,
5022 static int __init cxgb4_init_module(void)
5026 /* Debugfs support is optional, just warn if this fails */
5027 cxgb4_debugfs_root = debugfs_create_dir(KBUILD_MODNAME, NULL);
5028 if (!cxgb4_debugfs_root)
5029 pr_warn("could not create debugfs entry, continuing\n");
5031 ret = pci_register_driver(&cxgb4_driver);
5033 debugfs_remove(cxgb4_debugfs_root);
5035 #if IS_ENABLED(CONFIG_IPV6)
5036 if (!inet6addr_registered) {
5037 register_inet6addr_notifier(&cxgb4_inet6addr_notifier);
5038 inet6addr_registered = true;
5045 static void __exit cxgb4_cleanup_module(void)
5047 #if IS_ENABLED(CONFIG_IPV6)
5048 if (inet6addr_registered) {
5049 unregister_inet6addr_notifier(&cxgb4_inet6addr_notifier);
5050 inet6addr_registered = false;
5053 pci_unregister_driver(&cxgb4_driver);
5054 debugfs_remove(cxgb4_debugfs_root); /* NULL ok */
5057 module_init(cxgb4_init_module);
5058 module_exit(cxgb4_cleanup_module);