2 * This file is part of the Chelsio T4 Ethernet driver for Linux.
4 * Copyright (c) 2003-2014 Chelsio Communications, Inc. All rights reserved.
6 * This software is available to you under a choice of one of two
7 * licenses. You may choose to be licensed under the terms of the GNU
8 * General Public License (GPL) Version 2, available from the file
9 * COPYING in the main directory of this source tree, or the
10 * OpenIB.org BSD license below:
12 * Redistribution and use in source and binary forms, with or
13 * without modification, are permitted provided that the following
16 * - Redistributions of source code must retain the above
17 * copyright notice, this list of conditions and the following
20 * - Redistributions in binary form must reproduce the above
21 * copyright notice, this list of conditions and the following
22 * disclaimer in the documentation and/or other materials
23 * provided with the distribution.
25 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
26 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
27 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
28 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
29 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
30 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
31 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
35 #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
37 #include <linux/bitmap.h>
38 #include <linux/crc32.h>
39 #include <linux/ctype.h>
40 #include <linux/debugfs.h>
41 #include <linux/err.h>
42 #include <linux/etherdevice.h>
43 #include <linux/firmware.h>
45 #include <linux/if_vlan.h>
46 #include <linux/init.h>
47 #include <linux/log2.h>
48 #include <linux/mdio.h>
49 #include <linux/module.h>
50 #include <linux/moduleparam.h>
51 #include <linux/mutex.h>
52 #include <linux/netdevice.h>
53 #include <linux/pci.h>
54 #include <linux/aer.h>
55 #include <linux/rtnetlink.h>
56 #include <linux/sched.h>
57 #include <linux/seq_file.h>
58 #include <linux/sockios.h>
59 #include <linux/vmalloc.h>
60 #include <linux/workqueue.h>
61 #include <net/neighbour.h>
62 #include <net/netevent.h>
63 #include <net/addrconf.h>
64 #include <net/bonding.h>
65 #include <net/addrconf.h>
66 #include <asm/uaccess.h>
70 #include "t4_values.h"
73 #include "t4fw_version.h"
74 #include "cxgb4_dcb.h"
75 #include "cxgb4_debugfs.h"
79 char cxgb4_driver_name[] = KBUILD_MODNAME;
84 #define DRV_VERSION "2.0.0-ko"
85 const char cxgb4_driver_version[] = DRV_VERSION;
86 #define DRV_DESC "Chelsio T4/T5/T6 Network Driver"
88 /* Host shadow copy of ingress filter entry. This is in host native format
89 * and doesn't match the ordering or bit order, etc. of the hardware of the
90 * firmware command. The use of bit-field structure elements is purely to
91 * remind ourselves of the field size limitations and save memory in the case
92 * where the filter table is large.
95 /* Administrative fields for filter.
97 u32 valid:1; /* filter allocated and valid */
98 u32 locked:1; /* filter is administratively locked */
100 u32 pending:1; /* filter action is pending firmware reply */
101 u32 smtidx:8; /* Source MAC Table index for smac */
102 struct l2t_entry *l2t; /* Layer Two Table entry for dmac */
104 /* The filter itself. Most of this is a straight copy of information
105 * provided by the extended ioctl(). Some fields are translated to
106 * internal forms -- for instance the Ingress Queue ID passed in from
107 * the ioctl() is translated into the Absolute Ingress Queue ID.
109 struct ch_filter_specification fs;
112 #define DFLT_MSG_ENABLE (NETIF_MSG_DRV | NETIF_MSG_PROBE | NETIF_MSG_LINK | \
113 NETIF_MSG_TIMER | NETIF_MSG_IFDOWN | NETIF_MSG_IFUP |\
114 NETIF_MSG_RX_ERR | NETIF_MSG_TX_ERR)
116 /* Macros needed to support the PCI Device ID Table ...
118 #define CH_PCI_DEVICE_ID_TABLE_DEFINE_BEGIN \
119 static const struct pci_device_id cxgb4_pci_tbl[] = {
120 #define CH_PCI_DEVICE_ID_FUNCTION 0x4
122 /* Include PCI Device IDs for both PF4 and PF0-3 so our PCI probe() routine is
125 #define CH_PCI_DEVICE_ID_FUNCTION2 0x0
127 #define CH_PCI_ID_TABLE_ENTRY(devid) \
128 {PCI_VDEVICE(CHELSIO, (devid)), 4}
130 #define CH_PCI_DEVICE_ID_TABLE_DEFINE_END \
134 #include "t4_pci_id_tbl.h"
136 #define FW4_FNAME "cxgb4/t4fw.bin"
137 #define FW5_FNAME "cxgb4/t5fw.bin"
138 #define FW6_FNAME "cxgb4/t6fw.bin"
139 #define FW4_CFNAME "cxgb4/t4-config.txt"
140 #define FW5_CFNAME "cxgb4/t5-config.txt"
141 #define FW6_CFNAME "cxgb4/t6-config.txt"
142 #define PHY_AQ1202_FIRMWARE "cxgb4/aq1202_fw.cld"
143 #define PHY_BCM84834_FIRMWARE "cxgb4/bcm8483.bin"
144 #define PHY_AQ1202_DEVICEID 0x4409
145 #define PHY_BCM84834_DEVICEID 0x4486
147 MODULE_DESCRIPTION(DRV_DESC);
148 MODULE_AUTHOR("Chelsio Communications");
149 MODULE_LICENSE("Dual BSD/GPL");
150 MODULE_VERSION(DRV_VERSION);
151 MODULE_DEVICE_TABLE(pci, cxgb4_pci_tbl);
152 MODULE_FIRMWARE(FW4_FNAME);
153 MODULE_FIRMWARE(FW5_FNAME);
154 MODULE_FIRMWARE(FW6_FNAME);
157 * Normally we're willing to become the firmware's Master PF but will be happy
158 * if another PF has already become the Master and initialized the adapter.
159 * Setting "force_init" will cause this driver to forcibly establish itself as
160 * the Master PF and initialize the adapter.
162 static uint force_init;
164 module_param(force_init, uint, 0644);
165 MODULE_PARM_DESC(force_init, "Forcibly become Master PF and initialize adapter");
168 * Normally if the firmware we connect to has Configuration File support, we
169 * use that and only fall back to the old Driver-based initialization if the
170 * Configuration File fails for some reason. If force_old_init is set, then
171 * we'll always use the old Driver-based initialization sequence.
173 static uint force_old_init;
175 module_param(force_old_init, uint, 0644);
176 MODULE_PARM_DESC(force_old_init, "Force old initialization sequence, deprecated"
179 static int dflt_msg_enable = DFLT_MSG_ENABLE;
181 module_param(dflt_msg_enable, int, 0644);
182 MODULE_PARM_DESC(dflt_msg_enable, "Chelsio T4 default message enable bitmap");
185 * The driver uses the best interrupt scheme available on a platform in the
186 * order MSI-X, MSI, legacy INTx interrupts. This parameter determines which
187 * of these schemes the driver may consider as follows:
189 * msi = 2: choose from among all three options
190 * msi = 1: only consider MSI and INTx interrupts
191 * msi = 0: force INTx interrupts
195 module_param(msi, int, 0644);
196 MODULE_PARM_DESC(msi, "whether to use INTx (0), MSI (1) or MSI-X (2)");
199 * Queue interrupt hold-off timer values. Queues default to the first of these
202 static unsigned int intr_holdoff[SGE_NTIMERS - 1] = { 5, 10, 20, 50, 100 };
204 module_param_array(intr_holdoff, uint, NULL, 0644);
205 MODULE_PARM_DESC(intr_holdoff, "values for queue interrupt hold-off timers "
206 "0..4 in microseconds, deprecated parameter");
208 static unsigned int intr_cnt[SGE_NCOUNTERS - 1] = { 4, 8, 16 };
210 module_param_array(intr_cnt, uint, NULL, 0644);
211 MODULE_PARM_DESC(intr_cnt,
212 "thresholds 1..3 for queue interrupt packet counters, "
213 "deprecated parameter");
216 * Normally we tell the chip to deliver Ingress Packets into our DMA buffers
217 * offset by 2 bytes in order to have the IP headers line up on 4-byte
218 * boundaries. This is a requirement for many architectures which will throw
219 * a machine check fault if an attempt is made to access one of the 4-byte IP
220 * header fields on a non-4-byte boundary. And it's a major performance issue
221 * even on some architectures which allow it like some implementations of the
222 * x86 ISA. However, some architectures don't mind this and for some very
223 * edge-case performance sensitive applications (like forwarding large volumes
224 * of small packets), setting this DMA offset to 0 will decrease the number of
225 * PCI-E Bus transfers enough to measurably affect performance.
227 static int rx_dma_offset = 2;
231 #ifdef CONFIG_PCI_IOV
232 module_param(vf_acls, bool, 0644);
233 MODULE_PARM_DESC(vf_acls, "if set enable virtualization L2 ACL enforcement, "
234 "deprecated parameter");
236 /* Configure the number of PCI-E Virtual Function which are to be instantiated
237 * on SR-IOV Capable Physical Functions.
239 static unsigned int num_vf[NUM_OF_PF_WITH_SRIOV];
241 module_param_array(num_vf, uint, NULL, 0644);
242 MODULE_PARM_DESC(num_vf, "number of VFs for each of PFs 0-3");
245 /* TX Queue select used to determine what algorithm to use for selecting TX
246 * queue. Select between the kernel provided function (select_queue=0) or user
247 * cxgb_select_queue function (select_queue=1)
249 * Default: select_queue=0
251 static int select_queue;
252 module_param(select_queue, int, 0644);
253 MODULE_PARM_DESC(select_queue,
254 "Select between kernel provided method of selecting or driver method of selecting TX queue. Default is kernel method.");
256 static unsigned int tp_vlan_pri_map = HW_TPL_FR_MT_PR_IV_P_FC;
258 module_param(tp_vlan_pri_map, uint, 0644);
259 MODULE_PARM_DESC(tp_vlan_pri_map, "global compressed filter configuration, "
260 "deprecated parameter");
262 static struct dentry *cxgb4_debugfs_root;
264 static LIST_HEAD(adapter_list);
265 static DEFINE_MUTEX(uld_mutex);
266 /* Adapter list to be accessed from atomic context */
267 static LIST_HEAD(adap_rcu_list);
268 static DEFINE_SPINLOCK(adap_rcu_lock);
269 static struct cxgb4_uld_info ulds[CXGB4_ULD_MAX];
270 static const char *uld_str[] = { "RDMA", "iSCSI" };
272 static void link_report(struct net_device *dev)
274 if (!netif_carrier_ok(dev))
275 netdev_info(dev, "link down\n");
277 static const char *fc[] = { "no", "Rx", "Tx", "Tx/Rx" };
280 const struct port_info *p = netdev_priv(dev);
282 switch (p->link_cfg.speed) {
296 pr_info("%s: unsupported speed: %d\n",
297 dev->name, p->link_cfg.speed);
301 netdev_info(dev, "link up, %s, full-duplex, %s PAUSE\n", s,
306 #ifdef CONFIG_CHELSIO_T4_DCB
307 /* Set up/tear down Data Center Bridging Priority mapping for a net device. */
308 static void dcb_tx_queue_prio_enable(struct net_device *dev, int enable)
310 struct port_info *pi = netdev_priv(dev);
311 struct adapter *adap = pi->adapter;
312 struct sge_eth_txq *txq = &adap->sge.ethtxq[pi->first_qset];
315 /* We use a simple mapping of Port TX Queue Index to DCB
316 * Priority when we're enabling DCB.
318 for (i = 0; i < pi->nqsets; i++, txq++) {
322 name = (FW_PARAMS_MNEM_V(FW_PARAMS_MNEM_DMAQ) |
324 FW_PARAMS_PARAM_DMAQ_EQ_DCBPRIO_ETH) |
325 FW_PARAMS_PARAM_YZ_V(txq->q.cntxt_id));
326 value = enable ? i : 0xffffffff;
328 /* Since we can be called while atomic (from "interrupt
329 * level") we need to issue the Set Parameters Commannd
330 * without sleeping (timeout < 0).
332 err = t4_set_params_timeout(adap, adap->mbox, adap->pf, 0, 1,
334 -FW_CMD_MAX_TIMEOUT);
337 dev_err(adap->pdev_dev,
338 "Can't %s DCB Priority on port %d, TX Queue %d: err=%d\n",
339 enable ? "set" : "unset", pi->port_id, i, -err);
341 txq->dcb_prio = value;
344 #endif /* CONFIG_CHELSIO_T4_DCB */
346 void t4_os_link_changed(struct adapter *adapter, int port_id, int link_stat)
348 struct net_device *dev = adapter->port[port_id];
350 /* Skip changes from disabled ports. */
351 if (netif_running(dev) && link_stat != netif_carrier_ok(dev)) {
353 netif_carrier_on(dev);
355 #ifdef CONFIG_CHELSIO_T4_DCB
356 cxgb4_dcb_state_init(dev);
357 dcb_tx_queue_prio_enable(dev, false);
358 #endif /* CONFIG_CHELSIO_T4_DCB */
359 netif_carrier_off(dev);
366 void t4_os_portmod_changed(const struct adapter *adap, int port_id)
368 static const char *mod_str[] = {
369 NULL, "LR", "SR", "ER", "passive DA", "active DA", "LRM"
372 const struct net_device *dev = adap->port[port_id];
373 const struct port_info *pi = netdev_priv(dev);
375 if (pi->mod_type == FW_PORT_MOD_TYPE_NONE)
376 netdev_info(dev, "port module unplugged\n");
377 else if (pi->mod_type < ARRAY_SIZE(mod_str))
378 netdev_info(dev, "%s module inserted\n", mod_str[pi->mod_type]);
382 * Configure the exact and hash address filters to handle a port's multicast
383 * and secondary unicast MAC addresses.
385 static int set_addr_filters(const struct net_device *dev, bool sleep)
393 const struct netdev_hw_addr *ha;
394 int uc_cnt = netdev_uc_count(dev);
395 int mc_cnt = netdev_mc_count(dev);
396 const struct port_info *pi = netdev_priv(dev);
397 unsigned int mb = pi->adapter->pf;
399 /* first do the secondary unicast addresses */
400 netdev_for_each_uc_addr(ha, dev) {
401 addr[naddr++] = ha->addr;
402 if (--uc_cnt == 0 || naddr >= ARRAY_SIZE(addr)) {
403 ret = t4_alloc_mac_filt(pi->adapter, mb, pi->viid, free,
404 naddr, addr, filt_idx, &uhash, sleep);
413 /* next set up the multicast addresses */
414 netdev_for_each_mc_addr(ha, dev) {
415 addr[naddr++] = ha->addr;
416 if (--mc_cnt == 0 || naddr >= ARRAY_SIZE(addr)) {
417 ret = t4_alloc_mac_filt(pi->adapter, mb, pi->viid, free,
418 naddr, addr, filt_idx, &mhash, sleep);
427 return t4_set_addr_hash(pi->adapter, mb, pi->viid, uhash != 0,
428 uhash | mhash, sleep);
431 int dbfifo_int_thresh = 10; /* 10 == 640 entry threshold */
432 module_param(dbfifo_int_thresh, int, 0644);
433 MODULE_PARM_DESC(dbfifo_int_thresh, "doorbell fifo interrupt threshold");
436 * usecs to sleep while draining the dbfifo
438 static int dbfifo_drain_delay = 1000;
439 module_param(dbfifo_drain_delay, int, 0644);
440 MODULE_PARM_DESC(dbfifo_drain_delay,
441 "usecs to sleep while draining the dbfifo");
444 * Set Rx properties of a port, such as promiscruity, address filters, and MTU.
445 * If @mtu is -1 it is left unchanged.
447 static int set_rxmode(struct net_device *dev, int mtu, bool sleep_ok)
450 struct port_info *pi = netdev_priv(dev);
452 ret = set_addr_filters(dev, sleep_ok);
454 ret = t4_set_rxmode(pi->adapter, pi->adapter->pf, pi->viid, mtu,
455 (dev->flags & IFF_PROMISC) ? 1 : 0,
456 (dev->flags & IFF_ALLMULTI) ? 1 : 0, 1, -1,
462 * link_start - enable a port
463 * @dev: the port to enable
465 * Performs the MAC and PHY actions needed to enable a port.
467 static int link_start(struct net_device *dev)
470 struct port_info *pi = netdev_priv(dev);
471 unsigned int mb = pi->adapter->pf;
474 * We do not set address filters and promiscuity here, the stack does
475 * that step explicitly.
477 ret = t4_set_rxmode(pi->adapter, mb, pi->viid, dev->mtu, -1, -1, -1,
478 !!(dev->features & NETIF_F_HW_VLAN_CTAG_RX), true);
480 ret = t4_change_mac(pi->adapter, mb, pi->viid,
481 pi->xact_addr_filt, dev->dev_addr, true,
484 pi->xact_addr_filt = ret;
489 ret = t4_link_l1cfg(pi->adapter, mb, pi->tx_chan,
493 ret = t4_enable_vi_params(pi->adapter, mb, pi->viid, true,
494 true, CXGB4_DCB_ENABLED);
501 int cxgb4_dcb_enabled(const struct net_device *dev)
503 #ifdef CONFIG_CHELSIO_T4_DCB
504 struct port_info *pi = netdev_priv(dev);
506 if (!pi->dcb.enabled)
509 return ((pi->dcb.state == CXGB4_DCB_STATE_FW_ALLSYNCED) ||
510 (pi->dcb.state == CXGB4_DCB_STATE_HOST));
515 EXPORT_SYMBOL(cxgb4_dcb_enabled);
517 #ifdef CONFIG_CHELSIO_T4_DCB
518 /* Handle a Data Center Bridging update message from the firmware. */
519 static void dcb_rpl(struct adapter *adap, const struct fw_port_cmd *pcmd)
521 int port = FW_PORT_CMD_PORTID_G(ntohl(pcmd->op_to_portid));
522 struct net_device *dev = adap->port[port];
523 int old_dcb_enabled = cxgb4_dcb_enabled(dev);
526 cxgb4_dcb_handle_fw_update(adap, pcmd);
527 new_dcb_enabled = cxgb4_dcb_enabled(dev);
529 /* If the DCB has become enabled or disabled on the port then we're
530 * going to need to set up/tear down DCB Priority parameters for the
531 * TX Queues associated with the port.
533 if (new_dcb_enabled != old_dcb_enabled)
534 dcb_tx_queue_prio_enable(dev, new_dcb_enabled);
536 #endif /* CONFIG_CHELSIO_T4_DCB */
538 /* Clear a filter and release any of its resources that we own. This also
539 * clears the filter's "pending" status.
541 static void clear_filter(struct adapter *adap, struct filter_entry *f)
543 /* If the new or old filter have loopback rewriteing rules then we'll
544 * need to free any existing Layer Two Table (L2T) entries of the old
545 * filter rule. The firmware will handle freeing up any Source MAC
546 * Table (SMT) entries used for rewriting Source MAC Addresses in
550 cxgb4_l2t_release(f->l2t);
552 /* The zeroing of the filter rule below clears the filter valid,
553 * pending, locked flags, l2t pointer, etc. so it's all we need for
556 memset(f, 0, sizeof(*f));
559 /* Handle a filter write/deletion reply.
561 static void filter_rpl(struct adapter *adap, const struct cpl_set_tcb_rpl *rpl)
563 unsigned int idx = GET_TID(rpl);
564 unsigned int nidx = idx - adap->tids.ftid_base;
566 struct filter_entry *f;
568 if (idx >= adap->tids.ftid_base && nidx <
569 (adap->tids.nftids + adap->tids.nsftids)) {
571 ret = TCB_COOKIE_G(rpl->cookie);
572 f = &adap->tids.ftid_tab[idx];
574 if (ret == FW_FILTER_WR_FLT_DELETED) {
575 /* Clear the filter when we get confirmation from the
576 * hardware that the filter has been deleted.
578 clear_filter(adap, f);
579 } else if (ret == FW_FILTER_WR_SMT_TBL_FULL) {
580 dev_err(adap->pdev_dev, "filter %u setup failed due to full SMT\n",
582 clear_filter(adap, f);
583 } else if (ret == FW_FILTER_WR_FLT_ADDED) {
584 f->smtidx = (be64_to_cpu(rpl->oldval) >> 24) & 0xff;
585 f->pending = 0; /* asynchronous setup completed */
588 /* Something went wrong. Issue a warning about the
589 * problem and clear everything out.
591 dev_err(adap->pdev_dev, "filter %u setup failed with error %u\n",
593 clear_filter(adap, f);
598 /* Response queue handler for the FW event queue.
600 static int fwevtq_handler(struct sge_rspq *q, const __be64 *rsp,
601 const struct pkt_gl *gl)
603 u8 opcode = ((const struct rss_header *)rsp)->opcode;
605 rsp++; /* skip RSS header */
607 /* FW can send EGR_UPDATEs encapsulated in a CPL_FW4_MSG.
609 if (unlikely(opcode == CPL_FW4_MSG &&
610 ((const struct cpl_fw4_msg *)rsp)->type == FW_TYPE_RSSCPL)) {
612 opcode = ((const struct rss_header *)rsp)->opcode;
614 if (opcode != CPL_SGE_EGR_UPDATE) {
615 dev_err(q->adap->pdev_dev, "unexpected FW4/CPL %#x on FW event queue\n"
621 if (likely(opcode == CPL_SGE_EGR_UPDATE)) {
622 const struct cpl_sge_egr_update *p = (void *)rsp;
623 unsigned int qid = EGR_QID_G(ntohl(p->opcode_qid));
626 txq = q->adap->sge.egr_map[qid - q->adap->sge.egr_start];
628 if ((u8 *)txq < (u8 *)q->adap->sge.ofldtxq) {
629 struct sge_eth_txq *eq;
631 eq = container_of(txq, struct sge_eth_txq, q);
632 netif_tx_wake_queue(eq->txq);
634 struct sge_ofld_txq *oq;
636 oq = container_of(txq, struct sge_ofld_txq, q);
637 tasklet_schedule(&oq->qresume_tsk);
639 } else if (opcode == CPL_FW6_MSG || opcode == CPL_FW4_MSG) {
640 const struct cpl_fw6_msg *p = (void *)rsp;
642 #ifdef CONFIG_CHELSIO_T4_DCB
643 const struct fw_port_cmd *pcmd = (const void *)p->data;
644 unsigned int cmd = FW_CMD_OP_G(ntohl(pcmd->op_to_portid));
645 unsigned int action =
646 FW_PORT_CMD_ACTION_G(ntohl(pcmd->action_to_len16));
648 if (cmd == FW_PORT_CMD &&
649 action == FW_PORT_ACTION_GET_PORT_INFO) {
650 int port = FW_PORT_CMD_PORTID_G(
651 be32_to_cpu(pcmd->op_to_portid));
652 struct net_device *dev = q->adap->port[port];
653 int state_input = ((pcmd->u.info.dcbxdis_pkd &
654 FW_PORT_CMD_DCBXDIS_F)
655 ? CXGB4_DCB_INPUT_FW_DISABLED
656 : CXGB4_DCB_INPUT_FW_ENABLED);
658 cxgb4_dcb_state_fsm(dev, state_input);
661 if (cmd == FW_PORT_CMD &&
662 action == FW_PORT_ACTION_L2_DCB_CFG)
663 dcb_rpl(q->adap, pcmd);
667 t4_handle_fw_rpl(q->adap, p->data);
668 } else if (opcode == CPL_L2T_WRITE_RPL) {
669 const struct cpl_l2t_write_rpl *p = (void *)rsp;
671 do_l2t_write_rpl(q->adap, p);
672 } else if (opcode == CPL_SET_TCB_RPL) {
673 const struct cpl_set_tcb_rpl *p = (void *)rsp;
675 filter_rpl(q->adap, p);
677 dev_err(q->adap->pdev_dev,
678 "unexpected CPL %#x on FW event queue\n", opcode);
684 * uldrx_handler - response queue handler for ULD queues
685 * @q: the response queue that received the packet
686 * @rsp: the response queue descriptor holding the offload message
687 * @gl: the gather list of packet fragments
689 * Deliver an ingress offload packet to a ULD. All processing is done by
690 * the ULD, we just maintain statistics.
692 static int uldrx_handler(struct sge_rspq *q, const __be64 *rsp,
693 const struct pkt_gl *gl)
695 struct sge_ofld_rxq *rxq = container_of(q, struct sge_ofld_rxq, rspq);
697 /* FW can send CPLs encapsulated in a CPL_FW4_MSG.
699 if (((const struct rss_header *)rsp)->opcode == CPL_FW4_MSG &&
700 ((const struct cpl_fw4_msg *)(rsp + 1))->type == FW_TYPE_RSSCPL)
703 if (ulds[q->uld].rx_handler(q->adap->uld_handle[q->uld], rsp, gl)) {
709 else if (gl == CXGB4_MSG_AN)
716 static void disable_msi(struct adapter *adapter)
718 if (adapter->flags & USING_MSIX) {
719 pci_disable_msix(adapter->pdev);
720 adapter->flags &= ~USING_MSIX;
721 } else if (adapter->flags & USING_MSI) {
722 pci_disable_msi(adapter->pdev);
723 adapter->flags &= ~USING_MSI;
728 * Interrupt handler for non-data events used with MSI-X.
730 static irqreturn_t t4_nondata_intr(int irq, void *cookie)
732 struct adapter *adap = cookie;
733 u32 v = t4_read_reg(adap, MYPF_REG(PL_PF_INT_CAUSE_A));
737 t4_write_reg(adap, MYPF_REG(PL_PF_INT_CAUSE_A), v);
739 if (adap->flags & MASTER_PF)
740 t4_slow_intr_handler(adap);
745 * Name the MSI-X interrupts.
747 static void name_msix_vecs(struct adapter *adap)
749 int i, j, msi_idx = 2, n = sizeof(adap->msix_info[0].desc);
751 /* non-data interrupts */
752 snprintf(adap->msix_info[0].desc, n, "%s", adap->port[0]->name);
755 snprintf(adap->msix_info[1].desc, n, "%s-FWeventq",
756 adap->port[0]->name);
758 /* Ethernet queues */
759 for_each_port(adap, j) {
760 struct net_device *d = adap->port[j];
761 const struct port_info *pi = netdev_priv(d);
763 for (i = 0; i < pi->nqsets; i++, msi_idx++)
764 snprintf(adap->msix_info[msi_idx].desc, n, "%s-Rx%d",
769 for_each_ofldrxq(&adap->sge, i)
770 snprintf(adap->msix_info[msi_idx++].desc, n, "%s-ofld%d",
771 adap->port[0]->name, i);
773 for_each_rdmarxq(&adap->sge, i)
774 snprintf(adap->msix_info[msi_idx++].desc, n, "%s-rdma%d",
775 adap->port[0]->name, i);
777 for_each_rdmaciq(&adap->sge, i)
778 snprintf(adap->msix_info[msi_idx++].desc, n, "%s-rdma-ciq%d",
779 adap->port[0]->name, i);
782 static int request_msix_queue_irqs(struct adapter *adap)
784 struct sge *s = &adap->sge;
785 int err, ethqidx, ofldqidx = 0, rdmaqidx = 0, rdmaciqqidx = 0;
788 err = request_irq(adap->msix_info[1].vec, t4_sge_intr_msix, 0,
789 adap->msix_info[1].desc, &s->fw_evtq);
793 for_each_ethrxq(s, ethqidx) {
794 err = request_irq(adap->msix_info[msi_index].vec,
796 adap->msix_info[msi_index].desc,
797 &s->ethrxq[ethqidx].rspq);
802 for_each_ofldrxq(s, ofldqidx) {
803 err = request_irq(adap->msix_info[msi_index].vec,
805 adap->msix_info[msi_index].desc,
806 &s->ofldrxq[ofldqidx].rspq);
811 for_each_rdmarxq(s, rdmaqidx) {
812 err = request_irq(adap->msix_info[msi_index].vec,
814 adap->msix_info[msi_index].desc,
815 &s->rdmarxq[rdmaqidx].rspq);
820 for_each_rdmaciq(s, rdmaciqqidx) {
821 err = request_irq(adap->msix_info[msi_index].vec,
823 adap->msix_info[msi_index].desc,
824 &s->rdmaciq[rdmaciqqidx].rspq);
832 while (--rdmaciqqidx >= 0)
833 free_irq(adap->msix_info[--msi_index].vec,
834 &s->rdmaciq[rdmaciqqidx].rspq);
835 while (--rdmaqidx >= 0)
836 free_irq(adap->msix_info[--msi_index].vec,
837 &s->rdmarxq[rdmaqidx].rspq);
838 while (--ofldqidx >= 0)
839 free_irq(adap->msix_info[--msi_index].vec,
840 &s->ofldrxq[ofldqidx].rspq);
841 while (--ethqidx >= 0)
842 free_irq(adap->msix_info[--msi_index].vec,
843 &s->ethrxq[ethqidx].rspq);
844 free_irq(adap->msix_info[1].vec, &s->fw_evtq);
848 static void free_msix_queue_irqs(struct adapter *adap)
850 int i, msi_index = 2;
851 struct sge *s = &adap->sge;
853 free_irq(adap->msix_info[1].vec, &s->fw_evtq);
854 for_each_ethrxq(s, i)
855 free_irq(adap->msix_info[msi_index++].vec, &s->ethrxq[i].rspq);
856 for_each_ofldrxq(s, i)
857 free_irq(adap->msix_info[msi_index++].vec, &s->ofldrxq[i].rspq);
858 for_each_rdmarxq(s, i)
859 free_irq(adap->msix_info[msi_index++].vec, &s->rdmarxq[i].rspq);
860 for_each_rdmaciq(s, i)
861 free_irq(adap->msix_info[msi_index++].vec, &s->rdmaciq[i].rspq);
865 * cxgb4_write_rss - write the RSS table for a given port
867 * @queues: array of queue indices for RSS
869 * Sets up the portion of the HW RSS table for the port's VI to distribute
870 * packets to the Rx queues in @queues.
871 * Should never be called before setting up sge eth rx queues
873 int cxgb4_write_rss(const struct port_info *pi, const u16 *queues)
877 struct adapter *adapter = pi->adapter;
878 const struct sge_eth_rxq *rxq;
880 rxq = &adapter->sge.ethrxq[pi->first_qset];
881 rss = kmalloc(pi->rss_size * sizeof(u16), GFP_KERNEL);
885 /* map the queue indices to queue ids */
886 for (i = 0; i < pi->rss_size; i++, queues++)
887 rss[i] = rxq[*queues].rspq.abs_id;
889 err = t4_config_rss_range(adapter, adapter->pf, pi->viid, 0,
890 pi->rss_size, rss, pi->rss_size);
891 /* If Tunnel All Lookup isn't specified in the global RSS
892 * Configuration, then we need to specify a default Ingress
893 * Queue for any ingress packets which aren't hashed. We'll
894 * use our first ingress queue ...
897 err = t4_config_vi_rss(adapter, adapter->mbox, pi->viid,
898 FW_RSS_VI_CONFIG_CMD_IP6FOURTUPEN_F |
899 FW_RSS_VI_CONFIG_CMD_IP6TWOTUPEN_F |
900 FW_RSS_VI_CONFIG_CMD_IP4FOURTUPEN_F |
901 FW_RSS_VI_CONFIG_CMD_IP4TWOTUPEN_F |
902 FW_RSS_VI_CONFIG_CMD_UDPEN_F,
909 * setup_rss - configure RSS
912 * Sets up RSS for each port.
914 static int setup_rss(struct adapter *adap)
918 for_each_port(adap, i) {
919 const struct port_info *pi = adap2pinfo(adap, i);
921 /* Fill default values with equal distribution */
922 for (j = 0; j < pi->rss_size; j++)
923 pi->rss[j] = j % pi->nqsets;
925 err = cxgb4_write_rss(pi, pi->rss);
933 * Return the channel of the ingress queue with the given qid.
935 static unsigned int rxq_to_chan(const struct sge *p, unsigned int qid)
937 qid -= p->ingr_start;
938 return netdev2pinfo(p->ingr_map[qid]->netdev)->tx_chan;
942 * Wait until all NAPI handlers are descheduled.
944 static void quiesce_rx(struct adapter *adap)
948 for (i = 0; i < adap->sge.ingr_sz; i++) {
949 struct sge_rspq *q = adap->sge.ingr_map[i];
951 if (q && q->handler) {
952 napi_disable(&q->napi);
954 while (!cxgb_poll_lock_napi(q))
962 /* Disable interrupt and napi handler */
963 static void disable_interrupts(struct adapter *adap)
965 if (adap->flags & FULL_INIT_DONE) {
966 t4_intr_disable(adap);
967 if (adap->flags & USING_MSIX) {
968 free_msix_queue_irqs(adap);
969 free_irq(adap->msix_info[0].vec, adap);
971 free_irq(adap->pdev->irq, adap);
978 * Enable NAPI scheduling and interrupt generation for all Rx queues.
980 static void enable_rx(struct adapter *adap)
984 for (i = 0; i < adap->sge.ingr_sz; i++) {
985 struct sge_rspq *q = adap->sge.ingr_map[i];
990 cxgb_busy_poll_init_lock(q);
991 napi_enable(&q->napi);
993 /* 0-increment GTS to start the timer and enable interrupts */
994 t4_write_reg(adap, MYPF_REG(SGE_PF_GTS_A),
995 SEINTARM_V(q->intr_params) |
996 INGRESSQID_V(q->cntxt_id));
1000 static int alloc_ofld_rxqs(struct adapter *adap, struct sge_ofld_rxq *q,
1001 unsigned int nq, unsigned int per_chan, int msi_idx,
1006 for (i = 0; i < nq; i++, q++) {
1009 err = t4_sge_alloc_rxq(adap, &q->rspq, false,
1010 adap->port[i / per_chan],
1011 msi_idx, q->fl.size ? &q->fl : NULL,
1015 memset(&q->stats, 0, sizeof(q->stats));
1017 ids[i] = q->rspq.abs_id;
1023 * setup_sge_queues - configure SGE Tx/Rx/response queues
1024 * @adap: the adapter
1026 * Determines how many sets of SGE queues to use and initializes them.
1027 * We support multiple queue sets per port if we have MSI-X, otherwise
1028 * just one queue set per port.
1030 static int setup_sge_queues(struct adapter *adap)
1032 int err, msi_idx, i, j;
1033 struct sge *s = &adap->sge;
1035 bitmap_zero(s->starving_fl, s->egr_sz);
1036 bitmap_zero(s->txq_maperr, s->egr_sz);
1038 if (adap->flags & USING_MSIX)
1039 msi_idx = 1; /* vector 0 is for non-queue interrupts */
1041 err = t4_sge_alloc_rxq(adap, &s->intrq, false, adap->port[0], 0,
1045 msi_idx = -((int)s->intrq.abs_id + 1);
1048 /* NOTE: If you add/delete any Ingress/Egress Queue allocations in here,
1049 * don't forget to update the following which need to be
1050 * synchronized to and changes here.
1052 * 1. The calculations of MAX_INGQ in cxgb4.h.
1054 * 2. Update enable_msix/name_msix_vecs/request_msix_queue_irqs
1055 * to accommodate any new/deleted Ingress Queues
1056 * which need MSI-X Vectors.
1058 * 3. Update sge_qinfo_show() to include information on the
1059 * new/deleted queues.
1061 err = t4_sge_alloc_rxq(adap, &s->fw_evtq, true, adap->port[0],
1062 msi_idx, NULL, fwevtq_handler, -1);
1064 freeout: t4_free_sge_resources(adap);
1068 for_each_port(adap, i) {
1069 struct net_device *dev = adap->port[i];
1070 struct port_info *pi = netdev_priv(dev);
1071 struct sge_eth_rxq *q = &s->ethrxq[pi->first_qset];
1072 struct sge_eth_txq *t = &s->ethtxq[pi->first_qset];
1074 for (j = 0; j < pi->nqsets; j++, q++) {
1077 err = t4_sge_alloc_rxq(adap, &q->rspq, false, dev,
1080 t4_get_mps_bg_map(adap,
1085 memset(&q->stats, 0, sizeof(q->stats));
1087 for (j = 0; j < pi->nqsets; j++, t++) {
1088 err = t4_sge_alloc_eth_txq(adap, t, dev,
1089 netdev_get_tx_queue(dev, j),
1090 s->fw_evtq.cntxt_id);
1096 j = s->ofldqsets / adap->params.nports; /* ofld queues per channel */
1097 for_each_ofldrxq(s, i) {
1098 err = t4_sge_alloc_ofld_txq(adap, &s->ofldtxq[i],
1100 s->fw_evtq.cntxt_id);
1105 #define ALLOC_OFLD_RXQS(firstq, nq, per_chan, ids) do { \
1106 err = alloc_ofld_rxqs(adap, firstq, nq, per_chan, msi_idx, ids); \
1113 ALLOC_OFLD_RXQS(s->ofldrxq, s->ofldqsets, j, s->ofld_rxq);
1114 ALLOC_OFLD_RXQS(s->rdmarxq, s->rdmaqs, 1, s->rdma_rxq);
1115 j = s->rdmaciqs / adap->params.nports; /* rdmaq queues per channel */
1116 ALLOC_OFLD_RXQS(s->rdmaciq, s->rdmaciqs, j, s->rdma_ciq);
1118 #undef ALLOC_OFLD_RXQS
1120 for_each_port(adap, i) {
1122 * Note that ->rdmarxq[i].rspq.cntxt_id below is 0 if we don't
1123 * have RDMA queues, and that's the right value.
1125 err = t4_sge_alloc_ctrl_txq(adap, &s->ctrlq[i], adap->port[i],
1126 s->fw_evtq.cntxt_id,
1127 s->rdmarxq[i].rspq.cntxt_id);
1132 t4_write_reg(adap, is_t4(adap->params.chip) ?
1133 MPS_TRC_RSS_CONTROL_A :
1134 MPS_T5_TRC_RSS_CONTROL_A,
1135 RSSCONTROL_V(netdev2pinfo(adap->port[0])->tx_chan) |
1136 QUEUENUMBER_V(s->ethrxq[0].rspq.abs_id));
1141 * Allocate a chunk of memory using kmalloc or, if that fails, vmalloc.
1142 * The allocated memory is cleared.
1144 void *t4_alloc_mem(size_t size)
1146 void *p = kzalloc(size, GFP_KERNEL | __GFP_NOWARN);
1154 * Free memory allocated through alloc_mem().
1156 void t4_free_mem(void *addr)
1161 /* Send a Work Request to write the filter at a specified index. We construct
1162 * a Firmware Filter Work Request to have the work done and put the indicated
1163 * filter into "pending" mode which will prevent any further actions against
1164 * it till we get a reply from the firmware on the completion status of the
1167 static int set_filter_wr(struct adapter *adapter, int fidx)
1169 struct filter_entry *f = &adapter->tids.ftid_tab[fidx];
1170 struct sk_buff *skb;
1171 struct fw_filter_wr *fwr;
1174 skb = alloc_skb(sizeof(*fwr), GFP_KERNEL);
1178 /* If the new filter requires loopback Destination MAC and/or VLAN
1179 * rewriting then we need to allocate a Layer 2 Table (L2T) entry for
1182 if (f->fs.newdmac || f->fs.newvlan) {
1183 /* allocate L2T entry for new filter */
1184 f->l2t = t4_l2t_alloc_switching(adapter->l2t);
1185 if (f->l2t == NULL) {
1189 if (t4_l2t_set_switching(adapter, f->l2t, f->fs.vlan,
1190 f->fs.eport, f->fs.dmac)) {
1191 cxgb4_l2t_release(f->l2t);
1198 ftid = adapter->tids.ftid_base + fidx;
1200 fwr = (struct fw_filter_wr *)__skb_put(skb, sizeof(*fwr));
1201 memset(fwr, 0, sizeof(*fwr));
1203 /* It would be nice to put most of the following in t4_hw.c but most
1204 * of the work is translating the cxgbtool ch_filter_specification
1205 * into the Work Request and the definition of that structure is
1206 * currently in cxgbtool.h which isn't appropriate to pull into the
1207 * common code. We may eventually try to come up with a more neutral
1208 * filter specification structure but for now it's easiest to simply
1209 * put this fairly direct code in line ...
1211 fwr->op_pkd = htonl(FW_WR_OP_V(FW_FILTER_WR));
1212 fwr->len16_pkd = htonl(FW_WR_LEN16_V(sizeof(*fwr)/16));
1214 htonl(FW_FILTER_WR_TID_V(ftid) |
1215 FW_FILTER_WR_RQTYPE_V(f->fs.type) |
1216 FW_FILTER_WR_NOREPLY_V(0) |
1217 FW_FILTER_WR_IQ_V(f->fs.iq));
1218 fwr->del_filter_to_l2tix =
1219 htonl(FW_FILTER_WR_RPTTID_V(f->fs.rpttid) |
1220 FW_FILTER_WR_DROP_V(f->fs.action == FILTER_DROP) |
1221 FW_FILTER_WR_DIRSTEER_V(f->fs.dirsteer) |
1222 FW_FILTER_WR_MASKHASH_V(f->fs.maskhash) |
1223 FW_FILTER_WR_DIRSTEERHASH_V(f->fs.dirsteerhash) |
1224 FW_FILTER_WR_LPBK_V(f->fs.action == FILTER_SWITCH) |
1225 FW_FILTER_WR_DMAC_V(f->fs.newdmac) |
1226 FW_FILTER_WR_SMAC_V(f->fs.newsmac) |
1227 FW_FILTER_WR_INSVLAN_V(f->fs.newvlan == VLAN_INSERT ||
1228 f->fs.newvlan == VLAN_REWRITE) |
1229 FW_FILTER_WR_RMVLAN_V(f->fs.newvlan == VLAN_REMOVE ||
1230 f->fs.newvlan == VLAN_REWRITE) |
1231 FW_FILTER_WR_HITCNTS_V(f->fs.hitcnts) |
1232 FW_FILTER_WR_TXCHAN_V(f->fs.eport) |
1233 FW_FILTER_WR_PRIO_V(f->fs.prio) |
1234 FW_FILTER_WR_L2TIX_V(f->l2t ? f->l2t->idx : 0));
1235 fwr->ethtype = htons(f->fs.val.ethtype);
1236 fwr->ethtypem = htons(f->fs.mask.ethtype);
1237 fwr->frag_to_ovlan_vldm =
1238 (FW_FILTER_WR_FRAG_V(f->fs.val.frag) |
1239 FW_FILTER_WR_FRAGM_V(f->fs.mask.frag) |
1240 FW_FILTER_WR_IVLAN_VLD_V(f->fs.val.ivlan_vld) |
1241 FW_FILTER_WR_OVLAN_VLD_V(f->fs.val.ovlan_vld) |
1242 FW_FILTER_WR_IVLAN_VLDM_V(f->fs.mask.ivlan_vld) |
1243 FW_FILTER_WR_OVLAN_VLDM_V(f->fs.mask.ovlan_vld));
1245 fwr->rx_chan_rx_rpl_iq =
1246 htons(FW_FILTER_WR_RX_CHAN_V(0) |
1247 FW_FILTER_WR_RX_RPL_IQ_V(adapter->sge.fw_evtq.abs_id));
1248 fwr->maci_to_matchtypem =
1249 htonl(FW_FILTER_WR_MACI_V(f->fs.val.macidx) |
1250 FW_FILTER_WR_MACIM_V(f->fs.mask.macidx) |
1251 FW_FILTER_WR_FCOE_V(f->fs.val.fcoe) |
1252 FW_FILTER_WR_FCOEM_V(f->fs.mask.fcoe) |
1253 FW_FILTER_WR_PORT_V(f->fs.val.iport) |
1254 FW_FILTER_WR_PORTM_V(f->fs.mask.iport) |
1255 FW_FILTER_WR_MATCHTYPE_V(f->fs.val.matchtype) |
1256 FW_FILTER_WR_MATCHTYPEM_V(f->fs.mask.matchtype));
1257 fwr->ptcl = f->fs.val.proto;
1258 fwr->ptclm = f->fs.mask.proto;
1259 fwr->ttyp = f->fs.val.tos;
1260 fwr->ttypm = f->fs.mask.tos;
1261 fwr->ivlan = htons(f->fs.val.ivlan);
1262 fwr->ivlanm = htons(f->fs.mask.ivlan);
1263 fwr->ovlan = htons(f->fs.val.ovlan);
1264 fwr->ovlanm = htons(f->fs.mask.ovlan);
1265 memcpy(fwr->lip, f->fs.val.lip, sizeof(fwr->lip));
1266 memcpy(fwr->lipm, f->fs.mask.lip, sizeof(fwr->lipm));
1267 memcpy(fwr->fip, f->fs.val.fip, sizeof(fwr->fip));
1268 memcpy(fwr->fipm, f->fs.mask.fip, sizeof(fwr->fipm));
1269 fwr->lp = htons(f->fs.val.lport);
1270 fwr->lpm = htons(f->fs.mask.lport);
1271 fwr->fp = htons(f->fs.val.fport);
1272 fwr->fpm = htons(f->fs.mask.fport);
1274 memcpy(fwr->sma, f->fs.smac, sizeof(fwr->sma));
1276 /* Mark the filter as "pending" and ship off the Filter Work Request.
1277 * When we get the Work Request Reply we'll clear the pending status.
1280 set_wr_txq(skb, CPL_PRIORITY_CONTROL, f->fs.val.iport & 0x3);
1281 t4_ofld_send(adapter, skb);
1285 /* Delete the filter at a specified index.
1287 static int del_filter_wr(struct adapter *adapter, int fidx)
1289 struct filter_entry *f = &adapter->tids.ftid_tab[fidx];
1290 struct sk_buff *skb;
1291 struct fw_filter_wr *fwr;
1292 unsigned int len, ftid;
1295 ftid = adapter->tids.ftid_base + fidx;
1297 skb = alloc_skb(len, GFP_KERNEL);
1301 fwr = (struct fw_filter_wr *)__skb_put(skb, len);
1302 t4_mk_filtdelwr(ftid, fwr, adapter->sge.fw_evtq.abs_id);
1304 /* Mark the filter as "pending" and ship off the Filter Work Request.
1305 * When we get the Work Request Reply we'll clear the pending status.
1308 t4_mgmt_tx(adapter, skb);
1312 static u16 cxgb_select_queue(struct net_device *dev, struct sk_buff *skb,
1313 void *accel_priv, select_queue_fallback_t fallback)
1317 #ifdef CONFIG_CHELSIO_T4_DCB
1318 /* If a Data Center Bridging has been successfully negotiated on this
1319 * link then we'll use the skb's priority to map it to a TX Queue.
1320 * The skb's priority is determined via the VLAN Tag Priority Code
1323 if (cxgb4_dcb_enabled(dev)) {
1327 err = vlan_get_tag(skb, &vlan_tci);
1328 if (unlikely(err)) {
1329 if (net_ratelimit())
1331 "TX Packet without VLAN Tag on DCB Link\n");
1334 txq = (vlan_tci & VLAN_PRIO_MASK) >> VLAN_PRIO_SHIFT;
1335 #ifdef CONFIG_CHELSIO_T4_FCOE
1336 if (skb->protocol == htons(ETH_P_FCOE))
1337 txq = skb->priority & 0x7;
1338 #endif /* CONFIG_CHELSIO_T4_FCOE */
1342 #endif /* CONFIG_CHELSIO_T4_DCB */
1345 txq = (skb_rx_queue_recorded(skb)
1346 ? skb_get_rx_queue(skb)
1347 : smp_processor_id());
1349 while (unlikely(txq >= dev->real_num_tx_queues))
1350 txq -= dev->real_num_tx_queues;
1355 return fallback(dev, skb) % dev->real_num_tx_queues;
1358 static int closest_timer(const struct sge *s, int time)
1360 int i, delta, match = 0, min_delta = INT_MAX;
1362 for (i = 0; i < ARRAY_SIZE(s->timer_val); i++) {
1363 delta = time - s->timer_val[i];
1366 if (delta < min_delta) {
1374 static int closest_thres(const struct sge *s, int thres)
1376 int i, delta, match = 0, min_delta = INT_MAX;
1378 for (i = 0; i < ARRAY_SIZE(s->counter_val); i++) {
1379 delta = thres - s->counter_val[i];
1382 if (delta < min_delta) {
1391 * cxgb4_set_rspq_intr_params - set a queue's interrupt holdoff parameters
1393 * @us: the hold-off time in us, or 0 to disable timer
1394 * @cnt: the hold-off packet count, or 0 to disable counter
1396 * Sets an Rx queue's interrupt hold-off time and packet count. At least
1397 * one of the two needs to be enabled for the queue to generate interrupts.
1399 int cxgb4_set_rspq_intr_params(struct sge_rspq *q,
1400 unsigned int us, unsigned int cnt)
1402 struct adapter *adap = q->adap;
1404 if ((us | cnt) == 0)
1411 new_idx = closest_thres(&adap->sge, cnt);
1412 if (q->desc && q->pktcnt_idx != new_idx) {
1413 /* the queue has already been created, update it */
1414 v = FW_PARAMS_MNEM_V(FW_PARAMS_MNEM_DMAQ) |
1415 FW_PARAMS_PARAM_X_V(
1416 FW_PARAMS_PARAM_DMAQ_IQ_INTCNTTHRESH) |
1417 FW_PARAMS_PARAM_YZ_V(q->cntxt_id);
1418 err = t4_set_params(adap, adap->mbox, adap->pf, 0, 1,
1423 q->pktcnt_idx = new_idx;
1426 us = us == 0 ? 6 : closest_timer(&adap->sge, us);
1427 q->intr_params = QINTR_TIMER_IDX_V(us) | QINTR_CNT_EN_V(cnt > 0);
1431 static int cxgb_set_features(struct net_device *dev, netdev_features_t features)
1433 const struct port_info *pi = netdev_priv(dev);
1434 netdev_features_t changed = dev->features ^ features;
1437 if (!(changed & NETIF_F_HW_VLAN_CTAG_RX))
1440 err = t4_set_rxmode(pi->adapter, pi->adapter->pf, pi->viid, -1,
1442 !!(features & NETIF_F_HW_VLAN_CTAG_RX), true);
1444 dev->features = features ^ NETIF_F_HW_VLAN_CTAG_RX;
1448 static int setup_debugfs(struct adapter *adap)
1450 if (IS_ERR_OR_NULL(adap->debugfs_root))
1453 #ifdef CONFIG_DEBUG_FS
1454 t4_setup_debugfs(adap);
1460 * upper-layer driver support
1464 * Allocate an active-open TID and set it to the supplied value.
1466 int cxgb4_alloc_atid(struct tid_info *t, void *data)
1470 spin_lock_bh(&t->atid_lock);
1472 union aopen_entry *p = t->afree;
1474 atid = (p - t->atid_tab) + t->atid_base;
1479 spin_unlock_bh(&t->atid_lock);
1482 EXPORT_SYMBOL(cxgb4_alloc_atid);
1485 * Release an active-open TID.
1487 void cxgb4_free_atid(struct tid_info *t, unsigned int atid)
1489 union aopen_entry *p = &t->atid_tab[atid - t->atid_base];
1491 spin_lock_bh(&t->atid_lock);
1495 spin_unlock_bh(&t->atid_lock);
1497 EXPORT_SYMBOL(cxgb4_free_atid);
1500 * Allocate a server TID and set it to the supplied value.
1502 int cxgb4_alloc_stid(struct tid_info *t, int family, void *data)
1506 spin_lock_bh(&t->stid_lock);
1507 if (family == PF_INET) {
1508 stid = find_first_zero_bit(t->stid_bmap, t->nstids);
1509 if (stid < t->nstids)
1510 __set_bit(stid, t->stid_bmap);
1514 stid = bitmap_find_free_region(t->stid_bmap, t->nstids, 2);
1519 t->stid_tab[stid].data = data;
1520 stid += t->stid_base;
1521 /* IPv6 requires max of 520 bits or 16 cells in TCAM
1522 * This is equivalent to 4 TIDs. With CLIP enabled it
1525 if (family == PF_INET)
1528 t->stids_in_use += 4;
1530 spin_unlock_bh(&t->stid_lock);
1533 EXPORT_SYMBOL(cxgb4_alloc_stid);
1535 /* Allocate a server filter TID and set it to the supplied value.
1537 int cxgb4_alloc_sftid(struct tid_info *t, int family, void *data)
1541 spin_lock_bh(&t->stid_lock);
1542 if (family == PF_INET) {
1543 stid = find_next_zero_bit(t->stid_bmap,
1544 t->nstids + t->nsftids, t->nstids);
1545 if (stid < (t->nstids + t->nsftids))
1546 __set_bit(stid, t->stid_bmap);
1553 t->stid_tab[stid].data = data;
1555 stid += t->sftid_base;
1558 spin_unlock_bh(&t->stid_lock);
1561 EXPORT_SYMBOL(cxgb4_alloc_sftid);
1563 /* Release a server TID.
1565 void cxgb4_free_stid(struct tid_info *t, unsigned int stid, int family)
1567 /* Is it a server filter TID? */
1568 if (t->nsftids && (stid >= t->sftid_base)) {
1569 stid -= t->sftid_base;
1572 stid -= t->stid_base;
1575 spin_lock_bh(&t->stid_lock);
1576 if (family == PF_INET)
1577 __clear_bit(stid, t->stid_bmap);
1579 bitmap_release_region(t->stid_bmap, stid, 2);
1580 t->stid_tab[stid].data = NULL;
1581 if (stid < t->nstids) {
1582 if (family == PF_INET)
1585 t->stids_in_use -= 4;
1589 spin_unlock_bh(&t->stid_lock);
1591 EXPORT_SYMBOL(cxgb4_free_stid);
1594 * Populate a TID_RELEASE WR. Caller must properly size the skb.
1596 static void mk_tid_release(struct sk_buff *skb, unsigned int chan,
1599 struct cpl_tid_release *req;
1601 set_wr_txq(skb, CPL_PRIORITY_SETUP, chan);
1602 req = (struct cpl_tid_release *)__skb_put(skb, sizeof(*req));
1603 INIT_TP_WR(req, tid);
1604 OPCODE_TID(req) = htonl(MK_OPCODE_TID(CPL_TID_RELEASE, tid));
1608 * Queue a TID release request and if necessary schedule a work queue to
1611 static void cxgb4_queue_tid_release(struct tid_info *t, unsigned int chan,
1614 void **p = &t->tid_tab[tid];
1615 struct adapter *adap = container_of(t, struct adapter, tids);
1617 spin_lock_bh(&adap->tid_release_lock);
1618 *p = adap->tid_release_head;
1619 /* Low 2 bits encode the Tx channel number */
1620 adap->tid_release_head = (void **)((uintptr_t)p | chan);
1621 if (!adap->tid_release_task_busy) {
1622 adap->tid_release_task_busy = true;
1623 queue_work(adap->workq, &adap->tid_release_task);
1625 spin_unlock_bh(&adap->tid_release_lock);
1629 * Process the list of pending TID release requests.
1631 static void process_tid_release_list(struct work_struct *work)
1633 struct sk_buff *skb;
1634 struct adapter *adap;
1636 adap = container_of(work, struct adapter, tid_release_task);
1638 spin_lock_bh(&adap->tid_release_lock);
1639 while (adap->tid_release_head) {
1640 void **p = adap->tid_release_head;
1641 unsigned int chan = (uintptr_t)p & 3;
1642 p = (void *)p - chan;
1644 adap->tid_release_head = *p;
1646 spin_unlock_bh(&adap->tid_release_lock);
1648 while (!(skb = alloc_skb(sizeof(struct cpl_tid_release),
1650 schedule_timeout_uninterruptible(1);
1652 mk_tid_release(skb, chan, p - adap->tids.tid_tab);
1653 t4_ofld_send(adap, skb);
1654 spin_lock_bh(&adap->tid_release_lock);
1656 adap->tid_release_task_busy = false;
1657 spin_unlock_bh(&adap->tid_release_lock);
1661 * Release a TID and inform HW. If we are unable to allocate the release
1662 * message we defer to a work queue.
1664 void cxgb4_remove_tid(struct tid_info *t, unsigned int chan, unsigned int tid)
1666 struct sk_buff *skb;
1667 struct adapter *adap = container_of(t, struct adapter, tids);
1669 WARN_ON(tid >= t->ntids);
1671 if (t->tid_tab[tid]) {
1672 t->tid_tab[tid] = NULL;
1673 if (t->hash_base && (tid >= t->hash_base))
1674 atomic_dec(&t->hash_tids_in_use);
1676 atomic_dec(&t->tids_in_use);
1679 skb = alloc_skb(sizeof(struct cpl_tid_release), GFP_ATOMIC);
1681 mk_tid_release(skb, chan, tid);
1682 t4_ofld_send(adap, skb);
1684 cxgb4_queue_tid_release(t, chan, tid);
1686 EXPORT_SYMBOL(cxgb4_remove_tid);
1689 * Allocate and initialize the TID tables. Returns 0 on success.
1691 static int tid_init(struct tid_info *t)
1694 unsigned int stid_bmap_size;
1695 unsigned int natids = t->natids;
1696 struct adapter *adap = container_of(t, struct adapter, tids);
1698 stid_bmap_size = BITS_TO_LONGS(t->nstids + t->nsftids);
1699 size = t->ntids * sizeof(*t->tid_tab) +
1700 natids * sizeof(*t->atid_tab) +
1701 t->nstids * sizeof(*t->stid_tab) +
1702 t->nsftids * sizeof(*t->stid_tab) +
1703 stid_bmap_size * sizeof(long) +
1704 t->nftids * sizeof(*t->ftid_tab) +
1705 t->nsftids * sizeof(*t->ftid_tab);
1707 t->tid_tab = t4_alloc_mem(size);
1711 t->atid_tab = (union aopen_entry *)&t->tid_tab[t->ntids];
1712 t->stid_tab = (struct serv_entry *)&t->atid_tab[natids];
1713 t->stid_bmap = (unsigned long *)&t->stid_tab[t->nstids + t->nsftids];
1714 t->ftid_tab = (struct filter_entry *)&t->stid_bmap[stid_bmap_size];
1715 spin_lock_init(&t->stid_lock);
1716 spin_lock_init(&t->atid_lock);
1718 t->stids_in_use = 0;
1719 t->sftids_in_use = 0;
1721 t->atids_in_use = 0;
1722 atomic_set(&t->tids_in_use, 0);
1723 atomic_set(&t->hash_tids_in_use, 0);
1725 /* Setup the free list for atid_tab and clear the stid bitmap. */
1728 t->atid_tab[natids - 1].next = &t->atid_tab[natids];
1729 t->afree = t->atid_tab;
1731 bitmap_zero(t->stid_bmap, t->nstids + t->nsftids);
1732 /* Reserve stid 0 for T4/T5 adapters */
1733 if (!t->stid_base &&
1734 (CHELSIO_CHIP_VERSION(adap->params.chip) <= CHELSIO_T5))
1735 __set_bit(0, t->stid_bmap);
1741 * cxgb4_create_server - create an IP server
1743 * @stid: the server TID
1744 * @sip: local IP address to bind server to
1745 * @sport: the server's TCP port
1746 * @queue: queue to direct messages from this server to
1748 * Create an IP server for the given port and address.
1749 * Returns <0 on error and one of the %NET_XMIT_* values on success.
1751 int cxgb4_create_server(const struct net_device *dev, unsigned int stid,
1752 __be32 sip, __be16 sport, __be16 vlan,
1756 struct sk_buff *skb;
1757 struct adapter *adap;
1758 struct cpl_pass_open_req *req;
1761 skb = alloc_skb(sizeof(*req), GFP_KERNEL);
1765 adap = netdev2adap(dev);
1766 req = (struct cpl_pass_open_req *)__skb_put(skb, sizeof(*req));
1768 OPCODE_TID(req) = htonl(MK_OPCODE_TID(CPL_PASS_OPEN_REQ, stid));
1769 req->local_port = sport;
1770 req->peer_port = htons(0);
1771 req->local_ip = sip;
1772 req->peer_ip = htonl(0);
1773 chan = rxq_to_chan(&adap->sge, queue);
1774 req->opt0 = cpu_to_be64(TX_CHAN_V(chan));
1775 req->opt1 = cpu_to_be64(CONN_POLICY_V(CPL_CONN_POLICY_ASK) |
1776 SYN_RSS_ENABLE_F | SYN_RSS_QUEUE_V(queue));
1777 ret = t4_mgmt_tx(adap, skb);
1778 return net_xmit_eval(ret);
1780 EXPORT_SYMBOL(cxgb4_create_server);
1782 /* cxgb4_create_server6 - create an IPv6 server
1784 * @stid: the server TID
1785 * @sip: local IPv6 address to bind server to
1786 * @sport: the server's TCP port
1787 * @queue: queue to direct messages from this server to
1789 * Create an IPv6 server for the given port and address.
1790 * Returns <0 on error and one of the %NET_XMIT_* values on success.
1792 int cxgb4_create_server6(const struct net_device *dev, unsigned int stid,
1793 const struct in6_addr *sip, __be16 sport,
1797 struct sk_buff *skb;
1798 struct adapter *adap;
1799 struct cpl_pass_open_req6 *req;
1802 skb = alloc_skb(sizeof(*req), GFP_KERNEL);
1806 adap = netdev2adap(dev);
1807 req = (struct cpl_pass_open_req6 *)__skb_put(skb, sizeof(*req));
1809 OPCODE_TID(req) = htonl(MK_OPCODE_TID(CPL_PASS_OPEN_REQ6, stid));
1810 req->local_port = sport;
1811 req->peer_port = htons(0);
1812 req->local_ip_hi = *(__be64 *)(sip->s6_addr);
1813 req->local_ip_lo = *(__be64 *)(sip->s6_addr + 8);
1814 req->peer_ip_hi = cpu_to_be64(0);
1815 req->peer_ip_lo = cpu_to_be64(0);
1816 chan = rxq_to_chan(&adap->sge, queue);
1817 req->opt0 = cpu_to_be64(TX_CHAN_V(chan));
1818 req->opt1 = cpu_to_be64(CONN_POLICY_V(CPL_CONN_POLICY_ASK) |
1819 SYN_RSS_ENABLE_F | SYN_RSS_QUEUE_V(queue));
1820 ret = t4_mgmt_tx(adap, skb);
1821 return net_xmit_eval(ret);
1823 EXPORT_SYMBOL(cxgb4_create_server6);
1825 int cxgb4_remove_server(const struct net_device *dev, unsigned int stid,
1826 unsigned int queue, bool ipv6)
1828 struct sk_buff *skb;
1829 struct adapter *adap;
1830 struct cpl_close_listsvr_req *req;
1833 adap = netdev2adap(dev);
1835 skb = alloc_skb(sizeof(*req), GFP_KERNEL);
1839 req = (struct cpl_close_listsvr_req *)__skb_put(skb, sizeof(*req));
1841 OPCODE_TID(req) = htonl(MK_OPCODE_TID(CPL_CLOSE_LISTSRV_REQ, stid));
1842 req->reply_ctrl = htons(NO_REPLY_V(0) | (ipv6 ? LISTSVR_IPV6_V(1) :
1843 LISTSVR_IPV6_V(0)) | QUEUENO_V(queue));
1844 ret = t4_mgmt_tx(adap, skb);
1845 return net_xmit_eval(ret);
1847 EXPORT_SYMBOL(cxgb4_remove_server);
1850 * cxgb4_best_mtu - find the entry in the MTU table closest to an MTU
1851 * @mtus: the HW MTU table
1852 * @mtu: the target MTU
1853 * @idx: index of selected entry in the MTU table
1855 * Returns the index and the value in the HW MTU table that is closest to
1856 * but does not exceed @mtu, unless @mtu is smaller than any value in the
1857 * table, in which case that smallest available value is selected.
1859 unsigned int cxgb4_best_mtu(const unsigned short *mtus, unsigned short mtu,
1864 while (i < NMTUS - 1 && mtus[i + 1] <= mtu)
1870 EXPORT_SYMBOL(cxgb4_best_mtu);
1873 * cxgb4_best_aligned_mtu - find best MTU, [hopefully] data size aligned
1874 * @mtus: the HW MTU table
1875 * @header_size: Header Size
1876 * @data_size_max: maximum Data Segment Size
1877 * @data_size_align: desired Data Segment Size Alignment (2^N)
1878 * @mtu_idxp: HW MTU Table Index return value pointer (possibly NULL)
1880 * Similar to cxgb4_best_mtu() but instead of searching the Hardware
1881 * MTU Table based solely on a Maximum MTU parameter, we break that
1882 * parameter up into a Header Size and Maximum Data Segment Size, and
1883 * provide a desired Data Segment Size Alignment. If we find an MTU in
1884 * the Hardware MTU Table which will result in a Data Segment Size with
1885 * the requested alignment _and_ that MTU isn't "too far" from the
1886 * closest MTU, then we'll return that rather than the closest MTU.
1888 unsigned int cxgb4_best_aligned_mtu(const unsigned short *mtus,
1889 unsigned short header_size,
1890 unsigned short data_size_max,
1891 unsigned short data_size_align,
1892 unsigned int *mtu_idxp)
1894 unsigned short max_mtu = header_size + data_size_max;
1895 unsigned short data_size_align_mask = data_size_align - 1;
1896 int mtu_idx, aligned_mtu_idx;
1898 /* Scan the MTU Table till we find an MTU which is larger than our
1899 * Maximum MTU or we reach the end of the table. Along the way,
1900 * record the last MTU found, if any, which will result in a Data
1901 * Segment Length matching the requested alignment.
1903 for (mtu_idx = 0, aligned_mtu_idx = -1; mtu_idx < NMTUS; mtu_idx++) {
1904 unsigned short data_size = mtus[mtu_idx] - header_size;
1906 /* If this MTU minus the Header Size would result in a
1907 * Data Segment Size of the desired alignment, remember it.
1909 if ((data_size & data_size_align_mask) == 0)
1910 aligned_mtu_idx = mtu_idx;
1912 /* If we're not at the end of the Hardware MTU Table and the
1913 * next element is larger than our Maximum MTU, drop out of
1916 if (mtu_idx+1 < NMTUS && mtus[mtu_idx+1] > max_mtu)
1920 /* If we fell out of the loop because we ran to the end of the table,
1921 * then we just have to use the last [largest] entry.
1923 if (mtu_idx == NMTUS)
1926 /* If we found an MTU which resulted in the requested Data Segment
1927 * Length alignment and that's "not far" from the largest MTU which is
1928 * less than or equal to the maximum MTU, then use that.
1930 if (aligned_mtu_idx >= 0 &&
1931 mtu_idx - aligned_mtu_idx <= 1)
1932 mtu_idx = aligned_mtu_idx;
1934 /* If the caller has passed in an MTU Index pointer, pass the
1935 * MTU Index back. Return the MTU value.
1938 *mtu_idxp = mtu_idx;
1939 return mtus[mtu_idx];
1941 EXPORT_SYMBOL(cxgb4_best_aligned_mtu);
1944 * cxgb4_port_chan - get the HW channel of a port
1945 * @dev: the net device for the port
1947 * Return the HW Tx channel of the given port.
1949 unsigned int cxgb4_port_chan(const struct net_device *dev)
1951 return netdev2pinfo(dev)->tx_chan;
1953 EXPORT_SYMBOL(cxgb4_port_chan);
1955 unsigned int cxgb4_dbfifo_count(const struct net_device *dev, int lpfifo)
1957 struct adapter *adap = netdev2adap(dev);
1958 u32 v1, v2, lp_count, hp_count;
1960 v1 = t4_read_reg(adap, SGE_DBFIFO_STATUS_A);
1961 v2 = t4_read_reg(adap, SGE_DBFIFO_STATUS2_A);
1962 if (is_t4(adap->params.chip)) {
1963 lp_count = LP_COUNT_G(v1);
1964 hp_count = HP_COUNT_G(v1);
1966 lp_count = LP_COUNT_T5_G(v1);
1967 hp_count = HP_COUNT_T5_G(v2);
1969 return lpfifo ? lp_count : hp_count;
1971 EXPORT_SYMBOL(cxgb4_dbfifo_count);
1974 * cxgb4_port_viid - get the VI id of a port
1975 * @dev: the net device for the port
1977 * Return the VI id of the given port.
1979 unsigned int cxgb4_port_viid(const struct net_device *dev)
1981 return netdev2pinfo(dev)->viid;
1983 EXPORT_SYMBOL(cxgb4_port_viid);
1986 * cxgb4_port_idx - get the index of a port
1987 * @dev: the net device for the port
1989 * Return the index of the given port.
1991 unsigned int cxgb4_port_idx(const struct net_device *dev)
1993 return netdev2pinfo(dev)->port_id;
1995 EXPORT_SYMBOL(cxgb4_port_idx);
1997 void cxgb4_get_tcp_stats(struct pci_dev *pdev, struct tp_tcp_stats *v4,
1998 struct tp_tcp_stats *v6)
2000 struct adapter *adap = pci_get_drvdata(pdev);
2002 spin_lock(&adap->stats_lock);
2003 t4_tp_get_tcp_stats(adap, v4, v6);
2004 spin_unlock(&adap->stats_lock);
2006 EXPORT_SYMBOL(cxgb4_get_tcp_stats);
2008 void cxgb4_iscsi_init(struct net_device *dev, unsigned int tag_mask,
2009 const unsigned int *pgsz_order)
2011 struct adapter *adap = netdev2adap(dev);
2013 t4_write_reg(adap, ULP_RX_ISCSI_TAGMASK_A, tag_mask);
2014 t4_write_reg(adap, ULP_RX_ISCSI_PSZ_A, HPZ0_V(pgsz_order[0]) |
2015 HPZ1_V(pgsz_order[1]) | HPZ2_V(pgsz_order[2]) |
2016 HPZ3_V(pgsz_order[3]));
2018 EXPORT_SYMBOL(cxgb4_iscsi_init);
2020 int cxgb4_flush_eq_cache(struct net_device *dev)
2022 struct adapter *adap = netdev2adap(dev);
2024 return t4_sge_ctxt_flush(adap, adap->mbox);
2026 EXPORT_SYMBOL(cxgb4_flush_eq_cache);
2028 static int read_eq_indices(struct adapter *adap, u16 qid, u16 *pidx, u16 *cidx)
2030 u32 addr = t4_read_reg(adap, SGE_DBQ_CTXT_BADDR_A) + 24 * qid + 8;
2034 spin_lock(&adap->win0_lock);
2035 ret = t4_memory_rw(adap, 0, MEM_EDC0, addr,
2036 sizeof(indices), (__be32 *)&indices,
2038 spin_unlock(&adap->win0_lock);
2040 *cidx = (be64_to_cpu(indices) >> 25) & 0xffff;
2041 *pidx = (be64_to_cpu(indices) >> 9) & 0xffff;
2046 int cxgb4_sync_txq_pidx(struct net_device *dev, u16 qid, u16 pidx,
2049 struct adapter *adap = netdev2adap(dev);
2050 u16 hw_pidx, hw_cidx;
2053 ret = read_eq_indices(adap, qid, &hw_pidx, &hw_cidx);
2057 if (pidx != hw_pidx) {
2061 if (pidx >= hw_pidx)
2062 delta = pidx - hw_pidx;
2064 delta = size - hw_pidx + pidx;
2066 if (is_t4(adap->params.chip))
2067 val = PIDX_V(delta);
2069 val = PIDX_T5_V(delta);
2071 t4_write_reg(adap, MYPF_REG(SGE_PF_KDOORBELL_A),
2077 EXPORT_SYMBOL(cxgb4_sync_txq_pidx);
2079 int cxgb4_read_tpte(struct net_device *dev, u32 stag, __be32 *tpte)
2081 struct adapter *adap;
2082 u32 offset, memtype, memaddr;
2083 u32 edc0_size, edc1_size, mc0_size, mc1_size, size;
2084 u32 edc0_end, edc1_end, mc0_end, mc1_end;
2087 adap = netdev2adap(dev);
2089 offset = ((stag >> 8) * 32) + adap->vres.stag.start;
2091 /* Figure out where the offset lands in the Memory Type/Address scheme.
2092 * This code assumes that the memory is laid out starting at offset 0
2093 * with no breaks as: EDC0, EDC1, MC0, MC1. All cards have both EDC0
2094 * and EDC1. Some cards will have neither MC0 nor MC1, most cards have
2095 * MC0, and some have both MC0 and MC1.
2097 size = t4_read_reg(adap, MA_EDRAM0_BAR_A);
2098 edc0_size = EDRAM0_SIZE_G(size) << 20;
2099 size = t4_read_reg(adap, MA_EDRAM1_BAR_A);
2100 edc1_size = EDRAM1_SIZE_G(size) << 20;
2101 size = t4_read_reg(adap, MA_EXT_MEMORY0_BAR_A);
2102 mc0_size = EXT_MEM0_SIZE_G(size) << 20;
2104 edc0_end = edc0_size;
2105 edc1_end = edc0_end + edc1_size;
2106 mc0_end = edc1_end + mc0_size;
2108 if (offset < edc0_end) {
2111 } else if (offset < edc1_end) {
2113 memaddr = offset - edc0_end;
2115 if (offset < mc0_end) {
2117 memaddr = offset - edc1_end;
2118 } else if (is_t5(adap->params.chip)) {
2119 size = t4_read_reg(adap, MA_EXT_MEMORY1_BAR_A);
2120 mc1_size = EXT_MEM1_SIZE_G(size) << 20;
2121 mc1_end = mc0_end + mc1_size;
2122 if (offset < mc1_end) {
2124 memaddr = offset - mc0_end;
2126 /* offset beyond the end of any memory */
2130 /* T4/T6 only has a single memory channel */
2135 spin_lock(&adap->win0_lock);
2136 ret = t4_memory_rw(adap, 0, memtype, memaddr, 32, tpte, T4_MEMORY_READ);
2137 spin_unlock(&adap->win0_lock);
2141 dev_err(adap->pdev_dev, "stag %#x, offset %#x out of range\n",
2145 EXPORT_SYMBOL(cxgb4_read_tpte);
2147 u64 cxgb4_read_sge_timestamp(struct net_device *dev)
2150 struct adapter *adap;
2152 adap = netdev2adap(dev);
2153 lo = t4_read_reg(adap, SGE_TIMESTAMP_LO_A);
2154 hi = TSVAL_G(t4_read_reg(adap, SGE_TIMESTAMP_HI_A));
2156 return ((u64)hi << 32) | (u64)lo;
2158 EXPORT_SYMBOL(cxgb4_read_sge_timestamp);
2160 int cxgb4_bar2_sge_qregs(struct net_device *dev,
2162 enum cxgb4_bar2_qtype qtype,
2165 unsigned int *pbar2_qid)
2167 return t4_bar2_sge_qregs(netdev2adap(dev),
2169 (qtype == CXGB4_BAR2_QTYPE_EGRESS
2170 ? T4_BAR2_QTYPE_EGRESS
2171 : T4_BAR2_QTYPE_INGRESS),
2176 EXPORT_SYMBOL(cxgb4_bar2_sge_qregs);
2178 static struct pci_driver cxgb4_driver;
2180 static void check_neigh_update(struct neighbour *neigh)
2182 const struct device *parent;
2183 const struct net_device *netdev = neigh->dev;
2185 if (netdev->priv_flags & IFF_802_1Q_VLAN)
2186 netdev = vlan_dev_real_dev(netdev);
2187 parent = netdev->dev.parent;
2188 if (parent && parent->driver == &cxgb4_driver.driver)
2189 t4_l2t_update(dev_get_drvdata(parent), neigh);
2192 static int netevent_cb(struct notifier_block *nb, unsigned long event,
2196 case NETEVENT_NEIGH_UPDATE:
2197 check_neigh_update(data);
2199 case NETEVENT_REDIRECT:
2206 static bool netevent_registered;
2207 static struct notifier_block cxgb4_netevent_nb = {
2208 .notifier_call = netevent_cb
2211 static void drain_db_fifo(struct adapter *adap, int usecs)
2213 u32 v1, v2, lp_count, hp_count;
2216 v1 = t4_read_reg(adap, SGE_DBFIFO_STATUS_A);
2217 v2 = t4_read_reg(adap, SGE_DBFIFO_STATUS2_A);
2218 if (is_t4(adap->params.chip)) {
2219 lp_count = LP_COUNT_G(v1);
2220 hp_count = HP_COUNT_G(v1);
2222 lp_count = LP_COUNT_T5_G(v1);
2223 hp_count = HP_COUNT_T5_G(v2);
2226 if (lp_count == 0 && hp_count == 0)
2228 set_current_state(TASK_UNINTERRUPTIBLE);
2229 schedule_timeout(usecs_to_jiffies(usecs));
2233 static void disable_txq_db(struct sge_txq *q)
2235 unsigned long flags;
2237 spin_lock_irqsave(&q->db_lock, flags);
2239 spin_unlock_irqrestore(&q->db_lock, flags);
2242 static void enable_txq_db(struct adapter *adap, struct sge_txq *q)
2244 spin_lock_irq(&q->db_lock);
2245 if (q->db_pidx_inc) {
2246 /* Make sure that all writes to the TX descriptors
2247 * are committed before we tell HW about them.
2250 t4_write_reg(adap, MYPF_REG(SGE_PF_KDOORBELL_A),
2251 QID_V(q->cntxt_id) | PIDX_V(q->db_pidx_inc));
2255 spin_unlock_irq(&q->db_lock);
2258 static void disable_dbs(struct adapter *adap)
2262 for_each_ethrxq(&adap->sge, i)
2263 disable_txq_db(&adap->sge.ethtxq[i].q);
2264 for_each_ofldrxq(&adap->sge, i)
2265 disable_txq_db(&adap->sge.ofldtxq[i].q);
2266 for_each_port(adap, i)
2267 disable_txq_db(&adap->sge.ctrlq[i].q);
2270 static void enable_dbs(struct adapter *adap)
2274 for_each_ethrxq(&adap->sge, i)
2275 enable_txq_db(adap, &adap->sge.ethtxq[i].q);
2276 for_each_ofldrxq(&adap->sge, i)
2277 enable_txq_db(adap, &adap->sge.ofldtxq[i].q);
2278 for_each_port(adap, i)
2279 enable_txq_db(adap, &adap->sge.ctrlq[i].q);
2282 static void notify_rdma_uld(struct adapter *adap, enum cxgb4_control cmd)
2284 if (adap->uld_handle[CXGB4_ULD_RDMA])
2285 ulds[CXGB4_ULD_RDMA].control(adap->uld_handle[CXGB4_ULD_RDMA],
2289 static void process_db_full(struct work_struct *work)
2291 struct adapter *adap;
2293 adap = container_of(work, struct adapter, db_full_task);
2295 drain_db_fifo(adap, dbfifo_drain_delay);
2297 notify_rdma_uld(adap, CXGB4_CONTROL_DB_EMPTY);
2298 if (CHELSIO_CHIP_VERSION(adap->params.chip) <= CHELSIO_T5)
2299 t4_set_reg_field(adap, SGE_INT_ENABLE3_A,
2300 DBFIFO_HP_INT_F | DBFIFO_LP_INT_F,
2301 DBFIFO_HP_INT_F | DBFIFO_LP_INT_F);
2303 t4_set_reg_field(adap, SGE_INT_ENABLE3_A,
2304 DBFIFO_LP_INT_F, DBFIFO_LP_INT_F);
2307 static void sync_txq_pidx(struct adapter *adap, struct sge_txq *q)
2309 u16 hw_pidx, hw_cidx;
2312 spin_lock_irq(&q->db_lock);
2313 ret = read_eq_indices(adap, (u16)q->cntxt_id, &hw_pidx, &hw_cidx);
2316 if (q->db_pidx != hw_pidx) {
2320 if (q->db_pidx >= hw_pidx)
2321 delta = q->db_pidx - hw_pidx;
2323 delta = q->size - hw_pidx + q->db_pidx;
2325 if (is_t4(adap->params.chip))
2326 val = PIDX_V(delta);
2328 val = PIDX_T5_V(delta);
2330 t4_write_reg(adap, MYPF_REG(SGE_PF_KDOORBELL_A),
2331 QID_V(q->cntxt_id) | val);
2336 spin_unlock_irq(&q->db_lock);
2338 CH_WARN(adap, "DB drop recovery failed.\n");
2340 static void recover_all_queues(struct adapter *adap)
2344 for_each_ethrxq(&adap->sge, i)
2345 sync_txq_pidx(adap, &adap->sge.ethtxq[i].q);
2346 for_each_ofldrxq(&adap->sge, i)
2347 sync_txq_pidx(adap, &adap->sge.ofldtxq[i].q);
2348 for_each_port(adap, i)
2349 sync_txq_pidx(adap, &adap->sge.ctrlq[i].q);
2352 static void process_db_drop(struct work_struct *work)
2354 struct adapter *adap;
2356 adap = container_of(work, struct adapter, db_drop_task);
2358 if (is_t4(adap->params.chip)) {
2359 drain_db_fifo(adap, dbfifo_drain_delay);
2360 notify_rdma_uld(adap, CXGB4_CONTROL_DB_DROP);
2361 drain_db_fifo(adap, dbfifo_drain_delay);
2362 recover_all_queues(adap);
2363 drain_db_fifo(adap, dbfifo_drain_delay);
2365 notify_rdma_uld(adap, CXGB4_CONTROL_DB_EMPTY);
2366 } else if (is_t5(adap->params.chip)) {
2367 u32 dropped_db = t4_read_reg(adap, 0x010ac);
2368 u16 qid = (dropped_db >> 15) & 0x1ffff;
2369 u16 pidx_inc = dropped_db & 0x1fff;
2371 unsigned int bar2_qid;
2374 ret = t4_bar2_sge_qregs(adap, qid, T4_BAR2_QTYPE_EGRESS,
2375 0, &bar2_qoffset, &bar2_qid);
2377 dev_err(adap->pdev_dev, "doorbell drop recovery: "
2378 "qid=%d, pidx_inc=%d\n", qid, pidx_inc);
2380 writel(PIDX_T5_V(pidx_inc) | QID_V(bar2_qid),
2381 adap->bar2 + bar2_qoffset + SGE_UDB_KDOORBELL);
2383 /* Re-enable BAR2 WC */
2384 t4_set_reg_field(adap, 0x10b0, 1<<15, 1<<15);
2387 if (CHELSIO_CHIP_VERSION(adap->params.chip) <= CHELSIO_T5)
2388 t4_set_reg_field(adap, SGE_DOORBELL_CONTROL_A, DROPPED_DB_F, 0);
2391 void t4_db_full(struct adapter *adap)
2393 if (is_t4(adap->params.chip)) {
2395 notify_rdma_uld(adap, CXGB4_CONTROL_DB_FULL);
2396 t4_set_reg_field(adap, SGE_INT_ENABLE3_A,
2397 DBFIFO_HP_INT_F | DBFIFO_LP_INT_F, 0);
2398 queue_work(adap->workq, &adap->db_full_task);
2402 void t4_db_dropped(struct adapter *adap)
2404 if (is_t4(adap->params.chip)) {
2406 notify_rdma_uld(adap, CXGB4_CONTROL_DB_FULL);
2408 queue_work(adap->workq, &adap->db_drop_task);
2411 static void uld_attach(struct adapter *adap, unsigned int uld)
2414 struct cxgb4_lld_info lli;
2417 lli.pdev = adap->pdev;
2419 lli.l2t = adap->l2t;
2420 lli.tids = &adap->tids;
2421 lli.ports = adap->port;
2422 lli.vr = &adap->vres;
2423 lli.mtus = adap->params.mtus;
2424 if (uld == CXGB4_ULD_RDMA) {
2425 lli.rxq_ids = adap->sge.rdma_rxq;
2426 lli.ciq_ids = adap->sge.rdma_ciq;
2427 lli.nrxq = adap->sge.rdmaqs;
2428 lli.nciq = adap->sge.rdmaciqs;
2429 } else if (uld == CXGB4_ULD_ISCSI) {
2430 lli.rxq_ids = adap->sge.ofld_rxq;
2431 lli.nrxq = adap->sge.ofldqsets;
2433 lli.ntxq = adap->sge.ofldqsets;
2434 lli.nchan = adap->params.nports;
2435 lli.nports = adap->params.nports;
2436 lli.wr_cred = adap->params.ofldq_wr_cred;
2437 lli.adapter_type = adap->params.chip;
2438 lli.iscsi_iolen = MAXRXDATA_G(t4_read_reg(adap, TP_PARA_REG2_A));
2439 lli.cclk_ps = 1000000000 / adap->params.vpd.cclk;
2440 lli.udb_density = 1 << adap->params.sge.eq_qpp;
2441 lli.ucq_density = 1 << adap->params.sge.iq_qpp;
2442 lli.filt_mode = adap->params.tp.vlan_pri_map;
2443 /* MODQ_REQ_MAP sets queues 0-3 to chan 0-3 */
2444 for (i = 0; i < NCHAN; i++)
2446 lli.gts_reg = adap->regs + MYPF_REG(SGE_PF_GTS_A);
2447 lli.db_reg = adap->regs + MYPF_REG(SGE_PF_KDOORBELL_A);
2448 lli.fw_vers = adap->params.fw_vers;
2449 lli.dbfifo_int_thresh = dbfifo_int_thresh;
2450 lli.sge_ingpadboundary = adap->sge.fl_align;
2451 lli.sge_egrstatuspagesize = adap->sge.stat_len;
2452 lli.sge_pktshift = adap->sge.pktshift;
2453 lli.enable_fw_ofld_conn = adap->flags & FW_OFLD_CONN;
2454 lli.max_ordird_qp = adap->params.max_ordird_qp;
2455 lli.max_ird_adapter = adap->params.max_ird_adapter;
2456 lli.ulptx_memwrite_dsgl = adap->params.ulptx_memwrite_dsgl;
2457 lli.nodeid = dev_to_node(adap->pdev_dev);
2459 handle = ulds[uld].add(&lli);
2460 if (IS_ERR(handle)) {
2461 dev_warn(adap->pdev_dev,
2462 "could not attach to the %s driver, error %ld\n",
2463 uld_str[uld], PTR_ERR(handle));
2467 adap->uld_handle[uld] = handle;
2469 if (!netevent_registered) {
2470 register_netevent_notifier(&cxgb4_netevent_nb);
2471 netevent_registered = true;
2474 if (adap->flags & FULL_INIT_DONE)
2475 ulds[uld].state_change(handle, CXGB4_STATE_UP);
2478 static void attach_ulds(struct adapter *adap)
2482 spin_lock(&adap_rcu_lock);
2483 list_add_tail_rcu(&adap->rcu_node, &adap_rcu_list);
2484 spin_unlock(&adap_rcu_lock);
2486 mutex_lock(&uld_mutex);
2487 list_add_tail(&adap->list_node, &adapter_list);
2488 for (i = 0; i < CXGB4_ULD_MAX; i++)
2490 uld_attach(adap, i);
2491 mutex_unlock(&uld_mutex);
2494 static void detach_ulds(struct adapter *adap)
2498 mutex_lock(&uld_mutex);
2499 list_del(&adap->list_node);
2500 for (i = 0; i < CXGB4_ULD_MAX; i++)
2501 if (adap->uld_handle[i]) {
2502 ulds[i].state_change(adap->uld_handle[i],
2503 CXGB4_STATE_DETACH);
2504 adap->uld_handle[i] = NULL;
2506 if (netevent_registered && list_empty(&adapter_list)) {
2507 unregister_netevent_notifier(&cxgb4_netevent_nb);
2508 netevent_registered = false;
2510 mutex_unlock(&uld_mutex);
2512 spin_lock(&adap_rcu_lock);
2513 list_del_rcu(&adap->rcu_node);
2514 spin_unlock(&adap_rcu_lock);
2517 static void notify_ulds(struct adapter *adap, enum cxgb4_state new_state)
2521 mutex_lock(&uld_mutex);
2522 for (i = 0; i < CXGB4_ULD_MAX; i++)
2523 if (adap->uld_handle[i])
2524 ulds[i].state_change(adap->uld_handle[i], new_state);
2525 mutex_unlock(&uld_mutex);
2529 * cxgb4_register_uld - register an upper-layer driver
2530 * @type: the ULD type
2531 * @p: the ULD methods
2533 * Registers an upper-layer driver with this driver and notifies the ULD
2534 * about any presently available devices that support its type. Returns
2535 * %-EBUSY if a ULD of the same type is already registered.
2537 int cxgb4_register_uld(enum cxgb4_uld type, const struct cxgb4_uld_info *p)
2540 struct adapter *adap;
2542 if (type >= CXGB4_ULD_MAX)
2544 mutex_lock(&uld_mutex);
2545 if (ulds[type].add) {
2550 list_for_each_entry(adap, &adapter_list, list_node)
2551 uld_attach(adap, type);
2552 out: mutex_unlock(&uld_mutex);
2555 EXPORT_SYMBOL(cxgb4_register_uld);
2558 * cxgb4_unregister_uld - unregister an upper-layer driver
2559 * @type: the ULD type
2561 * Unregisters an existing upper-layer driver.
2563 int cxgb4_unregister_uld(enum cxgb4_uld type)
2565 struct adapter *adap;
2567 if (type >= CXGB4_ULD_MAX)
2569 mutex_lock(&uld_mutex);
2570 list_for_each_entry(adap, &adapter_list, list_node)
2571 adap->uld_handle[type] = NULL;
2572 ulds[type].add = NULL;
2573 mutex_unlock(&uld_mutex);
2576 EXPORT_SYMBOL(cxgb4_unregister_uld);
2578 #if IS_ENABLED(CONFIG_IPV6)
2579 static int cxgb4_inet6addr_handler(struct notifier_block *this,
2580 unsigned long event, void *data)
2582 struct inet6_ifaddr *ifa = data;
2583 struct net_device *event_dev = ifa->idev->dev;
2584 const struct device *parent = NULL;
2585 #if IS_ENABLED(CONFIG_BONDING)
2586 struct adapter *adap;
2588 if (event_dev->priv_flags & IFF_802_1Q_VLAN)
2589 event_dev = vlan_dev_real_dev(event_dev);
2590 #if IS_ENABLED(CONFIG_BONDING)
2591 if (event_dev->flags & IFF_MASTER) {
2592 list_for_each_entry(adap, &adapter_list, list_node) {
2595 cxgb4_clip_get(adap->port[0],
2596 (const u32 *)ifa, 1);
2599 cxgb4_clip_release(adap->port[0],
2600 (const u32 *)ifa, 1);
2611 parent = event_dev->dev.parent;
2613 if (parent && parent->driver == &cxgb4_driver.driver) {
2616 cxgb4_clip_get(event_dev, (const u32 *)ifa, 1);
2619 cxgb4_clip_release(event_dev, (const u32 *)ifa, 1);
2628 static bool inet6addr_registered;
2629 static struct notifier_block cxgb4_inet6addr_notifier = {
2630 .notifier_call = cxgb4_inet6addr_handler
2633 static void update_clip(const struct adapter *adap)
2636 struct net_device *dev;
2641 for (i = 0; i < MAX_NPORTS; i++) {
2642 dev = adap->port[i];
2646 ret = cxgb4_update_root_dev_clip(dev);
2653 #endif /* IS_ENABLED(CONFIG_IPV6) */
2656 * cxgb_up - enable the adapter
2657 * @adap: adapter being enabled
2659 * Called when the first port is enabled, this function performs the
2660 * actions necessary to make an adapter operational, such as completing
2661 * the initialization of HW modules, and enabling interrupts.
2663 * Must be called with the rtnl lock held.
2665 static int cxgb_up(struct adapter *adap)
2669 err = setup_sge_queues(adap);
2672 err = setup_rss(adap);
2676 if (adap->flags & USING_MSIX) {
2677 name_msix_vecs(adap);
2678 err = request_irq(adap->msix_info[0].vec, t4_nondata_intr, 0,
2679 adap->msix_info[0].desc, adap);
2683 err = request_msix_queue_irqs(adap);
2685 free_irq(adap->msix_info[0].vec, adap);
2689 err = request_irq(adap->pdev->irq, t4_intr_handler(adap),
2690 (adap->flags & USING_MSI) ? 0 : IRQF_SHARED,
2691 adap->port[0]->name, adap);
2697 t4_intr_enable(adap);
2698 adap->flags |= FULL_INIT_DONE;
2699 notify_ulds(adap, CXGB4_STATE_UP);
2700 #if IS_ENABLED(CONFIG_IPV6)
2706 dev_err(adap->pdev_dev, "request_irq failed, err %d\n", err);
2708 t4_free_sge_resources(adap);
2712 static void cxgb_down(struct adapter *adapter)
2714 cancel_work_sync(&adapter->tid_release_task);
2715 cancel_work_sync(&adapter->db_full_task);
2716 cancel_work_sync(&adapter->db_drop_task);
2717 adapter->tid_release_task_busy = false;
2718 adapter->tid_release_head = NULL;
2720 t4_sge_stop(adapter);
2721 t4_free_sge_resources(adapter);
2722 adapter->flags &= ~FULL_INIT_DONE;
2726 * net_device operations
2728 static int cxgb_open(struct net_device *dev)
2731 struct port_info *pi = netdev_priv(dev);
2732 struct adapter *adapter = pi->adapter;
2734 netif_carrier_off(dev);
2736 if (!(adapter->flags & FULL_INIT_DONE)) {
2737 err = cxgb_up(adapter);
2742 err = link_start(dev);
2744 netif_tx_start_all_queues(dev);
2748 static int cxgb_close(struct net_device *dev)
2750 struct port_info *pi = netdev_priv(dev);
2751 struct adapter *adapter = pi->adapter;
2753 netif_tx_stop_all_queues(dev);
2754 netif_carrier_off(dev);
2755 return t4_enable_vi(adapter, adapter->pf, pi->viid, false, false);
2758 /* Return an error number if the indicated filter isn't writable ...
2760 static int writable_filter(struct filter_entry *f)
2770 /* Delete the filter at the specified index (if valid). The checks for all
2771 * the common problems with doing this like the filter being locked, currently
2772 * pending in another operation, etc.
2774 static int delete_filter(struct adapter *adapter, unsigned int fidx)
2776 struct filter_entry *f;
2779 if (fidx >= adapter->tids.nftids + adapter->tids.nsftids)
2782 f = &adapter->tids.ftid_tab[fidx];
2783 ret = writable_filter(f);
2787 return del_filter_wr(adapter, fidx);
2792 int cxgb4_create_server_filter(const struct net_device *dev, unsigned int stid,
2793 __be32 sip, __be16 sport, __be16 vlan,
2794 unsigned int queue, unsigned char port, unsigned char mask)
2797 struct filter_entry *f;
2798 struct adapter *adap;
2802 adap = netdev2adap(dev);
2804 /* Adjust stid to correct filter index */
2805 stid -= adap->tids.sftid_base;
2806 stid += adap->tids.nftids;
2808 /* Check to make sure the filter requested is writable ...
2810 f = &adap->tids.ftid_tab[stid];
2811 ret = writable_filter(f);
2815 /* Clear out any old resources being used by the filter before
2816 * we start constructing the new filter.
2819 clear_filter(adap, f);
2821 /* Clear out filter specifications */
2822 memset(&f->fs, 0, sizeof(struct ch_filter_specification));
2823 f->fs.val.lport = cpu_to_be16(sport);
2824 f->fs.mask.lport = ~0;
2826 if ((val[0] | val[1] | val[2] | val[3]) != 0) {
2827 for (i = 0; i < 4; i++) {
2828 f->fs.val.lip[i] = val[i];
2829 f->fs.mask.lip[i] = ~0;
2831 if (adap->params.tp.vlan_pri_map & PORT_F) {
2832 f->fs.val.iport = port;
2833 f->fs.mask.iport = mask;
2837 if (adap->params.tp.vlan_pri_map & PROTOCOL_F) {
2838 f->fs.val.proto = IPPROTO_TCP;
2839 f->fs.mask.proto = ~0;
2844 /* Mark filter as locked */
2848 ret = set_filter_wr(adap, stid);
2850 clear_filter(adap, f);
2856 EXPORT_SYMBOL(cxgb4_create_server_filter);
2858 int cxgb4_remove_server_filter(const struct net_device *dev, unsigned int stid,
2859 unsigned int queue, bool ipv6)
2862 struct filter_entry *f;
2863 struct adapter *adap;
2865 adap = netdev2adap(dev);
2867 /* Adjust stid to correct filter index */
2868 stid -= adap->tids.sftid_base;
2869 stid += adap->tids.nftids;
2871 f = &adap->tids.ftid_tab[stid];
2872 /* Unlock the filter */
2875 ret = delete_filter(adap, stid);
2881 EXPORT_SYMBOL(cxgb4_remove_server_filter);
2883 static struct rtnl_link_stats64 *cxgb_get_stats(struct net_device *dev,
2884 struct rtnl_link_stats64 *ns)
2886 struct port_stats stats;
2887 struct port_info *p = netdev_priv(dev);
2888 struct adapter *adapter = p->adapter;
2890 /* Block retrieving statistics during EEH error
2891 * recovery. Otherwise, the recovery might fail
2892 * and the PCI device will be removed permanently
2894 spin_lock(&adapter->stats_lock);
2895 if (!netif_device_present(dev)) {
2896 spin_unlock(&adapter->stats_lock);
2899 t4_get_port_stats_offset(adapter, p->tx_chan, &stats,
2901 spin_unlock(&adapter->stats_lock);
2903 ns->tx_bytes = stats.tx_octets;
2904 ns->tx_packets = stats.tx_frames;
2905 ns->rx_bytes = stats.rx_octets;
2906 ns->rx_packets = stats.rx_frames;
2907 ns->multicast = stats.rx_mcast_frames;
2909 /* detailed rx_errors */
2910 ns->rx_length_errors = stats.rx_jabber + stats.rx_too_long +
2912 ns->rx_over_errors = 0;
2913 ns->rx_crc_errors = stats.rx_fcs_err;
2914 ns->rx_frame_errors = stats.rx_symbol_err;
2915 ns->rx_fifo_errors = stats.rx_ovflow0 + stats.rx_ovflow1 +
2916 stats.rx_ovflow2 + stats.rx_ovflow3 +
2917 stats.rx_trunc0 + stats.rx_trunc1 +
2918 stats.rx_trunc2 + stats.rx_trunc3;
2919 ns->rx_missed_errors = 0;
2921 /* detailed tx_errors */
2922 ns->tx_aborted_errors = 0;
2923 ns->tx_carrier_errors = 0;
2924 ns->tx_fifo_errors = 0;
2925 ns->tx_heartbeat_errors = 0;
2926 ns->tx_window_errors = 0;
2928 ns->tx_errors = stats.tx_error_frames;
2929 ns->rx_errors = stats.rx_symbol_err + stats.rx_fcs_err +
2930 ns->rx_length_errors + stats.rx_len_err + ns->rx_fifo_errors;
2934 static int cxgb_ioctl(struct net_device *dev, struct ifreq *req, int cmd)
2937 int ret = 0, prtad, devad;
2938 struct port_info *pi = netdev_priv(dev);
2939 struct mii_ioctl_data *data = (struct mii_ioctl_data *)&req->ifr_data;
2943 if (pi->mdio_addr < 0)
2945 data->phy_id = pi->mdio_addr;
2949 if (mdio_phy_id_is_c45(data->phy_id)) {
2950 prtad = mdio_phy_id_prtad(data->phy_id);
2951 devad = mdio_phy_id_devad(data->phy_id);
2952 } else if (data->phy_id < 32) {
2953 prtad = data->phy_id;
2955 data->reg_num &= 0x1f;
2959 mbox = pi->adapter->pf;
2960 if (cmd == SIOCGMIIREG)
2961 ret = t4_mdio_rd(pi->adapter, mbox, prtad, devad,
2962 data->reg_num, &data->val_out);
2964 ret = t4_mdio_wr(pi->adapter, mbox, prtad, devad,
2965 data->reg_num, data->val_in);
2968 return copy_to_user(req->ifr_data, &pi->tstamp_config,
2969 sizeof(pi->tstamp_config)) ?
2972 if (copy_from_user(&pi->tstamp_config, req->ifr_data,
2973 sizeof(pi->tstamp_config)))
2976 switch (pi->tstamp_config.rx_filter) {
2977 case HWTSTAMP_FILTER_NONE:
2978 pi->rxtstamp = false;
2980 case HWTSTAMP_FILTER_ALL:
2981 pi->rxtstamp = true;
2984 pi->tstamp_config.rx_filter = HWTSTAMP_FILTER_NONE;
2988 return copy_to_user(req->ifr_data, &pi->tstamp_config,
2989 sizeof(pi->tstamp_config)) ?
2997 static void cxgb_set_rxmode(struct net_device *dev)
2999 /* unfortunately we can't return errors to the stack */
3000 set_rxmode(dev, -1, false);
3003 static int cxgb_change_mtu(struct net_device *dev, int new_mtu)
3006 struct port_info *pi = netdev_priv(dev);
3008 if (new_mtu < 81 || new_mtu > MAX_MTU) /* accommodate SACK */
3010 ret = t4_set_rxmode(pi->adapter, pi->adapter->pf, pi->viid, new_mtu, -1,
3017 static int cxgb_set_mac_addr(struct net_device *dev, void *p)
3020 struct sockaddr *addr = p;
3021 struct port_info *pi = netdev_priv(dev);
3023 if (!is_valid_ether_addr(addr->sa_data))
3024 return -EADDRNOTAVAIL;
3026 ret = t4_change_mac(pi->adapter, pi->adapter->pf, pi->viid,
3027 pi->xact_addr_filt, addr->sa_data, true, true);
3031 memcpy(dev->dev_addr, addr->sa_data, dev->addr_len);
3032 pi->xact_addr_filt = ret;
3036 #ifdef CONFIG_NET_POLL_CONTROLLER
3037 static void cxgb_netpoll(struct net_device *dev)
3039 struct port_info *pi = netdev_priv(dev);
3040 struct adapter *adap = pi->adapter;
3042 if (adap->flags & USING_MSIX) {
3044 struct sge_eth_rxq *rx = &adap->sge.ethrxq[pi->first_qset];
3046 for (i = pi->nqsets; i; i--, rx++)
3047 t4_sge_intr_msix(0, &rx->rspq);
3049 t4_intr_handler(adap)(0, adap);
3053 static const struct net_device_ops cxgb4_netdev_ops = {
3054 .ndo_open = cxgb_open,
3055 .ndo_stop = cxgb_close,
3056 .ndo_start_xmit = t4_eth_xmit,
3057 .ndo_select_queue = cxgb_select_queue,
3058 .ndo_get_stats64 = cxgb_get_stats,
3059 .ndo_set_rx_mode = cxgb_set_rxmode,
3060 .ndo_set_mac_address = cxgb_set_mac_addr,
3061 .ndo_set_features = cxgb_set_features,
3062 .ndo_validate_addr = eth_validate_addr,
3063 .ndo_do_ioctl = cxgb_ioctl,
3064 .ndo_change_mtu = cxgb_change_mtu,
3065 #ifdef CONFIG_NET_POLL_CONTROLLER
3066 .ndo_poll_controller = cxgb_netpoll,
3068 #ifdef CONFIG_CHELSIO_T4_FCOE
3069 .ndo_fcoe_enable = cxgb_fcoe_enable,
3070 .ndo_fcoe_disable = cxgb_fcoe_disable,
3071 #endif /* CONFIG_CHELSIO_T4_FCOE */
3072 #ifdef CONFIG_NET_RX_BUSY_POLL
3073 .ndo_busy_poll = cxgb_busy_poll,
3078 void t4_fatal_err(struct adapter *adap)
3080 t4_set_reg_field(adap, SGE_CONTROL_A, GLOBALENABLE_F, 0);
3081 t4_intr_disable(adap);
3082 dev_alert(adap->pdev_dev, "encountered fatal error, adapter stopped\n");
3085 static void setup_memwin(struct adapter *adap)
3087 u32 nic_win_base = t4_get_util_window(adap);
3089 t4_setup_memwin(adap, nic_win_base, MEMWIN_NIC);
3092 static void setup_memwin_rdma(struct adapter *adap)
3094 if (adap->vres.ocq.size) {
3098 start = t4_read_pcie_cfg4(adap, PCI_BASE_ADDRESS_2);
3099 start &= PCI_BASE_ADDRESS_MEM_MASK;
3100 start += OCQ_WIN_OFFSET(adap->pdev, &adap->vres);
3101 sz_kb = roundup_pow_of_two(adap->vres.ocq.size) >> 10;
3103 PCIE_MEM_ACCESS_REG(PCIE_MEM_ACCESS_BASE_WIN_A, 3),
3104 start | BIR_V(1) | WINDOW_V(ilog2(sz_kb)));
3106 PCIE_MEM_ACCESS_REG(PCIE_MEM_ACCESS_OFFSET_A, 3),
3107 adap->vres.ocq.start);
3109 PCIE_MEM_ACCESS_REG(PCIE_MEM_ACCESS_OFFSET_A, 3));
3113 static int adap_init1(struct adapter *adap, struct fw_caps_config_cmd *c)
3118 /* get device capabilities */
3119 memset(c, 0, sizeof(*c));
3120 c->op_to_write = htonl(FW_CMD_OP_V(FW_CAPS_CONFIG_CMD) |
3121 FW_CMD_REQUEST_F | FW_CMD_READ_F);
3122 c->cfvalid_to_len16 = htonl(FW_LEN16(*c));
3123 ret = t4_wr_mbox(adap, adap->mbox, c, sizeof(*c), c);
3127 /* select capabilities we'll be using */
3128 if (c->niccaps & htons(FW_CAPS_CONFIG_NIC_VM)) {
3130 c->niccaps ^= htons(FW_CAPS_CONFIG_NIC_VM);
3132 c->niccaps = htons(FW_CAPS_CONFIG_NIC_VM);
3133 } else if (vf_acls) {
3134 dev_err(adap->pdev_dev, "virtualization ACLs not supported");
3137 c->op_to_write = htonl(FW_CMD_OP_V(FW_CAPS_CONFIG_CMD) |
3138 FW_CMD_REQUEST_F | FW_CMD_WRITE_F);
3139 ret = t4_wr_mbox(adap, adap->mbox, c, sizeof(*c), NULL);
3143 ret = t4_config_glbl_rss(adap, adap->pf,
3144 FW_RSS_GLB_CONFIG_CMD_MODE_BASICVIRTUAL,
3145 FW_RSS_GLB_CONFIG_CMD_TNLMAPEN_F |
3146 FW_RSS_GLB_CONFIG_CMD_TNLALLLKP_F);
3150 ret = t4_cfg_pfvf(adap, adap->mbox, adap->pf, 0, adap->sge.egr_sz, 64,
3151 MAX_INGQ, 0, 0, 4, 0xf, 0xf, 16, FW_CMD_CAP_PF,
3158 /* tweak some settings */
3159 t4_write_reg(adap, TP_SHIFT_CNT_A, 0x64f8849);
3160 t4_write_reg(adap, ULP_RX_TDDP_PSZ_A, HPZ0_V(PAGE_SHIFT - 12));
3161 t4_write_reg(adap, TP_PIO_ADDR_A, TP_INGRESS_CONFIG_A);
3162 v = t4_read_reg(adap, TP_PIO_DATA_A);
3163 t4_write_reg(adap, TP_PIO_DATA_A, v & ~CSUM_HAS_PSEUDO_HDR_F);
3165 /* first 4 Tx modulation queues point to consecutive Tx channels */
3166 adap->params.tp.tx_modq_map = 0xE4;
3167 t4_write_reg(adap, TP_TX_MOD_QUEUE_REQ_MAP_A,
3168 TX_MOD_QUEUE_REQ_MAP_V(adap->params.tp.tx_modq_map));
3170 /* associate each Tx modulation queue with consecutive Tx channels */
3172 t4_write_indirect(adap, TP_PIO_ADDR_A, TP_PIO_DATA_A,
3173 &v, 1, TP_TX_SCHED_HDR_A);
3174 t4_write_indirect(adap, TP_PIO_ADDR_A, TP_PIO_DATA_A,
3175 &v, 1, TP_TX_SCHED_FIFO_A);
3176 t4_write_indirect(adap, TP_PIO_ADDR_A, TP_PIO_DATA_A,
3177 &v, 1, TP_TX_SCHED_PCMD_A);
3179 #define T4_TX_MODQ_10G_WEIGHT_DEFAULT 16 /* in KB units */
3180 if (is_offload(adap)) {
3181 t4_write_reg(adap, TP_TX_MOD_QUEUE_WEIGHT0_A,
3182 TX_MODQ_WEIGHT0_V(T4_TX_MODQ_10G_WEIGHT_DEFAULT) |
3183 TX_MODQ_WEIGHT1_V(T4_TX_MODQ_10G_WEIGHT_DEFAULT) |
3184 TX_MODQ_WEIGHT2_V(T4_TX_MODQ_10G_WEIGHT_DEFAULT) |
3185 TX_MODQ_WEIGHT3_V(T4_TX_MODQ_10G_WEIGHT_DEFAULT));
3186 t4_write_reg(adap, TP_TX_MOD_CHANNEL_WEIGHT_A,
3187 TX_MODQ_WEIGHT0_V(T4_TX_MODQ_10G_WEIGHT_DEFAULT) |
3188 TX_MODQ_WEIGHT1_V(T4_TX_MODQ_10G_WEIGHT_DEFAULT) |
3189 TX_MODQ_WEIGHT2_V(T4_TX_MODQ_10G_WEIGHT_DEFAULT) |
3190 TX_MODQ_WEIGHT3_V(T4_TX_MODQ_10G_WEIGHT_DEFAULT));
3193 /* get basic stuff going */
3194 return t4_early_init(adap, adap->pf);
3198 * Max # of ATIDs. The absolute HW max is 16K but we keep it lower.
3200 #define MAX_ATIDS 8192U
3203 * Phase 0 of initialization: contact FW, obtain config, perform basic init.
3205 * If the firmware we're dealing with has Configuration File support, then
3206 * we use that to perform all configuration
3210 * Tweak configuration based on module parameters, etc. Most of these have
3211 * defaults assigned to them by Firmware Configuration Files (if we're using
3212 * them) but need to be explicitly set if we're using hard-coded
3213 * initialization. But even in the case of using Firmware Configuration
3214 * Files, we'd like to expose the ability to change these via module
3215 * parameters so these are essentially common tweaks/settings for
3216 * Configuration Files and hard-coded initialization ...
3218 static int adap_init0_tweaks(struct adapter *adapter)
3221 * Fix up various Host-Dependent Parameters like Page Size, Cache
3222 * Line Size, etc. The firmware default is for a 4KB Page Size and
3223 * 64B Cache Line Size ...
3225 t4_fixup_host_params(adapter, PAGE_SIZE, L1_CACHE_BYTES);
3228 * Process module parameters which affect early initialization.
3230 if (rx_dma_offset != 2 && rx_dma_offset != 0) {
3231 dev_err(&adapter->pdev->dev,
3232 "Ignoring illegal rx_dma_offset=%d, using 2\n",
3236 t4_set_reg_field(adapter, SGE_CONTROL_A,
3237 PKTSHIFT_V(PKTSHIFT_M),
3238 PKTSHIFT_V(rx_dma_offset));
3241 * Don't include the "IP Pseudo Header" in CPL_RX_PKT checksums: Linux
3242 * adds the pseudo header itself.
3244 t4_tp_wr_bits_indirect(adapter, TP_INGRESS_CONFIG_A,
3245 CSUM_HAS_PSEUDO_HDR_F, 0);
3250 /* 10Gb/s-BT PHY Support. chip-external 10Gb/s-BT PHYs are complex chips
3251 * unto themselves and they contain their own firmware to perform their
3254 static int phy_aq1202_version(const u8 *phy_fw_data,
3259 /* At offset 0x8 you're looking for the primary image's
3260 * starting offset which is 3 Bytes wide
3262 * At offset 0xa of the primary image, you look for the offset
3263 * of the DRAM segment which is 3 Bytes wide.
3265 * The FW version is at offset 0x27e of the DRAM and is 2 Bytes
3268 #define be16(__p) (((__p)[0] << 8) | (__p)[1])
3269 #define le16(__p) ((__p)[0] | ((__p)[1] << 8))
3270 #define le24(__p) (le16(__p) | ((__p)[2] << 16))
3272 offset = le24(phy_fw_data + 0x8) << 12;
3273 offset = le24(phy_fw_data + offset + 0xa);
3274 return be16(phy_fw_data + offset + 0x27e);
3281 static struct info_10gbt_phy_fw {
3282 unsigned int phy_fw_id; /* PCI Device ID */
3283 char *phy_fw_file; /* /lib/firmware/ PHY Firmware file */
3284 int (*phy_fw_version)(const u8 *phy_fw_data, size_t phy_fw_size);
3285 int phy_flash; /* Has FLASH for PHY Firmware */
3286 } phy_info_array[] = {
3288 PHY_AQ1202_DEVICEID,
3289 PHY_AQ1202_FIRMWARE,
3294 PHY_BCM84834_DEVICEID,
3295 PHY_BCM84834_FIRMWARE,
3302 static struct info_10gbt_phy_fw *find_phy_info(int devid)
3306 for (i = 0; i < ARRAY_SIZE(phy_info_array); i++) {
3307 if (phy_info_array[i].phy_fw_id == devid)
3308 return &phy_info_array[i];
3313 /* Handle updating of chip-external 10Gb/s-BT PHY firmware. This needs to
3314 * happen after the FW_RESET_CMD but before the FW_INITIALIZE_CMD. On error
3315 * we return a negative error number. If we transfer new firmware we return 1
3316 * (from t4_load_phy_fw()). If we don't do anything we return 0.
3318 static int adap_init0_phy(struct adapter *adap)
3320 const struct firmware *phyf;
3322 struct info_10gbt_phy_fw *phy_info;
3324 /* Use the device ID to determine which PHY file to flash.
3326 phy_info = find_phy_info(adap->pdev->device);
3328 dev_warn(adap->pdev_dev,
3329 "No PHY Firmware file found for this PHY\n");
3333 /* If we have a T4 PHY firmware file under /lib/firmware/cxgb4/, then
3334 * use that. The adapter firmware provides us with a memory buffer
3335 * where we can load a PHY firmware file from the host if we want to
3336 * override the PHY firmware File in flash.
3338 ret = request_firmware_direct(&phyf, phy_info->phy_fw_file,
3341 /* For adapters without FLASH attached to PHY for their
3342 * firmware, it's obviously a fatal error if we can't get the
3343 * firmware to the adapter. For adapters with PHY firmware
3344 * FLASH storage, it's worth a warning if we can't find the
3345 * PHY Firmware but we'll neuter the error ...
3347 dev_err(adap->pdev_dev, "unable to find PHY Firmware image "
3348 "/lib/firmware/%s, error %d\n",
3349 phy_info->phy_fw_file, -ret);
3350 if (phy_info->phy_flash) {
3351 int cur_phy_fw_ver = 0;
3353 t4_phy_fw_ver(adap, &cur_phy_fw_ver);
3354 dev_warn(adap->pdev_dev, "continuing with, on-adapter "
3355 "FLASH copy, version %#x\n", cur_phy_fw_ver);
3362 /* Load PHY Firmware onto adapter.
3364 ret = t4_load_phy_fw(adap, MEMWIN_NIC, &adap->win0_lock,
3365 phy_info->phy_fw_version,
3366 (u8 *)phyf->data, phyf->size);
3368 dev_err(adap->pdev_dev, "PHY Firmware transfer error %d\n",
3371 int new_phy_fw_ver = 0;
3373 if (phy_info->phy_fw_version)
3374 new_phy_fw_ver = phy_info->phy_fw_version(phyf->data,
3376 dev_info(adap->pdev_dev, "Successfully transferred PHY "
3377 "Firmware /lib/firmware/%s, version %#x\n",
3378 phy_info->phy_fw_file, new_phy_fw_ver);
3381 release_firmware(phyf);
3387 * Attempt to initialize the adapter via a Firmware Configuration File.
3389 static int adap_init0_config(struct adapter *adapter, int reset)
3391 struct fw_caps_config_cmd caps_cmd;
3392 const struct firmware *cf;
3393 unsigned long mtype = 0, maddr = 0;
3394 u32 finiver, finicsum, cfcsum;
3396 int config_issued = 0;
3397 char *fw_config_file, fw_config_file_path[256];
3398 char *config_name = NULL;
3401 * Reset device if necessary.
3404 ret = t4_fw_reset(adapter, adapter->mbox,
3405 PIORSTMODE_F | PIORST_F);
3410 /* If this is a 10Gb/s-BT adapter make sure the chip-external
3411 * 10Gb/s-BT PHYs have up-to-date firmware. Note that this step needs
3412 * to be performed after any global adapter RESET above since some
3413 * PHYs only have local RAM copies of the PHY firmware.
3415 if (is_10gbt_device(adapter->pdev->device)) {
3416 ret = adap_init0_phy(adapter);
3421 * If we have a T4 configuration file under /lib/firmware/cxgb4/,
3422 * then use that. Otherwise, use the configuration file stored
3423 * in the adapter flash ...
3425 switch (CHELSIO_CHIP_VERSION(adapter->params.chip)) {
3427 fw_config_file = FW4_CFNAME;
3430 fw_config_file = FW5_CFNAME;
3433 fw_config_file = FW6_CFNAME;
3436 dev_err(adapter->pdev_dev, "Device %d is not supported\n",
3437 adapter->pdev->device);
3442 ret = request_firmware(&cf, fw_config_file, adapter->pdev_dev);
3444 config_name = "On FLASH";
3445 mtype = FW_MEMTYPE_CF_FLASH;
3446 maddr = t4_flash_cfg_addr(adapter);
3448 u32 params[7], val[7];
3450 sprintf(fw_config_file_path,
3451 "/lib/firmware/%s", fw_config_file);
3452 config_name = fw_config_file_path;
3454 if (cf->size >= FLASH_CFG_MAX_SIZE)
3457 params[0] = (FW_PARAMS_MNEM_V(FW_PARAMS_MNEM_DEV) |
3458 FW_PARAMS_PARAM_X_V(FW_PARAMS_PARAM_DEV_CF));
3459 ret = t4_query_params(adapter, adapter->mbox,
3460 adapter->pf, 0, 1, params, val);
3463 * For t4_memory_rw() below addresses and
3464 * sizes have to be in terms of multiples of 4
3465 * bytes. So, if the Configuration File isn't
3466 * a multiple of 4 bytes in length we'll have
3467 * to write that out separately since we can't
3468 * guarantee that the bytes following the
3469 * residual byte in the buffer returned by
3470 * request_firmware() are zeroed out ...
3472 size_t resid = cf->size & 0x3;
3473 size_t size = cf->size & ~0x3;
3474 __be32 *data = (__be32 *)cf->data;
3476 mtype = FW_PARAMS_PARAM_Y_G(val[0]);
3477 maddr = FW_PARAMS_PARAM_Z_G(val[0]) << 16;
3479 spin_lock(&adapter->win0_lock);
3480 ret = t4_memory_rw(adapter, 0, mtype, maddr,
3481 size, data, T4_MEMORY_WRITE);
3482 if (ret == 0 && resid != 0) {
3489 last.word = data[size >> 2];
3490 for (i = resid; i < 4; i++)
3492 ret = t4_memory_rw(adapter, 0, mtype,
3497 spin_unlock(&adapter->win0_lock);
3501 release_firmware(cf);
3507 * Issue a Capability Configuration command to the firmware to get it
3508 * to parse the Configuration File. We don't use t4_fw_config_file()
3509 * because we want the ability to modify various features after we've
3510 * processed the configuration file ...
3512 memset(&caps_cmd, 0, sizeof(caps_cmd));
3513 caps_cmd.op_to_write =
3514 htonl(FW_CMD_OP_V(FW_CAPS_CONFIG_CMD) |
3517 caps_cmd.cfvalid_to_len16 =
3518 htonl(FW_CAPS_CONFIG_CMD_CFVALID_F |
3519 FW_CAPS_CONFIG_CMD_MEMTYPE_CF_V(mtype) |
3520 FW_CAPS_CONFIG_CMD_MEMADDR64K_CF_V(maddr >> 16) |
3521 FW_LEN16(caps_cmd));
3522 ret = t4_wr_mbox(adapter, adapter->mbox, &caps_cmd, sizeof(caps_cmd),
3525 /* If the CAPS_CONFIG failed with an ENOENT (for a Firmware
3526 * Configuration File in FLASH), our last gasp effort is to use the
3527 * Firmware Configuration File which is embedded in the firmware. A
3528 * very few early versions of the firmware didn't have one embedded
3529 * but we can ignore those.
3531 if (ret == -ENOENT) {
3532 memset(&caps_cmd, 0, sizeof(caps_cmd));
3533 caps_cmd.op_to_write =
3534 htonl(FW_CMD_OP_V(FW_CAPS_CONFIG_CMD) |
3537 caps_cmd.cfvalid_to_len16 = htonl(FW_LEN16(caps_cmd));
3538 ret = t4_wr_mbox(adapter, adapter->mbox, &caps_cmd,
3539 sizeof(caps_cmd), &caps_cmd);
3540 config_name = "Firmware Default";
3547 finiver = ntohl(caps_cmd.finiver);
3548 finicsum = ntohl(caps_cmd.finicsum);
3549 cfcsum = ntohl(caps_cmd.cfcsum);
3550 if (finicsum != cfcsum)
3551 dev_warn(adapter->pdev_dev, "Configuration File checksum "\
3552 "mismatch: [fini] csum=%#x, computed csum=%#x\n",
3556 * And now tell the firmware to use the configuration we just loaded.
3558 caps_cmd.op_to_write =
3559 htonl(FW_CMD_OP_V(FW_CAPS_CONFIG_CMD) |
3562 caps_cmd.cfvalid_to_len16 = htonl(FW_LEN16(caps_cmd));
3563 ret = t4_wr_mbox(adapter, adapter->mbox, &caps_cmd, sizeof(caps_cmd),
3569 * Tweak configuration based on system architecture, module
3572 ret = adap_init0_tweaks(adapter);
3577 * And finally tell the firmware to initialize itself using the
3578 * parameters from the Configuration File.
3580 ret = t4_fw_initialize(adapter, adapter->mbox);
3584 /* Emit Firmware Configuration File information and return
3587 dev_info(adapter->pdev_dev, "Successfully configured using Firmware "\
3588 "Configuration File \"%s\", version %#x, computed checksum %#x\n",
3589 config_name, finiver, cfcsum);
3593 * Something bad happened. Return the error ... (If the "error"
3594 * is that there's no Configuration File on the adapter we don't
3595 * want to issue a warning since this is fairly common.)
3598 if (config_issued && ret != -ENOENT)
3599 dev_warn(adapter->pdev_dev, "\"%s\" configuration file error %d\n",
3604 static struct fw_info fw_info_array[] = {
3607 .fs_name = FW4_CFNAME,
3608 .fw_mod_name = FW4_FNAME,
3610 .chip = FW_HDR_CHIP_T4,
3611 .fw_ver = __cpu_to_be32(FW_VERSION(T4)),
3612 .intfver_nic = FW_INTFVER(T4, NIC),
3613 .intfver_vnic = FW_INTFVER(T4, VNIC),
3614 .intfver_ri = FW_INTFVER(T4, RI),
3615 .intfver_iscsi = FW_INTFVER(T4, ISCSI),
3616 .intfver_fcoe = FW_INTFVER(T4, FCOE),
3620 .fs_name = FW5_CFNAME,
3621 .fw_mod_name = FW5_FNAME,
3623 .chip = FW_HDR_CHIP_T5,
3624 .fw_ver = __cpu_to_be32(FW_VERSION(T5)),
3625 .intfver_nic = FW_INTFVER(T5, NIC),
3626 .intfver_vnic = FW_INTFVER(T5, VNIC),
3627 .intfver_ri = FW_INTFVER(T5, RI),
3628 .intfver_iscsi = FW_INTFVER(T5, ISCSI),
3629 .intfver_fcoe = FW_INTFVER(T5, FCOE),
3633 .fs_name = FW6_CFNAME,
3634 .fw_mod_name = FW6_FNAME,
3636 .chip = FW_HDR_CHIP_T6,
3637 .fw_ver = __cpu_to_be32(FW_VERSION(T6)),
3638 .intfver_nic = FW_INTFVER(T6, NIC),
3639 .intfver_vnic = FW_INTFVER(T6, VNIC),
3640 .intfver_ofld = FW_INTFVER(T6, OFLD),
3641 .intfver_ri = FW_INTFVER(T6, RI),
3642 .intfver_iscsipdu = FW_INTFVER(T6, ISCSIPDU),
3643 .intfver_iscsi = FW_INTFVER(T6, ISCSI),
3644 .intfver_fcoepdu = FW_INTFVER(T6, FCOEPDU),
3645 .intfver_fcoe = FW_INTFVER(T6, FCOE),
3651 static struct fw_info *find_fw_info(int chip)
3655 for (i = 0; i < ARRAY_SIZE(fw_info_array); i++) {
3656 if (fw_info_array[i].chip == chip)
3657 return &fw_info_array[i];
3663 * Phase 0 of initialization: contact FW, obtain config, perform basic init.
3665 static int adap_init0(struct adapter *adap)
3669 enum dev_state state;
3670 u32 params[7], val[7];
3671 struct fw_caps_config_cmd caps_cmd;
3674 /* Grab Firmware Device Log parameters as early as possible so we have
3675 * access to it for debugging, etc.
3677 ret = t4_init_devlog_params(adap);
3681 /* Contact FW, advertising Master capability */
3682 ret = t4_fw_hello(adap, adap->mbox, adap->mbox, MASTER_MAY, &state);
3684 dev_err(adap->pdev_dev, "could not connect to FW, error %d\n",
3688 if (ret == adap->mbox)
3689 adap->flags |= MASTER_PF;
3692 * If we're the Master PF Driver and the device is uninitialized,
3693 * then let's consider upgrading the firmware ... (We always want
3694 * to check the firmware version number in order to A. get it for
3695 * later reporting and B. to warn if the currently loaded firmware
3696 * is excessively mismatched relative to the driver.)
3698 t4_get_fw_version(adap, &adap->params.fw_vers);
3699 t4_get_tp_version(adap, &adap->params.tp_vers);
3700 ret = t4_check_fw_version(adap);
3701 /* If firmware is too old (not supported by driver) force an update. */
3703 state = DEV_STATE_UNINIT;
3704 if ((adap->flags & MASTER_PF) && state != DEV_STATE_INIT) {
3705 struct fw_info *fw_info;
3706 struct fw_hdr *card_fw;
3707 const struct firmware *fw;
3708 const u8 *fw_data = NULL;
3709 unsigned int fw_size = 0;
3711 /* This is the firmware whose headers the driver was compiled
3714 fw_info = find_fw_info(CHELSIO_CHIP_VERSION(adap->params.chip));
3715 if (fw_info == NULL) {
3716 dev_err(adap->pdev_dev,
3717 "unable to get firmware info for chip %d.\n",
3718 CHELSIO_CHIP_VERSION(adap->params.chip));
3722 /* allocate memory to read the header of the firmware on the
3725 card_fw = t4_alloc_mem(sizeof(*card_fw));
3727 /* Get FW from from /lib/firmware/ */
3728 ret = request_firmware(&fw, fw_info->fw_mod_name,
3731 dev_err(adap->pdev_dev,
3732 "unable to load firmware image %s, error %d\n",
3733 fw_info->fw_mod_name, ret);
3739 /* upgrade FW logic */
3740 ret = t4_prep_fw(adap, fw_info, fw_data, fw_size, card_fw,
3744 release_firmware(fw);
3745 t4_free_mem(card_fw);
3752 * Grab VPD parameters. This should be done after we establish a
3753 * connection to the firmware since some of the VPD parameters
3754 * (notably the Core Clock frequency) are retrieved via requests to
3755 * the firmware. On the other hand, we need these fairly early on
3756 * so we do this right after getting ahold of the firmware.
3758 ret = t4_get_vpd_params(adap, &adap->params.vpd);
3763 * Find out what ports are available to us. Note that we need to do
3764 * this before calling adap_init0_no_config() since it needs nports
3768 FW_PARAMS_MNEM_V(FW_PARAMS_MNEM_DEV) |
3769 FW_PARAMS_PARAM_X_V(FW_PARAMS_PARAM_DEV_PORTVEC);
3770 ret = t4_query_params(adap, adap->mbox, adap->pf, 0, 1, &v, &port_vec);
3774 adap->params.nports = hweight32(port_vec);
3775 adap->params.portvec = port_vec;
3777 /* If the firmware is initialized already, emit a simply note to that
3778 * effect. Otherwise, it's time to try initializing the adapter.
3780 if (state == DEV_STATE_INIT) {
3781 dev_info(adap->pdev_dev, "Coming up as %s: "\
3782 "Adapter already initialized\n",
3783 adap->flags & MASTER_PF ? "MASTER" : "SLAVE");
3785 dev_info(adap->pdev_dev, "Coming up as MASTER: "\
3786 "Initializing adapter\n");
3788 /* Find out whether we're dealing with a version of the
3789 * firmware which has configuration file support.
3791 params[0] = (FW_PARAMS_MNEM_V(FW_PARAMS_MNEM_DEV) |
3792 FW_PARAMS_PARAM_X_V(FW_PARAMS_PARAM_DEV_CF));
3793 ret = t4_query_params(adap, adap->mbox, adap->pf, 0, 1,
3796 /* If the firmware doesn't support Configuration Files,
3800 dev_err(adap->pdev_dev, "firmware doesn't support "
3801 "Firmware Configuration Files\n");
3805 /* The firmware provides us with a memory buffer where we can
3806 * load a Configuration File from the host if we want to
3807 * override the Configuration File in flash.
3809 ret = adap_init0_config(adap, reset);
3810 if (ret == -ENOENT) {
3811 dev_err(adap->pdev_dev, "no Configuration File "
3812 "present on adapter.\n");
3816 dev_err(adap->pdev_dev, "could not initialize "
3817 "adapter, error %d\n", -ret);
3822 /* Give the SGE code a chance to pull in anything that it needs ...
3823 * Note that this must be called after we retrieve our VPD parameters
3824 * in order to know how to convert core ticks to seconds, etc.
3826 ret = t4_sge_init(adap);
3830 if (is_bypass_device(adap->pdev->device))
3831 adap->params.bypass = 1;
3834 * Grab some of our basic fundamental operating parameters.
3836 #define FW_PARAM_DEV(param) \
3837 (FW_PARAMS_MNEM_V(FW_PARAMS_MNEM_DEV) | \
3838 FW_PARAMS_PARAM_X_V(FW_PARAMS_PARAM_DEV_##param))
3840 #define FW_PARAM_PFVF(param) \
3841 FW_PARAMS_MNEM_V(FW_PARAMS_MNEM_PFVF) | \
3842 FW_PARAMS_PARAM_X_V(FW_PARAMS_PARAM_PFVF_##param)| \
3843 FW_PARAMS_PARAM_Y_V(0) | \
3844 FW_PARAMS_PARAM_Z_V(0)
3846 params[0] = FW_PARAM_PFVF(EQ_START);
3847 params[1] = FW_PARAM_PFVF(L2T_START);
3848 params[2] = FW_PARAM_PFVF(L2T_END);
3849 params[3] = FW_PARAM_PFVF(FILTER_START);
3850 params[4] = FW_PARAM_PFVF(FILTER_END);
3851 params[5] = FW_PARAM_PFVF(IQFLINT_START);
3852 ret = t4_query_params(adap, adap->mbox, adap->pf, 0, 6, params, val);
3855 adap->sge.egr_start = val[0];
3856 adap->l2t_start = val[1];
3857 adap->l2t_end = val[2];
3858 adap->tids.ftid_base = val[3];
3859 adap->tids.nftids = val[4] - val[3] + 1;
3860 adap->sge.ingr_start = val[5];
3862 /* qids (ingress/egress) returned from firmware can be anywhere
3863 * in the range from EQ(IQFLINT)_START to EQ(IQFLINT)_END.
3864 * Hence driver needs to allocate memory for this range to
3865 * store the queue info. Get the highest IQFLINT/EQ index returned
3866 * in FW_EQ_*_CMD.alloc command.
3868 params[0] = FW_PARAM_PFVF(EQ_END);
3869 params[1] = FW_PARAM_PFVF(IQFLINT_END);
3870 ret = t4_query_params(adap, adap->mbox, adap->pf, 0, 2, params, val);
3873 adap->sge.egr_sz = val[0] - adap->sge.egr_start + 1;
3874 adap->sge.ingr_sz = val[1] - adap->sge.ingr_start + 1;
3876 adap->sge.egr_map = kcalloc(adap->sge.egr_sz,
3877 sizeof(*adap->sge.egr_map), GFP_KERNEL);
3878 if (!adap->sge.egr_map) {
3883 adap->sge.ingr_map = kcalloc(adap->sge.ingr_sz,
3884 sizeof(*adap->sge.ingr_map), GFP_KERNEL);
3885 if (!adap->sge.ingr_map) {
3890 /* Allocate the memory for the vaious egress queue bitmaps
3891 * ie starving_fl, txq_maperr and blocked_fl.
3893 adap->sge.starving_fl = kcalloc(BITS_TO_LONGS(adap->sge.egr_sz),
3894 sizeof(long), GFP_KERNEL);
3895 if (!adap->sge.starving_fl) {
3900 adap->sge.txq_maperr = kcalloc(BITS_TO_LONGS(adap->sge.egr_sz),
3901 sizeof(long), GFP_KERNEL);
3902 if (!adap->sge.txq_maperr) {
3907 #ifdef CONFIG_DEBUG_FS
3908 adap->sge.blocked_fl = kcalloc(BITS_TO_LONGS(adap->sge.egr_sz),
3909 sizeof(long), GFP_KERNEL);
3910 if (!adap->sge.blocked_fl) {
3916 params[0] = FW_PARAM_PFVF(CLIP_START);
3917 params[1] = FW_PARAM_PFVF(CLIP_END);
3918 ret = t4_query_params(adap, adap->mbox, adap->pf, 0, 2, params, val);
3921 adap->clipt_start = val[0];
3922 adap->clipt_end = val[1];
3924 /* query params related to active filter region */
3925 params[0] = FW_PARAM_PFVF(ACTIVE_FILTER_START);
3926 params[1] = FW_PARAM_PFVF(ACTIVE_FILTER_END);
3927 ret = t4_query_params(adap, adap->mbox, adap->pf, 0, 2, params, val);
3928 /* If Active filter size is set we enable establishing
3929 * offload connection through firmware work request
3931 if ((val[0] != val[1]) && (ret >= 0)) {
3932 adap->flags |= FW_OFLD_CONN;
3933 adap->tids.aftid_base = val[0];
3934 adap->tids.aftid_end = val[1];
3937 /* If we're running on newer firmware, let it know that we're
3938 * prepared to deal with encapsulated CPL messages. Older
3939 * firmware won't understand this and we'll just get
3940 * unencapsulated messages ...
3942 params[0] = FW_PARAM_PFVF(CPLFW4MSG_ENCAP);
3944 (void)t4_set_params(adap, adap->mbox, adap->pf, 0, 1, params, val);
3947 * Find out whether we're allowed to use the T5+ ULPTX MEMWRITE DSGL
3948 * capability. Earlier versions of the firmware didn't have the
3949 * ULPTX_MEMWRITE_DSGL so we'll interpret a query failure as no
3950 * permission to use ULPTX MEMWRITE DSGL.
3952 if (is_t4(adap->params.chip)) {
3953 adap->params.ulptx_memwrite_dsgl = false;
3955 params[0] = FW_PARAM_DEV(ULPTX_MEMWRITE_DSGL);
3956 ret = t4_query_params(adap, adap->mbox, adap->pf, 0,
3958 adap->params.ulptx_memwrite_dsgl = (ret == 0 && val[0] != 0);
3962 * Get device capabilities so we can determine what resources we need
3965 memset(&caps_cmd, 0, sizeof(caps_cmd));
3966 caps_cmd.op_to_write = htonl(FW_CMD_OP_V(FW_CAPS_CONFIG_CMD) |
3967 FW_CMD_REQUEST_F | FW_CMD_READ_F);
3968 caps_cmd.cfvalid_to_len16 = htonl(FW_LEN16(caps_cmd));
3969 ret = t4_wr_mbox(adap, adap->mbox, &caps_cmd, sizeof(caps_cmd),
3974 if (caps_cmd.ofldcaps) {
3975 /* query offload-related parameters */
3976 params[0] = FW_PARAM_DEV(NTID);
3977 params[1] = FW_PARAM_PFVF(SERVER_START);
3978 params[2] = FW_PARAM_PFVF(SERVER_END);
3979 params[3] = FW_PARAM_PFVF(TDDP_START);
3980 params[4] = FW_PARAM_PFVF(TDDP_END);
3981 params[5] = FW_PARAM_DEV(FLOWC_BUFFIFO_SZ);
3982 ret = t4_query_params(adap, adap->mbox, adap->pf, 0, 6,
3986 adap->tids.ntids = val[0];
3987 adap->tids.natids = min(adap->tids.ntids / 2, MAX_ATIDS);
3988 adap->tids.stid_base = val[1];
3989 adap->tids.nstids = val[2] - val[1] + 1;
3991 * Setup server filter region. Divide the available filter
3992 * region into two parts. Regular filters get 1/3rd and server
3993 * filters get 2/3rd part. This is only enabled if workarond
3995 * 1. For regular filters.
3996 * 2. Server filter: This are special filters which are used
3997 * to redirect SYN packets to offload queue.
3999 if (adap->flags & FW_OFLD_CONN && !is_bypass(adap)) {
4000 adap->tids.sftid_base = adap->tids.ftid_base +
4001 DIV_ROUND_UP(adap->tids.nftids, 3);
4002 adap->tids.nsftids = adap->tids.nftids -
4003 DIV_ROUND_UP(adap->tids.nftids, 3);
4004 adap->tids.nftids = adap->tids.sftid_base -
4005 adap->tids.ftid_base;
4007 adap->vres.ddp.start = val[3];
4008 adap->vres.ddp.size = val[4] - val[3] + 1;
4009 adap->params.ofldq_wr_cred = val[5];
4011 adap->params.offload = 1;
4013 if (caps_cmd.rdmacaps) {
4014 params[0] = FW_PARAM_PFVF(STAG_START);
4015 params[1] = FW_PARAM_PFVF(STAG_END);
4016 params[2] = FW_PARAM_PFVF(RQ_START);
4017 params[3] = FW_PARAM_PFVF(RQ_END);
4018 params[4] = FW_PARAM_PFVF(PBL_START);
4019 params[5] = FW_PARAM_PFVF(PBL_END);
4020 ret = t4_query_params(adap, adap->mbox, adap->pf, 0, 6,
4024 adap->vres.stag.start = val[0];
4025 adap->vres.stag.size = val[1] - val[0] + 1;
4026 adap->vres.rq.start = val[2];
4027 adap->vres.rq.size = val[3] - val[2] + 1;
4028 adap->vres.pbl.start = val[4];
4029 adap->vres.pbl.size = val[5] - val[4] + 1;
4031 params[0] = FW_PARAM_PFVF(SQRQ_START);
4032 params[1] = FW_PARAM_PFVF(SQRQ_END);
4033 params[2] = FW_PARAM_PFVF(CQ_START);
4034 params[3] = FW_PARAM_PFVF(CQ_END);
4035 params[4] = FW_PARAM_PFVF(OCQ_START);
4036 params[5] = FW_PARAM_PFVF(OCQ_END);
4037 ret = t4_query_params(adap, adap->mbox, adap->pf, 0, 6, params,
4041 adap->vres.qp.start = val[0];
4042 adap->vres.qp.size = val[1] - val[0] + 1;
4043 adap->vres.cq.start = val[2];
4044 adap->vres.cq.size = val[3] - val[2] + 1;
4045 adap->vres.ocq.start = val[4];
4046 adap->vres.ocq.size = val[5] - val[4] + 1;
4048 params[0] = FW_PARAM_DEV(MAXORDIRD_QP);
4049 params[1] = FW_PARAM_DEV(MAXIRD_ADAPTER);
4050 ret = t4_query_params(adap, adap->mbox, adap->pf, 0, 2, params,
4053 adap->params.max_ordird_qp = 8;
4054 adap->params.max_ird_adapter = 32 * adap->tids.ntids;
4057 adap->params.max_ordird_qp = val[0];
4058 adap->params.max_ird_adapter = val[1];
4060 dev_info(adap->pdev_dev,
4061 "max_ordird_qp %d max_ird_adapter %d\n",
4062 adap->params.max_ordird_qp,
4063 adap->params.max_ird_adapter);
4065 if (caps_cmd.iscsicaps) {
4066 params[0] = FW_PARAM_PFVF(ISCSI_START);
4067 params[1] = FW_PARAM_PFVF(ISCSI_END);
4068 ret = t4_query_params(adap, adap->mbox, adap->pf, 0, 2,
4072 adap->vres.iscsi.start = val[0];
4073 adap->vres.iscsi.size = val[1] - val[0] + 1;
4075 #undef FW_PARAM_PFVF
4078 /* The MTU/MSS Table is initialized by now, so load their values. If
4079 * we're initializing the adapter, then we'll make any modifications
4080 * we want to the MTU/MSS Table and also initialize the congestion
4083 t4_read_mtu_tbl(adap, adap->params.mtus, NULL);
4084 if (state != DEV_STATE_INIT) {
4087 /* The default MTU Table contains values 1492 and 1500.
4088 * However, for TCP, it's better to have two values which are
4089 * a multiple of 8 +/- 4 bytes apart near this popular MTU.
4090 * This allows us to have a TCP Data Payload which is a
4091 * multiple of 8 regardless of what combination of TCP Options
4092 * are in use (always a multiple of 4 bytes) which is
4093 * important for performance reasons. For instance, if no
4094 * options are in use, then we have a 20-byte IP header and a
4095 * 20-byte TCP header. In this case, a 1500-byte MSS would
4096 * result in a TCP Data Payload of 1500 - 40 == 1460 bytes
4097 * which is not a multiple of 8. So using an MSS of 1488 in
4098 * this case results in a TCP Data Payload of 1448 bytes which
4099 * is a multiple of 8. On the other hand, if 12-byte TCP Time
4100 * Stamps have been negotiated, then an MTU of 1500 bytes
4101 * results in a TCP Data Payload of 1448 bytes which, as
4102 * above, is a multiple of 8 bytes ...
4104 for (i = 0; i < NMTUS; i++)
4105 if (adap->params.mtus[i] == 1492) {
4106 adap->params.mtus[i] = 1488;
4110 t4_load_mtus(adap, adap->params.mtus, adap->params.a_wnd,
4111 adap->params.b_wnd);
4113 t4_init_sge_params(adap);
4114 adap->flags |= FW_OK;
4115 t4_init_tp_params(adap);
4119 * Something bad happened. If a command timed out or failed with EIO
4120 * FW does not operate within its spec or something catastrophic
4121 * happened to HW/FW, stop issuing commands.
4124 kfree(adap->sge.egr_map);
4125 kfree(adap->sge.ingr_map);
4126 kfree(adap->sge.starving_fl);
4127 kfree(adap->sge.txq_maperr);
4128 #ifdef CONFIG_DEBUG_FS
4129 kfree(adap->sge.blocked_fl);
4131 if (ret != -ETIMEDOUT && ret != -EIO)
4132 t4_fw_bye(adap, adap->mbox);
4138 static pci_ers_result_t eeh_err_detected(struct pci_dev *pdev,
4139 pci_channel_state_t state)
4142 struct adapter *adap = pci_get_drvdata(pdev);
4148 adap->flags &= ~FW_OK;
4149 notify_ulds(adap, CXGB4_STATE_START_RECOVERY);
4150 spin_lock(&adap->stats_lock);
4151 for_each_port(adap, i) {
4152 struct net_device *dev = adap->port[i];
4154 netif_device_detach(dev);
4155 netif_carrier_off(dev);
4157 spin_unlock(&adap->stats_lock);
4158 disable_interrupts(adap);
4159 if (adap->flags & FULL_INIT_DONE)
4162 if ((adap->flags & DEV_ENABLED)) {
4163 pci_disable_device(pdev);
4164 adap->flags &= ~DEV_ENABLED;
4166 out: return state == pci_channel_io_perm_failure ?
4167 PCI_ERS_RESULT_DISCONNECT : PCI_ERS_RESULT_NEED_RESET;
4170 static pci_ers_result_t eeh_slot_reset(struct pci_dev *pdev)
4173 struct fw_caps_config_cmd c;
4174 struct adapter *adap = pci_get_drvdata(pdev);
4177 pci_restore_state(pdev);
4178 pci_save_state(pdev);
4179 return PCI_ERS_RESULT_RECOVERED;
4182 if (!(adap->flags & DEV_ENABLED)) {
4183 if (pci_enable_device(pdev)) {
4184 dev_err(&pdev->dev, "Cannot reenable PCI "
4185 "device after reset\n");
4186 return PCI_ERS_RESULT_DISCONNECT;
4188 adap->flags |= DEV_ENABLED;
4191 pci_set_master(pdev);
4192 pci_restore_state(pdev);
4193 pci_save_state(pdev);
4194 pci_cleanup_aer_uncorrect_error_status(pdev);
4196 if (t4_wait_dev_ready(adap->regs) < 0)
4197 return PCI_ERS_RESULT_DISCONNECT;
4198 if (t4_fw_hello(adap, adap->mbox, adap->pf, MASTER_MUST, NULL) < 0)
4199 return PCI_ERS_RESULT_DISCONNECT;
4200 adap->flags |= FW_OK;
4201 if (adap_init1(adap, &c))
4202 return PCI_ERS_RESULT_DISCONNECT;
4204 for_each_port(adap, i) {
4205 struct port_info *p = adap2pinfo(adap, i);
4207 ret = t4_alloc_vi(adap, adap->mbox, p->tx_chan, adap->pf, 0, 1,
4210 return PCI_ERS_RESULT_DISCONNECT;
4212 p->xact_addr_filt = -1;
4215 t4_load_mtus(adap, adap->params.mtus, adap->params.a_wnd,
4216 adap->params.b_wnd);
4219 return PCI_ERS_RESULT_DISCONNECT;
4220 return PCI_ERS_RESULT_RECOVERED;
4223 static void eeh_resume(struct pci_dev *pdev)
4226 struct adapter *adap = pci_get_drvdata(pdev);
4232 for_each_port(adap, i) {
4233 struct net_device *dev = adap->port[i];
4235 if (netif_running(dev)) {
4237 cxgb_set_rxmode(dev);
4239 netif_device_attach(dev);
4244 static const struct pci_error_handlers cxgb4_eeh = {
4245 .error_detected = eeh_err_detected,
4246 .slot_reset = eeh_slot_reset,
4247 .resume = eeh_resume,
4250 static inline bool is_x_10g_port(const struct link_config *lc)
4252 return (lc->supported & FW_PORT_CAP_SPEED_10G) != 0 ||
4253 (lc->supported & FW_PORT_CAP_SPEED_40G) != 0;
4256 static inline void init_rspq(struct adapter *adap, struct sge_rspq *q,
4257 unsigned int us, unsigned int cnt,
4258 unsigned int size, unsigned int iqe_size)
4261 cxgb4_set_rspq_intr_params(q, us, cnt);
4262 q->iqe_len = iqe_size;
4267 * Perform default configuration of DMA queues depending on the number and type
4268 * of ports we found and the number of available CPUs. Most settings can be
4269 * modified by the admin prior to actual use.
4271 static void cfg_queues(struct adapter *adap)
4273 struct sge *s = &adap->sge;
4274 int i, n10g = 0, qidx = 0;
4275 #ifndef CONFIG_CHELSIO_T4_DCB
4280 for_each_port(adap, i)
4281 n10g += is_x_10g_port(&adap2pinfo(adap, i)->link_cfg);
4282 #ifdef CONFIG_CHELSIO_T4_DCB
4283 /* For Data Center Bridging support we need to be able to support up
4284 * to 8 Traffic Priorities; each of which will be assigned to its
4285 * own TX Queue in order to prevent Head-Of-Line Blocking.
4287 if (adap->params.nports * 8 > MAX_ETH_QSETS) {
4288 dev_err(adap->pdev_dev, "MAX_ETH_QSETS=%d < %d!\n",
4289 MAX_ETH_QSETS, adap->params.nports * 8);
4293 for_each_port(adap, i) {
4294 struct port_info *pi = adap2pinfo(adap, i);
4296 pi->first_qset = qidx;
4300 #else /* !CONFIG_CHELSIO_T4_DCB */
4302 * We default to 1 queue per non-10G port and up to # of cores queues
4306 q10g = (MAX_ETH_QSETS - (adap->params.nports - n10g)) / n10g;
4307 if (q10g > netif_get_num_default_rss_queues())
4308 q10g = netif_get_num_default_rss_queues();
4310 for_each_port(adap, i) {
4311 struct port_info *pi = adap2pinfo(adap, i);
4313 pi->first_qset = qidx;
4314 pi->nqsets = is_x_10g_port(&pi->link_cfg) ? q10g : 1;
4317 #endif /* !CONFIG_CHELSIO_T4_DCB */
4320 s->max_ethqsets = qidx; /* MSI-X may lower it later */
4322 if (is_offload(adap)) {
4324 * For offload we use 1 queue/channel if all ports are up to 1G,
4325 * otherwise we divide all available queues amongst the channels
4326 * capped by the number of available cores.
4329 i = min_t(int, ARRAY_SIZE(s->ofldrxq),
4331 s->ofldqsets = roundup(i, adap->params.nports);
4333 s->ofldqsets = adap->params.nports;
4334 /* For RDMA one Rx queue per channel suffices */
4335 s->rdmaqs = adap->params.nports;
4336 /* Try and allow at least 1 CIQ per cpu rounding down
4337 * to the number of ports, with a minimum of 1 per port.
4338 * A 2 port card in a 6 cpu system: 6 CIQs, 3 / port.
4339 * A 4 port card in a 6 cpu system: 4 CIQs, 1 / port.
4340 * A 4 port card in a 2 cpu system: 4 CIQs, 1 / port.
4342 s->rdmaciqs = min_t(int, MAX_RDMA_CIQS, num_online_cpus());
4343 s->rdmaciqs = (s->rdmaciqs / adap->params.nports) *
4344 adap->params.nports;
4345 s->rdmaciqs = max_t(int, s->rdmaciqs, adap->params.nports);
4348 for (i = 0; i < ARRAY_SIZE(s->ethrxq); i++) {
4349 struct sge_eth_rxq *r = &s->ethrxq[i];
4351 init_rspq(adap, &r->rspq, 5, 10, 1024, 64);
4355 for (i = 0; i < ARRAY_SIZE(s->ethtxq); i++)
4356 s->ethtxq[i].q.size = 1024;
4358 for (i = 0; i < ARRAY_SIZE(s->ctrlq); i++)
4359 s->ctrlq[i].q.size = 512;
4361 for (i = 0; i < ARRAY_SIZE(s->ofldtxq); i++)
4362 s->ofldtxq[i].q.size = 1024;
4364 for (i = 0; i < ARRAY_SIZE(s->ofldrxq); i++) {
4365 struct sge_ofld_rxq *r = &s->ofldrxq[i];
4367 init_rspq(adap, &r->rspq, 5, 1, 1024, 64);
4368 r->rspq.uld = CXGB4_ULD_ISCSI;
4372 for (i = 0; i < ARRAY_SIZE(s->rdmarxq); i++) {
4373 struct sge_ofld_rxq *r = &s->rdmarxq[i];
4375 init_rspq(adap, &r->rspq, 5, 1, 511, 64);
4376 r->rspq.uld = CXGB4_ULD_RDMA;
4380 ciq_size = 64 + adap->vres.cq.size + adap->tids.nftids;
4381 if (ciq_size > SGE_MAX_IQ_SIZE) {
4382 CH_WARN(adap, "CIQ size too small for available IQs\n");
4383 ciq_size = SGE_MAX_IQ_SIZE;
4386 for (i = 0; i < ARRAY_SIZE(s->rdmaciq); i++) {
4387 struct sge_ofld_rxq *r = &s->rdmaciq[i];
4389 init_rspq(adap, &r->rspq, 5, 1, ciq_size, 64);
4390 r->rspq.uld = CXGB4_ULD_RDMA;
4393 init_rspq(adap, &s->fw_evtq, 0, 1, 1024, 64);
4394 init_rspq(adap, &s->intrq, 0, 1, 2 * MAX_INGQ, 64);
4398 * Reduce the number of Ethernet queues across all ports to at most n.
4399 * n provides at least one queue per port.
4401 static void reduce_ethqs(struct adapter *adap, int n)
4404 struct port_info *pi;
4406 while (n < adap->sge.ethqsets)
4407 for_each_port(adap, i) {
4408 pi = adap2pinfo(adap, i);
4409 if (pi->nqsets > 1) {
4411 adap->sge.ethqsets--;
4412 if (adap->sge.ethqsets <= n)
4418 for_each_port(adap, i) {
4419 pi = adap2pinfo(adap, i);
4425 /* 2 MSI-X vectors needed for the FW queue and non-data interrupts */
4426 #define EXTRA_VECS 2
4428 static int enable_msix(struct adapter *adap)
4431 int i, want, need, allocated;
4432 struct sge *s = &adap->sge;
4433 unsigned int nchan = adap->params.nports;
4434 struct msix_entry *entries;
4436 entries = kmalloc(sizeof(*entries) * (MAX_INGQ + 1),
4441 for (i = 0; i < MAX_INGQ + 1; ++i)
4442 entries[i].entry = i;
4444 want = s->max_ethqsets + EXTRA_VECS;
4445 if (is_offload(adap)) {
4446 want += s->rdmaqs + s->rdmaciqs + s->ofldqsets;
4447 /* need nchan for each possible ULD */
4448 ofld_need = 3 * nchan;
4450 #ifdef CONFIG_CHELSIO_T4_DCB
4451 /* For Data Center Bridging we need 8 Ethernet TX Priority Queues for
4454 need = 8 * adap->params.nports + EXTRA_VECS + ofld_need;
4456 need = adap->params.nports + EXTRA_VECS + ofld_need;
4458 allocated = pci_enable_msix_range(adap->pdev, entries, need, want);
4459 if (allocated < 0) {
4460 dev_info(adap->pdev_dev, "not enough MSI-X vectors left,"
4461 " not using MSI-X\n");
4466 /* Distribute available vectors to the various queue groups.
4467 * Every group gets its minimum requirement and NIC gets top
4468 * priority for leftovers.
4470 i = allocated - EXTRA_VECS - ofld_need;
4471 if (i < s->max_ethqsets) {
4472 s->max_ethqsets = i;
4473 if (i < s->ethqsets)
4474 reduce_ethqs(adap, i);
4476 if (is_offload(adap)) {
4477 if (allocated < want) {
4479 s->rdmaciqs = nchan;
4482 /* leftovers go to OFLD */
4483 i = allocated - EXTRA_VECS - s->max_ethqsets -
4484 s->rdmaqs - s->rdmaciqs;
4485 s->ofldqsets = (i / nchan) * nchan; /* round down */
4487 for (i = 0; i < allocated; ++i)
4488 adap->msix_info[i].vec = entries[i].vector;
4489 dev_info(adap->pdev_dev, "%d MSI-X vectors allocated, "
4490 "nic %d iscsi %d rdma cpl %d rdma ciq %d\n",
4491 allocated, s->max_ethqsets, s->ofldqsets, s->rdmaqs,
4500 static int init_rss(struct adapter *adap)
4505 err = t4_init_rss_mode(adap, adap->mbox);
4509 for_each_port(adap, i) {
4510 struct port_info *pi = adap2pinfo(adap, i);
4512 pi->rss = kcalloc(pi->rss_size, sizeof(u16), GFP_KERNEL);
4519 static void print_port_info(const struct net_device *dev)
4523 const char *spd = "";
4524 const struct port_info *pi = netdev_priv(dev);
4525 const struct adapter *adap = pi->adapter;
4527 if (adap->params.pci.speed == PCI_EXP_LNKSTA_CLS_2_5GB)
4529 else if (adap->params.pci.speed == PCI_EXP_LNKSTA_CLS_5_0GB)
4531 else if (adap->params.pci.speed == PCI_EXP_LNKSTA_CLS_8_0GB)
4534 if (pi->link_cfg.supported & FW_PORT_CAP_SPEED_100M)
4535 bufp += sprintf(bufp, "100/");
4536 if (pi->link_cfg.supported & FW_PORT_CAP_SPEED_1G)
4537 bufp += sprintf(bufp, "1000/");
4538 if (pi->link_cfg.supported & FW_PORT_CAP_SPEED_10G)
4539 bufp += sprintf(bufp, "10G/");
4540 if (pi->link_cfg.supported & FW_PORT_CAP_SPEED_40G)
4541 bufp += sprintf(bufp, "40G/");
4544 sprintf(bufp, "BASE-%s", t4_get_port_type_description(pi->port_type));
4546 netdev_info(dev, "Chelsio %s rev %d %s %sNIC PCIe x%d%s%s\n",
4547 adap->params.vpd.id,
4548 CHELSIO_CHIP_RELEASE(adap->params.chip), buf,
4549 is_offload(adap) ? "R" : "", adap->params.pci.width, spd,
4550 (adap->flags & USING_MSIX) ? " MSI-X" :
4551 (adap->flags & USING_MSI) ? " MSI" : "");
4552 netdev_info(dev, "S/N: %s, P/N: %s\n",
4553 adap->params.vpd.sn, adap->params.vpd.pn);
4556 static void enable_pcie_relaxed_ordering(struct pci_dev *dev)
4558 pcie_capability_set_word(dev, PCI_EXP_DEVCTL, PCI_EXP_DEVCTL_RELAX_EN);
4562 * Free the following resources:
4563 * - memory used for tables
4566 * - resources FW is holding for us
4568 static void free_some_resources(struct adapter *adapter)
4572 t4_free_mem(adapter->l2t);
4573 t4_free_mem(adapter->tids.tid_tab);
4574 kfree(adapter->sge.egr_map);
4575 kfree(adapter->sge.ingr_map);
4576 kfree(adapter->sge.starving_fl);
4577 kfree(adapter->sge.txq_maperr);
4578 #ifdef CONFIG_DEBUG_FS
4579 kfree(adapter->sge.blocked_fl);
4581 disable_msi(adapter);
4583 for_each_port(adapter, i)
4584 if (adapter->port[i]) {
4585 struct port_info *pi = adap2pinfo(adapter, i);
4588 t4_free_vi(adapter, adapter->mbox, adapter->pf,
4590 kfree(adap2pinfo(adapter, i)->rss);
4591 free_netdev(adapter->port[i]);
4593 if (adapter->flags & FW_OK)
4594 t4_fw_bye(adapter, adapter->pf);
4597 #define TSO_FLAGS (NETIF_F_TSO | NETIF_F_TSO6 | NETIF_F_TSO_ECN)
4598 #define VLAN_FEAT (NETIF_F_SG | NETIF_F_IP_CSUM | TSO_FLAGS | \
4599 NETIF_F_IPV6_CSUM | NETIF_F_HIGHDMA)
4600 #define SEGMENT_SIZE 128
4602 static int get_chip_type(struct pci_dev *pdev, u32 pl_rev)
4606 /* Retrieve adapter's device ID */
4607 pci_read_config_word(pdev, PCI_DEVICE_ID, &device_id);
4609 switch (device_id >> 12) {
4611 return CHELSIO_CHIP_CODE(CHELSIO_T4, pl_rev);
4613 return CHELSIO_CHIP_CODE(CHELSIO_T5, pl_rev);
4615 return CHELSIO_CHIP_CODE(CHELSIO_T6, pl_rev);
4617 dev_err(&pdev->dev, "Device %d is not supported\n",
4623 static int init_one(struct pci_dev *pdev, const struct pci_device_id *ent)
4625 int func, i, err, s_qpp, qpp, num_seg;
4626 struct port_info *pi;
4627 bool highdma = false;
4628 struct adapter *adapter = NULL;
4631 enum chip_type chip;
4633 printk_once(KERN_INFO "%s - version %s\n", DRV_DESC, DRV_VERSION);
4635 err = pci_request_regions(pdev, KBUILD_MODNAME);
4637 /* Just info, some other driver may have claimed the device. */
4638 dev_info(&pdev->dev, "cannot obtain PCI resources\n");
4642 err = pci_enable_device(pdev);
4644 dev_err(&pdev->dev, "cannot enable PCI device\n");
4645 goto out_release_regions;
4648 regs = pci_ioremap_bar(pdev, 0);
4650 dev_err(&pdev->dev, "cannot map device registers\n");
4652 goto out_disable_device;
4655 err = t4_wait_dev_ready(regs);
4657 goto out_unmap_bar0;
4659 /* We control everything through one PF */
4660 whoami = readl(regs + PL_WHOAMI_A);
4661 pl_rev = REV_G(readl(regs + PL_REV_A));
4662 chip = get_chip_type(pdev, pl_rev);
4663 func = CHELSIO_CHIP_VERSION(chip) <= CHELSIO_T5 ?
4664 SOURCEPF_G(whoami) : T6_SOURCEPF_G(whoami);
4665 if (func != ent->driver_data) {
4667 pci_disable_device(pdev);
4668 pci_save_state(pdev); /* to restore SR-IOV later */
4672 if (!pci_set_dma_mask(pdev, DMA_BIT_MASK(64))) {
4674 err = pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(64));
4676 dev_err(&pdev->dev, "unable to obtain 64-bit DMA for "
4677 "coherent allocations\n");
4678 goto out_unmap_bar0;
4681 err = pci_set_dma_mask(pdev, DMA_BIT_MASK(32));
4683 dev_err(&pdev->dev, "no usable DMA configuration\n");
4684 goto out_unmap_bar0;
4688 pci_enable_pcie_error_reporting(pdev);
4689 enable_pcie_relaxed_ordering(pdev);
4690 pci_set_master(pdev);
4691 pci_save_state(pdev);
4693 adapter = kzalloc(sizeof(*adapter), GFP_KERNEL);
4696 goto out_unmap_bar0;
4699 adapter->workq = create_singlethread_workqueue("cxgb4");
4700 if (!adapter->workq) {
4702 goto out_free_adapter;
4705 /* PCI device has been enabled */
4706 adapter->flags |= DEV_ENABLED;
4708 adapter->regs = regs;
4709 adapter->pdev = pdev;
4710 adapter->pdev_dev = &pdev->dev;
4711 adapter->mbox = func;
4713 adapter->msg_enable = dflt_msg_enable;
4714 memset(adapter->chan_map, 0xff, sizeof(adapter->chan_map));
4716 spin_lock_init(&adapter->stats_lock);
4717 spin_lock_init(&adapter->tid_release_lock);
4718 spin_lock_init(&adapter->win0_lock);
4720 INIT_WORK(&adapter->tid_release_task, process_tid_release_list);
4721 INIT_WORK(&adapter->db_full_task, process_db_full);
4722 INIT_WORK(&adapter->db_drop_task, process_db_drop);
4724 err = t4_prep_adapter(adapter);
4726 goto out_free_adapter;
4729 if (!is_t4(adapter->params.chip)) {
4730 s_qpp = (QUEUESPERPAGEPF0_S +
4731 (QUEUESPERPAGEPF1_S - QUEUESPERPAGEPF0_S) *
4733 qpp = 1 << QUEUESPERPAGEPF0_G(t4_read_reg(adapter,
4734 SGE_EGRESS_QUEUES_PER_PAGE_PF_A) >> s_qpp);
4735 num_seg = PAGE_SIZE / SEGMENT_SIZE;
4737 /* Each segment size is 128B. Write coalescing is enabled only
4738 * when SGE_EGRESS_QUEUES_PER_PAGE_PF reg value for the
4739 * queue is less no of segments that can be accommodated in
4742 if (qpp > num_seg) {
4744 "Incorrect number of egress queues per page\n");
4746 goto out_free_adapter;
4748 adapter->bar2 = ioremap_wc(pci_resource_start(pdev, 2),
4749 pci_resource_len(pdev, 2));
4750 if (!adapter->bar2) {
4751 dev_err(&pdev->dev, "cannot map device bar2 region\n");
4753 goto out_free_adapter;
4757 setup_memwin(adapter);
4758 err = adap_init0(adapter);
4759 #ifdef CONFIG_DEBUG_FS
4760 bitmap_zero(adapter->sge.blocked_fl, adapter->sge.egr_sz);
4762 setup_memwin_rdma(adapter);
4766 /* configure SGE_STAT_CFG_A to read WC stats */
4767 if (!is_t4(adapter->params.chip))
4768 t4_write_reg(adapter, SGE_STAT_CFG_A,
4769 STATSOURCE_T5_V(7) | STATMODE_V(0));
4771 for_each_port(adapter, i) {
4772 struct net_device *netdev;
4774 netdev = alloc_etherdev_mq(sizeof(struct port_info),
4781 SET_NETDEV_DEV(netdev, &pdev->dev);
4783 adapter->port[i] = netdev;
4784 pi = netdev_priv(netdev);
4785 pi->adapter = adapter;
4786 pi->xact_addr_filt = -1;
4788 netdev->irq = pdev->irq;
4790 netdev->hw_features = NETIF_F_SG | TSO_FLAGS |
4791 NETIF_F_IP_CSUM | NETIF_F_IPV6_CSUM |
4792 NETIF_F_RXCSUM | NETIF_F_RXHASH |
4793 NETIF_F_HW_VLAN_CTAG_TX | NETIF_F_HW_VLAN_CTAG_RX;
4795 netdev->hw_features |= NETIF_F_HIGHDMA;
4796 netdev->features |= netdev->hw_features;
4797 netdev->vlan_features = netdev->features & VLAN_FEAT;
4799 netdev->priv_flags |= IFF_UNICAST_FLT;
4801 netdev->netdev_ops = &cxgb4_netdev_ops;
4802 #ifdef CONFIG_CHELSIO_T4_DCB
4803 netdev->dcbnl_ops = &cxgb4_dcb_ops;
4804 cxgb4_dcb_state_init(netdev);
4806 cxgb4_set_ethtool_ops(netdev);
4809 pci_set_drvdata(pdev, adapter);
4811 if (adapter->flags & FW_OK) {
4812 err = t4_port_init(adapter, func, func, 0);
4815 } else if (adapter->params.nports == 1) {
4816 /* If we don't have a connection to the firmware -- possibly
4817 * because of an error -- grab the raw VPD parameters so we
4818 * can set the proper MAC Address on the debug network
4819 * interface that we've created.
4821 u8 hw_addr[ETH_ALEN];
4822 u8 *na = adapter->params.vpd.na;
4824 err = t4_get_raw_vpd_params(adapter, &adapter->params.vpd);
4826 for (i = 0; i < ETH_ALEN; i++)
4827 hw_addr[i] = (hex2val(na[2 * i + 0]) * 16 +
4828 hex2val(na[2 * i + 1]));
4829 t4_set_hw_addr(adapter, 0, hw_addr);
4833 /* Configure queues and allocate tables now, they can be needed as
4834 * soon as the first register_netdev completes.
4836 cfg_queues(adapter);
4838 adapter->l2t = t4_init_l2t(adapter->l2t_start, adapter->l2t_end);
4839 if (!adapter->l2t) {
4840 /* We tolerate a lack of L2T, giving up some functionality */
4841 dev_warn(&pdev->dev, "could not allocate L2T, continuing\n");
4842 adapter->params.offload = 0;
4845 #if IS_ENABLED(CONFIG_IPV6)
4846 adapter->clipt = t4_init_clip_tbl(adapter->clipt_start,
4847 adapter->clipt_end);
4848 if (!adapter->clipt) {
4849 /* We tolerate a lack of clip_table, giving up
4850 * some functionality
4852 dev_warn(&pdev->dev,
4853 "could not allocate Clip table, continuing\n");
4854 adapter->params.offload = 0;
4857 if (is_offload(adapter) && tid_init(&adapter->tids) < 0) {
4858 dev_warn(&pdev->dev, "could not allocate TID table, "
4860 adapter->params.offload = 0;
4863 if (is_offload(adapter)) {
4864 if (t4_read_reg(adapter, LE_DB_CONFIG_A) & HASHEN_F) {
4865 u32 hash_base, hash_reg;
4867 if (chip <= CHELSIO_T5) {
4868 hash_reg = LE_DB_TID_HASHBASE_A;
4869 hash_base = t4_read_reg(adapter, hash_reg);
4870 adapter->tids.hash_base = hash_base / 4;
4872 hash_reg = T6_LE_DB_HASH_TID_BASE_A;
4873 hash_base = t4_read_reg(adapter, hash_reg);
4874 adapter->tids.hash_base = hash_base;
4879 /* See what interrupts we'll be using */
4880 if (msi > 1 && enable_msix(adapter) == 0)
4881 adapter->flags |= USING_MSIX;
4882 else if (msi > 0 && pci_enable_msi(pdev) == 0)
4883 adapter->flags |= USING_MSI;
4885 err = init_rss(adapter);
4890 * The card is now ready to go. If any errors occur during device
4891 * registration we do not fail the whole card but rather proceed only
4892 * with the ports we manage to register successfully. However we must
4893 * register at least one net device.
4895 for_each_port(adapter, i) {
4896 pi = adap2pinfo(adapter, i);
4897 netif_set_real_num_tx_queues(adapter->port[i], pi->nqsets);
4898 netif_set_real_num_rx_queues(adapter->port[i], pi->nqsets);
4900 err = register_netdev(adapter->port[i]);
4903 adapter->chan_map[pi->tx_chan] = i;
4904 print_port_info(adapter->port[i]);
4907 dev_err(&pdev->dev, "could not register any net devices\n");
4911 dev_warn(&pdev->dev, "only %d net devices registered\n", i);
4915 if (cxgb4_debugfs_root) {
4916 adapter->debugfs_root = debugfs_create_dir(pci_name(pdev),
4917 cxgb4_debugfs_root);
4918 setup_debugfs(adapter);
4921 /* PCIe EEH recovery on powerpc platforms needs fundamental reset */
4922 pdev->needs_freset = 1;
4924 if (is_offload(adapter))
4925 attach_ulds(adapter);
4928 #ifdef CONFIG_PCI_IOV
4929 if (func < ARRAY_SIZE(num_vf) && num_vf[func] > 0)
4930 if (pci_enable_sriov(pdev, num_vf[func]) == 0)
4931 dev_info(&pdev->dev,
4932 "instantiated %u virtual functions\n",
4938 free_some_resources(adapter);
4940 if (!is_t4(adapter->params.chip))
4941 iounmap(adapter->bar2);
4944 destroy_workqueue(adapter->workq);
4950 pci_disable_pcie_error_reporting(pdev);
4951 pci_disable_device(pdev);
4952 out_release_regions:
4953 pci_release_regions(pdev);
4957 static void remove_one(struct pci_dev *pdev)
4959 struct adapter *adapter = pci_get_drvdata(pdev);
4961 #ifdef CONFIG_PCI_IOV
4962 pci_disable_sriov(pdev);
4969 /* Tear down per-adapter Work Queue first since it can contain
4970 * references to our adapter data structure.
4972 destroy_workqueue(adapter->workq);
4974 if (is_offload(adapter))
4975 detach_ulds(adapter);
4977 disable_interrupts(adapter);
4979 for_each_port(adapter, i)
4980 if (adapter->port[i]->reg_state == NETREG_REGISTERED)
4981 unregister_netdev(adapter->port[i]);
4983 debugfs_remove_recursive(adapter->debugfs_root);
4985 /* If we allocated filters, free up state associated with any
4988 if (adapter->tids.ftid_tab) {
4989 struct filter_entry *f = &adapter->tids.ftid_tab[0];
4990 for (i = 0; i < (adapter->tids.nftids +
4991 adapter->tids.nsftids); i++, f++)
4993 clear_filter(adapter, f);
4996 if (adapter->flags & FULL_INIT_DONE)
4999 free_some_resources(adapter);
5000 #if IS_ENABLED(CONFIG_IPV6)
5001 t4_cleanup_clip_tbl(adapter);
5003 iounmap(adapter->regs);
5004 if (!is_t4(adapter->params.chip))
5005 iounmap(adapter->bar2);
5006 pci_disable_pcie_error_reporting(pdev);
5007 if ((adapter->flags & DEV_ENABLED)) {
5008 pci_disable_device(pdev);
5009 adapter->flags &= ~DEV_ENABLED;
5011 pci_release_regions(pdev);
5015 pci_release_regions(pdev);
5018 static struct pci_driver cxgb4_driver = {
5019 .name = KBUILD_MODNAME,
5020 .id_table = cxgb4_pci_tbl,
5022 .remove = remove_one,
5023 .shutdown = remove_one,
5024 .err_handler = &cxgb4_eeh,
5027 static int __init cxgb4_init_module(void)
5031 /* Debugfs support is optional, just warn if this fails */
5032 cxgb4_debugfs_root = debugfs_create_dir(KBUILD_MODNAME, NULL);
5033 if (!cxgb4_debugfs_root)
5034 pr_warn("could not create debugfs entry, continuing\n");
5036 ret = pci_register_driver(&cxgb4_driver);
5038 debugfs_remove(cxgb4_debugfs_root);
5040 #if IS_ENABLED(CONFIG_IPV6)
5041 if (!inet6addr_registered) {
5042 register_inet6addr_notifier(&cxgb4_inet6addr_notifier);
5043 inet6addr_registered = true;
5050 static void __exit cxgb4_cleanup_module(void)
5052 #if IS_ENABLED(CONFIG_IPV6)
5053 if (inet6addr_registered) {
5054 unregister_inet6addr_notifier(&cxgb4_inet6addr_notifier);
5055 inet6addr_registered = false;
5058 pci_unregister_driver(&cxgb4_driver);
5059 debugfs_remove(cxgb4_debugfs_root); /* NULL ok */
5062 module_init(cxgb4_init_module);
5063 module_exit(cxgb4_cleanup_module);