2 * This file is part of the Chelsio T4 Ethernet driver for Linux.
4 * Copyright (c) 2003-2014 Chelsio Communications, Inc. All rights reserved.
6 * This software is available to you under a choice of one of two
7 * licenses. You may choose to be licensed under the terms of the GNU
8 * General Public License (GPL) Version 2, available from the file
9 * COPYING in the main directory of this source tree, or the
10 * OpenIB.org BSD license below:
12 * Redistribution and use in source and binary forms, with or
13 * without modification, are permitted provided that the following
16 * - Redistributions of source code must retain the above
17 * copyright notice, this list of conditions and the following
20 * - Redistributions in binary form must reproduce the above
21 * copyright notice, this list of conditions and the following
22 * disclaimer in the documentation and/or other materials
23 * provided with the distribution.
25 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
26 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
27 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
28 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
29 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
30 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
31 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
35 #include <linux/skbuff.h>
36 #include <linux/netdevice.h>
37 #include <linux/etherdevice.h>
38 #include <linux/if_vlan.h>
40 #include <linux/dma-mapping.h>
41 #include <linux/jiffies.h>
42 #include <linux/prefetch.h>
43 #include <linux/export.h>
46 #ifdef CONFIG_NET_RX_BUSY_POLL
47 #include <net/busy_poll.h>
48 #endif /* CONFIG_NET_RX_BUSY_POLL */
49 #ifdef CONFIG_CHELSIO_T4_FCOE
50 #include <scsi/fc/fc_fcoe.h>
51 #endif /* CONFIG_CHELSIO_T4_FCOE */
54 #include "t4_values.h"
59 * Rx buffer size. We use largish buffers if possible but settle for single
60 * pages under memory shortage.
63 # define FL_PG_ORDER 0
65 # define FL_PG_ORDER (16 - PAGE_SHIFT)
68 /* RX_PULL_LEN should be <= RX_COPY_THRES */
69 #define RX_COPY_THRES 256
70 #define RX_PULL_LEN 128
73 * Main body length for sk_buffs used for Rx Ethernet packets with fragments.
74 * Should be >= RX_PULL_LEN but possibly bigger to give pskb_may_pull some room.
76 #define RX_PKT_SKB_LEN 512
79 * Max number of Tx descriptors we clean up at a time. Should be modest as
80 * freeing skbs isn't cheap and it happens while holding locks. We just need
81 * to free packets faster than they arrive, we eventually catch up and keep
82 * the amortized cost reasonable. Must be >= 2 * TXQ_STOP_THRES.
84 #define MAX_TX_RECLAIM 16
87 * Max number of Rx buffers we replenish at a time. Again keep this modest,
88 * allocating buffers isn't cheap either.
90 #define MAX_RX_REFILL 16U
93 * Period of the Rx queue check timer. This timer is infrequent as it has
94 * something to do only when the system experiences severe memory shortage.
96 #define RX_QCHECK_PERIOD (HZ / 2)
99 * Period of the Tx queue check timer.
101 #define TX_QCHECK_PERIOD (HZ / 2)
104 * Max number of Tx descriptors to be reclaimed by the Tx timer.
106 #define MAX_TIMER_TX_RECLAIM 100
109 * Timer index used when backing off due to memory shortage.
111 #define NOMEM_TMR_IDX (SGE_NTIMERS - 1)
114 * Suspend an Ethernet Tx queue with fewer available descriptors than this.
115 * This is the same as calc_tx_descs() for a TSO packet with
116 * nr_frags == MAX_SKB_FRAGS.
118 #define ETHTXQ_STOP_THRES \
119 (1 + DIV_ROUND_UP((3 * MAX_SKB_FRAGS) / 2 + (MAX_SKB_FRAGS & 1), 8))
122 * Suspension threshold for non-Ethernet Tx queues. We require enough room
123 * for a full sized WR.
125 #define TXQ_STOP_THRES (SGE_MAX_WR_LEN / sizeof(struct tx_desc))
128 * Max Tx descriptor space we allow for an Ethernet packet to be inlined
131 #define MAX_IMM_TX_PKT_LEN 256
134 * Max size of a WR sent through a control Tx queue.
136 #define MAX_CTRL_WR_LEN SGE_MAX_WR_LEN
138 struct tx_sw_desc { /* SW state per Tx descriptor */
140 struct ulptx_sgl *sgl;
143 struct rx_sw_desc { /* SW state per Rx descriptor */
149 * Rx buffer sizes for "useskbs" Free List buffers (one ingress packet pe skb
150 * buffer). We currently only support two sizes for 1500- and 9000-byte MTUs.
151 * We could easily support more but there doesn't seem to be much need for
154 #define FL_MTU_SMALL 1500
155 #define FL_MTU_LARGE 9000
157 static inline unsigned int fl_mtu_bufsize(struct adapter *adapter,
160 struct sge *s = &adapter->sge;
162 return ALIGN(s->pktshift + ETH_HLEN + VLAN_HLEN + mtu, s->fl_align);
165 #define FL_MTU_SMALL_BUFSIZE(adapter) fl_mtu_bufsize(adapter, FL_MTU_SMALL)
166 #define FL_MTU_LARGE_BUFSIZE(adapter) fl_mtu_bufsize(adapter, FL_MTU_LARGE)
169 * Bits 0..3 of rx_sw_desc.dma_addr have special meaning. The hardware uses
170 * these to specify the buffer size as an index into the SGE Free List Buffer
171 * Size register array. We also use bit 4, when the buffer has been unmapped
172 * for DMA, but this is of course never sent to the hardware and is only used
173 * to prevent double unmappings. All of the above requires that the Free List
174 * Buffers which we allocate have the bottom 5 bits free (0) -- i.e. are
175 * 32-byte or or a power of 2 greater in alignment. Since the SGE's minimal
176 * Free List Buffer alignment is 32 bytes, this works out for us ...
179 RX_BUF_FLAGS = 0x1f, /* bottom five bits are special */
180 RX_BUF_SIZE = 0x0f, /* bottom three bits are for buf sizes */
181 RX_UNMAPPED_BUF = 0x10, /* buffer is not mapped */
184 * XXX We shouldn't depend on being able to use these indices.
185 * XXX Especially when some other Master PF has initialized the
186 * XXX adapter or we use the Firmware Configuration File. We
187 * XXX should really search through the Host Buffer Size register
188 * XXX array for the appropriately sized buffer indices.
190 RX_SMALL_PG_BUF = 0x0, /* small (PAGE_SIZE) page buffer */
191 RX_LARGE_PG_BUF = 0x1, /* buffer large (FL_PG_ORDER) page buffer */
193 RX_SMALL_MTU_BUF = 0x2, /* small MTU buffer */
194 RX_LARGE_MTU_BUF = 0x3, /* large MTU buffer */
197 static int timer_pkt_quota[] = {1, 1, 2, 3, 4, 5};
198 #define MIN_NAPI_WORK 1
200 static inline dma_addr_t get_buf_addr(const struct rx_sw_desc *d)
202 return d->dma_addr & ~(dma_addr_t)RX_BUF_FLAGS;
205 static inline bool is_buf_mapped(const struct rx_sw_desc *d)
207 return !(d->dma_addr & RX_UNMAPPED_BUF);
211 * txq_avail - return the number of available slots in a Tx queue
214 * Returns the number of descriptors in a Tx queue available to write new
217 static inline unsigned int txq_avail(const struct sge_txq *q)
219 return q->size - 1 - q->in_use;
223 * fl_cap - return the capacity of a free-buffer list
226 * Returns the capacity of a free-buffer list. The capacity is less than
227 * the size because one descriptor needs to be left unpopulated, otherwise
228 * HW will think the FL is empty.
230 static inline unsigned int fl_cap(const struct sge_fl *fl)
232 return fl->size - 8; /* 1 descriptor = 8 buffers */
236 * fl_starving - return whether a Free List is starving.
237 * @adapter: pointer to the adapter
240 * Tests specified Free List to see whether the number of buffers
241 * available to the hardware has falled below our "starvation"
244 static inline bool fl_starving(const struct adapter *adapter,
245 const struct sge_fl *fl)
247 const struct sge *s = &adapter->sge;
249 return fl->avail - fl->pend_cred <= s->fl_starve_thres;
252 static int map_skb(struct device *dev, const struct sk_buff *skb,
255 const skb_frag_t *fp, *end;
256 const struct skb_shared_info *si;
258 *addr = dma_map_single(dev, skb->data, skb_headlen(skb), DMA_TO_DEVICE);
259 if (dma_mapping_error(dev, *addr))
262 si = skb_shinfo(skb);
263 end = &si->frags[si->nr_frags];
265 for (fp = si->frags; fp < end; fp++) {
266 *++addr = skb_frag_dma_map(dev, fp, 0, skb_frag_size(fp),
268 if (dma_mapping_error(dev, *addr))
274 while (fp-- > si->frags)
275 dma_unmap_page(dev, *--addr, skb_frag_size(fp), DMA_TO_DEVICE);
277 dma_unmap_single(dev, addr[-1], skb_headlen(skb), DMA_TO_DEVICE);
282 #ifdef CONFIG_NEED_DMA_MAP_STATE
283 static void unmap_skb(struct device *dev, const struct sk_buff *skb,
284 const dma_addr_t *addr)
286 const skb_frag_t *fp, *end;
287 const struct skb_shared_info *si;
289 dma_unmap_single(dev, *addr++, skb_headlen(skb), DMA_TO_DEVICE);
291 si = skb_shinfo(skb);
292 end = &si->frags[si->nr_frags];
293 for (fp = si->frags; fp < end; fp++)
294 dma_unmap_page(dev, *addr++, skb_frag_size(fp), DMA_TO_DEVICE);
298 * deferred_unmap_destructor - unmap a packet when it is freed
301 * This is the packet destructor used for Tx packets that need to remain
302 * mapped until they are freed rather than until their Tx descriptors are
305 static void deferred_unmap_destructor(struct sk_buff *skb)
307 unmap_skb(skb->dev->dev.parent, skb, (dma_addr_t *)skb->head);
311 static void unmap_sgl(struct device *dev, const struct sk_buff *skb,
312 const struct ulptx_sgl *sgl, const struct sge_txq *q)
314 const struct ulptx_sge_pair *p;
315 unsigned int nfrags = skb_shinfo(skb)->nr_frags;
317 if (likely(skb_headlen(skb)))
318 dma_unmap_single(dev, be64_to_cpu(sgl->addr0), ntohl(sgl->len0),
321 dma_unmap_page(dev, be64_to_cpu(sgl->addr0), ntohl(sgl->len0),
327 * the complexity below is because of the possibility of a wrap-around
328 * in the middle of an SGL
330 for (p = sgl->sge; nfrags >= 2; nfrags -= 2) {
331 if (likely((u8 *)(p + 1) <= (u8 *)q->stat)) {
332 unmap: dma_unmap_page(dev, be64_to_cpu(p->addr[0]),
333 ntohl(p->len[0]), DMA_TO_DEVICE);
334 dma_unmap_page(dev, be64_to_cpu(p->addr[1]),
335 ntohl(p->len[1]), DMA_TO_DEVICE);
337 } else if ((u8 *)p == (u8 *)q->stat) {
338 p = (const struct ulptx_sge_pair *)q->desc;
340 } else if ((u8 *)p + 8 == (u8 *)q->stat) {
341 const __be64 *addr = (const __be64 *)q->desc;
343 dma_unmap_page(dev, be64_to_cpu(addr[0]),
344 ntohl(p->len[0]), DMA_TO_DEVICE);
345 dma_unmap_page(dev, be64_to_cpu(addr[1]),
346 ntohl(p->len[1]), DMA_TO_DEVICE);
347 p = (const struct ulptx_sge_pair *)&addr[2];
349 const __be64 *addr = (const __be64 *)q->desc;
351 dma_unmap_page(dev, be64_to_cpu(p->addr[0]),
352 ntohl(p->len[0]), DMA_TO_DEVICE);
353 dma_unmap_page(dev, be64_to_cpu(addr[0]),
354 ntohl(p->len[1]), DMA_TO_DEVICE);
355 p = (const struct ulptx_sge_pair *)&addr[1];
361 if ((u8 *)p == (u8 *)q->stat)
362 p = (const struct ulptx_sge_pair *)q->desc;
363 addr = (u8 *)p + 16 <= (u8 *)q->stat ? p->addr[0] :
364 *(const __be64 *)q->desc;
365 dma_unmap_page(dev, be64_to_cpu(addr), ntohl(p->len[0]),
371 * free_tx_desc - reclaims Tx descriptors and their buffers
372 * @adapter: the adapter
373 * @q: the Tx queue to reclaim descriptors from
374 * @n: the number of descriptors to reclaim
375 * @unmap: whether the buffers should be unmapped for DMA
377 * Reclaims Tx descriptors from an SGE Tx queue and frees the associated
378 * Tx buffers. Called with the Tx queue lock held.
380 static void free_tx_desc(struct adapter *adap, struct sge_txq *q,
381 unsigned int n, bool unmap)
383 struct tx_sw_desc *d;
384 unsigned int cidx = q->cidx;
385 struct device *dev = adap->pdev_dev;
389 if (d->skb) { /* an SGL is present */
391 unmap_sgl(dev, d->skb, d->sgl, q);
392 dev_consume_skb_any(d->skb);
396 if (++cidx == q->size) {
405 * Return the number of reclaimable descriptors in a Tx queue.
407 static inline int reclaimable(const struct sge_txq *q)
409 int hw_cidx = ntohs(q->stat->cidx);
411 return hw_cidx < 0 ? hw_cidx + q->size : hw_cidx;
415 * reclaim_completed_tx - reclaims completed Tx descriptors
417 * @q: the Tx queue to reclaim completed descriptors from
418 * @unmap: whether the buffers should be unmapped for DMA
420 * Reclaims Tx descriptors that the SGE has indicated it has processed,
421 * and frees the associated buffers if possible. Called with the Tx
424 static inline void reclaim_completed_tx(struct adapter *adap, struct sge_txq *q,
427 int avail = reclaimable(q);
431 * Limit the amount of clean up work we do at a time to keep
432 * the Tx lock hold time O(1).
434 if (avail > MAX_TX_RECLAIM)
435 avail = MAX_TX_RECLAIM;
437 free_tx_desc(adap, q, avail, unmap);
442 static inline int get_buf_size(struct adapter *adapter,
443 const struct rx_sw_desc *d)
445 struct sge *s = &adapter->sge;
446 unsigned int rx_buf_size_idx = d->dma_addr & RX_BUF_SIZE;
449 switch (rx_buf_size_idx) {
450 case RX_SMALL_PG_BUF:
451 buf_size = PAGE_SIZE;
454 case RX_LARGE_PG_BUF:
455 buf_size = PAGE_SIZE << s->fl_pg_order;
458 case RX_SMALL_MTU_BUF:
459 buf_size = FL_MTU_SMALL_BUFSIZE(adapter);
462 case RX_LARGE_MTU_BUF:
463 buf_size = FL_MTU_LARGE_BUFSIZE(adapter);
474 * free_rx_bufs - free the Rx buffers on an SGE free list
476 * @q: the SGE free list to free buffers from
477 * @n: how many buffers to free
479 * Release the next @n buffers on an SGE free-buffer Rx queue. The
480 * buffers must be made inaccessible to HW before calling this function.
482 static void free_rx_bufs(struct adapter *adap, struct sge_fl *q, int n)
485 struct rx_sw_desc *d = &q->sdesc[q->cidx];
487 if (is_buf_mapped(d))
488 dma_unmap_page(adap->pdev_dev, get_buf_addr(d),
489 get_buf_size(adap, d),
493 if (++q->cidx == q->size)
500 * unmap_rx_buf - unmap the current Rx buffer on an SGE free list
502 * @q: the SGE free list
504 * Unmap the current buffer on an SGE free-buffer Rx queue. The
505 * buffer must be made inaccessible to HW before calling this function.
507 * This is similar to @free_rx_bufs above but does not free the buffer.
508 * Do note that the FL still loses any further access to the buffer.
510 static void unmap_rx_buf(struct adapter *adap, struct sge_fl *q)
512 struct rx_sw_desc *d = &q->sdesc[q->cidx];
514 if (is_buf_mapped(d))
515 dma_unmap_page(adap->pdev_dev, get_buf_addr(d),
516 get_buf_size(adap, d), PCI_DMA_FROMDEVICE);
518 if (++q->cidx == q->size)
523 static inline void ring_fl_db(struct adapter *adap, struct sge_fl *q)
525 if (q->pend_cred >= 8) {
526 u32 val = adap->params.arch.sge_fl_db;
528 if (is_t4(adap->params.chip))
529 val |= PIDX_V(q->pend_cred / 8);
531 val |= PIDX_T5_V(q->pend_cred / 8);
533 /* Make sure all memory writes to the Free List queue are
534 * committed before we tell the hardware about them.
538 /* If we don't have access to the new User Doorbell (T5+), use
539 * the old doorbell mechanism; otherwise use the new BAR2
542 if (unlikely(q->bar2_addr == NULL)) {
543 t4_write_reg(adap, MYPF_REG(SGE_PF_KDOORBELL_A),
544 val | QID_V(q->cntxt_id));
546 writel(val | QID_V(q->bar2_qid),
547 q->bar2_addr + SGE_UDB_KDOORBELL);
549 /* This Write memory Barrier will force the write to
550 * the User Doorbell area to be flushed.
558 static inline void set_rx_sw_desc(struct rx_sw_desc *sd, struct page *pg,
562 sd->dma_addr = mapping; /* includes size low bits */
566 * refill_fl - refill an SGE Rx buffer ring
568 * @q: the ring to refill
569 * @n: the number of new buffers to allocate
570 * @gfp: the gfp flags for the allocations
572 * (Re)populate an SGE free-buffer queue with up to @n new packet buffers,
573 * allocated with the supplied gfp flags. The caller must assure that
574 * @n does not exceed the queue's capacity. If afterwards the queue is
575 * found critically low mark it as starving in the bitmap of starving FLs.
577 * Returns the number of buffers allocated.
579 static unsigned int refill_fl(struct adapter *adap, struct sge_fl *q, int n,
582 struct sge *s = &adap->sge;
585 unsigned int cred = q->avail;
586 __be64 *d = &q->desc[q->pidx];
587 struct rx_sw_desc *sd = &q->sdesc[q->pidx];
590 #ifdef CONFIG_DEBUG_FS
591 if (test_bit(q->cntxt_id - adap->sge.egr_start, adap->sge.blocked_fl))
596 node = dev_to_node(adap->pdev_dev);
598 if (s->fl_pg_order == 0)
599 goto alloc_small_pages;
602 * Prefer large buffers
605 pg = alloc_pages_node(node, gfp | __GFP_COMP, s->fl_pg_order);
607 q->large_alloc_failed++;
608 break; /* fall back to single pages */
611 mapping = dma_map_page(adap->pdev_dev, pg, 0,
612 PAGE_SIZE << s->fl_pg_order,
614 if (unlikely(dma_mapping_error(adap->pdev_dev, mapping))) {
615 __free_pages(pg, s->fl_pg_order);
616 goto out; /* do not try small pages for this error */
618 mapping |= RX_LARGE_PG_BUF;
619 *d++ = cpu_to_be64(mapping);
621 set_rx_sw_desc(sd, pg, mapping);
625 if (++q->pidx == q->size) {
635 pg = alloc_pages_node(node, gfp, 0);
641 mapping = dma_map_page(adap->pdev_dev, pg, 0, PAGE_SIZE,
643 if (unlikely(dma_mapping_error(adap->pdev_dev, mapping))) {
647 *d++ = cpu_to_be64(mapping);
649 set_rx_sw_desc(sd, pg, mapping);
653 if (++q->pidx == q->size) {
660 out: cred = q->avail - cred;
661 q->pend_cred += cred;
664 if (unlikely(fl_starving(adap, q))) {
666 set_bit(q->cntxt_id - adap->sge.egr_start,
667 adap->sge.starving_fl);
673 static inline void __refill_fl(struct adapter *adap, struct sge_fl *fl)
675 refill_fl(adap, fl, min(MAX_RX_REFILL, fl_cap(fl) - fl->avail),
680 * alloc_ring - allocate resources for an SGE descriptor ring
681 * @dev: the PCI device's core device
682 * @nelem: the number of descriptors
683 * @elem_size: the size of each descriptor
684 * @sw_size: the size of the SW state associated with each ring element
685 * @phys: the physical address of the allocated ring
686 * @metadata: address of the array holding the SW state for the ring
687 * @stat_size: extra space in HW ring for status information
688 * @node: preferred node for memory allocations
690 * Allocates resources for an SGE descriptor ring, such as Tx queues,
691 * free buffer lists, or response queues. Each SGE ring requires
692 * space for its HW descriptors plus, optionally, space for the SW state
693 * associated with each HW entry (the metadata). The function returns
694 * three values: the virtual address for the HW ring (the return value
695 * of the function), the bus address of the HW ring, and the address
698 static void *alloc_ring(struct device *dev, size_t nelem, size_t elem_size,
699 size_t sw_size, dma_addr_t *phys, void *metadata,
700 size_t stat_size, int node)
702 size_t len = nelem * elem_size + stat_size;
704 void *p = dma_alloc_coherent(dev, len, phys, GFP_KERNEL);
709 s = kzalloc_node(nelem * sw_size, GFP_KERNEL, node);
712 dma_free_coherent(dev, len, p, *phys);
717 *(void **)metadata = s;
723 * sgl_len - calculates the size of an SGL of the given capacity
724 * @n: the number of SGL entries
726 * Calculates the number of flits needed for a scatter/gather list that
727 * can hold the given number of entries.
729 static inline unsigned int sgl_len(unsigned int n)
731 /* A Direct Scatter Gather List uses 32-bit lengths and 64-bit PCI DMA
732 * addresses. The DSGL Work Request starts off with a 32-bit DSGL
733 * ULPTX header, then Length0, then Address0, then, for 1 <= i <= N,
734 * repeated sequences of { Length[i], Length[i+1], Address[i],
735 * Address[i+1] } (this ensures that all addresses are on 64-bit
736 * boundaries). If N is even, then Length[N+1] should be set to 0 and
737 * Address[N+1] is omitted.
739 * The following calculation incorporates all of the above. It's
740 * somewhat hard to follow but, briefly: the "+2" accounts for the
741 * first two flits which include the DSGL header, Length0 and
742 * Address0; the "(3*(n-1))/2" covers the main body of list entries (3
743 * flits for every pair of the remaining N) +1 if (n-1) is odd; and
744 * finally the "+((n-1)&1)" adds the one remaining flit needed if
748 return (3 * n) / 2 + (n & 1) + 2;
752 * flits_to_desc - returns the num of Tx descriptors for the given flits
753 * @n: the number of flits
755 * Returns the number of Tx descriptors needed for the supplied number
758 static inline unsigned int flits_to_desc(unsigned int n)
760 BUG_ON(n > SGE_MAX_WR_LEN / 8);
761 return DIV_ROUND_UP(n, 8);
765 * is_eth_imm - can an Ethernet packet be sent as immediate data?
768 * Returns whether an Ethernet packet is small enough to fit as
769 * immediate data. Return value corresponds to headroom required.
771 static inline int is_eth_imm(const struct sk_buff *skb)
773 int hdrlen = skb_shinfo(skb)->gso_size ?
774 sizeof(struct cpl_tx_pkt_lso_core) : 0;
776 hdrlen += sizeof(struct cpl_tx_pkt);
777 if (skb->len <= MAX_IMM_TX_PKT_LEN - hdrlen)
783 * calc_tx_flits - calculate the number of flits for a packet Tx WR
786 * Returns the number of flits needed for a Tx WR for the given Ethernet
787 * packet, including the needed WR and CPL headers.
789 static inline unsigned int calc_tx_flits(const struct sk_buff *skb)
792 int hdrlen = is_eth_imm(skb);
794 /* If the skb is small enough, we can pump it out as a work request
795 * with only immediate data. In that case we just have to have the
796 * TX Packet header plus the skb data in the Work Request.
800 return DIV_ROUND_UP(skb->len + hdrlen, sizeof(__be64));
802 /* Otherwise, we're going to have to construct a Scatter gather list
803 * of the skb body and fragments. We also include the flits necessary
804 * for the TX Packet Work Request and CPL. We always have a firmware
805 * Write Header (incorporated as part of the cpl_tx_pkt_lso and
806 * cpl_tx_pkt structures), followed by either a TX Packet Write CPL
807 * message or, if we're doing a Large Send Offload, an LSO CPL message
808 * with an embedded TX Packet Write CPL message.
810 flits = sgl_len(skb_shinfo(skb)->nr_frags + 1) + 4;
811 if (skb_shinfo(skb)->gso_size)
812 flits += (sizeof(struct fw_eth_tx_pkt_wr) +
813 sizeof(struct cpl_tx_pkt_lso_core) +
814 sizeof(struct cpl_tx_pkt_core)) / sizeof(__be64);
816 flits += (sizeof(struct fw_eth_tx_pkt_wr) +
817 sizeof(struct cpl_tx_pkt_core)) / sizeof(__be64);
822 * calc_tx_descs - calculate the number of Tx descriptors for a packet
825 * Returns the number of Tx descriptors needed for the given Ethernet
826 * packet, including the needed WR and CPL headers.
828 static inline unsigned int calc_tx_descs(const struct sk_buff *skb)
830 return flits_to_desc(calc_tx_flits(skb));
834 * write_sgl - populate a scatter/gather list for a packet
836 * @q: the Tx queue we are writing into
837 * @sgl: starting location for writing the SGL
838 * @end: points right after the end of the SGL
839 * @start: start offset into skb main-body data to include in the SGL
840 * @addr: the list of bus addresses for the SGL elements
842 * Generates a gather list for the buffers that make up a packet.
843 * The caller must provide adequate space for the SGL that will be written.
844 * The SGL includes all of the packet's page fragments and the data in its
845 * main body except for the first @start bytes. @sgl must be 16-byte
846 * aligned and within a Tx descriptor with available space. @end points
847 * right after the end of the SGL but does not account for any potential
848 * wrap around, i.e., @end > @sgl.
850 static void write_sgl(const struct sk_buff *skb, struct sge_txq *q,
851 struct ulptx_sgl *sgl, u64 *end, unsigned int start,
852 const dma_addr_t *addr)
855 struct ulptx_sge_pair *to;
856 const struct skb_shared_info *si = skb_shinfo(skb);
857 unsigned int nfrags = si->nr_frags;
858 struct ulptx_sge_pair buf[MAX_SKB_FRAGS / 2 + 1];
860 len = skb_headlen(skb) - start;
862 sgl->len0 = htonl(len);
863 sgl->addr0 = cpu_to_be64(addr[0] + start);
866 sgl->len0 = htonl(skb_frag_size(&si->frags[0]));
867 sgl->addr0 = cpu_to_be64(addr[1]);
870 sgl->cmd_nsge = htonl(ULPTX_CMD_V(ULP_TX_SC_DSGL) |
871 ULPTX_NSGE_V(nfrags));
872 if (likely(--nfrags == 0))
875 * Most of the complexity below deals with the possibility we hit the
876 * end of the queue in the middle of writing the SGL. For this case
877 * only we create the SGL in a temporary buffer and then copy it.
879 to = (u8 *)end > (u8 *)q->stat ? buf : sgl->sge;
881 for (i = (nfrags != si->nr_frags); nfrags >= 2; nfrags -= 2, to++) {
882 to->len[0] = cpu_to_be32(skb_frag_size(&si->frags[i]));
883 to->len[1] = cpu_to_be32(skb_frag_size(&si->frags[++i]));
884 to->addr[0] = cpu_to_be64(addr[i]);
885 to->addr[1] = cpu_to_be64(addr[++i]);
888 to->len[0] = cpu_to_be32(skb_frag_size(&si->frags[i]));
889 to->len[1] = cpu_to_be32(0);
890 to->addr[0] = cpu_to_be64(addr[i + 1]);
892 if (unlikely((u8 *)end > (u8 *)q->stat)) {
893 unsigned int part0 = (u8 *)q->stat - (u8 *)sgl->sge, part1;
896 memcpy(sgl->sge, buf, part0);
897 part1 = (u8 *)end - (u8 *)q->stat;
898 memcpy(q->desc, (u8 *)buf + part0, part1);
899 end = (void *)q->desc + part1;
901 if ((uintptr_t)end & 8) /* 0-pad to multiple of 16 */
905 /* This function copies 64 byte coalesced work request to
906 * memory mapped BAR2 space. For coalesced WR SGE fetches
907 * data from the FIFO instead of from Host.
909 static void cxgb_pio_copy(u64 __iomem *dst, u64 *src)
922 * ring_tx_db - check and potentially ring a Tx queue's doorbell
925 * @n: number of new descriptors to give to HW
927 * Ring the doorbel for a Tx queue.
929 static inline void ring_tx_db(struct adapter *adap, struct sge_txq *q, int n)
931 /* Make sure that all writes to the TX Descriptors are committed
932 * before we tell the hardware about them.
936 /* If we don't have access to the new User Doorbell (T5+), use the old
937 * doorbell mechanism; otherwise use the new BAR2 mechanism.
939 if (unlikely(q->bar2_addr == NULL)) {
943 /* For T4 we need to participate in the Doorbell Recovery
946 spin_lock_irqsave(&q->db_lock, flags);
948 t4_write_reg(adap, MYPF_REG(SGE_PF_KDOORBELL_A),
949 QID_V(q->cntxt_id) | val);
952 q->db_pidx = q->pidx;
953 spin_unlock_irqrestore(&q->db_lock, flags);
955 u32 val = PIDX_T5_V(n);
957 /* T4 and later chips share the same PIDX field offset within
958 * the doorbell, but T5 and later shrank the field in order to
959 * gain a bit for Doorbell Priority. The field was absurdly
960 * large in the first place (14 bits) so we just use the T5
961 * and later limits and warn if a Queue ID is too large.
963 WARN_ON(val & DBPRIO_F);
965 /* If we're only writing a single TX Descriptor and we can use
966 * Inferred QID registers, we can use the Write Combining
967 * Gather Buffer; otherwise we use the simple doorbell.
969 if (n == 1 && q->bar2_qid == 0) {
973 u64 *wr = (u64 *)&q->desc[index];
975 cxgb_pio_copy((u64 __iomem *)
976 (q->bar2_addr + SGE_UDB_WCDOORBELL),
979 writel(val | QID_V(q->bar2_qid),
980 q->bar2_addr + SGE_UDB_KDOORBELL);
983 /* This Write Memory Barrier will force the write to the User
984 * Doorbell area to be flushed. This is needed to prevent
985 * writes on different CPUs for the same queue from hitting
986 * the adapter out of order. This is required when some Work
987 * Requests take the Write Combine Gather Buffer path (user
988 * doorbell area offset [SGE_UDB_WCDOORBELL..+63]) and some
989 * take the traditional path where we simply increment the
990 * PIDX (User Doorbell area SGE_UDB_KDOORBELL) and have the
991 * hardware DMA read the actual Work Request.
998 * inline_tx_skb - inline a packet's data into Tx descriptors
1000 * @q: the Tx queue where the packet will be inlined
1001 * @pos: starting position in the Tx queue where to inline the packet
1003 * Inline a packet's contents directly into Tx descriptors, starting at
1004 * the given position within the Tx DMA ring.
1005 * Most of the complexity of this operation is dealing with wrap arounds
1006 * in the middle of the packet we want to inline.
1008 static void inline_tx_skb(const struct sk_buff *skb, const struct sge_txq *q,
1012 int left = (void *)q->stat - pos;
1014 if (likely(skb->len <= left)) {
1015 if (likely(!skb->data_len))
1016 skb_copy_from_linear_data(skb, pos, skb->len);
1018 skb_copy_bits(skb, 0, pos, skb->len);
1021 skb_copy_bits(skb, 0, pos, left);
1022 skb_copy_bits(skb, left, q->desc, skb->len - left);
1023 pos = (void *)q->desc + (skb->len - left);
1026 /* 0-pad to multiple of 16 */
1027 p = PTR_ALIGN(pos, 8);
1028 if ((uintptr_t)p & 8)
1033 * Figure out what HW csum a packet wants and return the appropriate control
1036 static u64 hwcsum(enum chip_type chip, const struct sk_buff *skb)
1039 const struct iphdr *iph = ip_hdr(skb);
1041 if (iph->version == 4) {
1042 if (iph->protocol == IPPROTO_TCP)
1043 csum_type = TX_CSUM_TCPIP;
1044 else if (iph->protocol == IPPROTO_UDP)
1045 csum_type = TX_CSUM_UDPIP;
1048 * unknown protocol, disable HW csum
1049 * and hope a bad packet is detected
1051 return TXPKT_L4CSUM_DIS_F;
1055 * this doesn't work with extension headers
1057 const struct ipv6hdr *ip6h = (const struct ipv6hdr *)iph;
1059 if (ip6h->nexthdr == IPPROTO_TCP)
1060 csum_type = TX_CSUM_TCPIP6;
1061 else if (ip6h->nexthdr == IPPROTO_UDP)
1062 csum_type = TX_CSUM_UDPIP6;
1067 if (likely(csum_type >= TX_CSUM_TCPIP)) {
1068 u64 hdr_len = TXPKT_IPHDR_LEN_V(skb_network_header_len(skb));
1069 int eth_hdr_len = skb_network_offset(skb) - ETH_HLEN;
1071 if (CHELSIO_CHIP_VERSION(chip) <= CHELSIO_T5)
1072 hdr_len |= TXPKT_ETHHDR_LEN_V(eth_hdr_len);
1074 hdr_len |= T6_TXPKT_ETHHDR_LEN_V(eth_hdr_len);
1075 return TXPKT_CSUM_TYPE_V(csum_type) | hdr_len;
1077 int start = skb_transport_offset(skb);
1079 return TXPKT_CSUM_TYPE_V(csum_type) |
1080 TXPKT_CSUM_START_V(start) |
1081 TXPKT_CSUM_LOC_V(start + skb->csum_offset);
1085 static void eth_txq_stop(struct sge_eth_txq *q)
1087 netif_tx_stop_queue(q->txq);
1091 static inline void txq_advance(struct sge_txq *q, unsigned int n)
1095 if (q->pidx >= q->size)
1099 #ifdef CONFIG_CHELSIO_T4_FCOE
1101 cxgb_fcoe_offload(struct sk_buff *skb, struct adapter *adap,
1102 const struct port_info *pi, u64 *cntrl)
1104 const struct cxgb_fcoe *fcoe = &pi->fcoe;
1106 if (!(fcoe->flags & CXGB_FCOE_ENABLED))
1109 if (skb->protocol != htons(ETH_P_FCOE))
1112 skb_reset_mac_header(skb);
1113 skb->mac_len = sizeof(struct ethhdr);
1115 skb_set_network_header(skb, skb->mac_len);
1116 skb_set_transport_header(skb, skb->mac_len + sizeof(struct fcoe_hdr));
1118 if (!cxgb_fcoe_sof_eof_supported(adap, skb))
1121 /* FC CRC offload */
1122 *cntrl = TXPKT_CSUM_TYPE_V(TX_CSUM_FCOE) |
1123 TXPKT_L4CSUM_DIS_F | TXPKT_IPCSUM_DIS_F |
1124 TXPKT_CSUM_START_V(CXGB_FCOE_TXPKT_CSUM_START) |
1125 TXPKT_CSUM_END_V(CXGB_FCOE_TXPKT_CSUM_END) |
1126 TXPKT_CSUM_LOC_V(CXGB_FCOE_TXPKT_CSUM_END);
1129 #endif /* CONFIG_CHELSIO_T4_FCOE */
1132 * t4_eth_xmit - add a packet to an Ethernet Tx queue
1134 * @dev: the egress net device
1136 * Add a packet to an SGE Ethernet Tx queue. Runs with softirqs disabled.
1138 netdev_tx_t t4_eth_xmit(struct sk_buff *skb, struct net_device *dev)
1143 unsigned int flits, ndesc;
1144 struct adapter *adap;
1145 struct sge_eth_txq *q;
1146 const struct port_info *pi;
1147 struct fw_eth_tx_pkt_wr *wr;
1148 struct cpl_tx_pkt_core *cpl;
1149 const struct skb_shared_info *ssi;
1150 dma_addr_t addr[MAX_SKB_FRAGS + 1];
1151 bool immediate = false;
1152 int len, max_pkt_len;
1153 #ifdef CONFIG_CHELSIO_T4_FCOE
1155 #endif /* CONFIG_CHELSIO_T4_FCOE */
1158 * The chip min packet length is 10 octets but play safe and reject
1159 * anything shorter than an Ethernet header.
1161 if (unlikely(skb->len < ETH_HLEN)) {
1162 out_free: dev_kfree_skb_any(skb);
1163 return NETDEV_TX_OK;
1166 /* Discard the packet if the length is greater than mtu */
1167 max_pkt_len = ETH_HLEN + dev->mtu;
1168 if (skb_vlan_tag_present(skb))
1169 max_pkt_len += VLAN_HLEN;
1170 if (!skb_shinfo(skb)->gso_size && (unlikely(skb->len > max_pkt_len)))
1173 pi = netdev_priv(dev);
1175 qidx = skb_get_queue_mapping(skb);
1176 q = &adap->sge.ethtxq[qidx + pi->first_qset];
1178 reclaim_completed_tx(adap, &q->q, true);
1179 cntrl = TXPKT_L4CSUM_DIS_F | TXPKT_IPCSUM_DIS_F;
1181 #ifdef CONFIG_CHELSIO_T4_FCOE
1182 err = cxgb_fcoe_offload(skb, adap, pi, &cntrl);
1183 if (unlikely(err == -ENOTSUPP))
1185 #endif /* CONFIG_CHELSIO_T4_FCOE */
1187 flits = calc_tx_flits(skb);
1188 ndesc = flits_to_desc(flits);
1189 credits = txq_avail(&q->q) - ndesc;
1191 if (unlikely(credits < 0)) {
1193 dev_err(adap->pdev_dev,
1194 "%s: Tx ring %u full while queue awake!\n",
1196 return NETDEV_TX_BUSY;
1199 if (is_eth_imm(skb))
1203 unlikely(map_skb(adap->pdev_dev, skb, addr) < 0)) {
1208 wr_mid = FW_WR_LEN16_V(DIV_ROUND_UP(flits, 2));
1209 if (unlikely(credits < ETHTXQ_STOP_THRES)) {
1211 wr_mid |= FW_WR_EQUEQ_F | FW_WR_EQUIQ_F;
1214 wr = (void *)&q->q.desc[q->q.pidx];
1215 wr->equiq_to_len16 = htonl(wr_mid);
1216 wr->r3 = cpu_to_be64(0);
1217 end = (u64 *)wr + flits;
1219 len = immediate ? skb->len : 0;
1220 ssi = skb_shinfo(skb);
1221 if (ssi->gso_size) {
1222 struct cpl_tx_pkt_lso *lso = (void *)wr;
1223 bool v6 = (ssi->gso_type & SKB_GSO_TCPV6) != 0;
1224 int l3hdr_len = skb_network_header_len(skb);
1225 int eth_xtra_len = skb_network_offset(skb) - ETH_HLEN;
1227 len += sizeof(*lso);
1228 wr->op_immdlen = htonl(FW_WR_OP_V(FW_ETH_TX_PKT_WR) |
1229 FW_WR_IMMDLEN_V(len));
1230 lso->c.lso_ctrl = htonl(LSO_OPCODE_V(CPL_TX_PKT_LSO) |
1231 LSO_FIRST_SLICE_F | LSO_LAST_SLICE_F |
1233 LSO_ETHHDR_LEN_V(eth_xtra_len / 4) |
1234 LSO_IPHDR_LEN_V(l3hdr_len / 4) |
1235 LSO_TCPHDR_LEN_V(tcp_hdr(skb)->doff));
1236 lso->c.ipid_ofst = htons(0);
1237 lso->c.mss = htons(ssi->gso_size);
1238 lso->c.seqno_offset = htonl(0);
1239 if (is_t4(adap->params.chip))
1240 lso->c.len = htonl(skb->len);
1242 lso->c.len = htonl(LSO_T5_XFER_SIZE_V(skb->len));
1243 cpl = (void *)(lso + 1);
1245 if (CHELSIO_CHIP_VERSION(adap->params.chip) <= CHELSIO_T5)
1246 cntrl = TXPKT_ETHHDR_LEN_V(eth_xtra_len);
1248 cntrl = T6_TXPKT_ETHHDR_LEN_V(eth_xtra_len);
1250 cntrl |= TXPKT_CSUM_TYPE_V(v6 ?
1251 TX_CSUM_TCPIP6 : TX_CSUM_TCPIP) |
1252 TXPKT_IPHDR_LEN_V(l3hdr_len);
1254 q->tx_cso += ssi->gso_segs;
1256 len += sizeof(*cpl);
1257 wr->op_immdlen = htonl(FW_WR_OP_V(FW_ETH_TX_PKT_WR) |
1258 FW_WR_IMMDLEN_V(len));
1259 cpl = (void *)(wr + 1);
1260 if (skb->ip_summed == CHECKSUM_PARTIAL) {
1261 cntrl = hwcsum(adap->params.chip, skb) |
1267 if (skb_vlan_tag_present(skb)) {
1269 cntrl |= TXPKT_VLAN_VLD_F | TXPKT_VLAN_V(skb_vlan_tag_get(skb));
1270 #ifdef CONFIG_CHELSIO_T4_FCOE
1271 if (skb->protocol == htons(ETH_P_FCOE))
1272 cntrl |= TXPKT_VLAN_V(
1273 ((skb->priority & 0x7) << VLAN_PRIO_SHIFT));
1274 #endif /* CONFIG_CHELSIO_T4_FCOE */
1277 cpl->ctrl0 = htonl(TXPKT_OPCODE_V(CPL_TX_PKT_XT) |
1278 TXPKT_INTF_V(pi->tx_chan) |
1279 TXPKT_PF_V(adap->pf));
1280 cpl->pack = htons(0);
1281 cpl->len = htons(skb->len);
1282 cpl->ctrl1 = cpu_to_be64(cntrl);
1285 inline_tx_skb(skb, &q->q, cpl + 1);
1286 dev_consume_skb_any(skb);
1290 write_sgl(skb, &q->q, (struct ulptx_sgl *)(cpl + 1), end, 0,
1294 last_desc = q->q.pidx + ndesc - 1;
1295 if (last_desc >= q->q.size)
1296 last_desc -= q->q.size;
1297 q->q.sdesc[last_desc].skb = skb;
1298 q->q.sdesc[last_desc].sgl = (struct ulptx_sgl *)(cpl + 1);
1301 txq_advance(&q->q, ndesc);
1303 ring_tx_db(adap, &q->q, ndesc);
1304 return NETDEV_TX_OK;
1308 * reclaim_completed_tx_imm - reclaim completed control-queue Tx descs
1309 * @q: the SGE control Tx queue
1311 * This is a variant of reclaim_completed_tx() that is used for Tx queues
1312 * that send only immediate data (presently just the control queues) and
1313 * thus do not have any sk_buffs to release.
1315 static inline void reclaim_completed_tx_imm(struct sge_txq *q)
1317 int hw_cidx = ntohs(q->stat->cidx);
1318 int reclaim = hw_cidx - q->cidx;
1323 q->in_use -= reclaim;
1328 * is_imm - check whether a packet can be sent as immediate data
1331 * Returns true if a packet can be sent as a WR with immediate data.
1333 static inline int is_imm(const struct sk_buff *skb)
1335 return skb->len <= MAX_CTRL_WR_LEN;
1339 * ctrlq_check_stop - check if a control queue is full and should stop
1341 * @wr: most recent WR written to the queue
1343 * Check if a control queue has become full and should be stopped.
1344 * We clean up control queue descriptors very lazily, only when we are out.
1345 * If the queue is still full after reclaiming any completed descriptors
1346 * we suspend it and have the last WR wake it up.
1348 static void ctrlq_check_stop(struct sge_ctrl_txq *q, struct fw_wr_hdr *wr)
1350 reclaim_completed_tx_imm(&q->q);
1351 if (unlikely(txq_avail(&q->q) < TXQ_STOP_THRES)) {
1352 wr->lo |= htonl(FW_WR_EQUEQ_F | FW_WR_EQUIQ_F);
1359 * ctrl_xmit - send a packet through an SGE control Tx queue
1360 * @q: the control queue
1363 * Send a packet through an SGE control Tx queue. Packets sent through
1364 * a control queue must fit entirely as immediate data.
1366 static int ctrl_xmit(struct sge_ctrl_txq *q, struct sk_buff *skb)
1369 struct fw_wr_hdr *wr;
1371 if (unlikely(!is_imm(skb))) {
1374 return NET_XMIT_DROP;
1377 ndesc = DIV_ROUND_UP(skb->len, sizeof(struct tx_desc));
1378 spin_lock(&q->sendq.lock);
1380 if (unlikely(q->full)) {
1381 skb->priority = ndesc; /* save for restart */
1382 __skb_queue_tail(&q->sendq, skb);
1383 spin_unlock(&q->sendq.lock);
1387 wr = (struct fw_wr_hdr *)&q->q.desc[q->q.pidx];
1388 inline_tx_skb(skb, &q->q, wr);
1390 txq_advance(&q->q, ndesc);
1391 if (unlikely(txq_avail(&q->q) < TXQ_STOP_THRES))
1392 ctrlq_check_stop(q, wr);
1394 ring_tx_db(q->adap, &q->q, ndesc);
1395 spin_unlock(&q->sendq.lock);
1398 return NET_XMIT_SUCCESS;
1402 * restart_ctrlq - restart a suspended control queue
1403 * @data: the control queue to restart
1405 * Resumes transmission on a suspended Tx control queue.
1407 static void restart_ctrlq(unsigned long data)
1409 struct sk_buff *skb;
1410 unsigned int written = 0;
1411 struct sge_ctrl_txq *q = (struct sge_ctrl_txq *)data;
1413 spin_lock(&q->sendq.lock);
1414 reclaim_completed_tx_imm(&q->q);
1415 BUG_ON(txq_avail(&q->q) < TXQ_STOP_THRES); /* q should be empty */
1417 while ((skb = __skb_dequeue(&q->sendq)) != NULL) {
1418 struct fw_wr_hdr *wr;
1419 unsigned int ndesc = skb->priority; /* previously saved */
1422 * Write descriptors and free skbs outside the lock to limit
1423 * wait times. q->full is still set so new skbs will be queued.
1425 spin_unlock(&q->sendq.lock);
1427 wr = (struct fw_wr_hdr *)&q->q.desc[q->q.pidx];
1428 inline_tx_skb(skb, &q->q, wr);
1432 txq_advance(&q->q, ndesc);
1433 if (unlikely(txq_avail(&q->q) < TXQ_STOP_THRES)) {
1434 unsigned long old = q->q.stops;
1436 ctrlq_check_stop(q, wr);
1437 if (q->q.stops != old) { /* suspended anew */
1438 spin_lock(&q->sendq.lock);
1443 ring_tx_db(q->adap, &q->q, written);
1446 spin_lock(&q->sendq.lock);
1449 ringdb: if (written)
1450 ring_tx_db(q->adap, &q->q, written);
1451 spin_unlock(&q->sendq.lock);
1455 * t4_mgmt_tx - send a management message
1456 * @adap: the adapter
1457 * @skb: the packet containing the management message
1459 * Send a management message through control queue 0.
1461 int t4_mgmt_tx(struct adapter *adap, struct sk_buff *skb)
1466 ret = ctrl_xmit(&adap->sge.ctrlq[0], skb);
1472 * is_ofld_imm - check whether a packet can be sent as immediate data
1475 * Returns true if a packet can be sent as an offload WR with immediate
1476 * data. We currently use the same limit as for Ethernet packets.
1478 static inline int is_ofld_imm(const struct sk_buff *skb)
1480 return skb->len <= MAX_IMM_TX_PKT_LEN;
1484 * calc_tx_flits_ofld - calculate # of flits for an offload packet
1487 * Returns the number of flits needed for the given offload packet.
1488 * These packets are already fully constructed and no additional headers
1491 static inline unsigned int calc_tx_flits_ofld(const struct sk_buff *skb)
1493 unsigned int flits, cnt;
1495 if (is_ofld_imm(skb))
1496 return DIV_ROUND_UP(skb->len, 8);
1498 flits = skb_transport_offset(skb) / 8U; /* headers */
1499 cnt = skb_shinfo(skb)->nr_frags;
1500 if (skb_tail_pointer(skb) != skb_transport_header(skb))
1502 return flits + sgl_len(cnt);
1506 * txq_stop_maperr - stop a Tx queue due to I/O MMU exhaustion
1507 * @adap: the adapter
1508 * @q: the queue to stop
1510 * Mark a Tx queue stopped due to I/O MMU exhaustion and resulting
1511 * inability to map packets. A periodic timer attempts to restart
1514 static void txq_stop_maperr(struct sge_ofld_txq *q)
1518 set_bit(q->q.cntxt_id - q->adap->sge.egr_start,
1519 q->adap->sge.txq_maperr);
1523 * ofldtxq_stop - stop an offload Tx queue that has become full
1524 * @q: the queue to stop
1525 * @skb: the packet causing the queue to become full
1527 * Stops an offload Tx queue that has become full and modifies the packet
1528 * being written to request a wakeup.
1530 static void ofldtxq_stop(struct sge_ofld_txq *q, struct sk_buff *skb)
1532 struct fw_wr_hdr *wr = (struct fw_wr_hdr *)skb->data;
1534 wr->lo |= htonl(FW_WR_EQUEQ_F | FW_WR_EQUIQ_F);
1540 * service_ofldq - restart a suspended offload queue
1541 * @q: the offload queue
1543 * Services an offload Tx queue by moving packets from its packet queue
1544 * to the HW Tx ring. The function starts and ends with the queue locked.
1546 static void service_ofldq(struct sge_ofld_txq *q)
1550 struct sk_buff *skb;
1551 unsigned int written = 0;
1552 unsigned int flits, ndesc;
1554 while ((skb = skb_peek(&q->sendq)) != NULL && !q->full) {
1556 * We drop the lock but leave skb on sendq, thus retaining
1557 * exclusive access to the state of the queue.
1559 spin_unlock(&q->sendq.lock);
1561 reclaim_completed_tx(q->adap, &q->q, false);
1563 flits = skb->priority; /* previously saved */
1564 ndesc = flits_to_desc(flits);
1565 credits = txq_avail(&q->q) - ndesc;
1566 BUG_ON(credits < 0);
1567 if (unlikely(credits < TXQ_STOP_THRES))
1568 ofldtxq_stop(q, skb);
1570 pos = (u64 *)&q->q.desc[q->q.pidx];
1571 if (is_ofld_imm(skb))
1572 inline_tx_skb(skb, &q->q, pos);
1573 else if (map_skb(q->adap->pdev_dev, skb,
1574 (dma_addr_t *)skb->head)) {
1576 spin_lock(&q->sendq.lock);
1579 int last_desc, hdr_len = skb_transport_offset(skb);
1581 memcpy(pos, skb->data, hdr_len);
1582 write_sgl(skb, &q->q, (void *)pos + hdr_len,
1583 pos + flits, hdr_len,
1584 (dma_addr_t *)skb->head);
1585 #ifdef CONFIG_NEED_DMA_MAP_STATE
1586 skb->dev = q->adap->port[0];
1587 skb->destructor = deferred_unmap_destructor;
1589 last_desc = q->q.pidx + ndesc - 1;
1590 if (last_desc >= q->q.size)
1591 last_desc -= q->q.size;
1592 q->q.sdesc[last_desc].skb = skb;
1595 txq_advance(&q->q, ndesc);
1597 if (unlikely(written > 32)) {
1598 ring_tx_db(q->adap, &q->q, written);
1602 spin_lock(&q->sendq.lock);
1603 __skb_unlink(skb, &q->sendq);
1604 if (is_ofld_imm(skb))
1607 if (likely(written))
1608 ring_tx_db(q->adap, &q->q, written);
1612 * ofld_xmit - send a packet through an offload queue
1613 * @q: the Tx offload queue
1616 * Send an offload packet through an SGE offload queue.
1618 static int ofld_xmit(struct sge_ofld_txq *q, struct sk_buff *skb)
1620 skb->priority = calc_tx_flits_ofld(skb); /* save for restart */
1621 spin_lock(&q->sendq.lock);
1622 __skb_queue_tail(&q->sendq, skb);
1623 if (q->sendq.qlen == 1)
1625 spin_unlock(&q->sendq.lock);
1626 return NET_XMIT_SUCCESS;
1630 * restart_ofldq - restart a suspended offload queue
1631 * @data: the offload queue to restart
1633 * Resumes transmission on a suspended Tx offload queue.
1635 static void restart_ofldq(unsigned long data)
1637 struct sge_ofld_txq *q = (struct sge_ofld_txq *)data;
1639 spin_lock(&q->sendq.lock);
1640 q->full = 0; /* the queue actually is completely empty now */
1642 spin_unlock(&q->sendq.lock);
1646 * skb_txq - return the Tx queue an offload packet should use
1649 * Returns the Tx queue an offload packet should use as indicated by bits
1650 * 1-15 in the packet's queue_mapping.
1652 static inline unsigned int skb_txq(const struct sk_buff *skb)
1654 return skb->queue_mapping >> 1;
1658 * is_ctrl_pkt - return whether an offload packet is a control packet
1661 * Returns whether an offload packet should use an OFLD or a CTRL
1662 * Tx queue as indicated by bit 0 in the packet's queue_mapping.
1664 static inline unsigned int is_ctrl_pkt(const struct sk_buff *skb)
1666 return skb->queue_mapping & 1;
1669 static inline int ofld_send(struct adapter *adap, struct sk_buff *skb)
1671 unsigned int idx = skb_txq(skb);
1673 if (unlikely(is_ctrl_pkt(skb))) {
1674 /* Single ctrl queue is a requirement for LE workaround path */
1675 if (adap->tids.nsftids)
1677 return ctrl_xmit(&adap->sge.ctrlq[idx], skb);
1679 return ofld_xmit(&adap->sge.ofldtxq[idx], skb);
1683 * t4_ofld_send - send an offload packet
1684 * @adap: the adapter
1687 * Sends an offload packet. We use the packet queue_mapping to select the
1688 * appropriate Tx queue as follows: bit 0 indicates whether the packet
1689 * should be sent as regular or control, bits 1-15 select the queue.
1691 int t4_ofld_send(struct adapter *adap, struct sk_buff *skb)
1696 ret = ofld_send(adap, skb);
1702 * cxgb4_ofld_send - send an offload packet
1703 * @dev: the net device
1706 * Sends an offload packet. This is an exported version of @t4_ofld_send,
1707 * intended for ULDs.
1709 int cxgb4_ofld_send(struct net_device *dev, struct sk_buff *skb)
1711 return t4_ofld_send(netdev2adap(dev), skb);
1713 EXPORT_SYMBOL(cxgb4_ofld_send);
1715 static inline void copy_frags(struct sk_buff *skb,
1716 const struct pkt_gl *gl, unsigned int offset)
1720 /* usually there's just one frag */
1721 __skb_fill_page_desc(skb, 0, gl->frags[0].page,
1722 gl->frags[0].offset + offset,
1723 gl->frags[0].size - offset);
1724 skb_shinfo(skb)->nr_frags = gl->nfrags;
1725 for (i = 1; i < gl->nfrags; i++)
1726 __skb_fill_page_desc(skb, i, gl->frags[i].page,
1727 gl->frags[i].offset,
1730 /* get a reference to the last page, we don't own it */
1731 get_page(gl->frags[gl->nfrags - 1].page);
1735 * cxgb4_pktgl_to_skb - build an sk_buff from a packet gather list
1736 * @gl: the gather list
1737 * @skb_len: size of sk_buff main body if it carries fragments
1738 * @pull_len: amount of data to move to the sk_buff's main body
1740 * Builds an sk_buff from the given packet gather list. Returns the
1741 * sk_buff or %NULL if sk_buff allocation failed.
1743 struct sk_buff *cxgb4_pktgl_to_skb(const struct pkt_gl *gl,
1744 unsigned int skb_len, unsigned int pull_len)
1746 struct sk_buff *skb;
1749 * Below we rely on RX_COPY_THRES being less than the smallest Rx buffer
1750 * size, which is expected since buffers are at least PAGE_SIZEd.
1751 * In this case packets up to RX_COPY_THRES have only one fragment.
1753 if (gl->tot_len <= RX_COPY_THRES) {
1754 skb = dev_alloc_skb(gl->tot_len);
1757 __skb_put(skb, gl->tot_len);
1758 skb_copy_to_linear_data(skb, gl->va, gl->tot_len);
1760 skb = dev_alloc_skb(skb_len);
1763 __skb_put(skb, pull_len);
1764 skb_copy_to_linear_data(skb, gl->va, pull_len);
1766 copy_frags(skb, gl, pull_len);
1767 skb->len = gl->tot_len;
1768 skb->data_len = skb->len - pull_len;
1769 skb->truesize += skb->data_len;
1773 EXPORT_SYMBOL(cxgb4_pktgl_to_skb);
1776 * t4_pktgl_free - free a packet gather list
1777 * @gl: the gather list
1779 * Releases the pages of a packet gather list. We do not own the last
1780 * page on the list and do not free it.
1782 static void t4_pktgl_free(const struct pkt_gl *gl)
1785 const struct page_frag *p;
1787 for (p = gl->frags, n = gl->nfrags - 1; n--; p++)
1792 * Process an MPS trace packet. Give it an unused protocol number so it won't
1793 * be delivered to anyone and send it to the stack for capture.
1795 static noinline int handle_trace_pkt(struct adapter *adap,
1796 const struct pkt_gl *gl)
1798 struct sk_buff *skb;
1800 skb = cxgb4_pktgl_to_skb(gl, RX_PULL_LEN, RX_PULL_LEN);
1801 if (unlikely(!skb)) {
1806 if (is_t4(adap->params.chip))
1807 __skb_pull(skb, sizeof(struct cpl_trace_pkt));
1809 __skb_pull(skb, sizeof(struct cpl_t5_trace_pkt));
1811 skb_reset_mac_header(skb);
1812 skb->protocol = htons(0xffff);
1813 skb->dev = adap->port[0];
1814 netif_receive_skb(skb);
1818 static void do_gro(struct sge_eth_rxq *rxq, const struct pkt_gl *gl,
1819 const struct cpl_rx_pkt *pkt)
1821 struct adapter *adapter = rxq->rspq.adap;
1822 struct sge *s = &adapter->sge;
1824 struct sk_buff *skb;
1826 skb = napi_get_frags(&rxq->rspq.napi);
1827 if (unlikely(!skb)) {
1829 rxq->stats.rx_drops++;
1833 copy_frags(skb, gl, s->pktshift);
1834 skb->len = gl->tot_len - s->pktshift;
1835 skb->data_len = skb->len;
1836 skb->truesize += skb->data_len;
1837 skb->ip_summed = CHECKSUM_UNNECESSARY;
1838 skb_record_rx_queue(skb, rxq->rspq.idx);
1839 skb_mark_napi_id(skb, &rxq->rspq.napi);
1840 if (rxq->rspq.netdev->features & NETIF_F_RXHASH)
1841 skb_set_hash(skb, (__force u32)pkt->rsshdr.hash_val,
1844 if (unlikely(pkt->vlan_ex)) {
1845 __vlan_hwaccel_put_tag(skb, htons(ETH_P_8021Q), ntohs(pkt->vlan));
1846 rxq->stats.vlan_ex++;
1848 ret = napi_gro_frags(&rxq->rspq.napi);
1849 if (ret == GRO_HELD)
1850 rxq->stats.lro_pkts++;
1851 else if (ret == GRO_MERGED || ret == GRO_MERGED_FREE)
1852 rxq->stats.lro_merged++;
1854 rxq->stats.rx_cso++;
1858 * t4_ethrx_handler - process an ingress ethernet packet
1859 * @q: the response queue that received the packet
1860 * @rsp: the response queue descriptor holding the RX_PKT message
1861 * @si: the gather list of packet fragments
1863 * Process an ingress ethernet packet and deliver it to the stack.
1865 int t4_ethrx_handler(struct sge_rspq *q, const __be64 *rsp,
1866 const struct pkt_gl *si)
1869 struct sk_buff *skb;
1870 const struct cpl_rx_pkt *pkt;
1871 struct sge_eth_rxq *rxq = container_of(q, struct sge_eth_rxq, rspq);
1872 struct sge *s = &q->adap->sge;
1873 int cpl_trace_pkt = is_t4(q->adap->params.chip) ?
1874 CPL_TRACE_PKT : CPL_TRACE_PKT_T5;
1875 #ifdef CONFIG_CHELSIO_T4_FCOE
1876 struct port_info *pi;
1879 if (unlikely(*(u8 *)rsp == cpl_trace_pkt))
1880 return handle_trace_pkt(q->adap, si);
1882 pkt = (const struct cpl_rx_pkt *)rsp;
1883 csum_ok = pkt->csum_calc && !pkt->err_vec &&
1884 (q->netdev->features & NETIF_F_RXCSUM);
1885 if ((pkt->l2info & htonl(RXF_TCP_F)) &&
1886 !(cxgb_poll_busy_polling(q)) &&
1887 (q->netdev->features & NETIF_F_GRO) && csum_ok && !pkt->ip_frag) {
1888 do_gro(rxq, si, pkt);
1892 skb = cxgb4_pktgl_to_skb(si, RX_PKT_SKB_LEN, RX_PULL_LEN);
1893 if (unlikely(!skb)) {
1895 rxq->stats.rx_drops++;
1899 __skb_pull(skb, s->pktshift); /* remove ethernet header padding */
1900 skb->protocol = eth_type_trans(skb, q->netdev);
1901 skb_record_rx_queue(skb, q->idx);
1902 if (skb->dev->features & NETIF_F_RXHASH)
1903 skb_set_hash(skb, (__force u32)pkt->rsshdr.hash_val,
1908 if (csum_ok && (pkt->l2info & htonl(RXF_UDP_F | RXF_TCP_F))) {
1909 if (!pkt->ip_frag) {
1910 skb->ip_summed = CHECKSUM_UNNECESSARY;
1911 rxq->stats.rx_cso++;
1912 } else if (pkt->l2info & htonl(RXF_IP_F)) {
1913 __sum16 c = (__force __sum16)pkt->csum;
1914 skb->csum = csum_unfold(c);
1915 skb->ip_summed = CHECKSUM_COMPLETE;
1916 rxq->stats.rx_cso++;
1919 skb_checksum_none_assert(skb);
1920 #ifdef CONFIG_CHELSIO_T4_FCOE
1921 #define CPL_RX_PKT_FLAGS (RXF_PSH_F | RXF_SYN_F | RXF_UDP_F | \
1922 RXF_TCP_F | RXF_IP_F | RXF_IP6_F | RXF_LRO_F)
1924 pi = netdev_priv(skb->dev);
1925 if (!(pkt->l2info & cpu_to_be32(CPL_RX_PKT_FLAGS))) {
1926 if ((pkt->l2info & cpu_to_be32(RXF_FCOE_F)) &&
1927 (pi->fcoe.flags & CXGB_FCOE_ENABLED)) {
1928 if (!(pkt->err_vec & cpu_to_be16(RXERR_CSUM_F)))
1929 skb->ip_summed = CHECKSUM_UNNECESSARY;
1933 #undef CPL_RX_PKT_FLAGS
1934 #endif /* CONFIG_CHELSIO_T4_FCOE */
1937 if (unlikely(pkt->vlan_ex)) {
1938 __vlan_hwaccel_put_tag(skb, htons(ETH_P_8021Q), ntohs(pkt->vlan));
1939 rxq->stats.vlan_ex++;
1941 skb_mark_napi_id(skb, &q->napi);
1942 netif_receive_skb(skb);
1947 * restore_rx_bufs - put back a packet's Rx buffers
1948 * @si: the packet gather list
1949 * @q: the SGE free list
1950 * @frags: number of FL buffers to restore
1952 * Puts back on an FL the Rx buffers associated with @si. The buffers
1953 * have already been unmapped and are left unmapped, we mark them so to
1954 * prevent further unmapping attempts.
1956 * This function undoes a series of @unmap_rx_buf calls when we find out
1957 * that the current packet can't be processed right away afterall and we
1958 * need to come back to it later. This is a very rare event and there's
1959 * no effort to make this particularly efficient.
1961 static void restore_rx_bufs(const struct pkt_gl *si, struct sge_fl *q,
1964 struct rx_sw_desc *d;
1968 q->cidx = q->size - 1;
1971 d = &q->sdesc[q->cidx];
1972 d->page = si->frags[frags].page;
1973 d->dma_addr |= RX_UNMAPPED_BUF;
1979 * is_new_response - check if a response is newly written
1980 * @r: the response descriptor
1981 * @q: the response queue
1983 * Returns true if a response descriptor contains a yet unprocessed
1986 static inline bool is_new_response(const struct rsp_ctrl *r,
1987 const struct sge_rspq *q)
1989 return (r->type_gen >> RSPD_GEN_S) == q->gen;
1993 * rspq_next - advance to the next entry in a response queue
1996 * Updates the state of a response queue to advance it to the next entry.
1998 static inline void rspq_next(struct sge_rspq *q)
2000 q->cur_desc = (void *)q->cur_desc + q->iqe_len;
2001 if (unlikely(++q->cidx == q->size)) {
2004 q->cur_desc = q->desc;
2009 * process_responses - process responses from an SGE response queue
2010 * @q: the ingress queue to process
2011 * @budget: how many responses can be processed in this round
2013 * Process responses from an SGE response queue up to the supplied budget.
2014 * Responses include received packets as well as control messages from FW
2017 * Additionally choose the interrupt holdoff time for the next interrupt
2018 * on this queue. If the system is under memory shortage use a fairly
2019 * long delay to help recovery.
2021 static int process_responses(struct sge_rspq *q, int budget)
2024 int budget_left = budget;
2025 const struct rsp_ctrl *rc;
2026 struct sge_eth_rxq *rxq = container_of(q, struct sge_eth_rxq, rspq);
2027 struct adapter *adapter = q->adap;
2028 struct sge *s = &adapter->sge;
2030 while (likely(budget_left)) {
2031 rc = (void *)q->cur_desc + (q->iqe_len - sizeof(*rc));
2032 if (!is_new_response(rc, q))
2036 rsp_type = RSPD_TYPE_G(rc->type_gen);
2037 if (likely(rsp_type == RSPD_TYPE_FLBUF_X)) {
2038 struct page_frag *fp;
2040 const struct rx_sw_desc *rsd;
2041 u32 len = ntohl(rc->pldbuflen_qid), bufsz, frags;
2043 if (len & RSPD_NEWBUF_F) {
2044 if (likely(q->offset > 0)) {
2045 free_rx_bufs(q->adap, &rxq->fl, 1);
2048 len = RSPD_LEN_G(len);
2052 /* gather packet fragments */
2053 for (frags = 0, fp = si.frags; ; frags++, fp++) {
2054 rsd = &rxq->fl.sdesc[rxq->fl.cidx];
2055 bufsz = get_buf_size(adapter, rsd);
2056 fp->page = rsd->page;
2057 fp->offset = q->offset;
2058 fp->size = min(bufsz, len);
2062 unmap_rx_buf(q->adap, &rxq->fl);
2066 * Last buffer remains mapped so explicitly make it
2067 * coherent for CPU access.
2069 dma_sync_single_for_cpu(q->adap->pdev_dev,
2071 fp->size, DMA_FROM_DEVICE);
2073 si.va = page_address(si.frags[0].page) +
2077 si.nfrags = frags + 1;
2078 ret = q->handler(q, q->cur_desc, &si);
2079 if (likely(ret == 0))
2080 q->offset += ALIGN(fp->size, s->fl_align);
2082 restore_rx_bufs(&si, &rxq->fl, frags);
2083 } else if (likely(rsp_type == RSPD_TYPE_CPL_X)) {
2084 ret = q->handler(q, q->cur_desc, NULL);
2086 ret = q->handler(q, (const __be64 *)rc, CXGB4_MSG_AN);
2089 if (unlikely(ret)) {
2090 /* couldn't process descriptor, back off for recovery */
2091 q->next_intr_params = QINTR_TIMER_IDX_V(NOMEM_TMR_IDX);
2099 if (q->offset >= 0 && rxq->fl.size - rxq->fl.avail >= 16)
2100 __refill_fl(q->adap, &rxq->fl);
2101 return budget - budget_left;
2104 #ifdef CONFIG_NET_RX_BUSY_POLL
2105 int cxgb_busy_poll(struct napi_struct *napi)
2107 struct sge_rspq *q = container_of(napi, struct sge_rspq, napi);
2108 unsigned int params, work_done;
2111 if (!cxgb_poll_lock_poll(q))
2112 return LL_FLUSH_BUSY;
2114 work_done = process_responses(q, 4);
2115 params = QINTR_TIMER_IDX_V(TIMERREG_COUNTER0_X) | QINTR_CNT_EN_V(1);
2116 q->next_intr_params = params;
2117 val = CIDXINC_V(work_done) | SEINTARM_V(params);
2119 /* If we don't have access to the new User GTS (T5+), use the old
2120 * doorbell mechanism; otherwise use the new BAR2 mechanism.
2122 if (unlikely(!q->bar2_addr))
2123 t4_write_reg(q->adap, MYPF_REG(SGE_PF_GTS_A),
2124 val | INGRESSQID_V((u32)q->cntxt_id));
2126 writel(val | INGRESSQID_V(q->bar2_qid),
2127 q->bar2_addr + SGE_UDB_GTS);
2131 cxgb_poll_unlock_poll(q);
2134 #endif /* CONFIG_NET_RX_BUSY_POLL */
2137 * napi_rx_handler - the NAPI handler for Rx processing
2138 * @napi: the napi instance
2139 * @budget: how many packets we can process in this round
2141 * Handler for new data events when using NAPI. This does not need any
2142 * locking or protection from interrupts as data interrupts are off at
2143 * this point and other adapter interrupts do not interfere (the latter
2144 * in not a concern at all with MSI-X as non-data interrupts then have
2145 * a separate handler).
2147 static int napi_rx_handler(struct napi_struct *napi, int budget)
2149 unsigned int params;
2150 struct sge_rspq *q = container_of(napi, struct sge_rspq, napi);
2154 if (!cxgb_poll_lock_napi(q))
2157 work_done = process_responses(q, budget);
2158 if (likely(work_done < budget)) {
2161 napi_complete(napi);
2162 timer_index = QINTR_TIMER_IDX_G(q->next_intr_params);
2164 if (q->adaptive_rx) {
2165 if (work_done > max(timer_pkt_quota[timer_index],
2167 timer_index = (timer_index + 1);
2169 timer_index = timer_index - 1;
2171 timer_index = clamp(timer_index, 0, SGE_TIMERREGS - 1);
2172 q->next_intr_params =
2173 QINTR_TIMER_IDX_V(timer_index) |
2175 params = q->next_intr_params;
2177 params = q->next_intr_params;
2178 q->next_intr_params = q->intr_params;
2181 params = QINTR_TIMER_IDX_V(7);
2183 val = CIDXINC_V(work_done) | SEINTARM_V(params);
2185 /* If we don't have access to the new User GTS (T5+), use the old
2186 * doorbell mechanism; otherwise use the new BAR2 mechanism.
2188 if (unlikely(q->bar2_addr == NULL)) {
2189 t4_write_reg(q->adap, MYPF_REG(SGE_PF_GTS_A),
2190 val | INGRESSQID_V((u32)q->cntxt_id));
2192 writel(val | INGRESSQID_V(q->bar2_qid),
2193 q->bar2_addr + SGE_UDB_GTS);
2196 cxgb_poll_unlock_napi(q);
2201 * The MSI-X interrupt handler for an SGE response queue.
2203 irqreturn_t t4_sge_intr_msix(int irq, void *cookie)
2205 struct sge_rspq *q = cookie;
2207 napi_schedule(&q->napi);
2212 * Process the indirect interrupt entries in the interrupt queue and kick off
2213 * NAPI for each queue that has generated an entry.
2215 static unsigned int process_intrq(struct adapter *adap)
2217 unsigned int credits;
2218 const struct rsp_ctrl *rc;
2219 struct sge_rspq *q = &adap->sge.intrq;
2222 spin_lock(&adap->sge.intrq_lock);
2223 for (credits = 0; ; credits++) {
2224 rc = (void *)q->cur_desc + (q->iqe_len - sizeof(*rc));
2225 if (!is_new_response(rc, q))
2229 if (RSPD_TYPE_G(rc->type_gen) == RSPD_TYPE_INTR_X) {
2230 unsigned int qid = ntohl(rc->pldbuflen_qid);
2232 qid -= adap->sge.ingr_start;
2233 napi_schedule(&adap->sge.ingr_map[qid]->napi);
2239 val = CIDXINC_V(credits) | SEINTARM_V(q->intr_params);
2241 /* If we don't have access to the new User GTS (T5+), use the old
2242 * doorbell mechanism; otherwise use the new BAR2 mechanism.
2244 if (unlikely(q->bar2_addr == NULL)) {
2245 t4_write_reg(adap, MYPF_REG(SGE_PF_GTS_A),
2246 val | INGRESSQID_V(q->cntxt_id));
2248 writel(val | INGRESSQID_V(q->bar2_qid),
2249 q->bar2_addr + SGE_UDB_GTS);
2252 spin_unlock(&adap->sge.intrq_lock);
2257 * The MSI interrupt handler, which handles data events from SGE response queues
2258 * as well as error and other async events as they all use the same MSI vector.
2260 static irqreturn_t t4_intr_msi(int irq, void *cookie)
2262 struct adapter *adap = cookie;
2264 if (adap->flags & MASTER_PF)
2265 t4_slow_intr_handler(adap);
2266 process_intrq(adap);
2271 * Interrupt handler for legacy INTx interrupts.
2272 * Handles data events from SGE response queues as well as error and other
2273 * async events as they all use the same interrupt line.
2275 static irqreturn_t t4_intr_intx(int irq, void *cookie)
2277 struct adapter *adap = cookie;
2279 t4_write_reg(adap, MYPF_REG(PCIE_PF_CLI_A), 0);
2280 if (((adap->flags & MASTER_PF) && t4_slow_intr_handler(adap)) |
2281 process_intrq(adap))
2283 return IRQ_NONE; /* probably shared interrupt */
2287 * t4_intr_handler - select the top-level interrupt handler
2288 * @adap: the adapter
2290 * Selects the top-level interrupt handler based on the type of interrupts
2291 * (MSI-X, MSI, or INTx).
2293 irq_handler_t t4_intr_handler(struct adapter *adap)
2295 if (adap->flags & USING_MSIX)
2296 return t4_sge_intr_msix;
2297 if (adap->flags & USING_MSI)
2299 return t4_intr_intx;
2302 static void sge_rx_timer_cb(unsigned long data)
2306 struct adapter *adap = (struct adapter *)data;
2307 struct sge *s = &adap->sge;
2309 for (i = 0; i < BITS_TO_LONGS(s->egr_sz); i++)
2310 for (m = s->starving_fl[i]; m; m &= m - 1) {
2311 struct sge_eth_rxq *rxq;
2312 unsigned int id = __ffs(m) + i * BITS_PER_LONG;
2313 struct sge_fl *fl = s->egr_map[id];
2315 clear_bit(id, s->starving_fl);
2316 smp_mb__after_atomic();
2318 if (fl_starving(adap, fl)) {
2319 rxq = container_of(fl, struct sge_eth_rxq, fl);
2320 if (napi_reschedule(&rxq->rspq.napi))
2323 set_bit(id, s->starving_fl);
2326 /* The remainder of the SGE RX Timer Callback routine is dedicated to
2327 * global Master PF activities like checking for chip ingress stalls,
2330 if (!(adap->flags & MASTER_PF))
2333 t4_idma_monitor(adap, &s->idma_monitor, HZ, RX_QCHECK_PERIOD);
2336 mod_timer(&s->rx_timer, jiffies + RX_QCHECK_PERIOD);
2339 static void sge_tx_timer_cb(unsigned long data)
2342 unsigned int i, budget;
2343 struct adapter *adap = (struct adapter *)data;
2344 struct sge *s = &adap->sge;
2346 for (i = 0; i < BITS_TO_LONGS(s->egr_sz); i++)
2347 for (m = s->txq_maperr[i]; m; m &= m - 1) {
2348 unsigned long id = __ffs(m) + i * BITS_PER_LONG;
2349 struct sge_ofld_txq *txq = s->egr_map[id];
2351 clear_bit(id, s->txq_maperr);
2352 tasklet_schedule(&txq->qresume_tsk);
2355 budget = MAX_TIMER_TX_RECLAIM;
2356 i = s->ethtxq_rover;
2358 struct sge_eth_txq *q = &s->ethtxq[i];
2361 time_after_eq(jiffies, q->txq->trans_start + HZ / 100) &&
2362 __netif_tx_trylock(q->txq)) {
2363 int avail = reclaimable(&q->q);
2369 free_tx_desc(adap, &q->q, avail, true);
2370 q->q.in_use -= avail;
2373 __netif_tx_unlock(q->txq);
2376 if (++i >= s->ethqsets)
2378 } while (budget && i != s->ethtxq_rover);
2379 s->ethtxq_rover = i;
2380 mod_timer(&s->tx_timer, jiffies + (budget ? TX_QCHECK_PERIOD : 2));
2384 * bar2_address - return the BAR2 address for an SGE Queue's Registers
2385 * @adapter: the adapter
2386 * @qid: the SGE Queue ID
2387 * @qtype: the SGE Queue Type (Egress or Ingress)
2388 * @pbar2_qid: BAR2 Queue ID or 0 for Queue ID inferred SGE Queues
2390 * Returns the BAR2 address for the SGE Queue Registers associated with
2391 * @qid. If BAR2 SGE Registers aren't available, returns NULL. Also
2392 * returns the BAR2 Queue ID to be used with writes to the BAR2 SGE
2393 * Queue Registers. If the BAR2 Queue ID is 0, then "Inferred Queue ID"
2394 * Registers are supported (e.g. the Write Combining Doorbell Buffer).
2396 static void __iomem *bar2_address(struct adapter *adapter,
2398 enum t4_bar2_qtype qtype,
2399 unsigned int *pbar2_qid)
2404 ret = t4_bar2_sge_qregs(adapter, qid, qtype,
2405 &bar2_qoffset, pbar2_qid);
2409 return adapter->bar2 + bar2_qoffset;
2412 /* @intr_idx: MSI/MSI-X vector if >=0, -(absolute qid + 1) if < 0
2413 * @cong: < 0 -> no congestion feedback, >= 0 -> congestion channel map
2415 int t4_sge_alloc_rxq(struct adapter *adap, struct sge_rspq *iq, bool fwevtq,
2416 struct net_device *dev, int intr_idx,
2417 struct sge_fl *fl, rspq_handler_t hnd, int cong)
2421 struct sge *s = &adap->sge;
2422 struct port_info *pi = netdev_priv(dev);
2424 /* Size needs to be multiple of 16, including status entry. */
2425 iq->size = roundup(iq->size, 16);
2427 iq->desc = alloc_ring(adap->pdev_dev, iq->size, iq->iqe_len, 0,
2428 &iq->phys_addr, NULL, 0, NUMA_NO_NODE);
2432 memset(&c, 0, sizeof(c));
2433 c.op_to_vfn = htonl(FW_CMD_OP_V(FW_IQ_CMD) | FW_CMD_REQUEST_F |
2434 FW_CMD_WRITE_F | FW_CMD_EXEC_F |
2435 FW_IQ_CMD_PFN_V(adap->pf) | FW_IQ_CMD_VFN_V(0));
2436 c.alloc_to_len16 = htonl(FW_IQ_CMD_ALLOC_F | FW_IQ_CMD_IQSTART_F |
2438 c.type_to_iqandstindex = htonl(FW_IQ_CMD_TYPE_V(FW_IQ_TYPE_FL_INT_CAP) |
2439 FW_IQ_CMD_IQASYNCH_V(fwevtq) | FW_IQ_CMD_VIID_V(pi->viid) |
2440 FW_IQ_CMD_IQANDST_V(intr_idx < 0) |
2441 FW_IQ_CMD_IQANUD_V(UPDATEDELIVERY_INTERRUPT_X) |
2442 FW_IQ_CMD_IQANDSTINDEX_V(intr_idx >= 0 ? intr_idx :
2444 c.iqdroprss_to_iqesize = htons(FW_IQ_CMD_IQPCIECH_V(pi->tx_chan) |
2445 FW_IQ_CMD_IQGTSMODE_F |
2446 FW_IQ_CMD_IQINTCNTTHRESH_V(iq->pktcnt_idx) |
2447 FW_IQ_CMD_IQESIZE_V(ilog2(iq->iqe_len) - 4));
2448 c.iqsize = htons(iq->size);
2449 c.iqaddr = cpu_to_be64(iq->phys_addr);
2451 c.iqns_to_fl0congen = htonl(FW_IQ_CMD_IQFLINTCONGEN_F);
2454 enum chip_type chip = CHELSIO_CHIP_VERSION(adap->params.chip);
2456 /* Allocate the ring for the hardware free list (with space
2457 * for its status page) along with the associated software
2458 * descriptor ring. The free list size needs to be a multiple
2459 * of the Egress Queue Unit and at least 2 Egress Units larger
2460 * than the SGE's Egress Congrestion Threshold
2461 * (fl_starve_thres - 1).
2463 if (fl->size < s->fl_starve_thres - 1 + 2 * 8)
2464 fl->size = s->fl_starve_thres - 1 + 2 * 8;
2465 fl->size = roundup(fl->size, 8);
2466 fl->desc = alloc_ring(adap->pdev_dev, fl->size, sizeof(__be64),
2467 sizeof(struct rx_sw_desc), &fl->addr,
2468 &fl->sdesc, s->stat_len, NUMA_NO_NODE);
2472 flsz = fl->size / 8 + s->stat_len / sizeof(struct tx_desc);
2473 c.iqns_to_fl0congen |= htonl(FW_IQ_CMD_FL0PACKEN_F |
2474 FW_IQ_CMD_FL0FETCHRO_F |
2475 FW_IQ_CMD_FL0DATARO_F |
2476 FW_IQ_CMD_FL0PADEN_F);
2478 c.iqns_to_fl0congen |=
2479 htonl(FW_IQ_CMD_FL0CNGCHMAP_V(cong) |
2480 FW_IQ_CMD_FL0CONGCIF_F |
2481 FW_IQ_CMD_FL0CONGEN_F);
2482 c.fl0dcaen_to_fl0cidxfthresh =
2483 htons(FW_IQ_CMD_FL0FBMIN_V(FETCHBURSTMIN_64B_X) |
2484 FW_IQ_CMD_FL0FBMAX_V((chip <= CHELSIO_T5) ?
2485 FETCHBURSTMAX_512B_X :
2486 FETCHBURSTMAX_256B_X));
2487 c.fl0size = htons(flsz);
2488 c.fl0addr = cpu_to_be64(fl->addr);
2491 ret = t4_wr_mbox(adap, adap->mbox, &c, sizeof(c), &c);
2495 netif_napi_add(dev, &iq->napi, napi_rx_handler, 64);
2496 napi_hash_add(&iq->napi);
2497 iq->cur_desc = iq->desc;
2500 iq->next_intr_params = iq->intr_params;
2501 iq->cntxt_id = ntohs(c.iqid);
2502 iq->abs_id = ntohs(c.physiqid);
2503 iq->bar2_addr = bar2_address(adap,
2505 T4_BAR2_QTYPE_INGRESS,
2507 iq->size--; /* subtract status entry */
2511 /* set offset to -1 to distinguish ingress queues without FL */
2512 iq->offset = fl ? 0 : -1;
2514 adap->sge.ingr_map[iq->cntxt_id - adap->sge.ingr_start] = iq;
2517 fl->cntxt_id = ntohs(c.fl0id);
2518 fl->avail = fl->pend_cred = 0;
2519 fl->pidx = fl->cidx = 0;
2520 fl->alloc_failed = fl->large_alloc_failed = fl->starving = 0;
2521 adap->sge.egr_map[fl->cntxt_id - adap->sge.egr_start] = fl;
2523 /* Note, we must initialize the BAR2 Free List User Doorbell
2524 * information before refilling the Free List!
2526 fl->bar2_addr = bar2_address(adap,
2528 T4_BAR2_QTYPE_EGRESS,
2530 refill_fl(adap, fl, fl_cap(fl), GFP_KERNEL);
2533 /* For T5 and later we attempt to set up the Congestion Manager values
2534 * of the new RX Ethernet Queue. This should really be handled by
2535 * firmware because it's more complex than any host driver wants to
2536 * get involved with and it's different per chip and this is almost
2537 * certainly wrong. Firmware would be wrong as well, but it would be
2538 * a lot easier to fix in one place ... For now we do something very
2539 * simple (and hopefully less wrong).
2541 if (!is_t4(adap->params.chip) && cong >= 0) {
2545 param = (FW_PARAMS_MNEM_V(FW_PARAMS_MNEM_DMAQ) |
2546 FW_PARAMS_PARAM_X_V(FW_PARAMS_PARAM_DMAQ_CONM_CTXT) |
2547 FW_PARAMS_PARAM_YZ_V(iq->cntxt_id));
2549 val = CONMCTXT_CNGTPMODE_V(CONMCTXT_CNGTPMODE_QUEUE_X);
2552 CONMCTXT_CNGTPMODE_V(CONMCTXT_CNGTPMODE_CHANNEL_X);
2553 for (i = 0; i < 4; i++) {
2554 if (cong & (1 << i))
2556 CONMCTXT_CNGCHMAP_V(1 << (i << 2));
2559 ret = t4_set_params(adap, adap->mbox, adap->pf, 0, 1,
2562 dev_warn(adap->pdev_dev, "Failed to set Congestion"
2563 " Manager Context for Ingress Queue %d: %d\n",
2564 iq->cntxt_id, -ret);
2573 dma_free_coherent(adap->pdev_dev, iq->size * iq->iqe_len,
2574 iq->desc, iq->phys_addr);
2577 if (fl && fl->desc) {
2580 dma_free_coherent(adap->pdev_dev, flsz * sizeof(struct tx_desc),
2581 fl->desc, fl->addr);
2587 static void init_txq(struct adapter *adap, struct sge_txq *q, unsigned int id)
2590 q->bar2_addr = bar2_address(adap,
2592 T4_BAR2_QTYPE_EGRESS,
2595 q->cidx = q->pidx = 0;
2596 q->stops = q->restarts = 0;
2597 q->stat = (void *)&q->desc[q->size];
2598 spin_lock_init(&q->db_lock);
2599 adap->sge.egr_map[id - adap->sge.egr_start] = q;
2602 int t4_sge_alloc_eth_txq(struct adapter *adap, struct sge_eth_txq *txq,
2603 struct net_device *dev, struct netdev_queue *netdevq,
2607 struct fw_eq_eth_cmd c;
2608 struct sge *s = &adap->sge;
2609 struct port_info *pi = netdev_priv(dev);
2611 /* Add status entries */
2612 nentries = txq->q.size + s->stat_len / sizeof(struct tx_desc);
2614 txq->q.desc = alloc_ring(adap->pdev_dev, txq->q.size,
2615 sizeof(struct tx_desc), sizeof(struct tx_sw_desc),
2616 &txq->q.phys_addr, &txq->q.sdesc, s->stat_len,
2617 netdev_queue_numa_node_read(netdevq));
2621 memset(&c, 0, sizeof(c));
2622 c.op_to_vfn = htonl(FW_CMD_OP_V(FW_EQ_ETH_CMD) | FW_CMD_REQUEST_F |
2623 FW_CMD_WRITE_F | FW_CMD_EXEC_F |
2624 FW_EQ_ETH_CMD_PFN_V(adap->pf) |
2625 FW_EQ_ETH_CMD_VFN_V(0));
2626 c.alloc_to_len16 = htonl(FW_EQ_ETH_CMD_ALLOC_F |
2627 FW_EQ_ETH_CMD_EQSTART_F | FW_LEN16(c));
2628 c.viid_pkd = htonl(FW_EQ_ETH_CMD_AUTOEQUEQE_F |
2629 FW_EQ_ETH_CMD_VIID_V(pi->viid));
2630 c.fetchszm_to_iqid =
2631 htonl(FW_EQ_ETH_CMD_HOSTFCMODE_V(HOSTFCMODE_STATUS_PAGE_X) |
2632 FW_EQ_ETH_CMD_PCIECHN_V(pi->tx_chan) |
2633 FW_EQ_ETH_CMD_FETCHRO_F | FW_EQ_ETH_CMD_IQID_V(iqid));
2635 htonl(FW_EQ_ETH_CMD_FBMIN_V(FETCHBURSTMIN_64B_X) |
2636 FW_EQ_ETH_CMD_FBMAX_V(FETCHBURSTMAX_512B_X) |
2637 FW_EQ_ETH_CMD_CIDXFTHRESH_V(CIDXFLUSHTHRESH_32_X) |
2638 FW_EQ_ETH_CMD_EQSIZE_V(nentries));
2639 c.eqaddr = cpu_to_be64(txq->q.phys_addr);
2641 ret = t4_wr_mbox(adap, adap->mbox, &c, sizeof(c), &c);
2643 kfree(txq->q.sdesc);
2644 txq->q.sdesc = NULL;
2645 dma_free_coherent(adap->pdev_dev,
2646 nentries * sizeof(struct tx_desc),
2647 txq->q.desc, txq->q.phys_addr);
2652 init_txq(adap, &txq->q, FW_EQ_ETH_CMD_EQID_G(ntohl(c.eqid_pkd)));
2654 txq->tso = txq->tx_cso = txq->vlan_ins = 0;
2655 txq->mapping_err = 0;
2659 int t4_sge_alloc_ctrl_txq(struct adapter *adap, struct sge_ctrl_txq *txq,
2660 struct net_device *dev, unsigned int iqid,
2661 unsigned int cmplqid)
2664 struct fw_eq_ctrl_cmd c;
2665 struct sge *s = &adap->sge;
2666 struct port_info *pi = netdev_priv(dev);
2668 /* Add status entries */
2669 nentries = txq->q.size + s->stat_len / sizeof(struct tx_desc);
2671 txq->q.desc = alloc_ring(adap->pdev_dev, nentries,
2672 sizeof(struct tx_desc), 0, &txq->q.phys_addr,
2673 NULL, 0, dev_to_node(adap->pdev_dev));
2677 c.op_to_vfn = htonl(FW_CMD_OP_V(FW_EQ_CTRL_CMD) | FW_CMD_REQUEST_F |
2678 FW_CMD_WRITE_F | FW_CMD_EXEC_F |
2679 FW_EQ_CTRL_CMD_PFN_V(adap->pf) |
2680 FW_EQ_CTRL_CMD_VFN_V(0));
2681 c.alloc_to_len16 = htonl(FW_EQ_CTRL_CMD_ALLOC_F |
2682 FW_EQ_CTRL_CMD_EQSTART_F | FW_LEN16(c));
2683 c.cmpliqid_eqid = htonl(FW_EQ_CTRL_CMD_CMPLIQID_V(cmplqid));
2684 c.physeqid_pkd = htonl(0);
2685 c.fetchszm_to_iqid =
2686 htonl(FW_EQ_CTRL_CMD_HOSTFCMODE_V(HOSTFCMODE_STATUS_PAGE_X) |
2687 FW_EQ_CTRL_CMD_PCIECHN_V(pi->tx_chan) |
2688 FW_EQ_CTRL_CMD_FETCHRO_F | FW_EQ_CTRL_CMD_IQID_V(iqid));
2690 htonl(FW_EQ_CTRL_CMD_FBMIN_V(FETCHBURSTMIN_64B_X) |
2691 FW_EQ_CTRL_CMD_FBMAX_V(FETCHBURSTMAX_512B_X) |
2692 FW_EQ_CTRL_CMD_CIDXFTHRESH_V(CIDXFLUSHTHRESH_32_X) |
2693 FW_EQ_CTRL_CMD_EQSIZE_V(nentries));
2694 c.eqaddr = cpu_to_be64(txq->q.phys_addr);
2696 ret = t4_wr_mbox(adap, adap->mbox, &c, sizeof(c), &c);
2698 dma_free_coherent(adap->pdev_dev,
2699 nentries * sizeof(struct tx_desc),
2700 txq->q.desc, txq->q.phys_addr);
2705 init_txq(adap, &txq->q, FW_EQ_CTRL_CMD_EQID_G(ntohl(c.cmpliqid_eqid)));
2707 skb_queue_head_init(&txq->sendq);
2708 tasklet_init(&txq->qresume_tsk, restart_ctrlq, (unsigned long)txq);
2713 int t4_sge_alloc_ofld_txq(struct adapter *adap, struct sge_ofld_txq *txq,
2714 struct net_device *dev, unsigned int iqid)
2717 struct fw_eq_ofld_cmd c;
2718 struct sge *s = &adap->sge;
2719 struct port_info *pi = netdev_priv(dev);
2721 /* Add status entries */
2722 nentries = txq->q.size + s->stat_len / sizeof(struct tx_desc);
2724 txq->q.desc = alloc_ring(adap->pdev_dev, txq->q.size,
2725 sizeof(struct tx_desc), sizeof(struct tx_sw_desc),
2726 &txq->q.phys_addr, &txq->q.sdesc, s->stat_len,
2731 memset(&c, 0, sizeof(c));
2732 c.op_to_vfn = htonl(FW_CMD_OP_V(FW_EQ_OFLD_CMD) | FW_CMD_REQUEST_F |
2733 FW_CMD_WRITE_F | FW_CMD_EXEC_F |
2734 FW_EQ_OFLD_CMD_PFN_V(adap->pf) |
2735 FW_EQ_OFLD_CMD_VFN_V(0));
2736 c.alloc_to_len16 = htonl(FW_EQ_OFLD_CMD_ALLOC_F |
2737 FW_EQ_OFLD_CMD_EQSTART_F | FW_LEN16(c));
2738 c.fetchszm_to_iqid =
2739 htonl(FW_EQ_OFLD_CMD_HOSTFCMODE_V(HOSTFCMODE_STATUS_PAGE_X) |
2740 FW_EQ_OFLD_CMD_PCIECHN_V(pi->tx_chan) |
2741 FW_EQ_OFLD_CMD_FETCHRO_F | FW_EQ_OFLD_CMD_IQID_V(iqid));
2743 htonl(FW_EQ_OFLD_CMD_FBMIN_V(FETCHBURSTMIN_64B_X) |
2744 FW_EQ_OFLD_CMD_FBMAX_V(FETCHBURSTMAX_512B_X) |
2745 FW_EQ_OFLD_CMD_CIDXFTHRESH_V(CIDXFLUSHTHRESH_32_X) |
2746 FW_EQ_OFLD_CMD_EQSIZE_V(nentries));
2747 c.eqaddr = cpu_to_be64(txq->q.phys_addr);
2749 ret = t4_wr_mbox(adap, adap->mbox, &c, sizeof(c), &c);
2751 kfree(txq->q.sdesc);
2752 txq->q.sdesc = NULL;
2753 dma_free_coherent(adap->pdev_dev,
2754 nentries * sizeof(struct tx_desc),
2755 txq->q.desc, txq->q.phys_addr);
2760 init_txq(adap, &txq->q, FW_EQ_OFLD_CMD_EQID_G(ntohl(c.eqid_pkd)));
2762 skb_queue_head_init(&txq->sendq);
2763 tasklet_init(&txq->qresume_tsk, restart_ofldq, (unsigned long)txq);
2765 txq->mapping_err = 0;
2769 static void free_txq(struct adapter *adap, struct sge_txq *q)
2771 struct sge *s = &adap->sge;
2773 dma_free_coherent(adap->pdev_dev,
2774 q->size * sizeof(struct tx_desc) + s->stat_len,
2775 q->desc, q->phys_addr);
2781 static void free_rspq_fl(struct adapter *adap, struct sge_rspq *rq,
2784 struct sge *s = &adap->sge;
2785 unsigned int fl_id = fl ? fl->cntxt_id : 0xffff;
2787 adap->sge.ingr_map[rq->cntxt_id - adap->sge.ingr_start] = NULL;
2788 t4_iq_free(adap, adap->mbox, adap->pf, 0, FW_IQ_TYPE_FL_INT_CAP,
2789 rq->cntxt_id, fl_id, 0xffff);
2790 dma_free_coherent(adap->pdev_dev, (rq->size + 1) * rq->iqe_len,
2791 rq->desc, rq->phys_addr);
2792 napi_hash_del(&rq->napi);
2793 netif_napi_del(&rq->napi);
2795 rq->cntxt_id = rq->abs_id = 0;
2799 free_rx_bufs(adap, fl, fl->avail);
2800 dma_free_coherent(adap->pdev_dev, fl->size * 8 + s->stat_len,
2801 fl->desc, fl->addr);
2810 * t4_free_ofld_rxqs - free a block of consecutive Rx queues
2811 * @adap: the adapter
2812 * @n: number of queues
2813 * @q: pointer to first queue
2815 * Release the resources of a consecutive block of offload Rx queues.
2817 void t4_free_ofld_rxqs(struct adapter *adap, int n, struct sge_ofld_rxq *q)
2819 for ( ; n; n--, q++)
2821 free_rspq_fl(adap, &q->rspq,
2822 q->fl.size ? &q->fl : NULL);
2826 * t4_free_sge_resources - free SGE resources
2827 * @adap: the adapter
2829 * Frees resources used by the SGE queue sets.
2831 void t4_free_sge_resources(struct adapter *adap)
2834 struct sge_eth_rxq *eq = adap->sge.ethrxq;
2835 struct sge_eth_txq *etq = adap->sge.ethtxq;
2837 /* clean up Ethernet Tx/Rx queues */
2838 for (i = 0; i < adap->sge.ethqsets; i++, eq++, etq++) {
2840 free_rspq_fl(adap, &eq->rspq,
2841 eq->fl.size ? &eq->fl : NULL);
2843 t4_eth_eq_free(adap, adap->mbox, adap->pf, 0,
2845 free_tx_desc(adap, &etq->q, etq->q.in_use, true);
2846 kfree(etq->q.sdesc);
2847 free_txq(adap, &etq->q);
2851 /* clean up RDMA and iSCSI Rx queues */
2852 t4_free_ofld_rxqs(adap, adap->sge.ofldqsets, adap->sge.ofldrxq);
2853 t4_free_ofld_rxqs(adap, adap->sge.rdmaqs, adap->sge.rdmarxq);
2854 t4_free_ofld_rxqs(adap, adap->sge.rdmaciqs, adap->sge.rdmaciq);
2856 /* clean up offload Tx queues */
2857 for (i = 0; i < ARRAY_SIZE(adap->sge.ofldtxq); i++) {
2858 struct sge_ofld_txq *q = &adap->sge.ofldtxq[i];
2861 tasklet_kill(&q->qresume_tsk);
2862 t4_ofld_eq_free(adap, adap->mbox, adap->pf, 0,
2864 free_tx_desc(adap, &q->q, q->q.in_use, false);
2866 __skb_queue_purge(&q->sendq);
2867 free_txq(adap, &q->q);
2871 /* clean up control Tx queues */
2872 for (i = 0; i < ARRAY_SIZE(adap->sge.ctrlq); i++) {
2873 struct sge_ctrl_txq *cq = &adap->sge.ctrlq[i];
2876 tasklet_kill(&cq->qresume_tsk);
2877 t4_ctrl_eq_free(adap, adap->mbox, adap->pf, 0,
2879 __skb_queue_purge(&cq->sendq);
2880 free_txq(adap, &cq->q);
2884 if (adap->sge.fw_evtq.desc)
2885 free_rspq_fl(adap, &adap->sge.fw_evtq, NULL);
2887 if (adap->sge.intrq.desc)
2888 free_rspq_fl(adap, &adap->sge.intrq, NULL);
2890 /* clear the reverse egress queue map */
2891 memset(adap->sge.egr_map, 0,
2892 adap->sge.egr_sz * sizeof(*adap->sge.egr_map));
2895 void t4_sge_start(struct adapter *adap)
2897 adap->sge.ethtxq_rover = 0;
2898 mod_timer(&adap->sge.rx_timer, jiffies + RX_QCHECK_PERIOD);
2899 mod_timer(&adap->sge.tx_timer, jiffies + TX_QCHECK_PERIOD);
2903 * t4_sge_stop - disable SGE operation
2904 * @adap: the adapter
2906 * Stop tasklets and timers associated with the DMA engine. Note that
2907 * this is effective only if measures have been taken to disable any HW
2908 * events that may restart them.
2910 void t4_sge_stop(struct adapter *adap)
2913 struct sge *s = &adap->sge;
2915 if (in_interrupt()) /* actions below require waiting */
2918 if (s->rx_timer.function)
2919 del_timer_sync(&s->rx_timer);
2920 if (s->tx_timer.function)
2921 del_timer_sync(&s->tx_timer);
2923 for (i = 0; i < ARRAY_SIZE(s->ofldtxq); i++) {
2924 struct sge_ofld_txq *q = &s->ofldtxq[i];
2927 tasklet_kill(&q->qresume_tsk);
2929 for (i = 0; i < ARRAY_SIZE(s->ctrlq); i++) {
2930 struct sge_ctrl_txq *cq = &s->ctrlq[i];
2933 tasklet_kill(&cq->qresume_tsk);
2938 * t4_sge_init_soft - grab core SGE values needed by SGE code
2939 * @adap: the adapter
2941 * We need to grab the SGE operating parameters that we need to have
2942 * in order to do our job and make sure we can live with them.
2945 static int t4_sge_init_soft(struct adapter *adap)
2947 struct sge *s = &adap->sge;
2948 u32 fl_small_pg, fl_large_pg, fl_small_mtu, fl_large_mtu;
2949 u32 timer_value_0_and_1, timer_value_2_and_3, timer_value_4_and_5;
2950 u32 ingress_rx_threshold;
2953 * Verify that CPL messages are going to the Ingress Queue for
2954 * process_responses() and that only packet data is going to the
2957 if ((t4_read_reg(adap, SGE_CONTROL_A) & RXPKTCPLMODE_F) !=
2958 RXPKTCPLMODE_V(RXPKTCPLMODE_SPLIT_X)) {
2959 dev_err(adap->pdev_dev, "bad SGE CPL MODE\n");
2964 * Validate the Host Buffer Register Array indices that we want to
2967 * XXX Note that we should really read through the Host Buffer Size
2968 * XXX register array and find the indices of the Buffer Sizes which
2969 * XXX meet our needs!
2971 #define READ_FL_BUF(x) \
2972 t4_read_reg(adap, SGE_FL_BUFFER_SIZE0_A+(x)*sizeof(u32))
2974 fl_small_pg = READ_FL_BUF(RX_SMALL_PG_BUF);
2975 fl_large_pg = READ_FL_BUF(RX_LARGE_PG_BUF);
2976 fl_small_mtu = READ_FL_BUF(RX_SMALL_MTU_BUF);
2977 fl_large_mtu = READ_FL_BUF(RX_LARGE_MTU_BUF);
2979 /* We only bother using the Large Page logic if the Large Page Buffer
2980 * is larger than our Page Size Buffer.
2982 if (fl_large_pg <= fl_small_pg)
2987 /* The Page Size Buffer must be exactly equal to our Page Size and the
2988 * Large Page Size Buffer should be 0 (per above) or a power of 2.
2990 if (fl_small_pg != PAGE_SIZE ||
2991 (fl_large_pg & (fl_large_pg-1)) != 0) {
2992 dev_err(adap->pdev_dev, "bad SGE FL page buffer sizes [%d, %d]\n",
2993 fl_small_pg, fl_large_pg);
2997 s->fl_pg_order = ilog2(fl_large_pg) - PAGE_SHIFT;
2999 if (fl_small_mtu < FL_MTU_SMALL_BUFSIZE(adap) ||
3000 fl_large_mtu < FL_MTU_LARGE_BUFSIZE(adap)) {
3001 dev_err(adap->pdev_dev, "bad SGE FL MTU sizes [%d, %d]\n",
3002 fl_small_mtu, fl_large_mtu);
3007 * Retrieve our RX interrupt holdoff timer values and counter
3008 * threshold values from the SGE parameters.
3010 timer_value_0_and_1 = t4_read_reg(adap, SGE_TIMER_VALUE_0_AND_1_A);
3011 timer_value_2_and_3 = t4_read_reg(adap, SGE_TIMER_VALUE_2_AND_3_A);
3012 timer_value_4_and_5 = t4_read_reg(adap, SGE_TIMER_VALUE_4_AND_5_A);
3013 s->timer_val[0] = core_ticks_to_us(adap,
3014 TIMERVALUE0_G(timer_value_0_and_1));
3015 s->timer_val[1] = core_ticks_to_us(adap,
3016 TIMERVALUE1_G(timer_value_0_and_1));
3017 s->timer_val[2] = core_ticks_to_us(adap,
3018 TIMERVALUE2_G(timer_value_2_and_3));
3019 s->timer_val[3] = core_ticks_to_us(adap,
3020 TIMERVALUE3_G(timer_value_2_and_3));
3021 s->timer_val[4] = core_ticks_to_us(adap,
3022 TIMERVALUE4_G(timer_value_4_and_5));
3023 s->timer_val[5] = core_ticks_to_us(adap,
3024 TIMERVALUE5_G(timer_value_4_and_5));
3026 ingress_rx_threshold = t4_read_reg(adap, SGE_INGRESS_RX_THRESHOLD_A);
3027 s->counter_val[0] = THRESHOLD_0_G(ingress_rx_threshold);
3028 s->counter_val[1] = THRESHOLD_1_G(ingress_rx_threshold);
3029 s->counter_val[2] = THRESHOLD_2_G(ingress_rx_threshold);
3030 s->counter_val[3] = THRESHOLD_3_G(ingress_rx_threshold);
3036 * t4_sge_init - initialize SGE
3037 * @adap: the adapter
3039 * Perform low-level SGE code initialization needed every time after a
3042 int t4_sge_init(struct adapter *adap)
3044 struct sge *s = &adap->sge;
3045 u32 sge_control, sge_control2, sge_conm_ctrl;
3046 unsigned int ingpadboundary, ingpackboundary;
3047 int ret, egress_threshold;
3050 * Ingress Padding Boundary and Egress Status Page Size are set up by
3051 * t4_fixup_host_params().
3053 sge_control = t4_read_reg(adap, SGE_CONTROL_A);
3054 s->pktshift = PKTSHIFT_G(sge_control);
3055 s->stat_len = (sge_control & EGRSTATUSPAGESIZE_F) ? 128 : 64;
3057 /* T4 uses a single control field to specify both the PCIe Padding and
3058 * Packing Boundary. T5 introduced the ability to specify these
3059 * separately. The actual Ingress Packet Data alignment boundary
3060 * within Packed Buffer Mode is the maximum of these two
3061 * specifications. (Note that it makes no real practical sense to
3062 * have the Pading Boudary be larger than the Packing Boundary but you
3063 * could set the chip up that way and, in fact, legacy T4 code would
3064 * end doing this because it would initialize the Padding Boundary and
3065 * leave the Packing Boundary initialized to 0 (16 bytes).)
3067 ingpadboundary = 1 << (INGPADBOUNDARY_G(sge_control) +
3068 INGPADBOUNDARY_SHIFT_X);
3069 if (is_t4(adap->params.chip)) {
3070 s->fl_align = ingpadboundary;
3072 /* T5 has a different interpretation of one of the PCIe Packing
3075 sge_control2 = t4_read_reg(adap, SGE_CONTROL2_A);
3076 ingpackboundary = INGPACKBOUNDARY_G(sge_control2);
3077 if (ingpackboundary == INGPACKBOUNDARY_16B_X)
3078 ingpackboundary = 16;
3080 ingpackboundary = 1 << (ingpackboundary +
3081 INGPACKBOUNDARY_SHIFT_X);
3083 s->fl_align = max(ingpadboundary, ingpackboundary);
3086 ret = t4_sge_init_soft(adap);
3091 * A FL with <= fl_starve_thres buffers is starving and a periodic
3092 * timer will attempt to refill it. This needs to be larger than the
3093 * SGE's Egress Congestion Threshold. If it isn't, then we can get
3094 * stuck waiting for new packets while the SGE is waiting for us to
3095 * give it more Free List entries. (Note that the SGE's Egress
3096 * Congestion Threshold is in units of 2 Free List pointers.) For T4,
3097 * there was only a single field to control this. For T5 there's the
3098 * original field which now only applies to Unpacked Mode Free List
3099 * buffers and a new field which only applies to Packed Mode Free List
3102 sge_conm_ctrl = t4_read_reg(adap, SGE_CONM_CTRL_A);
3103 if (is_t4(adap->params.chip))
3104 egress_threshold = EGRTHRESHOLD_G(sge_conm_ctrl);
3106 egress_threshold = EGRTHRESHOLDPACKING_G(sge_conm_ctrl);
3107 s->fl_starve_thres = 2*egress_threshold + 1;
3109 t4_idma_monitor_init(adap, &s->idma_monitor);
3111 /* Set up timers used for recuring callbacks to process RX and TX
3112 * administrative tasks.
3114 setup_timer(&s->rx_timer, sge_rx_timer_cb, (unsigned long)adap);
3115 setup_timer(&s->tx_timer, sge_tx_timer_cb, (unsigned long)adap);
3117 spin_lock_init(&s->intrq_lock);