2 * This file is part of the Chelsio T4 Ethernet driver for Linux.
4 * Copyright (c) 2003-2014 Chelsio Communications, Inc. All rights reserved.
6 * This software is available to you under a choice of one of two
7 * licenses. You may choose to be licensed under the terms of the GNU
8 * General Public License (GPL) Version 2, available from the file
9 * COPYING in the main directory of this source tree, or the
10 * OpenIB.org BSD license below:
12 * Redistribution and use in source and binary forms, with or
13 * without modification, are permitted provided that the following
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17 * copyright notice, this list of conditions and the following
20 * - Redistributions in binary form must reproduce the above
21 * copyright notice, this list of conditions and the following
22 * disclaimer in the documentation and/or other materials
23 * provided with the distribution.
25 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
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31 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
38 #include <linux/types.h>
41 CPL_PASS_OPEN_REQ = 0x1,
42 CPL_PASS_ACCEPT_RPL = 0x2,
43 CPL_ACT_OPEN_REQ = 0x3,
44 CPL_SET_TCB_FIELD = 0x5,
46 CPL_CLOSE_CON_REQ = 0x8,
47 CPL_CLOSE_LISTSRV_REQ = 0x9,
50 CPL_RX_DATA_ACK = 0xD,
52 CPL_L2T_WRITE_REQ = 0x12,
53 CPL_TID_RELEASE = 0x1A,
55 CPL_CLOSE_LISTSRV_RPL = 0x20,
56 CPL_L2T_WRITE_RPL = 0x23,
57 CPL_PASS_OPEN_RPL = 0x24,
58 CPL_ACT_OPEN_RPL = 0x25,
59 CPL_PEER_CLOSE = 0x26,
60 CPL_ABORT_REQ_RSS = 0x2B,
61 CPL_ABORT_RPL_RSS = 0x2D,
63 CPL_CLOSE_CON_RPL = 0x32,
66 CPL_RDMA_CQE_READ_RSP = 0x36,
67 CPL_RDMA_CQE_ERR = 0x37,
69 CPL_SET_TCB_RPL = 0x3A,
71 CPL_RX_DDP_COMPLETE = 0x3F,
73 CPL_ACT_ESTABLISH = 0x40,
74 CPL_PASS_ESTABLISH = 0x41,
75 CPL_RX_DATA_DDP = 0x42,
76 CPL_PASS_ACCEPT_REQ = 0x44,
77 CPL_TRACE_PKT_T5 = 0x48,
78 CPL_RX_ISCSI_DDP = 0x49,
80 CPL_RDMA_READ_REQ = 0x60,
82 CPL_PASS_OPEN_REQ6 = 0x81,
83 CPL_ACT_OPEN_REQ6 = 0x83,
85 CPL_RDMA_TERMINATE = 0xA2,
86 CPL_RDMA_WRITE = 0xA4,
87 CPL_SGE_EGR_UPDATE = 0xA5,
90 CPL_ISCSI_DATA = 0xB2,
98 CPL_TX_PKT_LSO = 0xED,
106 CPL_ERR_TCAM_FULL = 3,
107 CPL_ERR_BAD_LENGTH = 15,
108 CPL_ERR_BAD_ROUTE = 18,
109 CPL_ERR_CONN_RESET = 20,
110 CPL_ERR_CONN_EXIST_SYNRECV = 21,
111 CPL_ERR_CONN_EXIST = 22,
112 CPL_ERR_ARP_MISS = 23,
113 CPL_ERR_BAD_SYN = 24,
114 CPL_ERR_CONN_TIMEDOUT = 30,
115 CPL_ERR_XMIT_TIMEDOUT = 31,
116 CPL_ERR_PERSIST_TIMEDOUT = 32,
117 CPL_ERR_FINWAIT2_TIMEDOUT = 33,
118 CPL_ERR_KEEPALIVE_TIMEDOUT = 34,
119 CPL_ERR_RTX_NEG_ADVICE = 35,
120 CPL_ERR_PERSIST_NEG_ADVICE = 36,
121 CPL_ERR_KEEPALV_NEG_ADVICE = 37,
122 CPL_ERR_ABORT_FAILED = 42,
123 CPL_ERR_IWARP_FLM = 50,
135 ULP_CRC_HEADER = 1 << 0,
136 ULP_CRC_DATA = 1 << 1
140 CPL_ABORT_SEND_RST = 0,
144 enum { /* TX_PKT_XT checksum types */
163 #define CPL_OPCODE(x) ((x) << 24)
164 #define G_CPL_OPCODE(x) (((x) >> 24) & 0xFF)
165 #define MK_OPCODE_TID(opcode, tid) (CPL_OPCODE(opcode) | (tid))
166 #define OPCODE_TID(cmd) ((cmd)->ot.opcode_tid)
167 #define GET_TID(cmd) (ntohl(OPCODE_TID(cmd)) & 0xFFFFFF)
169 /* partitioning of TID fields that also carry a queue id */
170 #define GET_TID_TID(x) ((x) & 0x3fff)
171 #define GET_TID_QID(x) (((x) >> 14) & 0x3ff)
172 #define TID_QID(x) ((x) << 14)
176 #if defined(__LITTLE_ENDIAN_BITFIELD)
195 struct work_request_hdr {
203 #define V_WR_OP(x) ((__u64)(x) << S_WR_OP)
205 #define WR_HDR struct work_request_hdr wr
207 /* option 0 fields */
209 #define TX_CHAN_V(x) ((x) << TX_CHAN_S)
212 #define ULP_MODE_V(x) ((x) << ULP_MODE_S)
214 #define RCV_BUFSIZ_S 12
215 #define RCV_BUFSIZ_M 0x3FFU
216 #define RCV_BUFSIZ_V(x) ((x) << RCV_BUFSIZ_S)
218 #define SMAC_SEL_S 28
219 #define SMAC_SEL_V(x) ((__u64)(x) << SMAC_SEL_S)
222 #define L2T_IDX_V(x) ((__u64)(x) << L2T_IDX_S)
224 #define WND_SCALE_S 50
225 #define WND_SCALE_V(x) ((__u64)(x) << WND_SCALE_S)
227 #define KEEP_ALIVE_S 54
228 #define KEEP_ALIVE_V(x) ((__u64)(x) << KEEP_ALIVE_S)
229 #define KEEP_ALIVE_F KEEP_ALIVE_V(1ULL)
232 #define MSS_IDX_M 0xF
233 #define MSS_IDX_V(x) ((__u64)(x) << MSS_IDX_S)
234 #define MSS_IDX_G(x) (((x) >> MSS_IDX_S) & MSS_IDX_M)
236 /* option 2 fields */
237 #define RSS_QUEUE_S 0
238 #define RSS_QUEUE_M 0x3FF
239 #define RSS_QUEUE_V(x) ((x) << RSS_QUEUE_S)
240 #define RSS_QUEUE_G(x) (((x) >> RSS_QUEUE_S) & RSS_QUEUE_M)
242 #define RSS_QUEUE_VALID_S 10
243 #define RSS_QUEUE_VALID_V(x) ((x) << RSS_QUEUE_VALID_S)
244 #define RSS_QUEUE_VALID_F RSS_QUEUE_VALID_V(1U)
246 #define RX_FC_DISABLE_S 20
247 #define RX_FC_DISABLE_V(x) ((x) << RX_FC_DISABLE_S)
248 #define RX_FC_DISABLE_F RX_FC_DISABLE_V(1U)
250 #define RX_FC_VALID_S 22
251 #define RX_FC_VALID_V(x) ((x) << RX_FC_VALID_S)
252 #define RX_FC_VALID_F RX_FC_VALID_V(1U)
254 #define RX_CHANNEL_S 26
255 #define RX_CHANNEL_V(x) ((x) << RX_CHANNEL_S)
257 #define WND_SCALE_EN_S 28
258 #define WND_SCALE_EN_V(x) ((x) << WND_SCALE_EN_S)
259 #define WND_SCALE_EN_F WND_SCALE_EN_V(1U)
261 #define T5_OPT_2_VALID_S 31
262 #define T5_OPT_2_VALID_V(x) ((x) << T5_OPT_2_VALID_S)
263 #define T5_OPT_2_VALID_F T5_OPT_2_VALID_V(1U)
265 struct cpl_pass_open_req {
273 #define NO_CONG(x) ((x) << 4)
274 #define DELACK(x) ((x) << 5)
275 #define DSCP(x) ((x) << 22)
276 #define TCAM_BYPASS(x) ((u64)(x) << 48)
277 #define NAGLE(x) ((u64)(x) << 49)
279 #define SYN_RSS_ENABLE (1 << 0)
280 #define SYN_RSS_QUEUE(x) ((x) << 2)
281 #define CONN_POLICY_ASK (1 << 22)
284 struct cpl_pass_open_req6 {
297 struct cpl_pass_open_rpl {
303 struct cpl_pass_accept_rpl {
307 #define RX_COALESCE_VALID(x) ((x) << 11)
308 #define RX_COALESCE(x) ((x) << 12)
309 #define PACE(x) ((x) << 16)
310 #define TX_QUEUE(x) ((x) << 23)
311 #define CCTRL_ECN(x) ((x) << 27)
312 #define TSTAMPS_EN(x) ((x) << 29)
313 #define SACK_EN(x) ((x) << 30)
317 struct cpl_t5_pass_accept_rpl {
326 struct cpl_act_open_req {
338 #define FILTER_TUPLE_S 24
339 #define FILTER_TUPLE_M 0xFFFFFFFFFF
340 #define FILTER_TUPLE_V(x) ((x) << FILTER_TUPLE_S)
341 #define FILTER_TUPLE_G(x) (((x) >> FILTER_TUPLE_S) & FILTER_TUPLE_M)
342 struct cpl_t5_act_open_req {
355 struct cpl_act_open_req6 {
369 struct cpl_t5_act_open_req6 {
384 struct cpl_act_open_rpl {
387 #define GET_AOPEN_STATUS(x) ((x) & 0xff)
388 #define GET_AOPEN_ATID(x) (((x) >> 8) & 0xffffff)
391 struct cpl_pass_establish {
395 #define PASS_OPEN_TID(x) ((x) << 0)
396 #define PASS_OPEN_TOS(x) ((x) << 24)
397 #define GET_PASS_OPEN_TID(x) (((x) >> 0) & 0xFFFFFF)
398 #define GET_POPEN_TID(x) ((x) & 0xffffff)
399 #define GET_POPEN_TOS(x) (((x) >> 24) & 0xff)
402 #define GET_TCPOPT_WSCALE_OK(x) (((x) >> 5) & 1)
403 #define GET_TCPOPT_SACK(x) (((x) >> 6) & 1)
404 #define GET_TCPOPT_TSTAMP(x) (((x) >> 7) & 1)
405 #define GET_TCPOPT_SND_WSCALE(x) (((x) >> 8) & 0xf)
406 #define GET_TCPOPT_MSS(x) (((x) >> 12) & 0xf)
411 struct cpl_act_establish {
425 #define QUEUENO(x) ((x) << 0)
426 #define REPLY_CHAN(x) ((x) << 14)
427 #define NO_REPLY(x) ((x) << 15)
431 struct cpl_set_tcb_field {
436 #define TCB_WORD(x) ((x) << 0)
437 #define TCB_COOKIE(x) ((x) << 5)
438 #define GET_TCB_COOKIE(x) (((x) >> 5) & 7)
443 struct cpl_set_tcb_rpl {
451 struct cpl_close_con_req {
457 struct cpl_close_con_rpl {
465 struct cpl_close_listsvr_req {
469 #define LISTSVR_IPV6(x) ((x) << 14)
473 struct cpl_close_listsvr_rpl {
479 struct cpl_abort_req_rss {
485 struct cpl_abort_req {
494 struct cpl_abort_rpl_rss {
500 struct cpl_abort_rpl {
509 struct cpl_peer_close {
514 struct cpl_tid_release {
520 struct cpl_tx_pkt_core {
522 #define TXPKT_VF(x) ((x) << 0)
523 #define TXPKT_PF(x) ((x) << 8)
524 #define TXPKT_VF_VLD (1 << 11)
525 #define TXPKT_OVLAN_IDX(x) ((x) << 12)
526 #define TXPKT_INTF(x) ((x) << 16)
527 #define TXPKT_INS_OVLAN (1 << 21)
528 #define TXPKT_OPCODE(x) ((x) << 24)
532 #define TXPKT_CSUM_END(x) ((x) << 12)
533 #define TXPKT_CSUM_START(x) ((x) << 20)
534 #define TXPKT_IPHDR_LEN(x) ((u64)(x) << 20)
535 #define TXPKT_CSUM_LOC(x) ((u64)(x) << 30)
536 #define TXPKT_ETHHDR_LEN(x) ((u64)(x) << 34)
537 #define TXPKT_CSUM_TYPE(x) ((u64)(x) << 40)
538 #define TXPKT_VLAN(x) ((u64)(x) << 44)
539 #define TXPKT_VLAN_VLD (1ULL << 60)
540 #define TXPKT_IPCSUM_DIS (1ULL << 62)
541 #define TXPKT_L4CSUM_DIS (1ULL << 63)
546 struct cpl_tx_pkt_core c;
549 #define cpl_tx_pkt_xt cpl_tx_pkt
551 struct cpl_tx_pkt_lso_core {
553 #define LSO_TCPHDR_LEN(x) ((x) << 0)
554 #define LSO_IPHDR_LEN(x) ((x) << 4)
555 #define LSO_ETHHDR_LEN(x) ((x) << 16)
556 #define LSO_IPV6(x) ((x) << 20)
557 #define LSO_LAST_SLICE (1 << 22)
558 #define LSO_FIRST_SLICE (1 << 23)
559 #define LSO_OPCODE(x) ((x) << 24)
560 #define LSO_T5_XFER_SIZE(x) ((x) << 0)
565 /* encapsulated CPL (TX_PKT, TX_PKT_XT or TX_DATA) follows here */
568 struct cpl_tx_pkt_lso {
570 struct cpl_tx_pkt_lso_core c;
571 /* encapsulated CPL (TX_PKT, TX_PKT_XT or TX_DATA) follows here */
574 struct cpl_iscsi_hdr {
577 #define ISCSI_PDU_LEN(x) ((x) & 0x7FFF)
578 #define ISCSI_DDP (1 << 15)
592 #if defined(__LITTLE_ENDIAN_BITFIELD)
608 struct cpl_rx_data_ack {
614 /* cpl_rx_data_ack.ack_seq fields */
615 #define RX_CREDITS_S 0
616 #define RX_CREDITS_V(x) ((x) << RX_CREDITS_S)
618 #define RX_FORCE_ACK_S 28
619 #define RX_FORCE_ACK_V(x) ((x) << RX_FORCE_ACK_S)
620 #define RX_FORCE_ACK_F RX_FORCE_ACK_V(1U)
623 struct rss_header rsshdr;
625 #if defined(__LITTLE_ENDIAN_BITFIELD)
642 #define RXF_UDP (1 << 22)
643 #define RXF_TCP (1 << 23)
644 #define RXF_IP (1 << 24)
645 #define RXF_IP6 (1 << 25)
650 /* rx_pkt.l2info fields */
651 #define S_RX_ETHHDR_LEN 0
652 #define M_RX_ETHHDR_LEN 0x1F
653 #define V_RX_ETHHDR_LEN(x) ((x) << S_RX_ETHHDR_LEN)
654 #define G_RX_ETHHDR_LEN(x) (((x) >> S_RX_ETHHDR_LEN) & M_RX_ETHHDR_LEN)
656 #define S_RX_T5_ETHHDR_LEN 0
657 #define M_RX_T5_ETHHDR_LEN 0x3F
658 #define V_RX_T5_ETHHDR_LEN(x) ((x) << S_RX_T5_ETHHDR_LEN)
659 #define G_RX_T5_ETHHDR_LEN(x) (((x) >> S_RX_T5_ETHHDR_LEN) & M_RX_T5_ETHHDR_LEN)
661 #define S_RX_MACIDX 8
662 #define M_RX_MACIDX 0x1FF
663 #define V_RX_MACIDX(x) ((x) << S_RX_MACIDX)
664 #define G_RX_MACIDX(x) (((x) >> S_RX_MACIDX) & M_RX_MACIDX)
667 #define V_RXF_SYN(x) ((x) << S_RXF_SYN)
668 #define F_RXF_SYN V_RXF_SYN(1U)
671 #define M_RX_CHAN 0xF
672 #define V_RX_CHAN(x) ((x) << S_RX_CHAN)
673 #define G_RX_CHAN(x) (((x) >> S_RX_CHAN) & M_RX_CHAN)
675 /* rx_pkt.hdr_len fields */
676 #define S_RX_TCPHDR_LEN 0
677 #define M_RX_TCPHDR_LEN 0x3F
678 #define V_RX_TCPHDR_LEN(x) ((x) << S_RX_TCPHDR_LEN)
679 #define G_RX_TCPHDR_LEN(x) (((x) >> S_RX_TCPHDR_LEN) & M_RX_TCPHDR_LEN)
681 #define S_RX_IPHDR_LEN 6
682 #define M_RX_IPHDR_LEN 0x3FF
683 #define V_RX_IPHDR_LEN(x) ((x) << S_RX_IPHDR_LEN)
684 #define G_RX_IPHDR_LEN(x) (((x) >> S_RX_IPHDR_LEN) & M_RX_IPHDR_LEN)
686 struct cpl_trace_pkt {
689 #if defined(__LITTLE_ENDIAN_BITFIELD)
707 struct cpl_t5_trace_pkt {
710 #if defined(__LITTLE_ENDIAN_BITFIELD)
729 struct cpl_l2t_write_req {
733 #define L2T_W_INFO(x) ((x) << 2)
734 #define L2T_W_PORT(x) ((x) << 8)
735 #define L2T_W_NOREPLY(x) ((x) << 15)
741 struct cpl_l2t_write_rpl {
747 struct cpl_rdma_terminate {
753 struct cpl_sge_egr_update {
755 #define EGR_QID(x) ((x) & 0x1FFFF)
760 /* cpl_fw*.type values */
765 FW_TYPE_OFLD_CONNECTION_WR_RPL = 3,
812 /* cpl_fw6_msg.type values */
814 FW6_TYPE_CMD_RPL = 0,
817 FW6_TYPE_OFLD_CONNECTION_WR_RPL = 3,
818 FW6_TYPE_RSSCPL = FW_TYPE_RSSCPL,
821 struct cpl_fw6_msg_ofld_connection_wr_rpl {
823 __be32 tid; /* or atid in case of active failure */
831 ULP_TX_MEM_WRITE = 3,
836 ULP_TX_SC_NOOP = 0x80,
837 ULP_TX_SC_IMM = 0x81,
838 ULP_TX_SC_DSGL = 0x82,
839 ULP_TX_SC_ISGL = 0x83
842 #define ULPTX_CMD_S 24
843 #define ULPTX_CMD_V(x) ((x) << ULPTX_CMD_S)
845 struct ulptx_sge_pair {
852 #define ULPTX_NSGE(x) ((x) << 0)
853 #define ULPTX_MORE (1U << 23)
856 struct ulptx_sge_pair sge[0];
862 __be32 len16; /* command length */
863 __be32 dlen; /* data length in 32-byte units */
865 #define ULP_MEMIO_LOCK(x) ((x) << 31)
868 /* additional ulp_mem_io.cmd fields */
869 #define ULP_MEMIO_ORDER_S 23
870 #define ULP_MEMIO_ORDER_V(x) ((x) << ULP_MEMIO_ORDER_S)
871 #define ULP_MEMIO_ORDER_F ULP_MEMIO_ORDER_V(1U)
873 #define T5_ULP_MEMIO_IMM_S 23
874 #define T5_ULP_MEMIO_IMM_V(x) ((x) << T5_ULP_MEMIO_IMM_S)
875 #define T5_ULP_MEMIO_IMM_F T5_ULP_MEMIO_IMM_V(1U)
877 #define S_T5_ULP_MEMIO_IMM 23
878 #define V_T5_ULP_MEMIO_IMM(x) ((x) << S_T5_ULP_MEMIO_IMM)
879 #define F_T5_ULP_MEMIO_IMM V_T5_ULP_MEMIO_IMM(1U)
881 #define S_T5_ULP_MEMIO_ORDER 22
882 #define V_T5_ULP_MEMIO_ORDER(x) ((x) << S_T5_ULP_MEMIO_ORDER)
883 #define F_T5_ULP_MEMIO_ORDER V_T5_ULP_MEMIO_ORDER(1U)
885 /* ulp_mem_io.lock_addr fields */
886 #define ULP_MEMIO_ADDR_S 0
887 #define ULP_MEMIO_ADDR_V(x) ((x) << ULP_MEMIO_ADDR_S)
889 /* ulp_mem_io.dlen fields */
890 #define ULP_MEMIO_DATA_LEN_S 0
891 #define ULP_MEMIO_DATA_LEN_V(x) ((x) << ULP_MEMIO_DATA_LEN_S)
893 #endif /* __T4_MSG_H */