2 * This file is part of the Chelsio T4 Ethernet driver for Linux.
4 * Copyright (c) 2003-2014 Chelsio Communications, Inc. All rights reserved.
6 * This software is available to you under a choice of one of two
7 * licenses. You may choose to be licensed under the terms of the GNU
8 * General Public License (GPL) Version 2, available from the file
9 * COPYING in the main directory of this source tree, or the
10 * OpenIB.org BSD license below:
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13 * without modification, are permitted provided that the following
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17 * copyright notice, this list of conditions and the following
20 * - Redistributions in binary form must reproduce the above
21 * copyright notice, this list of conditions and the following
22 * disclaimer in the documentation and/or other materials
23 * provided with the distribution.
25 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
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31 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
38 #include <linux/types.h>
41 CPL_PASS_OPEN_REQ = 0x1,
42 CPL_PASS_ACCEPT_RPL = 0x2,
43 CPL_ACT_OPEN_REQ = 0x3,
44 CPL_SET_TCB_FIELD = 0x5,
46 CPL_CLOSE_CON_REQ = 0x8,
47 CPL_CLOSE_LISTSRV_REQ = 0x9,
50 CPL_RX_DATA_ACK = 0xD,
52 CPL_L2T_WRITE_REQ = 0x12,
53 CPL_TID_RELEASE = 0x1A,
55 CPL_CLOSE_LISTSRV_RPL = 0x20,
56 CPL_L2T_WRITE_RPL = 0x23,
57 CPL_PASS_OPEN_RPL = 0x24,
58 CPL_ACT_OPEN_RPL = 0x25,
59 CPL_PEER_CLOSE = 0x26,
60 CPL_ABORT_REQ_RSS = 0x2B,
61 CPL_ABORT_RPL_RSS = 0x2D,
63 CPL_CLOSE_CON_RPL = 0x32,
66 CPL_RDMA_CQE_READ_RSP = 0x36,
67 CPL_RDMA_CQE_ERR = 0x37,
69 CPL_SET_TCB_RPL = 0x3A,
71 CPL_RX_DDP_COMPLETE = 0x3F,
73 CPL_ACT_ESTABLISH = 0x40,
74 CPL_PASS_ESTABLISH = 0x41,
75 CPL_RX_DATA_DDP = 0x42,
76 CPL_PASS_ACCEPT_REQ = 0x44,
77 CPL_TRACE_PKT_T5 = 0x48,
78 CPL_RX_ISCSI_DDP = 0x49,
80 CPL_RDMA_READ_REQ = 0x60,
82 CPL_PASS_OPEN_REQ6 = 0x81,
83 CPL_ACT_OPEN_REQ6 = 0x83,
85 CPL_RDMA_TERMINATE = 0xA2,
86 CPL_RDMA_WRITE = 0xA4,
87 CPL_SGE_EGR_UPDATE = 0xA5,
90 CPL_ISCSI_DATA = 0xB2,
98 CPL_TX_PKT_LSO = 0xED,
106 CPL_ERR_TCAM_FULL = 3,
107 CPL_ERR_BAD_LENGTH = 15,
108 CPL_ERR_BAD_ROUTE = 18,
109 CPL_ERR_CONN_RESET = 20,
110 CPL_ERR_CONN_EXIST_SYNRECV = 21,
111 CPL_ERR_CONN_EXIST = 22,
112 CPL_ERR_ARP_MISS = 23,
113 CPL_ERR_BAD_SYN = 24,
114 CPL_ERR_CONN_TIMEDOUT = 30,
115 CPL_ERR_XMIT_TIMEDOUT = 31,
116 CPL_ERR_PERSIST_TIMEDOUT = 32,
117 CPL_ERR_FINWAIT2_TIMEDOUT = 33,
118 CPL_ERR_KEEPALIVE_TIMEDOUT = 34,
119 CPL_ERR_RTX_NEG_ADVICE = 35,
120 CPL_ERR_PERSIST_NEG_ADVICE = 36,
121 CPL_ERR_KEEPALV_NEG_ADVICE = 37,
122 CPL_ERR_ABORT_FAILED = 42,
123 CPL_ERR_IWARP_FLM = 50,
135 ULP_CRC_HEADER = 1 << 0,
136 ULP_CRC_DATA = 1 << 1
140 CPL_ABORT_SEND_RST = 0,
144 enum { /* TX_PKT_XT checksum types */
163 #define CPL_OPCODE(x) ((x) << 24)
164 #define G_CPL_OPCODE(x) (((x) >> 24) & 0xFF)
165 #define MK_OPCODE_TID(opcode, tid) (CPL_OPCODE(opcode) | (tid))
166 #define OPCODE_TID(cmd) ((cmd)->ot.opcode_tid)
167 #define GET_TID(cmd) (ntohl(OPCODE_TID(cmd)) & 0xFFFFFF)
169 /* partitioning of TID fields that also carry a queue id */
170 #define GET_TID_TID(x) ((x) & 0x3fff)
171 #define GET_TID_QID(x) (((x) >> 14) & 0x3ff)
172 #define TID_QID(x) ((x) << 14)
176 #if defined(__LITTLE_ENDIAN_BITFIELD)
195 struct work_request_hdr {
203 #define V_WR_OP(x) ((__u64)(x) << S_WR_OP)
205 #define WR_HDR struct work_request_hdr wr
207 /* option 0 fields */
209 #define M_MSS_IDX 0xF
210 #define V_MSS_IDX(x) ((__u64)(x) << S_MSS_IDX)
211 #define G_MSS_IDX(x) (((x) >> S_MSS_IDX) & M_MSS_IDX)
213 /* option 2 fields */
214 #define S_RSS_QUEUE 0
215 #define M_RSS_QUEUE 0x3FF
216 #define V_RSS_QUEUE(x) ((x) << S_RSS_QUEUE)
217 #define G_RSS_QUEUE(x) (((x) >> S_RSS_QUEUE) & M_RSS_QUEUE)
219 struct cpl_pass_open_req {
227 #define TX_CHAN(x) ((x) << 2)
228 #define NO_CONG(x) ((x) << 4)
229 #define DELACK(x) ((x) << 5)
230 #define ULP_MODE(x) ((x) << 8)
231 #define RCV_BUFSIZ(x) ((x) << 12)
232 #define RCV_BUFSIZ_MASK 0x3FFU
233 #define DSCP(x) ((x) << 22)
234 #define SMAC_SEL(x) ((u64)(x) << 28)
235 #define L2T_IDX(x) ((u64)(x) << 36)
236 #define TCAM_BYPASS(x) ((u64)(x) << 48)
237 #define NAGLE(x) ((u64)(x) << 49)
238 #define WND_SCALE(x) ((u64)(x) << 50)
239 #define KEEP_ALIVE(x) ((u64)(x) << 54)
240 #define MSS_IDX(x) ((u64)(x) << 60)
242 #define SYN_RSS_ENABLE (1 << 0)
243 #define SYN_RSS_QUEUE(x) ((x) << 2)
244 #define CONN_POLICY_ASK (1 << 22)
247 struct cpl_pass_open_req6 {
260 struct cpl_pass_open_rpl {
266 struct cpl_pass_accept_rpl {
270 #define RSS_QUEUE(x) ((x) << 0)
271 #define RSS_QUEUE_VALID (1 << 10)
272 #define RX_COALESCE_VALID(x) ((x) << 11)
273 #define RX_COALESCE(x) ((x) << 12)
274 #define PACE(x) ((x) << 16)
275 #define RX_FC_VALID ((1U) << 19)
276 #define RX_FC_DISABLE ((1U) << 20)
277 #define TX_QUEUE(x) ((x) << 23)
278 #define RX_CHANNEL(x) ((x) << 26)
279 #define CCTRL_ECN(x) ((x) << 27)
280 #define WND_SCALE_EN(x) ((x) << 28)
281 #define TSTAMPS_EN(x) ((x) << 29)
282 #define SACK_EN(x) ((x) << 30)
283 #define T5_OPT_2_VALID ((1U) << 31)
287 struct cpl_t5_pass_accept_rpl {
296 struct cpl_act_open_req {
308 #define S_FILTER_TUPLE 24
309 #define M_FILTER_TUPLE 0xFFFFFFFFFF
310 #define V_FILTER_TUPLE(x) ((x) << S_FILTER_TUPLE)
311 #define G_FILTER_TUPLE(x) (((x) >> S_FILTER_TUPLE) & M_FILTER_TUPLE)
312 struct cpl_t5_act_open_req {
325 struct cpl_act_open_req6 {
339 struct cpl_t5_act_open_req6 {
354 struct cpl_act_open_rpl {
357 #define GET_AOPEN_STATUS(x) ((x) & 0xff)
358 #define GET_AOPEN_ATID(x) (((x) >> 8) & 0xffffff)
361 struct cpl_pass_establish {
365 #define PASS_OPEN_TID(x) ((x) << 0)
366 #define PASS_OPEN_TOS(x) ((x) << 24)
367 #define GET_PASS_OPEN_TID(x) (((x) >> 0) & 0xFFFFFF)
368 #define GET_POPEN_TID(x) ((x) & 0xffffff)
369 #define GET_POPEN_TOS(x) (((x) >> 24) & 0xff)
372 #define GET_TCPOPT_WSCALE_OK(x) (((x) >> 5) & 1)
373 #define GET_TCPOPT_SACK(x) (((x) >> 6) & 1)
374 #define GET_TCPOPT_TSTAMP(x) (((x) >> 7) & 1)
375 #define GET_TCPOPT_SND_WSCALE(x) (((x) >> 8) & 0xf)
376 #define GET_TCPOPT_MSS(x) (((x) >> 12) & 0xf)
381 struct cpl_act_establish {
395 #define QUEUENO(x) ((x) << 0)
396 #define REPLY_CHAN(x) ((x) << 14)
397 #define NO_REPLY(x) ((x) << 15)
401 struct cpl_set_tcb_field {
406 #define TCB_WORD(x) ((x) << 0)
407 #define TCB_COOKIE(x) ((x) << 5)
408 #define GET_TCB_COOKIE(x) (((x) >> 5) & 7)
413 struct cpl_set_tcb_rpl {
421 struct cpl_close_con_req {
427 struct cpl_close_con_rpl {
435 struct cpl_close_listsvr_req {
439 #define LISTSVR_IPV6(x) ((x) << 14)
443 struct cpl_close_listsvr_rpl {
449 struct cpl_abort_req_rss {
455 struct cpl_abort_req {
464 struct cpl_abort_rpl_rss {
470 struct cpl_abort_rpl {
479 struct cpl_peer_close {
484 struct cpl_tid_release {
490 struct cpl_tx_pkt_core {
492 #define TXPKT_VF(x) ((x) << 0)
493 #define TXPKT_PF(x) ((x) << 8)
494 #define TXPKT_VF_VLD (1 << 11)
495 #define TXPKT_OVLAN_IDX(x) ((x) << 12)
496 #define TXPKT_INTF(x) ((x) << 16)
497 #define TXPKT_INS_OVLAN (1 << 21)
498 #define TXPKT_OPCODE(x) ((x) << 24)
502 #define TXPKT_CSUM_END(x) ((x) << 12)
503 #define TXPKT_CSUM_START(x) ((x) << 20)
504 #define TXPKT_IPHDR_LEN(x) ((u64)(x) << 20)
505 #define TXPKT_CSUM_LOC(x) ((u64)(x) << 30)
506 #define TXPKT_ETHHDR_LEN(x) ((u64)(x) << 34)
507 #define TXPKT_CSUM_TYPE(x) ((u64)(x) << 40)
508 #define TXPKT_VLAN(x) ((u64)(x) << 44)
509 #define TXPKT_VLAN_VLD (1ULL << 60)
510 #define TXPKT_IPCSUM_DIS (1ULL << 62)
511 #define TXPKT_L4CSUM_DIS (1ULL << 63)
516 struct cpl_tx_pkt_core c;
519 #define cpl_tx_pkt_xt cpl_tx_pkt
521 struct cpl_tx_pkt_lso_core {
523 #define LSO_TCPHDR_LEN(x) ((x) << 0)
524 #define LSO_IPHDR_LEN(x) ((x) << 4)
525 #define LSO_ETHHDR_LEN(x) ((x) << 16)
526 #define LSO_IPV6(x) ((x) << 20)
527 #define LSO_LAST_SLICE (1 << 22)
528 #define LSO_FIRST_SLICE (1 << 23)
529 #define LSO_OPCODE(x) ((x) << 24)
530 #define LSO_T5_XFER_SIZE(x) ((x) << 0)
535 /* encapsulated CPL (TX_PKT, TX_PKT_XT or TX_DATA) follows here */
538 struct cpl_tx_pkt_lso {
540 struct cpl_tx_pkt_lso_core c;
541 /* encapsulated CPL (TX_PKT, TX_PKT_XT or TX_DATA) follows here */
544 struct cpl_iscsi_hdr {
547 #define ISCSI_PDU_LEN(x) ((x) & 0x7FFF)
548 #define ISCSI_DDP (1 << 15)
562 #if defined(__LITTLE_ENDIAN_BITFIELD)
578 struct cpl_rx_data_ack {
582 #define RX_CREDITS(x) ((x) << 0)
583 #define RX_FORCE_ACK(x) ((x) << 28)
587 struct rss_header rsshdr;
589 #if defined(__LITTLE_ENDIAN_BITFIELD)
606 #define RXF_UDP (1 << 22)
607 #define RXF_TCP (1 << 23)
608 #define RXF_IP (1 << 24)
609 #define RXF_IP6 (1 << 25)
614 /* rx_pkt.l2info fields */
615 #define S_RX_ETHHDR_LEN 0
616 #define M_RX_ETHHDR_LEN 0x1F
617 #define V_RX_ETHHDR_LEN(x) ((x) << S_RX_ETHHDR_LEN)
618 #define G_RX_ETHHDR_LEN(x) (((x) >> S_RX_ETHHDR_LEN) & M_RX_ETHHDR_LEN)
620 #define S_RX_T5_ETHHDR_LEN 0
621 #define M_RX_T5_ETHHDR_LEN 0x3F
622 #define V_RX_T5_ETHHDR_LEN(x) ((x) << S_RX_T5_ETHHDR_LEN)
623 #define G_RX_T5_ETHHDR_LEN(x) (((x) >> S_RX_T5_ETHHDR_LEN) & M_RX_T5_ETHHDR_LEN)
625 #define S_RX_MACIDX 8
626 #define M_RX_MACIDX 0x1FF
627 #define V_RX_MACIDX(x) ((x) << S_RX_MACIDX)
628 #define G_RX_MACIDX(x) (((x) >> S_RX_MACIDX) & M_RX_MACIDX)
631 #define V_RXF_SYN(x) ((x) << S_RXF_SYN)
632 #define F_RXF_SYN V_RXF_SYN(1U)
635 #define M_RX_CHAN 0xF
636 #define V_RX_CHAN(x) ((x) << S_RX_CHAN)
637 #define G_RX_CHAN(x) (((x) >> S_RX_CHAN) & M_RX_CHAN)
639 /* rx_pkt.hdr_len fields */
640 #define S_RX_TCPHDR_LEN 0
641 #define M_RX_TCPHDR_LEN 0x3F
642 #define V_RX_TCPHDR_LEN(x) ((x) << S_RX_TCPHDR_LEN)
643 #define G_RX_TCPHDR_LEN(x) (((x) >> S_RX_TCPHDR_LEN) & M_RX_TCPHDR_LEN)
645 #define S_RX_IPHDR_LEN 6
646 #define M_RX_IPHDR_LEN 0x3FF
647 #define V_RX_IPHDR_LEN(x) ((x) << S_RX_IPHDR_LEN)
648 #define G_RX_IPHDR_LEN(x) (((x) >> S_RX_IPHDR_LEN) & M_RX_IPHDR_LEN)
650 struct cpl_trace_pkt {
653 #if defined(__LITTLE_ENDIAN_BITFIELD)
671 struct cpl_t5_trace_pkt {
674 #if defined(__LITTLE_ENDIAN_BITFIELD)
693 struct cpl_l2t_write_req {
697 #define L2T_W_INFO(x) ((x) << 2)
698 #define L2T_W_PORT(x) ((x) << 8)
699 #define L2T_W_NOREPLY(x) ((x) << 15)
705 struct cpl_l2t_write_rpl {
711 struct cpl_rdma_terminate {
717 struct cpl_sge_egr_update {
719 #define EGR_QID(x) ((x) & 0x1FFFF)
724 /* cpl_fw*.type values */
729 FW_TYPE_OFLD_CONNECTION_WR_RPL = 3,
776 /* cpl_fw6_msg.type values */
778 FW6_TYPE_CMD_RPL = 0,
781 FW6_TYPE_OFLD_CONNECTION_WR_RPL = 3,
782 FW6_TYPE_RSSCPL = FW_TYPE_RSSCPL,
785 struct cpl_fw6_msg_ofld_connection_wr_rpl {
787 __be32 tid; /* or atid in case of active failure */
795 ULP_TX_MEM_WRITE = 3,
800 ULP_TX_SC_NOOP = 0x80,
801 ULP_TX_SC_IMM = 0x81,
802 ULP_TX_SC_DSGL = 0x82,
803 ULP_TX_SC_ISGL = 0x83
806 struct ulptx_sge_pair {
813 #define ULPTX_CMD(x) ((x) << 24)
814 #define ULPTX_NSGE(x) ((x) << 0)
815 #define ULPTX_MORE (1U << 23)
818 struct ulptx_sge_pair sge[0];
824 #define ULP_MEMIO_ORDER(x) ((x) << 23)
825 __be32 len16; /* command length */
826 __be32 dlen; /* data length in 32-byte units */
827 #define ULP_MEMIO_DATA_LEN(x) ((x) << 0)
829 #define ULP_MEMIO_ADDR(x) ((x) << 0)
830 #define ULP_MEMIO_LOCK(x) ((x) << 31)
833 #define S_T5_ULP_MEMIO_IMM 23
834 #define V_T5_ULP_MEMIO_IMM(x) ((x) << S_T5_ULP_MEMIO_IMM)
835 #define F_T5_ULP_MEMIO_IMM V_T5_ULP_MEMIO_IMM(1U)
837 #define S_T5_ULP_MEMIO_ORDER 22
838 #define V_T5_ULP_MEMIO_ORDER(x) ((x) << S_T5_ULP_MEMIO_ORDER)
839 #define F_T5_ULP_MEMIO_ORDER V_T5_ULP_MEMIO_ORDER(1U)
841 #endif /* __T4_MSG_H */