drivers/net/ethernet/emulex/benet/be_cmds.c

   1 /*
   2  * Copyright (C) 2005 - 2011 Emulex
   3  * All rights reserved.
   4  *
   5  * This program is free software; you can redistribute it and/or
   6  * modify it under the terms of the GNU General Public License version 2
   7  * as published by the Free Software Foundation.  The full GNU General
   8  * Public License is included in this distribution in the file called COPYING.
   9  *
  10  * Contact Information:
  11  * linux-drivers@emulex.com
  12  *
  13  * Emulex
  14  * 3333 Susan Street
  15  * Costa Mesa, CA 92626
  16  */
  17
  18 #include <linux/module.h>
  19 #include "be.h"
  20 #include "be_cmds.h"
  21
  22 static inline void *embedded_payload(struct be_mcc_wrb *wrb)
  23 {
  24         return wrb->payload.embedded_payload;
  25 }
  26
  27 static void be_mcc_notify(struct be_adapter *adapter)
  28 {
  29         struct be_queue_info *mccq = &adapter->mcc_obj.q;
  30         u32 val = 0;
  31
  32         if (be_error(adapter))
  33                 return;
  34
  35         val |= mccq->id & DB_MCCQ_RING_ID_MASK;
  36         val |= 1 << DB_MCCQ_NUM_POSTED_SHIFT;
  37
  38         wmb();
  39         iowrite32(val, adapter->db + DB_MCCQ_OFFSET);
  40 }
  41
  42 /* To check if valid bit is set, check the entire word as we don't know
  43  * the endianness of the data (old entry is host endian while a new entry is
  44  * little endian) */
  45 static inline bool be_mcc_compl_is_new(struct be_mcc_compl *compl)
  46 {
  47         if (compl->flags != 0) {
  48                 compl->flags = le32_to_cpu(compl->flags);
  49                 BUG_ON((compl->flags & CQE_FLAGS_VALID_MASK) == 0);
  50                 return true;
  51         } else {
  52                 return false;
  53         }
  54 }
  55
  56 /* Need to reset the entire word that houses the valid bit */
  57 static inline void be_mcc_compl_use(struct be_mcc_compl *compl)
  58 {
  59         compl->flags = 0;
  60 }
  61
  62 static struct be_cmd_resp_hdr *be_decode_resp_hdr(u32 tag0, u32 tag1)
  63 {
  64         unsigned long addr;
  65
  66         addr = tag1;
  67         addr = ((addr << 16) << 16) | tag0;
  68         return (void *)addr;
  69 }
  70
  71 static int be_mcc_compl_process(struct be_adapter *adapter,
  72                                 struct be_mcc_compl *compl)
  73 {
  74         u16 compl_status, extd_status;
  75         struct be_cmd_resp_hdr *resp_hdr;
  76         u8 opcode = 0, subsystem = 0;
  77
  78         /* Just swap the status to host endian; mcc tag is opaquely copied
  79          * from mcc_wrb */
  80         be_dws_le_to_cpu(compl, 4);
  81
  82         compl_status = (compl->status >> CQE_STATUS_COMPL_SHIFT) &
  83                                 CQE_STATUS_COMPL_MASK;
  84
  85         resp_hdr = be_decode_resp_hdr(compl->tag0, compl->tag1);
  86
  87         if (resp_hdr) {
  88                 opcode = resp_hdr->opcode;
  89                 subsystem = resp_hdr->subsystem;
  90         }
  91
  92         if (((opcode == OPCODE_COMMON_WRITE_FLASHROM) ||
  93              (opcode == OPCODE_COMMON_WRITE_OBJECT)) &&
  94             (subsystem == CMD_SUBSYSTEM_COMMON)) {
  95                 adapter->flash_status = compl_status;
  96                 complete(&adapter->flash_compl);
  97         }
  98
  99         if (compl_status == MCC_STATUS_SUCCESS) {
 100                 if (((opcode == OPCODE_ETH_GET_STATISTICS) ||
 101                      (opcode == OPCODE_ETH_GET_PPORT_STATS)) &&
 102                     (subsystem == CMD_SUBSYSTEM_ETH)) {
 103                         be_parse_stats(adapter);
 104                         adapter->stats_cmd_sent = false;
 105                 }
 106                 if (opcode == OPCODE_COMMON_GET_CNTL_ADDITIONAL_ATTRIBUTES &&
 107                     subsystem == CMD_SUBSYSTEM_COMMON) {
 108                         struct be_cmd_resp_get_cntl_addnl_attribs *resp =
 109                                 (void *)resp_hdr;
 110                         adapter->drv_stats.be_on_die_temperature =
 111                                 resp->on_die_temperature;
 112                 }
 113         } else {
 114                 if (opcode == OPCODE_COMMON_GET_CNTL_ADDITIONAL_ATTRIBUTES)
 115                         adapter->be_get_temp_freq = 0;
 116
 117                 if (compl_status == MCC_STATUS_NOT_SUPPORTED ||
 118                         compl_status == MCC_STATUS_ILLEGAL_REQUEST)
 119                         goto done;
 120
 121                 if (compl_status == MCC_STATUS_UNAUTHORIZED_REQUEST) {
 122                         dev_warn(&adapter->pdev->dev,
 123                                  "opcode %d-%d is not permitted\n",
 124                                  opcode, subsystem);
 125                 } else {
 126                         extd_status = (compl->status >> CQE_STATUS_EXTD_SHIFT) &
 127                                         CQE_STATUS_EXTD_MASK;
 128                         dev_err(&adapter->pdev->dev,
 129                                 "opcode %d-%d failed:status %d-%d\n",
 130                                 opcode, subsystem, compl_status, extd_status);
 131                 }
 132         }
 133 done:
 134         return compl_status;
 135 }
 136
 137 /* Link state evt is a string of bytes; no need for endian swapping */
 138 static void be_async_link_state_process(struct be_adapter *adapter,
 139                 struct be_async_event_link_state *evt)
 140 {
 141         /* When link status changes, link speed must be re-queried from FW */
 142         adapter->phy.link_speed = -1;
 143
 144         /* For the initial link status do not rely on the ASYNC event as
 145          * it may not be received in some cases.
 146          */
 147         if (adapter->flags & BE_FLAGS_LINK_STATUS_INIT)
 148                 be_link_status_update(adapter, evt->port_link_status);
 149 }
 150
 151 /* Grp5 CoS Priority evt */
 152 static void be_async_grp5_cos_priority_process(struct be_adapter *adapter,
 153                 struct be_async_event_grp5_cos_priority *evt)
 154 {
 155         if (evt->valid) {
 156                 adapter->vlan_prio_bmap = evt->available_priority_bmap;
 157                 adapter->recommended_prio &= ~VLAN_PRIO_MASK;
 158                 adapter->recommended_prio =
 159                         evt->reco_default_priority << VLAN_PRIO_SHIFT;
 160         }
 161 }
 162
 163 /* Grp5 QOS Speed evt */
 164 static void be_async_grp5_qos_speed_process(struct be_adapter *adapter,
 165                 struct be_async_event_grp5_qos_link_speed *evt)
 166 {
 167         if (evt->physical_port == adapter->port_num) {
 168                 /* qos_link_speed is in units of 10 Mbps */
 169                 adapter->phy.link_speed = evt->qos_link_speed * 10;
 170         }
 171 }
 172
 173 /*Grp5 PVID evt*/
 174 static void be_async_grp5_pvid_state_process(struct be_adapter *adapter,
 175                 struct be_async_event_grp5_pvid_state *evt)
 176 {
 177         if (evt->enabled)
 178                 adapter->pvid = le16_to_cpu(evt->tag) & VLAN_VID_MASK;
 179         else
 180                 adapter->pvid = 0;
 181 }
 182
 183 static void be_async_grp5_evt_process(struct be_adapter *adapter,
 184                 u32 trailer, struct be_mcc_compl *evt)
 185 {
 186         u8 event_type = 0;
 187
 188         event_type = (trailer >> ASYNC_TRAILER_EVENT_TYPE_SHIFT) &
 189                 ASYNC_TRAILER_EVENT_TYPE_MASK;
 190
 191         switch (event_type) {
 192         case ASYNC_EVENT_COS_PRIORITY:
 193                 be_async_grp5_cos_priority_process(adapter,
 194                 (struct be_async_event_grp5_cos_priority *)evt);
 195         break;
 196         case ASYNC_EVENT_QOS_SPEED:
 197                 be_async_grp5_qos_speed_process(adapter,
 198                 (struct be_async_event_grp5_qos_link_speed *)evt);
 199         break;
 200         case ASYNC_EVENT_PVID_STATE:
 201                 be_async_grp5_pvid_state_process(adapter,
 202                 (struct be_async_event_grp5_pvid_state *)evt);
 203         break;
 204         default:
 205                 dev_warn(&adapter->pdev->dev, "Unknown grp5 event!\n");
 206                 break;
 207         }
 208 }
 209
 210 static inline bool is_link_state_evt(u32 trailer)
 211 {
 212         return ((trailer >> ASYNC_TRAILER_EVENT_CODE_SHIFT) &
 213                 ASYNC_TRAILER_EVENT_CODE_MASK) ==
 214                                 ASYNC_EVENT_CODE_LINK_STATE;
 215 }
 216
 217 static inline bool is_grp5_evt(u32 trailer)
 218 {
 219         return (((trailer >> ASYNC_TRAILER_EVENT_CODE_SHIFT) &
 220                 ASYNC_TRAILER_EVENT_CODE_MASK) ==
 221                                 ASYNC_EVENT_CODE_GRP_5);
 222 }
 223
 224 static struct be_mcc_compl *be_mcc_compl_get(struct be_adapter *adapter)
 225 {
 226         struct be_queue_info *mcc_cq = &adapter->mcc_obj.cq;
 227         struct be_mcc_compl *compl = queue_tail_node(mcc_cq);
 228
 229         if (be_mcc_compl_is_new(compl)) {
 230                 queue_tail_inc(mcc_cq);
 231                 return compl;
 232         }
 233         return NULL;
 234 }
 235
 236 void be_async_mcc_enable(struct be_adapter *adapter)
 237 {
 238         spin_lock_bh(&adapter->mcc_cq_lock);
 239
 240         be_cq_notify(adapter, adapter->mcc_obj.cq.id, true, 0);
 241         adapter->mcc_obj.rearm_cq = true;
 242
 243         spin_unlock_bh(&adapter->mcc_cq_lock);
 244 }
 245
 246 void be_async_mcc_disable(struct be_adapter *adapter)
 247 {
 248         adapter->mcc_obj.rearm_cq = false;
 249 }
 250
 251 int be_process_mcc(struct be_adapter *adapter)
 252 {
 253         struct be_mcc_compl *compl;
 254         int num = 0, status = 0;
 255         struct be_mcc_obj *mcc_obj = &adapter->mcc_obj;
 256
 257         spin_lock_bh(&adapter->mcc_cq_lock);
 258         while ((compl = be_mcc_compl_get(adapter))) {
 259                 if (compl->flags & CQE_FLAGS_ASYNC_MASK) {
 260                         /* Interpret flags as an async trailer */
 261                         if (is_link_state_evt(compl->flags))
 262                                 be_async_link_state_process(adapter,
 263                                 (struct be_async_event_link_state *) compl);
 264                         else if (is_grp5_evt(compl->flags))
 265                                 be_async_grp5_evt_process(adapter,
 266                                 compl->flags, compl);
 267                 } else if (compl->flags & CQE_FLAGS_COMPLETED_MASK) {
 268                                 status = be_mcc_compl_process(adapter, compl);
 269                                 atomic_dec(&mcc_obj->q.used);
 270                 }
 271                 be_mcc_compl_use(compl);
 272                 num++;
 273         }
 274
 275         if (num)
 276                 be_cq_notify(adapter, mcc_obj->cq.id, mcc_obj->rearm_cq, num);
 277
 278         spin_unlock_bh(&adapter->mcc_cq_lock);
 279         return status;
 280 }
 281
 282 /* Wait till no more pending mcc requests are present */
 283 static int be_mcc_wait_compl(struct be_adapter *adapter)
 284 {
 285 #define mcc_timeout             120000 /* 12s timeout */
 286         int i, status = 0;
 287         struct be_mcc_obj *mcc_obj = &adapter->mcc_obj;
 288
 289         for (i = 0; i < mcc_timeout; i++) {
 290                 if (be_error(adapter))
 291                         return -EIO;
 292
 293                 status = be_process_mcc(adapter);
 294
 295                 if (atomic_read(&mcc_obj->q.used) == 0)
 296                         break;
 297                 udelay(100);
 298         }
 299         if (i == mcc_timeout) {
 300                 dev_err(&adapter->pdev->dev, "FW not responding\n");
 301                 adapter->fw_timeout = true;
 302                 return -EIO;
 303         }
 304         return status;
 305 }
 306
 307 /* Notify MCC requests and wait for completion */
 308 static int be_mcc_notify_wait(struct be_adapter *adapter)
 309 {
 310         int status;
 311         struct be_mcc_wrb *wrb;
 312         struct be_mcc_obj *mcc_obj = &adapter->mcc_obj;
 313         u16 index = mcc_obj->q.head;
 314         struct be_cmd_resp_hdr *resp;
 315
 316         index_dec(&index, mcc_obj->q.len);
 317         wrb = queue_index_node(&mcc_obj->q, index);
 318
 319         resp = be_decode_resp_hdr(wrb->tag0, wrb->tag1);
 320
 321         be_mcc_notify(adapter);
 322
 323         status = be_mcc_wait_compl(adapter);
 324         if (status == -EIO)
 325                 goto out;
 326
 327         status = resp->status;
 328 out:
 329         return status;
 330 }
 331
 332 static int be_mbox_db_ready_wait(struct be_adapter *adapter, void __iomem *db)
 333 {
 334         int msecs = 0;
 335         u32 ready;
 336
 337         do {
 338                 if (be_error(adapter))
 339                         return -EIO;
 340
 341                 ready = ioread32(db);
 342                 if (ready == 0xffffffff)
 343                         return -1;
 344
 345                 ready &= MPU_MAILBOX_DB_RDY_MASK;
 346                 if (ready)
 347                         break;
 348
 349                 if (msecs > 4000) {
 350                         dev_err(&adapter->pdev->dev, "FW not responding\n");
 351                         adapter->fw_timeout = true;
 352                         be_detect_error(adapter);
 353                         return -1;
 354                 }
 355
 356                 msleep(1);
 357                 msecs++;
 358         } while (true);
 359
 360         return 0;
 361 }
 362
 363 /*
 364  * Insert the mailbox address into the doorbell in two steps
 365  * Polls on the mbox doorbell till a command completion (or a timeout) occurs
 366  */
 367 static int be_mbox_notify_wait(struct be_adapter *adapter)
 368 {
 369         int status;
 370         u32 val = 0;
 371         void __iomem *db = adapter->db + MPU_MAILBOX_DB_OFFSET;
 372         struct be_dma_mem *mbox_mem = &adapter->mbox_mem;
 373         struct be_mcc_mailbox *mbox = mbox_mem->va;
 374         struct be_mcc_compl *compl = &mbox->compl;
 375
 376         /* wait for ready to be set */
 377         status = be_mbox_db_ready_wait(adapter, db);
 378         if (status != 0)
 379                 return status;
 380
 381         val |= MPU_MAILBOX_DB_HI_MASK;
 382         /* at bits 2 - 31 place mbox dma addr msb bits 34 - 63 */
 383         val |= (upper_32_bits(mbox_mem->dma) >> 2) << 2;
 384         iowrite32(val, db);
 385
 386         /* wait for ready to be set */
 387         status = be_mbox_db_ready_wait(adapter, db);
 388         if (status != 0)
 389                 return status;
 390
 391         val = 0;
 392         /* at bits 2 - 31 place mbox dma addr lsb bits 4 - 33 */
 393         val |= (u32)(mbox_mem->dma >> 4) << 2;
 394         iowrite32(val, db);
 395
 396         status = be_mbox_db_ready_wait(adapter, db);
 397         if (status != 0)
 398                 return status;
 399
 400         /* A cq entry has been made now */
 401         if (be_mcc_compl_is_new(compl)) {
 402                 status = be_mcc_compl_process(adapter, &mbox->compl);
 403                 be_mcc_compl_use(compl);
 404                 if (status)
 405                         return status;
 406         } else {
 407                 dev_err(&adapter->pdev->dev, "invalid mailbox completion\n");
 408                 return -1;
 409         }
 410         return 0;
 411 }
 412
 413 static int be_POST_stage_get(struct be_adapter *adapter, u16 *stage)
 414 {
 415         u32 sem;
 416
 417         if (lancer_chip(adapter))
 418                 sem  = ioread32(adapter->db + MPU_EP_SEMAPHORE_IF_TYPE2_OFFSET);
 419         else
 420                 sem  = ioread32(adapter->csr + MPU_EP_SEMAPHORE_OFFSET);
 421
 422         *stage = sem & EP_SEMAPHORE_POST_STAGE_MASK;
 423         if ((sem >> EP_SEMAPHORE_POST_ERR_SHIFT) & EP_SEMAPHORE_POST_ERR_MASK)
 424                 return -1;
 425         else
 426                 return 0;
 427 }
 428
 429 int lancer_wait_ready(struct be_adapter *adapter)
 430 {
 431 #define SLIPORT_READY_TIMEOUT 30
 432         u32 sliport_status;
 433         int status = 0, i;
 434
 435         for (i = 0; i < SLIPORT_READY_TIMEOUT; i++) {
 436                 sliport_status = ioread32(adapter->db + SLIPORT_STATUS_OFFSET);
 437                 if (sliport_status & SLIPORT_STATUS_RDY_MASK)
 438                         break;
 439
 440                 msleep(1000);
 441         }
 442
 443         if (i == SLIPORT_READY_TIMEOUT)
 444                 status = -1;
 445
 446         return status;
 447 }
 448
 449 int lancer_test_and_set_rdy_state(struct be_adapter *adapter)
 450 {
 451         int status;
 452         u32 sliport_status, err, reset_needed;
 453         status = lancer_wait_ready(adapter);
 454         if (!status) {
 455                 sliport_status = ioread32(adapter->db + SLIPORT_STATUS_OFFSET);
 456                 err = sliport_status & SLIPORT_STATUS_ERR_MASK;
 457                 reset_needed = sliport_status & SLIPORT_STATUS_RN_MASK;
 458                 if (err && reset_needed) {
 459                         iowrite32(SLI_PORT_CONTROL_IP_MASK,
 460                                   adapter->db + SLIPORT_CONTROL_OFFSET);
 461
 462                         /* check adapter has corrected the error */
 463                         status = lancer_wait_ready(adapter);
 464                         sliport_status = ioread32(adapter->db +
 465                                                   SLIPORT_STATUS_OFFSET);
 466                         sliport_status &= (SLIPORT_STATUS_ERR_MASK |
 467                                                 SLIPORT_STATUS_RN_MASK);
 468                         if (status || sliport_status)
 469                                 status = -1;
 470                 } else if (err || reset_needed) {
 471                         status = -1;
 472                 }
 473         }
 474         return status;
 475 }
 476
 477 int be_fw_wait_ready(struct be_adapter *adapter)
 478 {
 479         u16 stage;
 480         int status, timeout = 0;
 481         struct device *dev = &adapter->pdev->dev;
 482
 483         if (lancer_chip(adapter)) {
 484                 status = lancer_wait_ready(adapter);
 485                 return status;
 486         }
 487
 488         do {
 489                 status = be_POST_stage_get(adapter, &stage);
 490                 if (status) {
 491                         dev_err(dev, "POST error; stage=0x%x\n", stage);
 492                         return -1;
 493                 } else if (stage != POST_STAGE_ARMFW_RDY) {
 494                         if (msleep_interruptible(2000)) {
 495                                 dev_err(dev, "Waiting for POST aborted\n");
 496                                 return -EINTR;
 497                         }
 498                         timeout += 2;
 499                 } else {
 500                         return 0;
 501                 }
 502         } while (timeout < 60);
 503
 504         dev_err(dev, "POST timeout; stage=0x%x\n", stage);
 505         return -1;
 506 }
 507
 508
 509 static inline struct be_sge *nonembedded_sgl(struct be_mcc_wrb *wrb)
 510 {
 511         return &wrb->payload.sgl[0];
 512 }
 513
 514
 515 /* Don't touch the hdr after it's prepared */
 516 /* mem will be NULL for embedded commands */
 517 static void be_wrb_cmd_hdr_prepare(struct be_cmd_req_hdr *req_hdr,
 518                                 u8 subsystem, u8 opcode, int cmd_len,
 519                                 struct be_mcc_wrb *wrb, struct be_dma_mem *mem)
 520 {
 521         struct be_sge *sge;
 522         unsigned long addr = (unsigned long)req_hdr;
 523         u64 req_addr = addr;
 524
 525         req_hdr->opcode = opcode;
 526         req_hdr->subsystem = subsystem;
 527         req_hdr->request_length = cpu_to_le32(cmd_len - sizeof(*req_hdr));
 528         req_hdr->version = 0;
 529
 530         wrb->tag0 = req_addr & 0xFFFFFFFF;
 531         wrb->tag1 = upper_32_bits(req_addr);
 532
 533         wrb->payload_length = cmd_len;
 534         if (mem) {
 535                 wrb->embedded |= (1 & MCC_WRB_SGE_CNT_MASK) <<
 536                         MCC_WRB_SGE_CNT_SHIFT;
 537                 sge = nonembedded_sgl(wrb);
 538                 sge->pa_hi = cpu_to_le32(upper_32_bits(mem->dma));
 539                 sge->pa_lo = cpu_to_le32(mem->dma & 0xFFFFFFFF);
 540                 sge->len = cpu_to_le32(mem->size);
 541         } else
 542                 wrb->embedded |= MCC_WRB_EMBEDDED_MASK;
 543         be_dws_cpu_to_le(wrb, 8);
 544 }
 545
 546 static void be_cmd_page_addrs_prepare(struct phys_addr *pages, u32 max_pages,
 547                         struct be_dma_mem *mem)
 548 {
 549         int i, buf_pages = min(PAGES_4K_SPANNED(mem->va, mem->size), max_pages);
 550         u64 dma = (u64)mem->dma;
 551
 552         for (i = 0; i < buf_pages; i++) {
 553                 pages[i].lo = cpu_to_le32(dma & 0xFFFFFFFF);
 554                 pages[i].hi = cpu_to_le32(upper_32_bits(dma));
 555                 dma += PAGE_SIZE_4K;
 556         }
 557 }
 558
 559 /* Converts interrupt delay in microseconds to multiplier value */
 560 static u32 eq_delay_to_mult(u32 usec_delay)
 561 {
 562 #define MAX_INTR_RATE                   651042
 563         const u32 round = 10;
 564         u32 multiplier;
 565
 566         if (usec_delay == 0)
 567                 multiplier = 0;
 568         else {
 569                 u32 interrupt_rate = 1000000 / usec_delay;
 570                 /* Max delay, corresponding to the lowest interrupt rate */
 571                 if (interrupt_rate == 0)
 572                         multiplier = 1023;
 573                 else {
 574                         multiplier = (MAX_INTR_RATE - interrupt_rate) * round;
 575                         multiplier /= interrupt_rate;
 576                         /* Round the multiplier to the closest value.*/
 577                         multiplier = (multiplier + round/2) / round;
 578                         multiplier = min(multiplier, (u32)1023);
 579                 }
 580         }
 581         return multiplier;
 582 }
 583
 584 static inline struct be_mcc_wrb *wrb_from_mbox(struct be_adapter *adapter)
 585 {
 586         struct be_dma_mem *mbox_mem = &adapter->mbox_mem;
 587         struct be_mcc_wrb *wrb
 588                 = &((struct be_mcc_mailbox *)(mbox_mem->va))->wrb;
 589         memset(wrb, 0, sizeof(*wrb));
 590         return wrb;
 591 }
 592
 593 static struct be_mcc_wrb *wrb_from_mccq(struct be_adapter *adapter)
 594 {
 595         struct be_queue_info *mccq = &adapter->mcc_obj.q;
 596         struct be_mcc_wrb *wrb;
 597
 598         if (atomic_read(&mccq->used) >= mccq->len) {
 599                 dev_err(&adapter->pdev->dev, "Out of MCCQ wrbs\n");
 600                 return NULL;
 601         }
 602
 603         wrb = queue_head_node(mccq);
 604         queue_head_inc(mccq);
 605         atomic_inc(&mccq->used);
 606         memset(wrb, 0, sizeof(*wrb));
 607         return wrb;
 608 }
 609
 610 /* Tell fw we're about to start firing cmds by writing a
 611  * special pattern across the wrb hdr; uses mbox
 612  */
 613 int be_cmd_fw_init(struct be_adapter *adapter)
 614 {
 615         u8 *wrb;
 616         int status;
 617
 618         if (lancer_chip(adapter))
 619                 return 0;
 620
 621         if (mutex_lock_interruptible(&adapter->mbox_lock))
 622                 return -1;
 623
 624         wrb = (u8 *)wrb_from_mbox(adapter);
 625         *wrb++ = 0xFF;
 626         *wrb++ = 0x12;
 627         *wrb++ = 0x34;
 628         *wrb++ = 0xFF;
 629         *wrb++ = 0xFF;
 630         *wrb++ = 0x56;
 631         *wrb++ = 0x78;
 632         *wrb = 0xFF;
 633
 634         status = be_mbox_notify_wait(adapter);
 635
 636         mutex_unlock(&adapter->mbox_lock);
 637         return status;
 638 }
 639
 640 /* Tell fw we're done with firing cmds by writing a
 641  * special pattern across the wrb hdr; uses mbox
 642  */
 643 int be_cmd_fw_clean(struct be_adapter *adapter)
 644 {
 645         u8 *wrb;
 646         int status;
 647
 648         if (lancer_chip(adapter))
 649                 return 0;
 650
 651         if (mutex_lock_interruptible(&adapter->mbox_lock))
 652                 return -1;
 653
 654         wrb = (u8 *)wrb_from_mbox(adapter);
 655         *wrb++ = 0xFF;
 656         *wrb++ = 0xAA;
 657         *wrb++ = 0xBB;
 658         *wrb++ = 0xFF;
 659         *wrb++ = 0xFF;
 660         *wrb++ = 0xCC;
 661         *wrb++ = 0xDD;
 662         *wrb = 0xFF;
 663
 664         status = be_mbox_notify_wait(adapter);
 665
 666         mutex_unlock(&adapter->mbox_lock);
 667         return status;
 668 }
 669
 670 int be_cmd_eq_create(struct be_adapter *adapter,
 671                 struct be_queue_info *eq, int eq_delay)
 672 {
 673         struct be_mcc_wrb *wrb;
 674         struct be_cmd_req_eq_create *req;
 675         struct be_dma_mem *q_mem = &eq->dma_mem;
 676         int status;
 677
 678         if (mutex_lock_interruptible(&adapter->mbox_lock))
 679                 return -1;
 680
 681         wrb = wrb_from_mbox(adapter);
 682         req = embedded_payload(wrb);
 683
 684         be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
 685                 OPCODE_COMMON_EQ_CREATE, sizeof(*req), wrb, NULL);
 686
 687         req->num_pages =  cpu_to_le16(PAGES_4K_SPANNED(q_mem->va, q_mem->size));
 688
 689         AMAP_SET_BITS(struct amap_eq_context, valid, req->context, 1);
 690         /* 4byte eqe*/
 691         AMAP_SET_BITS(struct amap_eq_context, size, req->context, 0);
 692         AMAP_SET_BITS(struct amap_eq_context, count, req->context,
 693                         __ilog2_u32(eq->len/256));
 694         AMAP_SET_BITS(struct amap_eq_context, delaymult, req->context,
 695                         eq_delay_to_mult(eq_delay));
 696         be_dws_cpu_to_le(req->context, sizeof(req->context));
 697
 698         be_cmd_page_addrs_prepare(req->pages, ARRAY_SIZE(req->pages), q_mem);
 699
 700         status = be_mbox_notify_wait(adapter);
 701         if (!status) {
 702                 struct be_cmd_resp_eq_create *resp = embedded_payload(wrb);
 703                 eq->id = le16_to_cpu(resp->eq_id);
 704                 eq->created = true;
 705         }
 706
 707         mutex_unlock(&adapter->mbox_lock);
 708         return status;
 709 }
 710
 711 /* Use MCC */
 712 int be_cmd_mac_addr_query(struct be_adapter *adapter, u8 *mac_addr,
 713                         u8 type, bool permanent, u32 if_handle, u32 pmac_id)
 714 {
 715         struct be_mcc_wrb *wrb;
 716         struct be_cmd_req_mac_query *req;
 717         int status;
 718
 719         spin_lock_bh(&adapter->mcc_lock);
 720
 721         wrb = wrb_from_mccq(adapter);
 722         if (!wrb) {
 723                 status = -EBUSY;
 724                 goto err;
 725         }
 726         req = embedded_payload(wrb);
 727
 728         be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
 729                 OPCODE_COMMON_NTWK_MAC_QUERY, sizeof(*req), wrb, NULL);
 730         req->type = type;
 731         if (permanent) {
 732                 req->permanent = 1;
 733         } else {
 734                 req->if_id = cpu_to_le16((u16) if_handle);
 735                 req->pmac_id = cpu_to_le32(pmac_id);
 736                 req->permanent = 0;
 737         }
 738
 739         status = be_mcc_notify_wait(adapter);
 740         if (!status) {
 741                 struct be_cmd_resp_mac_query *resp = embedded_payload(wrb);
 742                 memcpy(mac_addr, resp->mac.addr, ETH_ALEN);
 743         }
 744
 745 err:
 746         spin_unlock_bh(&adapter->mcc_lock);
 747         return status;
 748 }
 749
 750 /* Uses synchronous MCCQ */
 751 int be_cmd_pmac_add(struct be_adapter *adapter, u8 *mac_addr,
 752                 u32 if_id, u32 *pmac_id, u32 domain)
 753 {
 754         struct be_mcc_wrb *wrb;
 755         struct be_cmd_req_pmac_add *req;
 756         int status;
 757
 758         spin_lock_bh(&adapter->mcc_lock);
 759
 760         wrb = wrb_from_mccq(adapter);
 761         if (!wrb) {
 762                 status = -EBUSY;
 763                 goto err;
 764         }
 765         req = embedded_payload(wrb);
 766
 767         be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
 768                 OPCODE_COMMON_NTWK_PMAC_ADD, sizeof(*req), wrb, NULL);
 769
 770         req->hdr.domain = domain;
 771         req->if_id = cpu_to_le32(if_id);
 772         memcpy(req->mac_address, mac_addr, ETH_ALEN);
 773
 774         status = be_mcc_notify_wait(adapter);
 775         if (!status) {
 776                 struct be_cmd_resp_pmac_add *resp = embedded_payload(wrb);
 777                 *pmac_id = le32_to_cpu(resp->pmac_id);
 778         }
 779
 780 err:
 781         spin_unlock_bh(&adapter->mcc_lock);
 782
 783          if (status == MCC_STATUS_UNAUTHORIZED_REQUEST)
 784                 status = -EPERM;
 785
 786         return status;
 787 }
 788
 789 /* Uses synchronous MCCQ */
 790 int be_cmd_pmac_del(struct be_adapter *adapter, u32 if_id, int pmac_id, u32 dom)
 791 {
 792         struct be_mcc_wrb *wrb;
 793         struct be_cmd_req_pmac_del *req;
 794         int status;
 795
 796         if (pmac_id == -1)
 797                 return 0;
 798
 799         spin_lock_bh(&adapter->mcc_lock);
 800
 801         wrb = wrb_from_mccq(adapter);
 802         if (!wrb) {
 803                 status = -EBUSY;
 804                 goto err;
 805         }
 806         req = embedded_payload(wrb);
 807
 808         be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
 809                 OPCODE_COMMON_NTWK_PMAC_DEL, sizeof(*req), wrb, NULL);
 810
 811         req->hdr.domain = dom;
 812         req->if_id = cpu_to_le32(if_id);
 813         req->pmac_id = cpu_to_le32(pmac_id);
 814
 815         status = be_mcc_notify_wait(adapter);
 816
 817 err:
 818         spin_unlock_bh(&adapter->mcc_lock);
 819         return status;
 820 }
 821
 822 /* Uses Mbox */
 823 int be_cmd_cq_create(struct be_adapter *adapter, struct be_queue_info *cq,
 824                 struct be_queue_info *eq, bool no_delay, int coalesce_wm)
 825 {
 826         struct be_mcc_wrb *wrb;
 827         struct be_cmd_req_cq_create *req;
 828         struct be_dma_mem *q_mem = &cq->dma_mem;
 829         void *ctxt;
 830         int status;
 831
 832         if (mutex_lock_interruptible(&adapter->mbox_lock))
 833                 return -1;
 834
 835         wrb = wrb_from_mbox(adapter);
 836         req = embedded_payload(wrb);
 837         ctxt = &req->context;
 838
 839         be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
 840                 OPCODE_COMMON_CQ_CREATE, sizeof(*req), wrb, NULL);
 841
 842         req->num_pages =  cpu_to_le16(PAGES_4K_SPANNED(q_mem->va, q_mem->size));
 843         if (lancer_chip(adapter)) {
 844                 req->hdr.version = 2;
 845                 req->page_size = 1; /* 1 for 4K */
 846                 AMAP_SET_BITS(struct amap_cq_context_lancer, nodelay, ctxt,
 847                                                                 no_delay);
 848                 AMAP_SET_BITS(struct amap_cq_context_lancer, count, ctxt,
 849                                                 __ilog2_u32(cq->len/256));
 850                 AMAP_SET_BITS(struct amap_cq_context_lancer, valid, ctxt, 1);
 851                 AMAP_SET_BITS(struct amap_cq_context_lancer, eventable,
 852                                                                 ctxt, 1);
 853                 AMAP_SET_BITS(struct amap_cq_context_lancer, eqid,
 854                                                                 ctxt, eq->id);
 855         } else {
 856                 AMAP_SET_BITS(struct amap_cq_context_be, coalescwm, ctxt,
 857                                                                 coalesce_wm);
 858                 AMAP_SET_BITS(struct amap_cq_context_be, nodelay,
 859                                                                 ctxt, no_delay);
 860                 AMAP_SET_BITS(struct amap_cq_context_be, count, ctxt,
 861                                                 __ilog2_u32(cq->len/256));
 862                 AMAP_SET_BITS(struct amap_cq_context_be, valid, ctxt, 1);
 863                 AMAP_SET_BITS(struct amap_cq_context_be, eventable, ctxt, 1);
 864                 AMAP_SET_BITS(struct amap_cq_context_be, eqid, ctxt, eq->id);
 865         }
 866
 867         be_dws_cpu_to_le(ctxt, sizeof(req->context));
 868
 869         be_cmd_page_addrs_prepare(req->pages, ARRAY_SIZE(req->pages), q_mem);
 870
 871         status = be_mbox_notify_wait(adapter);
 872         if (!status) {
 873                 struct be_cmd_resp_cq_create *resp = embedded_payload(wrb);
 874                 cq->id = le16_to_cpu(resp->cq_id);
 875                 cq->created = true;
 876         }
 877
 878         mutex_unlock(&adapter->mbox_lock);
 879
 880         return status;
 881 }
 882
 883 static u32 be_encoded_q_len(int q_len)
 884 {
 885         u32 len_encoded = fls(q_len); /* log2(len) + 1 */
 886         if (len_encoded == 16)
 887                 len_encoded = 0;
 888         return len_encoded;
 889 }
 890
 891 int be_cmd_mccq_ext_create(struct be_adapter *adapter,
 892                         struct be_queue_info *mccq,
 893                         struct be_queue_info *cq)
 894 {
 895         struct be_mcc_wrb *wrb;
 896         struct be_cmd_req_mcc_ext_create *req;
 897         struct be_dma_mem *q_mem = &mccq->dma_mem;
 898         void *ctxt;
 899         int status;
 900
 901         if (mutex_lock_interruptible(&adapter->mbox_lock))
 902                 return -1;
 903
 904         wrb = wrb_from_mbox(adapter);
 905         req = embedded_payload(wrb);
 906         ctxt = &req->context;
 907
 908         be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
 909                         OPCODE_COMMON_MCC_CREATE_EXT, sizeof(*req), wrb, NULL);
 910
 911         req->num_pages = cpu_to_le16(PAGES_4K_SPANNED(q_mem->va, q_mem->size));
 912         if (lancer_chip(adapter)) {
 913                 req->hdr.version = 1;
 914                 req->cq_id = cpu_to_le16(cq->id);
 915
 916                 AMAP_SET_BITS(struct amap_mcc_context_lancer, ring_size, ctxt,
 917                                                 be_encoded_q_len(mccq->len));
 918                 AMAP_SET_BITS(struct amap_mcc_context_lancer, valid, ctxt, 1);
 919                 AMAP_SET_BITS(struct amap_mcc_context_lancer, async_cq_id,
 920                                                                 ctxt, cq->id);
 921                 AMAP_SET_BITS(struct amap_mcc_context_lancer, async_cq_valid,
 922                                                                  ctxt, 1);
 923
 924         } else {
 925                 AMAP_SET_BITS(struct amap_mcc_context_be, valid, ctxt, 1);
 926                 AMAP_SET_BITS(struct amap_mcc_context_be, ring_size, ctxt,
 927                                                 be_encoded_q_len(mccq->len));
 928                 AMAP_SET_BITS(struct amap_mcc_context_be, cq_id, ctxt, cq->id);
 929         }
 930
 931         /* Subscribe to Link State and Group 5 Events(bits 1 and 5 set) */
 932         req->async_event_bitmap[0] = cpu_to_le32(0x00000022);
 933         be_dws_cpu_to_le(ctxt, sizeof(req->context));
 934
 935         be_cmd_page_addrs_prepare(req->pages, ARRAY_SIZE(req->pages), q_mem);
 936
 937         status = be_mbox_notify_wait(adapter);
 938         if (!status) {
 939                 struct be_cmd_resp_mcc_create *resp = embedded_payload(wrb);
 940                 mccq->id = le16_to_cpu(resp->id);
 941                 mccq->created = true;
 942         }
 943         mutex_unlock(&adapter->mbox_lock);
 944
 945         return status;
 946 }
 947
 948 int be_cmd_mccq_org_create(struct be_adapter *adapter,
 949                         struct be_queue_info *mccq,
 950                         struct be_queue_info *cq)
 951 {
 952         struct be_mcc_wrb *wrb;
 953         struct be_cmd_req_mcc_create *req;
 954         struct be_dma_mem *q_mem = &mccq->dma_mem;
 955         void *ctxt;
 956         int status;
 957
 958         if (mutex_lock_interruptible(&adapter->mbox_lock))
 959                 return -1;
 960
 961         wrb = wrb_from_mbox(adapter);
 962         req = embedded_payload(wrb);
 963         ctxt = &req->context;
 964
 965         be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
 966                         OPCODE_COMMON_MCC_CREATE, sizeof(*req), wrb, NULL);
 967
 968         req->num_pages = cpu_to_le16(PAGES_4K_SPANNED(q_mem->va, q_mem->size));
 969
 970         AMAP_SET_BITS(struct amap_mcc_context_be, valid, ctxt, 1);
 971         AMAP_SET_BITS(struct amap_mcc_context_be, ring_size, ctxt,
 972                         be_encoded_q_len(mccq->len));
 973         AMAP_SET_BITS(struct amap_mcc_context_be, cq_id, ctxt, cq->id);
 974
 975         be_dws_cpu_to_le(ctxt, sizeof(req->context));
 976
 977         be_cmd_page_addrs_prepare(req->pages, ARRAY_SIZE(req->pages), q_mem);
 978
 979         status = be_mbox_notify_wait(adapter);
 980         if (!status) {
 981                 struct be_cmd_resp_mcc_create *resp = embedded_payload(wrb);
 982                 mccq->id = le16_to_cpu(resp->id);
 983                 mccq->created = true;
 984         }
 985
 986         mutex_unlock(&adapter->mbox_lock);
 987         return status;
 988 }
 989
 990 int be_cmd_mccq_create(struct be_adapter *adapter,
 991                         struct be_queue_info *mccq,
 992                         struct be_queue_info *cq)
 993 {
 994         int status;
 995
 996         status = be_cmd_mccq_ext_create(adapter, mccq, cq);
 997         if (status && !lancer_chip(adapter)) {
 998                 dev_warn(&adapter->pdev->dev, "Upgrade to F/W ver 2.102.235.0 "
 999                         "or newer to avoid conflicting priorities between NIC "
1000                         "and FCoE traffic");
1001                 status = be_cmd_mccq_org_create(adapter, mccq, cq);
1002         }
1003         return status;
1004 }
1005
1006 int be_cmd_txq_create(struct be_adapter *adapter,
1007                         struct be_queue_info *txq,
1008                         struct be_queue_info *cq)
1009 {
1010         struct be_mcc_wrb *wrb;
1011         struct be_cmd_req_eth_tx_create *req;
1012         struct be_dma_mem *q_mem = &txq->dma_mem;
1013         void *ctxt;
1014         int status;
1015
1016         spin_lock_bh(&adapter->mcc_lock);
1017
1018         wrb = wrb_from_mccq(adapter);
1019         if (!wrb) {
1020                 status = -EBUSY;
1021                 goto err;
1022         }
1023
1024         req = embedded_payload(wrb);
1025         ctxt = &req->context;
1026
1027         be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_ETH,
1028                 OPCODE_ETH_TX_CREATE, sizeof(*req), wrb, NULL);
1029
1030         if (lancer_chip(adapter)) {
1031                 req->hdr.version = 1;
1032                 AMAP_SET_BITS(struct amap_tx_context, if_id, ctxt,
1033                                         adapter->if_handle);
1034         }
1035
1036         req->num_pages = PAGES_4K_SPANNED(q_mem->va, q_mem->size);
1037         req->ulp_num = BE_ULP1_NUM;
1038         req->type = BE_ETH_TX_RING_TYPE_STANDARD;
1039
1040         AMAP_SET_BITS(struct amap_tx_context, tx_ring_size, ctxt,
1041                 be_encoded_q_len(txq->len));
1042         AMAP_SET_BITS(struct amap_tx_context, ctx_valid, ctxt, 1);
1043         AMAP_SET_BITS(struct amap_tx_context, cq_id_send, ctxt, cq->id);
1044
1045         be_dws_cpu_to_le(ctxt, sizeof(req->context));
1046
1047         be_cmd_page_addrs_prepare(req->pages, ARRAY_SIZE(req->pages), q_mem);
1048
1049         status = be_mcc_notify_wait(adapter);
1050         if (!status) {
1051                 struct be_cmd_resp_eth_tx_create *resp = embedded_payload(wrb);
1052                 txq->id = le16_to_cpu(resp->cid);
1053                 txq->created = true;
1054         }
1055
1056 err:
1057         spin_unlock_bh(&adapter->mcc_lock);
1058
1059         return status;
1060 }
1061
1062 /* Uses MCC */
1063 int be_cmd_rxq_create(struct be_adapter *adapter,
1064                 struct be_queue_info *rxq, u16 cq_id, u16 frag_size,
1065                 u32 if_id, u32 rss, u8 *rss_id)
1066 {
1067         struct be_mcc_wrb *wrb;
1068         struct be_cmd_req_eth_rx_create *req;
1069         struct be_dma_mem *q_mem = &rxq->dma_mem;
1070         int status;
1071
1072         spin_lock_bh(&adapter->mcc_lock);
1073
1074         wrb = wrb_from_mccq(adapter);
1075         if (!wrb) {
1076                 status = -EBUSY;
1077                 goto err;
1078         }
1079         req = embedded_payload(wrb);
1080
1081         be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_ETH,
1082                                 OPCODE_ETH_RX_CREATE, sizeof(*req), wrb, NULL);
1083
1084         req->cq_id = cpu_to_le16(cq_id);
1085         req->frag_size = fls(frag_size) - 1;
1086         req->num_pages = 2;
1087         be_cmd_page_addrs_prepare(req->pages, ARRAY_SIZE(req->pages), q_mem);
1088         req->interface_id = cpu_to_le32(if_id);
1089         req->max_frame_size = cpu_to_le16(BE_MAX_JUMBO_FRAME_SIZE);
1090         req->rss_queue = cpu_to_le32(rss);
1091
1092         status = be_mcc_notify_wait(adapter);
1093         if (!status) {
1094                 struct be_cmd_resp_eth_rx_create *resp = embedded_payload(wrb);
1095                 rxq->id = le16_to_cpu(resp->id);
1096                 rxq->created = true;
1097                 *rss_id = resp->rss_id;
1098         }
1099
1100 err:
1101         spin_unlock_bh(&adapter->mcc_lock);
1102         return status;
1103 }
1104
1105 /* Generic destroyer function for all types of queues
1106  * Uses Mbox
1107  */
1108 int be_cmd_q_destroy(struct be_adapter *adapter, struct be_queue_info *q,
1109                 int queue_type)
1110 {
1111         struct be_mcc_wrb *wrb;
1112         struct be_cmd_req_q_destroy *req;
1113         u8 subsys = 0, opcode = 0;
1114         int status;
1115
1116         if (mutex_lock_interruptible(&adapter->mbox_lock))
1117                 return -1;
1118
1119         wrb = wrb_from_mbox(adapter);
1120         req = embedded_payload(wrb);
1121
1122         switch (queue_type) {
1123         case QTYPE_EQ:
1124                 subsys = CMD_SUBSYSTEM_COMMON;
1125                 opcode = OPCODE_COMMON_EQ_DESTROY;
1126                 break;
1127         case QTYPE_CQ:
1128                 subsys = CMD_SUBSYSTEM_COMMON;
1129                 opcode = OPCODE_COMMON_CQ_DESTROY;
1130                 break;
1131         case QTYPE_TXQ:
1132                 subsys = CMD_SUBSYSTEM_ETH;
1133                 opcode = OPCODE_ETH_TX_DESTROY;
1134                 break;
1135         case QTYPE_RXQ:
1136                 subsys = CMD_SUBSYSTEM_ETH;
1137                 opcode = OPCODE_ETH_RX_DESTROY;
1138                 break;
1139         case QTYPE_MCCQ:
1140                 subsys = CMD_SUBSYSTEM_COMMON;
1141                 opcode = OPCODE_COMMON_MCC_DESTROY;
1142                 break;
1143         default:
1144                 BUG();
1145         }
1146
1147         be_wrb_cmd_hdr_prepare(&req->hdr, subsys, opcode, sizeof(*req), wrb,
1148                                 NULL);
1149         req->id = cpu_to_le16(q->id);
1150
1151         status = be_mbox_notify_wait(adapter);
1152         if (!status)
1153                 q->created = false;
1154
1155         mutex_unlock(&adapter->mbox_lock);
1156         return status;
1157 }
1158
1159 /* Uses MCC */
1160 int be_cmd_rxq_destroy(struct be_adapter *adapter, struct be_queue_info *q)
1161 {
1162         struct be_mcc_wrb *wrb;
1163         struct be_cmd_req_q_destroy *req;
1164         int status;
1165
1166         spin_lock_bh(&adapter->mcc_lock);
1167
1168         wrb = wrb_from_mccq(adapter);
1169         if (!wrb) {
1170                 status = -EBUSY;
1171                 goto err;
1172         }
1173         req = embedded_payload(wrb);
1174
1175         be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_ETH,
1176                         OPCODE_ETH_RX_DESTROY, sizeof(*req), wrb, NULL);
1177         req->id = cpu_to_le16(q->id);
1178
1179         status = be_mcc_notify_wait(adapter);
1180         if (!status)
1181                 q->created = false;
1182
1183 err:
1184         spin_unlock_bh(&adapter->mcc_lock);
1185         return status;
1186 }
1187
1188 /* Create an rx filtering policy configuration on an i/f
1189  * Uses MCCQ
1190  */
1191 int be_cmd_if_create(struct be_adapter *adapter, u32 cap_flags, u32 en_flags,
1192                      u32 *if_handle, u32 domain)
1193 {
1194         struct be_mcc_wrb *wrb;
1195         struct be_cmd_req_if_create *req;
1196         int status;
1197
1198         spin_lock_bh(&adapter->mcc_lock);
1199
1200         wrb = wrb_from_mccq(adapter);
1201         if (!wrb) {
1202                 status = -EBUSY;
1203                 goto err;
1204         }
1205         req = embedded_payload(wrb);
1206
1207         be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
1208                 OPCODE_COMMON_NTWK_INTERFACE_CREATE, sizeof(*req), wrb, NULL);
1209         req->hdr.domain = domain;
1210         req->capability_flags = cpu_to_le32(cap_flags);
1211         req->enable_flags = cpu_to_le32(en_flags);
1212
1213         req->pmac_invalid = true;
1214
1215         status = be_mcc_notify_wait(adapter);
1216         if (!status) {
1217                 struct be_cmd_resp_if_create *resp = embedded_payload(wrb);
1218                 *if_handle = le32_to_cpu(resp->interface_id);
1219         }
1220
1221 err:
1222         spin_unlock_bh(&adapter->mcc_lock);
1223         return status;
1224 }
1225
1226 /* Uses MCCQ */
1227 int be_cmd_if_destroy(struct be_adapter *adapter, int interface_id, u32 domain)
1228 {
1229         struct be_mcc_wrb *wrb;
1230         struct be_cmd_req_if_destroy *req;
1231         int status;
1232
1233         if (interface_id == -1)
1234                 return 0;
1235
1236         spin_lock_bh(&adapter->mcc_lock);
1237
1238         wrb = wrb_from_mccq(adapter);
1239         if (!wrb) {
1240                 status = -EBUSY;
1241                 goto err;
1242         }
1243         req = embedded_payload(wrb);
1244
1245         be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
1246                 OPCODE_COMMON_NTWK_INTERFACE_DESTROY, sizeof(*req), wrb, NULL);
1247         req->hdr.domain = domain;
1248         req->interface_id = cpu_to_le32(interface_id);
1249
1250         status = be_mcc_notify_wait(adapter);
1251 err:
1252         spin_unlock_bh(&adapter->mcc_lock);
1253         return status;
1254 }
1255
1256 /* Get stats is a non embedded command: the request is not embedded inside
1257  * WRB but is a separate dma memory block
1258  * Uses asynchronous MCC
1259  */
1260 int be_cmd_get_stats(struct be_adapter *adapter, struct be_dma_mem *nonemb_cmd)
1261 {
1262         struct be_mcc_wrb *wrb;
1263         struct be_cmd_req_hdr *hdr;
1264         int status = 0;
1265
1266         spin_lock_bh(&adapter->mcc_lock);
1267
1268         wrb = wrb_from_mccq(adapter);
1269         if (!wrb) {
1270                 status = -EBUSY;
1271                 goto err;
1272         }
1273         hdr = nonemb_cmd->va;
1274
1275         be_wrb_cmd_hdr_prepare(hdr, CMD_SUBSYSTEM_ETH,
1276                 OPCODE_ETH_GET_STATISTICS, nonemb_cmd->size, wrb, nonemb_cmd);
1277
1278         if (adapter->generation == BE_GEN3)
1279                 hdr->version = 1;
1280
1281         be_mcc_notify(adapter);
1282         adapter->stats_cmd_sent = true;
1283
1284 err:
1285         spin_unlock_bh(&adapter->mcc_lock);
1286         return status;
1287 }
1288
1289 /* Lancer Stats */
1290 int lancer_cmd_get_pport_stats(struct be_adapter *adapter,
1291                                 struct be_dma_mem *nonemb_cmd)
1292 {
1293
1294         struct be_mcc_wrb *wrb;
1295         struct lancer_cmd_req_pport_stats *req;
1296         int status = 0;
1297
1298         spin_lock_bh(&adapter->mcc_lock);
1299
1300         wrb = wrb_from_mccq(adapter);
1301         if (!wrb) {
1302                 status = -EBUSY;
1303                 goto err;
1304         }
1305         req = nonemb_cmd->va;
1306
1307         be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_ETH,
1308                         OPCODE_ETH_GET_PPORT_STATS, nonemb_cmd->size, wrb,
1309                         nonemb_cmd);
1310
1311         req->cmd_params.params.pport_num = cpu_to_le16(adapter->hba_port_num);
1312         req->cmd_params.params.reset_stats = 0;
1313
1314         be_mcc_notify(adapter);
1315         adapter->stats_cmd_sent = true;
1316
1317 err:
1318         spin_unlock_bh(&adapter->mcc_lock);
1319         return status;
1320 }
1321
1322 /* Uses synchronous mcc */
1323 int be_cmd_link_status_query(struct be_adapter *adapter, u8 *mac_speed,
1324                              u16 *link_speed, u8 *link_status, u32 dom)
1325 {
1326         struct be_mcc_wrb *wrb;
1327         struct be_cmd_req_link_status *req;
1328         int status;
1329
1330         spin_lock_bh(&adapter->mcc_lock);
1331
1332         if (link_status)
1333                 *link_status = LINK_DOWN;
1334
1335         wrb = wrb_from_mccq(adapter);
1336         if (!wrb) {
1337                 status = -EBUSY;
1338                 goto err;
1339         }
1340         req = embedded_payload(wrb);
1341
1342         be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
1343                 OPCODE_COMMON_NTWK_LINK_STATUS_QUERY, sizeof(*req), wrb, NULL);
1344
1345         if (adapter->generation == BE_GEN3 || lancer_chip(adapter))
1346                 req->hdr.version = 1;
1347
1348         req->hdr.domain = dom;
1349
1350         status = be_mcc_notify_wait(adapter);
1351         if (!status) {
1352                 struct be_cmd_resp_link_status *resp = embedded_payload(wrb);
1353                 if (resp->mac_speed != PHY_LINK_SPEED_ZERO) {
1354                         if (link_speed)
1355                                 *link_speed = le16_to_cpu(resp->link_speed);
1356                         if (mac_speed)
1357                                 *mac_speed = resp->mac_speed;
1358                 }
1359                 if (link_status)
1360                         *link_status = resp->logical_link_status;
1361         }
1362
1363 err:
1364         spin_unlock_bh(&adapter->mcc_lock);
1365         return status;
1366 }
1367
1368 /* Uses synchronous mcc */
1369 int be_cmd_get_die_temperature(struct be_adapter *adapter)
1370 {
1371         struct be_mcc_wrb *wrb;
1372         struct be_cmd_req_get_cntl_addnl_attribs *req;
1373         int status;
1374
1375         spin_lock_bh(&adapter->mcc_lock);
1376
1377         wrb = wrb_from_mccq(adapter);
1378         if (!wrb) {
1379                 status = -EBUSY;
1380                 goto err;
1381         }
1382         req = embedded_payload(wrb);
1383
1384         be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
1385                 OPCODE_COMMON_GET_CNTL_ADDITIONAL_ATTRIBUTES, sizeof(*req),
1386                 wrb, NULL);
1387
1388         be_mcc_notify(adapter);
1389
1390 err:
1391         spin_unlock_bh(&adapter->mcc_lock);
1392         return status;
1393 }
1394
1395 /* Uses synchronous mcc */
1396 int be_cmd_get_reg_len(struct be_adapter *adapter, u32 *log_size)
1397 {
1398         struct be_mcc_wrb *wrb;
1399         struct be_cmd_req_get_fat *req;
1400         int status;
1401
1402         spin_lock_bh(&adapter->mcc_lock);
1403
1404         wrb = wrb_from_mccq(adapter);
1405         if (!wrb) {
1406                 status = -EBUSY;
1407                 goto err;
1408         }
1409         req = embedded_payload(wrb);
1410
1411         be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
1412                 OPCODE_COMMON_MANAGE_FAT, sizeof(*req), wrb, NULL);
1413         req->fat_operation = cpu_to_le32(QUERY_FAT);
1414         status = be_mcc_notify_wait(adapter);
1415         if (!status) {
1416                 struct be_cmd_resp_get_fat *resp = embedded_payload(wrb);
1417                 if (log_size && resp->log_size)
1418                         *log_size = le32_to_cpu(resp->log_size) -
1419                                         sizeof(u32);
1420         }
1421 err:
1422         spin_unlock_bh(&adapter->mcc_lock);
1423         return status;
1424 }
1425
1426 void be_cmd_get_regs(struct be_adapter *adapter, u32 buf_len, void *buf)
1427 {
1428         struct be_dma_mem get_fat_cmd;
1429         struct be_mcc_wrb *wrb;
1430         struct be_cmd_req_get_fat *req;
1431         u32 offset = 0, total_size, buf_size,
1432                                 log_offset = sizeof(u32), payload_len;
1433         int status;
1434
1435         if (buf_len == 0)
1436                 return;
1437
1438         total_size = buf_len;
1439
1440         get_fat_cmd.size = sizeof(struct be_cmd_req_get_fat) + 60*1024;
1441         get_fat_cmd.va = pci_alloc_consistent(adapter->pdev,
1442                         get_fat_cmd.size,
1443                         &get_fat_cmd.dma);
1444         if (!get_fat_cmd.va) {
1445                 status = -ENOMEM;
1446                 dev_err(&adapter->pdev->dev,
1447                 "Memory allocation failure while retrieving FAT data\n");
1448                 return;
1449         }
1450
1451         spin_lock_bh(&adapter->mcc_lock);
1452
1453         while (total_size) {
1454                 buf_size = min(total_size, (u32)60*1024);
1455                 total_size -= buf_size;
1456
1457                 wrb = wrb_from_mccq(adapter);
1458                 if (!wrb) {
1459                         status = -EBUSY;
1460                         goto err;
1461                 }
1462                 req = get_fat_cmd.va;
1463
1464                 payload_len = sizeof(struct be_cmd_req_get_fat) + buf_size;
1465                 be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
1466                                 OPCODE_COMMON_MANAGE_FAT, payload_len, wrb,
1467                                 &get_fat_cmd);
1468
1469                 req->fat_operation = cpu_to_le32(RETRIEVE_FAT);
1470                 req->read_log_offset = cpu_to_le32(log_offset);
1471                 req->read_log_length = cpu_to_le32(buf_size);
1472                 req->data_buffer_size = cpu_to_le32(buf_size);
1473
1474                 status = be_mcc_notify_wait(adapter);
1475                 if (!status) {
1476                         struct be_cmd_resp_get_fat *resp = get_fat_cmd.va;
1477                         memcpy(buf + offset,
1478                                 resp->data_buffer,
1479                                 le32_to_cpu(resp->read_log_length));
1480                 } else {
1481                         dev_err(&adapter->pdev->dev, "FAT Table Retrieve error\n");
1482                         goto err;
1483                 }
1484                 offset += buf_size;
1485                 log_offset += buf_size;
1486         }
1487 err:
1488         pci_free_consistent(adapter->pdev, get_fat_cmd.size,
1489                         get_fat_cmd.va,
1490                         get_fat_cmd.dma);
1491         spin_unlock_bh(&adapter->mcc_lock);
1492 }
1493
1494 /* Uses synchronous mcc */
1495 int be_cmd_get_fw_ver(struct be_adapter *adapter, char *fw_ver,
1496                         char *fw_on_flash)
1497 {
1498         struct be_mcc_wrb *wrb;
1499         struct be_cmd_req_get_fw_version *req;
1500         int status;
1501
1502         spin_lock_bh(&adapter->mcc_lock);
1503
1504         wrb = wrb_from_mccq(adapter);
1505         if (!wrb) {
1506                 status = -EBUSY;
1507                 goto err;
1508         }
1509
1510         req = embedded_payload(wrb);
1511
1512         be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
1513                 OPCODE_COMMON_GET_FW_VERSION, sizeof(*req), wrb, NULL);
1514         status = be_mcc_notify_wait(adapter);
1515         if (!status) {
1516                 struct be_cmd_resp_get_fw_version *resp = embedded_payload(wrb);
1517                 strcpy(fw_ver, resp->firmware_version_string);
1518                 if (fw_on_flash)
1519                         strcpy(fw_on_flash, resp->fw_on_flash_version_string);
1520         }
1521 err:
1522         spin_unlock_bh(&adapter->mcc_lock);
1523         return status;
1524 }
1525
1526 /* set the EQ delay interval of an EQ to specified value
1527  * Uses async mcc
1528  */
1529 int be_cmd_modify_eqd(struct be_adapter *adapter, u32 eq_id, u32 eqd)
1530 {
1531         struct be_mcc_wrb *wrb;
1532         struct be_cmd_req_modify_eq_delay *req;
1533         int status = 0;
1534
1535         spin_lock_bh(&adapter->mcc_lock);
1536
1537         wrb = wrb_from_mccq(adapter);
1538         if (!wrb) {
1539                 status = -EBUSY;
1540                 goto err;
1541         }
1542         req = embedded_payload(wrb);
1543
1544         be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
1545                 OPCODE_COMMON_MODIFY_EQ_DELAY, sizeof(*req), wrb, NULL);
1546
1547         req->num_eq = cpu_to_le32(1);
1548         req->delay[0].eq_id = cpu_to_le32(eq_id);
1549         req->delay[0].phase = 0;
1550         req->delay[0].delay_multiplier = cpu_to_le32(eqd);
1551
1552         be_mcc_notify(adapter);
1553
1554 err:
1555         spin_unlock_bh(&adapter->mcc_lock);
1556         return status;
1557 }
1558
1559 /* Uses sycnhronous mcc */
1560 int be_cmd_vlan_config(struct be_adapter *adapter, u32 if_id, u16 *vtag_array,
1561                         u32 num, bool untagged, bool promiscuous)
1562 {
1563         struct be_mcc_wrb *wrb;
1564         struct be_cmd_req_vlan_config *req;
1565         int status;
1566
1567         spin_lock_bh(&adapter->mcc_lock);
1568
1569         wrb = wrb_from_mccq(adapter);
1570         if (!wrb) {
1571                 status = -EBUSY;
1572                 goto err;
1573         }
1574         req = embedded_payload(wrb);
1575
1576         be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
1577                 OPCODE_COMMON_NTWK_VLAN_CONFIG, sizeof(*req), wrb, NULL);
1578
1579         req->interface_id = if_id;
1580         req->promiscuous = promiscuous;
1581         req->untagged = untagged;
1582         req->num_vlan = num;
1583         if (!promiscuous) {
1584                 memcpy(req->normal_vlan, vtag_array,
1585                         req->num_vlan * sizeof(vtag_array[0]));
1586         }
1587
1588         status = be_mcc_notify_wait(adapter);
1589
1590 err:
1591         spin_unlock_bh(&adapter->mcc_lock);
1592         return status;
1593 }
1594
1595 int be_cmd_rx_filter(struct be_adapter *adapter, u32 flags, u32 value)
1596 {
1597         struct be_mcc_wrb *wrb;
1598         struct be_dma_mem *mem = &adapter->rx_filter;
1599         struct be_cmd_req_rx_filter *req = mem->va;
1600         int status;
1601
1602         spin_lock_bh(&adapter->mcc_lock);
1603
1604         wrb = wrb_from_mccq(adapter);
1605         if (!wrb) {
1606                 status = -EBUSY;
1607                 goto err;
1608         }
1609         memset(req, 0, sizeof(*req));
1610         be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
1611                                 OPCODE_COMMON_NTWK_RX_FILTER, sizeof(*req),
1612                                 wrb, mem);
1613
1614         req->if_id = cpu_to_le32(adapter->if_handle);
1615         if (flags & IFF_PROMISC) {
1616                 req->if_flags_mask = cpu_to_le32(BE_IF_FLAGS_PROMISCUOUS |
1617                                         BE_IF_FLAGS_VLAN_PROMISCUOUS);
1618                 if (value == ON)
1619                         req->if_flags = cpu_to_le32(BE_IF_FLAGS_PROMISCUOUS |
1620                                                 BE_IF_FLAGS_VLAN_PROMISCUOUS);
1621         } else if (flags & IFF_ALLMULTI) {
1622                 req->if_flags_mask = req->if_flags =
1623                                 cpu_to_le32(BE_IF_FLAGS_MCAST_PROMISCUOUS);
1624         } else {
1625                 struct netdev_hw_addr *ha;
1626                 int i = 0;
1627
1628                 req->if_flags_mask = req->if_flags =
1629                                 cpu_to_le32(BE_IF_FLAGS_MULTICAST);
1630
1631                 /* Reset mcast promisc mode if already set by setting mask
1632                  * and not setting flags field
1633                  */
1634                 if (!lancer_chip(adapter) || be_physfn(adapter))
1635                         req->if_flags_mask |=
1636                                 cpu_to_le32(BE_IF_FLAGS_MCAST_PROMISCUOUS);
1637
1638                 req->mcast_num = cpu_to_le32(netdev_mc_count(adapter->netdev));
1639                 netdev_for_each_mc_addr(ha, adapter->netdev)
1640                         memcpy(req->mcast_mac[i++].byte, ha->addr, ETH_ALEN);
1641         }
1642
1643         status = be_mcc_notify_wait(adapter);
1644 err:
1645         spin_unlock_bh(&adapter->mcc_lock);
1646         return status;
1647 }
1648
1649 /* Uses synchrounous mcc */
1650 int be_cmd_set_flow_control(struct be_adapter *adapter, u32 tx_fc, u32 rx_fc)
1651 {
1652         struct be_mcc_wrb *wrb;
1653         struct be_cmd_req_set_flow_control *req;
1654         int status;
1655
1656         spin_lock_bh(&adapter->mcc_lock);
1657
1658         wrb = wrb_from_mccq(adapter);
1659         if (!wrb) {
1660                 status = -EBUSY;
1661                 goto err;
1662         }
1663         req = embedded_payload(wrb);
1664
1665         be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
1666                 OPCODE_COMMON_SET_FLOW_CONTROL, sizeof(*req), wrb, NULL);
1667
1668         req->tx_flow_control = cpu_to_le16((u16)tx_fc);
1669         req->rx_flow_control = cpu_to_le16((u16)rx_fc);
1670
1671         status = be_mcc_notify_wait(adapter);
1672
1673 err:
1674         spin_unlock_bh(&adapter->mcc_lock);
1675         return status;
1676 }
1677
1678 /* Uses sycn mcc */
1679 int be_cmd_get_flow_control(struct be_adapter *adapter, u32 *tx_fc, u32 *rx_fc)
1680 {
1681         struct be_mcc_wrb *wrb;
1682         struct be_cmd_req_get_flow_control *req;
1683         int status;
1684
1685         spin_lock_bh(&adapter->mcc_lock);
1686
1687         wrb = wrb_from_mccq(adapter);
1688         if (!wrb) {
1689                 status = -EBUSY;
1690                 goto err;
1691         }
1692         req = embedded_payload(wrb);
1693
1694         be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
1695                 OPCODE_COMMON_GET_FLOW_CONTROL, sizeof(*req), wrb, NULL);
1696
1697         status = be_mcc_notify_wait(adapter);
1698         if (!status) {
1699                 struct be_cmd_resp_get_flow_control *resp =
1700                                                 embedded_payload(wrb);
1701                 *tx_fc = le16_to_cpu(resp->tx_flow_control);
1702                 *rx_fc = le16_to_cpu(resp->rx_flow_control);
1703         }
1704
1705 err:
1706         spin_unlock_bh(&adapter->mcc_lock);
1707         return status;
1708 }
1709
1710 /* Uses mbox */
1711 int be_cmd_query_fw_cfg(struct be_adapter *adapter, u32 *port_num,
1712                 u32 *mode, u32 *caps)
1713 {
1714         struct be_mcc_wrb *wrb;
1715         struct be_cmd_req_query_fw_cfg *req;
1716         int status;
1717
1718         if (mutex_lock_interruptible(&adapter->mbox_lock))
1719                 return -1;
1720
1721         wrb = wrb_from_mbox(adapter);
1722         req = embedded_payload(wrb);
1723
1724         be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
1725                 OPCODE_COMMON_QUERY_FIRMWARE_CONFIG, sizeof(*req), wrb, NULL);
1726
1727         status = be_mbox_notify_wait(adapter);
1728         if (!status) {
1729                 struct be_cmd_resp_query_fw_cfg *resp = embedded_payload(wrb);
1730                 *port_num = le32_to_cpu(resp->phys_port);
1731                 *mode = le32_to_cpu(resp->function_mode);
1732                 *caps = le32_to_cpu(resp->function_caps);
1733         }
1734
1735         mutex_unlock(&adapter->mbox_lock);
1736         return status;
1737 }
1738
1739 /* Uses mbox */
1740 int be_cmd_reset_function(struct be_adapter *adapter)
1741 {
1742         struct be_mcc_wrb *wrb;
1743         struct be_cmd_req_hdr *req;
1744         int status;
1745
1746         if (lancer_chip(adapter)) {
1747                 status = lancer_wait_ready(adapter);
1748                 if (!status) {
1749                         iowrite32(SLI_PORT_CONTROL_IP_MASK,
1750                                   adapter->db + SLIPORT_CONTROL_OFFSET);
1751                         status = lancer_test_and_set_rdy_state(adapter);
1752                 }
1753                 if (status) {
1754                         dev_err(&adapter->pdev->dev,
1755                                 "Adapter in non recoverable error\n");
1756                 }
1757                 return status;
1758         }
1759
1760         if (mutex_lock_interruptible(&adapter->mbox_lock))
1761                 return -1;
1762
1763         wrb = wrb_from_mbox(adapter);
1764         req = embedded_payload(wrb);
1765
1766         be_wrb_cmd_hdr_prepare(req, CMD_SUBSYSTEM_COMMON,
1767                 OPCODE_COMMON_FUNCTION_RESET, sizeof(*req), wrb, NULL);
1768
1769         status = be_mbox_notify_wait(adapter);
1770
1771         mutex_unlock(&adapter->mbox_lock);
1772         return status;
1773 }
1774
1775 int be_cmd_rss_config(struct be_adapter *adapter, u8 *rsstable, u16 table_size)
1776 {
1777         struct be_mcc_wrb *wrb;
1778         struct be_cmd_req_rss_config *req;
1779         u32 myhash[10] = {0x15d43fa5, 0x2534685a, 0x5f87693a, 0x5668494e,
1780                         0x33cf6a53, 0x383334c6, 0x76ac4257, 0x59b242b2,
1781                         0x3ea83c02, 0x4a110304};
1782         int status;
1783
1784         if (mutex_lock_interruptible(&adapter->mbox_lock))
1785                 return -1;
1786
1787         wrb = wrb_from_mbox(adapter);
1788         req = embedded_payload(wrb);
1789
1790         be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_ETH,
1791                 OPCODE_ETH_RSS_CONFIG, sizeof(*req), wrb, NULL);
1792
1793         req->if_id = cpu_to_le32(adapter->if_handle);
1794         req->enable_rss = cpu_to_le16(RSS_ENABLE_TCP_IPV4 | RSS_ENABLE_IPV4 |
1795                                       RSS_ENABLE_TCP_IPV6 | RSS_ENABLE_IPV6);
1796
1797         if (lancer_chip(adapter) || skyhawk_chip(adapter)) {
1798                 req->hdr.version = 1;
1799                 req->enable_rss |= cpu_to_le16(RSS_ENABLE_UDP_IPV4 |
1800                                                RSS_ENABLE_UDP_IPV6);
1801         }
1802
1803         req->cpu_table_size_log2 = cpu_to_le16(fls(table_size) - 1);
1804         memcpy(req->cpu_table, rsstable, table_size);
1805         memcpy(req->hash, myhash, sizeof(myhash));
1806         be_dws_cpu_to_le(req->hash, sizeof(req->hash));
1807
1808         status = be_mbox_notify_wait(adapter);
1809
1810         mutex_unlock(&adapter->mbox_lock);
1811         return status;
1812 }
1813
1814 /* Uses sync mcc */
1815 int be_cmd_set_beacon_state(struct be_adapter *adapter, u8 port_num,
1816                         u8 bcn, u8 sts, u8 state)
1817 {
1818         struct be_mcc_wrb *wrb;
1819         struct be_cmd_req_enable_disable_beacon *req;
1820         int status;
1821
1822         spin_lock_bh(&adapter->mcc_lock);
1823
1824         wrb = wrb_from_mccq(adapter);
1825         if (!wrb) {
1826                 status = -EBUSY;
1827                 goto err;
1828         }
1829         req = embedded_payload(wrb);
1830
1831         be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
1832                 OPCODE_COMMON_ENABLE_DISABLE_BEACON, sizeof(*req), wrb, NULL);
1833
1834         req->port_num = port_num;
1835         req->beacon_state = state;
1836         req->beacon_duration = bcn;
1837         req->status_duration = sts;
1838
1839         status = be_mcc_notify_wait(adapter);
1840
1841 err:
1842         spin_unlock_bh(&adapter->mcc_lock);
1843         return status;
1844 }
1845
1846 /* Uses sync mcc */
1847 int be_cmd_get_beacon_state(struct be_adapter *adapter, u8 port_num, u32 *state)
1848 {
1849         struct be_mcc_wrb *wrb;
1850         struct be_cmd_req_get_beacon_state *req;
1851         int status;
1852
1853         spin_lock_bh(&adapter->mcc_lock);
1854
1855         wrb = wrb_from_mccq(adapter);
1856         if (!wrb) {
1857                 status = -EBUSY;
1858                 goto err;
1859         }
1860         req = embedded_payload(wrb);
1861
1862         be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
1863                 OPCODE_COMMON_GET_BEACON_STATE, sizeof(*req), wrb, NULL);
1864
1865         req->port_num = port_num;
1866
1867         status = be_mcc_notify_wait(adapter);
1868         if (!status) {
1869                 struct be_cmd_resp_get_beacon_state *resp =
1870                                                 embedded_payload(wrb);
1871                 *state = resp->beacon_state;
1872         }
1873
1874 err:
1875         spin_unlock_bh(&adapter->mcc_lock);
1876         return status;
1877 }
1878
1879 int lancer_cmd_write_object(struct be_adapter *adapter, struct be_dma_mem *cmd,
1880                             u32 data_size, u32 data_offset,
1881                             const char *obj_name, u32 *data_written,
1882                             u8 *change_status, u8 *addn_status)
1883 {
1884         struct be_mcc_wrb *wrb;
1885         struct lancer_cmd_req_write_object *req;
1886         struct lancer_cmd_resp_write_object *resp;
1887         void *ctxt = NULL;
1888         int status;
1889
1890         spin_lock_bh(&adapter->mcc_lock);
1891         adapter->flash_status = 0;
1892
1893         wrb = wrb_from_mccq(adapter);
1894         if (!wrb) {
1895                 status = -EBUSY;
1896                 goto err_unlock;
1897         }
1898
1899         req = embedded_payload(wrb);
1900
1901         be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
1902                                 OPCODE_COMMON_WRITE_OBJECT,
1903                                 sizeof(struct lancer_cmd_req_write_object), wrb,
1904                                 NULL);
1905
1906         ctxt = &req->context;
1907         AMAP_SET_BITS(struct amap_lancer_write_obj_context,
1908                         write_length, ctxt, data_size);
1909
1910         if (data_size == 0)
1911                 AMAP_SET_BITS(struct amap_lancer_write_obj_context,
1912                                 eof, ctxt, 1);
1913         else
1914                 AMAP_SET_BITS(struct amap_lancer_write_obj_context,
1915                                 eof, ctxt, 0);
1916
1917         be_dws_cpu_to_le(ctxt, sizeof(req->context));
1918         req->write_offset = cpu_to_le32(data_offset);
1919         strcpy(req->object_name, obj_name);
1920         req->descriptor_count = cpu_to_le32(1);
1921         req->buf_len = cpu_to_le32(data_size);
1922         req->addr_low = cpu_to_le32((cmd->dma +
1923                                 sizeof(struct lancer_cmd_req_write_object))
1924                                 & 0xFFFFFFFF);
1925         req->addr_high = cpu_to_le32(upper_32_bits(cmd->dma +
1926                                 sizeof(struct lancer_cmd_req_write_object)));
1927
1928         be_mcc_notify(adapter);
1929         spin_unlock_bh(&adapter->mcc_lock);
1930
1931         if (!wait_for_completion_timeout(&adapter->flash_compl,
1932                                          msecs_to_jiffies(30000)))
1933                 status = -1;
1934         else
1935                 status = adapter->flash_status;
1936
1937         resp = embedded_payload(wrb);
1938         if (!status) {
1939                 *data_written = le32_to_cpu(resp->actual_write_len);
1940                 *change_status = resp->change_status;
1941         } else {
1942                 *addn_status = resp->additional_status;
1943         }
1944
1945         return status;
1946
1947 err_unlock:
1948         spin_unlock_bh(&adapter->mcc_lock);
1949         return status;
1950 }
1951
1952 int lancer_cmd_read_object(struct be_adapter *adapter, struct be_dma_mem *cmd,
1953                 u32 data_size, u32 data_offset, const char *obj_name,
1954                 u32 *data_read, u32 *eof, u8 *addn_status)
1955 {
1956         struct be_mcc_wrb *wrb;
1957         struct lancer_cmd_req_read_object *req;
1958         struct lancer_cmd_resp_read_object *resp;
1959         int status;
1960
1961         spin_lock_bh(&adapter->mcc_lock);
1962
1963         wrb = wrb_from_mccq(adapter);
1964         if (!wrb) {
1965                 status = -EBUSY;
1966                 goto err_unlock;
1967         }
1968
1969         req = embedded_payload(wrb);
1970
1971         be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
1972                         OPCODE_COMMON_READ_OBJECT,
1973                         sizeof(struct lancer_cmd_req_read_object), wrb,
1974                         NULL);
1975
1976         req->desired_read_len = cpu_to_le32(data_size);
1977         req->read_offset = cpu_to_le32(data_offset);
1978         strcpy(req->object_name, obj_name);
1979         req->descriptor_count = cpu_to_le32(1);
1980         req->buf_len = cpu_to_le32(data_size);
1981         req->addr_low = cpu_to_le32((cmd->dma & 0xFFFFFFFF));
1982         req->addr_high = cpu_to_le32(upper_32_bits(cmd->dma));
1983
1984         status = be_mcc_notify_wait(adapter);
1985
1986         resp = embedded_payload(wrb);
1987         if (!status) {
1988                 *data_read = le32_to_cpu(resp->actual_read_len);
1989                 *eof = le32_to_cpu(resp->eof);
1990         } else {
1991                 *addn_status = resp->additional_status;
1992         }
1993
1994 err_unlock:
1995         spin_unlock_bh(&adapter->mcc_lock);
1996         return status;
1997 }
1998
1999 int be_cmd_write_flashrom(struct be_adapter *adapter, struct be_dma_mem *cmd,
2000                         u32 flash_type, u32 flash_opcode, u32 buf_size)
2001 {
2002         struct be_mcc_wrb *wrb;
2003         struct be_cmd_write_flashrom *req;
2004         int status;
2005
2006         spin_lock_bh(&adapter->mcc_lock);
2007         adapter->flash_status = 0;
2008
2009         wrb = wrb_from_mccq(adapter);
2010         if (!wrb) {
2011                 status = -EBUSY;
2012                 goto err_unlock;
2013         }
2014         req = cmd->va;
2015
2016         be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
2017                 OPCODE_COMMON_WRITE_FLASHROM, cmd->size, wrb, cmd);
2018
2019         req->params.op_type = cpu_to_le32(flash_type);
2020         req->params.op_code = cpu_to_le32(flash_opcode);
2021         req->params.data_buf_size = cpu_to_le32(buf_size);
2022
2023         be_mcc_notify(adapter);
2024         spin_unlock_bh(&adapter->mcc_lock);
2025
2026         if (!wait_for_completion_timeout(&adapter->flash_compl,
2027                         msecs_to_jiffies(40000)))
2028                 status = -1;
2029         else
2030                 status = adapter->flash_status;
2031
2032         return status;
2033
2034 err_unlock:
2035         spin_unlock_bh(&adapter->mcc_lock);
2036         return status;
2037 }
2038
2039 int be_cmd_get_flash_crc(struct be_adapter *adapter, u8 *flashed_crc,
2040                          int offset)
2041 {
2042         struct be_mcc_wrb *wrb;
2043         struct be_cmd_write_flashrom *req;
2044         int status;
2045
2046         spin_lock_bh(&adapter->mcc_lock);
2047
2048         wrb = wrb_from_mccq(adapter);
2049         if (!wrb) {
2050                 status = -EBUSY;
2051                 goto err;
2052         }
2053         req = embedded_payload(wrb);
2054
2055         be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
2056                 OPCODE_COMMON_READ_FLASHROM, sizeof(*req)+4, wrb, NULL);
2057
2058         req->params.op_type = cpu_to_le32(OPTYPE_REDBOOT);
2059         req->params.op_code = cpu_to_le32(FLASHROM_OPER_REPORT);
2060         req->params.offset = cpu_to_le32(offset);
2061         req->params.data_buf_size = cpu_to_le32(0x4);
2062
2063         status = be_mcc_notify_wait(adapter);
2064         if (!status)
2065                 memcpy(flashed_crc, req->params.data_buf, 4);
2066
2067 err:
2068         spin_unlock_bh(&adapter->mcc_lock);
2069         return status;
2070 }
2071
2072 int be_cmd_enable_magic_wol(struct be_adapter *adapter, u8 *mac,
2073                                 struct be_dma_mem *nonemb_cmd)
2074 {
2075         struct be_mcc_wrb *wrb;
2076         struct be_cmd_req_acpi_wol_magic_config *req;
2077         int status;
2078
2079         spin_lock_bh(&adapter->mcc_lock);
2080
2081         wrb = wrb_from_mccq(adapter);
2082         if (!wrb) {
2083                 status = -EBUSY;
2084                 goto err;
2085         }
2086         req = nonemb_cmd->va;
2087
2088         be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_ETH,
2089                 OPCODE_ETH_ACPI_WOL_MAGIC_CONFIG, sizeof(*req), wrb,
2090                 nonemb_cmd);
2091         memcpy(req->magic_mac, mac, ETH_ALEN);
2092
2093         status = be_mcc_notify_wait(adapter);
2094
2095 err:
2096         spin_unlock_bh(&adapter->mcc_lock);
2097         return status;
2098 }
2099
2100 int be_cmd_set_loopback(struct be_adapter *adapter, u8 port_num,
2101                         u8 loopback_type, u8 enable)
2102 {
2103         struct be_mcc_wrb *wrb;
2104         struct be_cmd_req_set_lmode *req;
2105         int status;
2106
2107         spin_lock_bh(&adapter->mcc_lock);
2108
2109         wrb = wrb_from_mccq(adapter);
2110         if (!wrb) {
2111                 status = -EBUSY;
2112                 goto err;
2113         }
2114
2115         req = embedded_payload(wrb);
2116
2117         be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_LOWLEVEL,
2118                         OPCODE_LOWLEVEL_SET_LOOPBACK_MODE, sizeof(*req), wrb,
2119                         NULL);
2120
2121         req->src_port = port_num;
2122         req->dest_port = port_num;
2123         req->loopback_type = loopback_type;
2124         req->loopback_state = enable;
2125
2126         status = be_mcc_notify_wait(adapter);
2127 err:
2128         spin_unlock_bh(&adapter->mcc_lock);
2129         return status;
2130 }
2131
2132 int be_cmd_loopback_test(struct be_adapter *adapter, u32 port_num,
2133                 u32 loopback_type, u32 pkt_size, u32 num_pkts, u64 pattern)
2134 {
2135         struct be_mcc_wrb *wrb;
2136         struct be_cmd_req_loopback_test *req;
2137         int status;
2138
2139         spin_lock_bh(&adapter->mcc_lock);
2140
2141         wrb = wrb_from_mccq(adapter);
2142         if (!wrb) {
2143                 status = -EBUSY;
2144                 goto err;
2145         }
2146
2147         req = embedded_payload(wrb);
2148
2149         be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_LOWLEVEL,
2150                         OPCODE_LOWLEVEL_LOOPBACK_TEST, sizeof(*req), wrb, NULL);
2151         req->hdr.timeout = cpu_to_le32(4);
2152
2153         req->pattern = cpu_to_le64(pattern);
2154         req->src_port = cpu_to_le32(port_num);
2155         req->dest_port = cpu_to_le32(port_num);
2156         req->pkt_size = cpu_to_le32(pkt_size);
2157         req->num_pkts = cpu_to_le32(num_pkts);
2158         req->loopback_type = cpu_to_le32(loopback_type);
2159
2160         status = be_mcc_notify_wait(adapter);
2161         if (!status) {
2162                 struct be_cmd_resp_loopback_test *resp = embedded_payload(wrb);
2163                 status = le32_to_cpu(resp->status);
2164         }
2165
2166 err:
2167         spin_unlock_bh(&adapter->mcc_lock);
2168         return status;
2169 }
2170
2171 int be_cmd_ddr_dma_test(struct be_adapter *adapter, u64 pattern,
2172                                 u32 byte_cnt, struct be_dma_mem *cmd)
2173 {
2174         struct be_mcc_wrb *wrb;
2175         struct be_cmd_req_ddrdma_test *req;
2176         int status;
2177         int i, j = 0;
2178
2179         spin_lock_bh(&adapter->mcc_lock);
2180
2181         wrb = wrb_from_mccq(adapter);
2182         if (!wrb) {
2183                 status = -EBUSY;
2184                 goto err;
2185         }
2186         req = cmd->va;
2187         be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_LOWLEVEL,
2188                         OPCODE_LOWLEVEL_HOST_DDR_DMA, cmd->size, wrb, cmd);
2189
2190         req->pattern = cpu_to_le64(pattern);
2191         req->byte_count = cpu_to_le32(byte_cnt);
2192         for (i = 0; i < byte_cnt; i++) {
2193                 req->snd_buff[i] = (u8)(pattern >> (j*8));
2194                 j++;
2195                 if (j > 7)
2196                         j = 0;
2197         }
2198
2199         status = be_mcc_notify_wait(adapter);
2200
2201         if (!status) {
2202                 struct be_cmd_resp_ddrdma_test *resp;
2203                 resp = cmd->va;
2204                 if ((memcmp(resp->rcv_buff, req->snd_buff, byte_cnt) != 0) ||
2205                                 resp->snd_err) {
2206                         status = -1;
2207                 }
2208         }
2209
2210 err:
2211         spin_unlock_bh(&adapter->mcc_lock);
2212         return status;
2213 }
2214
2215 int be_cmd_get_seeprom_data(struct be_adapter *adapter,
2216                                 struct be_dma_mem *nonemb_cmd)
2217 {
2218         struct be_mcc_wrb *wrb;
2219         struct be_cmd_req_seeprom_read *req;
2220         struct be_sge *sge;
2221         int status;
2222
2223         spin_lock_bh(&adapter->mcc_lock);
2224
2225         wrb = wrb_from_mccq(adapter);
2226         if (!wrb) {
2227                 status = -EBUSY;
2228                 goto err;
2229         }
2230         req = nonemb_cmd->va;
2231         sge = nonembedded_sgl(wrb);
2232
2233         be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
2234                         OPCODE_COMMON_SEEPROM_READ, sizeof(*req), wrb,
2235                         nonemb_cmd);
2236
2237         status = be_mcc_notify_wait(adapter);
2238
2239 err:
2240         spin_unlock_bh(&adapter->mcc_lock);
2241         return status;
2242 }
2243
2244 int be_cmd_get_phy_info(struct be_adapter *adapter)
2245 {
2246         struct be_mcc_wrb *wrb;
2247         struct be_cmd_req_get_phy_info *req;
2248         struct be_dma_mem cmd;
2249         int status;
2250
2251         spin_lock_bh(&adapter->mcc_lock);
2252
2253         wrb = wrb_from_mccq(adapter);
2254         if (!wrb) {
2255                 status = -EBUSY;
2256                 goto err;
2257         }
2258         cmd.size = sizeof(struct be_cmd_req_get_phy_info);
2259         cmd.va = pci_alloc_consistent(adapter->pdev, cmd.size,
2260                                         &cmd.dma);
2261         if (!cmd.va) {
2262                 dev_err(&adapter->pdev->dev, "Memory alloc failure\n");
2263                 status = -ENOMEM;
2264                 goto err;
2265         }
2266
2267         req = cmd.va;
2268
2269         be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
2270                         OPCODE_COMMON_GET_PHY_DETAILS, sizeof(*req),
2271                         wrb, &cmd);
2272
2273         status = be_mcc_notify_wait(adapter);
2274         if (!status) {
2275                 struct be_phy_info *resp_phy_info =
2276                                 cmd.va + sizeof(struct be_cmd_req_hdr);
2277                 adapter->phy.phy_type = le16_to_cpu(resp_phy_info->phy_type);
2278                 adapter->phy.interface_type =
2279                         le16_to_cpu(resp_phy_info->interface_type);
2280                 adapter->phy.auto_speeds_supported =
2281                         le16_to_cpu(resp_phy_info->auto_speeds_supported);
2282                 adapter->phy.fixed_speeds_supported =
2283                         le16_to_cpu(resp_phy_info->fixed_speeds_supported);
2284                 adapter->phy.misc_params =
2285                         le32_to_cpu(resp_phy_info->misc_params);
2286         }
2287         pci_free_consistent(adapter->pdev, cmd.size,
2288                                 cmd.va, cmd.dma);
2289 err:
2290         spin_unlock_bh(&adapter->mcc_lock);
2291         return status;
2292 }
2293
2294 int be_cmd_set_qos(struct be_adapter *adapter, u32 bps, u32 domain)
2295 {
2296         struct be_mcc_wrb *wrb;
2297         struct be_cmd_req_set_qos *req;
2298         int status;
2299
2300         spin_lock_bh(&adapter->mcc_lock);
2301
2302         wrb = wrb_from_mccq(adapter);
2303         if (!wrb) {
2304                 status = -EBUSY;
2305                 goto err;
2306         }
2307
2308         req = embedded_payload(wrb);
2309
2310         be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
2311                         OPCODE_COMMON_SET_QOS, sizeof(*req), wrb, NULL);
2312
2313         req->hdr.domain = domain;
2314         req->valid_bits = cpu_to_le32(BE_QOS_BITS_NIC);
2315         req->max_bps_nic = cpu_to_le32(bps);
2316
2317         status = be_mcc_notify_wait(adapter);
2318
2319 err:
2320         spin_unlock_bh(&adapter->mcc_lock);
2321         return status;
2322 }
2323
2324 int be_cmd_get_cntl_attributes(struct be_adapter *adapter)
2325 {
2326         struct be_mcc_wrb *wrb;
2327         struct be_cmd_req_cntl_attribs *req;
2328         struct be_cmd_resp_cntl_attribs *resp;
2329         int status;
2330         int payload_len = max(sizeof(*req), sizeof(*resp));
2331         struct mgmt_controller_attrib *attribs;
2332         struct be_dma_mem attribs_cmd;
2333
2334         memset(&attribs_cmd, 0, sizeof(struct be_dma_mem));
2335         attribs_cmd.size = sizeof(struct be_cmd_resp_cntl_attribs);
2336         attribs_cmd.va = pci_alloc_consistent(adapter->pdev, attribs_cmd.size,
2337                                                 &attribs_cmd.dma);
2338         if (!attribs_cmd.va) {
2339                 dev_err(&adapter->pdev->dev,
2340                                 "Memory allocation failure\n");
2341                 return -ENOMEM;
2342         }
2343
2344         if (mutex_lock_interruptible(&adapter->mbox_lock))
2345                 return -1;
2346
2347         wrb = wrb_from_mbox(adapter);
2348         if (!wrb) {
2349                 status = -EBUSY;
2350                 goto err;
2351         }
2352         req = attribs_cmd.va;
2353
2354         be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
2355                          OPCODE_COMMON_GET_CNTL_ATTRIBUTES, payload_len, wrb,
2356                         &attribs_cmd);
2357
2358         status = be_mbox_notify_wait(adapter);
2359         if (!status) {
2360                 attribs = attribs_cmd.va + sizeof(struct be_cmd_resp_hdr);
2361                 adapter->hba_port_num = attribs->hba_attribs.phy_port;
2362         }
2363
2364 err:
2365         mutex_unlock(&adapter->mbox_lock);
2366         pci_free_consistent(adapter->pdev, attribs_cmd.size, attribs_cmd.va,
2367                                         attribs_cmd.dma);
2368         return status;
2369 }
2370
2371 /* Uses mbox */
2372 int be_cmd_req_native_mode(struct be_adapter *adapter)
2373 {
2374         struct be_mcc_wrb *wrb;
2375         struct be_cmd_req_set_func_cap *req;
2376         int status;
2377
2378         if (mutex_lock_interruptible(&adapter->mbox_lock))
2379                 return -1;
2380
2381         wrb = wrb_from_mbox(adapter);
2382         if (!wrb) {
2383                 status = -EBUSY;
2384                 goto err;
2385         }
2386
2387         req = embedded_payload(wrb);
2388
2389         be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
2390                 OPCODE_COMMON_SET_DRIVER_FUNCTION_CAP, sizeof(*req), wrb, NULL);
2391
2392         req->valid_cap_flags = cpu_to_le32(CAPABILITY_SW_TIMESTAMPS |
2393                                 CAPABILITY_BE3_NATIVE_ERX_API);
2394         req->cap_flags = cpu_to_le32(CAPABILITY_BE3_NATIVE_ERX_API);
2395
2396         status = be_mbox_notify_wait(adapter);
2397         if (!status) {
2398                 struct be_cmd_resp_set_func_cap *resp = embedded_payload(wrb);
2399                 adapter->be3_native = le32_to_cpu(resp->cap_flags) &
2400                                         CAPABILITY_BE3_NATIVE_ERX_API;
2401         }
2402 err:
2403         mutex_unlock(&adapter->mbox_lock);
2404         return status;
2405 }
2406
2407 /* Uses synchronous MCCQ */
2408 int be_cmd_get_mac_from_list(struct be_adapter *adapter, u8 *mac,
2409                              bool *pmac_id_active, u32 *pmac_id, u8 domain)
2410 {
2411         struct be_mcc_wrb *wrb;
2412         struct be_cmd_req_get_mac_list *req;
2413         int status;
2414         int mac_count;
2415         struct be_dma_mem get_mac_list_cmd;
2416         int i;
2417
2418         memset(&get_mac_list_cmd, 0, sizeof(struct be_dma_mem));
2419         get_mac_list_cmd.size = sizeof(struct be_cmd_resp_get_mac_list);
2420         get_mac_list_cmd.va = pci_alloc_consistent(adapter->pdev,
2421                         get_mac_list_cmd.size,
2422                         &get_mac_list_cmd.dma);
2423
2424         if (!get_mac_list_cmd.va) {
2425                 dev_err(&adapter->pdev->dev,
2426                                 "Memory allocation failure during GET_MAC_LIST\n");
2427                 return -ENOMEM;
2428         }
2429
2430         spin_lock_bh(&adapter->mcc_lock);
2431
2432         wrb = wrb_from_mccq(adapter);
2433         if (!wrb) {
2434                 status = -EBUSY;
2435                 goto out;
2436         }
2437
2438         req = get_mac_list_cmd.va;
2439
2440         be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
2441                                 OPCODE_COMMON_GET_MAC_LIST, sizeof(*req),
2442                                 wrb, &get_mac_list_cmd);
2443
2444         req->hdr.domain = domain;
2445         req->mac_type = MAC_ADDRESS_TYPE_NETWORK;
2446         req->perm_override = 1;
2447
2448         status = be_mcc_notify_wait(adapter);
2449         if (!status) {
2450                 struct be_cmd_resp_get_mac_list *resp =
2451                                                 get_mac_list_cmd.va;
2452                 mac_count = resp->true_mac_count + resp->pseudo_mac_count;
2453                 /* Mac list returned could contain one or more active mac_ids
2454                  * or one or more true or pseudo permanant mac addresses.
2455                  * If an active mac_id is present, return first active mac_id
2456                  * found.
2457                  */
2458                 for (i = 0; i < mac_count; i++) {
2459                         struct get_list_macaddr *mac_entry;
2460                         u16 mac_addr_size;
2461                         u32 mac_id;
2462
2463                         mac_entry = &resp->macaddr_list[i];
2464                         mac_addr_size = le16_to_cpu(mac_entry->mac_addr_size);
2465                         /* mac_id is a 32 bit value and mac_addr size
2466                          * is 6 bytes
2467                          */
2468                         if (mac_addr_size == sizeof(u32)) {
2469                                 *pmac_id_active = true;
2470                                 mac_id = mac_entry->mac_addr_id.s_mac_id.mac_id;
2471                                 *pmac_id = le32_to_cpu(mac_id);
2472                                 goto out;
2473                         }
2474                 }
2475                 /* If no active mac_id found, return first mac addr */
2476                 *pmac_id_active = false;
2477                 memcpy(mac, resp->macaddr_list[0].mac_addr_id.macaddr,
2478                                                                 ETH_ALEN);
2479         }
2480
2481 out:
2482         spin_unlock_bh(&adapter->mcc_lock);
2483         pci_free_consistent(adapter->pdev, get_mac_list_cmd.size,
2484                         get_mac_list_cmd.va, get_mac_list_cmd.dma);
2485         return status;
2486 }
2487
2488 /* Uses synchronous MCCQ */
2489 int be_cmd_set_mac_list(struct be_adapter *adapter, u8 *mac_array,
2490                         u8 mac_count, u32 domain)
2491 {
2492         struct be_mcc_wrb *wrb;
2493         struct be_cmd_req_set_mac_list *req;
2494         int status;
2495         struct be_dma_mem cmd;
2496
2497         memset(&cmd, 0, sizeof(struct be_dma_mem));
2498         cmd.size = sizeof(struct be_cmd_req_set_mac_list);
2499         cmd.va = dma_alloc_coherent(&adapter->pdev->dev, cmd.size,
2500                         &cmd.dma, GFP_KERNEL);
2501         if (!cmd.va) {
2502                 dev_err(&adapter->pdev->dev, "Memory alloc failure\n");
2503                 return -ENOMEM;
2504         }
2505
2506         spin_lock_bh(&adapter->mcc_lock);
2507
2508         wrb = wrb_from_mccq(adapter);
2509         if (!wrb) {
2510                 status = -EBUSY;
2511                 goto err;
2512         }
2513
2514         req = cmd.va;
2515         be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
2516                                 OPCODE_COMMON_SET_MAC_LIST, sizeof(*req),
2517                                 wrb, &cmd);
2518
2519         req->hdr.domain = domain;
2520         req->mac_count = mac_count;
2521         if (mac_count)
2522                 memcpy(req->mac, mac_array, ETH_ALEN*mac_count);
2523
2524         status = be_mcc_notify_wait(adapter);
2525
2526 err:
2527         dma_free_coherent(&adapter->pdev->dev, cmd.size,
2528                                 cmd.va, cmd.dma);
2529         spin_unlock_bh(&adapter->mcc_lock);
2530         return status;
2531 }
2532
2533 int be_cmd_set_hsw_config(struct be_adapter *adapter, u16 pvid,
2534                         u32 domain, u16 intf_id)
2535 {
2536         struct be_mcc_wrb *wrb;
2537         struct be_cmd_req_set_hsw_config *req;
2538         void *ctxt;
2539         int status;
2540
2541         spin_lock_bh(&adapter->mcc_lock);
2542
2543         wrb = wrb_from_mccq(adapter);
2544         if (!wrb) {
2545                 status = -EBUSY;
2546                 goto err;
2547         }
2548
2549         req = embedded_payload(wrb);
2550         ctxt = &req->context;
2551
2552         be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
2553                         OPCODE_COMMON_SET_HSW_CONFIG, sizeof(*req), wrb, NULL);
2554
2555         req->hdr.domain = domain;
2556         AMAP_SET_BITS(struct amap_set_hsw_context, interface_id, ctxt, intf_id);
2557         if (pvid) {
2558                 AMAP_SET_BITS(struct amap_set_hsw_context, pvid_valid, ctxt, 1);
2559                 AMAP_SET_BITS(struct amap_set_hsw_context, pvid, ctxt, pvid);
2560         }
2561
2562         be_dws_cpu_to_le(req->context, sizeof(req->context));
2563         status = be_mcc_notify_wait(adapter);
2564
2565 err:
2566         spin_unlock_bh(&adapter->mcc_lock);
2567         return status;
2568 }
2569
2570 /* Get Hyper switch config */
2571 int be_cmd_get_hsw_config(struct be_adapter *adapter, u16 *pvid,
2572                         u32 domain, u16 intf_id)
2573 {
2574         struct be_mcc_wrb *wrb;
2575         struct be_cmd_req_get_hsw_config *req;
2576         void *ctxt;
2577         int status;
2578         u16 vid;
2579
2580         spin_lock_bh(&adapter->mcc_lock);
2581
2582         wrb = wrb_from_mccq(adapter);
2583         if (!wrb) {
2584                 status = -EBUSY;
2585                 goto err;
2586         }
2587
2588         req = embedded_payload(wrb);
2589         ctxt = &req->context;
2590
2591         be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
2592                         OPCODE_COMMON_GET_HSW_CONFIG, sizeof(*req), wrb, NULL);
2593
2594         req->hdr.domain = domain;
2595         AMAP_SET_BITS(struct amap_get_hsw_req_context, interface_id, ctxt,
2596                                                                 intf_id);
2597         AMAP_SET_BITS(struct amap_get_hsw_req_context, pvid_valid, ctxt, 1);
2598         be_dws_cpu_to_le(req->context, sizeof(req->context));
2599
2600         status = be_mcc_notify_wait(adapter);
2601         if (!status) {
2602                 struct be_cmd_resp_get_hsw_config *resp =
2603                                                 embedded_payload(wrb);
2604                 be_dws_le_to_cpu(&resp->context,
2605                                                 sizeof(resp->context));
2606                 vid = AMAP_GET_BITS(struct amap_get_hsw_resp_context,
2607                                                         pvid, &resp->context);
2608                 *pvid = le16_to_cpu(vid);
2609         }
2610
2611 err:
2612         spin_unlock_bh(&adapter->mcc_lock);
2613         return status;
2614 }
2615
2616 int be_cmd_get_acpi_wol_cap(struct be_adapter *adapter)
2617 {
2618         struct be_mcc_wrb *wrb;
2619         struct be_cmd_req_acpi_wol_magic_config_v1 *req;
2620         int status;
2621         int payload_len = sizeof(*req);
2622         struct be_dma_mem cmd;
2623
2624         memset(&cmd, 0, sizeof(struct be_dma_mem));
2625         cmd.size = sizeof(struct be_cmd_resp_acpi_wol_magic_config_v1);
2626         cmd.va = pci_alloc_consistent(adapter->pdev, cmd.size,
2627                                                &cmd.dma);
2628         if (!cmd.va) {
2629                 dev_err(&adapter->pdev->dev,
2630                                 "Memory allocation failure\n");
2631                 return -ENOMEM;
2632         }
2633
2634         if (mutex_lock_interruptible(&adapter->mbox_lock))
2635                 return -1;
2636
2637         wrb = wrb_from_mbox(adapter);
2638         if (!wrb) {
2639                 status = -EBUSY;
2640                 goto err;
2641         }
2642
2643         req = cmd.va;
2644
2645         be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_ETH,
2646                                OPCODE_ETH_ACPI_WOL_MAGIC_CONFIG,
2647                                payload_len, wrb, &cmd);
2648
2649         req->hdr.version = 1;
2650         req->query_options = BE_GET_WOL_CAP;
2651
2652         status = be_mbox_notify_wait(adapter);
2653         if (!status) {
2654                 struct be_cmd_resp_acpi_wol_magic_config_v1 *resp;
2655                 resp = (struct be_cmd_resp_acpi_wol_magic_config_v1 *) cmd.va;
2656
2657                 /* the command could succeed misleadingly on old f/w
2658                  * which is not aware of the V1 version. fake an error. */
2659                 if (resp->hdr.response_length < payload_len) {
2660                         status = -1;
2661                         goto err;
2662                 }
2663                 adapter->wol_cap = resp->wol_settings;
2664         }
2665 err:
2666         mutex_unlock(&adapter->mbox_lock);
2667         pci_free_consistent(adapter->pdev, cmd.size, cmd.va, cmd.dma);
2668         return status;
2669
2670 }
2671 int be_cmd_get_ext_fat_capabilites(struct be_adapter *adapter,
2672                                    struct be_dma_mem *cmd)
2673 {
2674         struct be_mcc_wrb *wrb;
2675         struct be_cmd_req_get_ext_fat_caps *req;
2676         int status;
2677
2678         if (mutex_lock_interruptible(&adapter->mbox_lock))
2679                 return -1;
2680
2681         wrb = wrb_from_mbox(adapter);
2682         if (!wrb) {
2683                 status = -EBUSY;
2684                 goto err;
2685         }
2686
2687         req = cmd->va;
2688         be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
2689                                OPCODE_COMMON_GET_EXT_FAT_CAPABILITES,
2690                                cmd->size, wrb, cmd);
2691         req->parameter_type = cpu_to_le32(1);
2692
2693         status = be_mbox_notify_wait(adapter);
2694 err:
2695         mutex_unlock(&adapter->mbox_lock);
2696         return status;
2697 }
2698
2699 int be_cmd_set_ext_fat_capabilites(struct be_adapter *adapter,
2700                                    struct be_dma_mem *cmd,
2701                                    struct be_fat_conf_params *configs)
2702 {
2703         struct be_mcc_wrb *wrb;
2704         struct be_cmd_req_set_ext_fat_caps *req;
2705         int status;
2706
2707         spin_lock_bh(&adapter->mcc_lock);
2708
2709         wrb = wrb_from_mccq(adapter);
2710         if (!wrb) {
2711                 status = -EBUSY;
2712                 goto err;
2713         }
2714
2715         req = cmd->va;
2716         memcpy(&req->set_params, configs, sizeof(struct be_fat_conf_params));
2717         be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
2718                                OPCODE_COMMON_SET_EXT_FAT_CAPABILITES,
2719                                cmd->size, wrb, cmd);
2720
2721         status = be_mcc_notify_wait(adapter);
2722 err:
2723         spin_unlock_bh(&adapter->mcc_lock);
2724         return status;
2725 }
2726
2727 int be_cmd_query_port_name(struct be_adapter *adapter, u8 *port_name)
2728 {
2729         struct be_mcc_wrb *wrb;
2730         struct be_cmd_req_get_port_name *req;
2731         int status;
2732
2733         if (!lancer_chip(adapter)) {
2734                 *port_name = adapter->hba_port_num + '0';
2735                 return 0;
2736         }
2737
2738         spin_lock_bh(&adapter->mcc_lock);
2739
2740         wrb = wrb_from_mccq(adapter);
2741         if (!wrb) {
2742                 status = -EBUSY;
2743                 goto err;
2744         }
2745
2746         req = embedded_payload(wrb);
2747
2748         be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
2749                                OPCODE_COMMON_GET_PORT_NAME, sizeof(*req), wrb,
2750                                NULL);
2751         req->hdr.version = 1;
2752
2753         status = be_mcc_notify_wait(adapter);
2754         if (!status) {
2755                 struct be_cmd_resp_get_port_name *resp = embedded_payload(wrb);
2756                 *port_name = resp->port_name[adapter->hba_port_num];
2757         } else {
2758                 *port_name = adapter->hba_port_num + '0';
2759         }
2760 err:
2761         spin_unlock_bh(&adapter->mcc_lock);
2762         return status;
2763 }
2764
2765 int be_roce_mcc_cmd(void *netdev_handle, void *wrb_payload,
2766                         int wrb_payload_size, u16 *cmd_status, u16 *ext_status)
2767 {
2768         struct be_adapter *adapter = netdev_priv(netdev_handle);
2769         struct be_mcc_wrb *wrb;
2770         struct be_cmd_req_hdr *hdr = (struct be_cmd_req_hdr *) wrb_payload;
2771         struct be_cmd_req_hdr *req;
2772         struct be_cmd_resp_hdr *resp;
2773         int status;
2774
2775         spin_lock_bh(&adapter->mcc_lock);
2776
2777         wrb = wrb_from_mccq(adapter);
2778         if (!wrb) {
2779                 status = -EBUSY;
2780                 goto err;
2781         }
2782         req = embedded_payload(wrb);
2783         resp = embedded_payload(wrb);
2784
2785         be_wrb_cmd_hdr_prepare(req, hdr->subsystem,
2786                                hdr->opcode, wrb_payload_size, wrb, NULL);
2787         memcpy(req, wrb_payload, wrb_payload_size);
2788         be_dws_cpu_to_le(req, wrb_payload_size);
2789
2790         status = be_mcc_notify_wait(adapter);
2791         if (cmd_status)
2792                 *cmd_status = (status & 0xffff);
2793         if (ext_status)
2794                 *ext_status = 0;
2795         memcpy(wrb_payload, resp, sizeof(*resp) + resp->response_length);
2796         be_dws_le_to_cpu(wrb_payload, sizeof(*resp) + resp->response_length);
2797 err:
2798         spin_unlock_bh(&adapter->mcc_lock);
2799         return status;
2800 }
2801 EXPORT_SYMBOL(be_roce_mcc_cmd);