drivers/net/ethernet/emulex/benet/be_cmds.c

   1 /*
   2  * Copyright (C) 2005 - 2011 Emulex
   3  * All rights reserved.
   4  *
   5  * This program is free software; you can redistribute it and/or
   6  * modify it under the terms of the GNU General Public License version 2
   7  * as published by the Free Software Foundation.  The full GNU General
   8  * Public License is included in this distribution in the file called COPYING.
   9  *
  10  * Contact Information:
  11  * linux-drivers@emulex.com
  12  *
  13  * Emulex
  14  * 3333 Susan Street
  15  * Costa Mesa, CA 92626
  16  */
  17
  18 #include "be.h"
  19 #include "be_cmds.h"
  20
  21 /* Must be a power of 2 or else MODULO will BUG_ON */
  22 static int be_get_temp_freq = 64;
  23
  24 static inline void *embedded_payload(struct be_mcc_wrb *wrb)
  25 {
  26         return wrb->payload.embedded_payload;
  27 }
  28
  29 static void be_mcc_notify(struct be_adapter *adapter)
  30 {
  31         struct be_queue_info *mccq = &adapter->mcc_obj.q;
  32         u32 val = 0;
  33
  34         if (adapter->eeh_err) {
  35                 dev_info(&adapter->pdev->dev,
  36                         "Error in Card Detected! Cannot issue commands\n");
  37                 return;
  38         }
  39
  40         val |= mccq->id & DB_MCCQ_RING_ID_MASK;
  41         val |= 1 << DB_MCCQ_NUM_POSTED_SHIFT;
  42
  43         wmb();
  44         iowrite32(val, adapter->db + DB_MCCQ_OFFSET);
  45 }
  46
  47 /* To check if valid bit is set, check the entire word as we don't know
  48  * the endianness of the data (old entry is host endian while a new entry is
  49  * little endian) */
  50 static inline bool be_mcc_compl_is_new(struct be_mcc_compl *compl)
  51 {
  52         if (compl->flags != 0) {
  53                 compl->flags = le32_to_cpu(compl->flags);
  54                 BUG_ON((compl->flags & CQE_FLAGS_VALID_MASK) == 0);
  55                 return true;
  56         } else {
  57                 return false;
  58         }
  59 }
  60
  61 /* Need to reset the entire word that houses the valid bit */
  62 static inline void be_mcc_compl_use(struct be_mcc_compl *compl)
  63 {
  64         compl->flags = 0;
  65 }
  66
  67 static int be_mcc_compl_process(struct be_adapter *adapter,
  68         struct be_mcc_compl *compl)
  69 {
  70         u16 compl_status, extd_status;
  71
  72         /* Just swap the status to host endian; mcc tag is opaquely copied
  73          * from mcc_wrb */
  74         be_dws_le_to_cpu(compl, 4);
  75
  76         compl_status = (compl->status >> CQE_STATUS_COMPL_SHIFT) &
  77                                 CQE_STATUS_COMPL_MASK;
  78
  79         if (((compl->tag0 == OPCODE_COMMON_WRITE_FLASHROM) ||
  80                 (compl->tag0 == OPCODE_COMMON_WRITE_OBJECT)) &&
  81                 (compl->tag1 == CMD_SUBSYSTEM_COMMON)) {
  82                 adapter->flash_status = compl_status;
  83                 complete(&adapter->flash_compl);
  84         }
  85
  86         if (compl_status == MCC_STATUS_SUCCESS) {
  87                 if (((compl->tag0 == OPCODE_ETH_GET_STATISTICS) ||
  88                          (compl->tag0 == OPCODE_ETH_GET_PPORT_STATS)) &&
  89                         (compl->tag1 == CMD_SUBSYSTEM_ETH)) {
  90                         be_parse_stats(adapter);
  91                         adapter->stats_cmd_sent = false;
  92                 }
  93                 if (compl->tag0 ==
  94                                 OPCODE_COMMON_GET_CNTL_ADDITIONAL_ATTRIBUTES) {
  95                         struct be_mcc_wrb *mcc_wrb =
  96                                 queue_index_node(&adapter->mcc_obj.q,
  97                                                 compl->tag1);
  98                         struct be_cmd_resp_get_cntl_addnl_attribs *resp =
  99                                 embedded_payload(mcc_wrb);
 100                         adapter->drv_stats.be_on_die_temperature =
 101                                 resp->on_die_temperature;
 102                 }
 103         } else {
 104                 if (compl->tag0 == OPCODE_COMMON_GET_CNTL_ADDITIONAL_ATTRIBUTES)
 105                         be_get_temp_freq = 0;
 106
 107                 if (compl_status == MCC_STATUS_NOT_SUPPORTED ||
 108                         compl_status == MCC_STATUS_ILLEGAL_REQUEST)
 109                         goto done;
 110
 111                 if (compl_status == MCC_STATUS_UNAUTHORIZED_REQUEST) {
 112                         dev_warn(&adapter->pdev->dev, "This domain(VM) is not "
 113                                 "permitted to execute this cmd (opcode %d)\n",
 114                                 compl->tag0);
 115                 } else {
 116                         extd_status = (compl->status >> CQE_STATUS_EXTD_SHIFT) &
 117                                         CQE_STATUS_EXTD_MASK;
 118                         dev_err(&adapter->pdev->dev, "Cmd (opcode %d) failed:"
 119                                 "status %d, extd-status %d\n",
 120                                 compl->tag0, compl_status, extd_status);
 121                 }
 122         }
 123 done:
 124         return compl_status;
 125 }
 126
 127 /* Link state evt is a string of bytes; no need for endian swapping */
 128 static void be_async_link_state_process(struct be_adapter *adapter,
 129                 struct be_async_event_link_state *evt)
 130 {
 131         be_link_status_update(adapter, evt->port_link_status);
 132 }
 133
 134 /* Grp5 CoS Priority evt */
 135 static void be_async_grp5_cos_priority_process(struct be_adapter *adapter,
 136                 struct be_async_event_grp5_cos_priority *evt)
 137 {
 138         if (evt->valid) {
 139                 adapter->vlan_prio_bmap = evt->available_priority_bmap;
 140                 adapter->recommended_prio &= ~VLAN_PRIO_MASK;
 141                 adapter->recommended_prio =
 142                         evt->reco_default_priority << VLAN_PRIO_SHIFT;
 143         }
 144 }
 145
 146 /* Grp5 QOS Speed evt */
 147 static void be_async_grp5_qos_speed_process(struct be_adapter *adapter,
 148                 struct be_async_event_grp5_qos_link_speed *evt)
 149 {
 150         if (evt->physical_port == adapter->port_num) {
 151                 /* qos_link_speed is in units of 10 Mbps */
 152                 adapter->link_speed = evt->qos_link_speed * 10;
 153         }
 154 }
 155
 156 /*Grp5 PVID evt*/
 157 static void be_async_grp5_pvid_state_process(struct be_adapter *adapter,
 158                 struct be_async_event_grp5_pvid_state *evt)
 159 {
 160         if (evt->enabled)
 161                 adapter->pvid = le16_to_cpu(evt->tag) & VLAN_VID_MASK;
 162         else
 163                 adapter->pvid = 0;
 164 }
 165
 166 static void be_async_grp5_evt_process(struct be_adapter *adapter,
 167                 u32 trailer, struct be_mcc_compl *evt)
 168 {
 169         u8 event_type = 0;
 170
 171         event_type = (trailer >> ASYNC_TRAILER_EVENT_TYPE_SHIFT) &
 172                 ASYNC_TRAILER_EVENT_TYPE_MASK;
 173
 174         switch (event_type) {
 175         case ASYNC_EVENT_COS_PRIORITY:
 176                 be_async_grp5_cos_priority_process(adapter,
 177                 (struct be_async_event_grp5_cos_priority *)evt);
 178         break;
 179         case ASYNC_EVENT_QOS_SPEED:
 180                 be_async_grp5_qos_speed_process(adapter,
 181                 (struct be_async_event_grp5_qos_link_speed *)evt);
 182         break;
 183         case ASYNC_EVENT_PVID_STATE:
 184                 be_async_grp5_pvid_state_process(adapter,
 185                 (struct be_async_event_grp5_pvid_state *)evt);
 186         break;
 187         default:
 188                 dev_warn(&adapter->pdev->dev, "Unknown grp5 event!\n");
 189                 break;
 190         }
 191 }
 192
 193 static inline bool is_link_state_evt(u32 trailer)
 194 {
 195         return ((trailer >> ASYNC_TRAILER_EVENT_CODE_SHIFT) &
 196                 ASYNC_TRAILER_EVENT_CODE_MASK) ==
 197                                 ASYNC_EVENT_CODE_LINK_STATE;
 198 }
 199
 200 static inline bool is_grp5_evt(u32 trailer)
 201 {
 202         return (((trailer >> ASYNC_TRAILER_EVENT_CODE_SHIFT) &
 203                 ASYNC_TRAILER_EVENT_CODE_MASK) ==
 204                                 ASYNC_EVENT_CODE_GRP_5);
 205 }
 206
 207 static struct be_mcc_compl *be_mcc_compl_get(struct be_adapter *adapter)
 208 {
 209         struct be_queue_info *mcc_cq = &adapter->mcc_obj.cq;
 210         struct be_mcc_compl *compl = queue_tail_node(mcc_cq);
 211
 212         if (be_mcc_compl_is_new(compl)) {
 213                 queue_tail_inc(mcc_cq);
 214                 return compl;
 215         }
 216         return NULL;
 217 }
 218
 219 void be_async_mcc_enable(struct be_adapter *adapter)
 220 {
 221         spin_lock_bh(&adapter->mcc_cq_lock);
 222
 223         be_cq_notify(adapter, adapter->mcc_obj.cq.id, true, 0);
 224         adapter->mcc_obj.rearm_cq = true;
 225
 226         spin_unlock_bh(&adapter->mcc_cq_lock);
 227 }
 228
 229 void be_async_mcc_disable(struct be_adapter *adapter)
 230 {
 231         adapter->mcc_obj.rearm_cq = false;
 232 }
 233
 234 int be_process_mcc(struct be_adapter *adapter, int *status)
 235 {
 236         struct be_mcc_compl *compl;
 237         int num = 0;
 238         struct be_mcc_obj *mcc_obj = &adapter->mcc_obj;
 239
 240         spin_lock_bh(&adapter->mcc_cq_lock);
 241         while ((compl = be_mcc_compl_get(adapter))) {
 242                 if (compl->flags & CQE_FLAGS_ASYNC_MASK) {
 243                         /* Interpret flags as an async trailer */
 244                         if (is_link_state_evt(compl->flags))
 245                                 be_async_link_state_process(adapter,
 246                                 (struct be_async_event_link_state *) compl);
 247                         else if (is_grp5_evt(compl->flags))
 248                                 be_async_grp5_evt_process(adapter,
 249                                 compl->flags, compl);
 250                 } else if (compl->flags & CQE_FLAGS_COMPLETED_MASK) {
 251                                 *status = be_mcc_compl_process(adapter, compl);
 252                                 atomic_dec(&mcc_obj->q.used);
 253                 }
 254                 be_mcc_compl_use(compl);
 255                 num++;
 256         }
 257
 258         spin_unlock_bh(&adapter->mcc_cq_lock);
 259         return num;
 260 }
 261
 262 /* Wait till no more pending mcc requests are present */
 263 static int be_mcc_wait_compl(struct be_adapter *adapter)
 264 {
 265 #define mcc_timeout             120000 /* 12s timeout */
 266         int i, num, status = 0;
 267         struct be_mcc_obj *mcc_obj = &adapter->mcc_obj;
 268
 269         if (adapter->eeh_err)
 270                 return -EIO;
 271
 272         for (i = 0; i < mcc_timeout; i++) {
 273                 num = be_process_mcc(adapter, &status);
 274                 if (num)
 275                         be_cq_notify(adapter, mcc_obj->cq.id,
 276                                 mcc_obj->rearm_cq, num);
 277
 278                 if (atomic_read(&mcc_obj->q.used) == 0)
 279                         break;
 280                 udelay(100);
 281         }
 282         if (i == mcc_timeout) {
 283                 dev_err(&adapter->pdev->dev, "mccq poll timed out\n");
 284                 return -1;
 285         }
 286         return status;
 287 }
 288
 289 /* Notify MCC requests and wait for completion */
 290 static int be_mcc_notify_wait(struct be_adapter *adapter)
 291 {
 292         be_mcc_notify(adapter);
 293         return be_mcc_wait_compl(adapter);
 294 }
 295
 296 static int be_mbox_db_ready_wait(struct be_adapter *adapter, void __iomem *db)
 297 {
 298         int msecs = 0;
 299         u32 ready;
 300
 301         if (adapter->eeh_err) {
 302                 dev_err(&adapter->pdev->dev,
 303                         "Error detected in card.Cannot issue commands\n");
 304                 return -EIO;
 305         }
 306
 307         do {
 308                 ready = ioread32(db);
 309                 if (ready == 0xffffffff) {
 310                         dev_err(&adapter->pdev->dev,
 311                                 "pci slot disconnected\n");
 312                         return -1;
 313                 }
 314
 315                 ready &= MPU_MAILBOX_DB_RDY_MASK;
 316                 if (ready)
 317                         break;
 318
 319                 if (msecs > 4000) {
 320                         dev_err(&adapter->pdev->dev, "mbox poll timed out\n");
 321                         if (!lancer_chip(adapter))
 322                                 be_detect_dump_ue(adapter);
 323                         return -1;
 324                 }
 325
 326                 msleep(1);
 327                 msecs++;
 328         } while (true);
 329
 330         return 0;
 331 }
 332
 333 /*
 334  * Insert the mailbox address into the doorbell in two steps
 335  * Polls on the mbox doorbell till a command completion (or a timeout) occurs
 336  */
 337 static int be_mbox_notify_wait(struct be_adapter *adapter)
 338 {
 339         int status;
 340         u32 val = 0;
 341         void __iomem *db = adapter->db + MPU_MAILBOX_DB_OFFSET;
 342         struct be_dma_mem *mbox_mem = &adapter->mbox_mem;
 343         struct be_mcc_mailbox *mbox = mbox_mem->va;
 344         struct be_mcc_compl *compl = &mbox->compl;
 345
 346         /* wait for ready to be set */
 347         status = be_mbox_db_ready_wait(adapter, db);
 348         if (status != 0)
 349                 return status;
 350
 351         val |= MPU_MAILBOX_DB_HI_MASK;
 352         /* at bits 2 - 31 place mbox dma addr msb bits 34 - 63 */
 353         val |= (upper_32_bits(mbox_mem->dma) >> 2) << 2;
 354         iowrite32(val, db);
 355
 356         /* wait for ready to be set */
 357         status = be_mbox_db_ready_wait(adapter, db);
 358         if (status != 0)
 359                 return status;
 360
 361         val = 0;
 362         /* at bits 2 - 31 place mbox dma addr lsb bits 4 - 33 */
 363         val |= (u32)(mbox_mem->dma >> 4) << 2;
 364         iowrite32(val, db);
 365
 366         status = be_mbox_db_ready_wait(adapter, db);
 367         if (status != 0)
 368                 return status;
 369
 370         /* A cq entry has been made now */
 371         if (be_mcc_compl_is_new(compl)) {
 372                 status = be_mcc_compl_process(adapter, &mbox->compl);
 373                 be_mcc_compl_use(compl);
 374                 if (status)
 375                         return status;
 376         } else {
 377                 dev_err(&adapter->pdev->dev, "invalid mailbox completion\n");
 378                 return -1;
 379         }
 380         return 0;
 381 }
 382
 383 static int be_POST_stage_get(struct be_adapter *adapter, u16 *stage)
 384 {
 385         u32 sem;
 386
 387         if (lancer_chip(adapter))
 388                 sem  = ioread32(adapter->db + MPU_EP_SEMAPHORE_IF_TYPE2_OFFSET);
 389         else
 390                 sem  = ioread32(adapter->csr + MPU_EP_SEMAPHORE_OFFSET);
 391
 392         *stage = sem & EP_SEMAPHORE_POST_STAGE_MASK;
 393         if ((sem >> EP_SEMAPHORE_POST_ERR_SHIFT) & EP_SEMAPHORE_POST_ERR_MASK)
 394                 return -1;
 395         else
 396                 return 0;
 397 }
 398
 399 int be_cmd_POST(struct be_adapter *adapter)
 400 {
 401         u16 stage;
 402         int status, timeout = 0;
 403         struct device *dev = &adapter->pdev->dev;
 404
 405         do {
 406                 status = be_POST_stage_get(adapter, &stage);
 407                 if (status) {
 408                         dev_err(dev, "POST error; stage=0x%x\n", stage);
 409                         return -1;
 410                 } else if (stage != POST_STAGE_ARMFW_RDY) {
 411                         if (msleep_interruptible(2000)) {
 412                                 dev_err(dev, "Waiting for POST aborted\n");
 413                                 return -EINTR;
 414                         }
 415                         timeout += 2;
 416                 } else {
 417                         return 0;
 418                 }
 419         } while (timeout < 60);
 420
 421         dev_err(dev, "POST timeout; stage=0x%x\n", stage);
 422         return -1;
 423 }
 424
 425
 426 static inline struct be_sge *nonembedded_sgl(struct be_mcc_wrb *wrb)
 427 {
 428         return &wrb->payload.sgl[0];
 429 }
 430
 431
 432 /* Don't touch the hdr after it's prepared */
 433 /* mem will be NULL for embedded commands */
 434 static void be_wrb_cmd_hdr_prepare(struct be_cmd_req_hdr *req_hdr,
 435                                 u8 subsystem, u8 opcode, int cmd_len,
 436                                 struct be_mcc_wrb *wrb, struct be_dma_mem *mem)
 437 {
 438         struct be_sge *sge;
 439
 440         req_hdr->opcode = opcode;
 441         req_hdr->subsystem = subsystem;
 442         req_hdr->request_length = cpu_to_le32(cmd_len - sizeof(*req_hdr));
 443         req_hdr->version = 0;
 444
 445         wrb->tag0 = opcode;
 446         wrb->tag1 = subsystem;
 447         wrb->payload_length = cmd_len;
 448         if (mem) {
 449                 wrb->embedded |= (1 & MCC_WRB_SGE_CNT_MASK) <<
 450                         MCC_WRB_SGE_CNT_SHIFT;
 451                 sge = nonembedded_sgl(wrb);
 452                 sge->pa_hi = cpu_to_le32(upper_32_bits(mem->dma));
 453                 sge->pa_lo = cpu_to_le32(mem->dma & 0xFFFFFFFF);
 454                 sge->len = cpu_to_le32(mem->size);
 455         } else
 456                 wrb->embedded |= MCC_WRB_EMBEDDED_MASK;
 457         be_dws_cpu_to_le(wrb, 8);
 458 }
 459
 460 static void be_cmd_page_addrs_prepare(struct phys_addr *pages, u32 max_pages,
 461                         struct be_dma_mem *mem)
 462 {
 463         int i, buf_pages = min(PAGES_4K_SPANNED(mem->va, mem->size), max_pages);
 464         u64 dma = (u64)mem->dma;
 465
 466         for (i = 0; i < buf_pages; i++) {
 467                 pages[i].lo = cpu_to_le32(dma & 0xFFFFFFFF);
 468                 pages[i].hi = cpu_to_le32(upper_32_bits(dma));
 469                 dma += PAGE_SIZE_4K;
 470         }
 471 }
 472
 473 /* Converts interrupt delay in microseconds to multiplier value */
 474 static u32 eq_delay_to_mult(u32 usec_delay)
 475 {
 476 #define MAX_INTR_RATE                   651042
 477         const u32 round = 10;
 478         u32 multiplier;
 479
 480         if (usec_delay == 0)
 481                 multiplier = 0;
 482         else {
 483                 u32 interrupt_rate = 1000000 / usec_delay;
 484                 /* Max delay, corresponding to the lowest interrupt rate */
 485                 if (interrupt_rate == 0)
 486                         multiplier = 1023;
 487                 else {
 488                         multiplier = (MAX_INTR_RATE - interrupt_rate) * round;
 489                         multiplier /= interrupt_rate;
 490                         /* Round the multiplier to the closest value.*/
 491                         multiplier = (multiplier + round/2) / round;
 492                         multiplier = min(multiplier, (u32)1023);
 493                 }
 494         }
 495         return multiplier;
 496 }
 497
 498 static inline struct be_mcc_wrb *wrb_from_mbox(struct be_adapter *adapter)
 499 {
 500         struct be_dma_mem *mbox_mem = &adapter->mbox_mem;
 501         struct be_mcc_wrb *wrb
 502                 = &((struct be_mcc_mailbox *)(mbox_mem->va))->wrb;
 503         memset(wrb, 0, sizeof(*wrb));
 504         return wrb;
 505 }
 506
 507 static struct be_mcc_wrb *wrb_from_mccq(struct be_adapter *adapter)
 508 {
 509         struct be_queue_info *mccq = &adapter->mcc_obj.q;
 510         struct be_mcc_wrb *wrb;
 511
 512         if (atomic_read(&mccq->used) >= mccq->len) {
 513                 dev_err(&adapter->pdev->dev, "Out of MCCQ wrbs\n");
 514                 return NULL;
 515         }
 516
 517         wrb = queue_head_node(mccq);
 518         queue_head_inc(mccq);
 519         atomic_inc(&mccq->used);
 520         memset(wrb, 0, sizeof(*wrb));
 521         return wrb;
 522 }
 523
 524 /* Tell fw we're about to start firing cmds by writing a
 525  * special pattern across the wrb hdr; uses mbox
 526  */
 527 int be_cmd_fw_init(struct be_adapter *adapter)
 528 {
 529         u8 *wrb;
 530         int status;
 531
 532         if (mutex_lock_interruptible(&adapter->mbox_lock))
 533                 return -1;
 534
 535         wrb = (u8 *)wrb_from_mbox(adapter);
 536         *wrb++ = 0xFF;
 537         *wrb++ = 0x12;
 538         *wrb++ = 0x34;
 539         *wrb++ = 0xFF;
 540         *wrb++ = 0xFF;
 541         *wrb++ = 0x56;
 542         *wrb++ = 0x78;
 543         *wrb = 0xFF;
 544
 545         status = be_mbox_notify_wait(adapter);
 546
 547         mutex_unlock(&adapter->mbox_lock);
 548         return status;
 549 }
 550
 551 /* Tell fw we're done with firing cmds by writing a
 552  * special pattern across the wrb hdr; uses mbox
 553  */
 554 int be_cmd_fw_clean(struct be_adapter *adapter)
 555 {
 556         u8 *wrb;
 557         int status;
 558
 559         if (adapter->eeh_err)
 560                 return -EIO;
 561
 562         if (mutex_lock_interruptible(&adapter->mbox_lock))
 563                 return -1;
 564
 565         wrb = (u8 *)wrb_from_mbox(adapter);
 566         *wrb++ = 0xFF;
 567         *wrb++ = 0xAA;
 568         *wrb++ = 0xBB;
 569         *wrb++ = 0xFF;
 570         *wrb++ = 0xFF;
 571         *wrb++ = 0xCC;
 572         *wrb++ = 0xDD;
 573         *wrb = 0xFF;
 574
 575         status = be_mbox_notify_wait(adapter);
 576
 577         mutex_unlock(&adapter->mbox_lock);
 578         return status;
 579 }
 580 int be_cmd_eq_create(struct be_adapter *adapter,
 581                 struct be_queue_info *eq, int eq_delay)
 582 {
 583         struct be_mcc_wrb *wrb;
 584         struct be_cmd_req_eq_create *req;
 585         struct be_dma_mem *q_mem = &eq->dma_mem;
 586         int status;
 587
 588         if (mutex_lock_interruptible(&adapter->mbox_lock))
 589                 return -1;
 590
 591         wrb = wrb_from_mbox(adapter);
 592         req = embedded_payload(wrb);
 593
 594         be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
 595                 OPCODE_COMMON_EQ_CREATE, sizeof(*req), wrb, NULL);
 596
 597         req->num_pages =  cpu_to_le16(PAGES_4K_SPANNED(q_mem->va, q_mem->size));
 598
 599         AMAP_SET_BITS(struct amap_eq_context, valid, req->context, 1);
 600         /* 4byte eqe*/
 601         AMAP_SET_BITS(struct amap_eq_context, size, req->context, 0);
 602         AMAP_SET_BITS(struct amap_eq_context, count, req->context,
 603                         __ilog2_u32(eq->len/256));
 604         AMAP_SET_BITS(struct amap_eq_context, delaymult, req->context,
 605                         eq_delay_to_mult(eq_delay));
 606         be_dws_cpu_to_le(req->context, sizeof(req->context));
 607
 608         be_cmd_page_addrs_prepare(req->pages, ARRAY_SIZE(req->pages), q_mem);
 609
 610         status = be_mbox_notify_wait(adapter);
 611         if (!status) {
 612                 struct be_cmd_resp_eq_create *resp = embedded_payload(wrb);
 613                 eq->id = le16_to_cpu(resp->eq_id);
 614                 eq->created = true;
 615         }
 616
 617         mutex_unlock(&adapter->mbox_lock);
 618         return status;
 619 }
 620
 621 /* Use MCC */
 622 int be_cmd_mac_addr_query(struct be_adapter *adapter, u8 *mac_addr,
 623                         u8 type, bool permanent, u32 if_handle)
 624 {
 625         struct be_mcc_wrb *wrb;
 626         struct be_cmd_req_mac_query *req;
 627         int status;
 628
 629         spin_lock_bh(&adapter->mcc_lock);
 630
 631         wrb = wrb_from_mccq(adapter);
 632         if (!wrb) {
 633                 status = -EBUSY;
 634                 goto err;
 635         }
 636         req = embedded_payload(wrb);
 637
 638         be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
 639                 OPCODE_COMMON_NTWK_MAC_QUERY, sizeof(*req), wrb, NULL);
 640         req->type = type;
 641         if (permanent) {
 642                 req->permanent = 1;
 643         } else {
 644                 req->if_id = cpu_to_le16((u16) if_handle);
 645                 req->permanent = 0;
 646         }
 647
 648         status = be_mcc_notify_wait(adapter);
 649         if (!status) {
 650                 struct be_cmd_resp_mac_query *resp = embedded_payload(wrb);
 651                 memcpy(mac_addr, resp->mac.addr, ETH_ALEN);
 652         }
 653
 654 err:
 655         spin_unlock_bh(&adapter->mcc_lock);
 656         return status;
 657 }
 658
 659 /* Uses synchronous MCCQ */
 660 int be_cmd_pmac_add(struct be_adapter *adapter, u8 *mac_addr,
 661                 u32 if_id, u32 *pmac_id, u32 domain)
 662 {
 663         struct be_mcc_wrb *wrb;
 664         struct be_cmd_req_pmac_add *req;
 665         int status;
 666
 667         spin_lock_bh(&adapter->mcc_lock);
 668
 669         wrb = wrb_from_mccq(adapter);
 670         if (!wrb) {
 671                 status = -EBUSY;
 672                 goto err;
 673         }
 674         req = embedded_payload(wrb);
 675
 676         be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
 677                 OPCODE_COMMON_NTWK_PMAC_ADD, sizeof(*req), wrb, NULL);
 678
 679         req->hdr.domain = domain;
 680         req->if_id = cpu_to_le32(if_id);
 681         memcpy(req->mac_address, mac_addr, ETH_ALEN);
 682
 683         status = be_mcc_notify_wait(adapter);
 684         if (!status) {
 685                 struct be_cmd_resp_pmac_add *resp = embedded_payload(wrb);
 686                 *pmac_id = le32_to_cpu(resp->pmac_id);
 687         }
 688
 689 err:
 690         spin_unlock_bh(&adapter->mcc_lock);
 691         return status;
 692 }
 693
 694 /* Uses synchronous MCCQ */
 695 int be_cmd_pmac_del(struct be_adapter *adapter, u32 if_id, u32 pmac_id, u32 dom)
 696 {
 697         struct be_mcc_wrb *wrb;
 698         struct be_cmd_req_pmac_del *req;
 699         int status;
 700
 701         spin_lock_bh(&adapter->mcc_lock);
 702
 703         wrb = wrb_from_mccq(adapter);
 704         if (!wrb) {
 705                 status = -EBUSY;
 706                 goto err;
 707         }
 708         req = embedded_payload(wrb);
 709
 710         be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
 711                 OPCODE_COMMON_NTWK_PMAC_DEL, sizeof(*req), wrb, NULL);
 712
 713         req->hdr.domain = dom;
 714         req->if_id = cpu_to_le32(if_id);
 715         req->pmac_id = cpu_to_le32(pmac_id);
 716
 717         status = be_mcc_notify_wait(adapter);
 718
 719 err:
 720         spin_unlock_bh(&adapter->mcc_lock);
 721         return status;
 722 }
 723
 724 /* Uses Mbox */
 725 int be_cmd_cq_create(struct be_adapter *adapter,
 726                 struct be_queue_info *cq, struct be_queue_info *eq,
 727                 bool sol_evts, bool no_delay, int coalesce_wm)
 728 {
 729         struct be_mcc_wrb *wrb;
 730         struct be_cmd_req_cq_create *req;
 731         struct be_dma_mem *q_mem = &cq->dma_mem;
 732         void *ctxt;
 733         int status;
 734
 735         if (mutex_lock_interruptible(&adapter->mbox_lock))
 736                 return -1;
 737
 738         wrb = wrb_from_mbox(adapter);
 739         req = embedded_payload(wrb);
 740         ctxt = &req->context;
 741
 742         be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
 743                 OPCODE_COMMON_CQ_CREATE, sizeof(*req), wrb, NULL);
 744
 745         req->num_pages =  cpu_to_le16(PAGES_4K_SPANNED(q_mem->va, q_mem->size));
 746         if (lancer_chip(adapter)) {
 747                 req->hdr.version = 2;
 748                 req->page_size = 1; /* 1 for 4K */
 749                 AMAP_SET_BITS(struct amap_cq_context_lancer, nodelay, ctxt,
 750                                                                 no_delay);
 751                 AMAP_SET_BITS(struct amap_cq_context_lancer, count, ctxt,
 752                                                 __ilog2_u32(cq->len/256));
 753                 AMAP_SET_BITS(struct amap_cq_context_lancer, valid, ctxt, 1);
 754                 AMAP_SET_BITS(struct amap_cq_context_lancer, eventable,
 755                                                                 ctxt, 1);
 756                 AMAP_SET_BITS(struct amap_cq_context_lancer, eqid,
 757                                                                 ctxt, eq->id);
 758                 AMAP_SET_BITS(struct amap_cq_context_lancer, armed, ctxt, 1);
 759         } else {
 760                 AMAP_SET_BITS(struct amap_cq_context_be, coalescwm, ctxt,
 761                                                                 coalesce_wm);
 762                 AMAP_SET_BITS(struct amap_cq_context_be, nodelay,
 763                                                                 ctxt, no_delay);
 764                 AMAP_SET_BITS(struct amap_cq_context_be, count, ctxt,
 765                                                 __ilog2_u32(cq->len/256));
 766                 AMAP_SET_BITS(struct amap_cq_context_be, valid, ctxt, 1);
 767                 AMAP_SET_BITS(struct amap_cq_context_be, solevent,
 768                                                                 ctxt, sol_evts);
 769                 AMAP_SET_BITS(struct amap_cq_context_be, eventable, ctxt, 1);
 770                 AMAP_SET_BITS(struct amap_cq_context_be, eqid, ctxt, eq->id);
 771                 AMAP_SET_BITS(struct amap_cq_context_be, armed, ctxt, 1);
 772         }
 773
 774         be_dws_cpu_to_le(ctxt, sizeof(req->context));
 775
 776         be_cmd_page_addrs_prepare(req->pages, ARRAY_SIZE(req->pages), q_mem);
 777
 778         status = be_mbox_notify_wait(adapter);
 779         if (!status) {
 780                 struct be_cmd_resp_cq_create *resp = embedded_payload(wrb);
 781                 cq->id = le16_to_cpu(resp->cq_id);
 782                 cq->created = true;
 783         }
 784
 785         mutex_unlock(&adapter->mbox_lock);
 786
 787         return status;
 788 }
 789
 790 static u32 be_encoded_q_len(int q_len)
 791 {
 792         u32 len_encoded = fls(q_len); /* log2(len) + 1 */
 793         if (len_encoded == 16)
 794                 len_encoded = 0;
 795         return len_encoded;
 796 }
 797
 798 int be_cmd_mccq_ext_create(struct be_adapter *adapter,
 799                         struct be_queue_info *mccq,
 800                         struct be_queue_info *cq)
 801 {
 802         struct be_mcc_wrb *wrb;
 803         struct be_cmd_req_mcc_ext_create *req;
 804         struct be_dma_mem *q_mem = &mccq->dma_mem;
 805         void *ctxt;
 806         int status;
 807
 808         if (mutex_lock_interruptible(&adapter->mbox_lock))
 809                 return -1;
 810
 811         wrb = wrb_from_mbox(adapter);
 812         req = embedded_payload(wrb);
 813         ctxt = &req->context;
 814
 815         be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
 816                         OPCODE_COMMON_MCC_CREATE_EXT, sizeof(*req), wrb, NULL);
 817
 818         req->num_pages = cpu_to_le16(PAGES_4K_SPANNED(q_mem->va, q_mem->size));
 819         if (lancer_chip(adapter)) {
 820                 req->hdr.version = 1;
 821                 req->cq_id = cpu_to_le16(cq->id);
 822
 823                 AMAP_SET_BITS(struct amap_mcc_context_lancer, ring_size, ctxt,
 824                                                 be_encoded_q_len(mccq->len));
 825                 AMAP_SET_BITS(struct amap_mcc_context_lancer, valid, ctxt, 1);
 826                 AMAP_SET_BITS(struct amap_mcc_context_lancer, async_cq_id,
 827                                                                 ctxt, cq->id);
 828                 AMAP_SET_BITS(struct amap_mcc_context_lancer, async_cq_valid,
 829                                                                  ctxt, 1);
 830
 831         } else {
 832                 AMAP_SET_BITS(struct amap_mcc_context_be, valid, ctxt, 1);
 833                 AMAP_SET_BITS(struct amap_mcc_context_be, ring_size, ctxt,
 834                                                 be_encoded_q_len(mccq->len));
 835                 AMAP_SET_BITS(struct amap_mcc_context_be, cq_id, ctxt, cq->id);
 836         }
 837
 838         /* Subscribe to Link State and Group 5 Events(bits 1 and 5 set) */
 839         req->async_event_bitmap[0] = cpu_to_le32(0x00000022);
 840         be_dws_cpu_to_le(ctxt, sizeof(req->context));
 841
 842         be_cmd_page_addrs_prepare(req->pages, ARRAY_SIZE(req->pages), q_mem);
 843
 844         status = be_mbox_notify_wait(adapter);
 845         if (!status) {
 846                 struct be_cmd_resp_mcc_create *resp = embedded_payload(wrb);
 847                 mccq->id = le16_to_cpu(resp->id);
 848                 mccq->created = true;
 849         }
 850         mutex_unlock(&adapter->mbox_lock);
 851
 852         return status;
 853 }
 854
 855 int be_cmd_mccq_org_create(struct be_adapter *adapter,
 856                         struct be_queue_info *mccq,
 857                         struct be_queue_info *cq)
 858 {
 859         struct be_mcc_wrb *wrb;
 860         struct be_cmd_req_mcc_create *req;
 861         struct be_dma_mem *q_mem = &mccq->dma_mem;
 862         void *ctxt;
 863         int status;
 864
 865         if (mutex_lock_interruptible(&adapter->mbox_lock))
 866                 return -1;
 867
 868         wrb = wrb_from_mbox(adapter);
 869         req = embedded_payload(wrb);
 870         ctxt = &req->context;
 871
 872         be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
 873                         OPCODE_COMMON_MCC_CREATE, sizeof(*req), wrb, NULL);
 874
 875         req->num_pages = cpu_to_le16(PAGES_4K_SPANNED(q_mem->va, q_mem->size));
 876
 877         AMAP_SET_BITS(struct amap_mcc_context_be, valid, ctxt, 1);
 878         AMAP_SET_BITS(struct amap_mcc_context_be, ring_size, ctxt,
 879                         be_encoded_q_len(mccq->len));
 880         AMAP_SET_BITS(struct amap_mcc_context_be, cq_id, ctxt, cq->id);
 881
 882         be_dws_cpu_to_le(ctxt, sizeof(req->context));
 883
 884         be_cmd_page_addrs_prepare(req->pages, ARRAY_SIZE(req->pages), q_mem);
 885
 886         status = be_mbox_notify_wait(adapter);
 887         if (!status) {
 888                 struct be_cmd_resp_mcc_create *resp = embedded_payload(wrb);
 889                 mccq->id = le16_to_cpu(resp->id);
 890                 mccq->created = true;
 891         }
 892
 893         mutex_unlock(&adapter->mbox_lock);
 894         return status;
 895 }
 896
 897 int be_cmd_mccq_create(struct be_adapter *adapter,
 898                         struct be_queue_info *mccq,
 899                         struct be_queue_info *cq)
 900 {
 901         int status;
 902
 903         status = be_cmd_mccq_ext_create(adapter, mccq, cq);
 904         if (status && !lancer_chip(adapter)) {
 905                 dev_warn(&adapter->pdev->dev, "Upgrade to F/W ver 2.102.235.0 "
 906                         "or newer to avoid conflicting priorities between NIC "
 907                         "and FCoE traffic");
 908                 status = be_cmd_mccq_org_create(adapter, mccq, cq);
 909         }
 910         return status;
 911 }
 912
 913 int be_cmd_txq_create(struct be_adapter *adapter,
 914                         struct be_queue_info *txq,
 915                         struct be_queue_info *cq)
 916 {
 917         struct be_mcc_wrb *wrb;
 918         struct be_cmd_req_eth_tx_create *req;
 919         struct be_dma_mem *q_mem = &txq->dma_mem;
 920         void *ctxt;
 921         int status;
 922
 923         if (mutex_lock_interruptible(&adapter->mbox_lock))
 924                 return -1;
 925
 926         wrb = wrb_from_mbox(adapter);
 927         req = embedded_payload(wrb);
 928         ctxt = &req->context;
 929
 930         be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_ETH,
 931                 OPCODE_ETH_TX_CREATE, sizeof(*req), wrb, NULL);
 932
 933         if (lancer_chip(adapter)) {
 934                 req->hdr.version = 1;
 935                 AMAP_SET_BITS(struct amap_tx_context, if_id, ctxt,
 936                                         adapter->if_handle);
 937         }
 938
 939         req->num_pages = PAGES_4K_SPANNED(q_mem->va, q_mem->size);
 940         req->ulp_num = BE_ULP1_NUM;
 941         req->type = BE_ETH_TX_RING_TYPE_STANDARD;
 942
 943         AMAP_SET_BITS(struct amap_tx_context, tx_ring_size, ctxt,
 944                 be_encoded_q_len(txq->len));
 945         AMAP_SET_BITS(struct amap_tx_context, ctx_valid, ctxt, 1);
 946         AMAP_SET_BITS(struct amap_tx_context, cq_id_send, ctxt, cq->id);
 947
 948         be_dws_cpu_to_le(ctxt, sizeof(req->context));
 949
 950         be_cmd_page_addrs_prepare(req->pages, ARRAY_SIZE(req->pages), q_mem);
 951
 952         status = be_mbox_notify_wait(adapter);
 953         if (!status) {
 954                 struct be_cmd_resp_eth_tx_create *resp = embedded_payload(wrb);
 955                 txq->id = le16_to_cpu(resp->cid);
 956                 txq->created = true;
 957         }
 958
 959         mutex_unlock(&adapter->mbox_lock);
 960
 961         return status;
 962 }
 963
 964 /* Uses MCC */
 965 int be_cmd_rxq_create(struct be_adapter *adapter,
 966                 struct be_queue_info *rxq, u16 cq_id, u16 frag_size,
 967                 u16 max_frame_size, u32 if_id, u32 rss, u8 *rss_id)
 968 {
 969         struct be_mcc_wrb *wrb;
 970         struct be_cmd_req_eth_rx_create *req;
 971         struct be_dma_mem *q_mem = &rxq->dma_mem;
 972         int status;
 973
 974         spin_lock_bh(&adapter->mcc_lock);
 975
 976         wrb = wrb_from_mccq(adapter);
 977         if (!wrb) {
 978                 status = -EBUSY;
 979                 goto err;
 980         }
 981         req = embedded_payload(wrb);
 982
 983         be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_ETH,
 984                                 OPCODE_ETH_RX_CREATE, sizeof(*req), wrb, NULL);
 985
 986         req->cq_id = cpu_to_le16(cq_id);
 987         req->frag_size = fls(frag_size) - 1;
 988         req->num_pages = 2;
 989         be_cmd_page_addrs_prepare(req->pages, ARRAY_SIZE(req->pages), q_mem);
 990         req->interface_id = cpu_to_le32(if_id);
 991         req->max_frame_size = cpu_to_le16(max_frame_size);
 992         req->rss_queue = cpu_to_le32(rss);
 993
 994         status = be_mcc_notify_wait(adapter);
 995         if (!status) {
 996                 struct be_cmd_resp_eth_rx_create *resp = embedded_payload(wrb);
 997                 rxq->id = le16_to_cpu(resp->id);
 998                 rxq->created = true;
 999                 *rss_id = resp->rss_id;
1000         }
1001
1002 err:
1003         spin_unlock_bh(&adapter->mcc_lock);
1004         return status;
1005 }
1006
1007 /* Generic destroyer function for all types of queues
1008  * Uses Mbox
1009  */
1010 int be_cmd_q_destroy(struct be_adapter *adapter, struct be_queue_info *q,
1011                 int queue_type)
1012 {
1013         struct be_mcc_wrb *wrb;
1014         struct be_cmd_req_q_destroy *req;
1015         u8 subsys = 0, opcode = 0;
1016         int status;
1017
1018         if (adapter->eeh_err)
1019                 return -EIO;
1020
1021         if (mutex_lock_interruptible(&adapter->mbox_lock))
1022                 return -1;
1023
1024         wrb = wrb_from_mbox(adapter);
1025         req = embedded_payload(wrb);
1026
1027         switch (queue_type) {
1028         case QTYPE_EQ:
1029                 subsys = CMD_SUBSYSTEM_COMMON;
1030                 opcode = OPCODE_COMMON_EQ_DESTROY;
1031                 break;
1032         case QTYPE_CQ:
1033                 subsys = CMD_SUBSYSTEM_COMMON;
1034                 opcode = OPCODE_COMMON_CQ_DESTROY;
1035                 break;
1036         case QTYPE_TXQ:
1037                 subsys = CMD_SUBSYSTEM_ETH;
1038                 opcode = OPCODE_ETH_TX_DESTROY;
1039                 break;
1040         case QTYPE_RXQ:
1041                 subsys = CMD_SUBSYSTEM_ETH;
1042                 opcode = OPCODE_ETH_RX_DESTROY;
1043                 break;
1044         case QTYPE_MCCQ:
1045                 subsys = CMD_SUBSYSTEM_COMMON;
1046                 opcode = OPCODE_COMMON_MCC_DESTROY;
1047                 break;
1048         default:
1049                 BUG();
1050         }
1051
1052         be_wrb_cmd_hdr_prepare(&req->hdr, subsys, opcode, sizeof(*req), wrb,
1053                                 NULL);
1054         req->id = cpu_to_le16(q->id);
1055
1056         status = be_mbox_notify_wait(adapter);
1057         if (!status)
1058                 q->created = false;
1059
1060         mutex_unlock(&adapter->mbox_lock);
1061         return status;
1062 }
1063
1064 /* Uses MCC */
1065 int be_cmd_rxq_destroy(struct be_adapter *adapter, struct be_queue_info *q)
1066 {
1067         struct be_mcc_wrb *wrb;
1068         struct be_cmd_req_q_destroy *req;
1069         int status;
1070
1071         spin_lock_bh(&adapter->mcc_lock);
1072
1073         wrb = wrb_from_mccq(adapter);
1074         if (!wrb) {
1075                 status = -EBUSY;
1076                 goto err;
1077         }
1078         req = embedded_payload(wrb);
1079
1080         be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_ETH,
1081                         OPCODE_ETH_RX_DESTROY, sizeof(*req), wrb, NULL);
1082         req->id = cpu_to_le16(q->id);
1083
1084         status = be_mcc_notify_wait(adapter);
1085         if (!status)
1086                 q->created = false;
1087
1088 err:
1089         spin_unlock_bh(&adapter->mcc_lock);
1090         return status;
1091 }
1092
1093 /* Create an rx filtering policy configuration on an i/f
1094  * Uses MCCQ
1095  */
1096 int be_cmd_if_create(struct be_adapter *adapter, u32 cap_flags, u32 en_flags,
1097                 u8 *mac, u32 *if_handle, u32 *pmac_id, u32 domain)
1098 {
1099         struct be_mcc_wrb *wrb;
1100         struct be_cmd_req_if_create *req;
1101         int status;
1102
1103         spin_lock_bh(&adapter->mcc_lock);
1104
1105         wrb = wrb_from_mccq(adapter);
1106         if (!wrb) {
1107                 status = -EBUSY;
1108                 goto err;
1109         }
1110         req = embedded_payload(wrb);
1111
1112         be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
1113                 OPCODE_COMMON_NTWK_INTERFACE_CREATE, sizeof(*req), wrb, NULL);
1114         req->hdr.domain = domain;
1115         req->capability_flags = cpu_to_le32(cap_flags);
1116         req->enable_flags = cpu_to_le32(en_flags);
1117         if (mac)
1118                 memcpy(req->mac_addr, mac, ETH_ALEN);
1119         else
1120                 req->pmac_invalid = true;
1121
1122         status = be_mcc_notify_wait(adapter);
1123         if (!status) {
1124                 struct be_cmd_resp_if_create *resp = embedded_payload(wrb);
1125                 *if_handle = le32_to_cpu(resp->interface_id);
1126                 if (mac)
1127                         *pmac_id = le32_to_cpu(resp->pmac_id);
1128         }
1129
1130 err:
1131         spin_unlock_bh(&adapter->mcc_lock);
1132         return status;
1133 }
1134
1135 /* Uses MCCQ */
1136 int be_cmd_if_destroy(struct be_adapter *adapter, u32 interface_id, u32 domain)
1137 {
1138         struct be_mcc_wrb *wrb;
1139         struct be_cmd_req_if_destroy *req;
1140         int status;
1141
1142         if (adapter->eeh_err)
1143                 return -EIO;
1144
1145         if (!interface_id)
1146                 return 0;
1147
1148         spin_lock_bh(&adapter->mcc_lock);
1149
1150         wrb = wrb_from_mccq(adapter);
1151         if (!wrb) {
1152                 status = -EBUSY;
1153                 goto err;
1154         }
1155         req = embedded_payload(wrb);
1156
1157         be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
1158                 OPCODE_COMMON_NTWK_INTERFACE_DESTROY, sizeof(*req), wrb, NULL);
1159         req->hdr.domain = domain;
1160         req->interface_id = cpu_to_le32(interface_id);
1161
1162         status = be_mcc_notify_wait(adapter);
1163 err:
1164         spin_unlock_bh(&adapter->mcc_lock);
1165         return status;
1166 }
1167
1168 /* Get stats is a non embedded command: the request is not embedded inside
1169  * WRB but is a separate dma memory block
1170  * Uses asynchronous MCC
1171  */
1172 int be_cmd_get_stats(struct be_adapter *adapter, struct be_dma_mem *nonemb_cmd)
1173 {
1174         struct be_mcc_wrb *wrb;
1175         struct be_cmd_req_hdr *hdr;
1176         int status = 0;
1177
1178         if (MODULO(adapter->work_counter, be_get_temp_freq) == 0)
1179                 be_cmd_get_die_temperature(adapter);
1180
1181         spin_lock_bh(&adapter->mcc_lock);
1182
1183         wrb = wrb_from_mccq(adapter);
1184         if (!wrb) {
1185                 status = -EBUSY;
1186                 goto err;
1187         }
1188         hdr = nonemb_cmd->va;
1189
1190         be_wrb_cmd_hdr_prepare(hdr, CMD_SUBSYSTEM_ETH,
1191                 OPCODE_ETH_GET_STATISTICS, nonemb_cmd->size, wrb, nonemb_cmd);
1192
1193         if (adapter->generation == BE_GEN3)
1194                 hdr->version = 1;
1195
1196         be_mcc_notify(adapter);
1197         adapter->stats_cmd_sent = true;
1198
1199 err:
1200         spin_unlock_bh(&adapter->mcc_lock);
1201         return status;
1202 }
1203
1204 /* Lancer Stats */
1205 int lancer_cmd_get_pport_stats(struct be_adapter *adapter,
1206                                 struct be_dma_mem *nonemb_cmd)
1207 {
1208
1209         struct be_mcc_wrb *wrb;
1210         struct lancer_cmd_req_pport_stats *req;
1211         int status = 0;
1212
1213         spin_lock_bh(&adapter->mcc_lock);
1214
1215         wrb = wrb_from_mccq(adapter);
1216         if (!wrb) {
1217                 status = -EBUSY;
1218                 goto err;
1219         }
1220         req = nonemb_cmd->va;
1221
1222         be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_ETH,
1223                         OPCODE_ETH_GET_PPORT_STATS, nonemb_cmd->size, wrb,
1224                         nonemb_cmd);
1225
1226         req->cmd_params.params.pport_num = cpu_to_le16(adapter->port_num);
1227         req->cmd_params.params.reset_stats = 0;
1228
1229         be_mcc_notify(adapter);
1230         adapter->stats_cmd_sent = true;
1231
1232 err:
1233         spin_unlock_bh(&adapter->mcc_lock);
1234         return status;
1235 }
1236
1237 /* Uses synchronous mcc */
1238 int be_cmd_link_status_query(struct be_adapter *adapter, u8 *mac_speed,
1239                         u16 *link_speed, u32 dom)
1240 {
1241         struct be_mcc_wrb *wrb;
1242         struct be_cmd_req_link_status *req;
1243         int status;
1244
1245         spin_lock_bh(&adapter->mcc_lock);
1246
1247         wrb = wrb_from_mccq(adapter);
1248         if (!wrb) {
1249                 status = -EBUSY;
1250                 goto err;
1251         }
1252         req = embedded_payload(wrb);
1253
1254         be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
1255                 OPCODE_COMMON_NTWK_LINK_STATUS_QUERY, sizeof(*req), wrb, NULL);
1256
1257         status = be_mcc_notify_wait(adapter);
1258         if (!status) {
1259                 struct be_cmd_resp_link_status *resp = embedded_payload(wrb);
1260                 if (resp->mac_speed != PHY_LINK_SPEED_ZERO) {
1261                         *link_speed = le16_to_cpu(resp->link_speed);
1262                         if (mac_speed)
1263                                 *mac_speed = resp->mac_speed;
1264                 }
1265         }
1266
1267 err:
1268         spin_unlock_bh(&adapter->mcc_lock);
1269         return status;
1270 }
1271
1272 /* Uses synchronous mcc */
1273 int be_cmd_get_die_temperature(struct be_adapter *adapter)
1274 {
1275         struct be_mcc_wrb *wrb;
1276         struct be_cmd_req_get_cntl_addnl_attribs *req;
1277         u16 mccq_index;
1278         int status;
1279
1280         spin_lock_bh(&adapter->mcc_lock);
1281
1282         mccq_index = adapter->mcc_obj.q.head;
1283
1284         wrb = wrb_from_mccq(adapter);
1285         if (!wrb) {
1286                 status = -EBUSY;
1287                 goto err;
1288         }
1289         req = embedded_payload(wrb);
1290
1291         be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
1292                 OPCODE_COMMON_GET_CNTL_ADDITIONAL_ATTRIBUTES, sizeof(*req),
1293                 wrb, NULL);
1294
1295         wrb->tag1 = mccq_index;
1296
1297         be_mcc_notify(adapter);
1298
1299 err:
1300         spin_unlock_bh(&adapter->mcc_lock);
1301         return status;
1302 }
1303
1304 /* Uses synchronous mcc */
1305 int be_cmd_get_reg_len(struct be_adapter *adapter, u32 *log_size)
1306 {
1307         struct be_mcc_wrb *wrb;
1308         struct be_cmd_req_get_fat *req;
1309         int status;
1310
1311         spin_lock_bh(&adapter->mcc_lock);
1312
1313         wrb = wrb_from_mccq(adapter);
1314         if (!wrb) {
1315                 status = -EBUSY;
1316                 goto err;
1317         }
1318         req = embedded_payload(wrb);
1319
1320         be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
1321                 OPCODE_COMMON_MANAGE_FAT, sizeof(*req), wrb, NULL);
1322         req->fat_operation = cpu_to_le32(QUERY_FAT);
1323         status = be_mcc_notify_wait(adapter);
1324         if (!status) {
1325                 struct be_cmd_resp_get_fat *resp = embedded_payload(wrb);
1326                 if (log_size && resp->log_size)
1327                         *log_size = le32_to_cpu(resp->log_size) -
1328                                         sizeof(u32);
1329         }
1330 err:
1331         spin_unlock_bh(&adapter->mcc_lock);
1332         return status;
1333 }
1334
1335 void be_cmd_get_regs(struct be_adapter *adapter, u32 buf_len, void *buf)
1336 {
1337         struct be_dma_mem get_fat_cmd;
1338         struct be_mcc_wrb *wrb;
1339         struct be_cmd_req_get_fat *req;
1340         u32 offset = 0, total_size, buf_size,
1341                                 log_offset = sizeof(u32), payload_len;
1342         int status;
1343
1344         if (buf_len == 0)
1345                 return;
1346
1347         total_size = buf_len;
1348
1349         get_fat_cmd.size = sizeof(struct be_cmd_req_get_fat) + 60*1024;
1350         get_fat_cmd.va = pci_alloc_consistent(adapter->pdev,
1351                         get_fat_cmd.size,
1352                         &get_fat_cmd.dma);
1353         if (!get_fat_cmd.va) {
1354                 status = -ENOMEM;
1355                 dev_err(&adapter->pdev->dev,
1356                 "Memory allocation failure while retrieving FAT data\n");
1357                 return;
1358         }
1359
1360         spin_lock_bh(&adapter->mcc_lock);
1361
1362         while (total_size) {
1363                 buf_size = min(total_size, (u32)60*1024);
1364                 total_size -= buf_size;
1365
1366                 wrb = wrb_from_mccq(adapter);
1367                 if (!wrb) {
1368                         status = -EBUSY;
1369                         goto err;
1370                 }
1371                 req = get_fat_cmd.va;
1372
1373                 payload_len = sizeof(struct be_cmd_req_get_fat) + buf_size;
1374                 be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
1375                                 OPCODE_COMMON_MANAGE_FAT, payload_len, wrb,
1376                                 &get_fat_cmd);
1377
1378                 req->fat_operation = cpu_to_le32(RETRIEVE_FAT);
1379                 req->read_log_offset = cpu_to_le32(log_offset);
1380                 req->read_log_length = cpu_to_le32(buf_size);
1381                 req->data_buffer_size = cpu_to_le32(buf_size);
1382
1383                 status = be_mcc_notify_wait(adapter);
1384                 if (!status) {
1385                         struct be_cmd_resp_get_fat *resp = get_fat_cmd.va;
1386                         memcpy(buf + offset,
1387                                 resp->data_buffer,
1388                                 le32_to_cpu(resp->read_log_length));
1389                 } else {
1390                         dev_err(&adapter->pdev->dev, "FAT Table Retrieve error\n");
1391                         goto err;
1392                 }
1393                 offset += buf_size;
1394                 log_offset += buf_size;
1395         }
1396 err:
1397         pci_free_consistent(adapter->pdev, get_fat_cmd.size,
1398                         get_fat_cmd.va,
1399                         get_fat_cmd.dma);
1400         spin_unlock_bh(&adapter->mcc_lock);
1401 }
1402
1403 /* Uses synchronous mcc */
1404 int be_cmd_get_fw_ver(struct be_adapter *adapter, char *fw_ver,
1405                         char *fw_on_flash)
1406 {
1407         struct be_mcc_wrb *wrb;
1408         struct be_cmd_req_get_fw_version *req;
1409         int status;
1410
1411         spin_lock_bh(&adapter->mcc_lock);
1412
1413         wrb = wrb_from_mccq(adapter);
1414         if (!wrb) {
1415                 status = -EBUSY;
1416                 goto err;
1417         }
1418
1419         req = embedded_payload(wrb);
1420
1421         be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
1422                 OPCODE_COMMON_GET_FW_VERSION, sizeof(*req), wrb, NULL);
1423         status = be_mcc_notify_wait(adapter);
1424         if (!status) {
1425                 struct be_cmd_resp_get_fw_version *resp = embedded_payload(wrb);
1426                 strcpy(fw_ver, resp->firmware_version_string);
1427                 if (fw_on_flash)
1428                         strcpy(fw_on_flash, resp->fw_on_flash_version_string);
1429         }
1430 err:
1431         spin_unlock_bh(&adapter->mcc_lock);
1432         return status;
1433 }
1434
1435 /* set the EQ delay interval of an EQ to specified value
1436  * Uses async mcc
1437  */
1438 int be_cmd_modify_eqd(struct be_adapter *adapter, u32 eq_id, u32 eqd)
1439 {
1440         struct be_mcc_wrb *wrb;
1441         struct be_cmd_req_modify_eq_delay *req;
1442         int status = 0;
1443
1444         spin_lock_bh(&adapter->mcc_lock);
1445
1446         wrb = wrb_from_mccq(adapter);
1447         if (!wrb) {
1448                 status = -EBUSY;
1449                 goto err;
1450         }
1451         req = embedded_payload(wrb);
1452
1453         be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
1454                 OPCODE_COMMON_MODIFY_EQ_DELAY, sizeof(*req), wrb, NULL);
1455
1456         req->num_eq = cpu_to_le32(1);
1457         req->delay[0].eq_id = cpu_to_le32(eq_id);
1458         req->delay[0].phase = 0;
1459         req->delay[0].delay_multiplier = cpu_to_le32(eqd);
1460
1461         be_mcc_notify(adapter);
1462
1463 err:
1464         spin_unlock_bh(&adapter->mcc_lock);
1465         return status;
1466 }
1467
1468 /* Uses sycnhronous mcc */
1469 int be_cmd_vlan_config(struct be_adapter *adapter, u32 if_id, u16 *vtag_array,
1470                         u32 num, bool untagged, bool promiscuous)
1471 {
1472         struct be_mcc_wrb *wrb;
1473         struct be_cmd_req_vlan_config *req;
1474         int status;
1475
1476         spin_lock_bh(&adapter->mcc_lock);
1477
1478         wrb = wrb_from_mccq(adapter);
1479         if (!wrb) {
1480                 status = -EBUSY;
1481                 goto err;
1482         }
1483         req = embedded_payload(wrb);
1484
1485         be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
1486                 OPCODE_COMMON_NTWK_VLAN_CONFIG, sizeof(*req), wrb, NULL);
1487
1488         req->interface_id = if_id;
1489         req->promiscuous = promiscuous;
1490         req->untagged = untagged;
1491         req->num_vlan = num;
1492         if (!promiscuous) {
1493                 memcpy(req->normal_vlan, vtag_array,
1494                         req->num_vlan * sizeof(vtag_array[0]));
1495         }
1496
1497         status = be_mcc_notify_wait(adapter);
1498
1499 err:
1500         spin_unlock_bh(&adapter->mcc_lock);
1501         return status;
1502 }
1503
1504 int be_cmd_rx_filter(struct be_adapter *adapter, u32 flags, u32 value)
1505 {
1506         struct be_mcc_wrb *wrb;
1507         struct be_dma_mem *mem = &adapter->rx_filter;
1508         struct be_cmd_req_rx_filter *req = mem->va;
1509         int status;
1510
1511         spin_lock_bh(&adapter->mcc_lock);
1512
1513         wrb = wrb_from_mccq(adapter);
1514         if (!wrb) {
1515                 status = -EBUSY;
1516                 goto err;
1517         }
1518         memset(req, 0, sizeof(*req));
1519         be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
1520                                 OPCODE_COMMON_NTWK_RX_FILTER, sizeof(*req),
1521                                 wrb, mem);
1522
1523         req->if_id = cpu_to_le32(adapter->if_handle);
1524         if (flags & IFF_PROMISC) {
1525                 req->if_flags_mask = cpu_to_le32(BE_IF_FLAGS_PROMISCUOUS |
1526                                         BE_IF_FLAGS_VLAN_PROMISCUOUS);
1527                 if (value == ON)
1528                         req->if_flags = cpu_to_le32(BE_IF_FLAGS_PROMISCUOUS |
1529                                                 BE_IF_FLAGS_VLAN_PROMISCUOUS);
1530         } else if (flags & IFF_ALLMULTI) {
1531                 req->if_flags_mask = req->if_flags =
1532                                 cpu_to_le32(BE_IF_FLAGS_MCAST_PROMISCUOUS);
1533         } else {
1534                 struct netdev_hw_addr *ha;
1535                 int i = 0;
1536
1537                 req->if_flags_mask = req->if_flags =
1538                                 cpu_to_le32(BE_IF_FLAGS_MULTICAST);
1539                 req->mcast_num = cpu_to_le16(netdev_mc_count(adapter->netdev));
1540                 netdev_for_each_mc_addr(ha, adapter->netdev)
1541                         memcpy(req->mcast_mac[i++].byte, ha->addr, ETH_ALEN);
1542         }
1543
1544         status = be_mcc_notify_wait(adapter);
1545 err:
1546         spin_unlock_bh(&adapter->mcc_lock);
1547         return status;
1548 }
1549
1550 /* Uses synchrounous mcc */
1551 int be_cmd_set_flow_control(struct be_adapter *adapter, u32 tx_fc, u32 rx_fc)
1552 {
1553         struct be_mcc_wrb *wrb;
1554         struct be_cmd_req_set_flow_control *req;
1555         int status;
1556
1557         spin_lock_bh(&adapter->mcc_lock);
1558
1559         wrb = wrb_from_mccq(adapter);
1560         if (!wrb) {
1561                 status = -EBUSY;
1562                 goto err;
1563         }
1564         req = embedded_payload(wrb);
1565
1566         be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
1567                 OPCODE_COMMON_SET_FLOW_CONTROL, sizeof(*req), wrb, NULL);
1568
1569         req->tx_flow_control = cpu_to_le16((u16)tx_fc);
1570         req->rx_flow_control = cpu_to_le16((u16)rx_fc);
1571
1572         status = be_mcc_notify_wait(adapter);
1573
1574 err:
1575         spin_unlock_bh(&adapter->mcc_lock);
1576         return status;
1577 }
1578
1579 /* Uses sycn mcc */
1580 int be_cmd_get_flow_control(struct be_adapter *adapter, u32 *tx_fc, u32 *rx_fc)
1581 {
1582         struct be_mcc_wrb *wrb;
1583         struct be_cmd_req_get_flow_control *req;
1584         int status;
1585
1586         spin_lock_bh(&adapter->mcc_lock);
1587
1588         wrb = wrb_from_mccq(adapter);
1589         if (!wrb) {
1590                 status = -EBUSY;
1591                 goto err;
1592         }
1593         req = embedded_payload(wrb);
1594
1595         be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
1596                 OPCODE_COMMON_GET_FLOW_CONTROL, sizeof(*req), wrb, NULL);
1597
1598         status = be_mcc_notify_wait(adapter);
1599         if (!status) {
1600                 struct be_cmd_resp_get_flow_control *resp =
1601                                                 embedded_payload(wrb);
1602                 *tx_fc = le16_to_cpu(resp->tx_flow_control);
1603                 *rx_fc = le16_to_cpu(resp->rx_flow_control);
1604         }
1605
1606 err:
1607         spin_unlock_bh(&adapter->mcc_lock);
1608         return status;
1609 }
1610
1611 /* Uses mbox */
1612 int be_cmd_query_fw_cfg(struct be_adapter *adapter, u32 *port_num,
1613                 u32 *mode, u32 *caps)
1614 {
1615         struct be_mcc_wrb *wrb;
1616         struct be_cmd_req_query_fw_cfg *req;
1617         int status;
1618
1619         if (mutex_lock_interruptible(&adapter->mbox_lock))
1620                 return -1;
1621
1622         wrb = wrb_from_mbox(adapter);
1623         req = embedded_payload(wrb);
1624
1625         be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
1626                 OPCODE_COMMON_QUERY_FIRMWARE_CONFIG, sizeof(*req), wrb, NULL);
1627
1628         status = be_mbox_notify_wait(adapter);
1629         if (!status) {
1630                 struct be_cmd_resp_query_fw_cfg *resp = embedded_payload(wrb);
1631                 *port_num = le32_to_cpu(resp->phys_port);
1632                 *mode = le32_to_cpu(resp->function_mode);
1633                 *caps = le32_to_cpu(resp->function_caps);
1634         }
1635
1636         mutex_unlock(&adapter->mbox_lock);
1637         return status;
1638 }
1639
1640 /* Uses mbox */
1641 int be_cmd_reset_function(struct be_adapter *adapter)
1642 {
1643         struct be_mcc_wrb *wrb;
1644         struct be_cmd_req_hdr *req;
1645         int status;
1646
1647         if (mutex_lock_interruptible(&adapter->mbox_lock))
1648                 return -1;
1649
1650         wrb = wrb_from_mbox(adapter);
1651         req = embedded_payload(wrb);
1652
1653         be_wrb_cmd_hdr_prepare(req, CMD_SUBSYSTEM_COMMON,
1654                 OPCODE_COMMON_FUNCTION_RESET, sizeof(*req), wrb, NULL);
1655
1656         status = be_mbox_notify_wait(adapter);
1657
1658         mutex_unlock(&adapter->mbox_lock);
1659         return status;
1660 }
1661
1662 int be_cmd_rss_config(struct be_adapter *adapter, u8 *rsstable, u16 table_size)
1663 {
1664         struct be_mcc_wrb *wrb;
1665         struct be_cmd_req_rss_config *req;
1666         u32 myhash[10] = {0x0123, 0x4567, 0x89AB, 0xCDEF, 0x01EF,
1667                         0x0123, 0x4567, 0x89AB, 0xCDEF, 0x01EF};
1668         int status;
1669
1670         if (mutex_lock_interruptible(&adapter->mbox_lock))
1671                 return -1;
1672
1673         wrb = wrb_from_mbox(adapter);
1674         req = embedded_payload(wrb);
1675
1676         be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_ETH,
1677                 OPCODE_ETH_RSS_CONFIG, sizeof(*req), wrb, NULL);
1678
1679         req->if_id = cpu_to_le32(adapter->if_handle);
1680         req->enable_rss = cpu_to_le16(RSS_ENABLE_TCP_IPV4 | RSS_ENABLE_IPV4);
1681         req->cpu_table_size_log2 = cpu_to_le16(fls(table_size) - 1);
1682         memcpy(req->cpu_table, rsstable, table_size);
1683         memcpy(req->hash, myhash, sizeof(myhash));
1684         be_dws_cpu_to_le(req->hash, sizeof(req->hash));
1685
1686         status = be_mbox_notify_wait(adapter);
1687
1688         mutex_unlock(&adapter->mbox_lock);
1689         return status;
1690 }
1691
1692 /* Uses sync mcc */
1693 int be_cmd_set_beacon_state(struct be_adapter *adapter, u8 port_num,
1694                         u8 bcn, u8 sts, u8 state)
1695 {
1696         struct be_mcc_wrb *wrb;
1697         struct be_cmd_req_enable_disable_beacon *req;
1698         int status;
1699
1700         spin_lock_bh(&adapter->mcc_lock);
1701
1702         wrb = wrb_from_mccq(adapter);
1703         if (!wrb) {
1704                 status = -EBUSY;
1705                 goto err;
1706         }
1707         req = embedded_payload(wrb);
1708
1709         be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
1710                 OPCODE_COMMON_ENABLE_DISABLE_BEACON, sizeof(*req), wrb, NULL);
1711
1712         req->port_num = port_num;
1713         req->beacon_state = state;
1714         req->beacon_duration = bcn;
1715         req->status_duration = sts;
1716
1717         status = be_mcc_notify_wait(adapter);
1718
1719 err:
1720         spin_unlock_bh(&adapter->mcc_lock);
1721         return status;
1722 }
1723
1724 /* Uses sync mcc */
1725 int be_cmd_get_beacon_state(struct be_adapter *adapter, u8 port_num, u32 *state)
1726 {
1727         struct be_mcc_wrb *wrb;
1728         struct be_cmd_req_get_beacon_state *req;
1729         int status;
1730
1731         spin_lock_bh(&adapter->mcc_lock);
1732
1733         wrb = wrb_from_mccq(adapter);
1734         if (!wrb) {
1735                 status = -EBUSY;
1736                 goto err;
1737         }
1738         req = embedded_payload(wrb);
1739
1740         be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
1741                 OPCODE_COMMON_GET_BEACON_STATE, sizeof(*req), wrb, NULL);
1742
1743         req->port_num = port_num;
1744
1745         status = be_mcc_notify_wait(adapter);
1746         if (!status) {
1747                 struct be_cmd_resp_get_beacon_state *resp =
1748                                                 embedded_payload(wrb);
1749                 *state = resp->beacon_state;
1750         }
1751
1752 err:
1753         spin_unlock_bh(&adapter->mcc_lock);
1754         return status;
1755 }
1756
1757 int lancer_cmd_write_object(struct be_adapter *adapter, struct be_dma_mem *cmd,
1758                         u32 data_size, u32 data_offset, const char *obj_name,
1759                         u32 *data_written, u8 *addn_status)
1760 {
1761         struct be_mcc_wrb *wrb;
1762         struct lancer_cmd_req_write_object *req;
1763         struct lancer_cmd_resp_write_object *resp;
1764         void *ctxt = NULL;
1765         int status;
1766
1767         spin_lock_bh(&adapter->mcc_lock);
1768         adapter->flash_status = 0;
1769
1770         wrb = wrb_from_mccq(adapter);
1771         if (!wrb) {
1772                 status = -EBUSY;
1773                 goto err_unlock;
1774         }
1775
1776         req = embedded_payload(wrb);
1777
1778         be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
1779                                 OPCODE_COMMON_WRITE_OBJECT,
1780                                 sizeof(struct lancer_cmd_req_write_object), wrb,
1781                                 NULL);
1782
1783         ctxt = &req->context;
1784         AMAP_SET_BITS(struct amap_lancer_write_obj_context,
1785                         write_length, ctxt, data_size);
1786
1787         if (data_size == 0)
1788                 AMAP_SET_BITS(struct amap_lancer_write_obj_context,
1789                                 eof, ctxt, 1);
1790         else
1791                 AMAP_SET_BITS(struct amap_lancer_write_obj_context,
1792                                 eof, ctxt, 0);
1793
1794         be_dws_cpu_to_le(ctxt, sizeof(req->context));
1795         req->write_offset = cpu_to_le32(data_offset);
1796         strcpy(req->object_name, obj_name);
1797         req->descriptor_count = cpu_to_le32(1);
1798         req->buf_len = cpu_to_le32(data_size);
1799         req->addr_low = cpu_to_le32((cmd->dma +
1800                                 sizeof(struct lancer_cmd_req_write_object))
1801                                 & 0xFFFFFFFF);
1802         req->addr_high = cpu_to_le32(upper_32_bits(cmd->dma +
1803                                 sizeof(struct lancer_cmd_req_write_object)));
1804
1805         be_mcc_notify(adapter);
1806         spin_unlock_bh(&adapter->mcc_lock);
1807
1808         if (!wait_for_completion_timeout(&adapter->flash_compl,
1809                         msecs_to_jiffies(12000)))
1810                 status = -1;
1811         else
1812                 status = adapter->flash_status;
1813
1814         resp = embedded_payload(wrb);
1815         if (!status) {
1816                 *data_written = le32_to_cpu(resp->actual_write_len);
1817         } else {
1818                 *addn_status = resp->additional_status;
1819                 status = resp->status;
1820         }
1821
1822         return status;
1823
1824 err_unlock:
1825         spin_unlock_bh(&adapter->mcc_lock);
1826         return status;
1827 }
1828
1829 int be_cmd_write_flashrom(struct be_adapter *adapter, struct be_dma_mem *cmd,
1830                         u32 flash_type, u32 flash_opcode, u32 buf_size)
1831 {
1832         struct be_mcc_wrb *wrb;
1833         struct be_cmd_write_flashrom *req;
1834         int status;
1835
1836         spin_lock_bh(&adapter->mcc_lock);
1837         adapter->flash_status = 0;
1838
1839         wrb = wrb_from_mccq(adapter);
1840         if (!wrb) {
1841                 status = -EBUSY;
1842                 goto err_unlock;
1843         }
1844         req = cmd->va;
1845
1846         be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
1847                 OPCODE_COMMON_WRITE_FLASHROM, cmd->size, wrb, cmd);
1848
1849         req->params.op_type = cpu_to_le32(flash_type);
1850         req->params.op_code = cpu_to_le32(flash_opcode);
1851         req->params.data_buf_size = cpu_to_le32(buf_size);
1852
1853         be_mcc_notify(adapter);
1854         spin_unlock_bh(&adapter->mcc_lock);
1855
1856         if (!wait_for_completion_timeout(&adapter->flash_compl,
1857                         msecs_to_jiffies(40000)))
1858                 status = -1;
1859         else
1860                 status = adapter->flash_status;
1861
1862         return status;
1863
1864 err_unlock:
1865         spin_unlock_bh(&adapter->mcc_lock);
1866         return status;
1867 }
1868
1869 int be_cmd_get_flash_crc(struct be_adapter *adapter, u8 *flashed_crc,
1870                          int offset)
1871 {
1872         struct be_mcc_wrb *wrb;
1873         struct be_cmd_write_flashrom *req;
1874         int status;
1875
1876         spin_lock_bh(&adapter->mcc_lock);
1877
1878         wrb = wrb_from_mccq(adapter);
1879         if (!wrb) {
1880                 status = -EBUSY;
1881                 goto err;
1882         }
1883         req = embedded_payload(wrb);
1884
1885         be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
1886                 OPCODE_COMMON_READ_FLASHROM, sizeof(*req)+4, wrb, NULL);
1887
1888         req->params.op_type = cpu_to_le32(IMG_TYPE_REDBOOT);
1889         req->params.op_code = cpu_to_le32(FLASHROM_OPER_REPORT);
1890         req->params.offset = cpu_to_le32(offset);
1891         req->params.data_buf_size = cpu_to_le32(0x4);
1892
1893         status = be_mcc_notify_wait(adapter);
1894         if (!status)
1895                 memcpy(flashed_crc, req->params.data_buf, 4);
1896
1897 err:
1898         spin_unlock_bh(&adapter->mcc_lock);
1899         return status;
1900 }
1901
1902 int be_cmd_enable_magic_wol(struct be_adapter *adapter, u8 *mac,
1903                                 struct be_dma_mem *nonemb_cmd)
1904 {
1905         struct be_mcc_wrb *wrb;
1906         struct be_cmd_req_acpi_wol_magic_config *req;
1907         int status;
1908
1909         spin_lock_bh(&adapter->mcc_lock);
1910
1911         wrb = wrb_from_mccq(adapter);
1912         if (!wrb) {
1913                 status = -EBUSY;
1914                 goto err;
1915         }
1916         req = nonemb_cmd->va;
1917
1918         be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_ETH,
1919                 OPCODE_ETH_ACPI_WOL_MAGIC_CONFIG, sizeof(*req), wrb,
1920                 nonemb_cmd);
1921         memcpy(req->magic_mac, mac, ETH_ALEN);
1922
1923         status = be_mcc_notify_wait(adapter);
1924
1925 err:
1926         spin_unlock_bh(&adapter->mcc_lock);
1927         return status;
1928 }
1929
1930 int be_cmd_set_loopback(struct be_adapter *adapter, u8 port_num,
1931                         u8 loopback_type, u8 enable)
1932 {
1933         struct be_mcc_wrb *wrb;
1934         struct be_cmd_req_set_lmode *req;
1935         int status;
1936
1937         spin_lock_bh(&adapter->mcc_lock);
1938
1939         wrb = wrb_from_mccq(adapter);
1940         if (!wrb) {
1941                 status = -EBUSY;
1942                 goto err;
1943         }
1944
1945         req = embedded_payload(wrb);
1946
1947         be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_LOWLEVEL,
1948                         OPCODE_LOWLEVEL_SET_LOOPBACK_MODE, sizeof(*req), wrb,
1949                         NULL);
1950
1951         req->src_port = port_num;
1952         req->dest_port = port_num;
1953         req->loopback_type = loopback_type;
1954         req->loopback_state = enable;
1955
1956         status = be_mcc_notify_wait(adapter);
1957 err:
1958         spin_unlock_bh(&adapter->mcc_lock);
1959         return status;
1960 }
1961
1962 int be_cmd_loopback_test(struct be_adapter *adapter, u32 port_num,
1963                 u32 loopback_type, u32 pkt_size, u32 num_pkts, u64 pattern)
1964 {
1965         struct be_mcc_wrb *wrb;
1966         struct be_cmd_req_loopback_test *req;
1967         int status;
1968
1969         spin_lock_bh(&adapter->mcc_lock);
1970
1971         wrb = wrb_from_mccq(adapter);
1972         if (!wrb) {
1973                 status = -EBUSY;
1974                 goto err;
1975         }
1976
1977         req = embedded_payload(wrb);
1978
1979         be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_LOWLEVEL,
1980                         OPCODE_LOWLEVEL_LOOPBACK_TEST, sizeof(*req), wrb, NULL);
1981         req->hdr.timeout = cpu_to_le32(4);
1982
1983         req->pattern = cpu_to_le64(pattern);
1984         req->src_port = cpu_to_le32(port_num);
1985         req->dest_port = cpu_to_le32(port_num);
1986         req->pkt_size = cpu_to_le32(pkt_size);
1987         req->num_pkts = cpu_to_le32(num_pkts);
1988         req->loopback_type = cpu_to_le32(loopback_type);
1989
1990         status = be_mcc_notify_wait(adapter);
1991         if (!status) {
1992                 struct be_cmd_resp_loopback_test *resp = embedded_payload(wrb);
1993                 status = le32_to_cpu(resp->status);
1994         }
1995
1996 err:
1997         spin_unlock_bh(&adapter->mcc_lock);
1998         return status;
1999 }
2000
2001 int be_cmd_ddr_dma_test(struct be_adapter *adapter, u64 pattern,
2002                                 u32 byte_cnt, struct be_dma_mem *cmd)
2003 {
2004         struct be_mcc_wrb *wrb;
2005         struct be_cmd_req_ddrdma_test *req;
2006         int status;
2007         int i, j = 0;
2008
2009         spin_lock_bh(&adapter->mcc_lock);
2010
2011         wrb = wrb_from_mccq(adapter);
2012         if (!wrb) {
2013                 status = -EBUSY;
2014                 goto err;
2015         }
2016         req = cmd->va;
2017         be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_LOWLEVEL,
2018                         OPCODE_LOWLEVEL_HOST_DDR_DMA, cmd->size, wrb, cmd);
2019
2020         req->pattern = cpu_to_le64(pattern);
2021         req->byte_count = cpu_to_le32(byte_cnt);
2022         for (i = 0; i < byte_cnt; i++) {
2023                 req->snd_buff[i] = (u8)(pattern >> (j*8));
2024                 j++;
2025                 if (j > 7)
2026                         j = 0;
2027         }
2028
2029         status = be_mcc_notify_wait(adapter);
2030
2031         if (!status) {
2032                 struct be_cmd_resp_ddrdma_test *resp;
2033                 resp = cmd->va;
2034                 if ((memcmp(resp->rcv_buff, req->snd_buff, byte_cnt) != 0) ||
2035                                 resp->snd_err) {
2036                         status = -1;
2037                 }
2038         }
2039
2040 err:
2041         spin_unlock_bh(&adapter->mcc_lock);
2042         return status;
2043 }
2044
2045 int be_cmd_get_seeprom_data(struct be_adapter *adapter,
2046                                 struct be_dma_mem *nonemb_cmd)
2047 {
2048         struct be_mcc_wrb *wrb;
2049         struct be_cmd_req_seeprom_read *req;
2050         struct be_sge *sge;
2051         int status;
2052
2053         spin_lock_bh(&adapter->mcc_lock);
2054
2055         wrb = wrb_from_mccq(adapter);
2056         if (!wrb) {
2057                 status = -EBUSY;
2058                 goto err;
2059         }
2060         req = nonemb_cmd->va;
2061         sge = nonembedded_sgl(wrb);
2062
2063         be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
2064                         OPCODE_COMMON_SEEPROM_READ, sizeof(*req), wrb,
2065                         nonemb_cmd);
2066
2067         status = be_mcc_notify_wait(adapter);
2068
2069 err:
2070         spin_unlock_bh(&adapter->mcc_lock);
2071         return status;
2072 }
2073
2074 int be_cmd_get_phy_info(struct be_adapter *adapter,
2075                                 struct be_phy_info *phy_info)
2076 {
2077         struct be_mcc_wrb *wrb;
2078         struct be_cmd_req_get_phy_info *req;
2079         struct be_dma_mem cmd;
2080         int status;
2081
2082         spin_lock_bh(&adapter->mcc_lock);
2083
2084         wrb = wrb_from_mccq(adapter);
2085         if (!wrb) {
2086                 status = -EBUSY;
2087                 goto err;
2088         }
2089         cmd.size = sizeof(struct be_cmd_req_get_phy_info);
2090         cmd.va = pci_alloc_consistent(adapter->pdev, cmd.size,
2091                                         &cmd.dma);
2092         if (!cmd.va) {
2093                 dev_err(&adapter->pdev->dev, "Memory alloc failure\n");
2094                 status = -ENOMEM;
2095                 goto err;
2096         }
2097
2098         req = cmd.va;
2099
2100         be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
2101                         OPCODE_COMMON_GET_PHY_DETAILS, sizeof(*req),
2102                         wrb, &cmd);
2103
2104         status = be_mcc_notify_wait(adapter);
2105         if (!status) {
2106                 struct be_phy_info *resp_phy_info =
2107                                 cmd.va + sizeof(struct be_cmd_req_hdr);
2108                 phy_info->phy_type = le16_to_cpu(resp_phy_info->phy_type);
2109                 phy_info->interface_type =
2110                         le16_to_cpu(resp_phy_info->interface_type);
2111         }
2112         pci_free_consistent(adapter->pdev, cmd.size,
2113                                 cmd.va, cmd.dma);
2114 err:
2115         spin_unlock_bh(&adapter->mcc_lock);
2116         return status;
2117 }
2118
2119 int be_cmd_set_qos(struct be_adapter *adapter, u32 bps, u32 domain)
2120 {
2121         struct be_mcc_wrb *wrb;
2122         struct be_cmd_req_set_qos *req;
2123         int status;
2124
2125         spin_lock_bh(&adapter->mcc_lock);
2126
2127         wrb = wrb_from_mccq(adapter);
2128         if (!wrb) {
2129                 status = -EBUSY;
2130                 goto err;
2131         }
2132
2133         req = embedded_payload(wrb);
2134
2135         be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
2136                         OPCODE_COMMON_SET_QOS, sizeof(*req), wrb, NULL);
2137
2138         req->hdr.domain = domain;
2139         req->valid_bits = cpu_to_le32(BE_QOS_BITS_NIC);
2140         req->max_bps_nic = cpu_to_le32(bps);
2141
2142         status = be_mcc_notify_wait(adapter);
2143
2144 err:
2145         spin_unlock_bh(&adapter->mcc_lock);
2146         return status;
2147 }
2148
2149 int be_cmd_get_cntl_attributes(struct be_adapter *adapter)
2150 {
2151         struct be_mcc_wrb *wrb;
2152         struct be_cmd_req_cntl_attribs *req;
2153         struct be_cmd_resp_cntl_attribs *resp;
2154         int status;
2155         int payload_len = max(sizeof(*req), sizeof(*resp));
2156         struct mgmt_controller_attrib *attribs;
2157         struct be_dma_mem attribs_cmd;
2158
2159         memset(&attribs_cmd, 0, sizeof(struct be_dma_mem));
2160         attribs_cmd.size = sizeof(struct be_cmd_resp_cntl_attribs);
2161         attribs_cmd.va = pci_alloc_consistent(adapter->pdev, attribs_cmd.size,
2162                                                 &attribs_cmd.dma);
2163         if (!attribs_cmd.va) {
2164                 dev_err(&adapter->pdev->dev,
2165                                 "Memory allocation failure\n");
2166                 return -ENOMEM;
2167         }
2168
2169         if (mutex_lock_interruptible(&adapter->mbox_lock))
2170                 return -1;
2171
2172         wrb = wrb_from_mbox(adapter);
2173         if (!wrb) {
2174                 status = -EBUSY;
2175                 goto err;
2176         }
2177         req = attribs_cmd.va;
2178
2179         be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
2180                          OPCODE_COMMON_GET_CNTL_ATTRIBUTES, payload_len, wrb,
2181                         &attribs_cmd);
2182
2183         status = be_mbox_notify_wait(adapter);
2184         if (!status) {
2185                 attribs = attribs_cmd.va + sizeof(struct be_cmd_resp_hdr);
2186                 adapter->hba_port_num = attribs->hba_attribs.phy_port;
2187         }
2188
2189 err:
2190         mutex_unlock(&adapter->mbox_lock);
2191         pci_free_consistent(adapter->pdev, attribs_cmd.size, attribs_cmd.va,
2192                                         attribs_cmd.dma);
2193         return status;
2194 }
2195
2196 /* Uses mbox */
2197 int be_cmd_req_native_mode(struct be_adapter *adapter)
2198 {
2199         struct be_mcc_wrb *wrb;
2200         struct be_cmd_req_set_func_cap *req;
2201         int status;
2202
2203         if (mutex_lock_interruptible(&adapter->mbox_lock))
2204                 return -1;
2205
2206         wrb = wrb_from_mbox(adapter);
2207         if (!wrb) {
2208                 status = -EBUSY;
2209                 goto err;
2210         }
2211
2212         req = embedded_payload(wrb);
2213
2214         be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
2215                 OPCODE_COMMON_SET_DRIVER_FUNCTION_CAP, sizeof(*req), wrb, NULL);
2216
2217         req->valid_cap_flags = cpu_to_le32(CAPABILITY_SW_TIMESTAMPS |
2218                                 CAPABILITY_BE3_NATIVE_ERX_API);
2219         req->cap_flags = cpu_to_le32(CAPABILITY_BE3_NATIVE_ERX_API);
2220
2221         status = be_mbox_notify_wait(adapter);
2222         if (!status) {
2223                 struct be_cmd_resp_set_func_cap *resp = embedded_payload(wrb);
2224                 adapter->be3_native = le32_to_cpu(resp->cap_flags) &
2225                                         CAPABILITY_BE3_NATIVE_ERX_API;
2226         }
2227 err:
2228         mutex_unlock(&adapter->mbox_lock);
2229         return status;
2230 }