2 * Copyright (C) 2005 - 2014 Emulex
5 * This program is free software; you can redistribute it and/or
6 * modify it under the terms of the GNU General Public License version 2
7 * as published by the Free Software Foundation. The full GNU General
8 * Public License is included in this distribution in the file called COPYING.
10 * Contact Information:
11 * linux-drivers@emulex.com
15 * Costa Mesa, CA 92626
18 /********* Mailbox door bell *************/
19 /* Used for driver communication with the FW.
20 * The software must write this register twice to post any command. First,
21 * it writes the register with hi=1 and the upper bits of the physical address
22 * for the MAILBOX structure. Software must poll the ready bit until this
23 * is acknowledged. Then, sotware writes the register with hi=0 with the lower
24 * bits in the address. It must poll the ready bit until the command is
25 * complete. Upon completion, the MAILBOX will contain a valid completion
28 #define MPU_MAILBOX_DB_OFFSET 0x160
29 #define MPU_MAILBOX_DB_RDY_MASK 0x1 /* bit 0 */
30 #define MPU_MAILBOX_DB_HI_MASK 0x2 /* bit 1 */
32 #define MPU_EP_CONTROL 0
34 /********** MPU semphore: used for SH & BE *************/
35 #define SLIPORT_SEMAPHORE_OFFSET_BEx 0xac /* CSR BAR offset */
36 #define SLIPORT_SEMAPHORE_OFFSET_SH 0x94 /* PCI-CFG offset */
37 #define POST_STAGE_MASK 0x0000FFFF
38 #define POST_ERR_MASK 0x1
39 #define POST_ERR_SHIFT 31
41 /* MPU semphore POST stage values */
42 #define POST_STAGE_AWAITING_HOST_RDY 0x1 /* FW awaiting goahead from host */
43 #define POST_STAGE_HOST_RDY 0x2 /* Host has given go-ahed to FW */
44 #define POST_STAGE_BE_RESET 0x3 /* Host wants to reset chip */
45 #define POST_STAGE_ARMFW_RDY 0xc000 /* FW is done with POST */
48 /* Lancer SLIPORT registers */
49 #define SLIPORT_STATUS_OFFSET 0x404
50 #define SLIPORT_CONTROL_OFFSET 0x408
51 #define SLIPORT_ERROR1_OFFSET 0x40C
52 #define SLIPORT_ERROR2_OFFSET 0x410
53 #define PHYSDEV_CONTROL_OFFSET 0x414
55 #define SLIPORT_STATUS_ERR_MASK 0x80000000
56 #define SLIPORT_STATUS_DIP_MASK 0x02000000
57 #define SLIPORT_STATUS_RN_MASK 0x01000000
58 #define SLIPORT_STATUS_RDY_MASK 0x00800000
59 #define SLI_PORT_CONTROL_IP_MASK 0x08000000
60 #define PHYSDEV_CONTROL_FW_RESET_MASK 0x00000002
61 #define PHYSDEV_CONTROL_DD_MASK 0x00000004
62 #define PHYSDEV_CONTROL_INP_MASK 0x40000000
64 #define SLIPORT_ERROR_NO_RESOURCE1 0x2
65 #define SLIPORT_ERROR_NO_RESOURCE2 0x9
67 #define SLIPORT_ERROR_FW_RESET1 0x2
68 #define SLIPORT_ERROR_FW_RESET2 0x0
70 /********* Memory BAR register ************/
71 #define PCICFG_MEMBAR_CTRL_INT_CTRL_OFFSET 0xfc
72 /* Host Interrupt Enable, if set interrupts are enabled although "PCI Interrupt
73 * Disable" may still globally block interrupts in addition to individual
74 * interrupt masks; a mechanism for the device driver to block all interrupts
75 * atomically without having to arbitrate for the PCI Interrupt Disable bit
78 #define MEMBAR_CTRL_INT_CTRL_HOSTINTR_MASK (1 << 29) /* bit 29 */
80 /********* PCI Function Capability *********/
81 #define BE_FUNCTION_CAPS_RSS 0x2
82 #define BE_FUNCTION_CAPS_SUPER_NIC 0x40
84 /********* Power management (WOL) **********/
85 #define PCICFG_PM_CONTROL_OFFSET 0x44
86 #define PCICFG_PM_CONTROL_MASK 0x108 /* bits 3 & 8 */
88 /********* Online Control Registers *******/
89 #define PCICFG_ONLINE0 0xB0
90 #define PCICFG_ONLINE1 0xB4
92 /********* UE Status and Mask Registers ***/
93 #define PCICFG_UE_STATUS_LOW 0xA0
94 #define PCICFG_UE_STATUS_HIGH 0xA4
95 #define PCICFG_UE_STATUS_LOW_MASK 0xA8
96 #define PCICFG_UE_STATUS_HI_MASK 0xAC
98 /******** SLI_INTF ***********************/
99 #define SLI_INTF_REG_OFFSET 0x58
100 #define SLI_INTF_VALID_MASK 0xE0000000
101 #define SLI_INTF_VALID 0xC0000000
102 #define SLI_INTF_HINT2_MASK 0x1F000000
103 #define SLI_INTF_HINT2_SHIFT 24
104 #define SLI_INTF_HINT1_MASK 0x00FF0000
105 #define SLI_INTF_HINT1_SHIFT 16
106 #define SLI_INTF_FAMILY_MASK 0x00000F00
107 #define SLI_INTF_FAMILY_SHIFT 8
108 #define SLI_INTF_IF_TYPE_MASK 0x0000F000
109 #define SLI_INTF_IF_TYPE_SHIFT 12
110 #define SLI_INTF_REV_MASK 0x000000F0
111 #define SLI_INTF_REV_SHIFT 4
112 #define SLI_INTF_FT_MASK 0x00000001
114 #define SLI_INTF_TYPE_2 2
115 #define SLI_INTF_TYPE_3 3
117 /********* ISR0 Register offset **********/
118 #define CEV_ISR0_OFFSET 0xC18
119 #define CEV_ISR_SIZE 4
121 /********* Event Q door bell *************/
122 #define DB_EQ_OFFSET DB_CQ_OFFSET
123 #define DB_EQ_RING_ID_MASK 0x1FF /* bits 0 - 8 */
124 #define DB_EQ_RING_ID_EXT_MASK 0x3e00 /* bits 9-13 */
125 #define DB_EQ_RING_ID_EXT_MASK_SHIFT (2) /* qid bits 9-13 placing at 11-15 */
127 /* Clear the interrupt for this eq */
128 #define DB_EQ_CLR_SHIFT (9) /* bit 9 */
130 #define DB_EQ_EVNT_SHIFT (10) /* bit 10 */
131 /* Number of event entries processed */
132 #define DB_EQ_NUM_POPPED_SHIFT (16) /* bits 16 - 28 */
134 #define DB_EQ_REARM_SHIFT (29) /* bit 29 */
136 /********* Compl Q door bell *************/
137 #define DB_CQ_OFFSET 0x120
138 #define DB_CQ_RING_ID_MASK 0x3FF /* bits 0 - 9 */
139 #define DB_CQ_RING_ID_EXT_MASK 0x7C00 /* bits 10-14 */
140 #define DB_CQ_RING_ID_EXT_MASK_SHIFT (1) /* qid bits 10-14
143 /* Number of event entries processed */
144 #define DB_CQ_NUM_POPPED_SHIFT (16) /* bits 16 - 28 */
146 #define DB_CQ_REARM_SHIFT (29) /* bit 29 */
148 /********** TX ULP door bell *************/
149 #define DB_TXULP1_OFFSET 0x60
150 #define DB_TXULP_RING_ID_MASK 0x7FF /* bits 0 - 10 */
151 /* Number of tx entries posted */
152 #define DB_TXULP_NUM_POSTED_SHIFT (16) /* bits 16 - 29 */
153 #define DB_TXULP_NUM_POSTED_MASK 0x3FFF /* bits 16 - 29 */
155 /********** RQ(erx) door bell ************/
156 #define DB_RQ_OFFSET 0x100
157 #define DB_RQ_RING_ID_MASK 0x3FF /* bits 0 - 9 */
158 /* Number of rx frags posted */
159 #define DB_RQ_NUM_POSTED_SHIFT (24) /* bits 24 - 31 */
161 /********** MCC door bell ************/
162 #define DB_MCCQ_OFFSET 0x140
163 #define DB_MCCQ_RING_ID_MASK 0x7FF /* bits 0 - 10 */
164 /* Number of entries posted */
165 #define DB_MCCQ_NUM_POSTED_SHIFT (16) /* bits 16 - 29 */
167 /********** SRIOV VF PCICFG OFFSET ********/
168 #define SRIOV_VF_PCICFG_OFFSET (4096)
170 /********** FAT TABLE ********/
171 #define RETRIEVE_FAT 0
174 /* Flashrom related descriptors */
175 #define MAX_FLASH_COMP 32
176 #define IMAGE_TYPE_FIRMWARE 160
177 #define IMAGE_TYPE_BOOTCODE 224
178 #define IMAGE_TYPE_OPTIONROM 32
180 #define NUM_FLASHDIR_ENTRIES 32
182 #define OPTYPE_ISCSI_ACTIVE 0
183 #define OPTYPE_REDBOOT 1
184 #define OPTYPE_BIOS 2
185 #define OPTYPE_PXE_BIOS 3
186 #define OPTYPE_FCOE_BIOS 8
187 #define OPTYPE_ISCSI_BACKUP 9
188 #define OPTYPE_FCOE_FW_ACTIVE 10
189 #define OPTYPE_FCOE_FW_BACKUP 11
190 #define OPTYPE_NCSI_FW 13
191 #define OPTYPE_REDBOOT_DIR 18
192 #define OPTYPE_REDBOOT_CONFIG 19
193 #define OPTYPE_SH_PHY_FW 21
194 #define OPTYPE_FLASHISM_JUMPVECTOR 22
195 #define OPTYPE_UFI_DIR 23
196 #define OPTYPE_PHY_FW 99
199 #define FLASHROM_OPER_PHY_FLASH 9
200 #define FLASHROM_OPER_PHY_SAVE 10
201 #define FLASHROM_OPER_FLASH 1
202 #define FLASHROM_OPER_SAVE 2
203 #define FLASHROM_OPER_REPORT 4
205 #define FLASH_IMAGE_MAX_SIZE_g2 (1310720) /* Max firmware image size */
206 #define FLASH_BIOS_IMAGE_MAX_SIZE_g2 (262144) /* Max OPTION ROM image sz */
207 #define FLASH_REDBOOT_IMAGE_MAX_SIZE_g2 (262144) /* Max Redboot image sz */
208 #define FLASH_IMAGE_MAX_SIZE_g3 (2097152) /* Max firmware image size */
209 #define FLASH_BIOS_IMAGE_MAX_SIZE_g3 (524288) /* Max OPTION ROM image sz */
210 #define FLASH_REDBOOT_IMAGE_MAX_SIZE_g3 (1048576) /* Max Redboot image sz */
211 #define FLASH_NCSI_IMAGE_MAX_SIZE_g3 (262144)
212 #define FLASH_PHY_FW_IMAGE_MAX_SIZE_g3 262144
214 #define FLASH_NCSI_MAGIC (0x16032009)
215 #define FLASH_NCSI_DISABLED (0)
216 #define FLASH_NCSI_ENABLED (1)
218 #define FLASH_NCSI_BITFILE_HDR_OFFSET (0x600000)
220 /* Offsets for components on Flash. */
221 #define FLASH_iSCSI_PRIMARY_IMAGE_START_g2 (1048576)
222 #define FLASH_iSCSI_BACKUP_IMAGE_START_g2 (2359296)
223 #define FLASH_FCoE_PRIMARY_IMAGE_START_g2 (3670016)
224 #define FLASH_FCoE_BACKUP_IMAGE_START_g2 (4980736)
225 #define FLASH_iSCSI_BIOS_START_g2 (7340032)
226 #define FLASH_PXE_BIOS_START_g2 (7864320)
227 #define FLASH_FCoE_BIOS_START_g2 (524288)
228 #define FLASH_REDBOOT_START_g2 (0)
230 #define FLASH_NCSI_START_g3 (15990784)
231 #define FLASH_iSCSI_PRIMARY_IMAGE_START_g3 (2097152)
232 #define FLASH_iSCSI_BACKUP_IMAGE_START_g3 (4194304)
233 #define FLASH_FCoE_PRIMARY_IMAGE_START_g3 (6291456)
234 #define FLASH_FCoE_BACKUP_IMAGE_START_g3 (8388608)
235 #define FLASH_iSCSI_BIOS_START_g3 (12582912)
236 #define FLASH_PXE_BIOS_START_g3 (13107200)
237 #define FLASH_FCoE_BIOS_START_g3 (13631488)
238 #define FLASH_REDBOOT_START_g3 (262144)
239 #define FLASH_PHY_FW_START_g3 1310720
241 #define IMAGE_NCSI 16
242 #define IMAGE_OPTION_ROM_PXE 32
243 #define IMAGE_OPTION_ROM_FCoE 33
244 #define IMAGE_OPTION_ROM_ISCSI 34
245 #define IMAGE_FLASHISM_JUMPVECTOR 48
246 #define IMAGE_FLASH_ISM 49
247 #define IMAGE_JUMP_VECTOR 50
248 #define IMAGE_FIRMWARE_iSCSI 160
249 #define IMAGE_FIRMWARE_COMP_iSCSI 161
250 #define IMAGE_FIRMWARE_FCoE 162
251 #define IMAGE_FIRMWARE_COMP_FCoE 163
252 #define IMAGE_FIRMWARE_BACKUP_iSCSI 176
253 #define IMAGE_FIRMWARE_BACKUP_COMP_iSCSI 177
254 #define IMAGE_FIRMWARE_BACKUP_FCoE 178
255 #define IMAGE_FIRMWARE_BACKUP_COMP_FCoE 179
256 #define IMAGE_FIRMWARE_PHY 192
257 #define IMAGE_REDBOOT_DIR 208
258 #define IMAGE_REDBOOT_CONFIG 209
259 #define IMAGE_UFI_DIR 210
260 #define IMAGE_BOOT_CODE 224
262 /************* Rx Packet Type Encoding **************/
263 #define BE_UNICAST_PACKET 0
264 #define BE_MULTICAST_PACKET 1
265 #define BE_BROADCAST_PACKET 2
266 #define BE_RSVD_PACKET 3
269 * BE descriptors: host memory data structures whose formats
270 * are hardwired in BE silicon.
272 /* Event Queue Descriptor */
273 #define EQ_ENTRY_VALID_MASK 0x1 /* bit 0 */
274 #define EQ_ENTRY_RES_ID_MASK 0xFFFF /* bits 16 - 31 */
275 #define EQ_ENTRY_RES_ID_SHIFT 16
281 /* TX Queue Descriptor */
282 #define ETH_WRB_FRAG_LEN_MASK 0xFFFF
284 u32 frag_pa_hi; /* dword 0 */
285 u32 frag_pa_lo; /* dword 1 */
286 u32 rsvd0; /* dword 2 */
287 u32 frag_len; /* dword 3: bits 0 - 15 */
290 /* Pseudo amap definition for eth_hdr_wrb in which each bit of the
291 * actual structure is defined as a byte : used to calculate
292 * offset/shift/mask of each field */
293 struct amap_eth_hdr_wrb {
294 u8 rsvd0[32]; /* dword 0 */
295 u8 rsvd1[32]; /* dword 1 */
296 u8 complete; /* dword 2 */
310 u8 len[16]; /* dword 3 */
314 struct be_eth_hdr_wrb {
318 /* TX Compl Queue Descriptor */
320 /* Pseudo amap definition for eth_tx_compl in which each bit of the
321 * actual structure is defined as a byte: used to calculate
322 * offset/shift/mask of each field */
323 struct amap_eth_tx_compl {
324 u8 wrb_index[16]; /* dword 0 */
325 u8 ct[2]; /* dword 0 */
326 u8 port[2]; /* dword 0 */
327 u8 rsvd0[8]; /* dword 0 */
328 u8 status[4]; /* dword 0 */
329 u8 user_bytes[16]; /* dword 1 */
330 u8 nwh_bytes[8]; /* dword 1 */
331 u8 lso; /* dword 1 */
332 u8 cast_enc[2]; /* dword 1 */
333 u8 rsvd1[5]; /* dword 1 */
334 u8 rsvd2[32]; /* dword 2 */
335 u8 pkts[16]; /* dword 3 */
336 u8 ringid[11]; /* dword 3 */
337 u8 hash_val[4]; /* dword 3 */
338 u8 valid; /* dword 3 */
341 struct be_eth_tx_compl {
345 /* RX Queue Descriptor */
351 /* RX Compl Queue Descriptor */
353 /* Pseudo amap definition for BE2 and BE3 legacy mode eth_rx_compl in which
354 * each bit of the actual structure is defined as a byte: used to calculate
355 * offset/shift/mask of each field */
356 struct amap_eth_rx_compl_v0 {
357 u8 vlan_tag[16]; /* dword 0 */
358 u8 pktsize[14]; /* dword 0 */
359 u8 port; /* dword 0 */
360 u8 ip_opt; /* dword 0 */
361 u8 err; /* dword 1 */
362 u8 rsshp; /* dword 1 */
363 u8 ipf; /* dword 1 */
364 u8 tcpf; /* dword 1 */
365 u8 udpf; /* dword 1 */
366 u8 ipcksm; /* dword 1 */
367 u8 l4_cksm; /* dword 1 */
368 u8 ip_version; /* dword 1 */
369 u8 macdst[6]; /* dword 1 */
370 u8 vtp; /* dword 1 */
371 u8 ip_frag; /* dword 1 */
372 u8 fragndx[10]; /* dword 1 */
373 u8 ct[2]; /* dword 1 */
375 u8 numfrags[3]; /* dword 1 */
376 u8 rss_flush; /* dword 2 */
377 u8 cast_enc[2]; /* dword 2 */
378 u8 qnq; /* dword 2 */
379 u8 rss_bank; /* dword 2 */
380 u8 rsvd1[23]; /* dword 2 */
381 u8 lro_pkt; /* dword 2 */
382 u8 rsvd2[2]; /* dword 2 */
383 u8 valid; /* dword 2 */
384 u8 rsshash[32]; /* dword 3 */
387 /* Pseudo amap definition for BE3 native mode eth_rx_compl in which
388 * each bit of the actual structure is defined as a byte: used to calculate
389 * offset/shift/mask of each field */
390 struct amap_eth_rx_compl_v1 {
391 u8 vlan_tag[16]; /* dword 0 */
392 u8 pktsize[14]; /* dword 0 */
393 u8 vtp; /* dword 0 */
394 u8 ip_opt; /* dword 0 */
395 u8 err; /* dword 1 */
396 u8 rsshp; /* dword 1 */
397 u8 ipf; /* dword 1 */
398 u8 tcpf; /* dword 1 */
399 u8 udpf; /* dword 1 */
400 u8 ipcksm; /* dword 1 */
401 u8 l4_cksm; /* dword 1 */
402 u8 ip_version; /* dword 1 */
403 u8 macdst[7]; /* dword 1 */
404 u8 rsvd0; /* dword 1 */
405 u8 fragndx[10]; /* dword 1 */
406 u8 ct[2]; /* dword 1 */
408 u8 numfrags[3]; /* dword 1 */
409 u8 rss_flush; /* dword 2 */
410 u8 cast_enc[2]; /* dword 2 */
411 u8 qnq; /* dword 2 */
412 u8 rss_bank; /* dword 2 */
413 u8 port[2]; /* dword 2 */
414 u8 vntagp; /* dword 2 */
415 u8 header_len[8]; /* dword 2 */
416 u8 header_split[2]; /* dword 2 */
417 u8 rsvd1[12]; /* dword 2 */
419 u8 valid; /* dword 2 */
420 u8 rsshash[32]; /* dword 3 */
423 struct be_eth_rx_compl {
427 struct mgmt_hba_attribs {
428 u8 flashrom_version_string[32];
429 u8 manufacturer_name[32];
432 u8 ncsi_ver_string[12];
433 u32 default_extended_timeout;
434 u8 controller_model_number[32];
435 u8 controller_description[64];
436 u8 controller_serial_number[32];
437 u8 ip_version_string[32];
438 u8 firmware_version_string[32];
439 u8 bios_version_string[32];
440 u8 redboot_version_string[32];
441 u8 driver_version_string[32];
442 u8 fw_on_flash_version_string[32];
443 u32 functionalities_supported;
446 u8 generational_guid[16];
448 u16 default_link_down_timeout;
449 u8 iscsi_ver_min_max;
450 u8 multifunction_device;
453 u8 max_domains_supported;
455 u32 firmware_post_status;
460 struct mgmt_controller_attrib {
461 struct mgmt_hba_attribs hba_attribs;
464 u16 pci_sub_vendor_id;
465 u16 pci_sub_system_id;
467 u8 pci_device_number;
468 u8 pci_function_number;
470 u64 unique_identifier;
474 struct controller_id {
482 unsigned long offset;
493 u8 image_version[32];
495 struct flash_file_hdr_g2 {
499 struct controller_id cont_id;
507 struct flash_file_hdr_g3 {
519 struct flash_section_hdr {
528 struct flash_section_hdr_g2 {
537 struct flash_section_entry {
550 struct flash_section_info {
552 struct flash_section_hdr fsec_hdr;
553 struct flash_section_entry fsec_entry[32];
556 struct flash_section_info_g2 {
558 struct flash_section_hdr_g2 fsec_hdr;
559 struct flash_section_entry fsec_entry[32];