2 * Faraday FTGMAC100 Gigabit Ethernet
4 * (C) Copyright 2009-2011 Faraday Technology
5 * Po-Yu Chuang <ratbert@faraday-tech.com>
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License as published by
9 * the Free Software Foundation; either version 2 of the License, or
10 * (at your option) any later version.
12 * This program is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 * GNU General Public License for more details.
17 * You should have received a copy of the GNU General Public License
18 * along with this program; if not, write to the Free Software
19 * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
22 #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
24 #include <linux/dma-mapping.h>
25 #include <linux/etherdevice.h>
26 #include <linux/ethtool.h>
27 #include <linux/interrupt.h>
29 #include <linux/module.h>
30 #include <linux/netdevice.h>
32 #include <linux/phy.h>
33 #include <linux/platform_device.h>
34 #include <linux/property.h>
38 #include "ftgmac100.h"
40 #define DRV_NAME "ftgmac100"
41 #define DRV_VERSION "0.7"
43 #define RX_QUEUE_ENTRIES 256 /* must be power of 2 */
44 #define TX_QUEUE_ENTRIES 512 /* must be power of 2 */
46 #define MAX_PKT_SIZE 1536
47 #define RX_BUF_SIZE MAX_PKT_SIZE /* must be smaller than 0x3fff */
49 /* Min number of tx ring entries before stopping queue */
50 #define TX_THRESHOLD (MAX_SKB_FRAGS + 1)
52 struct ftgmac100_descs {
53 struct ftgmac100_rxdes rxdes[RX_QUEUE_ENTRIES];
54 struct ftgmac100_txdes txdes[TX_QUEUE_ENTRIES];
62 struct ftgmac100_descs *descs;
63 dma_addr_t descs_dma_addr;
66 struct sk_buff *rx_skbs[RX_QUEUE_ENTRIES];
67 unsigned int rx_pointer;
68 u32 rxdes0_edorr_mask;
71 struct sk_buff *tx_skbs[TX_QUEUE_ENTRIES];
72 unsigned int tx_clean_pointer;
73 unsigned int tx_pointer;
74 u32 txdes0_edotr_mask;
76 /* Scratch page to use when rx skb alloc fails */
78 dma_addr_t rx_scratch_dma;
80 /* Component structures */
81 struct net_device *netdev;
83 struct ncsi_dev *ndev;
84 struct napi_struct napi;
85 struct work_struct reset_task;
86 struct mii_bus *mii_bus;
94 bool need_mac_restart;
97 static void ftgmac100_set_rx_ring_base(struct ftgmac100 *priv, dma_addr_t addr)
99 iowrite32(addr, priv->base + FTGMAC100_OFFSET_RXR_BADR);
102 static void ftgmac100_set_rx_buffer_size(struct ftgmac100 *priv,
105 size = FTGMAC100_RBSR_SIZE(size);
106 iowrite32(size, priv->base + FTGMAC100_OFFSET_RBSR);
109 static void ftgmac100_set_normal_prio_tx_ring_base(struct ftgmac100 *priv,
112 iowrite32(addr, priv->base + FTGMAC100_OFFSET_NPTXR_BADR);
115 static void ftgmac100_txdma_normal_prio_start_polling(struct ftgmac100 *priv)
117 iowrite32(1, priv->base + FTGMAC100_OFFSET_NPTXPD);
120 static int ftgmac100_reset_mac(struct ftgmac100 *priv, u32 maccr)
122 struct net_device *netdev = priv->netdev;
125 /* NOTE: reset clears all registers */
126 iowrite32(maccr, priv->base + FTGMAC100_OFFSET_MACCR);
127 iowrite32(maccr | FTGMAC100_MACCR_SW_RST,
128 priv->base + FTGMAC100_OFFSET_MACCR);
129 for (i = 0; i < 50; i++) {
132 maccr = ioread32(priv->base + FTGMAC100_OFFSET_MACCR);
133 if (!(maccr & FTGMAC100_MACCR_SW_RST))
139 netdev_err(netdev, "Hardware reset failed\n");
143 static int ftgmac100_reset_and_config_mac(struct ftgmac100 *priv)
147 switch (priv->cur_speed) {
149 case 0: /* no link */
153 maccr |= FTGMAC100_MACCR_FAST_MODE;
157 maccr |= FTGMAC100_MACCR_GIGA_MODE;
160 netdev_err(priv->netdev, "Unknown speed %d !\n",
165 /* (Re)initialize the queue pointers */
166 priv->rx_pointer = 0;
167 priv->tx_clean_pointer = 0;
168 priv->tx_pointer = 0;
170 /* The doc says reset twice with 10us interval */
171 if (ftgmac100_reset_mac(priv, maccr))
173 usleep_range(10, 1000);
174 return ftgmac100_reset_mac(priv, maccr);
177 static void ftgmac100_set_mac(struct ftgmac100 *priv, const unsigned char *mac)
179 unsigned int maddr = mac[0] << 8 | mac[1];
180 unsigned int laddr = mac[2] << 24 | mac[3] << 16 | mac[4] << 8 | mac[5];
182 iowrite32(maddr, priv->base + FTGMAC100_OFFSET_MAC_MADR);
183 iowrite32(laddr, priv->base + FTGMAC100_OFFSET_MAC_LADR);
186 static void ftgmac100_setup_mac(struct ftgmac100 *priv)
193 addr = device_get_mac_address(priv->dev, mac, ETH_ALEN);
195 ether_addr_copy(priv->netdev->dev_addr, mac);
196 dev_info(priv->dev, "Read MAC address %pM from device tree\n",
201 m = ioread32(priv->base + FTGMAC100_OFFSET_MAC_MADR);
202 l = ioread32(priv->base + FTGMAC100_OFFSET_MAC_LADR);
204 mac[0] = (m >> 8) & 0xff;
206 mac[2] = (l >> 24) & 0xff;
207 mac[3] = (l >> 16) & 0xff;
208 mac[4] = (l >> 8) & 0xff;
211 if (is_valid_ether_addr(mac)) {
212 ether_addr_copy(priv->netdev->dev_addr, mac);
213 dev_info(priv->dev, "Read MAC address %pM from chip\n", mac);
215 eth_hw_addr_random(priv->netdev);
216 dev_info(priv->dev, "Generated random MAC address %pM\n",
217 priv->netdev->dev_addr);
221 static int ftgmac100_set_mac_addr(struct net_device *dev, void *p)
225 ret = eth_prepare_mac_addr_change(dev, p);
229 eth_commit_mac_addr_change(dev, p);
230 ftgmac100_set_mac(netdev_priv(dev), dev->dev_addr);
235 static void ftgmac100_init_hw(struct ftgmac100 *priv)
237 /* setup ring buffer base registers */
238 ftgmac100_set_rx_ring_base(priv,
239 priv->descs_dma_addr +
240 offsetof(struct ftgmac100_descs, rxdes));
241 ftgmac100_set_normal_prio_tx_ring_base(priv,
242 priv->descs_dma_addr +
243 offsetof(struct ftgmac100_descs, txdes));
245 ftgmac100_set_rx_buffer_size(priv, RX_BUF_SIZE);
247 iowrite32(FTGMAC100_APTC_RXPOLL_CNT(1), priv->base + FTGMAC100_OFFSET_APTC);
249 ftgmac100_set_mac(priv, priv->netdev->dev_addr);
252 static void ftgmac100_start_hw(struct ftgmac100 *priv)
254 u32 maccr = ioread32(priv->base + FTGMAC100_OFFSET_MACCR);
256 /* Keep the original GMAC and FAST bits */
257 maccr &= (FTGMAC100_MACCR_FAST_MODE | FTGMAC100_MACCR_GIGA_MODE);
259 /* Add all the main enable bits */
260 maccr |= FTGMAC100_MACCR_TXDMA_EN |
261 FTGMAC100_MACCR_RXDMA_EN |
262 FTGMAC100_MACCR_TXMAC_EN |
263 FTGMAC100_MACCR_RXMAC_EN |
264 FTGMAC100_MACCR_CRC_APD |
265 FTGMAC100_MACCR_PHY_LINK_LEVEL |
266 FTGMAC100_MACCR_RX_RUNT |
267 FTGMAC100_MACCR_RX_BROADPKT;
269 /* Add other bits as needed */
270 if (priv->cur_duplex == DUPLEX_FULL)
271 maccr |= FTGMAC100_MACCR_FULLDUP;
274 iowrite32(maccr, priv->base + FTGMAC100_OFFSET_MACCR);
277 static void ftgmac100_stop_hw(struct ftgmac100 *priv)
279 iowrite32(0, priv->base + FTGMAC100_OFFSET_MACCR);
282 static int ftgmac100_alloc_rx_buf(struct ftgmac100 *priv, unsigned int entry,
283 struct ftgmac100_rxdes *rxdes, gfp_t gfp)
285 struct net_device *netdev = priv->netdev;
290 skb = netdev_alloc_skb_ip_align(netdev, RX_BUF_SIZE);
291 if (unlikely(!skb)) {
293 netdev_warn(netdev, "failed to allocate rx skb\n");
295 map = priv->rx_scratch_dma;
297 map = dma_map_single(priv->dev, skb->data, RX_BUF_SIZE,
299 if (unlikely(dma_mapping_error(priv->dev, map))) {
301 netdev_err(netdev, "failed to map rx page\n");
302 dev_kfree_skb_any(skb);
303 map = priv->rx_scratch_dma;
310 priv->rx_skbs[entry] = skb;
312 /* Store DMA address into RX desc */
313 rxdes->rxdes3 = cpu_to_le32(map);
315 /* Ensure the above is ordered vs clearing the OWN bit */
318 /* Clean status (which resets own bit) */
319 if (entry == (RX_QUEUE_ENTRIES - 1))
320 rxdes->rxdes0 = cpu_to_le32(priv->rxdes0_edorr_mask);
327 static int ftgmac100_next_rx_pointer(int pointer)
329 return (pointer + 1) & (RX_QUEUE_ENTRIES - 1);
332 static void ftgmac100_rx_packet_error(struct ftgmac100 *priv, u32 status)
334 struct net_device *netdev = priv->netdev;
336 if (status & FTGMAC100_RXDES0_RX_ERR)
337 netdev->stats.rx_errors++;
339 if (status & FTGMAC100_RXDES0_CRC_ERR)
340 netdev->stats.rx_crc_errors++;
342 if (status & (FTGMAC100_RXDES0_FTL |
343 FTGMAC100_RXDES0_RUNT |
344 FTGMAC100_RXDES0_RX_ODD_NB))
345 netdev->stats.rx_length_errors++;
348 static bool ftgmac100_rx_packet(struct ftgmac100 *priv, int *processed)
350 struct net_device *netdev = priv->netdev;
351 struct ftgmac100_rxdes *rxdes;
353 unsigned int pointer, size;
354 u32 status, csum_vlan;
357 /* Grab next RX descriptor */
358 pointer = priv->rx_pointer;
359 rxdes = &priv->descs->rxdes[pointer];
361 /* Grab descriptor status */
362 status = le32_to_cpu(rxdes->rxdes0);
364 /* Do we have a packet ? */
365 if (!(status & FTGMAC100_RXDES0_RXPKT_RDY))
368 /* Order subsequent reads with the test for the ready bit */
371 /* We don't cope with fragmented RX packets */
372 if (unlikely(!(status & FTGMAC100_RXDES0_FRS) ||
373 !(status & FTGMAC100_RXDES0_LRS)))
376 /* Grab received size and csum vlan field in the descriptor */
377 size = status & FTGMAC100_RXDES0_VDBC;
378 csum_vlan = le32_to_cpu(rxdes->rxdes1);
380 /* Any error (other than csum offload) flagged ? */
381 if (unlikely(status & RXDES0_ANY_ERROR)) {
382 /* Correct for incorrect flagging of runt packets
383 * with vlan tags... Just accept a runt packet that
384 * has been flagged as vlan and whose size is at
387 if ((status & FTGMAC100_RXDES0_RUNT) &&
388 (csum_vlan & FTGMAC100_RXDES1_VLANTAG_AVAIL) &&
390 status &= ~FTGMAC100_RXDES0_RUNT;
392 /* Any error still in there ? */
393 if (status & RXDES0_ANY_ERROR) {
394 ftgmac100_rx_packet_error(priv, status);
399 /* If the packet had no skb (failed to allocate earlier)
400 * then try to allocate one and skip
402 skb = priv->rx_skbs[pointer];
403 if (!unlikely(skb)) {
404 ftgmac100_alloc_rx_buf(priv, pointer, rxdes, GFP_ATOMIC);
408 if (unlikely(status & FTGMAC100_RXDES0_MULTICAST))
409 netdev->stats.multicast++;
411 /* If the HW found checksum errors, bounce it to software.
413 * If we didn't, we need to see if the packet was recognized
414 * by HW as one of the supported checksummed protocols before
415 * we accept the HW test results.
417 if (netdev->features & NETIF_F_RXCSUM) {
418 u32 err_bits = FTGMAC100_RXDES1_TCP_CHKSUM_ERR |
419 FTGMAC100_RXDES1_UDP_CHKSUM_ERR |
420 FTGMAC100_RXDES1_IP_CHKSUM_ERR;
421 if ((csum_vlan & err_bits) ||
422 !(csum_vlan & FTGMAC100_RXDES1_PROT_MASK))
423 skb->ip_summed = CHECKSUM_NONE;
425 skb->ip_summed = CHECKSUM_UNNECESSARY;
428 /* Transfer received size to skb */
431 /* Tear down DMA mapping, do necessary cache management */
432 map = le32_to_cpu(rxdes->rxdes3);
434 #if defined(CONFIG_ARM) && !defined(CONFIG_ARM_DMA_USE_IOMMU)
435 /* When we don't have an iommu, we can save cycles by not
436 * invalidating the cache for the part of the packet that
439 dma_unmap_single(priv->dev, map, size, DMA_FROM_DEVICE);
441 dma_unmap_single(priv->dev, map, RX_BUF_SIZE, DMA_FROM_DEVICE);
445 /* Resplenish rx ring */
446 ftgmac100_alloc_rx_buf(priv, pointer, rxdes, GFP_ATOMIC);
447 priv->rx_pointer = ftgmac100_next_rx_pointer(pointer);
449 skb->protocol = eth_type_trans(skb, netdev);
451 netdev->stats.rx_packets++;
452 netdev->stats.rx_bytes += size;
454 /* push packet to protocol stack */
455 if (skb->ip_summed == CHECKSUM_NONE)
456 netif_receive_skb(skb);
458 napi_gro_receive(&priv->napi, skb);
464 /* Clean rxdes0 (which resets own bit) */
465 rxdes->rxdes0 = cpu_to_le32(status & priv->rxdes0_edorr_mask);
466 priv->rx_pointer = ftgmac100_next_rx_pointer(pointer);
467 netdev->stats.rx_dropped++;
471 static u32 ftgmac100_base_tx_ctlstat(struct ftgmac100 *priv,
474 if (index == (TX_QUEUE_ENTRIES - 1))
475 return priv->txdes0_edotr_mask;
480 static int ftgmac100_next_tx_pointer(int pointer)
482 return (pointer + 1) & (TX_QUEUE_ENTRIES - 1);
485 static u32 ftgmac100_tx_buf_avail(struct ftgmac100 *priv)
487 /* Returns the number of available slots in the TX queue
489 * This always leaves one free slot so we don't have to
490 * worry about empty vs. full, and this simplifies the
491 * test for ftgmac100_tx_buf_cleanable() below
493 return (priv->tx_clean_pointer - priv->tx_pointer - 1) &
494 (TX_QUEUE_ENTRIES - 1);
497 static bool ftgmac100_tx_buf_cleanable(struct ftgmac100 *priv)
499 return priv->tx_pointer != priv->tx_clean_pointer;
502 static void ftgmac100_free_tx_packet(struct ftgmac100 *priv,
503 unsigned int pointer,
505 struct ftgmac100_txdes *txdes,
508 dma_addr_t map = le32_to_cpu(txdes->txdes3);
511 if (ctl_stat & FTGMAC100_TXDES0_FTS) {
512 len = skb_headlen(skb);
513 dma_unmap_single(priv->dev, map, len, DMA_TO_DEVICE);
515 len = FTGMAC100_TXDES0_TXBUF_SIZE(ctl_stat);
516 dma_unmap_page(priv->dev, map, len, DMA_TO_DEVICE);
519 /* Free SKB on last segment */
520 if (ctl_stat & FTGMAC100_TXDES0_LTS)
522 priv->tx_skbs[pointer] = NULL;
525 static bool ftgmac100_tx_complete_packet(struct ftgmac100 *priv)
527 struct net_device *netdev = priv->netdev;
528 struct ftgmac100_txdes *txdes;
530 unsigned int pointer;
533 pointer = priv->tx_clean_pointer;
534 txdes = &priv->descs->txdes[pointer];
536 ctl_stat = le32_to_cpu(txdes->txdes0);
537 if (ctl_stat & FTGMAC100_TXDES0_TXDMA_OWN)
540 skb = priv->tx_skbs[pointer];
541 netdev->stats.tx_packets++;
542 netdev->stats.tx_bytes += skb->len;
543 ftgmac100_free_tx_packet(priv, pointer, skb, txdes, ctl_stat);
544 txdes->txdes0 = cpu_to_le32(ctl_stat & priv->txdes0_edotr_mask);
546 priv->tx_clean_pointer = ftgmac100_next_tx_pointer(pointer);
551 static void ftgmac100_tx_complete(struct ftgmac100 *priv)
553 struct net_device *netdev = priv->netdev;
555 /* Process all completed packets */
556 while (ftgmac100_tx_buf_cleanable(priv) &&
557 ftgmac100_tx_complete_packet(priv))
560 /* Restart queue if needed */
562 if (unlikely(netif_queue_stopped(netdev) &&
563 ftgmac100_tx_buf_avail(priv) >= TX_THRESHOLD)) {
564 struct netdev_queue *txq;
566 txq = netdev_get_tx_queue(netdev, 0);
567 __netif_tx_lock(txq, smp_processor_id());
568 if (netif_queue_stopped(netdev) &&
569 ftgmac100_tx_buf_avail(priv) >= TX_THRESHOLD)
570 netif_wake_queue(netdev);
571 __netif_tx_unlock(txq);
575 static int ftgmac100_hard_start_xmit(struct sk_buff *skb,
576 struct net_device *netdev)
578 struct ftgmac100 *priv = netdev_priv(netdev);
579 struct ftgmac100_txdes *txdes, *first;
580 unsigned int pointer, nfrags, len, i, j;
581 u32 f_ctl_stat, ctl_stat, csum_vlan;
584 /* The HW doesn't pad small frames */
585 if (eth_skb_pad(skb)) {
586 netdev->stats.tx_dropped++;
590 /* Reject oversize packets */
591 if (unlikely(skb->len > MAX_PKT_SIZE)) {
593 netdev_dbg(netdev, "tx packet too big\n");
597 /* Do we have a limit on #fragments ? I yet have to get a reply
598 * from Aspeed. If there's one I haven't hit it.
600 nfrags = skb_shinfo(skb)->nr_frags;
603 len = skb_headlen(skb);
605 /* Map the packet head */
606 map = dma_map_single(priv->dev, skb->data, len, DMA_TO_DEVICE);
607 if (dma_mapping_error(priv->dev, map)) {
609 netdev_err(netdev, "map tx packet head failed\n");
613 /* Grab the next free tx descriptor */
614 pointer = priv->tx_pointer;
615 txdes = first = &priv->descs->txdes[pointer];
617 /* Setup it up with the packet head. Don't write the head to the
620 priv->tx_skbs[pointer] = skb;
621 f_ctl_stat = ftgmac100_base_tx_ctlstat(priv, pointer);
622 f_ctl_stat |= FTGMAC100_TXDES0_TXDMA_OWN;
623 f_ctl_stat |= FTGMAC100_TXDES0_TXBUF_SIZE(len);
624 f_ctl_stat |= FTGMAC100_TXDES0_FTS;
626 f_ctl_stat |= FTGMAC100_TXDES0_LTS;
627 txdes->txdes3 = cpu_to_le32(map);
629 /* Setup HW checksumming */
631 if (skb->ip_summed == CHECKSUM_PARTIAL) {
632 __be16 protocol = skb->protocol;
634 if (protocol == cpu_to_be16(ETH_P_IP)) {
635 u8 ip_proto = ip_hdr(skb)->protocol;
637 csum_vlan |= FTGMAC100_TXDES1_IP_CHKSUM;
638 if (ip_proto == IPPROTO_TCP)
639 csum_vlan |= FTGMAC100_TXDES1_TCP_CHKSUM;
640 else if (ip_proto == IPPROTO_UDP)
641 csum_vlan |= FTGMAC100_TXDES1_UDP_CHKSUM;
644 txdes->txdes1 = cpu_to_le32(csum_vlan);
646 /* Next descriptor */
647 pointer = ftgmac100_next_tx_pointer(pointer);
649 /* Add the fragments */
650 for (i = 0; i < nfrags; i++) {
651 skb_frag_t *frag = &skb_shinfo(skb)->frags[i];
656 map = skb_frag_dma_map(priv->dev, frag, 0, len,
658 if (dma_mapping_error(priv->dev, map))
661 /* Setup descriptor */
662 priv->tx_skbs[pointer] = skb;
663 txdes = &priv->descs->txdes[pointer];
664 ctl_stat = ftgmac100_base_tx_ctlstat(priv, pointer);
665 ctl_stat |= FTGMAC100_TXDES0_TXDMA_OWN;
666 ctl_stat |= FTGMAC100_TXDES0_TXBUF_SIZE(len);
667 if (i == (nfrags - 1))
668 ctl_stat |= FTGMAC100_TXDES0_LTS;
669 txdes->txdes0 = cpu_to_le32(ctl_stat);
671 txdes->txdes3 = cpu_to_le32(map);
674 pointer = ftgmac100_next_tx_pointer(pointer);
677 /* Order the previous packet and descriptor udpates
678 * before setting the OWN bit on the first descriptor.
681 first->txdes0 = cpu_to_le32(f_ctl_stat);
683 /* Update next TX pointer */
684 priv->tx_pointer = pointer;
686 /* If there isn't enough room for all the fragments of a new packet
687 * in the TX ring, stop the queue. The sequence below is race free
688 * vs. a concurrent restart in ftgmac100_poll()
690 if (unlikely(ftgmac100_tx_buf_avail(priv) < TX_THRESHOLD)) {
691 netif_stop_queue(netdev);
692 /* Order the queue stop with the test below */
694 if (ftgmac100_tx_buf_avail(priv) >= TX_THRESHOLD)
695 netif_wake_queue(netdev);
698 ftgmac100_txdma_normal_prio_start_polling(priv);
704 netdev_err(netdev, "map tx fragment failed\n");
707 pointer = priv->tx_pointer;
708 ftgmac100_free_tx_packet(priv, pointer, skb, first, f_ctl_stat);
709 first->txdes0 = cpu_to_le32(f_ctl_stat & priv->txdes0_edotr_mask);
711 /* Then all fragments */
712 for (j = 0; j < i; j++) {
713 pointer = ftgmac100_next_tx_pointer(pointer);
714 txdes = &priv->descs->txdes[pointer];
715 ctl_stat = le32_to_cpu(txdes->txdes0);
716 ftgmac100_free_tx_packet(priv, pointer, skb, txdes, ctl_stat);
717 txdes->txdes0 = cpu_to_le32(ctl_stat & priv->txdes0_edotr_mask);
720 /* This cannot be reached if we successfully mapped the
721 * last fragment, so we know ftgmac100_free_tx_packet()
722 * hasn't freed the skb yet.
725 /* Drop the packet */
726 dev_kfree_skb_any(skb);
727 netdev->stats.tx_dropped++;
732 static void ftgmac100_free_buffers(struct ftgmac100 *priv)
736 /* Free all RX buffers */
737 for (i = 0; i < RX_QUEUE_ENTRIES; i++) {
738 struct ftgmac100_rxdes *rxdes = &priv->descs->rxdes[i];
739 struct sk_buff *skb = priv->rx_skbs[i];
740 dma_addr_t map = le32_to_cpu(rxdes->rxdes3);
745 priv->rx_skbs[i] = NULL;
746 dma_unmap_single(priv->dev, map, RX_BUF_SIZE, DMA_FROM_DEVICE);
747 dev_kfree_skb_any(skb);
750 /* Free all TX buffers */
751 for (i = 0; i < TX_QUEUE_ENTRIES; i++) {
752 struct ftgmac100_txdes *txdes = &priv->descs->txdes[i];
753 struct sk_buff *skb = priv->tx_skbs[i];
757 ftgmac100_free_tx_packet(priv, i, skb, txdes,
758 le32_to_cpu(txdes->txdes0));
762 static void ftgmac100_free_rings(struct ftgmac100 *priv)
764 /* Free descriptors */
766 dma_free_coherent(priv->dev, sizeof(struct ftgmac100_descs),
767 priv->descs, priv->descs_dma_addr);
769 /* Free scratch packet buffer */
770 if (priv->rx_scratch)
771 dma_free_coherent(priv->dev, RX_BUF_SIZE,
772 priv->rx_scratch, priv->rx_scratch_dma);
775 static int ftgmac100_alloc_rings(struct ftgmac100 *priv)
777 /* Allocate descriptors */
778 priv->descs = dma_zalloc_coherent(priv->dev,
779 sizeof(struct ftgmac100_descs),
780 &priv->descs_dma_addr, GFP_KERNEL);
784 /* Allocate scratch packet buffer */
785 priv->rx_scratch = dma_alloc_coherent(priv->dev,
787 &priv->rx_scratch_dma,
789 if (!priv->rx_scratch)
795 static void ftgmac100_init_rings(struct ftgmac100 *priv)
797 struct ftgmac100_rxdes *rxdes;
798 struct ftgmac100_txdes *txdes;
801 /* Initialize RX ring */
802 for (i = 0; i < RX_QUEUE_ENTRIES; i++) {
803 rxdes = &priv->descs->rxdes[i];
805 rxdes->rxdes3 = cpu_to_le32(priv->rx_scratch_dma);
807 /* Mark the end of the ring */
808 rxdes->rxdes0 |= cpu_to_le32(priv->rxdes0_edorr_mask);
810 /* Initialize TX ring */
811 for (i = 0; i < TX_QUEUE_ENTRIES; i++) {
812 txdes = &priv->descs->txdes[i];
815 txdes->txdes0 |= cpu_to_le32(priv->txdes0_edotr_mask);
818 static int ftgmac100_alloc_rx_buffers(struct ftgmac100 *priv)
822 for (i = 0; i < RX_QUEUE_ENTRIES; i++) {
823 struct ftgmac100_rxdes *rxdes = &priv->descs->rxdes[i];
825 if (ftgmac100_alloc_rx_buf(priv, i, rxdes, GFP_KERNEL))
831 static void ftgmac100_adjust_link(struct net_device *netdev)
833 struct ftgmac100 *priv = netdev_priv(netdev);
834 struct phy_device *phydev = netdev->phydev;
837 /* We store "no link" as speed 0 */
841 new_speed = phydev->speed;
843 if (phydev->speed == priv->cur_speed &&
844 phydev->duplex == priv->cur_duplex)
847 /* Print status if we have a link or we had one and just lost it,
848 * don't print otherwise.
850 if (new_speed || priv->cur_speed)
851 phy_print_status(phydev);
853 priv->cur_speed = new_speed;
854 priv->cur_duplex = phydev->duplex;
856 /* Link is down, do nothing else */
860 /* Disable all interrupts */
861 iowrite32(0, priv->base + FTGMAC100_OFFSET_IER);
863 /* Reset the adapter asynchronously */
864 schedule_work(&priv->reset_task);
867 static int ftgmac100_mii_probe(struct ftgmac100 *priv)
869 struct net_device *netdev = priv->netdev;
870 struct phy_device *phydev;
872 phydev = phy_find_first(priv->mii_bus);
874 netdev_info(netdev, "%s: no PHY found\n", netdev->name);
878 phydev = phy_connect(netdev, phydev_name(phydev),
879 &ftgmac100_adjust_link, PHY_INTERFACE_MODE_GMII);
881 if (IS_ERR(phydev)) {
882 netdev_err(netdev, "%s: Could not attach to PHY\n", netdev->name);
883 return PTR_ERR(phydev);
889 static int ftgmac100_mdiobus_read(struct mii_bus *bus, int phy_addr, int regnum)
891 struct net_device *netdev = bus->priv;
892 struct ftgmac100 *priv = netdev_priv(netdev);
896 phycr = ioread32(priv->base + FTGMAC100_OFFSET_PHYCR);
898 /* preserve MDC cycle threshold */
899 phycr &= FTGMAC100_PHYCR_MDC_CYCTHR_MASK;
901 phycr |= FTGMAC100_PHYCR_PHYAD(phy_addr) |
902 FTGMAC100_PHYCR_REGAD(regnum) |
903 FTGMAC100_PHYCR_MIIRD;
905 iowrite32(phycr, priv->base + FTGMAC100_OFFSET_PHYCR);
907 for (i = 0; i < 10; i++) {
908 phycr = ioread32(priv->base + FTGMAC100_OFFSET_PHYCR);
910 if ((phycr & FTGMAC100_PHYCR_MIIRD) == 0) {
913 data = ioread32(priv->base + FTGMAC100_OFFSET_PHYDATA);
914 return FTGMAC100_PHYDATA_MIIRDATA(data);
920 netdev_err(netdev, "mdio read timed out\n");
924 static int ftgmac100_mdiobus_write(struct mii_bus *bus, int phy_addr,
925 int regnum, u16 value)
927 struct net_device *netdev = bus->priv;
928 struct ftgmac100 *priv = netdev_priv(netdev);
933 phycr = ioread32(priv->base + FTGMAC100_OFFSET_PHYCR);
935 /* preserve MDC cycle threshold */
936 phycr &= FTGMAC100_PHYCR_MDC_CYCTHR_MASK;
938 phycr |= FTGMAC100_PHYCR_PHYAD(phy_addr) |
939 FTGMAC100_PHYCR_REGAD(regnum) |
940 FTGMAC100_PHYCR_MIIWR;
942 data = FTGMAC100_PHYDATA_MIIWDATA(value);
944 iowrite32(data, priv->base + FTGMAC100_OFFSET_PHYDATA);
945 iowrite32(phycr, priv->base + FTGMAC100_OFFSET_PHYCR);
947 for (i = 0; i < 10; i++) {
948 phycr = ioread32(priv->base + FTGMAC100_OFFSET_PHYCR);
950 if ((phycr & FTGMAC100_PHYCR_MIIWR) == 0)
956 netdev_err(netdev, "mdio write timed out\n");
960 static void ftgmac100_get_drvinfo(struct net_device *netdev,
961 struct ethtool_drvinfo *info)
963 strlcpy(info->driver, DRV_NAME, sizeof(info->driver));
964 strlcpy(info->version, DRV_VERSION, sizeof(info->version));
965 strlcpy(info->bus_info, dev_name(&netdev->dev), sizeof(info->bus_info));
968 static const struct ethtool_ops ftgmac100_ethtool_ops = {
969 .get_drvinfo = ftgmac100_get_drvinfo,
970 .get_link = ethtool_op_get_link,
971 .get_link_ksettings = phy_ethtool_get_link_ksettings,
972 .set_link_ksettings = phy_ethtool_set_link_ksettings,
975 static irqreturn_t ftgmac100_interrupt(int irq, void *dev_id)
977 struct net_device *netdev = dev_id;
978 struct ftgmac100 *priv = netdev_priv(netdev);
979 unsigned int status, new_mask = FTGMAC100_INT_BAD;
981 /* Fetch and clear interrupt bits, process abnormal ones */
982 status = ioread32(priv->base + FTGMAC100_OFFSET_ISR);
983 iowrite32(status, priv->base + FTGMAC100_OFFSET_ISR);
984 if (unlikely(status & FTGMAC100_INT_BAD)) {
986 /* RX buffer unavailable */
987 if (status & FTGMAC100_INT_NO_RXBUF)
988 netdev->stats.rx_over_errors++;
990 /* received packet lost due to RX FIFO full */
991 if (status & FTGMAC100_INT_RPKT_LOST)
992 netdev->stats.rx_fifo_errors++;
994 /* sent packet lost due to excessive TX collision */
995 if (status & FTGMAC100_INT_XPKT_LOST)
996 netdev->stats.tx_fifo_errors++;
998 /* AHB error -> Reset the chip */
999 if (status & FTGMAC100_INT_AHB_ERR) {
1000 if (net_ratelimit())
1002 "AHB bus error ! Resetting chip.\n");
1003 iowrite32(0, priv->base + FTGMAC100_OFFSET_IER);
1004 schedule_work(&priv->reset_task);
1008 /* We may need to restart the MAC after such errors, delay
1009 * this until after we have freed some Rx buffers though
1011 priv->need_mac_restart = true;
1013 /* Disable those errors until we restart */
1014 new_mask &= ~status;
1017 /* Only enable "bad" interrupts while NAPI is on */
1018 iowrite32(new_mask, priv->base + FTGMAC100_OFFSET_IER);
1020 /* Schedule NAPI bh */
1021 napi_schedule_irqoff(&priv->napi);
1026 static bool ftgmac100_check_rx(struct ftgmac100 *priv)
1028 struct ftgmac100_rxdes *rxdes = &priv->descs->rxdes[priv->rx_pointer];
1030 /* Do we have a packet ? */
1031 return !!(rxdes->rxdes0 & cpu_to_le32(FTGMAC100_RXDES0_RXPKT_RDY));
1034 static int ftgmac100_poll(struct napi_struct *napi, int budget)
1036 struct ftgmac100 *priv = container_of(napi, struct ftgmac100, napi);
1040 /* Handle TX completions */
1041 if (ftgmac100_tx_buf_cleanable(priv))
1042 ftgmac100_tx_complete(priv);
1044 /* Handle RX packets */
1046 more = ftgmac100_rx_packet(priv, &work_done);
1047 } while (more && work_done < budget);
1050 /* The interrupt is telling us to kick the MAC back to life
1051 * after an RX overflow
1053 if (unlikely(priv->need_mac_restart)) {
1054 ftgmac100_start_hw(priv);
1056 /* Re-enable "bad" interrupts */
1057 iowrite32(FTGMAC100_INT_BAD,
1058 priv->base + FTGMAC100_OFFSET_IER);
1061 /* As long as we are waiting for transmit packets to be
1062 * completed we keep NAPI going
1064 if (ftgmac100_tx_buf_cleanable(priv))
1067 if (work_done < budget) {
1068 /* We are about to re-enable all interrupts. However
1069 * the HW has been latching RX/TX packet interrupts while
1070 * they were masked. So we clear them first, then we need
1071 * to re-check if there's something to process
1073 iowrite32(FTGMAC100_INT_RXTX,
1074 priv->base + FTGMAC100_OFFSET_ISR);
1075 if (ftgmac100_check_rx(priv) ||
1076 ftgmac100_tx_buf_cleanable(priv))
1079 /* deschedule NAPI */
1080 napi_complete(napi);
1082 /* enable all interrupts */
1083 iowrite32(FTGMAC100_INT_ALL,
1084 priv->base + FTGMAC100_OFFSET_IER);
1090 static int ftgmac100_init_all(struct ftgmac100 *priv, bool ignore_alloc_err)
1094 /* Re-init descriptors (adjust queue sizes) */
1095 ftgmac100_init_rings(priv);
1097 /* Realloc rx descriptors */
1098 err = ftgmac100_alloc_rx_buffers(priv);
1099 if (err && !ignore_alloc_err)
1102 /* Reinit and restart HW */
1103 ftgmac100_init_hw(priv);
1104 ftgmac100_start_hw(priv);
1106 /* Re-enable the device */
1107 napi_enable(&priv->napi);
1108 netif_start_queue(priv->netdev);
1110 /* Enable all interrupts */
1111 iowrite32(FTGMAC100_INT_ALL, priv->base + FTGMAC100_OFFSET_IER);
1116 static void ftgmac100_reset_task(struct work_struct *work)
1118 struct ftgmac100 *priv = container_of(work, struct ftgmac100,
1120 struct net_device *netdev = priv->netdev;
1123 netdev_dbg(netdev, "Resetting NIC...\n");
1125 /* Lock the world */
1128 mutex_lock(&netdev->phydev->lock);
1130 mutex_lock(&priv->mii_bus->mdio_lock);
1133 /* Check if the interface is still up */
1134 if (!netif_running(netdev))
1137 /* Stop the network stack */
1138 netif_trans_update(netdev);
1139 napi_disable(&priv->napi);
1140 netif_tx_disable(netdev);
1142 /* Stop and reset the MAC */
1143 ftgmac100_stop_hw(priv);
1144 err = ftgmac100_reset_and_config_mac(priv);
1146 /* Not much we can do ... it might come back... */
1147 netdev_err(netdev, "attempting to continue...\n");
1150 /* Free all rx and tx buffers */
1151 ftgmac100_free_buffers(priv);
1153 /* Setup everything again and restart chip */
1154 ftgmac100_init_all(priv, true);
1156 netdev_dbg(netdev, "Reset done !\n");
1159 mutex_unlock(&priv->mii_bus->mdio_lock);
1161 mutex_unlock(&netdev->phydev->lock);
1165 static int ftgmac100_open(struct net_device *netdev)
1167 struct ftgmac100 *priv = netdev_priv(netdev);
1170 /* Allocate ring buffers */
1171 err = ftgmac100_alloc_rings(priv);
1173 netdev_err(netdev, "Failed to allocate descriptors\n");
1177 /* When using NC-SI we force the speed to 100Mbit/s full duplex,
1179 * Otherwise we leave it set to 0 (no link), the link
1180 * message from the PHY layer will handle setting it up to
1181 * something else if needed.
1183 if (priv->use_ncsi) {
1184 priv->cur_duplex = DUPLEX_FULL;
1185 priv->cur_speed = SPEED_100;
1187 priv->cur_duplex = 0;
1188 priv->cur_speed = 0;
1191 /* Reset the hardware */
1192 err = ftgmac100_reset_and_config_mac(priv);
1196 /* Initialize NAPI */
1197 netif_napi_add(netdev, &priv->napi, ftgmac100_poll, 64);
1199 /* Grab our interrupt */
1200 err = request_irq(netdev->irq, ftgmac100_interrupt, 0, netdev->name, netdev);
1202 netdev_err(netdev, "failed to request irq %d\n", netdev->irq);
1206 /* Start things up */
1207 err = ftgmac100_init_all(priv, false);
1209 netdev_err(netdev, "Failed to allocate packet buffers\n");
1213 if (netdev->phydev) {
1214 /* If we have a PHY, start polling */
1215 phy_start(netdev->phydev);
1216 } else if (priv->use_ncsi) {
1217 /* If using NC-SI, set our carrier on and start the stack */
1218 netif_carrier_on(netdev);
1220 /* Start the NCSI device */
1221 err = ncsi_start_dev(priv->ndev);
1229 napi_disable(&priv->napi);
1230 netif_stop_queue(netdev);
1232 ftgmac100_free_buffers(priv);
1233 free_irq(netdev->irq, netdev);
1235 netif_napi_del(&priv->napi);
1237 iowrite32(0, priv->base + FTGMAC100_OFFSET_IER);
1238 ftgmac100_free_rings(priv);
1242 static int ftgmac100_stop(struct net_device *netdev)
1244 struct ftgmac100 *priv = netdev_priv(netdev);
1246 /* Note about the reset task: We are called with the rtnl lock
1247 * held, so we are synchronized against the core of the reset
1248 * task. We must not try to synchronously cancel it otherwise
1249 * we can deadlock. But since it will test for netif_running()
1250 * which has already been cleared by the net core, we don't
1251 * anything special to do.
1254 /* disable all interrupts */
1255 iowrite32(0, priv->base + FTGMAC100_OFFSET_IER);
1257 netif_stop_queue(netdev);
1258 napi_disable(&priv->napi);
1259 netif_napi_del(&priv->napi);
1261 phy_stop(netdev->phydev);
1262 else if (priv->use_ncsi)
1263 ncsi_stop_dev(priv->ndev);
1265 ftgmac100_stop_hw(priv);
1266 free_irq(netdev->irq, netdev);
1267 ftgmac100_free_buffers(priv);
1268 ftgmac100_free_rings(priv);
1274 static int ftgmac100_do_ioctl(struct net_device *netdev, struct ifreq *ifr, int cmd)
1276 if (!netdev->phydev)
1279 return phy_mii_ioctl(netdev->phydev, ifr, cmd);
1282 static void ftgmac100_tx_timeout(struct net_device *netdev)
1284 struct ftgmac100 *priv = netdev_priv(netdev);
1286 /* Disable all interrupts */
1287 iowrite32(0, priv->base + FTGMAC100_OFFSET_IER);
1289 /* Do the reset outside of interrupt context */
1290 schedule_work(&priv->reset_task);
1293 static const struct net_device_ops ftgmac100_netdev_ops = {
1294 .ndo_open = ftgmac100_open,
1295 .ndo_stop = ftgmac100_stop,
1296 .ndo_start_xmit = ftgmac100_hard_start_xmit,
1297 .ndo_set_mac_address = ftgmac100_set_mac_addr,
1298 .ndo_validate_addr = eth_validate_addr,
1299 .ndo_do_ioctl = ftgmac100_do_ioctl,
1300 .ndo_tx_timeout = ftgmac100_tx_timeout,
1303 static int ftgmac100_setup_mdio(struct net_device *netdev)
1305 struct ftgmac100 *priv = netdev_priv(netdev);
1306 struct platform_device *pdev = to_platform_device(priv->dev);
1310 /* initialize mdio bus */
1311 priv->mii_bus = mdiobus_alloc();
1315 if (of_machine_is_compatible("aspeed,ast2400") ||
1316 of_machine_is_compatible("aspeed,ast2500")) {
1317 /* This driver supports the old MDIO interface */
1318 reg = ioread32(priv->base + FTGMAC100_OFFSET_REVR);
1319 reg &= ~FTGMAC100_REVR_NEW_MDIO_INTERFACE;
1320 iowrite32(reg, priv->base + FTGMAC100_OFFSET_REVR);
1323 priv->mii_bus->name = "ftgmac100_mdio";
1324 snprintf(priv->mii_bus->id, MII_BUS_ID_SIZE, "%s-%d",
1325 pdev->name, pdev->id);
1326 priv->mii_bus->priv = priv->netdev;
1327 priv->mii_bus->read = ftgmac100_mdiobus_read;
1328 priv->mii_bus->write = ftgmac100_mdiobus_write;
1330 for (i = 0; i < PHY_MAX_ADDR; i++)
1331 priv->mii_bus->irq[i] = PHY_POLL;
1333 err = mdiobus_register(priv->mii_bus);
1335 dev_err(priv->dev, "Cannot register MDIO bus!\n");
1336 goto err_register_mdiobus;
1339 err = ftgmac100_mii_probe(priv);
1341 dev_err(priv->dev, "MII Probe failed!\n");
1348 mdiobus_unregister(priv->mii_bus);
1349 err_register_mdiobus:
1350 mdiobus_free(priv->mii_bus);
1354 static void ftgmac100_destroy_mdio(struct net_device *netdev)
1356 struct ftgmac100 *priv = netdev_priv(netdev);
1358 if (!netdev->phydev)
1361 phy_disconnect(netdev->phydev);
1362 mdiobus_unregister(priv->mii_bus);
1363 mdiobus_free(priv->mii_bus);
1366 static void ftgmac100_ncsi_handler(struct ncsi_dev *nd)
1368 if (unlikely(nd->state != ncsi_dev_state_functional))
1371 netdev_info(nd->dev, "NCSI interface %s\n",
1372 nd->link_up ? "up" : "down");
1375 static int ftgmac100_probe(struct platform_device *pdev)
1377 struct resource *res;
1379 struct net_device *netdev;
1380 struct ftgmac100 *priv;
1386 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1390 irq = platform_get_irq(pdev, 0);
1394 /* setup net_device */
1395 netdev = alloc_etherdev(sizeof(*priv));
1398 goto err_alloc_etherdev;
1401 SET_NETDEV_DEV(netdev, &pdev->dev);
1403 netdev->ethtool_ops = &ftgmac100_ethtool_ops;
1404 netdev->netdev_ops = &ftgmac100_netdev_ops;
1405 netdev->watchdog_timeo = 5 * HZ;
1407 platform_set_drvdata(pdev, netdev);
1409 /* setup private data */
1410 priv = netdev_priv(netdev);
1411 priv->netdev = netdev;
1412 priv->dev = &pdev->dev;
1413 INIT_WORK(&priv->reset_task, ftgmac100_reset_task);
1416 priv->res = request_mem_region(res->start, resource_size(res),
1417 dev_name(&pdev->dev));
1419 dev_err(&pdev->dev, "Could not reserve memory region\n");
1424 priv->base = ioremap(res->start, resource_size(res));
1426 dev_err(&pdev->dev, "Failed to ioremap ethernet registers\n");
1433 /* MAC address from chip or random one */
1434 ftgmac100_setup_mac(priv);
1436 if (of_machine_is_compatible("aspeed,ast2400") ||
1437 of_machine_is_compatible("aspeed,ast2500")) {
1438 priv->rxdes0_edorr_mask = BIT(30);
1439 priv->txdes0_edotr_mask = BIT(30);
1441 priv->rxdes0_edorr_mask = BIT(15);
1442 priv->txdes0_edotr_mask = BIT(15);
1445 if (pdev->dev.of_node &&
1446 of_get_property(pdev->dev.of_node, "use-ncsi", NULL)) {
1447 if (!IS_ENABLED(CONFIG_NET_NCSI)) {
1448 dev_err(&pdev->dev, "NCSI stack not enabled\n");
1452 dev_info(&pdev->dev, "Using NCSI interface\n");
1453 priv->use_ncsi = true;
1454 priv->ndev = ncsi_register_dev(netdev, ftgmac100_ncsi_handler);
1458 priv->use_ncsi = false;
1459 err = ftgmac100_setup_mdio(netdev);
1461 goto err_setup_mdio;
1464 /* We have to disable on-chip IP checksum functionality
1465 * when NCSI is enabled on the interface. It doesn't work
1468 netdev->features = NETIF_F_RXCSUM | NETIF_F_IP_CSUM |
1469 NETIF_F_GRO | NETIF_F_SG;
1470 if (priv->use_ncsi &&
1471 of_get_property(pdev->dev.of_node, "no-hw-checksum", NULL))
1472 netdev->features &= ~NETIF_F_IP_CSUM;
1474 /* register network device */
1475 err = register_netdev(netdev);
1477 dev_err(&pdev->dev, "Failed to register netdev\n");
1478 goto err_register_netdev;
1481 netdev_info(netdev, "irq %d, mapped at %p\n", netdev->irq, priv->base);
1486 err_register_netdev:
1487 ftgmac100_destroy_mdio(netdev);
1489 iounmap(priv->base);
1491 release_resource(priv->res);
1493 netif_napi_del(&priv->napi);
1494 free_netdev(netdev);
1499 static int ftgmac100_remove(struct platform_device *pdev)
1501 struct net_device *netdev;
1502 struct ftgmac100 *priv;
1504 netdev = platform_get_drvdata(pdev);
1505 priv = netdev_priv(netdev);
1507 unregister_netdev(netdev);
1509 /* There's a small chance the reset task will have been re-queued,
1510 * during stop, make sure it's gone before we free the structure.
1512 cancel_work_sync(&priv->reset_task);
1514 ftgmac100_destroy_mdio(netdev);
1516 iounmap(priv->base);
1517 release_resource(priv->res);
1519 netif_napi_del(&priv->napi);
1520 free_netdev(netdev);
1524 static const struct of_device_id ftgmac100_of_match[] = {
1525 { .compatible = "faraday,ftgmac100" },
1528 MODULE_DEVICE_TABLE(of, ftgmac100_of_match);
1530 static struct platform_driver ftgmac100_driver = {
1531 .probe = ftgmac100_probe,
1532 .remove = ftgmac100_remove,
1535 .of_match_table = ftgmac100_of_match,
1538 module_platform_driver(ftgmac100_driver);
1540 MODULE_AUTHOR("Po-Yu Chuang <ratbert@faraday-tech.com>");
1541 MODULE_DESCRIPTION("FTGMAC100 driver");
1542 MODULE_LICENSE("GPL");