drivers/net/ethernet/freescale/gianfar.c

   1 /* drivers/net/ethernet/freescale/gianfar.c
   2  *
   3  * Gianfar Ethernet Driver
   4  * This driver is designed for the non-CPM ethernet controllers
   5  * on the 85xx and 83xx family of integrated processors
   6  * Based on 8260_io/fcc_enet.c
   7  *
   8  * Author: Andy Fleming
   9  * Maintainer: Kumar Gala
  10  * Modifier: Sandeep Gopalpet <sandeep.kumar@freescale.com>
  11  *
  12  * Copyright 2002-2009, 2011-2013 Freescale Semiconductor, Inc.
  13  * Copyright 2007 MontaVista Software, Inc.
  14  *
  15  * This program is free software; you can redistribute  it and/or modify it
  16  * under  the terms of  the GNU General  Public License as published by the
  17  * Free Software Foundation;  either version 2 of the  License, or (at your
  18  * option) any later version.
  19  *
  20  *  Gianfar:  AKA Lambda Draconis, "Dragon"
  21  *  RA 11 31 24.2
  22  *  Dec +69 19 52
  23  *  V 3.84
  24  *  B-V +1.62
  25  *
  26  *  Theory of operation
  27  *
  28  *  The driver is initialized through of_device. Configuration information
  29  *  is therefore conveyed through an OF-style device tree.
  30  *
  31  *  The Gianfar Ethernet Controller uses a ring of buffer
  32  *  descriptors.  The beginning is indicated by a register
  33  *  pointing to the physical address of the start of the ring.
  34  *  The end is determined by a "wrap" bit being set in the
  35  *  last descriptor of the ring.
  36  *
  37  *  When a packet is received, the RXF bit in the
  38  *  IEVENT register is set, triggering an interrupt when the
  39  *  corresponding bit in the IMASK register is also set (if
  40  *  interrupt coalescing is active, then the interrupt may not
  41  *  happen immediately, but will wait until either a set number
  42  *  of frames or amount of time have passed).  In NAPI, the
  43  *  interrupt handler will signal there is work to be done, and
  44  *  exit. This method will start at the last known empty
  45  *  descriptor, and process every subsequent descriptor until there
  46  *  are none left with data (NAPI will stop after a set number of
  47  *  packets to give time to other tasks, but will eventually
  48  *  process all the packets).  The data arrives inside a
  49  *  pre-allocated skb, and so after the skb is passed up to the
  50  *  stack, a new skb must be allocated, and the address field in
  51  *  the buffer descriptor must be updated to indicate this new
  52  *  skb.
  53  *
  54  *  When the kernel requests that a packet be transmitted, the
  55  *  driver starts where it left off last time, and points the
  56  *  descriptor at the buffer which was passed in.  The driver
  57  *  then informs the DMA engine that there are packets ready to
  58  *  be transmitted.  Once the controller is finished transmitting
  59  *  the packet, an interrupt may be triggered (under the same
  60  *  conditions as for reception, but depending on the TXF bit).
  61  *  The driver then cleans up the buffer.
  62  */
  63
  64 #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
  65 #define DEBUG
  66
  67 #include <linux/kernel.h>
  68 #include <linux/string.h>
  69 #include <linux/errno.h>
  70 #include <linux/unistd.h>
  71 #include <linux/slab.h>
  72 #include <linux/interrupt.h>
  73 #include <linux/delay.h>
  74 #include <linux/netdevice.h>
  75 #include <linux/etherdevice.h>
  76 #include <linux/skbuff.h>
  77 #include <linux/if_vlan.h>
  78 #include <linux/spinlock.h>
  79 #include <linux/mm.h>
  80 #include <linux/of_address.h>
  81 #include <linux/of_irq.h>
  82 #include <linux/of_mdio.h>
  83 #include <linux/of_platform.h>
  84 #include <linux/ip.h>
  85 #include <linux/tcp.h>
  86 #include <linux/udp.h>
  87 #include <linux/in.h>
  88 #include <linux/net_tstamp.h>
  89
  90 #include <asm/io.h>
  91 #ifdef CONFIG_PPC
  92 #include <asm/reg.h>
  93 #include <asm/mpc85xx.h>
  94 #endif
  95 #include <asm/irq.h>
  96 #include <asm/uaccess.h>
  97 #include <linux/module.h>
  98 #include <linux/dma-mapping.h>
  99 #include <linux/crc32.h>
 100 #include <linux/mii.h>
 101 #include <linux/phy.h>
 102 #include <linux/phy_fixed.h>
 103 #include <linux/of.h>
 104 #include <linux/of_net.h>
 105 #include <linux/of_address.h>
 106 #include <linux/of_irq.h>
 107
 108 #include "gianfar.h"
 109
 110 #define TX_TIMEOUT      (5*HZ)
 111
 112 const char gfar_driver_version[] = "2.0";
 113
 114 static int gfar_enet_open(struct net_device *dev);
 115 static int gfar_start_xmit(struct sk_buff *skb, struct net_device *dev);
 116 static void gfar_reset_task(struct work_struct *work);
 117 static void gfar_timeout(struct net_device *dev);
 118 static int gfar_close(struct net_device *dev);
 119 static void gfar_alloc_rx_buffs(struct gfar_priv_rx_q *rx_queue,
 120                                 int alloc_cnt);
 121 static int gfar_set_mac_address(struct net_device *dev);
 122 static int gfar_change_mtu(struct net_device *dev, int new_mtu);
 123 static irqreturn_t gfar_error(int irq, void *dev_id);
 124 static irqreturn_t gfar_transmit(int irq, void *dev_id);
 125 static irqreturn_t gfar_interrupt(int irq, void *dev_id);
 126 static void adjust_link(struct net_device *dev);
 127 static noinline void gfar_update_link_state(struct gfar_private *priv);
 128 static int init_phy(struct net_device *dev);
 129 static int gfar_probe(struct platform_device *ofdev);
 130 static int gfar_remove(struct platform_device *ofdev);
 131 static void free_skb_resources(struct gfar_private *priv);
 132 static void gfar_set_multi(struct net_device *dev);
 133 static void gfar_set_hash_for_addr(struct net_device *dev, u8 *addr);
 134 static void gfar_configure_serdes(struct net_device *dev);
 135 static int gfar_poll_rx(struct napi_struct *napi, int budget);
 136 static int gfar_poll_tx(struct napi_struct *napi, int budget);
 137 static int gfar_poll_rx_sq(struct napi_struct *napi, int budget);
 138 static int gfar_poll_tx_sq(struct napi_struct *napi, int budget);
 139 #ifdef CONFIG_NET_POLL_CONTROLLER
 140 static void gfar_netpoll(struct net_device *dev);
 141 #endif
 142 int gfar_clean_rx_ring(struct gfar_priv_rx_q *rx_queue, int rx_work_limit);
 143 static void gfar_clean_tx_ring(struct gfar_priv_tx_q *tx_queue);
 144 static void gfar_process_frame(struct net_device *ndev, struct sk_buff *skb);
 145 static void gfar_halt_nodisable(struct gfar_private *priv);
 146 static void gfar_clear_exact_match(struct net_device *dev);
 147 static void gfar_set_mac_for_addr(struct net_device *dev, int num,
 148                                   const u8 *addr);
 149 static int gfar_ioctl(struct net_device *dev, struct ifreq *rq, int cmd);
 150
 151 MODULE_AUTHOR("Freescale Semiconductor, Inc");
 152 MODULE_DESCRIPTION("Gianfar Ethernet Driver");
 153 MODULE_LICENSE("GPL");
 154
 155 static void gfar_init_rxbdp(struct gfar_priv_rx_q *rx_queue, struct rxbd8 *bdp,
 156                             dma_addr_t buf)
 157 {
 158         u32 lstatus;
 159
 160         bdp->bufPtr = cpu_to_be32(buf);
 161
 162         lstatus = BD_LFLAG(RXBD_EMPTY | RXBD_INTERRUPT);
 163         if (bdp == rx_queue->rx_bd_base + rx_queue->rx_ring_size - 1)
 164                 lstatus |= BD_LFLAG(RXBD_WRAP);
 165
 166         gfar_wmb();
 167
 168         bdp->lstatus = cpu_to_be32(lstatus);
 169 }
 170
 171 static void gfar_init_bds(struct net_device *ndev)
 172 {
 173         struct gfar_private *priv = netdev_priv(ndev);
 174         struct gfar __iomem *regs = priv->gfargrp[0].regs;
 175         struct gfar_priv_tx_q *tx_queue = NULL;
 176         struct gfar_priv_rx_q *rx_queue = NULL;
 177         struct txbd8 *txbdp;
 178         u32 __iomem *rfbptr;
 179         int i, j;
 180
 181         for (i = 0; i < priv->num_tx_queues; i++) {
 182                 tx_queue = priv->tx_queue[i];
 183                 /* Initialize some variables in our dev structure */
 184                 tx_queue->num_txbdfree = tx_queue->tx_ring_size;
 185                 tx_queue->dirty_tx = tx_queue->tx_bd_base;
 186                 tx_queue->cur_tx = tx_queue->tx_bd_base;
 187                 tx_queue->skb_curtx = 0;
 188                 tx_queue->skb_dirtytx = 0;
 189
 190                 /* Initialize Transmit Descriptor Ring */
 191                 txbdp = tx_queue->tx_bd_base;
 192                 for (j = 0; j < tx_queue->tx_ring_size; j++) {
 193                         txbdp->lstatus = 0;
 194                         txbdp->bufPtr = 0;
 195                         txbdp++;
 196                 }
 197
 198                 /* Set the last descriptor in the ring to indicate wrap */
 199                 txbdp--;
 200                 txbdp->status = cpu_to_be16(be16_to_cpu(txbdp->status) |
 201                                             TXBD_WRAP);
 202         }
 203
 204         rfbptr = &regs->rfbptr0;
 205         for (i = 0; i < priv->num_rx_queues; i++) {
 206                 rx_queue = priv->rx_queue[i];
 207
 208                 rx_queue->next_to_clean = 0;
 209                 rx_queue->next_to_use = 0;
 210                 rx_queue->next_to_alloc = 0;
 211
 212                 /* make sure next_to_clean != next_to_use after this
 213                  * by leaving at least 1 unused descriptor
 214                  */
 215                 gfar_alloc_rx_buffs(rx_queue, gfar_rxbd_unused(rx_queue));
 216
 217                 rx_queue->rfbptr = rfbptr;
 218                 rfbptr += 2;
 219         }
 220 }
 221
 222 static int gfar_alloc_skb_resources(struct net_device *ndev)
 223 {
 224         void *vaddr;
 225         dma_addr_t addr;
 226         int i, j;
 227         struct gfar_private *priv = netdev_priv(ndev);
 228         struct device *dev = priv->dev;
 229         struct gfar_priv_tx_q *tx_queue = NULL;
 230         struct gfar_priv_rx_q *rx_queue = NULL;
 231
 232         priv->total_tx_ring_size = 0;
 233         for (i = 0; i < priv->num_tx_queues; i++)
 234                 priv->total_tx_ring_size += priv->tx_queue[i]->tx_ring_size;
 235
 236         priv->total_rx_ring_size = 0;
 237         for (i = 0; i < priv->num_rx_queues; i++)
 238                 priv->total_rx_ring_size += priv->rx_queue[i]->rx_ring_size;
 239
 240         /* Allocate memory for the buffer descriptors */
 241         vaddr = dma_alloc_coherent(dev,
 242                                    (priv->total_tx_ring_size *
 243                                     sizeof(struct txbd8)) +
 244                                    (priv->total_rx_ring_size *
 245                                     sizeof(struct rxbd8)),
 246                                    &addr, GFP_KERNEL);
 247         if (!vaddr)
 248                 return -ENOMEM;
 249
 250         for (i = 0; i < priv->num_tx_queues; i++) {
 251                 tx_queue = priv->tx_queue[i];
 252                 tx_queue->tx_bd_base = vaddr;
 253                 tx_queue->tx_bd_dma_base = addr;
 254                 tx_queue->dev = ndev;
 255                 /* enet DMA only understands physical addresses */
 256                 addr  += sizeof(struct txbd8) * tx_queue->tx_ring_size;
 257                 vaddr += sizeof(struct txbd8) * tx_queue->tx_ring_size;
 258         }
 259
 260         /* Start the rx descriptor ring where the tx ring leaves off */
 261         for (i = 0; i < priv->num_rx_queues; i++) {
 262                 rx_queue = priv->rx_queue[i];
 263                 rx_queue->rx_bd_base = vaddr;
 264                 rx_queue->rx_bd_dma_base = addr;
 265                 rx_queue->ndev = ndev;
 266                 rx_queue->dev = dev;
 267                 addr  += sizeof(struct rxbd8) * rx_queue->rx_ring_size;
 268                 vaddr += sizeof(struct rxbd8) * rx_queue->rx_ring_size;
 269         }
 270
 271         /* Setup the skbuff rings */
 272         for (i = 0; i < priv->num_tx_queues; i++) {
 273                 tx_queue = priv->tx_queue[i];
 274                 tx_queue->tx_skbuff =
 275                         kmalloc_array(tx_queue->tx_ring_size,
 276                                       sizeof(*tx_queue->tx_skbuff),
 277                                       GFP_KERNEL);
 278                 if (!tx_queue->tx_skbuff)
 279                         goto cleanup;
 280
 281                 for (j = 0; j < tx_queue->tx_ring_size; j++)
 282                         tx_queue->tx_skbuff[j] = NULL;
 283         }
 284
 285         for (i = 0; i < priv->num_rx_queues; i++) {
 286                 rx_queue = priv->rx_queue[i];
 287                 rx_queue->rx_buff = kcalloc(rx_queue->rx_ring_size,
 288                                             sizeof(*rx_queue->rx_buff),
 289                                             GFP_KERNEL);
 290                 if (!rx_queue->rx_buff)
 291                         goto cleanup;
 292         }
 293
 294         gfar_init_bds(ndev);
 295
 296         return 0;
 297
 298 cleanup:
 299         free_skb_resources(priv);
 300         return -ENOMEM;
 301 }
 302
 303 static void gfar_init_tx_rx_base(struct gfar_private *priv)
 304 {
 305         struct gfar __iomem *regs = priv->gfargrp[0].regs;
 306         u32 __iomem *baddr;
 307         int i;
 308
 309         baddr = &regs->tbase0;
 310         for (i = 0; i < priv->num_tx_queues; i++) {
 311                 gfar_write(baddr, priv->tx_queue[i]->tx_bd_dma_base);
 312                 baddr += 2;
 313         }
 314
 315         baddr = &regs->rbase0;
 316         for (i = 0; i < priv->num_rx_queues; i++) {
 317                 gfar_write(baddr, priv->rx_queue[i]->rx_bd_dma_base);
 318                 baddr += 2;
 319         }
 320 }
 321
 322 static void gfar_init_rqprm(struct gfar_private *priv)
 323 {
 324         struct gfar __iomem *regs = priv->gfargrp[0].regs;
 325         u32 __iomem *baddr;
 326         int i;
 327
 328         baddr = &regs->rqprm0;
 329         for (i = 0; i < priv->num_rx_queues; i++) {
 330                 gfar_write(baddr, priv->rx_queue[i]->rx_ring_size |
 331                            (DEFAULT_RX_LFC_THR << FBTHR_SHIFT));
 332                 baddr++;
 333         }
 334 }
 335
 336 static void gfar_rx_offload_en(struct gfar_private *priv)
 337 {
 338         /* set this when rx hw offload (TOE) functions are being used */
 339         priv->uses_rxfcb = 0;
 340
 341         if (priv->ndev->features & (NETIF_F_RXCSUM | NETIF_F_HW_VLAN_CTAG_RX))
 342                 priv->uses_rxfcb = 1;
 343
 344         if (priv->hwts_rx_en || priv->rx_filer_enable)
 345                 priv->uses_rxfcb = 1;
 346 }
 347
 348 static void gfar_mac_rx_config(struct gfar_private *priv)
 349 {
 350         struct gfar __iomem *regs = priv->gfargrp[0].regs;
 351         u32 rctrl = 0;
 352
 353         if (priv->rx_filer_enable) {
 354                 rctrl |= RCTRL_FILREN | RCTRL_PRSDEP_INIT;
 355                 /* Program the RIR0 reg with the required distribution */
 356                 if (priv->poll_mode == GFAR_SQ_POLLING)
 357                         gfar_write(&regs->rir0, DEFAULT_2RXQ_RIR0);
 358                 else /* GFAR_MQ_POLLING */
 359                         gfar_write(&regs->rir0, DEFAULT_8RXQ_RIR0);
 360         }
 361
 362         /* Restore PROMISC mode */
 363         if (priv->ndev->flags & IFF_PROMISC)
 364                 rctrl |= RCTRL_PROM;
 365
 366         if (priv->ndev->features & NETIF_F_RXCSUM)
 367                 rctrl |= RCTRL_CHECKSUMMING;
 368
 369         if (priv->extended_hash)
 370                 rctrl |= RCTRL_EXTHASH | RCTRL_EMEN;
 371
 372         if (priv->padding) {
 373                 rctrl &= ~RCTRL_PAL_MASK;
 374                 rctrl |= RCTRL_PADDING(priv->padding);
 375         }
 376
 377         /* Enable HW time stamping if requested from user space */
 378         if (priv->hwts_rx_en)
 379                 rctrl |= RCTRL_PRSDEP_INIT | RCTRL_TS_ENABLE;
 380
 381         if (priv->ndev->features & NETIF_F_HW_VLAN_CTAG_RX)
 382                 rctrl |= RCTRL_VLEX | RCTRL_PRSDEP_INIT;
 383
 384         /* Clear the LFC bit */
 385         gfar_write(&regs->rctrl, rctrl);
 386         /* Init flow control threshold values */
 387         gfar_init_rqprm(priv);
 388         gfar_write(&regs->ptv, DEFAULT_LFC_PTVVAL);
 389         rctrl |= RCTRL_LFC;
 390
 391         /* Init rctrl based on our settings */
 392         gfar_write(&regs->rctrl, rctrl);
 393 }
 394
 395 static void gfar_mac_tx_config(struct gfar_private *priv)
 396 {
 397         struct gfar __iomem *regs = priv->gfargrp[0].regs;
 398         u32 tctrl = 0;
 399
 400         if (priv->ndev->features & NETIF_F_IP_CSUM)
 401                 tctrl |= TCTRL_INIT_CSUM;
 402
 403         if (priv->prio_sched_en)
 404                 tctrl |= TCTRL_TXSCHED_PRIO;
 405         else {
 406                 tctrl |= TCTRL_TXSCHED_WRRS;
 407                 gfar_write(&regs->tr03wt, DEFAULT_WRRS_WEIGHT);
 408                 gfar_write(&regs->tr47wt, DEFAULT_WRRS_WEIGHT);
 409         }
 410
 411         if (priv->ndev->features & NETIF_F_HW_VLAN_CTAG_TX)
 412                 tctrl |= TCTRL_VLINS;
 413
 414         gfar_write(&regs->tctrl, tctrl);
 415 }
 416
 417 static void gfar_configure_coalescing(struct gfar_private *priv,
 418                                unsigned long tx_mask, unsigned long rx_mask)
 419 {
 420         struct gfar __iomem *regs = priv->gfargrp[0].regs;
 421         u32 __iomem *baddr;
 422
 423         if (priv->mode == MQ_MG_MODE) {
 424                 int i = 0;
 425
 426                 baddr = &regs->txic0;
 427                 for_each_set_bit(i, &tx_mask, priv->num_tx_queues) {
 428                         gfar_write(baddr + i, 0);
 429                         if (likely(priv->tx_queue[i]->txcoalescing))
 430                                 gfar_write(baddr + i, priv->tx_queue[i]->txic);
 431                 }
 432
 433                 baddr = &regs->rxic0;
 434                 for_each_set_bit(i, &rx_mask, priv->num_rx_queues) {
 435                         gfar_write(baddr + i, 0);
 436                         if (likely(priv->rx_queue[i]->rxcoalescing))
 437                                 gfar_write(baddr + i, priv->rx_queue[i]->rxic);
 438                 }
 439         } else {
 440                 /* Backward compatible case -- even if we enable
 441                  * multiple queues, there's only single reg to program
 442                  */
 443                 gfar_write(&regs->txic, 0);
 444                 if (likely(priv->tx_queue[0]->txcoalescing))
 445                         gfar_write(&regs->txic, priv->tx_queue[0]->txic);
 446
 447                 gfar_write(&regs->rxic, 0);
 448                 if (unlikely(priv->rx_queue[0]->rxcoalescing))
 449                         gfar_write(&regs->rxic, priv->rx_queue[0]->rxic);
 450         }
 451 }
 452
 453 void gfar_configure_coalescing_all(struct gfar_private *priv)
 454 {
 455         gfar_configure_coalescing(priv, 0xFF, 0xFF);
 456 }
 457
 458 static struct net_device_stats *gfar_get_stats(struct net_device *dev)
 459 {
 460         struct gfar_private *priv = netdev_priv(dev);
 461         unsigned long rx_packets = 0, rx_bytes = 0, rx_dropped = 0;
 462         unsigned long tx_packets = 0, tx_bytes = 0;
 463         int i;
 464
 465         for (i = 0; i < priv->num_rx_queues; i++) {
 466                 rx_packets += priv->rx_queue[i]->stats.rx_packets;
 467                 rx_bytes   += priv->rx_queue[i]->stats.rx_bytes;
 468                 rx_dropped += priv->rx_queue[i]->stats.rx_dropped;
 469         }
 470
 471         dev->stats.rx_packets = rx_packets;
 472         dev->stats.rx_bytes   = rx_bytes;
 473         dev->stats.rx_dropped = rx_dropped;
 474
 475         for (i = 0; i < priv->num_tx_queues; i++) {
 476                 tx_bytes += priv->tx_queue[i]->stats.tx_bytes;
 477                 tx_packets += priv->tx_queue[i]->stats.tx_packets;
 478         }
 479
 480         dev->stats.tx_bytes   = tx_bytes;
 481         dev->stats.tx_packets = tx_packets;
 482
 483         return &dev->stats;
 484 }
 485
 486 static int gfar_set_mac_addr(struct net_device *dev, void *p)
 487 {
 488         eth_mac_addr(dev, p);
 489
 490         gfar_set_mac_for_addr(dev, 0, dev->dev_addr);
 491
 492         return 0;
 493 }
 494
 495 static const struct net_device_ops gfar_netdev_ops = {
 496         .ndo_open = gfar_enet_open,
 497         .ndo_start_xmit = gfar_start_xmit,
 498         .ndo_stop = gfar_close,
 499         .ndo_change_mtu = gfar_change_mtu,
 500         .ndo_set_features = gfar_set_features,
 501         .ndo_set_rx_mode = gfar_set_multi,
 502         .ndo_tx_timeout = gfar_timeout,
 503         .ndo_do_ioctl = gfar_ioctl,
 504         .ndo_get_stats = gfar_get_stats,
 505         .ndo_set_mac_address = gfar_set_mac_addr,
 506         .ndo_validate_addr = eth_validate_addr,
 507 #ifdef CONFIG_NET_POLL_CONTROLLER
 508         .ndo_poll_controller = gfar_netpoll,
 509 #endif
 510 };
 511
 512 static void gfar_ints_disable(struct gfar_private *priv)
 513 {
 514         int i;
 515         for (i = 0; i < priv->num_grps; i++) {
 516                 struct gfar __iomem *regs = priv->gfargrp[i].regs;
 517                 /* Clear IEVENT */
 518                 gfar_write(&regs->ievent, IEVENT_INIT_CLEAR);
 519
 520                 /* Initialize IMASK */
 521                 gfar_write(&regs->imask, IMASK_INIT_CLEAR);
 522         }
 523 }
 524
 525 static void gfar_ints_enable(struct gfar_private *priv)
 526 {
 527         int i;
 528         for (i = 0; i < priv->num_grps; i++) {
 529                 struct gfar __iomem *regs = priv->gfargrp[i].regs;
 530                 /* Unmask the interrupts we look for */
 531                 gfar_write(&regs->imask, IMASK_DEFAULT);
 532         }
 533 }
 534
 535 static int gfar_alloc_tx_queues(struct gfar_private *priv)
 536 {
 537         int i;
 538
 539         for (i = 0; i < priv->num_tx_queues; i++) {
 540                 priv->tx_queue[i] = kzalloc(sizeof(struct gfar_priv_tx_q),
 541                                             GFP_KERNEL);
 542                 if (!priv->tx_queue[i])
 543                         return -ENOMEM;
 544
 545                 priv->tx_queue[i]->tx_skbuff = NULL;
 546                 priv->tx_queue[i]->qindex = i;
 547                 priv->tx_queue[i]->dev = priv->ndev;
 548                 spin_lock_init(&(priv->tx_queue[i]->txlock));
 549         }
 550         return 0;
 551 }
 552
 553 static int gfar_alloc_rx_queues(struct gfar_private *priv)
 554 {
 555         int i;
 556
 557         for (i = 0; i < priv->num_rx_queues; i++) {
 558                 priv->rx_queue[i] = kzalloc(sizeof(struct gfar_priv_rx_q),
 559                                             GFP_KERNEL);
 560                 if (!priv->rx_queue[i])
 561                         return -ENOMEM;
 562
 563                 priv->rx_queue[i]->qindex = i;
 564                 priv->rx_queue[i]->ndev = priv->ndev;
 565         }
 566         return 0;
 567 }
 568
 569 static void gfar_free_tx_queues(struct gfar_private *priv)
 570 {
 571         int i;
 572
 573         for (i = 0; i < priv->num_tx_queues; i++)
 574                 kfree(priv->tx_queue[i]);
 575 }
 576
 577 static void gfar_free_rx_queues(struct gfar_private *priv)
 578 {
 579         int i;
 580
 581         for (i = 0; i < priv->num_rx_queues; i++)
 582                 kfree(priv->rx_queue[i]);
 583 }
 584
 585 static void unmap_group_regs(struct gfar_private *priv)
 586 {
 587         int i;
 588
 589         for (i = 0; i < MAXGROUPS; i++)
 590                 if (priv->gfargrp[i].regs)
 591                         iounmap(priv->gfargrp[i].regs);
 592 }
 593
 594 static void free_gfar_dev(struct gfar_private *priv)
 595 {
 596         int i, j;
 597
 598         for (i = 0; i < priv->num_grps; i++)
 599                 for (j = 0; j < GFAR_NUM_IRQS; j++) {
 600                         kfree(priv->gfargrp[i].irqinfo[j]);
 601                         priv->gfargrp[i].irqinfo[j] = NULL;
 602                 }
 603
 604         free_netdev(priv->ndev);
 605 }
 606
 607 static void disable_napi(struct gfar_private *priv)
 608 {
 609         int i;
 610
 611         for (i = 0; i < priv->num_grps; i++) {
 612                 napi_disable(&priv->gfargrp[i].napi_rx);
 613                 napi_disable(&priv->gfargrp[i].napi_tx);
 614         }
 615 }
 616
 617 static void enable_napi(struct gfar_private *priv)
 618 {
 619         int i;
 620
 621         for (i = 0; i < priv->num_grps; i++) {
 622                 napi_enable(&priv->gfargrp[i].napi_rx);
 623                 napi_enable(&priv->gfargrp[i].napi_tx);
 624         }
 625 }
 626
 627 static int gfar_parse_group(struct device_node *np,
 628                             struct gfar_private *priv, const char *model)
 629 {
 630         struct gfar_priv_grp *grp = &priv->gfargrp[priv->num_grps];
 631         int i;
 632
 633         for (i = 0; i < GFAR_NUM_IRQS; i++) {
 634                 grp->irqinfo[i] = kzalloc(sizeof(struct gfar_irqinfo),
 635                                           GFP_KERNEL);
 636                 if (!grp->irqinfo[i])
 637                         return -ENOMEM;
 638         }
 639
 640         grp->regs = of_iomap(np, 0);
 641         if (!grp->regs)
 642                 return -ENOMEM;
 643
 644         gfar_irq(grp, TX)->irq = irq_of_parse_and_map(np, 0);
 645
 646         /* If we aren't the FEC we have multiple interrupts */
 647         if (model && strcasecmp(model, "FEC")) {
 648                 gfar_irq(grp, RX)->irq = irq_of_parse_and_map(np, 1);
 649                 gfar_irq(grp, ER)->irq = irq_of_parse_and_map(np, 2);
 650                 if (!gfar_irq(grp, TX)->irq ||
 651                     !gfar_irq(grp, RX)->irq ||
 652                     !gfar_irq(grp, ER)->irq)
 653                         return -EINVAL;
 654         }
 655
 656         grp->priv = priv;
 657         spin_lock_init(&grp->grplock);
 658         if (priv->mode == MQ_MG_MODE) {
 659                 u32 rxq_mask, txq_mask;
 660                 int ret;
 661
 662                 grp->rx_bit_map = (DEFAULT_MAPPING >> priv->num_grps);
 663                 grp->tx_bit_map = (DEFAULT_MAPPING >> priv->num_grps);
 664
 665                 ret = of_property_read_u32(np, "fsl,rx-bit-map", &rxq_mask);
 666                 if (!ret) {
 667                         grp->rx_bit_map = rxq_mask ?
 668                         rxq_mask : (DEFAULT_MAPPING >> priv->num_grps);
 669                 }
 670
 671                 ret = of_property_read_u32(np, "fsl,tx-bit-map", &txq_mask);
 672                 if (!ret) {
 673                         grp->tx_bit_map = txq_mask ?
 674                         txq_mask : (DEFAULT_MAPPING >> priv->num_grps);
 675                 }
 676
 677                 if (priv->poll_mode == GFAR_SQ_POLLING) {
 678                         /* One Q per interrupt group: Q0 to G0, Q1 to G1 */
 679                         grp->rx_bit_map = (DEFAULT_MAPPING >> priv->num_grps);
 680                         grp->tx_bit_map = (DEFAULT_MAPPING >> priv->num_grps);
 681                 }
 682         } else {
 683                 grp->rx_bit_map = 0xFF;
 684                 grp->tx_bit_map = 0xFF;
 685         }
 686
 687         /* bit_map's MSB is q0 (from q0 to q7) but, for_each_set_bit parses
 688          * right to left, so we need to revert the 8 bits to get the q index
 689          */
 690         grp->rx_bit_map = bitrev8(grp->rx_bit_map);
 691         grp->tx_bit_map = bitrev8(grp->tx_bit_map);
 692
 693         /* Calculate RSTAT, TSTAT, RQUEUE and TQUEUE values,
 694          * also assign queues to groups
 695          */
 696         for_each_set_bit(i, &grp->rx_bit_map, priv->num_rx_queues) {
 697                 if (!grp->rx_queue)
 698                         grp->rx_queue = priv->rx_queue[i];
 699                 grp->num_rx_queues++;
 700                 grp->rstat |= (RSTAT_CLEAR_RHALT >> i);
 701                 priv->rqueue |= ((RQUEUE_EN0 | RQUEUE_EX0) >> i);
 702                 priv->rx_queue[i]->grp = grp;
 703         }
 704
 705         for_each_set_bit(i, &grp->tx_bit_map, priv->num_tx_queues) {
 706                 if (!grp->tx_queue)
 707                         grp->tx_queue = priv->tx_queue[i];
 708                 grp->num_tx_queues++;
 709                 grp->tstat |= (TSTAT_CLEAR_THALT >> i);
 710                 priv->tqueue |= (TQUEUE_EN0 >> i);
 711                 priv->tx_queue[i]->grp = grp;
 712         }
 713
 714         priv->num_grps++;
 715
 716         return 0;
 717 }
 718
 719 static int gfar_of_group_count(struct device_node *np)
 720 {
 721         struct device_node *child;
 722         int num = 0;
 723
 724         for_each_available_child_of_node(np, child)
 725                 if (!of_node_cmp(child->name, "queue-group"))
 726                         num++;
 727
 728         return num;
 729 }
 730
 731 static int gfar_of_init(struct platform_device *ofdev, struct net_device **pdev)
 732 {
 733         const char *model;
 734         const char *ctype;
 735         const void *mac_addr;
 736         int err = 0, i;
 737         struct net_device *dev = NULL;
 738         struct gfar_private *priv = NULL;
 739         struct device_node *np = ofdev->dev.of_node;
 740         struct device_node *child = NULL;
 741         u32 stash_len = 0;
 742         u32 stash_idx = 0;
 743         unsigned int num_tx_qs, num_rx_qs;
 744         unsigned short mode, poll_mode;
 745
 746         if (!np)
 747                 return -ENODEV;
 748
 749         if (of_device_is_compatible(np, "fsl,etsec2")) {
 750                 mode = MQ_MG_MODE;
 751                 poll_mode = GFAR_SQ_POLLING;
 752         } else {
 753                 mode = SQ_SG_MODE;
 754                 poll_mode = GFAR_SQ_POLLING;
 755         }
 756
 757         if (mode == SQ_SG_MODE) {
 758                 num_tx_qs = 1;
 759                 num_rx_qs = 1;
 760         } else { /* MQ_MG_MODE */
 761                 /* get the actual number of supported groups */
 762                 unsigned int num_grps = gfar_of_group_count(np);
 763
 764                 if (num_grps == 0 || num_grps > MAXGROUPS) {
 765                         dev_err(&ofdev->dev, "Invalid # of int groups(%d)\n",
 766                                 num_grps);
 767                         pr_err("Cannot do alloc_etherdev, aborting\n");
 768                         return -EINVAL;
 769                 }
 770
 771                 if (poll_mode == GFAR_SQ_POLLING) {
 772                         num_tx_qs = num_grps; /* one txq per int group */
 773                         num_rx_qs = num_grps; /* one rxq per int group */
 774                 } else { /* GFAR_MQ_POLLING */
 775                         u32 tx_queues, rx_queues;
 776                         int ret;
 777
 778                         /* parse the num of HW tx and rx queues */
 779                         ret = of_property_read_u32(np, "fsl,num_tx_queues",
 780                                                    &tx_queues);
 781                         num_tx_qs = ret ? 1 : tx_queues;
 782
 783                         ret = of_property_read_u32(np, "fsl,num_rx_queues",
 784                                                    &rx_queues);
 785                         num_rx_qs = ret ? 1 : rx_queues;
 786                 }
 787         }
 788
 789         if (num_tx_qs > MAX_TX_QS) {
 790                 pr_err("num_tx_qs(=%d) greater than MAX_TX_QS(=%d)\n",
 791                        num_tx_qs, MAX_TX_QS);
 792                 pr_err("Cannot do alloc_etherdev, aborting\n");
 793                 return -EINVAL;
 794         }
 795
 796         if (num_rx_qs > MAX_RX_QS) {
 797                 pr_err("num_rx_qs(=%d) greater than MAX_RX_QS(=%d)\n",
 798                        num_rx_qs, MAX_RX_QS);
 799                 pr_err("Cannot do alloc_etherdev, aborting\n");
 800                 return -EINVAL;
 801         }
 802
 803         *pdev = alloc_etherdev_mq(sizeof(*priv), num_tx_qs);
 804         dev = *pdev;
 805         if (NULL == dev)
 806                 return -ENOMEM;
 807
 808         priv = netdev_priv(dev);
 809         priv->ndev = dev;
 810
 811         priv->mode = mode;
 812         priv->poll_mode = poll_mode;
 813
 814         priv->num_tx_queues = num_tx_qs;
 815         netif_set_real_num_rx_queues(dev, num_rx_qs);
 816         priv->num_rx_queues = num_rx_qs;
 817
 818         err = gfar_alloc_tx_queues(priv);
 819         if (err)
 820                 goto tx_alloc_failed;
 821
 822         err = gfar_alloc_rx_queues(priv);
 823         if (err)
 824                 goto rx_alloc_failed;
 825
 826         err = of_property_read_string(np, "model", &model);
 827         if (err) {
 828                 pr_err("Device model property missing, aborting\n");
 829                 goto rx_alloc_failed;
 830         }
 831
 832         /* Init Rx queue filer rule set linked list */
 833         INIT_LIST_HEAD(&priv->rx_list.list);
 834         priv->rx_list.count = 0;
 835         mutex_init(&priv->rx_queue_access);
 836
 837         for (i = 0; i < MAXGROUPS; i++)
 838                 priv->gfargrp[i].regs = NULL;
 839
 840         /* Parse and initialize group specific information */
 841         if (priv->mode == MQ_MG_MODE) {
 842                 for_each_available_child_of_node(np, child) {
 843                         if (of_node_cmp(child->name, "queue-group"))
 844                                 continue;
 845
 846                         err = gfar_parse_group(child, priv, model);
 847                         if (err)
 848                                 goto err_grp_init;
 849                 }
 850         } else { /* SQ_SG_MODE */
 851                 err = gfar_parse_group(np, priv, model);
 852                 if (err)
 853                         goto err_grp_init;
 854         }
 855
 856         if (of_property_read_bool(np, "bd-stash")) {
 857                 priv->device_flags |= FSL_GIANFAR_DEV_HAS_BD_STASHING;
 858                 priv->bd_stash_en = 1;
 859         }
 860
 861         err = of_property_read_u32(np, "rx-stash-len", &stash_len);
 862
 863         if (err == 0)
 864                 priv->rx_stash_size = stash_len;
 865
 866         err = of_property_read_u32(np, "rx-stash-idx", &stash_idx);
 867
 868         if (err == 0)
 869                 priv->rx_stash_index = stash_idx;
 870
 871         if (stash_len || stash_idx)
 872                 priv->device_flags |= FSL_GIANFAR_DEV_HAS_BUF_STASHING;
 873
 874         mac_addr = of_get_mac_address(np);
 875
 876         if (mac_addr)
 877                 memcpy(dev->dev_addr, mac_addr, ETH_ALEN);
 878
 879         if (model && !strcasecmp(model, "TSEC"))
 880                 priv->device_flags |= FSL_GIANFAR_DEV_HAS_GIGABIT |
 881                                      FSL_GIANFAR_DEV_HAS_COALESCE |
 882                                      FSL_GIANFAR_DEV_HAS_RMON |
 883                                      FSL_GIANFAR_DEV_HAS_MULTI_INTR;
 884
 885         if (model && !strcasecmp(model, "eTSEC"))
 886                 priv->device_flags |= FSL_GIANFAR_DEV_HAS_GIGABIT |
 887                                      FSL_GIANFAR_DEV_HAS_COALESCE |
 888                                      FSL_GIANFAR_DEV_HAS_RMON |
 889                                      FSL_GIANFAR_DEV_HAS_MULTI_INTR |
 890                                      FSL_GIANFAR_DEV_HAS_CSUM |
 891                                      FSL_GIANFAR_DEV_HAS_VLAN |
 892                                      FSL_GIANFAR_DEV_HAS_MAGIC_PACKET |
 893                                      FSL_GIANFAR_DEV_HAS_EXTENDED_HASH |
 894                                      FSL_GIANFAR_DEV_HAS_TIMER;
 895
 896         err = of_property_read_string(np, "phy-connection-type", &ctype);
 897
 898         /* We only care about rgmii-id.  The rest are autodetected */
 899         if (err == 0 && !strcmp(ctype, "rgmii-id"))
 900                 priv->interface = PHY_INTERFACE_MODE_RGMII_ID;
 901         else
 902                 priv->interface = PHY_INTERFACE_MODE_MII;
 903
 904         if (of_find_property(np, "fsl,magic-packet", NULL))
 905                 priv->device_flags |= FSL_GIANFAR_DEV_HAS_MAGIC_PACKET;
 906
 907         if (of_get_property(np, "fsl,wake-on-filer", NULL))
 908                 priv->device_flags |= FSL_GIANFAR_DEV_HAS_WAKE_ON_FILER;
 909
 910         priv->phy_node = of_parse_phandle(np, "phy-handle", 0);
 911
 912         /* In the case of a fixed PHY, the DT node associated
 913          * to the PHY is the Ethernet MAC DT node.
 914          */
 915         if (!priv->phy_node && of_phy_is_fixed_link(np)) {
 916                 err = of_phy_register_fixed_link(np);
 917                 if (err)
 918                         goto err_grp_init;
 919
 920                 priv->phy_node = of_node_get(np);
 921         }
 922
 923         /* Find the TBI PHY.  If it's not there, we don't support SGMII */
 924         priv->tbi_node = of_parse_phandle(np, "tbi-handle", 0);
 925
 926         return 0;
 927
 928 err_grp_init:
 929         unmap_group_regs(priv);
 930 rx_alloc_failed:
 931         gfar_free_rx_queues(priv);
 932 tx_alloc_failed:
 933         gfar_free_tx_queues(priv);
 934         free_gfar_dev(priv);
 935         return err;
 936 }
 937
 938 static int gfar_hwtstamp_set(struct net_device *netdev, struct ifreq *ifr)
 939 {
 940         struct hwtstamp_config config;
 941         struct gfar_private *priv = netdev_priv(netdev);
 942
 943         if (copy_from_user(&config, ifr->ifr_data, sizeof(config)))
 944                 return -EFAULT;
 945
 946         /* reserved for future extensions */
 947         if (config.flags)
 948                 return -EINVAL;
 949
 950         switch (config.tx_type) {
 951         case HWTSTAMP_TX_OFF:
 952                 priv->hwts_tx_en = 0;
 953                 break;
 954         case HWTSTAMP_TX_ON:
 955                 if (!(priv->device_flags & FSL_GIANFAR_DEV_HAS_TIMER))
 956                         return -ERANGE;
 957                 priv->hwts_tx_en = 1;
 958                 break;
 959         default:
 960                 return -ERANGE;
 961         }
 962
 963         switch (config.rx_filter) {
 964         case HWTSTAMP_FILTER_NONE:
 965                 if (priv->hwts_rx_en) {
 966                         priv->hwts_rx_en = 0;
 967                         reset_gfar(netdev);
 968                 }
 969                 break;
 970         default:
 971                 if (!(priv->device_flags & FSL_GIANFAR_DEV_HAS_TIMER))
 972                         return -ERANGE;
 973                 if (!priv->hwts_rx_en) {
 974                         priv->hwts_rx_en = 1;
 975                         reset_gfar(netdev);
 976                 }
 977                 config.rx_filter = HWTSTAMP_FILTER_ALL;
 978                 break;
 979         }
 980
 981         return copy_to_user(ifr->ifr_data, &config, sizeof(config)) ?
 982                 -EFAULT : 0;
 983 }
 984
 985 static int gfar_hwtstamp_get(struct net_device *netdev, struct ifreq *ifr)
 986 {
 987         struct hwtstamp_config config;
 988         struct gfar_private *priv = netdev_priv(netdev);
 989
 990         config.flags = 0;
 991         config.tx_type = priv->hwts_tx_en ? HWTSTAMP_TX_ON : HWTSTAMP_TX_OFF;
 992         config.rx_filter = (priv->hwts_rx_en ?
 993                             HWTSTAMP_FILTER_ALL : HWTSTAMP_FILTER_NONE);
 994
 995         return copy_to_user(ifr->ifr_data, &config, sizeof(config)) ?
 996                 -EFAULT : 0;
 997 }
 998
 999 static int gfar_ioctl(struct net_device *dev, struct ifreq *rq, int cmd)
1000 {
1001         struct gfar_private *priv = netdev_priv(dev);
1002
1003         if (!netif_running(dev))
1004                 return -EINVAL;
1005
1006         if (cmd == SIOCSHWTSTAMP)
1007                 return gfar_hwtstamp_set(dev, rq);
1008         if (cmd == SIOCGHWTSTAMP)
1009                 return gfar_hwtstamp_get(dev, rq);
1010
1011         if (!priv->phydev)
1012                 return -ENODEV;
1013
1014         return phy_mii_ioctl(priv->phydev, rq, cmd);
1015 }
1016
1017 static u32 cluster_entry_per_class(struct gfar_private *priv, u32 rqfar,
1018                                    u32 class)
1019 {
1020         u32 rqfpr = FPR_FILER_MASK;
1021         u32 rqfcr = 0x0;
1022
1023         rqfar--;
1024         rqfcr = RQFCR_CLE | RQFCR_PID_MASK | RQFCR_CMP_EXACT;
1025         priv->ftp_rqfpr[rqfar] = rqfpr;
1026         priv->ftp_rqfcr[rqfar] = rqfcr;
1027         gfar_write_filer(priv, rqfar, rqfcr, rqfpr);
1028
1029         rqfar--;
1030         rqfcr = RQFCR_CMP_NOMATCH;
1031         priv->ftp_rqfpr[rqfar] = rqfpr;
1032         priv->ftp_rqfcr[rqfar] = rqfcr;
1033         gfar_write_filer(priv, rqfar, rqfcr, rqfpr);
1034
1035         rqfar--;
1036         rqfcr = RQFCR_CMP_EXACT | RQFCR_PID_PARSE | RQFCR_CLE | RQFCR_AND;
1037         rqfpr = class;
1038         priv->ftp_rqfcr[rqfar] = rqfcr;
1039         priv->ftp_rqfpr[rqfar] = rqfpr;
1040         gfar_write_filer(priv, rqfar, rqfcr, rqfpr);
1041
1042         rqfar--;
1043         rqfcr = RQFCR_CMP_EXACT | RQFCR_PID_MASK | RQFCR_AND;
1044         rqfpr = class;
1045         priv->ftp_rqfcr[rqfar] = rqfcr;
1046         priv->ftp_rqfpr[rqfar] = rqfpr;
1047         gfar_write_filer(priv, rqfar, rqfcr, rqfpr);
1048
1049         return rqfar;
1050 }
1051
1052 static void gfar_init_filer_table(struct gfar_private *priv)
1053 {
1054         int i = 0x0;
1055         u32 rqfar = MAX_FILER_IDX;
1056         u32 rqfcr = 0x0;
1057         u32 rqfpr = FPR_FILER_MASK;
1058
1059         /* Default rule */
1060         rqfcr = RQFCR_CMP_MATCH;
1061         priv->ftp_rqfcr[rqfar] = rqfcr;
1062         priv->ftp_rqfpr[rqfar] = rqfpr;
1063         gfar_write_filer(priv, rqfar, rqfcr, rqfpr);
1064
1065         rqfar = cluster_entry_per_class(priv, rqfar, RQFPR_IPV6);
1066         rqfar = cluster_entry_per_class(priv, rqfar, RQFPR_IPV6 | RQFPR_UDP);
1067         rqfar = cluster_entry_per_class(priv, rqfar, RQFPR_IPV6 | RQFPR_TCP);
1068         rqfar = cluster_entry_per_class(priv, rqfar, RQFPR_IPV4);
1069         rqfar = cluster_entry_per_class(priv, rqfar, RQFPR_IPV4 | RQFPR_UDP);
1070         rqfar = cluster_entry_per_class(priv, rqfar, RQFPR_IPV4 | RQFPR_TCP);
1071
1072         /* cur_filer_idx indicated the first non-masked rule */
1073         priv->cur_filer_idx = rqfar;
1074
1075         /* Rest are masked rules */
1076         rqfcr = RQFCR_CMP_NOMATCH;
1077         for (i = 0; i < rqfar; i++) {
1078                 priv->ftp_rqfcr[i] = rqfcr;
1079                 priv->ftp_rqfpr[i] = rqfpr;
1080                 gfar_write_filer(priv, i, rqfcr, rqfpr);
1081         }
1082 }
1083
1084 #ifdef CONFIG_PPC
1085 static void __gfar_detect_errata_83xx(struct gfar_private *priv)
1086 {
1087         unsigned int pvr = mfspr(SPRN_PVR);
1088         unsigned int svr = mfspr(SPRN_SVR);
1089         unsigned int mod = (svr >> 16) & 0xfff6; /* w/o E suffix */
1090         unsigned int rev = svr & 0xffff;
1091
1092         /* MPC8313 Rev 2.0 and higher; All MPC837x */
1093         if ((pvr == 0x80850010 && mod == 0x80b0 && rev >= 0x0020) ||
1094             (pvr == 0x80861010 && (mod & 0xfff9) == 0x80c0))
1095                 priv->errata |= GFAR_ERRATA_74;
1096
1097         /* MPC8313 and MPC837x all rev */
1098         if ((pvr == 0x80850010 && mod == 0x80b0) ||
1099             (pvr == 0x80861010 && (mod & 0xfff9) == 0x80c0))
1100                 priv->errata |= GFAR_ERRATA_76;
1101
1102         /* MPC8313 Rev < 2.0 */
1103         if (pvr == 0x80850010 && mod == 0x80b0 && rev < 0x0020)
1104                 priv->errata |= GFAR_ERRATA_12;
1105 }
1106
1107 static void __gfar_detect_errata_85xx(struct gfar_private *priv)
1108 {
1109         unsigned int svr = mfspr(SPRN_SVR);
1110
1111         if ((SVR_SOC_VER(svr) == SVR_8548) && (SVR_REV(svr) == 0x20))
1112                 priv->errata |= GFAR_ERRATA_12;
1113         if (((SVR_SOC_VER(svr) == SVR_P2020) && (SVR_REV(svr) < 0x20)) ||
1114             ((SVR_SOC_VER(svr) == SVR_P2010) && (SVR_REV(svr) < 0x20)))
1115                 priv->errata |= GFAR_ERRATA_76; /* aka eTSEC 20 */
1116 }
1117 #endif
1118
1119 static void gfar_detect_errata(struct gfar_private *priv)
1120 {
1121         struct device *dev = &priv->ofdev->dev;
1122
1123         /* no plans to fix */
1124         priv->errata |= GFAR_ERRATA_A002;
1125
1126 #ifdef CONFIG_PPC
1127         if (pvr_version_is(PVR_VER_E500V1) || pvr_version_is(PVR_VER_E500V2))
1128                 __gfar_detect_errata_85xx(priv);
1129         else /* non-mpc85xx parts, i.e. e300 core based */
1130                 __gfar_detect_errata_83xx(priv);
1131 #endif
1132
1133         if (priv->errata)
1134                 dev_info(dev, "enabled errata workarounds, flags: 0x%x\n",
1135                          priv->errata);
1136 }
1137
1138 void gfar_mac_reset(struct gfar_private *priv)
1139 {
1140         struct gfar __iomem *regs = priv->gfargrp[0].regs;
1141         u32 tempval;
1142
1143         /* Reset MAC layer */
1144         gfar_write(&regs->maccfg1, MACCFG1_SOFT_RESET);
1145
1146         /* We need to delay at least 3 TX clocks */
1147         udelay(3);
1148
1149         /* the soft reset bit is not self-resetting, so we need to
1150          * clear it before resuming normal operation
1151          */
1152         gfar_write(&regs->maccfg1, 0);
1153
1154         udelay(3);
1155
1156         gfar_rx_offload_en(priv);
1157
1158         /* Initialize the max receive frame/buffer lengths */
1159         gfar_write(&regs->maxfrm, GFAR_JUMBO_FRAME_SIZE);
1160         gfar_write(&regs->mrblr, GFAR_RXB_SIZE);
1161
1162         /* Initialize the Minimum Frame Length Register */
1163         gfar_write(&regs->minflr, MINFLR_INIT_SETTINGS);
1164
1165         /* Initialize MACCFG2. */
1166         tempval = MACCFG2_INIT_SETTINGS;
1167
1168         /* eTSEC74 erratum: Rx frames of length MAXFRM or MAXFRM-1
1169          * are marked as truncated.  Avoid this by MACCFG2[Huge Frame]=1,
1170          * and by checking RxBD[LG] and discarding larger than MAXFRM.
1171          */
1172         if (gfar_has_errata(priv, GFAR_ERRATA_74))
1173                 tempval |= MACCFG2_HUGEFRAME | MACCFG2_LENGTHCHECK;
1174
1175         gfar_write(&regs->maccfg2, tempval);
1176
1177         /* Clear mac addr hash registers */
1178         gfar_write(&regs->igaddr0, 0);
1179         gfar_write(&regs->igaddr1, 0);
1180         gfar_write(&regs->igaddr2, 0);
1181         gfar_write(&regs->igaddr3, 0);
1182         gfar_write(&regs->igaddr4, 0);
1183         gfar_write(&regs->igaddr5, 0);
1184         gfar_write(&regs->igaddr6, 0);
1185         gfar_write(&regs->igaddr7, 0);
1186
1187         gfar_write(&regs->gaddr0, 0);
1188         gfar_write(&regs->gaddr1, 0);
1189         gfar_write(&regs->gaddr2, 0);
1190         gfar_write(&regs->gaddr3, 0);
1191         gfar_write(&regs->gaddr4, 0);
1192         gfar_write(&regs->gaddr5, 0);
1193         gfar_write(&regs->gaddr6, 0);
1194         gfar_write(&regs->gaddr7, 0);
1195
1196         if (priv->extended_hash)
1197                 gfar_clear_exact_match(priv->ndev);
1198
1199         gfar_mac_rx_config(priv);
1200
1201         gfar_mac_tx_config(priv);
1202
1203         gfar_set_mac_address(priv->ndev);
1204
1205         gfar_set_multi(priv->ndev);
1206
1207         /* clear ievent and imask before configuring coalescing */
1208         gfar_ints_disable(priv);
1209
1210         /* Configure the coalescing support */
1211         gfar_configure_coalescing_all(priv);
1212 }
1213
1214 static void gfar_hw_init(struct gfar_private *priv)
1215 {
1216         struct gfar __iomem *regs = priv->gfargrp[0].regs;
1217         u32 attrs;
1218
1219         /* Stop the DMA engine now, in case it was running before
1220          * (The firmware could have used it, and left it running).
1221          */
1222         gfar_halt(priv);
1223
1224         gfar_mac_reset(priv);
1225
1226         /* Zero out the rmon mib registers if it has them */
1227         if (priv->device_flags & FSL_GIANFAR_DEV_HAS_RMON) {
1228                 memset_io(&(regs->rmon), 0, sizeof(struct rmon_mib));
1229
1230                 /* Mask off the CAM interrupts */
1231                 gfar_write(&regs->rmon.cam1, 0xffffffff);
1232                 gfar_write(&regs->rmon.cam2, 0xffffffff);
1233         }
1234
1235         /* Initialize ECNTRL */
1236         gfar_write(&regs->ecntrl, ECNTRL_INIT_SETTINGS);
1237
1238         /* Set the extraction length and index */
1239         attrs = ATTRELI_EL(priv->rx_stash_size) |
1240                 ATTRELI_EI(priv->rx_stash_index);
1241
1242         gfar_write(&regs->attreli, attrs);
1243
1244         /* Start with defaults, and add stashing
1245          * depending on driver parameters
1246          */
1247         attrs = ATTR_INIT_SETTINGS;
1248
1249         if (priv->bd_stash_en)
1250                 attrs |= ATTR_BDSTASH;
1251
1252         if (priv->rx_stash_size != 0)
1253                 attrs |= ATTR_BUFSTASH;
1254
1255         gfar_write(&regs->attr, attrs);
1256
1257         /* FIFO configs */
1258         gfar_write(&regs->fifo_tx_thr, DEFAULT_FIFO_TX_THR);
1259         gfar_write(&regs->fifo_tx_starve, DEFAULT_FIFO_TX_STARVE);
1260         gfar_write(&regs->fifo_tx_starve_shutoff, DEFAULT_FIFO_TX_STARVE_OFF);
1261
1262         /* Program the interrupt steering regs, only for MG devices */
1263         if (priv->num_grps > 1)
1264                 gfar_write_isrg(priv);
1265 }
1266
1267 static void gfar_init_addr_hash_table(struct gfar_private *priv)
1268 {
1269         struct gfar __iomem *regs = priv->gfargrp[0].regs;
1270
1271         if (priv->device_flags & FSL_GIANFAR_DEV_HAS_EXTENDED_HASH) {
1272                 priv->extended_hash = 1;
1273                 priv->hash_width = 9;
1274
1275                 priv->hash_regs[0] = &regs->igaddr0;
1276                 priv->hash_regs[1] = &regs->igaddr1;
1277                 priv->hash_regs[2] = &regs->igaddr2;
1278                 priv->hash_regs[3] = &regs->igaddr3;
1279                 priv->hash_regs[4] = &regs->igaddr4;
1280                 priv->hash_regs[5] = &regs->igaddr5;
1281                 priv->hash_regs[6] = &regs->igaddr6;
1282                 priv->hash_regs[7] = &regs->igaddr7;
1283                 priv->hash_regs[8] = &regs->gaddr0;
1284                 priv->hash_regs[9] = &regs->gaddr1;
1285                 priv->hash_regs[10] = &regs->gaddr2;
1286                 priv->hash_regs[11] = &regs->gaddr3;
1287                 priv->hash_regs[12] = &regs->gaddr4;
1288                 priv->hash_regs[13] = &regs->gaddr5;
1289                 priv->hash_regs[14] = &regs->gaddr6;
1290                 priv->hash_regs[15] = &regs->gaddr7;
1291
1292         } else {
1293                 priv->extended_hash = 0;
1294                 priv->hash_width = 8;
1295
1296                 priv->hash_regs[0] = &regs->gaddr0;
1297                 priv->hash_regs[1] = &regs->gaddr1;
1298                 priv->hash_regs[2] = &regs->gaddr2;
1299                 priv->hash_regs[3] = &regs->gaddr3;
1300                 priv->hash_regs[4] = &regs->gaddr4;
1301                 priv->hash_regs[5] = &regs->gaddr5;
1302                 priv->hash_regs[6] = &regs->gaddr6;
1303                 priv->hash_regs[7] = &regs->gaddr7;
1304         }
1305 }
1306
1307 /* Set up the ethernet device structure, private data,
1308  * and anything else we need before we start
1309  */
1310 static int gfar_probe(struct platform_device *ofdev)
1311 {
1312         struct net_device *dev = NULL;
1313         struct gfar_private *priv = NULL;
1314         int err = 0, i;
1315
1316         err = gfar_of_init(ofdev, &dev);
1317
1318         if (err)
1319                 return err;
1320
1321         priv = netdev_priv(dev);
1322         priv->ndev = dev;
1323         priv->ofdev = ofdev;
1324         priv->dev = &ofdev->dev;
1325         SET_NETDEV_DEV(dev, &ofdev->dev);
1326
1327         INIT_WORK(&priv->reset_task, gfar_reset_task);
1328
1329         platform_set_drvdata(ofdev, priv);
1330
1331         gfar_detect_errata(priv);
1332
1333         /* Set the dev->base_addr to the gfar reg region */
1334         dev->base_addr = (unsigned long) priv->gfargrp[0].regs;
1335
1336         /* Fill in the dev structure */
1337         dev->watchdog_timeo = TX_TIMEOUT;
1338         dev->mtu = 1500;
1339         dev->netdev_ops = &gfar_netdev_ops;
1340         dev->ethtool_ops = &gfar_ethtool_ops;
1341
1342         /* Register for napi ...We are registering NAPI for each grp */
1343         for (i = 0; i < priv->num_grps; i++) {
1344                 if (priv->poll_mode == GFAR_SQ_POLLING) {
1345                         netif_napi_add(dev, &priv->gfargrp[i].napi_rx,
1346                                        gfar_poll_rx_sq, GFAR_DEV_WEIGHT);
1347                         netif_tx_napi_add(dev, &priv->gfargrp[i].napi_tx,
1348                                        gfar_poll_tx_sq, 2);
1349                 } else {
1350                         netif_napi_add(dev, &priv->gfargrp[i].napi_rx,
1351                                        gfar_poll_rx, GFAR_DEV_WEIGHT);
1352                         netif_tx_napi_add(dev, &priv->gfargrp[i].napi_tx,
1353                                        gfar_poll_tx, 2);
1354                 }
1355         }
1356
1357         if (priv->device_flags & FSL_GIANFAR_DEV_HAS_CSUM) {
1358                 dev->hw_features = NETIF_F_IP_CSUM | NETIF_F_SG |
1359                                    NETIF_F_RXCSUM;
1360                 dev->features |= NETIF_F_IP_CSUM | NETIF_F_SG |
1361                                  NETIF_F_RXCSUM | NETIF_F_HIGHDMA;
1362         }
1363
1364         if (priv->device_flags & FSL_GIANFAR_DEV_HAS_VLAN) {
1365                 dev->hw_features |= NETIF_F_HW_VLAN_CTAG_TX |
1366                                     NETIF_F_HW_VLAN_CTAG_RX;
1367                 dev->features |= NETIF_F_HW_VLAN_CTAG_RX;
1368         }
1369
1370         dev->priv_flags |= IFF_LIVE_ADDR_CHANGE;
1371
1372         gfar_init_addr_hash_table(priv);
1373
1374         /* Insert receive time stamps into padding alignment bytes */
1375         if (priv->device_flags & FSL_GIANFAR_DEV_HAS_TIMER)
1376                 priv->padding = 8;
1377
1378         if (dev->features & NETIF_F_IP_CSUM ||
1379             priv->device_flags & FSL_GIANFAR_DEV_HAS_TIMER)
1380                 dev->needed_headroom = GMAC_FCB_LEN;
1381
1382         /* Initializing some of the rx/tx queue level parameters */
1383         for (i = 0; i < priv->num_tx_queues; i++) {
1384                 priv->tx_queue[i]->tx_ring_size = DEFAULT_TX_RING_SIZE;
1385                 priv->tx_queue[i]->num_txbdfree = DEFAULT_TX_RING_SIZE;
1386                 priv->tx_queue[i]->txcoalescing = DEFAULT_TX_COALESCE;
1387                 priv->tx_queue[i]->txic = DEFAULT_TXIC;
1388         }
1389
1390         for (i = 0; i < priv->num_rx_queues; i++) {
1391                 priv->rx_queue[i]->rx_ring_size = DEFAULT_RX_RING_SIZE;
1392                 priv->rx_queue[i]->rxcoalescing = DEFAULT_RX_COALESCE;
1393                 priv->rx_queue[i]->rxic = DEFAULT_RXIC;
1394         }
1395
1396         /* always enable rx filer */
1397         priv->rx_filer_enable = 1;
1398         /* Enable most messages by default */
1399         priv->msg_enable = (NETIF_MSG_IFUP << 1 ) - 1;
1400         /* use pritority h/w tx queue scheduling for single queue devices */
1401         if (priv->num_tx_queues == 1)
1402                 priv->prio_sched_en = 1;
1403
1404         set_bit(GFAR_DOWN, &priv->state);
1405
1406         gfar_hw_init(priv);
1407
1408         /* Carrier starts down, phylib will bring it up */
1409         netif_carrier_off(dev);
1410
1411         err = register_netdev(dev);
1412
1413         if (err) {
1414                 pr_err("%s: Cannot register net device, aborting\n", dev->name);
1415                 goto register_fail;
1416         }
1417
1418         if (priv->device_flags & FSL_GIANFAR_DEV_HAS_MAGIC_PACKET)
1419                 priv->wol_supported |= GFAR_WOL_MAGIC;
1420
1421         if ((priv->device_flags & FSL_GIANFAR_DEV_HAS_WAKE_ON_FILER) &&
1422             priv->rx_filer_enable)
1423                 priv->wol_supported |= GFAR_WOL_FILER_UCAST;
1424
1425         device_set_wakeup_capable(&ofdev->dev, priv->wol_supported);
1426
1427         /* fill out IRQ number and name fields */
1428         for (i = 0; i < priv->num_grps; i++) {
1429                 struct gfar_priv_grp *grp = &priv->gfargrp[i];
1430                 if (priv->device_flags & FSL_GIANFAR_DEV_HAS_MULTI_INTR) {
1431                         sprintf(gfar_irq(grp, TX)->name, "%s%s%c%s",
1432                                 dev->name, "_g", '0' + i, "_tx");
1433                         sprintf(gfar_irq(grp, RX)->name, "%s%s%c%s",
1434                                 dev->name, "_g", '0' + i, "_rx");
1435                         sprintf(gfar_irq(grp, ER)->name, "%s%s%c%s",
1436                                 dev->name, "_g", '0' + i, "_er");
1437                 } else
1438                         strcpy(gfar_irq(grp, TX)->name, dev->name);
1439         }
1440
1441         /* Initialize the filer table */
1442         gfar_init_filer_table(priv);
1443
1444         /* Print out the device info */
1445         netdev_info(dev, "mac: %pM\n", dev->dev_addr);
1446
1447         /* Even more device info helps when determining which kernel
1448          * provided which set of benchmarks.
1449          */
1450         netdev_info(dev, "Running with NAPI enabled\n");
1451         for (i = 0; i < priv->num_rx_queues; i++)
1452                 netdev_info(dev, "RX BD ring size for Q[%d]: %d\n",
1453                             i, priv->rx_queue[i]->rx_ring_size);
1454         for (i = 0; i < priv->num_tx_queues; i++)
1455                 netdev_info(dev, "TX BD ring size for Q[%d]: %d\n",
1456                             i, priv->tx_queue[i]->tx_ring_size);
1457
1458         return 0;
1459
1460 register_fail:
1461         unmap_group_regs(priv);
1462         gfar_free_rx_queues(priv);
1463         gfar_free_tx_queues(priv);
1464         of_node_put(priv->phy_node);
1465         of_node_put(priv->tbi_node);
1466         free_gfar_dev(priv);
1467         return err;
1468 }
1469
1470 static int gfar_remove(struct platform_device *ofdev)
1471 {
1472         struct gfar_private *priv = platform_get_drvdata(ofdev);
1473
1474         of_node_put(priv->phy_node);
1475         of_node_put(priv->tbi_node);
1476
1477         unregister_netdev(priv->ndev);
1478         unmap_group_regs(priv);
1479         gfar_free_rx_queues(priv);
1480         gfar_free_tx_queues(priv);
1481         free_gfar_dev(priv);
1482
1483         return 0;
1484 }
1485
1486 #ifdef CONFIG_PM
1487
1488 static void __gfar_filer_disable(struct gfar_private *priv)
1489 {
1490         struct gfar __iomem *regs = priv->gfargrp[0].regs;
1491         u32 temp;
1492
1493         temp = gfar_read(&regs->rctrl);
1494         temp &= ~(RCTRL_FILREN | RCTRL_PRSDEP_INIT);
1495         gfar_write(&regs->rctrl, temp);
1496 }
1497
1498 static void __gfar_filer_enable(struct gfar_private *priv)
1499 {
1500         struct gfar __iomem *regs = priv->gfargrp[0].regs;
1501         u32 temp;
1502
1503         temp = gfar_read(&regs->rctrl);
1504         temp |= RCTRL_FILREN | RCTRL_PRSDEP_INIT;
1505         gfar_write(&regs->rctrl, temp);
1506 }
1507
1508 /* Filer rules implementing wol capabilities */
1509 static void gfar_filer_config_wol(struct gfar_private *priv)
1510 {
1511         unsigned int i;
1512         u32 rqfcr;
1513
1514         __gfar_filer_disable(priv);
1515
1516         /* clear the filer table, reject any packet by default */
1517         rqfcr = RQFCR_RJE | RQFCR_CMP_MATCH;
1518         for (i = 0; i <= MAX_FILER_IDX; i++)
1519                 gfar_write_filer(priv, i, rqfcr, 0);
1520
1521         i = 0;
1522         if (priv->wol_opts & GFAR_WOL_FILER_UCAST) {
1523                 /* unicast packet, accept it */
1524                 struct net_device *ndev = priv->ndev;
1525                 /* get the default rx queue index */
1526                 u8 qindex = (u8)priv->gfargrp[0].rx_queue->qindex;
1527                 u32 dest_mac_addr = (ndev->dev_addr[0] << 16) |
1528                                     (ndev->dev_addr[1] << 8) |
1529                                      ndev->dev_addr[2];
1530
1531                 rqfcr = (qindex << 10) | RQFCR_AND |
1532                         RQFCR_CMP_EXACT | RQFCR_PID_DAH;
1533
1534                 gfar_write_filer(priv, i++, rqfcr, dest_mac_addr);
1535
1536                 dest_mac_addr = (ndev->dev_addr[3] << 16) |
1537                                 (ndev->dev_addr[4] << 8) |
1538                                  ndev->dev_addr[5];
1539                 rqfcr = (qindex << 10) | RQFCR_GPI |
1540                         RQFCR_CMP_EXACT | RQFCR_PID_DAL;
1541                 gfar_write_filer(priv, i++, rqfcr, dest_mac_addr);
1542         }
1543
1544         __gfar_filer_enable(priv);
1545 }
1546
1547 static void gfar_filer_restore_table(struct gfar_private *priv)
1548 {
1549         u32 rqfcr, rqfpr;
1550         unsigned int i;
1551
1552         __gfar_filer_disable(priv);
1553
1554         for (i = 0; i <= MAX_FILER_IDX; i++) {
1555                 rqfcr = priv->ftp_rqfcr[i];
1556                 rqfpr = priv->ftp_rqfpr[i];
1557                 gfar_write_filer(priv, i, rqfcr, rqfpr);
1558         }
1559
1560         __gfar_filer_enable(priv);
1561 }
1562
1563 /* gfar_start() for Rx only and with the FGPI filer interrupt enabled */
1564 static void gfar_start_wol_filer(struct gfar_private *priv)
1565 {
1566         struct gfar __iomem *regs = priv->gfargrp[0].regs;
1567         u32 tempval;
1568         int i = 0;
1569
1570         /* Enable Rx hw queues */
1571         gfar_write(&regs->rqueue, priv->rqueue);
1572
1573         /* Initialize DMACTRL to have WWR and WOP */
1574         tempval = gfar_read(&regs->dmactrl);
1575         tempval |= DMACTRL_INIT_SETTINGS;
1576         gfar_write(&regs->dmactrl, tempval);
1577
1578         /* Make sure we aren't stopped */
1579         tempval = gfar_read(&regs->dmactrl);
1580         tempval &= ~DMACTRL_GRS;
1581         gfar_write(&regs->dmactrl, tempval);
1582
1583         for (i = 0; i < priv->num_grps; i++) {
1584                 regs = priv->gfargrp[i].regs;
1585                 /* Clear RHLT, so that the DMA starts polling now */
1586                 gfar_write(&regs->rstat, priv->gfargrp[i].rstat);
1587                 /* enable the Filer General Purpose Interrupt */
1588                 gfar_write(&regs->imask, IMASK_FGPI);
1589         }
1590
1591         /* Enable Rx DMA */
1592         tempval = gfar_read(&regs->maccfg1);
1593         tempval |= MACCFG1_RX_EN;
1594         gfar_write(&regs->maccfg1, tempval);
1595 }
1596
1597 static int gfar_suspend(struct device *dev)
1598 {
1599         struct gfar_private *priv = dev_get_drvdata(dev);
1600         struct net_device *ndev = priv->ndev;
1601         struct gfar __iomem *regs = priv->gfargrp[0].regs;
1602         u32 tempval;
1603         u16 wol = priv->wol_opts;
1604
1605         if (!netif_running(ndev))
1606                 return 0;
1607
1608         disable_napi(priv);
1609         netif_tx_lock(ndev);
1610         netif_device_detach(ndev);
1611         netif_tx_unlock(ndev);
1612
1613         gfar_halt(priv);
1614
1615         if (wol & GFAR_WOL_MAGIC) {
1616                 /* Enable interrupt on Magic Packet */
1617                 gfar_write(&regs->imask, IMASK_MAG);
1618
1619                 /* Enable Magic Packet mode */
1620                 tempval = gfar_read(&regs->maccfg2);
1621                 tempval |= MACCFG2_MPEN;
1622                 gfar_write(&regs->maccfg2, tempval);
1623
1624                 /* re-enable the Rx block */
1625                 tempval = gfar_read(&regs->maccfg1);
1626                 tempval |= MACCFG1_RX_EN;
1627                 gfar_write(&regs->maccfg1, tempval);
1628
1629         } else if (wol & GFAR_WOL_FILER_UCAST) {
1630                 gfar_filer_config_wol(priv);
1631                 gfar_start_wol_filer(priv);
1632
1633         } else {
1634                 phy_stop(priv->phydev);
1635         }
1636
1637         return 0;
1638 }
1639
1640 static int gfar_resume(struct device *dev)
1641 {
1642         struct gfar_private *priv = dev_get_drvdata(dev);
1643         struct net_device *ndev = priv->ndev;
1644         struct gfar __iomem *regs = priv->gfargrp[0].regs;
1645         u32 tempval;
1646         u16 wol = priv->wol_opts;
1647
1648         if (!netif_running(ndev))
1649                 return 0;
1650
1651         if (wol & GFAR_WOL_MAGIC) {
1652                 /* Disable Magic Packet mode */
1653                 tempval = gfar_read(&regs->maccfg2);
1654                 tempval &= ~MACCFG2_MPEN;
1655                 gfar_write(&regs->maccfg2, tempval);
1656
1657         } else if (wol & GFAR_WOL_FILER_UCAST) {
1658                 /* need to stop rx only, tx is already down */
1659                 gfar_halt(priv);
1660                 gfar_filer_restore_table(priv);
1661
1662         } else {
1663                 phy_start(priv->phydev);
1664         }
1665
1666         gfar_start(priv);
1667
1668         netif_device_attach(ndev);
1669         enable_napi(priv);
1670
1671         return 0;
1672 }
1673
1674 static int gfar_restore(struct device *dev)
1675 {
1676         struct gfar_private *priv = dev_get_drvdata(dev);
1677         struct net_device *ndev = priv->ndev;
1678
1679         if (!netif_running(ndev)) {
1680                 netif_device_attach(ndev);
1681
1682                 return 0;
1683         }
1684
1685         gfar_init_bds(ndev);
1686
1687         gfar_mac_reset(priv);
1688
1689         gfar_init_tx_rx_base(priv);
1690
1691         gfar_start(priv);
1692
1693         priv->oldlink = 0;
1694         priv->oldspeed = 0;
1695         priv->oldduplex = -1;
1696
1697         if (priv->phydev)
1698                 phy_start(priv->phydev);
1699
1700         netif_device_attach(ndev);
1701         enable_napi(priv);
1702
1703         return 0;
1704 }
1705
1706 static struct dev_pm_ops gfar_pm_ops = {
1707         .suspend = gfar_suspend,
1708         .resume = gfar_resume,
1709         .freeze = gfar_suspend,
1710         .thaw = gfar_resume,
1711         .restore = gfar_restore,
1712 };
1713
1714 #define GFAR_PM_OPS (&gfar_pm_ops)
1715
1716 #else
1717
1718 #define GFAR_PM_OPS NULL
1719
1720 #endif
1721
1722 /* Reads the controller's registers to determine what interface
1723  * connects it to the PHY.
1724  */
1725 static phy_interface_t gfar_get_interface(struct net_device *dev)
1726 {
1727         struct gfar_private *priv = netdev_priv(dev);
1728         struct gfar __iomem *regs = priv->gfargrp[0].regs;
1729         u32 ecntrl;
1730
1731         ecntrl = gfar_read(&regs->ecntrl);
1732
1733         if (ecntrl & ECNTRL_SGMII_MODE)
1734                 return PHY_INTERFACE_MODE_SGMII;
1735
1736         if (ecntrl & ECNTRL_TBI_MODE) {
1737                 if (ecntrl & ECNTRL_REDUCED_MODE)
1738                         return PHY_INTERFACE_MODE_RTBI;
1739                 else
1740                         return PHY_INTERFACE_MODE_TBI;
1741         }
1742
1743         if (ecntrl & ECNTRL_REDUCED_MODE) {
1744                 if (ecntrl & ECNTRL_REDUCED_MII_MODE) {
1745                         return PHY_INTERFACE_MODE_RMII;
1746                 }
1747                 else {
1748                         phy_interface_t interface = priv->interface;
1749
1750                         /* This isn't autodetected right now, so it must
1751                          * be set by the device tree or platform code.
1752                          */
1753                         if (interface == PHY_INTERFACE_MODE_RGMII_ID)
1754                                 return PHY_INTERFACE_MODE_RGMII_ID;
1755
1756                         return PHY_INTERFACE_MODE_RGMII;
1757                 }
1758         }
1759
1760         if (priv->device_flags & FSL_GIANFAR_DEV_HAS_GIGABIT)
1761                 return PHY_INTERFACE_MODE_GMII;
1762
1763         return PHY_INTERFACE_MODE_MII;
1764 }
1765
1766
1767 /* Initializes driver's PHY state, and attaches to the PHY.
1768  * Returns 0 on success.
1769  */
1770 static int init_phy(struct net_device *dev)
1771 {
1772         struct gfar_private *priv = netdev_priv(dev);
1773         uint gigabit_support =
1774                 priv->device_flags & FSL_GIANFAR_DEV_HAS_GIGABIT ?
1775                 GFAR_SUPPORTED_GBIT : 0;
1776         phy_interface_t interface;
1777
1778         priv->oldlink = 0;
1779         priv->oldspeed = 0;
1780         priv->oldduplex = -1;
1781
1782         interface = gfar_get_interface(dev);
1783
1784         priv->phydev = of_phy_connect(dev, priv->phy_node, &adjust_link, 0,
1785                                       interface);
1786         if (!priv->phydev) {
1787                 dev_err(&dev->dev, "could not attach to PHY\n");
1788                 return -ENODEV;
1789         }
1790
1791         if (interface == PHY_INTERFACE_MODE_SGMII)
1792                 gfar_configure_serdes(dev);
1793
1794         /* Remove any features not supported by the controller */
1795         priv->phydev->supported &= (GFAR_SUPPORTED | gigabit_support);
1796         priv->phydev->advertising = priv->phydev->supported;
1797
1798         /* Add support for flow control, but don't advertise it by default */
1799         priv->phydev->supported |= (SUPPORTED_Pause | SUPPORTED_Asym_Pause);
1800
1801         return 0;
1802 }
1803
1804 /* Initialize TBI PHY interface for communicating with the
1805  * SERDES lynx PHY on the chip.  We communicate with this PHY
1806  * through the MDIO bus on each controller, treating it as a
1807  * "normal" PHY at the address found in the TBIPA register.  We assume
1808  * that the TBIPA register is valid.  Either the MDIO bus code will set
1809  * it to a value that doesn't conflict with other PHYs on the bus, or the
1810  * value doesn't matter, as there are no other PHYs on the bus.
1811  */
1812 static void gfar_configure_serdes(struct net_device *dev)
1813 {
1814         struct gfar_private *priv = netdev_priv(dev);
1815         struct phy_device *tbiphy;
1816
1817         if (!priv->tbi_node) {
1818                 dev_warn(&dev->dev, "error: SGMII mode requires that the "
1819                                     "device tree specify a tbi-handle\n");
1820                 return;
1821         }
1822
1823         tbiphy = of_phy_find_device(priv->tbi_node);
1824         if (!tbiphy) {
1825                 dev_err(&dev->dev, "error: Could not get TBI device\n");
1826                 return;
1827         }
1828
1829         /* If the link is already up, we must already be ok, and don't need to
1830          * configure and reset the TBI<->SerDes link.  Maybe U-Boot configured
1831          * everything for us?  Resetting it takes the link down and requires
1832          * several seconds for it to come back.
1833          */
1834         if (phy_read(tbiphy, MII_BMSR) & BMSR_LSTATUS) {
1835                 put_device(&tbiphy->dev);
1836                 return;
1837         }
1838
1839         /* Single clk mode, mii mode off(for serdes communication) */
1840         phy_write(tbiphy, MII_TBICON, TBICON_CLK_SELECT);
1841
1842         phy_write(tbiphy, MII_ADVERTISE,
1843                   ADVERTISE_1000XFULL | ADVERTISE_1000XPAUSE |
1844                   ADVERTISE_1000XPSE_ASYM);
1845
1846         phy_write(tbiphy, MII_BMCR,
1847                   BMCR_ANENABLE | BMCR_ANRESTART | BMCR_FULLDPLX |
1848                   BMCR_SPEED1000);
1849
1850         put_device(&tbiphy->dev);
1851 }
1852
1853 static int __gfar_is_rx_idle(struct gfar_private *priv)
1854 {
1855         u32 res;
1856
1857         /* Normaly TSEC should not hang on GRS commands, so we should
1858          * actually wait for IEVENT_GRSC flag.
1859          */
1860         if (!gfar_has_errata(priv, GFAR_ERRATA_A002))
1861                 return 0;
1862
1863         /* Read the eTSEC register at offset 0xD1C. If bits 7-14 are
1864          * the same as bits 23-30, the eTSEC Rx is assumed to be idle
1865          * and the Rx can be safely reset.
1866          */
1867         res = gfar_read((void __iomem *)priv->gfargrp[0].regs + 0xd1c);
1868         res &= 0x7f807f80;
1869         if ((res & 0xffff) == (res >> 16))
1870                 return 1;
1871
1872         return 0;
1873 }
1874
1875 /* Halt the receive and transmit queues */
1876 static void gfar_halt_nodisable(struct gfar_private *priv)
1877 {
1878         struct gfar __iomem *regs = priv->gfargrp[0].regs;
1879         u32 tempval;
1880         unsigned int timeout;
1881         int stopped;
1882
1883         gfar_ints_disable(priv);
1884
1885         if (gfar_is_dma_stopped(priv))
1886                 return;
1887
1888         /* Stop the DMA, and wait for it to stop */
1889         tempval = gfar_read(&regs->dmactrl);
1890         tempval |= (DMACTRL_GRS | DMACTRL_GTS);
1891         gfar_write(&regs->dmactrl, tempval);
1892
1893 retry:
1894         timeout = 1000;
1895         while (!(stopped = gfar_is_dma_stopped(priv)) && timeout) {
1896                 cpu_relax();
1897                 timeout--;
1898         }
1899
1900         if (!timeout)
1901                 stopped = gfar_is_dma_stopped(priv);
1902
1903         if (!stopped && !gfar_is_rx_dma_stopped(priv) &&
1904             !__gfar_is_rx_idle(priv))
1905                 goto retry;
1906 }
1907
1908 /* Halt the receive and transmit queues */
1909 void gfar_halt(struct gfar_private *priv)
1910 {
1911         struct gfar __iomem *regs = priv->gfargrp[0].regs;
1912         u32 tempval;
1913
1914         /* Dissable the Rx/Tx hw queues */
1915         gfar_write(&regs->rqueue, 0);
1916         gfar_write(&regs->tqueue, 0);
1917
1918         mdelay(10);
1919
1920         gfar_halt_nodisable(priv);
1921
1922         /* Disable Rx/Tx DMA */
1923         tempval = gfar_read(&regs->maccfg1);
1924         tempval &= ~(MACCFG1_RX_EN | MACCFG1_TX_EN);
1925         gfar_write(&regs->maccfg1, tempval);
1926 }
1927
1928 void stop_gfar(struct net_device *dev)
1929 {
1930         struct gfar_private *priv = netdev_priv(dev);
1931
1932         netif_tx_stop_all_queues(dev);
1933
1934         smp_mb__before_atomic();
1935         set_bit(GFAR_DOWN, &priv->state);
1936         smp_mb__after_atomic();
1937
1938         disable_napi(priv);
1939
1940         /* disable ints and gracefully shut down Rx/Tx DMA */
1941         gfar_halt(priv);
1942
1943         phy_stop(priv->phydev);
1944
1945         free_skb_resources(priv);
1946 }
1947
1948 static void free_skb_tx_queue(struct gfar_priv_tx_q *tx_queue)
1949 {
1950         struct txbd8 *txbdp;
1951         struct gfar_private *priv = netdev_priv(tx_queue->dev);
1952         int i, j;
1953
1954         txbdp = tx_queue->tx_bd_base;
1955
1956         for (i = 0; i < tx_queue->tx_ring_size; i++) {
1957                 if (!tx_queue->tx_skbuff[i])
1958                         continue;
1959
1960                 dma_unmap_single(priv->dev, be32_to_cpu(txbdp->bufPtr),
1961                                  be16_to_cpu(txbdp->length), DMA_TO_DEVICE);
1962                 txbdp->lstatus = 0;
1963                 for (j = 0; j < skb_shinfo(tx_queue->tx_skbuff[i])->nr_frags;
1964                      j++) {
1965                         txbdp++;
1966                         dma_unmap_page(priv->dev, be32_to_cpu(txbdp->bufPtr),
1967                                        be16_to_cpu(txbdp->length),
1968                                        DMA_TO_DEVICE);
1969                 }
1970                 txbdp++;
1971                 dev_kfree_skb_any(tx_queue->tx_skbuff[i]);
1972                 tx_queue->tx_skbuff[i] = NULL;
1973         }
1974         kfree(tx_queue->tx_skbuff);
1975         tx_queue->tx_skbuff = NULL;
1976 }
1977
1978 static void free_skb_rx_queue(struct gfar_priv_rx_q *rx_queue)
1979 {
1980         int i;
1981
1982         struct rxbd8 *rxbdp = rx_queue->rx_bd_base;
1983
1984         if (rx_queue->skb)
1985                 dev_kfree_skb(rx_queue->skb);
1986
1987         for (i = 0; i < rx_queue->rx_ring_size; i++) {
1988                 struct  gfar_rx_buff *rxb = &rx_queue->rx_buff[i];
1989
1990                 rxbdp->lstatus = 0;
1991                 rxbdp->bufPtr = 0;
1992                 rxbdp++;
1993
1994                 if (!rxb->page)
1995                         continue;
1996
1997                 dma_unmap_single(rx_queue->dev, rxb->dma,
1998                                  PAGE_SIZE, DMA_FROM_DEVICE);
1999                 __free_page(rxb->page);
2000
2001                 rxb->page = NULL;
2002         }
2003
2004         kfree(rx_queue->rx_buff);
2005         rx_queue->rx_buff = NULL;
2006 }
2007
2008 /* If there are any tx skbs or rx skbs still around, free them.
2009  * Then free tx_skbuff and rx_skbuff
2010  */
2011 static void free_skb_resources(struct gfar_private *priv)
2012 {
2013         struct gfar_priv_tx_q *tx_queue = NULL;
2014         struct gfar_priv_rx_q *rx_queue = NULL;
2015         int i;
2016
2017         /* Go through all the buffer descriptors and free their data buffers */
2018         for (i = 0; i < priv->num_tx_queues; i++) {
2019                 struct netdev_queue *txq;
2020
2021                 tx_queue = priv->tx_queue[i];
2022                 txq = netdev_get_tx_queue(tx_queue->dev, tx_queue->qindex);
2023                 if (tx_queue->tx_skbuff)
2024                         free_skb_tx_queue(tx_queue);
2025                 netdev_tx_reset_queue(txq);
2026         }
2027
2028         for (i = 0; i < priv->num_rx_queues; i++) {
2029                 rx_queue = priv->rx_queue[i];
2030                 if (rx_queue->rx_buff)
2031                         free_skb_rx_queue(rx_queue);
2032         }
2033
2034         dma_free_coherent(priv->dev,
2035                           sizeof(struct txbd8) * priv->total_tx_ring_size +
2036                           sizeof(struct rxbd8) * priv->total_rx_ring_size,
2037                           priv->tx_queue[0]->tx_bd_base,
2038                           priv->tx_queue[0]->tx_bd_dma_base);
2039 }
2040
2041 void gfar_start(struct gfar_private *priv)
2042 {
2043         struct gfar __iomem *regs = priv->gfargrp[0].regs;
2044         u32 tempval;
2045         int i = 0;
2046
2047         /* Enable Rx/Tx hw queues */
2048         gfar_write(&regs->rqueue, priv->rqueue);
2049         gfar_write(&regs->tqueue, priv->tqueue);
2050
2051         /* Initialize DMACTRL to have WWR and WOP */
2052         tempval = gfar_read(&regs->dmactrl);
2053         tempval |= DMACTRL_INIT_SETTINGS;
2054         gfar_write(&regs->dmactrl, tempval);
2055
2056         /* Make sure we aren't stopped */
2057         tempval = gfar_read(&regs->dmactrl);
2058         tempval &= ~(DMACTRL_GRS | DMACTRL_GTS);
2059         gfar_write(&regs->dmactrl, tempval);
2060
2061         for (i = 0; i < priv->num_grps; i++) {
2062                 regs = priv->gfargrp[i].regs;
2063                 /* Clear THLT/RHLT, so that the DMA starts polling now */
2064                 gfar_write(&regs->tstat, priv->gfargrp[i].tstat);
2065                 gfar_write(&regs->rstat, priv->gfargrp[i].rstat);
2066         }
2067
2068         /* Enable Rx/Tx DMA */
2069         tempval = gfar_read(&regs->maccfg1);
2070         tempval |= (MACCFG1_RX_EN | MACCFG1_TX_EN);
2071         gfar_write(&regs->maccfg1, tempval);
2072
2073         gfar_ints_enable(priv);
2074
2075         priv->ndev->trans_start = jiffies; /* prevent tx timeout */
2076 }
2077
2078 static void free_grp_irqs(struct gfar_priv_grp *grp)
2079 {
2080         free_irq(gfar_irq(grp, TX)->irq, grp);
2081         free_irq(gfar_irq(grp, RX)->irq, grp);
2082         free_irq(gfar_irq(grp, ER)->irq, grp);
2083 }
2084
2085 static int register_grp_irqs(struct gfar_priv_grp *grp)
2086 {
2087         struct gfar_private *priv = grp->priv;
2088         struct net_device *dev = priv->ndev;
2089         int err;
2090
2091         /* If the device has multiple interrupts, register for
2092          * them.  Otherwise, only register for the one
2093          */
2094         if (priv->device_flags & FSL_GIANFAR_DEV_HAS_MULTI_INTR) {
2095                 /* Install our interrupt handlers for Error,
2096                  * Transmit, and Receive
2097                  */
2098                 err = request_irq(gfar_irq(grp, ER)->irq, gfar_error, 0,
2099                                   gfar_irq(grp, ER)->name, grp);
2100                 if (err < 0) {
2101                         netif_err(priv, intr, dev, "Can't get IRQ %d\n",
2102                                   gfar_irq(grp, ER)->irq);
2103
2104                         goto err_irq_fail;
2105                 }
2106                 enable_irq_wake(gfar_irq(grp, ER)->irq);
2107
2108                 err = request_irq(gfar_irq(grp, TX)->irq, gfar_transmit, 0,
2109                                   gfar_irq(grp, TX)->name, grp);
2110                 if (err < 0) {
2111                         netif_err(priv, intr, dev, "Can't get IRQ %d\n",
2112                                   gfar_irq(grp, TX)->irq);
2113                         goto tx_irq_fail;
2114                 }
2115                 err = request_irq(gfar_irq(grp, RX)->irq, gfar_receive, 0,
2116                                   gfar_irq(grp, RX)->name, grp);
2117                 if (err < 0) {
2118                         netif_err(priv, intr, dev, "Can't get IRQ %d\n",
2119                                   gfar_irq(grp, RX)->irq);
2120                         goto rx_irq_fail;
2121                 }
2122                 enable_irq_wake(gfar_irq(grp, RX)->irq);
2123
2124         } else {
2125                 err = request_irq(gfar_irq(grp, TX)->irq, gfar_interrupt, 0,
2126                                   gfar_irq(grp, TX)->name, grp);
2127                 if (err < 0) {
2128                         netif_err(priv, intr, dev, "Can't get IRQ %d\n",
2129                                   gfar_irq(grp, TX)->irq);
2130                         goto err_irq_fail;
2131                 }
2132                 enable_irq_wake(gfar_irq(grp, TX)->irq);
2133         }
2134
2135         return 0;
2136
2137 rx_irq_fail:
2138         free_irq(gfar_irq(grp, TX)->irq, grp);
2139 tx_irq_fail:
2140         free_irq(gfar_irq(grp, ER)->irq, grp);
2141 err_irq_fail:
2142         return err;
2143
2144 }
2145
2146 static void gfar_free_irq(struct gfar_private *priv)
2147 {
2148         int i;
2149
2150         /* Free the IRQs */
2151         if (priv->device_flags & FSL_GIANFAR_DEV_HAS_MULTI_INTR) {
2152                 for (i = 0; i < priv->num_grps; i++)
2153                         free_grp_irqs(&priv->gfargrp[i]);
2154         } else {
2155                 for (i = 0; i < priv->num_grps; i++)
2156                         free_irq(gfar_irq(&priv->gfargrp[i], TX)->irq,
2157                                  &priv->gfargrp[i]);
2158         }
2159 }
2160
2161 static int gfar_request_irq(struct gfar_private *priv)
2162 {
2163         int err, i, j;
2164
2165         for (i = 0; i < priv->num_grps; i++) {
2166                 err = register_grp_irqs(&priv->gfargrp[i]);
2167                 if (err) {
2168                         for (j = 0; j < i; j++)
2169                                 free_grp_irqs(&priv->gfargrp[j]);
2170                         return err;
2171                 }
2172         }
2173
2174         return 0;
2175 }
2176
2177 /* Bring the controller up and running */
2178 int startup_gfar(struct net_device *ndev)
2179 {
2180         struct gfar_private *priv = netdev_priv(ndev);
2181         int err;
2182
2183         gfar_mac_reset(priv);
2184
2185         err = gfar_alloc_skb_resources(ndev);
2186         if (err)
2187                 return err;
2188
2189         gfar_init_tx_rx_base(priv);
2190
2191         smp_mb__before_atomic();
2192         clear_bit(GFAR_DOWN, &priv->state);
2193         smp_mb__after_atomic();
2194
2195         /* Start Rx/Tx DMA and enable the interrupts */
2196         gfar_start(priv);
2197
2198         /* force link state update after mac reset */
2199         priv->oldlink = 0;
2200         priv->oldspeed = 0;
2201         priv->oldduplex = -1;
2202
2203         phy_start(priv->phydev);
2204
2205         enable_napi(priv);
2206
2207         netif_tx_wake_all_queues(ndev);
2208
2209         return 0;
2210 }
2211
2212 /* Called when something needs to use the ethernet device
2213  * Returns 0 for success.
2214  */
2215 static int gfar_enet_open(struct net_device *dev)
2216 {
2217         struct gfar_private *priv = netdev_priv(dev);
2218         int err;
2219
2220         err = init_phy(dev);
2221         if (err)
2222                 return err;
2223
2224         err = gfar_request_irq(priv);
2225         if (err)
2226                 return err;
2227
2228         err = startup_gfar(dev);
2229         if (err)
2230                 return err;
2231
2232         return err;
2233 }
2234
2235 static inline struct txfcb *gfar_add_fcb(struct sk_buff *skb)
2236 {
2237         struct txfcb *fcb = (struct txfcb *)skb_push(skb, GMAC_FCB_LEN);
2238
2239         memset(fcb, 0, GMAC_FCB_LEN);
2240
2241         return fcb;
2242 }
2243
2244 static inline void gfar_tx_checksum(struct sk_buff *skb, struct txfcb *fcb,
2245                                     int fcb_length)
2246 {
2247         /* If we're here, it's a IP packet with a TCP or UDP
2248          * payload.  We set it to checksum, using a pseudo-header
2249          * we provide
2250          */
2251         u8 flags = TXFCB_DEFAULT;
2252
2253         /* Tell the controller what the protocol is
2254          * And provide the already calculated phcs
2255          */
2256         if (ip_hdr(skb)->protocol == IPPROTO_UDP) {
2257                 flags |= TXFCB_UDP;
2258                 fcb->phcs = (__force __be16)(udp_hdr(skb)->check);
2259         } else
2260                 fcb->phcs = (__force __be16)(tcp_hdr(skb)->check);
2261
2262         /* l3os is the distance between the start of the
2263          * frame (skb->data) and the start of the IP hdr.
2264          * l4os is the distance between the start of the
2265          * l3 hdr and the l4 hdr
2266          */
2267         fcb->l3os = (u8)(skb_network_offset(skb) - fcb_length);
2268         fcb->l4os = skb_network_header_len(skb);
2269
2270         fcb->flags = flags;
2271 }
2272
2273 void inline gfar_tx_vlan(struct sk_buff *skb, struct txfcb *fcb)
2274 {
2275         fcb->flags |= TXFCB_VLN;
2276         fcb->vlctl = cpu_to_be16(skb_vlan_tag_get(skb));
2277 }
2278
2279 static inline struct txbd8 *skip_txbd(struct txbd8 *bdp, int stride,
2280                                       struct txbd8 *base, int ring_size)
2281 {
2282         struct txbd8 *new_bd = bdp + stride;
2283
2284         return (new_bd >= (base + ring_size)) ? (new_bd - ring_size) : new_bd;
2285 }
2286
2287 static inline struct txbd8 *next_txbd(struct txbd8 *bdp, struct txbd8 *base,
2288                                       int ring_size)
2289 {
2290         return skip_txbd(bdp, 1, base, ring_size);
2291 }
2292
2293 /* eTSEC12: csum generation not supported for some fcb offsets */
2294 static inline bool gfar_csum_errata_12(struct gfar_private *priv,
2295                                        unsigned long fcb_addr)
2296 {
2297         return (gfar_has_errata(priv, GFAR_ERRATA_12) &&
2298                (fcb_addr % 0x20) > 0x18);
2299 }
2300
2301 /* eTSEC76: csum generation for frames larger than 2500 may
2302  * cause excess delays before start of transmission
2303  */
2304 static inline bool gfar_csum_errata_76(struct gfar_private *priv,
2305                                        unsigned int len)
2306 {
2307         return (gfar_has_errata(priv, GFAR_ERRATA_76) &&
2308                (len > 2500));
2309 }
2310
2311 /* This is called by the kernel when a frame is ready for transmission.
2312  * It is pointed to by the dev->hard_start_xmit function pointer
2313  */
2314 static int gfar_start_xmit(struct sk_buff *skb, struct net_device *dev)
2315 {
2316         struct gfar_private *priv = netdev_priv(dev);
2317         struct gfar_priv_tx_q *tx_queue = NULL;
2318         struct netdev_queue *txq;
2319         struct gfar __iomem *regs = NULL;
2320         struct txfcb *fcb = NULL;
2321         struct txbd8 *txbdp, *txbdp_start, *base, *txbdp_tstamp = NULL;
2322         u32 lstatus;
2323         int i, rq = 0;
2324         int do_tstamp, do_csum, do_vlan;
2325         u32 bufaddr;
2326         unsigned int nr_frags, nr_txbds, bytes_sent, fcb_len = 0;
2327
2328         rq = skb->queue_mapping;
2329         tx_queue = priv->tx_queue[rq];
2330         txq = netdev_get_tx_queue(dev, rq);
2331         base = tx_queue->tx_bd_base;
2332         regs = tx_queue->grp->regs;
2333
2334         do_csum = (CHECKSUM_PARTIAL == skb->ip_summed);
2335         do_vlan = skb_vlan_tag_present(skb);
2336         do_tstamp = (skb_shinfo(skb)->tx_flags & SKBTX_HW_TSTAMP) &&
2337                     priv->hwts_tx_en;
2338
2339         if (do_csum || do_vlan)
2340                 fcb_len = GMAC_FCB_LEN;
2341
2342         /* check if time stamp should be generated */
2343         if (unlikely(do_tstamp))
2344                 fcb_len = GMAC_FCB_LEN + GMAC_TXPAL_LEN;
2345
2346         /* make space for additional header when fcb is needed */
2347         if (fcb_len && unlikely(skb_headroom(skb) < fcb_len)) {
2348                 struct sk_buff *skb_new;
2349
2350                 skb_new = skb_realloc_headroom(skb, fcb_len);
2351                 if (!skb_new) {
2352                         dev->stats.tx_errors++;
2353                         dev_kfree_skb_any(skb);
2354                         return NETDEV_TX_OK;
2355                 }
2356
2357                 if (skb->sk)
2358                         skb_set_owner_w(skb_new, skb->sk);
2359                 dev_consume_skb_any(skb);
2360                 skb = skb_new;
2361         }
2362
2363         /* total number of fragments in the SKB */
2364         nr_frags = skb_shinfo(skb)->nr_frags;
2365
2366         /* calculate the required number of TxBDs for this skb */
2367         if (unlikely(do_tstamp))
2368                 nr_txbds = nr_frags + 2;
2369         else
2370                 nr_txbds = nr_frags + 1;
2371
2372         /* check if there is space to queue this packet */
2373         if (nr_txbds > tx_queue->num_txbdfree) {
2374                 /* no space, stop the queue */
2375                 netif_tx_stop_queue(txq);
2376                 dev->stats.tx_fifo_errors++;
2377                 return NETDEV_TX_BUSY;
2378         }
2379
2380         /* Update transmit stats */
2381         bytes_sent = skb->len;
2382         tx_queue->stats.tx_bytes += bytes_sent;
2383         /* keep Tx bytes on wire for BQL accounting */
2384         GFAR_CB(skb)->bytes_sent = bytes_sent;
2385         tx_queue->stats.tx_packets++;
2386
2387         txbdp = txbdp_start = tx_queue->cur_tx;
2388         lstatus = be32_to_cpu(txbdp->lstatus);
2389
2390         /* Time stamp insertion requires one additional TxBD */
2391         if (unlikely(do_tstamp))
2392                 txbdp_tstamp = txbdp = next_txbd(txbdp, base,
2393                                                  tx_queue->tx_ring_size);
2394
2395         if (nr_frags == 0) {
2396                 if (unlikely(do_tstamp)) {
2397                         u32 lstatus_ts = be32_to_cpu(txbdp_tstamp->lstatus);
2398
2399                         lstatus_ts |= BD_LFLAG(TXBD_LAST | TXBD_INTERRUPT);
2400                         txbdp_tstamp->lstatus = cpu_to_be32(lstatus_ts);
2401                 } else {
2402                         lstatus |= BD_LFLAG(TXBD_LAST | TXBD_INTERRUPT);
2403                 }
2404         } else {
2405                 /* Place the fragment addresses and lengths into the TxBDs */
2406                 for (i = 0; i < nr_frags; i++) {
2407                         unsigned int frag_len;
2408                         /* Point at the next BD, wrapping as needed */
2409                         txbdp = next_txbd(txbdp, base, tx_queue->tx_ring_size);
2410
2411                         frag_len = skb_shinfo(skb)->frags[i].size;
2412
2413                         lstatus = be32_to_cpu(txbdp->lstatus) | frag_len |
2414                                   BD_LFLAG(TXBD_READY);
2415
2416                         /* Handle the last BD specially */
2417                         if (i == nr_frags - 1)
2418                                 lstatus |= BD_LFLAG(TXBD_LAST | TXBD_INTERRUPT);
2419
2420                         bufaddr = skb_frag_dma_map(priv->dev,
2421                                                    &skb_shinfo(skb)->frags[i],
2422                                                    0,
2423                                                    frag_len,
2424                                                    DMA_TO_DEVICE);
2425                         if (unlikely(dma_mapping_error(priv->dev, bufaddr)))
2426                                 goto dma_map_err;
2427
2428                         /* set the TxBD length and buffer pointer */
2429                         txbdp->bufPtr = cpu_to_be32(bufaddr);
2430                         txbdp->lstatus = cpu_to_be32(lstatus);
2431                 }
2432
2433                 lstatus = be32_to_cpu(txbdp_start->lstatus);
2434         }
2435
2436         /* Add TxPAL between FCB and frame if required */
2437         if (unlikely(do_tstamp)) {
2438                 skb_push(skb, GMAC_TXPAL_LEN);
2439                 memset(skb->data, 0, GMAC_TXPAL_LEN);
2440         }
2441
2442         /* Add TxFCB if required */
2443         if (fcb_len) {
2444                 fcb = gfar_add_fcb(skb);
2445                 lstatus |= BD_LFLAG(TXBD_TOE);
2446         }
2447
2448         /* Set up checksumming */
2449         if (do_csum) {
2450                 gfar_tx_checksum(skb, fcb, fcb_len);
2451
2452                 if (unlikely(gfar_csum_errata_12(priv, (unsigned long)fcb)) ||
2453                     unlikely(gfar_csum_errata_76(priv, skb->len))) {
2454                         __skb_pull(skb, GMAC_FCB_LEN);
2455                         skb_checksum_help(skb);
2456                         if (do_vlan || do_tstamp) {
2457                                 /* put back a new fcb for vlan/tstamp TOE */
2458                                 fcb = gfar_add_fcb(skb);
2459                         } else {
2460                                 /* Tx TOE not used */
2461                                 lstatus &= ~(BD_LFLAG(TXBD_TOE));
2462                                 fcb = NULL;
2463                         }
2464                 }
2465         }
2466
2467         if (do_vlan)
2468                 gfar_tx_vlan(skb, fcb);
2469
2470         /* Setup tx hardware time stamping if requested */
2471         if (unlikely(do_tstamp)) {
2472                 skb_shinfo(skb)->tx_flags |= SKBTX_IN_PROGRESS;
2473                 fcb->ptp = 1;
2474         }
2475
2476         bufaddr = dma_map_single(priv->dev, skb->data, skb_headlen(skb),
2477                                  DMA_TO_DEVICE);
2478         if (unlikely(dma_mapping_error(priv->dev, bufaddr)))
2479                 goto dma_map_err;
2480
2481         txbdp_start->bufPtr = cpu_to_be32(bufaddr);
2482
2483         /* If time stamping is requested one additional TxBD must be set up. The
2484          * first TxBD points to the FCB and must have a data length of
2485          * GMAC_FCB_LEN. The second TxBD points to the actual frame data with
2486          * the full frame length.
2487          */
2488         if (unlikely(do_tstamp)) {
2489                 u32 lstatus_ts = be32_to_cpu(txbdp_tstamp->lstatus);
2490
2491                 bufaddr = be32_to_cpu(txbdp_start->bufPtr);
2492                 bufaddr += fcb_len;
2493                 lstatus_ts |= BD_LFLAG(TXBD_READY) |
2494                               (skb_headlen(skb) - fcb_len);
2495
2496                 txbdp_tstamp->bufPtr = cpu_to_be32(bufaddr);
2497                 txbdp_tstamp->lstatus = cpu_to_be32(lstatus_ts);
2498                 lstatus |= BD_LFLAG(TXBD_CRC | TXBD_READY) | GMAC_FCB_LEN;
2499         } else {
2500                 lstatus |= BD_LFLAG(TXBD_CRC | TXBD_READY) | skb_headlen(skb);
2501         }
2502
2503         netdev_tx_sent_queue(txq, bytes_sent);
2504
2505         gfar_wmb();
2506
2507         txbdp_start->lstatus = cpu_to_be32(lstatus);
2508
2509         gfar_wmb(); /* force lstatus write before tx_skbuff */
2510
2511         tx_queue->tx_skbuff[tx_queue->skb_curtx] = skb;
2512
2513         /* Update the current skb pointer to the next entry we will use
2514          * (wrapping if necessary)
2515          */
2516         tx_queue->skb_curtx = (tx_queue->skb_curtx + 1) &
2517                               TX_RING_MOD_MASK(tx_queue->tx_ring_size);
2518
2519         tx_queue->cur_tx = next_txbd(txbdp, base, tx_queue->tx_ring_size);
2520
2521         /* We can work in parallel with gfar_clean_tx_ring(), except
2522          * when modifying num_txbdfree. Note that we didn't grab the lock
2523          * when we were reading the num_txbdfree and checking for available
2524          * space, that's because outside of this function it can only grow.
2525          */
2526         spin_lock_bh(&tx_queue->txlock);
2527         /* reduce TxBD free count */
2528         tx_queue->num_txbdfree -= (nr_txbds);
2529         spin_unlock_bh(&tx_queue->txlock);
2530
2531         /* If the next BD still needs to be cleaned up, then the bds
2532          * are full.  We need to tell the kernel to stop sending us stuff.
2533          */
2534         if (!tx_queue->num_txbdfree) {
2535                 netif_tx_stop_queue(txq);
2536
2537                 dev->stats.tx_fifo_errors++;
2538         }
2539
2540         /* Tell the DMA to go go go */
2541         gfar_write(&regs->tstat, TSTAT_CLEAR_THALT >> tx_queue->qindex);
2542
2543         return NETDEV_TX_OK;
2544
2545 dma_map_err:
2546         txbdp = next_txbd(txbdp_start, base, tx_queue->tx_ring_size);
2547         if (do_tstamp)
2548                 txbdp = next_txbd(txbdp, base, tx_queue->tx_ring_size);
2549         for (i = 0; i < nr_frags; i++) {
2550                 lstatus = be32_to_cpu(txbdp->lstatus);
2551                 if (!(lstatus & BD_LFLAG(TXBD_READY)))
2552                         break;
2553
2554                 lstatus &= ~BD_LFLAG(TXBD_READY);
2555                 txbdp->lstatus = cpu_to_be32(lstatus);
2556                 bufaddr = be32_to_cpu(txbdp->bufPtr);
2557                 dma_unmap_page(priv->dev, bufaddr, be16_to_cpu(txbdp->length),
2558                                DMA_TO_DEVICE);
2559                 txbdp = next_txbd(txbdp, base, tx_queue->tx_ring_size);
2560         }
2561         gfar_wmb();
2562         dev_kfree_skb_any(skb);
2563         return NETDEV_TX_OK;
2564 }
2565
2566 /* Stops the kernel queue, and halts the controller */
2567 static int gfar_close(struct net_device *dev)
2568 {
2569         struct gfar_private *priv = netdev_priv(dev);
2570
2571         cancel_work_sync(&priv->reset_task);
2572         stop_gfar(dev);
2573
2574         /* Disconnect from the PHY */
2575         phy_disconnect(priv->phydev);
2576         priv->phydev = NULL;
2577
2578         gfar_free_irq(priv);
2579
2580         return 0;
2581 }
2582
2583 /* Changes the mac address if the controller is not running. */
2584 static int gfar_set_mac_address(struct net_device *dev)
2585 {
2586         gfar_set_mac_for_addr(dev, 0, dev->dev_addr);
2587
2588         return 0;
2589 }
2590
2591 static int gfar_change_mtu(struct net_device *dev, int new_mtu)
2592 {
2593         struct gfar_private *priv = netdev_priv(dev);
2594         int frame_size = new_mtu + ETH_HLEN;
2595
2596         if ((frame_size < 64) || (frame_size > GFAR_JUMBO_FRAME_SIZE)) {
2597                 netif_err(priv, drv, dev, "Invalid MTU setting\n");
2598                 return -EINVAL;
2599         }
2600
2601         while (test_and_set_bit_lock(GFAR_RESETTING, &priv->state))
2602                 cpu_relax();
2603
2604         if (dev->flags & IFF_UP)
2605                 stop_gfar(dev);
2606
2607         dev->mtu = new_mtu;
2608
2609         if (dev->flags & IFF_UP)
2610                 startup_gfar(dev);
2611
2612         clear_bit_unlock(GFAR_RESETTING, &priv->state);
2613
2614         return 0;
2615 }
2616
2617 void reset_gfar(struct net_device *ndev)
2618 {
2619         struct gfar_private *priv = netdev_priv(ndev);
2620
2621         while (test_and_set_bit_lock(GFAR_RESETTING, &priv->state))
2622                 cpu_relax();
2623
2624         stop_gfar(ndev);
2625         startup_gfar(ndev);
2626
2627         clear_bit_unlock(GFAR_RESETTING, &priv->state);
2628 }
2629
2630 /* gfar_reset_task gets scheduled when a packet has not been
2631  * transmitted after a set amount of time.
2632  * For now, assume that clearing out all the structures, and
2633  * starting over will fix the problem.
2634  */
2635 static void gfar_reset_task(struct work_struct *work)
2636 {
2637         struct gfar_private *priv = container_of(work, struct gfar_private,
2638                                                  reset_task);
2639         reset_gfar(priv->ndev);
2640 }
2641
2642 static void gfar_timeout(struct net_device *dev)
2643 {
2644         struct gfar_private *priv = netdev_priv(dev);
2645
2646         dev->stats.tx_errors++;
2647         schedule_work(&priv->reset_task);
2648 }
2649
2650 /* Interrupt Handler for Transmit complete */
2651 static void gfar_clean_tx_ring(struct gfar_priv_tx_q *tx_queue)
2652 {
2653         struct net_device *dev = tx_queue->dev;
2654         struct netdev_queue *txq;
2655         struct gfar_private *priv = netdev_priv(dev);
2656         struct txbd8 *bdp, *next = NULL;
2657         struct txbd8 *lbdp = NULL;
2658         struct txbd8 *base = tx_queue->tx_bd_base;
2659         struct sk_buff *skb;
2660         int skb_dirtytx;
2661         int tx_ring_size = tx_queue->tx_ring_size;
2662         int frags = 0, nr_txbds = 0;
2663         int i;
2664         int howmany = 0;
2665         int tqi = tx_queue->qindex;
2666         unsigned int bytes_sent = 0;
2667         u32 lstatus;
2668         size_t buflen;
2669
2670         txq = netdev_get_tx_queue(dev, tqi);
2671         bdp = tx_queue->dirty_tx;
2672         skb_dirtytx = tx_queue->skb_dirtytx;
2673
2674         while ((skb = tx_queue->tx_skbuff[skb_dirtytx])) {
2675
2676                 frags = skb_shinfo(skb)->nr_frags;
2677
2678                 /* When time stamping, one additional TxBD must be freed.
2679                  * Also, we need to dma_unmap_single() the TxPAL.
2680                  */
2681                 if (unlikely(skb_shinfo(skb)->tx_flags & SKBTX_IN_PROGRESS))
2682                         nr_txbds = frags + 2;
2683                 else
2684                         nr_txbds = frags + 1;
2685
2686                 lbdp = skip_txbd(bdp, nr_txbds - 1, base, tx_ring_size);
2687
2688                 lstatus = be32_to_cpu(lbdp->lstatus);
2689
2690                 /* Only clean completed frames */
2691                 if ((lstatus & BD_LFLAG(TXBD_READY)) &&
2692                     (lstatus & BD_LENGTH_MASK))
2693                         break;
2694
2695                 if (unlikely(skb_shinfo(skb)->tx_flags & SKBTX_IN_PROGRESS)) {
2696                         next = next_txbd(bdp, base, tx_ring_size);
2697                         buflen = be16_to_cpu(next->length) +
2698                                  GMAC_FCB_LEN + GMAC_TXPAL_LEN;
2699                 } else
2700                         buflen = be16_to_cpu(bdp->length);
2701
2702                 dma_unmap_single(priv->dev, be32_to_cpu(bdp->bufPtr),
2703                                  buflen, DMA_TO_DEVICE);
2704
2705                 if (unlikely(skb_shinfo(skb)->tx_flags & SKBTX_IN_PROGRESS)) {
2706                         struct skb_shared_hwtstamps shhwtstamps;
2707                         u64 *ns = (u64 *)(((uintptr_t)skb->data + 0x10) &
2708                                           ~0x7UL);
2709
2710                         memset(&shhwtstamps, 0, sizeof(shhwtstamps));
2711                         shhwtstamps.hwtstamp = ns_to_ktime(*ns);
2712                         skb_pull(skb, GMAC_FCB_LEN + GMAC_TXPAL_LEN);
2713                         skb_tstamp_tx(skb, &shhwtstamps);
2714                         gfar_clear_txbd_status(bdp);
2715                         bdp = next;
2716                 }
2717
2718                 gfar_clear_txbd_status(bdp);
2719                 bdp = next_txbd(bdp, base, tx_ring_size);
2720
2721                 for (i = 0; i < frags; i++) {
2722                         dma_unmap_page(priv->dev, be32_to_cpu(bdp->bufPtr),
2723                                        be16_to_cpu(bdp->length),
2724                                        DMA_TO_DEVICE);
2725                         gfar_clear_txbd_status(bdp);
2726                         bdp = next_txbd(bdp, base, tx_ring_size);
2727                 }
2728
2729                 bytes_sent += GFAR_CB(skb)->bytes_sent;
2730
2731                 dev_kfree_skb_any(skb);
2732
2733                 tx_queue->tx_skbuff[skb_dirtytx] = NULL;
2734
2735                 skb_dirtytx = (skb_dirtytx + 1) &
2736                               TX_RING_MOD_MASK(tx_ring_size);
2737
2738                 howmany++;
2739                 spin_lock(&tx_queue->txlock);
2740                 tx_queue->num_txbdfree += nr_txbds;
2741                 spin_unlock(&tx_queue->txlock);
2742         }
2743
2744         /* If we freed a buffer, we can restart transmission, if necessary */
2745         if (tx_queue->num_txbdfree &&
2746             netif_tx_queue_stopped(txq) &&
2747             !(test_bit(GFAR_DOWN, &priv->state)))
2748                 netif_wake_subqueue(priv->ndev, tqi);
2749
2750         /* Update dirty indicators */
2751         tx_queue->skb_dirtytx = skb_dirtytx;
2752         tx_queue->dirty_tx = bdp;
2753
2754         netdev_tx_completed_queue(txq, howmany, bytes_sent);
2755 }
2756
2757 static bool gfar_new_page(struct gfar_priv_rx_q *rxq, struct gfar_rx_buff *rxb)
2758 {
2759         struct page *page;
2760         dma_addr_t addr;
2761
2762         page = dev_alloc_page();
2763         if (unlikely(!page))
2764                 return false;
2765
2766         addr = dma_map_page(rxq->dev, page, 0, PAGE_SIZE, DMA_FROM_DEVICE);
2767         if (unlikely(dma_mapping_error(rxq->dev, addr))) {
2768                 __free_page(page);
2769
2770                 return false;
2771         }
2772
2773         rxb->dma = addr;
2774         rxb->page = page;
2775         rxb->page_offset = 0;
2776
2777         return true;
2778 }
2779
2780 static void gfar_rx_alloc_err(struct gfar_priv_rx_q *rx_queue)
2781 {
2782         struct gfar_private *priv = netdev_priv(rx_queue->ndev);
2783         struct gfar_extra_stats *estats = &priv->extra_stats;
2784
2785         netdev_err(rx_queue->ndev, "Can't alloc RX buffers\n");
2786         atomic64_inc(&estats->rx_alloc_err);
2787 }
2788
2789 static void gfar_alloc_rx_buffs(struct gfar_priv_rx_q *rx_queue,
2790                                 int alloc_cnt)
2791 {
2792         struct rxbd8 *bdp;
2793         struct gfar_rx_buff *rxb;
2794         int i;
2795
2796         i = rx_queue->next_to_use;
2797         bdp = &rx_queue->rx_bd_base[i];
2798         rxb = &rx_queue->rx_buff[i];
2799
2800         while (alloc_cnt--) {
2801                 /* try reuse page */
2802                 if (unlikely(!rxb->page)) {
2803                         if (unlikely(!gfar_new_page(rx_queue, rxb))) {
2804                                 gfar_rx_alloc_err(rx_queue);
2805                                 break;
2806                         }
2807                 }
2808
2809                 /* Setup the new RxBD */
2810                 gfar_init_rxbdp(rx_queue, bdp,
2811                                 rxb->dma + rxb->page_offset + RXBUF_ALIGNMENT);
2812
2813                 /* Update to the next pointer */
2814                 bdp++;
2815                 rxb++;
2816
2817                 if (unlikely(++i == rx_queue->rx_ring_size)) {
2818                         i = 0;
2819                         bdp = rx_queue->rx_bd_base;
2820                         rxb = rx_queue->rx_buff;
2821                 }
2822         }
2823
2824         rx_queue->next_to_use = i;
2825         rx_queue->next_to_alloc = i;
2826 }
2827
2828 static void count_errors(u32 lstatus, struct net_device *ndev)
2829 {
2830         struct gfar_private *priv = netdev_priv(ndev);
2831         struct net_device_stats *stats = &ndev->stats;
2832         struct gfar_extra_stats *estats = &priv->extra_stats;
2833
2834         /* If the packet was truncated, none of the other errors matter */
2835         if (lstatus & BD_LFLAG(RXBD_TRUNCATED)) {
2836                 stats->rx_length_errors++;
2837
2838                 atomic64_inc(&estats->rx_trunc);
2839
2840                 return;
2841         }
2842         /* Count the errors, if there were any */
2843         if (lstatus & BD_LFLAG(RXBD_LARGE | RXBD_SHORT)) {
2844                 stats->rx_length_errors++;
2845
2846                 if (lstatus & BD_LFLAG(RXBD_LARGE))
2847                         atomic64_inc(&estats->rx_large);
2848                 else
2849                         atomic64_inc(&estats->rx_short);
2850         }
2851         if (lstatus & BD_LFLAG(RXBD_NONOCTET)) {
2852                 stats->rx_frame_errors++;
2853                 atomic64_inc(&estats->rx_nonoctet);
2854         }
2855         if (lstatus & BD_LFLAG(RXBD_CRCERR)) {
2856                 atomic64_inc(&estats->rx_crcerr);
2857                 stats->rx_crc_errors++;
2858         }
2859         if (lstatus & BD_LFLAG(RXBD_OVERRUN)) {
2860                 atomic64_inc(&estats->rx_overrun);
2861                 stats->rx_over_errors++;
2862         }
2863 }
2864
2865 irqreturn_t gfar_receive(int irq, void *grp_id)
2866 {
2867         struct gfar_priv_grp *grp = (struct gfar_priv_grp *)grp_id;
2868         unsigned long flags;
2869         u32 imask, ievent;
2870
2871         ievent = gfar_read(&grp->regs->ievent);
2872
2873         if (unlikely(ievent & IEVENT_FGPI)) {
2874                 gfar_write(&grp->regs->ievent, IEVENT_FGPI);
2875                 return IRQ_HANDLED;
2876         }
2877
2878         if (likely(napi_schedule_prep(&grp->napi_rx))) {
2879                 spin_lock_irqsave(&grp->grplock, flags);
2880                 imask = gfar_read(&grp->regs->imask);
2881                 imask &= IMASK_RX_DISABLED;
2882                 gfar_write(&grp->regs->imask, imask);
2883                 spin_unlock_irqrestore(&grp->grplock, flags);
2884                 __napi_schedule(&grp->napi_rx);
2885         } else {
2886                 /* Clear IEVENT, so interrupts aren't called again
2887                  * because of the packets that have already arrived.
2888                  */
2889                 gfar_write(&grp->regs->ievent, IEVENT_RX_MASK);
2890         }
2891
2892         return IRQ_HANDLED;
2893 }
2894
2895 /* Interrupt Handler for Transmit complete */
2896 static irqreturn_t gfar_transmit(int irq, void *grp_id)
2897 {
2898         struct gfar_priv_grp *grp = (struct gfar_priv_grp *)grp_id;
2899         unsigned long flags;
2900         u32 imask;
2901
2902         if (likely(napi_schedule_prep(&grp->napi_tx))) {
2903                 spin_lock_irqsave(&grp->grplock, flags);
2904                 imask = gfar_read(&grp->regs->imask);
2905                 imask &= IMASK_TX_DISABLED;
2906                 gfar_write(&grp->regs->imask, imask);
2907                 spin_unlock_irqrestore(&grp->grplock, flags);
2908                 __napi_schedule(&grp->napi_tx);
2909         } else {
2910                 /* Clear IEVENT, so interrupts aren't called again
2911                  * because of the packets that have already arrived.
2912                  */
2913                 gfar_write(&grp->regs->ievent, IEVENT_TX_MASK);
2914         }
2915
2916         return IRQ_HANDLED;
2917 }
2918
2919 static bool gfar_add_rx_frag(struct gfar_rx_buff *rxb, u32 lstatus,
2920                              struct sk_buff *skb, bool first)
2921 {
2922         unsigned int size = lstatus & BD_LENGTH_MASK;
2923         struct page *page = rxb->page;
2924
2925         /* Remove the FCS from the packet length */
2926         if (likely(lstatus & BD_LFLAG(RXBD_LAST)))
2927                 size -= ETH_FCS_LEN;
2928
2929         if (likely(first))
2930                 skb_put(skb, size);
2931         else
2932                 skb_add_rx_frag(skb, skb_shinfo(skb)->nr_frags, page,
2933                                 rxb->page_offset + RXBUF_ALIGNMENT,
2934                                 size, GFAR_RXB_TRUESIZE);
2935
2936         /* try reuse page */
2937         if (unlikely(page_count(page) != 1))
2938                 return false;
2939
2940         /* change offset to the other half */
2941         rxb->page_offset ^= GFAR_RXB_TRUESIZE;
2942
2943         atomic_inc(&page->_count);
2944
2945         return true;
2946 }
2947
2948 static void gfar_reuse_rx_page(struct gfar_priv_rx_q *rxq,
2949                                struct gfar_rx_buff *old_rxb)
2950 {
2951         struct gfar_rx_buff *new_rxb;
2952         u16 nta = rxq->next_to_alloc;
2953
2954         new_rxb = &rxq->rx_buff[nta];
2955
2956         /* find next buf that can reuse a page */
2957         nta++;
2958         rxq->next_to_alloc = (nta < rxq->rx_ring_size) ? nta : 0;
2959
2960         /* copy page reference */
2961         *new_rxb = *old_rxb;
2962
2963         /* sync for use by the device */
2964         dma_sync_single_range_for_device(rxq->dev, old_rxb->dma,
2965                                          old_rxb->page_offset,
2966                                          GFAR_RXB_TRUESIZE, DMA_FROM_DEVICE);
2967 }
2968
2969 static struct sk_buff *gfar_get_next_rxbuff(struct gfar_priv_rx_q *rx_queue,
2970                                             u32 lstatus, struct sk_buff *skb)
2971 {
2972         struct gfar_rx_buff *rxb = &rx_queue->rx_buff[rx_queue->next_to_clean];
2973         struct page *page = rxb->page;
2974         bool first = false;
2975
2976         if (likely(!skb)) {
2977                 void *buff_addr = page_address(page) + rxb->page_offset;
2978
2979                 skb = build_skb(buff_addr, GFAR_SKBFRAG_SIZE);
2980                 if (unlikely(!skb)) {
2981                         gfar_rx_alloc_err(rx_queue);
2982                         return NULL;
2983                 }
2984                 skb_reserve(skb, RXBUF_ALIGNMENT);
2985                 first = true;
2986         }
2987
2988         dma_sync_single_range_for_cpu(rx_queue->dev, rxb->dma, rxb->page_offset,
2989                                       GFAR_RXB_TRUESIZE, DMA_FROM_DEVICE);
2990
2991         if (gfar_add_rx_frag(rxb, lstatus, skb, first)) {
2992                 /* reuse the free half of the page */
2993                 gfar_reuse_rx_page(rx_queue, rxb);
2994         } else {
2995                 /* page cannot be reused, unmap it */
2996                 dma_unmap_page(rx_queue->dev, rxb->dma,
2997                                PAGE_SIZE, DMA_FROM_DEVICE);
2998         }
2999
3000         /* clear rxb content */
3001         rxb->page = NULL;
3002
3003         return skb;
3004 }
3005
3006 static inline void gfar_rx_checksum(struct sk_buff *skb, struct rxfcb *fcb)
3007 {
3008         /* If valid headers were found, and valid sums
3009          * were verified, then we tell the kernel that no
3010          * checksumming is necessary.  Otherwise, it is [FIXME]
3011          */
3012         if ((be16_to_cpu(fcb->flags) & RXFCB_CSUM_MASK) ==
3013             (RXFCB_CIP | RXFCB_CTU))
3014                 skb->ip_summed = CHECKSUM_UNNECESSARY;
3015         else
3016                 skb_checksum_none_assert(skb);
3017 }
3018
3019 /* gfar_process_frame() -- handle one incoming packet if skb isn't NULL. */
3020 static void gfar_process_frame(struct net_device *ndev, struct sk_buff *skb)
3021 {
3022         struct gfar_private *priv = netdev_priv(ndev);
3023         struct rxfcb *fcb = NULL;
3024
3025         /* fcb is at the beginning if exists */
3026         fcb = (struct rxfcb *)skb->data;
3027
3028         /* Remove the FCB from the skb
3029          * Remove the padded bytes, if there are any
3030          */
3031         if (priv->uses_rxfcb)
3032                 skb_pull(skb, GMAC_FCB_LEN);
3033
3034         /* Get receive timestamp from the skb */
3035         if (priv->hwts_rx_en) {
3036                 struct skb_shared_hwtstamps *shhwtstamps = skb_hwtstamps(skb);
3037                 u64 *ns = (u64 *) skb->data;
3038
3039                 memset(shhwtstamps, 0, sizeof(*shhwtstamps));
3040                 shhwtstamps->hwtstamp = ns_to_ktime(*ns);
3041         }
3042
3043         if (priv->padding)
3044                 skb_pull(skb, priv->padding);
3045
3046         if (ndev->features & NETIF_F_RXCSUM)
3047                 gfar_rx_checksum(skb, fcb);
3048
3049         /* Tell the skb what kind of packet this is */
3050         skb->protocol = eth_type_trans(skb, ndev);
3051
3052         /* There's need to check for NETIF_F_HW_VLAN_CTAG_RX here.
3053          * Even if vlan rx accel is disabled, on some chips
3054          * RXFCB_VLN is pseudo randomly set.
3055          */
3056         if (ndev->features & NETIF_F_HW_VLAN_CTAG_RX &&
3057             be16_to_cpu(fcb->flags) & RXFCB_VLN)
3058                 __vlan_hwaccel_put_tag(skb, htons(ETH_P_8021Q),
3059                                        be16_to_cpu(fcb->vlctl));
3060 }
3061
3062 /* gfar_clean_rx_ring() -- Processes each frame in the rx ring
3063  * until the budget/quota has been reached. Returns the number
3064  * of frames handled
3065  */
3066 int gfar_clean_rx_ring(struct gfar_priv_rx_q *rx_queue, int rx_work_limit)
3067 {
3068         struct net_device *ndev = rx_queue->ndev;
3069         struct gfar_private *priv = netdev_priv(ndev);
3070         struct rxbd8 *bdp;
3071         int i, howmany = 0;
3072         struct sk_buff *skb = rx_queue->skb;
3073         int cleaned_cnt = gfar_rxbd_unused(rx_queue);
3074         unsigned int total_bytes = 0, total_pkts = 0;
3075
3076         /* Get the first full descriptor */
3077         i = rx_queue->next_to_clean;
3078
3079         while (rx_work_limit--) {
3080                 u32 lstatus;
3081
3082                 if (cleaned_cnt >= GFAR_RX_BUFF_ALLOC) {
3083                         gfar_alloc_rx_buffs(rx_queue, cleaned_cnt);
3084                         cleaned_cnt = 0;
3085                 }
3086
3087                 bdp = &rx_queue->rx_bd_base[i];
3088                 lstatus = be32_to_cpu(bdp->lstatus);
3089                 if (lstatus & BD_LFLAG(RXBD_EMPTY))
3090                         break;
3091
3092                 /* order rx buffer descriptor reads */
3093                 rmb();
3094
3095                 /* fetch next to clean buffer from the ring */
3096                 skb = gfar_get_next_rxbuff(rx_queue, lstatus, skb);
3097                 if (unlikely(!skb))
3098                         break;
3099
3100                 cleaned_cnt++;
3101                 howmany++;
3102
3103                 if (unlikely(++i == rx_queue->rx_ring_size))
3104                         i = 0;
3105
3106                 rx_queue->next_to_clean = i;
3107
3108                 /* fetch next buffer if not the last in frame */
3109                 if (!(lstatus & BD_LFLAG(RXBD_LAST)))
3110                         continue;
3111
3112                 if (unlikely(lstatus & BD_LFLAG(RXBD_ERR))) {
3113                         count_errors(lstatus, ndev);
3114
3115                         /* discard faulty buffer */
3116                         dev_kfree_skb(skb);
3117                         skb = NULL;
3118                         rx_queue->stats.rx_dropped++;
3119                         continue;
3120                 }
3121
3122                 /* Increment the number of packets */
3123                 total_pkts++;
3124                 total_bytes += skb->len;
3125
3126                 skb_record_rx_queue(skb, rx_queue->qindex);
3127
3128                 gfar_process_frame(ndev, skb);
3129
3130                 /* Send the packet up the stack */
3131                 napi_gro_receive(&rx_queue->grp->napi_rx, skb);
3132
3133                 skb = NULL;
3134         }
3135
3136         /* Store incomplete frames for completion */
3137         rx_queue->skb = skb;
3138
3139         rx_queue->stats.rx_packets += total_pkts;
3140         rx_queue->stats.rx_bytes += total_bytes;
3141
3142         if (cleaned_cnt)
3143                 gfar_alloc_rx_buffs(rx_queue, cleaned_cnt);
3144
3145         /* Update Last Free RxBD pointer for LFC */
3146         if (unlikely(priv->tx_actual_en)) {
3147                 u32 bdp_dma = gfar_rxbd_dma_lastfree(rx_queue);
3148
3149                 gfar_write(rx_queue->rfbptr, bdp_dma);
3150         }
3151
3152         return howmany;
3153 }
3154
3155 static int gfar_poll_rx_sq(struct napi_struct *napi, int budget)
3156 {
3157         struct gfar_priv_grp *gfargrp =
3158                 container_of(napi, struct gfar_priv_grp, napi_rx);
3159         struct gfar __iomem *regs = gfargrp->regs;
3160         struct gfar_priv_rx_q *rx_queue = gfargrp->rx_queue;
3161         int work_done = 0;
3162
3163         /* Clear IEVENT, so interrupts aren't called again
3164          * because of the packets that have already arrived
3165          */
3166         gfar_write(&regs->ievent, IEVENT_RX_MASK);
3167
3168         work_done = gfar_clean_rx_ring(rx_queue, budget);
3169
3170         if (work_done < budget) {
3171                 u32 imask;
3172                 napi_complete(napi);
3173                 /* Clear the halt bit in RSTAT */
3174                 gfar_write(&regs->rstat, gfargrp->rstat);
3175
3176                 spin_lock_irq(&gfargrp->grplock);
3177                 imask = gfar_read(&regs->imask);
3178                 imask |= IMASK_RX_DEFAULT;
3179                 gfar_write(&regs->imask, imask);
3180                 spin_unlock_irq(&gfargrp->grplock);
3181         }
3182
3183         return work_done;
3184 }
3185
3186 static int gfar_poll_tx_sq(struct napi_struct *napi, int budget)
3187 {
3188         struct gfar_priv_grp *gfargrp =
3189                 container_of(napi, struct gfar_priv_grp, napi_tx);
3190         struct gfar __iomem *regs = gfargrp->regs;
3191         struct gfar_priv_tx_q *tx_queue = gfargrp->tx_queue;
3192         u32 imask;
3193
3194         /* Clear IEVENT, so interrupts aren't called again
3195          * because of the packets that have already arrived
3196          */
3197         gfar_write(&regs->ievent, IEVENT_TX_MASK);
3198
3199         /* run Tx cleanup to completion */
3200         if (tx_queue->tx_skbuff[tx_queue->skb_dirtytx])
3201                 gfar_clean_tx_ring(tx_queue);
3202
3203         napi_complete(napi);
3204
3205         spin_lock_irq(&gfargrp->grplock);
3206         imask = gfar_read(&regs->imask);
3207         imask |= IMASK_TX_DEFAULT;
3208         gfar_write(&regs->imask, imask);
3209         spin_unlock_irq(&gfargrp->grplock);
3210
3211         return 0;
3212 }
3213
3214 static int gfar_poll_rx(struct napi_struct *napi, int budget)
3215 {
3216         struct gfar_priv_grp *gfargrp =
3217                 container_of(napi, struct gfar_priv_grp, napi_rx);
3218         struct gfar_private *priv = gfargrp->priv;
3219         struct gfar __iomem *regs = gfargrp->regs;
3220         struct gfar_priv_rx_q *rx_queue = NULL;
3221         int work_done = 0, work_done_per_q = 0;
3222         int i, budget_per_q = 0;
3223         unsigned long rstat_rxf;
3224         int num_act_queues;
3225
3226         /* Clear IEVENT, so interrupts aren't called again
3227          * because of the packets that have already arrived
3228          */
3229         gfar_write(&regs->ievent, IEVENT_RX_MASK);
3230
3231         rstat_rxf = gfar_read(&regs->rstat) & RSTAT_RXF_MASK;
3232
3233         num_act_queues = bitmap_weight(&rstat_rxf, MAX_RX_QS);
3234         if (num_act_queues)
3235                 budget_per_q = budget/num_act_queues;
3236
3237         for_each_set_bit(i, &gfargrp->rx_bit_map, priv->num_rx_queues) {
3238                 /* skip queue if not active */
3239                 if (!(rstat_rxf & (RSTAT_CLEAR_RXF0 >> i)))
3240                         continue;
3241
3242                 rx_queue = priv->rx_queue[i];
3243                 work_done_per_q =
3244                         gfar_clean_rx_ring(rx_queue, budget_per_q);
3245                 work_done += work_done_per_q;
3246
3247                 /* finished processing this queue */
3248                 if (work_done_per_q < budget_per_q) {
3249                         /* clear active queue hw indication */
3250                         gfar_write(&regs->rstat,
3251                                    RSTAT_CLEAR_RXF0 >> i);
3252                         num_act_queues--;
3253
3254                         if (!num_act_queues)
3255                                 break;
3256                 }
3257         }
3258
3259         if (!num_act_queues) {
3260                 u32 imask;
3261                 napi_complete(napi);
3262
3263                 /* Clear the halt bit in RSTAT */
3264                 gfar_write(&regs->rstat, gfargrp->rstat);
3265
3266                 spin_lock_irq(&gfargrp->grplock);
3267                 imask = gfar_read(&regs->imask);
3268                 imask |= IMASK_RX_DEFAULT;
3269                 gfar_write(&regs->imask, imask);
3270                 spin_unlock_irq(&gfargrp->grplock);
3271         }
3272
3273         return work_done;
3274 }
3275
3276 static int gfar_poll_tx(struct napi_struct *napi, int budget)
3277 {
3278         struct gfar_priv_grp *gfargrp =
3279                 container_of(napi, struct gfar_priv_grp, napi_tx);
3280         struct gfar_private *priv = gfargrp->priv;
3281         struct gfar __iomem *regs = gfargrp->regs;
3282         struct gfar_priv_tx_q *tx_queue = NULL;
3283         int has_tx_work = 0;
3284         int i;
3285
3286         /* Clear IEVENT, so interrupts aren't called again
3287          * because of the packets that have already arrived
3288          */
3289         gfar_write(&regs->ievent, IEVENT_TX_MASK);
3290
3291         for_each_set_bit(i, &gfargrp->tx_bit_map, priv->num_tx_queues) {
3292                 tx_queue = priv->tx_queue[i];
3293                 /* run Tx cleanup to completion */
3294                 if (tx_queue->tx_skbuff[tx_queue->skb_dirtytx]) {
3295                         gfar_clean_tx_ring(tx_queue);
3296                         has_tx_work = 1;
3297                 }
3298         }
3299
3300         if (!has_tx_work) {
3301                 u32 imask;
3302                 napi_complete(napi);
3303
3304                 spin_lock_irq(&gfargrp->grplock);
3305                 imask = gfar_read(&regs->imask);
3306                 imask |= IMASK_TX_DEFAULT;
3307                 gfar_write(&regs->imask, imask);
3308                 spin_unlock_irq(&gfargrp->grplock);
3309         }
3310
3311         return 0;
3312 }
3313
3314
3315 #ifdef CONFIG_NET_POLL_CONTROLLER
3316 /* Polling 'interrupt' - used by things like netconsole to send skbs
3317  * without having to re-enable interrupts. It's not called while
3318  * the interrupt routine is executing.
3319  */
3320 static void gfar_netpoll(struct net_device *dev)
3321 {
3322         struct gfar_private *priv = netdev_priv(dev);
3323         int i;
3324
3325         /* If the device has multiple interrupts, run tx/rx */
3326         if (priv->device_flags & FSL_GIANFAR_DEV_HAS_MULTI_INTR) {
3327                 for (i = 0; i < priv->num_grps; i++) {
3328                         struct gfar_priv_grp *grp = &priv->gfargrp[i];
3329
3330                         disable_irq(gfar_irq(grp, TX)->irq);
3331                         disable_irq(gfar_irq(grp, RX)->irq);
3332                         disable_irq(gfar_irq(grp, ER)->irq);
3333                         gfar_interrupt(gfar_irq(grp, TX)->irq, grp);
3334                         enable_irq(gfar_irq(grp, ER)->irq);
3335                         enable_irq(gfar_irq(grp, RX)->irq);
3336                         enable_irq(gfar_irq(grp, TX)->irq);
3337                 }
3338         } else {
3339                 for (i = 0; i < priv->num_grps; i++) {
3340                         struct gfar_priv_grp *grp = &priv->gfargrp[i];
3341
3342                         disable_irq(gfar_irq(grp, TX)->irq);
3343                         gfar_interrupt(gfar_irq(grp, TX)->irq, grp);
3344                         enable_irq(gfar_irq(grp, TX)->irq);
3345                 }
3346         }
3347 }
3348 #endif
3349
3350 /* The interrupt handler for devices with one interrupt */
3351 static irqreturn_t gfar_interrupt(int irq, void *grp_id)
3352 {
3353         struct gfar_priv_grp *gfargrp = grp_id;
3354
3355         /* Save ievent for future reference */
3356         u32 events = gfar_read(&gfargrp->regs->ievent);
3357
3358         /* Check for reception */
3359         if (events & IEVENT_RX_MASK)
3360                 gfar_receive(irq, grp_id);
3361
3362         /* Check for transmit completion */
3363         if (events & IEVENT_TX_MASK)
3364                 gfar_transmit(irq, grp_id);
3365
3366         /* Check for errors */
3367         if (events & IEVENT_ERR_MASK)
3368                 gfar_error(irq, grp_id);
3369
3370         return IRQ_HANDLED;
3371 }
3372
3373 /* Called every time the controller might need to be made
3374  * aware of new link state.  The PHY code conveys this
3375  * information through variables in the phydev structure, and this
3376  * function converts those variables into the appropriate
3377  * register values, and can bring down the device if needed.
3378  */
3379 static void adjust_link(struct net_device *dev)
3380 {
3381         struct gfar_private *priv = netdev_priv(dev);
3382         struct phy_device *phydev = priv->phydev;
3383
3384         if (unlikely(phydev->link != priv->oldlink ||
3385                      (phydev->link && (phydev->duplex != priv->oldduplex ||
3386                                        phydev->speed != priv->oldspeed))))
3387                 gfar_update_link_state(priv);
3388 }
3389
3390 /* Update the hash table based on the current list of multicast
3391  * addresses we subscribe to.  Also, change the promiscuity of
3392  * the device based on the flags (this function is called
3393  * whenever dev->flags is changed
3394  */
3395 static void gfar_set_multi(struct net_device *dev)
3396 {
3397         struct netdev_hw_addr *ha;
3398         struct gfar_private *priv = netdev_priv(dev);
3399         struct gfar __iomem *regs = priv->gfargrp[0].regs;
3400         u32 tempval;
3401
3402         if (dev->flags & IFF_PROMISC) {
3403                 /* Set RCTRL to PROM */
3404                 tempval = gfar_read(&regs->rctrl);
3405                 tempval |= RCTRL_PROM;
3406                 gfar_write(&regs->rctrl, tempval);
3407         } else {
3408                 /* Set RCTRL to not PROM */
3409                 tempval = gfar_read(&regs->rctrl);
3410                 tempval &= ~(RCTRL_PROM);
3411                 gfar_write(&regs->rctrl, tempval);
3412         }
3413
3414         if (dev->flags & IFF_ALLMULTI) {
3415                 /* Set the hash to rx all multicast frames */
3416                 gfar_write(&regs->igaddr0, 0xffffffff);
3417                 gfar_write(&regs->igaddr1, 0xffffffff);
3418                 gfar_write(&regs->igaddr2, 0xffffffff);
3419                 gfar_write(&regs->igaddr3, 0xffffffff);
3420                 gfar_write(&regs->igaddr4, 0xffffffff);
3421                 gfar_write(&regs->igaddr5, 0xffffffff);
3422                 gfar_write(&regs->igaddr6, 0xffffffff);
3423                 gfar_write(&regs->igaddr7, 0xffffffff);
3424                 gfar_write(&regs->gaddr0, 0xffffffff);
3425                 gfar_write(&regs->gaddr1, 0xffffffff);
3426                 gfar_write(&regs->gaddr2, 0xffffffff);
3427                 gfar_write(&regs->gaddr3, 0xffffffff);
3428                 gfar_write(&regs->gaddr4, 0xffffffff);
3429                 gfar_write(&regs->gaddr5, 0xffffffff);
3430                 gfar_write(&regs->gaddr6, 0xffffffff);
3431                 gfar_write(&regs->gaddr7, 0xffffffff);
3432         } else {
3433                 int em_num;
3434                 int idx;
3435
3436                 /* zero out the hash */
3437                 gfar_write(&regs->igaddr0, 0x0);
3438                 gfar_write(&regs->igaddr1, 0x0);
3439                 gfar_write(&regs->igaddr2, 0x0);
3440                 gfar_write(&regs->igaddr3, 0x0);
3441                 gfar_write(&regs->igaddr4, 0x0);
3442                 gfar_write(&regs->igaddr5, 0x0);
3443                 gfar_write(&regs->igaddr6, 0x0);
3444                 gfar_write(&regs->igaddr7, 0x0);
3445                 gfar_write(&regs->gaddr0, 0x0);
3446                 gfar_write(&regs->gaddr1, 0x0);
3447                 gfar_write(&regs->gaddr2, 0x0);
3448                 gfar_write(&regs->gaddr3, 0x0);
3449                 gfar_write(&regs->gaddr4, 0x0);
3450                 gfar_write(&regs->gaddr5, 0x0);
3451                 gfar_write(&regs->gaddr6, 0x0);
3452                 gfar_write(&regs->gaddr7, 0x0);
3453
3454                 /* If we have extended hash tables, we need to
3455                  * clear the exact match registers to prepare for
3456                  * setting them
3457                  */
3458                 if (priv->extended_hash) {
3459                         em_num = GFAR_EM_NUM + 1;
3460                         gfar_clear_exact_match(dev);
3461                         idx = 1;
3462                 } else {
3463                         idx = 0;
3464                         em_num = 0;
3465                 }
3466
3467                 if (netdev_mc_empty(dev))
3468                         return;
3469
3470                 /* Parse the list, and set the appropriate bits */
3471                 netdev_for_each_mc_addr(ha, dev) {
3472                         if (idx < em_num) {
3473                                 gfar_set_mac_for_addr(dev, idx, ha->addr);
3474                                 idx++;
3475                         } else
3476                                 gfar_set_hash_for_addr(dev, ha->addr);
3477                 }
3478         }
3479 }
3480
3481
3482 /* Clears each of the exact match registers to zero, so they
3483  * don't interfere with normal reception
3484  */
3485 static void gfar_clear_exact_match(struct net_device *dev)
3486 {
3487         int idx;
3488         static const u8 zero_arr[ETH_ALEN] = {0, 0, 0, 0, 0, 0};
3489
3490         for (idx = 1; idx < GFAR_EM_NUM + 1; idx++)
3491                 gfar_set_mac_for_addr(dev, idx, zero_arr);
3492 }
3493
3494 /* Set the appropriate hash bit for the given addr */
3495 /* The algorithm works like so:
3496  * 1) Take the Destination Address (ie the multicast address), and
3497  * do a CRC on it (little endian), and reverse the bits of the
3498  * result.
3499  * 2) Use the 8 most significant bits as a hash into a 256-entry
3500  * table.  The table is controlled through 8 32-bit registers:
3501  * gaddr0-7.  gaddr0's MSB is entry 0, and gaddr7's LSB is
3502  * gaddr7.  This means that the 3 most significant bits in the
3503  * hash index which gaddr register to use, and the 5 other bits
3504  * indicate which bit (assuming an IBM numbering scheme, which
3505  * for PowerPC (tm) is usually the case) in the register holds
3506  * the entry.
3507  */
3508 static void gfar_set_hash_for_addr(struct net_device *dev, u8 *addr)
3509 {
3510         u32 tempval;
3511         struct gfar_private *priv = netdev_priv(dev);
3512         u32 result = ether_crc(ETH_ALEN, addr);
3513         int width = priv->hash_width;
3514         u8 whichbit = (result >> (32 - width)) & 0x1f;
3515         u8 whichreg = result >> (32 - width + 5);
3516         u32 value = (1 << (31-whichbit));
3517
3518         tempval = gfar_read(priv->hash_regs[whichreg]);
3519         tempval |= value;
3520         gfar_write(priv->hash_regs[whichreg], tempval);
3521 }
3522
3523
3524 /* There are multiple MAC Address register pairs on some controllers
3525  * This function sets the numth pair to a given address
3526  */
3527 static void gfar_set_mac_for_addr(struct net_device *dev, int num,
3528                                   const u8 *addr)
3529 {
3530         struct gfar_private *priv = netdev_priv(dev);
3531         struct gfar __iomem *regs = priv->gfargrp[0].regs;
3532         u32 tempval;
3533         u32 __iomem *macptr = &regs->macstnaddr1;
3534
3535         macptr += num*2;
3536
3537         /* For a station address of 0x12345678ABCD in transmission
3538          * order (BE), MACnADDR1 is set to 0xCDAB7856 and
3539          * MACnADDR2 is set to 0x34120000.
3540          */
3541         tempval = (addr[5] << 24) | (addr[4] << 16) |
3542                   (addr[3] << 8)  |  addr[2];
3543
3544         gfar_write(macptr, tempval);
3545
3546         tempval = (addr[1] << 24) | (addr[0] << 16);
3547
3548         gfar_write(macptr+1, tempval);
3549 }
3550
3551 /* GFAR error interrupt handler */
3552 static irqreturn_t gfar_error(int irq, void *grp_id)
3553 {
3554         struct gfar_priv_grp *gfargrp = grp_id;
3555         struct gfar __iomem *regs = gfargrp->regs;
3556         struct gfar_private *priv= gfargrp->priv;
3557         struct net_device *dev = priv->ndev;
3558
3559         /* Save ievent for future reference */
3560         u32 events = gfar_read(&regs->ievent);
3561
3562         /* Clear IEVENT */
3563         gfar_write(&regs->ievent, events & IEVENT_ERR_MASK);
3564
3565         /* Magic Packet is not an error. */
3566         if ((priv->device_flags & FSL_GIANFAR_DEV_HAS_MAGIC_PACKET) &&
3567             (events & IEVENT_MAG))
3568                 events &= ~IEVENT_MAG;
3569
3570         /* Hmm... */
3571         if (netif_msg_rx_err(priv) || netif_msg_tx_err(priv))
3572                 netdev_dbg(dev,
3573                            "error interrupt (ievent=0x%08x imask=0x%08x)\n",
3574                            events, gfar_read(&regs->imask));
3575
3576         /* Update the error counters */
3577         if (events & IEVENT_TXE) {
3578                 dev->stats.tx_errors++;
3579
3580                 if (events & IEVENT_LC)
3581                         dev->stats.tx_window_errors++;
3582                 if (events & IEVENT_CRL)
3583                         dev->stats.tx_aborted_errors++;
3584                 if (events & IEVENT_XFUN) {
3585                         netif_dbg(priv, tx_err, dev,
3586                                   "TX FIFO underrun, packet dropped\n");
3587                         dev->stats.tx_dropped++;
3588                         atomic64_inc(&priv->extra_stats.tx_underrun);
3589
3590                         schedule_work(&priv->reset_task);
3591                 }
3592                 netif_dbg(priv, tx_err, dev, "Transmit Error\n");
3593         }
3594         if (events & IEVENT_BSY) {
3595                 dev->stats.rx_over_errors++;
3596                 atomic64_inc(&priv->extra_stats.rx_bsy);
3597
3598                 netif_dbg(priv, rx_err, dev, "busy error (rstat: %x)\n",
3599                           gfar_read(&regs->rstat));
3600         }
3601         if (events & IEVENT_BABR) {
3602                 dev->stats.rx_errors++;
3603                 atomic64_inc(&priv->extra_stats.rx_babr);
3604
3605                 netif_dbg(priv, rx_err, dev, "babbling RX error\n");
3606         }
3607         if (events & IEVENT_EBERR) {
3608                 atomic64_inc(&priv->extra_stats.eberr);
3609                 netif_dbg(priv, rx_err, dev, "bus error\n");
3610         }
3611         if (events & IEVENT_RXC)
3612                 netif_dbg(priv, rx_status, dev, "control frame\n");
3613
3614         if (events & IEVENT_BABT) {
3615                 atomic64_inc(&priv->extra_stats.tx_babt);
3616                 netif_dbg(priv, tx_err, dev, "babbling TX error\n");
3617         }
3618         return IRQ_HANDLED;
3619 }
3620
3621 static u32 gfar_get_flowctrl_cfg(struct gfar_private *priv)
3622 {
3623         struct phy_device *phydev = priv->phydev;
3624         u32 val = 0;
3625
3626         if (!phydev->duplex)
3627                 return val;
3628
3629         if (!priv->pause_aneg_en) {
3630                 if (priv->tx_pause_en)
3631                         val |= MACCFG1_TX_FLOW;
3632                 if (priv->rx_pause_en)
3633                         val |= MACCFG1_RX_FLOW;
3634         } else {
3635                 u16 lcl_adv, rmt_adv;
3636                 u8 flowctrl;
3637                 /* get link partner capabilities */
3638                 rmt_adv = 0;
3639                 if (phydev->pause)
3640                         rmt_adv = LPA_PAUSE_CAP;
3641                 if (phydev->asym_pause)
3642                         rmt_adv |= LPA_PAUSE_ASYM;
3643
3644                 lcl_adv = 0;
3645                 if (phydev->advertising & ADVERTISED_Pause)
3646                         lcl_adv |= ADVERTISE_PAUSE_CAP;
3647                 if (phydev->advertising & ADVERTISED_Asym_Pause)
3648                         lcl_adv |= ADVERTISE_PAUSE_ASYM;
3649
3650                 flowctrl = mii_resolve_flowctrl_fdx(lcl_adv, rmt_adv);
3651                 if (flowctrl & FLOW_CTRL_TX)
3652                         val |= MACCFG1_TX_FLOW;
3653                 if (flowctrl & FLOW_CTRL_RX)
3654                         val |= MACCFG1_RX_FLOW;
3655         }
3656
3657         return val;
3658 }
3659
3660 static noinline void gfar_update_link_state(struct gfar_private *priv)
3661 {
3662         struct gfar __iomem *regs = priv->gfargrp[0].regs;
3663         struct phy_device *phydev = priv->phydev;
3664         struct gfar_priv_rx_q *rx_queue = NULL;
3665         int i;
3666
3667         if (unlikely(test_bit(GFAR_RESETTING, &priv->state)))
3668                 return;
3669
3670         if (phydev->link) {
3671                 u32 tempval1 = gfar_read(&regs->maccfg1);
3672                 u32 tempval = gfar_read(&regs->maccfg2);
3673                 u32 ecntrl = gfar_read(&regs->ecntrl);
3674                 u32 tx_flow_oldval = (tempval & MACCFG1_TX_FLOW);
3675
3676                 if (phydev->duplex != priv->oldduplex) {
3677                         if (!(phydev->duplex))
3678                                 tempval &= ~(MACCFG2_FULL_DUPLEX);
3679                         else
3680                                 tempval |= MACCFG2_FULL_DUPLEX;
3681
3682                         priv->oldduplex = phydev->duplex;
3683                 }
3684
3685                 if (phydev->speed != priv->oldspeed) {
3686                         switch (phydev->speed) {
3687                         case 1000:
3688                                 tempval =
3689                                     ((tempval & ~(MACCFG2_IF)) | MACCFG2_GMII);
3690
3691                                 ecntrl &= ~(ECNTRL_R100);
3692                                 break;
3693                         case 100:
3694                         case 10:
3695                                 tempval =
3696                                     ((tempval & ~(MACCFG2_IF)) | MACCFG2_MII);
3697
3698                                 /* Reduced mode distinguishes
3699                                  * between 10 and 100
3700                                  */
3701                                 if (phydev->speed == SPEED_100)
3702                                         ecntrl |= ECNTRL_R100;
3703                                 else
3704                                         ecntrl &= ~(ECNTRL_R100);
3705                                 break;
3706                         default:
3707                                 netif_warn(priv, link, priv->ndev,
3708                                            "Ack!  Speed (%d) is not 10/100/1000!\n",
3709                                            phydev->speed);
3710                                 break;
3711                         }
3712
3713                         priv->oldspeed = phydev->speed;
3714                 }
3715
3716                 tempval1 &= ~(MACCFG1_TX_FLOW | MACCFG1_RX_FLOW);
3717                 tempval1 |= gfar_get_flowctrl_cfg(priv);
3718
3719                 /* Turn last free buffer recording on */
3720                 if ((tempval1 & MACCFG1_TX_FLOW) && !tx_flow_oldval) {
3721                         for (i = 0; i < priv->num_rx_queues; i++) {
3722                                 u32 bdp_dma;
3723
3724                                 rx_queue = priv->rx_queue[i];
3725                                 bdp_dma = gfar_rxbd_dma_lastfree(rx_queue);
3726                                 gfar_write(rx_queue->rfbptr, bdp_dma);
3727                         }
3728
3729                         priv->tx_actual_en = 1;
3730                 }
3731
3732                 if (unlikely(!(tempval1 & MACCFG1_TX_FLOW) && tx_flow_oldval))
3733                         priv->tx_actual_en = 0;
3734
3735                 gfar_write(&regs->maccfg1, tempval1);
3736                 gfar_write(&regs->maccfg2, tempval);
3737                 gfar_write(&regs->ecntrl, ecntrl);
3738
3739                 if (!priv->oldlink)
3740                         priv->oldlink = 1;
3741
3742         } else if (priv->oldlink) {
3743                 priv->oldlink = 0;
3744                 priv->oldspeed = 0;
3745                 priv->oldduplex = -1;
3746         }
3747
3748         if (netif_msg_link(priv))
3749                 phy_print_status(phydev);
3750 }
3751
3752 static const struct of_device_id gfar_match[] =
3753 {
3754         {
3755                 .type = "network",
3756                 .compatible = "gianfar",
3757         },
3758         {
3759                 .compatible = "fsl,etsec2",
3760         },
3761         {},
3762 };
3763 MODULE_DEVICE_TABLE(of, gfar_match);
3764
3765 /* Structure for a device driver */
3766 static struct platform_driver gfar_driver = {
3767         .driver = {
3768                 .name = "fsl-gianfar",
3769                 .pm = GFAR_PM_OPS,
3770                 .of_match_table = gfar_match,
3771         },
3772         .probe = gfar_probe,
3773         .remove = gfar_remove,
3774 };
3775
3776 module_platform_driver(gfar_driver);