drivers/net/ethernet/hisilicon/hns/hns_dsaf_ppe.c

   1 /*
   2  * Copyright (c) 2014-2015 Hisilicon Limited.
   3  *
   4  * This program is free software; you can redistribute it and/or modify
   5  * it under the terms of the GNU General Public License as published by
   6  * the Free Software Foundation; either version 2 of the License, or
   7  * (at your option) any later version.
   8  */
   9
  10 #include <linux/module.h>
  11 #include <linux/kernel.h>
  12 #include <linux/init.h>
  13 #include <linux/netdevice.h>
  14 #include <linux/etherdevice.h>
  15 #include <linux/platform_device.h>
  16 #include <linux/of.h>
  17 #include <linux/of_address.h>
  18 #include <linux/of_platform.h>
  19
  20 #include "hns_dsaf_ppe.h"
  21
  22 void hns_ppe_set_rss_key(struct hns_ppe_cb *ppe_cb,
  23                          const u32 rss_key[HNS_PPEV2_RSS_KEY_NUM])
  24 {
  25         int key_item = 0;
  26
  27         for (key_item = 0; key_item < HNS_PPEV2_RSS_KEY_NUM; key_item++)
  28                 dsaf_write_dev(ppe_cb, PPEV2_RSS_KEY_REG + key_item * 0x4,
  29                                rss_key[key_item]);
  30 }
  31
  32 void hns_ppe_set_indir_table(struct hns_ppe_cb *ppe_cb,
  33                              const u32 rss_tab[HNS_PPEV2_RSS_IND_TBL_SIZE])
  34 {
  35         int i;
  36         int reg_value;
  37
  38         for (i = 0; i < (HNS_PPEV2_RSS_IND_TBL_SIZE / 4); i++) {
  39                 reg_value = dsaf_read_dev(ppe_cb,
  40                                           PPEV2_INDRECTION_TBL_REG + i * 0x4);
  41
  42                 dsaf_set_field(reg_value, PPEV2_CFG_RSS_TBL_4N0_M,
  43                                PPEV2_CFG_RSS_TBL_4N0_S,
  44                                rss_tab[i * 4 + 0] & 0x1F);
  45                 dsaf_set_field(reg_value, PPEV2_CFG_RSS_TBL_4N1_M,
  46                                PPEV2_CFG_RSS_TBL_4N1_S,
  47                                 rss_tab[i * 4 + 1] & 0x1F);
  48                 dsaf_set_field(reg_value, PPEV2_CFG_RSS_TBL_4N2_M,
  49                                PPEV2_CFG_RSS_TBL_4N2_S,
  50                                 rss_tab[i * 4 + 2] & 0x1F);
  51                 dsaf_set_field(reg_value, PPEV2_CFG_RSS_TBL_4N3_M,
  52                                PPEV2_CFG_RSS_TBL_4N3_S,
  53                                 rss_tab[i * 4 + 3] & 0x1F);
  54                 dsaf_write_dev(
  55                         ppe_cb, PPEV2_INDRECTION_TBL_REG + i * 0x4, reg_value);
  56         }
  57 }
  58
  59 static void __iomem *hns_ppe_common_get_ioaddr(
  60         struct ppe_common_cb *ppe_common)
  61 {
  62         void __iomem *base_addr;
  63
  64         int idx = ppe_common->comm_index;
  65
  66         if (idx == HNS_DSAF_COMM_SERVICE_NW_IDX)
  67                 base_addr = ppe_common->dsaf_dev->ppe_base
  68                         + PPE_COMMON_REG_OFFSET;
  69         else
  70                 base_addr = ppe_common->dsaf_dev->sds_base
  71                         + (idx - 1) * HNS_DSAF_DEBUG_NW_REG_OFFSET
  72                         + PPE_COMMON_REG_OFFSET;
  73
  74         return base_addr;
  75 }
  76
  77 /**
  78  * hns_ppe_common_get_cfg - get ppe common config
  79  * @dsaf_dev: dasf device
  80  * comm_index: common index
  81  * retuen 0 - success , negative --fail
  82  */
  83 int hns_ppe_common_get_cfg(struct dsaf_device *dsaf_dev, int comm_index)
  84 {
  85         struct ppe_common_cb *ppe_common;
  86         int ppe_num;
  87
  88         if (comm_index == HNS_DSAF_COMM_SERVICE_NW_IDX)
  89                 ppe_num = HNS_PPE_SERVICE_NW_ENGINE_NUM;
  90         else
  91                 ppe_num = HNS_PPE_DEBUG_NW_ENGINE_NUM;
  92
  93         ppe_common = devm_kzalloc(dsaf_dev->dev, sizeof(*ppe_common) +
  94                 ppe_num * sizeof(struct hns_ppe_cb), GFP_KERNEL);
  95         if (!ppe_common)
  96                 return -ENOMEM;
  97
  98         ppe_common->ppe_num = ppe_num;
  99         ppe_common->dsaf_dev = dsaf_dev;
 100         ppe_common->comm_index = comm_index;
 101         if (comm_index == HNS_DSAF_COMM_SERVICE_NW_IDX)
 102                 ppe_common->ppe_mode = PPE_COMMON_MODE_SERVICE;
 103         else
 104                 ppe_common->ppe_mode = PPE_COMMON_MODE_DEBUG;
 105         ppe_common->dev = dsaf_dev->dev;
 106
 107         ppe_common->io_base = hns_ppe_common_get_ioaddr(ppe_common);
 108
 109         dsaf_dev->ppe_common[comm_index] = ppe_common;
 110
 111         return 0;
 112 }
 113
 114 void hns_ppe_common_free_cfg(struct dsaf_device *dsaf_dev, u32 comm_index)
 115 {
 116         dsaf_dev->ppe_common[comm_index] = NULL;
 117 }
 118
 119 static void __iomem *hns_ppe_get_iobase(struct ppe_common_cb *ppe_common,
 120                                         int ppe_idx)
 121 {
 122         void __iomem *base_addr;
 123         int common_idx = ppe_common->comm_index;
 124
 125         if (ppe_common->ppe_mode == PPE_COMMON_MODE_SERVICE) {
 126                 base_addr = ppe_common->dsaf_dev->ppe_base +
 127                         ppe_idx * PPE_REG_OFFSET;
 128
 129         } else {
 130                 base_addr = ppe_common->dsaf_dev->sds_base +
 131                         (common_idx - 1) * HNS_DSAF_DEBUG_NW_REG_OFFSET;
 132         }
 133
 134         return base_addr;
 135 }
 136
 137 static int hns_ppe_get_port(struct ppe_common_cb *ppe_common, int idx)
 138 {
 139         int port;
 140
 141         if (ppe_common->ppe_mode == PPE_COMMON_MODE_SERVICE)
 142                 port = idx;
 143         else
 144                 port = HNS_PPE_SERVICE_NW_ENGINE_NUM
 145                         + ppe_common->comm_index - 1;
 146
 147         return port;
 148 }
 149
 150 static void hns_ppe_get_cfg(struct ppe_common_cb *ppe_common)
 151 {
 152         u32 i;
 153         struct hns_ppe_cb *ppe_cb;
 154         u32 ppe_num = ppe_common->ppe_num;
 155
 156         for (i = 0; i < ppe_num; i++) {
 157                 ppe_cb = &ppe_common->ppe_cb[i];
 158                 ppe_cb->dev = ppe_common->dev;
 159                 ppe_cb->next = NULL;
 160                 ppe_cb->ppe_common_cb = ppe_common;
 161                 ppe_cb->index = i;
 162                 ppe_cb->port = hns_ppe_get_port(ppe_common, i);
 163                 ppe_cb->io_base = hns_ppe_get_iobase(ppe_common, i);
 164                 ppe_cb->virq = 0;
 165         }
 166 }
 167
 168 static void hns_ppe_cnt_clr_ce(struct hns_ppe_cb *ppe_cb)
 169 {
 170         dsaf_set_dev_bit(ppe_cb, PPE_TNL_0_5_CNT_CLR_CE_REG,
 171                          PPE_CNT_CLR_CE_B, 1);
 172 }
 173
 174 /**
 175  * hns_ppe_checksum_hw - set ppe checksum caculate
 176  * @ppe_device: ppe device
 177  * @value: value
 178  */
 179 static void hns_ppe_checksum_hw(struct hns_ppe_cb *ppe_cb, u32 value)
 180 {
 181         dsaf_set_dev_field(ppe_cb, PPE_CFG_PRO_CHECK_EN_REG,
 182                            0xfffffff, 0, value);
 183 }
 184
 185 static void hns_ppe_set_qid_mode(struct ppe_common_cb *ppe_common,
 186                                  enum ppe_qid_mode qid_mdoe)
 187 {
 188         dsaf_set_dev_field(ppe_common, PPE_COM_CFG_QID_MODE_REG,
 189                            PPE_CFG_QID_MODE_CF_QID_MODE_M,
 190                            PPE_CFG_QID_MODE_CF_QID_MODE_S, qid_mdoe);
 191 }
 192
 193 /**
 194  * hns_ppe_set_qid - set ppe qid
 195  * @ppe_common: ppe common device
 196  * @qid: queue id
 197  */
 198 static void hns_ppe_set_qid(struct ppe_common_cb *ppe_common, u32 qid)
 199 {
 200         u32 qid_mod = dsaf_read_dev(ppe_common, PPE_COM_CFG_QID_MODE_REG);
 201
 202         if (!dsaf_get_field(qid_mod, PPE_CFG_QID_MODE_DEF_QID_M,
 203                             PPE_CFG_QID_MODE_DEF_QID_S)) {
 204                 dsaf_set_field(qid_mod, PPE_CFG_QID_MODE_DEF_QID_M,
 205                                PPE_CFG_QID_MODE_DEF_QID_S, qid);
 206                 dsaf_write_dev(ppe_common, PPE_COM_CFG_QID_MODE_REG, qid_mod);
 207         }
 208 }
 209
 210 /**
 211  * hns_ppe_set_port_mode - set port mode
 212  * @ppe_device: ppe device
 213  * @mode: port mode
 214  */
 215 static void hns_ppe_set_port_mode(struct hns_ppe_cb *ppe_cb,
 216                                   enum ppe_port_mode mode)
 217 {
 218         dsaf_write_dev(ppe_cb, PPE_CFG_XGE_MODE_REG, mode);
 219 }
 220
 221 /**
 222  * hns_ppe_common_init_hw - init ppe common device
 223  * @ppe_common: ppe common device
 224  *
 225  * Return 0 on success, negative on failure
 226  */
 227 static int hns_ppe_common_init_hw(struct ppe_common_cb *ppe_common)
 228 {
 229         enum ppe_qid_mode qid_mode;
 230         enum dsaf_mode dsaf_mode = ppe_common->dsaf_dev->dsaf_mode;
 231
 232         hns_ppe_com_srst(ppe_common, 0);
 233         mdelay(100);
 234         hns_ppe_com_srst(ppe_common, 1);
 235         mdelay(100);
 236
 237         if (ppe_common->ppe_mode == PPE_COMMON_MODE_SERVICE) {
 238                 switch (dsaf_mode) {
 239                 case DSAF_MODE_ENABLE_FIX:
 240                 case DSAF_MODE_DISABLE_FIX:
 241                         qid_mode = PPE_QID_MODE0;
 242                         hns_ppe_set_qid(ppe_common, 0);
 243                         break;
 244                 case DSAF_MODE_ENABLE_0VM:
 245                 case DSAF_MODE_DISABLE_2PORT_64VM:
 246                         qid_mode = PPE_QID_MODE3;
 247                         break;
 248                 case DSAF_MODE_ENABLE_8VM:
 249                 case DSAF_MODE_DISABLE_2PORT_16VM:
 250                         qid_mode = PPE_QID_MODE4;
 251                         break;
 252                 case DSAF_MODE_ENABLE_16VM:
 253                 case DSAF_MODE_DISABLE_6PORT_0VM:
 254                         qid_mode = PPE_QID_MODE5;
 255                         break;
 256                 case DSAF_MODE_ENABLE_32VM:
 257                 case DSAF_MODE_DISABLE_6PORT_16VM:
 258                         qid_mode = PPE_QID_MODE2;
 259                         break;
 260                 case DSAF_MODE_ENABLE_128VM:
 261                 case DSAF_MODE_DISABLE_6PORT_4VM:
 262                         qid_mode = PPE_QID_MODE1;
 263                         break;
 264                 case DSAF_MODE_DISABLE_2PORT_8VM:
 265                         qid_mode = PPE_QID_MODE7;
 266                         break;
 267                 case DSAF_MODE_DISABLE_6PORT_2VM:
 268                         qid_mode = PPE_QID_MODE6;
 269                         break;
 270                 default:
 271                         dev_err(ppe_common->dev,
 272                                 "get ppe queue mode failed! dsaf_mode=%d\n",
 273                                 dsaf_mode);
 274                         return -EINVAL;
 275                 }
 276                 hns_ppe_set_qid_mode(ppe_common, qid_mode);
 277         }
 278
 279         dsaf_set_dev_bit(ppe_common, PPE_COM_COMMON_CNT_CLR_CE_REG,
 280                          PPE_COMMON_CNT_CLR_CE_B, 1);
 281
 282         return 0;
 283 }
 284
 285 /*clr ppe exception irq*/
 286 static void hns_ppe_exc_irq_en(struct hns_ppe_cb *ppe_cb, int en)
 287 {
 288         u32 clr_vlue = 0xfffffffful;
 289         u32 msk_vlue = en ? 0xfffffffful : 0; /*1 is en, 0 is dis*/
 290         u32 vld_msk = 0;
 291
 292         /*only care bit 0,1,7*/
 293         dsaf_set_bit(vld_msk, 0, 1);
 294         dsaf_set_bit(vld_msk, 1, 1);
 295         dsaf_set_bit(vld_msk, 7, 1);
 296
 297         /*clr sts**/
 298         dsaf_write_dev(ppe_cb, PPE_RINT_REG, clr_vlue);
 299
 300         /*for some reserved bits, so set 0**/
 301         dsaf_write_dev(ppe_cb, PPE_INTEN_REG, msk_vlue & vld_msk);
 302 }
 303
 304 /**
 305  * ppe_init_hw - init ppe
 306  * @ppe_cb: ppe device
 307  */
 308 static void hns_ppe_init_hw(struct hns_ppe_cb *ppe_cb)
 309 {
 310         struct ppe_common_cb *ppe_common_cb = ppe_cb->ppe_common_cb;
 311         u32 port = ppe_cb->port;
 312         struct dsaf_device *dsaf_dev = ppe_common_cb->dsaf_dev;
 313         int i;
 314
 315         /* get default RSS key */
 316         netdev_rss_key_fill(ppe_cb->rss_key, HNS_PPEV2_RSS_KEY_SIZE);
 317
 318         hns_ppe_srst_by_port(dsaf_dev, port, 0);
 319         mdelay(10);
 320         hns_ppe_srst_by_port(dsaf_dev, port, 1);
 321
 322         /* clr and msk except irq*/
 323         hns_ppe_exc_irq_en(ppe_cb, 0);
 324
 325         if (ppe_common_cb->ppe_mode == PPE_COMMON_MODE_DEBUG)
 326                 hns_ppe_set_port_mode(ppe_cb, PPE_MODE_GE);
 327         else
 328                 hns_ppe_set_port_mode(ppe_cb, PPE_MODE_XGE);
 329
 330         hns_ppe_checksum_hw(ppe_cb, 0xffffffff);
 331         hns_ppe_cnt_clr_ce(ppe_cb);
 332
 333         if (!AE_IS_VER1(dsaf_dev->dsaf_ver)) {
 334                 /* set default RSS key in h/w */
 335                 hns_ppe_set_rss_key(ppe_cb, ppe_cb->rss_key);
 336
 337                 /* Set default indrection table in h/w */
 338                 for (i = 0; i < HNS_PPEV2_RSS_IND_TBL_SIZE; i++)
 339                         ppe_cb->rss_indir_table[i] = i;
 340                 hns_ppe_set_indir_table(ppe_cb, ppe_cb->rss_indir_table);
 341         }
 342 }
 343
 344 /**
 345  * ppe_uninit_hw - uninit ppe
 346  * @ppe_device: ppe device
 347  */
 348 static void hns_ppe_uninit_hw(struct hns_ppe_cb *ppe_cb)
 349 {
 350         u32 port;
 351
 352         if (ppe_cb->ppe_common_cb) {
 353                 port = ppe_cb->index;
 354                 hns_ppe_srst_by_port(ppe_cb->ppe_common_cb->dsaf_dev, port, 0);
 355         }
 356 }
 357
 358 void hns_ppe_uninit_ex(struct ppe_common_cb *ppe_common)
 359 {
 360         u32 i;
 361
 362         for (i = 0; i < ppe_common->ppe_num; i++) {
 363                 hns_ppe_uninit_hw(&ppe_common->ppe_cb[i]);
 364                 memset(&ppe_common->ppe_cb[i], 0, sizeof(struct hns_ppe_cb));
 365         }
 366 }
 367
 368 void hns_ppe_uninit(struct dsaf_device *dsaf_dev)
 369 {
 370         u32 i;
 371
 372         for (i = 0; i < HNS_PPE_COM_NUM; i++) {
 373                 if (dsaf_dev->ppe_common[i])
 374                         hns_ppe_uninit_ex(dsaf_dev->ppe_common[i]);
 375                 hns_rcb_common_free_cfg(dsaf_dev, i);
 376                 hns_ppe_common_free_cfg(dsaf_dev, i);
 377         }
 378 }
 379
 380 /**
 381  * hns_ppe_reset - reinit ppe/rcb hw
 382  * @dsaf_dev: dasf device
 383  * retuen void
 384  */
 385 void hns_ppe_reset_common(struct dsaf_device *dsaf_dev, u8 ppe_common_index)
 386 {
 387         u32 i;
 388         int ret;
 389         struct ppe_common_cb *ppe_common;
 390
 391         ppe_common = dsaf_dev->ppe_common[ppe_common_index];
 392         ret = hns_ppe_common_init_hw(ppe_common);
 393         if (ret)
 394                 return;
 395
 396         for (i = 0; i < ppe_common->ppe_num; i++)
 397                 hns_ppe_init_hw(&ppe_common->ppe_cb[i]);
 398
 399         ret = hns_rcb_common_init_hw(dsaf_dev->rcb_common[ppe_common_index]);
 400         if (ret)
 401                 return;
 402
 403         hns_rcb_common_init_commit_hw(dsaf_dev->rcb_common[ppe_common_index]);
 404 }
 405
 406 void hns_ppe_update_stats(struct hns_ppe_cb *ppe_cb)
 407 {
 408         struct hns_ppe_hw_stats *hw_stats = &ppe_cb->hw_stats;
 409
 410         hw_stats->rx_pkts_from_sw
 411                 += dsaf_read_dev(ppe_cb, PPE_HIS_RX_SW_PKT_CNT_REG);
 412         hw_stats->rx_pkts
 413                 += dsaf_read_dev(ppe_cb, PPE_HIS_RX_WR_BD_OK_PKT_CNT_REG);
 414         hw_stats->rx_drop_no_bd
 415                 += dsaf_read_dev(ppe_cb, PPE_HIS_RX_PKT_NO_BUF_CNT_REG);
 416         hw_stats->rx_alloc_buf_fail
 417                 += dsaf_read_dev(ppe_cb, PPE_HIS_RX_APP_BUF_FAIL_CNT_REG);
 418         hw_stats->rx_alloc_buf_wait
 419                 += dsaf_read_dev(ppe_cb, PPE_HIS_RX_APP_BUF_WAIT_CNT_REG);
 420         hw_stats->rx_drop_no_buf
 421                 += dsaf_read_dev(ppe_cb, PPE_HIS_RX_PKT_DROP_FUL_CNT_REG);
 422         hw_stats->rx_err_fifo_full
 423                 += dsaf_read_dev(ppe_cb, PPE_HIS_RX_PKT_DROP_PRT_CNT_REG);
 424
 425         hw_stats->tx_bd_form_rcb
 426                 += dsaf_read_dev(ppe_cb, PPE_HIS_TX_BD_CNT_REG);
 427         hw_stats->tx_pkts_from_rcb
 428                 += dsaf_read_dev(ppe_cb, PPE_HIS_TX_PKT_CNT_REG);
 429         hw_stats->tx_pkts
 430                 += dsaf_read_dev(ppe_cb, PPE_HIS_TX_PKT_OK_CNT_REG);
 431         hw_stats->tx_err_fifo_empty
 432                 += dsaf_read_dev(ppe_cb, PPE_HIS_TX_PKT_EPT_CNT_REG);
 433         hw_stats->tx_err_checksum
 434                 += dsaf_read_dev(ppe_cb, PPE_HIS_TX_PKT_CS_FAIL_CNT_REG);
 435 }
 436
 437 int hns_ppe_get_sset_count(int stringset)
 438 {
 439         if (stringset == ETH_SS_STATS)
 440                 return ETH_PPE_STATIC_NUM;
 441         return 0;
 442 }
 443
 444 int hns_ppe_get_regs_count(void)
 445 {
 446         return ETH_PPE_DUMP_NUM;
 447 }
 448
 449 /**
 450  * ppe_get_strings - get ppe srting
 451  * @ppe_device: ppe device
 452  * @stringset: string set type
 453  * @data: output string
 454  */
 455 void hns_ppe_get_strings(struct hns_ppe_cb *ppe_cb, int stringset, u8 *data)
 456 {
 457         char *buff = (char *)data;
 458         int index = ppe_cb->index;
 459
 460         snprintf(buff, ETH_GSTRING_LEN, "ppe%d_rx_sw_pkt", index);
 461         buff = buff + ETH_GSTRING_LEN;
 462         snprintf(buff, ETH_GSTRING_LEN, "ppe%d_rx_pkt_ok", index);
 463         buff = buff + ETH_GSTRING_LEN;
 464         snprintf(buff, ETH_GSTRING_LEN, "ppe%d_rx_drop_pkt_no_bd", index);
 465         buff = buff + ETH_GSTRING_LEN;
 466         snprintf(buff, ETH_GSTRING_LEN, "ppe%d_rx_alloc_buf_fail", index);
 467         buff = buff + ETH_GSTRING_LEN;
 468         snprintf(buff, ETH_GSTRING_LEN, "ppe%d_rx_alloc_buf_wait", index);
 469         buff = buff + ETH_GSTRING_LEN;
 470         snprintf(buff, ETH_GSTRING_LEN, "ppe%d_rx_pkt_drop_no_buf", index);
 471         buff = buff + ETH_GSTRING_LEN;
 472         snprintf(buff, ETH_GSTRING_LEN, "ppe%d_rx_pkt_err_fifo_full", index);
 473         buff = buff + ETH_GSTRING_LEN;
 474
 475         snprintf(buff, ETH_GSTRING_LEN, "ppe%d_tx_bd", index);
 476         buff = buff + ETH_GSTRING_LEN;
 477         snprintf(buff, ETH_GSTRING_LEN, "ppe%d_tx_pkt", index);
 478         buff = buff + ETH_GSTRING_LEN;
 479         snprintf(buff, ETH_GSTRING_LEN, "ppe%d_tx_pkt_ok", index);
 480         buff = buff + ETH_GSTRING_LEN;
 481         snprintf(buff, ETH_GSTRING_LEN, "ppe%d_tx_pkt_err_fifo_empty", index);
 482         buff = buff + ETH_GSTRING_LEN;
 483         snprintf(buff, ETH_GSTRING_LEN, "ppe%d_tx_pkt_err_csum_fail", index);
 484 }
 485
 486 void hns_ppe_get_stats(struct hns_ppe_cb *ppe_cb, u64 *data)
 487 {
 488         u64 *regs_buff = data;
 489         struct hns_ppe_hw_stats *hw_stats = &ppe_cb->hw_stats;
 490
 491         regs_buff[0] = hw_stats->rx_pkts_from_sw;
 492         regs_buff[1] = hw_stats->rx_pkts;
 493         regs_buff[2] = hw_stats->rx_drop_no_bd;
 494         regs_buff[3] = hw_stats->rx_alloc_buf_fail;
 495         regs_buff[4] = hw_stats->rx_alloc_buf_wait;
 496         regs_buff[5] = hw_stats->rx_drop_no_buf;
 497         regs_buff[6] = hw_stats->rx_err_fifo_full;
 498
 499         regs_buff[7] = hw_stats->tx_bd_form_rcb;
 500         regs_buff[8] = hw_stats->tx_pkts_from_rcb;
 501         regs_buff[9] = hw_stats->tx_pkts;
 502         regs_buff[10] = hw_stats->tx_err_fifo_empty;
 503         regs_buff[11] = hw_stats->tx_err_checksum;
 504 }
 505
 506 /**
 507  * hns_ppe_init - init ppe device
 508  * @dsaf_dev: dasf device
 509  * retuen 0 - success , negative --fail
 510  */
 511 int hns_ppe_init(struct dsaf_device *dsaf_dev)
 512 {
 513         int i, k;
 514         int ret;
 515
 516         for (i = 0; i < HNS_PPE_COM_NUM; i++) {
 517                 ret = hns_ppe_common_get_cfg(dsaf_dev, i);
 518                 if (ret)
 519                         goto get_ppe_cfg_fail;
 520
 521                 ret = hns_rcb_common_get_cfg(dsaf_dev, i);
 522                 if (ret)
 523                         goto get_rcb_cfg_fail;
 524
 525                 hns_ppe_get_cfg(dsaf_dev->ppe_common[i]);
 526
 527                 hns_rcb_get_cfg(dsaf_dev->rcb_common[i]);
 528         }
 529
 530         for (i = 0; i < HNS_PPE_COM_NUM; i++)
 531                 hns_ppe_reset_common(dsaf_dev, i);
 532
 533         return 0;
 534
 535 get_rcb_cfg_fail:
 536         hns_ppe_common_free_cfg(dsaf_dev, i);
 537 get_ppe_cfg_fail:
 538         for (k = i - 1; k >= 0; k--) {
 539                 hns_rcb_common_free_cfg(dsaf_dev, k);
 540                 hns_ppe_common_free_cfg(dsaf_dev, k);
 541         }
 542         return ret;
 543 }
 544
 545 void hns_ppe_get_regs(struct hns_ppe_cb *ppe_cb, void *data)
 546 {
 547         struct ppe_common_cb *ppe_common = ppe_cb->ppe_common_cb;
 548         u32 *regs = data;
 549         u32 i;
 550         u32 offset;
 551
 552         /* ppe common registers */
 553         regs[0] = dsaf_read_dev(ppe_common, PPE_COM_CFG_QID_MODE_REG);
 554         regs[1] = dsaf_read_dev(ppe_common, PPE_COM_INTEN_REG);
 555         regs[2] = dsaf_read_dev(ppe_common, PPE_COM_RINT_REG);
 556         regs[3] = dsaf_read_dev(ppe_common, PPE_COM_INTSTS_REG);
 557         regs[4] = dsaf_read_dev(ppe_common, PPE_COM_COMMON_CNT_CLR_CE_REG);
 558
 559         for (i = 0; i < DSAF_TOTAL_QUEUE_NUM; i++) {
 560                 offset = PPE_COM_HIS_RX_PKT_QID_DROP_CNT_REG + 0x4 * i;
 561                 regs[5 + i] = dsaf_read_dev(ppe_common, offset);
 562                 offset = PPE_COM_HIS_RX_PKT_QID_OK_CNT_REG + 0x4 * i;
 563                 regs[5 + i + DSAF_TOTAL_QUEUE_NUM]
 564                                 = dsaf_read_dev(ppe_common, offset);
 565                 offset = PPE_COM_HIS_TX_PKT_QID_ERR_CNT_REG + 0x4 * i;
 566                 regs[5 + i + DSAF_TOTAL_QUEUE_NUM * 2]
 567                                 = dsaf_read_dev(ppe_common, offset);
 568                 offset = PPE_COM_HIS_TX_PKT_QID_OK_CNT_REG + 0x4 * i;
 569                 regs[5 + i + DSAF_TOTAL_QUEUE_NUM * 3]
 570                                 = dsaf_read_dev(ppe_common, offset);
 571         }
 572
 573         /* mark end of ppe regs */
 574         for (i = 521; i < 524; i++)
 575                 regs[i] = 0xeeeeeeee;
 576
 577         /* ppe channel registers */
 578         regs[525] = dsaf_read_dev(ppe_cb, PPE_CFG_TX_FIFO_THRSLD_REG);
 579         regs[526] = dsaf_read_dev(ppe_cb, PPE_CFG_RX_FIFO_THRSLD_REG);
 580         regs[527] = dsaf_read_dev(ppe_cb, PPE_CFG_RX_FIFO_PAUSE_THRSLD_REG);
 581         regs[528] = dsaf_read_dev(ppe_cb, PPE_CFG_RX_FIFO_SW_BP_THRSLD_REG);
 582         regs[529] = dsaf_read_dev(ppe_cb, PPE_CFG_PAUSE_IDLE_CNT_REG);
 583         regs[530] = dsaf_read_dev(ppe_cb, PPE_CFG_BUS_CTRL_REG);
 584         regs[531] = dsaf_read_dev(ppe_cb, PPE_CFG_TNL_TO_BE_RST_REG);
 585         regs[532] = dsaf_read_dev(ppe_cb, PPE_CURR_TNL_CAN_RST_REG);
 586
 587         regs[533] = dsaf_read_dev(ppe_cb, PPE_CFG_XGE_MODE_REG);
 588         regs[534] = dsaf_read_dev(ppe_cb, PPE_CFG_MAX_FRAME_LEN_REG);
 589         regs[535] = dsaf_read_dev(ppe_cb, PPE_CFG_RX_PKT_MODE_REG);
 590         regs[536] = dsaf_read_dev(ppe_cb, PPE_CFG_RX_VLAN_TAG_REG);
 591         regs[537] = dsaf_read_dev(ppe_cb, PPE_CFG_TAG_GEN_REG);
 592         regs[538] = dsaf_read_dev(ppe_cb, PPE_CFG_PARSE_TAG_REG);
 593         regs[539] = dsaf_read_dev(ppe_cb, PPE_CFG_PRO_CHECK_EN_REG);
 594
 595         regs[540] = dsaf_read_dev(ppe_cb, PPE_INTEN_REG);
 596         regs[541] = dsaf_read_dev(ppe_cb, PPE_RINT_REG);
 597         regs[542] = dsaf_read_dev(ppe_cb, PPE_INTSTS_REG);
 598         regs[543] = dsaf_read_dev(ppe_cb, PPE_CFG_RX_PKT_INT_REG);
 599
 600         regs[544] = dsaf_read_dev(ppe_cb, PPE_CFG_HEAT_DECT_TIME0_REG);
 601         regs[545] = dsaf_read_dev(ppe_cb, PPE_CFG_HEAT_DECT_TIME1_REG);
 602
 603         /* ppe static */
 604         regs[546] = dsaf_read_dev(ppe_cb, PPE_HIS_RX_SW_PKT_CNT_REG);
 605         regs[547] = dsaf_read_dev(ppe_cb, PPE_HIS_RX_WR_BD_OK_PKT_CNT_REG);
 606         regs[548] = dsaf_read_dev(ppe_cb, PPE_HIS_RX_PKT_NO_BUF_CNT_REG);
 607         regs[549] = dsaf_read_dev(ppe_cb, PPE_HIS_TX_BD_CNT_REG);
 608         regs[550] = dsaf_read_dev(ppe_cb, PPE_HIS_TX_PKT_CNT_REG);
 609         regs[551] = dsaf_read_dev(ppe_cb, PPE_HIS_TX_PKT_OK_CNT_REG);
 610         regs[552] = dsaf_read_dev(ppe_cb, PPE_HIS_TX_PKT_EPT_CNT_REG);
 611         regs[553] = dsaf_read_dev(ppe_cb, PPE_HIS_TX_PKT_CS_FAIL_CNT_REG);
 612         regs[554] = dsaf_read_dev(ppe_cb, PPE_HIS_RX_APP_BUF_FAIL_CNT_REG);
 613         regs[555] = dsaf_read_dev(ppe_cb, PPE_HIS_RX_APP_BUF_WAIT_CNT_REG);
 614         regs[556] = dsaf_read_dev(ppe_cb, PPE_HIS_RX_PKT_DROP_FUL_CNT_REG);
 615         regs[557] = dsaf_read_dev(ppe_cb, PPE_HIS_RX_PKT_DROP_PRT_CNT_REG);
 616
 617         regs[558] = dsaf_read_dev(ppe_cb, PPE_TNL_0_5_CNT_CLR_CE_REG);
 618         regs[559] = dsaf_read_dev(ppe_cb, PPE_CFG_AXI_DBG_REG);
 619         regs[560] = dsaf_read_dev(ppe_cb, PPE_HIS_PRO_ERR_REG);
 620         regs[561] = dsaf_read_dev(ppe_cb, PPE_HIS_TNL_FIFO_ERR_REG);
 621         regs[562] = dsaf_read_dev(ppe_cb, PPE_CURR_CFF_DATA_NUM_REG);
 622         regs[563] = dsaf_read_dev(ppe_cb, PPE_CURR_RX_ST_REG);
 623         regs[564] = dsaf_read_dev(ppe_cb, PPE_CURR_TX_ST_REG);
 624         regs[565] = dsaf_read_dev(ppe_cb, PPE_CURR_RX_FIFO0_REG);
 625         regs[566] = dsaf_read_dev(ppe_cb, PPE_CURR_RX_FIFO1_REG);
 626         regs[567] = dsaf_read_dev(ppe_cb, PPE_CURR_TX_FIFO0_REG);
 627         regs[568] = dsaf_read_dev(ppe_cb, PPE_CURR_TX_FIFO1_REG);
 628         regs[569] = dsaf_read_dev(ppe_cb, PPE_ECO0_REG);
 629         regs[570] = dsaf_read_dev(ppe_cb, PPE_ECO1_REG);
 630         regs[571] = dsaf_read_dev(ppe_cb, PPE_ECO2_REG);
 631
 632         /* mark end of ppe regs */
 633         for (i = 572; i < 576; i++)
 634                 regs[i] = 0xeeeeeeee;
 635 }