1 /*******************************************************************************
3 * Intel Ethernet Controller XL710 Family Linux Driver
4 * Copyright(c) 2013 - 2014 Intel Corporation.
6 * This program is free software; you can redistribute it and/or modify it
7 * under the terms and conditions of the GNU General Public License,
8 * version 2, as published by the Free Software Foundation.
10 * This program is distributed in the hope it will be useful, but WITHOUT
11 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
12 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
15 * You should have received a copy of the GNU General Public License along
16 * with this program. If not, see <http://www.gnu.org/licenses/>.
18 * The full GNU General Public License is included in this distribution in
19 * the file called "COPYING".
21 * Contact Information:
22 * e1000-devel Mailing List <e1000-devel@lists.sourceforge.net>
23 * Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
25 ******************************************************************************/
30 #include "i40e_status.h"
31 #include "i40e_osdep.h"
32 #include "i40e_register.h"
33 #include "i40e_adminq.h"
35 #include "i40e_lan_hmc.h"
38 #define I40E_DEV_ID_SFP_XL710 0x1572
39 #define I40E_DEV_ID_SFP_X710 0x1573
40 #define I40E_DEV_ID_QEMU 0x1574
41 #define I40E_DEV_ID_KX_A 0x157F
42 #define I40E_DEV_ID_KX_B 0x1580
43 #define I40E_DEV_ID_KX_C 0x1581
44 #define I40E_DEV_ID_KX_D 0x1582
45 #define I40E_DEV_ID_QSFP_A 0x1583
46 #define I40E_DEV_ID_QSFP_B 0x1584
47 #define I40E_DEV_ID_QSFP_C 0x1585
48 #define I40E_DEV_ID_VF 0x154C
49 #define I40E_DEV_ID_VF_HV 0x1571
51 #define i40e_is_40G_device(d) ((d) == I40E_DEV_ID_QSFP_A || \
52 (d) == I40E_DEV_ID_QSFP_B || \
53 (d) == I40E_DEV_ID_QSFP_C)
55 #define I40E_MAX_VSI_QP 16
56 #define I40E_MAX_VF_VSI 3
57 #define I40E_MAX_CHAINED_RX_BUFFERS 5
58 #define I40E_MAX_PF_UDP_OFFLOAD_PORTS 16
60 /* Max default timeout in ms, */
61 #define I40E_MAX_NVM_TIMEOUT 18000
63 /* Switch from mc to the 2usec global time (this is the GTIME resolution) */
64 #define I40E_MS_TO_GTIME(time) (((time) * 1000) / 2)
66 /* forward declaration */
68 typedef void (*I40E_ADMINQ_CALLBACK)(struct i40e_hw *, struct i40e_aq_desc *);
70 /* Data type manipulation macros. */
72 #define I40E_DESC_UNUSED(R) \
73 ((((R)->next_to_clean > (R)->next_to_use) ? 0 : (R)->count) + \
74 (R)->next_to_clean - (R)->next_to_use - 1)
76 /* bitfields for Tx queue mapping in QTX_CTL */
77 #define I40E_QTX_CTL_VF_QUEUE 0x0
78 #define I40E_QTX_CTL_VM_QUEUE 0x1
79 #define I40E_QTX_CTL_PF_QUEUE 0x2
81 /* debug masks - set these bits in hw->debug_mask to control output */
82 enum i40e_debug_mask {
83 I40E_DEBUG_INIT = 0x00000001,
84 I40E_DEBUG_RELEASE = 0x00000002,
86 I40E_DEBUG_LINK = 0x00000010,
87 I40E_DEBUG_PHY = 0x00000020,
88 I40E_DEBUG_HMC = 0x00000040,
89 I40E_DEBUG_NVM = 0x00000080,
90 I40E_DEBUG_LAN = 0x00000100,
91 I40E_DEBUG_FLOW = 0x00000200,
92 I40E_DEBUG_DCB = 0x00000400,
93 I40E_DEBUG_DIAG = 0x00000800,
95 I40E_DEBUG_AQ_MESSAGE = 0x01000000,
96 I40E_DEBUG_AQ_DESCRIPTOR = 0x02000000,
97 I40E_DEBUG_AQ_DESC_BUFFER = 0x04000000,
98 I40E_DEBUG_AQ_COMMAND = 0x06000000,
99 I40E_DEBUG_AQ = 0x0F000000,
101 I40E_DEBUG_USER = 0xF0000000,
103 I40E_DEBUG_ALL = 0xFFFFFFFF
106 /* These are structs for managing the hardware information and the operations.
107 * The structures of function pointers are filled out at init time when we
108 * know for sure exactly which hardware we're working with. This gives us the
109 * flexibility of using the same main driver code but adapting to slightly
110 * different hardware needs as new parts are developed. For this architecture,
111 * the Firmware and AdminQ are intended to insulate the driver from most of the
112 * future changes, but these structures will also do part of the job.
115 I40E_MAC_UNKNOWN = 0,
122 enum i40e_media_type {
123 I40E_MEDIA_TYPE_UNKNOWN = 0,
124 I40E_MEDIA_TYPE_FIBER,
125 I40E_MEDIA_TYPE_BASET,
126 I40E_MEDIA_TYPE_BACKPLANE,
129 I40E_MEDIA_TYPE_VIRTUAL
150 I40E_VSI_TYPE_UNKNOWN
153 enum i40e_queue_type {
154 I40E_QUEUE_TYPE_RX = 0,
156 I40E_QUEUE_TYPE_PE_CEQ,
157 I40E_QUEUE_TYPE_UNKNOWN
160 struct i40e_link_status {
161 enum i40e_aq_phy_type phy_type;
162 enum i40e_aq_link_speed link_speed;
167 /* is Link Status Event notification to SW enabled */
171 struct i40e_phy_info {
172 struct i40e_link_status link_info;
173 struct i40e_link_status link_info_old;
174 u32 autoneg_advertised;
178 enum i40e_media_type media_type;
181 #define I40E_HW_CAP_MAX_GPIO 30
182 /* Capabilities of a PF or a VF or the whole device */
183 struct i40e_hw_capabilities {
185 #define I40E_NVM_IMAGE_TYPE_EVB 0x0
186 #define I40E_NVM_IMAGE_TYPE_CLOUD 0x2
187 #define I40E_NVM_IMAGE_TYPE_UDP_CLOUD 0x3
195 bool evb_802_1_qbg; /* Edge Virtual Bridging */
196 bool evb_802_1_qbh; /* Bridge Port Extension */
204 u32 fd_filters_guaranteed;
205 u32 fd_filters_best_effort;
208 u32 rss_table_entry_width;
209 bool led[I40E_HW_CAP_MAX_GPIO];
210 bool sdp[I40E_HW_CAP_MAX_GPIO];
212 u32 num_flow_director_filters;
219 u32 num_msix_vectors;
220 u32 num_msix_vectors_vf;
230 struct i40e_mac_info {
231 enum i40e_mac_type type;
233 u8 perm_addr[ETH_ALEN];
234 u8 san_addr[ETH_ALEN];
238 enum i40e_aq_resources_ids {
239 I40E_NVM_RESOURCE_ID = 1
242 enum i40e_aq_resource_access_type {
243 I40E_RESOURCE_READ = 1,
247 struct i40e_nvm_info {
248 u64 hw_semaphore_timeout; /* 2usec global time (GTIME resolution) */
249 u64 hw_semaphore_wait; /* - || - */
250 u32 timeout; /* [ms] */
251 u16 sr_size; /* Shadow RAM size in words */
252 bool blank_nvm_mode; /* is NVM empty (no FW present)*/
253 u16 version; /* NVM package version */
254 u32 eetrack; /* NVM data version */
259 i40e_bus_type_unknown = 0,
262 i40e_bus_type_pci_express,
263 i40e_bus_type_reserved
267 enum i40e_bus_speed {
268 i40e_bus_speed_unknown = 0,
269 i40e_bus_speed_33 = 33,
270 i40e_bus_speed_66 = 66,
271 i40e_bus_speed_100 = 100,
272 i40e_bus_speed_120 = 120,
273 i40e_bus_speed_133 = 133,
274 i40e_bus_speed_2500 = 2500,
275 i40e_bus_speed_5000 = 5000,
276 i40e_bus_speed_8000 = 8000,
277 i40e_bus_speed_reserved
281 enum i40e_bus_width {
282 i40e_bus_width_unknown = 0,
283 i40e_bus_width_pcie_x1 = 1,
284 i40e_bus_width_pcie_x2 = 2,
285 i40e_bus_width_pcie_x4 = 4,
286 i40e_bus_width_pcie_x8 = 8,
287 i40e_bus_width_32 = 32,
288 i40e_bus_width_64 = 64,
289 i40e_bus_width_reserved
293 struct i40e_bus_info {
294 enum i40e_bus_speed speed;
295 enum i40e_bus_width width;
296 enum i40e_bus_type type;
303 /* Flow control (FC) parameters */
304 struct i40e_fc_info {
305 enum i40e_fc_mode current_mode; /* FC mode in effect */
306 enum i40e_fc_mode requested_mode; /* FC mode requested by caller */
309 #define I40E_MAX_TRAFFIC_CLASS 8
310 #define I40E_MAX_USER_PRIORITY 8
311 #define I40E_DCBX_MAX_APPS 32
312 #define I40E_LLDPDU_SIZE 1500
314 /* IEEE 802.1Qaz ETS Configuration data */
315 struct i40e_ieee_ets_config {
319 u8 prioritytable[I40E_MAX_TRAFFIC_CLASS];
320 u8 tcbwtable[I40E_MAX_TRAFFIC_CLASS];
321 u8 tsatable[I40E_MAX_TRAFFIC_CLASS];
324 /* IEEE 802.1Qaz ETS Recommendation data */
325 struct i40e_ieee_ets_recommend {
326 u8 prioritytable[I40E_MAX_TRAFFIC_CLASS];
327 u8 tcbwtable[I40E_MAX_TRAFFIC_CLASS];
328 u8 tsatable[I40E_MAX_TRAFFIC_CLASS];
331 /* IEEE 802.1Qaz PFC Configuration data */
332 struct i40e_ieee_pfc_config {
339 /* IEEE 802.1Qaz Application Priority data */
340 struct i40e_ieee_app_priority_table {
346 struct i40e_dcbx_config {
348 struct i40e_ieee_ets_config etscfg;
349 struct i40e_ieee_ets_recommend etsrec;
350 struct i40e_ieee_pfc_config pfc;
351 struct i40e_ieee_app_priority_table app[I40E_DCBX_MAX_APPS];
354 /* Port hardware description */
359 /* function pointer structs */
360 struct i40e_phy_info phy;
361 struct i40e_mac_info mac;
362 struct i40e_bus_info bus;
363 struct i40e_nvm_info nvm;
364 struct i40e_fc_info fc;
369 u16 subsystem_device_id;
370 u16 subsystem_vendor_id;
373 bool adapter_stopped;
375 /* capabilities for entire device and PCI func */
376 struct i40e_hw_capabilities dev_caps;
377 struct i40e_hw_capabilities func_caps;
379 /* Flow Director shared filter space */
380 u16 fdir_shared_filter_count;
382 /* device profile info */
386 /* Closest numa node to the device */
389 /* Admin Queue info */
390 struct i40e_adminq_info aq;
393 struct i40e_hmc_info hmc; /* HMC info struct */
395 /* LLDP/DCBX Status */
399 struct i40e_dcbx_config local_dcbx_config;
400 struct i40e_dcbx_config remote_dcbx_config;
406 struct i40e_driver_version {
414 union i40e_16byte_rx_desc {
416 __le64 pkt_addr; /* Packet buffer address */
417 __le64 hdr_addr; /* Header buffer address */
423 __le16 mirroring_status;
429 __le32 rss; /* RSS Hash */
430 __le32 fd_id; /* Flow director filter id */
431 __le32 fcoe_param; /* FCoE DDP Context id */
435 /* ext status/error/pktype/length */
436 __le64 status_error_len;
438 } wb; /* writeback */
441 union i40e_32byte_rx_desc {
443 __le64 pkt_addr; /* Packet buffer address */
444 __le64 hdr_addr; /* Header buffer address */
445 /* bit 0 of hdr_buffer_addr is DD bit */
453 __le16 mirroring_status;
459 __le32 rss; /* RSS Hash */
460 __le32 fcoe_param; /* FCoE DDP Context id */
461 /* Flow director filter id in case of
462 * Programming status desc WB
468 /* status/error/pktype/length */
469 __le64 status_error_len;
472 __le16 ext_status; /* extended status */
479 __le32 flex_bytes_lo;
483 __le32 flex_bytes_hi;
487 } wb; /* writeback */
490 #define I40E_RXD_QW1_STATUS_SHIFT 0
491 #define I40E_RXD_QW1_STATUS_MASK (0x7FFFUL << I40E_RXD_QW1_STATUS_SHIFT)
493 enum i40e_rx_desc_status_bits {
494 /* Note: These are predefined bit offsets */
495 I40E_RX_DESC_STATUS_DD_SHIFT = 0,
496 I40E_RX_DESC_STATUS_EOF_SHIFT = 1,
497 I40E_RX_DESC_STATUS_L2TAG1P_SHIFT = 2,
498 I40E_RX_DESC_STATUS_L3L4P_SHIFT = 3,
499 I40E_RX_DESC_STATUS_CRCP_SHIFT = 4,
500 I40E_RX_DESC_STATUS_TSYNINDX_SHIFT = 5, /* 2 BITS */
501 I40E_RX_DESC_STATUS_TSYNVALID_SHIFT = 7,
502 I40E_RX_DESC_STATUS_PIF_SHIFT = 8,
503 I40E_RX_DESC_STATUS_UMBCAST_SHIFT = 9, /* 2 BITS */
504 I40E_RX_DESC_STATUS_FLM_SHIFT = 11,
505 I40E_RX_DESC_STATUS_FLTSTAT_SHIFT = 12, /* 2 BITS */
506 I40E_RX_DESC_STATUS_LPBK_SHIFT = 14,
507 I40E_RX_DESC_STATUS_IPV6EXADD_SHIFT = 15,
508 I40E_RX_DESC_STATUS_RESERVED_SHIFT = 16, /* 2 BITS */
509 I40E_RX_DESC_STATUS_UDP_0_SHIFT = 18
512 #define I40E_RXD_QW1_STATUS_TSYNINDX_SHIFT I40E_RX_DESC_STATUS_TSYNINDX_SHIFT
513 #define I40E_RXD_QW1_STATUS_TSYNINDX_MASK (0x3UL << \
514 I40E_RXD_QW1_STATUS_TSYNINDX_SHIFT)
516 #define I40E_RXD_QW1_STATUS_TSYNVALID_SHIFT I40E_RX_DESC_STATUS_TSYNVALID_SHIFT
517 #define I40E_RXD_QW1_STATUS_TSYNVALID_MASK (0x1UL << \
518 I40E_RXD_QW1_STATUS_TSYNVALID_SHIFT)
520 enum i40e_rx_desc_fltstat_values {
521 I40E_RX_DESC_FLTSTAT_NO_DATA = 0,
522 I40E_RX_DESC_FLTSTAT_RSV_FD_ID = 1, /* 16byte desc? FD_ID : RSV */
523 I40E_RX_DESC_FLTSTAT_RSV = 2,
524 I40E_RX_DESC_FLTSTAT_RSS_HASH = 3,
527 #define I40E_RXD_QW1_ERROR_SHIFT 19
528 #define I40E_RXD_QW1_ERROR_MASK (0xFFUL << I40E_RXD_QW1_ERROR_SHIFT)
530 enum i40e_rx_desc_error_bits {
531 /* Note: These are predefined bit offsets */
532 I40E_RX_DESC_ERROR_RXE_SHIFT = 0,
533 I40E_RX_DESC_ERROR_RECIPE_SHIFT = 1,
534 I40E_RX_DESC_ERROR_HBO_SHIFT = 2,
535 I40E_RX_DESC_ERROR_L3L4E_SHIFT = 3, /* 3 BITS */
536 I40E_RX_DESC_ERROR_IPE_SHIFT = 3,
537 I40E_RX_DESC_ERROR_L4E_SHIFT = 4,
538 I40E_RX_DESC_ERROR_EIPE_SHIFT = 5,
539 I40E_RX_DESC_ERROR_OVERSIZE_SHIFT = 6
542 enum i40e_rx_desc_error_l3l4e_fcoe_masks {
543 I40E_RX_DESC_ERROR_L3L4E_NONE = 0,
544 I40E_RX_DESC_ERROR_L3L4E_PROT = 1,
545 I40E_RX_DESC_ERROR_L3L4E_FC = 2,
546 I40E_RX_DESC_ERROR_L3L4E_DMAC_ERR = 3,
547 I40E_RX_DESC_ERROR_L3L4E_DMAC_WARN = 4
550 #define I40E_RXD_QW1_PTYPE_SHIFT 30
551 #define I40E_RXD_QW1_PTYPE_MASK (0xFFULL << I40E_RXD_QW1_PTYPE_SHIFT)
553 /* Packet type non-ip values */
554 enum i40e_rx_l2_ptype {
555 I40E_RX_PTYPE_L2_RESERVED = 0,
556 I40E_RX_PTYPE_L2_MAC_PAY2 = 1,
557 I40E_RX_PTYPE_L2_TIMESYNC_PAY2 = 2,
558 I40E_RX_PTYPE_L2_FIP_PAY2 = 3,
559 I40E_RX_PTYPE_L2_OUI_PAY2 = 4,
560 I40E_RX_PTYPE_L2_MACCNTRL_PAY2 = 5,
561 I40E_RX_PTYPE_L2_LLDP_PAY2 = 6,
562 I40E_RX_PTYPE_L2_ECP_PAY2 = 7,
563 I40E_RX_PTYPE_L2_EVB_PAY2 = 8,
564 I40E_RX_PTYPE_L2_QCN_PAY2 = 9,
565 I40E_RX_PTYPE_L2_EAPOL_PAY2 = 10,
566 I40E_RX_PTYPE_L2_ARP = 11,
567 I40E_RX_PTYPE_L2_FCOE_PAY3 = 12,
568 I40E_RX_PTYPE_L2_FCOE_FCDATA_PAY3 = 13,
569 I40E_RX_PTYPE_L2_FCOE_FCRDY_PAY3 = 14,
570 I40E_RX_PTYPE_L2_FCOE_FCRSP_PAY3 = 15,
571 I40E_RX_PTYPE_L2_FCOE_FCOTHER_PA = 16,
572 I40E_RX_PTYPE_L2_FCOE_VFT_PAY3 = 17,
573 I40E_RX_PTYPE_L2_FCOE_VFT_FCDATA = 18,
574 I40E_RX_PTYPE_L2_FCOE_VFT_FCRDY = 19,
575 I40E_RX_PTYPE_L2_FCOE_VFT_FCRSP = 20,
576 I40E_RX_PTYPE_L2_FCOE_VFT_FCOTHER = 21,
577 I40E_RX_PTYPE_GRENAT4_MAC_PAY3 = 58,
578 I40E_RX_PTYPE_GRENAT4_MACVLAN_IPV6_ICMP_PAY4 = 87,
579 I40E_RX_PTYPE_GRENAT6_MAC_PAY3 = 124,
580 I40E_RX_PTYPE_GRENAT6_MACVLAN_IPV6_ICMP_PAY4 = 153
583 struct i40e_rx_ptype_decoded {
590 u32 tunnel_end_prot:2;
591 u32 tunnel_end_frag:1;
596 enum i40e_rx_ptype_outer_ip {
597 I40E_RX_PTYPE_OUTER_L2 = 0,
598 I40E_RX_PTYPE_OUTER_IP = 1
601 enum i40e_rx_ptype_outer_ip_ver {
602 I40E_RX_PTYPE_OUTER_NONE = 0,
603 I40E_RX_PTYPE_OUTER_IPV4 = 0,
604 I40E_RX_PTYPE_OUTER_IPV6 = 1
607 enum i40e_rx_ptype_outer_fragmented {
608 I40E_RX_PTYPE_NOT_FRAG = 0,
609 I40E_RX_PTYPE_FRAG = 1
612 enum i40e_rx_ptype_tunnel_type {
613 I40E_RX_PTYPE_TUNNEL_NONE = 0,
614 I40E_RX_PTYPE_TUNNEL_IP_IP = 1,
615 I40E_RX_PTYPE_TUNNEL_IP_GRENAT = 2,
616 I40E_RX_PTYPE_TUNNEL_IP_GRENAT_MAC = 3,
617 I40E_RX_PTYPE_TUNNEL_IP_GRENAT_MAC_VLAN = 4,
620 enum i40e_rx_ptype_tunnel_end_prot {
621 I40E_RX_PTYPE_TUNNEL_END_NONE = 0,
622 I40E_RX_PTYPE_TUNNEL_END_IPV4 = 1,
623 I40E_RX_PTYPE_TUNNEL_END_IPV6 = 2,
626 enum i40e_rx_ptype_inner_prot {
627 I40E_RX_PTYPE_INNER_PROT_NONE = 0,
628 I40E_RX_PTYPE_INNER_PROT_UDP = 1,
629 I40E_RX_PTYPE_INNER_PROT_TCP = 2,
630 I40E_RX_PTYPE_INNER_PROT_SCTP = 3,
631 I40E_RX_PTYPE_INNER_PROT_ICMP = 4,
632 I40E_RX_PTYPE_INNER_PROT_TIMESYNC = 5
635 enum i40e_rx_ptype_payload_layer {
636 I40E_RX_PTYPE_PAYLOAD_LAYER_NONE = 0,
637 I40E_RX_PTYPE_PAYLOAD_LAYER_PAY2 = 1,
638 I40E_RX_PTYPE_PAYLOAD_LAYER_PAY3 = 2,
639 I40E_RX_PTYPE_PAYLOAD_LAYER_PAY4 = 3,
642 #define I40E_RXD_QW1_LENGTH_PBUF_SHIFT 38
643 #define I40E_RXD_QW1_LENGTH_PBUF_MASK (0x3FFFULL << \
644 I40E_RXD_QW1_LENGTH_PBUF_SHIFT)
646 #define I40E_RXD_QW1_LENGTH_HBUF_SHIFT 52
647 #define I40E_RXD_QW1_LENGTH_HBUF_MASK (0x7FFULL << \
648 I40E_RXD_QW1_LENGTH_HBUF_SHIFT)
650 #define I40E_RXD_QW1_LENGTH_SPH_SHIFT 63
651 #define I40E_RXD_QW1_LENGTH_SPH_MASK (0x1ULL << \
652 I40E_RXD_QW1_LENGTH_SPH_SHIFT)
654 enum i40e_rx_desc_ext_status_bits {
655 /* Note: These are predefined bit offsets */
656 I40E_RX_DESC_EXT_STATUS_L2TAG2P_SHIFT = 0,
657 I40E_RX_DESC_EXT_STATUS_L2TAG3P_SHIFT = 1,
658 I40E_RX_DESC_EXT_STATUS_FLEXBL_SHIFT = 2, /* 2 BITS */
659 I40E_RX_DESC_EXT_STATUS_FLEXBH_SHIFT = 4, /* 2 BITS */
660 I40E_RX_DESC_EXT_STATUS_FTYPE_SHIFT = 6, /* 3 BITS */
661 I40E_RX_DESC_EXT_STATUS_FDLONGB_SHIFT = 9,
662 I40E_RX_DESC_EXT_STATUS_FCOELONGB_SHIFT = 10,
663 I40E_RX_DESC_EXT_STATUS_PELONGB_SHIFT = 11,
666 enum i40e_rx_desc_pe_status_bits {
667 /* Note: These are predefined bit offsets */
668 I40E_RX_DESC_PE_STATUS_QPID_SHIFT = 0, /* 18 BITS */
669 I40E_RX_DESC_PE_STATUS_L4PORT_SHIFT = 0, /* 16 BITS */
670 I40E_RX_DESC_PE_STATUS_IPINDEX_SHIFT = 16, /* 8 BITS */
671 I40E_RX_DESC_PE_STATUS_QPIDHIT_SHIFT = 24,
672 I40E_RX_DESC_PE_STATUS_APBVTHIT_SHIFT = 25,
673 I40E_RX_DESC_PE_STATUS_PORTV_SHIFT = 26,
674 I40E_RX_DESC_PE_STATUS_URG_SHIFT = 27,
675 I40E_RX_DESC_PE_STATUS_IPFRAG_SHIFT = 28,
676 I40E_RX_DESC_PE_STATUS_IPOPT_SHIFT = 29
679 #define I40E_RX_PROG_STATUS_DESC_LENGTH_SHIFT 38
680 #define I40E_RX_PROG_STATUS_DESC_LENGTH 0x2000000
682 #define I40E_RX_PROG_STATUS_DESC_QW1_PROGID_SHIFT 2
683 #define I40E_RX_PROG_STATUS_DESC_QW1_PROGID_MASK (0x7UL << \
684 I40E_RX_PROG_STATUS_DESC_QW1_PROGID_SHIFT)
686 #define I40E_RX_PROG_STATUS_DESC_QW1_ERROR_SHIFT 19
687 #define I40E_RX_PROG_STATUS_DESC_QW1_ERROR_MASK (0x3FUL << \
688 I40E_RX_PROG_STATUS_DESC_QW1_ERROR_SHIFT)
690 enum i40e_rx_prog_status_desc_status_bits {
691 /* Note: These are predefined bit offsets */
692 I40E_RX_PROG_STATUS_DESC_DD_SHIFT = 0,
693 I40E_RX_PROG_STATUS_DESC_PROG_ID_SHIFT = 2 /* 3 BITS */
696 enum i40e_rx_prog_status_desc_prog_id_masks {
697 I40E_RX_PROG_STATUS_DESC_FD_FILTER_STATUS = 1,
698 I40E_RX_PROG_STATUS_DESC_FCOE_CTXT_PROG_STATUS = 2,
699 I40E_RX_PROG_STATUS_DESC_FCOE_CTXT_INVL_STATUS = 4,
702 enum i40e_rx_prog_status_desc_error_bits {
703 /* Note: These are predefined bit offsets */
704 I40E_RX_PROG_STATUS_DESC_FD_TBL_FULL_SHIFT = 0,
705 I40E_RX_PROG_STATUS_DESC_NO_FD_ENTRY_SHIFT = 1,
706 I40E_RX_PROG_STATUS_DESC_FCOE_TBL_FULL_SHIFT = 2,
707 I40E_RX_PROG_STATUS_DESC_FCOE_CONFLICT_SHIFT = 3
711 struct i40e_tx_desc {
712 __le64 buffer_addr; /* Address of descriptor's data buf */
713 __le64 cmd_type_offset_bsz;
716 #define I40E_TXD_QW1_DTYPE_SHIFT 0
717 #define I40E_TXD_QW1_DTYPE_MASK (0xFUL << I40E_TXD_QW1_DTYPE_SHIFT)
719 enum i40e_tx_desc_dtype_value {
720 I40E_TX_DESC_DTYPE_DATA = 0x0,
721 I40E_TX_DESC_DTYPE_NOP = 0x1, /* same as Context desc */
722 I40E_TX_DESC_DTYPE_CONTEXT = 0x1,
723 I40E_TX_DESC_DTYPE_FCOE_CTX = 0x2,
724 I40E_TX_DESC_DTYPE_FILTER_PROG = 0x8,
725 I40E_TX_DESC_DTYPE_DDP_CTX = 0x9,
726 I40E_TX_DESC_DTYPE_FLEX_DATA = 0xB,
727 I40E_TX_DESC_DTYPE_FLEX_CTX_1 = 0xC,
728 I40E_TX_DESC_DTYPE_FLEX_CTX_2 = 0xD,
729 I40E_TX_DESC_DTYPE_DESC_DONE = 0xF
732 #define I40E_TXD_QW1_CMD_SHIFT 4
733 #define I40E_TXD_QW1_CMD_MASK (0x3FFUL << I40E_TXD_QW1_CMD_SHIFT)
735 enum i40e_tx_desc_cmd_bits {
736 I40E_TX_DESC_CMD_EOP = 0x0001,
737 I40E_TX_DESC_CMD_RS = 0x0002,
738 I40E_TX_DESC_CMD_ICRC = 0x0004,
739 I40E_TX_DESC_CMD_IL2TAG1 = 0x0008,
740 I40E_TX_DESC_CMD_DUMMY = 0x0010,
741 I40E_TX_DESC_CMD_IIPT_NONIP = 0x0000, /* 2 BITS */
742 I40E_TX_DESC_CMD_IIPT_IPV6 = 0x0020, /* 2 BITS */
743 I40E_TX_DESC_CMD_IIPT_IPV4 = 0x0040, /* 2 BITS */
744 I40E_TX_DESC_CMD_IIPT_IPV4_CSUM = 0x0060, /* 2 BITS */
745 I40E_TX_DESC_CMD_FCOET = 0x0080,
746 I40E_TX_DESC_CMD_L4T_EOFT_UNK = 0x0000, /* 2 BITS */
747 I40E_TX_DESC_CMD_L4T_EOFT_TCP = 0x0100, /* 2 BITS */
748 I40E_TX_DESC_CMD_L4T_EOFT_SCTP = 0x0200, /* 2 BITS */
749 I40E_TX_DESC_CMD_L4T_EOFT_UDP = 0x0300, /* 2 BITS */
750 I40E_TX_DESC_CMD_L4T_EOFT_EOF_N = 0x0000, /* 2 BITS */
751 I40E_TX_DESC_CMD_L4T_EOFT_EOF_T = 0x0100, /* 2 BITS */
752 I40E_TX_DESC_CMD_L4T_EOFT_EOF_NI = 0x0200, /* 2 BITS */
753 I40E_TX_DESC_CMD_L4T_EOFT_EOF_A = 0x0300, /* 2 BITS */
756 #define I40E_TXD_QW1_OFFSET_SHIFT 16
757 #define I40E_TXD_QW1_OFFSET_MASK (0x3FFFFULL << \
758 I40E_TXD_QW1_OFFSET_SHIFT)
760 enum i40e_tx_desc_length_fields {
761 /* Note: These are predefined bit offsets */
762 I40E_TX_DESC_LENGTH_MACLEN_SHIFT = 0, /* 7 BITS */
763 I40E_TX_DESC_LENGTH_IPLEN_SHIFT = 7, /* 7 BITS */
764 I40E_TX_DESC_LENGTH_L4_FC_LEN_SHIFT = 14 /* 4 BITS */
767 #define I40E_TXD_QW1_TX_BUF_SZ_SHIFT 34
768 #define I40E_TXD_QW1_TX_BUF_SZ_MASK (0x3FFFULL << \
769 I40E_TXD_QW1_TX_BUF_SZ_SHIFT)
771 #define I40E_TXD_QW1_L2TAG1_SHIFT 48
772 #define I40E_TXD_QW1_L2TAG1_MASK (0xFFFFULL << I40E_TXD_QW1_L2TAG1_SHIFT)
774 /* Context descriptors */
775 struct i40e_tx_context_desc {
776 __le32 tunneling_params;
779 __le64 type_cmd_tso_mss;
782 #define I40E_TXD_CTX_QW1_DTYPE_SHIFT 0
783 #define I40E_TXD_CTX_QW1_DTYPE_MASK (0xFUL << I40E_TXD_CTX_QW1_DTYPE_SHIFT)
785 #define I40E_TXD_CTX_QW1_CMD_SHIFT 4
786 #define I40E_TXD_CTX_QW1_CMD_MASK (0xFFFFUL << I40E_TXD_CTX_QW1_CMD_SHIFT)
788 enum i40e_tx_ctx_desc_cmd_bits {
789 I40E_TX_CTX_DESC_TSO = 0x01,
790 I40E_TX_CTX_DESC_TSYN = 0x02,
791 I40E_TX_CTX_DESC_IL2TAG2 = 0x04,
792 I40E_TX_CTX_DESC_IL2TAG2_IL2H = 0x08,
793 I40E_TX_CTX_DESC_SWTCH_NOTAG = 0x00,
794 I40E_TX_CTX_DESC_SWTCH_UPLINK = 0x10,
795 I40E_TX_CTX_DESC_SWTCH_LOCAL = 0x20,
796 I40E_TX_CTX_DESC_SWTCH_VSI = 0x30,
797 I40E_TX_CTX_DESC_SWPE = 0x40
800 #define I40E_TXD_CTX_QW1_TSO_LEN_SHIFT 30
801 #define I40E_TXD_CTX_QW1_TSO_LEN_MASK (0x3FFFFULL << \
802 I40E_TXD_CTX_QW1_TSO_LEN_SHIFT)
804 #define I40E_TXD_CTX_QW1_MSS_SHIFT 50
805 #define I40E_TXD_CTX_QW1_MSS_MASK (0x3FFFULL << \
806 I40E_TXD_CTX_QW1_MSS_SHIFT)
808 #define I40E_TXD_CTX_QW1_VSI_SHIFT 50
809 #define I40E_TXD_CTX_QW1_VSI_MASK (0x1FFULL << I40E_TXD_CTX_QW1_VSI_SHIFT)
811 #define I40E_TXD_CTX_QW0_EXT_IP_SHIFT 0
812 #define I40E_TXD_CTX_QW0_EXT_IP_MASK (0x3ULL << \
813 I40E_TXD_CTX_QW0_EXT_IP_SHIFT)
815 enum i40e_tx_ctx_desc_eipt_offload {
816 I40E_TX_CTX_EXT_IP_NONE = 0x0,
817 I40E_TX_CTX_EXT_IP_IPV6 = 0x1,
818 I40E_TX_CTX_EXT_IP_IPV4_NO_CSUM = 0x2,
819 I40E_TX_CTX_EXT_IP_IPV4 = 0x3
822 #define I40E_TXD_CTX_QW0_EXT_IPLEN_SHIFT 2
823 #define I40E_TXD_CTX_QW0_EXT_IPLEN_MASK (0x3FULL << \
824 I40E_TXD_CTX_QW0_EXT_IPLEN_SHIFT)
826 #define I40E_TXD_CTX_QW0_NATT_SHIFT 9
827 #define I40E_TXD_CTX_QW0_NATT_MASK (0x3ULL << I40E_TXD_CTX_QW0_NATT_SHIFT)
829 #define I40E_TXD_CTX_UDP_TUNNELING (0x1ULL << I40E_TXD_CTX_QW0_NATT_SHIFT)
830 #define I40E_TXD_CTX_GRE_TUNNELING (0x2ULL << I40E_TXD_CTX_QW0_NATT_SHIFT)
832 #define I40E_TXD_CTX_QW0_EIP_NOINC_SHIFT 11
833 #define I40E_TXD_CTX_QW0_EIP_NOINC_MASK (0x1ULL << \
834 I40E_TXD_CTX_QW0_EIP_NOINC_SHIFT)
836 #define I40E_TXD_CTX_EIP_NOINC_IPID_CONST I40E_TXD_CTX_QW0_EIP_NOINC_MASK
838 #define I40E_TXD_CTX_QW0_NATLEN_SHIFT 12
839 #define I40E_TXD_CTX_QW0_NATLEN_MASK (0X7FULL << \
840 I40E_TXD_CTX_QW0_NATLEN_SHIFT)
842 #define I40E_TXD_CTX_QW0_DECTTL_SHIFT 19
843 #define I40E_TXD_CTX_QW0_DECTTL_MASK (0xFULL << \
844 I40E_TXD_CTX_QW0_DECTTL_SHIFT)
846 struct i40e_filter_program_desc {
847 __le32 qindex_flex_ptype_vsi;
849 __le32 dtype_cmd_cntindex;
852 #define I40E_TXD_FLTR_QW0_QINDEX_SHIFT 0
853 #define I40E_TXD_FLTR_QW0_QINDEX_MASK (0x7FFUL << \
854 I40E_TXD_FLTR_QW0_QINDEX_SHIFT)
855 #define I40E_TXD_FLTR_QW0_FLEXOFF_SHIFT 11
856 #define I40E_TXD_FLTR_QW0_FLEXOFF_MASK (0x7UL << \
857 I40E_TXD_FLTR_QW0_FLEXOFF_SHIFT)
858 #define I40E_TXD_FLTR_QW0_PCTYPE_SHIFT 17
859 #define I40E_TXD_FLTR_QW0_PCTYPE_MASK (0x3FUL << \
860 I40E_TXD_FLTR_QW0_PCTYPE_SHIFT)
862 /* Packet Classifier Types for filters */
863 enum i40e_filter_pctype {
864 /* Note: Values 0-28 are reserved for future use */
865 I40E_FILTER_PCTYPE_NONF_UNICAST_IPV4_UDP = 29,
866 I40E_FILTER_PCTYPE_NONF_MULTICAST_IPV4_UDP = 30,
867 I40E_FILTER_PCTYPE_NONF_IPV4_UDP = 31,
868 I40E_FILTER_PCTYPE_NONF_IPV4_TCP_SYN = 32,
869 I40E_FILTER_PCTYPE_NONF_IPV4_TCP = 33,
870 I40E_FILTER_PCTYPE_NONF_IPV4_SCTP = 34,
871 I40E_FILTER_PCTYPE_NONF_IPV4_OTHER = 35,
872 I40E_FILTER_PCTYPE_FRAG_IPV4 = 36,
873 /* Note: Values 37-38 are reserved for future use */
874 I40E_FILTER_PCTYPE_NONF_UNICAST_IPV6_UDP = 39,
875 I40E_FILTER_PCTYPE_NONF_MULTICAST_IPV6_UDP = 40,
876 I40E_FILTER_PCTYPE_NONF_IPV6_UDP = 41,
877 I40E_FILTER_PCTYPE_NONF_IPV6_TCP_SYN = 42,
878 I40E_FILTER_PCTYPE_NONF_IPV6_TCP = 43,
879 I40E_FILTER_PCTYPE_NONF_IPV6_SCTP = 44,
880 I40E_FILTER_PCTYPE_NONF_IPV6_OTHER = 45,
881 I40E_FILTER_PCTYPE_FRAG_IPV6 = 46,
882 /* Note: Value 47 is reserved for future use */
883 I40E_FILTER_PCTYPE_FCOE_OX = 48,
884 I40E_FILTER_PCTYPE_FCOE_RX = 49,
885 I40E_FILTER_PCTYPE_FCOE_OTHER = 50,
886 /* Note: Values 51-62 are reserved for future use */
887 I40E_FILTER_PCTYPE_L2_PAYLOAD = 63,
890 enum i40e_filter_program_desc_dest {
891 I40E_FILTER_PROGRAM_DESC_DEST_DROP_PACKET = 0x0,
892 I40E_FILTER_PROGRAM_DESC_DEST_DIRECT_PACKET_QINDEX = 0x1,
893 I40E_FILTER_PROGRAM_DESC_DEST_DIRECT_PACKET_OTHER = 0x2,
896 enum i40e_filter_program_desc_fd_status {
897 I40E_FILTER_PROGRAM_DESC_FD_STATUS_NONE = 0x0,
898 I40E_FILTER_PROGRAM_DESC_FD_STATUS_FD_ID = 0x1,
899 I40E_FILTER_PROGRAM_DESC_FD_STATUS_FD_ID_4FLEX_BYTES = 0x2,
900 I40E_FILTER_PROGRAM_DESC_FD_STATUS_8FLEX_BYTES = 0x3,
903 #define I40E_TXD_FLTR_QW0_DEST_VSI_SHIFT 23
904 #define I40E_TXD_FLTR_QW0_DEST_VSI_MASK (0x1FFUL << \
905 I40E_TXD_FLTR_QW0_DEST_VSI_SHIFT)
907 #define I40E_TXD_FLTR_QW1_CMD_SHIFT 4
908 #define I40E_TXD_FLTR_QW1_CMD_MASK (0xFFFFULL << \
909 I40E_TXD_FLTR_QW1_CMD_SHIFT)
911 #define I40E_TXD_FLTR_QW1_PCMD_SHIFT (0x0ULL + I40E_TXD_FLTR_QW1_CMD_SHIFT)
912 #define I40E_TXD_FLTR_QW1_PCMD_MASK (0x7ULL << I40E_TXD_FLTR_QW1_PCMD_SHIFT)
914 enum i40e_filter_program_desc_pcmd {
915 I40E_FILTER_PROGRAM_DESC_PCMD_ADD_UPDATE = 0x1,
916 I40E_FILTER_PROGRAM_DESC_PCMD_REMOVE = 0x2,
919 #define I40E_TXD_FLTR_QW1_DEST_SHIFT (0x3ULL + I40E_TXD_FLTR_QW1_CMD_SHIFT)
920 #define I40E_TXD_FLTR_QW1_DEST_MASK (0x3ULL << I40E_TXD_FLTR_QW1_DEST_SHIFT)
922 #define I40E_TXD_FLTR_QW1_CNT_ENA_SHIFT (0x7ULL + I40E_TXD_FLTR_QW1_CMD_SHIFT)
923 #define I40E_TXD_FLTR_QW1_CNT_ENA_MASK (0x1ULL << \
924 I40E_TXD_FLTR_QW1_CNT_ENA_SHIFT)
926 #define I40E_TXD_FLTR_QW1_FD_STATUS_SHIFT (0x9ULL + \
927 I40E_TXD_FLTR_QW1_CMD_SHIFT)
928 #define I40E_TXD_FLTR_QW1_FD_STATUS_MASK (0x3ULL << \
929 I40E_TXD_FLTR_QW1_FD_STATUS_SHIFT)
931 #define I40E_TXD_FLTR_QW1_CNTINDEX_SHIFT 20
932 #define I40E_TXD_FLTR_QW1_CNTINDEX_MASK (0x1FFUL << \
933 I40E_TXD_FLTR_QW1_CNTINDEX_SHIFT)
935 enum i40e_filter_type {
936 I40E_FLOW_DIRECTOR_FLTR = 0,
937 I40E_PE_QUAD_HASH_FLTR = 1,
944 struct i40e_vsi_context {
949 u16 vsis_unallocated;
954 struct i40e_aqc_vsi_properties_data info;
957 /* Statistics collected by each port, VSI, VEB, and S-channel */
958 struct i40e_eth_stats {
959 u64 rx_bytes; /* gorc */
960 u64 rx_unicast; /* uprc */
961 u64 rx_multicast; /* mprc */
962 u64 rx_broadcast; /* bprc */
963 u64 rx_discards; /* rdpc */
964 u64 rx_errors; /* repc */
965 u64 rx_missed; /* rmpc */
966 u64 rx_unknown_protocol; /* rupp */
967 u64 tx_bytes; /* gotc */
968 u64 tx_unicast; /* uptc */
969 u64 tx_multicast; /* mptc */
970 u64 tx_broadcast; /* bptc */
971 u64 tx_discards; /* tdpc */
972 u64 tx_errors; /* tepc */
975 /* Statistics collected by the MAC */
976 struct i40e_hw_port_stats {
977 /* eth stats collected by the port */
978 struct i40e_eth_stats eth;
980 /* additional port specific stats */
981 u64 tx_dropped_link_down; /* tdold */
982 u64 crc_errors; /* crcerrs */
983 u64 illegal_bytes; /* illerrc */
984 u64 error_bytes; /* errbc */
985 u64 mac_local_faults; /* mlfc */
986 u64 mac_remote_faults; /* mrfc */
987 u64 rx_length_errors; /* rlec */
988 u64 link_xon_rx; /* lxonrxc */
989 u64 link_xoff_rx; /* lxoffrxc */
990 u64 priority_xon_rx[8]; /* pxonrxc[8] */
991 u64 priority_xoff_rx[8]; /* pxoffrxc[8] */
992 u64 link_xon_tx; /* lxontxc */
993 u64 link_xoff_tx; /* lxofftxc */
994 u64 priority_xon_tx[8]; /* pxontxc[8] */
995 u64 priority_xoff_tx[8]; /* pxofftxc[8] */
996 u64 priority_xon_2_xoff[8]; /* pxon2offc[8] */
997 u64 rx_size_64; /* prc64 */
998 u64 rx_size_127; /* prc127 */
999 u64 rx_size_255; /* prc255 */
1000 u64 rx_size_511; /* prc511 */
1001 u64 rx_size_1023; /* prc1023 */
1002 u64 rx_size_1522; /* prc1522 */
1003 u64 rx_size_big; /* prc9522 */
1004 u64 rx_undersize; /* ruc */
1005 u64 rx_fragments; /* rfc */
1006 u64 rx_oversize; /* roc */
1007 u64 rx_jabber; /* rjc */
1008 u64 tx_size_64; /* ptc64 */
1009 u64 tx_size_127; /* ptc127 */
1010 u64 tx_size_255; /* ptc255 */
1011 u64 tx_size_511; /* ptc511 */
1012 u64 tx_size_1023; /* ptc1023 */
1013 u64 tx_size_1522; /* ptc1522 */
1014 u64 tx_size_big; /* ptc9522 */
1015 u64 mac_short_packet_dropped; /* mspdc */
1016 u64 checksum_error; /* xec */
1020 u64 tx_lpi_count; /* etlpic */
1021 u64 rx_lpi_count; /* erlpic */
1024 /* Checksum and Shadow RAM pointers */
1025 #define I40E_SR_NVM_CONTROL_WORD 0x00
1026 #define I40E_SR_EMP_MODULE_PTR 0x0F
1027 #define I40E_SR_NVM_IMAGE_VERSION 0x18
1028 #define I40E_SR_NVM_WAKE_ON_LAN 0x19
1029 #define I40E_SR_ALTERNATE_SAN_MAC_ADDRESS_PTR 0x27
1030 #define I40E_SR_NVM_EETRACK_LO 0x2D
1031 #define I40E_SR_NVM_EETRACK_HI 0x2E
1032 #define I40E_SR_VPD_PTR 0x2F
1033 #define I40E_SR_PCIE_ALT_AUTO_LOAD_PTR 0x3E
1034 #define I40E_SR_SW_CHECKSUM_WORD 0x3F
1036 /* Auxiliary field, mask and shift definition for Shadow RAM and NVM Flash */
1037 #define I40E_SR_VPD_MODULE_MAX_SIZE 1024
1038 #define I40E_SR_PCIE_ALT_MODULE_MAX_SIZE 1024
1039 #define I40E_SR_CONTROL_WORD_1_SHIFT 0x06
1040 #define I40E_SR_CONTROL_WORD_1_MASK (0x03 << I40E_SR_CONTROL_WORD_1_SHIFT)
1042 /* Shadow RAM related */
1043 #define I40E_SR_SECTOR_SIZE_IN_WORDS 0x800
1044 #define I40E_SR_WORDS_IN_1KB 512
1045 /* Checksum should be calculated such that after adding all the words,
1046 * including the checksum word itself, the sum should be 0xBABA.
1048 #define I40E_SR_SW_CHECKSUM_BASE 0xBABA
1050 #define I40E_SRRD_SRCTL_ATTEMPTS 100000
1052 enum i40e_switch_element_types {
1053 I40E_SWITCH_ELEMENT_TYPE_MAC = 1,
1054 I40E_SWITCH_ELEMENT_TYPE_PF = 2,
1055 I40E_SWITCH_ELEMENT_TYPE_VF = 3,
1056 I40E_SWITCH_ELEMENT_TYPE_EMP = 4,
1057 I40E_SWITCH_ELEMENT_TYPE_BMC = 6,
1058 I40E_SWITCH_ELEMENT_TYPE_PE = 16,
1059 I40E_SWITCH_ELEMENT_TYPE_VEB = 17,
1060 I40E_SWITCH_ELEMENT_TYPE_PA = 18,
1061 I40E_SWITCH_ELEMENT_TYPE_VSI = 19,
1064 /* Supported EtherType filters */
1065 enum i40e_ether_type_index {
1066 I40E_ETHER_TYPE_1588 = 0,
1067 I40E_ETHER_TYPE_FIP = 1,
1068 I40E_ETHER_TYPE_OUI_EXTENDED = 2,
1069 I40E_ETHER_TYPE_MAC_CONTROL = 3,
1070 I40E_ETHER_TYPE_LLDP = 4,
1071 I40E_ETHER_TYPE_EVB_PROTOCOL1 = 5,
1072 I40E_ETHER_TYPE_EVB_PROTOCOL2 = 6,
1073 I40E_ETHER_TYPE_QCN_CNM = 7,
1074 I40E_ETHER_TYPE_8021X = 8,
1075 I40E_ETHER_TYPE_ARP = 9,
1076 I40E_ETHER_TYPE_RSV1 = 10,
1077 I40E_ETHER_TYPE_RSV2 = 11,
1080 /* Filter context base size is 1K */
1081 #define I40E_HASH_FILTER_BASE_SIZE 1024
1082 /* Supported Hash filter values */
1083 enum i40e_hash_filter_size {
1084 I40E_HASH_FILTER_SIZE_1K = 0,
1085 I40E_HASH_FILTER_SIZE_2K = 1,
1086 I40E_HASH_FILTER_SIZE_4K = 2,
1087 I40E_HASH_FILTER_SIZE_8K = 3,
1088 I40E_HASH_FILTER_SIZE_16K = 4,
1089 I40E_HASH_FILTER_SIZE_32K = 5,
1090 I40E_HASH_FILTER_SIZE_64K = 6,
1091 I40E_HASH_FILTER_SIZE_128K = 7,
1092 I40E_HASH_FILTER_SIZE_256K = 8,
1093 I40E_HASH_FILTER_SIZE_512K = 9,
1094 I40E_HASH_FILTER_SIZE_1M = 10,
1097 /* DMA context base size is 0.5K */
1098 #define I40E_DMA_CNTX_BASE_SIZE 512
1099 /* Supported DMA context values */
1100 enum i40e_dma_cntx_size {
1101 I40E_DMA_CNTX_SIZE_512 = 0,
1102 I40E_DMA_CNTX_SIZE_1K = 1,
1103 I40E_DMA_CNTX_SIZE_2K = 2,
1104 I40E_DMA_CNTX_SIZE_4K = 3,
1105 I40E_DMA_CNTX_SIZE_8K = 4,
1106 I40E_DMA_CNTX_SIZE_16K = 5,
1107 I40E_DMA_CNTX_SIZE_32K = 6,
1108 I40E_DMA_CNTX_SIZE_64K = 7,
1109 I40E_DMA_CNTX_SIZE_128K = 8,
1110 I40E_DMA_CNTX_SIZE_256K = 9,
1113 /* Supported Hash look up table (LUT) sizes */
1114 enum i40e_hash_lut_size {
1115 I40E_HASH_LUT_SIZE_128 = 0,
1116 I40E_HASH_LUT_SIZE_512 = 1,
1119 /* Structure to hold a per PF filter control settings */
1120 struct i40e_filter_control_settings {
1121 /* number of PE Quad Hash filter buckets */
1122 enum i40e_hash_filter_size pe_filt_num;
1123 /* number of PE Quad Hash contexts */
1124 enum i40e_dma_cntx_size pe_cntx_num;
1125 /* number of FCoE filter buckets */
1126 enum i40e_hash_filter_size fcoe_filt_num;
1127 /* number of FCoE DDP contexts */
1128 enum i40e_dma_cntx_size fcoe_cntx_num;
1129 /* size of the Hash LUT */
1130 enum i40e_hash_lut_size hash_lut_size;
1131 /* enable FDIR filters for PF and its VFs */
1133 /* enable Ethertype filters for PF and its VFs */
1134 bool enable_ethtype;
1135 /* enable MAC/VLAN filters for PF and its VFs */
1136 bool enable_macvlan;
1139 /* Structure to hold device level control filter counts */
1140 struct i40e_control_filter_stats {
1141 u16 mac_etype_used; /* Used perfect match MAC/EtherType filters */
1142 u16 etype_used; /* Used perfect EtherType filters */
1143 u16 mac_etype_free; /* Un-used perfect match MAC/EtherType filters */
1144 u16 etype_free; /* Un-used perfect EtherType filters */
1147 enum i40e_reset_type {
1149 I40E_RESET_CORER = 1,
1150 I40E_RESET_GLOBR = 2,
1151 I40E_RESET_EMPR = 3,
1153 #endif /* _I40E_TYPE_H_ */