1 /*******************************************************************************
3 * Intel Ethernet Controller XL710 Family Linux Virtual Function Driver
4 * Copyright(c) 2013 - 2015 Intel Corporation.
6 * This program is free software; you can redistribute it and/or modify it
7 * under the terms and conditions of the GNU General Public License,
8 * version 2, as published by the Free Software Foundation.
10 * This program is distributed in the hope it will be useful, but WITHOUT
11 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
12 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
15 * You should have received a copy of the GNU General Public License along
16 * with this program. If not, see <http://www.gnu.org/licenses/>.
18 * The full GNU General Public License is included in this distribution in
19 * the file called "COPYING".
21 * Contact Information:
22 * e1000-devel Mailing List <e1000-devel@lists.sourceforge.net>
23 * Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
25 ******************************************************************************/
30 #include "i40e_status.h"
31 #include "i40e_osdep.h"
32 #include "i40e_register.h"
33 #include "i40e_adminq.h"
35 #include "i40e_lan_hmc.h"
38 #define I40E_DEV_ID_SFP_XL710 0x1572
39 #define I40E_DEV_ID_QEMU 0x1574
40 #define I40E_DEV_ID_KX_A 0x157F
41 #define I40E_DEV_ID_KX_B 0x1580
42 #define I40E_DEV_ID_KX_C 0x1581
43 #define I40E_DEV_ID_QSFP_A 0x1583
44 #define I40E_DEV_ID_QSFP_B 0x1584
45 #define I40E_DEV_ID_QSFP_C 0x1585
46 #define I40E_DEV_ID_10G_BASE_T 0x1586
47 #define I40E_DEV_ID_20G_KR2 0x1587
48 #define I40E_DEV_ID_20G_KR2_A 0x1588
49 #define I40E_DEV_ID_10G_BASE_T4 0x1589
50 #define I40E_DEV_ID_VF 0x154C
51 #define I40E_DEV_ID_VF_HV 0x1571
52 #define I40E_DEV_ID_SFP_X722 0x37D0
53 #define I40E_DEV_ID_1G_BASE_T_X722 0x37D1
54 #define I40E_DEV_ID_10G_BASE_T_X722 0x37D2
55 #define I40E_DEV_ID_X722_VF 0x37CD
56 #define I40E_DEV_ID_X722_VF_HV 0x37D9
58 #define i40e_is_40G_device(d) ((d) == I40E_DEV_ID_QSFP_A || \
59 (d) == I40E_DEV_ID_QSFP_B || \
60 (d) == I40E_DEV_ID_QSFP_C)
62 /* I40E_MASK is a macro used on 32 bit registers */
63 #define I40E_MASK(mask, shift) (mask << shift)
65 #define I40E_MAX_VSI_QP 16
66 #define I40E_MAX_VF_VSI 3
67 #define I40E_MAX_CHAINED_RX_BUFFERS 5
68 #define I40E_MAX_PF_UDP_OFFLOAD_PORTS 16
70 /* Max default timeout in ms, */
71 #define I40E_MAX_NVM_TIMEOUT 18000
73 /* Switch from ms to the 1usec global time (this is the GTIME resolution) */
74 #define I40E_MS_TO_GTIME(time) ((time) * 1000)
76 /* forward declaration */
78 typedef void (*I40E_ADMINQ_CALLBACK)(struct i40e_hw *, struct i40e_aq_desc *);
80 /* Data type manipulation macros. */
82 #define I40E_DESC_UNUSED(R) \
83 ((((R)->next_to_clean > (R)->next_to_use) ? 0 : (R)->count) + \
84 (R)->next_to_clean - (R)->next_to_use - 1)
86 /* bitfields for Tx queue mapping in QTX_CTL */
87 #define I40E_QTX_CTL_VF_QUEUE 0x0
88 #define I40E_QTX_CTL_VM_QUEUE 0x1
89 #define I40E_QTX_CTL_PF_QUEUE 0x2
91 /* debug masks - set these bits in hw->debug_mask to control output */
92 enum i40e_debug_mask {
93 I40E_DEBUG_INIT = 0x00000001,
94 I40E_DEBUG_RELEASE = 0x00000002,
96 I40E_DEBUG_LINK = 0x00000010,
97 I40E_DEBUG_PHY = 0x00000020,
98 I40E_DEBUG_HMC = 0x00000040,
99 I40E_DEBUG_NVM = 0x00000080,
100 I40E_DEBUG_LAN = 0x00000100,
101 I40E_DEBUG_FLOW = 0x00000200,
102 I40E_DEBUG_DCB = 0x00000400,
103 I40E_DEBUG_DIAG = 0x00000800,
104 I40E_DEBUG_FD = 0x00001000,
106 I40E_DEBUG_AQ_MESSAGE = 0x01000000,
107 I40E_DEBUG_AQ_DESCRIPTOR = 0x02000000,
108 I40E_DEBUG_AQ_DESC_BUFFER = 0x04000000,
109 I40E_DEBUG_AQ_COMMAND = 0x06000000,
110 I40E_DEBUG_AQ = 0x0F000000,
112 I40E_DEBUG_USER = 0xF0000000,
114 I40E_DEBUG_ALL = 0xFFFFFFFF
117 /* These are structs for managing the hardware information and the operations.
118 * The structures of function pointers are filled out at init time when we
119 * know for sure exactly which hardware we're working with. This gives us the
120 * flexibility of using the same main driver code but adapting to slightly
121 * different hardware needs as new parts are developed. For this architecture,
122 * the Firmware and AdminQ are intended to insulate the driver from most of the
123 * future changes, but these structures will also do part of the job.
126 I40E_MAC_UNKNOWN = 0,
135 enum i40e_media_type {
136 I40E_MEDIA_TYPE_UNKNOWN = 0,
137 I40E_MEDIA_TYPE_FIBER,
138 I40E_MEDIA_TYPE_BASET,
139 I40E_MEDIA_TYPE_BACKPLANE,
142 I40E_MEDIA_TYPE_VIRTUAL
154 enum i40e_set_fc_aq_failures {
155 I40E_SET_FC_AQ_FAIL_NONE = 0,
156 I40E_SET_FC_AQ_FAIL_GET = 1,
157 I40E_SET_FC_AQ_FAIL_SET = 2,
158 I40E_SET_FC_AQ_FAIL_UPDATE = 4,
159 I40E_SET_FC_AQ_FAIL_SET_UPDATE = 6
171 I40E_VSI_TYPE_UNKNOWN
174 enum i40e_queue_type {
175 I40E_QUEUE_TYPE_RX = 0,
177 I40E_QUEUE_TYPE_PE_CEQ,
178 I40E_QUEUE_TYPE_UNKNOWN
181 struct i40e_link_status {
182 enum i40e_aq_phy_type phy_type;
183 enum i40e_aq_link_speed link_speed;
188 /* is Link Status Event notification to SW enabled */
196 struct i40e_phy_info {
197 struct i40e_link_status link_info;
198 struct i40e_link_status link_info_old;
199 u32 autoneg_advertised;
203 enum i40e_media_type media_type;
206 #define I40E_HW_CAP_MAX_GPIO 30
207 /* Capabilities of a PF or a VF or the whole device */
208 struct i40e_hw_capabilities {
210 #define I40E_NVM_IMAGE_TYPE_EVB 0x0
211 #define I40E_NVM_IMAGE_TYPE_CLOUD 0x2
212 #define I40E_NVM_IMAGE_TYPE_UDP_CLOUD 0x3
220 bool evb_802_1_qbg; /* Edge Virtual Bridging */
221 bool evb_802_1_qbh; /* Bridge Port Extension */
224 bool iscsi; /* Indicates iSCSI enabled */
228 #define I40E_FLEX10_MODE_UNKNOWN 0x0
229 #define I40E_FLEX10_MODE_DCC 0x1
230 #define I40E_FLEX10_MODE_DCI 0x2
233 #define I40E_FLEX10_STATUS_DCC_ERROR 0x1
234 #define I40E_FLEX10_STATUS_VC_MODE 0x2
240 u32 fd_filters_guaranteed;
241 u32 fd_filters_best_effort;
244 u32 rss_table_entry_width;
245 bool led[I40E_HW_CAP_MAX_GPIO];
246 bool sdp[I40E_HW_CAP_MAX_GPIO];
248 u32 num_flow_director_filters;
255 u32 num_msix_vectors;
256 u32 num_msix_vectors_vf;
267 struct i40e_mac_info {
268 enum i40e_mac_type type;
270 u8 perm_addr[ETH_ALEN];
271 u8 san_addr[ETH_ALEN];
275 enum i40e_aq_resources_ids {
276 I40E_NVM_RESOURCE_ID = 1
279 enum i40e_aq_resource_access_type {
280 I40E_RESOURCE_READ = 1,
284 struct i40e_nvm_info {
285 u64 hw_semaphore_timeout; /* usec global time (GTIME resolution) */
286 u32 timeout; /* [ms] */
287 u16 sr_size; /* Shadow RAM size in words */
288 bool blank_nvm_mode; /* is NVM empty (no FW present)*/
289 u16 version; /* NVM package version */
290 u32 eetrack; /* NVM data version */
293 /* definitions used in NVM update support */
295 enum i40e_nvmupd_cmd {
297 I40E_NVMUPD_READ_CON,
298 I40E_NVMUPD_READ_SNT,
299 I40E_NVMUPD_READ_LCB,
301 I40E_NVMUPD_WRITE_ERA,
302 I40E_NVMUPD_WRITE_CON,
303 I40E_NVMUPD_WRITE_SNT,
304 I40E_NVMUPD_WRITE_LCB,
305 I40E_NVMUPD_WRITE_SA,
306 I40E_NVMUPD_CSUM_CON,
308 I40E_NVMUPD_CSUM_LCB,
311 I40E_NVMUPD_GET_AQ_RESULT,
314 enum i40e_nvmupd_state {
315 I40E_NVMUPD_STATE_INIT,
316 I40E_NVMUPD_STATE_READING,
317 I40E_NVMUPD_STATE_WRITING,
318 I40E_NVMUPD_STATE_INIT_WAIT,
319 I40E_NVMUPD_STATE_WRITE_WAIT,
322 /* nvm_access definition and its masks/shifts need to be accessible to
323 * application, core driver, and shared code. Where is the right file?
325 #define I40E_NVM_READ 0xB
326 #define I40E_NVM_WRITE 0xC
328 #define I40E_NVM_MOD_PNT_MASK 0xFF
330 #define I40E_NVM_TRANS_SHIFT 8
331 #define I40E_NVM_TRANS_MASK (0xf << I40E_NVM_TRANS_SHIFT)
332 #define I40E_NVM_CON 0x0
333 #define I40E_NVM_SNT 0x1
334 #define I40E_NVM_LCB 0x2
335 #define I40E_NVM_SA (I40E_NVM_SNT | I40E_NVM_LCB)
336 #define I40E_NVM_ERA 0x4
337 #define I40E_NVM_CSUM 0x8
338 #define I40E_NVM_EXEC 0xf
340 #define I40E_NVM_ADAPT_SHIFT 16
341 #define I40E_NVM_ADAPT_MASK (0xffff << I40E_NVM_ADAPT_SHIFT)
343 #define I40E_NVMUPD_MAX_DATA 4096
344 #define I40E_NVMUPD_IFACE_TIMEOUT 2 /* seconds */
346 struct i40e_nvm_access {
349 u32 offset; /* in bytes */
350 u32 data_size; /* in bytes */
356 i40e_bus_type_unknown = 0,
359 i40e_bus_type_pci_express,
360 i40e_bus_type_reserved
364 enum i40e_bus_speed {
365 i40e_bus_speed_unknown = 0,
366 i40e_bus_speed_33 = 33,
367 i40e_bus_speed_66 = 66,
368 i40e_bus_speed_100 = 100,
369 i40e_bus_speed_120 = 120,
370 i40e_bus_speed_133 = 133,
371 i40e_bus_speed_2500 = 2500,
372 i40e_bus_speed_5000 = 5000,
373 i40e_bus_speed_8000 = 8000,
374 i40e_bus_speed_reserved
378 enum i40e_bus_width {
379 i40e_bus_width_unknown = 0,
380 i40e_bus_width_pcie_x1 = 1,
381 i40e_bus_width_pcie_x2 = 2,
382 i40e_bus_width_pcie_x4 = 4,
383 i40e_bus_width_pcie_x8 = 8,
384 i40e_bus_width_32 = 32,
385 i40e_bus_width_64 = 64,
386 i40e_bus_width_reserved
390 struct i40e_bus_info {
391 enum i40e_bus_speed speed;
392 enum i40e_bus_width width;
393 enum i40e_bus_type type;
400 /* Flow control (FC) parameters */
401 struct i40e_fc_info {
402 enum i40e_fc_mode current_mode; /* FC mode in effect */
403 enum i40e_fc_mode requested_mode; /* FC mode requested by caller */
406 #define I40E_MAX_TRAFFIC_CLASS 8
407 #define I40E_MAX_USER_PRIORITY 8
408 #define I40E_DCBX_MAX_APPS 32
409 #define I40E_LLDPDU_SIZE 1500
411 /* IEEE 802.1Qaz ETS Configuration data */
412 struct i40e_ieee_ets_config {
416 u8 prioritytable[I40E_MAX_TRAFFIC_CLASS];
417 u8 tcbwtable[I40E_MAX_TRAFFIC_CLASS];
418 u8 tsatable[I40E_MAX_TRAFFIC_CLASS];
421 /* IEEE 802.1Qaz ETS Recommendation data */
422 struct i40e_ieee_ets_recommend {
423 u8 prioritytable[I40E_MAX_TRAFFIC_CLASS];
424 u8 tcbwtable[I40E_MAX_TRAFFIC_CLASS];
425 u8 tsatable[I40E_MAX_TRAFFIC_CLASS];
428 /* IEEE 802.1Qaz PFC Configuration data */
429 struct i40e_ieee_pfc_config {
436 /* IEEE 802.1Qaz Application Priority data */
437 struct i40e_ieee_app_priority_table {
443 struct i40e_dcbx_config {
445 u32 tlv_status; /* CEE mode TLV status */
446 struct i40e_ieee_ets_config etscfg;
447 struct i40e_ieee_ets_recommend etsrec;
448 struct i40e_ieee_pfc_config pfc;
449 struct i40e_ieee_app_priority_table app[I40E_DCBX_MAX_APPS];
452 /* Port hardware description */
457 /* subsystem structs */
458 struct i40e_phy_info phy;
459 struct i40e_mac_info mac;
460 struct i40e_bus_info bus;
461 struct i40e_nvm_info nvm;
462 struct i40e_fc_info fc;
467 u16 subsystem_device_id;
468 u16 subsystem_vendor_id;
471 bool adapter_stopped;
473 /* capabilities for entire device and PCI func */
474 struct i40e_hw_capabilities dev_caps;
475 struct i40e_hw_capabilities func_caps;
477 /* Flow Director shared filter space */
478 u16 fdir_shared_filter_count;
480 /* device profile info */
484 /* for multi-function MACs */
489 /* Closest numa node to the device */
492 /* Admin Queue info */
493 struct i40e_adminq_info aq;
495 /* state of nvm update process */
496 enum i40e_nvmupd_state nvmupd_state;
497 struct i40e_aq_desc nvm_wb_desc;
498 struct i40e_virt_mem nvm_buff;
501 struct i40e_hmc_info hmc; /* HMC info struct */
503 /* LLDP/DCBX Status */
507 struct i40e_dcbx_config local_dcbx_config; /* Oper/Local Cfg */
508 struct i40e_dcbx_config remote_dcbx_config; /* Peer Cfg */
509 struct i40e_dcbx_config desired_dcbx_config; /* CEE Desired Cfg */
516 static inline bool i40e_is_vf(struct i40e_hw *hw)
518 return (hw->mac.type == I40E_MAC_VF ||
519 hw->mac.type == I40E_MAC_X722_VF);
522 struct i40e_driver_version {
527 u8 driver_string[32];
531 union i40e_16byte_rx_desc {
533 __le64 pkt_addr; /* Packet buffer address */
534 __le64 hdr_addr; /* Header buffer address */
540 __le16 mirroring_status;
546 __le32 rss; /* RSS Hash */
547 __le32 fd_id; /* Flow director filter id */
548 __le32 fcoe_param; /* FCoE DDP Context id */
552 /* ext status/error/pktype/length */
553 __le64 status_error_len;
555 } wb; /* writeback */
558 union i40e_32byte_rx_desc {
560 __le64 pkt_addr; /* Packet buffer address */
561 __le64 hdr_addr; /* Header buffer address */
562 /* bit 0 of hdr_buffer_addr is DD bit */
570 __le16 mirroring_status;
576 __le32 rss; /* RSS Hash */
577 __le32 fcoe_param; /* FCoE DDP Context id */
578 /* Flow director filter id in case of
579 * Programming status desc WB
585 /* status/error/pktype/length */
586 __le64 status_error_len;
589 __le16 ext_status; /* extended status */
596 __le32 flex_bytes_lo;
600 __le32 flex_bytes_hi;
604 } wb; /* writeback */
607 enum i40e_rx_desc_status_bits {
608 /* Note: These are predefined bit offsets */
609 I40E_RX_DESC_STATUS_DD_SHIFT = 0,
610 I40E_RX_DESC_STATUS_EOF_SHIFT = 1,
611 I40E_RX_DESC_STATUS_L2TAG1P_SHIFT = 2,
612 I40E_RX_DESC_STATUS_L3L4P_SHIFT = 3,
613 I40E_RX_DESC_STATUS_CRCP_SHIFT = 4,
614 I40E_RX_DESC_STATUS_TSYNINDX_SHIFT = 5, /* 2 BITS */
615 I40E_RX_DESC_STATUS_TSYNVALID_SHIFT = 7,
616 /* Note: Bit 8 is reserved in X710 and XL710 */
617 I40E_RX_DESC_STATUS_EXT_UDP_0_SHIFT = 8,
618 I40E_RX_DESC_STATUS_UMBCAST_SHIFT = 9, /* 2 BITS */
619 I40E_RX_DESC_STATUS_FLM_SHIFT = 11,
620 I40E_RX_DESC_STATUS_FLTSTAT_SHIFT = 12, /* 2 BITS */
621 I40E_RX_DESC_STATUS_LPBK_SHIFT = 14,
622 I40E_RX_DESC_STATUS_IPV6EXADD_SHIFT = 15,
623 I40E_RX_DESC_STATUS_RESERVED_SHIFT = 16, /* 2 BITS */
624 /* Note: For non-tunnel packets INT_UDP_0 is the right status for
627 I40E_RX_DESC_STATUS_INT_UDP_0_SHIFT = 18,
628 I40E_RX_DESC_STATUS_LAST /* this entry must be last!!! */
631 #define I40E_RXD_QW1_STATUS_SHIFT 0
632 #define I40E_RXD_QW1_STATUS_MASK ((BIT(I40E_RX_DESC_STATUS_LAST) - 1) \
633 << I40E_RXD_QW1_STATUS_SHIFT)
635 #define I40E_RXD_QW1_STATUS_TSYNINDX_SHIFT I40E_RX_DESC_STATUS_TSYNINDX_SHIFT
636 #define I40E_RXD_QW1_STATUS_TSYNINDX_MASK (0x3UL << \
637 I40E_RXD_QW1_STATUS_TSYNINDX_SHIFT)
639 #define I40E_RXD_QW1_STATUS_TSYNVALID_SHIFT I40E_RX_DESC_STATUS_TSYNVALID_SHIFT
640 #define I40E_RXD_QW1_STATUS_TSYNVALID_MASK \
641 BIT_ULL(I40E_RXD_QW1_STATUS_TSYNVALID_SHIFT)
643 enum i40e_rx_desc_fltstat_values {
644 I40E_RX_DESC_FLTSTAT_NO_DATA = 0,
645 I40E_RX_DESC_FLTSTAT_RSV_FD_ID = 1, /* 16byte desc? FD_ID : RSV */
646 I40E_RX_DESC_FLTSTAT_RSV = 2,
647 I40E_RX_DESC_FLTSTAT_RSS_HASH = 3,
650 #define I40E_RXD_QW1_ERROR_SHIFT 19
651 #define I40E_RXD_QW1_ERROR_MASK (0xFFUL << I40E_RXD_QW1_ERROR_SHIFT)
653 enum i40e_rx_desc_error_bits {
654 /* Note: These are predefined bit offsets */
655 I40E_RX_DESC_ERROR_RXE_SHIFT = 0,
656 I40E_RX_DESC_ERROR_RECIPE_SHIFT = 1,
657 I40E_RX_DESC_ERROR_HBO_SHIFT = 2,
658 I40E_RX_DESC_ERROR_L3L4E_SHIFT = 3, /* 3 BITS */
659 I40E_RX_DESC_ERROR_IPE_SHIFT = 3,
660 I40E_RX_DESC_ERROR_L4E_SHIFT = 4,
661 I40E_RX_DESC_ERROR_EIPE_SHIFT = 5,
662 I40E_RX_DESC_ERROR_OVERSIZE_SHIFT = 6,
663 I40E_RX_DESC_ERROR_PPRS_SHIFT = 7
666 enum i40e_rx_desc_error_l3l4e_fcoe_masks {
667 I40E_RX_DESC_ERROR_L3L4E_NONE = 0,
668 I40E_RX_DESC_ERROR_L3L4E_PROT = 1,
669 I40E_RX_DESC_ERROR_L3L4E_FC = 2,
670 I40E_RX_DESC_ERROR_L3L4E_DMAC_ERR = 3,
671 I40E_RX_DESC_ERROR_L3L4E_DMAC_WARN = 4
674 #define I40E_RXD_QW1_PTYPE_SHIFT 30
675 #define I40E_RXD_QW1_PTYPE_MASK (0xFFULL << I40E_RXD_QW1_PTYPE_SHIFT)
677 /* Packet type non-ip values */
678 enum i40e_rx_l2_ptype {
679 I40E_RX_PTYPE_L2_RESERVED = 0,
680 I40E_RX_PTYPE_L2_MAC_PAY2 = 1,
681 I40E_RX_PTYPE_L2_TIMESYNC_PAY2 = 2,
682 I40E_RX_PTYPE_L2_FIP_PAY2 = 3,
683 I40E_RX_PTYPE_L2_OUI_PAY2 = 4,
684 I40E_RX_PTYPE_L2_MACCNTRL_PAY2 = 5,
685 I40E_RX_PTYPE_L2_LLDP_PAY2 = 6,
686 I40E_RX_PTYPE_L2_ECP_PAY2 = 7,
687 I40E_RX_PTYPE_L2_EVB_PAY2 = 8,
688 I40E_RX_PTYPE_L2_QCN_PAY2 = 9,
689 I40E_RX_PTYPE_L2_EAPOL_PAY2 = 10,
690 I40E_RX_PTYPE_L2_ARP = 11,
691 I40E_RX_PTYPE_L2_FCOE_PAY3 = 12,
692 I40E_RX_PTYPE_L2_FCOE_FCDATA_PAY3 = 13,
693 I40E_RX_PTYPE_L2_FCOE_FCRDY_PAY3 = 14,
694 I40E_RX_PTYPE_L2_FCOE_FCRSP_PAY3 = 15,
695 I40E_RX_PTYPE_L2_FCOE_FCOTHER_PA = 16,
696 I40E_RX_PTYPE_L2_FCOE_VFT_PAY3 = 17,
697 I40E_RX_PTYPE_L2_FCOE_VFT_FCDATA = 18,
698 I40E_RX_PTYPE_L2_FCOE_VFT_FCRDY = 19,
699 I40E_RX_PTYPE_L2_FCOE_VFT_FCRSP = 20,
700 I40E_RX_PTYPE_L2_FCOE_VFT_FCOTHER = 21,
701 I40E_RX_PTYPE_GRENAT4_MAC_PAY3 = 58,
702 I40E_RX_PTYPE_GRENAT4_MACVLAN_IPV6_ICMP_PAY4 = 87,
703 I40E_RX_PTYPE_GRENAT6_MAC_PAY3 = 124,
704 I40E_RX_PTYPE_GRENAT6_MACVLAN_IPV6_ICMP_PAY4 = 153
707 struct i40e_rx_ptype_decoded {
714 u32 tunnel_end_prot:2;
715 u32 tunnel_end_frag:1;
720 enum i40e_rx_ptype_outer_ip {
721 I40E_RX_PTYPE_OUTER_L2 = 0,
722 I40E_RX_PTYPE_OUTER_IP = 1
725 enum i40e_rx_ptype_outer_ip_ver {
726 I40E_RX_PTYPE_OUTER_NONE = 0,
727 I40E_RX_PTYPE_OUTER_IPV4 = 0,
728 I40E_RX_PTYPE_OUTER_IPV6 = 1
731 enum i40e_rx_ptype_outer_fragmented {
732 I40E_RX_PTYPE_NOT_FRAG = 0,
733 I40E_RX_PTYPE_FRAG = 1
736 enum i40e_rx_ptype_tunnel_type {
737 I40E_RX_PTYPE_TUNNEL_NONE = 0,
738 I40E_RX_PTYPE_TUNNEL_IP_IP = 1,
739 I40E_RX_PTYPE_TUNNEL_IP_GRENAT = 2,
740 I40E_RX_PTYPE_TUNNEL_IP_GRENAT_MAC = 3,
741 I40E_RX_PTYPE_TUNNEL_IP_GRENAT_MAC_VLAN = 4,
744 enum i40e_rx_ptype_tunnel_end_prot {
745 I40E_RX_PTYPE_TUNNEL_END_NONE = 0,
746 I40E_RX_PTYPE_TUNNEL_END_IPV4 = 1,
747 I40E_RX_PTYPE_TUNNEL_END_IPV6 = 2,
750 enum i40e_rx_ptype_inner_prot {
751 I40E_RX_PTYPE_INNER_PROT_NONE = 0,
752 I40E_RX_PTYPE_INNER_PROT_UDP = 1,
753 I40E_RX_PTYPE_INNER_PROT_TCP = 2,
754 I40E_RX_PTYPE_INNER_PROT_SCTP = 3,
755 I40E_RX_PTYPE_INNER_PROT_ICMP = 4,
756 I40E_RX_PTYPE_INNER_PROT_TIMESYNC = 5
759 enum i40e_rx_ptype_payload_layer {
760 I40E_RX_PTYPE_PAYLOAD_LAYER_NONE = 0,
761 I40E_RX_PTYPE_PAYLOAD_LAYER_PAY2 = 1,
762 I40E_RX_PTYPE_PAYLOAD_LAYER_PAY3 = 2,
763 I40E_RX_PTYPE_PAYLOAD_LAYER_PAY4 = 3,
766 #define I40E_RXD_QW1_LENGTH_PBUF_SHIFT 38
767 #define I40E_RXD_QW1_LENGTH_PBUF_MASK (0x3FFFULL << \
768 I40E_RXD_QW1_LENGTH_PBUF_SHIFT)
770 #define I40E_RXD_QW1_LENGTH_HBUF_SHIFT 52
771 #define I40E_RXD_QW1_LENGTH_HBUF_MASK (0x7FFULL << \
772 I40E_RXD_QW1_LENGTH_HBUF_SHIFT)
774 #define I40E_RXD_QW1_LENGTH_SPH_SHIFT 63
775 #define I40E_RXD_QW1_LENGTH_SPH_MASK BIT_ULL(I40E_RXD_QW1_LENGTH_SPH_SHIFT)
777 enum i40e_rx_desc_ext_status_bits {
778 /* Note: These are predefined bit offsets */
779 I40E_RX_DESC_EXT_STATUS_L2TAG2P_SHIFT = 0,
780 I40E_RX_DESC_EXT_STATUS_L2TAG3P_SHIFT = 1,
781 I40E_RX_DESC_EXT_STATUS_FLEXBL_SHIFT = 2, /* 2 BITS */
782 I40E_RX_DESC_EXT_STATUS_FLEXBH_SHIFT = 4, /* 2 BITS */
783 I40E_RX_DESC_EXT_STATUS_FDLONGB_SHIFT = 9,
784 I40E_RX_DESC_EXT_STATUS_FCOELONGB_SHIFT = 10,
785 I40E_RX_DESC_EXT_STATUS_PELONGB_SHIFT = 11,
788 enum i40e_rx_desc_pe_status_bits {
789 /* Note: These are predefined bit offsets */
790 I40E_RX_DESC_PE_STATUS_QPID_SHIFT = 0, /* 18 BITS */
791 I40E_RX_DESC_PE_STATUS_L4PORT_SHIFT = 0, /* 16 BITS */
792 I40E_RX_DESC_PE_STATUS_IPINDEX_SHIFT = 16, /* 8 BITS */
793 I40E_RX_DESC_PE_STATUS_QPIDHIT_SHIFT = 24,
794 I40E_RX_DESC_PE_STATUS_APBVTHIT_SHIFT = 25,
795 I40E_RX_DESC_PE_STATUS_PORTV_SHIFT = 26,
796 I40E_RX_DESC_PE_STATUS_URG_SHIFT = 27,
797 I40E_RX_DESC_PE_STATUS_IPFRAG_SHIFT = 28,
798 I40E_RX_DESC_PE_STATUS_IPOPT_SHIFT = 29
801 #define I40E_RX_PROG_STATUS_DESC_LENGTH_SHIFT 38
802 #define I40E_RX_PROG_STATUS_DESC_LENGTH 0x2000000
804 #define I40E_RX_PROG_STATUS_DESC_QW1_PROGID_SHIFT 2
805 #define I40E_RX_PROG_STATUS_DESC_QW1_PROGID_MASK (0x7UL << \
806 I40E_RX_PROG_STATUS_DESC_QW1_PROGID_SHIFT)
808 #define I40E_RX_PROG_STATUS_DESC_QW1_ERROR_SHIFT 19
809 #define I40E_RX_PROG_STATUS_DESC_QW1_ERROR_MASK (0x3FUL << \
810 I40E_RX_PROG_STATUS_DESC_QW1_ERROR_SHIFT)
812 enum i40e_rx_prog_status_desc_status_bits {
813 /* Note: These are predefined bit offsets */
814 I40E_RX_PROG_STATUS_DESC_DD_SHIFT = 0,
815 I40E_RX_PROG_STATUS_DESC_PROG_ID_SHIFT = 2 /* 3 BITS */
818 enum i40e_rx_prog_status_desc_prog_id_masks {
819 I40E_RX_PROG_STATUS_DESC_FD_FILTER_STATUS = 1,
820 I40E_RX_PROG_STATUS_DESC_FCOE_CTXT_PROG_STATUS = 2,
821 I40E_RX_PROG_STATUS_DESC_FCOE_CTXT_INVL_STATUS = 4,
824 enum i40e_rx_prog_status_desc_error_bits {
825 /* Note: These are predefined bit offsets */
826 I40E_RX_PROG_STATUS_DESC_FD_TBL_FULL_SHIFT = 0,
827 I40E_RX_PROG_STATUS_DESC_NO_FD_ENTRY_SHIFT = 1,
828 I40E_RX_PROG_STATUS_DESC_FCOE_TBL_FULL_SHIFT = 2,
829 I40E_RX_PROG_STATUS_DESC_FCOE_CONFLICT_SHIFT = 3
833 struct i40e_tx_desc {
834 __le64 buffer_addr; /* Address of descriptor's data buf */
835 __le64 cmd_type_offset_bsz;
838 #define I40E_TXD_QW1_DTYPE_SHIFT 0
839 #define I40E_TXD_QW1_DTYPE_MASK (0xFUL << I40E_TXD_QW1_DTYPE_SHIFT)
841 enum i40e_tx_desc_dtype_value {
842 I40E_TX_DESC_DTYPE_DATA = 0x0,
843 I40E_TX_DESC_DTYPE_NOP = 0x1, /* same as Context desc */
844 I40E_TX_DESC_DTYPE_CONTEXT = 0x1,
845 I40E_TX_DESC_DTYPE_FCOE_CTX = 0x2,
846 I40E_TX_DESC_DTYPE_FILTER_PROG = 0x8,
847 I40E_TX_DESC_DTYPE_DDP_CTX = 0x9,
848 I40E_TX_DESC_DTYPE_FLEX_DATA = 0xB,
849 I40E_TX_DESC_DTYPE_FLEX_CTX_1 = 0xC,
850 I40E_TX_DESC_DTYPE_FLEX_CTX_2 = 0xD,
851 I40E_TX_DESC_DTYPE_DESC_DONE = 0xF
854 #define I40E_TXD_QW1_CMD_SHIFT 4
855 #define I40E_TXD_QW1_CMD_MASK (0x3FFUL << I40E_TXD_QW1_CMD_SHIFT)
857 enum i40e_tx_desc_cmd_bits {
858 I40E_TX_DESC_CMD_EOP = 0x0001,
859 I40E_TX_DESC_CMD_RS = 0x0002,
860 I40E_TX_DESC_CMD_ICRC = 0x0004,
861 I40E_TX_DESC_CMD_IL2TAG1 = 0x0008,
862 I40E_TX_DESC_CMD_DUMMY = 0x0010,
863 I40E_TX_DESC_CMD_IIPT_NONIP = 0x0000, /* 2 BITS */
864 I40E_TX_DESC_CMD_IIPT_IPV6 = 0x0020, /* 2 BITS */
865 I40E_TX_DESC_CMD_IIPT_IPV4 = 0x0040, /* 2 BITS */
866 I40E_TX_DESC_CMD_IIPT_IPV4_CSUM = 0x0060, /* 2 BITS */
867 I40E_TX_DESC_CMD_FCOET = 0x0080,
868 I40E_TX_DESC_CMD_L4T_EOFT_UNK = 0x0000, /* 2 BITS */
869 I40E_TX_DESC_CMD_L4T_EOFT_TCP = 0x0100, /* 2 BITS */
870 I40E_TX_DESC_CMD_L4T_EOFT_SCTP = 0x0200, /* 2 BITS */
871 I40E_TX_DESC_CMD_L4T_EOFT_UDP = 0x0300, /* 2 BITS */
872 I40E_TX_DESC_CMD_L4T_EOFT_EOF_N = 0x0000, /* 2 BITS */
873 I40E_TX_DESC_CMD_L4T_EOFT_EOF_T = 0x0100, /* 2 BITS */
874 I40E_TX_DESC_CMD_L4T_EOFT_EOF_NI = 0x0200, /* 2 BITS */
875 I40E_TX_DESC_CMD_L4T_EOFT_EOF_A = 0x0300, /* 2 BITS */
878 #define I40E_TXD_QW1_OFFSET_SHIFT 16
879 #define I40E_TXD_QW1_OFFSET_MASK (0x3FFFFULL << \
880 I40E_TXD_QW1_OFFSET_SHIFT)
882 enum i40e_tx_desc_length_fields {
883 /* Note: These are predefined bit offsets */
884 I40E_TX_DESC_LENGTH_MACLEN_SHIFT = 0, /* 7 BITS */
885 I40E_TX_DESC_LENGTH_IPLEN_SHIFT = 7, /* 7 BITS */
886 I40E_TX_DESC_LENGTH_L4_FC_LEN_SHIFT = 14 /* 4 BITS */
889 #define I40E_TXD_QW1_TX_BUF_SZ_SHIFT 34
890 #define I40E_TXD_QW1_TX_BUF_SZ_MASK (0x3FFFULL << \
891 I40E_TXD_QW1_TX_BUF_SZ_SHIFT)
893 #define I40E_TXD_QW1_L2TAG1_SHIFT 48
894 #define I40E_TXD_QW1_L2TAG1_MASK (0xFFFFULL << I40E_TXD_QW1_L2TAG1_SHIFT)
896 /* Context descriptors */
897 struct i40e_tx_context_desc {
898 __le32 tunneling_params;
901 __le64 type_cmd_tso_mss;
904 #define I40E_TXD_CTX_QW1_DTYPE_SHIFT 0
905 #define I40E_TXD_CTX_QW1_DTYPE_MASK (0xFUL << I40E_TXD_CTX_QW1_DTYPE_SHIFT)
907 #define I40E_TXD_CTX_QW1_CMD_SHIFT 4
908 #define I40E_TXD_CTX_QW1_CMD_MASK (0xFFFFUL << I40E_TXD_CTX_QW1_CMD_SHIFT)
910 enum i40e_tx_ctx_desc_cmd_bits {
911 I40E_TX_CTX_DESC_TSO = 0x01,
912 I40E_TX_CTX_DESC_TSYN = 0x02,
913 I40E_TX_CTX_DESC_IL2TAG2 = 0x04,
914 I40E_TX_CTX_DESC_IL2TAG2_IL2H = 0x08,
915 I40E_TX_CTX_DESC_SWTCH_NOTAG = 0x00,
916 I40E_TX_CTX_DESC_SWTCH_UPLINK = 0x10,
917 I40E_TX_CTX_DESC_SWTCH_LOCAL = 0x20,
918 I40E_TX_CTX_DESC_SWTCH_VSI = 0x30,
919 I40E_TX_CTX_DESC_SWPE = 0x40
922 #define I40E_TXD_CTX_QW1_TSO_LEN_SHIFT 30
923 #define I40E_TXD_CTX_QW1_TSO_LEN_MASK (0x3FFFFULL << \
924 I40E_TXD_CTX_QW1_TSO_LEN_SHIFT)
926 #define I40E_TXD_CTX_QW1_MSS_SHIFT 50
927 #define I40E_TXD_CTX_QW1_MSS_MASK (0x3FFFULL << \
928 I40E_TXD_CTX_QW1_MSS_SHIFT)
930 #define I40E_TXD_CTX_QW1_VSI_SHIFT 50
931 #define I40E_TXD_CTX_QW1_VSI_MASK (0x1FFULL << I40E_TXD_CTX_QW1_VSI_SHIFT)
933 #define I40E_TXD_CTX_QW0_EXT_IP_SHIFT 0
934 #define I40E_TXD_CTX_QW0_EXT_IP_MASK (0x3ULL << \
935 I40E_TXD_CTX_QW0_EXT_IP_SHIFT)
937 enum i40e_tx_ctx_desc_eipt_offload {
938 I40E_TX_CTX_EXT_IP_NONE = 0x0,
939 I40E_TX_CTX_EXT_IP_IPV6 = 0x1,
940 I40E_TX_CTX_EXT_IP_IPV4_NO_CSUM = 0x2,
941 I40E_TX_CTX_EXT_IP_IPV4 = 0x3
944 #define I40E_TXD_CTX_QW0_EXT_IPLEN_SHIFT 2
945 #define I40E_TXD_CTX_QW0_EXT_IPLEN_MASK (0x3FULL << \
946 I40E_TXD_CTX_QW0_EXT_IPLEN_SHIFT)
948 #define I40E_TXD_CTX_QW0_NATT_SHIFT 9
949 #define I40E_TXD_CTX_QW0_NATT_MASK (0x3ULL << I40E_TXD_CTX_QW0_NATT_SHIFT)
951 #define I40E_TXD_CTX_UDP_TUNNELING BIT_ULL(I40E_TXD_CTX_QW0_NATT_SHIFT)
952 #define I40E_TXD_CTX_GRE_TUNNELING (0x2ULL << I40E_TXD_CTX_QW0_NATT_SHIFT)
954 #define I40E_TXD_CTX_QW0_EIP_NOINC_SHIFT 11
955 #define I40E_TXD_CTX_QW0_EIP_NOINC_MASK \
956 BIT_ULL(I40E_TXD_CTX_QW0_EIP_NOINC_SHIFT)
958 #define I40E_TXD_CTX_EIP_NOINC_IPID_CONST I40E_TXD_CTX_QW0_EIP_NOINC_MASK
960 #define I40E_TXD_CTX_QW0_NATLEN_SHIFT 12
961 #define I40E_TXD_CTX_QW0_NATLEN_MASK (0X7FULL << \
962 I40E_TXD_CTX_QW0_NATLEN_SHIFT)
964 #define I40E_TXD_CTX_QW0_DECTTL_SHIFT 19
965 #define I40E_TXD_CTX_QW0_DECTTL_MASK (0xFULL << \
966 I40E_TXD_CTX_QW0_DECTTL_SHIFT)
968 #define I40E_TXD_CTX_QW0_L4T_CS_SHIFT 23
969 #define I40E_TXD_CTX_QW0_L4T_CS_MASK BIT_ULL(I40E_TXD_CTX_QW0_L4T_CS_SHIFT)
970 struct i40e_filter_program_desc {
971 __le32 qindex_flex_ptype_vsi;
973 __le32 dtype_cmd_cntindex;
976 #define I40E_TXD_FLTR_QW0_QINDEX_SHIFT 0
977 #define I40E_TXD_FLTR_QW0_QINDEX_MASK (0x7FFUL << \
978 I40E_TXD_FLTR_QW0_QINDEX_SHIFT)
979 #define I40E_TXD_FLTR_QW0_FLEXOFF_SHIFT 11
980 #define I40E_TXD_FLTR_QW0_FLEXOFF_MASK (0x7UL << \
981 I40E_TXD_FLTR_QW0_FLEXOFF_SHIFT)
982 #define I40E_TXD_FLTR_QW0_PCTYPE_SHIFT 17
983 #define I40E_TXD_FLTR_QW0_PCTYPE_MASK (0x3FUL << \
984 I40E_TXD_FLTR_QW0_PCTYPE_SHIFT)
986 /* Packet Classifier Types for filters */
987 enum i40e_filter_pctype {
988 /* Note: Values 0-28 are reserved for future use.
989 * Value 29, 30, 32 are not supported on XL710 and X710.
991 I40E_FILTER_PCTYPE_NONF_UNICAST_IPV4_UDP = 29,
992 I40E_FILTER_PCTYPE_NONF_MULTICAST_IPV4_UDP = 30,
993 I40E_FILTER_PCTYPE_NONF_IPV4_UDP = 31,
994 I40E_FILTER_PCTYPE_NONF_IPV4_TCP_SYN_NO_ACK = 32,
995 I40E_FILTER_PCTYPE_NONF_IPV4_TCP = 33,
996 I40E_FILTER_PCTYPE_NONF_IPV4_SCTP = 34,
997 I40E_FILTER_PCTYPE_NONF_IPV4_OTHER = 35,
998 I40E_FILTER_PCTYPE_FRAG_IPV4 = 36,
999 /* Note: Values 37-38 are reserved for future use.
1000 * Value 39, 40, 42 are not supported on XL710 and X710.
1002 I40E_FILTER_PCTYPE_NONF_UNICAST_IPV6_UDP = 39,
1003 I40E_FILTER_PCTYPE_NONF_MULTICAST_IPV6_UDP = 40,
1004 I40E_FILTER_PCTYPE_NONF_IPV6_UDP = 41,
1005 I40E_FILTER_PCTYPE_NONF_IPV6_TCP_SYN_NO_ACK = 42,
1006 I40E_FILTER_PCTYPE_NONF_IPV6_TCP = 43,
1007 I40E_FILTER_PCTYPE_NONF_IPV6_SCTP = 44,
1008 I40E_FILTER_PCTYPE_NONF_IPV6_OTHER = 45,
1009 I40E_FILTER_PCTYPE_FRAG_IPV6 = 46,
1010 /* Note: Value 47 is reserved for future use */
1011 I40E_FILTER_PCTYPE_FCOE_OX = 48,
1012 I40E_FILTER_PCTYPE_FCOE_RX = 49,
1013 I40E_FILTER_PCTYPE_FCOE_OTHER = 50,
1014 /* Note: Values 51-62 are reserved for future use */
1015 I40E_FILTER_PCTYPE_L2_PAYLOAD = 63,
1018 enum i40e_filter_program_desc_dest {
1019 I40E_FILTER_PROGRAM_DESC_DEST_DROP_PACKET = 0x0,
1020 I40E_FILTER_PROGRAM_DESC_DEST_DIRECT_PACKET_QINDEX = 0x1,
1021 I40E_FILTER_PROGRAM_DESC_DEST_DIRECT_PACKET_OTHER = 0x2,
1024 enum i40e_filter_program_desc_fd_status {
1025 I40E_FILTER_PROGRAM_DESC_FD_STATUS_NONE = 0x0,
1026 I40E_FILTER_PROGRAM_DESC_FD_STATUS_FD_ID = 0x1,
1027 I40E_FILTER_PROGRAM_DESC_FD_STATUS_FD_ID_4FLEX_BYTES = 0x2,
1028 I40E_FILTER_PROGRAM_DESC_FD_STATUS_8FLEX_BYTES = 0x3,
1031 #define I40E_TXD_FLTR_QW0_DEST_VSI_SHIFT 23
1032 #define I40E_TXD_FLTR_QW0_DEST_VSI_MASK \
1033 BIT_ULL(I40E_TXD_FLTR_QW0_DEST_VSI_SHIFT)
1035 #define I40E_TXD_FLTR_QW1_CMD_SHIFT 4
1036 #define I40E_TXD_FLTR_QW1_CMD_MASK (0xFFFFULL << \
1037 I40E_TXD_FLTR_QW1_CMD_SHIFT)
1039 #define I40E_TXD_FLTR_QW1_PCMD_SHIFT (0x0ULL + I40E_TXD_FLTR_QW1_CMD_SHIFT)
1040 #define I40E_TXD_FLTR_QW1_PCMD_MASK (0x7ULL << I40E_TXD_FLTR_QW1_PCMD_SHIFT)
1042 enum i40e_filter_program_desc_pcmd {
1043 I40E_FILTER_PROGRAM_DESC_PCMD_ADD_UPDATE = 0x1,
1044 I40E_FILTER_PROGRAM_DESC_PCMD_REMOVE = 0x2,
1047 #define I40E_TXD_FLTR_QW1_DEST_SHIFT (0x3ULL + I40E_TXD_FLTR_QW1_CMD_SHIFT)
1048 #define I40E_TXD_FLTR_QW1_DEST_MASK (0x3ULL << I40E_TXD_FLTR_QW1_DEST_SHIFT)
1050 #define I40E_TXD_FLTR_QW1_CNT_ENA_SHIFT (0x7ULL + I40E_TXD_FLTR_QW1_CMD_SHIFT)
1051 #define I40E_TXD_FLTR_QW1_CNT_ENA_MASK BIT_ULL(I40E_TXD_FLTR_QW1_CNT_ENA_SHIFT)
1053 #define I40E_TXD_FLTR_QW1_FD_STATUS_SHIFT (0x9ULL + \
1054 I40E_TXD_FLTR_QW1_CMD_SHIFT)
1055 #define I40E_TXD_FLTR_QW1_FD_STATUS_MASK (0x3ULL << \
1056 I40E_TXD_FLTR_QW1_FD_STATUS_SHIFT)
1058 #define I40E_TXD_FLTR_QW1_CNTINDEX_SHIFT 20
1059 #define I40E_TXD_FLTR_QW1_CNTINDEX_MASK (0x1FFUL << \
1060 I40E_TXD_FLTR_QW1_CNTINDEX_SHIFT)
1062 enum i40e_filter_type {
1063 I40E_FLOW_DIRECTOR_FLTR = 0,
1064 I40E_PE_QUAD_HASH_FLTR = 1,
1065 I40E_ETHERTYPE_FLTR,
1071 struct i40e_vsi_context {
1076 u16 vsis_unallocated;
1081 struct i40e_aqc_vsi_properties_data info;
1084 struct i40e_veb_context {
1089 u16 vebs_unallocated;
1091 struct i40e_aqc_get_veb_parameters_completion info;
1094 /* Statistics collected by each port, VSI, VEB, and S-channel */
1095 struct i40e_eth_stats {
1096 u64 rx_bytes; /* gorc */
1097 u64 rx_unicast; /* uprc */
1098 u64 rx_multicast; /* mprc */
1099 u64 rx_broadcast; /* bprc */
1100 u64 rx_discards; /* rdpc */
1101 u64 rx_unknown_protocol; /* rupp */
1102 u64 tx_bytes; /* gotc */
1103 u64 tx_unicast; /* uptc */
1104 u64 tx_multicast; /* mptc */
1105 u64 tx_broadcast; /* bptc */
1106 u64 tx_discards; /* tdpc */
1107 u64 tx_errors; /* tepc */
1110 /* Statistics collected per VEB per TC */
1111 struct i40e_veb_tc_stats {
1112 u64 tc_rx_packets[I40E_MAX_TRAFFIC_CLASS];
1113 u64 tc_rx_bytes[I40E_MAX_TRAFFIC_CLASS];
1114 u64 tc_tx_packets[I40E_MAX_TRAFFIC_CLASS];
1115 u64 tc_tx_bytes[I40E_MAX_TRAFFIC_CLASS];
1118 /* Statistics collected by the MAC */
1119 struct i40e_hw_port_stats {
1120 /* eth stats collected by the port */
1121 struct i40e_eth_stats eth;
1123 /* additional port specific stats */
1124 u64 tx_dropped_link_down; /* tdold */
1125 u64 crc_errors; /* crcerrs */
1126 u64 illegal_bytes; /* illerrc */
1127 u64 error_bytes; /* errbc */
1128 u64 mac_local_faults; /* mlfc */
1129 u64 mac_remote_faults; /* mrfc */
1130 u64 rx_length_errors; /* rlec */
1131 u64 link_xon_rx; /* lxonrxc */
1132 u64 link_xoff_rx; /* lxoffrxc */
1133 u64 priority_xon_rx[8]; /* pxonrxc[8] */
1134 u64 priority_xoff_rx[8]; /* pxoffrxc[8] */
1135 u64 link_xon_tx; /* lxontxc */
1136 u64 link_xoff_tx; /* lxofftxc */
1137 u64 priority_xon_tx[8]; /* pxontxc[8] */
1138 u64 priority_xoff_tx[8]; /* pxofftxc[8] */
1139 u64 priority_xon_2_xoff[8]; /* pxon2offc[8] */
1140 u64 rx_size_64; /* prc64 */
1141 u64 rx_size_127; /* prc127 */
1142 u64 rx_size_255; /* prc255 */
1143 u64 rx_size_511; /* prc511 */
1144 u64 rx_size_1023; /* prc1023 */
1145 u64 rx_size_1522; /* prc1522 */
1146 u64 rx_size_big; /* prc9522 */
1147 u64 rx_undersize; /* ruc */
1148 u64 rx_fragments; /* rfc */
1149 u64 rx_oversize; /* roc */
1150 u64 rx_jabber; /* rjc */
1151 u64 tx_size_64; /* ptc64 */
1152 u64 tx_size_127; /* ptc127 */
1153 u64 tx_size_255; /* ptc255 */
1154 u64 tx_size_511; /* ptc511 */
1155 u64 tx_size_1023; /* ptc1023 */
1156 u64 tx_size_1522; /* ptc1522 */
1157 u64 tx_size_big; /* ptc9522 */
1158 u64 mac_short_packet_dropped; /* mspdc */
1159 u64 checksum_error; /* xec */
1160 /* flow director stats */
1163 u64 fd_atr_tunnel_match;
1169 u64 tx_lpi_count; /* etlpic */
1170 u64 rx_lpi_count; /* erlpic */
1173 /* Checksum and Shadow RAM pointers */
1174 #define I40E_SR_NVM_CONTROL_WORD 0x00
1175 #define I40E_SR_EMP_MODULE_PTR 0x0F
1176 #define I40E_SR_NVM_DEV_STARTER_VERSION 0x18
1177 #define I40E_SR_NVM_WAKE_ON_LAN 0x19
1178 #define I40E_SR_ALTERNATE_SAN_MAC_ADDRESS_PTR 0x27
1179 #define I40E_SR_NVM_EETRACK_LO 0x2D
1180 #define I40E_SR_NVM_EETRACK_HI 0x2E
1181 #define I40E_SR_VPD_PTR 0x2F
1182 #define I40E_SR_PCIE_ALT_AUTO_LOAD_PTR 0x3E
1183 #define I40E_SR_SW_CHECKSUM_WORD 0x3F
1185 /* Auxiliary field, mask and shift definition for Shadow RAM and NVM Flash */
1186 #define I40E_SR_VPD_MODULE_MAX_SIZE 1024
1187 #define I40E_SR_PCIE_ALT_MODULE_MAX_SIZE 1024
1188 #define I40E_SR_CONTROL_WORD_1_SHIFT 0x06
1189 #define I40E_SR_CONTROL_WORD_1_MASK (0x03 << I40E_SR_CONTROL_WORD_1_SHIFT)
1191 /* Shadow RAM related */
1192 #define I40E_SR_SECTOR_SIZE_IN_WORDS 0x800
1193 #define I40E_SR_WORDS_IN_1KB 512
1194 /* Checksum should be calculated such that after adding all the words,
1195 * including the checksum word itself, the sum should be 0xBABA.
1197 #define I40E_SR_SW_CHECKSUM_BASE 0xBABA
1199 #define I40E_SRRD_SRCTL_ATTEMPTS 100000
1201 enum i40e_switch_element_types {
1202 I40E_SWITCH_ELEMENT_TYPE_MAC = 1,
1203 I40E_SWITCH_ELEMENT_TYPE_PF = 2,
1204 I40E_SWITCH_ELEMENT_TYPE_VF = 3,
1205 I40E_SWITCH_ELEMENT_TYPE_EMP = 4,
1206 I40E_SWITCH_ELEMENT_TYPE_BMC = 6,
1207 I40E_SWITCH_ELEMENT_TYPE_PE = 16,
1208 I40E_SWITCH_ELEMENT_TYPE_VEB = 17,
1209 I40E_SWITCH_ELEMENT_TYPE_PA = 18,
1210 I40E_SWITCH_ELEMENT_TYPE_VSI = 19,
1213 /* Supported EtherType filters */
1214 enum i40e_ether_type_index {
1215 I40E_ETHER_TYPE_1588 = 0,
1216 I40E_ETHER_TYPE_FIP = 1,
1217 I40E_ETHER_TYPE_OUI_EXTENDED = 2,
1218 I40E_ETHER_TYPE_MAC_CONTROL = 3,
1219 I40E_ETHER_TYPE_LLDP = 4,
1220 I40E_ETHER_TYPE_EVB_PROTOCOL1 = 5,
1221 I40E_ETHER_TYPE_EVB_PROTOCOL2 = 6,
1222 I40E_ETHER_TYPE_QCN_CNM = 7,
1223 I40E_ETHER_TYPE_8021X = 8,
1224 I40E_ETHER_TYPE_ARP = 9,
1225 I40E_ETHER_TYPE_RSV1 = 10,
1226 I40E_ETHER_TYPE_RSV2 = 11,
1229 /* Filter context base size is 1K */
1230 #define I40E_HASH_FILTER_BASE_SIZE 1024
1231 /* Supported Hash filter values */
1232 enum i40e_hash_filter_size {
1233 I40E_HASH_FILTER_SIZE_1K = 0,
1234 I40E_HASH_FILTER_SIZE_2K = 1,
1235 I40E_HASH_FILTER_SIZE_4K = 2,
1236 I40E_HASH_FILTER_SIZE_8K = 3,
1237 I40E_HASH_FILTER_SIZE_16K = 4,
1238 I40E_HASH_FILTER_SIZE_32K = 5,
1239 I40E_HASH_FILTER_SIZE_64K = 6,
1240 I40E_HASH_FILTER_SIZE_128K = 7,
1241 I40E_HASH_FILTER_SIZE_256K = 8,
1242 I40E_HASH_FILTER_SIZE_512K = 9,
1243 I40E_HASH_FILTER_SIZE_1M = 10,
1246 /* DMA context base size is 0.5K */
1247 #define I40E_DMA_CNTX_BASE_SIZE 512
1248 /* Supported DMA context values */
1249 enum i40e_dma_cntx_size {
1250 I40E_DMA_CNTX_SIZE_512 = 0,
1251 I40E_DMA_CNTX_SIZE_1K = 1,
1252 I40E_DMA_CNTX_SIZE_2K = 2,
1253 I40E_DMA_CNTX_SIZE_4K = 3,
1254 I40E_DMA_CNTX_SIZE_8K = 4,
1255 I40E_DMA_CNTX_SIZE_16K = 5,
1256 I40E_DMA_CNTX_SIZE_32K = 6,
1257 I40E_DMA_CNTX_SIZE_64K = 7,
1258 I40E_DMA_CNTX_SIZE_128K = 8,
1259 I40E_DMA_CNTX_SIZE_256K = 9,
1262 /* Supported Hash look up table (LUT) sizes */
1263 enum i40e_hash_lut_size {
1264 I40E_HASH_LUT_SIZE_128 = 0,
1265 I40E_HASH_LUT_SIZE_512 = 1,
1268 /* Structure to hold a per PF filter control settings */
1269 struct i40e_filter_control_settings {
1270 /* number of PE Quad Hash filter buckets */
1271 enum i40e_hash_filter_size pe_filt_num;
1272 /* number of PE Quad Hash contexts */
1273 enum i40e_dma_cntx_size pe_cntx_num;
1274 /* number of FCoE filter buckets */
1275 enum i40e_hash_filter_size fcoe_filt_num;
1276 /* number of FCoE DDP contexts */
1277 enum i40e_dma_cntx_size fcoe_cntx_num;
1278 /* size of the Hash LUT */
1279 enum i40e_hash_lut_size hash_lut_size;
1280 /* enable FDIR filters for PF and its VFs */
1282 /* enable Ethertype filters for PF and its VFs */
1283 bool enable_ethtype;
1284 /* enable MAC/VLAN filters for PF and its VFs */
1285 bool enable_macvlan;
1288 /* Structure to hold device level control filter counts */
1289 struct i40e_control_filter_stats {
1290 u16 mac_etype_used; /* Used perfect match MAC/EtherType filters */
1291 u16 etype_used; /* Used perfect EtherType filters */
1292 u16 mac_etype_free; /* Un-used perfect match MAC/EtherType filters */
1293 u16 etype_free; /* Un-used perfect EtherType filters */
1296 enum i40e_reset_type {
1298 I40E_RESET_CORER = 1,
1299 I40E_RESET_GLOBR = 2,
1300 I40E_RESET_EMPR = 3,
1303 /* RSS Hash Table Size */
1304 #define I40E_PFQF_CTL_0_HASHLUTSIZE_512 0x00010000
1305 #endif /* _I40E_TYPE_H_ */