drivers/net/ethernet/intel/igb/igb_main.c

   1 /*******************************************************************************
   2
   3   Intel(R) Gigabit Ethernet Linux driver
   4   Copyright(c) 2007-2013 Intel Corporation.
   5
   6   This program is free software; you can redistribute it and/or modify it
   7   under the terms and conditions of the GNU General Public License,
   8   version 2, as published by the Free Software Foundation.
   9
  10   This program is distributed in the hope it will be useful, but WITHOUT
  11   ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  12   FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
  13   more details.
  14
  15   You should have received a copy of the GNU General Public License along with
  16   this program; if not, write to the Free Software Foundation, Inc.,
  17   51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
  18
  19   The full GNU General Public License is included in this distribution in
  20   the file called "COPYING".
  21
  22   Contact Information:
  23   e1000-devel Mailing List <e1000-devel@lists.sourceforge.net>
  24   Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
  25
  26 *******************************************************************************/
  27
  28 #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
  29
  30 #include <linux/module.h>
  31 #include <linux/types.h>
  32 #include <linux/init.h>
  33 #include <linux/bitops.h>
  34 #include <linux/vmalloc.h>
  35 #include <linux/pagemap.h>
  36 #include <linux/netdevice.h>
  37 #include <linux/ipv6.h>
  38 #include <linux/slab.h>
  39 #include <net/checksum.h>
  40 #include <net/ip6_checksum.h>
  41 #include <linux/net_tstamp.h>
  42 #include <linux/mii.h>
  43 #include <linux/ethtool.h>
  44 #include <linux/if.h>
  45 #include <linux/if_vlan.h>
  46 #include <linux/pci.h>
  47 #include <linux/pci-aspm.h>
  48 #include <linux/delay.h>
  49 #include <linux/interrupt.h>
  50 #include <linux/ip.h>
  51 #include <linux/tcp.h>
  52 #include <linux/sctp.h>
  53 #include <linux/if_ether.h>
  54 #include <linux/aer.h>
  55 #include <linux/prefetch.h>
  56 #include <linux/pm_runtime.h>
  57 #ifdef CONFIG_IGB_DCA
  58 #include <linux/dca.h>
  59 #endif
  60 #include <linux/i2c.h>
  61 #include "igb.h"
  62
  63 #define MAJ 5
  64 #define MIN 0
  65 #define BUILD 3
  66 #define DRV_VERSION __stringify(MAJ) "." __stringify(MIN) "." \
  67 __stringify(BUILD) "-k"
  68 char igb_driver_name[] = "igb";
  69 char igb_driver_version[] = DRV_VERSION;
  70 static const char igb_driver_string[] =
  71                                 "Intel(R) Gigabit Ethernet Network Driver";
  72 static const char igb_copyright[] =
  73                                 "Copyright (c) 2007-2013 Intel Corporation.";
  74
  75 static const struct e1000_info *igb_info_tbl[] = {
  76         [board_82575] = &e1000_82575_info,
  77 };
  78
  79 static DEFINE_PCI_DEVICE_TABLE(igb_pci_tbl) = {
  80         { PCI_VDEVICE(INTEL, E1000_DEV_ID_I354_BACKPLANE_1GBPS) },
  81         { PCI_VDEVICE(INTEL, E1000_DEV_ID_I354_SGMII) },
  82         { PCI_VDEVICE(INTEL, E1000_DEV_ID_I354_BACKPLANE_2_5GBPS) },
  83         { PCI_VDEVICE(INTEL, E1000_DEV_ID_I211_COPPER), board_82575 },
  84         { PCI_VDEVICE(INTEL, E1000_DEV_ID_I210_COPPER), board_82575 },
  85         { PCI_VDEVICE(INTEL, E1000_DEV_ID_I210_FIBER), board_82575 },
  86         { PCI_VDEVICE(INTEL, E1000_DEV_ID_I210_SERDES), board_82575 },
  87         { PCI_VDEVICE(INTEL, E1000_DEV_ID_I210_SGMII), board_82575 },
  88         { PCI_VDEVICE(INTEL, E1000_DEV_ID_I210_COPPER_FLASHLESS), board_82575 },
  89         { PCI_VDEVICE(INTEL, E1000_DEV_ID_I210_SERDES_FLASHLESS), board_82575 },
  90         { PCI_VDEVICE(INTEL, E1000_DEV_ID_I350_COPPER), board_82575 },
  91         { PCI_VDEVICE(INTEL, E1000_DEV_ID_I350_FIBER), board_82575 },
  92         { PCI_VDEVICE(INTEL, E1000_DEV_ID_I350_SERDES), board_82575 },
  93         { PCI_VDEVICE(INTEL, E1000_DEV_ID_I350_SGMII), board_82575 },
  94         { PCI_VDEVICE(INTEL, E1000_DEV_ID_82580_COPPER), board_82575 },
  95         { PCI_VDEVICE(INTEL, E1000_DEV_ID_82580_FIBER), board_82575 },
  96         { PCI_VDEVICE(INTEL, E1000_DEV_ID_82580_QUAD_FIBER), board_82575 },
  97         { PCI_VDEVICE(INTEL, E1000_DEV_ID_82580_SERDES), board_82575 },
  98         { PCI_VDEVICE(INTEL, E1000_DEV_ID_82580_SGMII), board_82575 },
  99         { PCI_VDEVICE(INTEL, E1000_DEV_ID_82580_COPPER_DUAL), board_82575 },
 100         { PCI_VDEVICE(INTEL, E1000_DEV_ID_DH89XXCC_SGMII), board_82575 },
 101         { PCI_VDEVICE(INTEL, E1000_DEV_ID_DH89XXCC_SERDES), board_82575 },
 102         { PCI_VDEVICE(INTEL, E1000_DEV_ID_DH89XXCC_BACKPLANE), board_82575 },
 103         { PCI_VDEVICE(INTEL, E1000_DEV_ID_DH89XXCC_SFP), board_82575 },
 104         { PCI_VDEVICE(INTEL, E1000_DEV_ID_82576), board_82575 },
 105         { PCI_VDEVICE(INTEL, E1000_DEV_ID_82576_NS), board_82575 },
 106         { PCI_VDEVICE(INTEL, E1000_DEV_ID_82576_NS_SERDES), board_82575 },
 107         { PCI_VDEVICE(INTEL, E1000_DEV_ID_82576_FIBER), board_82575 },
 108         { PCI_VDEVICE(INTEL, E1000_DEV_ID_82576_SERDES), board_82575 },
 109         { PCI_VDEVICE(INTEL, E1000_DEV_ID_82576_SERDES_QUAD), board_82575 },
 110         { PCI_VDEVICE(INTEL, E1000_DEV_ID_82576_QUAD_COPPER_ET2), board_82575 },
 111         { PCI_VDEVICE(INTEL, E1000_DEV_ID_82576_QUAD_COPPER), board_82575 },
 112         { PCI_VDEVICE(INTEL, E1000_DEV_ID_82575EB_COPPER), board_82575 },
 113         { PCI_VDEVICE(INTEL, E1000_DEV_ID_82575EB_FIBER_SERDES), board_82575 },
 114         { PCI_VDEVICE(INTEL, E1000_DEV_ID_82575GB_QUAD_COPPER), board_82575 },
 115         /* required last entry */
 116         {0, }
 117 };
 118
 119 MODULE_DEVICE_TABLE(pci, igb_pci_tbl);
 120
 121 void igb_reset(struct igb_adapter *);
 122 static int igb_setup_all_tx_resources(struct igb_adapter *);
 123 static int igb_setup_all_rx_resources(struct igb_adapter *);
 124 static void igb_free_all_tx_resources(struct igb_adapter *);
 125 static void igb_free_all_rx_resources(struct igb_adapter *);
 126 static void igb_setup_mrqc(struct igb_adapter *);
 127 static int igb_probe(struct pci_dev *, const struct pci_device_id *);
 128 static void igb_remove(struct pci_dev *pdev);
 129 static int igb_sw_init(struct igb_adapter *);
 130 static int igb_open(struct net_device *);
 131 static int igb_close(struct net_device *);
 132 static void igb_configure(struct igb_adapter *);
 133 static void igb_configure_tx(struct igb_adapter *);
 134 static void igb_configure_rx(struct igb_adapter *);
 135 static void igb_clean_all_tx_rings(struct igb_adapter *);
 136 static void igb_clean_all_rx_rings(struct igb_adapter *);
 137 static void igb_clean_tx_ring(struct igb_ring *);
 138 static void igb_clean_rx_ring(struct igb_ring *);
 139 static void igb_set_rx_mode(struct net_device *);
 140 static void igb_update_phy_info(unsigned long);
 141 static void igb_watchdog(unsigned long);
 142 static void igb_watchdog_task(struct work_struct *);
 143 static netdev_tx_t igb_xmit_frame(struct sk_buff *skb, struct net_device *);
 144 static struct rtnl_link_stats64 *igb_get_stats64(struct net_device *dev,
 145                                                  struct rtnl_link_stats64 *stats);
 146 static int igb_change_mtu(struct net_device *, int);
 147 static int igb_set_mac(struct net_device *, void *);
 148 static void igb_set_uta(struct igb_adapter *adapter);
 149 static irqreturn_t igb_intr(int irq, void *);
 150 static irqreturn_t igb_intr_msi(int irq, void *);
 151 static irqreturn_t igb_msix_other(int irq, void *);
 152 static irqreturn_t igb_msix_ring(int irq, void *);
 153 #ifdef CONFIG_IGB_DCA
 154 static void igb_update_dca(struct igb_q_vector *);
 155 static void igb_setup_dca(struct igb_adapter *);
 156 #endif /* CONFIG_IGB_DCA */
 157 static int igb_poll(struct napi_struct *, int);
 158 static bool igb_clean_tx_irq(struct igb_q_vector *);
 159 static bool igb_clean_rx_irq(struct igb_q_vector *, int);
 160 static int igb_ioctl(struct net_device *, struct ifreq *, int cmd);
 161 static void igb_tx_timeout(struct net_device *);
 162 static void igb_reset_task(struct work_struct *);
 163 static void igb_vlan_mode(struct net_device *netdev, netdev_features_t features);
 164 static int igb_vlan_rx_add_vid(struct net_device *, __be16, u16);
 165 static int igb_vlan_rx_kill_vid(struct net_device *, __be16, u16);
 166 static void igb_restore_vlan(struct igb_adapter *);
 167 static void igb_rar_set_qsel(struct igb_adapter *, u8 *, u32 , u8);
 168 static void igb_ping_all_vfs(struct igb_adapter *);
 169 static void igb_msg_task(struct igb_adapter *);
 170 static void igb_vmm_control(struct igb_adapter *);
 171 static int igb_set_vf_mac(struct igb_adapter *, int, unsigned char *);
 172 static void igb_restore_vf_multicasts(struct igb_adapter *adapter);
 173 static int igb_ndo_set_vf_mac(struct net_device *netdev, int vf, u8 *mac);
 174 static int igb_ndo_set_vf_vlan(struct net_device *netdev,
 175                                int vf, u16 vlan, u8 qos);
 176 static int igb_ndo_set_vf_bw(struct net_device *netdev, int vf, int tx_rate);
 177 static int igb_ndo_set_vf_spoofchk(struct net_device *netdev, int vf,
 178                                    bool setting);
 179 static int igb_ndo_get_vf_config(struct net_device *netdev, int vf,
 180                                  struct ifla_vf_info *ivi);
 181 static void igb_check_vf_rate_limit(struct igb_adapter *);
 182
 183 #ifdef CONFIG_PCI_IOV
 184 static int igb_vf_configure(struct igb_adapter *adapter, int vf);
 185 #endif
 186
 187 #ifdef CONFIG_PM
 188 #ifdef CONFIG_PM_SLEEP
 189 static int igb_suspend(struct device *);
 190 #endif
 191 static int igb_resume(struct device *);
 192 #ifdef CONFIG_PM_RUNTIME
 193 static int igb_runtime_suspend(struct device *dev);
 194 static int igb_runtime_resume(struct device *dev);
 195 static int igb_runtime_idle(struct device *dev);
 196 #endif
 197 static const struct dev_pm_ops igb_pm_ops = {
 198         SET_SYSTEM_SLEEP_PM_OPS(igb_suspend, igb_resume)
 199         SET_RUNTIME_PM_OPS(igb_runtime_suspend, igb_runtime_resume,
 200                         igb_runtime_idle)
 201 };
 202 #endif
 203 static void igb_shutdown(struct pci_dev *);
 204 static int igb_pci_sriov_configure(struct pci_dev *dev, int num_vfs);
 205 #ifdef CONFIG_IGB_DCA
 206 static int igb_notify_dca(struct notifier_block *, unsigned long, void *);
 207 static struct notifier_block dca_notifier = {
 208         .notifier_call  = igb_notify_dca,
 209         .next           = NULL,
 210         .priority       = 0
 211 };
 212 #endif
 213 #ifdef CONFIG_NET_POLL_CONTROLLER
 214 /* for netdump / net console */
 215 static void igb_netpoll(struct net_device *);
 216 #endif
 217 #ifdef CONFIG_PCI_IOV
 218 static unsigned int max_vfs = 0;
 219 module_param(max_vfs, uint, 0);
 220 MODULE_PARM_DESC(max_vfs, "Maximum number of virtual functions to allocate "
 221                  "per physical function");
 222 #endif /* CONFIG_PCI_IOV */
 223
 224 static pci_ers_result_t igb_io_error_detected(struct pci_dev *,
 225                      pci_channel_state_t);
 226 static pci_ers_result_t igb_io_slot_reset(struct pci_dev *);
 227 static void igb_io_resume(struct pci_dev *);
 228
 229 static const struct pci_error_handlers igb_err_handler = {
 230         .error_detected = igb_io_error_detected,
 231         .slot_reset = igb_io_slot_reset,
 232         .resume = igb_io_resume,
 233 };
 234
 235 static void igb_init_dmac(struct igb_adapter *adapter, u32 pba);
 236
 237 static struct pci_driver igb_driver = {
 238         .name     = igb_driver_name,
 239         .id_table = igb_pci_tbl,
 240         .probe    = igb_probe,
 241         .remove   = igb_remove,
 242 #ifdef CONFIG_PM
 243         .driver.pm = &igb_pm_ops,
 244 #endif
 245         .shutdown = igb_shutdown,
 246         .sriov_configure = igb_pci_sriov_configure,
 247         .err_handler = &igb_err_handler
 248 };
 249
 250 MODULE_AUTHOR("Intel Corporation, <e1000-devel@lists.sourceforge.net>");
 251 MODULE_DESCRIPTION("Intel(R) Gigabit Ethernet Network Driver");
 252 MODULE_LICENSE("GPL");
 253 MODULE_VERSION(DRV_VERSION);
 254
 255 #define DEFAULT_MSG_ENABLE (NETIF_MSG_DRV|NETIF_MSG_PROBE|NETIF_MSG_LINK)
 256 static int debug = -1;
 257 module_param(debug, int, 0);
 258 MODULE_PARM_DESC(debug, "Debug level (0=none,...,16=all)");
 259
 260 struct igb_reg_info {
 261         u32 ofs;
 262         char *name;
 263 };
 264
 265 static const struct igb_reg_info igb_reg_info_tbl[] = {
 266
 267         /* General Registers */
 268         {E1000_CTRL, "CTRL"},
 269         {E1000_STATUS, "STATUS"},
 270         {E1000_CTRL_EXT, "CTRL_EXT"},
 271
 272         /* Interrupt Registers */
 273         {E1000_ICR, "ICR"},
 274
 275         /* RX Registers */
 276         {E1000_RCTL, "RCTL"},
 277         {E1000_RDLEN(0), "RDLEN"},
 278         {E1000_RDH(0), "RDH"},
 279         {E1000_RDT(0), "RDT"},
 280         {E1000_RXDCTL(0), "RXDCTL"},
 281         {E1000_RDBAL(0), "RDBAL"},
 282         {E1000_RDBAH(0), "RDBAH"},
 283
 284         /* TX Registers */
 285         {E1000_TCTL, "TCTL"},
 286         {E1000_TDBAL(0), "TDBAL"},
 287         {E1000_TDBAH(0), "TDBAH"},
 288         {E1000_TDLEN(0), "TDLEN"},
 289         {E1000_TDH(0), "TDH"},
 290         {E1000_TDT(0), "TDT"},
 291         {E1000_TXDCTL(0), "TXDCTL"},
 292         {E1000_TDFH, "TDFH"},
 293         {E1000_TDFT, "TDFT"},
 294         {E1000_TDFHS, "TDFHS"},
 295         {E1000_TDFPC, "TDFPC"},
 296
 297         /* List Terminator */
 298         {}
 299 };
 300
 301 /* igb_regdump - register printout routine */
 302 static void igb_regdump(struct e1000_hw *hw, struct igb_reg_info *reginfo)
 303 {
 304         int n = 0;
 305         char rname[16];
 306         u32 regs[8];
 307
 308         switch (reginfo->ofs) {
 309         case E1000_RDLEN(0):
 310                 for (n = 0; n < 4; n++)
 311                         regs[n] = rd32(E1000_RDLEN(n));
 312                 break;
 313         case E1000_RDH(0):
 314                 for (n = 0; n < 4; n++)
 315                         regs[n] = rd32(E1000_RDH(n));
 316                 break;
 317         case E1000_RDT(0):
 318                 for (n = 0; n < 4; n++)
 319                         regs[n] = rd32(E1000_RDT(n));
 320                 break;
 321         case E1000_RXDCTL(0):
 322                 for (n = 0; n < 4; n++)
 323                         regs[n] = rd32(E1000_RXDCTL(n));
 324                 break;
 325         case E1000_RDBAL(0):
 326                 for (n = 0; n < 4; n++)
 327                         regs[n] = rd32(E1000_RDBAL(n));
 328                 break;
 329         case E1000_RDBAH(0):
 330                 for (n = 0; n < 4; n++)
 331                         regs[n] = rd32(E1000_RDBAH(n));
 332                 break;
 333         case E1000_TDBAL(0):
 334                 for (n = 0; n < 4; n++)
 335                         regs[n] = rd32(E1000_RDBAL(n));
 336                 break;
 337         case E1000_TDBAH(0):
 338                 for (n = 0; n < 4; n++)
 339                         regs[n] = rd32(E1000_TDBAH(n));
 340                 break;
 341         case E1000_TDLEN(0):
 342                 for (n = 0; n < 4; n++)
 343                         regs[n] = rd32(E1000_TDLEN(n));
 344                 break;
 345         case E1000_TDH(0):
 346                 for (n = 0; n < 4; n++)
 347                         regs[n] = rd32(E1000_TDH(n));
 348                 break;
 349         case E1000_TDT(0):
 350                 for (n = 0; n < 4; n++)
 351                         regs[n] = rd32(E1000_TDT(n));
 352                 break;
 353         case E1000_TXDCTL(0):
 354                 for (n = 0; n < 4; n++)
 355                         regs[n] = rd32(E1000_TXDCTL(n));
 356                 break;
 357         default:
 358                 pr_info("%-15s %08x\n", reginfo->name, rd32(reginfo->ofs));
 359                 return;
 360         }
 361
 362         snprintf(rname, 16, "%s%s", reginfo->name, "[0-3]");
 363         pr_info("%-15s %08x %08x %08x %08x\n", rname, regs[0], regs[1],
 364                 regs[2], regs[3]);
 365 }
 366
 367 /* igb_dump - Print registers, Tx-rings and Rx-rings */
 368 static void igb_dump(struct igb_adapter *adapter)
 369 {
 370         struct net_device *netdev = adapter->netdev;
 371         struct e1000_hw *hw = &adapter->hw;
 372         struct igb_reg_info *reginfo;
 373         struct igb_ring *tx_ring;
 374         union e1000_adv_tx_desc *tx_desc;
 375         struct my_u0 { u64 a; u64 b; } *u0;
 376         struct igb_ring *rx_ring;
 377         union e1000_adv_rx_desc *rx_desc;
 378         u32 staterr;
 379         u16 i, n;
 380
 381         if (!netif_msg_hw(adapter))
 382                 return;
 383
 384         /* Print netdevice Info */
 385         if (netdev) {
 386                 dev_info(&adapter->pdev->dev, "Net device Info\n");
 387                 pr_info("Device Name     state            trans_start      "
 388                         "last_rx\n");
 389                 pr_info("%-15s %016lX %016lX %016lX\n", netdev->name,
 390                         netdev->state, netdev->trans_start, netdev->last_rx);
 391         }
 392
 393         /* Print Registers */
 394         dev_info(&adapter->pdev->dev, "Register Dump\n");
 395         pr_info(" Register Name   Value\n");
 396         for (reginfo = (struct igb_reg_info *)igb_reg_info_tbl;
 397              reginfo->name; reginfo++) {
 398                 igb_regdump(hw, reginfo);
 399         }
 400
 401         /* Print TX Ring Summary */
 402         if (!netdev || !netif_running(netdev))
 403                 goto exit;
 404
 405         dev_info(&adapter->pdev->dev, "TX Rings Summary\n");
 406         pr_info("Queue [NTU] [NTC] [bi(ntc)->dma  ] leng ntw timestamp\n");
 407         for (n = 0; n < adapter->num_tx_queues; n++) {
 408                 struct igb_tx_buffer *buffer_info;
 409                 tx_ring = adapter->tx_ring[n];
 410                 buffer_info = &tx_ring->tx_buffer_info[tx_ring->next_to_clean];
 411                 pr_info(" %5d %5X %5X %016llX %04X %p %016llX\n",
 412                         n, tx_ring->next_to_use, tx_ring->next_to_clean,
 413                         (u64)dma_unmap_addr(buffer_info, dma),
 414                         dma_unmap_len(buffer_info, len),
 415                         buffer_info->next_to_watch,
 416                         (u64)buffer_info->time_stamp);
 417         }
 418
 419         /* Print TX Rings */
 420         if (!netif_msg_tx_done(adapter))
 421                 goto rx_ring_summary;
 422
 423         dev_info(&adapter->pdev->dev, "TX Rings Dump\n");
 424
 425         /* Transmit Descriptor Formats
 426          *
 427          * Advanced Transmit Descriptor
 428          *   +--------------------------------------------------------------+
 429          * 0 |         Buffer Address [63:0]                                |
 430          *   +--------------------------------------------------------------+
 431          * 8 | PAYLEN  | PORTS  |CC|IDX | STA | DCMD  |DTYP|MAC|RSV| DTALEN |
 432          *   +--------------------------------------------------------------+
 433          *   63      46 45    40 39 38 36 35 32 31   24             15       0
 434          */
 435
 436         for (n = 0; n < adapter->num_tx_queues; n++) {
 437                 tx_ring = adapter->tx_ring[n];
 438                 pr_info("------------------------------------\n");
 439                 pr_info("TX QUEUE INDEX = %d\n", tx_ring->queue_index);
 440                 pr_info("------------------------------------\n");
 441                 pr_info("T [desc]     [address 63:0  ] [PlPOCIStDDM Ln] "
 442                         "[bi->dma       ] leng  ntw timestamp        "
 443                         "bi->skb\n");
 444
 445                 for (i = 0; tx_ring->desc && (i < tx_ring->count); i++) {
 446                         const char *next_desc;
 447                         struct igb_tx_buffer *buffer_info;
 448                         tx_desc = IGB_TX_DESC(tx_ring, i);
 449                         buffer_info = &tx_ring->tx_buffer_info[i];
 450                         u0 = (struct my_u0 *)tx_desc;
 451                         if (i == tx_ring->next_to_use &&
 452                             i == tx_ring->next_to_clean)
 453                                 next_desc = " NTC/U";
 454                         else if (i == tx_ring->next_to_use)
 455                                 next_desc = " NTU";
 456                         else if (i == tx_ring->next_to_clean)
 457                                 next_desc = " NTC";
 458                         else
 459                                 next_desc = "";
 460
 461                         pr_info("T [0x%03X]    %016llX %016llX %016llX"
 462                                 " %04X  %p %016llX %p%s\n", i,
 463                                 le64_to_cpu(u0->a),
 464                                 le64_to_cpu(u0->b),
 465                                 (u64)dma_unmap_addr(buffer_info, dma),
 466                                 dma_unmap_len(buffer_info, len),
 467                                 buffer_info->next_to_watch,
 468                                 (u64)buffer_info->time_stamp,
 469                                 buffer_info->skb, next_desc);
 470
 471                         if (netif_msg_pktdata(adapter) && buffer_info->skb)
 472                                 print_hex_dump(KERN_INFO, "",
 473                                         DUMP_PREFIX_ADDRESS,
 474                                         16, 1, buffer_info->skb->data,
 475                                         dma_unmap_len(buffer_info, len),
 476                                         true);
 477                 }
 478         }
 479
 480         /* Print RX Rings Summary */
 481 rx_ring_summary:
 482         dev_info(&adapter->pdev->dev, "RX Rings Summary\n");
 483         pr_info("Queue [NTU] [NTC]\n");
 484         for (n = 0; n < adapter->num_rx_queues; n++) {
 485                 rx_ring = adapter->rx_ring[n];
 486                 pr_info(" %5d %5X %5X\n",
 487                         n, rx_ring->next_to_use, rx_ring->next_to_clean);
 488         }
 489
 490         /* Print RX Rings */
 491         if (!netif_msg_rx_status(adapter))
 492                 goto exit;
 493
 494         dev_info(&adapter->pdev->dev, "RX Rings Dump\n");
 495
 496         /* Advanced Receive Descriptor (Read) Format
 497          *    63                                           1        0
 498          *    +-----------------------------------------------------+
 499          *  0 |       Packet Buffer Address [63:1]           |A0/NSE|
 500          *    +----------------------------------------------+------+
 501          *  8 |       Header Buffer Address [63:1]           |  DD  |
 502          *    +-----------------------------------------------------+
 503          *
 504          *
 505          * Advanced Receive Descriptor (Write-Back) Format
 506          *
 507          *   63       48 47    32 31  30      21 20 17 16   4 3     0
 508          *   +------------------------------------------------------+
 509          * 0 | Packet     IP     |SPH| HDR_LEN   | RSV|Packet|  RSS |
 510          *   | Checksum   Ident  |   |           |    | Type | Type |
 511          *   +------------------------------------------------------+
 512          * 8 | VLAN Tag | Length | Extended Error | Extended Status |
 513          *   +------------------------------------------------------+
 514          *   63       48 47    32 31            20 19               0
 515          */
 516
 517         for (n = 0; n < adapter->num_rx_queues; n++) {
 518                 rx_ring = adapter->rx_ring[n];
 519                 pr_info("------------------------------------\n");
 520                 pr_info("RX QUEUE INDEX = %d\n", rx_ring->queue_index);
 521                 pr_info("------------------------------------\n");
 522                 pr_info("R  [desc]      [ PktBuf     A0] [  HeadBuf   DD] "
 523                         "[bi->dma       ] [bi->skb] <-- Adv Rx Read format\n");
 524                 pr_info("RWB[desc]      [PcsmIpSHl PtRs] [vl er S cks ln] -----"
 525                         "----------- [bi->skb] <-- Adv Rx Write-Back format\n");
 526
 527                 for (i = 0; i < rx_ring->count; i++) {
 528                         const char *next_desc;
 529                         struct igb_rx_buffer *buffer_info;
 530                         buffer_info = &rx_ring->rx_buffer_info[i];
 531                         rx_desc = IGB_RX_DESC(rx_ring, i);
 532                         u0 = (struct my_u0 *)rx_desc;
 533                         staterr = le32_to_cpu(rx_desc->wb.upper.status_error);
 534
 535                         if (i == rx_ring->next_to_use)
 536                                 next_desc = " NTU";
 537                         else if (i == rx_ring->next_to_clean)
 538                                 next_desc = " NTC";
 539                         else
 540                                 next_desc = "";
 541
 542                         if (staterr & E1000_RXD_STAT_DD) {
 543                                 /* Descriptor Done */
 544                                 pr_info("%s[0x%03X]     %016llX %016llX ---------------- %s\n",
 545                                         "RWB", i,
 546                                         le64_to_cpu(u0->a),
 547                                         le64_to_cpu(u0->b),
 548                                         next_desc);
 549                         } else {
 550                                 pr_info("%s[0x%03X]     %016llX %016llX %016llX %s\n",
 551                                         "R  ", i,
 552                                         le64_to_cpu(u0->a),
 553                                         le64_to_cpu(u0->b),
 554                                         (u64)buffer_info->dma,
 555                                         next_desc);
 556
 557                                 if (netif_msg_pktdata(adapter) &&
 558                                     buffer_info->dma && buffer_info->page) {
 559                                         print_hex_dump(KERN_INFO, "",
 560                                           DUMP_PREFIX_ADDRESS,
 561                                           16, 1,
 562                                           page_address(buffer_info->page) +
 563                                                       buffer_info->page_offset,
 564                                           IGB_RX_BUFSZ, true);
 565                                 }
 566                         }
 567                 }
 568         }
 569
 570 exit:
 571         return;
 572 }
 573
 574 /**
 575  *  igb_get_i2c_data - Reads the I2C SDA data bit
 576  *  @hw: pointer to hardware structure
 577  *  @i2cctl: Current value of I2CCTL register
 578  *
 579  *  Returns the I2C data bit value
 580  **/
 581 static int igb_get_i2c_data(void *data)
 582 {
 583         struct igb_adapter *adapter = (struct igb_adapter *)data;
 584         struct e1000_hw *hw = &adapter->hw;
 585         s32 i2cctl = rd32(E1000_I2CPARAMS);
 586
 587         return ((i2cctl & E1000_I2C_DATA_IN) != 0);
 588 }
 589
 590 /**
 591  *  igb_set_i2c_data - Sets the I2C data bit
 592  *  @data: pointer to hardware structure
 593  *  @state: I2C data value (0 or 1) to set
 594  *
 595  *  Sets the I2C data bit
 596  **/
 597 static void igb_set_i2c_data(void *data, int state)
 598 {
 599         struct igb_adapter *adapter = (struct igb_adapter *)data;
 600         struct e1000_hw *hw = &adapter->hw;
 601         s32 i2cctl = rd32(E1000_I2CPARAMS);
 602
 603         if (state)
 604                 i2cctl |= E1000_I2C_DATA_OUT;
 605         else
 606                 i2cctl &= ~E1000_I2C_DATA_OUT;
 607
 608         i2cctl &= ~E1000_I2C_DATA_OE_N;
 609         i2cctl |= E1000_I2C_CLK_OE_N;
 610         wr32(E1000_I2CPARAMS, i2cctl);
 611         wrfl();
 612
 613 }
 614
 615 /**
 616  *  igb_set_i2c_clk - Sets the I2C SCL clock
 617  *  @data: pointer to hardware structure
 618  *  @state: state to set clock
 619  *
 620  *  Sets the I2C clock line to state
 621  **/
 622 static void igb_set_i2c_clk(void *data, int state)
 623 {
 624         struct igb_adapter *adapter = (struct igb_adapter *)data;
 625         struct e1000_hw *hw = &adapter->hw;
 626         s32 i2cctl = rd32(E1000_I2CPARAMS);
 627
 628         if (state) {
 629                 i2cctl |= E1000_I2C_CLK_OUT;
 630                 i2cctl &= ~E1000_I2C_CLK_OE_N;
 631         } else {
 632                 i2cctl &= ~E1000_I2C_CLK_OUT;
 633                 i2cctl &= ~E1000_I2C_CLK_OE_N;
 634         }
 635         wr32(E1000_I2CPARAMS, i2cctl);
 636         wrfl();
 637 }
 638
 639 /**
 640  *  igb_get_i2c_clk - Gets the I2C SCL clock state
 641  *  @data: pointer to hardware structure
 642  *
 643  *  Gets the I2C clock state
 644  **/
 645 static int igb_get_i2c_clk(void *data)
 646 {
 647         struct igb_adapter *adapter = (struct igb_adapter *)data;
 648         struct e1000_hw *hw = &adapter->hw;
 649         s32 i2cctl = rd32(E1000_I2CPARAMS);
 650
 651         return ((i2cctl & E1000_I2C_CLK_IN) != 0);
 652 }
 653
 654 static const struct i2c_algo_bit_data igb_i2c_algo = {
 655         .setsda         = igb_set_i2c_data,
 656         .setscl         = igb_set_i2c_clk,
 657         .getsda         = igb_get_i2c_data,
 658         .getscl         = igb_get_i2c_clk,
 659         .udelay         = 5,
 660         .timeout        = 20,
 661 };
 662
 663 /**
 664  *  igb_get_hw_dev - return device
 665  *  @hw: pointer to hardware structure
 666  *
 667  *  used by hardware layer to print debugging information
 668  **/
 669 struct net_device *igb_get_hw_dev(struct e1000_hw *hw)
 670 {
 671         struct igb_adapter *adapter = hw->back;
 672         return adapter->netdev;
 673 }
 674
 675 /**
 676  *  igb_init_module - Driver Registration Routine
 677  *
 678  *  igb_init_module is the first routine called when the driver is
 679  *  loaded. All it does is register with the PCI subsystem.
 680  **/
 681 static int __init igb_init_module(void)
 682 {
 683         int ret;
 684         pr_info("%s - version %s\n",
 685                igb_driver_string, igb_driver_version);
 686
 687         pr_info("%s\n", igb_copyright);
 688
 689 #ifdef CONFIG_IGB_DCA
 690         dca_register_notify(&dca_notifier);
 691 #endif
 692         ret = pci_register_driver(&igb_driver);
 693         return ret;
 694 }
 695
 696 module_init(igb_init_module);
 697
 698 /**
 699  *  igb_exit_module - Driver Exit Cleanup Routine
 700  *
 701  *  igb_exit_module is called just before the driver is removed
 702  *  from memory.
 703  **/
 704 static void __exit igb_exit_module(void)
 705 {
 706 #ifdef CONFIG_IGB_DCA
 707         dca_unregister_notify(&dca_notifier);
 708 #endif
 709         pci_unregister_driver(&igb_driver);
 710 }
 711
 712 module_exit(igb_exit_module);
 713
 714 #define Q_IDX_82576(i) (((i & 0x1) << 3) + (i >> 1))
 715 /**
 716  *  igb_cache_ring_register - Descriptor ring to register mapping
 717  *  @adapter: board private structure to initialize
 718  *
 719  *  Once we know the feature-set enabled for the device, we'll cache
 720  *  the register offset the descriptor ring is assigned to.
 721  **/
 722 static void igb_cache_ring_register(struct igb_adapter *adapter)
 723 {
 724         int i = 0, j = 0;
 725         u32 rbase_offset = adapter->vfs_allocated_count;
 726
 727         switch (adapter->hw.mac.type) {
 728         case e1000_82576:
 729                 /* The queues are allocated for virtualization such that VF 0
 730                  * is allocated queues 0 and 8, VF 1 queues 1 and 9, etc.
 731                  * In order to avoid collision we start at the first free queue
 732                  * and continue consuming queues in the same sequence
 733                  */
 734                 if (adapter->vfs_allocated_count) {
 735                         for (; i < adapter->rss_queues; i++)
 736                                 adapter->rx_ring[i]->reg_idx = rbase_offset +
 737                                                                Q_IDX_82576(i);
 738                 }
 739         case e1000_82575:
 740         case e1000_82580:
 741         case e1000_i350:
 742         case e1000_i354:
 743         case e1000_i210:
 744         case e1000_i211:
 745         default:
 746                 for (; i < adapter->num_rx_queues; i++)
 747                         adapter->rx_ring[i]->reg_idx = rbase_offset + i;
 748                 for (; j < adapter->num_tx_queues; j++)
 749                         adapter->tx_ring[j]->reg_idx = rbase_offset + j;
 750                 break;
 751         }
 752 }
 753
 754 /**
 755  *  igb_write_ivar - configure ivar for given MSI-X vector
 756  *  @hw: pointer to the HW structure
 757  *  @msix_vector: vector number we are allocating to a given ring
 758  *  @index: row index of IVAR register to write within IVAR table
 759  *  @offset: column offset of in IVAR, should be multiple of 8
 760  *
 761  *  This function is intended to handle the writing of the IVAR register
 762  *  for adapters 82576 and newer.  The IVAR table consists of 2 columns,
 763  *  each containing an cause allocation for an Rx and Tx ring, and a
 764  *  variable number of rows depending on the number of queues supported.
 765  **/
 766 static void igb_write_ivar(struct e1000_hw *hw, int msix_vector,
 767                            int index, int offset)
 768 {
 769         u32 ivar = array_rd32(E1000_IVAR0, index);
 770
 771         /* clear any bits that are currently set */
 772         ivar &= ~((u32)0xFF << offset);
 773
 774         /* write vector and valid bit */
 775         ivar |= (msix_vector | E1000_IVAR_VALID) << offset;
 776
 777         array_wr32(E1000_IVAR0, index, ivar);
 778 }
 779
 780 #define IGB_N0_QUEUE -1
 781 static void igb_assign_vector(struct igb_q_vector *q_vector, int msix_vector)
 782 {
 783         struct igb_adapter *adapter = q_vector->adapter;
 784         struct e1000_hw *hw = &adapter->hw;
 785         int rx_queue = IGB_N0_QUEUE;
 786         int tx_queue = IGB_N0_QUEUE;
 787         u32 msixbm = 0;
 788
 789         if (q_vector->rx.ring)
 790                 rx_queue = q_vector->rx.ring->reg_idx;
 791         if (q_vector->tx.ring)
 792                 tx_queue = q_vector->tx.ring->reg_idx;
 793
 794         switch (hw->mac.type) {
 795         case e1000_82575:
 796                 /* The 82575 assigns vectors using a bitmask, which matches the
 797                  * bitmask for the EICR/EIMS/EIMC registers.  To assign one
 798                  * or more queues to a vector, we write the appropriate bits
 799                  * into the MSIXBM register for that vector.
 800                  */
 801                 if (rx_queue > IGB_N0_QUEUE)
 802                         msixbm = E1000_EICR_RX_QUEUE0 << rx_queue;
 803                 if (tx_queue > IGB_N0_QUEUE)
 804                         msixbm |= E1000_EICR_TX_QUEUE0 << tx_queue;
 805                 if (!adapter->msix_entries && msix_vector == 0)
 806                         msixbm |= E1000_EIMS_OTHER;
 807                 array_wr32(E1000_MSIXBM(0), msix_vector, msixbm);
 808                 q_vector->eims_value = msixbm;
 809                 break;
 810         case e1000_82576:
 811                 /* 82576 uses a table that essentially consists of 2 columns
 812                  * with 8 rows.  The ordering is column-major so we use the
 813                  * lower 3 bits as the row index, and the 4th bit as the
 814                  * column offset.
 815                  */
 816                 if (rx_queue > IGB_N0_QUEUE)
 817                         igb_write_ivar(hw, msix_vector,
 818                                        rx_queue & 0x7,
 819                                        (rx_queue & 0x8) << 1);
 820                 if (tx_queue > IGB_N0_QUEUE)
 821                         igb_write_ivar(hw, msix_vector,
 822                                        tx_queue & 0x7,
 823                                        ((tx_queue & 0x8) << 1) + 8);
 824                 q_vector->eims_value = 1 << msix_vector;
 825                 break;
 826         case e1000_82580:
 827         case e1000_i350:
 828         case e1000_i354:
 829         case e1000_i210:
 830         case e1000_i211:
 831                 /* On 82580 and newer adapters the scheme is similar to 82576
 832                  * however instead of ordering column-major we have things
 833                  * ordered row-major.  So we traverse the table by using
 834                  * bit 0 as the column offset, and the remaining bits as the
 835                  * row index.
 836                  */
 837                 if (rx_queue > IGB_N0_QUEUE)
 838                         igb_write_ivar(hw, msix_vector,
 839                                        rx_queue >> 1,
 840                                        (rx_queue & 0x1) << 4);
 841                 if (tx_queue > IGB_N0_QUEUE)
 842                         igb_write_ivar(hw, msix_vector,
 843                                        tx_queue >> 1,
 844                                        ((tx_queue & 0x1) << 4) + 8);
 845                 q_vector->eims_value = 1 << msix_vector;
 846                 break;
 847         default:
 848                 BUG();
 849                 break;
 850         }
 851
 852         /* add q_vector eims value to global eims_enable_mask */
 853         adapter->eims_enable_mask |= q_vector->eims_value;
 854
 855         /* configure q_vector to set itr on first interrupt */
 856         q_vector->set_itr = 1;
 857 }
 858
 859 /**
 860  *  igb_configure_msix - Configure MSI-X hardware
 861  *  @adapter: board private structure to initialize
 862  *
 863  *  igb_configure_msix sets up the hardware to properly
 864  *  generate MSI-X interrupts.
 865  **/
 866 static void igb_configure_msix(struct igb_adapter *adapter)
 867 {
 868         u32 tmp;
 869         int i, vector = 0;
 870         struct e1000_hw *hw = &adapter->hw;
 871
 872         adapter->eims_enable_mask = 0;
 873
 874         /* set vector for other causes, i.e. link changes */
 875         switch (hw->mac.type) {
 876         case e1000_82575:
 877                 tmp = rd32(E1000_CTRL_EXT);
 878                 /* enable MSI-X PBA support*/
 879                 tmp |= E1000_CTRL_EXT_PBA_CLR;
 880
 881                 /* Auto-Mask interrupts upon ICR read. */
 882                 tmp |= E1000_CTRL_EXT_EIAME;
 883                 tmp |= E1000_CTRL_EXT_IRCA;
 884
 885                 wr32(E1000_CTRL_EXT, tmp);
 886
 887                 /* enable msix_other interrupt */
 888                 array_wr32(E1000_MSIXBM(0), vector++, E1000_EIMS_OTHER);
 889                 adapter->eims_other = E1000_EIMS_OTHER;
 890
 891                 break;
 892
 893         case e1000_82576:
 894         case e1000_82580:
 895         case e1000_i350:
 896         case e1000_i354:
 897         case e1000_i210:
 898         case e1000_i211:
 899                 /* Turn on MSI-X capability first, or our settings
 900                  * won't stick.  And it will take days to debug.
 901                  */
 902                 wr32(E1000_GPIE, E1000_GPIE_MSIX_MODE |
 903                      E1000_GPIE_PBA | E1000_GPIE_EIAME |
 904                      E1000_GPIE_NSICR);
 905
 906                 /* enable msix_other interrupt */
 907                 adapter->eims_other = 1 << vector;
 908                 tmp = (vector++ | E1000_IVAR_VALID) << 8;
 909
 910                 wr32(E1000_IVAR_MISC, tmp);
 911                 break;
 912         default:
 913                 /* do nothing, since nothing else supports MSI-X */
 914                 break;
 915         } /* switch (hw->mac.type) */
 916
 917         adapter->eims_enable_mask |= adapter->eims_other;
 918
 919         for (i = 0; i < adapter->num_q_vectors; i++)
 920                 igb_assign_vector(adapter->q_vector[i], vector++);
 921
 922         wrfl();
 923 }
 924
 925 /**
 926  *  igb_request_msix - Initialize MSI-X interrupts
 927  *  @adapter: board private structure to initialize
 928  *
 929  *  igb_request_msix allocates MSI-X vectors and requests interrupts from the
 930  *  kernel.
 931  **/
 932 static int igb_request_msix(struct igb_adapter *adapter)
 933 {
 934         struct net_device *netdev = adapter->netdev;
 935         struct e1000_hw *hw = &adapter->hw;
 936         int i, err = 0, vector = 0, free_vector = 0;
 937
 938         err = request_irq(adapter->msix_entries[vector].vector,
 939                           igb_msix_other, 0, netdev->name, adapter);
 940         if (err)
 941                 goto err_out;
 942
 943         for (i = 0; i < adapter->num_q_vectors; i++) {
 944                 struct igb_q_vector *q_vector = adapter->q_vector[i];
 945
 946                 vector++;
 947
 948                 q_vector->itr_register = hw->hw_addr + E1000_EITR(vector);
 949
 950                 if (q_vector->rx.ring && q_vector->tx.ring)
 951                         sprintf(q_vector->name, "%s-TxRx-%u", netdev->name,
 952                                 q_vector->rx.ring->queue_index);
 953                 else if (q_vector->tx.ring)
 954                         sprintf(q_vector->name, "%s-tx-%u", netdev->name,
 955                                 q_vector->tx.ring->queue_index);
 956                 else if (q_vector->rx.ring)
 957                         sprintf(q_vector->name, "%s-rx-%u", netdev->name,
 958                                 q_vector->rx.ring->queue_index);
 959                 else
 960                         sprintf(q_vector->name, "%s-unused", netdev->name);
 961
 962                 err = request_irq(adapter->msix_entries[vector].vector,
 963                                   igb_msix_ring, 0, q_vector->name,
 964                                   q_vector);
 965                 if (err)
 966                         goto err_free;
 967         }
 968
 969         igb_configure_msix(adapter);
 970         return 0;
 971
 972 err_free:
 973         /* free already assigned IRQs */
 974         free_irq(adapter->msix_entries[free_vector++].vector, adapter);
 975
 976         vector--;
 977         for (i = 0; i < vector; i++) {
 978                 free_irq(adapter->msix_entries[free_vector++].vector,
 979                          adapter->q_vector[i]);
 980         }
 981 err_out:
 982         return err;
 983 }
 984
 985 static void igb_reset_interrupt_capability(struct igb_adapter *adapter)
 986 {
 987         if (adapter->msix_entries) {
 988                 pci_disable_msix(adapter->pdev);
 989                 kfree(adapter->msix_entries);
 990                 adapter->msix_entries = NULL;
 991         } else if (adapter->flags & IGB_FLAG_HAS_MSI) {
 992                 pci_disable_msi(adapter->pdev);
 993         }
 994 }
 995
 996 /**
 997  *  igb_free_q_vector - Free memory allocated for specific interrupt vector
 998  *  @adapter: board private structure to initialize
 999  *  @v_idx: Index of vector to be freed
1000  *
1001  *  This function frees the memory allocated to the q_vector.  In addition if
1002  *  NAPI is enabled it will delete any references to the NAPI struct prior
1003  *  to freeing the q_vector.
1004  **/
1005 static void igb_free_q_vector(struct igb_adapter *adapter, int v_idx)
1006 {
1007         struct igb_q_vector *q_vector = adapter->q_vector[v_idx];
1008
1009         if (q_vector->tx.ring)
1010                 adapter->tx_ring[q_vector->tx.ring->queue_index] = NULL;
1011
1012         if (q_vector->rx.ring)
1013                 adapter->tx_ring[q_vector->rx.ring->queue_index] = NULL;
1014
1015         adapter->q_vector[v_idx] = NULL;
1016         netif_napi_del(&q_vector->napi);
1017
1018         /* igb_get_stats64() might access the rings on this vector,
1019          * we must wait a grace period before freeing it.
1020          */
1021         kfree_rcu(q_vector, rcu);
1022 }
1023
1024 /**
1025  *  igb_free_q_vectors - Free memory allocated for interrupt vectors
1026  *  @adapter: board private structure to initialize
1027  *
1028  *  This function frees the memory allocated to the q_vectors.  In addition if
1029  *  NAPI is enabled it will delete any references to the NAPI struct prior
1030  *  to freeing the q_vector.
1031  **/
1032 static void igb_free_q_vectors(struct igb_adapter *adapter)
1033 {
1034         int v_idx = adapter->num_q_vectors;
1035
1036         adapter->num_tx_queues = 0;
1037         adapter->num_rx_queues = 0;
1038         adapter->num_q_vectors = 0;
1039
1040         while (v_idx--)
1041                 igb_free_q_vector(adapter, v_idx);
1042 }
1043
1044 /**
1045  *  igb_clear_interrupt_scheme - reset the device to a state of no interrupts
1046  *  @adapter: board private structure to initialize
1047  *
1048  *  This function resets the device so that it has 0 Rx queues, Tx queues, and
1049  *  MSI-X interrupts allocated.
1050  */
1051 static void igb_clear_interrupt_scheme(struct igb_adapter *adapter)
1052 {
1053         igb_free_q_vectors(adapter);
1054         igb_reset_interrupt_capability(adapter);
1055 }
1056
1057 /**
1058  *  igb_set_interrupt_capability - set MSI or MSI-X if supported
1059  *  @adapter: board private structure to initialize
1060  *  @msix: boolean value of MSIX capability
1061  *
1062  *  Attempt to configure interrupts using the best available
1063  *  capabilities of the hardware and kernel.
1064  **/
1065 static void igb_set_interrupt_capability(struct igb_adapter *adapter, bool msix)
1066 {
1067         int err;
1068         int numvecs, i;
1069
1070         if (!msix)
1071                 goto msi_only;
1072
1073         /* Number of supported queues. */
1074         adapter->num_rx_queues = adapter->rss_queues;
1075         if (adapter->vfs_allocated_count)
1076                 adapter->num_tx_queues = 1;
1077         else
1078                 adapter->num_tx_queues = adapter->rss_queues;
1079
1080         /* start with one vector for every Rx queue */
1081         numvecs = adapter->num_rx_queues;
1082
1083         /* if Tx handler is separate add 1 for every Tx queue */
1084         if (!(adapter->flags & IGB_FLAG_QUEUE_PAIRS))
1085                 numvecs += adapter->num_tx_queues;
1086
1087         /* store the number of vectors reserved for queues */
1088         adapter->num_q_vectors = numvecs;
1089
1090         /* add 1 vector for link status interrupts */
1091         numvecs++;
1092         adapter->msix_entries = kcalloc(numvecs, sizeof(struct msix_entry),
1093                                         GFP_KERNEL);
1094
1095         if (!adapter->msix_entries)
1096                 goto msi_only;
1097
1098         for (i = 0; i < numvecs; i++)
1099                 adapter->msix_entries[i].entry = i;
1100
1101         err = pci_enable_msix(adapter->pdev,
1102                               adapter->msix_entries,
1103                               numvecs);
1104         if (err == 0)
1105                 return;
1106
1107         igb_reset_interrupt_capability(adapter);
1108
1109         /* If we can't do MSI-X, try MSI */
1110 msi_only:
1111 #ifdef CONFIG_PCI_IOV
1112         /* disable SR-IOV for non MSI-X configurations */
1113         if (adapter->vf_data) {
1114                 struct e1000_hw *hw = &adapter->hw;
1115                 /* disable iov and allow time for transactions to clear */
1116                 pci_disable_sriov(adapter->pdev);
1117                 msleep(500);
1118
1119                 kfree(adapter->vf_data);
1120                 adapter->vf_data = NULL;
1121                 wr32(E1000_IOVCTL, E1000_IOVCTL_REUSE_VFQ);
1122                 wrfl();
1123                 msleep(100);
1124                 dev_info(&adapter->pdev->dev, "IOV Disabled\n");
1125         }
1126 #endif
1127         adapter->vfs_allocated_count = 0;
1128         adapter->rss_queues = 1;
1129         adapter->flags |= IGB_FLAG_QUEUE_PAIRS;
1130         adapter->num_rx_queues = 1;
1131         adapter->num_tx_queues = 1;
1132         adapter->num_q_vectors = 1;
1133         if (!pci_enable_msi(adapter->pdev))
1134                 adapter->flags |= IGB_FLAG_HAS_MSI;
1135 }
1136
1137 static void igb_add_ring(struct igb_ring *ring,
1138                          struct igb_ring_container *head)
1139 {
1140         head->ring = ring;
1141         head->count++;
1142 }
1143
1144 /**
1145  *  igb_alloc_q_vector - Allocate memory for a single interrupt vector
1146  *  @adapter: board private structure to initialize
1147  *  @v_count: q_vectors allocated on adapter, used for ring interleaving
1148  *  @v_idx: index of vector in adapter struct
1149  *  @txr_count: total number of Tx rings to allocate
1150  *  @txr_idx: index of first Tx ring to allocate
1151  *  @rxr_count: total number of Rx rings to allocate
1152  *  @rxr_idx: index of first Rx ring to allocate
1153  *
1154  *  We allocate one q_vector.  If allocation fails we return -ENOMEM.
1155  **/
1156 static int igb_alloc_q_vector(struct igb_adapter *adapter,
1157                               int v_count, int v_idx,
1158                               int txr_count, int txr_idx,
1159                               int rxr_count, int rxr_idx)
1160 {
1161         struct igb_q_vector *q_vector;
1162         struct igb_ring *ring;
1163         int ring_count, size;
1164
1165         /* igb only supports 1 Tx and/or 1 Rx queue per vector */
1166         if (txr_count > 1 || rxr_count > 1)
1167                 return -ENOMEM;
1168
1169         ring_count = txr_count + rxr_count;
1170         size = sizeof(struct igb_q_vector) +
1171                (sizeof(struct igb_ring) * ring_count);
1172
1173         /* allocate q_vector and rings */
1174         q_vector = kzalloc(size, GFP_KERNEL);
1175         if (!q_vector)
1176                 return -ENOMEM;
1177
1178         /* initialize NAPI */
1179         netif_napi_add(adapter->netdev, &q_vector->napi,
1180                        igb_poll, 64);
1181
1182         /* tie q_vector and adapter together */
1183         adapter->q_vector[v_idx] = q_vector;
1184         q_vector->adapter = adapter;
1185
1186         /* initialize work limits */
1187         q_vector->tx.work_limit = adapter->tx_work_limit;
1188
1189         /* initialize ITR configuration */
1190         q_vector->itr_register = adapter->hw.hw_addr + E1000_EITR(0);
1191         q_vector->itr_val = IGB_START_ITR;
1192
1193         /* initialize pointer to rings */
1194         ring = q_vector->ring;
1195
1196         /* intialize ITR */
1197         if (rxr_count) {
1198                 /* rx or rx/tx vector */
1199                 if (!adapter->rx_itr_setting || adapter->rx_itr_setting > 3)
1200                         q_vector->itr_val = adapter->rx_itr_setting;
1201         } else {
1202                 /* tx only vector */
1203                 if (!adapter->tx_itr_setting || adapter->tx_itr_setting > 3)
1204                         q_vector->itr_val = adapter->tx_itr_setting;
1205         }
1206
1207         if (txr_count) {
1208                 /* assign generic ring traits */
1209                 ring->dev = &adapter->pdev->dev;
1210                 ring->netdev = adapter->netdev;
1211
1212                 /* configure backlink on ring */
1213                 ring->q_vector = q_vector;
1214
1215                 /* update q_vector Tx values */
1216                 igb_add_ring(ring, &q_vector->tx);
1217
1218                 /* For 82575, context index must be unique per ring. */
1219                 if (adapter->hw.mac.type == e1000_82575)
1220                         set_bit(IGB_RING_FLAG_TX_CTX_IDX, &ring->flags);
1221
1222                 /* apply Tx specific ring traits */
1223                 ring->count = adapter->tx_ring_count;
1224                 ring->queue_index = txr_idx;
1225
1226                 /* assign ring to adapter */
1227                 adapter->tx_ring[txr_idx] = ring;
1228
1229                 /* push pointer to next ring */
1230                 ring++;
1231         }
1232
1233         if (rxr_count) {
1234                 /* assign generic ring traits */
1235                 ring->dev = &adapter->pdev->dev;
1236                 ring->netdev = adapter->netdev;
1237
1238                 /* configure backlink on ring */
1239                 ring->q_vector = q_vector;
1240
1241                 /* update q_vector Rx values */
1242                 igb_add_ring(ring, &q_vector->rx);
1243
1244                 /* set flag indicating ring supports SCTP checksum offload */
1245                 if (adapter->hw.mac.type >= e1000_82576)
1246                         set_bit(IGB_RING_FLAG_RX_SCTP_CSUM, &ring->flags);
1247
1248                 /*
1249                  * On i350, i354, i210, and i211, loopback VLAN packets
1250                  * have the tag byte-swapped.
1251                  */
1252                 if (adapter->hw.mac.type >= e1000_i350)
1253                         set_bit(IGB_RING_FLAG_RX_LB_VLAN_BSWAP, &ring->flags);
1254
1255                 /* apply Rx specific ring traits */
1256                 ring->count = adapter->rx_ring_count;
1257                 ring->queue_index = rxr_idx;
1258
1259                 /* assign ring to adapter */
1260                 adapter->rx_ring[rxr_idx] = ring;
1261         }
1262
1263         return 0;
1264 }
1265
1266
1267 /**
1268  *  igb_alloc_q_vectors - Allocate memory for interrupt vectors
1269  *  @adapter: board private structure to initialize
1270  *
1271  *  We allocate one q_vector per queue interrupt.  If allocation fails we
1272  *  return -ENOMEM.
1273  **/
1274 static int igb_alloc_q_vectors(struct igb_adapter *adapter)
1275 {
1276         int q_vectors = adapter->num_q_vectors;
1277         int rxr_remaining = adapter->num_rx_queues;
1278         int txr_remaining = adapter->num_tx_queues;
1279         int rxr_idx = 0, txr_idx = 0, v_idx = 0;
1280         int err;
1281
1282         if (q_vectors >= (rxr_remaining + txr_remaining)) {
1283                 for (; rxr_remaining; v_idx++) {
1284                         err = igb_alloc_q_vector(adapter, q_vectors, v_idx,
1285                                                  0, 0, 1, rxr_idx);
1286
1287                         if (err)
1288                                 goto err_out;
1289
1290                         /* update counts and index */
1291                         rxr_remaining--;
1292                         rxr_idx++;
1293                 }
1294         }
1295
1296         for (; v_idx < q_vectors; v_idx++) {
1297                 int rqpv = DIV_ROUND_UP(rxr_remaining, q_vectors - v_idx);
1298                 int tqpv = DIV_ROUND_UP(txr_remaining, q_vectors - v_idx);
1299                 err = igb_alloc_q_vector(adapter, q_vectors, v_idx,
1300                                          tqpv, txr_idx, rqpv, rxr_idx);
1301
1302                 if (err)
1303                         goto err_out;
1304
1305                 /* update counts and index */
1306                 rxr_remaining -= rqpv;
1307                 txr_remaining -= tqpv;
1308                 rxr_idx++;
1309                 txr_idx++;
1310         }
1311
1312         return 0;
1313
1314 err_out:
1315         adapter->num_tx_queues = 0;
1316         adapter->num_rx_queues = 0;
1317         adapter->num_q_vectors = 0;
1318
1319         while (v_idx--)
1320                 igb_free_q_vector(adapter, v_idx);
1321
1322         return -ENOMEM;
1323 }
1324
1325 /**
1326  *  igb_init_interrupt_scheme - initialize interrupts, allocate queues/vectors
1327  *  @adapter: board private structure to initialize
1328  *  @msix: boolean value of MSIX capability
1329  *
1330  *  This function initializes the interrupts and allocates all of the queues.
1331  **/
1332 static int igb_init_interrupt_scheme(struct igb_adapter *adapter, bool msix)
1333 {
1334         struct pci_dev *pdev = adapter->pdev;
1335         int err;
1336
1337         igb_set_interrupt_capability(adapter, msix);
1338
1339         err = igb_alloc_q_vectors(adapter);
1340         if (err) {
1341                 dev_err(&pdev->dev, "Unable to allocate memory for vectors\n");
1342                 goto err_alloc_q_vectors;
1343         }
1344
1345         igb_cache_ring_register(adapter);
1346
1347         return 0;
1348
1349 err_alloc_q_vectors:
1350         igb_reset_interrupt_capability(adapter);
1351         return err;
1352 }
1353
1354 /**
1355  *  igb_request_irq - initialize interrupts
1356  *  @adapter: board private structure to initialize
1357  *
1358  *  Attempts to configure interrupts using the best available
1359  *  capabilities of the hardware and kernel.
1360  **/
1361 static int igb_request_irq(struct igb_adapter *adapter)
1362 {
1363         struct net_device *netdev = adapter->netdev;
1364         struct pci_dev *pdev = adapter->pdev;
1365         int err = 0;
1366
1367         if (adapter->msix_entries) {
1368                 err = igb_request_msix(adapter);
1369                 if (!err)
1370                         goto request_done;
1371                 /* fall back to MSI */
1372                 igb_free_all_tx_resources(adapter);
1373                 igb_free_all_rx_resources(adapter);
1374
1375                 igb_clear_interrupt_scheme(adapter);
1376                 err = igb_init_interrupt_scheme(adapter, false);
1377                 if (err)
1378                         goto request_done;
1379
1380                 igb_setup_all_tx_resources(adapter);
1381                 igb_setup_all_rx_resources(adapter);
1382                 igb_configure(adapter);
1383         }
1384
1385         igb_assign_vector(adapter->q_vector[0], 0);
1386
1387         if (adapter->flags & IGB_FLAG_HAS_MSI) {
1388                 err = request_irq(pdev->irq, igb_intr_msi, 0,
1389                                   netdev->name, adapter);
1390                 if (!err)
1391                         goto request_done;
1392
1393                 /* fall back to legacy interrupts */
1394                 igb_reset_interrupt_capability(adapter);
1395                 adapter->flags &= ~IGB_FLAG_HAS_MSI;
1396         }
1397
1398         err = request_irq(pdev->irq, igb_intr, IRQF_SHARED,
1399                           netdev->name, adapter);
1400
1401         if (err)
1402                 dev_err(&pdev->dev, "Error %d getting interrupt\n",
1403                         err);
1404
1405 request_done:
1406         return err;
1407 }
1408
1409 static void igb_free_irq(struct igb_adapter *adapter)
1410 {
1411         if (adapter->msix_entries) {
1412                 int vector = 0, i;
1413
1414                 free_irq(adapter->msix_entries[vector++].vector, adapter);
1415
1416                 for (i = 0; i < adapter->num_q_vectors; i++)
1417                         free_irq(adapter->msix_entries[vector++].vector,
1418                                  adapter->q_vector[i]);
1419         } else {
1420                 free_irq(adapter->pdev->irq, adapter);
1421         }
1422 }
1423
1424 /**
1425  *  igb_irq_disable - Mask off interrupt generation on the NIC
1426  *  @adapter: board private structure
1427  **/
1428 static void igb_irq_disable(struct igb_adapter *adapter)
1429 {
1430         struct e1000_hw *hw = &adapter->hw;
1431
1432         /* we need to be careful when disabling interrupts.  The VFs are also
1433          * mapped into these registers and so clearing the bits can cause
1434          * issues on the VF drivers so we only need to clear what we set
1435          */
1436         if (adapter->msix_entries) {
1437                 u32 regval = rd32(E1000_EIAM);
1438                 wr32(E1000_EIAM, regval & ~adapter->eims_enable_mask);
1439                 wr32(E1000_EIMC, adapter->eims_enable_mask);
1440                 regval = rd32(E1000_EIAC);
1441                 wr32(E1000_EIAC, regval & ~adapter->eims_enable_mask);
1442         }
1443
1444         wr32(E1000_IAM, 0);
1445         wr32(E1000_IMC, ~0);
1446         wrfl();
1447         if (adapter->msix_entries) {
1448                 int i;
1449                 for (i = 0; i < adapter->num_q_vectors; i++)
1450                         synchronize_irq(adapter->msix_entries[i].vector);
1451         } else {
1452                 synchronize_irq(adapter->pdev->irq);
1453         }
1454 }
1455
1456 /**
1457  *  igb_irq_enable - Enable default interrupt generation settings
1458  *  @adapter: board private structure
1459  **/
1460 static void igb_irq_enable(struct igb_adapter *adapter)
1461 {
1462         struct e1000_hw *hw = &adapter->hw;
1463
1464         if (adapter->msix_entries) {
1465                 u32 ims = E1000_IMS_LSC | E1000_IMS_DOUTSYNC | E1000_IMS_DRSTA;
1466                 u32 regval = rd32(E1000_EIAC);
1467                 wr32(E1000_EIAC, regval | adapter->eims_enable_mask);
1468                 regval = rd32(E1000_EIAM);
1469                 wr32(E1000_EIAM, regval | adapter->eims_enable_mask);
1470                 wr32(E1000_EIMS, adapter->eims_enable_mask);
1471                 if (adapter->vfs_allocated_count) {
1472                         wr32(E1000_MBVFIMR, 0xFF);
1473                         ims |= E1000_IMS_VMMB;
1474                 }
1475                 wr32(E1000_IMS, ims);
1476         } else {
1477                 wr32(E1000_IMS, IMS_ENABLE_MASK |
1478                                 E1000_IMS_DRSTA);
1479                 wr32(E1000_IAM, IMS_ENABLE_MASK |
1480                                 E1000_IMS_DRSTA);
1481         }
1482 }
1483
1484 static void igb_update_mng_vlan(struct igb_adapter *adapter)
1485 {
1486         struct e1000_hw *hw = &adapter->hw;
1487         u16 vid = adapter->hw.mng_cookie.vlan_id;
1488         u16 old_vid = adapter->mng_vlan_id;
1489
1490         if (hw->mng_cookie.status & E1000_MNG_DHCP_COOKIE_STATUS_VLAN) {
1491                 /* add VID to filter table */
1492                 igb_vfta_set(hw, vid, true);
1493                 adapter->mng_vlan_id = vid;
1494         } else {
1495                 adapter->mng_vlan_id = IGB_MNG_VLAN_NONE;
1496         }
1497
1498         if ((old_vid != (u16)IGB_MNG_VLAN_NONE) &&
1499             (vid != old_vid) &&
1500             !test_bit(old_vid, adapter->active_vlans)) {
1501                 /* remove VID from filter table */
1502                 igb_vfta_set(hw, old_vid, false);
1503         }
1504 }
1505
1506 /**
1507  *  igb_release_hw_control - release control of the h/w to f/w
1508  *  @adapter: address of board private structure
1509  *
1510  *  igb_release_hw_control resets CTRL_EXT:DRV_LOAD bit.
1511  *  For ASF and Pass Through versions of f/w this means that the
1512  *  driver is no longer loaded.
1513  **/
1514 static void igb_release_hw_control(struct igb_adapter *adapter)
1515 {
1516         struct e1000_hw *hw = &adapter->hw;
1517         u32 ctrl_ext;
1518
1519         /* Let firmware take over control of h/w */
1520         ctrl_ext = rd32(E1000_CTRL_EXT);
1521         wr32(E1000_CTRL_EXT,
1522                         ctrl_ext & ~E1000_CTRL_EXT_DRV_LOAD);
1523 }
1524
1525 /**
1526  *  igb_get_hw_control - get control of the h/w from f/w
1527  *  @adapter: address of board private structure
1528  *
1529  *  igb_get_hw_control sets CTRL_EXT:DRV_LOAD bit.
1530  *  For ASF and Pass Through versions of f/w this means that
1531  *  the driver is loaded.
1532  **/
1533 static void igb_get_hw_control(struct igb_adapter *adapter)
1534 {
1535         struct e1000_hw *hw = &adapter->hw;
1536         u32 ctrl_ext;
1537
1538         /* Let firmware know the driver has taken over */
1539         ctrl_ext = rd32(E1000_CTRL_EXT);
1540         wr32(E1000_CTRL_EXT,
1541                         ctrl_ext | E1000_CTRL_EXT_DRV_LOAD);
1542 }
1543
1544 /**
1545  *  igb_configure - configure the hardware for RX and TX
1546  *  @adapter: private board structure
1547  **/
1548 static void igb_configure(struct igb_adapter *adapter)
1549 {
1550         struct net_device *netdev = adapter->netdev;
1551         int i;
1552
1553         igb_get_hw_control(adapter);
1554         igb_set_rx_mode(netdev);
1555
1556         igb_restore_vlan(adapter);
1557
1558         igb_setup_tctl(adapter);
1559         igb_setup_mrqc(adapter);
1560         igb_setup_rctl(adapter);
1561
1562         igb_configure_tx(adapter);
1563         igb_configure_rx(adapter);
1564
1565         igb_rx_fifo_flush_82575(&adapter->hw);
1566
1567         /* call igb_desc_unused which always leaves
1568          * at least 1 descriptor unused to make sure
1569          * next_to_use != next_to_clean
1570          */
1571         for (i = 0; i < adapter->num_rx_queues; i++) {
1572                 struct igb_ring *ring = adapter->rx_ring[i];
1573                 igb_alloc_rx_buffers(ring, igb_desc_unused(ring));
1574         }
1575 }
1576
1577 /**
1578  *  igb_power_up_link - Power up the phy/serdes link
1579  *  @adapter: address of board private structure
1580  **/
1581 void igb_power_up_link(struct igb_adapter *adapter)
1582 {
1583         igb_reset_phy(&adapter->hw);
1584
1585         if (adapter->hw.phy.media_type == e1000_media_type_copper)
1586                 igb_power_up_phy_copper(&adapter->hw);
1587         else
1588                 igb_power_up_serdes_link_82575(&adapter->hw);
1589 }
1590
1591 /**
1592  *  igb_power_down_link - Power down the phy/serdes link
1593  *  @adapter: address of board private structure
1594  */
1595 static void igb_power_down_link(struct igb_adapter *adapter)
1596 {
1597         if (adapter->hw.phy.media_type == e1000_media_type_copper)
1598                 igb_power_down_phy_copper_82575(&adapter->hw);
1599         else
1600                 igb_shutdown_serdes_link_82575(&adapter->hw);
1601 }
1602
1603 /**
1604  *  igb_up - Open the interface and prepare it to handle traffic
1605  *  @adapter: board private structure
1606  **/
1607 int igb_up(struct igb_adapter *adapter)
1608 {
1609         struct e1000_hw *hw = &adapter->hw;
1610         int i;
1611
1612         /* hardware has been reset, we need to reload some things */
1613         igb_configure(adapter);
1614
1615         clear_bit(__IGB_DOWN, &adapter->state);
1616
1617         for (i = 0; i < adapter->num_q_vectors; i++)
1618                 napi_enable(&(adapter->q_vector[i]->napi));
1619
1620         if (adapter->msix_entries)
1621                 igb_configure_msix(adapter);
1622         else
1623                 igb_assign_vector(adapter->q_vector[0], 0);
1624
1625         /* Clear any pending interrupts. */
1626         rd32(E1000_ICR);
1627         igb_irq_enable(adapter);
1628
1629         /* notify VFs that reset has been completed */
1630         if (adapter->vfs_allocated_count) {
1631                 u32 reg_data = rd32(E1000_CTRL_EXT);
1632                 reg_data |= E1000_CTRL_EXT_PFRSTD;
1633                 wr32(E1000_CTRL_EXT, reg_data);
1634         }
1635
1636         netif_tx_start_all_queues(adapter->netdev);
1637
1638         /* start the watchdog. */
1639         hw->mac.get_link_status = 1;
1640         schedule_work(&adapter->watchdog_task);
1641
1642         return 0;
1643 }
1644
1645 void igb_down(struct igb_adapter *adapter)
1646 {
1647         struct net_device *netdev = adapter->netdev;
1648         struct e1000_hw *hw = &adapter->hw;
1649         u32 tctl, rctl;
1650         int i;
1651
1652         /* signal that we're down so the interrupt handler does not
1653          * reschedule our watchdog timer
1654          */
1655         set_bit(__IGB_DOWN, &adapter->state);
1656
1657         /* disable receives in the hardware */
1658         rctl = rd32(E1000_RCTL);
1659         wr32(E1000_RCTL, rctl & ~E1000_RCTL_EN);
1660         /* flush and sleep below */
1661
1662         netif_tx_stop_all_queues(netdev);
1663
1664         /* disable transmits in the hardware */
1665         tctl = rd32(E1000_TCTL);
1666         tctl &= ~E1000_TCTL_EN;
1667         wr32(E1000_TCTL, tctl);
1668         /* flush both disables and wait for them to finish */
1669         wrfl();
1670         msleep(10);
1671
1672         igb_irq_disable(adapter);
1673
1674         for (i = 0; i < adapter->num_q_vectors; i++) {
1675                 napi_synchronize(&(adapter->q_vector[i]->napi));
1676                 napi_disable(&(adapter->q_vector[i]->napi));
1677         }
1678
1679
1680         del_timer_sync(&adapter->watchdog_timer);
1681         del_timer_sync(&adapter->phy_info_timer);
1682
1683         netif_carrier_off(netdev);
1684
1685         /* record the stats before reset*/
1686         spin_lock(&adapter->stats64_lock);
1687         igb_update_stats(adapter, &adapter->stats64);
1688         spin_unlock(&adapter->stats64_lock);
1689
1690         adapter->link_speed = 0;
1691         adapter->link_duplex = 0;
1692
1693         if (!pci_channel_offline(adapter->pdev))
1694                 igb_reset(adapter);
1695         igb_clean_all_tx_rings(adapter);
1696         igb_clean_all_rx_rings(adapter);
1697 #ifdef CONFIG_IGB_DCA
1698
1699         /* since we reset the hardware DCA settings were cleared */
1700         igb_setup_dca(adapter);
1701 #endif
1702 }
1703
1704 void igb_reinit_locked(struct igb_adapter *adapter)
1705 {
1706         WARN_ON(in_interrupt());
1707         while (test_and_set_bit(__IGB_RESETTING, &adapter->state))
1708                 msleep(1);
1709         igb_down(adapter);
1710         igb_up(adapter);
1711         clear_bit(__IGB_RESETTING, &adapter->state);
1712 }
1713
1714 void igb_reset(struct igb_adapter *adapter)
1715 {
1716         struct pci_dev *pdev = adapter->pdev;
1717         struct e1000_hw *hw = &adapter->hw;
1718         struct e1000_mac_info *mac = &hw->mac;
1719         struct e1000_fc_info *fc = &hw->fc;
1720         u32 pba = 0, tx_space, min_tx_space, min_rx_space, hwm;
1721
1722         /* Repartition Pba for greater than 9k mtu
1723          * To take effect CTRL.RST is required.
1724          */
1725         switch (mac->type) {
1726         case e1000_i350:
1727         case e1000_i354:
1728         case e1000_82580:
1729                 pba = rd32(E1000_RXPBS);
1730                 pba = igb_rxpbs_adjust_82580(pba);
1731                 break;
1732         case e1000_82576:
1733                 pba = rd32(E1000_RXPBS);
1734                 pba &= E1000_RXPBS_SIZE_MASK_82576;
1735                 break;
1736         case e1000_82575:
1737         case e1000_i210:
1738         case e1000_i211:
1739         default:
1740                 pba = E1000_PBA_34K;
1741                 break;
1742         }
1743
1744         if ((adapter->max_frame_size > ETH_FRAME_LEN + ETH_FCS_LEN) &&
1745             (mac->type < e1000_82576)) {
1746                 /* adjust PBA for jumbo frames */
1747                 wr32(E1000_PBA, pba);
1748
1749                 /* To maintain wire speed transmits, the Tx FIFO should be
1750                  * large enough to accommodate two full transmit packets,
1751                  * rounded up to the next 1KB and expressed in KB.  Likewise,
1752                  * the Rx FIFO should be large enough to accommodate at least
1753                  * one full receive packet and is similarly rounded up and
1754                  * expressed in KB.
1755                  */
1756                 pba = rd32(E1000_PBA);
1757                 /* upper 16 bits has Tx packet buffer allocation size in KB */
1758                 tx_space = pba >> 16;
1759                 /* lower 16 bits has Rx packet buffer allocation size in KB */
1760                 pba &= 0xffff;
1761                 /* the Tx fifo also stores 16 bytes of information about the Tx
1762                  * but don't include ethernet FCS because hardware appends it
1763                  */
1764                 min_tx_space = (adapter->max_frame_size +
1765                                 sizeof(union e1000_adv_tx_desc) -
1766                                 ETH_FCS_LEN) * 2;
1767                 min_tx_space = ALIGN(min_tx_space, 1024);
1768                 min_tx_space >>= 10;
1769                 /* software strips receive CRC, so leave room for it */
1770                 min_rx_space = adapter->max_frame_size;
1771                 min_rx_space = ALIGN(min_rx_space, 1024);
1772                 min_rx_space >>= 10;
1773
1774                 /* If current Tx allocation is less than the min Tx FIFO size,
1775                  * and the min Tx FIFO size is less than the current Rx FIFO
1776                  * allocation, take space away from current Rx allocation
1777                  */
1778                 if (tx_space < min_tx_space &&
1779                     ((min_tx_space - tx_space) < pba)) {
1780                         pba = pba - (min_tx_space - tx_space);
1781
1782                         /* if short on Rx space, Rx wins and must trump Tx
1783                          * adjustment
1784                          */
1785                         if (pba < min_rx_space)
1786                                 pba = min_rx_space;
1787                 }
1788                 wr32(E1000_PBA, pba);
1789         }
1790
1791         /* flow control settings */
1792         /* The high water mark must be low enough to fit one full frame
1793          * (or the size used for early receive) above it in the Rx FIFO.
1794          * Set it to the lower of:
1795          * - 90% of the Rx FIFO size, or
1796          * - the full Rx FIFO size minus one full frame
1797          */
1798         hwm = min(((pba << 10) * 9 / 10),
1799                         ((pba << 10) - 2 * adapter->max_frame_size));
1800
1801         fc->high_water = hwm & 0xFFFFFFF0;      /* 16-byte granularity */
1802         fc->low_water = fc->high_water - 16;
1803         fc->pause_time = 0xFFFF;
1804         fc->send_xon = 1;
1805         fc->current_mode = fc->requested_mode;
1806
1807         /* disable receive for all VFs and wait one second */
1808         if (adapter->vfs_allocated_count) {
1809                 int i;
1810                 for (i = 0 ; i < adapter->vfs_allocated_count; i++)
1811                         adapter->vf_data[i].flags &= IGB_VF_FLAG_PF_SET_MAC;
1812
1813                 /* ping all the active vfs to let them know we are going down */
1814                 igb_ping_all_vfs(adapter);
1815
1816                 /* disable transmits and receives */
1817                 wr32(E1000_VFRE, 0);
1818                 wr32(E1000_VFTE, 0);
1819         }
1820
1821         /* Allow time for pending master requests to run */
1822         hw->mac.ops.reset_hw(hw);
1823         wr32(E1000_WUC, 0);
1824
1825         if (hw->mac.ops.init_hw(hw))
1826                 dev_err(&pdev->dev, "Hardware Error\n");
1827
1828         /* Flow control settings reset on hardware reset, so guarantee flow
1829          * control is off when forcing speed.
1830          */
1831         if (!hw->mac.autoneg)
1832                 igb_force_mac_fc(hw);
1833
1834         igb_init_dmac(adapter, pba);
1835 #ifdef CONFIG_IGB_HWMON
1836         /* Re-initialize the thermal sensor on i350 devices. */
1837         if (!test_bit(__IGB_DOWN, &adapter->state)) {
1838                 if (mac->type == e1000_i350 && hw->bus.func == 0) {
1839                         /* If present, re-initialize the external thermal sensor
1840                          * interface.
1841                          */
1842                         if (adapter->ets)
1843                                 mac->ops.init_thermal_sensor_thresh(hw);
1844                 }
1845         }
1846 #endif
1847         if (!netif_running(adapter->netdev))
1848                 igb_power_down_link(adapter);
1849
1850         igb_update_mng_vlan(adapter);
1851
1852         /* Enable h/w to recognize an 802.1Q VLAN Ethernet packet */
1853         wr32(E1000_VET, ETHERNET_IEEE_VLAN_TYPE);
1854
1855         /* Re-enable PTP, where applicable. */
1856         igb_ptp_reset(adapter);
1857
1858         igb_get_phy_info(hw);
1859 }
1860
1861 static netdev_features_t igb_fix_features(struct net_device *netdev,
1862         netdev_features_t features)
1863 {
1864         /* Since there is no support for separate Rx/Tx vlan accel
1865          * enable/disable make sure Tx flag is always in same state as Rx.
1866          */
1867         if (features & NETIF_F_HW_VLAN_CTAG_RX)
1868                 features |= NETIF_F_HW_VLAN_CTAG_TX;
1869         else
1870                 features &= ~NETIF_F_HW_VLAN_CTAG_TX;
1871
1872         return features;
1873 }
1874
1875 static int igb_set_features(struct net_device *netdev,
1876         netdev_features_t features)
1877 {
1878         netdev_features_t changed = netdev->features ^ features;
1879         struct igb_adapter *adapter = netdev_priv(netdev);
1880
1881         if (changed & NETIF_F_HW_VLAN_CTAG_RX)
1882                 igb_vlan_mode(netdev, features);
1883
1884         if (!(changed & NETIF_F_RXALL))
1885                 return 0;
1886
1887         netdev->features = features;
1888
1889         if (netif_running(netdev))
1890                 igb_reinit_locked(adapter);
1891         else
1892                 igb_reset(adapter);
1893
1894         return 0;
1895 }
1896
1897 static const struct net_device_ops igb_netdev_ops = {
1898         .ndo_open               = igb_open,
1899         .ndo_stop               = igb_close,
1900         .ndo_start_xmit         = igb_xmit_frame,
1901         .ndo_get_stats64        = igb_get_stats64,
1902         .ndo_set_rx_mode        = igb_set_rx_mode,
1903         .ndo_set_mac_address    = igb_set_mac,
1904         .ndo_change_mtu         = igb_change_mtu,
1905         .ndo_do_ioctl           = igb_ioctl,
1906         .ndo_tx_timeout         = igb_tx_timeout,
1907         .ndo_validate_addr      = eth_validate_addr,
1908         .ndo_vlan_rx_add_vid    = igb_vlan_rx_add_vid,
1909         .ndo_vlan_rx_kill_vid   = igb_vlan_rx_kill_vid,
1910         .ndo_set_vf_mac         = igb_ndo_set_vf_mac,
1911         .ndo_set_vf_vlan        = igb_ndo_set_vf_vlan,
1912         .ndo_set_vf_tx_rate     = igb_ndo_set_vf_bw,
1913         .ndo_set_vf_spoofchk    = igb_ndo_set_vf_spoofchk,
1914         .ndo_get_vf_config      = igb_ndo_get_vf_config,
1915 #ifdef CONFIG_NET_POLL_CONTROLLER
1916         .ndo_poll_controller    = igb_netpoll,
1917 #endif
1918         .ndo_fix_features       = igb_fix_features,
1919         .ndo_set_features       = igb_set_features,
1920 };
1921
1922 /**
1923  * igb_set_fw_version - Configure version string for ethtool
1924  * @adapter: adapter struct
1925  **/
1926 void igb_set_fw_version(struct igb_adapter *adapter)
1927 {
1928         struct e1000_hw *hw = &adapter->hw;
1929         struct e1000_fw_version fw;
1930
1931         igb_get_fw_version(hw, &fw);
1932
1933         switch (hw->mac.type) {
1934         case e1000_i210:
1935         case e1000_i211:
1936                 if (!(igb_get_flash_presence_i210(hw))) {
1937                         snprintf(adapter->fw_version,
1938                                  sizeof(adapter->fw_version),
1939                                  "%2d.%2d-%d",
1940                                  fw.invm_major, fw.invm_minor,
1941                                  fw.invm_img_type);
1942                         break;
1943                 }
1944                 /* fall through */
1945         default:
1946                 /* if option is rom valid, display its version too */
1947                 if (fw.or_valid) {
1948                         snprintf(adapter->fw_version,
1949                                  sizeof(adapter->fw_version),
1950                                  "%d.%d, 0x%08x, %d.%d.%d",
1951                                  fw.eep_major, fw.eep_minor, fw.etrack_id,
1952                                  fw.or_major, fw.or_build, fw.or_patch);
1953                 /* no option rom */
1954                 } else if (fw.etrack_id != 0X0000) {
1955                         snprintf(adapter->fw_version,
1956                             sizeof(adapter->fw_version),
1957                             "%d.%d, 0x%08x",
1958                             fw.eep_major, fw.eep_minor, fw.etrack_id);
1959                 } else {
1960                 snprintf(adapter->fw_version,
1961                     sizeof(adapter->fw_version),
1962                     "%d.%d.%d",
1963                     fw.eep_major, fw.eep_minor, fw.eep_build);
1964                 }
1965                 break;
1966         }
1967         return;
1968 }
1969
1970 /**
1971  *  igb_init_i2c - Init I2C interface
1972  *  @adapter: pointer to adapter structure
1973  **/
1974 static s32 igb_init_i2c(struct igb_adapter *adapter)
1975 {
1976         s32 status = E1000_SUCCESS;
1977
1978         /* I2C interface supported on i350 devices */
1979         if (adapter->hw.mac.type != e1000_i350)
1980                 return E1000_SUCCESS;
1981
1982         /* Initialize the i2c bus which is controlled by the registers.
1983          * This bus will use the i2c_algo_bit structue that implements
1984          * the protocol through toggling of the 4 bits in the register.
1985          */
1986         adapter->i2c_adap.owner = THIS_MODULE;
1987         adapter->i2c_algo = igb_i2c_algo;
1988         adapter->i2c_algo.data = adapter;
1989         adapter->i2c_adap.algo_data = &adapter->i2c_algo;
1990         adapter->i2c_adap.dev.parent = &adapter->pdev->dev;
1991         strlcpy(adapter->i2c_adap.name, "igb BB",
1992                 sizeof(adapter->i2c_adap.name));
1993         status = i2c_bit_add_bus(&adapter->i2c_adap);
1994         return status;
1995 }
1996
1997 /**
1998  *  igb_probe - Device Initialization Routine
1999  *  @pdev: PCI device information struct
2000  *  @ent: entry in igb_pci_tbl
2001  *
2002  *  Returns 0 on success, negative on failure
2003  *
2004  *  igb_probe initializes an adapter identified by a pci_dev structure.
2005  *  The OS initialization, configuring of the adapter private structure,
2006  *  and a hardware reset occur.
2007  **/
2008 static int igb_probe(struct pci_dev *pdev, const struct pci_device_id *ent)
2009 {
2010         struct net_device *netdev;
2011         struct igb_adapter *adapter;
2012         struct e1000_hw *hw;
2013         u16 eeprom_data = 0;
2014         s32 ret_val;
2015         static int global_quad_port_a; /* global quad port a indication */
2016         const struct e1000_info *ei = igb_info_tbl[ent->driver_data];
2017         unsigned long mmio_start, mmio_len;
2018         int err, pci_using_dac;
2019         u8 part_str[E1000_PBANUM_LENGTH];
2020
2021         /* Catch broken hardware that put the wrong VF device ID in
2022          * the PCIe SR-IOV capability.
2023          */
2024         if (pdev->is_virtfn) {
2025                 WARN(1, KERN_ERR "%s (%hx:%hx) should not be a VF!\n",
2026                         pci_name(pdev), pdev->vendor, pdev->device);
2027                 return -EINVAL;
2028         }
2029
2030         err = pci_enable_device_mem(pdev);
2031         if (err)
2032                 return err;
2033
2034         pci_using_dac = 0;
2035         err = dma_set_mask(&pdev->dev, DMA_BIT_MASK(64));
2036         if (!err) {
2037                 err = dma_set_coherent_mask(&pdev->dev, DMA_BIT_MASK(64));
2038                 if (!err)
2039                         pci_using_dac = 1;
2040         } else {
2041                 err = dma_set_mask(&pdev->dev, DMA_BIT_MASK(32));
2042                 if (err) {
2043                         err = dma_set_coherent_mask(&pdev->dev,
2044                                                     DMA_BIT_MASK(32));
2045                         if (err) {
2046                                 dev_err(&pdev->dev,
2047                                         "No usable DMA configuration, aborting\n");
2048                                 goto err_dma;
2049                         }
2050                 }
2051         }
2052
2053         err = pci_request_selected_regions(pdev, pci_select_bars(pdev,
2054                                            IORESOURCE_MEM),
2055                                            igb_driver_name);
2056         if (err)
2057                 goto err_pci_reg;
2058
2059         pci_enable_pcie_error_reporting(pdev);
2060
2061         pci_set_master(pdev);
2062         pci_save_state(pdev);
2063
2064         err = -ENOMEM;
2065         netdev = alloc_etherdev_mq(sizeof(struct igb_adapter),
2066                                    IGB_MAX_TX_QUEUES);
2067         if (!netdev)
2068                 goto err_alloc_etherdev;
2069
2070         SET_NETDEV_DEV(netdev, &pdev->dev);
2071
2072         pci_set_drvdata(pdev, netdev);
2073         adapter = netdev_priv(netdev);
2074         adapter->netdev = netdev;
2075         adapter->pdev = pdev;
2076         hw = &adapter->hw;
2077         hw->back = adapter;
2078         adapter->msg_enable = netif_msg_init(debug, DEFAULT_MSG_ENABLE);
2079
2080         mmio_start = pci_resource_start(pdev, 0);
2081         mmio_len = pci_resource_len(pdev, 0);
2082
2083         err = -EIO;
2084         hw->hw_addr = ioremap(mmio_start, mmio_len);
2085         if (!hw->hw_addr)
2086                 goto err_ioremap;
2087
2088         netdev->netdev_ops = &igb_netdev_ops;
2089         igb_set_ethtool_ops(netdev);
2090         netdev->watchdog_timeo = 5 * HZ;
2091
2092         strncpy(netdev->name, pci_name(pdev), sizeof(netdev->name) - 1);
2093
2094         netdev->mem_start = mmio_start;
2095         netdev->mem_end = mmio_start + mmio_len;
2096
2097         /* PCI config space info */
2098         hw->vendor_id = pdev->vendor;
2099         hw->device_id = pdev->device;
2100         hw->revision_id = pdev->revision;
2101         hw->subsystem_vendor_id = pdev->subsystem_vendor;
2102         hw->subsystem_device_id = pdev->subsystem_device;
2103
2104         /* Copy the default MAC, PHY and NVM function pointers */
2105         memcpy(&hw->mac.ops, ei->mac_ops, sizeof(hw->mac.ops));
2106         memcpy(&hw->phy.ops, ei->phy_ops, sizeof(hw->phy.ops));
2107         memcpy(&hw->nvm.ops, ei->nvm_ops, sizeof(hw->nvm.ops));
2108         /* Initialize skew-specific constants */
2109         err = ei->get_invariants(hw);
2110         if (err)
2111                 goto err_sw_init;
2112
2113         /* setup the private structure */
2114         err = igb_sw_init(adapter);
2115         if (err)
2116                 goto err_sw_init;
2117
2118         igb_get_bus_info_pcie(hw);
2119
2120         hw->phy.autoneg_wait_to_complete = false;
2121
2122         /* Copper options */
2123         if (hw->phy.media_type == e1000_media_type_copper) {
2124                 hw->phy.mdix = AUTO_ALL_MODES;
2125                 hw->phy.disable_polarity_correction = false;
2126                 hw->phy.ms_type = e1000_ms_hw_default;
2127         }
2128
2129         if (igb_check_reset_block(hw))
2130                 dev_info(&pdev->dev,
2131                         "PHY reset is blocked due to SOL/IDER session.\n");
2132
2133         /* features is initialized to 0 in allocation, it might have bits
2134          * set by igb_sw_init so we should use an or instead of an
2135          * assignment.
2136          */
2137         netdev->features |= NETIF_F_SG |
2138                             NETIF_F_IP_CSUM |
2139                             NETIF_F_IPV6_CSUM |
2140                             NETIF_F_TSO |
2141                             NETIF_F_TSO6 |
2142                             NETIF_F_RXHASH |
2143                             NETIF_F_RXCSUM |
2144                             NETIF_F_HW_VLAN_CTAG_RX |
2145                             NETIF_F_HW_VLAN_CTAG_TX;
2146
2147         /* copy netdev features into list of user selectable features */
2148         netdev->hw_features |= netdev->features;
2149         netdev->hw_features |= NETIF_F_RXALL;
2150
2151         /* set this bit last since it cannot be part of hw_features */
2152         netdev->features |= NETIF_F_HW_VLAN_CTAG_FILTER;
2153
2154         netdev->vlan_features |= NETIF_F_TSO |
2155                                  NETIF_F_TSO6 |
2156                                  NETIF_F_IP_CSUM |
2157                                  NETIF_F_IPV6_CSUM |
2158                                  NETIF_F_SG;
2159
2160         netdev->priv_flags |= IFF_SUPP_NOFCS;
2161
2162         if (pci_using_dac) {
2163                 netdev->features |= NETIF_F_HIGHDMA;
2164                 netdev->vlan_features |= NETIF_F_HIGHDMA;
2165         }
2166
2167         if (hw->mac.type >= e1000_82576) {
2168                 netdev->hw_features |= NETIF_F_SCTP_CSUM;
2169                 netdev->features |= NETIF_F_SCTP_CSUM;
2170         }
2171
2172         netdev->priv_flags |= IFF_UNICAST_FLT;
2173
2174         adapter->en_mng_pt = igb_enable_mng_pass_thru(hw);
2175
2176         /* before reading the NVM, reset the controller to put the device in a
2177          * known good starting state
2178          */
2179         hw->mac.ops.reset_hw(hw);
2180
2181         /* make sure the NVM is good , i211/i210 parts can have special NVM
2182          * that doesn't contain a checksum
2183          */
2184         switch (hw->mac.type) {
2185         case e1000_i210:
2186         case e1000_i211:
2187                 if (igb_get_flash_presence_i210(hw)) {
2188                         if (hw->nvm.ops.validate(hw) < 0) {
2189                                 dev_err(&pdev->dev,
2190                                         "The NVM Checksum Is Not Valid\n");
2191                                 err = -EIO;
2192                                 goto err_eeprom;
2193                         }
2194                 }
2195                 break;
2196         default:
2197                 if (hw->nvm.ops.validate(hw) < 0) {
2198                         dev_err(&pdev->dev, "The NVM Checksum Is Not Valid\n");
2199                         err = -EIO;
2200                         goto err_eeprom;
2201                 }
2202                 break;
2203         }
2204
2205         /* copy the MAC address out of the NVM */
2206         if (hw->mac.ops.read_mac_addr(hw))
2207                 dev_err(&pdev->dev, "NVM Read Error\n");
2208
2209         memcpy(netdev->dev_addr, hw->mac.addr, netdev->addr_len);
2210
2211         if (!is_valid_ether_addr(netdev->dev_addr)) {
2212                 dev_err(&pdev->dev, "Invalid MAC Address\n");
2213                 err = -EIO;
2214                 goto err_eeprom;
2215         }
2216
2217         /* get firmware version for ethtool -i */
2218         igb_set_fw_version(adapter);
2219
2220         setup_timer(&adapter->watchdog_timer, igb_watchdog,
2221                     (unsigned long) adapter);
2222         setup_timer(&adapter->phy_info_timer, igb_update_phy_info,
2223                     (unsigned long) adapter);
2224
2225         INIT_WORK(&adapter->reset_task, igb_reset_task);
2226         INIT_WORK(&adapter->watchdog_task, igb_watchdog_task);
2227
2228         /* Initialize link properties that are user-changeable */
2229         adapter->fc_autoneg = true;
2230         hw->mac.autoneg = true;
2231         hw->phy.autoneg_advertised = 0x2f;
2232
2233         hw->fc.requested_mode = e1000_fc_default;
2234         hw->fc.current_mode = e1000_fc_default;
2235
2236         igb_validate_mdi_setting(hw);
2237
2238         /* By default, support wake on port A */
2239         if (hw->bus.func == 0)
2240                 adapter->flags |= IGB_FLAG_WOL_SUPPORTED;
2241
2242         /* Check the NVM for wake support on non-port A ports */
2243         if (hw->mac.type >= e1000_82580)
2244                 hw->nvm.ops.read(hw, NVM_INIT_CONTROL3_PORT_A +
2245                                  NVM_82580_LAN_FUNC_OFFSET(hw->bus.func), 1,
2246                                  &eeprom_data);
2247         else if (hw->bus.func == 1)
2248                 hw->nvm.ops.read(hw, NVM_INIT_CONTROL3_PORT_B, 1, &eeprom_data);
2249
2250         if (eeprom_data & IGB_EEPROM_APME)
2251                 adapter->flags |= IGB_FLAG_WOL_SUPPORTED;
2252
2253         /* now that we have the eeprom settings, apply the special cases where
2254          * the eeprom may be wrong or the board simply won't support wake on
2255          * lan on a particular port
2256          */
2257         switch (pdev->device) {
2258         case E1000_DEV_ID_82575GB_QUAD_COPPER:
2259                 adapter->flags &= ~IGB_FLAG_WOL_SUPPORTED;
2260                 break;
2261         case E1000_DEV_ID_82575EB_FIBER_SERDES:
2262         case E1000_DEV_ID_82576_FIBER:
2263         case E1000_DEV_ID_82576_SERDES:
2264                 /* Wake events only supported on port A for dual fiber
2265                  * regardless of eeprom setting
2266                  */
2267                 if (rd32(E1000_STATUS) & E1000_STATUS_FUNC_1)
2268                         adapter->flags &= ~IGB_FLAG_WOL_SUPPORTED;
2269                 break;
2270         case E1000_DEV_ID_82576_QUAD_COPPER:
2271         case E1000_DEV_ID_82576_QUAD_COPPER_ET2:
2272                 /* if quad port adapter, disable WoL on all but port A */
2273                 if (global_quad_port_a != 0)
2274                         adapter->flags &= ~IGB_FLAG_WOL_SUPPORTED;
2275                 else
2276                         adapter->flags |= IGB_FLAG_QUAD_PORT_A;
2277                 /* Reset for multiple quad port adapters */
2278                 if (++global_quad_port_a == 4)
2279                         global_quad_port_a = 0;
2280                 break;
2281         default:
2282                 /* If the device can't wake, don't set software support */
2283                 if (!device_can_wakeup(&adapter->pdev->dev))
2284                         adapter->flags &= ~IGB_FLAG_WOL_SUPPORTED;
2285         }
2286
2287         /* initialize the wol settings based on the eeprom settings */
2288         if (adapter->flags & IGB_FLAG_WOL_SUPPORTED)
2289                 adapter->wol |= E1000_WUFC_MAG;
2290
2291         /* Some vendors want WoL disabled by default, but still supported */
2292         if ((hw->mac.type == e1000_i350) &&
2293             (pdev->subsystem_vendor == PCI_VENDOR_ID_HP)) {
2294                 adapter->flags |= IGB_FLAG_WOL_SUPPORTED;
2295                 adapter->wol = 0;
2296         }
2297
2298         device_set_wakeup_enable(&adapter->pdev->dev,
2299                                  adapter->flags & IGB_FLAG_WOL_SUPPORTED);
2300
2301         /* reset the hardware with the new settings */
2302         igb_reset(adapter);
2303
2304         /* Init the I2C interface */
2305         err = igb_init_i2c(adapter);
2306         if (err) {
2307                 dev_err(&pdev->dev, "failed to init i2c interface\n");
2308                 goto err_eeprom;
2309         }
2310
2311         /* let the f/w know that the h/w is now under the control of the
2312          * driver. */
2313         igb_get_hw_control(adapter);
2314
2315         strcpy(netdev->name, "eth%d");
2316         err = register_netdev(netdev);
2317         if (err)
2318                 goto err_register;
2319
2320         /* carrier off reporting is important to ethtool even BEFORE open */
2321         netif_carrier_off(netdev);
2322
2323 #ifdef CONFIG_IGB_DCA
2324         if (dca_add_requester(&pdev->dev) == 0) {
2325                 adapter->flags |= IGB_FLAG_DCA_ENABLED;
2326                 dev_info(&pdev->dev, "DCA enabled\n");
2327                 igb_setup_dca(adapter);
2328         }
2329
2330 #endif
2331 #ifdef CONFIG_IGB_HWMON
2332         /* Initialize the thermal sensor on i350 devices. */
2333         if (hw->mac.type == e1000_i350 && hw->bus.func == 0) {
2334                 u16 ets_word;
2335
2336                 /* Read the NVM to determine if this i350 device supports an
2337                  * external thermal sensor.
2338                  */
2339                 hw->nvm.ops.read(hw, NVM_ETS_CFG, 1, &ets_word);
2340                 if (ets_word != 0x0000 && ets_word != 0xFFFF)
2341                         adapter->ets = true;
2342                 else
2343                         adapter->ets = false;
2344                 if (igb_sysfs_init(adapter))
2345                         dev_err(&pdev->dev,
2346                                 "failed to allocate sysfs resources\n");
2347         } else {
2348                 adapter->ets = false;
2349         }
2350 #endif
2351         /* do hw tstamp init after resetting */
2352         igb_ptp_init(adapter);
2353
2354         dev_info(&pdev->dev, "Intel(R) Gigabit Ethernet Network Connection\n");
2355         /* print bus type/speed/width info, not applicable to i354 */
2356         if (hw->mac.type != e1000_i354) {
2357                 dev_info(&pdev->dev, "%s: (PCIe:%s:%s) %pM\n",
2358                          netdev->name,
2359                          ((hw->bus.speed == e1000_bus_speed_2500) ? "2.5Gb/s" :
2360                           (hw->bus.speed == e1000_bus_speed_5000) ? "5.0Gb/s" :
2361                            "unknown"),
2362                          ((hw->bus.width == e1000_bus_width_pcie_x4) ?
2363                           "Width x4" :
2364                           (hw->bus.width == e1000_bus_width_pcie_x2) ?
2365                           "Width x2" :
2366                           (hw->bus.width == e1000_bus_width_pcie_x1) ?
2367                           "Width x1" : "unknown"), netdev->dev_addr);
2368         }
2369
2370         if ((hw->mac.type >= e1000_i210 ||
2371              igb_get_flash_presence_i210(hw))) {
2372                 ret_val = igb_read_part_string(hw, part_str,
2373                                                E1000_PBANUM_LENGTH);
2374         } else {
2375                 ret_val = -E1000_ERR_INVM_VALUE_NOT_FOUND;
2376         }
2377
2378         if (ret_val)
2379                 strcpy(part_str, "Unknown");
2380         dev_info(&pdev->dev, "%s: PBA No: %s\n", netdev->name, part_str);
2381         dev_info(&pdev->dev,
2382                 "Using %s interrupts. %d rx queue(s), %d tx queue(s)\n",
2383                 adapter->msix_entries ? "MSI-X" :
2384                 (adapter->flags & IGB_FLAG_HAS_MSI) ? "MSI" : "legacy",
2385                 adapter->num_rx_queues, adapter->num_tx_queues);
2386         switch (hw->mac.type) {
2387         case e1000_i350:
2388         case e1000_i210:
2389         case e1000_i211:
2390                 igb_set_eee_i350(hw);
2391                 break;
2392         case e1000_i354:
2393                 if (hw->phy.media_type == e1000_media_type_copper) {
2394                         if ((rd32(E1000_CTRL_EXT) &
2395                             E1000_CTRL_EXT_LINK_MODE_SGMII))
2396                                 igb_set_eee_i354(hw);
2397                 }
2398                 break;
2399         default:
2400                 break;
2401         }
2402
2403         pm_runtime_put_noidle(&pdev->dev);
2404         return 0;
2405
2406 err_register:
2407         igb_release_hw_control(adapter);
2408         memset(&adapter->i2c_adap, 0, sizeof(adapter->i2c_adap));
2409 err_eeprom:
2410         if (!igb_check_reset_block(hw))
2411                 igb_reset_phy(hw);
2412
2413         if (hw->flash_address)
2414                 iounmap(hw->flash_address);
2415 err_sw_init:
2416         igb_clear_interrupt_scheme(adapter);
2417         iounmap(hw->hw_addr);
2418 err_ioremap:
2419         free_netdev(netdev);
2420 err_alloc_etherdev:
2421         pci_release_selected_regions(pdev,
2422                                      pci_select_bars(pdev, IORESOURCE_MEM));
2423 err_pci_reg:
2424 err_dma:
2425         pci_disable_device(pdev);
2426         return err;
2427 }
2428
2429 #ifdef CONFIG_PCI_IOV
2430 static int  igb_disable_sriov(struct pci_dev *pdev)
2431 {
2432         struct net_device *netdev = pci_get_drvdata(pdev);
2433         struct igb_adapter *adapter = netdev_priv(netdev);
2434         struct e1000_hw *hw = &adapter->hw;
2435
2436         /* reclaim resources allocated to VFs */
2437         if (adapter->vf_data) {
2438                 /* disable iov and allow time for transactions to clear */
2439                 if (pci_vfs_assigned(pdev)) {
2440                         dev_warn(&pdev->dev,
2441                                  "Cannot deallocate SR-IOV virtual functions while they are assigned - VFs will not be deallocated\n");
2442                         return -EPERM;
2443                 } else {
2444                         pci_disable_sriov(pdev);
2445                         msleep(500);
2446                 }
2447
2448                 kfree(adapter->vf_data);
2449                 adapter->vf_data = NULL;
2450                 adapter->vfs_allocated_count = 0;
2451                 wr32(E1000_IOVCTL, E1000_IOVCTL_REUSE_VFQ);
2452                 wrfl();
2453                 msleep(100);
2454                 dev_info(&pdev->dev, "IOV Disabled\n");
2455
2456                 /* Re-enable DMA Coalescing flag since IOV is turned off */
2457                 adapter->flags |= IGB_FLAG_DMAC;
2458         }
2459
2460         return 0;
2461 }
2462
2463 static int igb_enable_sriov(struct pci_dev *pdev, int num_vfs)
2464 {
2465         struct net_device *netdev = pci_get_drvdata(pdev);
2466         struct igb_adapter *adapter = netdev_priv(netdev);
2467         int old_vfs = pci_num_vf(pdev);
2468         int err = 0;
2469         int i;
2470
2471         if (!adapter->msix_entries) {
2472                 err = -EPERM;
2473                 goto out;
2474         }
2475
2476         if (!num_vfs)
2477                 goto out;
2478         else if (old_vfs && old_vfs == num_vfs)
2479                 goto out;
2480         else if (old_vfs && old_vfs != num_vfs)
2481                 err = igb_disable_sriov(pdev);
2482
2483         if (err)
2484                 goto out;
2485
2486         if (num_vfs > 7) {
2487                 err = -EPERM;
2488                 goto out;
2489         }
2490
2491         adapter->vfs_allocated_count = num_vfs;
2492
2493         adapter->vf_data = kcalloc(adapter->vfs_allocated_count,
2494                                 sizeof(struct vf_data_storage), GFP_KERNEL);
2495
2496         /* if allocation failed then we do not support SR-IOV */
2497         if (!adapter->vf_data) {
2498                 adapter->vfs_allocated_count = 0;
2499                 dev_err(&pdev->dev,
2500                         "Unable to allocate memory for VF Data Storage\n");
2501                 err = -ENOMEM;
2502                 goto out;
2503         }
2504
2505         err = pci_enable_sriov(pdev, adapter->vfs_allocated_count);
2506         if (err)
2507                 goto err_out;
2508
2509         dev_info(&pdev->dev, "%d VFs allocated\n",
2510                  adapter->vfs_allocated_count);
2511         for (i = 0; i < adapter->vfs_allocated_count; i++)
2512                 igb_vf_configure(adapter, i);
2513
2514         /* DMA Coalescing is not supported in IOV mode. */
2515         adapter->flags &= ~IGB_FLAG_DMAC;
2516         goto out;
2517
2518 err_out:
2519         kfree(adapter->vf_data);
2520         adapter->vf_data = NULL;
2521         adapter->vfs_allocated_count = 0;
2522 out:
2523         return err;
2524 }
2525
2526 #endif
2527 /**
2528  *  igb_remove_i2c - Cleanup  I2C interface
2529  *  @adapter: pointer to adapter structure
2530  **/
2531 static void igb_remove_i2c(struct igb_adapter *adapter)
2532 {
2533         /* free the adapter bus structure */
2534         i2c_del_adapter(&adapter->i2c_adap);
2535 }
2536
2537 /**
2538  *  igb_remove - Device Removal Routine
2539  *  @pdev: PCI device information struct
2540  *
2541  *  igb_remove is called by the PCI subsystem to alert the driver
2542  *  that it should release a PCI device.  The could be caused by a
2543  *  Hot-Plug event, or because the driver is going to be removed from
2544  *  memory.
2545  **/
2546 static void igb_remove(struct pci_dev *pdev)
2547 {
2548         struct net_device *netdev = pci_get_drvdata(pdev);
2549         struct igb_adapter *adapter = netdev_priv(netdev);
2550         struct e1000_hw *hw = &adapter->hw;
2551
2552         pm_runtime_get_noresume(&pdev->dev);
2553 #ifdef CONFIG_IGB_HWMON
2554         igb_sysfs_exit(adapter);
2555 #endif
2556         igb_remove_i2c(adapter);
2557         igb_ptp_stop(adapter);
2558         /* The watchdog timer may be rescheduled, so explicitly
2559          * disable watchdog from being rescheduled.
2560          */
2561         set_bit(__IGB_DOWN, &adapter->state);
2562         del_timer_sync(&adapter->watchdog_timer);
2563         del_timer_sync(&adapter->phy_info_timer);
2564
2565         cancel_work_sync(&adapter->reset_task);
2566         cancel_work_sync(&adapter->watchdog_task);
2567
2568 #ifdef CONFIG_IGB_DCA
2569         if (adapter->flags & IGB_FLAG_DCA_ENABLED) {
2570                 dev_info(&pdev->dev, "DCA disabled\n");
2571                 dca_remove_requester(&pdev->dev);
2572                 adapter->flags &= ~IGB_FLAG_DCA_ENABLED;
2573                 wr32(E1000_DCA_CTRL, E1000_DCA_CTRL_DCA_MODE_DISABLE);
2574         }
2575 #endif
2576
2577         /* Release control of h/w to f/w.  If f/w is AMT enabled, this
2578          * would have already happened in close and is redundant.
2579          */
2580         igb_release_hw_control(adapter);
2581
2582         unregister_netdev(netdev);
2583
2584         igb_clear_interrupt_scheme(adapter);
2585
2586 #ifdef CONFIG_PCI_IOV
2587         igb_disable_sriov(pdev);
2588 #endif
2589
2590         iounmap(hw->hw_addr);
2591         if (hw->flash_address)
2592                 iounmap(hw->flash_address);
2593         pci_release_selected_regions(pdev,
2594                                      pci_select_bars(pdev, IORESOURCE_MEM));
2595
2596         kfree(adapter->shadow_vfta);
2597         free_netdev(netdev);
2598
2599         pci_disable_pcie_error_reporting(pdev);
2600
2601         pci_disable_device(pdev);
2602 }
2603
2604 /**
2605  *  igb_probe_vfs - Initialize vf data storage and add VFs to pci config space
2606  *  @adapter: board private structure to initialize
2607  *
2608  *  This function initializes the vf specific data storage and then attempts to
2609  *  allocate the VFs.  The reason for ordering it this way is because it is much
2610  *  mor expensive time wise to disable SR-IOV than it is to allocate and free
2611  *  the memory for the VFs.
2612  **/
2613 static void igb_probe_vfs(struct igb_adapter *adapter)
2614 {
2615 #ifdef CONFIG_PCI_IOV
2616         struct pci_dev *pdev = adapter->pdev;
2617         struct e1000_hw *hw = &adapter->hw;
2618
2619         /* Virtualization features not supported on i210 family. */
2620         if ((hw->mac.type == e1000_i210) || (hw->mac.type == e1000_i211))
2621                 return;
2622
2623         pci_sriov_set_totalvfs(pdev, 7);
2624         igb_enable_sriov(pdev, max_vfs);
2625
2626 #endif /* CONFIG_PCI_IOV */
2627 }
2628
2629 static void igb_init_queue_configuration(struct igb_adapter *adapter)
2630 {
2631         struct e1000_hw *hw = &adapter->hw;
2632         u32 max_rss_queues;
2633
2634         /* Determine the maximum number of RSS queues supported. */
2635         switch (hw->mac.type) {
2636         case e1000_i211:
2637                 max_rss_queues = IGB_MAX_RX_QUEUES_I211;
2638                 break;
2639         case e1000_82575:
2640         case e1000_i210:
2641                 max_rss_queues = IGB_MAX_RX_QUEUES_82575;
2642                 break;
2643         case e1000_i350:
2644                 /* I350 cannot do RSS and SR-IOV at the same time */
2645                 if (!!adapter->vfs_allocated_count) {
2646                         max_rss_queues = 1;
2647                         break;
2648                 }
2649                 /* fall through */
2650         case e1000_82576:
2651                 if (!!adapter->vfs_allocated_count) {
2652                         max_rss_queues = 2;
2653                         break;
2654                 }
2655                 /* fall through */
2656         case e1000_82580:
2657         case e1000_i354:
2658         default:
2659                 max_rss_queues = IGB_MAX_RX_QUEUES;
2660                 break;
2661         }
2662
2663         adapter->rss_queues = min_t(u32, max_rss_queues, num_online_cpus());
2664
2665         /* Determine if we need to pair queues. */
2666         switch (hw->mac.type) {
2667         case e1000_82575:
2668         case e1000_i211:
2669                 /* Device supports enough interrupts without queue pairing. */
2670                 break;
2671         case e1000_82576:
2672                 /* If VFs are going to be allocated with RSS queues then we
2673                  * should pair the queues in order to conserve interrupts due
2674                  * to limited supply.
2675                  */
2676                 if ((adapter->rss_queues > 1) &&
2677                     (adapter->vfs_allocated_count > 6))
2678                         adapter->flags |= IGB_FLAG_QUEUE_PAIRS;
2679                 /* fall through */
2680         case e1000_82580:
2681         case e1000_i350:
2682         case e1000_i354:
2683         case e1000_i210:
2684         default:
2685                 /* If rss_queues > half of max_rss_queues, pair the queues in
2686                  * order to conserve interrupts due to limited supply.
2687                  */
2688                 if (adapter->rss_queues > (max_rss_queues / 2))
2689                         adapter->flags |= IGB_FLAG_QUEUE_PAIRS;
2690                 break;
2691         }
2692 }
2693
2694 /**
2695  *  igb_sw_init - Initialize general software structures (struct igb_adapter)
2696  *  @adapter: board private structure to initialize
2697  *
2698  *  igb_sw_init initializes the Adapter private data structure.
2699  *  Fields are initialized based on PCI device information and
2700  *  OS network device settings (MTU size).
2701  **/
2702 static int igb_sw_init(struct igb_adapter *adapter)
2703 {
2704         struct e1000_hw *hw = &adapter->hw;
2705         struct net_device *netdev = adapter->netdev;
2706         struct pci_dev *pdev = adapter->pdev;
2707
2708         pci_read_config_word(pdev, PCI_COMMAND, &hw->bus.pci_cmd_word);
2709
2710         /* set default ring sizes */
2711         adapter->tx_ring_count = IGB_DEFAULT_TXD;
2712         adapter->rx_ring_count = IGB_DEFAULT_RXD;
2713
2714         /* set default ITR values */
2715         adapter->rx_itr_setting = IGB_DEFAULT_ITR;
2716         adapter->tx_itr_setting = IGB_DEFAULT_ITR;
2717
2718         /* set default work limits */
2719         adapter->tx_work_limit = IGB_DEFAULT_TX_WORK;
2720
2721         adapter->max_frame_size = netdev->mtu + ETH_HLEN + ETH_FCS_LEN +
2722                                   VLAN_HLEN;
2723         adapter->min_frame_size = ETH_ZLEN + ETH_FCS_LEN;
2724
2725         spin_lock_init(&adapter->stats64_lock);
2726 #ifdef CONFIG_PCI_IOV
2727         switch (hw->mac.type) {
2728         case e1000_82576:
2729         case e1000_i350:
2730                 if (max_vfs > 7) {
2731                         dev_warn(&pdev->dev,
2732                                  "Maximum of 7 VFs per PF, using max\n");
2733                         max_vfs = adapter->vfs_allocated_count = 7;
2734                 } else
2735                         adapter->vfs_allocated_count = max_vfs;
2736                 if (adapter->vfs_allocated_count)
2737                         dev_warn(&pdev->dev,
2738                                  "Enabling SR-IOV VFs using the module parameter is deprecated - please use the pci sysfs interface.\n");
2739                 break;
2740         default:
2741                 break;
2742         }
2743 #endif /* CONFIG_PCI_IOV */
2744
2745         igb_init_queue_configuration(adapter);
2746
2747         /* Setup and initialize a copy of the hw vlan table array */
2748         adapter->shadow_vfta = kcalloc(E1000_VLAN_FILTER_TBL_SIZE, sizeof(u32),
2749                                        GFP_ATOMIC);
2750
2751         /* This call may decrease the number of queues */
2752         if (igb_init_interrupt_scheme(adapter, true)) {
2753                 dev_err(&pdev->dev, "Unable to allocate memory for queues\n");
2754                 return -ENOMEM;
2755         }
2756
2757         igb_probe_vfs(adapter);
2758
2759         /* Explicitly disable IRQ since the NIC can be in any state. */
2760         igb_irq_disable(adapter);
2761
2762         if (hw->mac.type >= e1000_i350)
2763                 adapter->flags &= ~IGB_FLAG_DMAC;
2764
2765         set_bit(__IGB_DOWN, &adapter->state);
2766         return 0;
2767 }
2768
2769 /**
2770  *  igb_open - Called when a network interface is made active
2771  *  @netdev: network interface device structure
2772  *
2773  *  Returns 0 on success, negative value on failure
2774  *
2775  *  The open entry point is called when a network interface is made
2776  *  active by the system (IFF_UP).  At this point all resources needed
2777  *  for transmit and receive operations are allocated, the interrupt
2778  *  handler is registered with the OS, the watchdog timer is started,
2779  *  and the stack is notified that the interface is ready.
2780  **/
2781 static int __igb_open(struct net_device *netdev, bool resuming)
2782 {
2783         struct igb_adapter *adapter = netdev_priv(netdev);
2784         struct e1000_hw *hw = &adapter->hw;
2785         struct pci_dev *pdev = adapter->pdev;
2786         int err;
2787         int i;
2788
2789         /* disallow open during test */
2790         if (test_bit(__IGB_TESTING, &adapter->state)) {
2791                 WARN_ON(resuming);
2792                 return -EBUSY;
2793         }
2794
2795         if (!resuming)
2796                 pm_runtime_get_sync(&pdev->dev);
2797
2798         netif_carrier_off(netdev);
2799
2800         /* allocate transmit descriptors */
2801         err = igb_setup_all_tx_resources(adapter);
2802         if (err)
2803                 goto err_setup_tx;
2804
2805         /* allocate receive descriptors */
2806         err = igb_setup_all_rx_resources(adapter);
2807         if (err)
2808                 goto err_setup_rx;
2809
2810         igb_power_up_link(adapter);
2811
2812         /* before we allocate an interrupt, we must be ready to handle it.
2813          * Setting DEBUG_SHIRQ in the kernel makes it fire an interrupt
2814          * as soon as we call pci_request_irq, so we have to setup our
2815          * clean_rx handler before we do so.
2816          */
2817         igb_configure(adapter);
2818
2819         err = igb_request_irq(adapter);
2820         if (err)
2821                 goto err_req_irq;
2822
2823         /* Notify the stack of the actual queue counts. */
2824         err = netif_set_real_num_tx_queues(adapter->netdev,
2825                                            adapter->num_tx_queues);
2826         if (err)
2827                 goto err_set_queues;
2828
2829         err = netif_set_real_num_rx_queues(adapter->netdev,
2830                                            adapter->num_rx_queues);
2831         if (err)
2832                 goto err_set_queues;
2833
2834         /* From here on the code is the same as igb_up() */
2835         clear_bit(__IGB_DOWN, &adapter->state);
2836
2837         for (i = 0; i < adapter->num_q_vectors; i++)
2838                 napi_enable(&(adapter->q_vector[i]->napi));
2839
2840         /* Clear any pending interrupts. */
2841         rd32(E1000_ICR);
2842
2843         igb_irq_enable(adapter);
2844
2845         /* notify VFs that reset has been completed */
2846         if (adapter->vfs_allocated_count) {
2847                 u32 reg_data = rd32(E1000_CTRL_EXT);
2848                 reg_data |= E1000_CTRL_EXT_PFRSTD;
2849                 wr32(E1000_CTRL_EXT, reg_data);
2850         }
2851
2852         netif_tx_start_all_queues(netdev);
2853
2854         if (!resuming)
2855                 pm_runtime_put(&pdev->dev);
2856
2857         /* start the watchdog. */
2858         hw->mac.get_link_status = 1;
2859         schedule_work(&adapter->watchdog_task);
2860
2861         return 0;
2862
2863 err_set_queues:
2864         igb_free_irq(adapter);
2865 err_req_irq:
2866         igb_release_hw_control(adapter);
2867         igb_power_down_link(adapter);
2868         igb_free_all_rx_resources(adapter);
2869 err_setup_rx:
2870         igb_free_all_tx_resources(adapter);
2871 err_setup_tx:
2872         igb_reset(adapter);
2873         if (!resuming)
2874                 pm_runtime_put(&pdev->dev);
2875
2876         return err;
2877 }
2878
2879 static int igb_open(struct net_device *netdev)
2880 {
2881         return __igb_open(netdev, false);
2882 }
2883
2884 /**
2885  *  igb_close - Disables a network interface
2886  *  @netdev: network interface device structure
2887  *
2888  *  Returns 0, this is not allowed to fail
2889  *
2890  *  The close entry point is called when an interface is de-activated
2891  *  by the OS.  The hardware is still under the driver's control, but
2892  *  needs to be disabled.  A global MAC reset is issued to stop the
2893  *  hardware, and all transmit and receive resources are freed.
2894  **/
2895 static int __igb_close(struct net_device *netdev, bool suspending)
2896 {
2897         struct igb_adapter *adapter = netdev_priv(netdev);
2898         struct pci_dev *pdev = adapter->pdev;
2899
2900         WARN_ON(test_bit(__IGB_RESETTING, &adapter->state));
2901
2902         if (!suspending)
2903                 pm_runtime_get_sync(&pdev->dev);
2904
2905         igb_down(adapter);
2906         igb_free_irq(adapter);
2907
2908         igb_free_all_tx_resources(adapter);
2909         igb_free_all_rx_resources(adapter);
2910
2911         if (!suspending)
2912                 pm_runtime_put_sync(&pdev->dev);
2913         return 0;
2914 }
2915
2916 static int igb_close(struct net_device *netdev)
2917 {
2918         return __igb_close(netdev, false);
2919 }
2920
2921 /**
2922  *  igb_setup_tx_resources - allocate Tx resources (Descriptors)
2923  *  @tx_ring: tx descriptor ring (for a specific queue) to setup
2924  *
2925  *  Return 0 on success, negative on failure
2926  **/
2927 int igb_setup_tx_resources(struct igb_ring *tx_ring)
2928 {
2929         struct device *dev = tx_ring->dev;
2930         int size;
2931
2932         size = sizeof(struct igb_tx_buffer) * tx_ring->count;
2933
2934         tx_ring->tx_buffer_info = vzalloc(size);
2935         if (!tx_ring->tx_buffer_info)
2936                 goto err;
2937
2938         /* round up to nearest 4K */
2939         tx_ring->size = tx_ring->count * sizeof(union e1000_adv_tx_desc);
2940         tx_ring->size = ALIGN(tx_ring->size, 4096);
2941
2942         tx_ring->desc = dma_alloc_coherent(dev, tx_ring->size,
2943                                            &tx_ring->dma, GFP_KERNEL);
2944         if (!tx_ring->desc)
2945                 goto err;
2946
2947         tx_ring->next_to_use = 0;
2948         tx_ring->next_to_clean = 0;
2949
2950         return 0;
2951
2952 err:
2953         vfree(tx_ring->tx_buffer_info);
2954         tx_ring->tx_buffer_info = NULL;
2955         dev_err(dev, "Unable to allocate memory for the Tx descriptor ring\n");
2956         return -ENOMEM;
2957 }
2958
2959 /**
2960  *  igb_setup_all_tx_resources - wrapper to allocate Tx resources
2961  *                               (Descriptors) for all queues
2962  *  @adapter: board private structure
2963  *
2964  *  Return 0 on success, negative on failure
2965  **/
2966 static int igb_setup_all_tx_resources(struct igb_adapter *adapter)
2967 {
2968         struct pci_dev *pdev = adapter->pdev;
2969         int i, err = 0;
2970
2971         for (i = 0; i < adapter->num_tx_queues; i++) {
2972                 err = igb_setup_tx_resources(adapter->tx_ring[i]);
2973                 if (err) {
2974                         dev_err(&pdev->dev,
2975                                 "Allocation for Tx Queue %u failed\n", i);
2976                         for (i--; i >= 0; i--)
2977                                 igb_free_tx_resources(adapter->tx_ring[i]);
2978                         break;
2979                 }
2980         }
2981
2982         return err;
2983 }
2984
2985 /**
2986  *  igb_setup_tctl - configure the transmit control registers
2987  *  @adapter: Board private structure
2988  **/
2989 void igb_setup_tctl(struct igb_adapter *adapter)
2990 {
2991         struct e1000_hw *hw = &adapter->hw;
2992         u32 tctl;
2993
2994         /* disable queue 0 which is enabled by default on 82575 and 82576 */
2995         wr32(E1000_TXDCTL(0), 0);
2996
2997         /* Program the Transmit Control Register */
2998         tctl = rd32(E1000_TCTL);
2999         tctl &= ~E1000_TCTL_CT;
3000         tctl |= E1000_TCTL_PSP | E1000_TCTL_RTLC |
3001                 (E1000_COLLISION_THRESHOLD << E1000_CT_SHIFT);
3002
3003         igb_config_collision_dist(hw);
3004
3005         /* Enable transmits */
3006         tctl |= E1000_TCTL_EN;
3007
3008         wr32(E1000_TCTL, tctl);
3009 }
3010
3011 /**
3012  *  igb_configure_tx_ring - Configure transmit ring after Reset
3013  *  @adapter: board private structure
3014  *  @ring: tx ring to configure
3015  *
3016  *  Configure a transmit ring after a reset.
3017  **/
3018 void igb_configure_tx_ring(struct igb_adapter *adapter,
3019                            struct igb_ring *ring)
3020 {
3021         struct e1000_hw *hw = &adapter->hw;
3022         u32 txdctl = 0;
3023         u64 tdba = ring->dma;
3024         int reg_idx = ring->reg_idx;
3025
3026         /* disable the queue */
3027         wr32(E1000_TXDCTL(reg_idx), 0);
3028         wrfl();
3029         mdelay(10);
3030
3031         wr32(E1000_TDLEN(reg_idx),
3032              ring->count * sizeof(union e1000_adv_tx_desc));
3033         wr32(E1000_TDBAL(reg_idx),
3034              tdba & 0x00000000ffffffffULL);
3035         wr32(E1000_TDBAH(reg_idx), tdba >> 32);
3036
3037         ring->tail = hw->hw_addr + E1000_TDT(reg_idx);
3038         wr32(E1000_TDH(reg_idx), 0);
3039         writel(0, ring->tail);
3040
3041         txdctl |= IGB_TX_PTHRESH;
3042         txdctl |= IGB_TX_HTHRESH << 8;
3043         txdctl |= IGB_TX_WTHRESH << 16;
3044
3045         txdctl |= E1000_TXDCTL_QUEUE_ENABLE;
3046         wr32(E1000_TXDCTL(reg_idx), txdctl);
3047 }
3048
3049 /**
3050  *  igb_configure_tx - Configure transmit Unit after Reset
3051  *  @adapter: board private structure
3052  *
3053  *  Configure the Tx unit of the MAC after a reset.
3054  **/
3055 static void igb_configure_tx(struct igb_adapter *adapter)
3056 {
3057         int i;
3058
3059         for (i = 0; i < adapter->num_tx_queues; i++)
3060                 igb_configure_tx_ring(adapter, adapter->tx_ring[i]);
3061 }
3062
3063 /**
3064  *  igb_setup_rx_resources - allocate Rx resources (Descriptors)
3065  *  @rx_ring: Rx descriptor ring (for a specific queue) to setup
3066  *
3067  *  Returns 0 on success, negative on failure
3068  **/
3069 int igb_setup_rx_resources(struct igb_ring *rx_ring)
3070 {
3071         struct device *dev = rx_ring->dev;
3072         int size;
3073
3074         size = sizeof(struct igb_rx_buffer) * rx_ring->count;
3075
3076         rx_ring->rx_buffer_info = vzalloc(size);
3077         if (!rx_ring->rx_buffer_info)
3078                 goto err;
3079
3080         /* Round up to nearest 4K */
3081         rx_ring->size = rx_ring->count * sizeof(union e1000_adv_rx_desc);
3082         rx_ring->size = ALIGN(rx_ring->size, 4096);
3083
3084         rx_ring->desc = dma_alloc_coherent(dev, rx_ring->size,
3085                                            &rx_ring->dma, GFP_KERNEL);
3086         if (!rx_ring->desc)
3087                 goto err;
3088
3089         rx_ring->next_to_alloc = 0;
3090         rx_ring->next_to_clean = 0;
3091         rx_ring->next_to_use = 0;
3092
3093         return 0;
3094
3095 err:
3096         vfree(rx_ring->rx_buffer_info);
3097         rx_ring->rx_buffer_info = NULL;
3098         dev_err(dev, "Unable to allocate memory for the Rx descriptor ring\n");
3099         return -ENOMEM;
3100 }
3101
3102 /**
3103  *  igb_setup_all_rx_resources - wrapper to allocate Rx resources
3104  *                               (Descriptors) for all queues
3105  *  @adapter: board private structure
3106  *
3107  *  Return 0 on success, negative on failure
3108  **/
3109 static int igb_setup_all_rx_resources(struct igb_adapter *adapter)
3110 {
3111         struct pci_dev *pdev = adapter->pdev;
3112         int i, err = 0;
3113
3114         for (i = 0; i < adapter->num_rx_queues; i++) {
3115                 err = igb_setup_rx_resources(adapter->rx_ring[i]);
3116                 if (err) {
3117                         dev_err(&pdev->dev,
3118                                 "Allocation for Rx Queue %u failed\n", i);
3119                         for (i--; i >= 0; i--)
3120                                 igb_free_rx_resources(adapter->rx_ring[i]);
3121                         break;
3122                 }
3123         }
3124
3125         return err;
3126 }
3127
3128 /**
3129  *  igb_setup_mrqc - configure the multiple receive queue control registers
3130  *  @adapter: Board private structure
3131  **/
3132 static void igb_setup_mrqc(struct igb_adapter *adapter)
3133 {
3134         struct e1000_hw *hw = &adapter->hw;
3135         u32 mrqc, rxcsum;
3136         u32 j, num_rx_queues;
3137         static const u32 rsskey[10] = { 0xDA565A6D, 0xC20E5B25, 0x3D256741,
3138                                         0xB08FA343, 0xCB2BCAD0, 0xB4307BAE,
3139                                         0xA32DCB77, 0x0CF23080, 0x3BB7426A,
3140                                         0xFA01ACBE };
3141
3142         /* Fill out hash function seeds */
3143         for (j = 0; j < 10; j++)
3144                 wr32(E1000_RSSRK(j), rsskey[j]);
3145
3146         num_rx_queues = adapter->rss_queues;
3147
3148         switch (hw->mac.type) {
3149         case e1000_82576:
3150                 /* 82576 supports 2 RSS queues for SR-IOV */
3151                 if (adapter->vfs_allocated_count)
3152                         num_rx_queues = 2;
3153                 break;
3154         default:
3155                 break;
3156         }
3157
3158         if (adapter->rss_indir_tbl_init != num_rx_queues) {
3159                 for (j = 0; j < IGB_RETA_SIZE; j++)
3160                         adapter->rss_indir_tbl[j] = (j * num_rx_queues) / IGB_RETA_SIZE;
3161                 adapter->rss_indir_tbl_init = num_rx_queues;
3162         }
3163         igb_write_rss_indir_tbl(adapter);
3164
3165         /* Disable raw packet checksumming so that RSS hash is placed in
3166          * descriptor on writeback.  No need to enable TCP/UDP/IP checksum
3167          * offloads as they are enabled by default
3168          */
3169         rxcsum = rd32(E1000_RXCSUM);
3170         rxcsum |= E1000_RXCSUM_PCSD;
3171
3172         if (adapter->hw.mac.type >= e1000_82576)
3173                 /* Enable Receive Checksum Offload for SCTP */
3174                 rxcsum |= E1000_RXCSUM_CRCOFL;
3175
3176         /* Don't need to set TUOFL or IPOFL, they default to 1 */
3177         wr32(E1000_RXCSUM, rxcsum);
3178
3179         /* Generate RSS hash based on packet types, TCP/UDP
3180          * port numbers and/or IPv4/v6 src and dst addresses
3181          */
3182         mrqc = E1000_MRQC_RSS_FIELD_IPV4 |
3183                E1000_MRQC_RSS_FIELD_IPV4_TCP |
3184                E1000_MRQC_RSS_FIELD_IPV6 |
3185                E1000_MRQC_RSS_FIELD_IPV6_TCP |
3186                E1000_MRQC_RSS_FIELD_IPV6_TCP_EX;
3187
3188         if (adapter->flags & IGB_FLAG_RSS_FIELD_IPV4_UDP)
3189                 mrqc |= E1000_MRQC_RSS_FIELD_IPV4_UDP;
3190         if (adapter->flags & IGB_FLAG_RSS_FIELD_IPV6_UDP)
3191                 mrqc |= E1000_MRQC_RSS_FIELD_IPV6_UDP;
3192
3193         /* If VMDq is enabled then we set the appropriate mode for that, else
3194          * we default to RSS so that an RSS hash is calculated per packet even
3195          * if we are only using one queue
3196          */
3197         if (adapter->vfs_allocated_count) {
3198                 if (hw->mac.type > e1000_82575) {
3199                         /* Set the default pool for the PF's first queue */
3200                         u32 vtctl = rd32(E1000_VT_CTL);
3201                         vtctl &= ~(E1000_VT_CTL_DEFAULT_POOL_MASK |
3202                                    E1000_VT_CTL_DISABLE_DEF_POOL);
3203                         vtctl |= adapter->vfs_allocated_count <<
3204                                 E1000_VT_CTL_DEFAULT_POOL_SHIFT;
3205                         wr32(E1000_VT_CTL, vtctl);
3206                 }
3207                 if (adapter->rss_queues > 1)
3208                         mrqc |= E1000_MRQC_ENABLE_VMDQ_RSS_2Q;
3209                 else
3210                         mrqc |= E1000_MRQC_ENABLE_VMDQ;
3211         } else {
3212                 if (hw->mac.type != e1000_i211)
3213                         mrqc |= E1000_MRQC_ENABLE_RSS_4Q;
3214         }
3215         igb_vmm_control(adapter);
3216
3217         wr32(E1000_MRQC, mrqc);
3218 }
3219
3220 /**
3221  *  igb_setup_rctl - configure the receive control registers
3222  *  @adapter: Board private structure
3223  **/
3224 void igb_setup_rctl(struct igb_adapter *adapter)
3225 {
3226         struct e1000_hw *hw = &adapter->hw;
3227         u32 rctl;
3228
3229         rctl = rd32(E1000_RCTL);
3230
3231         rctl &= ~(3 << E1000_RCTL_MO_SHIFT);
3232         rctl &= ~(E1000_RCTL_LBM_TCVR | E1000_RCTL_LBM_MAC);
3233
3234         rctl |= E1000_RCTL_EN | E1000_RCTL_BAM | E1000_RCTL_RDMTS_HALF |
3235                 (hw->mac.mc_filter_type << E1000_RCTL_MO_SHIFT);
3236
3237         /* enable stripping of CRC. It's unlikely this will break BMC
3238          * redirection as it did with e1000. Newer features require
3239          * that the HW strips the CRC.
3240          */
3241         rctl |= E1000_RCTL_SECRC;
3242
3243         /* disable store bad packets and clear size bits. */
3244         rctl &= ~(E1000_RCTL_SBP | E1000_RCTL_SZ_256);
3245
3246         /* enable LPE to prevent packets larger than max_frame_size */
3247         rctl |= E1000_RCTL_LPE;
3248
3249         /* disable queue 0 to prevent tail write w/o re-config */
3250         wr32(E1000_RXDCTL(0), 0);
3251
3252         /* Attention!!!  For SR-IOV PF driver operations you must enable
3253          * queue drop for all VF and PF queues to prevent head of line blocking
3254          * if an un-trusted VF does not provide descriptors to hardware.
3255          */
3256         if (adapter->vfs_allocated_count) {
3257                 /* set all queue drop enable bits */
3258                 wr32(E1000_QDE, ALL_QUEUES);
3259         }
3260
3261         /* This is useful for sniffing bad packets. */
3262         if (adapter->netdev->features & NETIF_F_RXALL) {
3263                 /* UPE and MPE will be handled by normal PROMISC logic
3264                  * in e1000e_set_rx_mode
3265                  */
3266                 rctl |= (E1000_RCTL_SBP | /* Receive bad packets */
3267                          E1000_RCTL_BAM | /* RX All Bcast Pkts */
3268                          E1000_RCTL_PMCF); /* RX All MAC Ctrl Pkts */
3269
3270                 rctl &= ~(E1000_RCTL_VFE | /* Disable VLAN filter */
3271                           E1000_RCTL_DPF | /* Allow filtered pause */
3272                           E1000_RCTL_CFIEN); /* Dis VLAN CFIEN Filter */
3273                 /* Do not mess with E1000_CTRL_VME, it affects transmit as well,
3274                  * and that breaks VLANs.
3275                  */
3276         }
3277
3278         wr32(E1000_RCTL, rctl);
3279 }
3280
3281 static inline int igb_set_vf_rlpml(struct igb_adapter *adapter, int size,
3282                                    int vfn)
3283 {
3284         struct e1000_hw *hw = &adapter->hw;
3285         u32 vmolr;
3286
3287         /* if it isn't the PF check to see if VFs are enabled and
3288          * increase the size to support vlan tags
3289          */
3290         if (vfn < adapter->vfs_allocated_count &&
3291             adapter->vf_data[vfn].vlans_enabled)
3292                 size += VLAN_TAG_SIZE;
3293
3294         vmolr = rd32(E1000_VMOLR(vfn));
3295         vmolr &= ~E1000_VMOLR_RLPML_MASK;
3296         vmolr |= size | E1000_VMOLR_LPE;
3297         wr32(E1000_VMOLR(vfn), vmolr);
3298
3299         return 0;
3300 }
3301
3302 /**
3303  *  igb_rlpml_set - set maximum receive packet size
3304  *  @adapter: board private structure
3305  *
3306  *  Configure maximum receivable packet size.
3307  **/
3308 static void igb_rlpml_set(struct igb_adapter *adapter)
3309 {
3310         u32 max_frame_size = adapter->max_frame_size;
3311         struct e1000_hw *hw = &adapter->hw;
3312         u16 pf_id = adapter->vfs_allocated_count;
3313
3314         if (pf_id) {
3315                 igb_set_vf_rlpml(adapter, max_frame_size, pf_id);
3316                 /* If we're in VMDQ or SR-IOV mode, then set global RLPML
3317                  * to our max jumbo frame size, in case we need to enable
3318                  * jumbo frames on one of the rings later.
3319                  * This will not pass over-length frames into the default
3320                  * queue because it's gated by the VMOLR.RLPML.
3321                  */
3322                 max_frame_size = MAX_JUMBO_FRAME_SIZE;
3323         }
3324
3325         wr32(E1000_RLPML, max_frame_size);
3326 }
3327
3328 static inline void igb_set_vmolr(struct igb_adapter *adapter,
3329                                  int vfn, bool aupe)
3330 {
3331         struct e1000_hw *hw = &adapter->hw;
3332         u32 vmolr;
3333
3334         /* This register exists only on 82576 and newer so if we are older then
3335          * we should exit and do nothing
3336          */
3337         if (hw->mac.type < e1000_82576)
3338                 return;
3339
3340         vmolr = rd32(E1000_VMOLR(vfn));
3341         vmolr |= E1000_VMOLR_STRVLAN; /* Strip vlan tags */
3342         if (aupe)
3343                 vmolr |= E1000_VMOLR_AUPE; /* Accept untagged packets */
3344         else
3345                 vmolr &= ~(E1000_VMOLR_AUPE); /* Tagged packets ONLY */
3346
3347         /* clear all bits that might not be set */
3348         vmolr &= ~(E1000_VMOLR_BAM | E1000_VMOLR_RSSE);
3349
3350         if (adapter->rss_queues > 1 && vfn == adapter->vfs_allocated_count)
3351                 vmolr |= E1000_VMOLR_RSSE; /* enable RSS */
3352         /* for VMDq only allow the VFs and pool 0 to accept broadcast and
3353          * multicast packets
3354          */
3355         if (vfn <= adapter->vfs_allocated_count)
3356                 vmolr |= E1000_VMOLR_BAM; /* Accept broadcast */
3357
3358         wr32(E1000_VMOLR(vfn), vmolr);
3359 }
3360
3361 /**
3362  *  igb_configure_rx_ring - Configure a receive ring after Reset
3363  *  @adapter: board private structure
3364  *  @ring: receive ring to be configured
3365  *
3366  *  Configure the Rx unit of the MAC after a reset.
3367  **/
3368 void igb_configure_rx_ring(struct igb_adapter *adapter,
3369                            struct igb_ring *ring)
3370 {
3371         struct e1000_hw *hw = &adapter->hw;
3372         u64 rdba = ring->dma;
3373         int reg_idx = ring->reg_idx;
3374         u32 srrctl = 0, rxdctl = 0;
3375
3376         /* disable the queue */
3377         wr32(E1000_RXDCTL(reg_idx), 0);
3378
3379         /* Set DMA base address registers */
3380         wr32(E1000_RDBAL(reg_idx),
3381              rdba & 0x00000000ffffffffULL);
3382         wr32(E1000_RDBAH(reg_idx), rdba >> 32);
3383         wr32(E1000_RDLEN(reg_idx),
3384              ring->count * sizeof(union e1000_adv_rx_desc));
3385
3386         /* initialize head and tail */
3387         ring->tail = hw->hw_addr + E1000_RDT(reg_idx);
3388         wr32(E1000_RDH(reg_idx), 0);
3389         writel(0, ring->tail);
3390
3391         /* set descriptor configuration */
3392         srrctl = IGB_RX_HDR_LEN << E1000_SRRCTL_BSIZEHDRSIZE_SHIFT;
3393         srrctl |= IGB_RX_BUFSZ >> E1000_SRRCTL_BSIZEPKT_SHIFT;
3394         srrctl |= E1000_SRRCTL_DESCTYPE_ADV_ONEBUF;
3395         if (hw->mac.type >= e1000_82580)
3396                 srrctl |= E1000_SRRCTL_TIMESTAMP;
3397         /* Only set Drop Enable if we are supporting multiple queues */
3398         if (adapter->vfs_allocated_count || adapter->num_rx_queues > 1)
3399                 srrctl |= E1000_SRRCTL_DROP_EN;
3400
3401         wr32(E1000_SRRCTL(reg_idx), srrctl);
3402
3403         /* set filtering for VMDQ pools */
3404         igb_set_vmolr(adapter, reg_idx & 0x7, true);
3405
3406         rxdctl |= IGB_RX_PTHRESH;
3407         rxdctl |= IGB_RX_HTHRESH << 8;
3408         rxdctl |= IGB_RX_WTHRESH << 16;
3409
3410         /* enable receive descriptor fetching */
3411         rxdctl |= E1000_RXDCTL_QUEUE_ENABLE;
3412         wr32(E1000_RXDCTL(reg_idx), rxdctl);
3413 }
3414
3415 /**
3416  *  igb_configure_rx - Configure receive Unit after Reset
3417  *  @adapter: board private structure
3418  *
3419  *  Configure the Rx unit of the MAC after a reset.
3420  **/
3421 static void igb_configure_rx(struct igb_adapter *adapter)
3422 {
3423         int i;
3424
3425         /* set UTA to appropriate mode */
3426         igb_set_uta(adapter);
3427
3428         /* set the correct pool for the PF default MAC address in entry 0 */
3429         igb_rar_set_qsel(adapter, adapter->hw.mac.addr, 0,
3430                          adapter->vfs_allocated_count);
3431
3432         /* Setup the HW Rx Head and Tail Descriptor Pointers and
3433          * the Base and Length of the Rx Descriptor Ring
3434          */
3435         for (i = 0; i < adapter->num_rx_queues; i++)
3436                 igb_configure_rx_ring(adapter, adapter->rx_ring[i]);
3437 }
3438
3439 /**
3440  *  igb_free_tx_resources - Free Tx Resources per Queue
3441  *  @tx_ring: Tx descriptor ring for a specific queue
3442  *
3443  *  Free all transmit software resources
3444  **/
3445 void igb_free_tx_resources(struct igb_ring *tx_ring)
3446 {
3447         igb_clean_tx_ring(tx_ring);
3448
3449         vfree(tx_ring->tx_buffer_info);
3450         tx_ring->tx_buffer_info = NULL;
3451
3452         /* if not set, then don't free */
3453         if (!tx_ring->desc)
3454                 return;
3455
3456         dma_free_coherent(tx_ring->dev, tx_ring->size,
3457                           tx_ring->desc, tx_ring->dma);
3458
3459         tx_ring->desc = NULL;
3460 }
3461
3462 /**
3463  *  igb_free_all_tx_resources - Free Tx Resources for All Queues
3464  *  @adapter: board private structure
3465  *
3466  *  Free all transmit software resources
3467  **/
3468 static void igb_free_all_tx_resources(struct igb_adapter *adapter)
3469 {
3470         int i;
3471
3472         for (i = 0; i < adapter->num_tx_queues; i++)
3473                 igb_free_tx_resources(adapter->tx_ring[i]);
3474 }
3475
3476 void igb_unmap_and_free_tx_resource(struct igb_ring *ring,
3477                                     struct igb_tx_buffer *tx_buffer)
3478 {
3479         if (tx_buffer->skb) {
3480                 dev_kfree_skb_any(tx_buffer->skb);
3481                 if (dma_unmap_len(tx_buffer, len))
3482                         dma_unmap_single(ring->dev,
3483                                          dma_unmap_addr(tx_buffer, dma),
3484                                          dma_unmap_len(tx_buffer, len),
3485                                          DMA_TO_DEVICE);
3486         } else if (dma_unmap_len(tx_buffer, len)) {
3487                 dma_unmap_page(ring->dev,
3488                                dma_unmap_addr(tx_buffer, dma),
3489                                dma_unmap_len(tx_buffer, len),
3490                                DMA_TO_DEVICE);
3491         }
3492         tx_buffer->next_to_watch = NULL;
3493         tx_buffer->skb = NULL;
3494         dma_unmap_len_set(tx_buffer, len, 0);
3495         /* buffer_info must be completely set up in the transmit path */
3496 }
3497
3498 /**
3499  *  igb_clean_tx_ring - Free Tx Buffers
3500  *  @tx_ring: ring to be cleaned
3501  **/
3502 static void igb_clean_tx_ring(struct igb_ring *tx_ring)
3503 {
3504         struct igb_tx_buffer *buffer_info;
3505         unsigned long size;
3506         u16 i;
3507
3508         if (!tx_ring->tx_buffer_info)
3509                 return;
3510         /* Free all the Tx ring sk_buffs */
3511
3512         for (i = 0; i < tx_ring->count; i++) {
3513                 buffer_info = &tx_ring->tx_buffer_info[i];
3514                 igb_unmap_and_free_tx_resource(tx_ring, buffer_info);
3515         }
3516
3517         netdev_tx_reset_queue(txring_txq(tx_ring));
3518
3519         size = sizeof(struct igb_tx_buffer) * tx_ring->count;
3520         memset(tx_ring->tx_buffer_info, 0, size);
3521
3522         /* Zero out the descriptor ring */
3523         memset(tx_ring->desc, 0, tx_ring->size);
3524
3525         tx_ring->next_to_use = 0;
3526         tx_ring->next_to_clean = 0;
3527 }
3528
3529 /**
3530  *  igb_clean_all_tx_rings - Free Tx Buffers for all queues
3531  *  @adapter: board private structure
3532  **/
3533 static void igb_clean_all_tx_rings(struct igb_adapter *adapter)
3534 {
3535         int i;
3536
3537         for (i = 0; i < adapter->num_tx_queues; i++)
3538                 igb_clean_tx_ring(adapter->tx_ring[i]);
3539 }
3540
3541 /**
3542  *  igb_free_rx_resources - Free Rx Resources
3543  *  @rx_ring: ring to clean the resources from
3544  *
3545  *  Free all receive software resources
3546  **/
3547 void igb_free_rx_resources(struct igb_ring *rx_ring)
3548 {
3549         igb_clean_rx_ring(rx_ring);
3550
3551         vfree(rx_ring->rx_buffer_info);
3552         rx_ring->rx_buffer_info = NULL;
3553
3554         /* if not set, then don't free */
3555         if (!rx_ring->desc)
3556                 return;
3557
3558         dma_free_coherent(rx_ring->dev, rx_ring->size,
3559                           rx_ring->desc, rx_ring->dma);
3560
3561         rx_ring->desc = NULL;
3562 }
3563
3564 /**
3565  *  igb_free_all_rx_resources - Free Rx Resources for All Queues
3566  *  @adapter: board private structure
3567  *
3568  *  Free all receive software resources
3569  **/
3570 static void igb_free_all_rx_resources(struct igb_adapter *adapter)
3571 {
3572         int i;
3573
3574         for (i = 0; i < adapter->num_rx_queues; i++)
3575                 igb_free_rx_resources(adapter->rx_ring[i]);
3576 }
3577
3578 /**
3579  *  igb_clean_rx_ring - Free Rx Buffers per Queue
3580  *  @rx_ring: ring to free buffers from
3581  **/
3582 static void igb_clean_rx_ring(struct igb_ring *rx_ring)
3583 {
3584         unsigned long size;
3585         u16 i;
3586
3587         if (rx_ring->skb)
3588                 dev_kfree_skb(rx_ring->skb);
3589         rx_ring->skb = NULL;
3590
3591         if (!rx_ring->rx_buffer_info)
3592                 return;
3593
3594         /* Free all the Rx ring sk_buffs */
3595         for (i = 0; i < rx_ring->count; i++) {
3596                 struct igb_rx_buffer *buffer_info = &rx_ring->rx_buffer_info[i];
3597
3598                 if (!buffer_info->page)
3599                         continue;
3600
3601                 dma_unmap_page(rx_ring->dev,
3602                                buffer_info->dma,
3603                                PAGE_SIZE,
3604                                DMA_FROM_DEVICE);
3605                 __free_page(buffer_info->page);
3606
3607                 buffer_info->page = NULL;
3608         }
3609
3610         size = sizeof(struct igb_rx_buffer) * rx_ring->count;
3611         memset(rx_ring->rx_buffer_info, 0, size);
3612
3613         /* Zero out the descriptor ring */
3614         memset(rx_ring->desc, 0, rx_ring->size);
3615
3616         rx_ring->next_to_alloc = 0;
3617         rx_ring->next_to_clean = 0;
3618         rx_ring->next_to_use = 0;
3619 }
3620
3621 /**
3622  *  igb_clean_all_rx_rings - Free Rx Buffers for all queues
3623  *  @adapter: board private structure
3624  **/
3625 static void igb_clean_all_rx_rings(struct igb_adapter *adapter)
3626 {
3627         int i;
3628
3629         for (i = 0; i < adapter->num_rx_queues; i++)
3630                 igb_clean_rx_ring(adapter->rx_ring[i]);
3631 }
3632
3633 /**
3634  *  igb_set_mac - Change the Ethernet Address of the NIC
3635  *  @netdev: network interface device structure
3636  *  @p: pointer to an address structure
3637  *
3638  *  Returns 0 on success, negative on failure
3639  **/
3640 static int igb_set_mac(struct net_device *netdev, void *p)
3641 {
3642         struct igb_adapter *adapter = netdev_priv(netdev);
3643         struct e1000_hw *hw = &adapter->hw;
3644         struct sockaddr *addr = p;
3645
3646         if (!is_valid_ether_addr(addr->sa_data))
3647                 return -EADDRNOTAVAIL;
3648
3649         memcpy(netdev->dev_addr, addr->sa_data, netdev->addr_len);
3650         memcpy(hw->mac.addr, addr->sa_data, netdev->addr_len);
3651
3652         /* set the correct pool for the new PF MAC address in entry 0 */
3653         igb_rar_set_qsel(adapter, hw->mac.addr, 0,
3654                          adapter->vfs_allocated_count);
3655
3656         return 0;
3657 }
3658
3659 /**
3660  *  igb_write_mc_addr_list - write multicast addresses to MTA
3661  *  @netdev: network interface device structure
3662  *
3663  *  Writes multicast address list to the MTA hash table.
3664  *  Returns: -ENOMEM on failure
3665  *           0 on no addresses written
3666  *           X on writing X addresses to MTA
3667  **/
3668 static int igb_write_mc_addr_list(struct net_device *netdev)
3669 {
3670         struct igb_adapter *adapter = netdev_priv(netdev);
3671         struct e1000_hw *hw = &adapter->hw;
3672         struct netdev_hw_addr *ha;
3673         u8  *mta_list;
3674         int i;
3675
3676         if (netdev_mc_empty(netdev)) {
3677                 /* nothing to program, so clear mc list */
3678                 igb_update_mc_addr_list(hw, NULL, 0);
3679                 igb_restore_vf_multicasts(adapter);
3680                 return 0;
3681         }
3682
3683         mta_list = kzalloc(netdev_mc_count(netdev) * 6, GFP_ATOMIC);
3684         if (!mta_list)
3685                 return -ENOMEM;
3686
3687         /* The shared function expects a packed array of only addresses. */
3688         i = 0;
3689         netdev_for_each_mc_addr(ha, netdev)
3690                 memcpy(mta_list + (i++ * ETH_ALEN), ha->addr, ETH_ALEN);
3691
3692         igb_update_mc_addr_list(hw, mta_list, i);
3693         kfree(mta_list);
3694
3695         return netdev_mc_count(netdev);
3696 }
3697
3698 /**
3699  *  igb_write_uc_addr_list - write unicast addresses to RAR table
3700  *  @netdev: network interface device structure
3701  *
3702  *  Writes unicast address list to the RAR table.
3703  *  Returns: -ENOMEM on failure/insufficient address space
3704  *           0 on no addresses written
3705  *           X on writing X addresses to the RAR table
3706  **/
3707 static int igb_write_uc_addr_list(struct net_device *netdev)
3708 {
3709         struct igb_adapter *adapter = netdev_priv(netdev);
3710         struct e1000_hw *hw = &adapter->hw;
3711         unsigned int vfn = adapter->vfs_allocated_count;
3712         unsigned int rar_entries = hw->mac.rar_entry_count - (vfn + 1);
3713         int count = 0;
3714
3715         /* return ENOMEM indicating insufficient memory for addresses */
3716         if (netdev_uc_count(netdev) > rar_entries)
3717                 return -ENOMEM;
3718
3719         if (!netdev_uc_empty(netdev) && rar_entries) {
3720                 struct netdev_hw_addr *ha;
3721
3722                 netdev_for_each_uc_addr(ha, netdev) {
3723                         if (!rar_entries)
3724                                 break;
3725                         igb_rar_set_qsel(adapter, ha->addr,
3726                                          rar_entries--,
3727                                          vfn);
3728                         count++;
3729                 }
3730         }
3731         /* write the addresses in reverse order to avoid write combining */
3732         for (; rar_entries > 0 ; rar_entries--) {
3733                 wr32(E1000_RAH(rar_entries), 0);
3734                 wr32(E1000_RAL(rar_entries), 0);
3735         }
3736         wrfl();
3737
3738         return count;
3739 }
3740
3741 /**
3742  *  igb_set_rx_mode - Secondary Unicast, Multicast and Promiscuous mode set
3743  *  @netdev: network interface device structure
3744  *
3745  *  The set_rx_mode entry point is called whenever the unicast or multicast
3746  *  address lists or the network interface flags are updated.  This routine is
3747  *  responsible for configuring the hardware for proper unicast, multicast,
3748  *  promiscuous mode, and all-multi behavior.
3749  **/
3750 static void igb_set_rx_mode(struct net_device *netdev)
3751 {
3752         struct igb_adapter *adapter = netdev_priv(netdev);
3753         struct e1000_hw *hw = &adapter->hw;
3754         unsigned int vfn = adapter->vfs_allocated_count;
3755         u32 rctl, vmolr = 0;
3756         int count;
3757
3758         /* Check for Promiscuous and All Multicast modes */
3759         rctl = rd32(E1000_RCTL);
3760
3761         /* clear the effected bits */
3762         rctl &= ~(E1000_RCTL_UPE | E1000_RCTL_MPE | E1000_RCTL_VFE);
3763
3764         if (netdev->flags & IFF_PROMISC) {
3765                 /* retain VLAN HW filtering if in VT mode */
3766                 if (adapter->vfs_allocated_count)
3767                         rctl |= E1000_RCTL_VFE;
3768                 rctl |= (E1000_RCTL_UPE | E1000_RCTL_MPE);
3769                 vmolr |= (E1000_VMOLR_ROPE | E1000_VMOLR_MPME);
3770         } else {
3771                 if (netdev->flags & IFF_ALLMULTI) {
3772                         rctl |= E1000_RCTL_MPE;
3773                         vmolr |= E1000_VMOLR_MPME;
3774                 } else {
3775                         /* Write addresses to the MTA, if the attempt fails
3776                          * then we should just turn on promiscuous mode so
3777                          * that we can at least receive multicast traffic
3778                          */
3779                         count = igb_write_mc_addr_list(netdev);
3780                         if (count < 0) {
3781                                 rctl |= E1000_RCTL_MPE;
3782                                 vmolr |= E1000_VMOLR_MPME;
3783                         } else if (count) {
3784                                 vmolr |= E1000_VMOLR_ROMPE;
3785                         }
3786                 }
3787                 /* Write addresses to available RAR registers, if there is not
3788                  * sufficient space to store all the addresses then enable
3789                  * unicast promiscuous mode
3790                  */
3791                 count = igb_write_uc_addr_list(netdev);
3792                 if (count < 0) {
3793                         rctl |= E1000_RCTL_UPE;
3794                         vmolr |= E1000_VMOLR_ROPE;
3795                 }
3796                 rctl |= E1000_RCTL_VFE;
3797         }
3798         wr32(E1000_RCTL, rctl);
3799
3800         /* In order to support SR-IOV and eventually VMDq it is necessary to set
3801          * the VMOLR to enable the appropriate modes.  Without this workaround
3802          * we will have issues with VLAN tag stripping not being done for frames
3803          * that are only arriving because we are the default pool
3804          */
3805         if ((hw->mac.type < e1000_82576) || (hw->mac.type > e1000_i350))
3806                 return;
3807
3808         vmolr |= rd32(E1000_VMOLR(vfn)) &
3809                  ~(E1000_VMOLR_ROPE | E1000_VMOLR_MPME | E1000_VMOLR_ROMPE);
3810         wr32(E1000_VMOLR(vfn), vmolr);
3811         igb_restore_vf_multicasts(adapter);
3812 }
3813
3814 static void igb_check_wvbr(struct igb_adapter *adapter)
3815 {
3816         struct e1000_hw *hw = &adapter->hw;
3817         u32 wvbr = 0;
3818
3819         switch (hw->mac.type) {
3820         case e1000_82576:
3821         case e1000_i350:
3822                 if (!(wvbr = rd32(E1000_WVBR)))
3823                         return;
3824                 break;
3825         default:
3826                 break;
3827         }
3828
3829         adapter->wvbr |= wvbr;
3830 }
3831
3832 #define IGB_STAGGERED_QUEUE_OFFSET 8
3833
3834 static void igb_spoof_check(struct igb_adapter *adapter)
3835 {
3836         int j;
3837
3838         if (!adapter->wvbr)
3839                 return;
3840
3841         for(j = 0; j < adapter->vfs_allocated_count; j++) {
3842                 if (adapter->wvbr & (1 << j) ||
3843                     adapter->wvbr & (1 << (j + IGB_STAGGERED_QUEUE_OFFSET))) {
3844                         dev_warn(&adapter->pdev->dev,
3845                                 "Spoof event(s) detected on VF %d\n", j);
3846                         adapter->wvbr &=
3847                                 ~((1 << j) |
3848                                   (1 << (j + IGB_STAGGERED_QUEUE_OFFSET)));
3849                 }
3850         }
3851 }
3852
3853 /* Need to wait a few seconds after link up to get diagnostic information from
3854  * the phy
3855  */
3856 static void igb_update_phy_info(unsigned long data)
3857 {
3858         struct igb_adapter *adapter = (struct igb_adapter *) data;
3859         igb_get_phy_info(&adapter->hw);
3860 }
3861
3862 /**
3863  *  igb_has_link - check shared code for link and determine up/down
3864  *  @adapter: pointer to driver private info
3865  **/
3866 bool igb_has_link(struct igb_adapter *adapter)
3867 {
3868         struct e1000_hw *hw = &adapter->hw;
3869         bool link_active = false;
3870
3871         /* get_link_status is set on LSC (link status) interrupt or
3872          * rx sequence error interrupt.  get_link_status will stay
3873          * false until the e1000_check_for_link establishes link
3874          * for copper adapters ONLY
3875          */
3876         switch (hw->phy.media_type) {
3877         case e1000_media_type_copper:
3878                 if (!hw->mac.get_link_status)
3879                         return true;
3880         case e1000_media_type_internal_serdes:
3881                 hw->mac.ops.check_for_link(hw);
3882                 link_active = !hw->mac.get_link_status;
3883                 break;
3884         default:
3885         case e1000_media_type_unknown:
3886                 break;
3887         }
3888
3889         return link_active;
3890 }
3891
3892 static bool igb_thermal_sensor_event(struct e1000_hw *hw, u32 event)
3893 {
3894         bool ret = false;
3895         u32 ctrl_ext, thstat;
3896
3897         /* check for thermal sensor event on i350 copper only */
3898         if (hw->mac.type == e1000_i350) {
3899                 thstat = rd32(E1000_THSTAT);
3900                 ctrl_ext = rd32(E1000_CTRL_EXT);
3901
3902                 if ((hw->phy.media_type == e1000_media_type_copper) &&
3903                     !(ctrl_ext & E1000_CTRL_EXT_LINK_MODE_SGMII))
3904                         ret = !!(thstat & event);
3905         }
3906
3907         return ret;
3908 }
3909
3910 /**
3911  *  igb_watchdog - Timer Call-back
3912  *  @data: pointer to adapter cast into an unsigned long
3913  **/
3914 static void igb_watchdog(unsigned long data)
3915 {
3916         struct igb_adapter *adapter = (struct igb_adapter *)data;
3917         /* Do the rest outside of interrupt context */
3918         schedule_work(&adapter->watchdog_task);
3919 }
3920
3921 static void igb_watchdog_task(struct work_struct *work)
3922 {
3923         struct igb_adapter *adapter = container_of(work,
3924                                                    struct igb_adapter,
3925                                                    watchdog_task);
3926         struct e1000_hw *hw = &adapter->hw;
3927         struct e1000_phy_info *phy = &hw->phy;
3928         struct net_device *netdev = adapter->netdev;
3929         u32 link;
3930         int i;
3931
3932         link = igb_has_link(adapter);
3933         if (link) {
3934                 /* Cancel scheduled suspend requests. */
3935                 pm_runtime_resume(netdev->dev.parent);
3936
3937                 if (!netif_carrier_ok(netdev)) {
3938                         u32 ctrl;
3939                         hw->mac.ops.get_speed_and_duplex(hw,
3940                                                          &adapter->link_speed,
3941                                                          &adapter->link_duplex);
3942
3943                         ctrl = rd32(E1000_CTRL);
3944                         /* Links status message must follow this format */
3945                         printk(KERN_INFO "igb: %s NIC Link is Up %d Mbps %s "
3946                                "Duplex, Flow Control: %s\n",
3947                                netdev->name,
3948                                adapter->link_speed,
3949                                adapter->link_duplex == FULL_DUPLEX ?
3950                                "Full" : "Half",
3951                                (ctrl & E1000_CTRL_TFCE) &&
3952                                (ctrl & E1000_CTRL_RFCE) ? "RX/TX" :
3953                                (ctrl & E1000_CTRL_RFCE) ?  "RX" :
3954                                (ctrl & E1000_CTRL_TFCE) ?  "TX" : "None");
3955
3956                         /* check if SmartSpeed worked */
3957                         igb_check_downshift(hw);
3958                         if (phy->speed_downgraded)
3959                                 netdev_warn(netdev, "Link Speed was downgraded by SmartSpeed\n");
3960
3961                         /* check for thermal sensor event */
3962                         if (igb_thermal_sensor_event(hw,
3963                             E1000_THSTAT_LINK_THROTTLE)) {
3964                                 netdev_info(netdev, "The network adapter link "
3965                                             "speed was downshifted because it "
3966                                             "overheated\n");
3967                         }
3968
3969                         /* adjust timeout factor according to speed/duplex */
3970                         adapter->tx_timeout_factor = 1;
3971                         switch (adapter->link_speed) {
3972                         case SPEED_10:
3973                                 adapter->tx_timeout_factor = 14;
3974                                 break;
3975                         case SPEED_100:
3976                                 /* maybe add some timeout factor ? */
3977                                 break;
3978                         }
3979
3980                         netif_carrier_on(netdev);
3981
3982                         igb_ping_all_vfs(adapter);
3983                         igb_check_vf_rate_limit(adapter);
3984
3985                         /* link state has changed, schedule phy info update */
3986                         if (!test_bit(__IGB_DOWN, &adapter->state))
3987                                 mod_timer(&adapter->phy_info_timer,
3988                                           round_jiffies(jiffies + 2 * HZ));
3989                 }
3990         } else {
3991                 if (netif_carrier_ok(netdev)) {
3992                         adapter->link_speed = 0;
3993                         adapter->link_duplex = 0;
3994
3995                         /* check for thermal sensor event */
3996                         if (igb_thermal_sensor_event(hw,
3997                             E1000_THSTAT_PWR_DOWN)) {
3998                                 netdev_err(netdev, "The network adapter was "
3999                                            "stopped because it overheated\n");
4000                         }
4001
4002                         /* Links status message must follow this format */
4003                         printk(KERN_INFO "igb: %s NIC Link is Down\n",
4004                                netdev->name);
4005                         netif_carrier_off(netdev);
4006
4007                         igb_ping_all_vfs(adapter);
4008
4009                         /* link state has changed, schedule phy info update */
4010                         if (!test_bit(__IGB_DOWN, &adapter->state))
4011                                 mod_timer(&adapter->phy_info_timer,
4012                                           round_jiffies(jiffies + 2 * HZ));
4013
4014                         pm_schedule_suspend(netdev->dev.parent,
4015                                             MSEC_PER_SEC * 5);
4016                 }
4017         }
4018
4019         spin_lock(&adapter->stats64_lock);
4020         igb_update_stats(adapter, &adapter->stats64);
4021         spin_unlock(&adapter->stats64_lock);
4022
4023         for (i = 0; i < adapter->num_tx_queues; i++) {
4024                 struct igb_ring *tx_ring = adapter->tx_ring[i];
4025                 if (!netif_carrier_ok(netdev)) {
4026                         /* We've lost link, so the controller stops DMA,
4027                          * but we've got queued Tx work that's never going
4028                          * to get done, so reset controller to flush Tx.
4029                          * (Do the reset outside of interrupt context).
4030                          */
4031                         if (igb_desc_unused(tx_ring) + 1 < tx_ring->count) {
4032                                 adapter->tx_timeout_count++;
4033                                 schedule_work(&adapter->reset_task);
4034                                 /* return immediately since reset is imminent */
4035                                 return;
4036                         }
4037                 }
4038
4039                 /* Force detection of hung controller every watchdog period */
4040                 set_bit(IGB_RING_FLAG_TX_DETECT_HANG, &tx_ring->flags);
4041         }
4042
4043         /* Cause software interrupt to ensure Rx ring is cleaned */
4044         if (adapter->msix_entries) {
4045                 u32 eics = 0;
4046                 for (i = 0; i < adapter->num_q_vectors; i++)
4047                         eics |= adapter->q_vector[i]->eims_value;
4048                 wr32(E1000_EICS, eics);
4049         } else {
4050                 wr32(E1000_ICS, E1000_ICS_RXDMT0);
4051         }
4052
4053         igb_spoof_check(adapter);
4054         igb_ptp_rx_hang(adapter);
4055
4056         /* Reset the timer */
4057         if (!test_bit(__IGB_DOWN, &adapter->state))
4058                 mod_timer(&adapter->watchdog_timer,
4059                           round_jiffies(jiffies + 2 * HZ));
4060 }
4061
4062 enum latency_range {
4063         lowest_latency = 0,
4064         low_latency = 1,
4065         bulk_latency = 2,
4066         latency_invalid = 255
4067 };
4068
4069 /**
4070  *  igb_update_ring_itr - update the dynamic ITR value based on packet size
4071  *  @q_vector: pointer to q_vector
4072  *
4073  *  Stores a new ITR value based on strictly on packet size.  This
4074  *  algorithm is less sophisticated than that used in igb_update_itr,
4075  *  due to the difficulty of synchronizing statistics across multiple
4076  *  receive rings.  The divisors and thresholds used by this function
4077  *  were determined based on theoretical maximum wire speed and testing
4078  *  data, in order to minimize response time while increasing bulk
4079  *  throughput.
4080  *  This functionality is controlled by the InterruptThrottleRate module
4081  *  parameter (see igb_param.c)
4082  *  NOTE:  This function is called only when operating in a multiqueue
4083  *         receive environment.
4084  **/
4085 static void igb_update_ring_itr(struct igb_q_vector *q_vector)
4086 {
4087         int new_val = q_vector->itr_val;
4088         int avg_wire_size = 0;
4089         struct igb_adapter *adapter = q_vector->adapter;
4090         unsigned int packets;
4091
4092         /* For non-gigabit speeds, just fix the interrupt rate at 4000
4093          * ints/sec - ITR timer value of 120 ticks.
4094          */
4095         if (adapter->link_speed != SPEED_1000) {
4096                 new_val = IGB_4K_ITR;
4097                 goto set_itr_val;
4098         }
4099
4100         packets = q_vector->rx.total_packets;
4101         if (packets)
4102                 avg_wire_size = q_vector->rx.total_bytes / packets;
4103
4104         packets = q_vector->tx.total_packets;
4105         if (packets)
4106                 avg_wire_size = max_t(u32, avg_wire_size,
4107                                       q_vector->tx.total_bytes / packets);
4108
4109         /* if avg_wire_size isn't set no work was done */
4110         if (!avg_wire_size)
4111                 goto clear_counts;
4112
4113         /* Add 24 bytes to size to account for CRC, preamble, and gap */
4114         avg_wire_size += 24;
4115
4116         /* Don't starve jumbo frames */
4117         avg_wire_size = min(avg_wire_size, 3000);
4118
4119         /* Give a little boost to mid-size frames */
4120         if ((avg_wire_size > 300) && (avg_wire_size < 1200))
4121                 new_val = avg_wire_size / 3;
4122         else
4123                 new_val = avg_wire_size / 2;
4124
4125         /* conservative mode (itr 3) eliminates the lowest_latency setting */
4126         if (new_val < IGB_20K_ITR &&
4127             ((q_vector->rx.ring && adapter->rx_itr_setting == 3) ||
4128              (!q_vector->rx.ring && adapter->tx_itr_setting == 3)))
4129                 new_val = IGB_20K_ITR;
4130
4131 set_itr_val:
4132         if (new_val != q_vector->itr_val) {
4133                 q_vector->itr_val = new_val;
4134                 q_vector->set_itr = 1;
4135         }
4136 clear_counts:
4137         q_vector->rx.total_bytes = 0;
4138         q_vector->rx.total_packets = 0;
4139         q_vector->tx.total_bytes = 0;
4140         q_vector->tx.total_packets = 0;
4141 }
4142
4143 /**
4144  *  igb_update_itr - update the dynamic ITR value based on statistics
4145  *  @q_vector: pointer to q_vector
4146  *  @ring_container: ring info to update the itr for
4147  *
4148  *  Stores a new ITR value based on packets and byte
4149  *  counts during the last interrupt.  The advantage of per interrupt
4150  *  computation is faster updates and more accurate ITR for the current
4151  *  traffic pattern.  Constants in this function were computed
4152  *  based on theoretical maximum wire speed and thresholds were set based
4153  *  on testing data as well as attempting to minimize response time
4154  *  while increasing bulk throughput.
4155  *  this functionality is controlled by the InterruptThrottleRate module
4156  *  parameter (see igb_param.c)
4157  *  NOTE:  These calculations are only valid when operating in a single-
4158  *         queue environment.
4159  **/
4160 static void igb_update_itr(struct igb_q_vector *q_vector,
4161                            struct igb_ring_container *ring_container)
4162 {
4163         unsigned int packets = ring_container->total_packets;
4164         unsigned int bytes = ring_container->total_bytes;
4165         u8 itrval = ring_container->itr;
4166
4167         /* no packets, exit with status unchanged */
4168         if (packets == 0)
4169                 return;
4170
4171         switch (itrval) {
4172         case lowest_latency:
4173                 /* handle TSO and jumbo frames */
4174                 if (bytes/packets > 8000)
4175                         itrval = bulk_latency;
4176                 else if ((packets < 5) && (bytes > 512))
4177                         itrval = low_latency;
4178                 break;
4179         case low_latency:  /* 50 usec aka 20000 ints/s */
4180                 if (bytes > 10000) {
4181                         /* this if handles the TSO accounting */
4182                         if (bytes/packets > 8000) {
4183                                 itrval = bulk_latency;
4184                         } else if ((packets < 10) || ((bytes/packets) > 1200)) {
4185                                 itrval = bulk_latency;
4186                         } else if ((packets > 35)) {
4187                                 itrval = lowest_latency;
4188                         }
4189                 } else if (bytes/packets > 2000) {
4190                         itrval = bulk_latency;
4191                 } else if (packets <= 2 && bytes < 512) {
4192                         itrval = lowest_latency;
4193                 }
4194                 break;
4195         case bulk_latency: /* 250 usec aka 4000 ints/s */
4196                 if (bytes > 25000) {
4197                         if (packets > 35)
4198                                 itrval = low_latency;
4199                 } else if (bytes < 1500) {
4200                         itrval = low_latency;
4201                 }
4202                 break;
4203         }
4204
4205         /* clear work counters since we have the values we need */
4206         ring_container->total_bytes = 0;
4207         ring_container->total_packets = 0;
4208
4209         /* write updated itr to ring container */
4210         ring_container->itr = itrval;
4211 }
4212
4213 static void igb_set_itr(struct igb_q_vector *q_vector)
4214 {
4215         struct igb_adapter *adapter = q_vector->adapter;
4216         u32 new_itr = q_vector->itr_val;
4217         u8 current_itr = 0;
4218
4219         /* for non-gigabit speeds, just fix the interrupt rate at 4000 */
4220         if (adapter->link_speed != SPEED_1000) {
4221                 current_itr = 0;
4222                 new_itr = IGB_4K_ITR;
4223                 goto set_itr_now;
4224         }
4225
4226         igb_update_itr(q_vector, &q_vector->tx);
4227         igb_update_itr(q_vector, &q_vector->rx);
4228
4229         current_itr = max(q_vector->rx.itr, q_vector->tx.itr);
4230
4231         /* conservative mode (itr 3) eliminates the lowest_latency setting */
4232         if (current_itr == lowest_latency &&
4233             ((q_vector->rx.ring && adapter->rx_itr_setting == 3) ||
4234              (!q_vector->rx.ring && adapter->tx_itr_setting == 3)))
4235                 current_itr = low_latency;
4236
4237         switch (current_itr) {
4238         /* counts and packets in update_itr are dependent on these numbers */
4239         case lowest_latency:
4240                 new_itr = IGB_70K_ITR; /* 70,000 ints/sec */
4241                 break;
4242         case low_latency:
4243                 new_itr = IGB_20K_ITR; /* 20,000 ints/sec */
4244                 break;
4245         case bulk_latency:
4246                 new_itr = IGB_4K_ITR;  /* 4,000 ints/sec */
4247                 break;
4248         default:
4249                 break;
4250         }
4251
4252 set_itr_now:
4253         if (new_itr != q_vector->itr_val) {
4254                 /* this attempts to bias the interrupt rate towards Bulk
4255                  * by adding intermediate steps when interrupt rate is
4256                  * increasing
4257                  */
4258                 new_itr = new_itr > q_vector->itr_val ?
4259                           max((new_itr * q_vector->itr_val) /
4260                           (new_itr + (q_vector->itr_val >> 2)),
4261                           new_itr) : new_itr;
4262                 /* Don't write the value here; it resets the adapter's
4263                  * internal timer, and causes us to delay far longer than
4264                  * we should between interrupts.  Instead, we write the ITR
4265                  * value at the beginning of the next interrupt so the timing
4266                  * ends up being correct.
4267                  */
4268                 q_vector->itr_val = new_itr;
4269                 q_vector->set_itr = 1;
4270         }
4271 }
4272
4273 static void igb_tx_ctxtdesc(struct igb_ring *tx_ring, u32 vlan_macip_lens,
4274                             u32 type_tucmd, u32 mss_l4len_idx)
4275 {
4276         struct e1000_adv_tx_context_desc *context_desc;
4277         u16 i = tx_ring->next_to_use;
4278
4279         context_desc = IGB_TX_CTXTDESC(tx_ring, i);
4280
4281         i++;
4282         tx_ring->next_to_use = (i < tx_ring->count) ? i : 0;
4283
4284         /* set bits to identify this as an advanced context descriptor */
4285         type_tucmd |= E1000_TXD_CMD_DEXT | E1000_ADVTXD_DTYP_CTXT;
4286
4287         /* For 82575, context index must be unique per ring. */
4288         if (test_bit(IGB_RING_FLAG_TX_CTX_IDX, &tx_ring->flags))
4289                 mss_l4len_idx |= tx_ring->reg_idx << 4;
4290
4291         context_desc->vlan_macip_lens   = cpu_to_le32(vlan_macip_lens);
4292         context_desc->seqnum_seed       = 0;
4293         context_desc->type_tucmd_mlhl   = cpu_to_le32(type_tucmd);
4294         context_desc->mss_l4len_idx     = cpu_to_le32(mss_l4len_idx);
4295 }
4296
4297 static int igb_tso(struct igb_ring *tx_ring,
4298                    struct igb_tx_buffer *first,
4299                    u8 *hdr_len)
4300 {
4301         struct sk_buff *skb = first->skb;
4302         u32 vlan_macip_lens, type_tucmd;
4303         u32 mss_l4len_idx, l4len;
4304
4305         if (skb->ip_summed != CHECKSUM_PARTIAL)
4306                 return 0;
4307
4308         if (!skb_is_gso(skb))
4309                 return 0;
4310
4311         if (skb_header_cloned(skb)) {
4312                 int err = pskb_expand_head(skb, 0, 0, GFP_ATOMIC);
4313                 if (err)
4314                         return err;
4315         }
4316
4317         /* ADV DTYP TUCMD MKRLOC/ISCSIHEDLEN */
4318         type_tucmd = E1000_ADVTXD_TUCMD_L4T_TCP;
4319
4320         if (first->protocol == __constant_htons(ETH_P_IP)) {
4321                 struct iphdr *iph = ip_hdr(skb);
4322                 iph->tot_len = 0;
4323                 iph->check = 0;
4324                 tcp_hdr(skb)->check = ~csum_tcpudp_magic(iph->saddr,
4325                                                          iph->daddr, 0,
4326                                                          IPPROTO_TCP,
4327                                                          0);
4328                 type_tucmd |= E1000_ADVTXD_TUCMD_IPV4;
4329                 first->tx_flags |= IGB_TX_FLAGS_TSO |
4330                                    IGB_TX_FLAGS_CSUM |
4331                                    IGB_TX_FLAGS_IPV4;
4332         } else if (skb_is_gso_v6(skb)) {
4333                 ipv6_hdr(skb)->payload_len = 0;
4334                 tcp_hdr(skb)->check = ~csum_ipv6_magic(&ipv6_hdr(skb)->saddr,
4335                                                        &ipv6_hdr(skb)->daddr,
4336                                                        0, IPPROTO_TCP, 0);
4337                 first->tx_flags |= IGB_TX_FLAGS_TSO |
4338                                    IGB_TX_FLAGS_CSUM;
4339         }
4340
4341         /* compute header lengths */
4342         l4len = tcp_hdrlen(skb);
4343         *hdr_len = skb_transport_offset(skb) + l4len;
4344
4345         /* update gso size and bytecount with header size */
4346         first->gso_segs = skb_shinfo(skb)->gso_segs;
4347         first->bytecount += (first->gso_segs - 1) * *hdr_len;
4348
4349         /* MSS L4LEN IDX */
4350         mss_l4len_idx = l4len << E1000_ADVTXD_L4LEN_SHIFT;
4351         mss_l4len_idx |= skb_shinfo(skb)->gso_size << E1000_ADVTXD_MSS_SHIFT;
4352
4353         /* VLAN MACLEN IPLEN */
4354         vlan_macip_lens = skb_network_header_len(skb);
4355         vlan_macip_lens |= skb_network_offset(skb) << E1000_ADVTXD_MACLEN_SHIFT;
4356         vlan_macip_lens |= first->tx_flags & IGB_TX_FLAGS_VLAN_MASK;
4357
4358         igb_tx_ctxtdesc(tx_ring, vlan_macip_lens, type_tucmd, mss_l4len_idx);
4359
4360         return 1;
4361 }
4362
4363 static void igb_tx_csum(struct igb_ring *tx_ring, struct igb_tx_buffer *first)
4364 {
4365         struct sk_buff *skb = first->skb;
4366         u32 vlan_macip_lens = 0;
4367         u32 mss_l4len_idx = 0;
4368         u32 type_tucmd = 0;
4369
4370         if (skb->ip_summed != CHECKSUM_PARTIAL) {
4371                 if (!(first->tx_flags & IGB_TX_FLAGS_VLAN))
4372                         return;
4373         } else {
4374                 u8 l4_hdr = 0;
4375                 switch (first->protocol) {
4376                 case __constant_htons(ETH_P_IP):
4377                         vlan_macip_lens |= skb_network_header_len(skb);
4378                         type_tucmd |= E1000_ADVTXD_TUCMD_IPV4;
4379                         l4_hdr = ip_hdr(skb)->protocol;
4380                         break;
4381                 case __constant_htons(ETH_P_IPV6):
4382                         vlan_macip_lens |= skb_network_header_len(skb);
4383                         l4_hdr = ipv6_hdr(skb)->nexthdr;
4384                         break;
4385                 default:
4386                         if (unlikely(net_ratelimit())) {
4387                                 dev_warn(tx_ring->dev,
4388                                          "partial checksum but proto=%x!\n",
4389                                          first->protocol);
4390                         }
4391                         break;
4392                 }
4393
4394                 switch (l4_hdr) {
4395                 case IPPROTO_TCP:
4396                         type_tucmd |= E1000_ADVTXD_TUCMD_L4T_TCP;
4397                         mss_l4len_idx = tcp_hdrlen(skb) <<
4398                                         E1000_ADVTXD_L4LEN_SHIFT;
4399                         break;
4400                 case IPPROTO_SCTP:
4401                         type_tucmd |= E1000_ADVTXD_TUCMD_L4T_SCTP;
4402                         mss_l4len_idx = sizeof(struct sctphdr) <<
4403                                         E1000_ADVTXD_L4LEN_SHIFT;
4404                         break;
4405                 case IPPROTO_UDP:
4406                         mss_l4len_idx = sizeof(struct udphdr) <<
4407                                         E1000_ADVTXD_L4LEN_SHIFT;
4408                         break;
4409                 default:
4410                         if (unlikely(net_ratelimit())) {
4411                                 dev_warn(tx_ring->dev,
4412                                          "partial checksum but l4 proto=%x!\n",
4413                                          l4_hdr);
4414                         }
4415                         break;
4416                 }
4417
4418                 /* update TX checksum flag */
4419                 first->tx_flags |= IGB_TX_FLAGS_CSUM;
4420         }
4421
4422         vlan_macip_lens |= skb_network_offset(skb) << E1000_ADVTXD_MACLEN_SHIFT;
4423         vlan_macip_lens |= first->tx_flags & IGB_TX_FLAGS_VLAN_MASK;
4424
4425         igb_tx_ctxtdesc(tx_ring, vlan_macip_lens, type_tucmd, mss_l4len_idx);
4426 }
4427
4428 #define IGB_SET_FLAG(_input, _flag, _result) \
4429         ((_flag <= _result) ? \
4430          ((u32)(_input & _flag) * (_result / _flag)) : \
4431          ((u32)(_input & _flag) / (_flag / _result)))
4432
4433 static u32 igb_tx_cmd_type(struct sk_buff *skb, u32 tx_flags)
4434 {
4435         /* set type for advanced descriptor with frame checksum insertion */
4436         u32 cmd_type = E1000_ADVTXD_DTYP_DATA |
4437                        E1000_ADVTXD_DCMD_DEXT |
4438                        E1000_ADVTXD_DCMD_IFCS;
4439
4440         /* set HW vlan bit if vlan is present */
4441         cmd_type |= IGB_SET_FLAG(tx_flags, IGB_TX_FLAGS_VLAN,
4442                                  (E1000_ADVTXD_DCMD_VLE));
4443
4444         /* set segmentation bits for TSO */
4445         cmd_type |= IGB_SET_FLAG(tx_flags, IGB_TX_FLAGS_TSO,
4446                                  (E1000_ADVTXD_DCMD_TSE));
4447
4448         /* set timestamp bit if present */
4449         cmd_type |= IGB_SET_FLAG(tx_flags, IGB_TX_FLAGS_TSTAMP,
4450                                  (E1000_ADVTXD_MAC_TSTAMP));
4451
4452         /* insert frame checksum */
4453         cmd_type ^= IGB_SET_FLAG(skb->no_fcs, 1, E1000_ADVTXD_DCMD_IFCS);
4454
4455         return cmd_type;
4456 }
4457
4458 static void igb_tx_olinfo_status(struct igb_ring *tx_ring,
4459                                  union e1000_adv_tx_desc *tx_desc,
4460                                  u32 tx_flags, unsigned int paylen)
4461 {
4462         u32 olinfo_status = paylen << E1000_ADVTXD_PAYLEN_SHIFT;
4463
4464         /* 82575 requires a unique index per ring */
4465         if (test_bit(IGB_RING_FLAG_TX_CTX_IDX, &tx_ring->flags))
4466                 olinfo_status |= tx_ring->reg_idx << 4;
4467
4468         /* insert L4 checksum */
4469         olinfo_status |= IGB_SET_FLAG(tx_flags,
4470                                       IGB_TX_FLAGS_CSUM,
4471                                       (E1000_TXD_POPTS_TXSM << 8));
4472
4473         /* insert IPv4 checksum */
4474         olinfo_status |= IGB_SET_FLAG(tx_flags,
4475                                       IGB_TX_FLAGS_IPV4,
4476                                       (E1000_TXD_POPTS_IXSM << 8));
4477
4478         tx_desc->read.olinfo_status = cpu_to_le32(olinfo_status);
4479 }
4480
4481 static void igb_tx_map(struct igb_ring *tx_ring,
4482                        struct igb_tx_buffer *first,
4483                        const u8 hdr_len)
4484 {
4485         struct sk_buff *skb = first->skb;
4486         struct igb_tx_buffer *tx_buffer;
4487         union e1000_adv_tx_desc *tx_desc;
4488         struct skb_frag_struct *frag;
4489         dma_addr_t dma;
4490         unsigned int data_len, size;
4491         u32 tx_flags = first->tx_flags;
4492         u32 cmd_type = igb_tx_cmd_type(skb, tx_flags);
4493         u16 i = tx_ring->next_to_use;
4494
4495         tx_desc = IGB_TX_DESC(tx_ring, i);
4496
4497         igb_tx_olinfo_status(tx_ring, tx_desc, tx_flags, skb->len - hdr_len);
4498
4499         size = skb_headlen(skb);
4500         data_len = skb->data_len;
4501
4502         dma = dma_map_single(tx_ring->dev, skb->data, size, DMA_TO_DEVICE);
4503
4504         tx_buffer = first;
4505
4506         for (frag = &skb_shinfo(skb)->frags[0];; frag++) {
4507                 if (dma_mapping_error(tx_ring->dev, dma))
4508                         goto dma_error;
4509
4510                 /* record length, and DMA address */
4511                 dma_unmap_len_set(tx_buffer, len, size);
4512                 dma_unmap_addr_set(tx_buffer, dma, dma);
4513
4514                 tx_desc->read.buffer_addr = cpu_to_le64(dma);
4515
4516                 while (unlikely(size > IGB_MAX_DATA_PER_TXD)) {
4517                         tx_desc->read.cmd_type_len =
4518                                 cpu_to_le32(cmd_type ^ IGB_MAX_DATA_PER_TXD);
4519
4520                         i++;
4521                         tx_desc++;
4522                         if (i == tx_ring->count) {
4523                                 tx_desc = IGB_TX_DESC(tx_ring, 0);
4524                                 i = 0;
4525                         }
4526                         tx_desc->read.olinfo_status = 0;
4527
4528                         dma += IGB_MAX_DATA_PER_TXD;
4529                         size -= IGB_MAX_DATA_PER_TXD;
4530
4531                         tx_desc->read.buffer_addr = cpu_to_le64(dma);
4532                 }
4533
4534                 if (likely(!data_len))
4535                         break;
4536
4537                 tx_desc->read.cmd_type_len = cpu_to_le32(cmd_type ^ size);
4538
4539                 i++;
4540                 tx_desc++;
4541                 if (i == tx_ring->count) {
4542                         tx_desc = IGB_TX_DESC(tx_ring, 0);
4543                         i = 0;
4544                 }
4545                 tx_desc->read.olinfo_status = 0;
4546
4547                 size = skb_frag_size(frag);
4548                 data_len -= size;
4549
4550                 dma = skb_frag_dma_map(tx_ring->dev, frag, 0,
4551                                        size, DMA_TO_DEVICE);
4552
4553                 tx_buffer = &tx_ring->tx_buffer_info[i];
4554         }
4555
4556         /* write last descriptor with RS and EOP bits */
4557         cmd_type |= size | IGB_TXD_DCMD;
4558         tx_desc->read.cmd_type_len = cpu_to_le32(cmd_type);
4559
4560         netdev_tx_sent_queue(txring_txq(tx_ring), first->bytecount);
4561
4562         /* set the timestamp */
4563         first->time_stamp = jiffies;
4564
4565         /* Force memory writes to complete before letting h/w know there
4566          * are new descriptors to fetch.  (Only applicable for weak-ordered
4567          * memory model archs, such as IA-64).
4568          *
4569          * We also need this memory barrier to make certain all of the
4570          * status bits have been updated before next_to_watch is written.
4571          */
4572         wmb();
4573
4574         /* set next_to_watch value indicating a packet is present */
4575         first->next_to_watch = tx_desc;
4576
4577         i++;
4578         if (i == tx_ring->count)
4579                 i = 0;
4580
4581         tx_ring->next_to_use = i;
4582
4583         writel(i, tx_ring->tail);
4584
4585         /* we need this if more than one processor can write to our tail
4586          * at a time, it synchronizes IO on IA64/Altix systems
4587          */
4588         mmiowb();
4589
4590         return;
4591
4592 dma_error:
4593         dev_err(tx_ring->dev, "TX DMA map failed\n");
4594
4595         /* clear dma mappings for failed tx_buffer_info map */
4596         for (;;) {
4597                 tx_buffer = &tx_ring->tx_buffer_info[i];
4598                 igb_unmap_and_free_tx_resource(tx_ring, tx_buffer);
4599                 if (tx_buffer == first)
4600                         break;
4601                 if (i == 0)
4602                         i = tx_ring->count;
4603                 i--;
4604         }
4605
4606         tx_ring->next_to_use = i;
4607 }
4608
4609 static int __igb_maybe_stop_tx(struct igb_ring *tx_ring, const u16 size)
4610 {
4611         struct net_device *netdev = tx_ring->netdev;
4612
4613         netif_stop_subqueue(netdev, tx_ring->queue_index);
4614
4615         /* Herbert's original patch had:
4616          *  smp_mb__after_netif_stop_queue();
4617          * but since that doesn't exist yet, just open code it.
4618          */
4619         smp_mb();
4620
4621         /* We need to check again in a case another CPU has just
4622          * made room available.
4623          */
4624         if (igb_desc_unused(tx_ring) < size)
4625                 return -EBUSY;
4626
4627         /* A reprieve! */
4628         netif_wake_subqueue(netdev, tx_ring->queue_index);
4629
4630         u64_stats_update_begin(&tx_ring->tx_syncp2);
4631         tx_ring->tx_stats.restart_queue2++;
4632         u64_stats_update_end(&tx_ring->tx_syncp2);
4633
4634         return 0;
4635 }
4636
4637 static inline int igb_maybe_stop_tx(struct igb_ring *tx_ring, const u16 size)
4638 {
4639         if (igb_desc_unused(tx_ring) >= size)
4640                 return 0;
4641         return __igb_maybe_stop_tx(tx_ring, size);
4642 }
4643
4644 netdev_tx_t igb_xmit_frame_ring(struct sk_buff *skb,
4645                                 struct igb_ring *tx_ring)
4646 {
4647         struct igb_tx_buffer *first;
4648         int tso;
4649         u32 tx_flags = 0;
4650         u16 count = TXD_USE_COUNT(skb_headlen(skb));
4651         __be16 protocol = vlan_get_protocol(skb);
4652         u8 hdr_len = 0;
4653
4654         /* need: 1 descriptor per page * PAGE_SIZE/IGB_MAX_DATA_PER_TXD,
4655          *       + 1 desc for skb_headlen/IGB_MAX_DATA_PER_TXD,
4656          *       + 2 desc gap to keep tail from touching head,
4657          *       + 1 desc for context descriptor,
4658          * otherwise try next time
4659          */
4660         if (NETDEV_FRAG_PAGE_MAX_SIZE > IGB_MAX_DATA_PER_TXD) {
4661                 unsigned short f;
4662                 for (f = 0; f < skb_shinfo(skb)->nr_frags; f++)
4663                         count += TXD_USE_COUNT(skb_shinfo(skb)->frags[f].size);
4664         } else {
4665                 count += skb_shinfo(skb)->nr_frags;
4666         }
4667
4668         if (igb_maybe_stop_tx(tx_ring, count + 3)) {
4669                 /* this is a hard error */
4670                 return NETDEV_TX_BUSY;
4671         }
4672
4673         /* record the location of the first descriptor for this packet */
4674         first = &tx_ring->tx_buffer_info[tx_ring->next_to_use];
4675         first->skb = skb;
4676         first->bytecount = skb->len;
4677         first->gso_segs = 1;
4678
4679         skb_tx_timestamp(skb);
4680
4681         if (unlikely(skb_shinfo(skb)->tx_flags & SKBTX_HW_TSTAMP)) {
4682                 struct igb_adapter *adapter = netdev_priv(tx_ring->netdev);
4683
4684                 if (!(adapter->ptp_tx_skb)) {
4685                         skb_shinfo(skb)->tx_flags |= SKBTX_IN_PROGRESS;
4686                         tx_flags |= IGB_TX_FLAGS_TSTAMP;
4687
4688                         adapter->ptp_tx_skb = skb_get(skb);
4689                         adapter->ptp_tx_start = jiffies;
4690                         if (adapter->hw.mac.type == e1000_82576)
4691                                 schedule_work(&adapter->ptp_tx_work);
4692                 }
4693         }
4694
4695         if (vlan_tx_tag_present(skb)) {
4696                 tx_flags |= IGB_TX_FLAGS_VLAN;
4697                 tx_flags |= (vlan_tx_tag_get(skb) << IGB_TX_FLAGS_VLAN_SHIFT);
4698         }
4699
4700         /* record initial flags and protocol */
4701         first->tx_flags = tx_flags;
4702         first->protocol = protocol;
4703
4704         tso = igb_tso(tx_ring, first, &hdr_len);
4705         if (tso < 0)
4706                 goto out_drop;
4707         else if (!tso)
4708                 igb_tx_csum(tx_ring, first);
4709
4710         igb_tx_map(tx_ring, first, hdr_len);
4711
4712         /* Make sure there is space in the ring for the next send. */
4713         igb_maybe_stop_tx(tx_ring, DESC_NEEDED);
4714
4715         return NETDEV_TX_OK;
4716
4717 out_drop:
4718         igb_unmap_and_free_tx_resource(tx_ring, first);
4719
4720         return NETDEV_TX_OK;
4721 }
4722
4723 static inline struct igb_ring *igb_tx_queue_mapping(struct igb_adapter *adapter,
4724                                                     struct sk_buff *skb)
4725 {
4726         unsigned int r_idx = skb->queue_mapping;
4727
4728         if (r_idx >= adapter->num_tx_queues)
4729                 r_idx = r_idx % adapter->num_tx_queues;
4730
4731         return adapter->tx_ring[r_idx];
4732 }
4733
4734 static netdev_tx_t igb_xmit_frame(struct sk_buff *skb,
4735                                   struct net_device *netdev)
4736 {
4737         struct igb_adapter *adapter = netdev_priv(netdev);
4738
4739         if (test_bit(__IGB_DOWN, &adapter->state)) {
4740                 dev_kfree_skb_any(skb);
4741                 return NETDEV_TX_OK;
4742         }
4743
4744         if (skb->len <= 0) {
4745                 dev_kfree_skb_any(skb);
4746                 return NETDEV_TX_OK;
4747         }
4748
4749         /* The minimum packet size with TCTL.PSP set is 17 so pad the skb
4750          * in order to meet this minimum size requirement.
4751          */
4752         if (unlikely(skb->len < 17)) {
4753                 if (skb_pad(skb, 17 - skb->len))
4754                         return NETDEV_TX_OK;
4755                 skb->len = 17;
4756                 skb_set_tail_pointer(skb, 17);
4757         }
4758
4759         return igb_xmit_frame_ring(skb, igb_tx_queue_mapping(adapter, skb));
4760 }
4761
4762 /**
4763  *  igb_tx_timeout - Respond to a Tx Hang
4764  *  @netdev: network interface device structure
4765  **/
4766 static void igb_tx_timeout(struct net_device *netdev)
4767 {
4768         struct igb_adapter *adapter = netdev_priv(netdev);
4769         struct e1000_hw *hw = &adapter->hw;
4770
4771         /* Do the reset outside of interrupt context */
4772         adapter->tx_timeout_count++;
4773
4774         if (hw->mac.type >= e1000_82580)
4775                 hw->dev_spec._82575.global_device_reset = true;
4776
4777         schedule_work(&adapter->reset_task);
4778         wr32(E1000_EICS,
4779              (adapter->eims_enable_mask & ~adapter->eims_other));
4780 }
4781
4782 static void igb_reset_task(struct work_struct *work)
4783 {
4784         struct igb_adapter *adapter;
4785         adapter = container_of(work, struct igb_adapter, reset_task);
4786
4787         igb_dump(adapter);
4788         netdev_err(adapter->netdev, "Reset adapter\n");
4789         igb_reinit_locked(adapter);
4790 }
4791
4792 /**
4793  *  igb_get_stats64 - Get System Network Statistics
4794  *  @netdev: network interface device structure
4795  *  @stats: rtnl_link_stats64 pointer
4796  **/
4797 static struct rtnl_link_stats64 *igb_get_stats64(struct net_device *netdev,
4798                                                 struct rtnl_link_stats64 *stats)
4799 {
4800         struct igb_adapter *adapter = netdev_priv(netdev);
4801
4802         spin_lock(&adapter->stats64_lock);
4803         igb_update_stats(adapter, &adapter->stats64);
4804         memcpy(stats, &adapter->stats64, sizeof(*stats));
4805         spin_unlock(&adapter->stats64_lock);
4806
4807         return stats;
4808 }
4809
4810 /**
4811  *  igb_change_mtu - Change the Maximum Transfer Unit
4812  *  @netdev: network interface device structure
4813  *  @new_mtu: new value for maximum frame size
4814  *
4815  *  Returns 0 on success, negative on failure
4816  **/
4817 static int igb_change_mtu(struct net_device *netdev, int new_mtu)
4818 {
4819         struct igb_adapter *adapter = netdev_priv(netdev);
4820         struct pci_dev *pdev = adapter->pdev;
4821         int max_frame = new_mtu + ETH_HLEN + ETH_FCS_LEN + VLAN_HLEN;
4822
4823         if ((new_mtu < 68) || (max_frame > MAX_JUMBO_FRAME_SIZE)) {
4824                 dev_err(&pdev->dev, "Invalid MTU setting\n");
4825                 return -EINVAL;
4826         }
4827
4828 #define MAX_STD_JUMBO_FRAME_SIZE 9238
4829         if (max_frame > MAX_STD_JUMBO_FRAME_SIZE) {
4830                 dev_err(&pdev->dev, "MTU > 9216 not supported.\n");
4831                 return -EINVAL;
4832         }
4833
4834         /* adjust max frame to be at least the size of a standard frame */
4835         if (max_frame < (ETH_FRAME_LEN + ETH_FCS_LEN))
4836                 max_frame = ETH_FRAME_LEN + ETH_FCS_LEN;
4837
4838         while (test_and_set_bit(__IGB_RESETTING, &adapter->state))
4839                 msleep(1);
4840
4841         /* igb_down has a dependency on max_frame_size */
4842         adapter->max_frame_size = max_frame;
4843
4844         if (netif_running(netdev))
4845                 igb_down(adapter);
4846
4847         dev_info(&pdev->dev, "changing MTU from %d to %d\n",
4848                  netdev->mtu, new_mtu);
4849         netdev->mtu = new_mtu;
4850
4851         if (netif_running(netdev))
4852                 igb_up(adapter);
4853         else
4854                 igb_reset(adapter);
4855
4856         clear_bit(__IGB_RESETTING, &adapter->state);
4857
4858         return 0;
4859 }
4860
4861 /**
4862  *  igb_update_stats - Update the board statistics counters
4863  *  @adapter: board private structure
4864  **/
4865 void igb_update_stats(struct igb_adapter *adapter,
4866                       struct rtnl_link_stats64 *net_stats)
4867 {
4868         struct e1000_hw *hw = &adapter->hw;
4869         struct pci_dev *pdev = adapter->pdev;
4870         u32 reg, mpc;
4871         u16 phy_tmp;
4872         int i;
4873         u64 bytes, packets;
4874         unsigned int start;
4875         u64 _bytes, _packets;
4876
4877 #define PHY_IDLE_ERROR_COUNT_MASK 0x00FF
4878
4879         /* Prevent stats update while adapter is being reset, or if the pci
4880          * connection is down.
4881          */
4882         if (adapter->link_speed == 0)
4883                 return;
4884         if (pci_channel_offline(pdev))
4885                 return;
4886
4887         bytes = 0;
4888         packets = 0;
4889
4890         rcu_read_lock();
4891         for (i = 0; i < adapter->num_rx_queues; i++) {
4892                 u32 rqdpc = rd32(E1000_RQDPC(i));
4893                 struct igb_ring *ring = adapter->rx_ring[i];
4894
4895                 if (rqdpc) {
4896                         ring->rx_stats.drops += rqdpc;
4897                         net_stats->rx_fifo_errors += rqdpc;
4898                 }
4899
4900                 do {
4901                         start = u64_stats_fetch_begin_bh(&ring->rx_syncp);
4902                         _bytes = ring->rx_stats.bytes;
4903                         _packets = ring->rx_stats.packets;
4904                 } while (u64_stats_fetch_retry_bh(&ring->rx_syncp, start));
4905                 bytes += _bytes;
4906                 packets += _packets;
4907         }
4908
4909         net_stats->rx_bytes = bytes;
4910         net_stats->rx_packets = packets;
4911
4912         bytes = 0;
4913         packets = 0;
4914         for (i = 0; i < adapter->num_tx_queues; i++) {
4915                 struct igb_ring *ring = adapter->tx_ring[i];
4916                 do {
4917                         start = u64_stats_fetch_begin_bh(&ring->tx_syncp);
4918                         _bytes = ring->tx_stats.bytes;
4919                         _packets = ring->tx_stats.packets;
4920                 } while (u64_stats_fetch_retry_bh(&ring->tx_syncp, start));
4921                 bytes += _bytes;
4922                 packets += _packets;
4923         }
4924         net_stats->tx_bytes = bytes;
4925         net_stats->tx_packets = packets;
4926         rcu_read_unlock();
4927
4928         /* read stats registers */
4929         adapter->stats.crcerrs += rd32(E1000_CRCERRS);
4930         adapter->stats.gprc += rd32(E1000_GPRC);
4931         adapter->stats.gorc += rd32(E1000_GORCL);
4932         rd32(E1000_GORCH); /* clear GORCL */
4933         adapter->stats.bprc += rd32(E1000_BPRC);
4934         adapter->stats.mprc += rd32(E1000_MPRC);
4935         adapter->stats.roc += rd32(E1000_ROC);
4936
4937         adapter->stats.prc64 += rd32(E1000_PRC64);
4938         adapter->stats.prc127 += rd32(E1000_PRC127);
4939         adapter->stats.prc255 += rd32(E1000_PRC255);
4940         adapter->stats.prc511 += rd32(E1000_PRC511);
4941         adapter->stats.prc1023 += rd32(E1000_PRC1023);
4942         adapter->stats.prc1522 += rd32(E1000_PRC1522);
4943         adapter->stats.symerrs += rd32(E1000_SYMERRS);
4944         adapter->stats.sec += rd32(E1000_SEC);
4945
4946         mpc = rd32(E1000_MPC);
4947         adapter->stats.mpc += mpc;
4948         net_stats->rx_fifo_errors += mpc;
4949         adapter->stats.scc += rd32(E1000_SCC);
4950         adapter->stats.ecol += rd32(E1000_ECOL);
4951         adapter->stats.mcc += rd32(E1000_MCC);
4952         adapter->stats.latecol += rd32(E1000_LATECOL);
4953         adapter->stats.dc += rd32(E1000_DC);
4954         adapter->stats.rlec += rd32(E1000_RLEC);
4955         adapter->stats.xonrxc += rd32(E1000_XONRXC);
4956         adapter->stats.xontxc += rd32(E1000_XONTXC);
4957         adapter->stats.xoffrxc += rd32(E1000_XOFFRXC);
4958         adapter->stats.xofftxc += rd32(E1000_XOFFTXC);
4959         adapter->stats.fcruc += rd32(E1000_FCRUC);
4960         adapter->stats.gptc += rd32(E1000_GPTC);
4961         adapter->stats.gotc += rd32(E1000_GOTCL);
4962         rd32(E1000_GOTCH); /* clear GOTCL */
4963         adapter->stats.rnbc += rd32(E1000_RNBC);
4964         adapter->stats.ruc += rd32(E1000_RUC);
4965         adapter->stats.rfc += rd32(E1000_RFC);
4966         adapter->stats.rjc += rd32(E1000_RJC);
4967         adapter->stats.tor += rd32(E1000_TORH);
4968         adapter->stats.tot += rd32(E1000_TOTH);
4969         adapter->stats.tpr += rd32(E1000_TPR);
4970
4971         adapter->stats.ptc64 += rd32(E1000_PTC64);
4972         adapter->stats.ptc127 += rd32(E1000_PTC127);
4973         adapter->stats.ptc255 += rd32(E1000_PTC255);
4974         adapter->stats.ptc511 += rd32(E1000_PTC511);
4975         adapter->stats.ptc1023 += rd32(E1000_PTC1023);
4976         adapter->stats.ptc1522 += rd32(E1000_PTC1522);
4977
4978         adapter->stats.mptc += rd32(E1000_MPTC);
4979         adapter->stats.bptc += rd32(E1000_BPTC);
4980
4981         adapter->stats.tpt += rd32(E1000_TPT);
4982         adapter->stats.colc += rd32(E1000_COLC);
4983
4984         adapter->stats.algnerrc += rd32(E1000_ALGNERRC);
4985         /* read internal phy specific stats */
4986         reg = rd32(E1000_CTRL_EXT);
4987         if (!(reg & E1000_CTRL_EXT_LINK_MODE_MASK)) {
4988                 adapter->stats.rxerrc += rd32(E1000_RXERRC);
4989
4990                 /* this stat has invalid values on i210/i211 */
4991                 if ((hw->mac.type != e1000_i210) &&
4992                     (hw->mac.type != e1000_i211))
4993                         adapter->stats.tncrs += rd32(E1000_TNCRS);
4994         }
4995
4996         adapter->stats.tsctc += rd32(E1000_TSCTC);
4997         adapter->stats.tsctfc += rd32(E1000_TSCTFC);
4998
4999         adapter->stats.iac += rd32(E1000_IAC);
5000         adapter->stats.icrxoc += rd32(E1000_ICRXOC);
5001         adapter->stats.icrxptc += rd32(E1000_ICRXPTC);
5002         adapter->stats.icrxatc += rd32(E1000_ICRXATC);
5003         adapter->stats.ictxptc += rd32(E1000_ICTXPTC);
5004         adapter->stats.ictxatc += rd32(E1000_ICTXATC);
5005         adapter->stats.ictxqec += rd32(E1000_ICTXQEC);
5006         adapter->stats.ictxqmtc += rd32(E1000_ICTXQMTC);
5007         adapter->stats.icrxdmtc += rd32(E1000_ICRXDMTC);
5008
5009         /* Fill out the OS statistics structure */
5010         net_stats->multicast = adapter->stats.mprc;
5011         net_stats->collisions = adapter->stats.colc;
5012
5013         /* Rx Errors */
5014
5015         /* RLEC on some newer hardware can be incorrect so build
5016          * our own version based on RUC and ROC
5017          */
5018         net_stats->rx_errors = adapter->stats.rxerrc +
5019                 adapter->stats.crcerrs + adapter->stats.algnerrc +
5020                 adapter->stats.ruc + adapter->stats.roc +
5021                 adapter->stats.cexterr;
5022         net_stats->rx_length_errors = adapter->stats.ruc +
5023                                       adapter->stats.roc;
5024         net_stats->rx_crc_errors = adapter->stats.crcerrs;
5025         net_stats->rx_frame_errors = adapter->stats.algnerrc;
5026         net_stats->rx_missed_errors = adapter->stats.mpc;
5027
5028         /* Tx Errors */
5029         net_stats->tx_errors = adapter->stats.ecol +
5030                                adapter->stats.latecol;
5031         net_stats->tx_aborted_errors = adapter->stats.ecol;
5032         net_stats->tx_window_errors = adapter->stats.latecol;
5033         net_stats->tx_carrier_errors = adapter->stats.tncrs;
5034
5035         /* Tx Dropped needs to be maintained elsewhere */
5036
5037         /* Phy Stats */
5038         if (hw->phy.media_type == e1000_media_type_copper) {
5039                 if ((adapter->link_speed == SPEED_1000) &&
5040                    (!igb_read_phy_reg(hw, PHY_1000T_STATUS, &phy_tmp))) {
5041                         phy_tmp &= PHY_IDLE_ERROR_COUNT_MASK;
5042                         adapter->phy_stats.idle_errors += phy_tmp;
5043                 }
5044         }
5045
5046         /* Management Stats */
5047         adapter->stats.mgptc += rd32(E1000_MGTPTC);
5048         adapter->stats.mgprc += rd32(E1000_MGTPRC);
5049         adapter->stats.mgpdc += rd32(E1000_MGTPDC);
5050
5051         /* OS2BMC Stats */
5052         reg = rd32(E1000_MANC);
5053         if (reg & E1000_MANC_EN_BMC2OS) {
5054                 adapter->stats.o2bgptc += rd32(E1000_O2BGPTC);
5055                 adapter->stats.o2bspc += rd32(E1000_O2BSPC);
5056                 adapter->stats.b2ospc += rd32(E1000_B2OSPC);
5057                 adapter->stats.b2ogprc += rd32(E1000_B2OGPRC);
5058         }
5059 }
5060
5061 static irqreturn_t igb_msix_other(int irq, void *data)
5062 {
5063         struct igb_adapter *adapter = data;
5064         struct e1000_hw *hw = &adapter->hw;
5065         u32 icr = rd32(E1000_ICR);
5066         /* reading ICR causes bit 31 of EICR to be cleared */
5067
5068         if (icr & E1000_ICR_DRSTA)
5069                 schedule_work(&adapter->reset_task);
5070
5071         if (icr & E1000_ICR_DOUTSYNC) {
5072                 /* HW is reporting DMA is out of sync */
5073                 adapter->stats.doosync++;
5074                 /* The DMA Out of Sync is also indication of a spoof event
5075                  * in IOV mode. Check the Wrong VM Behavior register to
5076                  * see if it is really a spoof event.
5077                  */
5078                 igb_check_wvbr(adapter);
5079         }
5080
5081         /* Check for a mailbox event */
5082         if (icr & E1000_ICR_VMMB)
5083                 igb_msg_task(adapter);
5084
5085         if (icr & E1000_ICR_LSC) {
5086                 hw->mac.get_link_status = 1;
5087                 /* guard against interrupt when we're going down */
5088                 if (!test_bit(__IGB_DOWN, &adapter->state))
5089                         mod_timer(&adapter->watchdog_timer, jiffies + 1);
5090         }
5091
5092         if (icr & E1000_ICR_TS) {
5093                 u32 tsicr = rd32(E1000_TSICR);
5094
5095                 if (tsicr & E1000_TSICR_TXTS) {
5096                         /* acknowledge the interrupt */
5097                         wr32(E1000_TSICR, E1000_TSICR_TXTS);
5098                         /* retrieve hardware timestamp */
5099                         schedule_work(&adapter->ptp_tx_work);
5100                 }
5101         }
5102
5103         wr32(E1000_EIMS, adapter->eims_other);
5104
5105         return IRQ_HANDLED;
5106 }
5107
5108 static void igb_write_itr(struct igb_q_vector *q_vector)
5109 {
5110         struct igb_adapter *adapter = q_vector->adapter;
5111         u32 itr_val = q_vector->itr_val & 0x7FFC;
5112
5113         if (!q_vector->set_itr)
5114                 return;
5115
5116         if (!itr_val)
5117                 itr_val = 0x4;
5118
5119         if (adapter->hw.mac.type == e1000_82575)
5120                 itr_val |= itr_val << 16;
5121         else
5122                 itr_val |= E1000_EITR_CNT_IGNR;
5123
5124         writel(itr_val, q_vector->itr_register);
5125         q_vector->set_itr = 0;
5126 }
5127
5128 static irqreturn_t igb_msix_ring(int irq, void *data)
5129 {
5130         struct igb_q_vector *q_vector = data;
5131
5132         /* Write the ITR value calculated from the previous interrupt. */
5133         igb_write_itr(q_vector);
5134
5135         napi_schedule(&q_vector->napi);
5136
5137         return IRQ_HANDLED;
5138 }
5139
5140 #ifdef CONFIG_IGB_DCA
5141 static void igb_update_tx_dca(struct igb_adapter *adapter,
5142                               struct igb_ring *tx_ring,
5143                               int cpu)
5144 {
5145         struct e1000_hw *hw = &adapter->hw;
5146         u32 txctrl = dca3_get_tag(tx_ring->dev, cpu);
5147
5148         if (hw->mac.type != e1000_82575)
5149                 txctrl <<= E1000_DCA_TXCTRL_CPUID_SHIFT;
5150
5151         /* We can enable relaxed ordering for reads, but not writes when
5152          * DCA is enabled.  This is due to a known issue in some chipsets
5153          * which will cause the DCA tag to be cleared.
5154          */
5155         txctrl |= E1000_DCA_TXCTRL_DESC_RRO_EN |
5156                   E1000_DCA_TXCTRL_DATA_RRO_EN |
5157                   E1000_DCA_TXCTRL_DESC_DCA_EN;
5158
5159         wr32(E1000_DCA_TXCTRL(tx_ring->reg_idx), txctrl);
5160 }
5161
5162 static void igb_update_rx_dca(struct igb_adapter *adapter,
5163                               struct igb_ring *rx_ring,
5164                               int cpu)
5165 {
5166         struct e1000_hw *hw = &adapter->hw;
5167         u32 rxctrl = dca3_get_tag(&adapter->pdev->dev, cpu);
5168
5169         if (hw->mac.type != e1000_82575)
5170                 rxctrl <<= E1000_DCA_RXCTRL_CPUID_SHIFT;
5171
5172         /* We can enable relaxed ordering for reads, but not writes when
5173          * DCA is enabled.  This is due to a known issue in some chipsets
5174          * which will cause the DCA tag to be cleared.
5175          */
5176         rxctrl |= E1000_DCA_RXCTRL_DESC_RRO_EN |
5177                   E1000_DCA_RXCTRL_DESC_DCA_EN;
5178
5179         wr32(E1000_DCA_RXCTRL(rx_ring->reg_idx), rxctrl);
5180 }
5181
5182 static void igb_update_dca(struct igb_q_vector *q_vector)
5183 {
5184         struct igb_adapter *adapter = q_vector->adapter;
5185         int cpu = get_cpu();
5186
5187         if (q_vector->cpu == cpu)
5188                 goto out_no_update;
5189
5190         if (q_vector->tx.ring)
5191                 igb_update_tx_dca(adapter, q_vector->tx.ring, cpu);
5192
5193         if (q_vector->rx.ring)
5194                 igb_update_rx_dca(adapter, q_vector->rx.ring, cpu);
5195
5196         q_vector->cpu = cpu;
5197 out_no_update:
5198         put_cpu();
5199 }
5200
5201 static void igb_setup_dca(struct igb_adapter *adapter)
5202 {
5203         struct e1000_hw *hw = &adapter->hw;
5204         int i;
5205
5206         if (!(adapter->flags & IGB_FLAG_DCA_ENABLED))
5207                 return;
5208
5209         /* Always use CB2 mode, difference is masked in the CB driver. */
5210         wr32(E1000_DCA_CTRL, E1000_DCA_CTRL_DCA_MODE_CB2);
5211
5212         for (i = 0; i < adapter->num_q_vectors; i++) {
5213                 adapter->q_vector[i]->cpu = -1;
5214                 igb_update_dca(adapter->q_vector[i]);
5215         }
5216 }
5217
5218 static int __igb_notify_dca(struct device *dev, void *data)
5219 {
5220         struct net_device *netdev = dev_get_drvdata(dev);
5221         struct igb_adapter *adapter = netdev_priv(netdev);
5222         struct pci_dev *pdev = adapter->pdev;
5223         struct e1000_hw *hw = &adapter->hw;
5224         unsigned long event = *(unsigned long *)data;
5225
5226         switch (event) {
5227         case DCA_PROVIDER_ADD:
5228                 /* if already enabled, don't do it again */
5229                 if (adapter->flags & IGB_FLAG_DCA_ENABLED)
5230                         break;
5231                 if (dca_add_requester(dev) == 0) {
5232                         adapter->flags |= IGB_FLAG_DCA_ENABLED;
5233                         dev_info(&pdev->dev, "DCA enabled\n");
5234                         igb_setup_dca(adapter);
5235                         break;
5236                 }
5237                 /* Fall Through since DCA is disabled. */
5238         case DCA_PROVIDER_REMOVE:
5239                 if (adapter->flags & IGB_FLAG_DCA_ENABLED) {
5240                         /* without this a class_device is left
5241                          * hanging around in the sysfs model
5242                          */
5243                         dca_remove_requester(dev);
5244                         dev_info(&pdev->dev, "DCA disabled\n");
5245                         adapter->flags &= ~IGB_FLAG_DCA_ENABLED;
5246                         wr32(E1000_DCA_CTRL, E1000_DCA_CTRL_DCA_MODE_DISABLE);
5247                 }
5248                 break;
5249         }
5250
5251         return 0;
5252 }
5253
5254 static int igb_notify_dca(struct notifier_block *nb, unsigned long event,
5255                           void *p)
5256 {
5257         int ret_val;
5258
5259         ret_val = driver_for_each_device(&igb_driver.driver, NULL, &event,
5260                                          __igb_notify_dca);
5261
5262         return ret_val ? NOTIFY_BAD : NOTIFY_DONE;
5263 }
5264 #endif /* CONFIG_IGB_DCA */
5265
5266 #ifdef CONFIG_PCI_IOV
5267 static int igb_vf_configure(struct igb_adapter *adapter, int vf)
5268 {
5269         unsigned char mac_addr[ETH_ALEN];
5270
5271         eth_zero_addr(mac_addr);
5272         igb_set_vf_mac(adapter, vf, mac_addr);
5273
5274         /* By default spoof check is enabled for all VFs */
5275         adapter->vf_data[vf].spoofchk_enabled = true;
5276
5277         return 0;
5278 }
5279
5280 #endif
5281 static void igb_ping_all_vfs(struct igb_adapter *adapter)
5282 {
5283         struct e1000_hw *hw = &adapter->hw;
5284         u32 ping;
5285         int i;
5286
5287         for (i = 0 ; i < adapter->vfs_allocated_count; i++) {
5288                 ping = E1000_PF_CONTROL_MSG;
5289                 if (adapter->vf_data[i].flags & IGB_VF_FLAG_CTS)
5290                         ping |= E1000_VT_MSGTYPE_CTS;
5291                 igb_write_mbx(hw, &ping, 1, i);
5292         }
5293 }
5294
5295 static int igb_set_vf_promisc(struct igb_adapter *adapter, u32 *msgbuf, u32 vf)
5296 {
5297         struct e1000_hw *hw = &adapter->hw;
5298         u32 vmolr = rd32(E1000_VMOLR(vf));
5299         struct vf_data_storage *vf_data = &adapter->vf_data[vf];
5300
5301         vf_data->flags &= ~(IGB_VF_FLAG_UNI_PROMISC |
5302                             IGB_VF_FLAG_MULTI_PROMISC);
5303         vmolr &= ~(E1000_VMOLR_ROPE | E1000_VMOLR_ROMPE | E1000_VMOLR_MPME);
5304
5305         if (*msgbuf & E1000_VF_SET_PROMISC_MULTICAST) {
5306                 vmolr |= E1000_VMOLR_MPME;
5307                 vf_data->flags |= IGB_VF_FLAG_MULTI_PROMISC;
5308                 *msgbuf &= ~E1000_VF_SET_PROMISC_MULTICAST;
5309         } else {
5310                 /* if we have hashes and we are clearing a multicast promisc
5311                  * flag we need to write the hashes to the MTA as this step
5312                  * was previously skipped
5313                  */
5314                 if (vf_data->num_vf_mc_hashes > 30) {
5315                         vmolr |= E1000_VMOLR_MPME;
5316                 } else if (vf_data->num_vf_mc_hashes) {
5317                         int j;
5318                         vmolr |= E1000_VMOLR_ROMPE;
5319                         for (j = 0; j < vf_data->num_vf_mc_hashes; j++)
5320                                 igb_mta_set(hw, vf_data->vf_mc_hashes[j]);
5321                 }
5322         }
5323
5324         wr32(E1000_VMOLR(vf), vmolr);
5325
5326         /* there are flags left unprocessed, likely not supported */
5327         if (*msgbuf & E1000_VT_MSGINFO_MASK)
5328                 return -EINVAL;
5329
5330         return 0;
5331 }
5332
5333 static int igb_set_vf_multicasts(struct igb_adapter *adapter,
5334                                   u32 *msgbuf, u32 vf)
5335 {
5336         int n = (msgbuf[0] & E1000_VT_MSGINFO_MASK) >> E1000_VT_MSGINFO_SHIFT;
5337         u16 *hash_list = (u16 *)&msgbuf[1];
5338         struct vf_data_storage *vf_data = &adapter->vf_data[vf];
5339         int i;
5340
5341         /* salt away the number of multicast addresses assigned
5342          * to this VF for later use to restore when the PF multi cast
5343          * list changes
5344          */
5345         vf_data->num_vf_mc_hashes = n;
5346
5347         /* only up to 30 hash values supported */
5348         if (n > 30)
5349                 n = 30;
5350
5351         /* store the hashes for later use */
5352         for (i = 0; i < n; i++)
5353                 vf_data->vf_mc_hashes[i] = hash_list[i];
5354
5355         /* Flush and reset the mta with the new values */
5356         igb_set_rx_mode(adapter->netdev);
5357
5358         return 0;
5359 }
5360
5361 static void igb_restore_vf_multicasts(struct igb_adapter *adapter)
5362 {
5363         struct e1000_hw *hw = &adapter->hw;
5364         struct vf_data_storage *vf_data;
5365         int i, j;
5366
5367         for (i = 0; i < adapter->vfs_allocated_count; i++) {
5368                 u32 vmolr = rd32(E1000_VMOLR(i));
5369                 vmolr &= ~(E1000_VMOLR_ROMPE | E1000_VMOLR_MPME);
5370
5371                 vf_data = &adapter->vf_data[i];
5372
5373                 if ((vf_data->num_vf_mc_hashes > 30) ||
5374                     (vf_data->flags & IGB_VF_FLAG_MULTI_PROMISC)) {
5375                         vmolr |= E1000_VMOLR_MPME;
5376                 } else if (vf_data->num_vf_mc_hashes) {
5377                         vmolr |= E1000_VMOLR_ROMPE;
5378                         for (j = 0; j < vf_data->num_vf_mc_hashes; j++)
5379                                 igb_mta_set(hw, vf_data->vf_mc_hashes[j]);
5380                 }
5381                 wr32(E1000_VMOLR(i), vmolr);
5382         }
5383 }
5384
5385 static void igb_clear_vf_vfta(struct igb_adapter *adapter, u32 vf)
5386 {
5387         struct e1000_hw *hw = &adapter->hw;
5388         u32 pool_mask, reg, vid;
5389         int i;
5390
5391         pool_mask = 1 << (E1000_VLVF_POOLSEL_SHIFT + vf);
5392
5393         /* Find the vlan filter for this id */
5394         for (i = 0; i < E1000_VLVF_ARRAY_SIZE; i++) {
5395                 reg = rd32(E1000_VLVF(i));
5396
5397                 /* remove the vf from the pool */
5398                 reg &= ~pool_mask;
5399
5400                 /* if pool is empty then remove entry from vfta */
5401                 if (!(reg & E1000_VLVF_POOLSEL_MASK) &&
5402                     (reg & E1000_VLVF_VLANID_ENABLE)) {
5403                         reg = 0;
5404                         vid = reg & E1000_VLVF_VLANID_MASK;
5405                         igb_vfta_set(hw, vid, false);
5406                 }
5407
5408                 wr32(E1000_VLVF(i), reg);
5409         }
5410
5411         adapter->vf_data[vf].vlans_enabled = 0;
5412 }
5413
5414 static s32 igb_vlvf_set(struct igb_adapter *adapter, u32 vid, bool add, u32 vf)
5415 {
5416         struct e1000_hw *hw = &adapter->hw;
5417         u32 reg, i;
5418
5419         /* The vlvf table only exists on 82576 hardware and newer */
5420         if (hw->mac.type < e1000_82576)
5421                 return -1;
5422
5423         /* we only need to do this if VMDq is enabled */
5424         if (!adapter->vfs_allocated_count)
5425                 return -1;
5426
5427         /* Find the vlan filter for this id */
5428         for (i = 0; i < E1000_VLVF_ARRAY_SIZE; i++) {
5429                 reg = rd32(E1000_VLVF(i));
5430                 if ((reg & E1000_VLVF_VLANID_ENABLE) &&
5431                     vid == (reg & E1000_VLVF_VLANID_MASK))
5432                         break;
5433         }
5434
5435         if (add) {
5436                 if (i == E1000_VLVF_ARRAY_SIZE) {
5437                         /* Did not find a matching VLAN ID entry that was
5438                          * enabled.  Search for a free filter entry, i.e.
5439                          * one without the enable bit set
5440                          */
5441                         for (i = 0; i < E1000_VLVF_ARRAY_SIZE; i++) {
5442                                 reg = rd32(E1000_VLVF(i));
5443                                 if (!(reg & E1000_VLVF_VLANID_ENABLE))
5444                                         break;
5445                         }
5446                 }
5447                 if (i < E1000_VLVF_ARRAY_SIZE) {
5448                         /* Found an enabled/available entry */
5449                         reg |= 1 << (E1000_VLVF_POOLSEL_SHIFT + vf);
5450
5451                         /* if !enabled we need to set this up in vfta */
5452                         if (!(reg & E1000_VLVF_VLANID_ENABLE)) {
5453                                 /* add VID to filter table */
5454                                 igb_vfta_set(hw, vid, true);
5455                                 reg |= E1000_VLVF_VLANID_ENABLE;
5456                         }
5457                         reg &= ~E1000_VLVF_VLANID_MASK;
5458                         reg |= vid;
5459                         wr32(E1000_VLVF(i), reg);
5460
5461                         /* do not modify RLPML for PF devices */
5462                         if (vf >= adapter->vfs_allocated_count)
5463                                 return 0;
5464
5465                         if (!adapter->vf_data[vf].vlans_enabled) {
5466                                 u32 size;
5467                                 reg = rd32(E1000_VMOLR(vf));
5468                                 size = reg & E1000_VMOLR_RLPML_MASK;
5469                                 size += 4;
5470                                 reg &= ~E1000_VMOLR_RLPML_MASK;
5471                                 reg |= size;
5472                                 wr32(E1000_VMOLR(vf), reg);
5473                         }
5474
5475                         adapter->vf_data[vf].vlans_enabled++;
5476                 }
5477         } else {
5478                 if (i < E1000_VLVF_ARRAY_SIZE) {
5479                         /* remove vf from the pool */
5480                         reg &= ~(1 << (E1000_VLVF_POOLSEL_SHIFT + vf));
5481                         /* if pool is empty then remove entry from vfta */
5482                         if (!(reg & E1000_VLVF_POOLSEL_MASK)) {
5483                                 reg = 0;
5484                                 igb_vfta_set(hw, vid, false);
5485                         }
5486                         wr32(E1000_VLVF(i), reg);
5487
5488                         /* do not modify RLPML for PF devices */
5489                         if (vf >= adapter->vfs_allocated_count)
5490                                 return 0;
5491
5492                         adapter->vf_data[vf].vlans_enabled--;
5493                         if (!adapter->vf_data[vf].vlans_enabled) {
5494                                 u32 size;
5495                                 reg = rd32(E1000_VMOLR(vf));
5496                                 size = reg & E1000_VMOLR_RLPML_MASK;
5497                                 size -= 4;
5498                                 reg &= ~E1000_VMOLR_RLPML_MASK;
5499                                 reg |= size;
5500                                 wr32(E1000_VMOLR(vf), reg);
5501                         }
5502                 }
5503         }
5504         return 0;
5505 }
5506
5507 static void igb_set_vmvir(struct igb_adapter *adapter, u32 vid, u32 vf)
5508 {
5509         struct e1000_hw *hw = &adapter->hw;
5510
5511         if (vid)
5512                 wr32(E1000_VMVIR(vf), (vid | E1000_VMVIR_VLANA_DEFAULT));
5513         else
5514                 wr32(E1000_VMVIR(vf), 0);
5515 }
5516
5517 static int igb_ndo_set_vf_vlan(struct net_device *netdev,
5518                                int vf, u16 vlan, u8 qos)
5519 {
5520         int err = 0;
5521         struct igb_adapter *adapter = netdev_priv(netdev);
5522
5523         if ((vf >= adapter->vfs_allocated_count) || (vlan > 4095) || (qos > 7))
5524                 return -EINVAL;
5525         if (vlan || qos) {
5526                 err = igb_vlvf_set(adapter, vlan, !!vlan, vf);
5527                 if (err)
5528                         goto out;
5529                 igb_set_vmvir(adapter, vlan | (qos << VLAN_PRIO_SHIFT), vf);
5530                 igb_set_vmolr(adapter, vf, !vlan);
5531                 adapter->vf_data[vf].pf_vlan = vlan;
5532                 adapter->vf_data[vf].pf_qos = qos;
5533                 dev_info(&adapter->pdev->dev,
5534                          "Setting VLAN %d, QOS 0x%x on VF %d\n", vlan, qos, vf);
5535                 if (test_bit(__IGB_DOWN, &adapter->state)) {
5536                         dev_warn(&adapter->pdev->dev,
5537                                  "The VF VLAN has been set, but the PF device is not up.\n");
5538                         dev_warn(&adapter->pdev->dev,
5539                                  "Bring the PF device up before attempting to use the VF device.\n");
5540                 }
5541         } else {
5542                 igb_vlvf_set(adapter, adapter->vf_data[vf].pf_vlan,
5543                              false, vf);
5544                 igb_set_vmvir(adapter, vlan, vf);
5545                 igb_set_vmolr(adapter, vf, true);
5546                 adapter->vf_data[vf].pf_vlan = 0;
5547                 adapter->vf_data[vf].pf_qos = 0;
5548         }
5549 out:
5550         return err;
5551 }
5552
5553 static int igb_find_vlvf_entry(struct igb_adapter *adapter, int vid)
5554 {
5555         struct e1000_hw *hw = &adapter->hw;
5556         int i;
5557         u32 reg;
5558
5559         /* Find the vlan filter for this id */
5560         for (i = 0; i < E1000_VLVF_ARRAY_SIZE; i++) {
5561                 reg = rd32(E1000_VLVF(i));
5562                 if ((reg & E1000_VLVF_VLANID_ENABLE) &&
5563                     vid == (reg & E1000_VLVF_VLANID_MASK))
5564                         break;
5565         }
5566
5567         if (i >= E1000_VLVF_ARRAY_SIZE)
5568                 i = -1;
5569
5570         return i;
5571 }
5572
5573 static int igb_set_vf_vlan(struct igb_adapter *adapter, u32 *msgbuf, u32 vf)
5574 {
5575         struct e1000_hw *hw = &adapter->hw;
5576         int add = (msgbuf[0] & E1000_VT_MSGINFO_MASK) >> E1000_VT_MSGINFO_SHIFT;
5577         int vid = (msgbuf[1] & E1000_VLVF_VLANID_MASK);
5578         int err = 0;
5579
5580         /* If in promiscuous mode we need to make sure the PF also has
5581          * the VLAN filter set.
5582          */
5583         if (add && (adapter->netdev->flags & IFF_PROMISC))
5584                 err = igb_vlvf_set(adapter, vid, add,
5585                                    adapter->vfs_allocated_count);
5586         if (err)
5587                 goto out;
5588
5589         err = igb_vlvf_set(adapter, vid, add, vf);
5590
5591         if (err)
5592                 goto out;
5593
5594         /* Go through all the checks to see if the VLAN filter should
5595          * be wiped completely.
5596          */
5597         if (!add && (adapter->netdev->flags & IFF_PROMISC)) {
5598                 u32 vlvf, bits;
5599
5600                 int regndx = igb_find_vlvf_entry(adapter, vid);
5601                 if (regndx < 0)
5602                         goto out;
5603                 /* See if any other pools are set for this VLAN filter
5604                  * entry other than the PF.
5605                  */
5606                 vlvf = bits = rd32(E1000_VLVF(regndx));
5607                 bits &= 1 << (E1000_VLVF_POOLSEL_SHIFT +
5608                               adapter->vfs_allocated_count);
5609                 /* If the filter was removed then ensure PF pool bit
5610                  * is cleared if the PF only added itself to the pool
5611                  * because the PF is in promiscuous mode.
5612                  */
5613                 if ((vlvf & VLAN_VID_MASK) == vid &&
5614                     !test_bit(vid, adapter->active_vlans) &&
5615                     !bits)
5616                         igb_vlvf_set(adapter, vid, add,
5617                                      adapter->vfs_allocated_count);
5618         }
5619
5620 out:
5621         return err;
5622 }
5623
5624 static inline void igb_vf_reset(struct igb_adapter *adapter, u32 vf)
5625 {
5626         /* clear flags - except flag that indicates PF has set the MAC */
5627         adapter->vf_data[vf].flags &= IGB_VF_FLAG_PF_SET_MAC;
5628         adapter->vf_data[vf].last_nack = jiffies;
5629
5630         /* reset offloads to defaults */
5631         igb_set_vmolr(adapter, vf, true);
5632
5633         /* reset vlans for device */
5634         igb_clear_vf_vfta(adapter, vf);
5635         if (adapter->vf_data[vf].pf_vlan)
5636                 igb_ndo_set_vf_vlan(adapter->netdev, vf,
5637                                     adapter->vf_data[vf].pf_vlan,
5638                                     adapter->vf_data[vf].pf_qos);
5639         else
5640                 igb_clear_vf_vfta(adapter, vf);
5641
5642         /* reset multicast table array for vf */
5643         adapter->vf_data[vf].num_vf_mc_hashes = 0;
5644
5645         /* Flush and reset the mta with the new values */
5646         igb_set_rx_mode(adapter->netdev);
5647 }
5648
5649 static void igb_vf_reset_event(struct igb_adapter *adapter, u32 vf)
5650 {
5651         unsigned char *vf_mac = adapter->vf_data[vf].vf_mac_addresses;
5652
5653         /* clear mac address as we were hotplug removed/added */
5654         if (!(adapter->vf_data[vf].flags & IGB_VF_FLAG_PF_SET_MAC))
5655                 eth_zero_addr(vf_mac);
5656
5657         /* process remaining reset events */
5658         igb_vf_reset(adapter, vf);
5659 }
5660
5661 static void igb_vf_reset_msg(struct igb_adapter *adapter, u32 vf)
5662 {
5663         struct e1000_hw *hw = &adapter->hw;
5664         unsigned char *vf_mac = adapter->vf_data[vf].vf_mac_addresses;
5665         int rar_entry = hw->mac.rar_entry_count - (vf + 1);
5666         u32 reg, msgbuf[3];
5667         u8 *addr = (u8 *)(&msgbuf[1]);
5668
5669         /* process all the same items cleared in a function level reset */
5670         igb_vf_reset(adapter, vf);
5671
5672         /* set vf mac address */
5673         igb_rar_set_qsel(adapter, vf_mac, rar_entry, vf);
5674
5675         /* enable transmit and receive for vf */
5676         reg = rd32(E1000_VFTE);
5677         wr32(E1000_VFTE, reg | (1 << vf));
5678         reg = rd32(E1000_VFRE);
5679         wr32(E1000_VFRE, reg | (1 << vf));
5680
5681         adapter->vf_data[vf].flags |= IGB_VF_FLAG_CTS;
5682
5683         /* reply to reset with ack and vf mac address */
5684         msgbuf[0] = E1000_VF_RESET | E1000_VT_MSGTYPE_ACK;
5685         memcpy(addr, vf_mac, 6);
5686         igb_write_mbx(hw, msgbuf, 3, vf);
5687 }
5688
5689 static int igb_set_vf_mac_addr(struct igb_adapter *adapter, u32 *msg, int vf)
5690 {
5691         /* The VF MAC Address is stored in a packed array of bytes
5692          * starting at the second 32 bit word of the msg array
5693          */
5694         unsigned char *addr = (char *)&msg[1];
5695         int err = -1;
5696
5697         if (is_valid_ether_addr(addr))
5698                 err = igb_set_vf_mac(adapter, vf, addr);
5699
5700         return err;
5701 }
5702
5703 static void igb_rcv_ack_from_vf(struct igb_adapter *adapter, u32 vf)
5704 {
5705         struct e1000_hw *hw = &adapter->hw;
5706         struct vf_data_storage *vf_data = &adapter->vf_data[vf];
5707         u32 msg = E1000_VT_MSGTYPE_NACK;
5708
5709         /* if device isn't clear to send it shouldn't be reading either */
5710         if (!(vf_data->flags & IGB_VF_FLAG_CTS) &&
5711             time_after(jiffies, vf_data->last_nack + (2 * HZ))) {
5712                 igb_write_mbx(hw, &msg, 1, vf);
5713                 vf_data->last_nack = jiffies;
5714         }
5715 }
5716
5717 static void igb_rcv_msg_from_vf(struct igb_adapter *adapter, u32 vf)
5718 {
5719         struct pci_dev *pdev = adapter->pdev;
5720         u32 msgbuf[E1000_VFMAILBOX_SIZE];
5721         struct e1000_hw *hw = &adapter->hw;
5722         struct vf_data_storage *vf_data = &adapter->vf_data[vf];
5723         s32 retval;
5724
5725         retval = igb_read_mbx(hw, msgbuf, E1000_VFMAILBOX_SIZE, vf);
5726
5727         if (retval) {
5728                 /* if receive failed revoke VF CTS stats and restart init */
5729                 dev_err(&pdev->dev, "Error receiving message from VF\n");
5730                 vf_data->flags &= ~IGB_VF_FLAG_CTS;
5731                 if (!time_after(jiffies, vf_data->last_nack + (2 * HZ)))
5732                         return;
5733                 goto out;
5734         }
5735
5736         /* this is a message we already processed, do nothing */
5737         if (msgbuf[0] & (E1000_VT_MSGTYPE_ACK | E1000_VT_MSGTYPE_NACK))
5738                 return;
5739
5740         /* until the vf completes a reset it should not be
5741          * allowed to start any configuration.
5742          */
5743         if (msgbuf[0] == E1000_VF_RESET) {
5744                 igb_vf_reset_msg(adapter, vf);
5745                 return;
5746         }
5747
5748         if (!(vf_data->flags & IGB_VF_FLAG_CTS)) {
5749                 if (!time_after(jiffies, vf_data->last_nack + (2 * HZ)))
5750                         return;
5751                 retval = -1;
5752                 goto out;
5753         }
5754
5755         switch ((msgbuf[0] & 0xFFFF)) {
5756         case E1000_VF_SET_MAC_ADDR:
5757                 retval = -EINVAL;
5758                 if (!(vf_data->flags & IGB_VF_FLAG_PF_SET_MAC))
5759                         retval = igb_set_vf_mac_addr(adapter, msgbuf, vf);
5760                 else
5761                         dev_warn(&pdev->dev,
5762                                  "VF %d attempted to override administratively set MAC address\nReload the VF driver to resume operations\n",
5763                                  vf);
5764                 break;
5765         case E1000_VF_SET_PROMISC:
5766                 retval = igb_set_vf_promisc(adapter, msgbuf, vf);
5767                 break;
5768         case E1000_VF_SET_MULTICAST:
5769                 retval = igb_set_vf_multicasts(adapter, msgbuf, vf);
5770                 break;
5771         case E1000_VF_SET_LPE:
5772                 retval = igb_set_vf_rlpml(adapter, msgbuf[1], vf);
5773                 break;
5774         case E1000_VF_SET_VLAN:
5775                 retval = -1;
5776                 if (vf_data->pf_vlan)
5777                         dev_warn(&pdev->dev,
5778                                  "VF %d attempted to override administratively set VLAN tag\nReload the VF driver to resume operations\n",
5779                                  vf);
5780                 else
5781                         retval = igb_set_vf_vlan(adapter, msgbuf, vf);
5782                 break;
5783         default:
5784                 dev_err(&pdev->dev, "Unhandled Msg %08x\n", msgbuf[0]);
5785                 retval = -1;
5786                 break;
5787         }
5788
5789         msgbuf[0] |= E1000_VT_MSGTYPE_CTS;
5790 out:
5791         /* notify the VF of the results of what it sent us */
5792         if (retval)
5793                 msgbuf[0] |= E1000_VT_MSGTYPE_NACK;
5794         else
5795                 msgbuf[0] |= E1000_VT_MSGTYPE_ACK;
5796
5797         igb_write_mbx(hw, msgbuf, 1, vf);
5798 }
5799
5800 static void igb_msg_task(struct igb_adapter *adapter)
5801 {
5802         struct e1000_hw *hw = &adapter->hw;
5803         u32 vf;
5804
5805         for (vf = 0; vf < adapter->vfs_allocated_count; vf++) {
5806                 /* process any reset requests */
5807                 if (!igb_check_for_rst(hw, vf))
5808                         igb_vf_reset_event(adapter, vf);
5809
5810                 /* process any messages pending */
5811                 if (!igb_check_for_msg(hw, vf))
5812                         igb_rcv_msg_from_vf(adapter, vf);
5813
5814                 /* process any acks */
5815                 if (!igb_check_for_ack(hw, vf))
5816                         igb_rcv_ack_from_vf(adapter, vf);
5817         }
5818 }
5819
5820 /**
5821  *  igb_set_uta - Set unicast filter table address
5822  *  @adapter: board private structure
5823  *
5824  *  The unicast table address is a register array of 32-bit registers.
5825  *  The table is meant to be used in a way similar to how the MTA is used
5826  *  however due to certain limitations in the hardware it is necessary to
5827  *  set all the hash bits to 1 and use the VMOLR ROPE bit as a promiscuous
5828  *  enable bit to allow vlan tag stripping when promiscuous mode is enabled
5829  **/
5830 static void igb_set_uta(struct igb_adapter *adapter)
5831 {
5832         struct e1000_hw *hw = &adapter->hw;
5833         int i;
5834
5835         /* The UTA table only exists on 82576 hardware and newer */
5836         if (hw->mac.type < e1000_82576)
5837                 return;
5838
5839         /* we only need to do this if VMDq is enabled */
5840         if (!adapter->vfs_allocated_count)
5841                 return;
5842
5843         for (i = 0; i < hw->mac.uta_reg_count; i++)
5844                 array_wr32(E1000_UTA, i, ~0);
5845 }
5846
5847 /**
5848  *  igb_intr_msi - Interrupt Handler
5849  *  @irq: interrupt number
5850  *  @data: pointer to a network interface device structure
5851  **/
5852 static irqreturn_t igb_intr_msi(int irq, void *data)
5853 {
5854         struct igb_adapter *adapter = data;
5855         struct igb_q_vector *q_vector = adapter->q_vector[0];
5856         struct e1000_hw *hw = &adapter->hw;
5857         /* read ICR disables interrupts using IAM */
5858         u32 icr = rd32(E1000_ICR);
5859
5860         igb_write_itr(q_vector);
5861
5862         if (icr & E1000_ICR_DRSTA)
5863                 schedule_work(&adapter->reset_task);
5864
5865         if (icr & E1000_ICR_DOUTSYNC) {
5866                 /* HW is reporting DMA is out of sync */
5867                 adapter->stats.doosync++;
5868         }
5869
5870         if (icr & (E1000_ICR_RXSEQ | E1000_ICR_LSC)) {
5871                 hw->mac.get_link_status = 1;
5872                 if (!test_bit(__IGB_DOWN, &adapter->state))
5873                         mod_timer(&adapter->watchdog_timer, jiffies + 1);
5874         }
5875
5876         if (icr & E1000_ICR_TS) {
5877                 u32 tsicr = rd32(E1000_TSICR);
5878
5879                 if (tsicr & E1000_TSICR_TXTS) {
5880                         /* acknowledge the interrupt */
5881                         wr32(E1000_TSICR, E1000_TSICR_TXTS);
5882                         /* retrieve hardware timestamp */
5883                         schedule_work(&adapter->ptp_tx_work);
5884                 }
5885         }
5886
5887         napi_schedule(&q_vector->napi);
5888
5889         return IRQ_HANDLED;
5890 }
5891
5892 /**
5893  *  igb_intr - Legacy Interrupt Handler
5894  *  @irq: interrupt number
5895  *  @data: pointer to a network interface device structure
5896  **/
5897 static irqreturn_t igb_intr(int irq, void *data)
5898 {
5899         struct igb_adapter *adapter = data;
5900         struct igb_q_vector *q_vector = adapter->q_vector[0];
5901         struct e1000_hw *hw = &adapter->hw;
5902         /* Interrupt Auto-Mask...upon reading ICR, interrupts are masked.  No
5903          * need for the IMC write
5904          */
5905         u32 icr = rd32(E1000_ICR);
5906
5907         /* IMS will not auto-mask if INT_ASSERTED is not set, and if it is
5908          * not set, then the adapter didn't send an interrupt
5909          */
5910         if (!(icr & E1000_ICR_INT_ASSERTED))
5911                 return IRQ_NONE;
5912
5913         igb_write_itr(q_vector);
5914
5915         if (icr & E1000_ICR_DRSTA)
5916                 schedule_work(&adapter->reset_task);
5917
5918         if (icr & E1000_ICR_DOUTSYNC) {
5919                 /* HW is reporting DMA is out of sync */
5920                 adapter->stats.doosync++;
5921         }
5922
5923         if (icr & (E1000_ICR_RXSEQ | E1000_ICR_LSC)) {
5924                 hw->mac.get_link_status = 1;
5925                 /* guard against interrupt when we're going down */
5926                 if (!test_bit(__IGB_DOWN, &adapter->state))
5927                         mod_timer(&adapter->watchdog_timer, jiffies + 1);
5928         }
5929
5930         if (icr & E1000_ICR_TS) {
5931                 u32 tsicr = rd32(E1000_TSICR);
5932
5933                 if (tsicr & E1000_TSICR_TXTS) {
5934                         /* acknowledge the interrupt */
5935                         wr32(E1000_TSICR, E1000_TSICR_TXTS);
5936                         /* retrieve hardware timestamp */
5937                         schedule_work(&adapter->ptp_tx_work);
5938                 }
5939         }
5940
5941         napi_schedule(&q_vector->napi);
5942
5943         return IRQ_HANDLED;
5944 }
5945
5946 static void igb_ring_irq_enable(struct igb_q_vector *q_vector)
5947 {
5948         struct igb_adapter *adapter = q_vector->adapter;
5949         struct e1000_hw *hw = &adapter->hw;
5950
5951         if ((q_vector->rx.ring && (adapter->rx_itr_setting & 3)) ||
5952             (!q_vector->rx.ring && (adapter->tx_itr_setting & 3))) {
5953                 if ((adapter->num_q_vectors == 1) && !adapter->vf_data)
5954                         igb_set_itr(q_vector);
5955                 else
5956                         igb_update_ring_itr(q_vector);
5957         }
5958
5959         if (!test_bit(__IGB_DOWN, &adapter->state)) {
5960                 if (adapter->msix_entries)
5961                         wr32(E1000_EIMS, q_vector->eims_value);
5962                 else
5963                         igb_irq_enable(adapter);
5964         }
5965 }
5966
5967 /**
5968  *  igb_poll - NAPI Rx polling callback
5969  *  @napi: napi polling structure
5970  *  @budget: count of how many packets we should handle
5971  **/
5972 static int igb_poll(struct napi_struct *napi, int budget)
5973 {
5974         struct igb_q_vector *q_vector = container_of(napi,
5975                                                      struct igb_q_vector,
5976                                                      napi);
5977         bool clean_complete = true;
5978
5979 #ifdef CONFIG_IGB_DCA
5980         if (q_vector->adapter->flags & IGB_FLAG_DCA_ENABLED)
5981                 igb_update_dca(q_vector);
5982 #endif
5983         if (q_vector->tx.ring)
5984                 clean_complete = igb_clean_tx_irq(q_vector);
5985
5986         if (q_vector->rx.ring)
5987                 clean_complete &= igb_clean_rx_irq(q_vector, budget);
5988
5989         /* If all work not completed, return budget and keep polling */
5990         if (!clean_complete)
5991                 return budget;
5992
5993         /* If not enough Rx work done, exit the polling mode */
5994         napi_complete(napi);
5995         igb_ring_irq_enable(q_vector);
5996
5997         return 0;
5998 }
5999
6000 /**
6001  *  igb_clean_tx_irq - Reclaim resources after transmit completes
6002  *  @q_vector: pointer to q_vector containing needed info
6003  *
6004  *  returns true if ring is completely cleaned
6005  **/
6006 static bool igb_clean_tx_irq(struct igb_q_vector *q_vector)
6007 {
6008         struct igb_adapter *adapter = q_vector->adapter;
6009         struct igb_ring *tx_ring = q_vector->tx.ring;
6010         struct igb_tx_buffer *tx_buffer;
6011         union e1000_adv_tx_desc *tx_desc;
6012         unsigned int total_bytes = 0, total_packets = 0;
6013         unsigned int budget = q_vector->tx.work_limit;
6014         unsigned int i = tx_ring->next_to_clean;
6015
6016         if (test_bit(__IGB_DOWN, &adapter->state))
6017                 return true;
6018
6019         tx_buffer = &tx_ring->tx_buffer_info[i];
6020         tx_desc = IGB_TX_DESC(tx_ring, i);
6021         i -= tx_ring->count;
6022
6023         do {
6024                 union e1000_adv_tx_desc *eop_desc = tx_buffer->next_to_watch;
6025
6026                 /* if next_to_watch is not set then there is no work pending */
6027                 if (!eop_desc)
6028                         break;
6029
6030                 /* prevent any other reads prior to eop_desc */
6031                 read_barrier_depends();
6032
6033                 /* if DD is not set pending work has not been completed */
6034                 if (!(eop_desc->wb.status & cpu_to_le32(E1000_TXD_STAT_DD)))
6035                         break;
6036
6037                 /* clear next_to_watch to prevent false hangs */
6038                 tx_buffer->next_to_watch = NULL;
6039
6040                 /* update the statistics for this packet */
6041                 total_bytes += tx_buffer->bytecount;
6042                 total_packets += tx_buffer->gso_segs;
6043
6044                 /* free the skb */
6045                 dev_kfree_skb_any(tx_buffer->skb);
6046
6047                 /* unmap skb header data */
6048                 dma_unmap_single(tx_ring->dev,
6049                                  dma_unmap_addr(tx_buffer, dma),
6050                                  dma_unmap_len(tx_buffer, len),
6051                                  DMA_TO_DEVICE);
6052
6053                 /* clear tx_buffer data */
6054                 tx_buffer->skb = NULL;
6055                 dma_unmap_len_set(tx_buffer, len, 0);
6056
6057                 /* clear last DMA location and unmap remaining buffers */
6058                 while (tx_desc != eop_desc) {
6059                         tx_buffer++;
6060                         tx_desc++;
6061                         i++;
6062                         if (unlikely(!i)) {
6063                                 i -= tx_ring->count;
6064                                 tx_buffer = tx_ring->tx_buffer_info;
6065                                 tx_desc = IGB_TX_DESC(tx_ring, 0);
6066                         }
6067
6068                         /* unmap any remaining paged data */
6069                         if (dma_unmap_len(tx_buffer, len)) {
6070                                 dma_unmap_page(tx_ring->dev,
6071                                                dma_unmap_addr(tx_buffer, dma),
6072                                                dma_unmap_len(tx_buffer, len),
6073                                                DMA_TO_DEVICE);
6074                                 dma_unmap_len_set(tx_buffer, len, 0);
6075                         }
6076                 }
6077
6078                 /* move us one more past the eop_desc for start of next pkt */
6079                 tx_buffer++;
6080                 tx_desc++;
6081                 i++;
6082                 if (unlikely(!i)) {
6083                         i -= tx_ring->count;
6084                         tx_buffer = tx_ring->tx_buffer_info;
6085                         tx_desc = IGB_TX_DESC(tx_ring, 0);
6086                 }
6087
6088                 /* issue prefetch for next Tx descriptor */
6089                 prefetch(tx_desc);
6090
6091                 /* update budget accounting */
6092                 budget--;
6093         } while (likely(budget));
6094
6095         netdev_tx_completed_queue(txring_txq(tx_ring),
6096                                   total_packets, total_bytes);
6097         i += tx_ring->count;
6098         tx_ring->next_to_clean = i;
6099         u64_stats_update_begin(&tx_ring->tx_syncp);
6100         tx_ring->tx_stats.bytes += total_bytes;
6101         tx_ring->tx_stats.packets += total_packets;
6102         u64_stats_update_end(&tx_ring->tx_syncp);
6103         q_vector->tx.total_bytes += total_bytes;
6104         q_vector->tx.total_packets += total_packets;
6105
6106         if (test_bit(IGB_RING_FLAG_TX_DETECT_HANG, &tx_ring->flags)) {
6107                 struct e1000_hw *hw = &adapter->hw;
6108
6109                 /* Detect a transmit hang in hardware, this serializes the
6110                  * check with the clearing of time_stamp and movement of i
6111                  */
6112                 clear_bit(IGB_RING_FLAG_TX_DETECT_HANG, &tx_ring->flags);
6113                 if (tx_buffer->next_to_watch &&
6114                     time_after(jiffies, tx_buffer->time_stamp +
6115                                (adapter->tx_timeout_factor * HZ)) &&
6116                     !(rd32(E1000_STATUS) & E1000_STATUS_TXOFF)) {
6117
6118                         /* detected Tx unit hang */
6119                         dev_err(tx_ring->dev,
6120                                 "Detected Tx Unit Hang\n"
6121                                 "  Tx Queue             <%d>\n"
6122                                 "  TDH                  <%x>\n"
6123                                 "  TDT                  <%x>\n"
6124                                 "  next_to_use          <%x>\n"
6125                                 "  next_to_clean        <%x>\n"
6126                                 "buffer_info[next_to_clean]\n"
6127                                 "  time_stamp           <%lx>\n"
6128                                 "  next_to_watch        <%p>\n"
6129                                 "  jiffies              <%lx>\n"
6130                                 "  desc.status          <%x>\n",
6131                                 tx_ring->queue_index,
6132                                 rd32(E1000_TDH(tx_ring->reg_idx)),
6133                                 readl(tx_ring->tail),
6134                                 tx_ring->next_to_use,
6135                                 tx_ring->next_to_clean,
6136                                 tx_buffer->time_stamp,
6137                                 tx_buffer->next_to_watch,
6138                                 jiffies,
6139                                 tx_buffer->next_to_watch->wb.status);
6140                         netif_stop_subqueue(tx_ring->netdev,
6141                                             tx_ring->queue_index);
6142
6143                         /* we are about to reset, no point in enabling stuff */
6144                         return true;
6145                 }
6146         }
6147
6148 #define TX_WAKE_THRESHOLD (DESC_NEEDED * 2)
6149         if (unlikely(total_packets &&
6150             netif_carrier_ok(tx_ring->netdev) &&
6151             igb_desc_unused(tx_ring) >= TX_WAKE_THRESHOLD)) {
6152                 /* Make sure that anybody stopping the queue after this
6153                  * sees the new next_to_clean.
6154                  */
6155                 smp_mb();
6156                 if (__netif_subqueue_stopped(tx_ring->netdev,
6157                                              tx_ring->queue_index) &&
6158                     !(test_bit(__IGB_DOWN, &adapter->state))) {
6159                         netif_wake_subqueue(tx_ring->netdev,
6160                                             tx_ring->queue_index);
6161
6162                         u64_stats_update_begin(&tx_ring->tx_syncp);
6163                         tx_ring->tx_stats.restart_queue++;
6164                         u64_stats_update_end(&tx_ring->tx_syncp);
6165                 }
6166         }
6167
6168         return !!budget;
6169 }
6170
6171 /**
6172  *  igb_reuse_rx_page - page flip buffer and store it back on the ring
6173  *  @rx_ring: rx descriptor ring to store buffers on
6174  *  @old_buff: donor buffer to have page reused
6175  *
6176  *  Synchronizes page for reuse by the adapter
6177  **/
6178 static void igb_reuse_rx_page(struct igb_ring *rx_ring,
6179                               struct igb_rx_buffer *old_buff)
6180 {
6181         struct igb_rx_buffer *new_buff;
6182         u16 nta = rx_ring->next_to_alloc;
6183
6184         new_buff = &rx_ring->rx_buffer_info[nta];
6185
6186         /* update, and store next to alloc */
6187         nta++;
6188         rx_ring->next_to_alloc = (nta < rx_ring->count) ? nta : 0;
6189
6190         /* transfer page from old buffer to new buffer */
6191         memcpy(new_buff, old_buff, sizeof(struct igb_rx_buffer));
6192
6193         /* sync the buffer for use by the device */
6194         dma_sync_single_range_for_device(rx_ring->dev, old_buff->dma,
6195                                          old_buff->page_offset,
6196                                          IGB_RX_BUFSZ,
6197                                          DMA_FROM_DEVICE);
6198 }
6199
6200 static bool igb_can_reuse_rx_page(struct igb_rx_buffer *rx_buffer,
6201                                   struct page *page,
6202                                   unsigned int truesize)
6203 {
6204         /* avoid re-using remote pages */
6205         if (unlikely(page_to_nid(page) != numa_node_id()))
6206                 return false;
6207
6208 #if (PAGE_SIZE < 8192)
6209         /* if we are only owner of page we can reuse it */
6210         if (unlikely(page_count(page) != 1))
6211                 return false;
6212
6213         /* flip page offset to other buffer */
6214         rx_buffer->page_offset ^= IGB_RX_BUFSZ;
6215
6216         /* since we are the only owner of the page and we need to
6217          * increment it, just set the value to 2 in order to avoid
6218          * an unnecessary locked operation
6219          */
6220         atomic_set(&page->_count, 2);
6221 #else
6222         /* move offset up to the next cache line */
6223         rx_buffer->page_offset += truesize;
6224
6225         if (rx_buffer->page_offset > (PAGE_SIZE - IGB_RX_BUFSZ))
6226                 return false;
6227
6228         /* bump ref count on page before it is given to the stack */
6229         get_page(page);
6230 #endif
6231
6232         return true;
6233 }
6234
6235 /**
6236  *  igb_add_rx_frag - Add contents of Rx buffer to sk_buff
6237  *  @rx_ring: rx descriptor ring to transact packets on
6238  *  @rx_buffer: buffer containing page to add
6239  *  @rx_desc: descriptor containing length of buffer written by hardware
6240  *  @skb: sk_buff to place the data into
6241  *
6242  *  This function will add the data contained in rx_buffer->page to the skb.
6243  *  This is done either through a direct copy if the data in the buffer is
6244  *  less than the skb header size, otherwise it will just attach the page as
6245  *  a frag to the skb.
6246  *
6247  *  The function will then update the page offset if necessary and return
6248  *  true if the buffer can be reused by the adapter.
6249  **/
6250 static bool igb_add_rx_frag(struct igb_ring *rx_ring,
6251                             struct igb_rx_buffer *rx_buffer,
6252                             union e1000_adv_rx_desc *rx_desc,
6253                             struct sk_buff *skb)
6254 {
6255         struct page *page = rx_buffer->page;
6256         unsigned int size = le16_to_cpu(rx_desc->wb.upper.length);
6257 #if (PAGE_SIZE < 8192)
6258         unsigned int truesize = IGB_RX_BUFSZ;
6259 #else
6260         unsigned int truesize = ALIGN(size, L1_CACHE_BYTES);
6261 #endif
6262
6263         if ((size <= IGB_RX_HDR_LEN) && !skb_is_nonlinear(skb)) {
6264                 unsigned char *va = page_address(page) + rx_buffer->page_offset;
6265
6266                 if (igb_test_staterr(rx_desc, E1000_RXDADV_STAT_TSIP)) {
6267                         igb_ptp_rx_pktstamp(rx_ring->q_vector, va, skb);
6268                         va += IGB_TS_HDR_LEN;
6269                         size -= IGB_TS_HDR_LEN;
6270                 }
6271
6272                 memcpy(__skb_put(skb, size), va, ALIGN(size, sizeof(long)));
6273
6274                 /* we can reuse buffer as-is, just make sure it is local */
6275                 if (likely(page_to_nid(page) == numa_node_id()))
6276                         return true;
6277
6278                 /* this page cannot be reused so discard it */
6279                 put_page(page);
6280                 return false;
6281         }
6282
6283         skb_add_rx_frag(skb, skb_shinfo(skb)->nr_frags, page,
6284                         rx_buffer->page_offset, size, truesize);
6285
6286         return igb_can_reuse_rx_page(rx_buffer, page, truesize);
6287 }
6288
6289 static struct sk_buff *igb_fetch_rx_buffer(struct igb_ring *rx_ring,
6290                                            union e1000_adv_rx_desc *rx_desc,
6291                                            struct sk_buff *skb)
6292 {
6293         struct igb_rx_buffer *rx_buffer;
6294         struct page *page;
6295
6296         rx_buffer = &rx_ring->rx_buffer_info[rx_ring->next_to_clean];
6297
6298         page = rx_buffer->page;
6299         prefetchw(page);
6300
6301         if (likely(!skb)) {
6302                 void *page_addr = page_address(page) +
6303                                   rx_buffer->page_offset;
6304
6305                 /* prefetch first cache line of first page */
6306                 prefetch(page_addr);
6307 #if L1_CACHE_BYTES < 128
6308                 prefetch(page_addr + L1_CACHE_BYTES);
6309 #endif
6310
6311                 /* allocate a skb to store the frags */
6312                 skb = netdev_alloc_skb_ip_align(rx_ring->netdev,
6313                                                 IGB_RX_HDR_LEN);
6314                 if (unlikely(!skb)) {
6315                         rx_ring->rx_stats.alloc_failed++;
6316                         return NULL;
6317                 }
6318
6319                 /* we will be copying header into skb->data in
6320                  * pskb_may_pull so it is in our interest to prefetch
6321                  * it now to avoid a possible cache miss
6322                  */
6323                 prefetchw(skb->data);
6324         }
6325
6326         /* we are reusing so sync this buffer for CPU use */
6327         dma_sync_single_range_for_cpu(rx_ring->dev,
6328                                       rx_buffer->dma,
6329                                       rx_buffer->page_offset,
6330                                       IGB_RX_BUFSZ,
6331                                       DMA_FROM_DEVICE);
6332
6333         /* pull page into skb */
6334         if (igb_add_rx_frag(rx_ring, rx_buffer, rx_desc, skb)) {
6335                 /* hand second half of page back to the ring */
6336                 igb_reuse_rx_page(rx_ring, rx_buffer);
6337         } else {
6338                 /* we are not reusing the buffer so unmap it */
6339                 dma_unmap_page(rx_ring->dev, rx_buffer->dma,
6340                                PAGE_SIZE, DMA_FROM_DEVICE);
6341         }
6342
6343         /* clear contents of rx_buffer */
6344         rx_buffer->page = NULL;
6345
6346         return skb;
6347 }
6348
6349 static inline void igb_rx_checksum(struct igb_ring *ring,
6350                                    union e1000_adv_rx_desc *rx_desc,
6351                                    struct sk_buff *skb)
6352 {
6353         skb_checksum_none_assert(skb);
6354
6355         /* Ignore Checksum bit is set */
6356         if (igb_test_staterr(rx_desc, E1000_RXD_STAT_IXSM))
6357                 return;
6358
6359         /* Rx checksum disabled via ethtool */
6360         if (!(ring->netdev->features & NETIF_F_RXCSUM))
6361                 return;
6362
6363         /* TCP/UDP checksum error bit is set */
6364         if (igb_test_staterr(rx_desc,
6365                              E1000_RXDEXT_STATERR_TCPE |
6366                              E1000_RXDEXT_STATERR_IPE)) {
6367                 /* work around errata with sctp packets where the TCPE aka
6368                  * L4E bit is set incorrectly on 64 byte (60 byte w/o crc)
6369                  * packets, (aka let the stack check the crc32c)
6370                  */
6371                 if (!((skb->len == 60) &&
6372                       test_bit(IGB_RING_FLAG_RX_SCTP_CSUM, &ring->flags))) {
6373                         u64_stats_update_begin(&ring->rx_syncp);
6374                         ring->rx_stats.csum_err++;
6375                         u64_stats_update_end(&ring->rx_syncp);
6376                 }
6377                 /* let the stack verify checksum errors */
6378                 return;
6379         }
6380         /* It must be a TCP or UDP packet with a valid checksum */
6381         if (igb_test_staterr(rx_desc, E1000_RXD_STAT_TCPCS |
6382                                       E1000_RXD_STAT_UDPCS))
6383                 skb->ip_summed = CHECKSUM_UNNECESSARY;
6384
6385         dev_dbg(ring->dev, "cksum success: bits %08X\n",
6386                 le32_to_cpu(rx_desc->wb.upper.status_error));
6387 }
6388
6389 static inline void igb_rx_hash(struct igb_ring *ring,
6390                                union e1000_adv_rx_desc *rx_desc,
6391                                struct sk_buff *skb)
6392 {
6393         if (ring->netdev->features & NETIF_F_RXHASH)
6394                 skb->rxhash = le32_to_cpu(rx_desc->wb.lower.hi_dword.rss);
6395 }
6396
6397 /**
6398  *  igb_is_non_eop - process handling of non-EOP buffers
6399  *  @rx_ring: Rx ring being processed
6400  *  @rx_desc: Rx descriptor for current buffer
6401  *  @skb: current socket buffer containing buffer in progress
6402  *
6403  *  This function updates next to clean.  If the buffer is an EOP buffer
6404  *  this function exits returning false, otherwise it will place the
6405  *  sk_buff in the next buffer to be chained and return true indicating
6406  *  that this is in fact a non-EOP buffer.
6407  **/
6408 static bool igb_is_non_eop(struct igb_ring *rx_ring,
6409                            union e1000_adv_rx_desc *rx_desc)
6410 {
6411         u32 ntc = rx_ring->next_to_clean + 1;
6412
6413         /* fetch, update, and store next to clean */
6414         ntc = (ntc < rx_ring->count) ? ntc : 0;
6415         rx_ring->next_to_clean = ntc;
6416
6417         prefetch(IGB_RX_DESC(rx_ring, ntc));
6418
6419         if (likely(igb_test_staterr(rx_desc, E1000_RXD_STAT_EOP)))
6420                 return false;
6421
6422         return true;
6423 }
6424
6425 /**
6426  *  igb_get_headlen - determine size of header for LRO/GRO
6427  *  @data: pointer to the start of the headers
6428  *  @max_len: total length of section to find headers in
6429  *
6430  *  This function is meant to determine the length of headers that will
6431  *  be recognized by hardware for LRO, and GRO offloads.  The main
6432  *  motivation of doing this is to only perform one pull for IPv4 TCP
6433  *  packets so that we can do basic things like calculating the gso_size
6434  *  based on the average data per packet.
6435  **/
6436 static unsigned int igb_get_headlen(unsigned char *data,
6437                                     unsigned int max_len)
6438 {
6439         union {
6440                 unsigned char *network;
6441                 /* l2 headers */
6442                 struct ethhdr *eth;
6443                 struct vlan_hdr *vlan;
6444                 /* l3 headers */
6445                 struct iphdr *ipv4;
6446                 struct ipv6hdr *ipv6;
6447         } hdr;
6448         __be16 protocol;
6449         u8 nexthdr = 0; /* default to not TCP */
6450         u8 hlen;
6451
6452         /* this should never happen, but better safe than sorry */
6453         if (max_len < ETH_HLEN)
6454                 return max_len;
6455
6456         /* initialize network frame pointer */
6457         hdr.network = data;
6458
6459         /* set first protocol and move network header forward */
6460         protocol = hdr.eth->h_proto;
6461         hdr.network += ETH_HLEN;
6462
6463         /* handle any vlan tag if present */
6464         if (protocol == __constant_htons(ETH_P_8021Q)) {
6465                 if ((hdr.network - data) > (max_len - VLAN_HLEN))
6466                         return max_len;
6467
6468                 protocol = hdr.vlan->h_vlan_encapsulated_proto;
6469                 hdr.network += VLAN_HLEN;
6470         }
6471
6472         /* handle L3 protocols */
6473         if (protocol == __constant_htons(ETH_P_IP)) {
6474                 if ((hdr.network - data) > (max_len - sizeof(struct iphdr)))
6475                         return max_len;
6476
6477                 /* access ihl as a u8 to avoid unaligned access on ia64 */
6478                 hlen = (hdr.network[0] & 0x0F) << 2;
6479
6480                 /* verify hlen meets minimum size requirements */
6481                 if (hlen < sizeof(struct iphdr))
6482                         return hdr.network - data;
6483
6484                 /* record next protocol if header is present */
6485                 if (!(hdr.ipv4->frag_off & htons(IP_OFFSET)))
6486                         nexthdr = hdr.ipv4->protocol;
6487         } else if (protocol == __constant_htons(ETH_P_IPV6)) {
6488                 if ((hdr.network - data) > (max_len - sizeof(struct ipv6hdr)))
6489                         return max_len;
6490
6491                 /* record next protocol */
6492                 nexthdr = hdr.ipv6->nexthdr;
6493                 hlen = sizeof(struct ipv6hdr);
6494         } else {
6495                 return hdr.network - data;
6496         }
6497
6498         /* relocate pointer to start of L4 header */
6499         hdr.network += hlen;
6500
6501         /* finally sort out TCP */
6502         if (nexthdr == IPPROTO_TCP) {
6503                 if ((hdr.network - data) > (max_len - sizeof(struct tcphdr)))
6504                         return max_len;
6505
6506                 /* access doff as a u8 to avoid unaligned access on ia64 */
6507                 hlen = (hdr.network[12] & 0xF0) >> 2;
6508
6509                 /* verify hlen meets minimum size requirements */
6510                 if (hlen < sizeof(struct tcphdr))
6511                         return hdr.network - data;
6512
6513                 hdr.network += hlen;
6514         } else if (nexthdr == IPPROTO_UDP) {
6515                 if ((hdr.network - data) > (max_len - sizeof(struct udphdr)))
6516                         return max_len;
6517
6518                 hdr.network += sizeof(struct udphdr);
6519         }
6520
6521         /* If everything has gone correctly hdr.network should be the
6522          * data section of the packet and will be the end of the header.
6523          * If not then it probably represents the end of the last recognized
6524          * header.
6525          */
6526         if ((hdr.network - data) < max_len)
6527                 return hdr.network - data;
6528         else
6529                 return max_len;
6530 }
6531
6532 /**
6533  *  igb_pull_tail - igb specific version of skb_pull_tail
6534  *  @rx_ring: rx descriptor ring packet is being transacted on
6535  *  @rx_desc: pointer to the EOP Rx descriptor
6536  *  @skb: pointer to current skb being adjusted
6537  *
6538  *  This function is an igb specific version of __pskb_pull_tail.  The
6539  *  main difference between this version and the original function is that
6540  *  this function can make several assumptions about the state of things
6541  *  that allow for significant optimizations versus the standard function.
6542  *  As a result we can do things like drop a frag and maintain an accurate
6543  *  truesize for the skb.
6544  */
6545 static void igb_pull_tail(struct igb_ring *rx_ring,
6546                           union e1000_adv_rx_desc *rx_desc,
6547                           struct sk_buff *skb)
6548 {
6549         struct skb_frag_struct *frag = &skb_shinfo(skb)->frags[0];
6550         unsigned char *va;
6551         unsigned int pull_len;
6552
6553         /* it is valid to use page_address instead of kmap since we are
6554          * working with pages allocated out of the lomem pool per
6555          * alloc_page(GFP_ATOMIC)
6556          */
6557         va = skb_frag_address(frag);
6558
6559         if (igb_test_staterr(rx_desc, E1000_RXDADV_STAT_TSIP)) {
6560                 /* retrieve timestamp from buffer */
6561                 igb_ptp_rx_pktstamp(rx_ring->q_vector, va, skb);
6562
6563                 /* update pointers to remove timestamp header */
6564                 skb_frag_size_sub(frag, IGB_TS_HDR_LEN);
6565                 frag->page_offset += IGB_TS_HDR_LEN;
6566                 skb->data_len -= IGB_TS_HDR_LEN;
6567                 skb->len -= IGB_TS_HDR_LEN;
6568
6569                 /* move va to start of packet data */
6570                 va += IGB_TS_HDR_LEN;
6571         }
6572
6573         /* we need the header to contain the greater of either ETH_HLEN or
6574          * 60 bytes if the skb->len is less than 60 for skb_pad.
6575          */
6576         pull_len = igb_get_headlen(va, IGB_RX_HDR_LEN);
6577
6578         /* align pull length to size of long to optimize memcpy performance */
6579         skb_copy_to_linear_data(skb, va, ALIGN(pull_len, sizeof(long)));
6580
6581         /* update all of the pointers */
6582         skb_frag_size_sub(frag, pull_len);
6583         frag->page_offset += pull_len;
6584         skb->data_len -= pull_len;
6585         skb->tail += pull_len;
6586 }
6587
6588 /**
6589  *  igb_cleanup_headers - Correct corrupted or empty headers
6590  *  @rx_ring: rx descriptor ring packet is being transacted on
6591  *  @rx_desc: pointer to the EOP Rx descriptor
6592  *  @skb: pointer to current skb being fixed
6593  *
6594  *  Address the case where we are pulling data in on pages only
6595  *  and as such no data is present in the skb header.
6596  *
6597  *  In addition if skb is not at least 60 bytes we need to pad it so that
6598  *  it is large enough to qualify as a valid Ethernet frame.
6599  *
6600  *  Returns true if an error was encountered and skb was freed.
6601  **/
6602 static bool igb_cleanup_headers(struct igb_ring *rx_ring,
6603                                 union e1000_adv_rx_desc *rx_desc,
6604                                 struct sk_buff *skb)
6605 {
6606         if (unlikely((igb_test_staterr(rx_desc,
6607                                        E1000_RXDEXT_ERR_FRAME_ERR_MASK)))) {
6608                 struct net_device *netdev = rx_ring->netdev;
6609                 if (!(netdev->features & NETIF_F_RXALL)) {
6610                         dev_kfree_skb_any(skb);
6611                         return true;
6612                 }
6613         }
6614
6615         /* place header in linear portion of buffer */
6616         if (skb_is_nonlinear(skb))
6617                 igb_pull_tail(rx_ring, rx_desc, skb);
6618
6619         /* if skb_pad returns an error the skb was freed */
6620         if (unlikely(skb->len < 60)) {
6621                 int pad_len = 60 - skb->len;
6622
6623                 if (skb_pad(skb, pad_len))
6624                         return true;
6625                 __skb_put(skb, pad_len);
6626         }
6627
6628         return false;
6629 }
6630
6631 /**
6632  *  igb_process_skb_fields - Populate skb header fields from Rx descriptor
6633  *  @rx_ring: rx descriptor ring packet is being transacted on
6634  *  @rx_desc: pointer to the EOP Rx descriptor
6635  *  @skb: pointer to current skb being populated
6636  *
6637  *  This function checks the ring, descriptor, and packet information in
6638  *  order to populate the hash, checksum, VLAN, timestamp, protocol, and
6639  *  other fields within the skb.
6640  **/
6641 static void igb_process_skb_fields(struct igb_ring *rx_ring,
6642                                    union e1000_adv_rx_desc *rx_desc,
6643                                    struct sk_buff *skb)
6644 {
6645         struct net_device *dev = rx_ring->netdev;
6646
6647         igb_rx_hash(rx_ring, rx_desc, skb);
6648
6649         igb_rx_checksum(rx_ring, rx_desc, skb);
6650
6651         igb_ptp_rx_hwtstamp(rx_ring, rx_desc, skb);
6652
6653         if ((dev->features & NETIF_F_HW_VLAN_CTAG_RX) &&
6654             igb_test_staterr(rx_desc, E1000_RXD_STAT_VP)) {
6655                 u16 vid;
6656                 if (igb_test_staterr(rx_desc, E1000_RXDEXT_STATERR_LB) &&
6657                     test_bit(IGB_RING_FLAG_RX_LB_VLAN_BSWAP, &rx_ring->flags))
6658                         vid = be16_to_cpu(rx_desc->wb.upper.vlan);
6659                 else
6660                         vid = le16_to_cpu(rx_desc->wb.upper.vlan);
6661
6662                 __vlan_hwaccel_put_tag(skb, htons(ETH_P_8021Q), vid);
6663         }
6664
6665         skb_record_rx_queue(skb, rx_ring->queue_index);
6666
6667         skb->protocol = eth_type_trans(skb, rx_ring->netdev);
6668 }
6669
6670 static bool igb_clean_rx_irq(struct igb_q_vector *q_vector, const int budget)
6671 {
6672         struct igb_ring *rx_ring = q_vector->rx.ring;
6673         struct sk_buff *skb = rx_ring->skb;
6674         unsigned int total_bytes = 0, total_packets = 0;
6675         u16 cleaned_count = igb_desc_unused(rx_ring);
6676
6677         do {
6678                 union e1000_adv_rx_desc *rx_desc;
6679
6680                 /* return some buffers to hardware, one at a time is too slow */
6681                 if (cleaned_count >= IGB_RX_BUFFER_WRITE) {
6682                         igb_alloc_rx_buffers(rx_ring, cleaned_count);
6683                         cleaned_count = 0;
6684                 }
6685
6686                 rx_desc = IGB_RX_DESC(rx_ring, rx_ring->next_to_clean);
6687
6688                 if (!igb_test_staterr(rx_desc, E1000_RXD_STAT_DD))
6689                         break;
6690
6691                 /* This memory barrier is needed to keep us from reading
6692                  * any other fields out of the rx_desc until we know the
6693                  * RXD_STAT_DD bit is set
6694                  */
6695                 rmb();
6696
6697                 /* retrieve a buffer from the ring */
6698                 skb = igb_fetch_rx_buffer(rx_ring, rx_desc, skb);
6699
6700                 /* exit if we failed to retrieve a buffer */
6701                 if (!skb)
6702                         break;
6703
6704                 cleaned_count++;
6705
6706                 /* fetch next buffer in frame if non-eop */
6707                 if (igb_is_non_eop(rx_ring, rx_desc))
6708                         continue;
6709
6710                 /* verify the packet layout is correct */
6711                 if (igb_cleanup_headers(rx_ring, rx_desc, skb)) {
6712                         skb = NULL;
6713                         continue;
6714                 }
6715
6716                 /* probably a little skewed due to removing CRC */
6717                 total_bytes += skb->len;
6718
6719                 /* populate checksum, timestamp, VLAN, and protocol */
6720                 igb_process_skb_fields(rx_ring, rx_desc, skb);
6721
6722                 napi_gro_receive(&q_vector->napi, skb);
6723
6724                 /* reset skb pointer */
6725                 skb = NULL;
6726
6727                 /* update budget accounting */
6728                 total_packets++;
6729         } while (likely(total_packets < budget));
6730
6731         /* place incomplete frames back on ring for completion */
6732         rx_ring->skb = skb;
6733
6734         u64_stats_update_begin(&rx_ring->rx_syncp);
6735         rx_ring->rx_stats.packets += total_packets;
6736         rx_ring->rx_stats.bytes += total_bytes;
6737         u64_stats_update_end(&rx_ring->rx_syncp);
6738         q_vector->rx.total_packets += total_packets;
6739         q_vector->rx.total_bytes += total_bytes;
6740
6741         if (cleaned_count)
6742                 igb_alloc_rx_buffers(rx_ring, cleaned_count);
6743
6744         return (total_packets < budget);
6745 }
6746
6747 static bool igb_alloc_mapped_page(struct igb_ring *rx_ring,
6748                                   struct igb_rx_buffer *bi)
6749 {
6750         struct page *page = bi->page;
6751         dma_addr_t dma;
6752
6753         /* since we are recycling buffers we should seldom need to alloc */
6754         if (likely(page))
6755                 return true;
6756
6757         /* alloc new page for storage */
6758         page = __skb_alloc_page(GFP_ATOMIC | __GFP_COLD, NULL);
6759         if (unlikely(!page)) {
6760                 rx_ring->rx_stats.alloc_failed++;
6761                 return false;
6762         }
6763
6764         /* map page for use */
6765         dma = dma_map_page(rx_ring->dev, page, 0, PAGE_SIZE, DMA_FROM_DEVICE);
6766
6767         /* if mapping failed free memory back to system since
6768          * there isn't much point in holding memory we can't use
6769          */
6770         if (dma_mapping_error(rx_ring->dev, dma)) {
6771                 __free_page(page);
6772
6773                 rx_ring->rx_stats.alloc_failed++;
6774                 return false;
6775         }
6776
6777         bi->dma = dma;
6778         bi->page = page;
6779         bi->page_offset = 0;
6780
6781         return true;
6782 }
6783
6784 /**
6785  *  igb_alloc_rx_buffers - Replace used receive buffers; packet split
6786  *  @adapter: address of board private structure
6787  **/
6788 void igb_alloc_rx_buffers(struct igb_ring *rx_ring, u16 cleaned_count)
6789 {
6790         union e1000_adv_rx_desc *rx_desc;
6791         struct igb_rx_buffer *bi;
6792         u16 i = rx_ring->next_to_use;
6793
6794         /* nothing to do */
6795         if (!cleaned_count)
6796                 return;
6797
6798         rx_desc = IGB_RX_DESC(rx_ring, i);
6799         bi = &rx_ring->rx_buffer_info[i];
6800         i -= rx_ring->count;
6801
6802         do {
6803                 if (!igb_alloc_mapped_page(rx_ring, bi))
6804                         break;
6805
6806                 /* Refresh the desc even if buffer_addrs didn't change
6807                  * because each write-back erases this info.
6808                  */
6809                 rx_desc->read.pkt_addr = cpu_to_le64(bi->dma + bi->page_offset);
6810
6811                 rx_desc++;
6812                 bi++;
6813                 i++;
6814                 if (unlikely(!i)) {
6815                         rx_desc = IGB_RX_DESC(rx_ring, 0);
6816                         bi = rx_ring->rx_buffer_info;
6817                         i -= rx_ring->count;
6818                 }
6819
6820                 /* clear the hdr_addr for the next_to_use descriptor */
6821                 rx_desc->read.hdr_addr = 0;
6822
6823                 cleaned_count--;
6824         } while (cleaned_count);
6825
6826         i += rx_ring->count;
6827
6828         if (rx_ring->next_to_use != i) {
6829                 /* record the next descriptor to use */
6830                 rx_ring->next_to_use = i;
6831
6832                 /* update next to alloc since we have filled the ring */
6833                 rx_ring->next_to_alloc = i;
6834
6835                 /* Force memory writes to complete before letting h/w
6836                  * know there are new descriptors to fetch.  (Only
6837                  * applicable for weak-ordered memory model archs,
6838                  * such as IA-64).
6839                  */
6840                 wmb();
6841                 writel(i, rx_ring->tail);
6842         }
6843 }
6844
6845 /**
6846  * igb_mii_ioctl -
6847  * @netdev:
6848  * @ifreq:
6849  * @cmd:
6850  **/
6851 static int igb_mii_ioctl(struct net_device *netdev, struct ifreq *ifr, int cmd)
6852 {
6853         struct igb_adapter *adapter = netdev_priv(netdev);
6854         struct mii_ioctl_data *data = if_mii(ifr);
6855
6856         if (adapter->hw.phy.media_type != e1000_media_type_copper)
6857                 return -EOPNOTSUPP;
6858
6859         switch (cmd) {
6860         case SIOCGMIIPHY:
6861                 data->phy_id = adapter->hw.phy.addr;
6862                 break;
6863         case SIOCGMIIREG:
6864                 if (igb_read_phy_reg(&adapter->hw, data->reg_num & 0x1F,
6865                                      &data->val_out))
6866                         return -EIO;
6867                 break;
6868         case SIOCSMIIREG:
6869         default:
6870                 return -EOPNOTSUPP;
6871         }
6872         return 0;
6873 }
6874
6875 /**
6876  * igb_ioctl -
6877  * @netdev:
6878  * @ifreq:
6879  * @cmd:
6880  **/
6881 static int igb_ioctl(struct net_device *netdev, struct ifreq *ifr, int cmd)
6882 {
6883         switch (cmd) {
6884         case SIOCGMIIPHY:
6885         case SIOCGMIIREG:
6886         case SIOCSMIIREG:
6887                 return igb_mii_ioctl(netdev, ifr, cmd);
6888         case SIOCSHWTSTAMP:
6889                 return igb_ptp_hwtstamp_ioctl(netdev, ifr, cmd);
6890         default:
6891                 return -EOPNOTSUPP;
6892         }
6893 }
6894
6895 s32 igb_read_pcie_cap_reg(struct e1000_hw *hw, u32 reg, u16 *value)
6896 {
6897         struct igb_adapter *adapter = hw->back;
6898
6899         if (pcie_capability_read_word(adapter->pdev, reg, value))
6900                 return -E1000_ERR_CONFIG;
6901
6902         return 0;
6903 }
6904
6905 s32 igb_write_pcie_cap_reg(struct e1000_hw *hw, u32 reg, u16 *value)
6906 {
6907         struct igb_adapter *adapter = hw->back;
6908
6909         if (pcie_capability_write_word(adapter->pdev, reg, *value))
6910                 return -E1000_ERR_CONFIG;
6911
6912         return 0;
6913 }
6914
6915 static void igb_vlan_mode(struct net_device *netdev, netdev_features_t features)
6916 {
6917         struct igb_adapter *adapter = netdev_priv(netdev);
6918         struct e1000_hw *hw = &adapter->hw;
6919         u32 ctrl, rctl;
6920         bool enable = !!(features & NETIF_F_HW_VLAN_CTAG_RX);
6921
6922         if (enable) {
6923                 /* enable VLAN tag insert/strip */
6924                 ctrl = rd32(E1000_CTRL);
6925                 ctrl |= E1000_CTRL_VME;
6926                 wr32(E1000_CTRL, ctrl);
6927
6928                 /* Disable CFI check */
6929                 rctl = rd32(E1000_RCTL);
6930                 rctl &= ~E1000_RCTL_CFIEN;
6931                 wr32(E1000_RCTL, rctl);
6932         } else {
6933                 /* disable VLAN tag insert/strip */
6934                 ctrl = rd32(E1000_CTRL);
6935                 ctrl &= ~E1000_CTRL_VME;
6936                 wr32(E1000_CTRL, ctrl);
6937         }
6938
6939         igb_rlpml_set(adapter);
6940 }
6941
6942 static int igb_vlan_rx_add_vid(struct net_device *netdev,
6943                                __be16 proto, u16 vid)
6944 {
6945         struct igb_adapter *adapter = netdev_priv(netdev);
6946         struct e1000_hw *hw = &adapter->hw;
6947         int pf_id = adapter->vfs_allocated_count;
6948
6949         /* attempt to add filter to vlvf array */
6950         igb_vlvf_set(adapter, vid, true, pf_id);
6951
6952         /* add the filter since PF can receive vlans w/o entry in vlvf */
6953         igb_vfta_set(hw, vid, true);
6954
6955         set_bit(vid, adapter->active_vlans);
6956
6957         return 0;
6958 }
6959
6960 static int igb_vlan_rx_kill_vid(struct net_device *netdev,
6961                                 __be16 proto, u16 vid)
6962 {
6963         struct igb_adapter *adapter = netdev_priv(netdev);
6964         struct e1000_hw *hw = &adapter->hw;
6965         int pf_id = adapter->vfs_allocated_count;
6966         s32 err;
6967
6968         /* remove vlan from VLVF table array */
6969         err = igb_vlvf_set(adapter, vid, false, pf_id);
6970
6971         /* if vid was not present in VLVF just remove it from table */
6972         if (err)
6973                 igb_vfta_set(hw, vid, false);
6974
6975         clear_bit(vid, adapter->active_vlans);
6976
6977         return 0;
6978 }
6979
6980 static void igb_restore_vlan(struct igb_adapter *adapter)
6981 {
6982         u16 vid;
6983
6984         igb_vlan_mode(adapter->netdev, adapter->netdev->features);
6985
6986         for_each_set_bit(vid, adapter->active_vlans, VLAN_N_VID)
6987                 igb_vlan_rx_add_vid(adapter->netdev, htons(ETH_P_8021Q), vid);
6988 }
6989
6990 int igb_set_spd_dplx(struct igb_adapter *adapter, u32 spd, u8 dplx)
6991 {
6992         struct pci_dev *pdev = adapter->pdev;
6993         struct e1000_mac_info *mac = &adapter->hw.mac;
6994
6995         mac->autoneg = 0;
6996
6997         /* Make sure dplx is at most 1 bit and lsb of speed is not set
6998          * for the switch() below to work
6999          */
7000         if ((spd & 1) || (dplx & ~1))
7001                 goto err_inval;
7002
7003         /* Fiber NIC's only allow 1000 gbps Full duplex
7004          * and 100Mbps Full duplex for 100baseFx sfp
7005          */
7006         if (adapter->hw.phy.media_type == e1000_media_type_internal_serdes) {
7007                 switch (spd + dplx) {
7008                 case SPEED_10 + DUPLEX_HALF:
7009                 case SPEED_10 + DUPLEX_FULL:
7010                 case SPEED_100 + DUPLEX_HALF:
7011                         goto err_inval;
7012                 default:
7013                         break;
7014                 }
7015         }
7016
7017         switch (spd + dplx) {
7018         case SPEED_10 + DUPLEX_HALF:
7019                 mac->forced_speed_duplex = ADVERTISE_10_HALF;
7020                 break;
7021         case SPEED_10 + DUPLEX_FULL:
7022                 mac->forced_speed_duplex = ADVERTISE_10_FULL;
7023                 break;
7024         case SPEED_100 + DUPLEX_HALF:
7025                 mac->forced_speed_duplex = ADVERTISE_100_HALF;
7026                 break;
7027         case SPEED_100 + DUPLEX_FULL:
7028                 mac->forced_speed_duplex = ADVERTISE_100_FULL;
7029                 break;
7030         case SPEED_1000 + DUPLEX_FULL:
7031                 mac->autoneg = 1;
7032                 adapter->hw.phy.autoneg_advertised = ADVERTISE_1000_FULL;
7033                 break;
7034         case SPEED_1000 + DUPLEX_HALF: /* not supported */
7035         default:
7036                 goto err_inval;
7037         }
7038
7039         /* clear MDI, MDI(-X) override is only allowed when autoneg enabled */
7040         adapter->hw.phy.mdix = AUTO_ALL_MODES;
7041
7042         return 0;
7043
7044 err_inval:
7045         dev_err(&pdev->dev, "Unsupported Speed/Duplex configuration\n");
7046         return -EINVAL;
7047 }
7048
7049 static int __igb_shutdown(struct pci_dev *pdev, bool *enable_wake,
7050                           bool runtime)
7051 {
7052         struct net_device *netdev = pci_get_drvdata(pdev);
7053         struct igb_adapter *adapter = netdev_priv(netdev);
7054         struct e1000_hw *hw = &adapter->hw;
7055         u32 ctrl, rctl, status;
7056         u32 wufc = runtime ? E1000_WUFC_LNKC : adapter->wol;
7057 #ifdef CONFIG_PM
7058         int retval = 0;
7059 #endif
7060
7061         netif_device_detach(netdev);
7062
7063         if (netif_running(netdev))
7064                 __igb_close(netdev, true);
7065
7066         igb_clear_interrupt_scheme(adapter);
7067
7068 #ifdef CONFIG_PM
7069         retval = pci_save_state(pdev);
7070         if (retval)
7071                 return retval;
7072 #endif
7073
7074         status = rd32(E1000_STATUS);
7075         if (status & E1000_STATUS_LU)
7076                 wufc &= ~E1000_WUFC_LNKC;
7077
7078         if (wufc) {
7079                 igb_setup_rctl(adapter);
7080                 igb_set_rx_mode(netdev);
7081
7082                 /* turn on all-multi mode if wake on multicast is enabled */
7083                 if (wufc & E1000_WUFC_MC) {
7084                         rctl = rd32(E1000_RCTL);
7085                         rctl |= E1000_RCTL_MPE;
7086                         wr32(E1000_RCTL, rctl);
7087                 }
7088
7089                 ctrl = rd32(E1000_CTRL);
7090                 /* advertise wake from D3Cold */
7091                 #define E1000_CTRL_ADVD3WUC 0x00100000
7092                 /* phy power management enable */
7093                 #define E1000_CTRL_EN_PHY_PWR_MGMT 0x00200000
7094                 ctrl |= E1000_CTRL_ADVD3WUC;
7095                 wr32(E1000_CTRL, ctrl);
7096
7097                 /* Allow time for pending master requests to run */
7098                 igb_disable_pcie_master(hw);
7099
7100                 wr32(E1000_WUC, E1000_WUC_PME_EN);
7101                 wr32(E1000_WUFC, wufc);
7102         } else {
7103                 wr32(E1000_WUC, 0);
7104                 wr32(E1000_WUFC, 0);
7105         }
7106
7107         *enable_wake = wufc || adapter->en_mng_pt;
7108         if (!*enable_wake)
7109                 igb_power_down_link(adapter);
7110         else
7111                 igb_power_up_link(adapter);
7112
7113         /* Release control of h/w to f/w.  If f/w is AMT enabled, this
7114          * would have already happened in close and is redundant.
7115          */
7116         igb_release_hw_control(adapter);
7117
7118         pci_disable_device(pdev);
7119
7120         return 0;
7121 }
7122
7123 #ifdef CONFIG_PM
7124 #ifdef CONFIG_PM_SLEEP
7125 static int igb_suspend(struct device *dev)
7126 {
7127         int retval;
7128         bool wake;
7129         struct pci_dev *pdev = to_pci_dev(dev);
7130
7131         retval = __igb_shutdown(pdev, &wake, 0);
7132         if (retval)
7133                 return retval;
7134
7135         if (wake) {
7136                 pci_prepare_to_sleep(pdev);
7137         } else {
7138                 pci_wake_from_d3(pdev, false);
7139                 pci_set_power_state(pdev, PCI_D3hot);
7140         }
7141
7142         return 0;
7143 }
7144 #endif /* CONFIG_PM_SLEEP */
7145
7146 static int igb_resume(struct device *dev)
7147 {
7148         struct pci_dev *pdev = to_pci_dev(dev);
7149         struct net_device *netdev = pci_get_drvdata(pdev);
7150         struct igb_adapter *adapter = netdev_priv(netdev);
7151         struct e1000_hw *hw = &adapter->hw;
7152         u32 err;
7153
7154         pci_set_power_state(pdev, PCI_D0);
7155         pci_restore_state(pdev);
7156         pci_save_state(pdev);
7157
7158         err = pci_enable_device_mem(pdev);
7159         if (err) {
7160                 dev_err(&pdev->dev,
7161                         "igb: Cannot enable PCI device from suspend\n");
7162                 return err;
7163         }
7164         pci_set_master(pdev);
7165
7166         pci_enable_wake(pdev, PCI_D3hot, 0);
7167         pci_enable_wake(pdev, PCI_D3cold, 0);
7168
7169         if (igb_init_interrupt_scheme(adapter, true)) {
7170                 dev_err(&pdev->dev, "Unable to allocate memory for queues\n");
7171                 return -ENOMEM;
7172         }
7173
7174         igb_reset(adapter);
7175
7176         /* let the f/w know that the h/w is now under the control of the
7177          * driver.
7178          */
7179         igb_get_hw_control(adapter);
7180
7181         wr32(E1000_WUS, ~0);
7182
7183         if (netdev->flags & IFF_UP) {
7184                 rtnl_lock();
7185                 err = __igb_open(netdev, true);
7186                 rtnl_unlock();
7187                 if (err)
7188                         return err;
7189         }
7190
7191         netif_device_attach(netdev);
7192         return 0;
7193 }
7194
7195 #ifdef CONFIG_PM_RUNTIME
7196 static int igb_runtime_idle(struct device *dev)
7197 {
7198         struct pci_dev *pdev = to_pci_dev(dev);
7199         struct net_device *netdev = pci_get_drvdata(pdev);
7200         struct igb_adapter *adapter = netdev_priv(netdev);
7201
7202         if (!igb_has_link(adapter))
7203                 pm_schedule_suspend(dev, MSEC_PER_SEC * 5);
7204
7205         return -EBUSY;
7206 }
7207
7208 static int igb_runtime_suspend(struct device *dev)
7209 {
7210         struct pci_dev *pdev = to_pci_dev(dev);
7211         int retval;
7212         bool wake;
7213
7214         retval = __igb_shutdown(pdev, &wake, 1);
7215         if (retval)
7216                 return retval;
7217
7218         if (wake) {
7219                 pci_prepare_to_sleep(pdev);
7220         } else {
7221                 pci_wake_from_d3(pdev, false);
7222                 pci_set_power_state(pdev, PCI_D3hot);
7223         }
7224
7225         return 0;
7226 }
7227
7228 static int igb_runtime_resume(struct device *dev)
7229 {
7230         return igb_resume(dev);
7231 }
7232 #endif /* CONFIG_PM_RUNTIME */
7233 #endif
7234
7235 static void igb_shutdown(struct pci_dev *pdev)
7236 {
7237         bool wake;
7238
7239         __igb_shutdown(pdev, &wake, 0);
7240
7241         if (system_state == SYSTEM_POWER_OFF) {
7242                 pci_wake_from_d3(pdev, wake);
7243                 pci_set_power_state(pdev, PCI_D3hot);
7244         }
7245 }
7246
7247 #ifdef CONFIG_PCI_IOV
7248 static int igb_sriov_reinit(struct pci_dev *dev)
7249 {
7250         struct net_device *netdev = pci_get_drvdata(dev);
7251         struct igb_adapter *adapter = netdev_priv(netdev);
7252         struct pci_dev *pdev = adapter->pdev;
7253
7254         rtnl_lock();
7255
7256         if (netif_running(netdev))
7257                 igb_close(netdev);
7258
7259         igb_clear_interrupt_scheme(adapter);
7260
7261         igb_init_queue_configuration(adapter);
7262
7263         if (igb_init_interrupt_scheme(adapter, true)) {
7264                 dev_err(&pdev->dev, "Unable to allocate memory for queues\n");
7265                 return -ENOMEM;
7266         }
7267
7268         if (netif_running(netdev))
7269                 igb_open(netdev);
7270
7271         rtnl_unlock();
7272
7273         return 0;
7274 }
7275
7276 static int igb_pci_disable_sriov(struct pci_dev *dev)
7277 {
7278         int err = igb_disable_sriov(dev);
7279
7280         if (!err)
7281                 err = igb_sriov_reinit(dev);
7282
7283         return err;
7284 }
7285
7286 static int igb_pci_enable_sriov(struct pci_dev *dev, int num_vfs)
7287 {
7288         int err = igb_enable_sriov(dev, num_vfs);
7289
7290         if (err)
7291                 goto out;
7292
7293         err = igb_sriov_reinit(dev);
7294         if (!err)
7295                 return num_vfs;
7296
7297 out:
7298         return err;
7299 }
7300
7301 #endif
7302 static int igb_pci_sriov_configure(struct pci_dev *dev, int num_vfs)
7303 {
7304 #ifdef CONFIG_PCI_IOV
7305         if (num_vfs == 0)
7306                 return igb_pci_disable_sriov(dev);
7307         else
7308                 return igb_pci_enable_sriov(dev, num_vfs);
7309 #endif
7310         return 0;
7311 }
7312
7313 #ifdef CONFIG_NET_POLL_CONTROLLER
7314 /* Polling 'interrupt' - used by things like netconsole to send skbs
7315  * without having to re-enable interrupts. It's not called while
7316  * the interrupt routine is executing.
7317  */
7318 static void igb_netpoll(struct net_device *netdev)
7319 {
7320         struct igb_adapter *adapter = netdev_priv(netdev);
7321         struct e1000_hw *hw = &adapter->hw;
7322         struct igb_q_vector *q_vector;
7323         int i;
7324
7325         for (i = 0; i < adapter->num_q_vectors; i++) {
7326                 q_vector = adapter->q_vector[i];
7327                 if (adapter->msix_entries)
7328                         wr32(E1000_EIMC, q_vector->eims_value);
7329                 else
7330                         igb_irq_disable(adapter);
7331                 napi_schedule(&q_vector->napi);
7332         }
7333 }
7334 #endif /* CONFIG_NET_POLL_CONTROLLER */
7335
7336 /**
7337  *  igb_io_error_detected - called when PCI error is detected
7338  *  @pdev: Pointer to PCI device
7339  *  @state: The current pci connection state
7340  *
7341  *  This function is called after a PCI bus error affecting
7342  *  this device has been detected.
7343  **/
7344 static pci_ers_result_t igb_io_error_detected(struct pci_dev *pdev,
7345                                               pci_channel_state_t state)
7346 {
7347         struct net_device *netdev = pci_get_drvdata(pdev);
7348         struct igb_adapter *adapter = netdev_priv(netdev);
7349
7350         netif_device_detach(netdev);
7351
7352         if (state == pci_channel_io_perm_failure)
7353                 return PCI_ERS_RESULT_DISCONNECT;
7354
7355         if (netif_running(netdev))
7356                 igb_down(adapter);
7357         pci_disable_device(pdev);
7358
7359         /* Request a slot slot reset. */
7360         return PCI_ERS_RESULT_NEED_RESET;
7361 }
7362
7363 /**
7364  *  igb_io_slot_reset - called after the pci bus has been reset.
7365  *  @pdev: Pointer to PCI device
7366  *
7367  *  Restart the card from scratch, as if from a cold-boot. Implementation
7368  *  resembles the first-half of the igb_resume routine.
7369  **/
7370 static pci_ers_result_t igb_io_slot_reset(struct pci_dev *pdev)
7371 {
7372         struct net_device *netdev = pci_get_drvdata(pdev);
7373         struct igb_adapter *adapter = netdev_priv(netdev);
7374         struct e1000_hw *hw = &adapter->hw;
7375         pci_ers_result_t result;
7376         int err;
7377
7378         if (pci_enable_device_mem(pdev)) {
7379                 dev_err(&pdev->dev,
7380                         "Cannot re-enable PCI device after reset.\n");
7381                 result = PCI_ERS_RESULT_DISCONNECT;
7382         } else {
7383                 pci_set_master(pdev);
7384                 pci_restore_state(pdev);
7385                 pci_save_state(pdev);
7386
7387                 pci_enable_wake(pdev, PCI_D3hot, 0);
7388                 pci_enable_wake(pdev, PCI_D3cold, 0);
7389
7390                 igb_reset(adapter);
7391                 wr32(E1000_WUS, ~0);
7392                 result = PCI_ERS_RESULT_RECOVERED;
7393         }
7394
7395         err = pci_cleanup_aer_uncorrect_error_status(pdev);
7396         if (err) {
7397                 dev_err(&pdev->dev,
7398                         "pci_cleanup_aer_uncorrect_error_status failed 0x%0x\n",
7399                         err);
7400                 /* non-fatal, continue */
7401         }
7402
7403         return result;
7404 }
7405
7406 /**
7407  *  igb_io_resume - called when traffic can start flowing again.
7408  *  @pdev: Pointer to PCI device
7409  *
7410  *  This callback is called when the error recovery driver tells us that
7411  *  its OK to resume normal operation. Implementation resembles the
7412  *  second-half of the igb_resume routine.
7413  */
7414 static void igb_io_resume(struct pci_dev *pdev)
7415 {
7416         struct net_device *netdev = pci_get_drvdata(pdev);
7417         struct igb_adapter *adapter = netdev_priv(netdev);
7418
7419         if (netif_running(netdev)) {
7420                 if (igb_up(adapter)) {
7421                         dev_err(&pdev->dev, "igb_up failed after reset\n");
7422                         return;
7423                 }
7424         }
7425
7426         netif_device_attach(netdev);
7427
7428         /* let the f/w know that the h/w is now under the control of the
7429          * driver.
7430          */
7431         igb_get_hw_control(adapter);
7432 }
7433
7434 static void igb_rar_set_qsel(struct igb_adapter *adapter, u8 *addr, u32 index,
7435                              u8 qsel)
7436 {
7437         u32 rar_low, rar_high;
7438         struct e1000_hw *hw = &adapter->hw;
7439
7440         /* HW expects these in little endian so we reverse the byte order
7441          * from network order (big endian) to little endian
7442          */
7443         rar_low = ((u32) addr[0] | ((u32) addr[1] << 8) |
7444                    ((u32) addr[2] << 16) | ((u32) addr[3] << 24));
7445         rar_high = ((u32) addr[4] | ((u32) addr[5] << 8));
7446
7447         /* Indicate to hardware the Address is Valid. */
7448         rar_high |= E1000_RAH_AV;
7449
7450         if (hw->mac.type == e1000_82575)
7451                 rar_high |= E1000_RAH_POOL_1 * qsel;
7452         else
7453                 rar_high |= E1000_RAH_POOL_1 << qsel;
7454
7455         wr32(E1000_RAL(index), rar_low);
7456         wrfl();
7457         wr32(E1000_RAH(index), rar_high);
7458         wrfl();
7459 }
7460
7461 static int igb_set_vf_mac(struct igb_adapter *adapter,
7462                           int vf, unsigned char *mac_addr)
7463 {
7464         struct e1000_hw *hw = &adapter->hw;
7465         /* VF MAC addresses start at end of receive addresses and moves
7466          * towards the first, as a result a collision should not be possible
7467          */
7468         int rar_entry = hw->mac.rar_entry_count - (vf + 1);
7469
7470         memcpy(adapter->vf_data[vf].vf_mac_addresses, mac_addr, ETH_ALEN);
7471
7472         igb_rar_set_qsel(adapter, mac_addr, rar_entry, vf);
7473
7474         return 0;
7475 }
7476
7477 static int igb_ndo_set_vf_mac(struct net_device *netdev, int vf, u8 *mac)
7478 {
7479         struct igb_adapter *adapter = netdev_priv(netdev);
7480         if (!is_valid_ether_addr(mac) || (vf >= adapter->vfs_allocated_count))
7481                 return -EINVAL;
7482         adapter->vf_data[vf].flags |= IGB_VF_FLAG_PF_SET_MAC;
7483         dev_info(&adapter->pdev->dev, "setting MAC %pM on VF %d\n", mac, vf);
7484         dev_info(&adapter->pdev->dev,
7485                  "Reload the VF driver to make this change effective.");
7486         if (test_bit(__IGB_DOWN, &adapter->state)) {
7487                 dev_warn(&adapter->pdev->dev,
7488                          "The VF MAC address has been set, but the PF device is not up.\n");
7489                 dev_warn(&adapter->pdev->dev,
7490                          "Bring the PF device up before attempting to use the VF device.\n");
7491         }
7492         return igb_set_vf_mac(adapter, vf, mac);
7493 }
7494
7495 static int igb_link_mbps(int internal_link_speed)
7496 {
7497         switch (internal_link_speed) {
7498         case SPEED_100:
7499                 return 100;
7500         case SPEED_1000:
7501                 return 1000;
7502         default:
7503                 return 0;
7504         }
7505 }
7506
7507 static void igb_set_vf_rate_limit(struct e1000_hw *hw, int vf, int tx_rate,
7508                                   int link_speed)
7509 {
7510         int rf_dec, rf_int;
7511         u32 bcnrc_val;
7512
7513         if (tx_rate != 0) {
7514                 /* Calculate the rate factor values to set */
7515                 rf_int = link_speed / tx_rate;
7516                 rf_dec = (link_speed - (rf_int * tx_rate));
7517                 rf_dec = (rf_dec * (1 << E1000_RTTBCNRC_RF_INT_SHIFT)) /
7518                          tx_rate;
7519
7520                 bcnrc_val = E1000_RTTBCNRC_RS_ENA;
7521                 bcnrc_val |= ((rf_int << E1000_RTTBCNRC_RF_INT_SHIFT) &
7522                               E1000_RTTBCNRC_RF_INT_MASK);
7523                 bcnrc_val |= (rf_dec & E1000_RTTBCNRC_RF_DEC_MASK);
7524         } else {
7525                 bcnrc_val = 0;
7526         }
7527
7528         wr32(E1000_RTTDQSEL, vf); /* vf X uses queue X */
7529         /* Set global transmit compensation time to the MMW_SIZE in RTTBCNRM
7530          * register. MMW_SIZE=0x014 if 9728-byte jumbo is supported.
7531          */
7532         wr32(E1000_RTTBCNRM, 0x14);
7533         wr32(E1000_RTTBCNRC, bcnrc_val);
7534 }
7535
7536 static void igb_check_vf_rate_limit(struct igb_adapter *adapter)
7537 {
7538         int actual_link_speed, i;
7539         bool reset_rate = false;
7540
7541         /* VF TX rate limit was not set or not supported */
7542         if ((adapter->vf_rate_link_speed == 0) ||
7543             (adapter->hw.mac.type != e1000_82576))
7544                 return;
7545
7546         actual_link_speed = igb_link_mbps(adapter->link_speed);
7547         if (actual_link_speed != adapter->vf_rate_link_speed) {
7548                 reset_rate = true;
7549                 adapter->vf_rate_link_speed = 0;
7550                 dev_info(&adapter->pdev->dev,
7551                          "Link speed has been changed. VF Transmit rate is disabled\n");
7552         }
7553
7554         for (i = 0; i < adapter->vfs_allocated_count; i++) {
7555                 if (reset_rate)
7556                         adapter->vf_data[i].tx_rate = 0;
7557
7558                 igb_set_vf_rate_limit(&adapter->hw, i,
7559                                       adapter->vf_data[i].tx_rate,
7560                                       actual_link_speed);
7561         }
7562 }
7563
7564 static int igb_ndo_set_vf_bw(struct net_device *netdev, int vf, int tx_rate)
7565 {
7566         struct igb_adapter *adapter = netdev_priv(netdev);
7567         struct e1000_hw *hw = &adapter->hw;
7568         int actual_link_speed;
7569
7570         if (hw->mac.type != e1000_82576)
7571                 return -EOPNOTSUPP;
7572
7573         actual_link_speed = igb_link_mbps(adapter->link_speed);
7574         if ((vf >= adapter->vfs_allocated_count) ||
7575             (!(rd32(E1000_STATUS) & E1000_STATUS_LU)) ||
7576             (tx_rate < 0) || (tx_rate > actual_link_speed))
7577                 return -EINVAL;
7578
7579         adapter->vf_rate_link_speed = actual_link_speed;
7580         adapter->vf_data[vf].tx_rate = (u16)tx_rate;
7581         igb_set_vf_rate_limit(hw, vf, tx_rate, actual_link_speed);
7582
7583         return 0;
7584 }
7585
7586 static int igb_ndo_set_vf_spoofchk(struct net_device *netdev, int vf,
7587                                    bool setting)
7588 {
7589         struct igb_adapter *adapter = netdev_priv(netdev);
7590         struct e1000_hw *hw = &adapter->hw;
7591         u32 reg_val, reg_offset;
7592
7593         if (!adapter->vfs_allocated_count)
7594                 return -EOPNOTSUPP;
7595
7596         if (vf >= adapter->vfs_allocated_count)
7597                 return -EINVAL;
7598
7599         reg_offset = (hw->mac.type == e1000_82576) ? E1000_DTXSWC : E1000_TXSWC;
7600         reg_val = rd32(reg_offset);
7601         if (setting)
7602                 reg_val |= ((1 << vf) |
7603                             (1 << (vf + E1000_DTXSWC_VLAN_SPOOF_SHIFT)));
7604         else
7605                 reg_val &= ~((1 << vf) |
7606                              (1 << (vf + E1000_DTXSWC_VLAN_SPOOF_SHIFT)));
7607         wr32(reg_offset, reg_val);
7608
7609         adapter->vf_data[vf].spoofchk_enabled = setting;
7610         return E1000_SUCCESS;
7611 }
7612
7613 static int igb_ndo_get_vf_config(struct net_device *netdev,
7614                                  int vf, struct ifla_vf_info *ivi)
7615 {
7616         struct igb_adapter *adapter = netdev_priv(netdev);
7617         if (vf >= adapter->vfs_allocated_count)
7618                 return -EINVAL;
7619         ivi->vf = vf;
7620         memcpy(&ivi->mac, adapter->vf_data[vf].vf_mac_addresses, ETH_ALEN);
7621         ivi->tx_rate = adapter->vf_data[vf].tx_rate;
7622         ivi->vlan = adapter->vf_data[vf].pf_vlan;
7623         ivi->qos = adapter->vf_data[vf].pf_qos;
7624         ivi->spoofchk = adapter->vf_data[vf].spoofchk_enabled;
7625         return 0;
7626 }
7627
7628 static void igb_vmm_control(struct igb_adapter *adapter)
7629 {
7630         struct e1000_hw *hw = &adapter->hw;
7631         u32 reg;
7632
7633         switch (hw->mac.type) {
7634         case e1000_82575:
7635         case e1000_i210:
7636         case e1000_i211:
7637         case e1000_i354:
7638         default:
7639                 /* replication is not supported for 82575 */
7640                 return;
7641         case e1000_82576:
7642                 /* notify HW that the MAC is adding vlan tags */
7643                 reg = rd32(E1000_DTXCTL);
7644                 reg |= E1000_DTXCTL_VLAN_ADDED;
7645                 wr32(E1000_DTXCTL, reg);
7646         case e1000_82580:
7647                 /* enable replication vlan tag stripping */
7648                 reg = rd32(E1000_RPLOLR);
7649                 reg |= E1000_RPLOLR_STRVLAN;
7650                 wr32(E1000_RPLOLR, reg);
7651         case e1000_i350:
7652                 /* none of the above registers are supported by i350 */
7653                 break;
7654         }
7655
7656         if (adapter->vfs_allocated_count) {
7657                 igb_vmdq_set_loopback_pf(hw, true);
7658                 igb_vmdq_set_replication_pf(hw, true);
7659                 igb_vmdq_set_anti_spoofing_pf(hw, true,
7660                                               adapter->vfs_allocated_count);
7661         } else {
7662                 igb_vmdq_set_loopback_pf(hw, false);
7663                 igb_vmdq_set_replication_pf(hw, false);
7664         }
7665 }
7666
7667 static void igb_init_dmac(struct igb_adapter *adapter, u32 pba)
7668 {
7669         struct e1000_hw *hw = &adapter->hw;
7670         u32 dmac_thr;
7671         u16 hwm;
7672
7673         if (hw->mac.type > e1000_82580) {
7674                 if (adapter->flags & IGB_FLAG_DMAC) {
7675                         u32 reg;
7676
7677                         /* force threshold to 0. */
7678                         wr32(E1000_DMCTXTH, 0);
7679
7680                         /* DMA Coalescing high water mark needs to be greater
7681                          * than the Rx threshold. Set hwm to PBA - max frame
7682                          * size in 16B units, capping it at PBA - 6KB.
7683                          */
7684                         hwm = 64 * pba - adapter->max_frame_size / 16;
7685                         if (hwm < 64 * (pba - 6))
7686                                 hwm = 64 * (pba - 6);
7687                         reg = rd32(E1000_FCRTC);
7688                         reg &= ~E1000_FCRTC_RTH_COAL_MASK;
7689                         reg |= ((hwm << E1000_FCRTC_RTH_COAL_SHIFT)
7690                                 & E1000_FCRTC_RTH_COAL_MASK);
7691                         wr32(E1000_FCRTC, reg);
7692
7693                         /* Set the DMA Coalescing Rx threshold to PBA - 2 * max
7694                          * frame size, capping it at PBA - 10KB.
7695                          */
7696                         dmac_thr = pba - adapter->max_frame_size / 512;
7697                         if (dmac_thr < pba - 10)
7698                                 dmac_thr = pba - 10;
7699                         reg = rd32(E1000_DMACR);
7700                         reg &= ~E1000_DMACR_DMACTHR_MASK;
7701                         reg |= ((dmac_thr << E1000_DMACR_DMACTHR_SHIFT)
7702                                 & E1000_DMACR_DMACTHR_MASK);
7703
7704                         /* transition to L0x or L1 if available..*/
7705                         reg |= (E1000_DMACR_DMAC_EN | E1000_DMACR_DMAC_LX_MASK);
7706
7707                         /* watchdog timer= +-1000 usec in 32usec intervals */
7708                         reg |= (1000 >> 5);
7709
7710                         /* Disable BMC-to-OS Watchdog Enable */
7711                         if (hw->mac.type != e1000_i354)
7712                                 reg &= ~E1000_DMACR_DC_BMC2OSW_EN;
7713
7714                         wr32(E1000_DMACR, reg);
7715
7716                         /* no lower threshold to disable
7717                          * coalescing(smart fifb)-UTRESH=0
7718                          */
7719                         wr32(E1000_DMCRTRH, 0);
7720
7721                         reg = (IGB_DMCTLX_DCFLUSH_DIS | 0x4);
7722
7723                         wr32(E1000_DMCTLX, reg);
7724
7725                         /* free space in tx packet buffer to wake from
7726                          * DMA coal
7727                          */
7728                         wr32(E1000_DMCTXTH, (IGB_MIN_TXPBSIZE -
7729                              (IGB_TX_BUF_4096 + adapter->max_frame_size)) >> 6);
7730
7731                         /* make low power state decision controlled
7732                          * by DMA coal
7733                          */
7734                         reg = rd32(E1000_PCIEMISC);
7735                         reg &= ~E1000_PCIEMISC_LX_DECISION;
7736                         wr32(E1000_PCIEMISC, reg);
7737                 } /* endif adapter->dmac is not disabled */
7738         } else if (hw->mac.type == e1000_82580) {
7739                 u32 reg = rd32(E1000_PCIEMISC);
7740                 wr32(E1000_PCIEMISC, reg & ~E1000_PCIEMISC_LX_DECISION);
7741                 wr32(E1000_DMACR, 0);
7742         }
7743 }
7744
7745 /**
7746  *  igb_read_i2c_byte - Reads 8 bit word over I2C
7747  *  @hw: pointer to hardware structure
7748  *  @byte_offset: byte offset to read
7749  *  @dev_addr: device address
7750  *  @data: value read
7751  *
7752  *  Performs byte read operation over I2C interface at
7753  *  a specified device address.
7754  **/
7755 s32 igb_read_i2c_byte(struct e1000_hw *hw, u8 byte_offset,
7756                       u8 dev_addr, u8 *data)
7757 {
7758         struct igb_adapter *adapter = container_of(hw, struct igb_adapter, hw);
7759         struct i2c_client *this_client = adapter->i2c_client;
7760         s32 status;
7761         u16 swfw_mask = 0;
7762
7763         if (!this_client)
7764                 return E1000_ERR_I2C;
7765
7766         swfw_mask = E1000_SWFW_PHY0_SM;
7767
7768         if (hw->mac.ops.acquire_swfw_sync(hw, swfw_mask)
7769             != E1000_SUCCESS)
7770                 return E1000_ERR_SWFW_SYNC;
7771
7772         status = i2c_smbus_read_byte_data(this_client, byte_offset);
7773         hw->mac.ops.release_swfw_sync(hw, swfw_mask);
7774
7775         if (status < 0)
7776                 return E1000_ERR_I2C;
7777         else {
7778                 *data = status;
7779                 return E1000_SUCCESS;
7780         }
7781 }
7782
7783 /**
7784  *  igb_write_i2c_byte - Writes 8 bit word over I2C
7785  *  @hw: pointer to hardware structure
7786  *  @byte_offset: byte offset to write
7787  *  @dev_addr: device address
7788  *  @data: value to write
7789  *
7790  *  Performs byte write operation over I2C interface at
7791  *  a specified device address.
7792  **/
7793 s32 igb_write_i2c_byte(struct e1000_hw *hw, u8 byte_offset,
7794                        u8 dev_addr, u8 data)
7795 {
7796         struct igb_adapter *adapter = container_of(hw, struct igb_adapter, hw);
7797         struct i2c_client *this_client = adapter->i2c_client;
7798         s32 status;
7799         u16 swfw_mask = E1000_SWFW_PHY0_SM;
7800
7801         if (!this_client)
7802                 return E1000_ERR_I2C;
7803
7804         if (hw->mac.ops.acquire_swfw_sync(hw, swfw_mask) != E1000_SUCCESS)
7805                 return E1000_ERR_SWFW_SYNC;
7806         status = i2c_smbus_write_byte_data(this_client, byte_offset, data);
7807         hw->mac.ops.release_swfw_sync(hw, swfw_mask);
7808
7809         if (status)
7810                 return E1000_ERR_I2C;
7811         else
7812                 return E1000_SUCCESS;
7813
7814 }
7815 /* igb_main.c */