drivers/net/ethernet/intel/ixgbe/ixgbe_main.c

   1 /*******************************************************************************
   2
   3   Intel 10 Gigabit PCI Express Linux driver
   4   Copyright(c) 1999 - 2011 Intel Corporation.
   5
   6   This program is free software; you can redistribute it and/or modify it
   7   under the terms and conditions of the GNU General Public License,
   8   version 2, as published by the Free Software Foundation.
   9
  10   This program is distributed in the hope it will be useful, but WITHOUT
  11   ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  12   FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
  13   more details.
  14
  15   You should have received a copy of the GNU General Public License along with
  16   this program; if not, write to the Free Software Foundation, Inc.,
  17   51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
  18
  19   The full GNU General Public License is included in this distribution in
  20   the file called "COPYING".
  21
  22   Contact Information:
  23   e1000-devel Mailing List <e1000-devel@lists.sourceforge.net>
  24   Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
  25
  26 *******************************************************************************/
  27
  28 #include <linux/types.h>
  29 #include <linux/module.h>
  30 #include <linux/pci.h>
  31 #include <linux/netdevice.h>
  32 #include <linux/vmalloc.h>
  33 #include <linux/string.h>
  34 #include <linux/in.h>
  35 #include <linux/interrupt.h>
  36 #include <linux/ip.h>
  37 #include <linux/tcp.h>
  38 #include <linux/sctp.h>
  39 #include <linux/pkt_sched.h>
  40 #include <linux/ipv6.h>
  41 #include <linux/slab.h>
  42 #include <net/checksum.h>
  43 #include <net/ip6_checksum.h>
  44 #include <linux/ethtool.h>
  45 #include <linux/if.h>
  46 #include <linux/if_vlan.h>
  47 #include <linux/prefetch.h>
  48 #include <scsi/fc/fc_fcoe.h>
  49
  50 #include "ixgbe.h"
  51 #include "ixgbe_common.h"
  52 #include "ixgbe_dcb_82599.h"
  53 #include "ixgbe_sriov.h"
  54
  55 char ixgbe_driver_name[] = "ixgbe";
  56 static const char ixgbe_driver_string[] =
  57                               "Intel(R) 10 Gigabit PCI Express Network Driver";
  58 #define MAJ 3
  59 #define MIN 4
  60 #define BUILD 8
  61 #define DRV_VERSION __stringify(MAJ) "." __stringify(MIN) "." \
  62         __stringify(BUILD) "-k"
  63 const char ixgbe_driver_version[] = DRV_VERSION;
  64 static const char ixgbe_copyright[] =
  65                                 "Copyright (c) 1999-2011 Intel Corporation.";
  66
  67 static const struct ixgbe_info *ixgbe_info_tbl[] = {
  68         [board_82598] = &ixgbe_82598_info,
  69         [board_82599] = &ixgbe_82599_info,
  70         [board_X540] = &ixgbe_X540_info,
  71 };
  72
  73 /* ixgbe_pci_tbl - PCI Device ID Table
  74  *
  75  * Wildcard entries (PCI_ANY_ID) should come last
  76  * Last entry must be all 0s
  77  *
  78  * { Vendor ID, Device ID, SubVendor ID, SubDevice ID,
  79  *   Class, Class Mask, private data (not used) }
  80  */
  81 static DEFINE_PCI_DEVICE_TABLE(ixgbe_pci_tbl) = {
  82         {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598), board_82598 },
  83         {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598AF_DUAL_PORT), board_82598 },
  84         {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598AF_SINGLE_PORT), board_82598 },
  85         {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598AT), board_82598 },
  86         {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598AT2), board_82598 },
  87         {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598EB_CX4), board_82598 },
  88         {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598_CX4_DUAL_PORT), board_82598 },
  89         {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598_DA_DUAL_PORT), board_82598 },
  90         {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598_SR_DUAL_PORT_EM), board_82598 },
  91         {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598EB_XF_LR), board_82598 },
  92         {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598EB_SFP_LOM), board_82598 },
  93         {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598_BX), board_82598 },
  94         {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_KX4), board_82599 },
  95         {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_XAUI_LOM), board_82599 },
  96         {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_KR), board_82599 },
  97         {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_SFP), board_82599 },
  98         {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_SFP_EM), board_82599 },
  99         {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_KX4_MEZZ), board_82599 },
 100         {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_CX4), board_82599 },
 101         {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_BACKPLANE_FCOE), board_82599 },
 102         {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_SFP_FCOE), board_82599 },
 103         {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_T3_LOM), board_82599 },
 104         {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_COMBO_BACKPLANE), board_82599 },
 105         {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_X540T), board_X540 },
 106         {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_SFP_SF2), board_82599 },
 107         {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_LS), board_82599 },
 108         /* required last entry */
 109         {0, }
 110 };
 111 MODULE_DEVICE_TABLE(pci, ixgbe_pci_tbl);
 112
 113 #ifdef CONFIG_IXGBE_DCA
 114 static int ixgbe_notify_dca(struct notifier_block *, unsigned long event,
 115                             void *p);
 116 static struct notifier_block dca_notifier = {
 117         .notifier_call = ixgbe_notify_dca,
 118         .next          = NULL,
 119         .priority      = 0
 120 };
 121 #endif
 122
 123 #ifdef CONFIG_PCI_IOV
 124 static unsigned int max_vfs;
 125 module_param(max_vfs, uint, 0);
 126 MODULE_PARM_DESC(max_vfs,
 127                  "Maximum number of virtual functions to allocate per physical function");
 128 #endif /* CONFIG_PCI_IOV */
 129
 130 MODULE_AUTHOR("Intel Corporation, <linux.nics@intel.com>");
 131 MODULE_DESCRIPTION("Intel(R) 10 Gigabit PCI Express Network Driver");
 132 MODULE_LICENSE("GPL");
 133 MODULE_VERSION(DRV_VERSION);
 134
 135 #define DEFAULT_DEBUG_LEVEL_SHIFT 3
 136
 137 static inline void ixgbe_disable_sriov(struct ixgbe_adapter *adapter)
 138 {
 139         struct ixgbe_hw *hw = &adapter->hw;
 140         u32 gcr;
 141         u32 gpie;
 142         u32 vmdctl;
 143
 144 #ifdef CONFIG_PCI_IOV
 145         /* disable iov and allow time for transactions to clear */
 146         pci_disable_sriov(adapter->pdev);
 147 #endif
 148
 149         /* turn off device IOV mode */
 150         gcr = IXGBE_READ_REG(hw, IXGBE_GCR_EXT);
 151         gcr &= ~(IXGBE_GCR_EXT_SRIOV);
 152         IXGBE_WRITE_REG(hw, IXGBE_GCR_EXT, gcr);
 153         gpie = IXGBE_READ_REG(hw, IXGBE_GPIE);
 154         gpie &= ~IXGBE_GPIE_VTMODE_MASK;
 155         IXGBE_WRITE_REG(hw, IXGBE_GPIE, gpie);
 156
 157         /* set default pool back to 0 */
 158         vmdctl = IXGBE_READ_REG(hw, IXGBE_VT_CTL);
 159         vmdctl &= ~IXGBE_VT_CTL_POOL_MASK;
 160         IXGBE_WRITE_REG(hw, IXGBE_VT_CTL, vmdctl);
 161         IXGBE_WRITE_FLUSH(hw);
 162
 163         /* take a breather then clean up driver data */
 164         msleep(100);
 165
 166         kfree(adapter->vfinfo);
 167         adapter->vfinfo = NULL;
 168
 169         adapter->num_vfs = 0;
 170         adapter->flags &= ~IXGBE_FLAG_SRIOV_ENABLED;
 171 }
 172
 173 static void ixgbe_service_event_schedule(struct ixgbe_adapter *adapter)
 174 {
 175         if (!test_bit(__IXGBE_DOWN, &adapter->state) &&
 176             !test_and_set_bit(__IXGBE_SERVICE_SCHED, &adapter->state))
 177                 schedule_work(&adapter->service_task);
 178 }
 179
 180 static void ixgbe_service_event_complete(struct ixgbe_adapter *adapter)
 181 {
 182         BUG_ON(!test_bit(__IXGBE_SERVICE_SCHED, &adapter->state));
 183
 184         /* flush memory to make sure state is correct before next watchog */
 185         smp_mb__before_clear_bit();
 186         clear_bit(__IXGBE_SERVICE_SCHED, &adapter->state);
 187 }
 188
 189 struct ixgbe_reg_info {
 190         u32 ofs;
 191         char *name;
 192 };
 193
 194 static const struct ixgbe_reg_info ixgbe_reg_info_tbl[] = {
 195
 196         /* General Registers */
 197         {IXGBE_CTRL, "CTRL"},
 198         {IXGBE_STATUS, "STATUS"},
 199         {IXGBE_CTRL_EXT, "CTRL_EXT"},
 200
 201         /* Interrupt Registers */
 202         {IXGBE_EICR, "EICR"},
 203
 204         /* RX Registers */
 205         {IXGBE_SRRCTL(0), "SRRCTL"},
 206         {IXGBE_DCA_RXCTRL(0), "DRXCTL"},
 207         {IXGBE_RDLEN(0), "RDLEN"},
 208         {IXGBE_RDH(0), "RDH"},
 209         {IXGBE_RDT(0), "RDT"},
 210         {IXGBE_RXDCTL(0), "RXDCTL"},
 211         {IXGBE_RDBAL(0), "RDBAL"},
 212         {IXGBE_RDBAH(0), "RDBAH"},
 213
 214         /* TX Registers */
 215         {IXGBE_TDBAL(0), "TDBAL"},
 216         {IXGBE_TDBAH(0), "TDBAH"},
 217         {IXGBE_TDLEN(0), "TDLEN"},
 218         {IXGBE_TDH(0), "TDH"},
 219         {IXGBE_TDT(0), "TDT"},
 220         {IXGBE_TXDCTL(0), "TXDCTL"},
 221
 222         /* List Terminator */
 223         {}
 224 };
 225
 226
 227 /*
 228  * ixgbe_regdump - register printout routine
 229  */
 230 static void ixgbe_regdump(struct ixgbe_hw *hw, struct ixgbe_reg_info *reginfo)
 231 {
 232         int i = 0, j = 0;
 233         char rname[16];
 234         u32 regs[64];
 235
 236         switch (reginfo->ofs) {
 237         case IXGBE_SRRCTL(0):
 238                 for (i = 0; i < 64; i++)
 239                         regs[i] = IXGBE_READ_REG(hw, IXGBE_SRRCTL(i));
 240                 break;
 241         case IXGBE_DCA_RXCTRL(0):
 242                 for (i = 0; i < 64; i++)
 243                         regs[i] = IXGBE_READ_REG(hw, IXGBE_DCA_RXCTRL(i));
 244                 break;
 245         case IXGBE_RDLEN(0):
 246                 for (i = 0; i < 64; i++)
 247                         regs[i] = IXGBE_READ_REG(hw, IXGBE_RDLEN(i));
 248                 break;
 249         case IXGBE_RDH(0):
 250                 for (i = 0; i < 64; i++)
 251                         regs[i] = IXGBE_READ_REG(hw, IXGBE_RDH(i));
 252                 break;
 253         case IXGBE_RDT(0):
 254                 for (i = 0; i < 64; i++)
 255                         regs[i] = IXGBE_READ_REG(hw, IXGBE_RDT(i));
 256                 break;
 257         case IXGBE_RXDCTL(0):
 258                 for (i = 0; i < 64; i++)
 259                         regs[i] = IXGBE_READ_REG(hw, IXGBE_RXDCTL(i));
 260                 break;
 261         case IXGBE_RDBAL(0):
 262                 for (i = 0; i < 64; i++)
 263                         regs[i] = IXGBE_READ_REG(hw, IXGBE_RDBAL(i));
 264                 break;
 265         case IXGBE_RDBAH(0):
 266                 for (i = 0; i < 64; i++)
 267                         regs[i] = IXGBE_READ_REG(hw, IXGBE_RDBAH(i));
 268                 break;
 269         case IXGBE_TDBAL(0):
 270                 for (i = 0; i < 64; i++)
 271                         regs[i] = IXGBE_READ_REG(hw, IXGBE_TDBAL(i));
 272                 break;
 273         case IXGBE_TDBAH(0):
 274                 for (i = 0; i < 64; i++)
 275                         regs[i] = IXGBE_READ_REG(hw, IXGBE_TDBAH(i));
 276                 break;
 277         case IXGBE_TDLEN(0):
 278                 for (i = 0; i < 64; i++)
 279                         regs[i] = IXGBE_READ_REG(hw, IXGBE_TDLEN(i));
 280                 break;
 281         case IXGBE_TDH(0):
 282                 for (i = 0; i < 64; i++)
 283                         regs[i] = IXGBE_READ_REG(hw, IXGBE_TDH(i));
 284                 break;
 285         case IXGBE_TDT(0):
 286                 for (i = 0; i < 64; i++)
 287                         regs[i] = IXGBE_READ_REG(hw, IXGBE_TDT(i));
 288                 break;
 289         case IXGBE_TXDCTL(0):
 290                 for (i = 0; i < 64; i++)
 291                         regs[i] = IXGBE_READ_REG(hw, IXGBE_TXDCTL(i));
 292                 break;
 293         default:
 294                 pr_info("%-15s %08x\n", reginfo->name,
 295                         IXGBE_READ_REG(hw, reginfo->ofs));
 296                 return;
 297         }
 298
 299         for (i = 0; i < 8; i++) {
 300                 snprintf(rname, 16, "%s[%d-%d]", reginfo->name, i*8, i*8+7);
 301                 pr_err("%-15s", rname);
 302                 for (j = 0; j < 8; j++)
 303                         pr_cont(" %08x", regs[i*8+j]);
 304                 pr_cont("\n");
 305         }
 306
 307 }
 308
 309 /*
 310  * ixgbe_dump - Print registers, tx-rings and rx-rings
 311  */
 312 static void ixgbe_dump(struct ixgbe_adapter *adapter)
 313 {
 314         struct net_device *netdev = adapter->netdev;
 315         struct ixgbe_hw *hw = &adapter->hw;
 316         struct ixgbe_reg_info *reginfo;
 317         int n = 0;
 318         struct ixgbe_ring *tx_ring;
 319         struct ixgbe_tx_buffer *tx_buffer_info;
 320         union ixgbe_adv_tx_desc *tx_desc;
 321         struct my_u0 { u64 a; u64 b; } *u0;
 322         struct ixgbe_ring *rx_ring;
 323         union ixgbe_adv_rx_desc *rx_desc;
 324         struct ixgbe_rx_buffer *rx_buffer_info;
 325         u32 staterr;
 326         int i = 0;
 327
 328         if (!netif_msg_hw(adapter))
 329                 return;
 330
 331         /* Print netdevice Info */
 332         if (netdev) {
 333                 dev_info(&adapter->pdev->dev, "Net device Info\n");
 334                 pr_info("Device Name     state            "
 335                         "trans_start      last_rx\n");
 336                 pr_info("%-15s %016lX %016lX %016lX\n",
 337                         netdev->name,
 338                         netdev->state,
 339                         netdev->trans_start,
 340                         netdev->last_rx);
 341         }
 342
 343         /* Print Registers */
 344         dev_info(&adapter->pdev->dev, "Register Dump\n");
 345         pr_info(" Register Name   Value\n");
 346         for (reginfo = (struct ixgbe_reg_info *)ixgbe_reg_info_tbl;
 347              reginfo->name; reginfo++) {
 348                 ixgbe_regdump(hw, reginfo);
 349         }
 350
 351         /* Print TX Ring Summary */
 352         if (!netdev || !netif_running(netdev))
 353                 goto exit;
 354
 355         dev_info(&adapter->pdev->dev, "TX Rings Summary\n");
 356         pr_info("Queue [NTU] [NTC] [bi(ntc)->dma  ] leng ntw timestamp\n");
 357         for (n = 0; n < adapter->num_tx_queues; n++) {
 358                 tx_ring = adapter->tx_ring[n];
 359                 tx_buffer_info =
 360                         &tx_ring->tx_buffer_info[tx_ring->next_to_clean];
 361                 pr_info(" %5d %5X %5X %016llX %04X %p %016llX\n",
 362                            n, tx_ring->next_to_use, tx_ring->next_to_clean,
 363                            (u64)tx_buffer_info->dma,
 364                            tx_buffer_info->length,
 365                            tx_buffer_info->next_to_watch,
 366                            (u64)tx_buffer_info->time_stamp);
 367         }
 368
 369         /* Print TX Rings */
 370         if (!netif_msg_tx_done(adapter))
 371                 goto rx_ring_summary;
 372
 373         dev_info(&adapter->pdev->dev, "TX Rings Dump\n");
 374
 375         /* Transmit Descriptor Formats
 376          *
 377          * Advanced Transmit Descriptor
 378          *   +--------------------------------------------------------------+
 379          * 0 |         Buffer Address [63:0]                                |
 380          *   +--------------------------------------------------------------+
 381          * 8 |  PAYLEN  | PORTS  | IDX | STA | DCMD  |DTYP |  RSV |  DTALEN |
 382          *   +--------------------------------------------------------------+
 383          *   63       46 45    40 39 36 35 32 31   24 23 20 19              0
 384          */
 385
 386         for (n = 0; n < adapter->num_tx_queues; n++) {
 387                 tx_ring = adapter->tx_ring[n];
 388                 pr_info("------------------------------------\n");
 389                 pr_info("TX QUEUE INDEX = %d\n", tx_ring->queue_index);
 390                 pr_info("------------------------------------\n");
 391                 pr_info("T [desc]     [address 63:0  ] "
 392                         "[PlPOIdStDDt Ln] [bi->dma       ] "
 393                         "leng  ntw timestamp        bi->skb\n");
 394
 395                 for (i = 0; tx_ring->desc && (i < tx_ring->count); i++) {
 396                         tx_desc = IXGBE_TX_DESC_ADV(tx_ring, i);
 397                         tx_buffer_info = &tx_ring->tx_buffer_info[i];
 398                         u0 = (struct my_u0 *)tx_desc;
 399                         pr_info("T [0x%03X]    %016llX %016llX %016llX"
 400                                 " %04X  %p %016llX %p", i,
 401                                 le64_to_cpu(u0->a),
 402                                 le64_to_cpu(u0->b),
 403                                 (u64)tx_buffer_info->dma,
 404                                 tx_buffer_info->length,
 405                                 tx_buffer_info->next_to_watch,
 406                                 (u64)tx_buffer_info->time_stamp,
 407                                 tx_buffer_info->skb);
 408                         if (i == tx_ring->next_to_use &&
 409                                 i == tx_ring->next_to_clean)
 410                                 pr_cont(" NTC/U\n");
 411                         else if (i == tx_ring->next_to_use)
 412                                 pr_cont(" NTU\n");
 413                         else if (i == tx_ring->next_to_clean)
 414                                 pr_cont(" NTC\n");
 415                         else
 416                                 pr_cont("\n");
 417
 418                         if (netif_msg_pktdata(adapter) &&
 419                                 tx_buffer_info->dma != 0)
 420                                 print_hex_dump(KERN_INFO, "",
 421                                         DUMP_PREFIX_ADDRESS, 16, 1,
 422                                         phys_to_virt(tx_buffer_info->dma),
 423                                         tx_buffer_info->length, true);
 424                 }
 425         }
 426
 427         /* Print RX Rings Summary */
 428 rx_ring_summary:
 429         dev_info(&adapter->pdev->dev, "RX Rings Summary\n");
 430         pr_info("Queue [NTU] [NTC]\n");
 431         for (n = 0; n < adapter->num_rx_queues; n++) {
 432                 rx_ring = adapter->rx_ring[n];
 433                 pr_info("%5d %5X %5X\n",
 434                         n, rx_ring->next_to_use, rx_ring->next_to_clean);
 435         }
 436
 437         /* Print RX Rings */
 438         if (!netif_msg_rx_status(adapter))
 439                 goto exit;
 440
 441         dev_info(&adapter->pdev->dev, "RX Rings Dump\n");
 442
 443         /* Advanced Receive Descriptor (Read) Format
 444          *    63                                           1        0
 445          *    +-----------------------------------------------------+
 446          *  0 |       Packet Buffer Address [63:1]           |A0/NSE|
 447          *    +----------------------------------------------+------+
 448          *  8 |       Header Buffer Address [63:1]           |  DD  |
 449          *    +-----------------------------------------------------+
 450          *
 451          *
 452          * Advanced Receive Descriptor (Write-Back) Format
 453          *
 454          *   63       48 47    32 31  30      21 20 16 15   4 3     0
 455          *   +------------------------------------------------------+
 456          * 0 | Packet     IP     |SPH| HDR_LEN   | RSV|Packet|  RSS |
 457          *   | Checksum   Ident  |   |           |    | Type | Type |
 458          *   +------------------------------------------------------+
 459          * 8 | VLAN Tag | Length | Extended Error | Extended Status |
 460          *   +------------------------------------------------------+
 461          *   63       48 47    32 31            20 19               0
 462          */
 463         for (n = 0; n < adapter->num_rx_queues; n++) {
 464                 rx_ring = adapter->rx_ring[n];
 465                 pr_info("------------------------------------\n");
 466                 pr_info("RX QUEUE INDEX = %d\n", rx_ring->queue_index);
 467                 pr_info("------------------------------------\n");
 468                 pr_info("R  [desc]      [ PktBuf     A0] "
 469                         "[  HeadBuf   DD] [bi->dma       ] [bi->skb] "
 470                         "<-- Adv Rx Read format\n");
 471                 pr_info("RWB[desc]      [PcsmIpSHl PtRs] "
 472                         "[vl er S cks ln] ---------------- [bi->skb] "
 473                         "<-- Adv Rx Write-Back format\n");
 474
 475                 for (i = 0; i < rx_ring->count; i++) {
 476                         rx_buffer_info = &rx_ring->rx_buffer_info[i];
 477                         rx_desc = IXGBE_RX_DESC_ADV(rx_ring, i);
 478                         u0 = (struct my_u0 *)rx_desc;
 479                         staterr = le32_to_cpu(rx_desc->wb.upper.status_error);
 480                         if (staterr & IXGBE_RXD_STAT_DD) {
 481                                 /* Descriptor Done */
 482                                 pr_info("RWB[0x%03X]     %016llX "
 483                                         "%016llX ---------------- %p", i,
 484                                         le64_to_cpu(u0->a),
 485                                         le64_to_cpu(u0->b),
 486                                         rx_buffer_info->skb);
 487                         } else {
 488                                 pr_info("R  [0x%03X]     %016llX "
 489                                         "%016llX %016llX %p", i,
 490                                         le64_to_cpu(u0->a),
 491                                         le64_to_cpu(u0->b),
 492                                         (u64)rx_buffer_info->dma,
 493                                         rx_buffer_info->skb);
 494
 495                                 if (netif_msg_pktdata(adapter)) {
 496                                         print_hex_dump(KERN_INFO, "",
 497                                            DUMP_PREFIX_ADDRESS, 16, 1,
 498                                            phys_to_virt(rx_buffer_info->dma),
 499                                            rx_ring->rx_buf_len, true);
 500
 501                                         if (rx_ring->rx_buf_len
 502                                                 < IXGBE_RXBUFFER_2K)
 503                                                 print_hex_dump(KERN_INFO, "",
 504                                                   DUMP_PREFIX_ADDRESS, 16, 1,
 505                                                   phys_to_virt(
 506                                                     rx_buffer_info->page_dma +
 507                                                     rx_buffer_info->page_offset
 508                                                   ),
 509                                                   PAGE_SIZE/2, true);
 510                                 }
 511                         }
 512
 513                         if (i == rx_ring->next_to_use)
 514                                 pr_cont(" NTU\n");
 515                         else if (i == rx_ring->next_to_clean)
 516                                 pr_cont(" NTC\n");
 517                         else
 518                                 pr_cont("\n");
 519
 520                 }
 521         }
 522
 523 exit:
 524         return;
 525 }
 526
 527 static void ixgbe_release_hw_control(struct ixgbe_adapter *adapter)
 528 {
 529         u32 ctrl_ext;
 530
 531         /* Let firmware take over control of h/w */
 532         ctrl_ext = IXGBE_READ_REG(&adapter->hw, IXGBE_CTRL_EXT);
 533         IXGBE_WRITE_REG(&adapter->hw, IXGBE_CTRL_EXT,
 534                         ctrl_ext & ~IXGBE_CTRL_EXT_DRV_LOAD);
 535 }
 536
 537 static void ixgbe_get_hw_control(struct ixgbe_adapter *adapter)
 538 {
 539         u32 ctrl_ext;
 540
 541         /* Let firmware know the driver has taken over */
 542         ctrl_ext = IXGBE_READ_REG(&adapter->hw, IXGBE_CTRL_EXT);
 543         IXGBE_WRITE_REG(&adapter->hw, IXGBE_CTRL_EXT,
 544                         ctrl_ext | IXGBE_CTRL_EXT_DRV_LOAD);
 545 }
 546
 547 /*
 548  * ixgbe_set_ivar - set the IVAR registers, mapping interrupt causes to vectors
 549  * @adapter: pointer to adapter struct
 550  * @direction: 0 for Rx, 1 for Tx, -1 for other causes
 551  * @queue: queue to map the corresponding interrupt to
 552  * @msix_vector: the vector to map to the corresponding queue
 553  *
 554  */
 555 static void ixgbe_set_ivar(struct ixgbe_adapter *adapter, s8 direction,
 556                            u8 queue, u8 msix_vector)
 557 {
 558         u32 ivar, index;
 559         struct ixgbe_hw *hw = &adapter->hw;
 560         switch (hw->mac.type) {
 561         case ixgbe_mac_82598EB:
 562                 msix_vector |= IXGBE_IVAR_ALLOC_VAL;
 563                 if (direction == -1)
 564                         direction = 0;
 565                 index = (((direction * 64) + queue) >> 2) & 0x1F;
 566                 ivar = IXGBE_READ_REG(hw, IXGBE_IVAR(index));
 567                 ivar &= ~(0xFF << (8 * (queue & 0x3)));
 568                 ivar |= (msix_vector << (8 * (queue & 0x3)));
 569                 IXGBE_WRITE_REG(hw, IXGBE_IVAR(index), ivar);
 570                 break;
 571         case ixgbe_mac_82599EB:
 572         case ixgbe_mac_X540:
 573                 if (direction == -1) {
 574                         /* other causes */
 575                         msix_vector |= IXGBE_IVAR_ALLOC_VAL;
 576                         index = ((queue & 1) * 8);
 577                         ivar = IXGBE_READ_REG(&adapter->hw, IXGBE_IVAR_MISC);
 578                         ivar &= ~(0xFF << index);
 579                         ivar |= (msix_vector << index);
 580                         IXGBE_WRITE_REG(&adapter->hw, IXGBE_IVAR_MISC, ivar);
 581                         break;
 582                 } else {
 583                         /* tx or rx causes */
 584                         msix_vector |= IXGBE_IVAR_ALLOC_VAL;
 585                         index = ((16 * (queue & 1)) + (8 * direction));
 586                         ivar = IXGBE_READ_REG(hw, IXGBE_IVAR(queue >> 1));
 587                         ivar &= ~(0xFF << index);
 588                         ivar |= (msix_vector << index);
 589                         IXGBE_WRITE_REG(hw, IXGBE_IVAR(queue >> 1), ivar);
 590                         break;
 591                 }
 592         default:
 593                 break;
 594         }
 595 }
 596
 597 static inline void ixgbe_irq_rearm_queues(struct ixgbe_adapter *adapter,
 598                                           u64 qmask)
 599 {
 600         u32 mask;
 601
 602         switch (adapter->hw.mac.type) {
 603         case ixgbe_mac_82598EB:
 604                 mask = (IXGBE_EIMS_RTX_QUEUE & qmask);
 605                 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EICS, mask);
 606                 break;
 607         case ixgbe_mac_82599EB:
 608         case ixgbe_mac_X540:
 609                 mask = (qmask & 0xFFFFFFFF);
 610                 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EICS_EX(0), mask);
 611                 mask = (qmask >> 32);
 612                 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EICS_EX(1), mask);
 613                 break;
 614         default:
 615                 break;
 616         }
 617 }
 618
 619 static inline void ixgbe_unmap_tx_resource(struct ixgbe_ring *ring,
 620                                            struct ixgbe_tx_buffer *tx_buffer)
 621 {
 622         if (tx_buffer->dma) {
 623                 if (tx_buffer->tx_flags & IXGBE_TX_FLAGS_MAPPED_AS_PAGE)
 624                         dma_unmap_page(ring->dev,
 625                                        tx_buffer->dma,
 626                                        tx_buffer->length,
 627                                        DMA_TO_DEVICE);
 628                 else
 629                         dma_unmap_single(ring->dev,
 630                                          tx_buffer->dma,
 631                                          tx_buffer->length,
 632                                          DMA_TO_DEVICE);
 633         }
 634         tx_buffer->dma = 0;
 635 }
 636
 637 void ixgbe_unmap_and_free_tx_resource(struct ixgbe_ring *tx_ring,
 638                                       struct ixgbe_tx_buffer *tx_buffer_info)
 639 {
 640         ixgbe_unmap_tx_resource(tx_ring, tx_buffer_info);
 641         if (tx_buffer_info->skb)
 642                 dev_kfree_skb_any(tx_buffer_info->skb);
 643         tx_buffer_info->skb = NULL;
 644         /* tx_buffer_info must be completely set up in the transmit path */
 645 }
 646
 647 static void ixgbe_update_xoff_received(struct ixgbe_adapter *adapter)
 648 {
 649         struct ixgbe_hw *hw = &adapter->hw;
 650         struct ixgbe_hw_stats *hwstats = &adapter->stats;
 651         u32 data = 0;
 652         u32 xoff[8] = {0};
 653         int i;
 654
 655         if ((hw->fc.current_mode == ixgbe_fc_full) ||
 656             (hw->fc.current_mode == ixgbe_fc_rx_pause)) {
 657                 switch (hw->mac.type) {
 658                 case ixgbe_mac_82598EB:
 659                         data = IXGBE_READ_REG(hw, IXGBE_LXOFFRXC);
 660                         break;
 661                 default:
 662                         data = IXGBE_READ_REG(hw, IXGBE_LXOFFRXCNT);
 663                 }
 664                 hwstats->lxoffrxc += data;
 665
 666                 /* refill credits (no tx hang) if we received xoff */
 667                 if (!data)
 668                         return;
 669
 670                 for (i = 0; i < adapter->num_tx_queues; i++)
 671                         clear_bit(__IXGBE_HANG_CHECK_ARMED,
 672                                   &adapter->tx_ring[i]->state);
 673                 return;
 674         } else if (!(adapter->dcb_cfg.pfc_mode_enable))
 675                 return;
 676
 677         /* update stats for each tc, only valid with PFC enabled */
 678         for (i = 0; i < MAX_TX_PACKET_BUFFERS; i++) {
 679                 switch (hw->mac.type) {
 680                 case ixgbe_mac_82598EB:
 681                         xoff[i] = IXGBE_READ_REG(hw, IXGBE_PXOFFRXC(i));
 682                         break;
 683                 default:
 684                         xoff[i] = IXGBE_READ_REG(hw, IXGBE_PXOFFRXCNT(i));
 685                 }
 686                 hwstats->pxoffrxc[i] += xoff[i];
 687         }
 688
 689         /* disarm tx queues that have received xoff frames */
 690         for (i = 0; i < adapter->num_tx_queues; i++) {
 691                 struct ixgbe_ring *tx_ring = adapter->tx_ring[i];
 692                 u8 tc = tx_ring->dcb_tc;
 693
 694                 if (xoff[tc])
 695                         clear_bit(__IXGBE_HANG_CHECK_ARMED, &tx_ring->state);
 696         }
 697 }
 698
 699 static u64 ixgbe_get_tx_completed(struct ixgbe_ring *ring)
 700 {
 701         return ring->tx_stats.completed;
 702 }
 703
 704 static u64 ixgbe_get_tx_pending(struct ixgbe_ring *ring)
 705 {
 706         struct ixgbe_adapter *adapter = netdev_priv(ring->netdev);
 707         struct ixgbe_hw *hw = &adapter->hw;
 708
 709         u32 head = IXGBE_READ_REG(hw, IXGBE_TDH(ring->reg_idx));
 710         u32 tail = IXGBE_READ_REG(hw, IXGBE_TDT(ring->reg_idx));
 711
 712         if (head != tail)
 713                 return (head < tail) ?
 714                         tail - head : (tail + ring->count - head);
 715
 716         return 0;
 717 }
 718
 719 static inline bool ixgbe_check_tx_hang(struct ixgbe_ring *tx_ring)
 720 {
 721         u32 tx_done = ixgbe_get_tx_completed(tx_ring);
 722         u32 tx_done_old = tx_ring->tx_stats.tx_done_old;
 723         u32 tx_pending = ixgbe_get_tx_pending(tx_ring);
 724         bool ret = false;
 725
 726         clear_check_for_tx_hang(tx_ring);
 727
 728         /*
 729          * Check for a hung queue, but be thorough. This verifies
 730          * that a transmit has been completed since the previous
 731          * check AND there is at least one packet pending. The
 732          * ARMED bit is set to indicate a potential hang. The
 733          * bit is cleared if a pause frame is received to remove
 734          * false hang detection due to PFC or 802.3x frames. By
 735          * requiring this to fail twice we avoid races with
 736          * pfc clearing the ARMED bit and conditions where we
 737          * run the check_tx_hang logic with a transmit completion
 738          * pending but without time to complete it yet.
 739          */
 740         if ((tx_done_old == tx_done) && tx_pending) {
 741                 /* make sure it is true for two checks in a row */
 742                 ret = test_and_set_bit(__IXGBE_HANG_CHECK_ARMED,
 743                                        &tx_ring->state);
 744         } else {
 745                 /* update completed stats and continue */
 746                 tx_ring->tx_stats.tx_done_old = tx_done;
 747                 /* reset the countdown */
 748                 clear_bit(__IXGBE_HANG_CHECK_ARMED, &tx_ring->state);
 749         }
 750
 751         return ret;
 752 }
 753
 754 /**
 755  * ixgbe_tx_timeout_reset - initiate reset due to Tx timeout
 756  * @adapter: driver private struct
 757  **/
 758 static void ixgbe_tx_timeout_reset(struct ixgbe_adapter *adapter)
 759 {
 760
 761         /* Do the reset outside of interrupt context */
 762         if (!test_bit(__IXGBE_DOWN, &adapter->state)) {
 763                 adapter->flags2 |= IXGBE_FLAG2_RESET_REQUESTED;
 764                 ixgbe_service_event_schedule(adapter);
 765         }
 766 }
 767
 768 /**
 769  * ixgbe_clean_tx_irq - Reclaim resources after transmit completes
 770  * @q_vector: structure containing interrupt and ring information
 771  * @tx_ring: tx ring to clean
 772  **/
 773 static bool ixgbe_clean_tx_irq(struct ixgbe_q_vector *q_vector,
 774                                struct ixgbe_ring *tx_ring)
 775 {
 776         struct ixgbe_adapter *adapter = q_vector->adapter;
 777         struct ixgbe_tx_buffer *tx_buffer;
 778         union ixgbe_adv_tx_desc *tx_desc;
 779         unsigned int total_bytes = 0, total_packets = 0;
 780         unsigned int budget = q_vector->tx.work_limit;
 781         u16 i = tx_ring->next_to_clean;
 782
 783         tx_buffer = &tx_ring->tx_buffer_info[i];
 784         tx_desc = IXGBE_TX_DESC_ADV(tx_ring, i);
 785
 786         for (; budget; budget--) {
 787                 union ixgbe_adv_tx_desc *eop_desc = tx_buffer->next_to_watch;
 788
 789                 /* if next_to_watch is not set then there is no work pending */
 790                 if (!eop_desc)
 791                         break;
 792
 793                 /* if DD is not set pending work has not been completed */
 794                 if (!(eop_desc->wb.status & cpu_to_le32(IXGBE_TXD_STAT_DD)))
 795                         break;
 796
 797                 /* count the packet as being completed */
 798                 tx_ring->tx_stats.completed++;
 799
 800                 /* clear next_to_watch to prevent false hangs */
 801                 tx_buffer->next_to_watch = NULL;
 802
 803                 /* prevent any other reads prior to eop_desc being verified */
 804                 rmb();
 805
 806                 do {
 807                         ixgbe_unmap_tx_resource(tx_ring, tx_buffer);
 808                         tx_desc->wb.status = 0;
 809                         if (likely(tx_desc == eop_desc)) {
 810                                 eop_desc = NULL;
 811                                 dev_kfree_skb_any(tx_buffer->skb);
 812                                 tx_buffer->skb = NULL;
 813
 814                                 total_bytes += tx_buffer->bytecount;
 815                                 total_packets += tx_buffer->gso_segs;
 816                         }
 817
 818                         tx_buffer++;
 819                         tx_desc++;
 820                         i++;
 821                         if (unlikely(i == tx_ring->count)) {
 822                                 i = 0;
 823
 824                                 tx_buffer = tx_ring->tx_buffer_info;
 825                                 tx_desc = IXGBE_TX_DESC_ADV(tx_ring, 0);
 826                         }
 827
 828                 } while (eop_desc);
 829         }
 830
 831         tx_ring->next_to_clean = i;
 832         u64_stats_update_begin(&tx_ring->syncp);
 833         tx_ring->stats.bytes += total_bytes;
 834         tx_ring->stats.packets += total_packets;
 835         u64_stats_update_end(&tx_ring->syncp);
 836         q_vector->tx.total_bytes += total_bytes;
 837         q_vector->tx.total_packets += total_packets;
 838
 839         if (check_for_tx_hang(tx_ring) && ixgbe_check_tx_hang(tx_ring)) {
 840                 /* schedule immediate reset if we believe we hung */
 841                 struct ixgbe_hw *hw = &adapter->hw;
 842                 tx_desc = IXGBE_TX_DESC_ADV(tx_ring, i);
 843                 e_err(drv, "Detected Tx Unit Hang\n"
 844                         "  Tx Queue             <%d>\n"
 845                         "  TDH, TDT             <%x>, <%x>\n"
 846                         "  next_to_use          <%x>\n"
 847                         "  next_to_clean        <%x>\n"
 848                         "tx_buffer_info[next_to_clean]\n"
 849                         "  time_stamp           <%lx>\n"
 850                         "  jiffies              <%lx>\n",
 851                         tx_ring->queue_index,
 852                         IXGBE_READ_REG(hw, IXGBE_TDH(tx_ring->reg_idx)),
 853                         IXGBE_READ_REG(hw, IXGBE_TDT(tx_ring->reg_idx)),
 854                         tx_ring->next_to_use, i,
 855                         tx_ring->tx_buffer_info[i].time_stamp, jiffies);
 856
 857                 netif_stop_subqueue(tx_ring->netdev, tx_ring->queue_index);
 858
 859                 e_info(probe,
 860                        "tx hang %d detected on queue %d, resetting adapter\n",
 861                         adapter->tx_timeout_count + 1, tx_ring->queue_index);
 862
 863                 /* schedule immediate reset if we believe we hung */
 864                 ixgbe_tx_timeout_reset(adapter);
 865
 866                 /* the adapter is about to reset, no point in enabling stuff */
 867                 return true;
 868         }
 869
 870 #define TX_WAKE_THRESHOLD (DESC_NEEDED * 2)
 871         if (unlikely(total_packets && netif_carrier_ok(tx_ring->netdev) &&
 872                      (ixgbe_desc_unused(tx_ring) >= TX_WAKE_THRESHOLD))) {
 873                 /* Make sure that anybody stopping the queue after this
 874                  * sees the new next_to_clean.
 875                  */
 876                 smp_mb();
 877                 if (__netif_subqueue_stopped(tx_ring->netdev, tx_ring->queue_index) &&
 878                     !test_bit(__IXGBE_DOWN, &adapter->state)) {
 879                         netif_wake_subqueue(tx_ring->netdev, tx_ring->queue_index);
 880                         ++tx_ring->tx_stats.restart_queue;
 881                 }
 882         }
 883
 884         return !!budget;
 885 }
 886
 887 #ifdef CONFIG_IXGBE_DCA
 888 static void ixgbe_update_rx_dca(struct ixgbe_adapter *adapter,
 889                                 struct ixgbe_ring *rx_ring,
 890                                 int cpu)
 891 {
 892         struct ixgbe_hw *hw = &adapter->hw;
 893         u32 rxctrl;
 894         u8 reg_idx = rx_ring->reg_idx;
 895
 896         rxctrl = IXGBE_READ_REG(hw, IXGBE_DCA_RXCTRL(reg_idx));
 897         switch (hw->mac.type) {
 898         case ixgbe_mac_82598EB:
 899                 rxctrl &= ~IXGBE_DCA_RXCTRL_CPUID_MASK;
 900                 rxctrl |= dca3_get_tag(rx_ring->dev, cpu);
 901                 break;
 902         case ixgbe_mac_82599EB:
 903         case ixgbe_mac_X540:
 904                 rxctrl &= ~IXGBE_DCA_RXCTRL_CPUID_MASK_82599;
 905                 rxctrl |= (dca3_get_tag(rx_ring->dev, cpu) <<
 906                            IXGBE_DCA_RXCTRL_CPUID_SHIFT_82599);
 907                 break;
 908         default:
 909                 break;
 910         }
 911         rxctrl |= IXGBE_DCA_RXCTRL_DESC_DCA_EN;
 912         rxctrl |= IXGBE_DCA_RXCTRL_HEAD_DCA_EN;
 913         rxctrl &= ~(IXGBE_DCA_RXCTRL_DESC_RRO_EN);
 914         IXGBE_WRITE_REG(hw, IXGBE_DCA_RXCTRL(reg_idx), rxctrl);
 915 }
 916
 917 static void ixgbe_update_tx_dca(struct ixgbe_adapter *adapter,
 918                                 struct ixgbe_ring *tx_ring,
 919                                 int cpu)
 920 {
 921         struct ixgbe_hw *hw = &adapter->hw;
 922         u32 txctrl;
 923         u8 reg_idx = tx_ring->reg_idx;
 924
 925         switch (hw->mac.type) {
 926         case ixgbe_mac_82598EB:
 927                 txctrl = IXGBE_READ_REG(hw, IXGBE_DCA_TXCTRL(reg_idx));
 928                 txctrl &= ~IXGBE_DCA_TXCTRL_CPUID_MASK;
 929                 txctrl |= dca3_get_tag(tx_ring->dev, cpu);
 930                 txctrl |= IXGBE_DCA_TXCTRL_DESC_DCA_EN;
 931                 IXGBE_WRITE_REG(hw, IXGBE_DCA_TXCTRL(reg_idx), txctrl);
 932                 break;
 933         case ixgbe_mac_82599EB:
 934         case ixgbe_mac_X540:
 935                 txctrl = IXGBE_READ_REG(hw, IXGBE_DCA_TXCTRL_82599(reg_idx));
 936                 txctrl &= ~IXGBE_DCA_TXCTRL_CPUID_MASK_82599;
 937                 txctrl |= (dca3_get_tag(tx_ring->dev, cpu) <<
 938                            IXGBE_DCA_TXCTRL_CPUID_SHIFT_82599);
 939                 txctrl |= IXGBE_DCA_TXCTRL_DESC_DCA_EN;
 940                 IXGBE_WRITE_REG(hw, IXGBE_DCA_TXCTRL_82599(reg_idx), txctrl);
 941                 break;
 942         default:
 943                 break;
 944         }
 945 }
 946
 947 static void ixgbe_update_dca(struct ixgbe_q_vector *q_vector)
 948 {
 949         struct ixgbe_adapter *adapter = q_vector->adapter;
 950         struct ixgbe_ring *ring;
 951         int cpu = get_cpu();
 952
 953         if (q_vector->cpu == cpu)
 954                 goto out_no_update;
 955
 956         for (ring = q_vector->tx.ring; ring != NULL; ring = ring->next)
 957                 ixgbe_update_tx_dca(adapter, ring, cpu);
 958
 959         for (ring = q_vector->rx.ring; ring != NULL; ring = ring->next)
 960                 ixgbe_update_rx_dca(adapter, ring, cpu);
 961
 962         q_vector->cpu = cpu;
 963 out_no_update:
 964         put_cpu();
 965 }
 966
 967 static void ixgbe_setup_dca(struct ixgbe_adapter *adapter)
 968 {
 969         int num_q_vectors;
 970         int i;
 971
 972         if (!(adapter->flags & IXGBE_FLAG_DCA_ENABLED))
 973                 return;
 974
 975         /* always use CB2 mode, difference is masked in the CB driver */
 976         IXGBE_WRITE_REG(&adapter->hw, IXGBE_DCA_CTRL, 2);
 977
 978         if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED)
 979                 num_q_vectors = adapter->num_msix_vectors - NON_Q_VECTORS;
 980         else
 981                 num_q_vectors = 1;
 982
 983         for (i = 0; i < num_q_vectors; i++) {
 984                 adapter->q_vector[i]->cpu = -1;
 985                 ixgbe_update_dca(adapter->q_vector[i]);
 986         }
 987 }
 988
 989 static int __ixgbe_notify_dca(struct device *dev, void *data)
 990 {
 991         struct ixgbe_adapter *adapter = dev_get_drvdata(dev);
 992         unsigned long event = *(unsigned long *)data;
 993
 994         if (!(adapter->flags & IXGBE_FLAG_DCA_CAPABLE))
 995                 return 0;
 996
 997         switch (event) {
 998         case DCA_PROVIDER_ADD:
 999                 /* if we're already enabled, don't do it again */
1000                 if (adapter->flags & IXGBE_FLAG_DCA_ENABLED)
1001                         break;
1002                 if (dca_add_requester(dev) == 0) {
1003                         adapter->flags |= IXGBE_FLAG_DCA_ENABLED;
1004                         ixgbe_setup_dca(adapter);
1005                         break;
1006                 }
1007                 /* Fall Through since DCA is disabled. */
1008         case DCA_PROVIDER_REMOVE:
1009                 if (adapter->flags & IXGBE_FLAG_DCA_ENABLED) {
1010                         dca_remove_requester(dev);
1011                         adapter->flags &= ~IXGBE_FLAG_DCA_ENABLED;
1012                         IXGBE_WRITE_REG(&adapter->hw, IXGBE_DCA_CTRL, 1);
1013                 }
1014                 break;
1015         }
1016
1017         return 0;
1018 }
1019 #endif /* CONFIG_IXGBE_DCA */
1020
1021 static inline void ixgbe_rx_hash(union ixgbe_adv_rx_desc *rx_desc,
1022                                  struct sk_buff *skb)
1023 {
1024         skb->rxhash = le32_to_cpu(rx_desc->wb.lower.hi_dword.rss);
1025 }
1026
1027 /**
1028  * ixgbe_rx_is_fcoe - check the rx desc for incoming pkt type
1029  * @adapter: address of board private structure
1030  * @rx_desc: advanced rx descriptor
1031  *
1032  * Returns : true if it is FCoE pkt
1033  */
1034 static inline bool ixgbe_rx_is_fcoe(struct ixgbe_adapter *adapter,
1035                                     union ixgbe_adv_rx_desc *rx_desc)
1036 {
1037         __le16 pkt_info = rx_desc->wb.lower.lo_dword.hs_rss.pkt_info;
1038
1039         return (adapter->flags & IXGBE_FLAG_FCOE_ENABLED) &&
1040                ((pkt_info & cpu_to_le16(IXGBE_RXDADV_PKTTYPE_ETQF_MASK)) ==
1041                 (cpu_to_le16(IXGBE_ETQF_FILTER_FCOE <<
1042                              IXGBE_RXDADV_PKTTYPE_ETQF_SHIFT)));
1043 }
1044
1045 /**
1046  * ixgbe_receive_skb - Send a completed packet up the stack
1047  * @adapter: board private structure
1048  * @skb: packet to send up
1049  * @status: hardware indication of status of receive
1050  * @rx_ring: rx descriptor ring (for a specific queue) to setup
1051  * @rx_desc: rx descriptor
1052  **/
1053 static void ixgbe_receive_skb(struct ixgbe_q_vector *q_vector,
1054                               struct sk_buff *skb, u8 status,
1055                               struct ixgbe_ring *ring,
1056                               union ixgbe_adv_rx_desc *rx_desc)
1057 {
1058         struct ixgbe_adapter *adapter = q_vector->adapter;
1059         struct napi_struct *napi = &q_vector->napi;
1060         bool is_vlan = (status & IXGBE_RXD_STAT_VP);
1061         u16 tag = le16_to_cpu(rx_desc->wb.upper.vlan);
1062
1063         if (is_vlan && (tag & VLAN_VID_MASK))
1064                 __vlan_hwaccel_put_tag(skb, tag);
1065
1066         if (!(adapter->flags & IXGBE_FLAG_IN_NETPOLL))
1067                 napi_gro_receive(napi, skb);
1068         else
1069                 netif_rx(skb);
1070 }
1071
1072 /**
1073  * ixgbe_rx_checksum - indicate in skb if hw indicated a good cksum
1074  * @adapter: address of board private structure
1075  * @status_err: hardware indication of status of receive
1076  * @skb: skb currently being received and modified
1077  * @status_err: status error value of last descriptor in packet
1078  **/
1079 static inline void ixgbe_rx_checksum(struct ixgbe_adapter *adapter,
1080                                      union ixgbe_adv_rx_desc *rx_desc,
1081                                      struct sk_buff *skb,
1082                                      u32 status_err)
1083 {
1084         skb->ip_summed = CHECKSUM_NONE;
1085
1086         /* Rx csum disabled */
1087         if (!(adapter->flags & IXGBE_FLAG_RX_CSUM_ENABLED))
1088                 return;
1089
1090         /* if IP and error */
1091         if ((status_err & IXGBE_RXD_STAT_IPCS) &&
1092             (status_err & IXGBE_RXDADV_ERR_IPE)) {
1093                 adapter->hw_csum_rx_error++;
1094                 return;
1095         }
1096
1097         if (!(status_err & IXGBE_RXD_STAT_L4CS))
1098                 return;
1099
1100         if (status_err & IXGBE_RXDADV_ERR_TCPE) {
1101                 u16 pkt_info = rx_desc->wb.lower.lo_dword.hs_rss.pkt_info;
1102
1103                 /*
1104                  * 82599 errata, UDP frames with a 0 checksum can be marked as
1105                  * checksum errors.
1106                  */
1107                 if ((pkt_info & IXGBE_RXDADV_PKTTYPE_UDP) &&
1108                     (adapter->hw.mac.type == ixgbe_mac_82599EB))
1109                         return;
1110
1111                 adapter->hw_csum_rx_error++;
1112                 return;
1113         }
1114
1115         /* It must be a TCP or UDP packet with a valid checksum */
1116         skb->ip_summed = CHECKSUM_UNNECESSARY;
1117 }
1118
1119 static inline void ixgbe_release_rx_desc(struct ixgbe_ring *rx_ring, u32 val)
1120 {
1121         /*
1122          * Force memory writes to complete before letting h/w
1123          * know there are new descriptors to fetch.  (Only
1124          * applicable for weak-ordered memory model archs,
1125          * such as IA-64).
1126          */
1127         wmb();
1128         writel(val, rx_ring->tail);
1129 }
1130
1131 /**
1132  * ixgbe_alloc_rx_buffers - Replace used receive buffers; packet split
1133  * @rx_ring: ring to place buffers on
1134  * @cleaned_count: number of buffers to replace
1135  **/
1136 void ixgbe_alloc_rx_buffers(struct ixgbe_ring *rx_ring, u16 cleaned_count)
1137 {
1138         union ixgbe_adv_rx_desc *rx_desc;
1139         struct ixgbe_rx_buffer *bi;
1140         struct sk_buff *skb;
1141         u16 i = rx_ring->next_to_use;
1142
1143         /* do nothing if no valid netdev defined */
1144         if (!rx_ring->netdev)
1145                 return;
1146
1147         while (cleaned_count--) {
1148                 rx_desc = IXGBE_RX_DESC_ADV(rx_ring, i);
1149                 bi = &rx_ring->rx_buffer_info[i];
1150                 skb = bi->skb;
1151
1152                 if (!skb) {
1153                         skb = netdev_alloc_skb_ip_align(rx_ring->netdev,
1154                                                         rx_ring->rx_buf_len);
1155                         if (!skb) {
1156                                 rx_ring->rx_stats.alloc_rx_buff_failed++;
1157                                 goto no_buffers;
1158                         }
1159                         /* initialize queue mapping */
1160                         skb_record_rx_queue(skb, rx_ring->queue_index);
1161                         bi->skb = skb;
1162                 }
1163
1164                 if (!bi->dma) {
1165                         bi->dma = dma_map_single(rx_ring->dev,
1166                                                  skb->data,
1167                                                  rx_ring->rx_buf_len,
1168                                                  DMA_FROM_DEVICE);
1169                         if (dma_mapping_error(rx_ring->dev, bi->dma)) {
1170                                 rx_ring->rx_stats.alloc_rx_buff_failed++;
1171                                 bi->dma = 0;
1172                                 goto no_buffers;
1173                         }
1174                 }
1175
1176                 if (ring_is_ps_enabled(rx_ring)) {
1177                         if (!bi->page) {
1178                                 bi->page = netdev_alloc_page(rx_ring->netdev);
1179                                 if (!bi->page) {
1180                                         rx_ring->rx_stats.alloc_rx_page_failed++;
1181                                         goto no_buffers;
1182                                 }
1183                         }
1184
1185                         if (!bi->page_dma) {
1186                                 /* use a half page if we're re-using */
1187                                 bi->page_offset ^= PAGE_SIZE / 2;
1188                                 bi->page_dma = dma_map_page(rx_ring->dev,
1189                                                             bi->page,
1190                                                             bi->page_offset,
1191                                                             PAGE_SIZE / 2,
1192                                                             DMA_FROM_DEVICE);
1193                                 if (dma_mapping_error(rx_ring->dev,
1194                                                       bi->page_dma)) {
1195                                         rx_ring->rx_stats.alloc_rx_page_failed++;
1196                                         bi->page_dma = 0;
1197                                         goto no_buffers;
1198                                 }
1199                         }
1200
1201                         /* Refresh the desc even if buffer_addrs didn't change
1202                          * because each write-back erases this info. */
1203                         rx_desc->read.pkt_addr = cpu_to_le64(bi->page_dma);
1204                         rx_desc->read.hdr_addr = cpu_to_le64(bi->dma);
1205                 } else {
1206                         rx_desc->read.pkt_addr = cpu_to_le64(bi->dma);
1207                         rx_desc->read.hdr_addr = 0;
1208                 }
1209
1210                 i++;
1211                 if (i == rx_ring->count)
1212                         i = 0;
1213         }
1214
1215 no_buffers:
1216         if (rx_ring->next_to_use != i) {
1217                 rx_ring->next_to_use = i;
1218                 ixgbe_release_rx_desc(rx_ring, i);
1219         }
1220 }
1221
1222 static inline u16 ixgbe_get_hlen(union ixgbe_adv_rx_desc *rx_desc)
1223 {
1224         /* HW will not DMA in data larger than the given buffer, even if it
1225          * parses the (NFS, of course) header to be larger.  In that case, it
1226          * fills the header buffer and spills the rest into the page.
1227          */
1228         u16 hdr_info = le16_to_cpu(rx_desc->wb.lower.lo_dword.hs_rss.hdr_info);
1229         u16 hlen = (hdr_info &  IXGBE_RXDADV_HDRBUFLEN_MASK) >>
1230                     IXGBE_RXDADV_HDRBUFLEN_SHIFT;
1231         if (hlen > IXGBE_RX_HDR_SIZE)
1232                 hlen = IXGBE_RX_HDR_SIZE;
1233         return hlen;
1234 }
1235
1236 /**
1237  * ixgbe_transform_rsc_queue - change rsc queue into a full packet
1238  * @skb: pointer to the last skb in the rsc queue
1239  *
1240  * This function changes a queue full of hw rsc buffers into a completed
1241  * packet.  It uses the ->prev pointers to find the first packet and then
1242  * turns it into the frag list owner.
1243  **/
1244 static inline struct sk_buff *ixgbe_transform_rsc_queue(struct sk_buff *skb)
1245 {
1246         unsigned int frag_list_size = 0;
1247         unsigned int skb_cnt = 1;
1248
1249         while (skb->prev) {
1250                 struct sk_buff *prev = skb->prev;
1251                 frag_list_size += skb->len;
1252                 skb->prev = NULL;
1253                 skb = prev;
1254                 skb_cnt++;
1255         }
1256
1257         skb_shinfo(skb)->frag_list = skb->next;
1258         skb->next = NULL;
1259         skb->len += frag_list_size;
1260         skb->data_len += frag_list_size;
1261         skb->truesize += frag_list_size;
1262         IXGBE_RSC_CB(skb)->skb_cnt = skb_cnt;
1263
1264         return skb;
1265 }
1266
1267 static inline bool ixgbe_get_rsc_state(union ixgbe_adv_rx_desc *rx_desc)
1268 {
1269         return !!(le32_to_cpu(rx_desc->wb.lower.lo_dword.data) &
1270                 IXGBE_RXDADV_RSCCNT_MASK);
1271 }
1272
1273 static bool ixgbe_clean_rx_irq(struct ixgbe_q_vector *q_vector,
1274                                struct ixgbe_ring *rx_ring,
1275                                int budget)
1276 {
1277         struct ixgbe_adapter *adapter = q_vector->adapter;
1278         union ixgbe_adv_rx_desc *rx_desc, *next_rxd;
1279         struct ixgbe_rx_buffer *rx_buffer_info, *next_buffer;
1280         struct sk_buff *skb;
1281         unsigned int total_rx_bytes = 0, total_rx_packets = 0;
1282         const int current_node = numa_node_id();
1283 #ifdef IXGBE_FCOE
1284         int ddp_bytes = 0;
1285 #endif /* IXGBE_FCOE */
1286         u32 staterr;
1287         u16 i;
1288         u16 cleaned_count = 0;
1289         bool pkt_is_rsc = false;
1290
1291         i = rx_ring->next_to_clean;
1292         rx_desc = IXGBE_RX_DESC_ADV(rx_ring, i);
1293         staterr = le32_to_cpu(rx_desc->wb.upper.status_error);
1294
1295         while (staterr & IXGBE_RXD_STAT_DD) {
1296                 u32 upper_len = 0;
1297
1298                 rmb(); /* read descriptor and rx_buffer_info after status DD */
1299
1300                 rx_buffer_info = &rx_ring->rx_buffer_info[i];
1301
1302                 skb = rx_buffer_info->skb;
1303                 rx_buffer_info->skb = NULL;
1304                 prefetch(skb->data);
1305
1306                 if (ring_is_rsc_enabled(rx_ring))
1307                         pkt_is_rsc = ixgbe_get_rsc_state(rx_desc);
1308
1309                 /* if this is a skb from previous receive DMA will be 0 */
1310                 if (rx_buffer_info->dma) {
1311                         u16 hlen;
1312                         if (pkt_is_rsc &&
1313                             !(staterr & IXGBE_RXD_STAT_EOP) &&
1314                             !skb->prev) {
1315                                 /*
1316                                  * When HWRSC is enabled, delay unmapping
1317                                  * of the first packet. It carries the
1318                                  * header information, HW may still
1319                                  * access the header after the writeback.
1320                                  * Only unmap it when EOP is reached
1321                                  */
1322                                 IXGBE_RSC_CB(skb)->delay_unmap = true;
1323                                 IXGBE_RSC_CB(skb)->dma = rx_buffer_info->dma;
1324                         } else {
1325                                 dma_unmap_single(rx_ring->dev,
1326                                                  rx_buffer_info->dma,
1327                                                  rx_ring->rx_buf_len,
1328                                                  DMA_FROM_DEVICE);
1329                         }
1330                         rx_buffer_info->dma = 0;
1331
1332                         if (ring_is_ps_enabled(rx_ring)) {
1333                                 hlen = ixgbe_get_hlen(rx_desc);
1334                                 upper_len = le16_to_cpu(rx_desc->wb.upper.length);
1335                         } else {
1336                                 hlen = le16_to_cpu(rx_desc->wb.upper.length);
1337                         }
1338
1339                         skb_put(skb, hlen);
1340                 } else {
1341                         /* assume packet split since header is unmapped */
1342                         upper_len = le16_to_cpu(rx_desc->wb.upper.length);
1343                 }
1344
1345                 if (upper_len) {
1346                         dma_unmap_page(rx_ring->dev,
1347                                        rx_buffer_info->page_dma,
1348                                        PAGE_SIZE / 2,
1349                                        DMA_FROM_DEVICE);
1350                         rx_buffer_info->page_dma = 0;
1351                         skb_fill_page_desc(skb, skb_shinfo(skb)->nr_frags,
1352                                            rx_buffer_info->page,
1353                                            rx_buffer_info->page_offset,
1354                                            upper_len);
1355
1356                         if ((page_count(rx_buffer_info->page) == 1) &&
1357                             (page_to_nid(rx_buffer_info->page) == current_node))
1358                                 get_page(rx_buffer_info->page);
1359                         else
1360                                 rx_buffer_info->page = NULL;
1361
1362                         skb->len += upper_len;
1363                         skb->data_len += upper_len;
1364                         skb->truesize += upper_len;
1365                 }
1366
1367                 i++;
1368                 if (i == rx_ring->count)
1369                         i = 0;
1370
1371                 next_rxd = IXGBE_RX_DESC_ADV(rx_ring, i);
1372                 prefetch(next_rxd);
1373                 cleaned_count++;
1374
1375                 if (pkt_is_rsc) {
1376                         u32 nextp = (staterr & IXGBE_RXDADV_NEXTP_MASK) >>
1377                                      IXGBE_RXDADV_NEXTP_SHIFT;
1378                         next_buffer = &rx_ring->rx_buffer_info[nextp];
1379                 } else {
1380                         next_buffer = &rx_ring->rx_buffer_info[i];
1381                 }
1382
1383                 if (!(staterr & IXGBE_RXD_STAT_EOP)) {
1384                         if (ring_is_ps_enabled(rx_ring)) {
1385                                 rx_buffer_info->skb = next_buffer->skb;
1386                                 rx_buffer_info->dma = next_buffer->dma;
1387                                 next_buffer->skb = skb;
1388                                 next_buffer->dma = 0;
1389                         } else {
1390                                 skb->next = next_buffer->skb;
1391                                 skb->next->prev = skb;
1392                         }
1393                         rx_ring->rx_stats.non_eop_descs++;
1394                         goto next_desc;
1395                 }
1396
1397                 if (skb->prev) {
1398                         skb = ixgbe_transform_rsc_queue(skb);
1399                         /* if we got here without RSC the packet is invalid */
1400                         if (!pkt_is_rsc) {
1401                                 __pskb_trim(skb, 0);
1402                                 rx_buffer_info->skb = skb;
1403                                 goto next_desc;
1404                         }
1405                 }
1406
1407                 if (ring_is_rsc_enabled(rx_ring)) {
1408                         if (IXGBE_RSC_CB(skb)->delay_unmap) {
1409                                 dma_unmap_single(rx_ring->dev,
1410                                                  IXGBE_RSC_CB(skb)->dma,
1411                                                  rx_ring->rx_buf_len,
1412                                                  DMA_FROM_DEVICE);
1413                                 IXGBE_RSC_CB(skb)->dma = 0;
1414                                 IXGBE_RSC_CB(skb)->delay_unmap = false;
1415                         }
1416                 }
1417                 if (pkt_is_rsc) {
1418                         if (ring_is_ps_enabled(rx_ring))
1419                                 rx_ring->rx_stats.rsc_count +=
1420                                         skb_shinfo(skb)->nr_frags;
1421                         else
1422                                 rx_ring->rx_stats.rsc_count +=
1423                                         IXGBE_RSC_CB(skb)->skb_cnt;
1424                         rx_ring->rx_stats.rsc_flush++;
1425                 }
1426
1427                 /* ERR_MASK will only have valid bits if EOP set */
1428                 if (unlikely(staterr & IXGBE_RXDADV_ERR_FRAME_ERR_MASK)) {
1429                         dev_kfree_skb_any(skb);
1430                         goto next_desc;
1431                 }
1432
1433                 ixgbe_rx_checksum(adapter, rx_desc, skb, staterr);
1434                 if (adapter->netdev->features & NETIF_F_RXHASH)
1435                         ixgbe_rx_hash(rx_desc, skb);
1436
1437                 /* probably a little skewed due to removing CRC */
1438                 total_rx_bytes += skb->len;
1439                 total_rx_packets++;
1440
1441                 skb->protocol = eth_type_trans(skb, rx_ring->netdev);
1442 #ifdef IXGBE_FCOE
1443                 /* if ddp, not passing to ULD unless for FCP_RSP or error */
1444                 if (ixgbe_rx_is_fcoe(adapter, rx_desc)) {
1445                         ddp_bytes = ixgbe_fcoe_ddp(adapter, rx_desc, skb,
1446                                                    staterr);
1447                         if (!ddp_bytes) {
1448                                 dev_kfree_skb_any(skb);
1449                                 goto next_desc;
1450                         }
1451                 }
1452 #endif /* IXGBE_FCOE */
1453                 ixgbe_receive_skb(q_vector, skb, staterr, rx_ring, rx_desc);
1454
1455                 budget--;
1456 next_desc:
1457                 rx_desc->wb.upper.status_error = 0;
1458
1459                 if (!budget)
1460                         break;
1461
1462                 /* return some buffers to hardware, one at a time is too slow */
1463                 if (cleaned_count >= IXGBE_RX_BUFFER_WRITE) {
1464                         ixgbe_alloc_rx_buffers(rx_ring, cleaned_count);
1465                         cleaned_count = 0;
1466                 }
1467
1468                 /* use prefetched values */
1469                 rx_desc = next_rxd;
1470                 staterr = le32_to_cpu(rx_desc->wb.upper.status_error);
1471         }
1472
1473         rx_ring->next_to_clean = i;
1474         cleaned_count = ixgbe_desc_unused(rx_ring);
1475
1476         if (cleaned_count)
1477                 ixgbe_alloc_rx_buffers(rx_ring, cleaned_count);
1478
1479 #ifdef IXGBE_FCOE
1480         /* include DDPed FCoE data */
1481         if (ddp_bytes > 0) {
1482                 unsigned int mss;
1483
1484                 mss = rx_ring->netdev->mtu - sizeof(struct fcoe_hdr) -
1485                         sizeof(struct fc_frame_header) -
1486                         sizeof(struct fcoe_crc_eof);
1487                 if (mss > 512)
1488                         mss &= ~511;
1489                 total_rx_bytes += ddp_bytes;
1490                 total_rx_packets += DIV_ROUND_UP(ddp_bytes, mss);
1491         }
1492 #endif /* IXGBE_FCOE */
1493
1494         u64_stats_update_begin(&rx_ring->syncp);
1495         rx_ring->stats.packets += total_rx_packets;
1496         rx_ring->stats.bytes += total_rx_bytes;
1497         u64_stats_update_end(&rx_ring->syncp);
1498         q_vector->rx.total_packets += total_rx_packets;
1499         q_vector->rx.total_bytes += total_rx_bytes;
1500
1501         return !!budget;
1502 }
1503
1504 /**
1505  * ixgbe_configure_msix - Configure MSI-X hardware
1506  * @adapter: board private structure
1507  *
1508  * ixgbe_configure_msix sets up the hardware to properly generate MSI-X
1509  * interrupts.
1510  **/
1511 static void ixgbe_configure_msix(struct ixgbe_adapter *adapter)
1512 {
1513         struct ixgbe_q_vector *q_vector;
1514         int q_vectors, v_idx;
1515         u32 mask;
1516
1517         q_vectors = adapter->num_msix_vectors - NON_Q_VECTORS;
1518
1519         /* Populate MSIX to EITR Select */
1520         if (adapter->num_vfs > 32) {
1521                 u32 eitrsel = (1 << (adapter->num_vfs - 32)) - 1;
1522                 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EITRSEL, eitrsel);
1523         }
1524
1525         /*
1526          * Populate the IVAR table and set the ITR values to the
1527          * corresponding register.
1528          */
1529         for (v_idx = 0; v_idx < q_vectors; v_idx++) {
1530                 struct ixgbe_ring *ring;
1531                 q_vector = adapter->q_vector[v_idx];
1532
1533                 for (ring = q_vector->rx.ring; ring != NULL; ring = ring->next)
1534                         ixgbe_set_ivar(adapter, 0, ring->reg_idx, v_idx);
1535
1536                 for (ring = q_vector->tx.ring; ring != NULL; ring = ring->next)
1537                         ixgbe_set_ivar(adapter, 1, ring->reg_idx, v_idx);
1538
1539                 if (q_vector->tx.ring && !q_vector->rx.ring)
1540                         /* tx only */
1541                         q_vector->eitr = adapter->tx_eitr_param;
1542                 else if (q_vector->rx.ring)
1543                         /* rx or mixed */
1544                         q_vector->eitr = adapter->rx_eitr_param;
1545
1546                 ixgbe_write_eitr(q_vector);
1547         }
1548
1549         switch (adapter->hw.mac.type) {
1550         case ixgbe_mac_82598EB:
1551                 ixgbe_set_ivar(adapter, -1, IXGBE_IVAR_OTHER_CAUSES_INDEX,
1552                                v_idx);
1553                 break;
1554         case ixgbe_mac_82599EB:
1555         case ixgbe_mac_X540:
1556                 ixgbe_set_ivar(adapter, -1, 1, v_idx);
1557                 break;
1558
1559         default:
1560                 break;
1561         }
1562         IXGBE_WRITE_REG(&adapter->hw, IXGBE_EITR(v_idx), 1950);
1563
1564         /* set up to autoclear timer, and the vectors */
1565         mask = IXGBE_EIMS_ENABLE_MASK;
1566         if (adapter->num_vfs)
1567                 mask &= ~(IXGBE_EIMS_OTHER |
1568                           IXGBE_EIMS_MAILBOX |
1569                           IXGBE_EIMS_LSC);
1570         else
1571                 mask &= ~(IXGBE_EIMS_OTHER | IXGBE_EIMS_LSC);
1572         IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIAC, mask);
1573 }
1574
1575 enum latency_range {
1576         lowest_latency = 0,
1577         low_latency = 1,
1578         bulk_latency = 2,
1579         latency_invalid = 255
1580 };
1581
1582 /**
1583  * ixgbe_update_itr - update the dynamic ITR value based on statistics
1584  * @q_vector: structure containing interrupt and ring information
1585  * @ring_container: structure containing ring performance data
1586  *
1587  *      Stores a new ITR value based on packets and byte
1588  *      counts during the last interrupt.  The advantage of per interrupt
1589  *      computation is faster updates and more accurate ITR for the current
1590  *      traffic pattern.  Constants in this function were computed
1591  *      based on theoretical maximum wire speed and thresholds were set based
1592  *      on testing data as well as attempting to minimize response time
1593  *      while increasing bulk throughput.
1594  *      this functionality is controlled by the InterruptThrottleRate module
1595  *      parameter (see ixgbe_param.c)
1596  **/
1597 static void ixgbe_update_itr(struct ixgbe_q_vector *q_vector,
1598                              struct ixgbe_ring_container *ring_container)
1599 {
1600         u64 bytes_perint;
1601         struct ixgbe_adapter *adapter = q_vector->adapter;
1602         int bytes = ring_container->total_bytes;
1603         int packets = ring_container->total_packets;
1604         u32 timepassed_us;
1605         u8 itr_setting = ring_container->itr;
1606
1607         if (packets == 0)
1608                 return;
1609
1610         /* simple throttlerate management
1611          *    0-20MB/s lowest (100000 ints/s)
1612          *   20-100MB/s low   (20000 ints/s)
1613          *  100-1249MB/s bulk (8000 ints/s)
1614          */
1615         /* what was last interrupt timeslice? */
1616         timepassed_us = 1000000/q_vector->eitr;
1617         bytes_perint = bytes / timepassed_us; /* bytes/usec */
1618
1619         switch (itr_setting) {
1620         case lowest_latency:
1621                 if (bytes_perint > adapter->eitr_low)
1622                         itr_setting = low_latency;
1623                 break;
1624         case low_latency:
1625                 if (bytes_perint > adapter->eitr_high)
1626                         itr_setting = bulk_latency;
1627                 else if (bytes_perint <= adapter->eitr_low)
1628                         itr_setting = lowest_latency;
1629                 break;
1630         case bulk_latency:
1631                 if (bytes_perint <= adapter->eitr_high)
1632                         itr_setting = low_latency;
1633                 break;
1634         }
1635
1636         /* clear work counters since we have the values we need */
1637         ring_container->total_bytes = 0;
1638         ring_container->total_packets = 0;
1639
1640         /* write updated itr to ring container */
1641         ring_container->itr = itr_setting;
1642 }
1643
1644 /**
1645  * ixgbe_write_eitr - write EITR register in hardware specific way
1646  * @q_vector: structure containing interrupt and ring information
1647  *
1648  * This function is made to be called by ethtool and by the driver
1649  * when it needs to update EITR registers at runtime.  Hardware
1650  * specific quirks/differences are taken care of here.
1651  */
1652 void ixgbe_write_eitr(struct ixgbe_q_vector *q_vector)
1653 {
1654         struct ixgbe_adapter *adapter = q_vector->adapter;
1655         struct ixgbe_hw *hw = &adapter->hw;
1656         int v_idx = q_vector->v_idx;
1657         u32 itr_reg = EITR_INTS_PER_SEC_TO_REG(q_vector->eitr);
1658
1659         switch (adapter->hw.mac.type) {
1660         case ixgbe_mac_82598EB:
1661                 /* must write high and low 16 bits to reset counter */
1662                 itr_reg |= (itr_reg << 16);
1663                 break;
1664         case ixgbe_mac_82599EB:
1665         case ixgbe_mac_X540:
1666                 /*
1667                  * 82599 and X540 can support a value of zero, so allow it for
1668                  * max interrupt rate, but there is an errata where it can
1669                  * not be zero with RSC
1670                  */
1671                 if (itr_reg == 8 &&
1672                     !(adapter->flags2 & IXGBE_FLAG2_RSC_ENABLED))
1673                         itr_reg = 0;
1674
1675                 /*
1676                  * set the WDIS bit to not clear the timer bits and cause an
1677                  * immediate assertion of the interrupt
1678                  */
1679                 itr_reg |= IXGBE_EITR_CNT_WDIS;
1680                 break;
1681         default:
1682                 break;
1683         }
1684         IXGBE_WRITE_REG(hw, IXGBE_EITR(v_idx), itr_reg);
1685 }
1686
1687 static void ixgbe_set_itr(struct ixgbe_q_vector *q_vector)
1688 {
1689         u32 new_itr = q_vector->eitr;
1690         u8 current_itr;
1691
1692         ixgbe_update_itr(q_vector, &q_vector->tx);
1693         ixgbe_update_itr(q_vector, &q_vector->rx);
1694
1695         current_itr = max(q_vector->rx.itr, q_vector->tx.itr);
1696
1697         switch (current_itr) {
1698         /* counts and packets in update_itr are dependent on these numbers */
1699         case lowest_latency:
1700                 new_itr = 100000;
1701                 break;
1702         case low_latency:
1703                 new_itr = 20000; /* aka hwitr = ~200 */
1704                 break;
1705         case bulk_latency:
1706                 new_itr = 8000;
1707                 break;
1708         default:
1709                 break;
1710         }
1711
1712         if (new_itr != q_vector->eitr) {
1713                 /* do an exponential smoothing */
1714                 new_itr = ((q_vector->eitr * 9) + new_itr)/10;
1715
1716                 /* save the algorithm value here */
1717                 q_vector->eitr = new_itr;
1718
1719                 ixgbe_write_eitr(q_vector);
1720         }
1721 }
1722
1723 /**
1724  * ixgbe_check_overtemp_subtask - check for over tempurature
1725  * @adapter: pointer to adapter
1726  **/
1727 static void ixgbe_check_overtemp_subtask(struct ixgbe_adapter *adapter)
1728 {
1729         struct ixgbe_hw *hw = &adapter->hw;
1730         u32 eicr = adapter->interrupt_event;
1731
1732         if (test_bit(__IXGBE_DOWN, &adapter->state))
1733                 return;
1734
1735         if (!(adapter->flags2 & IXGBE_FLAG2_TEMP_SENSOR_CAPABLE) &&
1736             !(adapter->flags2 & IXGBE_FLAG2_TEMP_SENSOR_EVENT))
1737                 return;
1738
1739         adapter->flags2 &= ~IXGBE_FLAG2_TEMP_SENSOR_EVENT;
1740
1741         switch (hw->device_id) {
1742         case IXGBE_DEV_ID_82599_T3_LOM:
1743                 /*
1744                  * Since the warning interrupt is for both ports
1745                  * we don't have to check if:
1746                  *  - This interrupt wasn't for our port.
1747                  *  - We may have missed the interrupt so always have to
1748                  *    check if we  got a LSC
1749                  */
1750                 if (!(eicr & IXGBE_EICR_GPI_SDP0) &&
1751                     !(eicr & IXGBE_EICR_LSC))
1752                         return;
1753
1754                 if (!(eicr & IXGBE_EICR_LSC) && hw->mac.ops.check_link) {
1755                         u32 autoneg;
1756                         bool link_up = false;
1757
1758                         hw->mac.ops.check_link(hw, &autoneg, &link_up, false);
1759
1760                         if (link_up)
1761                                 return;
1762                 }
1763
1764                 /* Check if this is not due to overtemp */
1765                 if (hw->phy.ops.check_overtemp(hw) != IXGBE_ERR_OVERTEMP)
1766                         return;
1767
1768                 break;
1769         default:
1770                 if (!(eicr & IXGBE_EICR_GPI_SDP0))
1771                         return;
1772                 break;
1773         }
1774         e_crit(drv,
1775                "Network adapter has been stopped because it has over heated. "
1776                "Restart the computer. If the problem persists, "
1777                "power off the system and replace the adapter\n");
1778
1779         adapter->interrupt_event = 0;
1780 }
1781
1782 static void ixgbe_check_fan_failure(struct ixgbe_adapter *adapter, u32 eicr)
1783 {
1784         struct ixgbe_hw *hw = &adapter->hw;
1785
1786         if ((adapter->flags & IXGBE_FLAG_FAN_FAIL_CAPABLE) &&
1787             (eicr & IXGBE_EICR_GPI_SDP1)) {
1788                 e_crit(probe, "Fan has stopped, replace the adapter\n");
1789                 /* write to clear the interrupt */
1790                 IXGBE_WRITE_REG(hw, IXGBE_EICR, IXGBE_EICR_GPI_SDP1);
1791         }
1792 }
1793
1794 static void ixgbe_check_sfp_event(struct ixgbe_adapter *adapter, u32 eicr)
1795 {
1796         struct ixgbe_hw *hw = &adapter->hw;
1797
1798         if (eicr & IXGBE_EICR_GPI_SDP2) {
1799                 /* Clear the interrupt */
1800                 IXGBE_WRITE_REG(hw, IXGBE_EICR, IXGBE_EICR_GPI_SDP2);
1801                 if (!test_bit(__IXGBE_DOWN, &adapter->state)) {
1802                         adapter->flags2 |= IXGBE_FLAG2_SFP_NEEDS_RESET;
1803                         ixgbe_service_event_schedule(adapter);
1804                 }
1805         }
1806
1807         if (eicr & IXGBE_EICR_GPI_SDP1) {
1808                 /* Clear the interrupt */
1809                 IXGBE_WRITE_REG(hw, IXGBE_EICR, IXGBE_EICR_GPI_SDP1);
1810                 if (!test_bit(__IXGBE_DOWN, &adapter->state)) {
1811                         adapter->flags |= IXGBE_FLAG_NEED_LINK_CONFIG;
1812                         ixgbe_service_event_schedule(adapter);
1813                 }
1814         }
1815 }
1816
1817 static void ixgbe_check_lsc(struct ixgbe_adapter *adapter)
1818 {
1819         struct ixgbe_hw *hw = &adapter->hw;
1820
1821         adapter->lsc_int++;
1822         adapter->flags |= IXGBE_FLAG_NEED_LINK_UPDATE;
1823         adapter->link_check_timeout = jiffies;
1824         if (!test_bit(__IXGBE_DOWN, &adapter->state)) {
1825                 IXGBE_WRITE_REG(hw, IXGBE_EIMC, IXGBE_EIMC_LSC);
1826                 IXGBE_WRITE_FLUSH(hw);
1827                 ixgbe_service_event_schedule(adapter);
1828         }
1829 }
1830
1831 static inline void ixgbe_irq_enable_queues(struct ixgbe_adapter *adapter,
1832                                            u64 qmask)
1833 {
1834         u32 mask;
1835         struct ixgbe_hw *hw = &adapter->hw;
1836
1837         switch (hw->mac.type) {
1838         case ixgbe_mac_82598EB:
1839                 mask = (IXGBE_EIMS_RTX_QUEUE & qmask);
1840                 IXGBE_WRITE_REG(hw, IXGBE_EIMS, mask);
1841                 break;
1842         case ixgbe_mac_82599EB:
1843         case ixgbe_mac_X540:
1844                 mask = (qmask & 0xFFFFFFFF);
1845                 if (mask)
1846                         IXGBE_WRITE_REG(hw, IXGBE_EIMS_EX(0), mask);
1847                 mask = (qmask >> 32);
1848                 if (mask)
1849                         IXGBE_WRITE_REG(hw, IXGBE_EIMS_EX(1), mask);
1850                 break;
1851         default:
1852                 break;
1853         }
1854         /* skip the flush */
1855 }
1856
1857 static inline void ixgbe_irq_disable_queues(struct ixgbe_adapter *adapter,
1858                                             u64 qmask)
1859 {
1860         u32 mask;
1861         struct ixgbe_hw *hw = &adapter->hw;
1862
1863         switch (hw->mac.type) {
1864         case ixgbe_mac_82598EB:
1865                 mask = (IXGBE_EIMS_RTX_QUEUE & qmask);
1866                 IXGBE_WRITE_REG(hw, IXGBE_EIMC, mask);
1867                 break;
1868         case ixgbe_mac_82599EB:
1869         case ixgbe_mac_X540:
1870                 mask = (qmask & 0xFFFFFFFF);
1871                 if (mask)
1872                         IXGBE_WRITE_REG(hw, IXGBE_EIMC_EX(0), mask);
1873                 mask = (qmask >> 32);
1874                 if (mask)
1875                         IXGBE_WRITE_REG(hw, IXGBE_EIMC_EX(1), mask);
1876                 break;
1877         default:
1878                 break;
1879         }
1880         /* skip the flush */
1881 }
1882
1883 /**
1884  * ixgbe_irq_enable - Enable default interrupt generation settings
1885  * @adapter: board private structure
1886  **/
1887 static inline void ixgbe_irq_enable(struct ixgbe_adapter *adapter, bool queues,
1888                                     bool flush)
1889 {
1890         u32 mask = (IXGBE_EIMS_ENABLE_MASK & ~IXGBE_EIMS_RTX_QUEUE);
1891
1892         /* don't reenable LSC while waiting for link */
1893         if (adapter->flags & IXGBE_FLAG_NEED_LINK_UPDATE)
1894                 mask &= ~IXGBE_EIMS_LSC;
1895
1896         if (adapter->flags2 & IXGBE_FLAG2_TEMP_SENSOR_CAPABLE)
1897                 mask |= IXGBE_EIMS_GPI_SDP0;
1898         if (adapter->flags & IXGBE_FLAG_FAN_FAIL_CAPABLE)
1899                 mask |= IXGBE_EIMS_GPI_SDP1;
1900         switch (adapter->hw.mac.type) {
1901         case ixgbe_mac_82599EB:
1902         case ixgbe_mac_X540:
1903                 mask |= IXGBE_EIMS_ECC;
1904                 mask |= IXGBE_EIMS_GPI_SDP1;
1905                 mask |= IXGBE_EIMS_GPI_SDP2;
1906                 mask |= IXGBE_EIMS_MAILBOX;
1907                 break;
1908         default:
1909                 break;
1910         }
1911         if ((adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE) &&
1912             !(adapter->flags2 & IXGBE_FLAG2_FDIR_REQUIRES_REINIT))
1913                 mask |= IXGBE_EIMS_FLOW_DIR;
1914
1915         IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMS, mask);
1916         if (queues)
1917                 ixgbe_irq_enable_queues(adapter, ~0);
1918         if (flush)
1919                 IXGBE_WRITE_FLUSH(&adapter->hw);
1920 }
1921
1922 static irqreturn_t ixgbe_msix_other(int irq, void *data)
1923 {
1924         struct ixgbe_adapter *adapter = data;
1925         struct ixgbe_hw *hw = &adapter->hw;
1926         u32 eicr;
1927
1928         /*
1929          * Workaround for Silicon errata.  Use clear-by-write instead
1930          * of clear-by-read.  Reading with EICS will return the
1931          * interrupt causes without clearing, which later be done
1932          * with the write to EICR.
1933          */
1934         eicr = IXGBE_READ_REG(hw, IXGBE_EICS);
1935         IXGBE_WRITE_REG(hw, IXGBE_EICR, eicr);
1936
1937         if (eicr & IXGBE_EICR_LSC)
1938                 ixgbe_check_lsc(adapter);
1939
1940         if (eicr & IXGBE_EICR_MAILBOX)
1941                 ixgbe_msg_task(adapter);
1942
1943         switch (hw->mac.type) {
1944         case ixgbe_mac_82599EB:
1945         case ixgbe_mac_X540:
1946                 if (eicr & IXGBE_EICR_ECC)
1947                         e_info(link, "Received unrecoverable ECC Err, please "
1948                                "reboot\n");
1949                 /* Handle Flow Director Full threshold interrupt */
1950                 if (eicr & IXGBE_EICR_FLOW_DIR) {
1951                         int reinit_count = 0;
1952                         int i;
1953                         for (i = 0; i < adapter->num_tx_queues; i++) {
1954                                 struct ixgbe_ring *ring = adapter->tx_ring[i];
1955                                 if (test_and_clear_bit(__IXGBE_TX_FDIR_INIT_DONE,
1956                                                        &ring->state))
1957                                         reinit_count++;
1958                         }
1959                         if (reinit_count) {
1960                                 /* no more flow director interrupts until after init */
1961                                 IXGBE_WRITE_REG(hw, IXGBE_EIMC, IXGBE_EIMC_FLOW_DIR);
1962                                 adapter->flags2 |= IXGBE_FLAG2_FDIR_REQUIRES_REINIT;
1963                                 ixgbe_service_event_schedule(adapter);
1964                         }
1965                 }
1966                 ixgbe_check_sfp_event(adapter, eicr);
1967                 if ((adapter->flags2 & IXGBE_FLAG2_TEMP_SENSOR_CAPABLE) &&
1968                     ((eicr & IXGBE_EICR_GPI_SDP0) || (eicr & IXGBE_EICR_LSC))) {
1969                         if (!test_bit(__IXGBE_DOWN, &adapter->state)) {
1970                                 adapter->interrupt_event = eicr;
1971                                 adapter->flags2 |= IXGBE_FLAG2_TEMP_SENSOR_EVENT;
1972                                 ixgbe_service_event_schedule(adapter);
1973                         }
1974                 }
1975                 break;
1976         default:
1977                 break;
1978         }
1979
1980         ixgbe_check_fan_failure(adapter, eicr);
1981
1982         /* re-enable the original interrupt state, no lsc, no queues */
1983         if (!test_bit(__IXGBE_DOWN, &adapter->state))
1984                 ixgbe_irq_enable(adapter, false, false);
1985
1986         return IRQ_HANDLED;
1987 }
1988
1989 static irqreturn_t ixgbe_msix_clean_rings(int irq, void *data)
1990 {
1991         struct ixgbe_q_vector *q_vector = data;
1992
1993         /* EIAM disabled interrupts (on this vector) for us */
1994
1995         if (q_vector->rx.ring || q_vector->tx.ring)
1996                 napi_schedule(&q_vector->napi);
1997
1998         return IRQ_HANDLED;
1999 }
2000
2001 static inline void map_vector_to_rxq(struct ixgbe_adapter *a, int v_idx,
2002                                      int r_idx)
2003 {
2004         struct ixgbe_q_vector *q_vector = a->q_vector[v_idx];
2005         struct ixgbe_ring *rx_ring = a->rx_ring[r_idx];
2006
2007         rx_ring->q_vector = q_vector;
2008         rx_ring->next = q_vector->rx.ring;
2009         q_vector->rx.ring = rx_ring;
2010         q_vector->rx.count++;
2011 }
2012
2013 static inline void map_vector_to_txq(struct ixgbe_adapter *a, int v_idx,
2014                                      int t_idx)
2015 {
2016         struct ixgbe_q_vector *q_vector = a->q_vector[v_idx];
2017         struct ixgbe_ring *tx_ring = a->tx_ring[t_idx];
2018
2019         tx_ring->q_vector = q_vector;
2020         tx_ring->next = q_vector->tx.ring;
2021         q_vector->tx.ring = tx_ring;
2022         q_vector->tx.count++;
2023         q_vector->tx.work_limit = a->tx_work_limit;
2024 }
2025
2026 /**
2027  * ixgbe_map_rings_to_vectors - Maps descriptor rings to vectors
2028  * @adapter: board private structure to initialize
2029  *
2030  * This function maps descriptor rings to the queue-specific vectors
2031  * we were allotted through the MSI-X enabling code.  Ideally, we'd have
2032  * one vector per ring/queue, but on a constrained vector budget, we
2033  * group the rings as "efficiently" as possible.  You would add new
2034  * mapping configurations in here.
2035  **/
2036 static void ixgbe_map_rings_to_vectors(struct ixgbe_adapter *adapter)
2037 {
2038         int q_vectors = adapter->num_msix_vectors - NON_Q_VECTORS;
2039         int rxr_remaining = adapter->num_rx_queues, rxr_idx = 0;
2040         int txr_remaining = adapter->num_tx_queues, txr_idx = 0;
2041         int v_start = 0;
2042
2043         /* only one q_vector if MSI-X is disabled. */
2044         if (!(adapter->flags & IXGBE_FLAG_MSIX_ENABLED))
2045                 q_vectors = 1;
2046
2047         /*
2048          * If we don't have enough vectors for a 1-to-1 mapping, we'll have to
2049          * group them so there are multiple queues per vector.
2050          *
2051          * Re-adjusting *qpv takes care of the remainder.
2052          */
2053         for (; v_start < q_vectors && rxr_remaining; v_start++) {
2054                 int rqpv = DIV_ROUND_UP(rxr_remaining, q_vectors - v_start);
2055                 for (; rqpv; rqpv--, rxr_idx++, rxr_remaining--)
2056                         map_vector_to_rxq(adapter, v_start, rxr_idx);
2057         }
2058
2059         /*
2060          * If there are not enough q_vectors for each ring to have it's own
2061          * vector then we must pair up Rx/Tx on a each vector
2062          */
2063         if ((v_start + txr_remaining) > q_vectors)
2064                 v_start = 0;
2065
2066         for (; v_start < q_vectors && txr_remaining; v_start++) {
2067                 int tqpv = DIV_ROUND_UP(txr_remaining, q_vectors - v_start);
2068                 for (; tqpv; tqpv--, txr_idx++, txr_remaining--)
2069                         map_vector_to_txq(adapter, v_start, txr_idx);
2070         }
2071 }
2072
2073 /**
2074  * ixgbe_request_msix_irqs - Initialize MSI-X interrupts
2075  * @adapter: board private structure
2076  *
2077  * ixgbe_request_msix_irqs allocates MSI-X vectors and requests
2078  * interrupts from the kernel.
2079  **/
2080 static int ixgbe_request_msix_irqs(struct ixgbe_adapter *adapter)
2081 {
2082         struct net_device *netdev = adapter->netdev;
2083         int q_vectors = adapter->num_msix_vectors - NON_Q_VECTORS;
2084         int vector, err;
2085         int ri = 0, ti = 0;
2086
2087         for (vector = 0; vector < q_vectors; vector++) {
2088                 struct ixgbe_q_vector *q_vector = adapter->q_vector[vector];
2089                 struct msix_entry *entry = &adapter->msix_entries[vector];
2090
2091                 if (q_vector->tx.ring && q_vector->rx.ring) {
2092                         snprintf(q_vector->name, sizeof(q_vector->name) - 1,
2093                                  "%s-%s-%d", netdev->name, "TxRx", ri++);
2094                         ti++;
2095                 } else if (q_vector->rx.ring) {
2096                         snprintf(q_vector->name, sizeof(q_vector->name) - 1,
2097                                  "%s-%s-%d", netdev->name, "rx", ri++);
2098                 } else if (q_vector->tx.ring) {
2099                         snprintf(q_vector->name, sizeof(q_vector->name) - 1,
2100                                  "%s-%s-%d", netdev->name, "tx", ti++);
2101                 } else {
2102                         /* skip this unused q_vector */
2103                         continue;
2104                 }
2105                 err = request_irq(entry->vector, &ixgbe_msix_clean_rings, 0,
2106                                   q_vector->name, q_vector);
2107                 if (err) {
2108                         e_err(probe, "request_irq failed for MSIX interrupt "
2109                               "Error: %d\n", err);
2110                         goto free_queue_irqs;
2111                 }
2112                 /* If Flow Director is enabled, set interrupt affinity */
2113                 if (adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE) {
2114                         /* assign the mask for this irq */
2115                         irq_set_affinity_hint(entry->vector,
2116                                               q_vector->affinity_mask);
2117                 }
2118         }
2119
2120         err = request_irq(adapter->msix_entries[vector].vector,
2121                           ixgbe_msix_other, 0, netdev->name, adapter);
2122         if (err) {
2123                 e_err(probe, "request_irq for msix_lsc failed: %d\n", err);
2124                 goto free_queue_irqs;
2125         }
2126
2127         return 0;
2128
2129 free_queue_irqs:
2130         while (vector) {
2131                 vector--;
2132                 irq_set_affinity_hint(adapter->msix_entries[vector].vector,
2133                                       NULL);
2134                 free_irq(adapter->msix_entries[vector].vector,
2135                          adapter->q_vector[vector]);
2136         }
2137         adapter->flags &= ~IXGBE_FLAG_MSIX_ENABLED;
2138         pci_disable_msix(adapter->pdev);
2139         kfree(adapter->msix_entries);
2140         adapter->msix_entries = NULL;
2141         return err;
2142 }
2143
2144 /**
2145  * ixgbe_intr - legacy mode Interrupt Handler
2146  * @irq: interrupt number
2147  * @data: pointer to a network interface device structure
2148  **/
2149 static irqreturn_t ixgbe_intr(int irq, void *data)
2150 {
2151         struct ixgbe_adapter *adapter = data;
2152         struct ixgbe_hw *hw = &adapter->hw;
2153         struct ixgbe_q_vector *q_vector = adapter->q_vector[0];
2154         u32 eicr;
2155
2156         /*
2157          * Workaround for silicon errata on 82598.  Mask the interrupts
2158          * before the read of EICR.
2159          */
2160         IXGBE_WRITE_REG(hw, IXGBE_EIMC, IXGBE_IRQ_CLEAR_MASK);
2161
2162         /* for NAPI, using EIAM to auto-mask tx/rx interrupt bits on read
2163          * therefore no explict interrupt disable is necessary */
2164         eicr = IXGBE_READ_REG(hw, IXGBE_EICR);
2165         if (!eicr) {
2166                 /*
2167                  * shared interrupt alert!
2168                  * make sure interrupts are enabled because the read will
2169                  * have disabled interrupts due to EIAM
2170                  * finish the workaround of silicon errata on 82598.  Unmask
2171                  * the interrupt that we masked before the EICR read.
2172                  */
2173                 if (!test_bit(__IXGBE_DOWN, &adapter->state))
2174                         ixgbe_irq_enable(adapter, true, true);
2175                 return IRQ_NONE;        /* Not our interrupt */
2176         }
2177
2178         if (eicr & IXGBE_EICR_LSC)
2179                 ixgbe_check_lsc(adapter);
2180
2181         switch (hw->mac.type) {
2182         case ixgbe_mac_82599EB:
2183                 ixgbe_check_sfp_event(adapter, eicr);
2184                 if ((adapter->flags2 & IXGBE_FLAG2_TEMP_SENSOR_CAPABLE) &&
2185                     ((eicr & IXGBE_EICR_GPI_SDP0) || (eicr & IXGBE_EICR_LSC))) {
2186                         if (!test_bit(__IXGBE_DOWN, &adapter->state)) {
2187                                 adapter->interrupt_event = eicr;
2188                                 adapter->flags2 |= IXGBE_FLAG2_TEMP_SENSOR_EVENT;
2189                                 ixgbe_service_event_schedule(adapter);
2190                         }
2191                 }
2192                 break;
2193         default:
2194                 break;
2195         }
2196
2197         ixgbe_check_fan_failure(adapter, eicr);
2198
2199         if (napi_schedule_prep(&(q_vector->napi))) {
2200                 /* would disable interrupts here but EIAM disabled it */
2201                 __napi_schedule(&(q_vector->napi));
2202         }
2203
2204         /*
2205          * re-enable link(maybe) and non-queue interrupts, no flush.
2206          * ixgbe_poll will re-enable the queue interrupts
2207          */
2208
2209         if (!test_bit(__IXGBE_DOWN, &adapter->state))
2210                 ixgbe_irq_enable(adapter, false, false);
2211
2212         return IRQ_HANDLED;
2213 }
2214
2215 static inline void ixgbe_reset_q_vectors(struct ixgbe_adapter *adapter)
2216 {
2217         int q_vectors = adapter->num_msix_vectors - NON_Q_VECTORS;
2218         int i;
2219
2220         /* legacy and MSI only use one vector */
2221         if (!(adapter->flags & IXGBE_FLAG_MSIX_ENABLED))
2222                 q_vectors = 1;
2223
2224         for (i = 0; i < adapter->num_rx_queues; i++) {
2225                 adapter->rx_ring[i]->q_vector = NULL;
2226                 adapter->rx_ring[i]->next = NULL;
2227         }
2228         for (i = 0; i < adapter->num_tx_queues; i++) {
2229                 adapter->tx_ring[i]->q_vector = NULL;
2230                 adapter->tx_ring[i]->next = NULL;
2231         }
2232
2233         for (i = 0; i < q_vectors; i++) {
2234                 struct ixgbe_q_vector *q_vector = adapter->q_vector[i];
2235                 memset(&q_vector->rx, 0, sizeof(struct ixgbe_ring_container));
2236                 memset(&q_vector->tx, 0, sizeof(struct ixgbe_ring_container));
2237         }
2238 }
2239
2240 /**
2241  * ixgbe_request_irq - initialize interrupts
2242  * @adapter: board private structure
2243  *
2244  * Attempts to configure interrupts using the best available
2245  * capabilities of the hardware and kernel.
2246  **/
2247 static int ixgbe_request_irq(struct ixgbe_adapter *adapter)
2248 {
2249         struct net_device *netdev = adapter->netdev;
2250         int err;
2251
2252         /* map all of the rings to the q_vectors */
2253         ixgbe_map_rings_to_vectors(adapter);
2254
2255         if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED)
2256                 err = ixgbe_request_msix_irqs(adapter);
2257         else if (adapter->flags & IXGBE_FLAG_MSI_ENABLED)
2258                 err = request_irq(adapter->pdev->irq, ixgbe_intr, 0,
2259                                   netdev->name, adapter);
2260         else
2261                 err = request_irq(adapter->pdev->irq, ixgbe_intr, IRQF_SHARED,
2262                                   netdev->name, adapter);
2263
2264         if (err) {
2265                 e_err(probe, "request_irq failed, Error %d\n", err);
2266
2267                 /* place q_vectors and rings back into a known good state */
2268                 ixgbe_reset_q_vectors(adapter);
2269         }
2270
2271         return err;
2272 }
2273
2274 static void ixgbe_free_irq(struct ixgbe_adapter *adapter)
2275 {
2276         if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED) {
2277                 int i, q_vectors;
2278
2279                 q_vectors = adapter->num_msix_vectors;
2280                 i = q_vectors - 1;
2281                 free_irq(adapter->msix_entries[i].vector, adapter);
2282                 i--;
2283
2284                 for (; i >= 0; i--) {
2285                         /* free only the irqs that were actually requested */
2286                         if (!adapter->q_vector[i]->rx.ring &&
2287                             !adapter->q_vector[i]->tx.ring)
2288                                 continue;
2289
2290                         /* clear the affinity_mask in the IRQ descriptor */
2291                         irq_set_affinity_hint(adapter->msix_entries[i].vector,
2292                                               NULL);
2293
2294                         free_irq(adapter->msix_entries[i].vector,
2295                                  adapter->q_vector[i]);
2296                 }
2297         } else {
2298                 free_irq(adapter->pdev->irq, adapter);
2299         }
2300
2301         /* clear q_vector state information */
2302         ixgbe_reset_q_vectors(adapter);
2303 }
2304
2305 /**
2306  * ixgbe_irq_disable - Mask off interrupt generation on the NIC
2307  * @adapter: board private structure
2308  **/
2309 static inline void ixgbe_irq_disable(struct ixgbe_adapter *adapter)
2310 {
2311         switch (adapter->hw.mac.type) {
2312         case ixgbe_mac_82598EB:
2313                 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMC, ~0);
2314                 break;
2315         case ixgbe_mac_82599EB:
2316         case ixgbe_mac_X540:
2317                 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMC, 0xFFFF0000);
2318                 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMC_EX(0), ~0);
2319                 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMC_EX(1), ~0);
2320                 break;
2321         default:
2322                 break;
2323         }
2324         IXGBE_WRITE_FLUSH(&adapter->hw);
2325         if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED) {
2326                 int i;
2327                 for (i = 0; i < adapter->num_msix_vectors; i++)
2328                         synchronize_irq(adapter->msix_entries[i].vector);
2329         } else {
2330                 synchronize_irq(adapter->pdev->irq);
2331         }
2332 }
2333
2334 /**
2335  * ixgbe_configure_msi_and_legacy - Initialize PIN (INTA...) and MSI interrupts
2336  *
2337  **/
2338 static void ixgbe_configure_msi_and_legacy(struct ixgbe_adapter *adapter)
2339 {
2340         struct ixgbe_hw *hw = &adapter->hw;
2341
2342         IXGBE_WRITE_REG(hw, IXGBE_EITR(0),
2343                         EITR_INTS_PER_SEC_TO_REG(adapter->rx_eitr_param));
2344
2345         ixgbe_set_ivar(adapter, 0, 0, 0);
2346         ixgbe_set_ivar(adapter, 1, 0, 0);
2347
2348         e_info(hw, "Legacy interrupt IVAR setup done\n");
2349 }
2350
2351 /**
2352  * ixgbe_configure_tx_ring - Configure 8259x Tx ring after Reset
2353  * @adapter: board private structure
2354  * @ring: structure containing ring specific data
2355  *
2356  * Configure the Tx descriptor ring after a reset.
2357  **/
2358 void ixgbe_configure_tx_ring(struct ixgbe_adapter *adapter,
2359                              struct ixgbe_ring *ring)
2360 {
2361         struct ixgbe_hw *hw = &adapter->hw;
2362         u64 tdba = ring->dma;
2363         int wait_loop = 10;
2364         u32 txdctl = IXGBE_TXDCTL_ENABLE;
2365         u8 reg_idx = ring->reg_idx;
2366
2367         /* disable queue to avoid issues while updating state */
2368         IXGBE_WRITE_REG(hw, IXGBE_TXDCTL(reg_idx), 0);
2369         IXGBE_WRITE_FLUSH(hw);
2370
2371         IXGBE_WRITE_REG(hw, IXGBE_TDBAL(reg_idx),
2372                         (tdba & DMA_BIT_MASK(32)));
2373         IXGBE_WRITE_REG(hw, IXGBE_TDBAH(reg_idx), (tdba >> 32));
2374         IXGBE_WRITE_REG(hw, IXGBE_TDLEN(reg_idx),
2375                         ring->count * sizeof(union ixgbe_adv_tx_desc));
2376         IXGBE_WRITE_REG(hw, IXGBE_TDH(reg_idx), 0);
2377         IXGBE_WRITE_REG(hw, IXGBE_TDT(reg_idx), 0);
2378         ring->tail = hw->hw_addr + IXGBE_TDT(reg_idx);
2379
2380         /*
2381          * set WTHRESH to encourage burst writeback, it should not be set
2382          * higher than 1 when ITR is 0 as it could cause false TX hangs
2383          *
2384          * In order to avoid issues WTHRESH + PTHRESH should always be equal
2385          * to or less than the number of on chip descriptors, which is
2386          * currently 40.
2387          */
2388         if (!adapter->tx_itr_setting || !adapter->rx_itr_setting)
2389                 txdctl |= (1 << 16);    /* WTHRESH = 1 */
2390         else
2391                 txdctl |= (8 << 16);    /* WTHRESH = 8 */
2392
2393         /* PTHRESH=32 is needed to avoid a Tx hang with DFP enabled. */
2394         txdctl |= (1 << 8) |    /* HTHRESH = 1 */
2395                    32;          /* PTHRESH = 32 */
2396
2397         /* reinitialize flowdirector state */
2398         if ((adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE) &&
2399             adapter->atr_sample_rate) {
2400                 ring->atr_sample_rate = adapter->atr_sample_rate;
2401                 ring->atr_count = 0;
2402                 set_bit(__IXGBE_TX_FDIR_INIT_DONE, &ring->state);
2403         } else {
2404                 ring->atr_sample_rate = 0;
2405         }
2406
2407         clear_bit(__IXGBE_HANG_CHECK_ARMED, &ring->state);
2408
2409         /* enable queue */
2410         IXGBE_WRITE_REG(hw, IXGBE_TXDCTL(reg_idx), txdctl);
2411
2412         /* TXDCTL.EN will return 0 on 82598 if link is down, so skip it */
2413         if (hw->mac.type == ixgbe_mac_82598EB &&
2414             !(IXGBE_READ_REG(hw, IXGBE_LINKS) & IXGBE_LINKS_UP))
2415                 return;
2416
2417         /* poll to verify queue is enabled */
2418         do {
2419                 usleep_range(1000, 2000);
2420                 txdctl = IXGBE_READ_REG(hw, IXGBE_TXDCTL(reg_idx));
2421         } while (--wait_loop && !(txdctl & IXGBE_TXDCTL_ENABLE));
2422         if (!wait_loop)
2423                 e_err(drv, "Could not enable Tx Queue %d\n", reg_idx);
2424 }
2425
2426 static void ixgbe_setup_mtqc(struct ixgbe_adapter *adapter)
2427 {
2428         struct ixgbe_hw *hw = &adapter->hw;
2429         u32 rttdcs;
2430         u32 reg;
2431         u8 tcs = netdev_get_num_tc(adapter->netdev);
2432
2433         if (hw->mac.type == ixgbe_mac_82598EB)
2434                 return;
2435
2436         /* disable the arbiter while setting MTQC */
2437         rttdcs = IXGBE_READ_REG(hw, IXGBE_RTTDCS);
2438         rttdcs |= IXGBE_RTTDCS_ARBDIS;
2439         IXGBE_WRITE_REG(hw, IXGBE_RTTDCS, rttdcs);
2440
2441         /* set transmit pool layout */
2442         switch (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED) {
2443         case (IXGBE_FLAG_SRIOV_ENABLED):
2444                 IXGBE_WRITE_REG(hw, IXGBE_MTQC,
2445                                 (IXGBE_MTQC_VT_ENA | IXGBE_MTQC_64VF));
2446                 break;
2447         default:
2448                 if (!tcs)
2449                         reg = IXGBE_MTQC_64Q_1PB;
2450                 else if (tcs <= 4)
2451                         reg = IXGBE_MTQC_RT_ENA | IXGBE_MTQC_4TC_4TQ;
2452                 else
2453                         reg = IXGBE_MTQC_RT_ENA | IXGBE_MTQC_8TC_8TQ;
2454
2455                 IXGBE_WRITE_REG(hw, IXGBE_MTQC, reg);
2456
2457                 /* Enable Security TX Buffer IFG for multiple pb */
2458                 if (tcs) {
2459                         reg = IXGBE_READ_REG(hw, IXGBE_SECTXMINIFG);
2460                         reg |= IXGBE_SECTX_DCB;
2461                         IXGBE_WRITE_REG(hw, IXGBE_SECTXMINIFG, reg);
2462                 }
2463                 break;
2464         }
2465
2466         /* re-enable the arbiter */
2467         rttdcs &= ~IXGBE_RTTDCS_ARBDIS;
2468         IXGBE_WRITE_REG(hw, IXGBE_RTTDCS, rttdcs);
2469 }
2470
2471 /**
2472  * ixgbe_configure_tx - Configure 8259x Transmit Unit after Reset
2473  * @adapter: board private structure
2474  *
2475  * Configure the Tx unit of the MAC after a reset.
2476  **/
2477 static void ixgbe_configure_tx(struct ixgbe_adapter *adapter)
2478 {
2479         struct ixgbe_hw *hw = &adapter->hw;
2480         u32 dmatxctl;
2481         u32 i;
2482
2483         ixgbe_setup_mtqc(adapter);
2484
2485         if (hw->mac.type != ixgbe_mac_82598EB) {
2486                 /* DMATXCTL.EN must be before Tx queues are enabled */
2487                 dmatxctl = IXGBE_READ_REG(hw, IXGBE_DMATXCTL);
2488                 dmatxctl |= IXGBE_DMATXCTL_TE;
2489                 IXGBE_WRITE_REG(hw, IXGBE_DMATXCTL, dmatxctl);
2490         }
2491
2492         /* Setup the HW Tx Head and Tail descriptor pointers */
2493         for (i = 0; i < adapter->num_tx_queues; i++)
2494                 ixgbe_configure_tx_ring(adapter, adapter->tx_ring[i]);
2495 }
2496
2497 #define IXGBE_SRRCTL_BSIZEHDRSIZE_SHIFT 2
2498
2499 static void ixgbe_configure_srrctl(struct ixgbe_adapter *adapter,
2500                                    struct ixgbe_ring *rx_ring)
2501 {
2502         u32 srrctl;
2503         u8 reg_idx = rx_ring->reg_idx;
2504
2505         switch (adapter->hw.mac.type) {
2506         case ixgbe_mac_82598EB: {
2507                 struct ixgbe_ring_feature *feature = adapter->ring_feature;
2508                 const int mask = feature[RING_F_RSS].mask;
2509                 reg_idx = reg_idx & mask;
2510         }
2511                 break;
2512         case ixgbe_mac_82599EB:
2513         case ixgbe_mac_X540:
2514         default:
2515                 break;
2516         }
2517
2518         srrctl = IXGBE_READ_REG(&adapter->hw, IXGBE_SRRCTL(reg_idx));
2519
2520         srrctl &= ~IXGBE_SRRCTL_BSIZEHDR_MASK;
2521         srrctl &= ~IXGBE_SRRCTL_BSIZEPKT_MASK;
2522         if (adapter->num_vfs)
2523                 srrctl |= IXGBE_SRRCTL_DROP_EN;
2524
2525         srrctl |= (IXGBE_RX_HDR_SIZE << IXGBE_SRRCTL_BSIZEHDRSIZE_SHIFT) &
2526                   IXGBE_SRRCTL_BSIZEHDR_MASK;
2527
2528         if (ring_is_ps_enabled(rx_ring)) {
2529 #if (PAGE_SIZE / 2) > IXGBE_MAX_RXBUFFER
2530                 srrctl |= IXGBE_MAX_RXBUFFER >> IXGBE_SRRCTL_BSIZEPKT_SHIFT;
2531 #else
2532                 srrctl |= (PAGE_SIZE / 2) >> IXGBE_SRRCTL_BSIZEPKT_SHIFT;
2533 #endif
2534                 srrctl |= IXGBE_SRRCTL_DESCTYPE_HDR_SPLIT_ALWAYS;
2535         } else {
2536                 srrctl |= ALIGN(rx_ring->rx_buf_len, 1024) >>
2537                           IXGBE_SRRCTL_BSIZEPKT_SHIFT;
2538                 srrctl |= IXGBE_SRRCTL_DESCTYPE_ADV_ONEBUF;
2539         }
2540
2541         IXGBE_WRITE_REG(&adapter->hw, IXGBE_SRRCTL(reg_idx), srrctl);
2542 }
2543
2544 static void ixgbe_setup_mrqc(struct ixgbe_adapter *adapter)
2545 {
2546         struct ixgbe_hw *hw = &adapter->hw;
2547         static const u32 seed[10] = { 0xE291D73D, 0x1805EC6C, 0x2A94B30D,
2548                           0xA54F2BEC, 0xEA49AF7C, 0xE214AD3D, 0xB855AABE,
2549                           0x6A3E67EA, 0x14364D17, 0x3BED200D};
2550         u32 mrqc = 0, reta = 0;
2551         u32 rxcsum;
2552         int i, j;
2553         u8 tcs = netdev_get_num_tc(adapter->netdev);
2554         int maxq = adapter->ring_feature[RING_F_RSS].indices;
2555
2556         if (tcs)
2557                 maxq = min(maxq, adapter->num_tx_queues / tcs);
2558
2559         /* Fill out hash function seeds */
2560         for (i = 0; i < 10; i++)
2561                 IXGBE_WRITE_REG(hw, IXGBE_RSSRK(i), seed[i]);
2562
2563         /* Fill out redirection table */
2564         for (i = 0, j = 0; i < 128; i++, j++) {
2565                 if (j == maxq)
2566                         j = 0;
2567                 /* reta = 4-byte sliding window of
2568                  * 0x00..(indices-1)(indices-1)00..etc. */
2569                 reta = (reta << 8) | (j * 0x11);
2570                 if ((i & 3) == 3)
2571                         IXGBE_WRITE_REG(hw, IXGBE_RETA(i >> 2), reta);
2572         }
2573
2574         /* Disable indicating checksum in descriptor, enables RSS hash */
2575         rxcsum = IXGBE_READ_REG(hw, IXGBE_RXCSUM);
2576         rxcsum |= IXGBE_RXCSUM_PCSD;
2577         IXGBE_WRITE_REG(hw, IXGBE_RXCSUM, rxcsum);
2578
2579         if (adapter->hw.mac.type == ixgbe_mac_82598EB &&
2580             (adapter->flags & IXGBE_FLAG_RSS_ENABLED)) {
2581                 mrqc = IXGBE_MRQC_RSSEN;
2582         } else {
2583                 int mask = adapter->flags & (IXGBE_FLAG_RSS_ENABLED
2584                                              | IXGBE_FLAG_SRIOV_ENABLED);
2585
2586                 switch (mask) {
2587                 case (IXGBE_FLAG_RSS_ENABLED):
2588                         if (!tcs)
2589                                 mrqc = IXGBE_MRQC_RSSEN;
2590                         else if (tcs <= 4)
2591                                 mrqc = IXGBE_MRQC_RTRSS4TCEN;
2592                         else
2593                                 mrqc = IXGBE_MRQC_RTRSS8TCEN;
2594                         break;
2595                 case (IXGBE_FLAG_SRIOV_ENABLED):
2596                         mrqc = IXGBE_MRQC_VMDQEN;
2597                         break;
2598                 default:
2599                         break;
2600                 }
2601         }
2602
2603         /* Perform hash on these packet types */
2604         mrqc |= IXGBE_MRQC_RSS_FIELD_IPV4
2605               | IXGBE_MRQC_RSS_FIELD_IPV4_TCP
2606               | IXGBE_MRQC_RSS_FIELD_IPV6
2607               | IXGBE_MRQC_RSS_FIELD_IPV6_TCP;
2608
2609         IXGBE_WRITE_REG(hw, IXGBE_MRQC, mrqc);
2610 }
2611
2612 /**
2613  * ixgbe_configure_rscctl - enable RSC for the indicated ring
2614  * @adapter:    address of board private structure
2615  * @index:      index of ring to set
2616  **/
2617 static void ixgbe_configure_rscctl(struct ixgbe_adapter *adapter,
2618                                    struct ixgbe_ring *ring)
2619 {
2620         struct ixgbe_hw *hw = &adapter->hw;
2621         u32 rscctrl;
2622         int rx_buf_len;
2623         u8 reg_idx = ring->reg_idx;
2624
2625         if (!ring_is_rsc_enabled(ring))
2626                 return;
2627
2628         rx_buf_len = ring->rx_buf_len;
2629         rscctrl = IXGBE_READ_REG(hw, IXGBE_RSCCTL(reg_idx));
2630         rscctrl |= IXGBE_RSCCTL_RSCEN;
2631         /*
2632          * we must limit the number of descriptors so that the
2633          * total size of max desc * buf_len is not greater
2634          * than 65535
2635          */
2636         if (ring_is_ps_enabled(ring)) {
2637 #if (MAX_SKB_FRAGS > 16)
2638                 rscctrl |= IXGBE_RSCCTL_MAXDESC_16;
2639 #elif (MAX_SKB_FRAGS > 8)
2640                 rscctrl |= IXGBE_RSCCTL_MAXDESC_8;
2641 #elif (MAX_SKB_FRAGS > 4)
2642                 rscctrl |= IXGBE_RSCCTL_MAXDESC_4;
2643 #else
2644                 rscctrl |= IXGBE_RSCCTL_MAXDESC_1;
2645 #endif
2646         } else {
2647                 if (rx_buf_len < IXGBE_RXBUFFER_4K)
2648                         rscctrl |= IXGBE_RSCCTL_MAXDESC_16;
2649                 else if (rx_buf_len < IXGBE_RXBUFFER_8K)
2650                         rscctrl |= IXGBE_RSCCTL_MAXDESC_8;
2651                 else
2652                         rscctrl |= IXGBE_RSCCTL_MAXDESC_4;
2653         }
2654         IXGBE_WRITE_REG(hw, IXGBE_RSCCTL(reg_idx), rscctrl);
2655 }
2656
2657 /**
2658  *  ixgbe_set_uta - Set unicast filter table address
2659  *  @adapter: board private structure
2660  *
2661  *  The unicast table address is a register array of 32-bit registers.
2662  *  The table is meant to be used in a way similar to how the MTA is used
2663  *  however due to certain limitations in the hardware it is necessary to
2664  *  set all the hash bits to 1 and use the VMOLR ROPE bit as a promiscuous
2665  *  enable bit to allow vlan tag stripping when promiscuous mode is enabled
2666  **/
2667 static void ixgbe_set_uta(struct ixgbe_adapter *adapter)
2668 {
2669         struct ixgbe_hw *hw = &adapter->hw;
2670         int i;
2671
2672         /* The UTA table only exists on 82599 hardware and newer */
2673         if (hw->mac.type < ixgbe_mac_82599EB)
2674                 return;
2675
2676         /* we only need to do this if VMDq is enabled */
2677         if (!(adapter->flags & IXGBE_FLAG_SRIOV_ENABLED))
2678                 return;
2679
2680         for (i = 0; i < 128; i++)
2681                 IXGBE_WRITE_REG(hw, IXGBE_UTA(i), ~0);
2682 }
2683
2684 #define IXGBE_MAX_RX_DESC_POLL 10
2685 static void ixgbe_rx_desc_queue_enable(struct ixgbe_adapter *adapter,
2686                                        struct ixgbe_ring *ring)
2687 {
2688         struct ixgbe_hw *hw = &adapter->hw;
2689         int wait_loop = IXGBE_MAX_RX_DESC_POLL;
2690         u32 rxdctl;
2691         u8 reg_idx = ring->reg_idx;
2692
2693         /* RXDCTL.EN will return 0 on 82598 if link is down, so skip it */
2694         if (hw->mac.type == ixgbe_mac_82598EB &&
2695             !(IXGBE_READ_REG(hw, IXGBE_LINKS) & IXGBE_LINKS_UP))
2696                 return;
2697
2698         do {
2699                 usleep_range(1000, 2000);
2700                 rxdctl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(reg_idx));
2701         } while (--wait_loop && !(rxdctl & IXGBE_RXDCTL_ENABLE));
2702
2703         if (!wait_loop) {
2704                 e_err(drv, "RXDCTL.ENABLE on Rx queue %d not set within "
2705                       "the polling period\n", reg_idx);
2706         }
2707 }
2708
2709 void ixgbe_disable_rx_queue(struct ixgbe_adapter *adapter,
2710                             struct ixgbe_ring *ring)
2711 {
2712         struct ixgbe_hw *hw = &adapter->hw;
2713         int wait_loop = IXGBE_MAX_RX_DESC_POLL;
2714         u32 rxdctl;
2715         u8 reg_idx = ring->reg_idx;
2716
2717         rxdctl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(reg_idx));
2718         rxdctl &= ~IXGBE_RXDCTL_ENABLE;
2719
2720         /* write value back with RXDCTL.ENABLE bit cleared */
2721         IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(reg_idx), rxdctl);
2722
2723         if (hw->mac.type == ixgbe_mac_82598EB &&
2724             !(IXGBE_READ_REG(hw, IXGBE_LINKS) & IXGBE_LINKS_UP))
2725                 return;
2726
2727         /* the hardware may take up to 100us to really disable the rx queue */
2728         do {
2729                 udelay(10);
2730                 rxdctl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(reg_idx));
2731         } while (--wait_loop && (rxdctl & IXGBE_RXDCTL_ENABLE));
2732
2733         if (!wait_loop) {
2734                 e_err(drv, "RXDCTL.ENABLE on Rx queue %d not cleared within "
2735                       "the polling period\n", reg_idx);
2736         }
2737 }
2738
2739 void ixgbe_configure_rx_ring(struct ixgbe_adapter *adapter,
2740                              struct ixgbe_ring *ring)
2741 {
2742         struct ixgbe_hw *hw = &adapter->hw;
2743         u64 rdba = ring->dma;
2744         u32 rxdctl;
2745         u8 reg_idx = ring->reg_idx;
2746
2747         /* disable queue to avoid issues while updating state */
2748         rxdctl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(reg_idx));
2749         ixgbe_disable_rx_queue(adapter, ring);
2750
2751         IXGBE_WRITE_REG(hw, IXGBE_RDBAL(reg_idx), (rdba & DMA_BIT_MASK(32)));
2752         IXGBE_WRITE_REG(hw, IXGBE_RDBAH(reg_idx), (rdba >> 32));
2753         IXGBE_WRITE_REG(hw, IXGBE_RDLEN(reg_idx),
2754                         ring->count * sizeof(union ixgbe_adv_rx_desc));
2755         IXGBE_WRITE_REG(hw, IXGBE_RDH(reg_idx), 0);
2756         IXGBE_WRITE_REG(hw, IXGBE_RDT(reg_idx), 0);
2757         ring->tail = hw->hw_addr + IXGBE_RDT(reg_idx);
2758
2759         ixgbe_configure_srrctl(adapter, ring);
2760         ixgbe_configure_rscctl(adapter, ring);
2761
2762         /* If operating in IOV mode set RLPML for X540 */
2763         if ((adapter->flags & IXGBE_FLAG_SRIOV_ENABLED) &&
2764             hw->mac.type == ixgbe_mac_X540) {
2765                 rxdctl &= ~IXGBE_RXDCTL_RLPMLMASK;
2766                 rxdctl |= ((ring->netdev->mtu + ETH_HLEN +
2767                             ETH_FCS_LEN + VLAN_HLEN) | IXGBE_RXDCTL_RLPML_EN);
2768         }
2769
2770         if (hw->mac.type == ixgbe_mac_82598EB) {
2771                 /*
2772                  * enable cache line friendly hardware writes:
2773                  * PTHRESH=32 descriptors (half the internal cache),
2774                  * this also removes ugly rx_no_buffer_count increment
2775                  * HTHRESH=4 descriptors (to minimize latency on fetch)
2776                  * WTHRESH=8 burst writeback up to two cache lines
2777                  */
2778                 rxdctl &= ~0x3FFFFF;
2779                 rxdctl |=  0x080420;
2780         }
2781
2782         /* enable receive descriptor ring */
2783         rxdctl |= IXGBE_RXDCTL_ENABLE;
2784         IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(reg_idx), rxdctl);
2785
2786         ixgbe_rx_desc_queue_enable(adapter, ring);
2787         ixgbe_alloc_rx_buffers(ring, ixgbe_desc_unused(ring));
2788 }
2789
2790 static void ixgbe_setup_psrtype(struct ixgbe_adapter *adapter)
2791 {
2792         struct ixgbe_hw *hw = &adapter->hw;
2793         int p;
2794
2795         /* PSRTYPE must be initialized in non 82598 adapters */
2796         u32 psrtype = IXGBE_PSRTYPE_TCPHDR |
2797                       IXGBE_PSRTYPE_UDPHDR |
2798                       IXGBE_PSRTYPE_IPV4HDR |
2799                       IXGBE_PSRTYPE_L2HDR |
2800                       IXGBE_PSRTYPE_IPV6HDR;
2801
2802         if (hw->mac.type == ixgbe_mac_82598EB)
2803                 return;
2804
2805         if (adapter->flags & IXGBE_FLAG_RSS_ENABLED)
2806                 psrtype |= (adapter->num_rx_queues_per_pool << 29);
2807
2808         for (p = 0; p < adapter->num_rx_pools; p++)
2809                 IXGBE_WRITE_REG(hw, IXGBE_PSRTYPE(adapter->num_vfs + p),
2810                                 psrtype);
2811 }
2812
2813 static void ixgbe_configure_virtualization(struct ixgbe_adapter *adapter)
2814 {
2815         struct ixgbe_hw *hw = &adapter->hw;
2816         u32 gcr_ext;
2817         u32 vt_reg_bits;
2818         u32 reg_offset, vf_shift;
2819         u32 vmdctl;
2820
2821         if (!(adapter->flags & IXGBE_FLAG_SRIOV_ENABLED))
2822                 return;
2823
2824         vmdctl = IXGBE_READ_REG(hw, IXGBE_VT_CTL);
2825         vt_reg_bits = IXGBE_VMD_CTL_VMDQ_EN | IXGBE_VT_CTL_REPLEN;
2826         vt_reg_bits |= (adapter->num_vfs << IXGBE_VT_CTL_POOL_SHIFT);
2827         IXGBE_WRITE_REG(hw, IXGBE_VT_CTL, vmdctl | vt_reg_bits);
2828
2829         vf_shift = adapter->num_vfs % 32;
2830         reg_offset = (adapter->num_vfs > 32) ? 1 : 0;
2831
2832         /* Enable only the PF's pool for Tx/Rx */
2833         IXGBE_WRITE_REG(hw, IXGBE_VFRE(reg_offset), (1 << vf_shift));
2834         IXGBE_WRITE_REG(hw, IXGBE_VFRE(reg_offset ^ 1), 0);
2835         IXGBE_WRITE_REG(hw, IXGBE_VFTE(reg_offset), (1 << vf_shift));
2836         IXGBE_WRITE_REG(hw, IXGBE_VFTE(reg_offset ^ 1), 0);
2837         IXGBE_WRITE_REG(hw, IXGBE_PFDTXGSWC, IXGBE_PFDTXGSWC_VT_LBEN);
2838
2839         /* Map PF MAC address in RAR Entry 0 to first pool following VFs */
2840         hw->mac.ops.set_vmdq(hw, 0, adapter->num_vfs);
2841
2842         /*
2843          * Set up VF register offsets for selected VT Mode,
2844          * i.e. 32 or 64 VFs for SR-IOV
2845          */
2846         gcr_ext = IXGBE_READ_REG(hw, IXGBE_GCR_EXT);
2847         gcr_ext |= IXGBE_GCR_EXT_MSIX_EN;
2848         gcr_ext |= IXGBE_GCR_EXT_VT_MODE_64;
2849         IXGBE_WRITE_REG(hw, IXGBE_GCR_EXT, gcr_ext);
2850
2851         /* enable Tx loopback for VF/PF communication */
2852         IXGBE_WRITE_REG(hw, IXGBE_PFDTXGSWC, IXGBE_PFDTXGSWC_VT_LBEN);
2853         /* Enable MAC Anti-Spoofing */
2854         hw->mac.ops.set_mac_anti_spoofing(hw,
2855                                           (adapter->antispoofing_enabled =
2856                                            (adapter->num_vfs != 0)),
2857                                           adapter->num_vfs);
2858 }
2859
2860 static void ixgbe_set_rx_buffer_len(struct ixgbe_adapter *adapter)
2861 {
2862         struct ixgbe_hw *hw = &adapter->hw;
2863         struct net_device *netdev = adapter->netdev;
2864         int max_frame = netdev->mtu + ETH_HLEN + ETH_FCS_LEN;
2865         int rx_buf_len;
2866         struct ixgbe_ring *rx_ring;
2867         int i;
2868         u32 mhadd, hlreg0;
2869
2870         /* Decide whether to use packet split mode or not */
2871         /* On by default */
2872         adapter->flags |= IXGBE_FLAG_RX_PS_ENABLED;
2873
2874         /* Do not use packet split if we're in SR-IOV Mode */
2875         if (adapter->num_vfs)
2876                 adapter->flags &= ~IXGBE_FLAG_RX_PS_ENABLED;
2877
2878         /* Disable packet split due to 82599 erratum #45 */
2879         if (hw->mac.type == ixgbe_mac_82599EB)
2880                 adapter->flags &= ~IXGBE_FLAG_RX_PS_ENABLED;
2881
2882 #ifdef IXGBE_FCOE
2883         /* adjust max frame to be able to do baby jumbo for FCoE */
2884         if ((adapter->flags & IXGBE_FLAG_FCOE_ENABLED) &&
2885             (max_frame < IXGBE_FCOE_JUMBO_FRAME_SIZE))
2886                 max_frame = IXGBE_FCOE_JUMBO_FRAME_SIZE;
2887
2888 #endif /* IXGBE_FCOE */
2889         mhadd = IXGBE_READ_REG(hw, IXGBE_MHADD);
2890         if (max_frame != (mhadd >> IXGBE_MHADD_MFS_SHIFT)) {
2891                 mhadd &= ~IXGBE_MHADD_MFS_MASK;
2892                 mhadd |= max_frame << IXGBE_MHADD_MFS_SHIFT;
2893
2894                 IXGBE_WRITE_REG(hw, IXGBE_MHADD, mhadd);
2895         }
2896
2897         /* MHADD will allow an extra 4 bytes past for vlan tagged frames */
2898         max_frame += VLAN_HLEN;
2899
2900         /* Set the RX buffer length according to the mode */
2901         if (adapter->flags & IXGBE_FLAG_RX_PS_ENABLED) {
2902                 rx_buf_len = IXGBE_RX_HDR_SIZE;
2903         } else {
2904                 if (!(adapter->flags2 & IXGBE_FLAG2_RSC_ENABLED) &&
2905                     (netdev->mtu <= ETH_DATA_LEN))
2906                         rx_buf_len = MAXIMUM_ETHERNET_VLAN_SIZE;
2907                 /*
2908                  * Make best use of allocation by using all but 1K of a
2909                  * power of 2 allocation that will be used for skb->head.
2910                  */
2911                 else if (max_frame <= IXGBE_RXBUFFER_3K)
2912                         rx_buf_len = IXGBE_RXBUFFER_3K;
2913                 else if (max_frame <= IXGBE_RXBUFFER_7K)
2914                         rx_buf_len = IXGBE_RXBUFFER_7K;
2915                 else if (max_frame <= IXGBE_RXBUFFER_15K)
2916                         rx_buf_len = IXGBE_RXBUFFER_15K;
2917                 else
2918                         rx_buf_len = IXGBE_MAX_RXBUFFER;
2919         }
2920
2921         hlreg0 = IXGBE_READ_REG(hw, IXGBE_HLREG0);
2922         /* set jumbo enable since MHADD.MFS is keeping size locked at max_frame */
2923         hlreg0 |= IXGBE_HLREG0_JUMBOEN;
2924         IXGBE_WRITE_REG(hw, IXGBE_HLREG0, hlreg0);
2925
2926         /*
2927          * Setup the HW Rx Head and Tail Descriptor Pointers and
2928          * the Base and Length of the Rx Descriptor Ring
2929          */
2930         for (i = 0; i < adapter->num_rx_queues; i++) {
2931                 rx_ring = adapter->rx_ring[i];
2932                 rx_ring->rx_buf_len = rx_buf_len;
2933
2934                 if (adapter->flags & IXGBE_FLAG_RX_PS_ENABLED)
2935                         set_ring_ps_enabled(rx_ring);
2936                 else
2937                         clear_ring_ps_enabled(rx_ring);
2938
2939                 if (adapter->flags2 & IXGBE_FLAG2_RSC_ENABLED)
2940                         set_ring_rsc_enabled(rx_ring);
2941                 else
2942                         clear_ring_rsc_enabled(rx_ring);
2943
2944 #ifdef IXGBE_FCOE
2945                 if (netdev->features & NETIF_F_FCOE_MTU) {
2946                         struct ixgbe_ring_feature *f;
2947                         f = &adapter->ring_feature[RING_F_FCOE];
2948                         if ((i >= f->mask) && (i < f->mask + f->indices)) {
2949                                 clear_ring_ps_enabled(rx_ring);
2950                                 if (rx_buf_len < IXGBE_FCOE_JUMBO_FRAME_SIZE)
2951                                         rx_ring->rx_buf_len =
2952                                                 IXGBE_FCOE_JUMBO_FRAME_SIZE;
2953                         } else if (!ring_is_rsc_enabled(rx_ring) &&
2954                                    !ring_is_ps_enabled(rx_ring)) {
2955                                 rx_ring->rx_buf_len =
2956                                                 IXGBE_FCOE_JUMBO_FRAME_SIZE;
2957                         }
2958                 }
2959 #endif /* IXGBE_FCOE */
2960         }
2961 }
2962
2963 static void ixgbe_setup_rdrxctl(struct ixgbe_adapter *adapter)
2964 {
2965         struct ixgbe_hw *hw = &adapter->hw;
2966         u32 rdrxctl = IXGBE_READ_REG(hw, IXGBE_RDRXCTL);
2967
2968         switch (hw->mac.type) {
2969         case ixgbe_mac_82598EB:
2970                 /*
2971                  * For VMDq support of different descriptor types or
2972                  * buffer sizes through the use of multiple SRRCTL
2973                  * registers, RDRXCTL.MVMEN must be set to 1
2974                  *
2975                  * also, the manual doesn't mention it clearly but DCA hints
2976                  * will only use queue 0's tags unless this bit is set.  Side
2977                  * effects of setting this bit are only that SRRCTL must be
2978                  * fully programmed [0..15]
2979                  */
2980                 rdrxctl |= IXGBE_RDRXCTL_MVMEN;
2981                 break;
2982         case ixgbe_mac_82599EB:
2983         case ixgbe_mac_X540:
2984                 /* Disable RSC for ACK packets */
2985                 IXGBE_WRITE_REG(hw, IXGBE_RSCDBU,
2986                    (IXGBE_RSCDBU_RSCACKDIS | IXGBE_READ_REG(hw, IXGBE_RSCDBU)));
2987                 rdrxctl &= ~IXGBE_RDRXCTL_RSCFRSTSIZE;
2988                 /* hardware requires some bits to be set by default */
2989                 rdrxctl |= (IXGBE_RDRXCTL_RSCACKC | IXGBE_RDRXCTL_FCOE_WRFIX);
2990                 rdrxctl |= IXGBE_RDRXCTL_CRCSTRIP;
2991                 break;
2992         default:
2993                 /* We should do nothing since we don't know this hardware */
2994                 return;
2995         }
2996
2997         IXGBE_WRITE_REG(hw, IXGBE_RDRXCTL, rdrxctl);
2998 }
2999
3000 /**
3001  * ixgbe_configure_rx - Configure 8259x Receive Unit after Reset
3002  * @adapter: board private structure
3003  *
3004  * Configure the Rx unit of the MAC after a reset.
3005  **/
3006 static void ixgbe_configure_rx(struct ixgbe_adapter *adapter)
3007 {
3008         struct ixgbe_hw *hw = &adapter->hw;
3009         int i;
3010         u32 rxctrl;
3011
3012         /* disable receives while setting up the descriptors */
3013         rxctrl = IXGBE_READ_REG(hw, IXGBE_RXCTRL);
3014         IXGBE_WRITE_REG(hw, IXGBE_RXCTRL, rxctrl & ~IXGBE_RXCTRL_RXEN);
3015
3016         ixgbe_setup_psrtype(adapter);
3017         ixgbe_setup_rdrxctl(adapter);
3018
3019         /* Program registers for the distribution of queues */
3020         ixgbe_setup_mrqc(adapter);
3021
3022         ixgbe_set_uta(adapter);
3023
3024         /* set_rx_buffer_len must be called before ring initialization */
3025         ixgbe_set_rx_buffer_len(adapter);
3026
3027         /*
3028          * Setup the HW Rx Head and Tail Descriptor Pointers and
3029          * the Base and Length of the Rx Descriptor Ring
3030          */
3031         for (i = 0; i < adapter->num_rx_queues; i++)
3032                 ixgbe_configure_rx_ring(adapter, adapter->rx_ring[i]);
3033
3034         /* disable drop enable for 82598 parts */
3035         if (hw->mac.type == ixgbe_mac_82598EB)
3036                 rxctrl |= IXGBE_RXCTRL_DMBYPS;
3037
3038         /* enable all receives */
3039         rxctrl |= IXGBE_RXCTRL_RXEN;
3040         hw->mac.ops.enable_rx_dma(hw, rxctrl);
3041 }
3042
3043 static void ixgbe_vlan_rx_add_vid(struct net_device *netdev, u16 vid)
3044 {
3045         struct ixgbe_adapter *adapter = netdev_priv(netdev);
3046         struct ixgbe_hw *hw = &adapter->hw;
3047         int pool_ndx = adapter->num_vfs;
3048
3049         /* add VID to filter table */
3050         hw->mac.ops.set_vfta(&adapter->hw, vid, pool_ndx, true);
3051         set_bit(vid, adapter->active_vlans);
3052 }
3053
3054 static void ixgbe_vlan_rx_kill_vid(struct net_device *netdev, u16 vid)
3055 {
3056         struct ixgbe_adapter *adapter = netdev_priv(netdev);
3057         struct ixgbe_hw *hw = &adapter->hw;
3058         int pool_ndx = adapter->num_vfs;
3059
3060         /* remove VID from filter table */
3061         hw->mac.ops.set_vfta(&adapter->hw, vid, pool_ndx, false);
3062         clear_bit(vid, adapter->active_vlans);
3063 }
3064
3065 /**
3066  * ixgbe_vlan_filter_disable - helper to disable hw vlan filtering
3067  * @adapter: driver data
3068  */
3069 static void ixgbe_vlan_filter_disable(struct ixgbe_adapter *adapter)
3070 {
3071         struct ixgbe_hw *hw = &adapter->hw;
3072         u32 vlnctrl;
3073
3074         vlnctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
3075         vlnctrl &= ~(IXGBE_VLNCTRL_VFE | IXGBE_VLNCTRL_CFIEN);
3076         IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, vlnctrl);
3077 }
3078
3079 /**
3080  * ixgbe_vlan_filter_enable - helper to enable hw vlan filtering
3081  * @adapter: driver data
3082  */
3083 static void ixgbe_vlan_filter_enable(struct ixgbe_adapter *adapter)
3084 {
3085         struct ixgbe_hw *hw = &adapter->hw;
3086         u32 vlnctrl;
3087
3088         vlnctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
3089         vlnctrl |= IXGBE_VLNCTRL_VFE;
3090         vlnctrl &= ~IXGBE_VLNCTRL_CFIEN;
3091         IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, vlnctrl);
3092 }
3093
3094 /**
3095  * ixgbe_vlan_strip_disable - helper to disable hw vlan stripping
3096  * @adapter: driver data
3097  */
3098 static void ixgbe_vlan_strip_disable(struct ixgbe_adapter *adapter)
3099 {
3100         struct ixgbe_hw *hw = &adapter->hw;
3101         u32 vlnctrl;
3102         int i, j;
3103
3104         switch (hw->mac.type) {
3105         case ixgbe_mac_82598EB:
3106                 vlnctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
3107                 vlnctrl &= ~IXGBE_VLNCTRL_VME;
3108                 IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, vlnctrl);
3109                 break;
3110         case ixgbe_mac_82599EB:
3111         case ixgbe_mac_X540:
3112                 for (i = 0; i < adapter->num_rx_queues; i++) {
3113                         j = adapter->rx_ring[i]->reg_idx;
3114                         vlnctrl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(j));
3115                         vlnctrl &= ~IXGBE_RXDCTL_VME;
3116                         IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(j), vlnctrl);
3117                 }
3118                 break;
3119         default:
3120                 break;
3121         }
3122 }
3123
3124 /**
3125  * ixgbe_vlan_strip_enable - helper to enable hw vlan stripping
3126  * @adapter: driver data
3127  */
3128 static void ixgbe_vlan_strip_enable(struct ixgbe_adapter *adapter)
3129 {
3130         struct ixgbe_hw *hw = &adapter->hw;
3131         u32 vlnctrl;
3132         int i, j;
3133
3134         switch (hw->mac.type) {
3135         case ixgbe_mac_82598EB:
3136                 vlnctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
3137                 vlnctrl |= IXGBE_VLNCTRL_VME;
3138                 IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, vlnctrl);
3139                 break;
3140         case ixgbe_mac_82599EB:
3141         case ixgbe_mac_X540:
3142                 for (i = 0; i < adapter->num_rx_queues; i++) {
3143                         j = adapter->rx_ring[i]->reg_idx;
3144                         vlnctrl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(j));
3145                         vlnctrl |= IXGBE_RXDCTL_VME;
3146                         IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(j), vlnctrl);
3147                 }
3148                 break;
3149         default:
3150                 break;
3151         }
3152 }
3153
3154 static void ixgbe_restore_vlan(struct ixgbe_adapter *adapter)
3155 {
3156         u16 vid;
3157
3158         ixgbe_vlan_rx_add_vid(adapter->netdev, 0);
3159
3160         for_each_set_bit(vid, adapter->active_vlans, VLAN_N_VID)
3161                 ixgbe_vlan_rx_add_vid(adapter->netdev, vid);
3162 }
3163
3164 /**
3165  * ixgbe_write_uc_addr_list - write unicast addresses to RAR table
3166  * @netdev: network interface device structure
3167  *
3168  * Writes unicast address list to the RAR table.
3169  * Returns: -ENOMEM on failure/insufficient address space
3170  *                0 on no addresses written
3171  *                X on writing X addresses to the RAR table
3172  **/
3173 static int ixgbe_write_uc_addr_list(struct net_device *netdev)
3174 {
3175         struct ixgbe_adapter *adapter = netdev_priv(netdev);
3176         struct ixgbe_hw *hw = &adapter->hw;
3177         unsigned int vfn = adapter->num_vfs;
3178         unsigned int rar_entries = IXGBE_MAX_PF_MACVLANS;
3179         int count = 0;
3180
3181         /* return ENOMEM indicating insufficient memory for addresses */
3182         if (netdev_uc_count(netdev) > rar_entries)
3183                 return -ENOMEM;
3184
3185         if (!netdev_uc_empty(netdev) && rar_entries) {
3186                 struct netdev_hw_addr *ha;
3187                 /* return error if we do not support writing to RAR table */
3188                 if (!hw->mac.ops.set_rar)
3189                         return -ENOMEM;
3190
3191                 netdev_for_each_uc_addr(ha, netdev) {
3192                         if (!rar_entries)
3193                                 break;
3194                         hw->mac.ops.set_rar(hw, rar_entries--, ha->addr,
3195                                             vfn, IXGBE_RAH_AV);
3196                         count++;
3197                 }
3198         }
3199         /* write the addresses in reverse order to avoid write combining */
3200         for (; rar_entries > 0 ; rar_entries--)
3201                 hw->mac.ops.clear_rar(hw, rar_entries);
3202
3203         return count;
3204 }
3205
3206 /**
3207  * ixgbe_set_rx_mode - Unicast, Multicast and Promiscuous mode set
3208  * @netdev: network interface device structure
3209  *
3210  * The set_rx_method entry point is called whenever the unicast/multicast
3211  * address list or the network interface flags are updated.  This routine is
3212  * responsible for configuring the hardware for proper unicast, multicast and
3213  * promiscuous mode.
3214  **/
3215 void ixgbe_set_rx_mode(struct net_device *netdev)
3216 {
3217         struct ixgbe_adapter *adapter = netdev_priv(netdev);
3218         struct ixgbe_hw *hw = &adapter->hw;
3219         u32 fctrl, vmolr = IXGBE_VMOLR_BAM | IXGBE_VMOLR_AUPE;
3220         int count;
3221
3222         /* Check for Promiscuous and All Multicast modes */
3223
3224         fctrl = IXGBE_READ_REG(hw, IXGBE_FCTRL);
3225
3226         /* set all bits that we expect to always be set */
3227         fctrl |= IXGBE_FCTRL_BAM;
3228         fctrl |= IXGBE_FCTRL_DPF; /* discard pause frames when FC enabled */
3229         fctrl |= IXGBE_FCTRL_PMCF;
3230
3231         /* clear the bits we are changing the status of */
3232         fctrl &= ~(IXGBE_FCTRL_UPE | IXGBE_FCTRL_MPE);
3233
3234         if (netdev->flags & IFF_PROMISC) {
3235                 hw->addr_ctrl.user_set_promisc = true;
3236                 fctrl |= (IXGBE_FCTRL_UPE | IXGBE_FCTRL_MPE);
3237                 vmolr |= (IXGBE_VMOLR_ROPE | IXGBE_VMOLR_MPE);
3238                 /* don't hardware filter vlans in promisc mode */
3239                 ixgbe_vlan_filter_disable(adapter);
3240         } else {
3241                 if (netdev->flags & IFF_ALLMULTI) {
3242                         fctrl |= IXGBE_FCTRL_MPE;
3243                         vmolr |= IXGBE_VMOLR_MPE;
3244                 } else {
3245                         /*
3246                          * Write addresses to the MTA, if the attempt fails
3247                          * then we should just turn on promiscuous mode so
3248                          * that we can at least receive multicast traffic
3249                          */
3250                         hw->mac.ops.update_mc_addr_list(hw, netdev);
3251                         vmolr |= IXGBE_VMOLR_ROMPE;
3252                 }
3253                 ixgbe_vlan_filter_enable(adapter);
3254                 hw->addr_ctrl.user_set_promisc = false;
3255                 /*
3256                  * Write addresses to available RAR registers, if there is not
3257                  * sufficient space to store all the addresses then enable
3258                  * unicast promiscuous mode
3259                  */
3260                 count = ixgbe_write_uc_addr_list(netdev);
3261                 if (count < 0) {
3262                         fctrl |= IXGBE_FCTRL_UPE;
3263                         vmolr |= IXGBE_VMOLR_ROPE;
3264                 }
3265         }
3266
3267         if (adapter->num_vfs) {
3268                 ixgbe_restore_vf_multicasts(adapter);
3269                 vmolr |= IXGBE_READ_REG(hw, IXGBE_VMOLR(adapter->num_vfs)) &
3270                          ~(IXGBE_VMOLR_MPE | IXGBE_VMOLR_ROMPE |
3271                            IXGBE_VMOLR_ROPE);
3272                 IXGBE_WRITE_REG(hw, IXGBE_VMOLR(adapter->num_vfs), vmolr);
3273         }
3274
3275         IXGBE_WRITE_REG(hw, IXGBE_FCTRL, fctrl);
3276
3277         if (netdev->features & NETIF_F_HW_VLAN_RX)
3278                 ixgbe_vlan_strip_enable(adapter);
3279         else
3280                 ixgbe_vlan_strip_disable(adapter);
3281 }
3282
3283 static void ixgbe_napi_enable_all(struct ixgbe_adapter *adapter)
3284 {
3285         int q_idx;
3286         struct ixgbe_q_vector *q_vector;
3287         int q_vectors = adapter->num_msix_vectors - NON_Q_VECTORS;
3288
3289         /* legacy and MSI only use one vector */
3290         if (!(adapter->flags & IXGBE_FLAG_MSIX_ENABLED))
3291                 q_vectors = 1;
3292
3293         for (q_idx = 0; q_idx < q_vectors; q_idx++) {
3294                 q_vector = adapter->q_vector[q_idx];
3295                 napi_enable(&q_vector->napi);
3296         }
3297 }
3298
3299 static void ixgbe_napi_disable_all(struct ixgbe_adapter *adapter)
3300 {
3301         int q_idx;
3302         struct ixgbe_q_vector *q_vector;
3303         int q_vectors = adapter->num_msix_vectors - NON_Q_VECTORS;
3304
3305         /* legacy and MSI only use one vector */
3306         if (!(adapter->flags & IXGBE_FLAG_MSIX_ENABLED))
3307                 q_vectors = 1;
3308
3309         for (q_idx = 0; q_idx < q_vectors; q_idx++) {
3310                 q_vector = adapter->q_vector[q_idx];
3311                 napi_disable(&q_vector->napi);
3312         }
3313 }
3314
3315 #ifdef CONFIG_IXGBE_DCB
3316 /*
3317  * ixgbe_configure_dcb - Configure DCB hardware
3318  * @adapter: ixgbe adapter struct
3319  *
3320  * This is called by the driver on open to configure the DCB hardware.
3321  * This is also called by the gennetlink interface when reconfiguring
3322  * the DCB state.
3323  */
3324 static void ixgbe_configure_dcb(struct ixgbe_adapter *adapter)
3325 {
3326         struct ixgbe_hw *hw = &adapter->hw;
3327         int max_frame = adapter->netdev->mtu + ETH_HLEN + ETH_FCS_LEN;
3328
3329         if (!(adapter->flags & IXGBE_FLAG_DCB_ENABLED)) {
3330                 if (hw->mac.type == ixgbe_mac_82598EB)
3331                         netif_set_gso_max_size(adapter->netdev, 65536);
3332                 return;
3333         }
3334
3335         if (hw->mac.type == ixgbe_mac_82598EB)
3336                 netif_set_gso_max_size(adapter->netdev, 32768);
3337
3338
3339         /* Enable VLAN tag insert/strip */
3340         adapter->netdev->features |= NETIF_F_HW_VLAN_RX;
3341
3342         hw->mac.ops.set_vfta(&adapter->hw, 0, 0, true);
3343
3344         /* reconfigure the hardware */
3345         if (adapter->dcbx_cap & DCB_CAP_DCBX_VER_CEE) {
3346 #ifdef IXGBE_FCOE
3347                 if (adapter->netdev->features & NETIF_F_FCOE_MTU)
3348                         max_frame = max(max_frame, IXGBE_FCOE_JUMBO_FRAME_SIZE);
3349 #endif
3350                 ixgbe_dcb_calculate_tc_credits(hw, &adapter->dcb_cfg, max_frame,
3351                                                 DCB_TX_CONFIG);
3352                 ixgbe_dcb_calculate_tc_credits(hw, &adapter->dcb_cfg, max_frame,
3353                                                 DCB_RX_CONFIG);
3354                 ixgbe_dcb_hw_config(hw, &adapter->dcb_cfg);
3355         } else {
3356                 struct net_device *dev = adapter->netdev;
3357
3358                 if (adapter->ixgbe_ieee_ets)
3359                         dev->dcbnl_ops->ieee_setets(dev,
3360                                                     adapter->ixgbe_ieee_ets);
3361                 if (adapter->ixgbe_ieee_pfc)
3362                         dev->dcbnl_ops->ieee_setpfc(dev,
3363                                                     adapter->ixgbe_ieee_pfc);
3364         }
3365
3366         /* Enable RSS Hash per TC */
3367         if (hw->mac.type != ixgbe_mac_82598EB) {
3368                 int i;
3369                 u32 reg = 0;
3370
3371                 for (i = 0; i < MAX_TRAFFIC_CLASS; i++) {
3372                         u8 msb = 0;
3373                         u8 cnt = adapter->netdev->tc_to_txq[i].count;
3374
3375                         while (cnt >>= 1)
3376                                 msb++;
3377
3378                         reg |= msb << IXGBE_RQTC_SHIFT_TC(i);
3379                 }
3380                 IXGBE_WRITE_REG(hw, IXGBE_RQTC, reg);
3381         }
3382 }
3383
3384 #endif
3385
3386 static void ixgbe_configure_pb(struct ixgbe_adapter *adapter)
3387 {
3388         struct ixgbe_hw *hw = &adapter->hw;
3389         int hdrm;
3390         u8 tc = netdev_get_num_tc(adapter->netdev);
3391
3392         if (adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE ||
3393             adapter->flags & IXGBE_FLAG_FDIR_PERFECT_CAPABLE)
3394                 hdrm = 32 << adapter->fdir_pballoc;
3395         else
3396                 hdrm = 0;
3397
3398         hw->mac.ops.set_rxpba(hw, tc, hdrm, PBA_STRATEGY_EQUAL);
3399 }
3400
3401 static void ixgbe_fdir_filter_restore(struct ixgbe_adapter *adapter)
3402 {
3403         struct ixgbe_hw *hw = &adapter->hw;
3404         struct hlist_node *node, *node2;
3405         struct ixgbe_fdir_filter *filter;
3406
3407         spin_lock(&adapter->fdir_perfect_lock);
3408
3409         if (!hlist_empty(&adapter->fdir_filter_list))
3410                 ixgbe_fdir_set_input_mask_82599(hw, &adapter->fdir_mask);
3411
3412         hlist_for_each_entry_safe(filter, node, node2,
3413                                   &adapter->fdir_filter_list, fdir_node) {
3414                 ixgbe_fdir_write_perfect_filter_82599(hw,
3415                                 &filter->filter,
3416                                 filter->sw_idx,
3417                                 (filter->action == IXGBE_FDIR_DROP_QUEUE) ?
3418                                 IXGBE_FDIR_DROP_QUEUE :
3419                                 adapter->rx_ring[filter->action]->reg_idx);
3420         }
3421
3422         spin_unlock(&adapter->fdir_perfect_lock);
3423 }
3424
3425 static void ixgbe_configure(struct ixgbe_adapter *adapter)
3426 {
3427         ixgbe_configure_pb(adapter);
3428 #ifdef CONFIG_IXGBE_DCB
3429         ixgbe_configure_dcb(adapter);
3430 #endif
3431
3432         ixgbe_set_rx_mode(adapter->netdev);
3433         ixgbe_restore_vlan(adapter);
3434
3435 #ifdef IXGBE_FCOE
3436         if (adapter->flags & IXGBE_FLAG_FCOE_ENABLED)
3437                 ixgbe_configure_fcoe(adapter);
3438
3439 #endif /* IXGBE_FCOE */
3440         if (adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE) {
3441                 ixgbe_init_fdir_signature_82599(&adapter->hw,
3442                                                 adapter->fdir_pballoc);
3443         } else if (adapter->flags & IXGBE_FLAG_FDIR_PERFECT_CAPABLE) {
3444                 ixgbe_init_fdir_perfect_82599(&adapter->hw,
3445                                               adapter->fdir_pballoc);
3446                 ixgbe_fdir_filter_restore(adapter);
3447         }
3448
3449         ixgbe_configure_virtualization(adapter);
3450
3451         ixgbe_configure_tx(adapter);
3452         ixgbe_configure_rx(adapter);
3453 }
3454
3455 static inline bool ixgbe_is_sfp(struct ixgbe_hw *hw)
3456 {
3457         switch (hw->phy.type) {
3458         case ixgbe_phy_sfp_avago:
3459         case ixgbe_phy_sfp_ftl:
3460         case ixgbe_phy_sfp_intel:
3461         case ixgbe_phy_sfp_unknown:
3462         case ixgbe_phy_sfp_passive_tyco:
3463         case ixgbe_phy_sfp_passive_unknown:
3464         case ixgbe_phy_sfp_active_unknown:
3465         case ixgbe_phy_sfp_ftl_active:
3466                 return true;
3467         case ixgbe_phy_nl:
3468                 if (hw->mac.type == ixgbe_mac_82598EB)
3469                         return true;
3470         default:
3471                 return false;
3472         }
3473 }
3474
3475 /**
3476  * ixgbe_sfp_link_config - set up SFP+ link
3477  * @adapter: pointer to private adapter struct
3478  **/
3479 static void ixgbe_sfp_link_config(struct ixgbe_adapter *adapter)
3480 {
3481         /*
3482          * We are assuming the worst case scenerio here, and that
3483          * is that an SFP was inserted/removed after the reset
3484          * but before SFP detection was enabled.  As such the best
3485          * solution is to just start searching as soon as we start
3486          */
3487         if (adapter->hw.mac.type == ixgbe_mac_82598EB)
3488                 adapter->flags2 |= IXGBE_FLAG2_SEARCH_FOR_SFP;
3489
3490         adapter->flags2 |= IXGBE_FLAG2_SFP_NEEDS_RESET;
3491 }
3492
3493 /**
3494  * ixgbe_non_sfp_link_config - set up non-SFP+ link
3495  * @hw: pointer to private hardware struct
3496  *
3497  * Returns 0 on success, negative on failure
3498  **/
3499 static int ixgbe_non_sfp_link_config(struct ixgbe_hw *hw)
3500 {
3501         u32 autoneg;
3502         bool negotiation, link_up = false;
3503         u32 ret = IXGBE_ERR_LINK_SETUP;
3504
3505         if (hw->mac.ops.check_link)
3506                 ret = hw->mac.ops.check_link(hw, &autoneg, &link_up, false);
3507
3508         if (ret)
3509                 goto link_cfg_out;
3510
3511         autoneg = hw->phy.autoneg_advertised;
3512         if ((!autoneg) && (hw->mac.ops.get_link_capabilities))
3513                 ret = hw->mac.ops.get_link_capabilities(hw, &autoneg,
3514                                                         &negotiation);
3515         if (ret)
3516                 goto link_cfg_out;
3517
3518         if (hw->mac.ops.setup_link)
3519                 ret = hw->mac.ops.setup_link(hw, autoneg, negotiation, link_up);
3520 link_cfg_out:
3521         return ret;
3522 }
3523
3524 static void ixgbe_setup_gpie(struct ixgbe_adapter *adapter)
3525 {
3526         struct ixgbe_hw *hw = &adapter->hw;
3527         u32 gpie = 0;
3528
3529         if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED) {
3530                 gpie = IXGBE_GPIE_MSIX_MODE | IXGBE_GPIE_PBA_SUPPORT |
3531                        IXGBE_GPIE_OCD;
3532                 gpie |= IXGBE_GPIE_EIAME;
3533                 /*
3534                  * use EIAM to auto-mask when MSI-X interrupt is asserted
3535                  * this saves a register write for every interrupt
3536                  */
3537                 switch (hw->mac.type) {
3538                 case ixgbe_mac_82598EB:
3539                         IXGBE_WRITE_REG(hw, IXGBE_EIAM, IXGBE_EICS_RTX_QUEUE);
3540                         break;
3541                 case ixgbe_mac_82599EB:
3542                 case ixgbe_mac_X540:
3543                 default:
3544                         IXGBE_WRITE_REG(hw, IXGBE_EIAM_EX(0), 0xFFFFFFFF);
3545                         IXGBE_WRITE_REG(hw, IXGBE_EIAM_EX(1), 0xFFFFFFFF);
3546                         break;
3547                 }
3548         } else {
3549                 /* legacy interrupts, use EIAM to auto-mask when reading EICR,
3550                  * specifically only auto mask tx and rx interrupts */
3551                 IXGBE_WRITE_REG(hw, IXGBE_EIAM, IXGBE_EICS_RTX_QUEUE);
3552         }
3553
3554         /* XXX: to interrupt immediately for EICS writes, enable this */
3555         /* gpie |= IXGBE_GPIE_EIMEN; */
3556
3557         if (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED) {
3558                 gpie &= ~IXGBE_GPIE_VTMODE_MASK;
3559                 gpie |= IXGBE_GPIE_VTMODE_64;
3560         }
3561
3562         /* Enable Thermal over heat sensor interrupt */
3563         if (adapter->flags2 & IXGBE_FLAG2_TEMP_SENSOR_CAPABLE)
3564                 gpie |= IXGBE_SDP0_GPIEN;
3565
3566         /* Enable fan failure interrupt */
3567         if (adapter->flags & IXGBE_FLAG_FAN_FAIL_CAPABLE)
3568                 gpie |= IXGBE_SDP1_GPIEN;
3569
3570         if (hw->mac.type == ixgbe_mac_82599EB) {
3571                 gpie |= IXGBE_SDP1_GPIEN;
3572                 gpie |= IXGBE_SDP2_GPIEN;
3573         }
3574
3575         IXGBE_WRITE_REG(hw, IXGBE_GPIE, gpie);
3576 }
3577
3578 static void ixgbe_up_complete(struct ixgbe_adapter *adapter)
3579 {
3580         struct ixgbe_hw *hw = &adapter->hw;
3581         int err;
3582         u32 ctrl_ext;
3583
3584         ixgbe_get_hw_control(adapter);
3585         ixgbe_setup_gpie(adapter);
3586
3587         if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED)
3588                 ixgbe_configure_msix(adapter);
3589         else
3590                 ixgbe_configure_msi_and_legacy(adapter);
3591
3592         /* enable the optics for both mult-speed fiber and 82599 SFP+ fiber */
3593         if (hw->mac.ops.enable_tx_laser &&
3594             ((hw->phy.multispeed_fiber) ||
3595              ((hw->mac.ops.get_media_type(hw) == ixgbe_media_type_fiber) &&
3596               (hw->mac.type == ixgbe_mac_82599EB))))
3597                 hw->mac.ops.enable_tx_laser(hw);
3598
3599         clear_bit(__IXGBE_DOWN, &adapter->state);
3600         ixgbe_napi_enable_all(adapter);
3601
3602         if (ixgbe_is_sfp(hw)) {
3603                 ixgbe_sfp_link_config(adapter);
3604         } else {
3605                 err = ixgbe_non_sfp_link_config(hw);
3606                 if (err)
3607                         e_err(probe, "link_config FAILED %d\n", err);
3608         }
3609
3610         /* clear any pending interrupts, may auto mask */
3611         IXGBE_READ_REG(hw, IXGBE_EICR);
3612         ixgbe_irq_enable(adapter, true, true);
3613
3614         /*
3615          * If this adapter has a fan, check to see if we had a failure
3616          * before we enabled the interrupt.
3617          */
3618         if (adapter->flags & IXGBE_FLAG_FAN_FAIL_CAPABLE) {
3619                 u32 esdp = IXGBE_READ_REG(hw, IXGBE_ESDP);
3620                 if (esdp & IXGBE_ESDP_SDP1)
3621                         e_crit(drv, "Fan has stopped, replace the adapter\n");
3622         }
3623
3624         /* enable transmits */
3625         netif_tx_start_all_queues(adapter->netdev);
3626
3627         /* bring the link up in the watchdog, this could race with our first
3628          * link up interrupt but shouldn't be a problem */
3629         adapter->flags |= IXGBE_FLAG_NEED_LINK_UPDATE;
3630         adapter->link_check_timeout = jiffies;
3631         mod_timer(&adapter->service_timer, jiffies);
3632
3633         /* Set PF Reset Done bit so PF/VF Mail Ops can work */
3634         ctrl_ext = IXGBE_READ_REG(hw, IXGBE_CTRL_EXT);
3635         ctrl_ext |= IXGBE_CTRL_EXT_PFRSTD;
3636         IXGBE_WRITE_REG(hw, IXGBE_CTRL_EXT, ctrl_ext);
3637 }
3638
3639 void ixgbe_reinit_locked(struct ixgbe_adapter *adapter)
3640 {
3641         WARN_ON(in_interrupt());
3642         /* put off any impending NetWatchDogTimeout */
3643         adapter->netdev->trans_start = jiffies;
3644
3645         while (test_and_set_bit(__IXGBE_RESETTING, &adapter->state))
3646                 usleep_range(1000, 2000);
3647         ixgbe_down(adapter);
3648         /*
3649          * If SR-IOV enabled then wait a bit before bringing the adapter
3650          * back up to give the VFs time to respond to the reset.  The
3651          * two second wait is based upon the watchdog timer cycle in
3652          * the VF driver.
3653          */
3654         if (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED)
3655                 msleep(2000);
3656         ixgbe_up(adapter);
3657         clear_bit(__IXGBE_RESETTING, &adapter->state);
3658 }
3659
3660 void ixgbe_up(struct ixgbe_adapter *adapter)
3661 {
3662         /* hardware has been reset, we need to reload some things */
3663         ixgbe_configure(adapter);
3664
3665         ixgbe_up_complete(adapter);
3666 }
3667
3668 void ixgbe_reset(struct ixgbe_adapter *adapter)
3669 {
3670         struct ixgbe_hw *hw = &adapter->hw;
3671         int err;
3672
3673         /* lock SFP init bit to prevent race conditions with the watchdog */
3674         while (test_and_set_bit(__IXGBE_IN_SFP_INIT, &adapter->state))
3675                 usleep_range(1000, 2000);
3676
3677         /* clear all SFP and link config related flags while holding SFP_INIT */
3678         adapter->flags2 &= ~(IXGBE_FLAG2_SEARCH_FOR_SFP |
3679                              IXGBE_FLAG2_SFP_NEEDS_RESET);
3680         adapter->flags &= ~IXGBE_FLAG_NEED_LINK_CONFIG;
3681
3682         err = hw->mac.ops.init_hw(hw);
3683         switch (err) {
3684         case 0:
3685         case IXGBE_ERR_SFP_NOT_PRESENT:
3686         case IXGBE_ERR_SFP_NOT_SUPPORTED:
3687                 break;
3688         case IXGBE_ERR_MASTER_REQUESTS_PENDING:
3689                 e_dev_err("master disable timed out\n");
3690                 break;
3691         case IXGBE_ERR_EEPROM_VERSION:
3692                 /* We are running on a pre-production device, log a warning */
3693                 e_dev_warn("This device is a pre-production adapter/LOM. "
3694                            "Please be aware there may be issuesassociated with "
3695                            "your hardware.  If you are experiencing problems "
3696                            "please contact your Intel or hardware "
3697                            "representative who provided you with this "
3698                            "hardware.\n");
3699                 break;
3700         default:
3701                 e_dev_err("Hardware Error: %d\n", err);
3702         }
3703
3704         clear_bit(__IXGBE_IN_SFP_INIT, &adapter->state);
3705
3706         /* reprogram the RAR[0] in case user changed it. */
3707         hw->mac.ops.set_rar(hw, 0, hw->mac.addr, adapter->num_vfs,
3708                             IXGBE_RAH_AV);
3709 }
3710
3711 /**
3712  * ixgbe_clean_rx_ring - Free Rx Buffers per Queue
3713  * @rx_ring: ring to free buffers from
3714  **/
3715 static void ixgbe_clean_rx_ring(struct ixgbe_ring *rx_ring)
3716 {
3717         struct device *dev = rx_ring->dev;
3718         unsigned long size;
3719         u16 i;
3720
3721         /* ring already cleared, nothing to do */
3722         if (!rx_ring->rx_buffer_info)
3723                 return;
3724
3725         /* Free all the Rx ring sk_buffs */
3726         for (i = 0; i < rx_ring->count; i++) {
3727                 struct ixgbe_rx_buffer *rx_buffer_info;
3728
3729                 rx_buffer_info = &rx_ring->rx_buffer_info[i];
3730                 if (rx_buffer_info->dma) {
3731                         dma_unmap_single(rx_ring->dev, rx_buffer_info->dma,
3732                                          rx_ring->rx_buf_len,
3733                                          DMA_FROM_DEVICE);
3734                         rx_buffer_info->dma = 0;
3735                 }
3736                 if (rx_buffer_info->skb) {
3737                         struct sk_buff *skb = rx_buffer_info->skb;
3738                         rx_buffer_info->skb = NULL;
3739                         do {
3740                                 struct sk_buff *this = skb;
3741                                 if (IXGBE_RSC_CB(this)->delay_unmap) {
3742                                         dma_unmap_single(dev,
3743                                                          IXGBE_RSC_CB(this)->dma,
3744                                                          rx_ring->rx_buf_len,
3745                                                          DMA_FROM_DEVICE);
3746                                         IXGBE_RSC_CB(this)->dma = 0;
3747                                         IXGBE_RSC_CB(skb)->delay_unmap = false;
3748                                 }
3749                                 skb = skb->prev;
3750                                 dev_kfree_skb(this);
3751                         } while (skb);
3752                 }
3753                 if (!rx_buffer_info->page)
3754                         continue;
3755                 if (rx_buffer_info->page_dma) {
3756                         dma_unmap_page(dev, rx_buffer_info->page_dma,
3757                                        PAGE_SIZE / 2, DMA_FROM_DEVICE);
3758                         rx_buffer_info->page_dma = 0;
3759                 }
3760                 put_page(rx_buffer_info->page);
3761                 rx_buffer_info->page = NULL;
3762                 rx_buffer_info->page_offset = 0;
3763         }
3764
3765         size = sizeof(struct ixgbe_rx_buffer) * rx_ring->count;
3766         memset(rx_ring->rx_buffer_info, 0, size);
3767
3768         /* Zero out the descriptor ring */
3769         memset(rx_ring->desc, 0, rx_ring->size);
3770
3771         rx_ring->next_to_clean = 0;
3772         rx_ring->next_to_use = 0;
3773 }
3774
3775 /**
3776  * ixgbe_clean_tx_ring - Free Tx Buffers
3777  * @tx_ring: ring to be cleaned
3778  **/
3779 static void ixgbe_clean_tx_ring(struct ixgbe_ring *tx_ring)
3780 {
3781         struct ixgbe_tx_buffer *tx_buffer_info;
3782         unsigned long size;
3783         u16 i;
3784
3785         /* ring already cleared, nothing to do */
3786         if (!tx_ring->tx_buffer_info)
3787                 return;
3788
3789         /* Free all the Tx ring sk_buffs */
3790         for (i = 0; i < tx_ring->count; i++) {
3791                 tx_buffer_info = &tx_ring->tx_buffer_info[i];
3792                 ixgbe_unmap_and_free_tx_resource(tx_ring, tx_buffer_info);
3793         }
3794
3795         size = sizeof(struct ixgbe_tx_buffer) * tx_ring->count;
3796         memset(tx_ring->tx_buffer_info, 0, size);
3797
3798         /* Zero out the descriptor ring */
3799         memset(tx_ring->desc, 0, tx_ring->size);
3800
3801         tx_ring->next_to_use = 0;
3802         tx_ring->next_to_clean = 0;
3803 }
3804
3805 /**
3806  * ixgbe_clean_all_rx_rings - Free Rx Buffers for all queues
3807  * @adapter: board private structure
3808  **/
3809 static void ixgbe_clean_all_rx_rings(struct ixgbe_adapter *adapter)
3810 {
3811         int i;
3812
3813         for (i = 0; i < adapter->num_rx_queues; i++)
3814                 ixgbe_clean_rx_ring(adapter->rx_ring[i]);
3815 }
3816
3817 /**
3818  * ixgbe_clean_all_tx_rings - Free Tx Buffers for all queues
3819  * @adapter: board private structure
3820  **/
3821 static void ixgbe_clean_all_tx_rings(struct ixgbe_adapter *adapter)
3822 {
3823         int i;
3824
3825         for (i = 0; i < adapter->num_tx_queues; i++)
3826                 ixgbe_clean_tx_ring(adapter->tx_ring[i]);
3827 }
3828
3829 static void ixgbe_fdir_filter_exit(struct ixgbe_adapter *adapter)
3830 {
3831         struct hlist_node *node, *node2;
3832         struct ixgbe_fdir_filter *filter;
3833
3834         spin_lock(&adapter->fdir_perfect_lock);
3835
3836         hlist_for_each_entry_safe(filter, node, node2,
3837                                   &adapter->fdir_filter_list, fdir_node) {
3838                 hlist_del(&filter->fdir_node);
3839                 kfree(filter);
3840         }
3841         adapter->fdir_filter_count = 0;
3842
3843         spin_unlock(&adapter->fdir_perfect_lock);
3844 }
3845
3846 void ixgbe_down(struct ixgbe_adapter *adapter)
3847 {
3848         struct net_device *netdev = adapter->netdev;
3849         struct ixgbe_hw *hw = &adapter->hw;
3850         u32 rxctrl;
3851         int i;
3852
3853         /* signal that we are down to the interrupt handler */
3854         set_bit(__IXGBE_DOWN, &adapter->state);
3855
3856         /* disable receives */
3857         rxctrl = IXGBE_READ_REG(hw, IXGBE_RXCTRL);
3858         IXGBE_WRITE_REG(hw, IXGBE_RXCTRL, rxctrl & ~IXGBE_RXCTRL_RXEN);
3859
3860         /* disable all enabled rx queues */
3861         for (i = 0; i < adapter->num_rx_queues; i++)
3862                 /* this call also flushes the previous write */
3863                 ixgbe_disable_rx_queue(adapter, adapter->rx_ring[i]);
3864
3865         usleep_range(10000, 20000);
3866
3867         netif_tx_stop_all_queues(netdev);
3868
3869         /* call carrier off first to avoid false dev_watchdog timeouts */
3870         netif_carrier_off(netdev);
3871         netif_tx_disable(netdev);
3872
3873         ixgbe_irq_disable(adapter);
3874
3875         ixgbe_napi_disable_all(adapter);
3876
3877         adapter->flags2 &= ~(IXGBE_FLAG2_FDIR_REQUIRES_REINIT |
3878                              IXGBE_FLAG2_RESET_REQUESTED);
3879         adapter->flags &= ~IXGBE_FLAG_NEED_LINK_UPDATE;
3880
3881         del_timer_sync(&adapter->service_timer);
3882
3883         if (adapter->num_vfs) {
3884                 /* Clear EITR Select mapping */
3885                 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EITRSEL, 0);
3886
3887                 /* Mark all the VFs as inactive */
3888                 for (i = 0 ; i < adapter->num_vfs; i++)
3889                         adapter->vfinfo[i].clear_to_send = 0;
3890
3891                 /* ping all the active vfs to let them know we are going down */
3892                 ixgbe_ping_all_vfs(adapter);
3893
3894                 /* Disable all VFTE/VFRE TX/RX */
3895                 ixgbe_disable_tx_rx(adapter);
3896         }
3897
3898         /* disable transmits in the hardware now that interrupts are off */
3899         for (i = 0; i < adapter->num_tx_queues; i++) {
3900                 u8 reg_idx = adapter->tx_ring[i]->reg_idx;
3901                 IXGBE_WRITE_REG(hw, IXGBE_TXDCTL(reg_idx), IXGBE_TXDCTL_SWFLSH);
3902         }
3903
3904         /* Disable the Tx DMA engine on 82599 and X540 */
3905         switch (hw->mac.type) {
3906         case ixgbe_mac_82599EB:
3907         case ixgbe_mac_X540:
3908                 IXGBE_WRITE_REG(hw, IXGBE_DMATXCTL,
3909                                 (IXGBE_READ_REG(hw, IXGBE_DMATXCTL) &
3910                                  ~IXGBE_DMATXCTL_TE));
3911                 break;
3912         default:
3913                 break;
3914         }
3915
3916         if (!pci_channel_offline(adapter->pdev))
3917                 ixgbe_reset(adapter);
3918
3919         /* power down the optics for multispeed fiber and 82599 SFP+ fiber */
3920         if (hw->mac.ops.disable_tx_laser &&
3921             ((hw->phy.multispeed_fiber) ||
3922              ((hw->mac.ops.get_media_type(hw) == ixgbe_media_type_fiber) &&
3923               (hw->mac.type == ixgbe_mac_82599EB))))
3924                 hw->mac.ops.disable_tx_laser(hw);
3925
3926         ixgbe_clean_all_tx_rings(adapter);
3927         ixgbe_clean_all_rx_rings(adapter);
3928
3929 #ifdef CONFIG_IXGBE_DCA
3930         /* since we reset the hardware DCA settings were cleared */
3931         ixgbe_setup_dca(adapter);
3932 #endif
3933 }
3934
3935 /**
3936  * ixgbe_poll - NAPI Rx polling callback
3937  * @napi: structure for representing this polling device
3938  * @budget: how many packets driver is allowed to clean
3939  *
3940  * This function is used for legacy and MSI, NAPI mode
3941  **/
3942 static int ixgbe_poll(struct napi_struct *napi, int budget)
3943 {
3944         struct ixgbe_q_vector *q_vector =
3945                                 container_of(napi, struct ixgbe_q_vector, napi);
3946         struct ixgbe_adapter *adapter = q_vector->adapter;
3947         struct ixgbe_ring *ring;
3948         int per_ring_budget;
3949         bool clean_complete = true;
3950
3951 #ifdef CONFIG_IXGBE_DCA
3952         if (adapter->flags & IXGBE_FLAG_DCA_ENABLED)
3953                 ixgbe_update_dca(q_vector);
3954 #endif
3955
3956         for (ring = q_vector->tx.ring; ring != NULL; ring = ring->next)
3957                 clean_complete &= !!ixgbe_clean_tx_irq(q_vector, ring);
3958
3959         /* attempt to distribute budget to each queue fairly, but don't allow
3960          * the budget to go below 1 because we'll exit polling */
3961         if (q_vector->rx.count > 1)
3962                 per_ring_budget = max(budget/q_vector->rx.count, 1);
3963         else
3964                 per_ring_budget = budget;
3965
3966         for (ring = q_vector->rx.ring; ring != NULL; ring = ring->next)
3967                 clean_complete &= ixgbe_clean_rx_irq(q_vector, ring,
3968                                                      per_ring_budget);
3969
3970         /* If all work not completed, return budget and keep polling */
3971         if (!clean_complete)
3972                 return budget;
3973
3974         /* all work done, exit the polling mode */
3975         napi_complete(napi);
3976         if (adapter->rx_itr_setting & 1)
3977                 ixgbe_set_itr(q_vector);
3978         if (!test_bit(__IXGBE_DOWN, &adapter->state))
3979                 ixgbe_irq_enable_queues(adapter, ((u64)1 << q_vector->v_idx));
3980
3981         return 0;
3982 }
3983
3984 /**
3985  * ixgbe_tx_timeout - Respond to a Tx Hang
3986  * @netdev: network interface device structure
3987  **/
3988 static void ixgbe_tx_timeout(struct net_device *netdev)
3989 {
3990         struct ixgbe_adapter *adapter = netdev_priv(netdev);
3991
3992         /* Do the reset outside of interrupt context */
3993         ixgbe_tx_timeout_reset(adapter);
3994 }
3995
3996 /**
3997  * ixgbe_set_rss_queues: Allocate queues for RSS
3998  * @adapter: board private structure to initialize
3999  *
4000  * This is our "base" multiqueue mode.  RSS (Receive Side Scaling) will try
4001  * to allocate one Rx queue per CPU, and if available, one Tx queue per CPU.
4002  *
4003  **/
4004 static inline bool ixgbe_set_rss_queues(struct ixgbe_adapter *adapter)
4005 {
4006         bool ret = false;
4007         struct ixgbe_ring_feature *f = &adapter->ring_feature[RING_F_RSS];
4008
4009         if (adapter->flags & IXGBE_FLAG_RSS_ENABLED) {
4010                 f->mask = 0xF;
4011                 adapter->num_rx_queues = f->indices;
4012                 adapter->num_tx_queues = f->indices;
4013                 ret = true;
4014         } else {
4015                 ret = false;
4016         }
4017
4018         return ret;
4019 }
4020
4021 /**
4022  * ixgbe_set_fdir_queues: Allocate queues for Flow Director
4023  * @adapter: board private structure to initialize
4024  *
4025  * Flow Director is an advanced Rx filter, attempting to get Rx flows back
4026  * to the original CPU that initiated the Tx session.  This runs in addition
4027  * to RSS, so if a packet doesn't match an FDIR filter, we can still spread the
4028  * Rx load across CPUs using RSS.
4029  *
4030  **/
4031 static inline bool ixgbe_set_fdir_queues(struct ixgbe_adapter *adapter)
4032 {
4033         bool ret = false;
4034         struct ixgbe_ring_feature *f_fdir = &adapter->ring_feature[RING_F_FDIR];
4035
4036         f_fdir->indices = min((int)num_online_cpus(), f_fdir->indices);
4037         f_fdir->mask = 0;
4038
4039         /* Flow Director must have RSS enabled */
4040         if ((adapter->flags & IXGBE_FLAG_RSS_ENABLED) &&
4041             (adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE)) {
4042                 adapter->num_tx_queues = f_fdir->indices;
4043                 adapter->num_rx_queues = f_fdir->indices;
4044                 ret = true;
4045         } else {
4046                 adapter->flags &= ~IXGBE_FLAG_FDIR_HASH_CAPABLE;
4047         }
4048         return ret;
4049 }
4050
4051 #ifdef IXGBE_FCOE
4052 /**
4053  * ixgbe_set_fcoe_queues: Allocate queues for Fiber Channel over Ethernet (FCoE)
4054  * @adapter: board private structure to initialize
4055  *
4056  * FCoE RX FCRETA can use up to 8 rx queues for up to 8 different exchanges.
4057  * The ring feature mask is not used as a mask for FCoE, as it can take any 8
4058  * rx queues out of the max number of rx queues, instead, it is used as the
4059  * index of the first rx queue used by FCoE.
4060  *
4061  **/
4062 static inline bool ixgbe_set_fcoe_queues(struct ixgbe_adapter *adapter)
4063 {
4064         struct ixgbe_ring_feature *f = &adapter->ring_feature[RING_F_FCOE];
4065
4066         if (!(adapter->flags & IXGBE_FLAG_FCOE_ENABLED))
4067                 return false;
4068
4069         f->indices = min((int)num_online_cpus(), f->indices);
4070
4071         adapter->num_rx_queues = 1;
4072         adapter->num_tx_queues = 1;
4073
4074         if (adapter->flags & IXGBE_FLAG_RSS_ENABLED) {
4075                 e_info(probe, "FCoE enabled with RSS\n");
4076                 if (adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE)
4077                         ixgbe_set_fdir_queues(adapter);
4078                 else
4079                         ixgbe_set_rss_queues(adapter);
4080         }
4081
4082         /* adding FCoE rx rings to the end */
4083         f->mask = adapter->num_rx_queues;
4084         adapter->num_rx_queues += f->indices;
4085         adapter->num_tx_queues += f->indices;
4086
4087         return true;
4088 }
4089 #endif /* IXGBE_FCOE */
4090
4091 /* Artificial max queue cap per traffic class in DCB mode */
4092 #define DCB_QUEUE_CAP 8
4093
4094 #ifdef CONFIG_IXGBE_DCB
4095 static inline bool ixgbe_set_dcb_queues(struct ixgbe_adapter *adapter)
4096 {
4097         int per_tc_q, q, i, offset = 0;
4098         struct net_device *dev = adapter->netdev;
4099         int tcs = netdev_get_num_tc(dev);
4100
4101         if (!tcs)
4102                 return false;
4103
4104         /* Map queue offset and counts onto allocated tx queues */
4105         per_tc_q = min(dev->num_tx_queues / tcs, (unsigned int)DCB_QUEUE_CAP);
4106         q = min((int)num_online_cpus(), per_tc_q);
4107
4108         for (i = 0; i < tcs; i++) {
4109                 netdev_set_prio_tc_map(dev, i, i);
4110                 netdev_set_tc_queue(dev, i, q, offset);
4111                 offset += q;
4112         }
4113
4114         adapter->num_tx_queues = q * tcs;
4115         adapter->num_rx_queues = q * tcs;
4116
4117 #ifdef IXGBE_FCOE
4118         /* FCoE enabled queues require special configuration indexed
4119          * by feature specific indices and mask. Here we map FCoE
4120          * indices onto the DCB queue pairs allowing FCoE to own
4121          * configuration later.
4122          */
4123         if (adapter->flags & IXGBE_FLAG_FCOE_ENABLED) {
4124                 int tc;
4125                 struct ixgbe_ring_feature *f =
4126                                         &adapter->ring_feature[RING_F_FCOE];
4127
4128                 tc = netdev_get_prio_tc_map(dev, adapter->fcoe.up);
4129                 f->indices = dev->tc_to_txq[tc].count;
4130                 f->mask = dev->tc_to_txq[tc].offset;
4131         }
4132 #endif
4133
4134         return true;
4135 }
4136 #endif
4137
4138 /**
4139  * ixgbe_set_sriov_queues: Allocate queues for IOV use
4140  * @adapter: board private structure to initialize
4141  *
4142  * IOV doesn't actually use anything, so just NAK the
4143  * request for now and let the other queue routines
4144  * figure out what to do.
4145  */
4146 static inline bool ixgbe_set_sriov_queues(struct ixgbe_adapter *adapter)
4147 {
4148         return false;
4149 }
4150
4151 /*
4152  * ixgbe_set_num_queues: Allocate queues for device, feature dependent
4153  * @adapter: board private structure to initialize
4154  *
4155  * This is the top level queue allocation routine.  The order here is very
4156  * important, starting with the "most" number of features turned on at once,
4157  * and ending with the smallest set of features.  This way large combinations
4158  * can be allocated if they're turned on, and smaller combinations are the
4159  * fallthrough conditions.
4160  *
4161  **/
4162 static int ixgbe_set_num_queues(struct ixgbe_adapter *adapter)
4163 {
4164         /* Start with base case */
4165         adapter->num_rx_queues = 1;
4166         adapter->num_tx_queues = 1;
4167         adapter->num_rx_pools = adapter->num_rx_queues;
4168         adapter->num_rx_queues_per_pool = 1;
4169
4170         if (ixgbe_set_sriov_queues(adapter))
4171                 goto done;
4172
4173 #ifdef CONFIG_IXGBE_DCB
4174         if (ixgbe_set_dcb_queues(adapter))
4175                 goto done;
4176
4177 #endif
4178 #ifdef IXGBE_FCOE
4179         if (ixgbe_set_fcoe_queues(adapter))
4180                 goto done;
4181
4182 #endif /* IXGBE_FCOE */
4183         if (ixgbe_set_fdir_queues(adapter))
4184                 goto done;
4185
4186         if (ixgbe_set_rss_queues(adapter))
4187                 goto done;
4188
4189         /* fallback to base case */
4190         adapter->num_rx_queues = 1;
4191         adapter->num_tx_queues = 1;
4192
4193 done:
4194         /* Notify the stack of the (possibly) reduced queue counts. */
4195         netif_set_real_num_tx_queues(adapter->netdev, adapter->num_tx_queues);
4196         return netif_set_real_num_rx_queues(adapter->netdev,
4197                                             adapter->num_rx_queues);
4198 }
4199
4200 static void ixgbe_acquire_msix_vectors(struct ixgbe_adapter *adapter,
4201                                        int vectors)
4202 {
4203         int err, vector_threshold;
4204
4205         /* We'll want at least 3 (vector_threshold):
4206          * 1) TxQ[0] Cleanup
4207          * 2) RxQ[0] Cleanup
4208          * 3) Other (Link Status Change, etc.)
4209          * 4) TCP Timer (optional)
4210          */
4211         vector_threshold = MIN_MSIX_COUNT;
4212
4213         /* The more we get, the more we will assign to Tx/Rx Cleanup
4214          * for the separate queues...where Rx Cleanup >= Tx Cleanup.
4215          * Right now, we simply care about how many we'll get; we'll
4216          * set them up later while requesting irq's.
4217          */
4218         while (vectors >= vector_threshold) {
4219                 err = pci_enable_msix(adapter->pdev, adapter->msix_entries,
4220                                       vectors);
4221                 if (!err) /* Success in acquiring all requested vectors. */
4222                         break;
4223                 else if (err < 0)
4224                         vectors = 0; /* Nasty failure, quit now */
4225                 else /* err == number of vectors we should try again with */
4226                         vectors = err;
4227         }
4228
4229         if (vectors < vector_threshold) {
4230                 /* Can't allocate enough MSI-X interrupts?  Oh well.
4231                  * This just means we'll go with either a single MSI
4232                  * vector or fall back to legacy interrupts.
4233                  */
4234                 netif_printk(adapter, hw, KERN_DEBUG, adapter->netdev,
4235                              "Unable to allocate MSI-X interrupts\n");
4236                 adapter->flags &= ~IXGBE_FLAG_MSIX_ENABLED;
4237                 kfree(adapter->msix_entries);
4238                 adapter->msix_entries = NULL;
4239         } else {
4240                 adapter->flags |= IXGBE_FLAG_MSIX_ENABLED; /* Woot! */
4241                 /*
4242                  * Adjust for only the vectors we'll use, which is minimum
4243                  * of max_msix_q_vectors + NON_Q_VECTORS, or the number of
4244                  * vectors we were allocated.
4245                  */
4246                 adapter->num_msix_vectors = min(vectors,
4247                                    adapter->max_msix_q_vectors + NON_Q_VECTORS);
4248         }
4249 }
4250
4251 /**
4252  * ixgbe_cache_ring_rss - Descriptor ring to register mapping for RSS
4253  * @adapter: board private structure to initialize
4254  *
4255  * Cache the descriptor ring offsets for RSS to the assigned rings.
4256  *
4257  **/
4258 static inline bool ixgbe_cache_ring_rss(struct ixgbe_adapter *adapter)
4259 {
4260         int i;
4261
4262         if (!(adapter->flags & IXGBE_FLAG_RSS_ENABLED))
4263                 return false;
4264
4265         for (i = 0; i < adapter->num_rx_queues; i++)
4266                 adapter->rx_ring[i]->reg_idx = i;
4267         for (i = 0; i < adapter->num_tx_queues; i++)
4268                 adapter->tx_ring[i]->reg_idx = i;
4269
4270         return true;
4271 }
4272
4273 #ifdef CONFIG_IXGBE_DCB
4274
4275 /* ixgbe_get_first_reg_idx - Return first register index associated with ring */
4276 static void ixgbe_get_first_reg_idx(struct ixgbe_adapter *adapter, u8 tc,
4277                                     unsigned int *tx, unsigned int *rx)
4278 {
4279         struct net_device *dev = adapter->netdev;
4280         struct ixgbe_hw *hw = &adapter->hw;
4281         u8 num_tcs = netdev_get_num_tc(dev);
4282
4283         *tx = 0;
4284         *rx = 0;
4285
4286         switch (hw->mac.type) {
4287         case ixgbe_mac_82598EB:
4288                 *tx = tc << 2;
4289                 *rx = tc << 3;
4290                 break;
4291         case ixgbe_mac_82599EB:
4292         case ixgbe_mac_X540:
4293                 if (num_tcs > 4) {
4294                         if (tc < 3) {
4295                                 *tx = tc << 5;
4296                                 *rx = tc << 4;
4297                         } else if (tc <  5) {
4298                                 *tx = ((tc + 2) << 4);
4299                                 *rx = tc << 4;
4300                         } else if (tc < num_tcs) {
4301                                 *tx = ((tc + 8) << 3);
4302                                 *rx = tc << 4;
4303                         }
4304                 } else {
4305                         *rx =  tc << 5;
4306                         switch (tc) {
4307                         case 0:
4308                                 *tx =  0;
4309                                 break;
4310                         case 1:
4311                                 *tx = 64;
4312                                 break;
4313                         case 2:
4314                                 *tx = 96;
4315                                 break;
4316                         case 3:
4317                                 *tx = 112;
4318                                 break;
4319                         default:
4320                                 break;
4321                         }
4322                 }
4323                 break;
4324         default:
4325                 break;
4326         }
4327 }
4328
4329 /**
4330  * ixgbe_cache_ring_dcb - Descriptor ring to register mapping for DCB
4331  * @adapter: board private structure to initialize
4332  *
4333  * Cache the descriptor ring offsets for DCB to the assigned rings.
4334  *
4335  **/
4336 static inline bool ixgbe_cache_ring_dcb(struct ixgbe_adapter *adapter)
4337 {
4338         struct net_device *dev = adapter->netdev;
4339         int i, j, k;
4340         u8 num_tcs = netdev_get_num_tc(dev);
4341
4342         if (!num_tcs)
4343                 return false;
4344
4345         for (i = 0, k = 0; i < num_tcs; i++) {
4346                 unsigned int tx_s, rx_s;
4347                 u16 count = dev->tc_to_txq[i].count;
4348
4349                 ixgbe_get_first_reg_idx(adapter, i, &tx_s, &rx_s);
4350                 for (j = 0; j < count; j++, k++) {
4351                         adapter->tx_ring[k]->reg_idx = tx_s + j;
4352                         adapter->rx_ring[k]->reg_idx = rx_s + j;
4353                         adapter->tx_ring[k]->dcb_tc = i;
4354                         adapter->rx_ring[k]->dcb_tc = i;
4355                 }
4356         }
4357
4358         return true;
4359 }
4360 #endif
4361
4362 /**
4363  * ixgbe_cache_ring_fdir - Descriptor ring to register mapping for Flow Director
4364  * @adapter: board private structure to initialize
4365  *
4366  * Cache the descriptor ring offsets for Flow Director to the assigned rings.
4367  *
4368  **/
4369 static inline bool ixgbe_cache_ring_fdir(struct ixgbe_adapter *adapter)
4370 {
4371         int i;
4372         bool ret = false;
4373
4374         if ((adapter->flags & IXGBE_FLAG_RSS_ENABLED) &&
4375             (adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE)) {
4376                 for (i = 0; i < adapter->num_rx_queues; i++)
4377                         adapter->rx_ring[i]->reg_idx = i;
4378                 for (i = 0; i < adapter->num_tx_queues; i++)
4379                         adapter->tx_ring[i]->reg_idx = i;
4380                 ret = true;
4381         }
4382
4383         return ret;
4384 }
4385
4386 #ifdef IXGBE_FCOE
4387 /**
4388  * ixgbe_cache_ring_fcoe - Descriptor ring to register mapping for the FCoE
4389  * @adapter: board private structure to initialize
4390  *
4391  * Cache the descriptor ring offsets for FCoE mode to the assigned rings.
4392  *
4393  */
4394 static inline bool ixgbe_cache_ring_fcoe(struct ixgbe_adapter *adapter)
4395 {
4396         struct ixgbe_ring_feature *f = &adapter->ring_feature[RING_F_FCOE];
4397         int i;
4398         u8 fcoe_rx_i = 0, fcoe_tx_i = 0;
4399
4400         if (!(adapter->flags & IXGBE_FLAG_FCOE_ENABLED))
4401                 return false;
4402
4403         if (adapter->flags & IXGBE_FLAG_RSS_ENABLED) {
4404                 if (adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE)
4405                         ixgbe_cache_ring_fdir(adapter);
4406                 else
4407                         ixgbe_cache_ring_rss(adapter);
4408
4409                 fcoe_rx_i = f->mask;
4410                 fcoe_tx_i = f->mask;
4411         }
4412         for (i = 0; i < f->indices; i++, fcoe_rx_i++, fcoe_tx_i++) {
4413                 adapter->rx_ring[f->mask + i]->reg_idx = fcoe_rx_i;
4414                 adapter->tx_ring[f->mask + i]->reg_idx = fcoe_tx_i;
4415         }
4416         return true;
4417 }
4418
4419 #endif /* IXGBE_FCOE */
4420 /**
4421  * ixgbe_cache_ring_sriov - Descriptor ring to register mapping for sriov
4422  * @adapter: board private structure to initialize
4423  *
4424  * SR-IOV doesn't use any descriptor rings but changes the default if
4425  * no other mapping is used.
4426  *
4427  */
4428 static inline bool ixgbe_cache_ring_sriov(struct ixgbe_adapter *adapter)
4429 {
4430         adapter->rx_ring[0]->reg_idx = adapter->num_vfs * 2;
4431         adapter->tx_ring[0]->reg_idx = adapter->num_vfs * 2;
4432         if (adapter->num_vfs)
4433                 return true;
4434         else
4435                 return false;
4436 }
4437
4438 /**
4439  * ixgbe_cache_ring_register - Descriptor ring to register mapping
4440  * @adapter: board private structure to initialize
4441  *
4442  * Once we know the feature-set enabled for the device, we'll cache
4443  * the register offset the descriptor ring is assigned to.
4444  *
4445  * Note, the order the various feature calls is important.  It must start with
4446  * the "most" features enabled at the same time, then trickle down to the
4447  * least amount of features turned on at once.
4448  **/
4449 static void ixgbe_cache_ring_register(struct ixgbe_adapter *adapter)
4450 {
4451         /* start with default case */
4452         adapter->rx_ring[0]->reg_idx = 0;
4453         adapter->tx_ring[0]->reg_idx = 0;
4454
4455         if (ixgbe_cache_ring_sriov(adapter))
4456                 return;
4457
4458 #ifdef CONFIG_IXGBE_DCB
4459         if (ixgbe_cache_ring_dcb(adapter))
4460                 return;
4461 #endif
4462
4463 #ifdef IXGBE_FCOE
4464         if (ixgbe_cache_ring_fcoe(adapter))
4465                 return;
4466 #endif /* IXGBE_FCOE */
4467
4468         if (ixgbe_cache_ring_fdir(adapter))
4469                 return;
4470
4471         if (ixgbe_cache_ring_rss(adapter))
4472                 return;
4473 }
4474
4475 /**
4476  * ixgbe_alloc_queues - Allocate memory for all rings
4477  * @adapter: board private structure to initialize
4478  *
4479  * We allocate one ring per queue at run-time since we don't know the
4480  * number of queues at compile-time.  The polling_netdev array is
4481  * intended for Multiqueue, but should work fine with a single queue.
4482  **/
4483 static int ixgbe_alloc_queues(struct ixgbe_adapter *adapter)
4484 {
4485         int rx = 0, tx = 0, nid = adapter->node;
4486
4487         if (nid < 0 || !node_online(nid))
4488                 nid = first_online_node;
4489
4490         for (; tx < adapter->num_tx_queues; tx++) {
4491                 struct ixgbe_ring *ring;
4492
4493                 ring = kzalloc_node(sizeof(*ring), GFP_KERNEL, nid);
4494                 if (!ring)
4495                         ring = kzalloc(sizeof(*ring), GFP_KERNEL);
4496                 if (!ring)
4497                         goto err_allocation;
4498                 ring->count = adapter->tx_ring_count;
4499                 ring->queue_index = tx;
4500                 ring->numa_node = nid;
4501                 ring->dev = &adapter->pdev->dev;
4502                 ring->netdev = adapter->netdev;
4503
4504                 adapter->tx_ring[tx] = ring;
4505         }
4506
4507         for (; rx < adapter->num_rx_queues; rx++) {
4508                 struct ixgbe_ring *ring;
4509
4510                 ring = kzalloc_node(sizeof(*ring), GFP_KERNEL, nid);
4511                 if (!ring)
4512                         ring = kzalloc(sizeof(*ring), GFP_KERNEL);
4513                 if (!ring)
4514                         goto err_allocation;
4515                 ring->count = adapter->rx_ring_count;
4516                 ring->queue_index = rx;
4517                 ring->numa_node = nid;
4518                 ring->dev = &adapter->pdev->dev;
4519                 ring->netdev = adapter->netdev;
4520
4521                 adapter->rx_ring[rx] = ring;
4522         }
4523
4524         ixgbe_cache_ring_register(adapter);
4525
4526         return 0;
4527
4528 err_allocation:
4529         while (tx)
4530                 kfree(adapter->tx_ring[--tx]);
4531
4532         while (rx)
4533                 kfree(adapter->rx_ring[--rx]);
4534         return -ENOMEM;
4535 }
4536
4537 /**
4538  * ixgbe_set_interrupt_capability - set MSI-X or MSI if supported
4539  * @adapter: board private structure to initialize
4540  *
4541  * Attempt to configure the interrupts using the best available
4542  * capabilities of the hardware and the kernel.
4543  **/
4544 static int ixgbe_set_interrupt_capability(struct ixgbe_adapter *adapter)
4545 {
4546         struct ixgbe_hw *hw = &adapter->hw;
4547         int err = 0;
4548         int vector, v_budget;
4549
4550         /*
4551          * It's easy to be greedy for MSI-X vectors, but it really
4552          * doesn't do us much good if we have a lot more vectors
4553          * than CPU's.  So let's be conservative and only ask for
4554          * (roughly) the same number of vectors as there are CPU's.
4555          */
4556         v_budget = min(adapter->num_rx_queues + adapter->num_tx_queues,
4557                        (int)num_online_cpus()) + NON_Q_VECTORS;
4558
4559         /*
4560          * At the same time, hardware can only support a maximum of
4561          * hw.mac->max_msix_vectors vectors.  With features
4562          * such as RSS and VMDq, we can easily surpass the number of Rx and Tx
4563          * descriptor queues supported by our device.  Thus, we cap it off in
4564          * those rare cases where the cpu count also exceeds our vector limit.
4565          */
4566         v_budget = min(v_budget, (int)hw->mac.max_msix_vectors);
4567
4568         /* A failure in MSI-X entry allocation isn't fatal, but it does
4569          * mean we disable MSI-X capabilities of the adapter. */
4570         adapter->msix_entries = kcalloc(v_budget,
4571                                         sizeof(struct msix_entry), GFP_KERNEL);
4572         if (adapter->msix_entries) {
4573                 for (vector = 0; vector < v_budget; vector++)
4574                         adapter->msix_entries[vector].entry = vector;
4575
4576                 ixgbe_acquire_msix_vectors(adapter, v_budget);
4577
4578                 if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED)
4579                         goto out;
4580         }
4581
4582         adapter->flags &= ~IXGBE_FLAG_DCB_ENABLED;
4583         adapter->flags &= ~IXGBE_FLAG_RSS_ENABLED;
4584         if (adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE) {
4585                 e_err(probe,
4586                       "ATR is not supported while multiple "
4587                       "queues are disabled.  Disabling Flow Director\n");
4588         }
4589         adapter->flags &= ~IXGBE_FLAG_FDIR_HASH_CAPABLE;
4590         adapter->atr_sample_rate = 0;
4591         if (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED)
4592                 ixgbe_disable_sriov(adapter);
4593
4594         err = ixgbe_set_num_queues(adapter);
4595         if (err)
4596                 return err;
4597
4598         err = pci_enable_msi(adapter->pdev);
4599         if (!err) {
4600                 adapter->flags |= IXGBE_FLAG_MSI_ENABLED;
4601         } else {
4602                 netif_printk(adapter, hw, KERN_DEBUG, adapter->netdev,
4603                              "Unable to allocate MSI interrupt, "
4604                              "falling back to legacy.  Error: %d\n", err);
4605                 /* reset err */
4606                 err = 0;
4607         }
4608
4609 out:
4610         return err;
4611 }
4612
4613 /**
4614  * ixgbe_alloc_q_vectors - Allocate memory for interrupt vectors
4615  * @adapter: board private structure to initialize
4616  *
4617  * We allocate one q_vector per queue interrupt.  If allocation fails we
4618  * return -ENOMEM.
4619  **/
4620 static int ixgbe_alloc_q_vectors(struct ixgbe_adapter *adapter)
4621 {
4622         int v_idx, num_q_vectors;
4623         struct ixgbe_q_vector *q_vector;
4624
4625         if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED)
4626                 num_q_vectors = adapter->num_msix_vectors - NON_Q_VECTORS;
4627         else
4628                 num_q_vectors = 1;
4629
4630         for (v_idx = 0; v_idx < num_q_vectors; v_idx++) {
4631                 q_vector = kzalloc_node(sizeof(struct ixgbe_q_vector),
4632                                         GFP_KERNEL, adapter->node);
4633                 if (!q_vector)
4634                         q_vector = kzalloc(sizeof(struct ixgbe_q_vector),
4635                                            GFP_KERNEL);
4636                 if (!q_vector)
4637                         goto err_out;
4638
4639                 q_vector->adapter = adapter;
4640                 q_vector->v_idx = v_idx;
4641
4642                 /* Allocate the affinity_hint cpumask, configure the mask */
4643                 if (!alloc_cpumask_var(&q_vector->affinity_mask, GFP_KERNEL))
4644                         goto err_out;
4645                 cpumask_set_cpu(v_idx, q_vector->affinity_mask);
4646
4647                 if (q_vector->tx.count && !q_vector->rx.count)
4648                         q_vector->eitr = adapter->tx_eitr_param;
4649                 else
4650                         q_vector->eitr = adapter->rx_eitr_param;
4651
4652                 netif_napi_add(adapter->netdev, &q_vector->napi,
4653                                ixgbe_poll, 64);
4654                 adapter->q_vector[v_idx] = q_vector;
4655         }
4656
4657         return 0;
4658
4659 err_out:
4660         while (v_idx) {
4661                 v_idx--;
4662                 q_vector = adapter->q_vector[v_idx];
4663                 netif_napi_del(&q_vector->napi);
4664                 free_cpumask_var(q_vector->affinity_mask);
4665                 kfree(q_vector);
4666                 adapter->q_vector[v_idx] = NULL;
4667         }
4668         return -ENOMEM;
4669 }
4670
4671 /**
4672  * ixgbe_free_q_vectors - Free memory allocated for interrupt vectors
4673  * @adapter: board private structure to initialize
4674  *
4675  * This function frees the memory allocated to the q_vectors.  In addition if
4676  * NAPI is enabled it will delete any references to the NAPI struct prior
4677  * to freeing the q_vector.
4678  **/
4679 static void ixgbe_free_q_vectors(struct ixgbe_adapter *adapter)
4680 {
4681         int v_idx, num_q_vectors;
4682
4683         if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED)
4684                 num_q_vectors = adapter->num_msix_vectors - NON_Q_VECTORS;
4685         else
4686                 num_q_vectors = 1;
4687
4688         for (v_idx = 0; v_idx < num_q_vectors; v_idx++) {
4689                 struct ixgbe_q_vector *q_vector = adapter->q_vector[v_idx];
4690                 adapter->q_vector[v_idx] = NULL;
4691                 netif_napi_del(&q_vector->napi);
4692                 free_cpumask_var(q_vector->affinity_mask);
4693                 kfree(q_vector);
4694         }
4695 }
4696
4697 static void ixgbe_reset_interrupt_capability(struct ixgbe_adapter *adapter)
4698 {
4699         if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED) {
4700                 adapter->flags &= ~IXGBE_FLAG_MSIX_ENABLED;
4701                 pci_disable_msix(adapter->pdev);
4702                 kfree(adapter->msix_entries);
4703                 adapter->msix_entries = NULL;
4704         } else if (adapter->flags & IXGBE_FLAG_MSI_ENABLED) {
4705                 adapter->flags &= ~IXGBE_FLAG_MSI_ENABLED;
4706                 pci_disable_msi(adapter->pdev);
4707         }
4708 }
4709
4710 /**
4711  * ixgbe_init_interrupt_scheme - Determine proper interrupt scheme
4712  * @adapter: board private structure to initialize
4713  *
4714  * We determine which interrupt scheme to use based on...
4715  * - Kernel support (MSI, MSI-X)
4716  *   - which can be user-defined (via MODULE_PARAM)
4717  * - Hardware queue count (num_*_queues)
4718  *   - defined by miscellaneous hardware support/features (RSS, etc.)
4719  **/
4720 int ixgbe_init_interrupt_scheme(struct ixgbe_adapter *adapter)
4721 {
4722         int err;
4723
4724         /* Number of supported queues */
4725         err = ixgbe_set_num_queues(adapter);
4726         if (err)
4727                 return err;
4728
4729         err = ixgbe_set_interrupt_capability(adapter);
4730         if (err) {
4731                 e_dev_err("Unable to setup interrupt capabilities\n");
4732                 goto err_set_interrupt;
4733         }
4734
4735         err = ixgbe_alloc_q_vectors(adapter);
4736         if (err) {
4737                 e_dev_err("Unable to allocate memory for queue vectors\n");
4738                 goto err_alloc_q_vectors;
4739         }
4740
4741         err = ixgbe_alloc_queues(adapter);
4742         if (err) {
4743                 e_dev_err("Unable to allocate memory for queues\n");
4744                 goto err_alloc_queues;
4745         }
4746
4747         e_dev_info("Multiqueue %s: Rx Queue count = %u, Tx Queue count = %u\n",
4748                    (adapter->num_rx_queues > 1) ? "Enabled" : "Disabled",
4749                    adapter->num_rx_queues, adapter->num_tx_queues);
4750
4751         set_bit(__IXGBE_DOWN, &adapter->state);
4752
4753         return 0;
4754
4755 err_alloc_queues:
4756         ixgbe_free_q_vectors(adapter);
4757 err_alloc_q_vectors:
4758         ixgbe_reset_interrupt_capability(adapter);
4759 err_set_interrupt:
4760         return err;
4761 }
4762
4763 /**
4764  * ixgbe_clear_interrupt_scheme - Clear the current interrupt scheme settings
4765  * @adapter: board private structure to clear interrupt scheme on
4766  *
4767  * We go through and clear interrupt specific resources and reset the structure
4768  * to pre-load conditions
4769  **/
4770 void ixgbe_clear_interrupt_scheme(struct ixgbe_adapter *adapter)
4771 {
4772         int i;
4773
4774         for (i = 0; i < adapter->num_tx_queues; i++) {
4775                 kfree(adapter->tx_ring[i]);
4776                 adapter->tx_ring[i] = NULL;
4777         }
4778         for (i = 0; i < adapter->num_rx_queues; i++) {
4779                 struct ixgbe_ring *ring = adapter->rx_ring[i];
4780
4781                 /* ixgbe_get_stats64() might access this ring, we must wait
4782                  * a grace period before freeing it.
4783                  */
4784                 kfree_rcu(ring, rcu);
4785                 adapter->rx_ring[i] = NULL;
4786         }
4787
4788         adapter->num_tx_queues = 0;
4789         adapter->num_rx_queues = 0;
4790
4791         ixgbe_free_q_vectors(adapter);
4792         ixgbe_reset_interrupt_capability(adapter);
4793 }
4794
4795 /**
4796  * ixgbe_sw_init - Initialize general software structures (struct ixgbe_adapter)
4797  * @adapter: board private structure to initialize
4798  *
4799  * ixgbe_sw_init initializes the Adapter private data structure.
4800  * Fields are initialized based on PCI device information and
4801  * OS network device settings (MTU size).
4802  **/
4803 static int __devinit ixgbe_sw_init(struct ixgbe_adapter *adapter)
4804 {
4805         struct ixgbe_hw *hw = &adapter->hw;
4806         struct pci_dev *pdev = adapter->pdev;
4807         struct net_device *dev = adapter->netdev;
4808         unsigned int rss;
4809 #ifdef CONFIG_IXGBE_DCB
4810         int j;
4811         struct tc_configuration *tc;
4812 #endif
4813         int max_frame = dev->mtu + ETH_HLEN + ETH_FCS_LEN;
4814
4815         /* PCI config space info */
4816
4817         hw->vendor_id = pdev->vendor;
4818         hw->device_id = pdev->device;
4819         hw->revision_id = pdev->revision;
4820         hw->subsystem_vendor_id = pdev->subsystem_vendor;
4821         hw->subsystem_device_id = pdev->subsystem_device;
4822
4823         /* Set capability flags */
4824         rss = min(IXGBE_MAX_RSS_INDICES, (int)num_online_cpus());
4825         adapter->ring_feature[RING_F_RSS].indices = rss;
4826         adapter->flags |= IXGBE_FLAG_RSS_ENABLED;
4827         switch (hw->mac.type) {
4828         case ixgbe_mac_82598EB:
4829                 if (hw->device_id == IXGBE_DEV_ID_82598AT)
4830                         adapter->flags |= IXGBE_FLAG_FAN_FAIL_CAPABLE;
4831                 adapter->max_msix_q_vectors = MAX_MSIX_Q_VECTORS_82598;
4832                 break;
4833         case ixgbe_mac_82599EB:
4834         case ixgbe_mac_X540:
4835                 adapter->max_msix_q_vectors = MAX_MSIX_Q_VECTORS_82599;
4836                 adapter->flags2 |= IXGBE_FLAG2_RSC_CAPABLE;
4837                 adapter->flags2 |= IXGBE_FLAG2_RSC_ENABLED;
4838                 if (hw->device_id == IXGBE_DEV_ID_82599_T3_LOM)
4839                         adapter->flags2 |= IXGBE_FLAG2_TEMP_SENSOR_CAPABLE;
4840                 /* Flow Director hash filters enabled */
4841                 adapter->flags |= IXGBE_FLAG_FDIR_HASH_CAPABLE;
4842                 adapter->atr_sample_rate = 20;
4843                 adapter->ring_feature[RING_F_FDIR].indices =
4844                                                          IXGBE_MAX_FDIR_INDICES;
4845                 adapter->fdir_pballoc = IXGBE_FDIR_PBALLOC_64K;
4846 #ifdef IXGBE_FCOE
4847                 adapter->flags |= IXGBE_FLAG_FCOE_CAPABLE;
4848                 adapter->flags &= ~IXGBE_FLAG_FCOE_ENABLED;
4849                 adapter->ring_feature[RING_F_FCOE].indices = 0;
4850 #ifdef CONFIG_IXGBE_DCB
4851                 /* Default traffic class to use for FCoE */
4852                 adapter->fcoe.up = IXGBE_FCOE_DEFTC;
4853 #endif
4854 #endif /* IXGBE_FCOE */
4855                 break;
4856         default:
4857                 break;
4858         }
4859
4860         /* n-tuple support exists, always init our spinlock */
4861         spin_lock_init(&adapter->fdir_perfect_lock);
4862
4863 #ifdef CONFIG_IXGBE_DCB
4864         /* Configure DCB traffic classes */
4865         for (j = 0; j < MAX_TRAFFIC_CLASS; j++) {
4866                 tc = &adapter->dcb_cfg.tc_config[j];
4867                 tc->path[DCB_TX_CONFIG].bwg_id = 0;
4868                 tc->path[DCB_TX_CONFIG].bwg_percent = 12 + (j & 1);
4869                 tc->path[DCB_RX_CONFIG].bwg_id = 0;
4870                 tc->path[DCB_RX_CONFIG].bwg_percent = 12 + (j & 1);
4871                 tc->dcb_pfc = pfc_disabled;
4872         }
4873         adapter->dcb_cfg.bw_percentage[DCB_TX_CONFIG][0] = 100;
4874         adapter->dcb_cfg.bw_percentage[DCB_RX_CONFIG][0] = 100;
4875         adapter->dcb_cfg.pfc_mode_enable = false;
4876         adapter->dcb_set_bitmap = 0x00;
4877         adapter->dcbx_cap = DCB_CAP_DCBX_HOST | DCB_CAP_DCBX_VER_CEE;
4878         ixgbe_copy_dcb_cfg(&adapter->dcb_cfg, &adapter->temp_dcb_cfg,
4879                            MAX_TRAFFIC_CLASS);
4880
4881 #endif
4882
4883         /* default flow control settings */
4884         hw->fc.requested_mode = ixgbe_fc_full;
4885         hw->fc.current_mode = ixgbe_fc_full;    /* init for ethtool output */
4886 #ifdef CONFIG_DCB
4887         adapter->last_lfc_mode = hw->fc.current_mode;
4888 #endif
4889         hw->fc.high_water = FC_HIGH_WATER(max_frame);
4890         hw->fc.low_water = FC_LOW_WATER(max_frame);
4891         hw->fc.pause_time = IXGBE_DEFAULT_FCPAUSE;
4892         hw->fc.send_xon = true;
4893         hw->fc.disable_fc_autoneg = false;
4894
4895         /* enable itr by default in dynamic mode */
4896         adapter->rx_itr_setting = 1;
4897         adapter->rx_eitr_param = 20000;
4898         adapter->tx_itr_setting = 1;
4899         adapter->tx_eitr_param = 10000;
4900
4901         /* set defaults for eitr in MegaBytes */
4902         adapter->eitr_low = 10;
4903         adapter->eitr_high = 20;
4904
4905         /* set default ring sizes */
4906         adapter->tx_ring_count = IXGBE_DEFAULT_TXD;
4907         adapter->rx_ring_count = IXGBE_DEFAULT_RXD;
4908
4909         /* set default work limits */
4910         adapter->tx_work_limit = IXGBE_DEFAULT_TX_WORK;
4911
4912         /* initialize eeprom parameters */
4913         if (ixgbe_init_eeprom_params_generic(hw)) {
4914                 e_dev_err("EEPROM initialization failed\n");
4915                 return -EIO;
4916         }
4917
4918         /* enable rx csum by default */
4919         adapter->flags |= IXGBE_FLAG_RX_CSUM_ENABLED;
4920
4921         /* get assigned NUMA node */
4922         adapter->node = dev_to_node(&pdev->dev);
4923
4924         set_bit(__IXGBE_DOWN, &adapter->state);
4925
4926         return 0;
4927 }
4928
4929 /**
4930  * ixgbe_setup_tx_resources - allocate Tx resources (Descriptors)
4931  * @tx_ring:    tx descriptor ring (for a specific queue) to setup
4932  *
4933  * Return 0 on success, negative on failure
4934  **/
4935 int ixgbe_setup_tx_resources(struct ixgbe_ring *tx_ring)
4936 {
4937         struct device *dev = tx_ring->dev;
4938         int size;
4939
4940         size = sizeof(struct ixgbe_tx_buffer) * tx_ring->count;
4941         tx_ring->tx_buffer_info = vzalloc_node(size, tx_ring->numa_node);
4942         if (!tx_ring->tx_buffer_info)
4943                 tx_ring->tx_buffer_info = vzalloc(size);
4944         if (!tx_ring->tx_buffer_info)
4945                 goto err;
4946
4947         /* round up to nearest 4K */
4948         tx_ring->size = tx_ring->count * sizeof(union ixgbe_adv_tx_desc);
4949         tx_ring->size = ALIGN(tx_ring->size, 4096);
4950
4951         tx_ring->desc = dma_alloc_coherent(dev, tx_ring->size,
4952                                            &tx_ring->dma, GFP_KERNEL);
4953         if (!tx_ring->desc)
4954                 goto err;
4955
4956         tx_ring->next_to_use = 0;
4957         tx_ring->next_to_clean = 0;
4958         return 0;
4959
4960 err:
4961         vfree(tx_ring->tx_buffer_info);
4962         tx_ring->tx_buffer_info = NULL;
4963         dev_err(dev, "Unable to allocate memory for the Tx descriptor ring\n");
4964         return -ENOMEM;
4965 }
4966
4967 /**
4968  * ixgbe_setup_all_tx_resources - allocate all queues Tx resources
4969  * @adapter: board private structure
4970  *
4971  * If this function returns with an error, then it's possible one or
4972  * more of the rings is populated (while the rest are not).  It is the
4973  * callers duty to clean those orphaned rings.
4974  *
4975  * Return 0 on success, negative on failure
4976  **/
4977 static int ixgbe_setup_all_tx_resources(struct ixgbe_adapter *adapter)
4978 {
4979         int i, err = 0;
4980
4981         for (i = 0; i < adapter->num_tx_queues; i++) {
4982                 err = ixgbe_setup_tx_resources(adapter->tx_ring[i]);
4983                 if (!err)
4984                         continue;
4985                 e_err(probe, "Allocation for Tx Queue %u failed\n", i);
4986                 break;
4987         }
4988
4989         return err;
4990 }
4991
4992 /**
4993  * ixgbe_setup_rx_resources - allocate Rx resources (Descriptors)
4994  * @rx_ring:    rx descriptor ring (for a specific queue) to setup
4995  *
4996  * Returns 0 on success, negative on failure
4997  **/
4998 int ixgbe_setup_rx_resources(struct ixgbe_ring *rx_ring)
4999 {
5000         struct device *dev = rx_ring->dev;
5001         int size;
5002
5003         size = sizeof(struct ixgbe_rx_buffer) * rx_ring->count;
5004         rx_ring->rx_buffer_info = vzalloc_node(size, rx_ring->numa_node);
5005         if (!rx_ring->rx_buffer_info)
5006                 rx_ring->rx_buffer_info = vzalloc(size);
5007         if (!rx_ring->rx_buffer_info)
5008                 goto err;
5009
5010         /* Round up to nearest 4K */
5011         rx_ring->size = rx_ring->count * sizeof(union ixgbe_adv_rx_desc);
5012         rx_ring->size = ALIGN(rx_ring->size, 4096);
5013
5014         rx_ring->desc = dma_alloc_coherent(dev, rx_ring->size,
5015                                            &rx_ring->dma, GFP_KERNEL);
5016
5017         if (!rx_ring->desc)
5018                 goto err;
5019
5020         rx_ring->next_to_clean = 0;
5021         rx_ring->next_to_use = 0;
5022
5023         return 0;
5024 err:
5025         vfree(rx_ring->rx_buffer_info);
5026         rx_ring->rx_buffer_info = NULL;
5027         dev_err(dev, "Unable to allocate memory for the Rx descriptor ring\n");
5028         return -ENOMEM;
5029 }
5030
5031 /**
5032  * ixgbe_setup_all_rx_resources - allocate all queues Rx resources
5033  * @adapter: board private structure
5034  *
5035  * If this function returns with an error, then it's possible one or
5036  * more of the rings is populated (while the rest are not).  It is the
5037  * callers duty to clean those orphaned rings.
5038  *
5039  * Return 0 on success, negative on failure
5040  **/
5041 static int ixgbe_setup_all_rx_resources(struct ixgbe_adapter *adapter)
5042 {
5043         int i, err = 0;
5044
5045         for (i = 0; i < adapter->num_rx_queues; i++) {
5046                 err = ixgbe_setup_rx_resources(adapter->rx_ring[i]);
5047                 if (!err)
5048                         continue;
5049                 e_err(probe, "Allocation for Rx Queue %u failed\n", i);
5050                 break;
5051         }
5052
5053         return err;
5054 }
5055
5056 /**
5057  * ixgbe_free_tx_resources - Free Tx Resources per Queue
5058  * @tx_ring: Tx descriptor ring for a specific queue
5059  *
5060  * Free all transmit software resources
5061  **/
5062 void ixgbe_free_tx_resources(struct ixgbe_ring *tx_ring)
5063 {
5064         ixgbe_clean_tx_ring(tx_ring);
5065
5066         vfree(tx_ring->tx_buffer_info);
5067         tx_ring->tx_buffer_info = NULL;
5068
5069         /* if not set, then don't free */
5070         if (!tx_ring->desc)
5071                 return;
5072
5073         dma_free_coherent(tx_ring->dev, tx_ring->size,
5074                           tx_ring->desc, tx_ring->dma);
5075
5076         tx_ring->desc = NULL;
5077 }
5078
5079 /**
5080  * ixgbe_free_all_tx_resources - Free Tx Resources for All Queues
5081  * @adapter: board private structure
5082  *
5083  * Free all transmit software resources
5084  **/
5085 static void ixgbe_free_all_tx_resources(struct ixgbe_adapter *adapter)
5086 {
5087         int i;
5088
5089         for (i = 0; i < adapter->num_tx_queues; i++)
5090                 if (adapter->tx_ring[i]->desc)
5091                         ixgbe_free_tx_resources(adapter->tx_ring[i]);
5092 }
5093
5094 /**
5095  * ixgbe_free_rx_resources - Free Rx Resources
5096  * @rx_ring: ring to clean the resources from
5097  *
5098  * Free all receive software resources
5099  **/
5100 void ixgbe_free_rx_resources(struct ixgbe_ring *rx_ring)
5101 {
5102         ixgbe_clean_rx_ring(rx_ring);
5103
5104         vfree(rx_ring->rx_buffer_info);
5105         rx_ring->rx_buffer_info = NULL;
5106
5107         /* if not set, then don't free */
5108         if (!rx_ring->desc)
5109                 return;
5110
5111         dma_free_coherent(rx_ring->dev, rx_ring->size,
5112                           rx_ring->desc, rx_ring->dma);
5113
5114         rx_ring->desc = NULL;
5115 }
5116
5117 /**
5118  * ixgbe_free_all_rx_resources - Free Rx Resources for All Queues
5119  * @adapter: board private structure
5120  *
5121  * Free all receive software resources
5122  **/
5123 static void ixgbe_free_all_rx_resources(struct ixgbe_adapter *adapter)
5124 {
5125         int i;
5126
5127         for (i = 0; i < adapter->num_rx_queues; i++)
5128                 if (adapter->rx_ring[i]->desc)
5129                         ixgbe_free_rx_resources(adapter->rx_ring[i]);
5130 }
5131
5132 /**
5133  * ixgbe_change_mtu - Change the Maximum Transfer Unit
5134  * @netdev: network interface device structure
5135  * @new_mtu: new value for maximum frame size
5136  *
5137  * Returns 0 on success, negative on failure
5138  **/
5139 static int ixgbe_change_mtu(struct net_device *netdev, int new_mtu)
5140 {
5141         struct ixgbe_adapter *adapter = netdev_priv(netdev);
5142         struct ixgbe_hw *hw = &adapter->hw;
5143         int max_frame = new_mtu + ETH_HLEN + ETH_FCS_LEN;
5144
5145         /* MTU < 68 is an error and causes problems on some kernels */
5146         if (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED &&
5147             hw->mac.type != ixgbe_mac_X540) {
5148                 if ((new_mtu < 68) || (max_frame > MAXIMUM_ETHERNET_VLAN_SIZE))
5149                         return -EINVAL;
5150         } else {
5151                 if ((new_mtu < 68) || (max_frame > IXGBE_MAX_JUMBO_FRAME_SIZE))
5152                         return -EINVAL;
5153         }
5154
5155         e_info(probe, "changing MTU from %d to %d\n", netdev->mtu, new_mtu);
5156         /* must set new MTU before calling down or up */
5157         netdev->mtu = new_mtu;
5158
5159         hw->fc.high_water = FC_HIGH_WATER(max_frame);
5160         hw->fc.low_water = FC_LOW_WATER(max_frame);
5161
5162         if (netif_running(netdev))
5163                 ixgbe_reinit_locked(adapter);
5164
5165         return 0;
5166 }
5167
5168 /**
5169  * ixgbe_open - Called when a network interface is made active
5170  * @netdev: network interface device structure
5171  *
5172  * Returns 0 on success, negative value on failure
5173  *
5174  * The open entry point is called when a network interface is made
5175  * active by the system (IFF_UP).  At this point all resources needed
5176  * for transmit and receive operations are allocated, the interrupt
5177  * handler is registered with the OS, the watchdog timer is started,
5178  * and the stack is notified that the interface is ready.
5179  **/
5180 static int ixgbe_open(struct net_device *netdev)
5181 {
5182         struct ixgbe_adapter *adapter = netdev_priv(netdev);
5183         int err;
5184
5185         /* disallow open during test */
5186         if (test_bit(__IXGBE_TESTING, &adapter->state))
5187                 return -EBUSY;
5188
5189         netif_carrier_off(netdev);
5190
5191         /* allocate transmit descriptors */
5192         err = ixgbe_setup_all_tx_resources(adapter);
5193         if (err)
5194                 goto err_setup_tx;
5195
5196         /* allocate receive descriptors */
5197         err = ixgbe_setup_all_rx_resources(adapter);
5198         if (err)
5199                 goto err_setup_rx;
5200
5201         ixgbe_configure(adapter);
5202
5203         err = ixgbe_request_irq(adapter);
5204         if (err)
5205                 goto err_req_irq;
5206
5207         ixgbe_up_complete(adapter);
5208
5209         netif_tx_start_all_queues(netdev);
5210
5211         return 0;
5212
5213 err_req_irq:
5214 err_setup_rx:
5215         ixgbe_free_all_rx_resources(adapter);
5216 err_setup_tx:
5217         ixgbe_free_all_tx_resources(adapter);
5218         ixgbe_reset(adapter);
5219
5220         return err;
5221 }
5222
5223 /**
5224  * ixgbe_close - Disables a network interface
5225  * @netdev: network interface device structure
5226  *
5227  * Returns 0, this is not allowed to fail
5228  *
5229  * The close entry point is called when an interface is de-activated
5230  * by the OS.  The hardware is still under the drivers control, but
5231  * needs to be disabled.  A global MAC reset is issued to stop the
5232  * hardware, and all transmit and receive resources are freed.
5233  **/
5234 static int ixgbe_close(struct net_device *netdev)
5235 {
5236         struct ixgbe_adapter *adapter = netdev_priv(netdev);
5237
5238         ixgbe_down(adapter);
5239         ixgbe_free_irq(adapter);
5240
5241         ixgbe_fdir_filter_exit(adapter);
5242
5243         ixgbe_free_all_tx_resources(adapter);
5244         ixgbe_free_all_rx_resources(adapter);
5245
5246         ixgbe_release_hw_control(adapter);
5247
5248         return 0;
5249 }
5250
5251 #ifdef CONFIG_PM
5252 static int ixgbe_resume(struct pci_dev *pdev)
5253 {
5254         struct ixgbe_adapter *adapter = pci_get_drvdata(pdev);
5255         struct net_device *netdev = adapter->netdev;
5256         u32 err;
5257
5258         pci_set_power_state(pdev, PCI_D0);
5259         pci_restore_state(pdev);
5260         /*
5261          * pci_restore_state clears dev->state_saved so call
5262          * pci_save_state to restore it.
5263          */
5264         pci_save_state(pdev);
5265
5266         err = pci_enable_device_mem(pdev);
5267         if (err) {
5268                 e_dev_err("Cannot enable PCI device from suspend\n");
5269                 return err;
5270         }
5271         pci_set_master(pdev);
5272
5273         pci_wake_from_d3(pdev, false);
5274
5275         err = ixgbe_init_interrupt_scheme(adapter);
5276         if (err) {
5277                 e_dev_err("Cannot initialize interrupts for device\n");
5278                 return err;
5279         }
5280
5281         ixgbe_reset(adapter);
5282
5283         IXGBE_WRITE_REG(&adapter->hw, IXGBE_WUS, ~0);
5284
5285         if (netif_running(netdev)) {
5286                 err = ixgbe_open(netdev);
5287                 if (err)
5288                         return err;
5289         }
5290
5291         netif_device_attach(netdev);
5292
5293         return 0;
5294 }
5295 #endif /* CONFIG_PM */
5296
5297 static int __ixgbe_shutdown(struct pci_dev *pdev, bool *enable_wake)
5298 {
5299         struct ixgbe_adapter *adapter = pci_get_drvdata(pdev);
5300         struct net_device *netdev = adapter->netdev;
5301         struct ixgbe_hw *hw = &adapter->hw;
5302         u32 ctrl, fctrl;
5303         u32 wufc = adapter->wol;
5304 #ifdef CONFIG_PM
5305         int retval = 0;
5306 #endif
5307
5308         netif_device_detach(netdev);
5309
5310         if (netif_running(netdev)) {
5311                 ixgbe_down(adapter);
5312                 ixgbe_free_irq(adapter);
5313                 ixgbe_free_all_tx_resources(adapter);
5314                 ixgbe_free_all_rx_resources(adapter);
5315         }
5316
5317         ixgbe_clear_interrupt_scheme(adapter);
5318 #ifdef CONFIG_DCB
5319         kfree(adapter->ixgbe_ieee_pfc);
5320         kfree(adapter->ixgbe_ieee_ets);
5321 #endif
5322
5323 #ifdef CONFIG_PM
5324         retval = pci_save_state(pdev);
5325         if (retval)
5326                 return retval;
5327
5328 #endif
5329         if (wufc) {
5330                 ixgbe_set_rx_mode(netdev);
5331
5332                 /* turn on all-multi mode if wake on multicast is enabled */
5333                 if (wufc & IXGBE_WUFC_MC) {
5334                         fctrl = IXGBE_READ_REG(hw, IXGBE_FCTRL);
5335                         fctrl |= IXGBE_FCTRL_MPE;
5336                         IXGBE_WRITE_REG(hw, IXGBE_FCTRL, fctrl);
5337                 }
5338
5339                 ctrl = IXGBE_READ_REG(hw, IXGBE_CTRL);
5340                 ctrl |= IXGBE_CTRL_GIO_DIS;
5341                 IXGBE_WRITE_REG(hw, IXGBE_CTRL, ctrl);
5342
5343                 IXGBE_WRITE_REG(hw, IXGBE_WUFC, wufc);
5344         } else {
5345                 IXGBE_WRITE_REG(hw, IXGBE_WUC, 0);
5346                 IXGBE_WRITE_REG(hw, IXGBE_WUFC, 0);
5347         }
5348
5349         switch (hw->mac.type) {
5350         case ixgbe_mac_82598EB:
5351                 pci_wake_from_d3(pdev, false);
5352                 break;
5353         case ixgbe_mac_82599EB:
5354         case ixgbe_mac_X540:
5355                 pci_wake_from_d3(pdev, !!wufc);
5356                 break;
5357         default:
5358                 break;
5359         }
5360
5361         *enable_wake = !!wufc;
5362
5363         ixgbe_release_hw_control(adapter);
5364
5365         pci_disable_device(pdev);
5366
5367         return 0;
5368 }
5369
5370 #ifdef CONFIG_PM
5371 static int ixgbe_suspend(struct pci_dev *pdev, pm_message_t state)
5372 {
5373         int retval;
5374         bool wake;
5375
5376         retval = __ixgbe_shutdown(pdev, &wake);
5377         if (retval)
5378                 return retval;
5379
5380         if (wake) {
5381                 pci_prepare_to_sleep(pdev);
5382         } else {
5383                 pci_wake_from_d3(pdev, false);
5384                 pci_set_power_state(pdev, PCI_D3hot);
5385         }
5386
5387         return 0;
5388 }
5389 #endif /* CONFIG_PM */
5390
5391 static void ixgbe_shutdown(struct pci_dev *pdev)
5392 {
5393         bool wake;
5394
5395         __ixgbe_shutdown(pdev, &wake);
5396
5397         if (system_state == SYSTEM_POWER_OFF) {
5398                 pci_wake_from_d3(pdev, wake);
5399                 pci_set_power_state(pdev, PCI_D3hot);
5400         }
5401 }
5402
5403 /**
5404  * ixgbe_update_stats - Update the board statistics counters.
5405  * @adapter: board private structure
5406  **/
5407 void ixgbe_update_stats(struct ixgbe_adapter *adapter)
5408 {
5409         struct net_device *netdev = adapter->netdev;
5410         struct ixgbe_hw *hw = &adapter->hw;
5411         struct ixgbe_hw_stats *hwstats = &adapter->stats;
5412         u64 total_mpc = 0;
5413         u32 i, missed_rx = 0, mpc, bprc, lxon, lxoff, xon_off_tot;
5414         u64 non_eop_descs = 0, restart_queue = 0, tx_busy = 0;
5415         u64 alloc_rx_page_failed = 0, alloc_rx_buff_failed = 0;
5416         u64 bytes = 0, packets = 0;
5417
5418         if (test_bit(__IXGBE_DOWN, &adapter->state) ||
5419             test_bit(__IXGBE_RESETTING, &adapter->state))
5420                 return;
5421
5422         if (adapter->flags2 & IXGBE_FLAG2_RSC_ENABLED) {
5423                 u64 rsc_count = 0;
5424                 u64 rsc_flush = 0;
5425                 for (i = 0; i < 16; i++)
5426                         adapter->hw_rx_no_dma_resources +=
5427                                 IXGBE_READ_REG(hw, IXGBE_QPRDC(i));
5428                 for (i = 0; i < adapter->num_rx_queues; i++) {
5429                         rsc_count += adapter->rx_ring[i]->rx_stats.rsc_count;
5430                         rsc_flush += adapter->rx_ring[i]->rx_stats.rsc_flush;
5431                 }
5432                 adapter->rsc_total_count = rsc_count;
5433                 adapter->rsc_total_flush = rsc_flush;
5434         }
5435
5436         for (i = 0; i < adapter->num_rx_queues; i++) {
5437                 struct ixgbe_ring *rx_ring = adapter->rx_ring[i];
5438                 non_eop_descs += rx_ring->rx_stats.non_eop_descs;
5439                 alloc_rx_page_failed += rx_ring->rx_stats.alloc_rx_page_failed;
5440                 alloc_rx_buff_failed += rx_ring->rx_stats.alloc_rx_buff_failed;
5441                 bytes += rx_ring->stats.bytes;
5442                 packets += rx_ring->stats.packets;
5443         }
5444         adapter->non_eop_descs = non_eop_descs;
5445         adapter->alloc_rx_page_failed = alloc_rx_page_failed;
5446         adapter->alloc_rx_buff_failed = alloc_rx_buff_failed;
5447         netdev->stats.rx_bytes = bytes;
5448         netdev->stats.rx_packets = packets;
5449
5450         bytes = 0;
5451         packets = 0;
5452         /* gather some stats to the adapter struct that are per queue */
5453         for (i = 0; i < adapter->num_tx_queues; i++) {
5454                 struct ixgbe_ring *tx_ring = adapter->tx_ring[i];
5455                 restart_queue += tx_ring->tx_stats.restart_queue;
5456                 tx_busy += tx_ring->tx_stats.tx_busy;
5457                 bytes += tx_ring->stats.bytes;
5458                 packets += tx_ring->stats.packets;
5459         }
5460         adapter->restart_queue = restart_queue;
5461         adapter->tx_busy = tx_busy;
5462         netdev->stats.tx_bytes = bytes;
5463         netdev->stats.tx_packets = packets;
5464
5465         hwstats->crcerrs += IXGBE_READ_REG(hw, IXGBE_CRCERRS);
5466
5467         /* 8 register reads */
5468         for (i = 0; i < 8; i++) {
5469                 /* for packet buffers not used, the register should read 0 */
5470                 mpc = IXGBE_READ_REG(hw, IXGBE_MPC(i));
5471                 missed_rx += mpc;
5472                 hwstats->mpc[i] += mpc;
5473                 total_mpc += hwstats->mpc[i];
5474                 hwstats->pxontxc[i] += IXGBE_READ_REG(hw, IXGBE_PXONTXC(i));
5475                 hwstats->pxofftxc[i] += IXGBE_READ_REG(hw, IXGBE_PXOFFTXC(i));
5476                 switch (hw->mac.type) {
5477                 case ixgbe_mac_82598EB:
5478                         hwstats->rnbc[i] += IXGBE_READ_REG(hw, IXGBE_RNBC(i));
5479                         hwstats->qbtc[i] += IXGBE_READ_REG(hw, IXGBE_QBTC(i));
5480                         hwstats->qbrc[i] += IXGBE_READ_REG(hw, IXGBE_QBRC(i));
5481                         hwstats->pxonrxc[i] +=
5482                                 IXGBE_READ_REG(hw, IXGBE_PXONRXC(i));
5483                         break;
5484                 case ixgbe_mac_82599EB:
5485                 case ixgbe_mac_X540:
5486                         hwstats->pxonrxc[i] +=
5487                                 IXGBE_READ_REG(hw, IXGBE_PXONRXCNT(i));
5488                         break;
5489                 default:
5490                         break;
5491                 }
5492         }
5493
5494         /*16 register reads */
5495         for (i = 0; i < 16; i++) {
5496                 hwstats->qptc[i] += IXGBE_READ_REG(hw, IXGBE_QPTC(i));
5497                 hwstats->qprc[i] += IXGBE_READ_REG(hw, IXGBE_QPRC(i));
5498                 if ((hw->mac.type == ixgbe_mac_82599EB) ||
5499                     (hw->mac.type == ixgbe_mac_X540)) {
5500                         hwstats->qbtc[i] += IXGBE_READ_REG(hw, IXGBE_QBTC_L(i));
5501                         IXGBE_READ_REG(hw, IXGBE_QBTC_H(i)); /* to clear */
5502                         hwstats->qbrc[i] += IXGBE_READ_REG(hw, IXGBE_QBRC_L(i));
5503                         IXGBE_READ_REG(hw, IXGBE_QBRC_H(i)); /* to clear */
5504                 }
5505         }
5506
5507         hwstats->gprc += IXGBE_READ_REG(hw, IXGBE_GPRC);
5508         /* work around hardware counting issue */
5509         hwstats->gprc -= missed_rx;
5510
5511         ixgbe_update_xoff_received(adapter);
5512
5513         /* 82598 hardware only has a 32 bit counter in the high register */
5514         switch (hw->mac.type) {
5515         case ixgbe_mac_82598EB:
5516                 hwstats->lxonrxc += IXGBE_READ_REG(hw, IXGBE_LXONRXC);
5517                 hwstats->gorc += IXGBE_READ_REG(hw, IXGBE_GORCH);
5518                 hwstats->gotc += IXGBE_READ_REG(hw, IXGBE_GOTCH);
5519                 hwstats->tor += IXGBE_READ_REG(hw, IXGBE_TORH);
5520                 break;
5521         case ixgbe_mac_X540:
5522                 /* OS2BMC stats are X540 only*/
5523                 hwstats->o2bgptc += IXGBE_READ_REG(hw, IXGBE_O2BGPTC);
5524                 hwstats->o2bspc += IXGBE_READ_REG(hw, IXGBE_O2BSPC);
5525                 hwstats->b2ospc += IXGBE_READ_REG(hw, IXGBE_B2OSPC);
5526                 hwstats->b2ogprc += IXGBE_READ_REG(hw, IXGBE_B2OGPRC);
5527         case ixgbe_mac_82599EB:
5528                 hwstats->gorc += IXGBE_READ_REG(hw, IXGBE_GORCL);
5529                 IXGBE_READ_REG(hw, IXGBE_GORCH); /* to clear */
5530                 hwstats->gotc += IXGBE_READ_REG(hw, IXGBE_GOTCL);
5531                 IXGBE_READ_REG(hw, IXGBE_GOTCH); /* to clear */
5532                 hwstats->tor += IXGBE_READ_REG(hw, IXGBE_TORL);
5533                 IXGBE_READ_REG(hw, IXGBE_TORH); /* to clear */
5534                 hwstats->lxonrxc += IXGBE_READ_REG(hw, IXGBE_LXONRXCNT);
5535                 hwstats->fdirmatch += IXGBE_READ_REG(hw, IXGBE_FDIRMATCH);
5536                 hwstats->fdirmiss += IXGBE_READ_REG(hw, IXGBE_FDIRMISS);
5537 #ifdef IXGBE_FCOE
5538                 hwstats->fccrc += IXGBE_READ_REG(hw, IXGBE_FCCRC);
5539                 hwstats->fcoerpdc += IXGBE_READ_REG(hw, IXGBE_FCOERPDC);
5540                 hwstats->fcoeprc += IXGBE_READ_REG(hw, IXGBE_FCOEPRC);
5541                 hwstats->fcoeptc += IXGBE_READ_REG(hw, IXGBE_FCOEPTC);
5542                 hwstats->fcoedwrc += IXGBE_READ_REG(hw, IXGBE_FCOEDWRC);
5543                 hwstats->fcoedwtc += IXGBE_READ_REG(hw, IXGBE_FCOEDWTC);
5544 #endif /* IXGBE_FCOE */
5545                 break;
5546         default:
5547                 break;
5548         }
5549         bprc = IXGBE_READ_REG(hw, IXGBE_BPRC);
5550         hwstats->bprc += bprc;
5551         hwstats->mprc += IXGBE_READ_REG(hw, IXGBE_MPRC);
5552         if (hw->mac.type == ixgbe_mac_82598EB)
5553                 hwstats->mprc -= bprc;
5554         hwstats->roc += IXGBE_READ_REG(hw, IXGBE_ROC);
5555         hwstats->prc64 += IXGBE_READ_REG(hw, IXGBE_PRC64);
5556         hwstats->prc127 += IXGBE_READ_REG(hw, IXGBE_PRC127);
5557         hwstats->prc255 += IXGBE_READ_REG(hw, IXGBE_PRC255);
5558         hwstats->prc511 += IXGBE_READ_REG(hw, IXGBE_PRC511);
5559         hwstats->prc1023 += IXGBE_READ_REG(hw, IXGBE_PRC1023);
5560         hwstats->prc1522 += IXGBE_READ_REG(hw, IXGBE_PRC1522);
5561         hwstats->rlec += IXGBE_READ_REG(hw, IXGBE_RLEC);
5562         lxon = IXGBE_READ_REG(hw, IXGBE_LXONTXC);
5563         hwstats->lxontxc += lxon;
5564         lxoff = IXGBE_READ_REG(hw, IXGBE_LXOFFTXC);
5565         hwstats->lxofftxc += lxoff;
5566         hwstats->gptc += IXGBE_READ_REG(hw, IXGBE_GPTC);
5567         hwstats->mptc += IXGBE_READ_REG(hw, IXGBE_MPTC);
5568         /*
5569          * 82598 errata - tx of flow control packets is included in tx counters
5570          */
5571         xon_off_tot = lxon + lxoff;
5572         hwstats->gptc -= xon_off_tot;
5573         hwstats->mptc -= xon_off_tot;
5574         hwstats->gotc -= (xon_off_tot * (ETH_ZLEN + ETH_FCS_LEN));
5575         hwstats->ruc += IXGBE_READ_REG(hw, IXGBE_RUC);
5576         hwstats->rfc += IXGBE_READ_REG(hw, IXGBE_RFC);
5577         hwstats->rjc += IXGBE_READ_REG(hw, IXGBE_RJC);
5578         hwstats->tpr += IXGBE_READ_REG(hw, IXGBE_TPR);
5579         hwstats->ptc64 += IXGBE_READ_REG(hw, IXGBE_PTC64);
5580         hwstats->ptc64 -= xon_off_tot;
5581         hwstats->ptc127 += IXGBE_READ_REG(hw, IXGBE_PTC127);
5582         hwstats->ptc255 += IXGBE_READ_REG(hw, IXGBE_PTC255);
5583         hwstats->ptc511 += IXGBE_READ_REG(hw, IXGBE_PTC511);
5584         hwstats->ptc1023 += IXGBE_READ_REG(hw, IXGBE_PTC1023);
5585         hwstats->ptc1522 += IXGBE_READ_REG(hw, IXGBE_PTC1522);
5586         hwstats->bptc += IXGBE_READ_REG(hw, IXGBE_BPTC);
5587
5588         /* Fill out the OS statistics structure */
5589         netdev->stats.multicast = hwstats->mprc;
5590
5591         /* Rx Errors */
5592         netdev->stats.rx_errors = hwstats->crcerrs + hwstats->rlec;
5593         netdev->stats.rx_dropped = 0;
5594         netdev->stats.rx_length_errors = hwstats->rlec;
5595         netdev->stats.rx_crc_errors = hwstats->crcerrs;
5596         netdev->stats.rx_missed_errors = total_mpc;
5597 }
5598
5599 /**
5600  * ixgbe_fdir_reinit_subtask - worker thread to reinit FDIR filter table
5601  * @adapter - pointer to the device adapter structure
5602  **/
5603 static void ixgbe_fdir_reinit_subtask(struct ixgbe_adapter *adapter)
5604 {
5605         struct ixgbe_hw *hw = &adapter->hw;
5606         int i;
5607
5608         if (!(adapter->flags2 & IXGBE_FLAG2_FDIR_REQUIRES_REINIT))
5609                 return;
5610
5611         adapter->flags2 &= ~IXGBE_FLAG2_FDIR_REQUIRES_REINIT;
5612
5613         /* if interface is down do nothing */
5614         if (test_bit(__IXGBE_DOWN, &adapter->state))
5615                 return;
5616
5617         /* do nothing if we are not using signature filters */
5618         if (!(adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE))
5619                 return;
5620
5621         adapter->fdir_overflow++;
5622
5623         if (ixgbe_reinit_fdir_tables_82599(hw) == 0) {
5624                 for (i = 0; i < adapter->num_tx_queues; i++)
5625                         set_bit(__IXGBE_TX_FDIR_INIT_DONE,
5626                                 &(adapter->tx_ring[i]->state));
5627                 /* re-enable flow director interrupts */
5628                 IXGBE_WRITE_REG(hw, IXGBE_EIMS, IXGBE_EIMS_FLOW_DIR);
5629         } else {
5630                 e_err(probe, "failed to finish FDIR re-initialization, "
5631                       "ignored adding FDIR ATR filters\n");
5632         }
5633 }
5634
5635 /**
5636  * ixgbe_check_hang_subtask - check for hung queues and dropped interrupts
5637  * @adapter - pointer to the device adapter structure
5638  *
5639  * This function serves two purposes.  First it strobes the interrupt lines
5640  * in order to make certain interrupts are occuring.  Secondly it sets the
5641  * bits needed to check for TX hangs.  As a result we should immediately
5642  * determine if a hang has occured.
5643  */
5644 static void ixgbe_check_hang_subtask(struct ixgbe_adapter *adapter)
5645 {
5646         struct ixgbe_hw *hw = &adapter->hw;
5647         u64 eics = 0;
5648         int i;
5649
5650         /* If we're down or resetting, just bail */
5651         if (test_bit(__IXGBE_DOWN, &adapter->state) ||
5652             test_bit(__IXGBE_RESETTING, &adapter->state))
5653                 return;
5654
5655         /* Force detection of hung controller */
5656         if (netif_carrier_ok(adapter->netdev)) {
5657                 for (i = 0; i < adapter->num_tx_queues; i++)
5658                         set_check_for_tx_hang(adapter->tx_ring[i]);
5659         }
5660
5661         if (!(adapter->flags & IXGBE_FLAG_MSIX_ENABLED)) {
5662                 /*
5663                  * for legacy and MSI interrupts don't set any bits
5664                  * that are enabled for EIAM, because this operation
5665                  * would set *both* EIMS and EICS for any bit in EIAM
5666                  */
5667                 IXGBE_WRITE_REG(hw, IXGBE_EICS,
5668                         (IXGBE_EICS_TCP_TIMER | IXGBE_EICS_OTHER));
5669         } else {
5670                 /* get one bit for every active tx/rx interrupt vector */
5671                 for (i = 0; i < adapter->num_msix_vectors - NON_Q_VECTORS; i++) {
5672                         struct ixgbe_q_vector *qv = adapter->q_vector[i];
5673                         if (qv->rx.ring || qv->tx.ring)
5674                                 eics |= ((u64)1 << i);
5675                 }
5676         }
5677
5678         /* Cause software interrupt to ensure rings are cleaned */
5679         ixgbe_irq_rearm_queues(adapter, eics);
5680
5681 }
5682
5683 /**
5684  * ixgbe_watchdog_update_link - update the link status
5685  * @adapter - pointer to the device adapter structure
5686  * @link_speed - pointer to a u32 to store the link_speed
5687  **/
5688 static void ixgbe_watchdog_update_link(struct ixgbe_adapter *adapter)
5689 {
5690         struct ixgbe_hw *hw = &adapter->hw;
5691         u32 link_speed = adapter->link_speed;
5692         bool link_up = adapter->link_up;
5693         int i;
5694
5695         if (!(adapter->flags & IXGBE_FLAG_NEED_LINK_UPDATE))
5696                 return;
5697
5698         if (hw->mac.ops.check_link) {
5699                 hw->mac.ops.check_link(hw, &link_speed, &link_up, false);
5700         } else {
5701                 /* always assume link is up, if no check link function */
5702                 link_speed = IXGBE_LINK_SPEED_10GB_FULL;
5703                 link_up = true;
5704         }
5705         if (link_up) {
5706                 if (adapter->flags & IXGBE_FLAG_DCB_ENABLED) {
5707                         for (i = 0; i < MAX_TRAFFIC_CLASS; i++)
5708                                 hw->mac.ops.fc_enable(hw, i);
5709                 } else {
5710                         hw->mac.ops.fc_enable(hw, 0);
5711                 }
5712         }
5713
5714         if (link_up ||
5715             time_after(jiffies, (adapter->link_check_timeout +
5716                                  IXGBE_TRY_LINK_TIMEOUT))) {
5717                 adapter->flags &= ~IXGBE_FLAG_NEED_LINK_UPDATE;
5718                 IXGBE_WRITE_REG(hw, IXGBE_EIMS, IXGBE_EIMC_LSC);
5719                 IXGBE_WRITE_FLUSH(hw);
5720         }
5721
5722         adapter->link_up = link_up;
5723         adapter->link_speed = link_speed;
5724 }
5725
5726 /**
5727  * ixgbe_watchdog_link_is_up - update netif_carrier status and
5728  *                             print link up message
5729  * @adapter - pointer to the device adapter structure
5730  **/
5731 static void ixgbe_watchdog_link_is_up(struct ixgbe_adapter *adapter)
5732 {
5733         struct net_device *netdev = adapter->netdev;
5734         struct ixgbe_hw *hw = &adapter->hw;
5735         u32 link_speed = adapter->link_speed;
5736         bool flow_rx, flow_tx;
5737
5738         /* only continue if link was previously down */
5739         if (netif_carrier_ok(netdev))
5740                 return;
5741
5742         adapter->flags2 &= ~IXGBE_FLAG2_SEARCH_FOR_SFP;
5743
5744         switch (hw->mac.type) {
5745         case ixgbe_mac_82598EB: {
5746                 u32 frctl = IXGBE_READ_REG(hw, IXGBE_FCTRL);
5747                 u32 rmcs = IXGBE_READ_REG(hw, IXGBE_RMCS);
5748                 flow_rx = !!(frctl & IXGBE_FCTRL_RFCE);
5749                 flow_tx = !!(rmcs & IXGBE_RMCS_TFCE_802_3X);
5750         }
5751                 break;
5752         case ixgbe_mac_X540:
5753         case ixgbe_mac_82599EB: {
5754                 u32 mflcn = IXGBE_READ_REG(hw, IXGBE_MFLCN);
5755                 u32 fccfg = IXGBE_READ_REG(hw, IXGBE_FCCFG);
5756                 flow_rx = !!(mflcn & IXGBE_MFLCN_RFCE);
5757                 flow_tx = !!(fccfg & IXGBE_FCCFG_TFCE_802_3X);
5758         }
5759                 break;
5760         default:
5761                 flow_tx = false;
5762                 flow_rx = false;
5763                 break;
5764         }
5765         e_info(drv, "NIC Link is Up %s, Flow Control: %s\n",
5766                (link_speed == IXGBE_LINK_SPEED_10GB_FULL ?
5767                "10 Gbps" :
5768                (link_speed == IXGBE_LINK_SPEED_1GB_FULL ?
5769                "1 Gbps" :
5770                (link_speed == IXGBE_LINK_SPEED_100_FULL ?
5771                "100 Mbps" :
5772                "unknown speed"))),
5773                ((flow_rx && flow_tx) ? "RX/TX" :
5774                (flow_rx ? "RX" :
5775                (flow_tx ? "TX" : "None"))));
5776
5777         netif_carrier_on(netdev);
5778         ixgbe_check_vf_rate_limit(adapter);
5779 }
5780
5781 /**
5782  * ixgbe_watchdog_link_is_down - update netif_carrier status and
5783  *                               print link down message
5784  * @adapter - pointer to the adapter structure
5785  **/
5786 static void ixgbe_watchdog_link_is_down(struct ixgbe_adapter* adapter)
5787 {
5788         struct net_device *netdev = adapter->netdev;
5789         struct ixgbe_hw *hw = &adapter->hw;
5790
5791         adapter->link_up = false;
5792         adapter->link_speed = 0;
5793
5794         /* only continue if link was up previously */
5795         if (!netif_carrier_ok(netdev))
5796                 return;
5797
5798         /* poll for SFP+ cable when link is down */
5799         if (ixgbe_is_sfp(hw) && hw->mac.type == ixgbe_mac_82598EB)
5800                 adapter->flags2 |= IXGBE_FLAG2_SEARCH_FOR_SFP;
5801
5802         e_info(drv, "NIC Link is Down\n");
5803         netif_carrier_off(netdev);
5804 }
5805
5806 /**
5807  * ixgbe_watchdog_flush_tx - flush queues on link down
5808  * @adapter - pointer to the device adapter structure
5809  **/
5810 static void ixgbe_watchdog_flush_tx(struct ixgbe_adapter *adapter)
5811 {
5812         int i;
5813         int some_tx_pending = 0;
5814
5815         if (!netif_carrier_ok(adapter->netdev)) {
5816                 for (i = 0; i < adapter->num_tx_queues; i++) {
5817                         struct ixgbe_ring *tx_ring = adapter->tx_ring[i];
5818                         if (tx_ring->next_to_use != tx_ring->next_to_clean) {
5819                                 some_tx_pending = 1;
5820                                 break;
5821                         }
5822                 }
5823
5824                 if (some_tx_pending) {
5825                         /* We've lost link, so the controller stops DMA,
5826                          * but we've got queued Tx work that's never going
5827                          * to get done, so reset controller to flush Tx.
5828                          * (Do the reset outside of interrupt context).
5829                          */
5830                         adapter->flags2 |= IXGBE_FLAG2_RESET_REQUESTED;
5831                 }
5832         }
5833 }
5834
5835 static void ixgbe_spoof_check(struct ixgbe_adapter *adapter)
5836 {
5837         u32 ssvpc;
5838
5839         /* Do not perform spoof check for 82598 */
5840         if (adapter->hw.mac.type == ixgbe_mac_82598EB)
5841                 return;
5842
5843         ssvpc = IXGBE_READ_REG(&adapter->hw, IXGBE_SSVPC);
5844
5845         /*
5846          * ssvpc register is cleared on read, if zero then no
5847          * spoofed packets in the last interval.
5848          */
5849         if (!ssvpc)
5850                 return;
5851
5852         e_warn(drv, "%d Spoofed packets detected\n", ssvpc);
5853 }
5854
5855 /**
5856  * ixgbe_watchdog_subtask - check and bring link up
5857  * @adapter - pointer to the device adapter structure
5858  **/
5859 static void ixgbe_watchdog_subtask(struct ixgbe_adapter *adapter)
5860 {
5861         /* if interface is down do nothing */
5862         if (test_bit(__IXGBE_DOWN, &adapter->state))
5863                 return;
5864
5865         ixgbe_watchdog_update_link(adapter);
5866
5867         if (adapter->link_up)
5868                 ixgbe_watchdog_link_is_up(adapter);
5869         else
5870                 ixgbe_watchdog_link_is_down(adapter);
5871
5872         ixgbe_spoof_check(adapter);
5873         ixgbe_update_stats(adapter);
5874
5875         ixgbe_watchdog_flush_tx(adapter);
5876 }
5877
5878 /**
5879  * ixgbe_sfp_detection_subtask - poll for SFP+ cable
5880  * @adapter - the ixgbe adapter structure
5881  **/
5882 static void ixgbe_sfp_detection_subtask(struct ixgbe_adapter *adapter)
5883 {
5884         struct ixgbe_hw *hw = &adapter->hw;
5885         s32 err;
5886
5887         /* not searching for SFP so there is nothing to do here */
5888         if (!(adapter->flags2 & IXGBE_FLAG2_SEARCH_FOR_SFP) &&
5889             !(adapter->flags2 & IXGBE_FLAG2_SFP_NEEDS_RESET))
5890                 return;
5891
5892         /* someone else is in init, wait until next service event */
5893         if (test_and_set_bit(__IXGBE_IN_SFP_INIT, &adapter->state))
5894                 return;
5895
5896         err = hw->phy.ops.identify_sfp(hw);
5897         if (err == IXGBE_ERR_SFP_NOT_SUPPORTED)
5898                 goto sfp_out;
5899
5900         if (err == IXGBE_ERR_SFP_NOT_PRESENT) {
5901                 /* If no cable is present, then we need to reset
5902                  * the next time we find a good cable. */
5903                 adapter->flags2 |= IXGBE_FLAG2_SFP_NEEDS_RESET;
5904         }
5905
5906         /* exit on error */
5907         if (err)
5908                 goto sfp_out;
5909
5910         /* exit if reset not needed */
5911         if (!(adapter->flags2 & IXGBE_FLAG2_SFP_NEEDS_RESET))
5912                 goto sfp_out;
5913
5914         adapter->flags2 &= ~IXGBE_FLAG2_SFP_NEEDS_RESET;
5915
5916         /*
5917          * A module may be identified correctly, but the EEPROM may not have
5918          * support for that module.  setup_sfp() will fail in that case, so
5919          * we should not allow that module to load.
5920          */
5921         if (hw->mac.type == ixgbe_mac_82598EB)
5922                 err = hw->phy.ops.reset(hw);
5923         else
5924                 err = hw->mac.ops.setup_sfp(hw);
5925
5926         if (err == IXGBE_ERR_SFP_NOT_SUPPORTED)
5927                 goto sfp_out;
5928
5929         adapter->flags |= IXGBE_FLAG_NEED_LINK_CONFIG;
5930         e_info(probe, "detected SFP+: %d\n", hw->phy.sfp_type);
5931
5932 sfp_out:
5933         clear_bit(__IXGBE_IN_SFP_INIT, &adapter->state);
5934
5935         if ((err == IXGBE_ERR_SFP_NOT_SUPPORTED) &&
5936             (adapter->netdev->reg_state == NETREG_REGISTERED)) {
5937                 e_dev_err("failed to initialize because an unsupported "
5938                           "SFP+ module type was detected.\n");
5939                 e_dev_err("Reload the driver after installing a "
5940                           "supported module.\n");
5941                 unregister_netdev(adapter->netdev);
5942         }
5943 }
5944
5945 /**
5946  * ixgbe_sfp_link_config_subtask - set up link SFP after module install
5947  * @adapter - the ixgbe adapter structure
5948  **/
5949 static void ixgbe_sfp_link_config_subtask(struct ixgbe_adapter *adapter)
5950 {
5951         struct ixgbe_hw *hw = &adapter->hw;
5952         u32 autoneg;
5953         bool negotiation;
5954
5955         if (!(adapter->flags & IXGBE_FLAG_NEED_LINK_CONFIG))
5956                 return;
5957
5958         /* someone else is in init, wait until next service event */
5959         if (test_and_set_bit(__IXGBE_IN_SFP_INIT, &adapter->state))
5960                 return;
5961
5962         adapter->flags &= ~IXGBE_FLAG_NEED_LINK_CONFIG;
5963
5964         autoneg = hw->phy.autoneg_advertised;
5965         if ((!autoneg) && (hw->mac.ops.get_link_capabilities))
5966                 hw->mac.ops.get_link_capabilities(hw, &autoneg, &negotiation);
5967         hw->mac.autotry_restart = false;
5968         if (hw->mac.ops.setup_link)
5969                 hw->mac.ops.setup_link(hw, autoneg, negotiation, true);
5970
5971         adapter->flags |= IXGBE_FLAG_NEED_LINK_UPDATE;
5972         adapter->link_check_timeout = jiffies;
5973         clear_bit(__IXGBE_IN_SFP_INIT, &adapter->state);
5974 }
5975
5976 /**
5977  * ixgbe_service_timer - Timer Call-back
5978  * @data: pointer to adapter cast into an unsigned long
5979  **/
5980 static void ixgbe_service_timer(unsigned long data)
5981 {
5982         struct ixgbe_adapter *adapter = (struct ixgbe_adapter *)data;
5983         unsigned long next_event_offset;
5984
5985         /* poll faster when waiting for link */
5986         if (adapter->flags & IXGBE_FLAG_NEED_LINK_UPDATE)
5987                 next_event_offset = HZ / 10;
5988         else
5989                 next_event_offset = HZ * 2;
5990
5991         /* Reset the timer */
5992         mod_timer(&adapter->service_timer, next_event_offset + jiffies);
5993
5994         ixgbe_service_event_schedule(adapter);
5995 }
5996
5997 static void ixgbe_reset_subtask(struct ixgbe_adapter *adapter)
5998 {
5999         if (!(adapter->flags2 & IXGBE_FLAG2_RESET_REQUESTED))
6000                 return;
6001
6002         adapter->flags2 &= ~IXGBE_FLAG2_RESET_REQUESTED;
6003
6004         /* If we're already down or resetting, just bail */
6005         if (test_bit(__IXGBE_DOWN, &adapter->state) ||
6006             test_bit(__IXGBE_RESETTING, &adapter->state))
6007                 return;
6008
6009         ixgbe_dump(adapter);
6010         netdev_err(adapter->netdev, "Reset adapter\n");
6011         adapter->tx_timeout_count++;
6012
6013         ixgbe_reinit_locked(adapter);
6014 }
6015
6016 /**
6017  * ixgbe_service_task - manages and runs subtasks
6018  * @work: pointer to work_struct containing our data
6019  **/
6020 static void ixgbe_service_task(struct work_struct *work)
6021 {
6022         struct ixgbe_adapter *adapter = container_of(work,
6023                                                      struct ixgbe_adapter,
6024                                                      service_task);
6025
6026         ixgbe_reset_subtask(adapter);
6027         ixgbe_sfp_detection_subtask(adapter);
6028         ixgbe_sfp_link_config_subtask(adapter);
6029         ixgbe_check_overtemp_subtask(adapter);
6030         ixgbe_watchdog_subtask(adapter);
6031         ixgbe_fdir_reinit_subtask(adapter);
6032         ixgbe_check_hang_subtask(adapter);
6033
6034         ixgbe_service_event_complete(adapter);
6035 }
6036
6037 void ixgbe_tx_ctxtdesc(struct ixgbe_ring *tx_ring, u32 vlan_macip_lens,
6038                        u32 fcoe_sof_eof, u32 type_tucmd, u32 mss_l4len_idx)
6039 {
6040         struct ixgbe_adv_tx_context_desc *context_desc;
6041         u16 i = tx_ring->next_to_use;
6042
6043         context_desc = IXGBE_TX_CTXTDESC_ADV(tx_ring, i);
6044
6045         i++;
6046         tx_ring->next_to_use = (i < tx_ring->count) ? i : 0;
6047
6048         /* set bits to identify this as an advanced context descriptor */
6049         type_tucmd |= IXGBE_TXD_CMD_DEXT | IXGBE_ADVTXD_DTYP_CTXT;
6050
6051         context_desc->vlan_macip_lens   = cpu_to_le32(vlan_macip_lens);
6052         context_desc->seqnum_seed       = cpu_to_le32(fcoe_sof_eof);
6053         context_desc->type_tucmd_mlhl   = cpu_to_le32(type_tucmd);
6054         context_desc->mss_l4len_idx     = cpu_to_le32(mss_l4len_idx);
6055 }
6056
6057 static int ixgbe_tso(struct ixgbe_ring *tx_ring, struct sk_buff *skb,
6058                      u32 tx_flags, __be16 protocol, u8 *hdr_len)
6059 {
6060         int err;
6061         u32 vlan_macip_lens, type_tucmd;
6062         u32 mss_l4len_idx, l4len;
6063
6064         if (!skb_is_gso(skb))
6065                 return 0;
6066
6067         if (skb_header_cloned(skb)) {
6068                 err = pskb_expand_head(skb, 0, 0, GFP_ATOMIC);
6069                 if (err)
6070                         return err;
6071         }
6072
6073         /* ADV DTYP TUCMD MKRLOC/ISCSIHEDLEN */
6074         type_tucmd = IXGBE_ADVTXD_TUCMD_L4T_TCP;
6075
6076         if (protocol == __constant_htons(ETH_P_IP)) {
6077                 struct iphdr *iph = ip_hdr(skb);
6078                 iph->tot_len = 0;
6079                 iph->check = 0;
6080                 tcp_hdr(skb)->check = ~csum_tcpudp_magic(iph->saddr,
6081                                                          iph->daddr, 0,
6082                                                          IPPROTO_TCP,
6083                                                          0);
6084                 type_tucmd |= IXGBE_ADVTXD_TUCMD_IPV4;
6085         } else if (skb_is_gso_v6(skb)) {
6086                 ipv6_hdr(skb)->payload_len = 0;
6087                 tcp_hdr(skb)->check =
6088                     ~csum_ipv6_magic(&ipv6_hdr(skb)->saddr,
6089                                      &ipv6_hdr(skb)->daddr,
6090                                      0, IPPROTO_TCP, 0);
6091         }
6092
6093         l4len = tcp_hdrlen(skb);
6094         *hdr_len = skb_transport_offset(skb) + l4len;
6095
6096         /* mss_l4len_id: use 1 as index for TSO */
6097         mss_l4len_idx = l4len << IXGBE_ADVTXD_L4LEN_SHIFT;
6098         mss_l4len_idx |= skb_shinfo(skb)->gso_size << IXGBE_ADVTXD_MSS_SHIFT;
6099         mss_l4len_idx |= 1 << IXGBE_ADVTXD_IDX_SHIFT;
6100
6101         /* vlan_macip_lens: HEADLEN, MACLEN, VLAN tag */
6102         vlan_macip_lens = skb_network_header_len(skb);
6103         vlan_macip_lens |= skb_network_offset(skb) << IXGBE_ADVTXD_MACLEN_SHIFT;
6104         vlan_macip_lens |= tx_flags & IXGBE_TX_FLAGS_VLAN_MASK;
6105
6106         ixgbe_tx_ctxtdesc(tx_ring, vlan_macip_lens, 0, type_tucmd,
6107                           mss_l4len_idx);
6108
6109         return 1;
6110 }
6111
6112 static bool ixgbe_tx_csum(struct ixgbe_ring *tx_ring,
6113                           struct sk_buff *skb, u32 tx_flags,
6114                           __be16 protocol)
6115 {
6116         u32 vlan_macip_lens = 0;
6117         u32 mss_l4len_idx = 0;
6118         u32 type_tucmd = 0;
6119
6120         if (skb->ip_summed != CHECKSUM_PARTIAL) {
6121             if (!(tx_flags & IXGBE_TX_FLAGS_HW_VLAN) &&
6122                 !(tx_flags & IXGBE_TX_FLAGS_TXSW))
6123                         return false;
6124         } else {
6125                 u8 l4_hdr = 0;
6126                 switch (protocol) {
6127                 case __constant_htons(ETH_P_IP):
6128                         vlan_macip_lens |= skb_network_header_len(skb);
6129                         type_tucmd |= IXGBE_ADVTXD_TUCMD_IPV4;
6130                         l4_hdr = ip_hdr(skb)->protocol;
6131                         break;
6132                 case __constant_htons(ETH_P_IPV6):
6133                         vlan_macip_lens |= skb_network_header_len(skb);
6134                         l4_hdr = ipv6_hdr(skb)->nexthdr;
6135                         break;
6136                 default:
6137                         if (unlikely(net_ratelimit())) {
6138                                 dev_warn(tx_ring->dev,
6139                                  "partial checksum but proto=%x!\n",
6140                                  skb->protocol);
6141                         }
6142                         break;
6143                 }
6144
6145                 switch (l4_hdr) {
6146                 case IPPROTO_TCP:
6147                         type_tucmd |= IXGBE_ADVTXD_TUCMD_L4T_TCP;
6148                         mss_l4len_idx = tcp_hdrlen(skb) <<
6149                                         IXGBE_ADVTXD_L4LEN_SHIFT;
6150                         break;
6151                 case IPPROTO_SCTP:
6152                         type_tucmd |= IXGBE_ADVTXD_TUCMD_L4T_SCTP;
6153                         mss_l4len_idx = sizeof(struct sctphdr) <<
6154                                         IXGBE_ADVTXD_L4LEN_SHIFT;
6155                         break;
6156                 case IPPROTO_UDP:
6157                         mss_l4len_idx = sizeof(struct udphdr) <<
6158                                         IXGBE_ADVTXD_L4LEN_SHIFT;
6159                         break;
6160                 default:
6161                         if (unlikely(net_ratelimit())) {
6162                                 dev_warn(tx_ring->dev,
6163                                  "partial checksum but l4 proto=%x!\n",
6164                                  skb->protocol);
6165                         }
6166                         break;
6167                 }
6168         }
6169
6170         vlan_macip_lens |= skb_network_offset(skb) << IXGBE_ADVTXD_MACLEN_SHIFT;
6171         vlan_macip_lens |= tx_flags & IXGBE_TX_FLAGS_VLAN_MASK;
6172
6173         ixgbe_tx_ctxtdesc(tx_ring, vlan_macip_lens, 0,
6174                           type_tucmd, mss_l4len_idx);
6175
6176         return (skb->ip_summed == CHECKSUM_PARTIAL);
6177 }
6178
6179 static __le32 ixgbe_tx_cmd_type(u32 tx_flags)
6180 {
6181         /* set type for advanced descriptor with frame checksum insertion */
6182         __le32 cmd_type = cpu_to_le32(IXGBE_ADVTXD_DTYP_DATA |
6183                                       IXGBE_ADVTXD_DCMD_IFCS |
6184                                       IXGBE_ADVTXD_DCMD_DEXT);
6185
6186         /* set HW vlan bit if vlan is present */
6187         if (tx_flags & IXGBE_TX_FLAGS_HW_VLAN)
6188                 cmd_type |= cpu_to_le32(IXGBE_ADVTXD_DCMD_VLE);
6189
6190         /* set segmentation enable bits for TSO/FSO */
6191 #ifdef IXGBE_FCOE
6192         if ((tx_flags & IXGBE_TX_FLAGS_TSO) || (tx_flags & IXGBE_TX_FLAGS_FSO))
6193 #else
6194         if (tx_flags & IXGBE_TX_FLAGS_TSO)
6195 #endif
6196                 cmd_type |= cpu_to_le32(IXGBE_ADVTXD_DCMD_TSE);
6197
6198         return cmd_type;
6199 }
6200
6201 static __le32 ixgbe_tx_olinfo_status(u32 tx_flags, unsigned int paylen)
6202 {
6203         __le32 olinfo_status =
6204                 cpu_to_le32(paylen << IXGBE_ADVTXD_PAYLEN_SHIFT);
6205
6206         if (tx_flags & IXGBE_TX_FLAGS_TSO) {
6207                 olinfo_status |= cpu_to_le32(IXGBE_ADVTXD_POPTS_TXSM |
6208                                             (1 << IXGBE_ADVTXD_IDX_SHIFT));
6209                 /* enble IPv4 checksum for TSO */
6210                 if (tx_flags & IXGBE_TX_FLAGS_IPV4)
6211                         olinfo_status |= cpu_to_le32(IXGBE_ADVTXD_POPTS_IXSM);
6212         }
6213
6214         /* enable L4 checksum for TSO and TX checksum offload */
6215         if (tx_flags & IXGBE_TX_FLAGS_CSUM)
6216                 olinfo_status |= cpu_to_le32(IXGBE_ADVTXD_POPTS_TXSM);
6217
6218 #ifdef IXGBE_FCOE
6219         /* use index 1 context for FCOE/FSO */
6220         if (tx_flags & IXGBE_TX_FLAGS_FCOE)
6221                 olinfo_status |= cpu_to_le32(IXGBE_ADVTXD_CC |
6222                                             (1 << IXGBE_ADVTXD_IDX_SHIFT));
6223
6224 #endif
6225         /*
6226          * Check Context must be set if Tx switch is enabled, which it
6227          * always is for case where virtual functions are running
6228          */
6229         if (tx_flags & IXGBE_TX_FLAGS_TXSW)
6230                 olinfo_status |= cpu_to_le32(IXGBE_ADVTXD_CC);
6231
6232         return olinfo_status;
6233 }
6234
6235 #define IXGBE_TXD_CMD (IXGBE_TXD_CMD_EOP | \
6236                        IXGBE_TXD_CMD_RS)
6237
6238 static void ixgbe_tx_map(struct ixgbe_ring *tx_ring,
6239                          struct sk_buff *skb,
6240                          struct ixgbe_tx_buffer *first,
6241                          u32 tx_flags,
6242                          const u8 hdr_len)
6243 {
6244         struct device *dev = tx_ring->dev;
6245         struct ixgbe_tx_buffer *tx_buffer_info;
6246         union ixgbe_adv_tx_desc *tx_desc;
6247         dma_addr_t dma;
6248         __le32 cmd_type, olinfo_status;
6249         struct skb_frag_struct *frag;
6250         unsigned int f = 0;
6251         unsigned int data_len = skb->data_len;
6252         unsigned int size = skb_headlen(skb);
6253         u32 offset = 0;
6254         u32 paylen = skb->len - hdr_len;
6255         u16 i = tx_ring->next_to_use;
6256         u16 gso_segs;
6257
6258 #ifdef IXGBE_FCOE
6259         if (tx_flags & IXGBE_TX_FLAGS_FCOE) {
6260                 if (data_len >= sizeof(struct fcoe_crc_eof)) {
6261                         data_len -= sizeof(struct fcoe_crc_eof);
6262                 } else {
6263                         size -= sizeof(struct fcoe_crc_eof) - data_len;
6264                         data_len = 0;
6265                 }
6266         }
6267
6268 #endif
6269         dma = dma_map_single(dev, skb->data, size, DMA_TO_DEVICE);
6270         if (dma_mapping_error(dev, dma))
6271                 goto dma_error;
6272
6273         cmd_type = ixgbe_tx_cmd_type(tx_flags);
6274         olinfo_status = ixgbe_tx_olinfo_status(tx_flags, paylen);
6275
6276         tx_desc = IXGBE_TX_DESC_ADV(tx_ring, i);
6277
6278         for (;;) {
6279                 while (size > IXGBE_MAX_DATA_PER_TXD) {
6280                         tx_desc->read.buffer_addr = cpu_to_le64(dma + offset);
6281                         tx_desc->read.cmd_type_len =
6282                                 cmd_type | cpu_to_le32(IXGBE_MAX_DATA_PER_TXD);
6283                         tx_desc->read.olinfo_status = olinfo_status;
6284
6285                         offset += IXGBE_MAX_DATA_PER_TXD;
6286                         size -= IXGBE_MAX_DATA_PER_TXD;
6287
6288                         tx_desc++;
6289                         i++;
6290                         if (i == tx_ring->count) {
6291                                 tx_desc = IXGBE_TX_DESC_ADV(tx_ring, 0);
6292                                 i = 0;
6293                         }
6294                 }
6295
6296                 tx_buffer_info = &tx_ring->tx_buffer_info[i];
6297                 tx_buffer_info->length = offset + size;
6298                 tx_buffer_info->tx_flags = tx_flags;
6299                 tx_buffer_info->dma = dma;
6300
6301                 tx_desc->read.buffer_addr = cpu_to_le64(dma + offset);
6302                 tx_desc->read.cmd_type_len = cmd_type | cpu_to_le32(size);
6303                 tx_desc->read.olinfo_status = olinfo_status;
6304
6305                 if (!data_len)
6306                         break;
6307
6308                 frag = &skb_shinfo(skb)->frags[f];
6309 #ifdef IXGBE_FCOE
6310                 size = min_t(unsigned int, data_len, frag->size);
6311 #else
6312                 size = frag->size;
6313 #endif
6314                 data_len -= size;
6315                 f++;
6316
6317                 offset = 0;
6318                 tx_flags |= IXGBE_TX_FLAGS_MAPPED_AS_PAGE;
6319
6320                 dma = skb_frag_dma_map(dev, frag, 0, size, DMA_TO_DEVICE);
6321                 if (dma_mapping_error(dev, dma))
6322                         goto dma_error;
6323
6324                 tx_desc++;
6325                 i++;
6326                 if (i == tx_ring->count) {
6327                         tx_desc = IXGBE_TX_DESC_ADV(tx_ring, 0);
6328                         i = 0;
6329                 }
6330         }
6331
6332         tx_desc->read.cmd_type_len |= cpu_to_le32(IXGBE_TXD_CMD);
6333
6334         i++;
6335         if (i == tx_ring->count)
6336                 i = 0;
6337
6338         tx_ring->next_to_use = i;
6339
6340         if (tx_flags & IXGBE_TX_FLAGS_TSO)
6341                 gso_segs = skb_shinfo(skb)->gso_segs;
6342 #ifdef IXGBE_FCOE
6343         /* adjust for FCoE Sequence Offload */
6344         else if (tx_flags & IXGBE_TX_FLAGS_FSO)
6345                 gso_segs = DIV_ROUND_UP(skb->len - hdr_len,
6346                                         skb_shinfo(skb)->gso_size);
6347 #endif /* IXGBE_FCOE */
6348         else
6349                 gso_segs = 1;
6350
6351         /* multiply data chunks by size of headers */
6352         tx_buffer_info->bytecount = paylen + (gso_segs * hdr_len);
6353         tx_buffer_info->gso_segs = gso_segs;
6354         tx_buffer_info->skb = skb;
6355
6356         /* set the timestamp */
6357         first->time_stamp = jiffies;
6358
6359         /*
6360          * Force memory writes to complete before letting h/w
6361          * know there are new descriptors to fetch.  (Only
6362          * applicable for weak-ordered memory model archs,
6363          * such as IA-64).
6364          */
6365         wmb();
6366
6367         /* set next_to_watch value indicating a packet is present */
6368         first->next_to_watch = tx_desc;
6369
6370         /* notify HW of packet */
6371         writel(i, tx_ring->tail);
6372
6373         return;
6374 dma_error:
6375         dev_err(dev, "TX DMA map failed\n");
6376
6377         /* clear dma mappings for failed tx_buffer_info map */
6378         for (;;) {
6379                 tx_buffer_info = &tx_ring->tx_buffer_info[i];
6380                 ixgbe_unmap_tx_resource(tx_ring, tx_buffer_info);
6381                 if (tx_buffer_info == first)
6382                         break;
6383                 if (i == 0)
6384                         i = tx_ring->count;
6385                 i--;
6386         }
6387
6388         dev_kfree_skb_any(skb);
6389
6390         tx_ring->next_to_use = i;
6391 }
6392
6393 static void ixgbe_atr(struct ixgbe_ring *ring, struct sk_buff *skb,
6394                       u32 tx_flags, __be16 protocol)
6395 {
6396         struct ixgbe_q_vector *q_vector = ring->q_vector;
6397         union ixgbe_atr_hash_dword input = { .dword = 0 };
6398         union ixgbe_atr_hash_dword common = { .dword = 0 };
6399         union {
6400                 unsigned char *network;
6401                 struct iphdr *ipv4;
6402                 struct ipv6hdr *ipv6;
6403         } hdr;
6404         struct tcphdr *th;
6405         __be16 vlan_id;
6406
6407         /* if ring doesn't have a interrupt vector, cannot perform ATR */
6408         if (!q_vector)
6409                 return;
6410
6411         /* do nothing if sampling is disabled */
6412         if (!ring->atr_sample_rate)
6413                 return;
6414
6415         ring->atr_count++;
6416
6417         /* snag network header to get L4 type and address */
6418         hdr.network = skb_network_header(skb);
6419
6420         /* Currently only IPv4/IPv6 with TCP is supported */
6421         if ((protocol != __constant_htons(ETH_P_IPV6) ||
6422              hdr.ipv6->nexthdr != IPPROTO_TCP) &&
6423             (protocol != __constant_htons(ETH_P_IP) ||
6424              hdr.ipv4->protocol != IPPROTO_TCP))
6425                 return;
6426
6427         th = tcp_hdr(skb);
6428
6429         /* skip this packet since it is invalid or the socket is closing */
6430         if (!th || th->fin)
6431                 return;
6432
6433         /* sample on all syn packets or once every atr sample count */
6434         if (!th->syn && (ring->atr_count < ring->atr_sample_rate))
6435                 return;
6436
6437         /* reset sample count */
6438         ring->atr_count = 0;
6439
6440         vlan_id = htons(tx_flags >> IXGBE_TX_FLAGS_VLAN_SHIFT);
6441
6442         /*
6443          * src and dst are inverted, think how the receiver sees them
6444          *
6445          * The input is broken into two sections, a non-compressed section
6446          * containing vm_pool, vlan_id, and flow_type.  The rest of the data
6447          * is XORed together and stored in the compressed dword.
6448          */
6449         input.formatted.vlan_id = vlan_id;
6450
6451         /*
6452          * since src port and flex bytes occupy the same word XOR them together
6453          * and write the value to source port portion of compressed dword
6454          */
6455         if (tx_flags & (IXGBE_TX_FLAGS_SW_VLAN | IXGBE_TX_FLAGS_HW_VLAN))
6456                 common.port.src ^= th->dest ^ __constant_htons(ETH_P_8021Q);
6457         else
6458                 common.port.src ^= th->dest ^ protocol;
6459         common.port.dst ^= th->source;
6460
6461         if (protocol == __constant_htons(ETH_P_IP)) {
6462                 input.formatted.flow_type = IXGBE_ATR_FLOW_TYPE_TCPV4;
6463                 common.ip ^= hdr.ipv4->saddr ^ hdr.ipv4->daddr;
6464         } else {
6465                 input.formatted.flow_type = IXGBE_ATR_FLOW_TYPE_TCPV6;
6466                 common.ip ^= hdr.ipv6->saddr.s6_addr32[0] ^
6467                              hdr.ipv6->saddr.s6_addr32[1] ^
6468                              hdr.ipv6->saddr.s6_addr32[2] ^
6469                              hdr.ipv6->saddr.s6_addr32[3] ^
6470                              hdr.ipv6->daddr.s6_addr32[0] ^
6471                              hdr.ipv6->daddr.s6_addr32[1] ^
6472                              hdr.ipv6->daddr.s6_addr32[2] ^
6473                              hdr.ipv6->daddr.s6_addr32[3];
6474         }
6475
6476         /* This assumes the Rx queue and Tx queue are bound to the same CPU */
6477         ixgbe_fdir_add_signature_filter_82599(&q_vector->adapter->hw,
6478                                               input, common, ring->queue_index);
6479 }
6480
6481 static int __ixgbe_maybe_stop_tx(struct ixgbe_ring *tx_ring, u16 size)
6482 {
6483         netif_stop_subqueue(tx_ring->netdev, tx_ring->queue_index);
6484         /* Herbert's original patch had:
6485          *  smp_mb__after_netif_stop_queue();
6486          * but since that doesn't exist yet, just open code it. */
6487         smp_mb();
6488
6489         /* We need to check again in a case another CPU has just
6490          * made room available. */
6491         if (likely(ixgbe_desc_unused(tx_ring) < size))
6492                 return -EBUSY;
6493
6494         /* A reprieve! - use start_queue because it doesn't call schedule */
6495         netif_start_subqueue(tx_ring->netdev, tx_ring->queue_index);
6496         ++tx_ring->tx_stats.restart_queue;
6497         return 0;
6498 }
6499
6500 static inline int ixgbe_maybe_stop_tx(struct ixgbe_ring *tx_ring, u16 size)
6501 {
6502         if (likely(ixgbe_desc_unused(tx_ring) >= size))
6503                 return 0;
6504         return __ixgbe_maybe_stop_tx(tx_ring, size);
6505 }
6506
6507 static u16 ixgbe_select_queue(struct net_device *dev, struct sk_buff *skb)
6508 {
6509         struct ixgbe_adapter *adapter = netdev_priv(dev);
6510         int txq = skb_rx_queue_recorded(skb) ? skb_get_rx_queue(skb) :
6511                                                smp_processor_id();
6512 #ifdef IXGBE_FCOE
6513         __be16 protocol = vlan_get_protocol(skb);
6514
6515         if (((protocol == htons(ETH_P_FCOE)) ||
6516             (protocol == htons(ETH_P_FIP))) &&
6517             (adapter->flags & IXGBE_FLAG_FCOE_ENABLED)) {
6518                 txq &= (adapter->ring_feature[RING_F_FCOE].indices - 1);
6519                 txq += adapter->ring_feature[RING_F_FCOE].mask;
6520                 return txq;
6521         }
6522 #endif
6523
6524         if (adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE) {
6525                 while (unlikely(txq >= dev->real_num_tx_queues))
6526                         txq -= dev->real_num_tx_queues;
6527                 return txq;
6528         }
6529
6530         return skb_tx_hash(dev, skb);
6531 }
6532
6533 netdev_tx_t ixgbe_xmit_frame_ring(struct sk_buff *skb,
6534                           struct ixgbe_adapter *adapter,
6535                           struct ixgbe_ring *tx_ring)
6536 {
6537         struct ixgbe_tx_buffer *first;
6538         int tso;
6539         u32 tx_flags = 0;
6540 #if PAGE_SIZE > IXGBE_MAX_DATA_PER_TXD
6541         unsigned short f;
6542 #endif
6543         u16 count = TXD_USE_COUNT(skb_headlen(skb));
6544         __be16 protocol = skb->protocol;
6545         u8 hdr_len = 0;
6546
6547         /*
6548          * need: 1 descriptor per page * PAGE_SIZE/IXGBE_MAX_DATA_PER_TXD,
6549          *       + 1 desc for skb_head_len/IXGBE_MAX_DATA_PER_TXD,
6550          *       + 2 desc gap to keep tail from touching head,
6551          *       + 1 desc for context descriptor,
6552          * otherwise try next time
6553          */
6554 #if PAGE_SIZE > IXGBE_MAX_DATA_PER_TXD
6555         for (f = 0; f < skb_shinfo(skb)->nr_frags; f++)
6556                 count += TXD_USE_COUNT(skb_shinfo(skb)->frags[f].size);
6557 #else
6558         count += skb_shinfo(skb)->nr_frags;
6559 #endif
6560         if (ixgbe_maybe_stop_tx(tx_ring, count + 3)) {
6561                 tx_ring->tx_stats.tx_busy++;
6562                 return NETDEV_TX_BUSY;
6563         }
6564
6565 #ifdef CONFIG_PCI_IOV
6566         if (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED)
6567                 tx_flags |= IXGBE_TX_FLAGS_TXSW;
6568
6569 #endif
6570         /* if we have a HW VLAN tag being added default to the HW one */
6571         if (vlan_tx_tag_present(skb)) {
6572                 tx_flags |= vlan_tx_tag_get(skb) << IXGBE_TX_FLAGS_VLAN_SHIFT;
6573                 tx_flags |= IXGBE_TX_FLAGS_HW_VLAN;
6574         /* else if it is a SW VLAN check the next protocol and store the tag */
6575         } else if (protocol == __constant_htons(ETH_P_8021Q)) {
6576                 struct vlan_hdr *vhdr, _vhdr;
6577                 vhdr = skb_header_pointer(skb, ETH_HLEN, sizeof(_vhdr), &_vhdr);
6578                 if (!vhdr)
6579                         goto out_drop;
6580
6581                 protocol = vhdr->h_vlan_encapsulated_proto;
6582                 tx_flags |= ntohs(vhdr->h_vlan_TCI) << IXGBE_TX_FLAGS_VLAN_SHIFT;
6583                 tx_flags |= IXGBE_TX_FLAGS_SW_VLAN;
6584         }
6585
6586         if ((adapter->flags & IXGBE_FLAG_DCB_ENABLED) &&
6587             ((tx_flags & (IXGBE_TX_FLAGS_HW_VLAN | IXGBE_TX_FLAGS_SW_VLAN)) ||
6588              (skb->priority != TC_PRIO_CONTROL))) {
6589                 tx_flags &= ~IXGBE_TX_FLAGS_VLAN_PRIO_MASK;
6590                 tx_flags |= tx_ring->dcb_tc <<
6591                             IXGBE_TX_FLAGS_VLAN_PRIO_SHIFT;
6592                 if (tx_flags & IXGBE_TX_FLAGS_SW_VLAN) {
6593                         struct vlan_ethhdr *vhdr;
6594                         if (skb_header_cloned(skb) &&
6595                             pskb_expand_head(skb, 0, 0, GFP_ATOMIC))
6596                                 goto out_drop;
6597                         vhdr = (struct vlan_ethhdr *)skb->data;
6598                         vhdr->h_vlan_TCI = htons(tx_flags >>
6599                                                  IXGBE_TX_FLAGS_VLAN_SHIFT);
6600                 } else {
6601                         tx_flags |= IXGBE_TX_FLAGS_HW_VLAN;
6602                 }
6603         }
6604
6605         /* record the location of the first descriptor for this packet */
6606         first = &tx_ring->tx_buffer_info[tx_ring->next_to_use];
6607
6608 #ifdef IXGBE_FCOE
6609         /* setup tx offload for FCoE */
6610         if ((protocol == __constant_htons(ETH_P_FCOE)) &&
6611             (adapter->flags & IXGBE_FLAG_FCOE_ENABLED)) {
6612                 tso = ixgbe_fso(tx_ring, skb, tx_flags, &hdr_len);
6613                 if (tso < 0)
6614                         goto out_drop;
6615                 else if (tso)
6616                         tx_flags |= IXGBE_TX_FLAGS_FSO |
6617                                     IXGBE_TX_FLAGS_FCOE;
6618                 else
6619                         tx_flags |= IXGBE_TX_FLAGS_FCOE;
6620
6621                 goto xmit_fcoe;
6622         }
6623
6624 #endif /* IXGBE_FCOE */
6625         /* setup IPv4/IPv6 offloads */
6626         if (protocol == __constant_htons(ETH_P_IP))
6627                 tx_flags |= IXGBE_TX_FLAGS_IPV4;
6628
6629         tso = ixgbe_tso(tx_ring, skb, tx_flags, protocol, &hdr_len);
6630         if (tso < 0)
6631                 goto out_drop;
6632         else if (tso)
6633                 tx_flags |= IXGBE_TX_FLAGS_TSO;
6634         else if (ixgbe_tx_csum(tx_ring, skb, tx_flags, protocol))
6635                 tx_flags |= IXGBE_TX_FLAGS_CSUM;
6636
6637         /* add the ATR filter if ATR is on */
6638         if (test_bit(__IXGBE_TX_FDIR_INIT_DONE, &tx_ring->state))
6639                 ixgbe_atr(tx_ring, skb, tx_flags, protocol);
6640
6641 #ifdef IXGBE_FCOE
6642 xmit_fcoe:
6643 #endif /* IXGBE_FCOE */
6644         ixgbe_tx_map(tx_ring, skb, first, tx_flags, hdr_len);
6645
6646         ixgbe_maybe_stop_tx(tx_ring, DESC_NEEDED);
6647
6648         return NETDEV_TX_OK;
6649
6650 out_drop:
6651         dev_kfree_skb_any(skb);
6652         return NETDEV_TX_OK;
6653 }
6654
6655 static netdev_tx_t ixgbe_xmit_frame(struct sk_buff *skb, struct net_device *netdev)
6656 {
6657         struct ixgbe_adapter *adapter = netdev_priv(netdev);
6658         struct ixgbe_ring *tx_ring;
6659
6660         tx_ring = adapter->tx_ring[skb->queue_mapping];
6661         return ixgbe_xmit_frame_ring(skb, adapter, tx_ring);
6662 }
6663
6664 /**
6665  * ixgbe_set_mac - Change the Ethernet Address of the NIC
6666  * @netdev: network interface device structure
6667  * @p: pointer to an address structure
6668  *
6669  * Returns 0 on success, negative on failure
6670  **/
6671 static int ixgbe_set_mac(struct net_device *netdev, void *p)
6672 {
6673         struct ixgbe_adapter *adapter = netdev_priv(netdev);
6674         struct ixgbe_hw *hw = &adapter->hw;
6675         struct sockaddr *addr = p;
6676
6677         if (!is_valid_ether_addr(addr->sa_data))
6678                 return -EADDRNOTAVAIL;
6679
6680         memcpy(netdev->dev_addr, addr->sa_data, netdev->addr_len);
6681         memcpy(hw->mac.addr, addr->sa_data, netdev->addr_len);
6682
6683         hw->mac.ops.set_rar(hw, 0, hw->mac.addr, adapter->num_vfs,
6684                             IXGBE_RAH_AV);
6685
6686         return 0;
6687 }
6688
6689 static int
6690 ixgbe_mdio_read(struct net_device *netdev, int prtad, int devad, u16 addr)
6691 {
6692         struct ixgbe_adapter *adapter = netdev_priv(netdev);
6693         struct ixgbe_hw *hw = &adapter->hw;
6694         u16 value;
6695         int rc;
6696
6697         if (prtad != hw->phy.mdio.prtad)
6698                 return -EINVAL;
6699         rc = hw->phy.ops.read_reg(hw, addr, devad, &value);
6700         if (!rc)
6701                 rc = value;
6702         return rc;
6703 }
6704
6705 static int ixgbe_mdio_write(struct net_device *netdev, int prtad, int devad,
6706                             u16 addr, u16 value)
6707 {
6708         struct ixgbe_adapter *adapter = netdev_priv(netdev);
6709         struct ixgbe_hw *hw = &adapter->hw;
6710
6711         if (prtad != hw->phy.mdio.prtad)
6712                 return -EINVAL;
6713         return hw->phy.ops.write_reg(hw, addr, devad, value);
6714 }
6715
6716 static int ixgbe_ioctl(struct net_device *netdev, struct ifreq *req, int cmd)
6717 {
6718         struct ixgbe_adapter *adapter = netdev_priv(netdev);
6719
6720         return mdio_mii_ioctl(&adapter->hw.phy.mdio, if_mii(req), cmd);
6721 }
6722
6723 /**
6724  * ixgbe_add_sanmac_netdev - Add the SAN MAC address to the corresponding
6725  * netdev->dev_addrs
6726  * @netdev: network interface device structure
6727  *
6728  * Returns non-zero on failure
6729  **/
6730 static int ixgbe_add_sanmac_netdev(struct net_device *dev)
6731 {
6732         int err = 0;
6733         struct ixgbe_adapter *adapter = netdev_priv(dev);
6734         struct ixgbe_mac_info *mac = &adapter->hw.mac;
6735
6736         if (is_valid_ether_addr(mac->san_addr)) {
6737                 rtnl_lock();
6738                 err = dev_addr_add(dev, mac->san_addr, NETDEV_HW_ADDR_T_SAN);
6739                 rtnl_unlock();
6740         }
6741         return err;
6742 }
6743
6744 /**
6745  * ixgbe_del_sanmac_netdev - Removes the SAN MAC address to the corresponding
6746  * netdev->dev_addrs
6747  * @netdev: network interface device structure
6748  *
6749  * Returns non-zero on failure
6750  **/
6751 static int ixgbe_del_sanmac_netdev(struct net_device *dev)
6752 {
6753         int err = 0;
6754         struct ixgbe_adapter *adapter = netdev_priv(dev);
6755         struct ixgbe_mac_info *mac = &adapter->hw.mac;
6756
6757         if (is_valid_ether_addr(mac->san_addr)) {
6758                 rtnl_lock();
6759                 err = dev_addr_del(dev, mac->san_addr, NETDEV_HW_ADDR_T_SAN);
6760                 rtnl_unlock();
6761         }
6762         return err;
6763 }
6764
6765 #ifdef CONFIG_NET_POLL_CONTROLLER
6766 /*
6767  * Polling 'interrupt' - used by things like netconsole to send skbs
6768  * without having to re-enable interrupts. It's not called while
6769  * the interrupt routine is executing.
6770  */
6771 static void ixgbe_netpoll(struct net_device *netdev)
6772 {
6773         struct ixgbe_adapter *adapter = netdev_priv(netdev);
6774         int i;
6775
6776         /* if interface is down do nothing */
6777         if (test_bit(__IXGBE_DOWN, &adapter->state))
6778                 return;
6779
6780         adapter->flags |= IXGBE_FLAG_IN_NETPOLL;
6781         if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED) {
6782                 int num_q_vectors = adapter->num_msix_vectors - NON_Q_VECTORS;
6783                 for (i = 0; i < num_q_vectors; i++) {
6784                         struct ixgbe_q_vector *q_vector = adapter->q_vector[i];
6785                         ixgbe_msix_clean_rings(0, q_vector);
6786                 }
6787         } else {
6788                 ixgbe_intr(adapter->pdev->irq, netdev);
6789         }
6790         adapter->flags &= ~IXGBE_FLAG_IN_NETPOLL;
6791 }
6792 #endif
6793
6794 static struct rtnl_link_stats64 *ixgbe_get_stats64(struct net_device *netdev,
6795                                                    struct rtnl_link_stats64 *stats)
6796 {
6797         struct ixgbe_adapter *adapter = netdev_priv(netdev);
6798         int i;
6799
6800         rcu_read_lock();
6801         for (i = 0; i < adapter->num_rx_queues; i++) {
6802                 struct ixgbe_ring *ring = ACCESS_ONCE(adapter->rx_ring[i]);
6803                 u64 bytes, packets;
6804                 unsigned int start;
6805
6806                 if (ring) {
6807                         do {
6808                                 start = u64_stats_fetch_begin_bh(&ring->syncp);
6809                                 packets = ring->stats.packets;
6810                                 bytes   = ring->stats.bytes;
6811                         } while (u64_stats_fetch_retry_bh(&ring->syncp, start));
6812                         stats->rx_packets += packets;
6813                         stats->rx_bytes   += bytes;
6814                 }
6815         }
6816
6817         for (i = 0; i < adapter->num_tx_queues; i++) {
6818                 struct ixgbe_ring *ring = ACCESS_ONCE(adapter->tx_ring[i]);
6819                 u64 bytes, packets;
6820                 unsigned int start;
6821
6822                 if (ring) {
6823                         do {
6824                                 start = u64_stats_fetch_begin_bh(&ring->syncp);
6825                                 packets = ring->stats.packets;
6826                                 bytes   = ring->stats.bytes;
6827                         } while (u64_stats_fetch_retry_bh(&ring->syncp, start));
6828                         stats->tx_packets += packets;
6829                         stats->tx_bytes   += bytes;
6830                 }
6831         }
6832         rcu_read_unlock();
6833         /* following stats updated by ixgbe_watchdog_task() */
6834         stats->multicast        = netdev->stats.multicast;
6835         stats->rx_errors        = netdev->stats.rx_errors;
6836         stats->rx_length_errors = netdev->stats.rx_length_errors;
6837         stats->rx_crc_errors    = netdev->stats.rx_crc_errors;
6838         stats->rx_missed_errors = netdev->stats.rx_missed_errors;
6839         return stats;
6840 }
6841
6842 /* ixgbe_validate_rtr - verify 802.1Qp to Rx packet buffer mapping is valid.
6843  * #adapter: pointer to ixgbe_adapter
6844  * @tc: number of traffic classes currently enabled
6845  *
6846  * Configure a valid 802.1Qp to Rx packet buffer mapping ie confirm
6847  * 802.1Q priority maps to a packet buffer that exists.
6848  */
6849 static void ixgbe_validate_rtr(struct ixgbe_adapter *adapter, u8 tc)
6850 {
6851         struct ixgbe_hw *hw = &adapter->hw;
6852         u32 reg, rsave;
6853         int i;
6854
6855         /* 82598 have a static priority to TC mapping that can not
6856          * be changed so no validation is needed.
6857          */
6858         if (hw->mac.type == ixgbe_mac_82598EB)
6859                 return;
6860
6861         reg = IXGBE_READ_REG(hw, IXGBE_RTRUP2TC);
6862         rsave = reg;
6863
6864         for (i = 0; i < MAX_TRAFFIC_CLASS; i++) {
6865                 u8 up2tc = reg >> (i * IXGBE_RTRUP2TC_UP_SHIFT);
6866
6867                 /* If up2tc is out of bounds default to zero */
6868                 if (up2tc > tc)
6869                         reg &= ~(0x7 << IXGBE_RTRUP2TC_UP_SHIFT);
6870         }
6871
6872         if (reg != rsave)
6873                 IXGBE_WRITE_REG(hw, IXGBE_RTRUP2TC, reg);
6874
6875         return;
6876 }
6877
6878
6879 /* ixgbe_setup_tc - routine to configure net_device for multiple traffic
6880  * classes.
6881  *
6882  * @netdev: net device to configure
6883  * @tc: number of traffic classes to enable
6884  */
6885 int ixgbe_setup_tc(struct net_device *dev, u8 tc)
6886 {
6887         struct ixgbe_adapter *adapter = netdev_priv(dev);
6888         struct ixgbe_hw *hw = &adapter->hw;
6889
6890         /* Multiple traffic classes requires multiple queues */
6891         if (!(adapter->flags & IXGBE_FLAG_MSIX_ENABLED)) {
6892                 e_err(drv, "Enable failed, needs MSI-X\n");
6893                 return -EINVAL;
6894         }
6895
6896         /* Hardware supports up to 8 traffic classes */
6897         if (tc > MAX_TRAFFIC_CLASS ||
6898             (hw->mac.type == ixgbe_mac_82598EB && tc < MAX_TRAFFIC_CLASS))
6899                 return -EINVAL;
6900
6901         /* Hardware has to reinitialize queues and interrupts to
6902          * match packet buffer alignment. Unfortunantly, the
6903          * hardware is not flexible enough to do this dynamically.
6904          */
6905         if (netif_running(dev))
6906                 ixgbe_close(dev);
6907         ixgbe_clear_interrupt_scheme(adapter);
6908
6909         if (tc) {
6910                 netdev_set_num_tc(dev, tc);
6911                 adapter->last_lfc_mode = adapter->hw.fc.current_mode;
6912
6913                 adapter->flags |= IXGBE_FLAG_DCB_ENABLED;
6914                 adapter->flags &= ~IXGBE_FLAG_FDIR_HASH_CAPABLE;
6915
6916                 if (adapter->hw.mac.type == ixgbe_mac_82598EB)
6917                         adapter->hw.fc.requested_mode = ixgbe_fc_none;
6918         } else {
6919                 netdev_reset_tc(dev);
6920
6921                 adapter->hw.fc.requested_mode = adapter->last_lfc_mode;
6922
6923                 adapter->flags &= ~IXGBE_FLAG_DCB_ENABLED;
6924                 adapter->flags |= IXGBE_FLAG_FDIR_HASH_CAPABLE;
6925
6926                 adapter->temp_dcb_cfg.pfc_mode_enable = false;
6927                 adapter->dcb_cfg.pfc_mode_enable = false;
6928         }
6929
6930         ixgbe_init_interrupt_scheme(adapter);
6931         ixgbe_validate_rtr(adapter, tc);
6932         if (netif_running(dev))
6933                 ixgbe_open(dev);
6934
6935         return 0;
6936 }
6937
6938 void ixgbe_do_reset(struct net_device *netdev)
6939 {
6940         struct ixgbe_adapter *adapter = netdev_priv(netdev);
6941
6942         if (netif_running(netdev))
6943                 ixgbe_reinit_locked(adapter);
6944         else
6945                 ixgbe_reset(adapter);
6946 }
6947
6948 static u32 ixgbe_fix_features(struct net_device *netdev, u32 data)
6949 {
6950         struct ixgbe_adapter *adapter = netdev_priv(netdev);
6951
6952 #ifdef CONFIG_DCB
6953         if (adapter->flags & IXGBE_FLAG_DCB_ENABLED)
6954                 data &= ~NETIF_F_HW_VLAN_RX;
6955 #endif
6956
6957         /* return error if RXHASH is being enabled when RSS is not supported */
6958         if (!(adapter->flags & IXGBE_FLAG_RSS_ENABLED))
6959                 data &= ~NETIF_F_RXHASH;
6960
6961         /* If Rx checksum is disabled, then RSC/LRO should also be disabled */
6962         if (!(data & NETIF_F_RXCSUM))
6963                 data &= ~NETIF_F_LRO;
6964
6965         /* Turn off LRO if not RSC capable or invalid ITR settings */
6966         if (!(adapter->flags2 & IXGBE_FLAG2_RSC_CAPABLE)) {
6967                 data &= ~NETIF_F_LRO;
6968         } else if (!(adapter->flags2 & IXGBE_FLAG2_RSC_ENABLED) &&
6969                    (adapter->rx_itr_setting != 1 &&
6970                     adapter->rx_itr_setting > IXGBE_MAX_RSC_INT_RATE)) {
6971                 data &= ~NETIF_F_LRO;
6972                 e_info(probe, "rx-usecs set too low, not enabling RSC\n");
6973         }
6974
6975         return data;
6976 }
6977
6978 static int ixgbe_set_features(struct net_device *netdev, u32 data)
6979 {
6980         struct ixgbe_adapter *adapter = netdev_priv(netdev);
6981         bool need_reset = false;
6982
6983         /* If Rx checksum is disabled, then RSC/LRO should also be disabled */
6984         if (!(data & NETIF_F_RXCSUM))
6985                 adapter->flags &= ~IXGBE_FLAG_RX_CSUM_ENABLED;
6986         else
6987                 adapter->flags |= IXGBE_FLAG_RX_CSUM_ENABLED;
6988
6989         /* Make sure RSC matches LRO, reset if change */
6990         if (!!(data & NETIF_F_LRO) !=
6991              !!(adapter->flags2 & IXGBE_FLAG2_RSC_ENABLED)) {
6992                 adapter->flags2 ^= IXGBE_FLAG2_RSC_ENABLED;
6993                 switch (adapter->hw.mac.type) {
6994                 case ixgbe_mac_X540:
6995                 case ixgbe_mac_82599EB:
6996                         need_reset = true;
6997                         break;
6998                 default:
6999                         break;
7000                 }
7001         }
7002
7003         /*
7004          * Check if Flow Director n-tuple support was enabled or disabled.  If
7005          * the state changed, we need to reset.
7006          */
7007         if (!(adapter->flags & IXGBE_FLAG_FDIR_PERFECT_CAPABLE)) {
7008                 /* turn off ATR, enable perfect filters and reset */
7009                 if (data & NETIF_F_NTUPLE) {
7010                         adapter->flags &= ~IXGBE_FLAG_FDIR_HASH_CAPABLE;
7011                         adapter->flags |= IXGBE_FLAG_FDIR_PERFECT_CAPABLE;
7012                         need_reset = true;
7013                 }
7014         } else if (!(data & NETIF_F_NTUPLE)) {
7015                 /* turn off Flow Director, set ATR and reset */
7016                 adapter->flags &= ~IXGBE_FLAG_FDIR_PERFECT_CAPABLE;
7017                 if ((adapter->flags &  IXGBE_FLAG_RSS_ENABLED) &&
7018                     !(adapter->flags &  IXGBE_FLAG_DCB_ENABLED))
7019                         adapter->flags |= IXGBE_FLAG_FDIR_HASH_CAPABLE;
7020                 need_reset = true;
7021         }
7022
7023         if (need_reset)
7024                 ixgbe_do_reset(netdev);
7025
7026         return 0;
7027
7028 }
7029
7030 static const struct net_device_ops ixgbe_netdev_ops = {
7031         .ndo_open               = ixgbe_open,
7032         .ndo_stop               = ixgbe_close,
7033         .ndo_start_xmit         = ixgbe_xmit_frame,
7034         .ndo_select_queue       = ixgbe_select_queue,
7035         .ndo_set_rx_mode        = ixgbe_set_rx_mode,
7036         .ndo_validate_addr      = eth_validate_addr,
7037         .ndo_set_mac_address    = ixgbe_set_mac,
7038         .ndo_change_mtu         = ixgbe_change_mtu,
7039         .ndo_tx_timeout         = ixgbe_tx_timeout,
7040         .ndo_vlan_rx_add_vid    = ixgbe_vlan_rx_add_vid,
7041         .ndo_vlan_rx_kill_vid   = ixgbe_vlan_rx_kill_vid,
7042         .ndo_do_ioctl           = ixgbe_ioctl,
7043         .ndo_set_vf_mac         = ixgbe_ndo_set_vf_mac,
7044         .ndo_set_vf_vlan        = ixgbe_ndo_set_vf_vlan,
7045         .ndo_set_vf_tx_rate     = ixgbe_ndo_set_vf_bw,
7046         .ndo_get_vf_config      = ixgbe_ndo_get_vf_config,
7047         .ndo_get_stats64        = ixgbe_get_stats64,
7048         .ndo_setup_tc           = ixgbe_setup_tc,
7049 #ifdef CONFIG_NET_POLL_CONTROLLER
7050         .ndo_poll_controller    = ixgbe_netpoll,
7051 #endif
7052 #ifdef IXGBE_FCOE
7053         .ndo_fcoe_ddp_setup = ixgbe_fcoe_ddp_get,
7054         .ndo_fcoe_ddp_target = ixgbe_fcoe_ddp_target,
7055         .ndo_fcoe_ddp_done = ixgbe_fcoe_ddp_put,
7056         .ndo_fcoe_enable = ixgbe_fcoe_enable,
7057         .ndo_fcoe_disable = ixgbe_fcoe_disable,
7058         .ndo_fcoe_get_wwn = ixgbe_fcoe_get_wwn,
7059 #endif /* IXGBE_FCOE */
7060         .ndo_set_features = ixgbe_set_features,
7061         .ndo_fix_features = ixgbe_fix_features,
7062 };
7063
7064 static void __devinit ixgbe_probe_vf(struct ixgbe_adapter *adapter,
7065                            const struct ixgbe_info *ii)
7066 {
7067 #ifdef CONFIG_PCI_IOV
7068         struct ixgbe_hw *hw = &adapter->hw;
7069         int err;
7070         int num_vf_macvlans, i;
7071         struct vf_macvlans *mv_list;
7072
7073         if (hw->mac.type == ixgbe_mac_82598EB || !max_vfs)
7074                 return;
7075
7076         /* The 82599 supports up to 64 VFs per physical function
7077          * but this implementation limits allocation to 63 so that
7078          * basic networking resources are still available to the
7079          * physical function
7080          */
7081         adapter->num_vfs = (max_vfs > 63) ? 63 : max_vfs;
7082         adapter->flags |= IXGBE_FLAG_SRIOV_ENABLED;
7083         err = pci_enable_sriov(adapter->pdev, adapter->num_vfs);
7084         if (err) {
7085                 e_err(probe, "Failed to enable PCI sriov: %d\n", err);
7086                 goto err_novfs;
7087         }
7088
7089         num_vf_macvlans = hw->mac.num_rar_entries -
7090                 (IXGBE_MAX_PF_MACVLANS + 1 + adapter->num_vfs);
7091
7092         adapter->mv_list = mv_list = kcalloc(num_vf_macvlans,
7093                                              sizeof(struct vf_macvlans),
7094                                              GFP_KERNEL);
7095         if (mv_list) {
7096                 /* Initialize list of VF macvlans */
7097                 INIT_LIST_HEAD(&adapter->vf_mvs.l);
7098                 for (i = 0; i < num_vf_macvlans; i++) {
7099                         mv_list->vf = -1;
7100                         mv_list->free = true;
7101                         mv_list->rar_entry = hw->mac.num_rar_entries -
7102                                 (i + adapter->num_vfs + 1);
7103                         list_add(&mv_list->l, &adapter->vf_mvs.l);
7104                         mv_list++;
7105                 }
7106         }
7107
7108         /* If call to enable VFs succeeded then allocate memory
7109          * for per VF control structures.
7110          */
7111         adapter->vfinfo =
7112                 kcalloc(adapter->num_vfs,
7113                         sizeof(struct vf_data_storage), GFP_KERNEL);
7114         if (adapter->vfinfo) {
7115                 /* Now that we're sure SR-IOV is enabled
7116                  * and memory allocated set up the mailbox parameters
7117                  */
7118                 ixgbe_init_mbx_params_pf(hw);
7119                 memcpy(&hw->mbx.ops, ii->mbx_ops,
7120                        sizeof(hw->mbx.ops));
7121
7122                 /* Disable RSC when in SR-IOV mode */
7123                 adapter->flags2 &= ~(IXGBE_FLAG2_RSC_CAPABLE |
7124                                      IXGBE_FLAG2_RSC_ENABLED);
7125                 return;
7126         }
7127
7128         /* Oh oh */
7129         e_err(probe, "Unable to allocate memory for VF Data Storage - "
7130               "SRIOV disabled\n");
7131         pci_disable_sriov(adapter->pdev);
7132
7133 err_novfs:
7134         adapter->flags &= ~IXGBE_FLAG_SRIOV_ENABLED;
7135         adapter->num_vfs = 0;
7136 #endif /* CONFIG_PCI_IOV */
7137 }
7138
7139 /**
7140  * ixgbe_probe - Device Initialization Routine
7141  * @pdev: PCI device information struct
7142  * @ent: entry in ixgbe_pci_tbl
7143  *
7144  * Returns 0 on success, negative on failure
7145  *
7146  * ixgbe_probe initializes an adapter identified by a pci_dev structure.
7147  * The OS initialization, configuring of the adapter private structure,
7148  * and a hardware reset occur.
7149  **/
7150 static int __devinit ixgbe_probe(struct pci_dev *pdev,
7151                                  const struct pci_device_id *ent)
7152 {
7153         struct net_device *netdev;
7154         struct ixgbe_adapter *adapter = NULL;
7155         struct ixgbe_hw *hw;
7156         const struct ixgbe_info *ii = ixgbe_info_tbl[ent->driver_data];
7157         static int cards_found;
7158         int i, err, pci_using_dac;
7159         u8 part_str[IXGBE_PBANUM_LENGTH];
7160         unsigned int indices = num_possible_cpus();
7161 #ifdef IXGBE_FCOE
7162         u16 device_caps;
7163 #endif
7164         u32 eec;
7165
7166         /* Catch broken hardware that put the wrong VF device ID in
7167          * the PCIe SR-IOV capability.
7168          */
7169         if (pdev->is_virtfn) {
7170                 WARN(1, KERN_ERR "%s (%hx:%hx) should not be a VF!\n",
7171                      pci_name(pdev), pdev->vendor, pdev->device);
7172                 return -EINVAL;
7173         }
7174
7175         err = pci_enable_device_mem(pdev);
7176         if (err)
7177                 return err;
7178
7179         if (!dma_set_mask(&pdev->dev, DMA_BIT_MASK(64)) &&
7180             !dma_set_coherent_mask(&pdev->dev, DMA_BIT_MASK(64))) {
7181                 pci_using_dac = 1;
7182         } else {
7183                 err = dma_set_mask(&pdev->dev, DMA_BIT_MASK(32));
7184                 if (err) {
7185                         err = dma_set_coherent_mask(&pdev->dev,
7186                                                     DMA_BIT_MASK(32));
7187                         if (err) {
7188                                 dev_err(&pdev->dev,
7189                                         "No usable DMA configuration, aborting\n");
7190                                 goto err_dma;
7191                         }
7192                 }
7193                 pci_using_dac = 0;
7194         }
7195
7196         err = pci_request_selected_regions(pdev, pci_select_bars(pdev,
7197                                            IORESOURCE_MEM), ixgbe_driver_name);
7198         if (err) {
7199                 dev_err(&pdev->dev,
7200                         "pci_request_selected_regions failed 0x%x\n", err);
7201                 goto err_pci_reg;
7202         }
7203
7204         pci_enable_pcie_error_reporting(pdev);
7205
7206         pci_set_master(pdev);
7207         pci_save_state(pdev);
7208
7209 #ifdef CONFIG_IXGBE_DCB
7210         indices *= MAX_TRAFFIC_CLASS;
7211 #endif
7212
7213         if (ii->mac == ixgbe_mac_82598EB)
7214                 indices = min_t(unsigned int, indices, IXGBE_MAX_RSS_INDICES);
7215         else
7216                 indices = min_t(unsigned int, indices, IXGBE_MAX_FDIR_INDICES);
7217
7218 #ifdef IXGBE_FCOE
7219         indices += min_t(unsigned int, num_possible_cpus(),
7220                          IXGBE_MAX_FCOE_INDICES);
7221 #endif
7222         netdev = alloc_etherdev_mq(sizeof(struct ixgbe_adapter), indices);
7223         if (!netdev) {
7224                 err = -ENOMEM;
7225                 goto err_alloc_etherdev;
7226         }
7227
7228         SET_NETDEV_DEV(netdev, &pdev->dev);
7229
7230         adapter = netdev_priv(netdev);
7231         pci_set_drvdata(pdev, adapter);
7232
7233         adapter->netdev = netdev;
7234         adapter->pdev = pdev;
7235         hw = &adapter->hw;
7236         hw->back = adapter;
7237         adapter->msg_enable = (1 << DEFAULT_DEBUG_LEVEL_SHIFT) - 1;
7238
7239         hw->hw_addr = ioremap(pci_resource_start(pdev, 0),
7240                               pci_resource_len(pdev, 0));
7241         if (!hw->hw_addr) {
7242                 err = -EIO;
7243                 goto err_ioremap;
7244         }
7245
7246         for (i = 1; i <= 5; i++) {
7247                 if (pci_resource_len(pdev, i) == 0)
7248                         continue;
7249         }
7250
7251         netdev->netdev_ops = &ixgbe_netdev_ops;
7252         ixgbe_set_ethtool_ops(netdev);
7253         netdev->watchdog_timeo = 5 * HZ;
7254         strncpy(netdev->name, pci_name(pdev), sizeof(netdev->name) - 1);
7255
7256         adapter->bd_number = cards_found;
7257
7258         /* Setup hw api */
7259         memcpy(&hw->mac.ops, ii->mac_ops, sizeof(hw->mac.ops));
7260         hw->mac.type  = ii->mac;
7261
7262         /* EEPROM */
7263         memcpy(&hw->eeprom.ops, ii->eeprom_ops, sizeof(hw->eeprom.ops));
7264         eec = IXGBE_READ_REG(hw, IXGBE_EEC);
7265         /* If EEPROM is valid (bit 8 = 1), use default otherwise use bit bang */
7266         if (!(eec & (1 << 8)))
7267                 hw->eeprom.ops.read = &ixgbe_read_eeprom_bit_bang_generic;
7268
7269         /* PHY */
7270         memcpy(&hw->phy.ops, ii->phy_ops, sizeof(hw->phy.ops));
7271         hw->phy.sfp_type = ixgbe_sfp_type_unknown;
7272         /* ixgbe_identify_phy_generic will set prtad and mmds properly */
7273         hw->phy.mdio.prtad = MDIO_PRTAD_NONE;
7274         hw->phy.mdio.mmds = 0;
7275         hw->phy.mdio.mode_support = MDIO_SUPPORTS_C45 | MDIO_EMULATE_C22;
7276         hw->phy.mdio.dev = netdev;
7277         hw->phy.mdio.mdio_read = ixgbe_mdio_read;
7278         hw->phy.mdio.mdio_write = ixgbe_mdio_write;
7279
7280         ii->get_invariants(hw);
7281
7282         /* setup the private structure */
7283         err = ixgbe_sw_init(adapter);
7284         if (err)
7285                 goto err_sw_init;
7286
7287         /* Make it possible the adapter to be woken up via WOL */
7288         switch (adapter->hw.mac.type) {
7289         case ixgbe_mac_82599EB:
7290         case ixgbe_mac_X540:
7291                 IXGBE_WRITE_REG(&adapter->hw, IXGBE_WUS, ~0);
7292                 break;
7293         default:
7294                 break;
7295         }
7296
7297         /*
7298          * If there is a fan on this device and it has failed log the
7299          * failure.
7300          */
7301         if (adapter->flags & IXGBE_FLAG_FAN_FAIL_CAPABLE) {
7302                 u32 esdp = IXGBE_READ_REG(hw, IXGBE_ESDP);
7303                 if (esdp & IXGBE_ESDP_SDP1)
7304                         e_crit(probe, "Fan has stopped, replace the adapter\n");
7305         }
7306
7307         /* reset_hw fills in the perm_addr as well */
7308         hw->phy.reset_if_overtemp = true;
7309         err = hw->mac.ops.reset_hw(hw);
7310         hw->phy.reset_if_overtemp = false;
7311         if (err == IXGBE_ERR_SFP_NOT_PRESENT &&
7312             hw->mac.type == ixgbe_mac_82598EB) {
7313                 err = 0;
7314         } else if (err == IXGBE_ERR_SFP_NOT_SUPPORTED) {
7315                 e_dev_err("failed to load because an unsupported SFP+ "
7316                           "module type was detected.\n");
7317                 e_dev_err("Reload the driver after installing a supported "
7318                           "module.\n");
7319                 goto err_sw_init;
7320         } else if (err) {
7321                 e_dev_err("HW Init failed: %d\n", err);
7322                 goto err_sw_init;
7323         }
7324
7325         ixgbe_probe_vf(adapter, ii);
7326
7327         netdev->features = NETIF_F_SG |
7328                            NETIF_F_IP_CSUM |
7329                            NETIF_F_IPV6_CSUM |
7330                            NETIF_F_HW_VLAN_TX |
7331                            NETIF_F_HW_VLAN_RX |
7332                            NETIF_F_HW_VLAN_FILTER |
7333                            NETIF_F_TSO |
7334                            NETIF_F_TSO6 |
7335                            NETIF_F_RXHASH |
7336                            NETIF_F_RXCSUM;
7337
7338         netdev->hw_features = netdev->features;
7339
7340         switch (adapter->hw.mac.type) {
7341         case ixgbe_mac_82599EB:
7342         case ixgbe_mac_X540:
7343                 netdev->features |= NETIF_F_SCTP_CSUM;
7344                 netdev->hw_features |= NETIF_F_SCTP_CSUM |
7345                                        NETIF_F_NTUPLE;
7346                 break;
7347         default:
7348                 break;
7349         }
7350
7351         netdev->vlan_features |= NETIF_F_TSO;
7352         netdev->vlan_features |= NETIF_F_TSO6;
7353         netdev->vlan_features |= NETIF_F_IP_CSUM;
7354         netdev->vlan_features |= NETIF_F_IPV6_CSUM;
7355         netdev->vlan_features |= NETIF_F_SG;
7356
7357         netdev->priv_flags |= IFF_UNICAST_FLT;
7358
7359         if (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED)
7360                 adapter->flags &= ~(IXGBE_FLAG_RSS_ENABLED |
7361                                     IXGBE_FLAG_DCB_ENABLED);
7362
7363 #ifdef CONFIG_IXGBE_DCB
7364         netdev->dcbnl_ops = &dcbnl_ops;
7365 #endif
7366
7367 #ifdef IXGBE_FCOE
7368         if (adapter->flags & IXGBE_FLAG_FCOE_CAPABLE) {
7369                 if (hw->mac.ops.get_device_caps) {
7370                         hw->mac.ops.get_device_caps(hw, &device_caps);
7371                         if (device_caps & IXGBE_DEVICE_CAPS_FCOE_OFFLOADS)
7372                                 adapter->flags &= ~IXGBE_FLAG_FCOE_CAPABLE;
7373                 }
7374         }
7375         if (adapter->flags & IXGBE_FLAG_FCOE_CAPABLE) {
7376                 netdev->vlan_features |= NETIF_F_FCOE_CRC;
7377                 netdev->vlan_features |= NETIF_F_FSO;
7378                 netdev->vlan_features |= NETIF_F_FCOE_MTU;
7379         }
7380 #endif /* IXGBE_FCOE */
7381         if (pci_using_dac) {
7382                 netdev->features |= NETIF_F_HIGHDMA;
7383                 netdev->vlan_features |= NETIF_F_HIGHDMA;
7384         }
7385
7386         if (adapter->flags2 & IXGBE_FLAG2_RSC_CAPABLE)
7387                 netdev->hw_features |= NETIF_F_LRO;
7388         if (adapter->flags2 & IXGBE_FLAG2_RSC_ENABLED)
7389                 netdev->features |= NETIF_F_LRO;
7390
7391         /* make sure the EEPROM is good */
7392         if (hw->eeprom.ops.validate_checksum(hw, NULL) < 0) {
7393                 e_dev_err("The EEPROM Checksum Is Not Valid\n");
7394                 err = -EIO;
7395                 goto err_eeprom;
7396         }
7397
7398         memcpy(netdev->dev_addr, hw->mac.perm_addr, netdev->addr_len);
7399         memcpy(netdev->perm_addr, hw->mac.perm_addr, netdev->addr_len);
7400
7401         if (ixgbe_validate_mac_addr(netdev->perm_addr)) {
7402                 e_dev_err("invalid MAC address\n");
7403                 err = -EIO;
7404                 goto err_eeprom;
7405         }
7406
7407         /* power down the optics for multispeed fiber and 82599 SFP+ fiber */
7408         if (hw->mac.ops.disable_tx_laser &&
7409             ((hw->phy.multispeed_fiber) ||
7410              ((hw->mac.ops.get_media_type(hw) == ixgbe_media_type_fiber) &&
7411               (hw->mac.type == ixgbe_mac_82599EB))))
7412                 hw->mac.ops.disable_tx_laser(hw);
7413
7414         setup_timer(&adapter->service_timer, &ixgbe_service_timer,
7415                     (unsigned long) adapter);
7416
7417         INIT_WORK(&adapter->service_task, ixgbe_service_task);
7418         clear_bit(__IXGBE_SERVICE_SCHED, &adapter->state);
7419
7420         err = ixgbe_init_interrupt_scheme(adapter);
7421         if (err)
7422                 goto err_sw_init;
7423
7424         if (!(adapter->flags & IXGBE_FLAG_RSS_ENABLED)) {
7425                 netdev->hw_features &= ~NETIF_F_RXHASH;
7426                 netdev->features &= ~NETIF_F_RXHASH;
7427         }
7428
7429         switch (pdev->device) {
7430         case IXGBE_DEV_ID_82599_SFP:
7431                 /* Only this subdevice supports WOL */
7432                 if (pdev->subsystem_device == IXGBE_SUBDEV_ID_82599_SFP)
7433                         adapter->wol = IXGBE_WUFC_MAG;
7434                 break;
7435         case IXGBE_DEV_ID_82599_COMBO_BACKPLANE:
7436                 /* All except this subdevice support WOL */
7437                 if (pdev->subsystem_device != IXGBE_SUBDEV_ID_82599_KX4_KR_MEZZ)
7438                         adapter->wol = IXGBE_WUFC_MAG;
7439                 break;
7440         case IXGBE_DEV_ID_82599_KX4:
7441                 adapter->wol = IXGBE_WUFC_MAG;
7442                 break;
7443         default:
7444                 adapter->wol = 0;
7445                 break;
7446         }
7447         device_set_wakeup_enable(&adapter->pdev->dev, adapter->wol);
7448
7449         /* pick up the PCI bus settings for reporting later */
7450         hw->mac.ops.get_bus_info(hw);
7451
7452         /* print bus type/speed/width info */
7453         e_dev_info("(PCI Express:%s:%s) %pM\n",
7454                    (hw->bus.speed == ixgbe_bus_speed_5000 ? "5.0GT/s" :
7455                     hw->bus.speed == ixgbe_bus_speed_2500 ? "2.5GT/s" :
7456                     "Unknown"),
7457                    (hw->bus.width == ixgbe_bus_width_pcie_x8 ? "Width x8" :
7458                     hw->bus.width == ixgbe_bus_width_pcie_x4 ? "Width x4" :
7459                     hw->bus.width == ixgbe_bus_width_pcie_x1 ? "Width x1" :
7460                     "Unknown"),
7461                    netdev->dev_addr);
7462
7463         err = ixgbe_read_pba_string_generic(hw, part_str, IXGBE_PBANUM_LENGTH);
7464         if (err)
7465                 strncpy(part_str, "Unknown", IXGBE_PBANUM_LENGTH);
7466         if (ixgbe_is_sfp(hw) && hw->phy.sfp_type != ixgbe_sfp_type_not_present)
7467                 e_dev_info("MAC: %d, PHY: %d, SFP+: %d, PBA No: %s\n",
7468                            hw->mac.type, hw->phy.type, hw->phy.sfp_type,
7469                            part_str);
7470         else
7471                 e_dev_info("MAC: %d, PHY: %d, PBA No: %s\n",
7472                            hw->mac.type, hw->phy.type, part_str);
7473
7474         if (hw->bus.width <= ixgbe_bus_width_pcie_x4) {
7475                 e_dev_warn("PCI-Express bandwidth available for this card is "
7476                            "not sufficient for optimal performance.\n");
7477                 e_dev_warn("For optimal performance a x8 PCI-Express slot "
7478                            "is required.\n");
7479         }
7480
7481         /* save off EEPROM version number */
7482         hw->eeprom.ops.read(hw, 0x29, &adapter->eeprom_version);
7483
7484         /* reset the hardware with the new settings */
7485         err = hw->mac.ops.start_hw(hw);
7486
7487         if (err == IXGBE_ERR_EEPROM_VERSION) {
7488                 /* We are running on a pre-production device, log a warning */
7489                 e_dev_warn("This device is a pre-production adapter/LOM. "
7490                            "Please be aware there may be issues associated "
7491                            "with your hardware.  If you are experiencing "
7492                            "problems please contact your Intel or hardware "
7493                            "representative who provided you with this "
7494                            "hardware.\n");
7495         }
7496         strcpy(netdev->name, "eth%d");
7497         err = register_netdev(netdev);
7498         if (err)
7499                 goto err_register;
7500
7501         /* carrier off reporting is important to ethtool even BEFORE open */
7502         netif_carrier_off(netdev);
7503
7504 #ifdef CONFIG_IXGBE_DCA
7505         if (dca_add_requester(&pdev->dev) == 0) {
7506                 adapter->flags |= IXGBE_FLAG_DCA_ENABLED;
7507                 ixgbe_setup_dca(adapter);
7508         }
7509 #endif
7510         if (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED) {
7511                 e_info(probe, "IOV is enabled with %d VFs\n", adapter->num_vfs);
7512                 for (i = 0; i < adapter->num_vfs; i++)
7513                         ixgbe_vf_configuration(pdev, (i | 0x10000000));
7514         }
7515
7516         /* Inform firmware of driver version */
7517         if (hw->mac.ops.set_fw_drv_ver)
7518                 hw->mac.ops.set_fw_drv_ver(hw, MAJ, MIN, BUILD,
7519                                            FW_CEM_UNUSED_VER);
7520
7521         /* add san mac addr to netdev */
7522         ixgbe_add_sanmac_netdev(netdev);
7523
7524         e_dev_info("Intel(R) 10 Gigabit Network Connection\n");
7525         cards_found++;
7526         return 0;
7527
7528 err_register:
7529         ixgbe_release_hw_control(adapter);
7530         ixgbe_clear_interrupt_scheme(adapter);
7531 err_sw_init:
7532 err_eeprom:
7533         if (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED)
7534                 ixgbe_disable_sriov(adapter);
7535         adapter->flags2 &= ~IXGBE_FLAG2_SEARCH_FOR_SFP;
7536         iounmap(hw->hw_addr);
7537 err_ioremap:
7538         free_netdev(netdev);
7539 err_alloc_etherdev:
7540         pci_release_selected_regions(pdev,
7541                                      pci_select_bars(pdev, IORESOURCE_MEM));
7542 err_pci_reg:
7543 err_dma:
7544         pci_disable_device(pdev);
7545         return err;
7546 }
7547
7548 /**
7549  * ixgbe_remove - Device Removal Routine
7550  * @pdev: PCI device information struct
7551  *
7552  * ixgbe_remove is called by the PCI subsystem to alert the driver
7553  * that it should release a PCI device.  The could be caused by a
7554  * Hot-Plug event, or because the driver is going to be removed from
7555  * memory.
7556  **/
7557 static void __devexit ixgbe_remove(struct pci_dev *pdev)
7558 {
7559         struct ixgbe_adapter *adapter = pci_get_drvdata(pdev);
7560         struct net_device *netdev = adapter->netdev;
7561
7562         set_bit(__IXGBE_DOWN, &adapter->state);
7563         cancel_work_sync(&adapter->service_task);
7564
7565 #ifdef CONFIG_IXGBE_DCA
7566         if (adapter->flags & IXGBE_FLAG_DCA_ENABLED) {
7567                 adapter->flags &= ~IXGBE_FLAG_DCA_ENABLED;
7568                 dca_remove_requester(&pdev->dev);
7569                 IXGBE_WRITE_REG(&adapter->hw, IXGBE_DCA_CTRL, 1);
7570         }
7571
7572 #endif
7573 #ifdef IXGBE_FCOE
7574         if (adapter->flags & IXGBE_FLAG_FCOE_ENABLED)
7575                 ixgbe_cleanup_fcoe(adapter);
7576
7577 #endif /* IXGBE_FCOE */
7578
7579         /* remove the added san mac */
7580         ixgbe_del_sanmac_netdev(netdev);
7581
7582         if (netdev->reg_state == NETREG_REGISTERED)
7583                 unregister_netdev(netdev);
7584
7585         if (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED)
7586                 ixgbe_disable_sriov(adapter);
7587
7588         ixgbe_clear_interrupt_scheme(adapter);
7589
7590         ixgbe_release_hw_control(adapter);
7591
7592         iounmap(adapter->hw.hw_addr);
7593         pci_release_selected_regions(pdev, pci_select_bars(pdev,
7594                                      IORESOURCE_MEM));
7595
7596         e_dev_info("complete\n");
7597
7598         free_netdev(netdev);
7599
7600         pci_disable_pcie_error_reporting(pdev);
7601
7602         pci_disable_device(pdev);
7603 }
7604
7605 /**
7606  * ixgbe_io_error_detected - called when PCI error is detected
7607  * @pdev: Pointer to PCI device
7608  * @state: The current pci connection state
7609  *
7610  * This function is called after a PCI bus error affecting
7611  * this device has been detected.
7612  */
7613 static pci_ers_result_t ixgbe_io_error_detected(struct pci_dev *pdev,
7614                                                 pci_channel_state_t state)
7615 {
7616         struct ixgbe_adapter *adapter = pci_get_drvdata(pdev);
7617         struct net_device *netdev = adapter->netdev;
7618
7619         netif_device_detach(netdev);
7620
7621         if (state == pci_channel_io_perm_failure)
7622                 return PCI_ERS_RESULT_DISCONNECT;
7623
7624         if (netif_running(netdev))
7625                 ixgbe_down(adapter);
7626         pci_disable_device(pdev);
7627
7628         /* Request a slot reset. */
7629         return PCI_ERS_RESULT_NEED_RESET;
7630 }
7631
7632 /**
7633  * ixgbe_io_slot_reset - called after the pci bus has been reset.
7634  * @pdev: Pointer to PCI device
7635  *
7636  * Restart the card from scratch, as if from a cold-boot.
7637  */
7638 static pci_ers_result_t ixgbe_io_slot_reset(struct pci_dev *pdev)
7639 {
7640         struct ixgbe_adapter *adapter = pci_get_drvdata(pdev);
7641         pci_ers_result_t result;
7642         int err;
7643
7644         if (pci_enable_device_mem(pdev)) {
7645                 e_err(probe, "Cannot re-enable PCI device after reset.\n");
7646                 result = PCI_ERS_RESULT_DISCONNECT;
7647         } else {
7648                 pci_set_master(pdev);
7649                 pci_restore_state(pdev);
7650                 pci_save_state(pdev);
7651
7652                 pci_wake_from_d3(pdev, false);
7653
7654                 ixgbe_reset(adapter);
7655                 IXGBE_WRITE_REG(&adapter->hw, IXGBE_WUS, ~0);
7656                 result = PCI_ERS_RESULT_RECOVERED;
7657         }
7658
7659         err = pci_cleanup_aer_uncorrect_error_status(pdev);
7660         if (err) {
7661                 e_dev_err("pci_cleanup_aer_uncorrect_error_status "
7662                           "failed 0x%0x\n", err);
7663                 /* non-fatal, continue */
7664         }
7665
7666         return result;
7667 }
7668
7669 /**
7670  * ixgbe_io_resume - called when traffic can start flowing again.
7671  * @pdev: Pointer to PCI device
7672  *
7673  * This callback is called when the error recovery driver tells us that
7674  * its OK to resume normal operation.
7675  */
7676 static void ixgbe_io_resume(struct pci_dev *pdev)
7677 {
7678         struct ixgbe_adapter *adapter = pci_get_drvdata(pdev);
7679         struct net_device *netdev = adapter->netdev;
7680
7681         if (netif_running(netdev))
7682                 ixgbe_up(adapter);
7683
7684         netif_device_attach(netdev);
7685 }
7686
7687 static struct pci_error_handlers ixgbe_err_handler = {
7688         .error_detected = ixgbe_io_error_detected,
7689         .slot_reset = ixgbe_io_slot_reset,
7690         .resume = ixgbe_io_resume,
7691 };
7692
7693 static struct pci_driver ixgbe_driver = {
7694         .name     = ixgbe_driver_name,
7695         .id_table = ixgbe_pci_tbl,
7696         .probe    = ixgbe_probe,
7697         .remove   = __devexit_p(ixgbe_remove),
7698 #ifdef CONFIG_PM
7699         .suspend  = ixgbe_suspend,
7700         .resume   = ixgbe_resume,
7701 #endif
7702         .shutdown = ixgbe_shutdown,
7703         .err_handler = &ixgbe_err_handler
7704 };
7705
7706 /**
7707  * ixgbe_init_module - Driver Registration Routine
7708  *
7709  * ixgbe_init_module is the first routine called when the driver is
7710  * loaded. All it does is register with the PCI subsystem.
7711  **/
7712 static int __init ixgbe_init_module(void)
7713 {
7714         int ret;
7715         pr_info("%s - version %s\n", ixgbe_driver_string, ixgbe_driver_version);
7716         pr_info("%s\n", ixgbe_copyright);
7717
7718 #ifdef CONFIG_IXGBE_DCA
7719         dca_register_notify(&dca_notifier);
7720 #endif
7721
7722         ret = pci_register_driver(&ixgbe_driver);
7723         return ret;
7724 }
7725
7726 module_init(ixgbe_init_module);
7727
7728 /**
7729  * ixgbe_exit_module - Driver Exit Cleanup Routine
7730  *
7731  * ixgbe_exit_module is called just before the driver is removed
7732  * from memory.
7733  **/
7734 static void __exit ixgbe_exit_module(void)
7735 {
7736 #ifdef CONFIG_IXGBE_DCA
7737         dca_unregister_notify(&dca_notifier);
7738 #endif
7739         pci_unregister_driver(&ixgbe_driver);
7740         rcu_barrier(); /* Wait for completion of call_rcu()'s */
7741 }
7742
7743 #ifdef CONFIG_IXGBE_DCA
7744 static int ixgbe_notify_dca(struct notifier_block *nb, unsigned long event,
7745                             void *p)
7746 {
7747         int ret_val;
7748
7749         ret_val = driver_for_each_device(&ixgbe_driver.driver, NULL, &event,
7750                                          __ixgbe_notify_dca);
7751
7752         return ret_val ? NOTIFY_BAD : NOTIFY_DONE;
7753 }
7754
7755 #endif /* CONFIG_IXGBE_DCA */
7756
7757 module_exit(ixgbe_exit_module);
7758
7759 /* ixgbe_main.c */