1 /*******************************************************************************
3 Intel 10 Gigabit PCI Express Linux driver
4 Copyright(c) 1999 - 2011 Intel Corporation.
6 This program is free software; you can redistribute it and/or modify it
7 under the terms and conditions of the GNU General Public License,
8 version 2, as published by the Free Software Foundation.
10 This program is distributed in the hope it will be useful, but WITHOUT
11 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
12 FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
15 You should have received a copy of the GNU General Public License along with
16 this program; if not, write to the Free Software Foundation, Inc.,
17 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
19 The full GNU General Public License is included in this distribution in
20 the file called "COPYING".
23 e1000-devel Mailing List <e1000-devel@lists.sourceforge.net>
24 Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
26 *******************************************************************************/
28 #include <linux/pci.h>
29 #include <linux/delay.h>
30 #include <linux/sched.h>
33 #include "ixgbe_phy.h"
35 #define IXGBE_X540_MAX_TX_QUEUES 128
36 #define IXGBE_X540_MAX_RX_QUEUES 128
37 #define IXGBE_X540_RAR_ENTRIES 128
38 #define IXGBE_X540_MC_TBL_SIZE 128
39 #define IXGBE_X540_VFT_TBL_SIZE 128
40 #define IXGBE_X540_RX_PB_SIZE 384
42 static s32 ixgbe_update_flash_X540(struct ixgbe_hw *hw);
43 static s32 ixgbe_poll_flash_update_done_X540(struct ixgbe_hw *hw);
44 static s32 ixgbe_acquire_swfw_sync_X540(struct ixgbe_hw *hw, u16 mask);
45 static void ixgbe_release_swfw_sync_X540(struct ixgbe_hw *hw, u16 mask);
46 static s32 ixgbe_get_swfw_sync_semaphore(struct ixgbe_hw *hw);
47 static void ixgbe_release_swfw_sync_semaphore(struct ixgbe_hw *hw);
49 static enum ixgbe_media_type ixgbe_get_media_type_X540(struct ixgbe_hw *hw)
51 return ixgbe_media_type_copper;
54 static s32 ixgbe_get_invariants_X540(struct ixgbe_hw *hw)
56 struct ixgbe_mac_info *mac = &hw->mac;
58 /* Call PHY identify routine to get the phy type */
59 ixgbe_identify_phy_generic(hw);
61 mac->mcft_size = IXGBE_X540_MC_TBL_SIZE;
62 mac->vft_size = IXGBE_X540_VFT_TBL_SIZE;
63 mac->num_rar_entries = IXGBE_X540_RAR_ENTRIES;
64 mac->max_rx_queues = IXGBE_X540_MAX_RX_QUEUES;
65 mac->max_tx_queues = IXGBE_X540_MAX_TX_QUEUES;
66 mac->max_msix_vectors = ixgbe_get_pcie_msix_count_generic(hw);
72 * ixgbe_setup_mac_link_X540 - Set the auto advertised capabilitires
73 * @hw: pointer to hardware structure
74 * @speed: new link speed
75 * @autoneg: true if autonegotiation enabled
76 * @autoneg_wait_to_complete: true when waiting for completion is needed
78 static s32 ixgbe_setup_mac_link_X540(struct ixgbe_hw *hw,
79 ixgbe_link_speed speed, bool autoneg,
80 bool autoneg_wait_to_complete)
82 return hw->phy.ops.setup_link_speed(hw, speed, autoneg,
83 autoneg_wait_to_complete);
87 * ixgbe_reset_hw_X540 - Perform hardware reset
88 * @hw: pointer to hardware structure
90 * Resets the hardware by resetting the transmit and receive units, masks
91 * and clears all interrupts, perform a PHY reset, and perform a link (MAC)
94 static s32 ixgbe_reset_hw_X540(struct ixgbe_hw *hw)
96 ixgbe_link_speed link_speed;
101 /* Call adapter stop to disable tx/rx and clear interrupts */
102 status = hw->mac.ops.stop_adapter(hw);
106 /* flush pending Tx transactions */
107 ixgbe_clear_tx_pending(hw);
111 * Issue global reset to the MAC. Needs to be SW reset if link is up.
112 * If link reset is used when link is up, it might reset the PHY when
113 * mng is using it. If link is down or the flag to force full link
114 * reset is set, then perform link reset.
116 ctrl = IXGBE_CTRL_LNK_RST;
117 if (!hw->force_full_reset) {
118 hw->mac.ops.check_link(hw, &link_speed, &link_up, false);
120 ctrl = IXGBE_CTRL_RST;
123 ctrl |= IXGBE_READ_REG(hw, IXGBE_CTRL);
124 IXGBE_WRITE_REG(hw, IXGBE_CTRL, ctrl);
125 IXGBE_WRITE_FLUSH(hw);
127 /* Poll for reset bit to self-clear indicating reset is complete */
128 for (i = 0; i < 10; i++) {
130 ctrl = IXGBE_READ_REG(hw, IXGBE_CTRL);
131 if (!(ctrl & IXGBE_CTRL_RST_MASK))
135 if (ctrl & IXGBE_CTRL_RST_MASK) {
136 status = IXGBE_ERR_RESET_FAILED;
137 hw_dbg(hw, "Reset polling failed to complete.\n");
143 * Double resets are required for recovery from certain error
144 * conditions. Between resets, it is necessary to stall to allow time
145 * for any pending HW events to complete.
147 if (hw->mac.flags & IXGBE_FLAGS_DOUBLE_RESET_REQUIRED) {
148 hw->mac.flags &= ~IXGBE_FLAGS_DOUBLE_RESET_REQUIRED;
152 /* Set the Rx packet buffer size. */
153 IXGBE_WRITE_REG(hw, IXGBE_RXPBSIZE(0), 384 << IXGBE_RXPBSIZE_SHIFT);
155 /* Store the permanent mac address */
156 hw->mac.ops.get_mac_addr(hw, hw->mac.perm_addr);
159 * Store MAC address from RAR0, clear receive address registers, and
160 * clear the multicast table. Also reset num_rar_entries to 128,
161 * since we modify this value when programming the SAN MAC address.
163 hw->mac.num_rar_entries = IXGBE_X540_MAX_TX_QUEUES;
164 hw->mac.ops.init_rx_addrs(hw);
166 /* Store the permanent SAN mac address */
167 hw->mac.ops.get_san_mac_addr(hw, hw->mac.san_addr);
169 /* Add the SAN MAC address to the RAR only if it's a valid address */
170 if (ixgbe_validate_mac_addr(hw->mac.san_addr) == 0) {
171 hw->mac.ops.set_rar(hw, hw->mac.num_rar_entries - 1,
172 hw->mac.san_addr, 0, IXGBE_RAH_AV);
174 /* Reserve the last RAR for the SAN MAC address */
175 hw->mac.num_rar_entries--;
178 /* Store the alternative WWNN/WWPN prefix */
179 hw->mac.ops.get_wwn_prefix(hw, &hw->mac.wwnn_prefix,
180 &hw->mac.wwpn_prefix);
187 * ixgbe_start_hw_X540 - Prepare hardware for Tx/Rx
188 * @hw: pointer to hardware structure
190 * Starts the hardware using the generic start_hw function
191 * and the generation start_hw function.
192 * Then performs revision-specific operations, if any.
194 static s32 ixgbe_start_hw_X540(struct ixgbe_hw *hw)
198 ret_val = ixgbe_start_hw_generic(hw);
202 ret_val = ixgbe_start_hw_gen2(hw);
203 hw->mac.rx_pb_size = IXGBE_X540_RX_PB_SIZE;
209 * ixgbe_get_supported_physical_layer_X540 - Returns physical layer type
210 * @hw: pointer to hardware structure
212 * Determines physical layer capabilities of the current configuration.
214 static u32 ixgbe_get_supported_physical_layer_X540(struct ixgbe_hw *hw)
216 u32 physical_layer = IXGBE_PHYSICAL_LAYER_UNKNOWN;
219 hw->phy.ops.identify(hw);
221 hw->phy.ops.read_reg(hw, MDIO_PMA_EXTABLE, MDIO_MMD_PMAPMD,
223 if (ext_ability & MDIO_PMA_EXTABLE_10GBT)
224 physical_layer |= IXGBE_PHYSICAL_LAYER_10GBASE_T;
225 if (ext_ability & MDIO_PMA_EXTABLE_1000BT)
226 physical_layer |= IXGBE_PHYSICAL_LAYER_1000BASE_T;
227 if (ext_ability & MDIO_PMA_EXTABLE_100BTX)
228 physical_layer |= IXGBE_PHYSICAL_LAYER_100BASE_TX;
230 return physical_layer;
234 * ixgbe_init_eeprom_params_X540 - Initialize EEPROM params
235 * @hw: pointer to hardware structure
237 * Initializes the EEPROM parameters ixgbe_eeprom_info within the
238 * ixgbe_hw struct in order to set up EEPROM access.
240 static s32 ixgbe_init_eeprom_params_X540(struct ixgbe_hw *hw)
242 struct ixgbe_eeprom_info *eeprom = &hw->eeprom;
246 if (eeprom->type == ixgbe_eeprom_uninitialized) {
247 eeprom->semaphore_delay = 10;
248 eeprom->type = ixgbe_flash;
250 eec = IXGBE_READ_REG(hw, IXGBE_EEC);
251 eeprom_size = (u16)((eec & IXGBE_EEC_SIZE) >>
252 IXGBE_EEC_SIZE_SHIFT);
253 eeprom->word_size = 1 << (eeprom_size +
254 IXGBE_EEPROM_WORD_SIZE_SHIFT);
256 hw_dbg(hw, "Eeprom params: type = %d, size = %d\n",
257 eeprom->type, eeprom->word_size);
264 * ixgbe_read_eerd_X540- Read EEPROM word using EERD
265 * @hw: pointer to hardware structure
266 * @offset: offset of word in the EEPROM to read
267 * @data: word read from the EEPROM
269 * Reads a 16 bit word from the EEPROM using the EERD register.
271 static s32 ixgbe_read_eerd_X540(struct ixgbe_hw *hw, u16 offset, u16 *data)
275 if (hw->mac.ops.acquire_swfw_sync(hw, IXGBE_GSSR_EEP_SM) ==
277 status = ixgbe_read_eerd_generic(hw, offset, data);
279 status = IXGBE_ERR_SWFW_SYNC;
281 hw->mac.ops.release_swfw_sync(hw, IXGBE_GSSR_EEP_SM);
286 * ixgbe_read_eerd_buffer_X540 - Read EEPROM word(s) using EERD
287 * @hw: pointer to hardware structure
288 * @offset: offset of word in the EEPROM to read
289 * @words: number of words
290 * @data: word(s) read from the EEPROM
292 * Reads a 16 bit word(s) from the EEPROM using the EERD register.
294 static s32 ixgbe_read_eerd_buffer_X540(struct ixgbe_hw *hw,
295 u16 offset, u16 words, u16 *data)
299 if (hw->mac.ops.acquire_swfw_sync(hw, IXGBE_GSSR_EEP_SM) ==
301 status = ixgbe_read_eerd_buffer_generic(hw, offset,
304 status = IXGBE_ERR_SWFW_SYNC;
306 hw->mac.ops.release_swfw_sync(hw, IXGBE_GSSR_EEP_SM);
311 * ixgbe_write_eewr_X540 - Write EEPROM word using EEWR
312 * @hw: pointer to hardware structure
313 * @offset: offset of word in the EEPROM to write
314 * @data: word write to the EEPROM
316 * Write a 16 bit word to the EEPROM using the EEWR register.
318 static s32 ixgbe_write_eewr_X540(struct ixgbe_hw *hw, u16 offset, u16 data)
322 if (hw->mac.ops.acquire_swfw_sync(hw, IXGBE_GSSR_EEP_SM) == 0)
323 status = ixgbe_write_eewr_generic(hw, offset, data);
325 status = IXGBE_ERR_SWFW_SYNC;
327 hw->mac.ops.release_swfw_sync(hw, IXGBE_GSSR_EEP_SM);
332 * ixgbe_write_eewr_buffer_X540 - Write EEPROM word(s) using EEWR
333 * @hw: pointer to hardware structure
334 * @offset: offset of word in the EEPROM to write
335 * @words: number of words
336 * @data: word(s) write to the EEPROM
338 * Write a 16 bit word(s) to the EEPROM using the EEWR register.
340 static s32 ixgbe_write_eewr_buffer_X540(struct ixgbe_hw *hw,
341 u16 offset, u16 words, u16 *data)
345 if (hw->mac.ops.acquire_swfw_sync(hw, IXGBE_GSSR_EEP_SM) ==
347 status = ixgbe_write_eewr_buffer_generic(hw, offset,
350 status = IXGBE_ERR_SWFW_SYNC;
352 hw->mac.ops.release_swfw_sync(hw, IXGBE_GSSR_EEP_SM);
357 * ixgbe_calc_eeprom_checksum_X540 - Calculates and returns the checksum
359 * This function does not use synchronization for EERD and EEWR. It can
360 * be used internally by function which utilize ixgbe_acquire_swfw_sync_X540.
362 * @hw: pointer to hardware structure
364 static u16 ixgbe_calc_eeprom_checksum_X540(struct ixgbe_hw *hw)
374 * Do not use hw->eeprom.ops.read because we do not want to take
375 * the synchronization semaphores here. Instead use
376 * ixgbe_read_eerd_generic
379 /* Include 0x0-0x3F in the checksum */
380 for (i = 0; i < IXGBE_EEPROM_CHECKSUM; i++) {
381 if (ixgbe_read_eerd_generic(hw, i, &word) != 0) {
382 hw_dbg(hw, "EEPROM read failed\n");
389 * Include all data from pointers 0x3, 0x6-0xE. This excludes the
390 * FW, PHY module, and PCIe Expansion/Option ROM pointers.
392 for (i = IXGBE_PCIE_ANALOG_PTR; i < IXGBE_FW_PTR; i++) {
393 if (i == IXGBE_PHY_PTR || i == IXGBE_OPTION_ROM_PTR)
396 if (ixgbe_read_eerd_generic(hw, i, &pointer) != 0) {
397 hw_dbg(hw, "EEPROM read failed\n");
401 /* Skip pointer section if the pointer is invalid. */
402 if (pointer == 0xFFFF || pointer == 0 ||
403 pointer >= hw->eeprom.word_size)
406 if (ixgbe_read_eerd_generic(hw, pointer, &length) != 0) {
407 hw_dbg(hw, "EEPROM read failed\n");
411 /* Skip pointer section if length is invalid. */
412 if (length == 0xFFFF || length == 0 ||
413 (pointer + length) >= hw->eeprom.word_size)
416 for (j = pointer+1; j <= pointer+length; j++) {
417 if (ixgbe_read_eerd_generic(hw, j, &word) != 0) {
418 hw_dbg(hw, "EEPROM read failed\n");
425 checksum = (u16)IXGBE_EEPROM_SUM - checksum;
431 * ixgbe_validate_eeprom_checksum_X540 - Validate EEPROM checksum
432 * @hw: pointer to hardware structure
433 * @checksum_val: calculated checksum
435 * Performs checksum calculation and validates the EEPROM checksum. If the
436 * caller does not need checksum_val, the value can be NULL.
438 static s32 ixgbe_validate_eeprom_checksum_X540(struct ixgbe_hw *hw,
443 u16 read_checksum = 0;
446 * Read the first word from the EEPROM. If this times out or fails, do
447 * not continue or we could be in for a very long wait while every
450 status = hw->eeprom.ops.read(hw, 0, &checksum);
453 hw_dbg(hw, "EEPROM read failed\n");
457 if (hw->mac.ops.acquire_swfw_sync(hw, IXGBE_GSSR_EEP_SM) == 0) {
458 checksum = hw->eeprom.ops.calc_checksum(hw);
461 * Do not use hw->eeprom.ops.read because we do not want to take
462 * the synchronization semaphores twice here.
464 ixgbe_read_eerd_generic(hw, IXGBE_EEPROM_CHECKSUM,
468 * Verify read checksum from EEPROM is the same as
469 * calculated checksum
471 if (read_checksum != checksum)
472 status = IXGBE_ERR_EEPROM_CHECKSUM;
474 /* If the user cares, return the calculated checksum */
476 *checksum_val = checksum;
478 status = IXGBE_ERR_SWFW_SYNC;
481 hw->mac.ops.release_swfw_sync(hw, IXGBE_GSSR_EEP_SM);
487 * ixgbe_update_eeprom_checksum_X540 - Updates the EEPROM checksum and flash
488 * @hw: pointer to hardware structure
490 * After writing EEPROM to shadow RAM using EEWR register, software calculates
491 * checksum and updates the EEPROM and instructs the hardware to update
494 static s32 ixgbe_update_eeprom_checksum_X540(struct ixgbe_hw *hw)
500 * Read the first word from the EEPROM. If this times out or fails, do
501 * not continue or we could be in for a very long wait while every
504 status = hw->eeprom.ops.read(hw, 0, &checksum);
507 hw_dbg(hw, "EEPROM read failed\n");
509 if (hw->mac.ops.acquire_swfw_sync(hw, IXGBE_GSSR_EEP_SM) == 0) {
510 checksum = hw->eeprom.ops.calc_checksum(hw);
513 * Do not use hw->eeprom.ops.write because we do not want to
514 * take the synchronization semaphores twice here.
516 status = ixgbe_write_eewr_generic(hw, IXGBE_EEPROM_CHECKSUM,
520 status = ixgbe_update_flash_X540(hw);
522 status = IXGBE_ERR_SWFW_SYNC;
525 hw->mac.ops.release_swfw_sync(hw, IXGBE_GSSR_EEP_SM);
531 * ixgbe_update_flash_X540 - Instruct HW to copy EEPROM to Flash device
532 * @hw: pointer to hardware structure
534 * Set FLUP (bit 23) of the EEC register to instruct Hardware to copy
535 * EEPROM from shadow RAM to the flash device.
537 static s32 ixgbe_update_flash_X540(struct ixgbe_hw *hw)
540 s32 status = IXGBE_ERR_EEPROM;
542 status = ixgbe_poll_flash_update_done_X540(hw);
543 if (status == IXGBE_ERR_EEPROM) {
544 hw_dbg(hw, "Flash update time out\n");
548 flup = IXGBE_READ_REG(hw, IXGBE_EEC) | IXGBE_EEC_FLUP;
549 IXGBE_WRITE_REG(hw, IXGBE_EEC, flup);
551 status = ixgbe_poll_flash_update_done_X540(hw);
553 hw_dbg(hw, "Flash update complete\n");
555 hw_dbg(hw, "Flash update time out\n");
557 if (hw->revision_id == 0) {
558 flup = IXGBE_READ_REG(hw, IXGBE_EEC);
560 if (flup & IXGBE_EEC_SEC1VAL) {
561 flup |= IXGBE_EEC_FLUP;
562 IXGBE_WRITE_REG(hw, IXGBE_EEC, flup);
565 status = ixgbe_poll_flash_update_done_X540(hw);
567 hw_dbg(hw, "Flash update complete\n");
569 hw_dbg(hw, "Flash update time out\n");
576 * ixgbe_poll_flash_update_done_X540 - Poll flash update status
577 * @hw: pointer to hardware structure
579 * Polls the FLUDONE (bit 26) of the EEC Register to determine when the
580 * flash update is done.
582 static s32 ixgbe_poll_flash_update_done_X540(struct ixgbe_hw *hw)
586 s32 status = IXGBE_ERR_EEPROM;
588 for (i = 0; i < IXGBE_FLUDONE_ATTEMPTS; i++) {
589 reg = IXGBE_READ_REG(hw, IXGBE_EEC);
590 if (reg & IXGBE_EEC_FLUDONE) {
600 * ixgbe_acquire_swfw_sync_X540 - Acquire SWFW semaphore
601 * @hw: pointer to hardware structure
602 * @mask: Mask to specify which semaphore to acquire
604 * Acquires the SWFW semaphore thought the SW_FW_SYNC register for
605 * the specified function (CSR, PHY0, PHY1, NVM, Flash)
607 static s32 ixgbe_acquire_swfw_sync_X540(struct ixgbe_hw *hw, u16 mask)
611 u32 fwmask = mask << 5;
616 if (swmask == IXGBE_GSSR_EEP_SM)
617 hwmask = IXGBE_GSSR_FLASH_SM;
619 for (i = 0; i < timeout; i++) {
621 * SW NVM semaphore bit is used for access to all
622 * SW_FW_SYNC bits (not just NVM)
624 if (ixgbe_get_swfw_sync_semaphore(hw))
625 return IXGBE_ERR_SWFW_SYNC;
627 swfw_sync = IXGBE_READ_REG(hw, IXGBE_SWFW_SYNC);
628 if (!(swfw_sync & (fwmask | swmask | hwmask))) {
630 IXGBE_WRITE_REG(hw, IXGBE_SWFW_SYNC, swfw_sync);
631 ixgbe_release_swfw_sync_semaphore(hw);
635 * Firmware currently using resource (fwmask),
636 * hardware currently using resource (hwmask),
637 * or other software thread currently using
640 ixgbe_release_swfw_sync_semaphore(hw);
641 usleep_range(5000, 10000);
646 * If the resource is not released by the FW/HW the SW can assume that
647 * the FW/HW malfunctions. In that case the SW should sets the
648 * SW bit(s) of the requested resource(s) while ignoring the
649 * corresponding FW/HW bits in the SW_FW_SYNC register.
652 swfw_sync = IXGBE_READ_REG(hw, IXGBE_SWFW_SYNC);
653 if (swfw_sync & (fwmask | hwmask)) {
654 if (ixgbe_get_swfw_sync_semaphore(hw))
655 return IXGBE_ERR_SWFW_SYNC;
658 IXGBE_WRITE_REG(hw, IXGBE_SWFW_SYNC, swfw_sync);
659 ixgbe_release_swfw_sync_semaphore(hw);
663 usleep_range(5000, 10000);
668 * ixgbe_release_swfw_sync_X540 - Release SWFW semaphore
669 * @hw: pointer to hardware structure
670 * @mask: Mask to specify which semaphore to release
672 * Releases the SWFW semaphore through the SW_FW_SYNC register
673 * for the specified function (CSR, PHY0, PHY1, EVM, Flash)
675 static void ixgbe_release_swfw_sync_X540(struct ixgbe_hw *hw, u16 mask)
680 ixgbe_get_swfw_sync_semaphore(hw);
682 swfw_sync = IXGBE_READ_REG(hw, IXGBE_SWFW_SYNC);
683 swfw_sync &= ~swmask;
684 IXGBE_WRITE_REG(hw, IXGBE_SWFW_SYNC, swfw_sync);
686 ixgbe_release_swfw_sync_semaphore(hw);
687 usleep_range(5000, 10000);
691 * ixgbe_get_nvm_semaphore - Get hardware semaphore
692 * @hw: pointer to hardware structure
694 * Sets the hardware semaphores so SW/FW can gain control of shared resources
696 static s32 ixgbe_get_swfw_sync_semaphore(struct ixgbe_hw *hw)
698 s32 status = IXGBE_ERR_EEPROM;
703 /* Get SMBI software semaphore between device drivers first */
704 for (i = 0; i < timeout; i++) {
706 * If the SMBI bit is 0 when we read it, then the bit will be
707 * set and we have the semaphore
709 swsm = IXGBE_READ_REG(hw, IXGBE_SWSM);
710 if (!(swsm & IXGBE_SWSM_SMBI)) {
717 /* Now get the semaphore between SW/FW through the REGSMP bit */
719 for (i = 0; i < timeout; i++) {
720 swsm = IXGBE_READ_REG(hw, IXGBE_SWFW_SYNC);
721 if (!(swsm & IXGBE_SWFW_REGSMP))
727 hw_dbg(hw, "Software semaphore SMBI between device drivers "
735 * ixgbe_release_nvm_semaphore - Release hardware semaphore
736 * @hw: pointer to hardware structure
738 * This function clears hardware semaphore bits.
740 static void ixgbe_release_swfw_sync_semaphore(struct ixgbe_hw *hw)
744 /* Release both semaphores by writing 0 to the bits REGSMP and SMBI */
746 swsm = IXGBE_READ_REG(hw, IXGBE_SWSM);
747 swsm &= ~IXGBE_SWSM_SMBI;
748 IXGBE_WRITE_REG(hw, IXGBE_SWSM, swsm);
750 swsm = IXGBE_READ_REG(hw, IXGBE_SWFW_SYNC);
751 swsm &= ~IXGBE_SWFW_REGSMP;
752 IXGBE_WRITE_REG(hw, IXGBE_SWFW_SYNC, swsm);
754 IXGBE_WRITE_FLUSH(hw);
758 * ixgbe_blink_led_start_X540 - Blink LED based on index.
759 * @hw: pointer to hardware structure
760 * @index: led number to blink
762 * Devices that implement the version 2 interface:
765 static s32 ixgbe_blink_led_start_X540(struct ixgbe_hw *hw, u32 index)
771 * In order for the blink bit in the LED control register
772 * to work, link and speed must be forced in the MAC. We
773 * will reverse this when we stop the blinking.
775 macc_reg = IXGBE_READ_REG(hw, IXGBE_MACC);
776 macc_reg |= IXGBE_MACC_FLU | IXGBE_MACC_FSV_10G | IXGBE_MACC_FS;
777 IXGBE_WRITE_REG(hw, IXGBE_MACC, macc_reg);
779 /* Set the LED to LINK_UP + BLINK. */
780 ledctl_reg = IXGBE_READ_REG(hw, IXGBE_LEDCTL);
781 ledctl_reg &= ~IXGBE_LED_MODE_MASK(index);
782 ledctl_reg |= IXGBE_LED_BLINK(index);
783 IXGBE_WRITE_REG(hw, IXGBE_LEDCTL, ledctl_reg);
784 IXGBE_WRITE_FLUSH(hw);
790 * ixgbe_blink_led_stop_X540 - Stop blinking LED based on index.
791 * @hw: pointer to hardware structure
792 * @index: led number to stop blinking
794 * Devices that implement the version 2 interface:
797 static s32 ixgbe_blink_led_stop_X540(struct ixgbe_hw *hw, u32 index)
802 /* Restore the LED to its default value. */
803 ledctl_reg = IXGBE_READ_REG(hw, IXGBE_LEDCTL);
804 ledctl_reg &= ~IXGBE_LED_MODE_MASK(index);
805 ledctl_reg |= IXGBE_LED_LINK_ACTIVE << IXGBE_LED_MODE_SHIFT(index);
806 ledctl_reg &= ~IXGBE_LED_BLINK(index);
807 IXGBE_WRITE_REG(hw, IXGBE_LEDCTL, ledctl_reg);
809 /* Unforce link and speed in the MAC. */
810 macc_reg = IXGBE_READ_REG(hw, IXGBE_MACC);
811 macc_reg &= ~(IXGBE_MACC_FLU | IXGBE_MACC_FSV_10G | IXGBE_MACC_FS);
812 IXGBE_WRITE_REG(hw, IXGBE_MACC, macc_reg);
813 IXGBE_WRITE_FLUSH(hw);
817 static struct ixgbe_mac_operations mac_ops_X540 = {
818 .init_hw = &ixgbe_init_hw_generic,
819 .reset_hw = &ixgbe_reset_hw_X540,
820 .start_hw = &ixgbe_start_hw_X540,
821 .clear_hw_cntrs = &ixgbe_clear_hw_cntrs_generic,
822 .get_media_type = &ixgbe_get_media_type_X540,
823 .get_supported_physical_layer =
824 &ixgbe_get_supported_physical_layer_X540,
825 .enable_rx_dma = &ixgbe_enable_rx_dma_generic,
826 .get_mac_addr = &ixgbe_get_mac_addr_generic,
827 .get_san_mac_addr = &ixgbe_get_san_mac_addr_generic,
828 .get_device_caps = &ixgbe_get_device_caps_generic,
829 .get_wwn_prefix = &ixgbe_get_wwn_prefix_generic,
830 .stop_adapter = &ixgbe_stop_adapter_generic,
831 .get_bus_info = &ixgbe_get_bus_info_generic,
832 .set_lan_id = &ixgbe_set_lan_id_multi_port_pcie,
833 .read_analog_reg8 = NULL,
834 .write_analog_reg8 = NULL,
835 .setup_link = &ixgbe_setup_mac_link_X540,
836 .set_rxpba = &ixgbe_set_rxpba_generic,
837 .check_link = &ixgbe_check_mac_link_generic,
838 .get_link_capabilities = &ixgbe_get_copper_link_capabilities_generic,
839 .led_on = &ixgbe_led_on_generic,
840 .led_off = &ixgbe_led_off_generic,
841 .blink_led_start = &ixgbe_blink_led_start_X540,
842 .blink_led_stop = &ixgbe_blink_led_stop_X540,
843 .set_rar = &ixgbe_set_rar_generic,
844 .clear_rar = &ixgbe_clear_rar_generic,
845 .set_vmdq = &ixgbe_set_vmdq_generic,
846 .clear_vmdq = &ixgbe_clear_vmdq_generic,
847 .init_rx_addrs = &ixgbe_init_rx_addrs_generic,
848 .update_mc_addr_list = &ixgbe_update_mc_addr_list_generic,
849 .enable_mc = &ixgbe_enable_mc_generic,
850 .disable_mc = &ixgbe_disable_mc_generic,
851 .clear_vfta = &ixgbe_clear_vfta_generic,
852 .set_vfta = &ixgbe_set_vfta_generic,
853 .fc_enable = &ixgbe_fc_enable_generic,
854 .set_fw_drv_ver = &ixgbe_set_fw_drv_ver_generic,
855 .init_uta_tables = &ixgbe_init_uta_tables_generic,
857 .set_mac_anti_spoofing = &ixgbe_set_mac_anti_spoofing,
858 .set_vlan_anti_spoofing = &ixgbe_set_vlan_anti_spoofing,
859 .acquire_swfw_sync = &ixgbe_acquire_swfw_sync_X540,
860 .release_swfw_sync = &ixgbe_release_swfw_sync_X540,
863 static struct ixgbe_eeprom_operations eeprom_ops_X540 = {
864 .init_params = &ixgbe_init_eeprom_params_X540,
865 .read = &ixgbe_read_eerd_X540,
866 .read_buffer = &ixgbe_read_eerd_buffer_X540,
867 .write = &ixgbe_write_eewr_X540,
868 .write_buffer = &ixgbe_write_eewr_buffer_X540,
869 .calc_checksum = &ixgbe_calc_eeprom_checksum_X540,
870 .validate_checksum = &ixgbe_validate_eeprom_checksum_X540,
871 .update_checksum = &ixgbe_update_eeprom_checksum_X540,
874 static struct ixgbe_phy_operations phy_ops_X540 = {
875 .identify = &ixgbe_identify_phy_generic,
876 .identify_sfp = &ixgbe_identify_sfp_module_generic,
879 .read_reg = &ixgbe_read_phy_reg_generic,
880 .write_reg = &ixgbe_write_phy_reg_generic,
881 .setup_link = &ixgbe_setup_phy_link_generic,
882 .setup_link_speed = &ixgbe_setup_phy_link_speed_generic,
883 .read_i2c_byte = &ixgbe_read_i2c_byte_generic,
884 .write_i2c_byte = &ixgbe_write_i2c_byte_generic,
885 .read_i2c_eeprom = &ixgbe_read_i2c_eeprom_generic,
886 .write_i2c_eeprom = &ixgbe_write_i2c_eeprom_generic,
887 .check_overtemp = &ixgbe_tn_check_overtemp,
890 struct ixgbe_info ixgbe_X540_info = {
891 .mac = ixgbe_mac_X540,
892 .get_invariants = &ixgbe_get_invariants_X540,
893 .mac_ops = &mac_ops_X540,
894 .eeprom_ops = &eeprom_ops_X540,
895 .phy_ops = &phy_ops_X540,
896 .mbx_ops = &mbx_ops_generic,