2 * Copyright (c) 2007 Mellanox Technologies. All rights reserved.
4 * This software is available to you under a choice of one of two
5 * licenses. You may choose to be licensed under the terms of the GNU
6 * General Public License (GPL) Version 2, available from the file
7 * COPYING in the main directory of this source tree, or the
8 * OpenIB.org BSD license below:
10 * Redistribution and use in source and binary forms, with or
11 * without modification, are permitted provided that the following
14 * - Redistributions of source code must retain the above
15 * copyright notice, this list of conditions and the following
18 * - Redistributions in binary form must reproduce the above
19 * copyright notice, this list of conditions and the following
20 * disclaimer in the documentation and/or other materials
21 * provided with the distribution.
23 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
24 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
25 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
26 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
27 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
28 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
29 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
34 #include <net/busy_poll.h>
35 #include <linux/bpf.h>
36 #include <linux/bpf_trace.h>
37 #include <linux/mlx4/cq.h>
38 #include <linux/slab.h>
39 #include <linux/mlx4/qp.h>
40 #include <linux/skbuff.h>
41 #include <linux/rculist.h>
42 #include <linux/if_ether.h>
43 #include <linux/if_vlan.h>
44 #include <linux/vmalloc.h>
45 #include <linux/irq.h>
47 #if IS_ENABLED(CONFIG_IPV6)
48 #include <net/ip6_checksum.h>
53 static int mlx4_alloc_pages(struct mlx4_en_priv *priv,
54 struct mlx4_en_rx_alloc *page_alloc,
55 const struct mlx4_en_frag_info *frag_info,
62 for (order = frag_info->order; ;) {
66 gfp |= __GFP_COMP | __GFP_NOWARN | __GFP_NOMEMALLOC;
67 page = alloc_pages(gfp, order);
71 ((PAGE_SIZE << order) < frag_info->frag_size))
74 dma = dma_map_page(priv->ddev, page, 0, PAGE_SIZE << order,
76 if (unlikely(dma_mapping_error(priv->ddev, dma))) {
80 page_alloc->page_size = PAGE_SIZE << order;
81 page_alloc->page = page;
82 page_alloc->dma = dma;
83 page_alloc->page_offset = 0;
84 /* Not doing get_page() for each frag is a big win
85 * on asymetric workloads. Note we can not use atomic_set().
87 page_ref_add(page, page_alloc->page_size / frag_info->frag_stride - 1);
91 static int mlx4_en_alloc_frags(struct mlx4_en_priv *priv,
92 struct mlx4_en_rx_desc *rx_desc,
93 struct mlx4_en_rx_alloc *frags,
94 struct mlx4_en_rx_alloc *ring_alloc,
97 struct mlx4_en_rx_alloc page_alloc[MLX4_EN_MAX_RX_FRAGS];
98 const struct mlx4_en_frag_info *frag_info;
102 for (i = 0; i < priv->num_frags; i++) {
103 frag_info = &priv->frag_info[i];
104 page_alloc[i] = ring_alloc[i];
105 page_alloc[i].page_offset += frag_info->frag_stride;
107 if (page_alloc[i].page_offset + frag_info->frag_stride <=
108 ring_alloc[i].page_size)
111 if (unlikely(mlx4_alloc_pages(priv, &page_alloc[i],
116 for (i = 0; i < priv->num_frags; i++) {
117 frags[i] = ring_alloc[i];
118 frags[i].page_offset += priv->frag_info[i].rx_headroom;
119 rx_desc->data[i].addr = cpu_to_be64(frags[i].dma +
120 frags[i].page_offset);
121 ring_alloc[i] = page_alloc[i];
128 if (page_alloc[i].page != ring_alloc[i].page) {
129 dma_unmap_page(priv->ddev, page_alloc[i].dma,
130 page_alloc[i].page_size,
131 priv->frag_info[i].dma_dir);
132 page = page_alloc[i].page;
133 /* Revert changes done by mlx4_alloc_pages */
134 page_ref_sub(page, page_alloc[i].page_size /
135 priv->frag_info[i].frag_stride - 1);
142 static void mlx4_en_free_frag(struct mlx4_en_priv *priv,
143 struct mlx4_en_rx_alloc *frags,
146 const struct mlx4_en_frag_info *frag_info = &priv->frag_info[i];
147 u32 next_frag_end = frags[i].page_offset + 2 * frag_info->frag_stride;
150 if (next_frag_end > frags[i].page_size)
151 dma_unmap_page(priv->ddev, frags[i].dma, frags[i].page_size,
155 put_page(frags[i].page);
158 static int mlx4_en_init_allocator(struct mlx4_en_priv *priv,
159 struct mlx4_en_rx_ring *ring)
162 struct mlx4_en_rx_alloc *page_alloc;
164 for (i = 0; i < priv->num_frags; i++) {
165 const struct mlx4_en_frag_info *frag_info = &priv->frag_info[i];
167 if (mlx4_alloc_pages(priv, &ring->page_alloc[i],
168 frag_info, GFP_KERNEL | __GFP_COLD))
171 en_dbg(DRV, priv, " frag %d allocator: - size:%d frags:%d\n",
172 i, ring->page_alloc[i].page_size,
173 page_ref_count(ring->page_alloc[i].page));
181 page_alloc = &ring->page_alloc[i];
182 dma_unmap_page(priv->ddev, page_alloc->dma,
183 page_alloc->page_size,
184 priv->frag_info[i].dma_dir);
185 page = page_alloc->page;
186 /* Revert changes done by mlx4_alloc_pages */
187 page_ref_sub(page, page_alloc->page_size /
188 priv->frag_info[i].frag_stride - 1);
190 page_alloc->page = NULL;
195 static void mlx4_en_destroy_allocator(struct mlx4_en_priv *priv,
196 struct mlx4_en_rx_ring *ring)
198 struct mlx4_en_rx_alloc *page_alloc;
201 for (i = 0; i < priv->num_frags; i++) {
202 const struct mlx4_en_frag_info *frag_info = &priv->frag_info[i];
204 page_alloc = &ring->page_alloc[i];
205 en_dbg(DRV, priv, "Freeing allocator:%d count:%d\n",
206 i, page_count(page_alloc->page));
208 dma_unmap_page(priv->ddev, page_alloc->dma,
209 page_alloc->page_size, frag_info->dma_dir);
210 while (page_alloc->page_offset + frag_info->frag_stride <
211 page_alloc->page_size) {
212 put_page(page_alloc->page);
213 page_alloc->page_offset += frag_info->frag_stride;
215 page_alloc->page = NULL;
219 static void mlx4_en_init_rx_desc(struct mlx4_en_priv *priv,
220 struct mlx4_en_rx_ring *ring, int index)
222 struct mlx4_en_rx_desc *rx_desc = ring->buf + ring->stride * index;
226 /* Set size and memtype fields */
227 for (i = 0; i < priv->num_frags; i++) {
228 rx_desc->data[i].byte_count =
229 cpu_to_be32(priv->frag_info[i].frag_size);
230 rx_desc->data[i].lkey = cpu_to_be32(priv->mdev->mr.key);
233 /* If the number of used fragments does not fill up the ring stride,
234 * remaining (unused) fragments must be padded with null address/size
235 * and a special memory key */
236 possible_frags = (ring->stride - sizeof(struct mlx4_en_rx_desc)) / DS_SIZE;
237 for (i = priv->num_frags; i < possible_frags; i++) {
238 rx_desc->data[i].byte_count = 0;
239 rx_desc->data[i].lkey = cpu_to_be32(MLX4_EN_MEMTYPE_PAD);
240 rx_desc->data[i].addr = 0;
244 static int mlx4_en_prepare_rx_desc(struct mlx4_en_priv *priv,
245 struct mlx4_en_rx_ring *ring, int index,
248 struct mlx4_en_rx_desc *rx_desc = ring->buf + (index * ring->stride);
249 struct mlx4_en_rx_alloc *frags = ring->rx_info +
250 (index << priv->log_rx_info);
252 if (ring->page_cache.index > 0) {
253 frags[0] = ring->page_cache.buf[--ring->page_cache.index];
254 rx_desc->data[0].addr = cpu_to_be64(frags[0].dma +
255 frags[0].page_offset);
259 return mlx4_en_alloc_frags(priv, rx_desc, frags, ring->page_alloc, gfp);
262 static inline bool mlx4_en_is_ring_empty(struct mlx4_en_rx_ring *ring)
264 return ring->prod == ring->cons;
267 static inline void mlx4_en_update_rx_prod_db(struct mlx4_en_rx_ring *ring)
269 *ring->wqres.db.db = cpu_to_be32(ring->prod & 0xffff);
272 static void mlx4_en_free_rx_desc(struct mlx4_en_priv *priv,
273 struct mlx4_en_rx_ring *ring,
276 struct mlx4_en_rx_alloc *frags;
279 frags = ring->rx_info + (index << priv->log_rx_info);
280 for (nr = 0; nr < priv->num_frags; nr++) {
281 en_dbg(DRV, priv, "Freeing fragment:%d\n", nr);
282 mlx4_en_free_frag(priv, frags, nr);
286 static int mlx4_en_fill_rx_buffers(struct mlx4_en_priv *priv)
288 struct mlx4_en_rx_ring *ring;
293 for (buf_ind = 0; buf_ind < priv->prof->rx_ring_size; buf_ind++) {
294 for (ring_ind = 0; ring_ind < priv->rx_ring_num; ring_ind++) {
295 ring = priv->rx_ring[ring_ind];
297 if (mlx4_en_prepare_rx_desc(priv, ring,
299 GFP_KERNEL | __GFP_COLD)) {
300 if (ring->actual_size < MLX4_EN_MIN_RX_SIZE) {
301 en_err(priv, "Failed to allocate enough rx buffers\n");
304 new_size = rounddown_pow_of_two(ring->actual_size);
305 en_warn(priv, "Only %d buffers allocated reducing ring size to %d\n",
306 ring->actual_size, new_size);
317 for (ring_ind = 0; ring_ind < priv->rx_ring_num; ring_ind++) {
318 ring = priv->rx_ring[ring_ind];
319 while (ring->actual_size > new_size) {
322 mlx4_en_free_rx_desc(priv, ring, ring->actual_size);
329 static void mlx4_en_free_rx_buf(struct mlx4_en_priv *priv,
330 struct mlx4_en_rx_ring *ring)
334 en_dbg(DRV, priv, "Freeing Rx buf - cons:%d prod:%d\n",
335 ring->cons, ring->prod);
337 /* Unmap and free Rx buffers */
338 while (!mlx4_en_is_ring_empty(ring)) {
339 index = ring->cons & ring->size_mask;
340 en_dbg(DRV, priv, "Processing descriptor:%d\n", index);
341 mlx4_en_free_rx_desc(priv, ring, index);
346 void mlx4_en_set_num_rx_rings(struct mlx4_en_dev *mdev)
351 struct mlx4_dev *dev = mdev->dev;
353 mlx4_foreach_port(i, dev, MLX4_PORT_TYPE_ETH) {
354 num_of_eqs = max_t(int, MIN_RX_RINGS,
356 mlx4_get_eqs_per_port(mdev->dev, i),
359 num_rx_rings = mlx4_low_memory_profile() ? MIN_RX_RINGS :
360 min_t(int, num_of_eqs,
361 netif_get_num_default_rss_queues());
362 mdev->profile.prof[i].rx_ring_num =
363 rounddown_pow_of_two(num_rx_rings);
367 int mlx4_en_create_rx_ring(struct mlx4_en_priv *priv,
368 struct mlx4_en_rx_ring **pring,
369 u32 size, u16 stride, int node)
371 struct mlx4_en_dev *mdev = priv->mdev;
372 struct mlx4_en_rx_ring *ring;
376 ring = kzalloc_node(sizeof(*ring), GFP_KERNEL, node);
378 ring = kzalloc(sizeof(*ring), GFP_KERNEL);
380 en_err(priv, "Failed to allocate RX ring structure\n");
388 ring->size_mask = size - 1;
389 ring->stride = stride;
390 ring->log_stride = ffs(ring->stride) - 1;
391 ring->buf_size = ring->size * ring->stride + TXBB_SIZE;
393 tmp = size * roundup_pow_of_two(MLX4_EN_MAX_RX_FRAGS *
394 sizeof(struct mlx4_en_rx_alloc));
395 ring->rx_info = vmalloc_node(tmp, node);
396 if (!ring->rx_info) {
397 ring->rx_info = vmalloc(tmp);
398 if (!ring->rx_info) {
404 en_dbg(DRV, priv, "Allocated rx_info ring at addr:%p size:%d\n",
407 /* Allocate HW buffers on provided NUMA node */
408 set_dev_node(&mdev->dev->persist->pdev->dev, node);
409 err = mlx4_alloc_hwq_res(mdev->dev, &ring->wqres, ring->buf_size);
410 set_dev_node(&mdev->dev->persist->pdev->dev, mdev->dev->numa_node);
414 ring->buf = ring->wqres.buf.direct.buf;
416 ring->hwtstamp_rx_filter = priv->hwtstamp_config.rx_filter;
422 vfree(ring->rx_info);
423 ring->rx_info = NULL;
431 int mlx4_en_activate_rx_rings(struct mlx4_en_priv *priv)
433 struct mlx4_en_rx_ring *ring;
437 int stride = roundup_pow_of_two(sizeof(struct mlx4_en_rx_desc) +
438 DS_SIZE * priv->num_frags);
440 for (ring_ind = 0; ring_ind < priv->rx_ring_num; ring_ind++) {
441 ring = priv->rx_ring[ring_ind];
445 ring->actual_size = 0;
446 ring->cqn = priv->rx_cq[ring_ind]->mcq.cqn;
448 ring->stride = stride;
449 if (ring->stride <= TXBB_SIZE) {
450 /* Stamp first unused send wqe */
451 __be32 *ptr = (__be32 *)ring->buf;
452 __be32 stamp = cpu_to_be32(1 << STAMP_SHIFT);
454 /* Move pointer to start of rx section */
455 ring->buf += TXBB_SIZE;
458 ring->log_stride = ffs(ring->stride) - 1;
459 ring->buf_size = ring->size * ring->stride;
461 memset(ring->buf, 0, ring->buf_size);
462 mlx4_en_update_rx_prod_db(ring);
464 /* Initialize all descriptors */
465 for (i = 0; i < ring->size; i++)
466 mlx4_en_init_rx_desc(priv, ring, i);
468 /* Initialize page allocators */
469 err = mlx4_en_init_allocator(priv, ring);
471 en_err(priv, "Failed initializing ring allocator\n");
472 if (ring->stride <= TXBB_SIZE)
473 ring->buf -= TXBB_SIZE;
478 err = mlx4_en_fill_rx_buffers(priv);
482 for (ring_ind = 0; ring_ind < priv->rx_ring_num; ring_ind++) {
483 ring = priv->rx_ring[ring_ind];
485 ring->size_mask = ring->actual_size - 1;
486 mlx4_en_update_rx_prod_db(ring);
492 for (ring_ind = 0; ring_ind < priv->rx_ring_num; ring_ind++)
493 mlx4_en_free_rx_buf(priv, priv->rx_ring[ring_ind]);
495 ring_ind = priv->rx_ring_num - 1;
497 while (ring_ind >= 0) {
498 if (priv->rx_ring[ring_ind]->stride <= TXBB_SIZE)
499 priv->rx_ring[ring_ind]->buf -= TXBB_SIZE;
500 mlx4_en_destroy_allocator(priv, priv->rx_ring[ring_ind]);
506 /* We recover from out of memory by scheduling our napi poll
507 * function (mlx4_en_process_cq), which tries to allocate
508 * all missing RX buffers (call to mlx4_en_refill_rx_buffers).
510 void mlx4_en_recover_from_oom(struct mlx4_en_priv *priv)
517 for (ring = 0; ring < priv->rx_ring_num; ring++) {
518 if (mlx4_en_is_ring_empty(priv->rx_ring[ring])) {
520 napi_reschedule(&priv->rx_cq[ring]->napi);
526 /* When the rx ring is running in page-per-packet mode, a released frame can go
527 * directly into a small cache, to avoid unmapping or touching the page
528 * allocator. In bpf prog performance scenarios, buffers are either forwarded
529 * or dropped, never converted to skbs, so every page can come directly from
530 * this cache when it is sized to be a multiple of the napi budget.
532 bool mlx4_en_rx_recycle(struct mlx4_en_rx_ring *ring,
533 struct mlx4_en_rx_alloc *frame)
535 struct mlx4_en_page_cache *cache = &ring->page_cache;
537 if (cache->index >= MLX4_EN_CACHE_SIZE)
540 cache->buf[cache->index++] = *frame;
544 void mlx4_en_destroy_rx_ring(struct mlx4_en_priv *priv,
545 struct mlx4_en_rx_ring **pring,
546 u32 size, u16 stride)
548 struct mlx4_en_dev *mdev = priv->mdev;
549 struct mlx4_en_rx_ring *ring = *pring;
550 struct bpf_prog *old_prog;
552 old_prog = rcu_dereference_protected(
554 lockdep_is_held(&mdev->state_lock));
556 bpf_prog_put(old_prog);
557 mlx4_free_hwq_res(mdev->dev, &ring->wqres, size * stride + TXBB_SIZE);
558 vfree(ring->rx_info);
559 ring->rx_info = NULL;
564 void mlx4_en_deactivate_rx_ring(struct mlx4_en_priv *priv,
565 struct mlx4_en_rx_ring *ring)
569 for (i = 0; i < ring->page_cache.index; i++) {
570 struct mlx4_en_rx_alloc *frame = &ring->page_cache.buf[i];
572 dma_unmap_page(priv->ddev, frame->dma, frame->page_size,
573 priv->frag_info[0].dma_dir);
574 put_page(frame->page);
576 ring->page_cache.index = 0;
577 mlx4_en_free_rx_buf(priv, ring);
578 if (ring->stride <= TXBB_SIZE)
579 ring->buf -= TXBB_SIZE;
580 mlx4_en_destroy_allocator(priv, ring);
584 static int mlx4_en_complete_rx_desc(struct mlx4_en_priv *priv,
585 struct mlx4_en_rx_desc *rx_desc,
586 struct mlx4_en_rx_alloc *frags,
590 struct skb_frag_struct *skb_frags_rx = skb_shinfo(skb)->frags;
591 struct mlx4_en_frag_info *frag_info;
595 /* Collect used fragments while replacing them in the HW descriptors */
596 for (nr = 0; nr < priv->num_frags; nr++) {
597 frag_info = &priv->frag_info[nr];
598 if (length <= frag_info->frag_prefix_size)
600 if (unlikely(!frags[nr].page))
603 dma = be64_to_cpu(rx_desc->data[nr].addr);
604 dma_sync_single_for_cpu(priv->ddev, dma, frag_info->frag_size,
607 /* Save page reference in skb */
608 __skb_frag_set_page(&skb_frags_rx[nr], frags[nr].page);
609 skb_frag_size_set(&skb_frags_rx[nr], frag_info->frag_size);
610 skb_frags_rx[nr].page_offset = frags[nr].page_offset;
611 skb->truesize += frag_info->frag_stride;
612 frags[nr].page = NULL;
614 /* Adjust size of last fragment to match actual length */
616 skb_frag_size_set(&skb_frags_rx[nr - 1],
617 length - priv->frag_info[nr - 1].frag_prefix_size);
623 __skb_frag_unref(&skb_frags_rx[nr]);
629 static struct sk_buff *mlx4_en_rx_skb(struct mlx4_en_priv *priv,
630 struct mlx4_en_rx_desc *rx_desc,
631 struct mlx4_en_rx_alloc *frags,
639 skb = netdev_alloc_skb(priv->dev, SMALL_PACKET_SIZE + NET_IP_ALIGN);
640 if (unlikely(!skb)) {
641 en_dbg(RX_ERR, priv, "Failed allocating skb\n");
644 skb_reserve(skb, NET_IP_ALIGN);
647 /* Get pointer to first fragment so we could copy the headers into the
648 * (linear part of the) skb */
649 va = page_address(frags[0].page) + frags[0].page_offset;
651 if (length <= SMALL_PACKET_SIZE) {
652 /* We are copying all relevant data to the skb - temporarily
653 * sync buffers for the copy */
654 dma = be64_to_cpu(rx_desc->data[0].addr);
655 dma_sync_single_for_cpu(priv->ddev, dma, length,
657 skb_copy_to_linear_data(skb, va, length);
660 unsigned int pull_len;
662 /* Move relevant fragments to skb */
663 used_frags = mlx4_en_complete_rx_desc(priv, rx_desc, frags,
665 if (unlikely(!used_frags)) {
669 skb_shinfo(skb)->nr_frags = used_frags;
671 pull_len = eth_get_headlen(va, SMALL_PACKET_SIZE);
672 /* Copy headers into the skb linear buffer */
673 memcpy(skb->data, va, pull_len);
674 skb->tail += pull_len;
676 /* Skip headers in first fragment */
677 skb_shinfo(skb)->frags[0].page_offset += pull_len;
679 /* Adjust size of first fragment */
680 skb_frag_size_sub(&skb_shinfo(skb)->frags[0], pull_len);
681 skb->data_len = length - pull_len;
686 static void validate_loopback(struct mlx4_en_priv *priv, struct sk_buff *skb)
689 int offset = ETH_HLEN;
691 for (i = 0; i < MLX4_LOOPBACK_TEST_PAYLOAD; i++, offset++) {
692 if (*(skb->data + offset) != (unsigned char) (i & 0xff))
696 priv->loopback_ok = 1;
699 dev_kfree_skb_any(skb);
702 static bool mlx4_en_refill_rx_buffers(struct mlx4_en_priv *priv,
703 struct mlx4_en_rx_ring *ring)
705 u32 missing = ring->actual_size - (ring->prod - ring->cons);
707 /* Try to batch allocations, but not too much. */
711 if (mlx4_en_prepare_rx_desc(priv, ring,
712 ring->prod & ring->size_mask,
713 GFP_ATOMIC | __GFP_COLD |
722 /* When hardware doesn't strip the vlan, we need to calculate the checksum
723 * over it and add it to the hardware's checksum calculation
725 static inline __wsum get_fixed_vlan_csum(__wsum hw_checksum,
726 struct vlan_hdr *vlanh)
728 return csum_add(hw_checksum, *(__wsum *)vlanh);
731 /* Although the stack expects checksum which doesn't include the pseudo
732 * header, the HW adds it. To address that, we are subtracting the pseudo
733 * header checksum from the checksum value provided by the HW.
735 static void get_fixed_ipv4_csum(__wsum hw_checksum, struct sk_buff *skb,
738 __u16 length_for_csum = 0;
739 __wsum csum_pseudo_header = 0;
741 length_for_csum = (be16_to_cpu(iph->tot_len) - (iph->ihl << 2));
742 csum_pseudo_header = csum_tcpudp_nofold(iph->saddr, iph->daddr,
743 length_for_csum, iph->protocol, 0);
744 skb->csum = csum_sub(hw_checksum, csum_pseudo_header);
747 #if IS_ENABLED(CONFIG_IPV6)
748 /* In IPv6 packets, besides subtracting the pseudo header checksum,
749 * we also compute/add the IP header checksum which
750 * is not added by the HW.
752 static int get_fixed_ipv6_csum(__wsum hw_checksum, struct sk_buff *skb,
753 struct ipv6hdr *ipv6h)
755 __wsum csum_pseudo_hdr = 0;
757 if (unlikely(ipv6h->nexthdr == IPPROTO_FRAGMENT ||
758 ipv6h->nexthdr == IPPROTO_HOPOPTS))
760 hw_checksum = csum_add(hw_checksum, (__force __wsum)htons(ipv6h->nexthdr));
762 csum_pseudo_hdr = csum_partial(&ipv6h->saddr,
763 sizeof(ipv6h->saddr) + sizeof(ipv6h->daddr), 0);
764 csum_pseudo_hdr = csum_add(csum_pseudo_hdr, (__force __wsum)ipv6h->payload_len);
765 csum_pseudo_hdr = csum_add(csum_pseudo_hdr, (__force __wsum)ntohs(ipv6h->nexthdr));
767 skb->csum = csum_sub(hw_checksum, csum_pseudo_hdr);
768 skb->csum = csum_add(skb->csum, csum_partial(ipv6h, sizeof(struct ipv6hdr), 0));
772 static int check_csum(struct mlx4_cqe *cqe, struct sk_buff *skb, void *va,
773 netdev_features_t dev_features)
775 __wsum hw_checksum = 0;
777 void *hdr = (u8 *)va + sizeof(struct ethhdr);
779 hw_checksum = csum_unfold((__force __sum16)cqe->checksum);
781 if (cqe->vlan_my_qpn & cpu_to_be32(MLX4_CQE_CVLAN_PRESENT_MASK) &&
782 !(dev_features & NETIF_F_HW_VLAN_CTAG_RX)) {
783 hw_checksum = get_fixed_vlan_csum(hw_checksum, hdr);
784 hdr += sizeof(struct vlan_hdr);
787 if (cqe->status & cpu_to_be16(MLX4_CQE_STATUS_IPV4))
788 get_fixed_ipv4_csum(hw_checksum, skb, hdr);
789 #if IS_ENABLED(CONFIG_IPV6)
790 else if (cqe->status & cpu_to_be16(MLX4_CQE_STATUS_IPV6))
791 if (unlikely(get_fixed_ipv6_csum(hw_checksum, skb, hdr)))
797 int mlx4_en_process_rx_cq(struct net_device *dev, struct mlx4_en_cq *cq, int budget)
799 struct mlx4_en_priv *priv = netdev_priv(dev);
800 struct mlx4_en_dev *mdev = priv->mdev;
801 struct mlx4_cqe *cqe;
802 struct mlx4_en_rx_ring *ring = priv->rx_ring[cq->ring];
803 struct mlx4_en_rx_alloc *frags;
804 struct mlx4_en_rx_desc *rx_desc;
805 struct bpf_prog *xdp_prog;
806 int doorbell_pending;
813 int factor = priv->cqe_factor;
817 if (unlikely(!priv->port_up))
820 if (unlikely(budget <= 0))
823 /* Protect accesses to: ring->xdp_prog, priv->mac_hash list */
825 xdp_prog = rcu_dereference(ring->xdp_prog);
826 doorbell_pending = 0;
828 /* We assume a 1:1 mapping between CQEs and Rx descriptors, so Rx
829 * descriptor offset can be deduced from the CQE index instead of
830 * reading 'cqe->index' */
831 index = cq->mcq.cons_index & ring->size_mask;
832 cqe = mlx4_en_get_cqe(cq->buf, index, priv->cqe_size) + factor;
834 /* Process all completed CQEs */
835 while (XNOR(cqe->owner_sr_opcode & MLX4_CQE_OWNER_MASK,
836 cq->mcq.cons_index & cq->size)) {
838 frags = ring->rx_info + (index << priv->log_rx_info);
839 rx_desc = ring->buf + (index << ring->log_stride);
842 * make sure we read the CQE after we read the ownership bit
846 /* Drop packet on bad receive or bad checksum */
847 if (unlikely((cqe->owner_sr_opcode & MLX4_CQE_OPCODE_MASK) ==
848 MLX4_CQE_OPCODE_ERROR)) {
849 en_err(priv, "CQE completed in error - vendor syndrom:%d syndrom:%d\n",
850 ((struct mlx4_err_cqe *)cqe)->vendor_err_syndrome,
851 ((struct mlx4_err_cqe *)cqe)->syndrome);
854 if (unlikely(cqe->badfcs_enc & MLX4_CQE_BAD_FCS)) {
855 en_dbg(RX_ERR, priv, "Accepted frame with bad FCS\n");
859 /* Check if we need to drop the packet if SRIOV is not enabled
860 * and not performing the selftest or flb disabled
862 if (priv->flags & MLX4_EN_FLAG_RX_FILTER_NEEDED) {
865 /* Get pointer to first fragment since we haven't
866 * skb yet and cast it to ethhdr struct
868 dma = be64_to_cpu(rx_desc->data[0].addr);
869 dma_sync_single_for_cpu(priv->ddev, dma, sizeof(*ethh),
871 ethh = (struct ethhdr *)(page_address(frags[0].page) +
872 frags[0].page_offset);
874 if (is_multicast_ether_addr(ethh->h_dest)) {
875 struct mlx4_mac_entry *entry;
876 struct hlist_head *bucket;
877 unsigned int mac_hash;
879 /* Drop the packet, since HW loopback-ed it */
880 mac_hash = ethh->h_source[MLX4_EN_MAC_HASH_IDX];
881 bucket = &priv->mac_hash[mac_hash];
882 hlist_for_each_entry_rcu(entry, bucket, hlist) {
883 if (ether_addr_equal_64bits(entry->mac,
891 * Packet is OK - process it.
893 length = be32_to_cpu(cqe->byte_cnt);
894 length -= ring->fcs_del;
895 l2_tunnel = (dev->hw_enc_features & NETIF_F_RXCSUM) &&
896 (cqe->vlan_my_qpn & cpu_to_be32(MLX4_CQE_L2_TUNNEL));
898 /* A bpf program gets first chance to drop the packet. It may
899 * read bytes but not past the end of the frag.
907 dma = be64_to_cpu(rx_desc->data[0].addr);
908 dma_sync_single_for_cpu(priv->ddev, dma,
909 priv->frag_info[0].frag_size,
912 xdp.data_hard_start = page_address(frags[0].page);
913 xdp.data = xdp.data_hard_start + frags[0].page_offset;
914 xdp.data_end = xdp.data + length;
915 orig_data = xdp.data;
917 act = bpf_prog_run_xdp(xdp_prog, &xdp);
919 if (xdp.data != orig_data) {
920 length = xdp.data_end - xdp.data;
921 frags[0].page_offset = xdp.data -
929 if (likely(!mlx4_en_xmit_frame(ring, frags, dev,
933 trace_xdp_exception(dev, xdp_prog, act);
934 goto xdp_drop_no_cnt; /* Drop on xmit failure */
936 bpf_warn_invalid_xdp_action(act);
938 trace_xdp_exception(dev, xdp_prog, act);
942 if (likely(mlx4_en_rx_recycle(ring, frags)))
948 ring->bytes += length;
951 if (likely(dev->features & NETIF_F_RXCSUM)) {
952 if (cqe->status & cpu_to_be16(MLX4_CQE_STATUS_TCP |
953 MLX4_CQE_STATUS_UDP)) {
954 if ((cqe->status & cpu_to_be16(MLX4_CQE_STATUS_IPOK)) &&
955 cqe->checksum == cpu_to_be16(0xffff)) {
956 ip_summed = CHECKSUM_UNNECESSARY;
959 ip_summed = CHECKSUM_NONE;
963 if (priv->flags & MLX4_EN_FLAG_RX_CSUM_NON_TCP_UDP &&
964 (cqe->status & cpu_to_be16(MLX4_CQE_STATUS_IPV4 |
965 MLX4_CQE_STATUS_IPV6))) {
966 ip_summed = CHECKSUM_COMPLETE;
967 ring->csum_complete++;
969 ip_summed = CHECKSUM_NONE;
974 ip_summed = CHECKSUM_NONE;
978 /* This packet is eligible for GRO if it is:
979 * - DIX Ethernet (type interpretation)
981 * - without IP options
982 * - not an IP fragment
984 if (dev->features & NETIF_F_GRO) {
985 struct sk_buff *gro_skb = napi_get_frags(&cq->napi);
989 nr = mlx4_en_complete_rx_desc(priv,
990 rx_desc, frags, gro_skb,
995 if (ip_summed == CHECKSUM_COMPLETE) {
996 void *va = skb_frag_address(skb_shinfo(gro_skb)->frags);
997 if (check_csum(cqe, gro_skb, va,
999 ip_summed = CHECKSUM_NONE;
1001 ring->csum_complete--;
1005 skb_shinfo(gro_skb)->nr_frags = nr;
1006 gro_skb->len = length;
1007 gro_skb->data_len = length;
1008 gro_skb->ip_summed = ip_summed;
1010 if (l2_tunnel && ip_summed == CHECKSUM_UNNECESSARY)
1011 gro_skb->csum_level = 1;
1013 if ((cqe->vlan_my_qpn &
1014 cpu_to_be32(MLX4_CQE_CVLAN_PRESENT_MASK)) &&
1015 (dev->features & NETIF_F_HW_VLAN_CTAG_RX)) {
1016 u16 vid = be16_to_cpu(cqe->sl_vid);
1018 __vlan_hwaccel_put_tag(gro_skb, htons(ETH_P_8021Q), vid);
1019 } else if ((be32_to_cpu(cqe->vlan_my_qpn) &
1020 MLX4_CQE_SVLAN_PRESENT_MASK) &&
1021 (dev->features & NETIF_F_HW_VLAN_STAG_RX)) {
1022 __vlan_hwaccel_put_tag(gro_skb,
1023 htons(ETH_P_8021AD),
1024 be16_to_cpu(cqe->sl_vid));
1027 if (dev->features & NETIF_F_RXHASH)
1028 skb_set_hash(gro_skb,
1029 be32_to_cpu(cqe->immed_rss_invalid),
1030 (ip_summed == CHECKSUM_UNNECESSARY) ?
1034 skb_record_rx_queue(gro_skb, cq->ring);
1036 if (ring->hwtstamp_rx_filter == HWTSTAMP_FILTER_ALL) {
1037 timestamp = mlx4_en_get_cqe_ts(cqe);
1038 mlx4_en_fill_hwtstamps(mdev,
1039 skb_hwtstamps(gro_skb),
1043 napi_gro_frags(&cq->napi);
1047 /* GRO not possible, complete processing here */
1048 skb = mlx4_en_rx_skb(priv, rx_desc, frags, length);
1049 if (unlikely(!skb)) {
1054 if (unlikely(priv->validate_loopback)) {
1055 validate_loopback(priv, skb);
1059 if (ip_summed == CHECKSUM_COMPLETE) {
1060 if (check_csum(cqe, skb, skb->data, dev->features)) {
1061 ip_summed = CHECKSUM_NONE;
1062 ring->csum_complete--;
1067 skb->ip_summed = ip_summed;
1068 skb->protocol = eth_type_trans(skb, dev);
1069 skb_record_rx_queue(skb, cq->ring);
1071 if (l2_tunnel && ip_summed == CHECKSUM_UNNECESSARY)
1072 skb->csum_level = 1;
1074 if (dev->features & NETIF_F_RXHASH)
1076 be32_to_cpu(cqe->immed_rss_invalid),
1077 (ip_summed == CHECKSUM_UNNECESSARY) ?
1081 if ((be32_to_cpu(cqe->vlan_my_qpn) &
1082 MLX4_CQE_CVLAN_PRESENT_MASK) &&
1083 (dev->features & NETIF_F_HW_VLAN_CTAG_RX))
1084 __vlan_hwaccel_put_tag(skb, htons(ETH_P_8021Q), be16_to_cpu(cqe->sl_vid));
1085 else if ((be32_to_cpu(cqe->vlan_my_qpn) &
1086 MLX4_CQE_SVLAN_PRESENT_MASK) &&
1087 (dev->features & NETIF_F_HW_VLAN_STAG_RX))
1088 __vlan_hwaccel_put_tag(skb, htons(ETH_P_8021AD),
1089 be16_to_cpu(cqe->sl_vid));
1091 if (ring->hwtstamp_rx_filter == HWTSTAMP_FILTER_ALL) {
1092 timestamp = mlx4_en_get_cqe_ts(cqe);
1093 mlx4_en_fill_hwtstamps(mdev, skb_hwtstamps(skb),
1097 napi_gro_receive(&cq->napi, skb);
1099 for (nr = 0; nr < priv->num_frags; nr++)
1100 mlx4_en_free_frag(priv, frags, nr);
1103 ++cq->mcq.cons_index;
1104 index = (cq->mcq.cons_index) & ring->size_mask;
1105 cqe = mlx4_en_get_cqe(cq->buf, index, priv->cqe_size) + factor;
1106 if (++polled == budget)
1114 if (doorbell_pending)
1115 mlx4_en_xmit_doorbell(priv->tx_ring[TX_XDP][cq->ring]);
1117 mlx4_cq_set_ci(&cq->mcq);
1118 wmb(); /* ensure HW sees CQ consumer before we post new buffers */
1119 ring->cons = cq->mcq.cons_index;
1121 AVG_PERF_COUNTER(priv->pstats.rx_coal_avg, polled);
1123 if (mlx4_en_refill_rx_buffers(priv, ring))
1124 mlx4_en_update_rx_prod_db(ring);
1130 void mlx4_en_rx_irq(struct mlx4_cq *mcq)
1132 struct mlx4_en_cq *cq = container_of(mcq, struct mlx4_en_cq, mcq);
1133 struct mlx4_en_priv *priv = netdev_priv(cq->dev);
1135 if (likely(priv->port_up))
1136 napi_schedule_irqoff(&cq->napi);
1138 mlx4_en_arm_cq(priv, cq);
1141 /* Rx CQ polling - called by NAPI */
1142 int mlx4_en_poll_rx_cq(struct napi_struct *napi, int budget)
1144 struct mlx4_en_cq *cq = container_of(napi, struct mlx4_en_cq, napi);
1145 struct net_device *dev = cq->dev;
1146 struct mlx4_en_priv *priv = netdev_priv(dev);
1149 done = mlx4_en_process_rx_cq(dev, cq, budget);
1151 /* If we used up all the quota - we're probably not done yet... */
1152 if (done == budget) {
1153 const struct cpumask *aff;
1154 struct irq_data *idata;
1157 INC_PERF_COUNTER(priv->pstats.napi_quota);
1159 cpu_curr = smp_processor_id();
1160 idata = irq_desc_get_irq_data(cq->irq_desc);
1161 aff = irq_data_get_affinity_mask(idata);
1163 if (likely(cpumask_test_cpu(cpu_curr, aff)))
1166 /* Current cpu is not according to smp_irq_affinity -
1167 * probably affinity changed. Need to stop this NAPI
1168 * poll, and restart it on the right CPU.
1169 * Try to avoid returning a too small value (like 0),
1170 * to not fool net_rx_action() and its netdev_budget
1176 if (napi_complete_done(napi, done))
1177 mlx4_en_arm_cq(priv, cq);
1181 static const int frag_sizes[] = {
1188 void mlx4_en_calc_rx_buf(struct net_device *dev)
1190 struct mlx4_en_priv *priv = netdev_priv(dev);
1191 int eff_mtu = MLX4_EN_EFF_MTU(dev->mtu);
1194 /* bpf requires buffers to be set up as 1 packet per page.
1195 * This only works when num_frags == 1.
1197 if (priv->tx_ring_num[TX_XDP]) {
1198 priv->frag_info[0].order = 0;
1199 priv->frag_info[0].frag_size = eff_mtu;
1200 priv->frag_info[0].frag_prefix_size = 0;
1201 /* This will gain efficient xdp frame recycling at the
1202 * expense of more costly truesize accounting
1204 priv->frag_info[0].frag_stride = PAGE_SIZE;
1205 priv->frag_info[0].dma_dir = PCI_DMA_BIDIRECTIONAL;
1206 priv->frag_info[0].rx_headroom = XDP_PACKET_HEADROOM;
1211 while (buf_size < eff_mtu) {
1212 priv->frag_info[i].order = MLX4_EN_ALLOC_PREFER_ORDER;
1213 priv->frag_info[i].frag_size =
1214 (eff_mtu > buf_size + frag_sizes[i]) ?
1215 frag_sizes[i] : eff_mtu - buf_size;
1216 priv->frag_info[i].frag_prefix_size = buf_size;
1217 priv->frag_info[i].frag_stride =
1218 ALIGN(priv->frag_info[i].frag_size,
1220 priv->frag_info[i].dma_dir = PCI_DMA_FROMDEVICE;
1221 priv->frag_info[i].rx_headroom = 0;
1222 buf_size += priv->frag_info[i].frag_size;
1227 priv->num_frags = i;
1228 priv->rx_skb_size = eff_mtu;
1229 priv->log_rx_info = ROUNDUP_LOG2(i * sizeof(struct mlx4_en_rx_alloc));
1231 en_dbg(DRV, priv, "Rx buffer scatter-list (effective-mtu:%d num_frags:%d):\n",
1232 eff_mtu, priv->num_frags);
1233 for (i = 0; i < priv->num_frags; i++) {
1235 " frag:%d - size:%d prefix:%d stride:%d\n",
1237 priv->frag_info[i].frag_size,
1238 priv->frag_info[i].frag_prefix_size,
1239 priv->frag_info[i].frag_stride);
1243 /* RSS related functions */
1245 static int mlx4_en_config_rss_qp(struct mlx4_en_priv *priv, int qpn,
1246 struct mlx4_en_rx_ring *ring,
1247 enum mlx4_qp_state *state,
1250 struct mlx4_en_dev *mdev = priv->mdev;
1251 struct mlx4_qp_context *context;
1254 context = kmalloc(sizeof(*context), GFP_KERNEL);
1258 err = mlx4_qp_alloc(mdev->dev, qpn, qp, GFP_KERNEL);
1260 en_err(priv, "Failed to allocate qp #%x\n", qpn);
1263 qp->event = mlx4_en_sqp_event;
1265 memset(context, 0, sizeof *context);
1266 mlx4_en_fill_qp_context(priv, ring->actual_size, ring->stride, 0, 0,
1267 qpn, ring->cqn, -1, context);
1268 context->db_rec_addr = cpu_to_be64(ring->wqres.db.dma);
1270 /* Cancel FCS removal if FW allows */
1271 if (mdev->dev->caps.flags & MLX4_DEV_CAP_FLAG_FCS_KEEP) {
1272 context->param3 |= cpu_to_be32(1 << 29);
1273 if (priv->dev->features & NETIF_F_RXFCS)
1276 ring->fcs_del = ETH_FCS_LEN;
1280 err = mlx4_qp_to_ready(mdev->dev, &ring->wqres.mtt, context, qp, state);
1282 mlx4_qp_remove(mdev->dev, qp);
1283 mlx4_qp_free(mdev->dev, qp);
1285 mlx4_en_update_rx_prod_db(ring);
1291 int mlx4_en_create_drop_qp(struct mlx4_en_priv *priv)
1296 err = mlx4_qp_reserve_range(priv->mdev->dev, 1, 1, &qpn,
1297 MLX4_RESERVE_A0_QP);
1299 en_err(priv, "Failed reserving drop qpn\n");
1302 err = mlx4_qp_alloc(priv->mdev->dev, qpn, &priv->drop_qp, GFP_KERNEL);
1304 en_err(priv, "Failed allocating drop qp\n");
1305 mlx4_qp_release_range(priv->mdev->dev, qpn, 1);
1312 void mlx4_en_destroy_drop_qp(struct mlx4_en_priv *priv)
1316 qpn = priv->drop_qp.qpn;
1317 mlx4_qp_remove(priv->mdev->dev, &priv->drop_qp);
1318 mlx4_qp_free(priv->mdev->dev, &priv->drop_qp);
1319 mlx4_qp_release_range(priv->mdev->dev, qpn, 1);
1322 /* Allocate rx qp's and configure them according to rss map */
1323 int mlx4_en_config_rss_steer(struct mlx4_en_priv *priv)
1325 struct mlx4_en_dev *mdev = priv->mdev;
1326 struct mlx4_en_rss_map *rss_map = &priv->rss_map;
1327 struct mlx4_qp_context context;
1328 struct mlx4_rss_context *rss_context;
1331 u8 rss_mask = (MLX4_RSS_IPV4 | MLX4_RSS_TCP_IPV4 | MLX4_RSS_IPV6 |
1337 en_dbg(DRV, priv, "Configuring rss steering\n");
1338 err = mlx4_qp_reserve_range(mdev->dev, priv->rx_ring_num,
1340 &rss_map->base_qpn, 0);
1342 en_err(priv, "Failed reserving %d qps\n", priv->rx_ring_num);
1346 for (i = 0; i < priv->rx_ring_num; i++) {
1347 qpn = rss_map->base_qpn + i;
1348 err = mlx4_en_config_rss_qp(priv, qpn, priv->rx_ring[i],
1357 /* Configure RSS indirection qp */
1358 err = mlx4_qp_alloc(mdev->dev, priv->base_qpn, &rss_map->indir_qp, GFP_KERNEL);
1360 en_err(priv, "Failed to allocate RSS indirection QP\n");
1363 rss_map->indir_qp.event = mlx4_en_sqp_event;
1364 mlx4_en_fill_qp_context(priv, 0, 0, 0, 1, priv->base_qpn,
1365 priv->rx_ring[0]->cqn, -1, &context);
1367 if (!priv->prof->rss_rings || priv->prof->rss_rings > priv->rx_ring_num)
1368 rss_rings = priv->rx_ring_num;
1370 rss_rings = priv->prof->rss_rings;
1372 ptr = ((void *) &context) + offsetof(struct mlx4_qp_context, pri_path)
1373 + MLX4_RSS_OFFSET_IN_QPC_PRI_PATH;
1375 rss_context->base_qpn = cpu_to_be32(ilog2(rss_rings) << 24 |
1376 (rss_map->base_qpn));
1377 rss_context->default_qpn = cpu_to_be32(rss_map->base_qpn);
1378 if (priv->mdev->profile.udp_rss) {
1379 rss_mask |= MLX4_RSS_UDP_IPV4 | MLX4_RSS_UDP_IPV6;
1380 rss_context->base_qpn_udp = rss_context->default_qpn;
1383 if (mdev->dev->caps.tunnel_offload_mode == MLX4_TUNNEL_OFFLOAD_MODE_VXLAN) {
1384 en_info(priv, "Setting RSS context tunnel type to RSS on inner headers\n");
1385 rss_mask |= MLX4_RSS_BY_INNER_HEADERS;
1388 rss_context->flags = rss_mask;
1389 rss_context->hash_fn = MLX4_RSS_HASH_TOP;
1390 if (priv->rss_hash_fn == ETH_RSS_HASH_XOR) {
1391 rss_context->hash_fn = MLX4_RSS_HASH_XOR;
1392 } else if (priv->rss_hash_fn == ETH_RSS_HASH_TOP) {
1393 rss_context->hash_fn = MLX4_RSS_HASH_TOP;
1394 memcpy(rss_context->rss_key, priv->rss_key,
1395 MLX4_EN_RSS_KEY_SIZE);
1397 en_err(priv, "Unknown RSS hash function requested\n");
1401 err = mlx4_qp_to_ready(mdev->dev, &priv->res.mtt, &context,
1402 &rss_map->indir_qp, &rss_map->indir_state);
1409 mlx4_qp_modify(mdev->dev, NULL, rss_map->indir_state,
1410 MLX4_QP_STATE_RST, NULL, 0, 0, &rss_map->indir_qp);
1411 mlx4_qp_remove(mdev->dev, &rss_map->indir_qp);
1412 mlx4_qp_free(mdev->dev, &rss_map->indir_qp);
1414 for (i = 0; i < good_qps; i++) {
1415 mlx4_qp_modify(mdev->dev, NULL, rss_map->state[i],
1416 MLX4_QP_STATE_RST, NULL, 0, 0, &rss_map->qps[i]);
1417 mlx4_qp_remove(mdev->dev, &rss_map->qps[i]);
1418 mlx4_qp_free(mdev->dev, &rss_map->qps[i]);
1420 mlx4_qp_release_range(mdev->dev, rss_map->base_qpn, priv->rx_ring_num);
1424 void mlx4_en_release_rss_steer(struct mlx4_en_priv *priv)
1426 struct mlx4_en_dev *mdev = priv->mdev;
1427 struct mlx4_en_rss_map *rss_map = &priv->rss_map;
1430 mlx4_qp_modify(mdev->dev, NULL, rss_map->indir_state,
1431 MLX4_QP_STATE_RST, NULL, 0, 0, &rss_map->indir_qp);
1432 mlx4_qp_remove(mdev->dev, &rss_map->indir_qp);
1433 mlx4_qp_free(mdev->dev, &rss_map->indir_qp);
1435 for (i = 0; i < priv->rx_ring_num; i++) {
1436 mlx4_qp_modify(mdev->dev, NULL, rss_map->state[i],
1437 MLX4_QP_STATE_RST, NULL, 0, 0, &rss_map->qps[i]);
1438 mlx4_qp_remove(mdev->dev, &rss_map->qps[i]);
1439 mlx4_qp_free(mdev->dev, &rss_map->qps[i]);
1441 mlx4_qp_release_range(mdev->dev, rss_map->base_qpn, priv->rx_ring_num);