drivers/net/ethernet/mellanox/mlx4/en_tx.c

   1 /*
   2  * Copyright (c) 2007 Mellanox Technologies. All rights reserved.
   3  *
   4  * This software is available to you under a choice of one of two
   5  * licenses.  You may choose to be licensed under the terms of the GNU
   6  * General Public License (GPL) Version 2, available from the file
   7  * COPYING in the main directory of this source tree, or the
   8  * OpenIB.org BSD license below:
   9  *
  10  *     Redistribution and use in source and binary forms, with or
  11  *     without modification, are permitted provided that the following
  12  *     conditions are met:
  13  *
  14  *      - Redistributions of source code must retain the above
  15  *        copyright notice, this list of conditions and the following
  16  *        disclaimer.
  17  *
  18  *      - Redistributions in binary form must reproduce the above
  19  *        copyright notice, this list of conditions and the following
  20  *        disclaimer in the documentation and/or other materials
  21  *        provided with the distribution.
  22  *
  23  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
  24  * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
  25  * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
  26  * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
  27  * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
  28  * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
  29  * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
  30  * SOFTWARE.
  31  *
  32  */
  33
  34 #include <asm/page.h>
  35 #include <linux/mlx4/cq.h>
  36 #include <linux/slab.h>
  37 #include <linux/mlx4/qp.h>
  38 #include <linux/skbuff.h>
  39 #include <linux/if_vlan.h>
  40 #include <linux/prefetch.h>
  41 #include <linux/vmalloc.h>
  42 #include <linux/tcp.h>
  43 #include <linux/ip.h>
  44 #include <linux/moduleparam.h>
  45
  46 #include "mlx4_en.h"
  47
  48 int mlx4_en_create_tx_ring(struct mlx4_en_priv *priv,
  49                            struct mlx4_en_tx_ring **pring, int qpn, u32 size,
  50                            u16 stride, int node, int queue_index)
  51 {
  52         struct mlx4_en_dev *mdev = priv->mdev;
  53         struct mlx4_en_tx_ring *ring;
  54         int tmp;
  55         int err;
  56
  57         ring = kzalloc_node(sizeof(*ring), GFP_KERNEL, node);
  58         if (!ring) {
  59                 ring = kzalloc(sizeof(*ring), GFP_KERNEL);
  60                 if (!ring) {
  61                         en_err(priv, "Failed allocating TX ring\n");
  62                         return -ENOMEM;
  63                 }
  64         }
  65
  66         ring->size = size;
  67         ring->size_mask = size - 1;
  68         ring->stride = stride;
  69
  70         tmp = size * sizeof(struct mlx4_en_tx_info);
  71         ring->tx_info = kmalloc_node(tmp, GFP_KERNEL | __GFP_NOWARN, node);
  72         if (!ring->tx_info) {
  73                 ring->tx_info = vmalloc(tmp);
  74                 if (!ring->tx_info) {
  75                         err = -ENOMEM;
  76                         goto err_ring;
  77                 }
  78         }
  79
  80         en_dbg(DRV, priv, "Allocated tx_info ring at addr:%p size:%d\n",
  81                  ring->tx_info, tmp);
  82
  83         ring->bounce_buf = kmalloc_node(MAX_DESC_SIZE, GFP_KERNEL, node);
  84         if (!ring->bounce_buf) {
  85                 ring->bounce_buf = kmalloc(MAX_DESC_SIZE, GFP_KERNEL);
  86                 if (!ring->bounce_buf) {
  87                         err = -ENOMEM;
  88                         goto err_info;
  89                 }
  90         }
  91         ring->buf_size = ALIGN(size * ring->stride, MLX4_EN_PAGE_SIZE);
  92
  93         /* Allocate HW buffers on provided NUMA node */
  94         set_dev_node(&mdev->dev->pdev->dev, node);
  95         err = mlx4_alloc_hwq_res(mdev->dev, &ring->wqres, ring->buf_size,
  96                                  2 * PAGE_SIZE);
  97         set_dev_node(&mdev->dev->pdev->dev, mdev->dev->numa_node);
  98         if (err) {
  99                 en_err(priv, "Failed allocating hwq resources\n");
 100                 goto err_bounce;
 101         }
 102
 103         err = mlx4_en_map_buffer(&ring->wqres.buf);
 104         if (err) {
 105                 en_err(priv, "Failed to map TX buffer\n");
 106                 goto err_hwq_res;
 107         }
 108
 109         ring->buf = ring->wqres.buf.direct.buf;
 110
 111         en_dbg(DRV, priv, "Allocated TX ring (addr:%p) - buf:%p size:%d buf_size:%d dma:%llx\n",
 112                ring, ring->buf, ring->size, ring->buf_size,
 113                (unsigned long long) ring->wqres.buf.direct.map);
 114
 115         ring->qpn = qpn;
 116         err = mlx4_qp_alloc(mdev->dev, ring->qpn, &ring->qp, GFP_KERNEL);
 117         if (err) {
 118                 en_err(priv, "Failed allocating qp %d\n", ring->qpn);
 119                 goto err_map;
 120         }
 121         ring->qp.event = mlx4_en_sqp_event;
 122
 123         err = mlx4_bf_alloc(mdev->dev, &ring->bf, node);
 124         if (err) {
 125                 en_dbg(DRV, priv, "working without blueflame (%d)\n", err);
 126                 ring->bf.uar = &mdev->priv_uar;
 127                 ring->bf.uar->map = mdev->uar_map;
 128                 ring->bf_enabled = false;
 129                 ring->bf_alloced = false;
 130                 priv->pflags &= ~MLX4_EN_PRIV_FLAGS_BLUEFLAME;
 131         } else {
 132                 ring->bf_alloced = true;
 133                 ring->bf_enabled = !!(priv->pflags &
 134                                       MLX4_EN_PRIV_FLAGS_BLUEFLAME);
 135         }
 136
 137         ring->hwtstamp_tx_type = priv->hwtstamp_config.tx_type;
 138         ring->queue_index = queue_index;
 139
 140         if (queue_index < priv->num_tx_rings_p_up && cpu_online(queue_index))
 141                 cpumask_set_cpu(queue_index, &ring->affinity_mask);
 142
 143         *pring = ring;
 144         return 0;
 145
 146 err_map:
 147         mlx4_en_unmap_buffer(&ring->wqres.buf);
 148 err_hwq_res:
 149         mlx4_free_hwq_res(mdev->dev, &ring->wqres, ring->buf_size);
 150 err_bounce:
 151         kfree(ring->bounce_buf);
 152         ring->bounce_buf = NULL;
 153 err_info:
 154         kvfree(ring->tx_info);
 155         ring->tx_info = NULL;
 156 err_ring:
 157         kfree(ring);
 158         *pring = NULL;
 159         return err;
 160 }
 161
 162 void mlx4_en_destroy_tx_ring(struct mlx4_en_priv *priv,
 163                              struct mlx4_en_tx_ring **pring)
 164 {
 165         struct mlx4_en_dev *mdev = priv->mdev;
 166         struct mlx4_en_tx_ring *ring = *pring;
 167         en_dbg(DRV, priv, "Destroying tx ring, qpn: %d\n", ring->qpn);
 168
 169         if (ring->bf_alloced)
 170                 mlx4_bf_free(mdev->dev, &ring->bf);
 171         mlx4_qp_remove(mdev->dev, &ring->qp);
 172         mlx4_qp_free(mdev->dev, &ring->qp);
 173         mlx4_en_unmap_buffer(&ring->wqres.buf);
 174         mlx4_free_hwq_res(mdev->dev, &ring->wqres, ring->buf_size);
 175         kfree(ring->bounce_buf);
 176         ring->bounce_buf = NULL;
 177         kvfree(ring->tx_info);
 178         ring->tx_info = NULL;
 179         kfree(ring);
 180         *pring = NULL;
 181 }
 182
 183 int mlx4_en_activate_tx_ring(struct mlx4_en_priv *priv,
 184                              struct mlx4_en_tx_ring *ring,
 185                              int cq, int user_prio)
 186 {
 187         struct mlx4_en_dev *mdev = priv->mdev;
 188         int err;
 189
 190         ring->cqn = cq;
 191         ring->prod = 0;
 192         ring->cons = 0xffffffff;
 193         ring->last_nr_txbb = 1;
 194         memset(ring->tx_info, 0, ring->size * sizeof(struct mlx4_en_tx_info));
 195         memset(ring->buf, 0, ring->buf_size);
 196
 197         ring->qp_state = MLX4_QP_STATE_RST;
 198         ring->doorbell_qpn = cpu_to_be32(ring->qp.qpn << 8);
 199         ring->mr_key = cpu_to_be32(mdev->mr.key);
 200
 201         mlx4_en_fill_qp_context(priv, ring->size, ring->stride, 1, 0, ring->qpn,
 202                                 ring->cqn, user_prio, &ring->context);
 203         if (ring->bf_alloced)
 204                 ring->context.usr_page = cpu_to_be32(ring->bf.uar->index);
 205
 206         err = mlx4_qp_to_ready(mdev->dev, &ring->wqres.mtt, &ring->context,
 207                                &ring->qp, &ring->qp_state);
 208         if (!user_prio && cpu_online(ring->queue_index))
 209                 netif_set_xps_queue(priv->dev, &ring->affinity_mask,
 210                                     ring->queue_index);
 211
 212         return err;
 213 }
 214
 215 void mlx4_en_deactivate_tx_ring(struct mlx4_en_priv *priv,
 216                                 struct mlx4_en_tx_ring *ring)
 217 {
 218         struct mlx4_en_dev *mdev = priv->mdev;
 219
 220         mlx4_qp_modify(mdev->dev, NULL, ring->qp_state,
 221                        MLX4_QP_STATE_RST, NULL, 0, 0, &ring->qp);
 222 }
 223
 224 static void mlx4_en_stamp_wqe(struct mlx4_en_priv *priv,
 225                               struct mlx4_en_tx_ring *ring, int index,
 226                               u8 owner)
 227 {
 228         __be32 stamp = cpu_to_be32(STAMP_VAL | (!!owner << STAMP_SHIFT));
 229         struct mlx4_en_tx_desc *tx_desc = ring->buf + index * TXBB_SIZE;
 230         struct mlx4_en_tx_info *tx_info = &ring->tx_info[index];
 231         void *end = ring->buf + ring->buf_size;
 232         __be32 *ptr = (__be32 *)tx_desc;
 233         int i;
 234
 235         /* Optimize the common case when there are no wraparounds */
 236         if (likely((void *)tx_desc + tx_info->nr_txbb * TXBB_SIZE <= end)) {
 237                 /* Stamp the freed descriptor */
 238                 for (i = 0; i < tx_info->nr_txbb * TXBB_SIZE;
 239                      i += STAMP_STRIDE) {
 240                         *ptr = stamp;
 241                         ptr += STAMP_DWORDS;
 242                 }
 243         } else {
 244                 /* Stamp the freed descriptor */
 245                 for (i = 0; i < tx_info->nr_txbb * TXBB_SIZE;
 246                      i += STAMP_STRIDE) {
 247                         *ptr = stamp;
 248                         ptr += STAMP_DWORDS;
 249                         if ((void *)ptr >= end) {
 250                                 ptr = ring->buf;
 251                                 stamp ^= cpu_to_be32(0x80000000);
 252                         }
 253                 }
 254         }
 255 }
 256
 257
 258 static u32 mlx4_en_free_tx_desc(struct mlx4_en_priv *priv,
 259                                 struct mlx4_en_tx_ring *ring,
 260                                 int index, u8 owner, u64 timestamp)
 261 {
 262         struct mlx4_en_tx_info *tx_info = &ring->tx_info[index];
 263         struct mlx4_en_tx_desc *tx_desc = ring->buf + index * TXBB_SIZE;
 264         struct mlx4_wqe_data_seg *data = (void *) tx_desc + tx_info->data_offset;
 265         void *end = ring->buf + ring->buf_size;
 266         struct sk_buff *skb = tx_info->skb;
 267         int nr_maps = tx_info->nr_maps;
 268         int i;
 269
 270         /* We do not touch skb here, so prefetch skb->users location
 271          * to speedup consume_skb()
 272          */
 273         prefetchw(&skb->users);
 274
 275         if (unlikely(timestamp)) {
 276                 struct skb_shared_hwtstamps hwts;
 277
 278                 mlx4_en_fill_hwtstamps(priv->mdev, &hwts, timestamp);
 279                 skb_tstamp_tx(skb, &hwts);
 280         }
 281
 282         /* Optimize the common case when there are no wraparounds */
 283         if (likely((void *) tx_desc + tx_info->nr_txbb * TXBB_SIZE <= end)) {
 284                 if (!tx_info->inl) {
 285                         if (tx_info->linear)
 286                                 dma_unmap_single(priv->ddev,
 287                                                 tx_info->map0_dma,
 288                                                 tx_info->map0_byte_count,
 289                                                 PCI_DMA_TODEVICE);
 290                         else
 291                                 dma_unmap_page(priv->ddev,
 292                                                tx_info->map0_dma,
 293                                                tx_info->map0_byte_count,
 294                                                PCI_DMA_TODEVICE);
 295                         for (i = 1; i < nr_maps; i++) {
 296                                 data++;
 297                                 dma_unmap_page(priv->ddev,
 298                                         (dma_addr_t)be64_to_cpu(data->addr),
 299                                         be32_to_cpu(data->byte_count),
 300                                         PCI_DMA_TODEVICE);
 301                         }
 302                 }
 303         } else {
 304                 if (!tx_info->inl) {
 305                         if ((void *) data >= end) {
 306                                 data = ring->buf + ((void *)data - end);
 307                         }
 308
 309                         if (tx_info->linear)
 310                                 dma_unmap_single(priv->ddev,
 311                                                 tx_info->map0_dma,
 312                                                 tx_info->map0_byte_count,
 313                                                 PCI_DMA_TODEVICE);
 314                         else
 315                                 dma_unmap_page(priv->ddev,
 316                                                tx_info->map0_dma,
 317                                                tx_info->map0_byte_count,
 318                                                PCI_DMA_TODEVICE);
 319                         for (i = 1; i < nr_maps; i++) {
 320                                 data++;
 321                                 /* Check for wraparound before unmapping */
 322                                 if ((void *) data >= end)
 323                                         data = ring->buf;
 324                                 dma_unmap_page(priv->ddev,
 325                                         (dma_addr_t)be64_to_cpu(data->addr),
 326                                         be32_to_cpu(data->byte_count),
 327                                         PCI_DMA_TODEVICE);
 328                         }
 329                 }
 330         }
 331         dev_consume_skb_any(skb);
 332         return tx_info->nr_txbb;
 333 }
 334
 335
 336 int mlx4_en_free_tx_buf(struct net_device *dev, struct mlx4_en_tx_ring *ring)
 337 {
 338         struct mlx4_en_priv *priv = netdev_priv(dev);
 339         int cnt = 0;
 340
 341         /* Skip last polled descriptor */
 342         ring->cons += ring->last_nr_txbb;
 343         en_dbg(DRV, priv, "Freeing Tx buf - cons:0x%x prod:0x%x\n",
 344                  ring->cons, ring->prod);
 345
 346         if ((u32) (ring->prod - ring->cons) > ring->size) {
 347                 if (netif_msg_tx_err(priv))
 348                         en_warn(priv, "Tx consumer passed producer!\n");
 349                 return 0;
 350         }
 351
 352         while (ring->cons != ring->prod) {
 353                 ring->last_nr_txbb = mlx4_en_free_tx_desc(priv, ring,
 354                                                 ring->cons & ring->size_mask,
 355                                                 !!(ring->cons & ring->size), 0);
 356                 ring->cons += ring->last_nr_txbb;
 357                 cnt++;
 358         }
 359
 360         netdev_tx_reset_queue(ring->tx_queue);
 361
 362         if (cnt)
 363                 en_dbg(DRV, priv, "Freed %d uncompleted tx descriptors\n", cnt);
 364
 365         return cnt;
 366 }
 367
 368 static bool mlx4_en_process_tx_cq(struct net_device *dev,
 369                                  struct mlx4_en_cq *cq)
 370 {
 371         struct mlx4_en_priv *priv = netdev_priv(dev);
 372         struct mlx4_cq *mcq = &cq->mcq;
 373         struct mlx4_en_tx_ring *ring = priv->tx_ring[cq->ring];
 374         struct mlx4_cqe *cqe;
 375         u16 index;
 376         u16 new_index, ring_index, stamp_index;
 377         u32 txbbs_skipped = 0;
 378         u32 txbbs_stamp = 0;
 379         u32 cons_index = mcq->cons_index;
 380         int size = cq->size;
 381         u32 size_mask = ring->size_mask;
 382         struct mlx4_cqe *buf = cq->buf;
 383         u32 packets = 0;
 384         u32 bytes = 0;
 385         int factor = priv->cqe_factor;
 386         u64 timestamp = 0;
 387         int done = 0;
 388         int budget = priv->tx_work_limit;
 389         u32 last_nr_txbb;
 390         u32 ring_cons;
 391
 392         if (!priv->port_up)
 393                 return true;
 394
 395         prefetchw(&ring->tx_queue->dql.limit);
 396         index = cons_index & size_mask;
 397         cqe = mlx4_en_get_cqe(buf, index, priv->cqe_size) + factor;
 398         last_nr_txbb = ACCESS_ONCE(ring->last_nr_txbb);
 399         ring_cons = ACCESS_ONCE(ring->cons);
 400         ring_index = ring_cons & size_mask;
 401         stamp_index = ring_index;
 402
 403         /* Process all completed CQEs */
 404         while (XNOR(cqe->owner_sr_opcode & MLX4_CQE_OWNER_MASK,
 405                         cons_index & size) && (done < budget)) {
 406                 /*
 407                  * make sure we read the CQE after we read the
 408                  * ownership bit
 409                  */
 410                 rmb();
 411
 412                 if (unlikely((cqe->owner_sr_opcode & MLX4_CQE_OPCODE_MASK) ==
 413                              MLX4_CQE_OPCODE_ERROR)) {
 414                         struct mlx4_err_cqe *cqe_err = (struct mlx4_err_cqe *)cqe;
 415
 416                         en_err(priv, "CQE error - vendor syndrome: 0x%x syndrome: 0x%x\n",
 417                                cqe_err->vendor_err_syndrome,
 418                                cqe_err->syndrome);
 419                 }
 420
 421                 /* Skip over last polled CQE */
 422                 new_index = be16_to_cpu(cqe->wqe_index) & size_mask;
 423
 424                 do {
 425                         txbbs_skipped += last_nr_txbb;
 426                         ring_index = (ring_index + last_nr_txbb) & size_mask;
 427                         if (ring->tx_info[ring_index].ts_requested)
 428                                 timestamp = mlx4_en_get_cqe_ts(cqe);
 429
 430                         /* free next descriptor */
 431                         last_nr_txbb = mlx4_en_free_tx_desc(
 432                                         priv, ring, ring_index,
 433                                         !!((ring_cons + txbbs_skipped) &
 434                                         ring->size), timestamp);
 435
 436                         mlx4_en_stamp_wqe(priv, ring, stamp_index,
 437                                           !!((ring_cons + txbbs_stamp) &
 438                                                 ring->size));
 439                         stamp_index = ring_index;
 440                         txbbs_stamp = txbbs_skipped;
 441                         packets++;
 442                         bytes += ring->tx_info[ring_index].nr_bytes;
 443                 } while ((++done < budget) && (ring_index != new_index));
 444
 445                 ++cons_index;
 446                 index = cons_index & size_mask;
 447                 cqe = mlx4_en_get_cqe(buf, index, priv->cqe_size) + factor;
 448         }
 449
 450
 451         /*
 452          * To prevent CQ overflow we first update CQ consumer and only then
 453          * the ring consumer.
 454          */
 455         mcq->cons_index = cons_index;
 456         mlx4_cq_set_ci(mcq);
 457         wmb();
 458
 459         /* we want to dirty this cache line once */
 460         ACCESS_ONCE(ring->last_nr_txbb) = last_nr_txbb;
 461         ACCESS_ONCE(ring->cons) = ring_cons + txbbs_skipped;
 462
 463         netdev_tx_completed_queue(ring->tx_queue, packets, bytes);
 464
 465         /*
 466          * Wakeup Tx queue if this stopped, and at least 1 packet
 467          * was completed
 468          */
 469         if (netif_tx_queue_stopped(ring->tx_queue) && txbbs_skipped > 0) {
 470                 netif_tx_wake_queue(ring->tx_queue);
 471                 ring->wake_queue++;
 472         }
 473         return done < budget;
 474 }
 475
 476 void mlx4_en_tx_irq(struct mlx4_cq *mcq)
 477 {
 478         struct mlx4_en_cq *cq = container_of(mcq, struct mlx4_en_cq, mcq);
 479         struct mlx4_en_priv *priv = netdev_priv(cq->dev);
 480
 481         if (priv->port_up)
 482                 napi_schedule(&cq->napi);
 483         else
 484                 mlx4_en_arm_cq(priv, cq);
 485 }
 486
 487 /* TX CQ polling - called by NAPI */
 488 int mlx4_en_poll_tx_cq(struct napi_struct *napi, int budget)
 489 {
 490         struct mlx4_en_cq *cq = container_of(napi, struct mlx4_en_cq, napi);
 491         struct net_device *dev = cq->dev;
 492         struct mlx4_en_priv *priv = netdev_priv(dev);
 493         int clean_complete;
 494
 495         clean_complete = mlx4_en_process_tx_cq(dev, cq);
 496         if (!clean_complete)
 497                 return budget;
 498
 499         napi_complete(napi);
 500         mlx4_en_arm_cq(priv, cq);
 501
 502         return 0;
 503 }
 504
 505 static struct mlx4_en_tx_desc *mlx4_en_bounce_to_desc(struct mlx4_en_priv *priv,
 506                                                       struct mlx4_en_tx_ring *ring,
 507                                                       u32 index,
 508                                                       unsigned int desc_size)
 509 {
 510         u32 copy = (ring->size - index) * TXBB_SIZE;
 511         int i;
 512
 513         for (i = desc_size - copy - 4; i >= 0; i -= 4) {
 514                 if ((i & (TXBB_SIZE - 1)) == 0)
 515                         wmb();
 516
 517                 *((u32 *) (ring->buf + i)) =
 518                         *((u32 *) (ring->bounce_buf + copy + i));
 519         }
 520
 521         for (i = copy - 4; i >= 4 ; i -= 4) {
 522                 if ((i & (TXBB_SIZE - 1)) == 0)
 523                         wmb();
 524
 525                 *((u32 *) (ring->buf + index * TXBB_SIZE + i)) =
 526                         *((u32 *) (ring->bounce_buf + i));
 527         }
 528
 529         /* Return real descriptor location */
 530         return ring->buf + index * TXBB_SIZE;
 531 }
 532
 533 /* Decide if skb can be inlined in tx descriptor to avoid dma mapping
 534  *
 535  * It seems strange we do not simply use skb_copy_bits().
 536  * This would allow to inline all skbs iff skb->len <= inline_thold
 537  *
 538  * Note that caller already checked skb was not a gso packet
 539  */
 540 static bool is_inline(int inline_thold, const struct sk_buff *skb,
 541                       const struct skb_shared_info *shinfo,
 542                       void **pfrag)
 543 {
 544         void *ptr;
 545
 546         if (skb->len > inline_thold || !inline_thold)
 547                 return false;
 548
 549         if (shinfo->nr_frags == 1) {
 550                 ptr = skb_frag_address_safe(&shinfo->frags[0]);
 551                 if (unlikely(!ptr))
 552                         return false;
 553                 *pfrag = ptr;
 554                 return true;
 555         }
 556         if (shinfo->nr_frags)
 557                 return false;
 558         return true;
 559 }
 560
 561 static int inline_size(const struct sk_buff *skb)
 562 {
 563         if (skb->len + CTRL_SIZE + sizeof(struct mlx4_wqe_inline_seg)
 564             <= MLX4_INLINE_ALIGN)
 565                 return ALIGN(skb->len + CTRL_SIZE +
 566                              sizeof(struct mlx4_wqe_inline_seg), 16);
 567         else
 568                 return ALIGN(skb->len + CTRL_SIZE + 2 *
 569                              sizeof(struct mlx4_wqe_inline_seg), 16);
 570 }
 571
 572 static int get_real_size(const struct sk_buff *skb,
 573                          const struct skb_shared_info *shinfo,
 574                          struct net_device *dev,
 575                          int *lso_header_size,
 576                          bool *inline_ok,
 577                          void **pfrag)
 578 {
 579         struct mlx4_en_priv *priv = netdev_priv(dev);
 580         int real_size;
 581
 582         if (shinfo->gso_size) {
 583                 *inline_ok = false;
 584                 if (skb->encapsulation)
 585                         *lso_header_size = (skb_inner_transport_header(skb) - skb->data) + inner_tcp_hdrlen(skb);
 586                 else
 587                         *lso_header_size = skb_transport_offset(skb) + tcp_hdrlen(skb);
 588                 real_size = CTRL_SIZE + shinfo->nr_frags * DS_SIZE +
 589                         ALIGN(*lso_header_size + 4, DS_SIZE);
 590                 if (unlikely(*lso_header_size != skb_headlen(skb))) {
 591                         /* We add a segment for the skb linear buffer only if
 592                          * it contains data */
 593                         if (*lso_header_size < skb_headlen(skb))
 594                                 real_size += DS_SIZE;
 595                         else {
 596                                 if (netif_msg_tx_err(priv))
 597                                         en_warn(priv, "Non-linear headers\n");
 598                                 return 0;
 599                         }
 600                 }
 601         } else {
 602                 *lso_header_size = 0;
 603                 *inline_ok = is_inline(priv->prof->inline_thold, skb,
 604                                        shinfo, pfrag);
 605
 606                 if (*inline_ok)
 607                         real_size = inline_size(skb);
 608                 else
 609                         real_size = CTRL_SIZE +
 610                                     (shinfo->nr_frags + 1) * DS_SIZE;
 611         }
 612
 613         return real_size;
 614 }
 615
 616 static void build_inline_wqe(struct mlx4_en_tx_desc *tx_desc,
 617                              const struct sk_buff *skb,
 618                              const struct skb_shared_info *shinfo,
 619                              int real_size, u16 *vlan_tag,
 620                              int tx_ind, void *fragptr)
 621 {
 622         struct mlx4_wqe_inline_seg *inl = &tx_desc->inl;
 623         int spc = MLX4_INLINE_ALIGN - CTRL_SIZE - sizeof *inl;
 624         unsigned int hlen = skb_headlen(skb);
 625
 626         if (skb->len <= spc) {
 627                 if (likely(skb->len >= MIN_PKT_LEN)) {
 628                         inl->byte_count = cpu_to_be32(1 << 31 | skb->len);
 629                 } else {
 630                         inl->byte_count = cpu_to_be32(1 << 31 | MIN_PKT_LEN);
 631                         memset(((void *)(inl + 1)) + skb->len, 0,
 632                                MIN_PKT_LEN - skb->len);
 633                 }
 634                 skb_copy_from_linear_data(skb, inl + 1, hlen);
 635                 if (shinfo->nr_frags)
 636                         memcpy(((void *)(inl + 1)) + hlen, fragptr,
 637                                skb_frag_size(&shinfo->frags[0]));
 638
 639         } else {
 640                 inl->byte_count = cpu_to_be32(1 << 31 | spc);
 641                 if (hlen <= spc) {
 642                         skb_copy_from_linear_data(skb, inl + 1, hlen);
 643                         if (hlen < spc) {
 644                                 memcpy(((void *)(inl + 1)) + hlen,
 645                                        fragptr, spc - hlen);
 646                                 fragptr +=  spc - hlen;
 647                         }
 648                         inl = (void *) (inl + 1) + spc;
 649                         memcpy(((void *)(inl + 1)), fragptr, skb->len - spc);
 650                 } else {
 651                         skb_copy_from_linear_data(skb, inl + 1, spc);
 652                         inl = (void *) (inl + 1) + spc;
 653                         skb_copy_from_linear_data_offset(skb, spc, inl + 1,
 654                                                          hlen - spc);
 655                         if (shinfo->nr_frags)
 656                                 memcpy(((void *)(inl + 1)) + hlen - spc,
 657                                        fragptr,
 658                                        skb_frag_size(&shinfo->frags[0]));
 659                 }
 660
 661                 wmb();
 662                 inl->byte_count = cpu_to_be32(1 << 31 | (skb->len - spc));
 663         }
 664 }
 665
 666 u16 mlx4_en_select_queue(struct net_device *dev, struct sk_buff *skb,
 667                          void *accel_priv, select_queue_fallback_t fallback)
 668 {
 669         struct mlx4_en_priv *priv = netdev_priv(dev);
 670         u16 rings_p_up = priv->num_tx_rings_p_up;
 671         u8 up = 0;
 672
 673         if (dev->num_tc)
 674                 return skb_tx_hash(dev, skb);
 675
 676         if (vlan_tx_tag_present(skb))
 677                 up = vlan_tx_tag_get(skb) >> VLAN_PRIO_SHIFT;
 678
 679         return fallback(dev, skb) % rings_p_up + up * rings_p_up;
 680 }
 681
 682 static void mlx4_bf_copy(void __iomem *dst, const void *src,
 683                          unsigned int bytecnt)
 684 {
 685         __iowrite64_copy(dst, src, bytecnt / 8);
 686 }
 687
 688 netdev_tx_t mlx4_en_xmit(struct sk_buff *skb, struct net_device *dev)
 689 {
 690         struct skb_shared_info *shinfo = skb_shinfo(skb);
 691         struct mlx4_en_priv *priv = netdev_priv(dev);
 692         struct device *ddev = priv->ddev;
 693         struct mlx4_en_tx_ring *ring;
 694         struct mlx4_en_tx_desc *tx_desc;
 695         struct mlx4_wqe_data_seg *data;
 696         struct mlx4_en_tx_info *tx_info;
 697         int tx_ind = 0;
 698         int nr_txbb;
 699         int desc_size;
 700         int real_size;
 701         u32 index, bf_index;
 702         __be32 op_own;
 703         u16 vlan_tag = 0;
 704         int i_frag;
 705         int lso_header_size;
 706         void *fragptr = NULL;
 707         bool bounce = false;
 708         bool send_doorbell;
 709         bool inline_ok;
 710         u32 ring_cons;
 711
 712         if (!priv->port_up)
 713                 goto tx_drop;
 714
 715         tx_ind = skb_get_queue_mapping(skb);
 716         ring = priv->tx_ring[tx_ind];
 717
 718         /* fetch ring->cons far ahead before needing it to avoid stall */
 719         ring_cons = ACCESS_ONCE(ring->cons);
 720
 721         real_size = get_real_size(skb, shinfo, dev, &lso_header_size,
 722                                   &inline_ok, &fragptr);
 723         if (unlikely(!real_size))
 724                 goto tx_drop;
 725
 726         /* Align descriptor to TXBB size */
 727         desc_size = ALIGN(real_size, TXBB_SIZE);
 728         nr_txbb = desc_size / TXBB_SIZE;
 729         if (unlikely(nr_txbb > MAX_DESC_TXBBS)) {
 730                 if (netif_msg_tx_err(priv))
 731                         en_warn(priv, "Oversized header or SG list\n");
 732                 goto tx_drop;
 733         }
 734
 735         if (vlan_tx_tag_present(skb))
 736                 vlan_tag = vlan_tx_tag_get(skb);
 737
 738         /* Check available TXBBs And 2K spare for prefetch */
 739         if (unlikely(((int)(ring->prod - ring_cons)) >
 740                      ring->size - HEADROOM - MAX_DESC_TXBBS)) {
 741                 /* every full Tx ring stops queue */
 742                 netif_tx_stop_queue(ring->tx_queue);
 743                 ring->queue_stopped++;
 744
 745                 /* If queue was emptied after the if, and before the
 746                  * stop_queue - need to wake the queue, or else it will remain
 747                  * stopped forever.
 748                  * Need a memory barrier to make sure ring->cons was not
 749                  * updated before queue was stopped.
 750                  */
 751                 wmb();
 752
 753                 ring_cons = ACCESS_ONCE(ring->cons);
 754                 if (unlikely(((int)(ring->prod - ring_cons)) <=
 755                              ring->size - HEADROOM - MAX_DESC_TXBBS)) {
 756                         netif_tx_wake_queue(ring->tx_queue);
 757                         ring->wake_queue++;
 758                 } else {
 759                         return NETDEV_TX_BUSY;
 760                 }
 761         }
 762
 763         prefetchw(&ring->tx_queue->dql);
 764
 765         /* Track current inflight packets for performance analysis */
 766         AVG_PERF_COUNTER(priv->pstats.inflight_avg,
 767                          (u32)(ring->prod - ring_cons - 1));
 768
 769         /* Packet is good - grab an index and transmit it */
 770         index = ring->prod & ring->size_mask;
 771         bf_index = ring->prod;
 772
 773         /* See if we have enough space for whole descriptor TXBB for setting
 774          * SW ownership on next descriptor; if not, use a bounce buffer. */
 775         if (likely(index + nr_txbb <= ring->size))
 776                 tx_desc = ring->buf + index * TXBB_SIZE;
 777         else {
 778                 tx_desc = (struct mlx4_en_tx_desc *) ring->bounce_buf;
 779                 bounce = true;
 780         }
 781
 782         /* Save skb in tx_info ring */
 783         tx_info = &ring->tx_info[index];
 784         tx_info->skb = skb;
 785         tx_info->nr_txbb = nr_txbb;
 786
 787         data = &tx_desc->data;
 788         if (lso_header_size)
 789                 data = ((void *)&tx_desc->lso + ALIGN(lso_header_size + 4,
 790                                                       DS_SIZE));
 791
 792         /* valid only for none inline segments */
 793         tx_info->data_offset = (void *)data - (void *)tx_desc;
 794
 795         tx_info->inl = inline_ok;
 796
 797         tx_info->linear = (lso_header_size < skb_headlen(skb) &&
 798                            !inline_ok) ? 1 : 0;
 799
 800         tx_info->nr_maps = shinfo->nr_frags + tx_info->linear;
 801         data += tx_info->nr_maps - 1;
 802
 803         if (!tx_info->inl) {
 804                 dma_addr_t dma = 0;
 805                 u32 byte_count = 0;
 806
 807                 /* Map fragments if any */
 808                 for (i_frag = shinfo->nr_frags - 1; i_frag >= 0; i_frag--) {
 809                         const struct skb_frag_struct *frag;
 810
 811                         frag = &shinfo->frags[i_frag];
 812                         byte_count = skb_frag_size(frag);
 813                         dma = skb_frag_dma_map(ddev, frag,
 814                                                0, byte_count,
 815                                                DMA_TO_DEVICE);
 816                         if (dma_mapping_error(ddev, dma))
 817                                 goto tx_drop_unmap;
 818
 819                         data->addr = cpu_to_be64(dma);
 820                         data->lkey = ring->mr_key;
 821                         wmb();
 822                         data->byte_count = cpu_to_be32(byte_count);
 823                         --data;
 824                 }
 825
 826                 /* Map linear part if needed */
 827                 if (tx_info->linear) {
 828                         byte_count = skb_headlen(skb) - lso_header_size;
 829
 830                         dma = dma_map_single(ddev, skb->data +
 831                                              lso_header_size, byte_count,
 832                                              PCI_DMA_TODEVICE);
 833                         if (dma_mapping_error(ddev, dma))
 834                                 goto tx_drop_unmap;
 835
 836                         data->addr = cpu_to_be64(dma);
 837                         data->lkey = ring->mr_key;
 838                         wmb();
 839                         data->byte_count = cpu_to_be32(byte_count);
 840                 }
 841                 /* tx completion can avoid cache line miss for common cases */
 842                 tx_info->map0_dma = dma;
 843                 tx_info->map0_byte_count = byte_count;
 844         }
 845
 846         /*
 847          * For timestamping add flag to skb_shinfo and
 848          * set flag for further reference
 849          */
 850         tx_info->ts_requested = 0;
 851         if (unlikely(ring->hwtstamp_tx_type == HWTSTAMP_TX_ON &&
 852                      shinfo->tx_flags & SKBTX_HW_TSTAMP)) {
 853                 shinfo->tx_flags |= SKBTX_IN_PROGRESS;
 854                 tx_info->ts_requested = 1;
 855         }
 856
 857         /* Prepare ctrl segement apart opcode+ownership, which depends on
 858          * whether LSO is used */
 859         tx_desc->ctrl.srcrb_flags = priv->ctrl_flags;
 860         if (likely(skb->ip_summed == CHECKSUM_PARTIAL)) {
 861                 tx_desc->ctrl.srcrb_flags |= cpu_to_be32(MLX4_WQE_CTRL_IP_CSUM |
 862                                                          MLX4_WQE_CTRL_TCP_UDP_CSUM);
 863                 ring->tx_csum++;
 864         }
 865
 866         if (priv->flags & MLX4_EN_FLAG_ENABLE_HW_LOOPBACK) {
 867                 struct ethhdr *ethh;
 868
 869                 /* Copy dst mac address to wqe. This allows loopback in eSwitch,
 870                  * so that VFs and PF can communicate with each other
 871                  */
 872                 ethh = (struct ethhdr *)skb->data;
 873                 tx_desc->ctrl.srcrb_flags16[0] = get_unaligned((__be16 *)ethh->h_dest);
 874                 tx_desc->ctrl.imm = get_unaligned((__be32 *)(ethh->h_dest + 2));
 875         }
 876
 877         /* Handle LSO (TSO) packets */
 878         if (lso_header_size) {
 879                 int i;
 880
 881                 /* Mark opcode as LSO */
 882                 op_own = cpu_to_be32(MLX4_OPCODE_LSO | (1 << 6)) |
 883                         ((ring->prod & ring->size) ?
 884                                 cpu_to_be32(MLX4_EN_BIT_DESC_OWN) : 0);
 885
 886                 /* Fill in the LSO prefix */
 887                 tx_desc->lso.mss_hdr_size = cpu_to_be32(
 888                         shinfo->gso_size << 16 | lso_header_size);
 889
 890                 /* Copy headers;
 891                  * note that we already verified that it is linear */
 892                 memcpy(tx_desc->lso.header, skb->data, lso_header_size);
 893
 894                 ring->tso_packets++;
 895
 896                 i = ((skb->len - lso_header_size) / shinfo->gso_size) +
 897                         !!((skb->len - lso_header_size) % shinfo->gso_size);
 898                 tx_info->nr_bytes = skb->len + (i - 1) * lso_header_size;
 899                 ring->packets += i;
 900         } else {
 901                 /* Normal (Non LSO) packet */
 902                 op_own = cpu_to_be32(MLX4_OPCODE_SEND) |
 903                         ((ring->prod & ring->size) ?
 904                          cpu_to_be32(MLX4_EN_BIT_DESC_OWN) : 0);
 905                 tx_info->nr_bytes = max_t(unsigned int, skb->len, ETH_ZLEN);
 906                 ring->packets++;
 907         }
 908         ring->bytes += tx_info->nr_bytes;
 909         netdev_tx_sent_queue(ring->tx_queue, tx_info->nr_bytes);
 910         AVG_PERF_COUNTER(priv->pstats.tx_pktsz_avg, skb->len);
 911
 912         if (tx_info->inl)
 913                 build_inline_wqe(tx_desc, skb, shinfo, real_size, &vlan_tag,
 914                                  tx_ind, fragptr);
 915
 916         if (skb->encapsulation) {
 917                 struct iphdr *ipv4 = (struct iphdr *)skb_inner_network_header(skb);
 918                 if (ipv4->protocol == IPPROTO_TCP || ipv4->protocol == IPPROTO_UDP)
 919                         op_own |= cpu_to_be32(MLX4_WQE_CTRL_IIP | MLX4_WQE_CTRL_ILP);
 920                 else
 921                         op_own |= cpu_to_be32(MLX4_WQE_CTRL_IIP);
 922         }
 923
 924         ring->prod += nr_txbb;
 925
 926         /* If we used a bounce buffer then copy descriptor back into place */
 927         if (unlikely(bounce))
 928                 tx_desc = mlx4_en_bounce_to_desc(priv, ring, index, desc_size);
 929
 930         skb_tx_timestamp(skb);
 931
 932         send_doorbell = !skb->xmit_more || netif_xmit_stopped(ring->tx_queue);
 933
 934         real_size = (real_size / 16) & 0x3f;
 935
 936         if (ring->bf_enabled && desc_size <= MAX_BF && !bounce &&
 937             !vlan_tx_tag_present(skb) && send_doorbell) {
 938                 tx_desc->ctrl.bf_qpn = ring->doorbell_qpn |
 939                                        cpu_to_be32(real_size);
 940
 941                 op_own |= htonl((bf_index & 0xffff) << 8);
 942                 /* Ensure new descriptor hits memory
 943                  * before setting ownership of this descriptor to HW
 944                  */
 945                 wmb();
 946                 tx_desc->ctrl.owner_opcode = op_own;
 947
 948                 wmb();
 949
 950                 mlx4_bf_copy(ring->bf.reg + ring->bf.offset, &tx_desc->ctrl,
 951                              desc_size);
 952
 953                 wmb();
 954
 955                 ring->bf.offset ^= ring->bf.buf_size;
 956         } else {
 957                 tx_desc->ctrl.vlan_tag = cpu_to_be16(vlan_tag);
 958                 tx_desc->ctrl.ins_vlan = MLX4_WQE_CTRL_INS_VLAN *
 959                         !!vlan_tx_tag_present(skb);
 960                 tx_desc->ctrl.fence_size = real_size;
 961
 962                 /* Ensure new descriptor hits memory
 963                  * before setting ownership of this descriptor to HW
 964                  */
 965                 wmb();
 966                 tx_desc->ctrl.owner_opcode = op_own;
 967                 if (send_doorbell) {
 968                         wmb();
 969                         iowrite32(ring->doorbell_qpn,
 970                                   ring->bf.uar->map + MLX4_SEND_DOORBELL);
 971                 } else {
 972                         ring->xmit_more++;
 973                 }
 974         }
 975
 976         return NETDEV_TX_OK;
 977
 978 tx_drop_unmap:
 979         en_err(priv, "DMA mapping error\n");
 980
 981         while (++i_frag < shinfo->nr_frags) {
 982                 ++data;
 983                 dma_unmap_page(ddev, (dma_addr_t) be64_to_cpu(data->addr),
 984                                be32_to_cpu(data->byte_count),
 985                                PCI_DMA_TODEVICE);
 986         }
 987
 988 tx_drop:
 989         dev_kfree_skb_any(skb);
 990         priv->stats.tx_dropped++;
 991         return NETDEV_TX_OK;
 992 }
 993