drivers/net/ethernet/mellanox/mlxsw/pci.c

   1 /*
   2  * drivers/net/ethernet/mellanox/mlxsw/pci.c
   3  * Copyright (c) 2015 Mellanox Technologies. All rights reserved.
   4  * Copyright (c) 2015 Jiri Pirko <jiri@mellanox.com>
   5  *
   6  * Redistribution and use in source and binary forms, with or without
   7  * modification, are permitted provided that the following conditions are met:
   8  *
   9  * 1. Redistributions of source code must retain the above copyright
  10  *    notice, this list of conditions and the following disclaimer.
  11  * 2. Redistributions in binary form must reproduce the above copyright
  12  *    notice, this list of conditions and the following disclaimer in the
  13  *    documentation and/or other materials provided with the distribution.
  14  * 3. Neither the names of the copyright holders nor the names of its
  15  *    contributors may be used to endorse or promote products derived from
  16  *    this software without specific prior written permission.
  17  *
  18  * Alternatively, this software may be distributed under the terms of the
  19  * GNU General Public License ("GPL") version 2 as published by the Free
  20  * Software Foundation.
  21  *
  22  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
  23  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
  24  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
  25  * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
  26  * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
  27  * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
  28  * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
  29  * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
  30  * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
  31  * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
  32  * POSSIBILITY OF SUCH DAMAGE.
  33  */
  34
  35 #include <linux/kernel.h>
  36 #include <linux/module.h>
  37 #include <linux/export.h>
  38 #include <linux/err.h>
  39 #include <linux/device.h>
  40 #include <linux/pci.h>
  41 #include <linux/interrupt.h>
  42 #include <linux/wait.h>
  43 #include <linux/types.h>
  44 #include <linux/skbuff.h>
  45 #include <linux/if_vlan.h>
  46 #include <linux/log2.h>
  47 #include <linux/debugfs.h>
  48 #include <linux/seq_file.h>
  49 #include <linux/string.h>
  50
  51 #include "pci.h"
  52 #include "core.h"
  53 #include "cmd.h"
  54 #include "port.h"
  55
  56 static const char mlxsw_pci_driver_name[] = "mlxsw_pci";
  57
  58 static const struct pci_device_id mlxsw_pci_id_table[] = {
  59         {PCI_VDEVICE(MELLANOX, PCI_DEVICE_ID_MELLANOX_SWITCHX2), 0},
  60         {0, }
  61 };
  62
  63 static struct dentry *mlxsw_pci_dbg_root;
  64
  65 static const char *mlxsw_pci_device_kind_get(const struct pci_device_id *id)
  66 {
  67         switch (id->device) {
  68         case PCI_DEVICE_ID_MELLANOX_SWITCHX2:
  69                 return MLXSW_DEVICE_KIND_SWITCHX2;
  70         default:
  71                 BUG();
  72         }
  73 }
  74
  75 #define mlxsw_pci_write32(mlxsw_pci, reg, val) \
  76         iowrite32be(val, (mlxsw_pci)->hw_addr + (MLXSW_PCI_ ## reg))
  77 #define mlxsw_pci_read32(mlxsw_pci, reg) \
  78         ioread32be((mlxsw_pci)->hw_addr + (MLXSW_PCI_ ## reg))
  79
  80 enum mlxsw_pci_queue_type {
  81         MLXSW_PCI_QUEUE_TYPE_SDQ,
  82         MLXSW_PCI_QUEUE_TYPE_RDQ,
  83         MLXSW_PCI_QUEUE_TYPE_CQ,
  84         MLXSW_PCI_QUEUE_TYPE_EQ,
  85 };
  86
  87 static const char *mlxsw_pci_queue_type_str(enum mlxsw_pci_queue_type q_type)
  88 {
  89         switch (q_type) {
  90         case MLXSW_PCI_QUEUE_TYPE_SDQ:
  91                 return "sdq";
  92         case MLXSW_PCI_QUEUE_TYPE_RDQ:
  93                 return "rdq";
  94         case MLXSW_PCI_QUEUE_TYPE_CQ:
  95                 return "cq";
  96         case MLXSW_PCI_QUEUE_TYPE_EQ:
  97                 return "eq";
  98         }
  99         BUG();
 100 }
 101
 102 #define MLXSW_PCI_QUEUE_TYPE_COUNT      4
 103
 104 static const u16 mlxsw_pci_doorbell_type_offset[] = {
 105         MLXSW_PCI_DOORBELL_SDQ_OFFSET,  /* for type MLXSW_PCI_QUEUE_TYPE_SDQ */
 106         MLXSW_PCI_DOORBELL_RDQ_OFFSET,  /* for type MLXSW_PCI_QUEUE_TYPE_RDQ */
 107         MLXSW_PCI_DOORBELL_CQ_OFFSET,   /* for type MLXSW_PCI_QUEUE_TYPE_CQ */
 108         MLXSW_PCI_DOORBELL_EQ_OFFSET,   /* for type MLXSW_PCI_QUEUE_TYPE_EQ */
 109 };
 110
 111 static const u16 mlxsw_pci_doorbell_arm_type_offset[] = {
 112         0, /* unused */
 113         0, /* unused */
 114         MLXSW_PCI_DOORBELL_ARM_CQ_OFFSET, /* for type MLXSW_PCI_QUEUE_TYPE_CQ */
 115         MLXSW_PCI_DOORBELL_ARM_EQ_OFFSET, /* for type MLXSW_PCI_QUEUE_TYPE_EQ */
 116 };
 117
 118 struct mlxsw_pci_mem_item {
 119         char *buf;
 120         dma_addr_t mapaddr;
 121         size_t size;
 122 };
 123
 124 struct mlxsw_pci_queue_elem_info {
 125         char *elem; /* pointer to actual dma mapped element mem chunk */
 126         union {
 127                 struct {
 128                         struct sk_buff *skb;
 129                 } sdq;
 130                 struct {
 131                         struct sk_buff *skb;
 132                 } rdq;
 133         } u;
 134 };
 135
 136 struct mlxsw_pci_queue {
 137         spinlock_t lock; /* for queue accesses */
 138         struct mlxsw_pci_mem_item mem_item;
 139         struct mlxsw_pci_queue_elem_info *elem_info;
 140         u16 producer_counter;
 141         u16 consumer_counter;
 142         u16 count; /* number of elements in queue */
 143         u8 num; /* queue number */
 144         u8 elem_size; /* size of one element */
 145         enum mlxsw_pci_queue_type type;
 146         struct tasklet_struct tasklet; /* queue processing tasklet */
 147         struct mlxsw_pci *pci;
 148         union {
 149                 struct {
 150                         u32 comp_sdq_count;
 151                         u32 comp_rdq_count;
 152                 } cq;
 153                 struct {
 154                         u32 ev_cmd_count;
 155                         u32 ev_comp_count;
 156                         u32 ev_other_count;
 157                 } eq;
 158         } u;
 159 };
 160
 161 struct mlxsw_pci_queue_type_group {
 162         struct mlxsw_pci_queue *q;
 163         u8 count; /* number of queues in group */
 164 };
 165
 166 struct mlxsw_pci {
 167         struct pci_dev *pdev;
 168         u8 __iomem *hw_addr;
 169         struct mlxsw_pci_queue_type_group queues[MLXSW_PCI_QUEUE_TYPE_COUNT];
 170         u32 doorbell_offset;
 171         struct msix_entry msix_entry;
 172         struct mlxsw_core *core;
 173         struct {
 174                 u16 num_pages;
 175                 struct mlxsw_pci_mem_item *items;
 176         } fw_area;
 177         struct {
 178                 struct mlxsw_pci_mem_item out_mbox;
 179                 struct mlxsw_pci_mem_item in_mbox;
 180                 struct mutex lock; /* Lock access to command registers */
 181                 bool nopoll;
 182                 wait_queue_head_t wait;
 183                 bool wait_done;
 184                 struct {
 185                         u8 status;
 186                         u64 out_param;
 187                 } comp;
 188         } cmd;
 189         struct mlxsw_bus_info bus_info;
 190         struct dentry *dbg_dir;
 191 };
 192
 193 static void mlxsw_pci_queue_tasklet_schedule(struct mlxsw_pci_queue *q)
 194 {
 195         tasklet_schedule(&q->tasklet);
 196 }
 197
 198 static char *__mlxsw_pci_queue_elem_get(struct mlxsw_pci_queue *q,
 199                                         size_t elem_size, int elem_index)
 200 {
 201         return q->mem_item.buf + (elem_size * elem_index);
 202 }
 203
 204 static struct mlxsw_pci_queue_elem_info *
 205 mlxsw_pci_queue_elem_info_get(struct mlxsw_pci_queue *q, int elem_index)
 206 {
 207         return &q->elem_info[elem_index];
 208 }
 209
 210 static struct mlxsw_pci_queue_elem_info *
 211 mlxsw_pci_queue_elem_info_producer_get(struct mlxsw_pci_queue *q)
 212 {
 213         int index = q->producer_counter & (q->count - 1);
 214
 215         if ((q->producer_counter - q->consumer_counter) == q->count)
 216                 return NULL;
 217         return mlxsw_pci_queue_elem_info_get(q, index);
 218 }
 219
 220 static struct mlxsw_pci_queue_elem_info *
 221 mlxsw_pci_queue_elem_info_consumer_get(struct mlxsw_pci_queue *q)
 222 {
 223         int index = q->consumer_counter & (q->count - 1);
 224
 225         return mlxsw_pci_queue_elem_info_get(q, index);
 226 }
 227
 228 static char *mlxsw_pci_queue_elem_get(struct mlxsw_pci_queue *q, int elem_index)
 229 {
 230         return mlxsw_pci_queue_elem_info_get(q, elem_index)->elem;
 231 }
 232
 233 static bool mlxsw_pci_elem_hw_owned(struct mlxsw_pci_queue *q, bool owner_bit)
 234 {
 235         return owner_bit != !!(q->consumer_counter & q->count);
 236 }
 237
 238 static char *mlxsw_pci_queue_sw_elem_get(struct mlxsw_pci_queue *q,
 239                                          u32 (*get_elem_owner_func)(char *))
 240 {
 241         struct mlxsw_pci_queue_elem_info *elem_info;
 242         char *elem;
 243         bool owner_bit;
 244
 245         elem_info = mlxsw_pci_queue_elem_info_consumer_get(q);
 246         elem = elem_info->elem;
 247         owner_bit = get_elem_owner_func(elem);
 248         if (mlxsw_pci_elem_hw_owned(q, owner_bit))
 249                 return NULL;
 250         q->consumer_counter++;
 251         rmb(); /* make sure we read owned bit before the rest of elem */
 252         return elem;
 253 }
 254
 255 static struct mlxsw_pci_queue_type_group *
 256 mlxsw_pci_queue_type_group_get(struct mlxsw_pci *mlxsw_pci,
 257                                enum mlxsw_pci_queue_type q_type)
 258 {
 259         return &mlxsw_pci->queues[q_type];
 260 }
 261
 262 static u8 __mlxsw_pci_queue_count(struct mlxsw_pci *mlxsw_pci,
 263                                   enum mlxsw_pci_queue_type q_type)
 264 {
 265         struct mlxsw_pci_queue_type_group *queue_group;
 266
 267         queue_group = mlxsw_pci_queue_type_group_get(mlxsw_pci, q_type);
 268         return queue_group->count;
 269 }
 270
 271 static u8 mlxsw_pci_sdq_count(struct mlxsw_pci *mlxsw_pci)
 272 {
 273         return __mlxsw_pci_queue_count(mlxsw_pci, MLXSW_PCI_QUEUE_TYPE_SDQ);
 274 }
 275
 276 static u8 mlxsw_pci_rdq_count(struct mlxsw_pci *mlxsw_pci)
 277 {
 278         return __mlxsw_pci_queue_count(mlxsw_pci, MLXSW_PCI_QUEUE_TYPE_RDQ);
 279 }
 280
 281 static u8 mlxsw_pci_cq_count(struct mlxsw_pci *mlxsw_pci)
 282 {
 283         return __mlxsw_pci_queue_count(mlxsw_pci, MLXSW_PCI_QUEUE_TYPE_CQ);
 284 }
 285
 286 static u8 mlxsw_pci_eq_count(struct mlxsw_pci *mlxsw_pci)
 287 {
 288         return __mlxsw_pci_queue_count(mlxsw_pci, MLXSW_PCI_QUEUE_TYPE_EQ);
 289 }
 290
 291 static struct mlxsw_pci_queue *
 292 __mlxsw_pci_queue_get(struct mlxsw_pci *mlxsw_pci,
 293                       enum mlxsw_pci_queue_type q_type, u8 q_num)
 294 {
 295         return &mlxsw_pci->queues[q_type].q[q_num];
 296 }
 297
 298 static struct mlxsw_pci_queue *mlxsw_pci_sdq_get(struct mlxsw_pci *mlxsw_pci,
 299                                                  u8 q_num)
 300 {
 301         return __mlxsw_pci_queue_get(mlxsw_pci,
 302                                      MLXSW_PCI_QUEUE_TYPE_SDQ, q_num);
 303 }
 304
 305 static struct mlxsw_pci_queue *mlxsw_pci_rdq_get(struct mlxsw_pci *mlxsw_pci,
 306                                                  u8 q_num)
 307 {
 308         return __mlxsw_pci_queue_get(mlxsw_pci,
 309                                      MLXSW_PCI_QUEUE_TYPE_RDQ, q_num);
 310 }
 311
 312 static struct mlxsw_pci_queue *mlxsw_pci_cq_get(struct mlxsw_pci *mlxsw_pci,
 313                                                 u8 q_num)
 314 {
 315         return __mlxsw_pci_queue_get(mlxsw_pci, MLXSW_PCI_QUEUE_TYPE_CQ, q_num);
 316 }
 317
 318 static struct mlxsw_pci_queue *mlxsw_pci_eq_get(struct mlxsw_pci *mlxsw_pci,
 319                                                 u8 q_num)
 320 {
 321         return __mlxsw_pci_queue_get(mlxsw_pci, MLXSW_PCI_QUEUE_TYPE_EQ, q_num);
 322 }
 323
 324 static void __mlxsw_pci_queue_doorbell_set(struct mlxsw_pci *mlxsw_pci,
 325                                            struct mlxsw_pci_queue *q,
 326                                            u16 val)
 327 {
 328         mlxsw_pci_write32(mlxsw_pci,
 329                           DOORBELL(mlxsw_pci->doorbell_offset,
 330                                    mlxsw_pci_doorbell_type_offset[q->type],
 331                                    q->num), val);
 332 }
 333
 334 static void __mlxsw_pci_queue_doorbell_arm_set(struct mlxsw_pci *mlxsw_pci,
 335                                                struct mlxsw_pci_queue *q,
 336                                                u16 val)
 337 {
 338         mlxsw_pci_write32(mlxsw_pci,
 339                           DOORBELL(mlxsw_pci->doorbell_offset,
 340                                    mlxsw_pci_doorbell_arm_type_offset[q->type],
 341                                    q->num), val);
 342 }
 343
 344 static void mlxsw_pci_queue_doorbell_producer_ring(struct mlxsw_pci *mlxsw_pci,
 345                                                    struct mlxsw_pci_queue *q)
 346 {
 347         wmb(); /* ensure all writes are done before we ring a bell */
 348         __mlxsw_pci_queue_doorbell_set(mlxsw_pci, q, q->producer_counter);
 349 }
 350
 351 static void mlxsw_pci_queue_doorbell_consumer_ring(struct mlxsw_pci *mlxsw_pci,
 352                                                    struct mlxsw_pci_queue *q)
 353 {
 354         wmb(); /* ensure all writes are done before we ring a bell */
 355         __mlxsw_pci_queue_doorbell_set(mlxsw_pci, q,
 356                                        q->consumer_counter + q->count);
 357 }
 358
 359 static void
 360 mlxsw_pci_queue_doorbell_arm_consumer_ring(struct mlxsw_pci *mlxsw_pci,
 361                                            struct mlxsw_pci_queue *q)
 362 {
 363         wmb(); /* ensure all writes are done before we ring a bell */
 364         __mlxsw_pci_queue_doorbell_arm_set(mlxsw_pci, q, q->consumer_counter);
 365 }
 366
 367 static dma_addr_t __mlxsw_pci_queue_page_get(struct mlxsw_pci_queue *q,
 368                                              int page_index)
 369 {
 370         return q->mem_item.mapaddr + MLXSW_PCI_PAGE_SIZE * page_index;
 371 }
 372
 373 static int mlxsw_pci_sdq_init(struct mlxsw_pci *mlxsw_pci, char *mbox,
 374                               struct mlxsw_pci_queue *q)
 375 {
 376         int i;
 377         int err;
 378
 379         q->producer_counter = 0;
 380         q->consumer_counter = 0;
 381
 382         /* Set CQ of same number of this SDQ. */
 383         mlxsw_cmd_mbox_sw2hw_dq_cq_set(mbox, q->num);
 384         mlxsw_cmd_mbox_sw2hw_dq_sdq_tclass_set(mbox, 7);
 385         mlxsw_cmd_mbox_sw2hw_dq_log2_dq_sz_set(mbox, 3); /* 8 pages */
 386         for (i = 0; i < MLXSW_PCI_AQ_PAGES; i++) {
 387                 dma_addr_t mapaddr = __mlxsw_pci_queue_page_get(q, i);
 388
 389                 mlxsw_cmd_mbox_sw2hw_dq_pa_set(mbox, i, mapaddr);
 390         }
 391
 392         err = mlxsw_cmd_sw2hw_sdq(mlxsw_pci->core, mbox, q->num);
 393         if (err)
 394                 return err;
 395         mlxsw_pci_queue_doorbell_producer_ring(mlxsw_pci, q);
 396         return 0;
 397 }
 398
 399 static void mlxsw_pci_sdq_fini(struct mlxsw_pci *mlxsw_pci,
 400                                struct mlxsw_pci_queue *q)
 401 {
 402         mlxsw_cmd_hw2sw_sdq(mlxsw_pci->core, q->num);
 403 }
 404
 405 static int mlxsw_pci_sdq_dbg_read(struct seq_file *file, void *data)
 406 {
 407         struct mlxsw_pci *mlxsw_pci = dev_get_drvdata(file->private);
 408         struct mlxsw_pci_queue *q;
 409         int i;
 410         static const char hdr[] =
 411                 "NUM PROD_COUNT CONS_COUNT COUNT\n";
 412
 413         seq_printf(file, hdr);
 414         for (i = 0; i < mlxsw_pci_sdq_count(mlxsw_pci); i++) {
 415                 q = mlxsw_pci_sdq_get(mlxsw_pci, i);
 416                 spin_lock_bh(&q->lock);
 417                 seq_printf(file, "%3d %10d %10d %5d\n",
 418                            i, q->producer_counter, q->consumer_counter,
 419                            q->count);
 420                 spin_unlock_bh(&q->lock);
 421         }
 422         return 0;
 423 }
 424
 425 static int mlxsw_pci_wqe_frag_map(struct mlxsw_pci *mlxsw_pci, char *wqe,
 426                                   int index, char *frag_data, size_t frag_len,
 427                                   int direction)
 428 {
 429         struct pci_dev *pdev = mlxsw_pci->pdev;
 430         dma_addr_t mapaddr;
 431
 432         mapaddr = pci_map_single(pdev, frag_data, frag_len, direction);
 433         if (unlikely(pci_dma_mapping_error(pdev, mapaddr))) {
 434                 if (net_ratelimit())
 435                         dev_err(&pdev->dev, "failed to dma map tx frag\n");
 436                 return -EIO;
 437         }
 438         mlxsw_pci_wqe_address_set(wqe, index, mapaddr);
 439         mlxsw_pci_wqe_byte_count_set(wqe, index, frag_len);
 440         return 0;
 441 }
 442
 443 static void mlxsw_pci_wqe_frag_unmap(struct mlxsw_pci *mlxsw_pci, char *wqe,
 444                                      int index, int direction)
 445 {
 446         struct pci_dev *pdev = mlxsw_pci->pdev;
 447         size_t frag_len = mlxsw_pci_wqe_byte_count_get(wqe, index);
 448         dma_addr_t mapaddr = mlxsw_pci_wqe_address_get(wqe, index);
 449
 450         if (!frag_len)
 451                 return;
 452         pci_unmap_single(pdev, mapaddr, frag_len, direction);
 453 }
 454
 455 static int mlxsw_pci_rdq_skb_alloc(struct mlxsw_pci *mlxsw_pci,
 456                                    struct mlxsw_pci_queue_elem_info *elem_info)
 457 {
 458         size_t buf_len = MLXSW_PORT_MAX_MTU;
 459         char *wqe = elem_info->elem;
 460         struct sk_buff *skb;
 461         int err;
 462
 463         elem_info->u.rdq.skb = NULL;
 464         skb = netdev_alloc_skb_ip_align(NULL, buf_len);
 465         if (!skb)
 466                 return -ENOMEM;
 467
 468         /* Assume that wqe was previously zeroed. */
 469
 470         err = mlxsw_pci_wqe_frag_map(mlxsw_pci, wqe, 0, skb->data,
 471                                      buf_len, DMA_FROM_DEVICE);
 472         if (err)
 473                 goto err_frag_map;
 474
 475         elem_info->u.rdq.skb = skb;
 476         return 0;
 477
 478 err_frag_map:
 479         dev_kfree_skb_any(skb);
 480         return err;
 481 }
 482
 483 static void mlxsw_pci_rdq_skb_free(struct mlxsw_pci *mlxsw_pci,
 484                                    struct mlxsw_pci_queue_elem_info *elem_info)
 485 {
 486         struct sk_buff *skb;
 487         char *wqe;
 488
 489         skb = elem_info->u.rdq.skb;
 490         wqe = elem_info->elem;
 491
 492         mlxsw_pci_wqe_frag_unmap(mlxsw_pci, wqe, 0, DMA_FROM_DEVICE);
 493         dev_kfree_skb_any(skb);
 494 }
 495
 496 static int mlxsw_pci_rdq_init(struct mlxsw_pci *mlxsw_pci, char *mbox,
 497                               struct mlxsw_pci_queue *q)
 498 {
 499         struct mlxsw_pci_queue_elem_info *elem_info;
 500         u8 sdq_count = mlxsw_pci_sdq_count(mlxsw_pci);
 501         int i;
 502         int err;
 503
 504         q->producer_counter = 0;
 505         q->consumer_counter = 0;
 506
 507         /* Set CQ of same number of this RDQ with base
 508          * above SDQ count as the lower ones are assigned to SDQs.
 509          */
 510         mlxsw_cmd_mbox_sw2hw_dq_cq_set(mbox, sdq_count + q->num);
 511         mlxsw_cmd_mbox_sw2hw_dq_log2_dq_sz_set(mbox, 3); /* 8 pages */
 512         for (i = 0; i < MLXSW_PCI_AQ_PAGES; i++) {
 513                 dma_addr_t mapaddr = __mlxsw_pci_queue_page_get(q, i);
 514
 515                 mlxsw_cmd_mbox_sw2hw_dq_pa_set(mbox, i, mapaddr);
 516         }
 517
 518         err = mlxsw_cmd_sw2hw_rdq(mlxsw_pci->core, mbox, q->num);
 519         if (err)
 520                 return err;
 521
 522         mlxsw_pci_queue_doorbell_producer_ring(mlxsw_pci, q);
 523
 524         for (i = 0; i < q->count; i++) {
 525                 elem_info = mlxsw_pci_queue_elem_info_producer_get(q);
 526                 BUG_ON(!elem_info);
 527                 err = mlxsw_pci_rdq_skb_alloc(mlxsw_pci, elem_info);
 528                 if (err)
 529                         goto rollback;
 530                 /* Everything is set up, ring doorbell to pass elem to HW */
 531                 q->producer_counter++;
 532                 mlxsw_pci_queue_doorbell_producer_ring(mlxsw_pci, q);
 533         }
 534
 535         return 0;
 536
 537 rollback:
 538         for (i--; i >= 0; i--) {
 539                 elem_info = mlxsw_pci_queue_elem_info_get(q, i);
 540                 mlxsw_pci_rdq_skb_free(mlxsw_pci, elem_info);
 541         }
 542         mlxsw_cmd_hw2sw_rdq(mlxsw_pci->core, q->num);
 543
 544         return err;
 545 }
 546
 547 static void mlxsw_pci_rdq_fini(struct mlxsw_pci *mlxsw_pci,
 548                                struct mlxsw_pci_queue *q)
 549 {
 550         struct mlxsw_pci_queue_elem_info *elem_info;
 551         int i;
 552
 553         mlxsw_cmd_hw2sw_rdq(mlxsw_pci->core, q->num);
 554         for (i = 0; i < q->count; i++) {
 555                 elem_info = mlxsw_pci_queue_elem_info_get(q, i);
 556                 mlxsw_pci_rdq_skb_free(mlxsw_pci, elem_info);
 557         }
 558 }
 559
 560 static int mlxsw_pci_rdq_dbg_read(struct seq_file *file, void *data)
 561 {
 562         struct mlxsw_pci *mlxsw_pci = dev_get_drvdata(file->private);
 563         struct mlxsw_pci_queue *q;
 564         int i;
 565         static const char hdr[] =
 566                 "NUM PROD_COUNT CONS_COUNT COUNT\n";
 567
 568         seq_printf(file, hdr);
 569         for (i = 0; i < mlxsw_pci_rdq_count(mlxsw_pci); i++) {
 570                 q = mlxsw_pci_rdq_get(mlxsw_pci, i);
 571                 spin_lock_bh(&q->lock);
 572                 seq_printf(file, "%3d %10d %10d %5d\n",
 573                            i, q->producer_counter, q->consumer_counter,
 574                            q->count);
 575                 spin_unlock_bh(&q->lock);
 576         }
 577         return 0;
 578 }
 579
 580 static int mlxsw_pci_cq_init(struct mlxsw_pci *mlxsw_pci, char *mbox,
 581                              struct mlxsw_pci_queue *q)
 582 {
 583         int i;
 584         int err;
 585
 586         q->consumer_counter = 0;
 587
 588         for (i = 0; i < q->count; i++) {
 589                 char *elem = mlxsw_pci_queue_elem_get(q, i);
 590
 591                 mlxsw_pci_cqe_owner_set(elem, 1);
 592         }
 593
 594         mlxsw_cmd_mbox_sw2hw_cq_cv_set(mbox, 0); /* CQE ver 0 */
 595         mlxsw_cmd_mbox_sw2hw_cq_c_eqn_set(mbox, MLXSW_PCI_EQ_COMP_NUM);
 596         mlxsw_cmd_mbox_sw2hw_cq_oi_set(mbox, 0);
 597         mlxsw_cmd_mbox_sw2hw_cq_st_set(mbox, 0);
 598         mlxsw_cmd_mbox_sw2hw_cq_log_cq_size_set(mbox, ilog2(q->count));
 599         for (i = 0; i < MLXSW_PCI_AQ_PAGES; i++) {
 600                 dma_addr_t mapaddr = __mlxsw_pci_queue_page_get(q, i);
 601
 602                 mlxsw_cmd_mbox_sw2hw_cq_pa_set(mbox, i, mapaddr);
 603         }
 604         err = mlxsw_cmd_sw2hw_cq(mlxsw_pci->core, mbox, q->num);
 605         if (err)
 606                 return err;
 607         mlxsw_pci_queue_doorbell_consumer_ring(mlxsw_pci, q);
 608         mlxsw_pci_queue_doorbell_arm_consumer_ring(mlxsw_pci, q);
 609         return 0;
 610 }
 611
 612 static void mlxsw_pci_cq_fini(struct mlxsw_pci *mlxsw_pci,
 613                               struct mlxsw_pci_queue *q)
 614 {
 615         mlxsw_cmd_hw2sw_cq(mlxsw_pci->core, q->num);
 616 }
 617
 618 static int mlxsw_pci_cq_dbg_read(struct seq_file *file, void *data)
 619 {
 620         struct mlxsw_pci *mlxsw_pci = dev_get_drvdata(file->private);
 621
 622         struct mlxsw_pci_queue *q;
 623         int i;
 624         static const char hdr[] =
 625                 "NUM CONS_INDEX  SDQ_COUNT  RDQ_COUNT COUNT\n";
 626
 627         seq_printf(file, hdr);
 628         for (i = 0; i < mlxsw_pci_cq_count(mlxsw_pci); i++) {
 629                 q = mlxsw_pci_cq_get(mlxsw_pci, i);
 630                 spin_lock_bh(&q->lock);
 631                 seq_printf(file, "%3d %10d %10d %10d %5d\n",
 632                            i, q->consumer_counter, q->u.cq.comp_sdq_count,
 633                            q->u.cq.comp_rdq_count, q->count);
 634                 spin_unlock_bh(&q->lock);
 635         }
 636         return 0;
 637 }
 638
 639 static void mlxsw_pci_cqe_sdq_handle(struct mlxsw_pci *mlxsw_pci,
 640                                      struct mlxsw_pci_queue *q,
 641                                      u16 consumer_counter_limit,
 642                                      char *cqe)
 643 {
 644         struct pci_dev *pdev = mlxsw_pci->pdev;
 645         struct mlxsw_pci_queue_elem_info *elem_info;
 646         char *wqe;
 647         struct sk_buff *skb;
 648         int i;
 649
 650         spin_lock(&q->lock);
 651         elem_info = mlxsw_pci_queue_elem_info_consumer_get(q);
 652         skb = elem_info->u.sdq.skb;
 653         wqe = elem_info->elem;
 654         for (i = 0; i < MLXSW_PCI_WQE_SG_ENTRIES; i++)
 655                 mlxsw_pci_wqe_frag_unmap(mlxsw_pci, wqe, i, DMA_TO_DEVICE);
 656         dev_kfree_skb_any(skb);
 657         elem_info->u.sdq.skb = NULL;
 658
 659         if (q->consumer_counter++ != consumer_counter_limit)
 660                 dev_dbg_ratelimited(&pdev->dev, "Consumer counter does not match limit in SDQ\n");
 661         spin_unlock(&q->lock);
 662 }
 663
 664 static void mlxsw_pci_cqe_rdq_handle(struct mlxsw_pci *mlxsw_pci,
 665                                      struct mlxsw_pci_queue *q,
 666                                      u16 consumer_counter_limit,
 667                                      char *cqe)
 668 {
 669         struct pci_dev *pdev = mlxsw_pci->pdev;
 670         struct mlxsw_pci_queue_elem_info *elem_info;
 671         char *wqe;
 672         struct sk_buff *skb;
 673         struct mlxsw_rx_info rx_info;
 674         u16 byte_count;
 675         int err;
 676
 677         elem_info = mlxsw_pci_queue_elem_info_consumer_get(q);
 678         skb = elem_info->u.sdq.skb;
 679         if (!skb)
 680                 return;
 681         wqe = elem_info->elem;
 682         mlxsw_pci_wqe_frag_unmap(mlxsw_pci, wqe, 0, DMA_FROM_DEVICE);
 683
 684         if (q->consumer_counter++ != consumer_counter_limit)
 685                 dev_dbg_ratelimited(&pdev->dev, "Consumer counter does not match limit in RDQ\n");
 686
 687         /* We do not support lag now */
 688         if (mlxsw_pci_cqe_lag_get(cqe))
 689                 goto drop;
 690
 691         rx_info.sys_port = mlxsw_pci_cqe_system_port_get(cqe);
 692         rx_info.trap_id = mlxsw_pci_cqe_trap_id_get(cqe);
 693
 694         byte_count = mlxsw_pci_cqe_byte_count_get(cqe);
 695         if (mlxsw_pci_cqe_crc_get(cqe))
 696                 byte_count -= ETH_FCS_LEN;
 697         skb_put(skb, byte_count);
 698         mlxsw_core_skb_receive(mlxsw_pci->core, skb, &rx_info);
 699
 700 put_new_skb:
 701         memset(wqe, 0, q->elem_size);
 702         err = mlxsw_pci_rdq_skb_alloc(mlxsw_pci, elem_info);
 703         if (err && net_ratelimit())
 704                 dev_dbg(&pdev->dev, "Failed to alloc skb for RDQ\n");
 705         /* Everything is set up, ring doorbell to pass elem to HW */
 706         q->producer_counter++;
 707         mlxsw_pci_queue_doorbell_producer_ring(mlxsw_pci, q);
 708         return;
 709
 710 drop:
 711         dev_kfree_skb_any(skb);
 712         goto put_new_skb;
 713 }
 714
 715 static char *mlxsw_pci_cq_sw_cqe_get(struct mlxsw_pci_queue *q)
 716 {
 717         return mlxsw_pci_queue_sw_elem_get(q, mlxsw_pci_cqe_owner_get);
 718 }
 719
 720 static void mlxsw_pci_cq_tasklet(unsigned long data)
 721 {
 722         struct mlxsw_pci_queue *q = (struct mlxsw_pci_queue *) data;
 723         struct mlxsw_pci *mlxsw_pci = q->pci;
 724         char *cqe;
 725         int items = 0;
 726         int credits = q->count >> 1;
 727
 728         while ((cqe = mlxsw_pci_cq_sw_cqe_get(q))) {
 729                 u16 wqe_counter = mlxsw_pci_cqe_wqe_counter_get(cqe);
 730                 u8 sendq = mlxsw_pci_cqe_sr_get(cqe);
 731                 u8 dqn = mlxsw_pci_cqe_dqn_get(cqe);
 732
 733                 if (sendq) {
 734                         struct mlxsw_pci_queue *sdq;
 735
 736                         sdq = mlxsw_pci_sdq_get(mlxsw_pci, dqn);
 737                         mlxsw_pci_cqe_sdq_handle(mlxsw_pci, sdq,
 738                                                  wqe_counter, cqe);
 739                         q->u.cq.comp_sdq_count++;
 740                 } else {
 741                         struct mlxsw_pci_queue *rdq;
 742
 743                         rdq = mlxsw_pci_rdq_get(mlxsw_pci, dqn);
 744                         mlxsw_pci_cqe_rdq_handle(mlxsw_pci, rdq,
 745                                                  wqe_counter, cqe);
 746                         q->u.cq.comp_rdq_count++;
 747                 }
 748                 if (++items == credits)
 749                         break;
 750         }
 751         if (items) {
 752                 mlxsw_pci_queue_doorbell_consumer_ring(mlxsw_pci, q);
 753                 mlxsw_pci_queue_doorbell_arm_consumer_ring(mlxsw_pci, q);
 754         }
 755 }
 756
 757 static int mlxsw_pci_eq_init(struct mlxsw_pci *mlxsw_pci, char *mbox,
 758                              struct mlxsw_pci_queue *q)
 759 {
 760         int i;
 761         int err;
 762
 763         q->consumer_counter = 0;
 764
 765         for (i = 0; i < q->count; i++) {
 766                 char *elem = mlxsw_pci_queue_elem_get(q, i);
 767
 768                 mlxsw_pci_eqe_owner_set(elem, 1);
 769         }
 770
 771         mlxsw_cmd_mbox_sw2hw_eq_int_msix_set(mbox, 1); /* MSI-X used */
 772         mlxsw_cmd_mbox_sw2hw_eq_oi_set(mbox, 0);
 773         mlxsw_cmd_mbox_sw2hw_eq_st_set(mbox, 1); /* armed */
 774         mlxsw_cmd_mbox_sw2hw_eq_log_eq_size_set(mbox, ilog2(q->count));
 775         for (i = 0; i < MLXSW_PCI_AQ_PAGES; i++) {
 776                 dma_addr_t mapaddr = __mlxsw_pci_queue_page_get(q, i);
 777
 778                 mlxsw_cmd_mbox_sw2hw_eq_pa_set(mbox, i, mapaddr);
 779         }
 780         err = mlxsw_cmd_sw2hw_eq(mlxsw_pci->core, mbox, q->num);
 781         if (err)
 782                 return err;
 783         mlxsw_pci_queue_doorbell_consumer_ring(mlxsw_pci, q);
 784         mlxsw_pci_queue_doorbell_arm_consumer_ring(mlxsw_pci, q);
 785         return 0;
 786 }
 787
 788 static void mlxsw_pci_eq_fini(struct mlxsw_pci *mlxsw_pci,
 789                               struct mlxsw_pci_queue *q)
 790 {
 791         mlxsw_cmd_hw2sw_eq(mlxsw_pci->core, q->num);
 792 }
 793
 794 static int mlxsw_pci_eq_dbg_read(struct seq_file *file, void *data)
 795 {
 796         struct mlxsw_pci *mlxsw_pci = dev_get_drvdata(file->private);
 797         struct mlxsw_pci_queue *q;
 798         int i;
 799         static const char hdr[] =
 800                 "NUM CONS_COUNT     EV_CMD    EV_COMP   EV_OTHER COUNT\n";
 801
 802         seq_printf(file, hdr);
 803         for (i = 0; i < mlxsw_pci_eq_count(mlxsw_pci); i++) {
 804                 q = mlxsw_pci_eq_get(mlxsw_pci, i);
 805                 spin_lock_bh(&q->lock);
 806                 seq_printf(file, "%3d %10d %10d %10d %10d %5d\n",
 807                            i, q->consumer_counter, q->u.eq.ev_cmd_count,
 808                            q->u.eq.ev_comp_count, q->u.eq.ev_other_count,
 809                            q->count);
 810                 spin_unlock_bh(&q->lock);
 811         }
 812         return 0;
 813 }
 814
 815 static void mlxsw_pci_eq_cmd_event(struct mlxsw_pci *mlxsw_pci, char *eqe)
 816 {
 817         mlxsw_pci->cmd.comp.status = mlxsw_pci_eqe_cmd_status_get(eqe);
 818         mlxsw_pci->cmd.comp.out_param =
 819                 ((u64) mlxsw_pci_eqe_cmd_out_param_h_get(eqe)) << 32 |
 820                 mlxsw_pci_eqe_cmd_out_param_l_get(eqe);
 821         mlxsw_pci->cmd.wait_done = true;
 822         wake_up(&mlxsw_pci->cmd.wait);
 823 }
 824
 825 static char *mlxsw_pci_eq_sw_eqe_get(struct mlxsw_pci_queue *q)
 826 {
 827         return mlxsw_pci_queue_sw_elem_get(q, mlxsw_pci_eqe_owner_get);
 828 }
 829
 830 static void mlxsw_pci_eq_tasklet(unsigned long data)
 831 {
 832         struct mlxsw_pci_queue *q = (struct mlxsw_pci_queue *) data;
 833         struct mlxsw_pci *mlxsw_pci = q->pci;
 834         u8 cq_count = mlxsw_pci_cq_count(mlxsw_pci);
 835         unsigned long active_cqns[BITS_TO_LONGS(MLXSW_PCI_CQS_MAX)];
 836         char *eqe;
 837         u8 cqn;
 838         bool cq_handle = false;
 839         int items = 0;
 840         int credits = q->count >> 1;
 841
 842         memset(&active_cqns, 0, sizeof(active_cqns));
 843
 844         while ((eqe = mlxsw_pci_eq_sw_eqe_get(q))) {
 845                 u8 event_type = mlxsw_pci_eqe_event_type_get(eqe);
 846
 847                 switch (event_type) {
 848                 case MLXSW_PCI_EQE_EVENT_TYPE_CMD:
 849                         mlxsw_pci_eq_cmd_event(mlxsw_pci, eqe);
 850                         q->u.eq.ev_cmd_count++;
 851                         break;
 852                 case MLXSW_PCI_EQE_EVENT_TYPE_COMP:
 853                         cqn = mlxsw_pci_eqe_cqn_get(eqe);
 854                         set_bit(cqn, active_cqns);
 855                         cq_handle = true;
 856                         q->u.eq.ev_comp_count++;
 857                         break;
 858                 default:
 859                         q->u.eq.ev_other_count++;
 860                 }
 861                 if (++items == credits)
 862                         break;
 863         }
 864         if (items) {
 865                 mlxsw_pci_queue_doorbell_consumer_ring(mlxsw_pci, q);
 866                 mlxsw_pci_queue_doorbell_arm_consumer_ring(mlxsw_pci, q);
 867         }
 868
 869         if (!cq_handle)
 870                 return;
 871         for_each_set_bit(cqn, active_cqns, cq_count) {
 872                 q = mlxsw_pci_cq_get(mlxsw_pci, cqn);
 873                 mlxsw_pci_queue_tasklet_schedule(q);
 874         }
 875 }
 876
 877 struct mlxsw_pci_queue_ops {
 878         const char *name;
 879         enum mlxsw_pci_queue_type type;
 880         int (*init)(struct mlxsw_pci *mlxsw_pci, char *mbox,
 881                     struct mlxsw_pci_queue *q);
 882         void (*fini)(struct mlxsw_pci *mlxsw_pci,
 883                      struct mlxsw_pci_queue *q);
 884         void (*tasklet)(unsigned long data);
 885         int (*dbg_read)(struct seq_file *s, void *data);
 886         u16 elem_count;
 887         u8 elem_size;
 888 };
 889
 890 static const struct mlxsw_pci_queue_ops mlxsw_pci_sdq_ops = {
 891         .type           = MLXSW_PCI_QUEUE_TYPE_SDQ,
 892         .init           = mlxsw_pci_sdq_init,
 893         .fini           = mlxsw_pci_sdq_fini,
 894         .dbg_read       = mlxsw_pci_sdq_dbg_read,
 895         .elem_count     = MLXSW_PCI_WQE_COUNT,
 896         .elem_size      = MLXSW_PCI_WQE_SIZE,
 897 };
 898
 899 static const struct mlxsw_pci_queue_ops mlxsw_pci_rdq_ops = {
 900         .type           = MLXSW_PCI_QUEUE_TYPE_RDQ,
 901         .init           = mlxsw_pci_rdq_init,
 902         .fini           = mlxsw_pci_rdq_fini,
 903         .dbg_read       = mlxsw_pci_rdq_dbg_read,
 904         .elem_count     = MLXSW_PCI_WQE_COUNT,
 905         .elem_size      = MLXSW_PCI_WQE_SIZE
 906 };
 907
 908 static const struct mlxsw_pci_queue_ops mlxsw_pci_cq_ops = {
 909         .type           = MLXSW_PCI_QUEUE_TYPE_CQ,
 910         .init           = mlxsw_pci_cq_init,
 911         .fini           = mlxsw_pci_cq_fini,
 912         .tasklet        = mlxsw_pci_cq_tasklet,
 913         .dbg_read       = mlxsw_pci_cq_dbg_read,
 914         .elem_count     = MLXSW_PCI_CQE_COUNT,
 915         .elem_size      = MLXSW_PCI_CQE_SIZE
 916 };
 917
 918 static const struct mlxsw_pci_queue_ops mlxsw_pci_eq_ops = {
 919         .type           = MLXSW_PCI_QUEUE_TYPE_EQ,
 920         .init           = mlxsw_pci_eq_init,
 921         .fini           = mlxsw_pci_eq_fini,
 922         .tasklet        = mlxsw_pci_eq_tasklet,
 923         .dbg_read       = mlxsw_pci_eq_dbg_read,
 924         .elem_count     = MLXSW_PCI_EQE_COUNT,
 925         .elem_size      = MLXSW_PCI_EQE_SIZE
 926 };
 927
 928 static int mlxsw_pci_queue_init(struct mlxsw_pci *mlxsw_pci, char *mbox,
 929                                 const struct mlxsw_pci_queue_ops *q_ops,
 930                                 struct mlxsw_pci_queue *q, u8 q_num)
 931 {
 932         struct mlxsw_pci_mem_item *mem_item = &q->mem_item;
 933         int i;
 934         int err;
 935
 936         spin_lock_init(&q->lock);
 937         q->num = q_num;
 938         q->count = q_ops->elem_count;
 939         q->elem_size = q_ops->elem_size;
 940         q->type = q_ops->type;
 941         q->pci = mlxsw_pci;
 942
 943         if (q_ops->tasklet)
 944                 tasklet_init(&q->tasklet, q_ops->tasklet, (unsigned long) q);
 945
 946         mem_item->size = MLXSW_PCI_AQ_SIZE;
 947         mem_item->buf = pci_alloc_consistent(mlxsw_pci->pdev,
 948                                              mem_item->size,
 949                                              &mem_item->mapaddr);
 950         if (!mem_item->buf)
 951                 return -ENOMEM;
 952         memset(mem_item->buf, 0, mem_item->size);
 953
 954         q->elem_info = kcalloc(q->count, sizeof(*q->elem_info), GFP_KERNEL);
 955         if (!q->elem_info) {
 956                 err = -ENOMEM;
 957                 goto err_elem_info_alloc;
 958         }
 959
 960         /* Initialize dma mapped elements info elem_info for
 961          * future easy access.
 962          */
 963         for (i = 0; i < q->count; i++) {
 964                 struct mlxsw_pci_queue_elem_info *elem_info;
 965
 966                 elem_info = mlxsw_pci_queue_elem_info_get(q, i);
 967                 elem_info->elem =
 968                         __mlxsw_pci_queue_elem_get(q, q_ops->elem_size, i);
 969         }
 970
 971         mlxsw_cmd_mbox_zero(mbox);
 972         err = q_ops->init(mlxsw_pci, mbox, q);
 973         if (err)
 974                 goto err_q_ops_init;
 975         return 0;
 976
 977 err_q_ops_init:
 978         kfree(q->elem_info);
 979 err_elem_info_alloc:
 980         pci_free_consistent(mlxsw_pci->pdev, mem_item->size,
 981                             mem_item->buf, mem_item->mapaddr);
 982         return err;
 983 }
 984
 985 static void mlxsw_pci_queue_fini(struct mlxsw_pci *mlxsw_pci,
 986                                  const struct mlxsw_pci_queue_ops *q_ops,
 987                                  struct mlxsw_pci_queue *q)
 988 {
 989         struct mlxsw_pci_mem_item *mem_item = &q->mem_item;
 990
 991         q_ops->fini(mlxsw_pci, q);
 992         kfree(q->elem_info);
 993         pci_free_consistent(mlxsw_pci->pdev, mem_item->size,
 994                             mem_item->buf, mem_item->mapaddr);
 995 }
 996
 997 static int mlxsw_pci_queue_group_init(struct mlxsw_pci *mlxsw_pci, char *mbox,
 998                                       const struct mlxsw_pci_queue_ops *q_ops,
 999                                       u8 num_qs)
1000 {
1001         struct pci_dev *pdev = mlxsw_pci->pdev;
1002         struct mlxsw_pci_queue_type_group *queue_group;
1003         char tmp[16];
1004         int i;
1005         int err;
1006
1007         queue_group = mlxsw_pci_queue_type_group_get(mlxsw_pci, q_ops->type);
1008         queue_group->q = kcalloc(num_qs, sizeof(*queue_group->q), GFP_KERNEL);
1009         if (!queue_group->q)
1010                 return -ENOMEM;
1011
1012         for (i = 0; i < num_qs; i++) {
1013                 err = mlxsw_pci_queue_init(mlxsw_pci, mbox, q_ops,
1014                                            &queue_group->q[i], i);
1015                 if (err)
1016                         goto err_queue_init;
1017         }
1018         queue_group->count = num_qs;
1019
1020         sprintf(tmp, "%s_stats", mlxsw_pci_queue_type_str(q_ops->type));
1021         debugfs_create_devm_seqfile(&pdev->dev, tmp, mlxsw_pci->dbg_dir,
1022                                     q_ops->dbg_read);
1023
1024         return 0;
1025
1026 err_queue_init:
1027         for (i--; i >= 0; i--)
1028                 mlxsw_pci_queue_fini(mlxsw_pci, q_ops, &queue_group->q[i]);
1029         kfree(queue_group->q);
1030         return err;
1031 }
1032
1033 static void mlxsw_pci_queue_group_fini(struct mlxsw_pci *mlxsw_pci,
1034                                        const struct mlxsw_pci_queue_ops *q_ops)
1035 {
1036         struct mlxsw_pci_queue_type_group *queue_group;
1037         int i;
1038
1039         queue_group = mlxsw_pci_queue_type_group_get(mlxsw_pci, q_ops->type);
1040         for (i = 0; i < queue_group->count; i++)
1041                 mlxsw_pci_queue_fini(mlxsw_pci, q_ops, &queue_group->q[i]);
1042         kfree(queue_group->q);
1043 }
1044
1045 static int mlxsw_pci_aqs_init(struct mlxsw_pci *mlxsw_pci, char *mbox)
1046 {
1047         struct pci_dev *pdev = mlxsw_pci->pdev;
1048         u8 num_sdqs;
1049         u8 sdq_log2sz;
1050         u8 num_rdqs;
1051         u8 rdq_log2sz;
1052         u8 num_cqs;
1053         u8 cq_log2sz;
1054         u8 num_eqs;
1055         u8 eq_log2sz;
1056         int err;
1057
1058         mlxsw_cmd_mbox_zero(mbox);
1059         err = mlxsw_cmd_query_aq_cap(mlxsw_pci->core, mbox);
1060         if (err)
1061                 return err;
1062
1063         num_sdqs = mlxsw_cmd_mbox_query_aq_cap_max_num_sdqs_get(mbox);
1064         sdq_log2sz = mlxsw_cmd_mbox_query_aq_cap_log_max_sdq_sz_get(mbox);
1065         num_rdqs = mlxsw_cmd_mbox_query_aq_cap_max_num_rdqs_get(mbox);
1066         rdq_log2sz = mlxsw_cmd_mbox_query_aq_cap_log_max_rdq_sz_get(mbox);
1067         num_cqs = mlxsw_cmd_mbox_query_aq_cap_max_num_cqs_get(mbox);
1068         cq_log2sz = mlxsw_cmd_mbox_query_aq_cap_log_max_cq_sz_get(mbox);
1069         num_eqs = mlxsw_cmd_mbox_query_aq_cap_max_num_eqs_get(mbox);
1070         eq_log2sz = mlxsw_cmd_mbox_query_aq_cap_log_max_eq_sz_get(mbox);
1071
1072         if ((num_sdqs != MLXSW_PCI_SDQS_COUNT) ||
1073             (num_rdqs != MLXSW_PCI_RDQS_COUNT) ||
1074             num_cqs > MLXSW_PCI_CQS_MAX || num_eqs != MLXSW_PCI_EQS_COUNT) {
1075                 dev_err(&pdev->dev, "Unsupported number of queues\n");
1076                 return -EINVAL;
1077         }
1078
1079         if ((1 << sdq_log2sz != MLXSW_PCI_WQE_COUNT) ||
1080             (1 << rdq_log2sz != MLXSW_PCI_WQE_COUNT) ||
1081             (1 << cq_log2sz != MLXSW_PCI_CQE_COUNT) ||
1082             (1 << eq_log2sz != MLXSW_PCI_EQE_COUNT)) {
1083                 dev_err(&pdev->dev, "Unsupported number of async queue descriptors\n");
1084                 return -EINVAL;
1085         }
1086
1087         err = mlxsw_pci_queue_group_init(mlxsw_pci, mbox, &mlxsw_pci_eq_ops,
1088                                          num_eqs);
1089         if (err) {
1090                 dev_err(&pdev->dev, "Failed to initialize event queues\n");
1091                 return err;
1092         }
1093
1094         err = mlxsw_pci_queue_group_init(mlxsw_pci, mbox, &mlxsw_pci_cq_ops,
1095                                          num_cqs);
1096         if (err) {
1097                 dev_err(&pdev->dev, "Failed to initialize completion queues\n");
1098                 goto err_cqs_init;
1099         }
1100
1101         err = mlxsw_pci_queue_group_init(mlxsw_pci, mbox, &mlxsw_pci_sdq_ops,
1102                                          num_sdqs);
1103         if (err) {
1104                 dev_err(&pdev->dev, "Failed to initialize send descriptor queues\n");
1105                 goto err_sdqs_init;
1106         }
1107
1108         err = mlxsw_pci_queue_group_init(mlxsw_pci, mbox, &mlxsw_pci_rdq_ops,
1109                                          num_rdqs);
1110         if (err) {
1111                 dev_err(&pdev->dev, "Failed to initialize receive descriptor queues\n");
1112                 goto err_rdqs_init;
1113         }
1114
1115         /* We have to poll in command interface until queues are initialized */
1116         mlxsw_pci->cmd.nopoll = true;
1117         return 0;
1118
1119 err_rdqs_init:
1120         mlxsw_pci_queue_group_fini(mlxsw_pci, &mlxsw_pci_sdq_ops);
1121 err_sdqs_init:
1122         mlxsw_pci_queue_group_fini(mlxsw_pci, &mlxsw_pci_cq_ops);
1123 err_cqs_init:
1124         mlxsw_pci_queue_group_fini(mlxsw_pci, &mlxsw_pci_eq_ops);
1125         return err;
1126 }
1127
1128 static void mlxsw_pci_aqs_fini(struct mlxsw_pci *mlxsw_pci)
1129 {
1130         mlxsw_pci->cmd.nopoll = false;
1131         mlxsw_pci_queue_group_fini(mlxsw_pci, &mlxsw_pci_rdq_ops);
1132         mlxsw_pci_queue_group_fini(mlxsw_pci, &mlxsw_pci_sdq_ops);
1133         mlxsw_pci_queue_group_fini(mlxsw_pci, &mlxsw_pci_cq_ops);
1134         mlxsw_pci_queue_group_fini(mlxsw_pci, &mlxsw_pci_eq_ops);
1135 }
1136
1137 static void
1138 mlxsw_pci_config_profile_swid_config(struct mlxsw_pci *mlxsw_pci,
1139                                      char *mbox, int index,
1140                                      const struct mlxsw_swid_config *swid)
1141 {
1142         u8 mask = 0;
1143
1144         if (swid->used_type) {
1145                 mlxsw_cmd_mbox_config_profile_swid_config_type_set(
1146                         mbox, index, swid->type);
1147                 mask |= 1;
1148         }
1149         if (swid->used_properties) {
1150                 mlxsw_cmd_mbox_config_profile_swid_config_properties_set(
1151                         mbox, index, swid->properties);
1152                 mask |= 2;
1153         }
1154         mlxsw_cmd_mbox_config_profile_swid_config_mask_set(mbox, index, mask);
1155 }
1156
1157 static int mlxsw_pci_config_profile(struct mlxsw_pci *mlxsw_pci, char *mbox,
1158                                     const struct mlxsw_config_profile *profile)
1159 {
1160         int i;
1161
1162         mlxsw_cmd_mbox_zero(mbox);
1163
1164         if (profile->used_max_vepa_channels) {
1165                 mlxsw_cmd_mbox_config_profile_set_max_vepa_channels_set(
1166                         mbox, 1);
1167                 mlxsw_cmd_mbox_config_profile_max_vepa_channels_set(
1168                         mbox, profile->max_vepa_channels);
1169         }
1170         if (profile->used_max_lag) {
1171                 mlxsw_cmd_mbox_config_profile_set_max_lag_set(
1172                         mbox, 1);
1173                 mlxsw_cmd_mbox_config_profile_max_lag_set(
1174                         mbox, profile->max_lag);
1175         }
1176         if (profile->used_max_port_per_lag) {
1177                 mlxsw_cmd_mbox_config_profile_set_max_port_per_lag_set(
1178                         mbox, 1);
1179                 mlxsw_cmd_mbox_config_profile_max_port_per_lag_set(
1180                         mbox, profile->max_port_per_lag);
1181         }
1182         if (profile->used_max_mid) {
1183                 mlxsw_cmd_mbox_config_profile_set_max_mid_set(
1184                         mbox, 1);
1185                 mlxsw_cmd_mbox_config_profile_max_mid_set(
1186                         mbox, profile->max_mid);
1187         }
1188         if (profile->used_max_pgt) {
1189                 mlxsw_cmd_mbox_config_profile_set_max_pgt_set(
1190                         mbox, 1);
1191                 mlxsw_cmd_mbox_config_profile_max_pgt_set(
1192                         mbox, profile->max_pgt);
1193         }
1194         if (profile->used_max_system_port) {
1195                 mlxsw_cmd_mbox_config_profile_set_max_system_port_set(
1196                         mbox, 1);
1197                 mlxsw_cmd_mbox_config_profile_max_system_port_set(
1198                         mbox, profile->max_system_port);
1199         }
1200         if (profile->used_max_vlan_groups) {
1201                 mlxsw_cmd_mbox_config_profile_set_max_vlan_groups_set(
1202                         mbox, 1);
1203                 mlxsw_cmd_mbox_config_profile_max_vlan_groups_set(
1204                         mbox, profile->max_vlan_groups);
1205         }
1206         if (profile->used_max_regions) {
1207                 mlxsw_cmd_mbox_config_profile_set_max_regions_set(
1208                         mbox, 1);
1209                 mlxsw_cmd_mbox_config_profile_max_regions_set(
1210                         mbox, profile->max_regions);
1211         }
1212         if (profile->used_flood_tables) {
1213                 mlxsw_cmd_mbox_config_profile_set_flood_tables_set(
1214                         mbox, 1);
1215                 mlxsw_cmd_mbox_config_profile_max_flood_tables_set(
1216                         mbox, profile->max_flood_tables);
1217                 mlxsw_cmd_mbox_config_profile_max_vid_flood_tables_set(
1218                         mbox, profile->max_vid_flood_tables);
1219         }
1220         if (profile->used_flood_mode) {
1221                 mlxsw_cmd_mbox_config_profile_set_flood_mode_set(
1222                         mbox, 1);
1223                 mlxsw_cmd_mbox_config_profile_flood_mode_set(
1224                         mbox, profile->flood_mode);
1225         }
1226         if (profile->used_max_ib_mc) {
1227                 mlxsw_cmd_mbox_config_profile_set_max_ib_mc_set(
1228                         mbox, 1);
1229                 mlxsw_cmd_mbox_config_profile_max_ib_mc_set(
1230                         mbox, profile->max_ib_mc);
1231         }
1232         if (profile->used_max_pkey) {
1233                 mlxsw_cmd_mbox_config_profile_set_max_pkey_set(
1234                         mbox, 1);
1235                 mlxsw_cmd_mbox_config_profile_max_pkey_set(
1236                         mbox, profile->max_pkey);
1237         }
1238         if (profile->used_ar_sec) {
1239                 mlxsw_cmd_mbox_config_profile_set_ar_sec_set(
1240                         mbox, 1);
1241                 mlxsw_cmd_mbox_config_profile_ar_sec_set(
1242                         mbox, profile->ar_sec);
1243         }
1244         if (profile->used_adaptive_routing_group_cap) {
1245                 mlxsw_cmd_mbox_config_profile_set_adaptive_routing_group_cap_set(
1246                         mbox, 1);
1247                 mlxsw_cmd_mbox_config_profile_adaptive_routing_group_cap_set(
1248                         mbox, profile->adaptive_routing_group_cap);
1249         }
1250
1251         for (i = 0; i < MLXSW_CONFIG_PROFILE_SWID_COUNT; i++)
1252                 mlxsw_pci_config_profile_swid_config(mlxsw_pci, mbox, i,
1253                                                      &profile->swid_config[i]);
1254
1255         return mlxsw_cmd_config_profile_set(mlxsw_pci->core, mbox);
1256 }
1257
1258 static int mlxsw_pci_boardinfo(struct mlxsw_pci *mlxsw_pci, char *mbox)
1259 {
1260         struct mlxsw_bus_info *bus_info = &mlxsw_pci->bus_info;
1261         int err;
1262
1263         mlxsw_cmd_mbox_zero(mbox);
1264         err = mlxsw_cmd_boardinfo(mlxsw_pci->core, mbox);
1265         if (err)
1266                 return err;
1267         mlxsw_cmd_mbox_boardinfo_vsd_memcpy_from(mbox, bus_info->vsd);
1268         mlxsw_cmd_mbox_boardinfo_psid_memcpy_from(mbox, bus_info->psid);
1269         return 0;
1270 }
1271
1272 static int mlxsw_pci_fw_area_init(struct mlxsw_pci *mlxsw_pci, char *mbox,
1273                                   u16 num_pages)
1274 {
1275         struct mlxsw_pci_mem_item *mem_item;
1276         int i;
1277         int err;
1278
1279         mlxsw_pci->fw_area.items = kcalloc(num_pages, sizeof(*mem_item),
1280                                            GFP_KERNEL);
1281         if (!mlxsw_pci->fw_area.items)
1282                 return -ENOMEM;
1283         mlxsw_pci->fw_area.num_pages = num_pages;
1284
1285         mlxsw_cmd_mbox_zero(mbox);
1286         for (i = 0; i < num_pages; i++) {
1287                 mem_item = &mlxsw_pci->fw_area.items[i];
1288
1289                 mem_item->size = MLXSW_PCI_PAGE_SIZE;
1290                 mem_item->buf = pci_alloc_consistent(mlxsw_pci->pdev,
1291                                                      mem_item->size,
1292                                                      &mem_item->mapaddr);
1293                 if (!mem_item->buf) {
1294                         err = -ENOMEM;
1295                         goto err_alloc;
1296                 }
1297                 mlxsw_cmd_mbox_map_fa_pa_set(mbox, i, mem_item->mapaddr);
1298                 mlxsw_cmd_mbox_map_fa_log2size_set(mbox, i, 0); /* 1 page */
1299         }
1300
1301         err = mlxsw_cmd_map_fa(mlxsw_pci->core, mbox, num_pages);
1302         if (err)
1303                 goto err_cmd_map_fa;
1304
1305         return 0;
1306
1307 err_cmd_map_fa:
1308 err_alloc:
1309         for (i--; i >= 0; i--) {
1310                 mem_item = &mlxsw_pci->fw_area.items[i];
1311
1312                 pci_free_consistent(mlxsw_pci->pdev, mem_item->size,
1313                                     mem_item->buf, mem_item->mapaddr);
1314         }
1315         kfree(mlxsw_pci->fw_area.items);
1316         return err;
1317 }
1318
1319 static void mlxsw_pci_fw_area_fini(struct mlxsw_pci *mlxsw_pci)
1320 {
1321         struct mlxsw_pci_mem_item *mem_item;
1322         int i;
1323
1324         mlxsw_cmd_unmap_fa(mlxsw_pci->core);
1325
1326         for (i = 0; i < mlxsw_pci->fw_area.num_pages; i++) {
1327                 mem_item = &mlxsw_pci->fw_area.items[i];
1328
1329                 pci_free_consistent(mlxsw_pci->pdev, mem_item->size,
1330                                     mem_item->buf, mem_item->mapaddr);
1331         }
1332         kfree(mlxsw_pci->fw_area.items);
1333 }
1334
1335 static irqreturn_t mlxsw_pci_eq_irq_handler(int irq, void *dev_id)
1336 {
1337         struct mlxsw_pci *mlxsw_pci = dev_id;
1338         struct mlxsw_pci_queue *q;
1339         int i;
1340
1341         for (i = 0; i < MLXSW_PCI_EQS_COUNT; i++) {
1342                 q = mlxsw_pci_eq_get(mlxsw_pci, i);
1343                 mlxsw_pci_queue_tasklet_schedule(q);
1344         }
1345         return IRQ_HANDLED;
1346 }
1347
1348 static int mlxsw_pci_mbox_alloc(struct mlxsw_pci *mlxsw_pci,
1349                                 struct mlxsw_pci_mem_item *mbox)
1350 {
1351         struct pci_dev *pdev = mlxsw_pci->pdev;
1352         int err = 0;
1353
1354         mbox->size = MLXSW_CMD_MBOX_SIZE;
1355         mbox->buf = pci_alloc_consistent(pdev, MLXSW_CMD_MBOX_SIZE,
1356                                          &mbox->mapaddr);
1357         if (!mbox->buf) {
1358                 dev_err(&pdev->dev, "Failed allocating memory for mailbox\n");
1359                 err = -ENOMEM;
1360         }
1361
1362         return err;
1363 }
1364
1365 static void mlxsw_pci_mbox_free(struct mlxsw_pci *mlxsw_pci,
1366                                 struct mlxsw_pci_mem_item *mbox)
1367 {
1368         struct pci_dev *pdev = mlxsw_pci->pdev;
1369
1370         pci_free_consistent(pdev, MLXSW_CMD_MBOX_SIZE, mbox->buf,
1371                             mbox->mapaddr);
1372 }
1373
1374 static int mlxsw_pci_init(void *bus_priv, struct mlxsw_core *mlxsw_core,
1375                           const struct mlxsw_config_profile *profile)
1376 {
1377         struct mlxsw_pci *mlxsw_pci = bus_priv;
1378         struct pci_dev *pdev = mlxsw_pci->pdev;
1379         char *mbox;
1380         u16 num_pages;
1381         int err;
1382
1383         mutex_init(&mlxsw_pci->cmd.lock);
1384         init_waitqueue_head(&mlxsw_pci->cmd.wait);
1385
1386         mlxsw_pci->core = mlxsw_core;
1387
1388         mbox = mlxsw_cmd_mbox_alloc();
1389         if (!mbox)
1390                 return -ENOMEM;
1391
1392         err = mlxsw_pci_mbox_alloc(mlxsw_pci, &mlxsw_pci->cmd.in_mbox);
1393         if (err)
1394                 goto mbox_put;
1395
1396         err = mlxsw_pci_mbox_alloc(mlxsw_pci, &mlxsw_pci->cmd.out_mbox);
1397         if (err)
1398                 goto err_out_mbox_alloc;
1399
1400         err = mlxsw_cmd_query_fw(mlxsw_core, mbox);
1401         if (err)
1402                 goto err_query_fw;
1403
1404         mlxsw_pci->bus_info.fw_rev.major =
1405                 mlxsw_cmd_mbox_query_fw_fw_rev_major_get(mbox);
1406         mlxsw_pci->bus_info.fw_rev.minor =
1407                 mlxsw_cmd_mbox_query_fw_fw_rev_minor_get(mbox);
1408         mlxsw_pci->bus_info.fw_rev.subminor =
1409                 mlxsw_cmd_mbox_query_fw_fw_rev_subminor_get(mbox);
1410
1411         if (mlxsw_cmd_mbox_query_fw_cmd_interface_rev_get(mbox) != 1) {
1412                 dev_err(&pdev->dev, "Unsupported cmd interface revision ID queried from hw\n");
1413                 err = -EINVAL;
1414                 goto err_iface_rev;
1415         }
1416         if (mlxsw_cmd_mbox_query_fw_doorbell_page_bar_get(mbox) != 0) {
1417                 dev_err(&pdev->dev, "Unsupported doorbell page bar queried from hw\n");
1418                 err = -EINVAL;
1419                 goto err_doorbell_page_bar;
1420         }
1421
1422         mlxsw_pci->doorbell_offset =
1423                 mlxsw_cmd_mbox_query_fw_doorbell_page_offset_get(mbox);
1424
1425         num_pages = mlxsw_cmd_mbox_query_fw_fw_pages_get(mbox);
1426         err = mlxsw_pci_fw_area_init(mlxsw_pci, mbox, num_pages);
1427         if (err)
1428                 goto err_fw_area_init;
1429
1430         err = mlxsw_pci_boardinfo(mlxsw_pci, mbox);
1431         if (err)
1432                 goto err_boardinfo;
1433
1434         err = mlxsw_pci_config_profile(mlxsw_pci, mbox, profile);
1435         if (err)
1436                 goto err_config_profile;
1437
1438         err = mlxsw_pci_aqs_init(mlxsw_pci, mbox);
1439         if (err)
1440                 goto err_aqs_init;
1441
1442         err = request_irq(mlxsw_pci->msix_entry.vector,
1443                           mlxsw_pci_eq_irq_handler, 0,
1444                           mlxsw_pci_driver_name, mlxsw_pci);
1445         if (err) {
1446                 dev_err(&pdev->dev, "IRQ request failed\n");
1447                 goto err_request_eq_irq;
1448         }
1449
1450         goto mbox_put;
1451
1452 err_request_eq_irq:
1453         mlxsw_pci_aqs_fini(mlxsw_pci);
1454 err_aqs_init:
1455 err_config_profile:
1456 err_boardinfo:
1457         mlxsw_pci_fw_area_fini(mlxsw_pci);
1458 err_fw_area_init:
1459 err_doorbell_page_bar:
1460 err_iface_rev:
1461 err_query_fw:
1462         mlxsw_pci_mbox_free(mlxsw_pci, &mlxsw_pci->cmd.out_mbox);
1463 err_out_mbox_alloc:
1464         mlxsw_pci_mbox_free(mlxsw_pci, &mlxsw_pci->cmd.in_mbox);
1465 mbox_put:
1466         mlxsw_cmd_mbox_free(mbox);
1467         return err;
1468 }
1469
1470 static void mlxsw_pci_fini(void *bus_priv)
1471 {
1472         struct mlxsw_pci *mlxsw_pci = bus_priv;
1473
1474         free_irq(mlxsw_pci->msix_entry.vector, mlxsw_pci);
1475         mlxsw_pci_aqs_fini(mlxsw_pci);
1476         mlxsw_pci_fw_area_fini(mlxsw_pci);
1477         mlxsw_pci_mbox_free(mlxsw_pci, &mlxsw_pci->cmd.out_mbox);
1478         mlxsw_pci_mbox_free(mlxsw_pci, &mlxsw_pci->cmd.in_mbox);
1479 }
1480
1481 static struct mlxsw_pci_queue *
1482 mlxsw_pci_sdq_pick(struct mlxsw_pci *mlxsw_pci,
1483                    const struct mlxsw_tx_info *tx_info)
1484 {
1485         u8 sdqn = tx_info->local_port % mlxsw_pci_sdq_count(mlxsw_pci);
1486
1487         return mlxsw_pci_sdq_get(mlxsw_pci, sdqn);
1488 }
1489
1490 static bool mlxsw_pci_skb_transmit_busy(void *bus_priv,
1491                                         const struct mlxsw_tx_info *tx_info)
1492 {
1493         struct mlxsw_pci *mlxsw_pci = bus_priv;
1494         struct mlxsw_pci_queue *q = mlxsw_pci_sdq_pick(mlxsw_pci, tx_info);
1495
1496         return !mlxsw_pci_queue_elem_info_producer_get(q);
1497 }
1498
1499 static int mlxsw_pci_skb_transmit(void *bus_priv, struct sk_buff *skb,
1500                                   const struct mlxsw_tx_info *tx_info)
1501 {
1502         struct mlxsw_pci *mlxsw_pci = bus_priv;
1503         struct mlxsw_pci_queue *q;
1504         struct mlxsw_pci_queue_elem_info *elem_info;
1505         char *wqe;
1506         int i;
1507         int err;
1508
1509         if (skb_shinfo(skb)->nr_frags > MLXSW_PCI_WQE_SG_ENTRIES - 1) {
1510                 err = skb_linearize(skb);
1511                 if (err)
1512                         return err;
1513         }
1514
1515         q = mlxsw_pci_sdq_pick(mlxsw_pci, tx_info);
1516         spin_lock_bh(&q->lock);
1517         elem_info = mlxsw_pci_queue_elem_info_producer_get(q);
1518         if (!elem_info) {
1519                 /* queue is full */
1520                 err = -EAGAIN;
1521                 goto unlock;
1522         }
1523         elem_info->u.sdq.skb = skb;
1524
1525         wqe = elem_info->elem;
1526         mlxsw_pci_wqe_c_set(wqe, 1); /* always report completion */
1527         mlxsw_pci_wqe_lp_set(wqe, !!tx_info->is_emad);
1528         mlxsw_pci_wqe_type_set(wqe, MLXSW_PCI_WQE_TYPE_ETHERNET);
1529
1530         err = mlxsw_pci_wqe_frag_map(mlxsw_pci, wqe, 0, skb->data,
1531                                      skb_headlen(skb), DMA_TO_DEVICE);
1532         if (err)
1533                 goto unlock;
1534
1535         for (i = 0; i < skb_shinfo(skb)->nr_frags; i++) {
1536                 const skb_frag_t *frag = &skb_shinfo(skb)->frags[i];
1537
1538                 err = mlxsw_pci_wqe_frag_map(mlxsw_pci, wqe, i + 1,
1539                                              skb_frag_address(frag),
1540                                              skb_frag_size(frag),
1541                                              DMA_TO_DEVICE);
1542                 if (err)
1543                         goto unmap_frags;
1544         }
1545
1546         /* Set unused sq entries byte count to zero. */
1547         for (i++; i < MLXSW_PCI_WQE_SG_ENTRIES; i++)
1548                 mlxsw_pci_wqe_byte_count_set(wqe, i, 0);
1549
1550         /* Everything is set up, ring producer doorbell to get HW going */
1551         q->producer_counter++;
1552         mlxsw_pci_queue_doorbell_producer_ring(mlxsw_pci, q);
1553
1554         goto unlock;
1555
1556 unmap_frags:
1557         for (; i >= 0; i--)
1558                 mlxsw_pci_wqe_frag_unmap(mlxsw_pci, wqe, i, DMA_TO_DEVICE);
1559 unlock:
1560         spin_unlock_bh(&q->lock);
1561         return err;
1562 }
1563
1564 static int mlxsw_pci_cmd_exec(void *bus_priv, u16 opcode, u8 opcode_mod,
1565                               u32 in_mod, bool out_mbox_direct,
1566                               char *in_mbox, size_t in_mbox_size,
1567                               char *out_mbox, size_t out_mbox_size,
1568                               u8 *p_status)
1569 {
1570         struct mlxsw_pci *mlxsw_pci = bus_priv;
1571         dma_addr_t in_mapaddr = mlxsw_pci->cmd.in_mbox.mapaddr;
1572         dma_addr_t out_mapaddr = mlxsw_pci->cmd.out_mbox.mapaddr;
1573         bool evreq = mlxsw_pci->cmd.nopoll;
1574         unsigned long timeout = msecs_to_jiffies(MLXSW_PCI_CIR_TIMEOUT_MSECS);
1575         bool *p_wait_done = &mlxsw_pci->cmd.wait_done;
1576         int err;
1577
1578         *p_status = MLXSW_CMD_STATUS_OK;
1579
1580         err = mutex_lock_interruptible(&mlxsw_pci->cmd.lock);
1581         if (err)
1582                 return err;
1583
1584         if (in_mbox)
1585                 memcpy(mlxsw_pci->cmd.in_mbox.buf, in_mbox, in_mbox_size);
1586         mlxsw_pci_write32(mlxsw_pci, CIR_IN_PARAM_HI, in_mapaddr >> 32);
1587         mlxsw_pci_write32(mlxsw_pci, CIR_IN_PARAM_LO, in_mapaddr);
1588
1589         mlxsw_pci_write32(mlxsw_pci, CIR_OUT_PARAM_HI, out_mapaddr >> 32);
1590         mlxsw_pci_write32(mlxsw_pci, CIR_OUT_PARAM_LO, out_mapaddr);
1591
1592         mlxsw_pci_write32(mlxsw_pci, CIR_IN_MODIFIER, in_mod);
1593         mlxsw_pci_write32(mlxsw_pci, CIR_TOKEN, 0);
1594
1595         *p_wait_done = false;
1596
1597         wmb(); /* all needs to be written before we write control register */
1598         mlxsw_pci_write32(mlxsw_pci, CIR_CTRL,
1599                           MLXSW_PCI_CIR_CTRL_GO_BIT |
1600                           (evreq ? MLXSW_PCI_CIR_CTRL_EVREQ_BIT : 0) |
1601                           (opcode_mod << MLXSW_PCI_CIR_CTRL_OPCODE_MOD_SHIFT) |
1602                           opcode);
1603
1604         if (!evreq) {
1605                 unsigned long end;
1606
1607                 end = jiffies + timeout;
1608                 do {
1609                         u32 ctrl = mlxsw_pci_read32(mlxsw_pci, CIR_CTRL);
1610
1611                         if (!(ctrl & MLXSW_PCI_CIR_CTRL_GO_BIT)) {
1612                                 *p_wait_done = true;
1613                                 *p_status = ctrl >> MLXSW_PCI_CIR_CTRL_STATUS_SHIFT;
1614                                 break;
1615                         }
1616                         cond_resched();
1617                 } while (time_before(jiffies, end));
1618         } else {
1619                 wait_event_timeout(mlxsw_pci->cmd.wait, *p_wait_done, timeout);
1620                 *p_status = mlxsw_pci->cmd.comp.status;
1621         }
1622
1623         err = 0;
1624         if (*p_wait_done) {
1625                 if (*p_status)
1626                         err = -EIO;
1627         } else {
1628                 err = -ETIMEDOUT;
1629         }
1630
1631         if (!err && out_mbox && out_mbox_direct) {
1632                 /* Some commands don't use output param as address to mailbox
1633                  * but they store output directly into registers. In that case,
1634                  * copy registers into mbox buffer.
1635                  */
1636                 __be32 tmp;
1637
1638                 if (!evreq) {
1639                         tmp = cpu_to_be32(mlxsw_pci_read32(mlxsw_pci,
1640                                                            CIR_OUT_PARAM_HI));
1641                         memcpy(out_mbox, &tmp, sizeof(tmp));
1642                         tmp = cpu_to_be32(mlxsw_pci_read32(mlxsw_pci,
1643                                                            CIR_OUT_PARAM_LO));
1644                         memcpy(out_mbox + sizeof(tmp), &tmp, sizeof(tmp));
1645                 }
1646         } else if (!err && out_mbox)
1647                 memcpy(out_mbox, mlxsw_pci->cmd.out_mbox.buf, out_mbox_size);
1648
1649         mutex_unlock(&mlxsw_pci->cmd.lock);
1650
1651         return err;
1652 }
1653
1654 static const struct mlxsw_bus mlxsw_pci_bus = {
1655         .kind                   = "pci",
1656         .init                   = mlxsw_pci_init,
1657         .fini                   = mlxsw_pci_fini,
1658         .skb_transmit_busy      = mlxsw_pci_skb_transmit_busy,
1659         .skb_transmit           = mlxsw_pci_skb_transmit,
1660         .cmd_exec               = mlxsw_pci_cmd_exec,
1661 };
1662
1663 static int mlxsw_pci_sw_reset(struct mlxsw_pci *mlxsw_pci)
1664 {
1665         mlxsw_pci_write32(mlxsw_pci, SW_RESET, MLXSW_PCI_SW_RESET_RST_BIT);
1666         /* Current firware does not let us know when the reset is done.
1667          * So we just wait here for constant time and hope for the best.
1668          */
1669         msleep(MLXSW_PCI_SW_RESET_TIMEOUT_MSECS);
1670         return 0;
1671 }
1672
1673 static int mlxsw_pci_probe(struct pci_dev *pdev, const struct pci_device_id *id)
1674 {
1675         struct mlxsw_pci *mlxsw_pci;
1676         int err;
1677
1678         mlxsw_pci = kzalloc(sizeof(*mlxsw_pci), GFP_KERNEL);
1679         if (!mlxsw_pci)
1680                 return -ENOMEM;
1681
1682         err = pci_enable_device(pdev);
1683         if (err) {
1684                 dev_err(&pdev->dev, "pci_enable_device failed\n");
1685                 goto err_pci_enable_device;
1686         }
1687
1688         err = pci_request_regions(pdev, mlxsw_pci_driver_name);
1689         if (err) {
1690                 dev_err(&pdev->dev, "pci_request_regions failed\n");
1691                 goto err_pci_request_regions;
1692         }
1693
1694         err = pci_set_dma_mask(pdev, DMA_BIT_MASK(64));
1695         if (!err) {
1696                 err = pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(64));
1697                 if (err) {
1698                         dev_err(&pdev->dev, "pci_set_consistent_dma_mask failed\n");
1699                         goto err_pci_set_dma_mask;
1700                 }
1701         } else {
1702                 err = pci_set_dma_mask(pdev, DMA_BIT_MASK(32));
1703                 if (err) {
1704                         dev_err(&pdev->dev, "pci_set_dma_mask failed\n");
1705                         goto err_pci_set_dma_mask;
1706                 }
1707         }
1708
1709         if (pci_resource_len(pdev, 0) < MLXSW_PCI_BAR0_SIZE) {
1710                 dev_err(&pdev->dev, "invalid PCI region size\n");
1711                 err = -EINVAL;
1712                 goto err_pci_resource_len_check;
1713         }
1714
1715         mlxsw_pci->hw_addr = ioremap(pci_resource_start(pdev, 0),
1716                                      pci_resource_len(pdev, 0));
1717         if (!mlxsw_pci->hw_addr) {
1718                 dev_err(&pdev->dev, "ioremap failed\n");
1719                 err = -EIO;
1720                 goto err_ioremap;
1721         }
1722         pci_set_master(pdev);
1723
1724         mlxsw_pci->pdev = pdev;
1725         pci_set_drvdata(pdev, mlxsw_pci);
1726
1727         err = mlxsw_pci_sw_reset(mlxsw_pci);
1728         if (err) {
1729                 dev_err(&pdev->dev, "Software reset failed\n");
1730                 goto err_sw_reset;
1731         }
1732
1733         err = pci_enable_msix_exact(pdev, &mlxsw_pci->msix_entry, 1);
1734         if (err) {
1735                 dev_err(&pdev->dev, "MSI-X init failed\n");
1736                 goto err_msix_init;
1737         }
1738
1739         mlxsw_pci->bus_info.device_kind = mlxsw_pci_device_kind_get(id);
1740         mlxsw_pci->bus_info.device_name = pci_name(mlxsw_pci->pdev);
1741         mlxsw_pci->bus_info.dev = &pdev->dev;
1742
1743         mlxsw_pci->dbg_dir = debugfs_create_dir(mlxsw_pci->bus_info.device_name,
1744                                                 mlxsw_pci_dbg_root);
1745         if (!mlxsw_pci->dbg_dir) {
1746                 dev_err(&pdev->dev, "Failed to create debugfs dir\n");
1747                 err = -ENOMEM;
1748                 goto err_dbg_create_dir;
1749         }
1750
1751         err = mlxsw_core_bus_device_register(&mlxsw_pci->bus_info,
1752                                              &mlxsw_pci_bus, mlxsw_pci);
1753         if (err) {
1754                 dev_err(&pdev->dev, "cannot register bus device\n");
1755                 goto err_bus_device_register;
1756         }
1757
1758         return 0;
1759
1760 err_bus_device_register:
1761         debugfs_remove_recursive(mlxsw_pci->dbg_dir);
1762 err_dbg_create_dir:
1763         pci_disable_msix(mlxsw_pci->pdev);
1764 err_msix_init:
1765 err_sw_reset:
1766         iounmap(mlxsw_pci->hw_addr);
1767 err_ioremap:
1768 err_pci_resource_len_check:
1769 err_pci_set_dma_mask:
1770         pci_release_regions(pdev);
1771 err_pci_request_regions:
1772         pci_disable_device(pdev);
1773 err_pci_enable_device:
1774         kfree(mlxsw_pci);
1775         return err;
1776 }
1777
1778 static void mlxsw_pci_remove(struct pci_dev *pdev)
1779 {
1780         struct mlxsw_pci *mlxsw_pci = pci_get_drvdata(pdev);
1781
1782         mlxsw_core_bus_device_unregister(mlxsw_pci->core);
1783         debugfs_remove_recursive(mlxsw_pci->dbg_dir);
1784         pci_disable_msix(mlxsw_pci->pdev);
1785         iounmap(mlxsw_pci->hw_addr);
1786         pci_release_regions(mlxsw_pci->pdev);
1787         pci_disable_device(mlxsw_pci->pdev);
1788         kfree(mlxsw_pci);
1789 }
1790
1791 static struct pci_driver mlxsw_pci_driver = {
1792         .name           = mlxsw_pci_driver_name,
1793         .id_table       = mlxsw_pci_id_table,
1794         .probe          = mlxsw_pci_probe,
1795         .remove         = mlxsw_pci_remove,
1796 };
1797
1798 static int __init mlxsw_pci_module_init(void)
1799 {
1800         int err;
1801
1802         mlxsw_pci_dbg_root = debugfs_create_dir(mlxsw_pci_driver_name, NULL);
1803         if (!mlxsw_pci_dbg_root)
1804                 return -ENOMEM;
1805         err = pci_register_driver(&mlxsw_pci_driver);
1806         if (err)
1807                 goto err_register_driver;
1808         return 0;
1809
1810 err_register_driver:
1811         debugfs_remove_recursive(mlxsw_pci_dbg_root);
1812         return err;
1813 }
1814
1815 static void __exit mlxsw_pci_module_exit(void)
1816 {
1817         pci_unregister_driver(&mlxsw_pci_driver);
1818         debugfs_remove_recursive(mlxsw_pci_dbg_root);
1819 }
1820
1821 module_init(mlxsw_pci_module_init);
1822 module_exit(mlxsw_pci_module_exit);
1823
1824 MODULE_LICENSE("Dual BSD/GPL");
1825 MODULE_AUTHOR("Jiri Pirko <jiri@mellanox.com>");
1826 MODULE_DESCRIPTION("Mellanox switch PCI interface driver");
1827 MODULE_DEVICE_TABLE(pci, mlxsw_pci_id_table);