drivers/net/ethernet/mellanox/mlxsw/pci.c

   1 /*
   2  * drivers/net/ethernet/mellanox/mlxsw/pci.c
   3  * Copyright (c) 2015 Mellanox Technologies. All rights reserved.
   4  * Copyright (c) 2015 Jiri Pirko <jiri@mellanox.com>
   5  *
   6  * Redistribution and use in source and binary forms, with or without
   7  * modification, are permitted provided that the following conditions are met:
   8  *
   9  * 1. Redistributions of source code must retain the above copyright
  10  *    notice, this list of conditions and the following disclaimer.
  11  * 2. Redistributions in binary form must reproduce the above copyright
  12  *    notice, this list of conditions and the following disclaimer in the
  13  *    documentation and/or other materials provided with the distribution.
  14  * 3. Neither the names of the copyright holders nor the names of its
  15  *    contributors may be used to endorse or promote products derived from
  16  *    this software without specific prior written permission.
  17  *
  18  * Alternatively, this software may be distributed under the terms of the
  19  * GNU General Public License ("GPL") version 2 as published by the Free
  20  * Software Foundation.
  21  *
  22  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
  23  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
  24  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
  25  * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
  26  * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
  27  * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
  28  * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
  29  * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
  30  * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
  31  * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
  32  * POSSIBILITY OF SUCH DAMAGE.
  33  */
  34
  35 #include <linux/kernel.h>
  36 #include <linux/module.h>
  37 #include <linux/export.h>
  38 #include <linux/err.h>
  39 #include <linux/device.h>
  40 #include <linux/pci.h>
  41 #include <linux/interrupt.h>
  42 #include <linux/wait.h>
  43 #include <linux/types.h>
  44 #include <linux/skbuff.h>
  45 #include <linux/if_vlan.h>
  46 #include <linux/log2.h>
  47 #include <linux/debugfs.h>
  48 #include <linux/seq_file.h>
  49 #include <linux/string.h>
  50
  51 #include "pci_hw.h"
  52 #include "pci.h"
  53 #include "core.h"
  54 #include "cmd.h"
  55 #include "port.h"
  56 #include "resources.h"
  57
  58 static const char mlxsw_pci_driver_name[] = "mlxsw_pci";
  59
  60 static struct dentry *mlxsw_pci_dbg_root;
  61
  62 #define mlxsw_pci_write32(mlxsw_pci, reg, val) \
  63         iowrite32be(val, (mlxsw_pci)->hw_addr + (MLXSW_PCI_ ## reg))
  64 #define mlxsw_pci_read32(mlxsw_pci, reg) \
  65         ioread32be((mlxsw_pci)->hw_addr + (MLXSW_PCI_ ## reg))
  66
  67 enum mlxsw_pci_queue_type {
  68         MLXSW_PCI_QUEUE_TYPE_SDQ,
  69         MLXSW_PCI_QUEUE_TYPE_RDQ,
  70         MLXSW_PCI_QUEUE_TYPE_CQ,
  71         MLXSW_PCI_QUEUE_TYPE_EQ,
  72 };
  73
  74 static const char *mlxsw_pci_queue_type_str(enum mlxsw_pci_queue_type q_type)
  75 {
  76         switch (q_type) {
  77         case MLXSW_PCI_QUEUE_TYPE_SDQ:
  78                 return "sdq";
  79         case MLXSW_PCI_QUEUE_TYPE_RDQ:
  80                 return "rdq";
  81         case MLXSW_PCI_QUEUE_TYPE_CQ:
  82                 return "cq";
  83         case MLXSW_PCI_QUEUE_TYPE_EQ:
  84                 return "eq";
  85         }
  86         BUG();
  87 }
  88
  89 #define MLXSW_PCI_QUEUE_TYPE_COUNT      4
  90
  91 static const u16 mlxsw_pci_doorbell_type_offset[] = {
  92         MLXSW_PCI_DOORBELL_SDQ_OFFSET,  /* for type MLXSW_PCI_QUEUE_TYPE_SDQ */
  93         MLXSW_PCI_DOORBELL_RDQ_OFFSET,  /* for type MLXSW_PCI_QUEUE_TYPE_RDQ */
  94         MLXSW_PCI_DOORBELL_CQ_OFFSET,   /* for type MLXSW_PCI_QUEUE_TYPE_CQ */
  95         MLXSW_PCI_DOORBELL_EQ_OFFSET,   /* for type MLXSW_PCI_QUEUE_TYPE_EQ */
  96 };
  97
  98 static const u16 mlxsw_pci_doorbell_arm_type_offset[] = {
  99         0, /* unused */
 100         0, /* unused */
 101         MLXSW_PCI_DOORBELL_ARM_CQ_OFFSET, /* for type MLXSW_PCI_QUEUE_TYPE_CQ */
 102         MLXSW_PCI_DOORBELL_ARM_EQ_OFFSET, /* for type MLXSW_PCI_QUEUE_TYPE_EQ */
 103 };
 104
 105 struct mlxsw_pci_mem_item {
 106         char *buf;
 107         dma_addr_t mapaddr;
 108         size_t size;
 109 };
 110
 111 struct mlxsw_pci_queue_elem_info {
 112         char *elem; /* pointer to actual dma mapped element mem chunk */
 113         union {
 114                 struct {
 115                         struct sk_buff *skb;
 116                 } sdq;
 117                 struct {
 118                         struct sk_buff *skb;
 119                 } rdq;
 120         } u;
 121 };
 122
 123 struct mlxsw_pci_queue {
 124         spinlock_t lock; /* for queue accesses */
 125         struct mlxsw_pci_mem_item mem_item;
 126         struct mlxsw_pci_queue_elem_info *elem_info;
 127         u16 producer_counter;
 128         u16 consumer_counter;
 129         u16 count; /* number of elements in queue */
 130         u8 num; /* queue number */
 131         u8 elem_size; /* size of one element */
 132         enum mlxsw_pci_queue_type type;
 133         struct tasklet_struct tasklet; /* queue processing tasklet */
 134         struct mlxsw_pci *pci;
 135         union {
 136                 struct {
 137                         u32 comp_sdq_count;
 138                         u32 comp_rdq_count;
 139                 } cq;
 140                 struct {
 141                         u32 ev_cmd_count;
 142                         u32 ev_comp_count;
 143                         u32 ev_other_count;
 144                 } eq;
 145         } u;
 146 };
 147
 148 struct mlxsw_pci_queue_type_group {
 149         struct mlxsw_pci_queue *q;
 150         u8 count; /* number of queues in group */
 151 };
 152
 153 struct mlxsw_pci {
 154         struct pci_dev *pdev;
 155         u8 __iomem *hw_addr;
 156         struct mlxsw_pci_queue_type_group queues[MLXSW_PCI_QUEUE_TYPE_COUNT];
 157         u32 doorbell_offset;
 158         struct msix_entry msix_entry;
 159         struct mlxsw_core *core;
 160         struct {
 161                 struct mlxsw_pci_mem_item *items;
 162                 unsigned int count;
 163         } fw_area;
 164         struct {
 165                 struct mlxsw_pci_mem_item out_mbox;
 166                 struct mlxsw_pci_mem_item in_mbox;
 167                 struct mutex lock; /* Lock access to command registers */
 168                 bool nopoll;
 169                 wait_queue_head_t wait;
 170                 bool wait_done;
 171                 struct {
 172                         u8 status;
 173                         u64 out_param;
 174                 } comp;
 175         } cmd;
 176         struct mlxsw_bus_info bus_info;
 177         struct dentry *dbg_dir;
 178 };
 179
 180 static void mlxsw_pci_queue_tasklet_schedule(struct mlxsw_pci_queue *q)
 181 {
 182         tasklet_schedule(&q->tasklet);
 183 }
 184
 185 static char *__mlxsw_pci_queue_elem_get(struct mlxsw_pci_queue *q,
 186                                         size_t elem_size, int elem_index)
 187 {
 188         return q->mem_item.buf + (elem_size * elem_index);
 189 }
 190
 191 static struct mlxsw_pci_queue_elem_info *
 192 mlxsw_pci_queue_elem_info_get(struct mlxsw_pci_queue *q, int elem_index)
 193 {
 194         return &q->elem_info[elem_index];
 195 }
 196
 197 static struct mlxsw_pci_queue_elem_info *
 198 mlxsw_pci_queue_elem_info_producer_get(struct mlxsw_pci_queue *q)
 199 {
 200         int index = q->producer_counter & (q->count - 1);
 201
 202         if ((u16) (q->producer_counter - q->consumer_counter) == q->count)
 203                 return NULL;
 204         return mlxsw_pci_queue_elem_info_get(q, index);
 205 }
 206
 207 static struct mlxsw_pci_queue_elem_info *
 208 mlxsw_pci_queue_elem_info_consumer_get(struct mlxsw_pci_queue *q)
 209 {
 210         int index = q->consumer_counter & (q->count - 1);
 211
 212         return mlxsw_pci_queue_elem_info_get(q, index);
 213 }
 214
 215 static char *mlxsw_pci_queue_elem_get(struct mlxsw_pci_queue *q, int elem_index)
 216 {
 217         return mlxsw_pci_queue_elem_info_get(q, elem_index)->elem;
 218 }
 219
 220 static bool mlxsw_pci_elem_hw_owned(struct mlxsw_pci_queue *q, bool owner_bit)
 221 {
 222         return owner_bit != !!(q->consumer_counter & q->count);
 223 }
 224
 225 static char *
 226 mlxsw_pci_queue_sw_elem_get(struct mlxsw_pci_queue *q,
 227                             u32 (*get_elem_owner_func)(const char *))
 228 {
 229         struct mlxsw_pci_queue_elem_info *elem_info;
 230         char *elem;
 231         bool owner_bit;
 232
 233         elem_info = mlxsw_pci_queue_elem_info_consumer_get(q);
 234         elem = elem_info->elem;
 235         owner_bit = get_elem_owner_func(elem);
 236         if (mlxsw_pci_elem_hw_owned(q, owner_bit))
 237                 return NULL;
 238         q->consumer_counter++;
 239         rmb(); /* make sure we read owned bit before the rest of elem */
 240         return elem;
 241 }
 242
 243 static struct mlxsw_pci_queue_type_group *
 244 mlxsw_pci_queue_type_group_get(struct mlxsw_pci *mlxsw_pci,
 245                                enum mlxsw_pci_queue_type q_type)
 246 {
 247         return &mlxsw_pci->queues[q_type];
 248 }
 249
 250 static u8 __mlxsw_pci_queue_count(struct mlxsw_pci *mlxsw_pci,
 251                                   enum mlxsw_pci_queue_type q_type)
 252 {
 253         struct mlxsw_pci_queue_type_group *queue_group;
 254
 255         queue_group = mlxsw_pci_queue_type_group_get(mlxsw_pci, q_type);
 256         return queue_group->count;
 257 }
 258
 259 static u8 mlxsw_pci_sdq_count(struct mlxsw_pci *mlxsw_pci)
 260 {
 261         return __mlxsw_pci_queue_count(mlxsw_pci, MLXSW_PCI_QUEUE_TYPE_SDQ);
 262 }
 263
 264 static u8 mlxsw_pci_rdq_count(struct mlxsw_pci *mlxsw_pci)
 265 {
 266         return __mlxsw_pci_queue_count(mlxsw_pci, MLXSW_PCI_QUEUE_TYPE_RDQ);
 267 }
 268
 269 static u8 mlxsw_pci_cq_count(struct mlxsw_pci *mlxsw_pci)
 270 {
 271         return __mlxsw_pci_queue_count(mlxsw_pci, MLXSW_PCI_QUEUE_TYPE_CQ);
 272 }
 273
 274 static u8 mlxsw_pci_eq_count(struct mlxsw_pci *mlxsw_pci)
 275 {
 276         return __mlxsw_pci_queue_count(mlxsw_pci, MLXSW_PCI_QUEUE_TYPE_EQ);
 277 }
 278
 279 static struct mlxsw_pci_queue *
 280 __mlxsw_pci_queue_get(struct mlxsw_pci *mlxsw_pci,
 281                       enum mlxsw_pci_queue_type q_type, u8 q_num)
 282 {
 283         return &mlxsw_pci->queues[q_type].q[q_num];
 284 }
 285
 286 static struct mlxsw_pci_queue *mlxsw_pci_sdq_get(struct mlxsw_pci *mlxsw_pci,
 287                                                  u8 q_num)
 288 {
 289         return __mlxsw_pci_queue_get(mlxsw_pci,
 290                                      MLXSW_PCI_QUEUE_TYPE_SDQ, q_num);
 291 }
 292
 293 static struct mlxsw_pci_queue *mlxsw_pci_rdq_get(struct mlxsw_pci *mlxsw_pci,
 294                                                  u8 q_num)
 295 {
 296         return __mlxsw_pci_queue_get(mlxsw_pci,
 297                                      MLXSW_PCI_QUEUE_TYPE_RDQ, q_num);
 298 }
 299
 300 static struct mlxsw_pci_queue *mlxsw_pci_cq_get(struct mlxsw_pci *mlxsw_pci,
 301                                                 u8 q_num)
 302 {
 303         return __mlxsw_pci_queue_get(mlxsw_pci, MLXSW_PCI_QUEUE_TYPE_CQ, q_num);
 304 }
 305
 306 static struct mlxsw_pci_queue *mlxsw_pci_eq_get(struct mlxsw_pci *mlxsw_pci,
 307                                                 u8 q_num)
 308 {
 309         return __mlxsw_pci_queue_get(mlxsw_pci, MLXSW_PCI_QUEUE_TYPE_EQ, q_num);
 310 }
 311
 312 static void __mlxsw_pci_queue_doorbell_set(struct mlxsw_pci *mlxsw_pci,
 313                                            struct mlxsw_pci_queue *q,
 314                                            u16 val)
 315 {
 316         mlxsw_pci_write32(mlxsw_pci,
 317                           DOORBELL(mlxsw_pci->doorbell_offset,
 318                                    mlxsw_pci_doorbell_type_offset[q->type],
 319                                    q->num), val);
 320 }
 321
 322 static void __mlxsw_pci_queue_doorbell_arm_set(struct mlxsw_pci *mlxsw_pci,
 323                                                struct mlxsw_pci_queue *q,
 324                                                u16 val)
 325 {
 326         mlxsw_pci_write32(mlxsw_pci,
 327                           DOORBELL(mlxsw_pci->doorbell_offset,
 328                                    mlxsw_pci_doorbell_arm_type_offset[q->type],
 329                                    q->num), val);
 330 }
 331
 332 static void mlxsw_pci_queue_doorbell_producer_ring(struct mlxsw_pci *mlxsw_pci,
 333                                                    struct mlxsw_pci_queue *q)
 334 {
 335         wmb(); /* ensure all writes are done before we ring a bell */
 336         __mlxsw_pci_queue_doorbell_set(mlxsw_pci, q, q->producer_counter);
 337 }
 338
 339 static void mlxsw_pci_queue_doorbell_consumer_ring(struct mlxsw_pci *mlxsw_pci,
 340                                                    struct mlxsw_pci_queue *q)
 341 {
 342         wmb(); /* ensure all writes are done before we ring a bell */
 343         __mlxsw_pci_queue_doorbell_set(mlxsw_pci, q,
 344                                        q->consumer_counter + q->count);
 345 }
 346
 347 static void
 348 mlxsw_pci_queue_doorbell_arm_consumer_ring(struct mlxsw_pci *mlxsw_pci,
 349                                            struct mlxsw_pci_queue *q)
 350 {
 351         wmb(); /* ensure all writes are done before we ring a bell */
 352         __mlxsw_pci_queue_doorbell_arm_set(mlxsw_pci, q, q->consumer_counter);
 353 }
 354
 355 static dma_addr_t __mlxsw_pci_queue_page_get(struct mlxsw_pci_queue *q,
 356                                              int page_index)
 357 {
 358         return q->mem_item.mapaddr + MLXSW_PCI_PAGE_SIZE * page_index;
 359 }
 360
 361 static int mlxsw_pci_sdq_init(struct mlxsw_pci *mlxsw_pci, char *mbox,
 362                               struct mlxsw_pci_queue *q)
 363 {
 364         int i;
 365         int err;
 366
 367         q->producer_counter = 0;
 368         q->consumer_counter = 0;
 369
 370         /* Set CQ of same number of this SDQ. */
 371         mlxsw_cmd_mbox_sw2hw_dq_cq_set(mbox, q->num);
 372         mlxsw_cmd_mbox_sw2hw_dq_sdq_tclass_set(mbox, 3);
 373         mlxsw_cmd_mbox_sw2hw_dq_log2_dq_sz_set(mbox, 3); /* 8 pages */
 374         for (i = 0; i < MLXSW_PCI_AQ_PAGES; i++) {
 375                 dma_addr_t mapaddr = __mlxsw_pci_queue_page_get(q, i);
 376
 377                 mlxsw_cmd_mbox_sw2hw_dq_pa_set(mbox, i, mapaddr);
 378         }
 379
 380         err = mlxsw_cmd_sw2hw_sdq(mlxsw_pci->core, mbox, q->num);
 381         if (err)
 382                 return err;
 383         mlxsw_pci_queue_doorbell_producer_ring(mlxsw_pci, q);
 384         return 0;
 385 }
 386
 387 static void mlxsw_pci_sdq_fini(struct mlxsw_pci *mlxsw_pci,
 388                                struct mlxsw_pci_queue *q)
 389 {
 390         mlxsw_cmd_hw2sw_sdq(mlxsw_pci->core, q->num);
 391 }
 392
 393 static int mlxsw_pci_sdq_dbg_read(struct seq_file *file, void *data)
 394 {
 395         struct mlxsw_pci *mlxsw_pci = dev_get_drvdata(file->private);
 396         struct mlxsw_pci_queue *q;
 397         int i;
 398         static const char hdr[] =
 399                 "NUM PROD_COUNT CONS_COUNT COUNT\n";
 400
 401         seq_printf(file, hdr);
 402         for (i = 0; i < mlxsw_pci_sdq_count(mlxsw_pci); i++) {
 403                 q = mlxsw_pci_sdq_get(mlxsw_pci, i);
 404                 spin_lock_bh(&q->lock);
 405                 seq_printf(file, "%3d %10d %10d %5d\n",
 406                            i, q->producer_counter, q->consumer_counter,
 407                            q->count);
 408                 spin_unlock_bh(&q->lock);
 409         }
 410         return 0;
 411 }
 412
 413 static int mlxsw_pci_wqe_frag_map(struct mlxsw_pci *mlxsw_pci, char *wqe,
 414                                   int index, char *frag_data, size_t frag_len,
 415                                   int direction)
 416 {
 417         struct pci_dev *pdev = mlxsw_pci->pdev;
 418         dma_addr_t mapaddr;
 419
 420         mapaddr = pci_map_single(pdev, frag_data, frag_len, direction);
 421         if (unlikely(pci_dma_mapping_error(pdev, mapaddr))) {
 422                 dev_err_ratelimited(&pdev->dev, "failed to dma map tx frag\n");
 423                 return -EIO;
 424         }
 425         mlxsw_pci_wqe_address_set(wqe, index, mapaddr);
 426         mlxsw_pci_wqe_byte_count_set(wqe, index, frag_len);
 427         return 0;
 428 }
 429
 430 static void mlxsw_pci_wqe_frag_unmap(struct mlxsw_pci *mlxsw_pci, char *wqe,
 431                                      int index, int direction)
 432 {
 433         struct pci_dev *pdev = mlxsw_pci->pdev;
 434         size_t frag_len = mlxsw_pci_wqe_byte_count_get(wqe, index);
 435         dma_addr_t mapaddr = mlxsw_pci_wqe_address_get(wqe, index);
 436
 437         if (!frag_len)
 438                 return;
 439         pci_unmap_single(pdev, mapaddr, frag_len, direction);
 440 }
 441
 442 static int mlxsw_pci_rdq_skb_alloc(struct mlxsw_pci *mlxsw_pci,
 443                                    struct mlxsw_pci_queue_elem_info *elem_info)
 444 {
 445         size_t buf_len = MLXSW_PORT_MAX_MTU;
 446         char *wqe = elem_info->elem;
 447         struct sk_buff *skb;
 448         int err;
 449
 450         elem_info->u.rdq.skb = NULL;
 451         skb = netdev_alloc_skb_ip_align(NULL, buf_len);
 452         if (!skb)
 453                 return -ENOMEM;
 454
 455         /* Assume that wqe was previously zeroed. */
 456
 457         err = mlxsw_pci_wqe_frag_map(mlxsw_pci, wqe, 0, skb->data,
 458                                      buf_len, DMA_FROM_DEVICE);
 459         if (err)
 460                 goto err_frag_map;
 461
 462         elem_info->u.rdq.skb = skb;
 463         return 0;
 464
 465 err_frag_map:
 466         dev_kfree_skb_any(skb);
 467         return err;
 468 }
 469
 470 static void mlxsw_pci_rdq_skb_free(struct mlxsw_pci *mlxsw_pci,
 471                                    struct mlxsw_pci_queue_elem_info *elem_info)
 472 {
 473         struct sk_buff *skb;
 474         char *wqe;
 475
 476         skb = elem_info->u.rdq.skb;
 477         wqe = elem_info->elem;
 478
 479         mlxsw_pci_wqe_frag_unmap(mlxsw_pci, wqe, 0, DMA_FROM_DEVICE);
 480         dev_kfree_skb_any(skb);
 481 }
 482
 483 static int mlxsw_pci_rdq_init(struct mlxsw_pci *mlxsw_pci, char *mbox,
 484                               struct mlxsw_pci_queue *q)
 485 {
 486         struct mlxsw_pci_queue_elem_info *elem_info;
 487         u8 sdq_count = mlxsw_pci_sdq_count(mlxsw_pci);
 488         int i;
 489         int err;
 490
 491         q->producer_counter = 0;
 492         q->consumer_counter = 0;
 493
 494         /* Set CQ of same number of this RDQ with base
 495          * above SDQ count as the lower ones are assigned to SDQs.
 496          */
 497         mlxsw_cmd_mbox_sw2hw_dq_cq_set(mbox, sdq_count + q->num);
 498         mlxsw_cmd_mbox_sw2hw_dq_log2_dq_sz_set(mbox, 3); /* 8 pages */
 499         for (i = 0; i < MLXSW_PCI_AQ_PAGES; i++) {
 500                 dma_addr_t mapaddr = __mlxsw_pci_queue_page_get(q, i);
 501
 502                 mlxsw_cmd_mbox_sw2hw_dq_pa_set(mbox, i, mapaddr);
 503         }
 504
 505         err = mlxsw_cmd_sw2hw_rdq(mlxsw_pci->core, mbox, q->num);
 506         if (err)
 507                 return err;
 508
 509         mlxsw_pci_queue_doorbell_producer_ring(mlxsw_pci, q);
 510
 511         for (i = 0; i < q->count; i++) {
 512                 elem_info = mlxsw_pci_queue_elem_info_producer_get(q);
 513                 BUG_ON(!elem_info);
 514                 err = mlxsw_pci_rdq_skb_alloc(mlxsw_pci, elem_info);
 515                 if (err)
 516                         goto rollback;
 517                 /* Everything is set up, ring doorbell to pass elem to HW */
 518                 q->producer_counter++;
 519                 mlxsw_pci_queue_doorbell_producer_ring(mlxsw_pci, q);
 520         }
 521
 522         return 0;
 523
 524 rollback:
 525         for (i--; i >= 0; i--) {
 526                 elem_info = mlxsw_pci_queue_elem_info_get(q, i);
 527                 mlxsw_pci_rdq_skb_free(mlxsw_pci, elem_info);
 528         }
 529         mlxsw_cmd_hw2sw_rdq(mlxsw_pci->core, q->num);
 530
 531         return err;
 532 }
 533
 534 static void mlxsw_pci_rdq_fini(struct mlxsw_pci *mlxsw_pci,
 535                                struct mlxsw_pci_queue *q)
 536 {
 537         struct mlxsw_pci_queue_elem_info *elem_info;
 538         int i;
 539
 540         mlxsw_cmd_hw2sw_rdq(mlxsw_pci->core, q->num);
 541         for (i = 0; i < q->count; i++) {
 542                 elem_info = mlxsw_pci_queue_elem_info_get(q, i);
 543                 mlxsw_pci_rdq_skb_free(mlxsw_pci, elem_info);
 544         }
 545 }
 546
 547 static int mlxsw_pci_rdq_dbg_read(struct seq_file *file, void *data)
 548 {
 549         struct mlxsw_pci *mlxsw_pci = dev_get_drvdata(file->private);
 550         struct mlxsw_pci_queue *q;
 551         int i;
 552         static const char hdr[] =
 553                 "NUM PROD_COUNT CONS_COUNT COUNT\n";
 554
 555         seq_printf(file, hdr);
 556         for (i = 0; i < mlxsw_pci_rdq_count(mlxsw_pci); i++) {
 557                 q = mlxsw_pci_rdq_get(mlxsw_pci, i);
 558                 spin_lock_bh(&q->lock);
 559                 seq_printf(file, "%3d %10d %10d %5d\n",
 560                            i, q->producer_counter, q->consumer_counter,
 561                            q->count);
 562                 spin_unlock_bh(&q->lock);
 563         }
 564         return 0;
 565 }
 566
 567 static int mlxsw_pci_cq_init(struct mlxsw_pci *mlxsw_pci, char *mbox,
 568                              struct mlxsw_pci_queue *q)
 569 {
 570         int i;
 571         int err;
 572
 573         q->consumer_counter = 0;
 574
 575         for (i = 0; i < q->count; i++) {
 576                 char *elem = mlxsw_pci_queue_elem_get(q, i);
 577
 578                 mlxsw_pci_cqe_owner_set(elem, 1);
 579         }
 580
 581         mlxsw_cmd_mbox_sw2hw_cq_cv_set(mbox, 0); /* CQE ver 0 */
 582         mlxsw_cmd_mbox_sw2hw_cq_c_eqn_set(mbox, MLXSW_PCI_EQ_COMP_NUM);
 583         mlxsw_cmd_mbox_sw2hw_cq_st_set(mbox, 0);
 584         mlxsw_cmd_mbox_sw2hw_cq_log_cq_size_set(mbox, ilog2(q->count));
 585         for (i = 0; i < MLXSW_PCI_AQ_PAGES; i++) {
 586                 dma_addr_t mapaddr = __mlxsw_pci_queue_page_get(q, i);
 587
 588                 mlxsw_cmd_mbox_sw2hw_cq_pa_set(mbox, i, mapaddr);
 589         }
 590         err = mlxsw_cmd_sw2hw_cq(mlxsw_pci->core, mbox, q->num);
 591         if (err)
 592                 return err;
 593         mlxsw_pci_queue_doorbell_consumer_ring(mlxsw_pci, q);
 594         mlxsw_pci_queue_doorbell_arm_consumer_ring(mlxsw_pci, q);
 595         return 0;
 596 }
 597
 598 static void mlxsw_pci_cq_fini(struct mlxsw_pci *mlxsw_pci,
 599                               struct mlxsw_pci_queue *q)
 600 {
 601         mlxsw_cmd_hw2sw_cq(mlxsw_pci->core, q->num);
 602 }
 603
 604 static int mlxsw_pci_cq_dbg_read(struct seq_file *file, void *data)
 605 {
 606         struct mlxsw_pci *mlxsw_pci = dev_get_drvdata(file->private);
 607
 608         struct mlxsw_pci_queue *q;
 609         int i;
 610         static const char hdr[] =
 611                 "NUM CONS_INDEX  SDQ_COUNT  RDQ_COUNT COUNT\n";
 612
 613         seq_printf(file, hdr);
 614         for (i = 0; i < mlxsw_pci_cq_count(mlxsw_pci); i++) {
 615                 q = mlxsw_pci_cq_get(mlxsw_pci, i);
 616                 spin_lock_bh(&q->lock);
 617                 seq_printf(file, "%3d %10d %10d %10d %5d\n",
 618                            i, q->consumer_counter, q->u.cq.comp_sdq_count,
 619                            q->u.cq.comp_rdq_count, q->count);
 620                 spin_unlock_bh(&q->lock);
 621         }
 622         return 0;
 623 }
 624
 625 static void mlxsw_pci_cqe_sdq_handle(struct mlxsw_pci *mlxsw_pci,
 626                                      struct mlxsw_pci_queue *q,
 627                                      u16 consumer_counter_limit,
 628                                      char *cqe)
 629 {
 630         struct pci_dev *pdev = mlxsw_pci->pdev;
 631         struct mlxsw_pci_queue_elem_info *elem_info;
 632         char *wqe;
 633         struct sk_buff *skb;
 634         int i;
 635
 636         spin_lock(&q->lock);
 637         elem_info = mlxsw_pci_queue_elem_info_consumer_get(q);
 638         skb = elem_info->u.sdq.skb;
 639         wqe = elem_info->elem;
 640         for (i = 0; i < MLXSW_PCI_WQE_SG_ENTRIES; i++)
 641                 mlxsw_pci_wqe_frag_unmap(mlxsw_pci, wqe, i, DMA_TO_DEVICE);
 642         dev_kfree_skb_any(skb);
 643         elem_info->u.sdq.skb = NULL;
 644
 645         if (q->consumer_counter++ != consumer_counter_limit)
 646                 dev_dbg_ratelimited(&pdev->dev, "Consumer counter does not match limit in SDQ\n");
 647         spin_unlock(&q->lock);
 648 }
 649
 650 static void mlxsw_pci_cqe_rdq_handle(struct mlxsw_pci *mlxsw_pci,
 651                                      struct mlxsw_pci_queue *q,
 652                                      u16 consumer_counter_limit,
 653                                      char *cqe)
 654 {
 655         struct pci_dev *pdev = mlxsw_pci->pdev;
 656         struct mlxsw_pci_queue_elem_info *elem_info;
 657         char *wqe;
 658         struct sk_buff *skb;
 659         struct mlxsw_rx_info rx_info;
 660         u16 byte_count;
 661         int err;
 662
 663         elem_info = mlxsw_pci_queue_elem_info_consumer_get(q);
 664         skb = elem_info->u.sdq.skb;
 665         if (!skb)
 666                 return;
 667         wqe = elem_info->elem;
 668         mlxsw_pci_wqe_frag_unmap(mlxsw_pci, wqe, 0, DMA_FROM_DEVICE);
 669
 670         if (q->consumer_counter++ != consumer_counter_limit)
 671                 dev_dbg_ratelimited(&pdev->dev, "Consumer counter does not match limit in RDQ\n");
 672
 673         if (mlxsw_pci_cqe_lag_get(cqe)) {
 674                 rx_info.is_lag = true;
 675                 rx_info.u.lag_id = mlxsw_pci_cqe_lag_id_get(cqe);
 676                 rx_info.lag_port_index = mlxsw_pci_cqe_lag_port_index_get(cqe);
 677         } else {
 678                 rx_info.is_lag = false;
 679                 rx_info.u.sys_port = mlxsw_pci_cqe_system_port_get(cqe);
 680         }
 681
 682         rx_info.trap_id = mlxsw_pci_cqe_trap_id_get(cqe);
 683
 684         byte_count = mlxsw_pci_cqe_byte_count_get(cqe);
 685         if (mlxsw_pci_cqe_crc_get(cqe))
 686                 byte_count -= ETH_FCS_LEN;
 687         skb_put(skb, byte_count);
 688         mlxsw_core_skb_receive(mlxsw_pci->core, skb, &rx_info);
 689
 690         memset(wqe, 0, q->elem_size);
 691         err = mlxsw_pci_rdq_skb_alloc(mlxsw_pci, elem_info);
 692         if (err)
 693                 dev_dbg_ratelimited(&pdev->dev, "Failed to alloc skb for RDQ\n");
 694         /* Everything is set up, ring doorbell to pass elem to HW */
 695         q->producer_counter++;
 696         mlxsw_pci_queue_doorbell_producer_ring(mlxsw_pci, q);
 697         return;
 698 }
 699
 700 static char *mlxsw_pci_cq_sw_cqe_get(struct mlxsw_pci_queue *q)
 701 {
 702         return mlxsw_pci_queue_sw_elem_get(q, mlxsw_pci_cqe_owner_get);
 703 }
 704
 705 static void mlxsw_pci_cq_tasklet(unsigned long data)
 706 {
 707         struct mlxsw_pci_queue *q = (struct mlxsw_pci_queue *) data;
 708         struct mlxsw_pci *mlxsw_pci = q->pci;
 709         char *cqe;
 710         int items = 0;
 711         int credits = q->count >> 1;
 712
 713         while ((cqe = mlxsw_pci_cq_sw_cqe_get(q))) {
 714                 u16 wqe_counter = mlxsw_pci_cqe_wqe_counter_get(cqe);
 715                 u8 sendq = mlxsw_pci_cqe_sr_get(cqe);
 716                 u8 dqn = mlxsw_pci_cqe_dqn_get(cqe);
 717
 718                 if (sendq) {
 719                         struct mlxsw_pci_queue *sdq;
 720
 721                         sdq = mlxsw_pci_sdq_get(mlxsw_pci, dqn);
 722                         mlxsw_pci_cqe_sdq_handle(mlxsw_pci, sdq,
 723                                                  wqe_counter, cqe);
 724                         q->u.cq.comp_sdq_count++;
 725                 } else {
 726                         struct mlxsw_pci_queue *rdq;
 727
 728                         rdq = mlxsw_pci_rdq_get(mlxsw_pci, dqn);
 729                         mlxsw_pci_cqe_rdq_handle(mlxsw_pci, rdq,
 730                                                  wqe_counter, cqe);
 731                         q->u.cq.comp_rdq_count++;
 732                 }
 733                 if (++items == credits)
 734                         break;
 735         }
 736         if (items) {
 737                 mlxsw_pci_queue_doorbell_consumer_ring(mlxsw_pci, q);
 738                 mlxsw_pci_queue_doorbell_arm_consumer_ring(mlxsw_pci, q);
 739         }
 740 }
 741
 742 static int mlxsw_pci_eq_init(struct mlxsw_pci *mlxsw_pci, char *mbox,
 743                              struct mlxsw_pci_queue *q)
 744 {
 745         int i;
 746         int err;
 747
 748         q->consumer_counter = 0;
 749
 750         for (i = 0; i < q->count; i++) {
 751                 char *elem = mlxsw_pci_queue_elem_get(q, i);
 752
 753                 mlxsw_pci_eqe_owner_set(elem, 1);
 754         }
 755
 756         mlxsw_cmd_mbox_sw2hw_eq_int_msix_set(mbox, 1); /* MSI-X used */
 757         mlxsw_cmd_mbox_sw2hw_eq_st_set(mbox, 1); /* armed */
 758         mlxsw_cmd_mbox_sw2hw_eq_log_eq_size_set(mbox, ilog2(q->count));
 759         for (i = 0; i < MLXSW_PCI_AQ_PAGES; i++) {
 760                 dma_addr_t mapaddr = __mlxsw_pci_queue_page_get(q, i);
 761
 762                 mlxsw_cmd_mbox_sw2hw_eq_pa_set(mbox, i, mapaddr);
 763         }
 764         err = mlxsw_cmd_sw2hw_eq(mlxsw_pci->core, mbox, q->num);
 765         if (err)
 766                 return err;
 767         mlxsw_pci_queue_doorbell_consumer_ring(mlxsw_pci, q);
 768         mlxsw_pci_queue_doorbell_arm_consumer_ring(mlxsw_pci, q);
 769         return 0;
 770 }
 771
 772 static void mlxsw_pci_eq_fini(struct mlxsw_pci *mlxsw_pci,
 773                               struct mlxsw_pci_queue *q)
 774 {
 775         mlxsw_cmd_hw2sw_eq(mlxsw_pci->core, q->num);
 776 }
 777
 778 static int mlxsw_pci_eq_dbg_read(struct seq_file *file, void *data)
 779 {
 780         struct mlxsw_pci *mlxsw_pci = dev_get_drvdata(file->private);
 781         struct mlxsw_pci_queue *q;
 782         int i;
 783         static const char hdr[] =
 784                 "NUM CONS_COUNT     EV_CMD    EV_COMP   EV_OTHER COUNT\n";
 785
 786         seq_printf(file, hdr);
 787         for (i = 0; i < mlxsw_pci_eq_count(mlxsw_pci); i++) {
 788                 q = mlxsw_pci_eq_get(mlxsw_pci, i);
 789                 spin_lock_bh(&q->lock);
 790                 seq_printf(file, "%3d %10d %10d %10d %10d %5d\n",
 791                            i, q->consumer_counter, q->u.eq.ev_cmd_count,
 792                            q->u.eq.ev_comp_count, q->u.eq.ev_other_count,
 793                            q->count);
 794                 spin_unlock_bh(&q->lock);
 795         }
 796         return 0;
 797 }
 798
 799 static void mlxsw_pci_eq_cmd_event(struct mlxsw_pci *mlxsw_pci, char *eqe)
 800 {
 801         mlxsw_pci->cmd.comp.status = mlxsw_pci_eqe_cmd_status_get(eqe);
 802         mlxsw_pci->cmd.comp.out_param =
 803                 ((u64) mlxsw_pci_eqe_cmd_out_param_h_get(eqe)) << 32 |
 804                 mlxsw_pci_eqe_cmd_out_param_l_get(eqe);
 805         mlxsw_pci->cmd.wait_done = true;
 806         wake_up(&mlxsw_pci->cmd.wait);
 807 }
 808
 809 static char *mlxsw_pci_eq_sw_eqe_get(struct mlxsw_pci_queue *q)
 810 {
 811         return mlxsw_pci_queue_sw_elem_get(q, mlxsw_pci_eqe_owner_get);
 812 }
 813
 814 static void mlxsw_pci_eq_tasklet(unsigned long data)
 815 {
 816         struct mlxsw_pci_queue *q = (struct mlxsw_pci_queue *) data;
 817         struct mlxsw_pci *mlxsw_pci = q->pci;
 818         u8 cq_count = mlxsw_pci_cq_count(mlxsw_pci);
 819         unsigned long active_cqns[BITS_TO_LONGS(MLXSW_PCI_CQS_MAX)];
 820         char *eqe;
 821         u8 cqn;
 822         bool cq_handle = false;
 823         int items = 0;
 824         int credits = q->count >> 1;
 825
 826         memset(&active_cqns, 0, sizeof(active_cqns));
 827
 828         while ((eqe = mlxsw_pci_eq_sw_eqe_get(q))) {
 829                 u8 event_type = mlxsw_pci_eqe_event_type_get(eqe);
 830
 831                 switch (event_type) {
 832                 case MLXSW_PCI_EQE_EVENT_TYPE_CMD:
 833                         mlxsw_pci_eq_cmd_event(mlxsw_pci, eqe);
 834                         q->u.eq.ev_cmd_count++;
 835                         break;
 836                 case MLXSW_PCI_EQE_EVENT_TYPE_COMP:
 837                         cqn = mlxsw_pci_eqe_cqn_get(eqe);
 838                         set_bit(cqn, active_cqns);
 839                         cq_handle = true;
 840                         q->u.eq.ev_comp_count++;
 841                         break;
 842                 default:
 843                         q->u.eq.ev_other_count++;
 844                 }
 845                 if (++items == credits)
 846                         break;
 847         }
 848         if (items) {
 849                 mlxsw_pci_queue_doorbell_consumer_ring(mlxsw_pci, q);
 850                 mlxsw_pci_queue_doorbell_arm_consumer_ring(mlxsw_pci, q);
 851         }
 852
 853         if (!cq_handle)
 854                 return;
 855         for_each_set_bit(cqn, active_cqns, cq_count) {
 856                 q = mlxsw_pci_cq_get(mlxsw_pci, cqn);
 857                 mlxsw_pci_queue_tasklet_schedule(q);
 858         }
 859 }
 860
 861 struct mlxsw_pci_queue_ops {
 862         const char *name;
 863         enum mlxsw_pci_queue_type type;
 864         int (*init)(struct mlxsw_pci *mlxsw_pci, char *mbox,
 865                     struct mlxsw_pci_queue *q);
 866         void (*fini)(struct mlxsw_pci *mlxsw_pci,
 867                      struct mlxsw_pci_queue *q);
 868         void (*tasklet)(unsigned long data);
 869         int (*dbg_read)(struct seq_file *s, void *data);
 870         u16 elem_count;
 871         u8 elem_size;
 872 };
 873
 874 static const struct mlxsw_pci_queue_ops mlxsw_pci_sdq_ops = {
 875         .type           = MLXSW_PCI_QUEUE_TYPE_SDQ,
 876         .init           = mlxsw_pci_sdq_init,
 877         .fini           = mlxsw_pci_sdq_fini,
 878         .dbg_read       = mlxsw_pci_sdq_dbg_read,
 879         .elem_count     = MLXSW_PCI_WQE_COUNT,
 880         .elem_size      = MLXSW_PCI_WQE_SIZE,
 881 };
 882
 883 static const struct mlxsw_pci_queue_ops mlxsw_pci_rdq_ops = {
 884         .type           = MLXSW_PCI_QUEUE_TYPE_RDQ,
 885         .init           = mlxsw_pci_rdq_init,
 886         .fini           = mlxsw_pci_rdq_fini,
 887         .dbg_read       = mlxsw_pci_rdq_dbg_read,
 888         .elem_count     = MLXSW_PCI_WQE_COUNT,
 889         .elem_size      = MLXSW_PCI_WQE_SIZE
 890 };
 891
 892 static const struct mlxsw_pci_queue_ops mlxsw_pci_cq_ops = {
 893         .type           = MLXSW_PCI_QUEUE_TYPE_CQ,
 894         .init           = mlxsw_pci_cq_init,
 895         .fini           = mlxsw_pci_cq_fini,
 896         .tasklet        = mlxsw_pci_cq_tasklet,
 897         .dbg_read       = mlxsw_pci_cq_dbg_read,
 898         .elem_count     = MLXSW_PCI_CQE_COUNT,
 899         .elem_size      = MLXSW_PCI_CQE_SIZE
 900 };
 901
 902 static const struct mlxsw_pci_queue_ops mlxsw_pci_eq_ops = {
 903         .type           = MLXSW_PCI_QUEUE_TYPE_EQ,
 904         .init           = mlxsw_pci_eq_init,
 905         .fini           = mlxsw_pci_eq_fini,
 906         .tasklet        = mlxsw_pci_eq_tasklet,
 907         .dbg_read       = mlxsw_pci_eq_dbg_read,
 908         .elem_count     = MLXSW_PCI_EQE_COUNT,
 909         .elem_size      = MLXSW_PCI_EQE_SIZE
 910 };
 911
 912 static int mlxsw_pci_queue_init(struct mlxsw_pci *mlxsw_pci, char *mbox,
 913                                 const struct mlxsw_pci_queue_ops *q_ops,
 914                                 struct mlxsw_pci_queue *q, u8 q_num)
 915 {
 916         struct mlxsw_pci_mem_item *mem_item = &q->mem_item;
 917         int i;
 918         int err;
 919
 920         spin_lock_init(&q->lock);
 921         q->num = q_num;
 922         q->count = q_ops->elem_count;
 923         q->elem_size = q_ops->elem_size;
 924         q->type = q_ops->type;
 925         q->pci = mlxsw_pci;
 926
 927         if (q_ops->tasklet)
 928                 tasklet_init(&q->tasklet, q_ops->tasklet, (unsigned long) q);
 929
 930         mem_item->size = MLXSW_PCI_AQ_SIZE;
 931         mem_item->buf = pci_alloc_consistent(mlxsw_pci->pdev,
 932                                              mem_item->size,
 933                                              &mem_item->mapaddr);
 934         if (!mem_item->buf)
 935                 return -ENOMEM;
 936         memset(mem_item->buf, 0, mem_item->size);
 937
 938         q->elem_info = kcalloc(q->count, sizeof(*q->elem_info), GFP_KERNEL);
 939         if (!q->elem_info) {
 940                 err = -ENOMEM;
 941                 goto err_elem_info_alloc;
 942         }
 943
 944         /* Initialize dma mapped elements info elem_info for
 945          * future easy access.
 946          */
 947         for (i = 0; i < q->count; i++) {
 948                 struct mlxsw_pci_queue_elem_info *elem_info;
 949
 950                 elem_info = mlxsw_pci_queue_elem_info_get(q, i);
 951                 elem_info->elem =
 952                         __mlxsw_pci_queue_elem_get(q, q_ops->elem_size, i);
 953         }
 954
 955         mlxsw_cmd_mbox_zero(mbox);
 956         err = q_ops->init(mlxsw_pci, mbox, q);
 957         if (err)
 958                 goto err_q_ops_init;
 959         return 0;
 960
 961 err_q_ops_init:
 962         kfree(q->elem_info);
 963 err_elem_info_alloc:
 964         pci_free_consistent(mlxsw_pci->pdev, mem_item->size,
 965                             mem_item->buf, mem_item->mapaddr);
 966         return err;
 967 }
 968
 969 static void mlxsw_pci_queue_fini(struct mlxsw_pci *mlxsw_pci,
 970                                  const struct mlxsw_pci_queue_ops *q_ops,
 971                                  struct mlxsw_pci_queue *q)
 972 {
 973         struct mlxsw_pci_mem_item *mem_item = &q->mem_item;
 974
 975         q_ops->fini(mlxsw_pci, q);
 976         kfree(q->elem_info);
 977         pci_free_consistent(mlxsw_pci->pdev, mem_item->size,
 978                             mem_item->buf, mem_item->mapaddr);
 979 }
 980
 981 static int mlxsw_pci_queue_group_init(struct mlxsw_pci *mlxsw_pci, char *mbox,
 982                                       const struct mlxsw_pci_queue_ops *q_ops,
 983                                       u8 num_qs)
 984 {
 985         struct pci_dev *pdev = mlxsw_pci->pdev;
 986         struct mlxsw_pci_queue_type_group *queue_group;
 987         char tmp[16];
 988         int i;
 989         int err;
 990
 991         queue_group = mlxsw_pci_queue_type_group_get(mlxsw_pci, q_ops->type);
 992         queue_group->q = kcalloc(num_qs, sizeof(*queue_group->q), GFP_KERNEL);
 993         if (!queue_group->q)
 994                 return -ENOMEM;
 995
 996         for (i = 0; i < num_qs; i++) {
 997                 err = mlxsw_pci_queue_init(mlxsw_pci, mbox, q_ops,
 998                                            &queue_group->q[i], i);
 999                 if (err)
1000                         goto err_queue_init;
1001         }
1002         queue_group->count = num_qs;
1003
1004         sprintf(tmp, "%s_stats", mlxsw_pci_queue_type_str(q_ops->type));
1005         debugfs_create_devm_seqfile(&pdev->dev, tmp, mlxsw_pci->dbg_dir,
1006                                     q_ops->dbg_read);
1007
1008         return 0;
1009
1010 err_queue_init:
1011         for (i--; i >= 0; i--)
1012                 mlxsw_pci_queue_fini(mlxsw_pci, q_ops, &queue_group->q[i]);
1013         kfree(queue_group->q);
1014         return err;
1015 }
1016
1017 static void mlxsw_pci_queue_group_fini(struct mlxsw_pci *mlxsw_pci,
1018                                        const struct mlxsw_pci_queue_ops *q_ops)
1019 {
1020         struct mlxsw_pci_queue_type_group *queue_group;
1021         int i;
1022
1023         queue_group = mlxsw_pci_queue_type_group_get(mlxsw_pci, q_ops->type);
1024         for (i = 0; i < queue_group->count; i++)
1025                 mlxsw_pci_queue_fini(mlxsw_pci, q_ops, &queue_group->q[i]);
1026         kfree(queue_group->q);
1027 }
1028
1029 static int mlxsw_pci_aqs_init(struct mlxsw_pci *mlxsw_pci, char *mbox)
1030 {
1031         struct pci_dev *pdev = mlxsw_pci->pdev;
1032         u8 num_sdqs;
1033         u8 sdq_log2sz;
1034         u8 num_rdqs;
1035         u8 rdq_log2sz;
1036         u8 num_cqs;
1037         u8 cq_log2sz;
1038         u8 num_eqs;
1039         u8 eq_log2sz;
1040         int err;
1041
1042         mlxsw_cmd_mbox_zero(mbox);
1043         err = mlxsw_cmd_query_aq_cap(mlxsw_pci->core, mbox);
1044         if (err)
1045                 return err;
1046
1047         num_sdqs = mlxsw_cmd_mbox_query_aq_cap_max_num_sdqs_get(mbox);
1048         sdq_log2sz = mlxsw_cmd_mbox_query_aq_cap_log_max_sdq_sz_get(mbox);
1049         num_rdqs = mlxsw_cmd_mbox_query_aq_cap_max_num_rdqs_get(mbox);
1050         rdq_log2sz = mlxsw_cmd_mbox_query_aq_cap_log_max_rdq_sz_get(mbox);
1051         num_cqs = mlxsw_cmd_mbox_query_aq_cap_max_num_cqs_get(mbox);
1052         cq_log2sz = mlxsw_cmd_mbox_query_aq_cap_log_max_cq_sz_get(mbox);
1053         num_eqs = mlxsw_cmd_mbox_query_aq_cap_max_num_eqs_get(mbox);
1054         eq_log2sz = mlxsw_cmd_mbox_query_aq_cap_log_max_eq_sz_get(mbox);
1055
1056         if (num_sdqs + num_rdqs > num_cqs ||
1057             num_cqs > MLXSW_PCI_CQS_MAX || num_eqs != MLXSW_PCI_EQS_COUNT) {
1058                 dev_err(&pdev->dev, "Unsupported number of queues\n");
1059                 return -EINVAL;
1060         }
1061
1062         if ((1 << sdq_log2sz != MLXSW_PCI_WQE_COUNT) ||
1063             (1 << rdq_log2sz != MLXSW_PCI_WQE_COUNT) ||
1064             (1 << cq_log2sz != MLXSW_PCI_CQE_COUNT) ||
1065             (1 << eq_log2sz != MLXSW_PCI_EQE_COUNT)) {
1066                 dev_err(&pdev->dev, "Unsupported number of async queue descriptors\n");
1067                 return -EINVAL;
1068         }
1069
1070         err = mlxsw_pci_queue_group_init(mlxsw_pci, mbox, &mlxsw_pci_eq_ops,
1071                                          num_eqs);
1072         if (err) {
1073                 dev_err(&pdev->dev, "Failed to initialize event queues\n");
1074                 return err;
1075         }
1076
1077         err = mlxsw_pci_queue_group_init(mlxsw_pci, mbox, &mlxsw_pci_cq_ops,
1078                                          num_cqs);
1079         if (err) {
1080                 dev_err(&pdev->dev, "Failed to initialize completion queues\n");
1081                 goto err_cqs_init;
1082         }
1083
1084         err = mlxsw_pci_queue_group_init(mlxsw_pci, mbox, &mlxsw_pci_sdq_ops,
1085                                          num_sdqs);
1086         if (err) {
1087                 dev_err(&pdev->dev, "Failed to initialize send descriptor queues\n");
1088                 goto err_sdqs_init;
1089         }
1090
1091         err = mlxsw_pci_queue_group_init(mlxsw_pci, mbox, &mlxsw_pci_rdq_ops,
1092                                          num_rdqs);
1093         if (err) {
1094                 dev_err(&pdev->dev, "Failed to initialize receive descriptor queues\n");
1095                 goto err_rdqs_init;
1096         }
1097
1098         /* We have to poll in command interface until queues are initialized */
1099         mlxsw_pci->cmd.nopoll = true;
1100         return 0;
1101
1102 err_rdqs_init:
1103         mlxsw_pci_queue_group_fini(mlxsw_pci, &mlxsw_pci_sdq_ops);
1104 err_sdqs_init:
1105         mlxsw_pci_queue_group_fini(mlxsw_pci, &mlxsw_pci_cq_ops);
1106 err_cqs_init:
1107         mlxsw_pci_queue_group_fini(mlxsw_pci, &mlxsw_pci_eq_ops);
1108         return err;
1109 }
1110
1111 static void mlxsw_pci_aqs_fini(struct mlxsw_pci *mlxsw_pci)
1112 {
1113         mlxsw_pci->cmd.nopoll = false;
1114         mlxsw_pci_queue_group_fini(mlxsw_pci, &mlxsw_pci_rdq_ops);
1115         mlxsw_pci_queue_group_fini(mlxsw_pci, &mlxsw_pci_sdq_ops);
1116         mlxsw_pci_queue_group_fini(mlxsw_pci, &mlxsw_pci_cq_ops);
1117         mlxsw_pci_queue_group_fini(mlxsw_pci, &mlxsw_pci_eq_ops);
1118 }
1119
1120 static void
1121 mlxsw_pci_config_profile_swid_config(struct mlxsw_pci *mlxsw_pci,
1122                                      char *mbox, int index,
1123                                      const struct mlxsw_swid_config *swid)
1124 {
1125         u8 mask = 0;
1126
1127         if (swid->used_type) {
1128                 mlxsw_cmd_mbox_config_profile_swid_config_type_set(
1129                         mbox, index, swid->type);
1130                 mask |= 1;
1131         }
1132         if (swid->used_properties) {
1133                 mlxsw_cmd_mbox_config_profile_swid_config_properties_set(
1134                         mbox, index, swid->properties);
1135                 mask |= 2;
1136         }
1137         mlxsw_cmd_mbox_config_profile_swid_config_mask_set(mbox, index, mask);
1138 }
1139
1140 static int mlxsw_pci_resources_query(struct mlxsw_pci *mlxsw_pci, char *mbox,
1141                                      struct mlxsw_res *res,
1142                                      u8 query_enabled)
1143 {
1144         int index, i;
1145         u64 data;
1146         u16 id;
1147         int err;
1148
1149         /* Not all the versions support resources query */
1150         if (!query_enabled)
1151                 return 0;
1152
1153         mlxsw_cmd_mbox_zero(mbox);
1154
1155         for (index = 0; index < MLXSW_CMD_QUERY_RESOURCES_MAX_QUERIES;
1156              index++) {
1157                 err = mlxsw_cmd_query_resources(mlxsw_pci->core, mbox, index);
1158                 if (err)
1159                         return err;
1160
1161                 for (i = 0; i < MLXSW_CMD_QUERY_RESOURCES_PER_QUERY; i++) {
1162                         id = mlxsw_cmd_mbox_query_resource_id_get(mbox, i);
1163                         data = mlxsw_cmd_mbox_query_resource_data_get(mbox, i);
1164
1165                         if (id == MLXSW_CMD_QUERY_RESOURCES_TABLE_END_ID)
1166                                 return 0;
1167
1168                         mlxsw_res_parse(res, id, data);
1169                 }
1170         }
1171
1172         /* If after MLXSW_RESOURCES_QUERY_MAX_QUERIES we still didn't get
1173          * MLXSW_RESOURCES_TABLE_END_ID, something went bad in the FW.
1174          */
1175         return -EIO;
1176 }
1177
1178 static int
1179 mlxsw_pci_profile_get_kvd_sizes(const struct mlxsw_config_profile *profile,
1180                                 struct mlxsw_res *res)
1181 {
1182         u32 single_size, double_size, linear_size;
1183
1184         if (!MLXSW_RES_VALID(res, KVD_SINGLE_MIN_SIZE) ||
1185             !MLXSW_RES_VALID(res, KVD_DOUBLE_MIN_SIZE) ||
1186             !profile->used_kvd_split_data)
1187                 return -EIO;
1188
1189         linear_size = profile->kvd_linear_size;
1190
1191         /* The hash part is what left of the kvd without the
1192          * linear part. It is split to the single size and
1193          * double size by the parts ratio from the profile.
1194          * Both sizes must be a multiplications of the
1195          * granularity from the profile.
1196          */
1197         double_size = MLXSW_RES_GET(res, KVD_SIZE) - linear_size;
1198         double_size *= profile->kvd_hash_double_parts;
1199         double_size /= profile->kvd_hash_double_parts +
1200                        profile->kvd_hash_single_parts;
1201         double_size /= profile->kvd_hash_granularity;
1202         double_size *= profile->kvd_hash_granularity;
1203         single_size = MLXSW_RES_GET(res, KVD_SIZE) - double_size -
1204                       linear_size;
1205
1206         /* Check results are legal. */
1207         if (single_size < MLXSW_RES_GET(res, KVD_SINGLE_MIN_SIZE) ||
1208             double_size < MLXSW_RES_GET(res, KVD_DOUBLE_MIN_SIZE) ||
1209             MLXSW_RES_GET(res, KVD_SIZE) < linear_size)
1210                 return -EIO;
1211
1212         MLXSW_RES_SET(res, KVD_SINGLE_SIZE, single_size);
1213         MLXSW_RES_SET(res, KVD_DOUBLE_SIZE, double_size);
1214         MLXSW_RES_SET(res, KVD_LINEAR_SIZE, linear_size);
1215
1216         return 0;
1217 }
1218
1219 static int mlxsw_pci_config_profile(struct mlxsw_pci *mlxsw_pci, char *mbox,
1220                                     const struct mlxsw_config_profile *profile,
1221                                     struct mlxsw_res *res)
1222 {
1223         int i;
1224         int err;
1225
1226         mlxsw_cmd_mbox_zero(mbox);
1227
1228         if (profile->used_max_vepa_channels) {
1229                 mlxsw_cmd_mbox_config_profile_set_max_vepa_channels_set(
1230                         mbox, 1);
1231                 mlxsw_cmd_mbox_config_profile_max_vepa_channels_set(
1232                         mbox, profile->max_vepa_channels);
1233         }
1234         if (profile->used_max_mid) {
1235                 mlxsw_cmd_mbox_config_profile_set_max_mid_set(
1236                         mbox, 1);
1237                 mlxsw_cmd_mbox_config_profile_max_mid_set(
1238                         mbox, profile->max_mid);
1239         }
1240         if (profile->used_max_pgt) {
1241                 mlxsw_cmd_mbox_config_profile_set_max_pgt_set(
1242                         mbox, 1);
1243                 mlxsw_cmd_mbox_config_profile_max_pgt_set(
1244                         mbox, profile->max_pgt);
1245         }
1246         if (profile->used_max_system_port) {
1247                 mlxsw_cmd_mbox_config_profile_set_max_system_port_set(
1248                         mbox, 1);
1249                 mlxsw_cmd_mbox_config_profile_max_system_port_set(
1250                         mbox, profile->max_system_port);
1251         }
1252         if (profile->used_max_vlan_groups) {
1253                 mlxsw_cmd_mbox_config_profile_set_max_vlan_groups_set(
1254                         mbox, 1);
1255                 mlxsw_cmd_mbox_config_profile_max_vlan_groups_set(
1256                         mbox, profile->max_vlan_groups);
1257         }
1258         if (profile->used_max_regions) {
1259                 mlxsw_cmd_mbox_config_profile_set_max_regions_set(
1260                         mbox, 1);
1261                 mlxsw_cmd_mbox_config_profile_max_regions_set(
1262                         mbox, profile->max_regions);
1263         }
1264         if (profile->used_flood_tables) {
1265                 mlxsw_cmd_mbox_config_profile_set_flood_tables_set(
1266                         mbox, 1);
1267                 mlxsw_cmd_mbox_config_profile_max_flood_tables_set(
1268                         mbox, profile->max_flood_tables);
1269                 mlxsw_cmd_mbox_config_profile_max_vid_flood_tables_set(
1270                         mbox, profile->max_vid_flood_tables);
1271                 mlxsw_cmd_mbox_config_profile_max_fid_offset_flood_tables_set(
1272                         mbox, profile->max_fid_offset_flood_tables);
1273                 mlxsw_cmd_mbox_config_profile_fid_offset_flood_table_size_set(
1274                         mbox, profile->fid_offset_flood_table_size);
1275                 mlxsw_cmd_mbox_config_profile_max_fid_flood_tables_set(
1276                         mbox, profile->max_fid_flood_tables);
1277                 mlxsw_cmd_mbox_config_profile_fid_flood_table_size_set(
1278                         mbox, profile->fid_flood_table_size);
1279         }
1280         if (profile->used_flood_mode) {
1281                 mlxsw_cmd_mbox_config_profile_set_flood_mode_set(
1282                         mbox, 1);
1283                 mlxsw_cmd_mbox_config_profile_flood_mode_set(
1284                         mbox, profile->flood_mode);
1285         }
1286         if (profile->used_max_ib_mc) {
1287                 mlxsw_cmd_mbox_config_profile_set_max_ib_mc_set(
1288                         mbox, 1);
1289                 mlxsw_cmd_mbox_config_profile_max_ib_mc_set(
1290                         mbox, profile->max_ib_mc);
1291         }
1292         if (profile->used_max_pkey) {
1293                 mlxsw_cmd_mbox_config_profile_set_max_pkey_set(
1294                         mbox, 1);
1295                 mlxsw_cmd_mbox_config_profile_max_pkey_set(
1296                         mbox, profile->max_pkey);
1297         }
1298         if (profile->used_ar_sec) {
1299                 mlxsw_cmd_mbox_config_profile_set_ar_sec_set(
1300                         mbox, 1);
1301                 mlxsw_cmd_mbox_config_profile_ar_sec_set(
1302                         mbox, profile->ar_sec);
1303         }
1304         if (profile->used_adaptive_routing_group_cap) {
1305                 mlxsw_cmd_mbox_config_profile_set_adaptive_routing_group_cap_set(
1306                         mbox, 1);
1307                 mlxsw_cmd_mbox_config_profile_adaptive_routing_group_cap_set(
1308                         mbox, profile->adaptive_routing_group_cap);
1309         }
1310         if (MLXSW_RES_VALID(res, KVD_SIZE)) {
1311                 err = mlxsw_pci_profile_get_kvd_sizes(profile, res);
1312                 if (err)
1313                         return err;
1314
1315                 mlxsw_cmd_mbox_config_profile_set_kvd_linear_size_set(mbox, 1);
1316                 mlxsw_cmd_mbox_config_profile_kvd_linear_size_set(mbox,
1317                                         MLXSW_RES_GET(res, KVD_LINEAR_SIZE));
1318                 mlxsw_cmd_mbox_config_profile_set_kvd_hash_single_size_set(mbox,
1319                                                                            1);
1320                 mlxsw_cmd_mbox_config_profile_kvd_hash_single_size_set(mbox,
1321                                         MLXSW_RES_GET(res, KVD_SINGLE_SIZE));
1322                 mlxsw_cmd_mbox_config_profile_set_kvd_hash_double_size_set(
1323                                                                 mbox, 1);
1324                 mlxsw_cmd_mbox_config_profile_kvd_hash_double_size_set(mbox,
1325                                         MLXSW_RES_GET(res, KVD_DOUBLE_SIZE));
1326         }
1327
1328         for (i = 0; i < MLXSW_CONFIG_PROFILE_SWID_COUNT; i++)
1329                 mlxsw_pci_config_profile_swid_config(mlxsw_pci, mbox, i,
1330                                                      &profile->swid_config[i]);
1331
1332         return mlxsw_cmd_config_profile_set(mlxsw_pci->core, mbox);
1333 }
1334
1335 static int mlxsw_pci_boardinfo(struct mlxsw_pci *mlxsw_pci, char *mbox)
1336 {
1337         struct mlxsw_bus_info *bus_info = &mlxsw_pci->bus_info;
1338         int err;
1339
1340         mlxsw_cmd_mbox_zero(mbox);
1341         err = mlxsw_cmd_boardinfo(mlxsw_pci->core, mbox);
1342         if (err)
1343                 return err;
1344         mlxsw_cmd_mbox_boardinfo_vsd_memcpy_from(mbox, bus_info->vsd);
1345         mlxsw_cmd_mbox_boardinfo_psid_memcpy_from(mbox, bus_info->psid);
1346         return 0;
1347 }
1348
1349 static int mlxsw_pci_fw_area_init(struct mlxsw_pci *mlxsw_pci, char *mbox,
1350                                   u16 num_pages)
1351 {
1352         struct mlxsw_pci_mem_item *mem_item;
1353         int nent = 0;
1354         int i;
1355         int err;
1356
1357         mlxsw_pci->fw_area.items = kcalloc(num_pages, sizeof(*mem_item),
1358                                            GFP_KERNEL);
1359         if (!mlxsw_pci->fw_area.items)
1360                 return -ENOMEM;
1361         mlxsw_pci->fw_area.count = num_pages;
1362
1363         mlxsw_cmd_mbox_zero(mbox);
1364         for (i = 0; i < num_pages; i++) {
1365                 mem_item = &mlxsw_pci->fw_area.items[i];
1366
1367                 mem_item->size = MLXSW_PCI_PAGE_SIZE;
1368                 mem_item->buf = pci_alloc_consistent(mlxsw_pci->pdev,
1369                                                      mem_item->size,
1370                                                      &mem_item->mapaddr);
1371                 if (!mem_item->buf) {
1372                         err = -ENOMEM;
1373                         goto err_alloc;
1374                 }
1375                 mlxsw_cmd_mbox_map_fa_pa_set(mbox, nent, mem_item->mapaddr);
1376                 mlxsw_cmd_mbox_map_fa_log2size_set(mbox, nent, 0); /* 1 page */
1377                 if (++nent == MLXSW_CMD_MAP_FA_VPM_ENTRIES_MAX) {
1378                         err = mlxsw_cmd_map_fa(mlxsw_pci->core, mbox, nent);
1379                         if (err)
1380                                 goto err_cmd_map_fa;
1381                         nent = 0;
1382                         mlxsw_cmd_mbox_zero(mbox);
1383                 }
1384         }
1385
1386         if (nent) {
1387                 err = mlxsw_cmd_map_fa(mlxsw_pci->core, mbox, nent);
1388                 if (err)
1389                         goto err_cmd_map_fa;
1390         }
1391
1392         return 0;
1393
1394 err_cmd_map_fa:
1395 err_alloc:
1396         for (i--; i >= 0; i--) {
1397                 mem_item = &mlxsw_pci->fw_area.items[i];
1398
1399                 pci_free_consistent(mlxsw_pci->pdev, mem_item->size,
1400                                     mem_item->buf, mem_item->mapaddr);
1401         }
1402         kfree(mlxsw_pci->fw_area.items);
1403         return err;
1404 }
1405
1406 static void mlxsw_pci_fw_area_fini(struct mlxsw_pci *mlxsw_pci)
1407 {
1408         struct mlxsw_pci_mem_item *mem_item;
1409         int i;
1410
1411         mlxsw_cmd_unmap_fa(mlxsw_pci->core);
1412
1413         for (i = 0; i < mlxsw_pci->fw_area.count; i++) {
1414                 mem_item = &mlxsw_pci->fw_area.items[i];
1415
1416                 pci_free_consistent(mlxsw_pci->pdev, mem_item->size,
1417                                     mem_item->buf, mem_item->mapaddr);
1418         }
1419         kfree(mlxsw_pci->fw_area.items);
1420 }
1421
1422 static irqreturn_t mlxsw_pci_eq_irq_handler(int irq, void *dev_id)
1423 {
1424         struct mlxsw_pci *mlxsw_pci = dev_id;
1425         struct mlxsw_pci_queue *q;
1426         int i;
1427
1428         for (i = 0; i < MLXSW_PCI_EQS_COUNT; i++) {
1429                 q = mlxsw_pci_eq_get(mlxsw_pci, i);
1430                 mlxsw_pci_queue_tasklet_schedule(q);
1431         }
1432         return IRQ_HANDLED;
1433 }
1434
1435 static int mlxsw_pci_mbox_alloc(struct mlxsw_pci *mlxsw_pci,
1436                                 struct mlxsw_pci_mem_item *mbox)
1437 {
1438         struct pci_dev *pdev = mlxsw_pci->pdev;
1439         int err = 0;
1440
1441         mbox->size = MLXSW_CMD_MBOX_SIZE;
1442         mbox->buf = pci_alloc_consistent(pdev, MLXSW_CMD_MBOX_SIZE,
1443                                          &mbox->mapaddr);
1444         if (!mbox->buf) {
1445                 dev_err(&pdev->dev, "Failed allocating memory for mailbox\n");
1446                 err = -ENOMEM;
1447         }
1448
1449         return err;
1450 }
1451
1452 static void mlxsw_pci_mbox_free(struct mlxsw_pci *mlxsw_pci,
1453                                 struct mlxsw_pci_mem_item *mbox)
1454 {
1455         struct pci_dev *pdev = mlxsw_pci->pdev;
1456
1457         pci_free_consistent(pdev, MLXSW_CMD_MBOX_SIZE, mbox->buf,
1458                             mbox->mapaddr);
1459 }
1460
1461 static int mlxsw_pci_init(void *bus_priv, struct mlxsw_core *mlxsw_core,
1462                           const struct mlxsw_config_profile *profile,
1463                           struct mlxsw_res *res)
1464 {
1465         struct mlxsw_pci *mlxsw_pci = bus_priv;
1466         struct pci_dev *pdev = mlxsw_pci->pdev;
1467         char *mbox;
1468         u16 num_pages;
1469         int err;
1470
1471         mutex_init(&mlxsw_pci->cmd.lock);
1472         init_waitqueue_head(&mlxsw_pci->cmd.wait);
1473
1474         mlxsw_pci->core = mlxsw_core;
1475
1476         mbox = mlxsw_cmd_mbox_alloc();
1477         if (!mbox)
1478                 return -ENOMEM;
1479
1480         err = mlxsw_pci_mbox_alloc(mlxsw_pci, &mlxsw_pci->cmd.in_mbox);
1481         if (err)
1482                 goto mbox_put;
1483
1484         err = mlxsw_pci_mbox_alloc(mlxsw_pci, &mlxsw_pci->cmd.out_mbox);
1485         if (err)
1486                 goto err_out_mbox_alloc;
1487
1488         err = mlxsw_cmd_query_fw(mlxsw_core, mbox);
1489         if (err)
1490                 goto err_query_fw;
1491
1492         mlxsw_pci->bus_info.fw_rev.major =
1493                 mlxsw_cmd_mbox_query_fw_fw_rev_major_get(mbox);
1494         mlxsw_pci->bus_info.fw_rev.minor =
1495                 mlxsw_cmd_mbox_query_fw_fw_rev_minor_get(mbox);
1496         mlxsw_pci->bus_info.fw_rev.subminor =
1497                 mlxsw_cmd_mbox_query_fw_fw_rev_subminor_get(mbox);
1498
1499         if (mlxsw_cmd_mbox_query_fw_cmd_interface_rev_get(mbox) != 1) {
1500                 dev_err(&pdev->dev, "Unsupported cmd interface revision ID queried from hw\n");
1501                 err = -EINVAL;
1502                 goto err_iface_rev;
1503         }
1504         if (mlxsw_cmd_mbox_query_fw_doorbell_page_bar_get(mbox) != 0) {
1505                 dev_err(&pdev->dev, "Unsupported doorbell page bar queried from hw\n");
1506                 err = -EINVAL;
1507                 goto err_doorbell_page_bar;
1508         }
1509
1510         mlxsw_pci->doorbell_offset =
1511                 mlxsw_cmd_mbox_query_fw_doorbell_page_offset_get(mbox);
1512
1513         num_pages = mlxsw_cmd_mbox_query_fw_fw_pages_get(mbox);
1514         err = mlxsw_pci_fw_area_init(mlxsw_pci, mbox, num_pages);
1515         if (err)
1516                 goto err_fw_area_init;
1517
1518         err = mlxsw_pci_boardinfo(mlxsw_pci, mbox);
1519         if (err)
1520                 goto err_boardinfo;
1521
1522         err = mlxsw_pci_resources_query(mlxsw_pci, mbox, res,
1523                                         profile->resource_query_enable);
1524         if (err)
1525                 goto err_query_resources;
1526
1527         err = mlxsw_pci_config_profile(mlxsw_pci, mbox, profile, res);
1528         if (err)
1529                 goto err_config_profile;
1530
1531         err = mlxsw_pci_aqs_init(mlxsw_pci, mbox);
1532         if (err)
1533                 goto err_aqs_init;
1534
1535         err = request_irq(mlxsw_pci->msix_entry.vector,
1536                           mlxsw_pci_eq_irq_handler, 0,
1537                           mlxsw_pci->bus_info.device_kind, mlxsw_pci);
1538         if (err) {
1539                 dev_err(&pdev->dev, "IRQ request failed\n");
1540                 goto err_request_eq_irq;
1541         }
1542
1543         goto mbox_put;
1544
1545 err_request_eq_irq:
1546         mlxsw_pci_aqs_fini(mlxsw_pci);
1547 err_aqs_init:
1548 err_config_profile:
1549 err_query_resources:
1550 err_boardinfo:
1551         mlxsw_pci_fw_area_fini(mlxsw_pci);
1552 err_fw_area_init:
1553 err_doorbell_page_bar:
1554 err_iface_rev:
1555 err_query_fw:
1556         mlxsw_pci_mbox_free(mlxsw_pci, &mlxsw_pci->cmd.out_mbox);
1557 err_out_mbox_alloc:
1558         mlxsw_pci_mbox_free(mlxsw_pci, &mlxsw_pci->cmd.in_mbox);
1559 mbox_put:
1560         mlxsw_cmd_mbox_free(mbox);
1561         return err;
1562 }
1563
1564 static void mlxsw_pci_fini(void *bus_priv)
1565 {
1566         struct mlxsw_pci *mlxsw_pci = bus_priv;
1567
1568         free_irq(mlxsw_pci->msix_entry.vector, mlxsw_pci);
1569         mlxsw_pci_aqs_fini(mlxsw_pci);
1570         mlxsw_pci_fw_area_fini(mlxsw_pci);
1571         mlxsw_pci_mbox_free(mlxsw_pci, &mlxsw_pci->cmd.out_mbox);
1572         mlxsw_pci_mbox_free(mlxsw_pci, &mlxsw_pci->cmd.in_mbox);
1573 }
1574
1575 static struct mlxsw_pci_queue *
1576 mlxsw_pci_sdq_pick(struct mlxsw_pci *mlxsw_pci,
1577                    const struct mlxsw_tx_info *tx_info)
1578 {
1579         u8 sdqn = tx_info->local_port % mlxsw_pci_sdq_count(mlxsw_pci);
1580
1581         return mlxsw_pci_sdq_get(mlxsw_pci, sdqn);
1582 }
1583
1584 static bool mlxsw_pci_skb_transmit_busy(void *bus_priv,
1585                                         const struct mlxsw_tx_info *tx_info)
1586 {
1587         struct mlxsw_pci *mlxsw_pci = bus_priv;
1588         struct mlxsw_pci_queue *q = mlxsw_pci_sdq_pick(mlxsw_pci, tx_info);
1589
1590         return !mlxsw_pci_queue_elem_info_producer_get(q);
1591 }
1592
1593 static int mlxsw_pci_skb_transmit(void *bus_priv, struct sk_buff *skb,
1594                                   const struct mlxsw_tx_info *tx_info)
1595 {
1596         struct mlxsw_pci *mlxsw_pci = bus_priv;
1597         struct mlxsw_pci_queue *q;
1598         struct mlxsw_pci_queue_elem_info *elem_info;
1599         char *wqe;
1600         int i;
1601         int err;
1602
1603         if (skb_shinfo(skb)->nr_frags > MLXSW_PCI_WQE_SG_ENTRIES - 1) {
1604                 err = skb_linearize(skb);
1605                 if (err)
1606                         return err;
1607         }
1608
1609         q = mlxsw_pci_sdq_pick(mlxsw_pci, tx_info);
1610         spin_lock_bh(&q->lock);
1611         elem_info = mlxsw_pci_queue_elem_info_producer_get(q);
1612         if (!elem_info) {
1613                 /* queue is full */
1614                 err = -EAGAIN;
1615                 goto unlock;
1616         }
1617         elem_info->u.sdq.skb = skb;
1618
1619         wqe = elem_info->elem;
1620         mlxsw_pci_wqe_c_set(wqe, 1); /* always report completion */
1621         mlxsw_pci_wqe_lp_set(wqe, !!tx_info->is_emad);
1622         mlxsw_pci_wqe_type_set(wqe, MLXSW_PCI_WQE_TYPE_ETHERNET);
1623
1624         err = mlxsw_pci_wqe_frag_map(mlxsw_pci, wqe, 0, skb->data,
1625                                      skb_headlen(skb), DMA_TO_DEVICE);
1626         if (err)
1627                 goto unlock;
1628
1629         for (i = 0; i < skb_shinfo(skb)->nr_frags; i++) {
1630                 const skb_frag_t *frag = &skb_shinfo(skb)->frags[i];
1631
1632                 err = mlxsw_pci_wqe_frag_map(mlxsw_pci, wqe, i + 1,
1633                                              skb_frag_address(frag),
1634                                              skb_frag_size(frag),
1635                                              DMA_TO_DEVICE);
1636                 if (err)
1637                         goto unmap_frags;
1638         }
1639
1640         /* Set unused sq entries byte count to zero. */
1641         for (i++; i < MLXSW_PCI_WQE_SG_ENTRIES; i++)
1642                 mlxsw_pci_wqe_byte_count_set(wqe, i, 0);
1643
1644         /* Everything is set up, ring producer doorbell to get HW going */
1645         q->producer_counter++;
1646         mlxsw_pci_queue_doorbell_producer_ring(mlxsw_pci, q);
1647
1648         goto unlock;
1649
1650 unmap_frags:
1651         for (; i >= 0; i--)
1652                 mlxsw_pci_wqe_frag_unmap(mlxsw_pci, wqe, i, DMA_TO_DEVICE);
1653 unlock:
1654         spin_unlock_bh(&q->lock);
1655         return err;
1656 }
1657
1658 static int mlxsw_pci_cmd_exec(void *bus_priv, u16 opcode, u8 opcode_mod,
1659                               u32 in_mod, bool out_mbox_direct,
1660                               char *in_mbox, size_t in_mbox_size,
1661                               char *out_mbox, size_t out_mbox_size,
1662                               u8 *p_status)
1663 {
1664         struct mlxsw_pci *mlxsw_pci = bus_priv;
1665         dma_addr_t in_mapaddr = mlxsw_pci->cmd.in_mbox.mapaddr;
1666         dma_addr_t out_mapaddr = mlxsw_pci->cmd.out_mbox.mapaddr;
1667         bool evreq = mlxsw_pci->cmd.nopoll;
1668         unsigned long timeout = msecs_to_jiffies(MLXSW_PCI_CIR_TIMEOUT_MSECS);
1669         bool *p_wait_done = &mlxsw_pci->cmd.wait_done;
1670         int err;
1671
1672         *p_status = MLXSW_CMD_STATUS_OK;
1673
1674         err = mutex_lock_interruptible(&mlxsw_pci->cmd.lock);
1675         if (err)
1676                 return err;
1677
1678         if (in_mbox)
1679                 memcpy(mlxsw_pci->cmd.in_mbox.buf, in_mbox, in_mbox_size);
1680         mlxsw_pci_write32(mlxsw_pci, CIR_IN_PARAM_HI, upper_32_bits(in_mapaddr));
1681         mlxsw_pci_write32(mlxsw_pci, CIR_IN_PARAM_LO, lower_32_bits(in_mapaddr));
1682
1683         mlxsw_pci_write32(mlxsw_pci, CIR_OUT_PARAM_HI, upper_32_bits(out_mapaddr));
1684         mlxsw_pci_write32(mlxsw_pci, CIR_OUT_PARAM_LO, lower_32_bits(out_mapaddr));
1685
1686         mlxsw_pci_write32(mlxsw_pci, CIR_IN_MODIFIER, in_mod);
1687         mlxsw_pci_write32(mlxsw_pci, CIR_TOKEN, 0);
1688
1689         *p_wait_done = false;
1690
1691         wmb(); /* all needs to be written before we write control register */
1692         mlxsw_pci_write32(mlxsw_pci, CIR_CTRL,
1693                           MLXSW_PCI_CIR_CTRL_GO_BIT |
1694                           (evreq ? MLXSW_PCI_CIR_CTRL_EVREQ_BIT : 0) |
1695                           (opcode_mod << MLXSW_PCI_CIR_CTRL_OPCODE_MOD_SHIFT) |
1696                           opcode);
1697
1698         if (!evreq) {
1699                 unsigned long end;
1700
1701                 end = jiffies + timeout;
1702                 do {
1703                         u32 ctrl = mlxsw_pci_read32(mlxsw_pci, CIR_CTRL);
1704
1705                         if (!(ctrl & MLXSW_PCI_CIR_CTRL_GO_BIT)) {
1706                                 *p_wait_done = true;
1707                                 *p_status = ctrl >> MLXSW_PCI_CIR_CTRL_STATUS_SHIFT;
1708                                 break;
1709                         }
1710                         cond_resched();
1711                 } while (time_before(jiffies, end));
1712         } else {
1713                 wait_event_timeout(mlxsw_pci->cmd.wait, *p_wait_done, timeout);
1714                 *p_status = mlxsw_pci->cmd.comp.status;
1715         }
1716
1717         err = 0;
1718         if (*p_wait_done) {
1719                 if (*p_status)
1720                         err = -EIO;
1721         } else {
1722                 err = -ETIMEDOUT;
1723         }
1724
1725         if (!err && out_mbox && out_mbox_direct) {
1726                 /* Some commands don't use output param as address to mailbox
1727                  * but they store output directly into registers. In that case,
1728                  * copy registers into mbox buffer.
1729                  */
1730                 __be32 tmp;
1731
1732                 if (!evreq) {
1733                         tmp = cpu_to_be32(mlxsw_pci_read32(mlxsw_pci,
1734                                                            CIR_OUT_PARAM_HI));
1735                         memcpy(out_mbox, &tmp, sizeof(tmp));
1736                         tmp = cpu_to_be32(mlxsw_pci_read32(mlxsw_pci,
1737                                                            CIR_OUT_PARAM_LO));
1738                         memcpy(out_mbox + sizeof(tmp), &tmp, sizeof(tmp));
1739                 }
1740         } else if (!err && out_mbox) {
1741                 memcpy(out_mbox, mlxsw_pci->cmd.out_mbox.buf, out_mbox_size);
1742         }
1743
1744         mutex_unlock(&mlxsw_pci->cmd.lock);
1745
1746         return err;
1747 }
1748
1749 static const struct mlxsw_bus mlxsw_pci_bus = {
1750         .kind                   = "pci",
1751         .init                   = mlxsw_pci_init,
1752         .fini                   = mlxsw_pci_fini,
1753         .skb_transmit_busy      = mlxsw_pci_skb_transmit_busy,
1754         .skb_transmit           = mlxsw_pci_skb_transmit,
1755         .cmd_exec               = mlxsw_pci_cmd_exec,
1756         .features               = MLXSW_BUS_F_TXRX,
1757 };
1758
1759 static int mlxsw_pci_sw_reset(struct mlxsw_pci *mlxsw_pci,
1760                               const struct pci_device_id *id)
1761 {
1762         unsigned long end;
1763
1764         mlxsw_pci_write32(mlxsw_pci, SW_RESET, MLXSW_PCI_SW_RESET_RST_BIT);
1765         if (id->device == PCI_DEVICE_ID_MELLANOX_SWITCHX2) {
1766                 msleep(MLXSW_PCI_SW_RESET_TIMEOUT_MSECS);
1767                 return 0;
1768         }
1769
1770         wmb(); /* reset needs to be written before we read control register */
1771         end = jiffies + msecs_to_jiffies(MLXSW_PCI_SW_RESET_TIMEOUT_MSECS);
1772         do {
1773                 u32 val = mlxsw_pci_read32(mlxsw_pci, FW_READY);
1774
1775                 if ((val & MLXSW_PCI_FW_READY_MASK) == MLXSW_PCI_FW_READY_MAGIC)
1776                         break;
1777                 cond_resched();
1778         } while (time_before(jiffies, end));
1779         return 0;
1780 }
1781
1782 static int mlxsw_pci_probe(struct pci_dev *pdev, const struct pci_device_id *id)
1783 {
1784         const char *driver_name = pdev->driver->name;
1785         struct mlxsw_pci *mlxsw_pci;
1786         int err;
1787
1788         mlxsw_pci = kzalloc(sizeof(*mlxsw_pci), GFP_KERNEL);
1789         if (!mlxsw_pci)
1790                 return -ENOMEM;
1791
1792         err = pci_enable_device(pdev);
1793         if (err) {
1794                 dev_err(&pdev->dev, "pci_enable_device failed\n");
1795                 goto err_pci_enable_device;
1796         }
1797
1798         err = pci_request_regions(pdev, driver_name);
1799         if (err) {
1800                 dev_err(&pdev->dev, "pci_request_regions failed\n");
1801                 goto err_pci_request_regions;
1802         }
1803
1804         err = pci_set_dma_mask(pdev, DMA_BIT_MASK(64));
1805         if (!err) {
1806                 err = pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(64));
1807                 if (err) {
1808                         dev_err(&pdev->dev, "pci_set_consistent_dma_mask failed\n");
1809                         goto err_pci_set_dma_mask;
1810                 }
1811         } else {
1812                 err = pci_set_dma_mask(pdev, DMA_BIT_MASK(32));
1813                 if (err) {
1814                         dev_err(&pdev->dev, "pci_set_dma_mask failed\n");
1815                         goto err_pci_set_dma_mask;
1816                 }
1817         }
1818
1819         if (pci_resource_len(pdev, 0) < MLXSW_PCI_BAR0_SIZE) {
1820                 dev_err(&pdev->dev, "invalid PCI region size\n");
1821                 err = -EINVAL;
1822                 goto err_pci_resource_len_check;
1823         }
1824
1825         mlxsw_pci->hw_addr = ioremap(pci_resource_start(pdev, 0),
1826                                      pci_resource_len(pdev, 0));
1827         if (!mlxsw_pci->hw_addr) {
1828                 dev_err(&pdev->dev, "ioremap failed\n");
1829                 err = -EIO;
1830                 goto err_ioremap;
1831         }
1832         pci_set_master(pdev);
1833
1834         mlxsw_pci->pdev = pdev;
1835         pci_set_drvdata(pdev, mlxsw_pci);
1836
1837         err = mlxsw_pci_sw_reset(mlxsw_pci, id);
1838         if (err) {
1839                 dev_err(&pdev->dev, "Software reset failed\n");
1840                 goto err_sw_reset;
1841         }
1842
1843         err = pci_enable_msix_exact(pdev, &mlxsw_pci->msix_entry, 1);
1844         if (err) {
1845                 dev_err(&pdev->dev, "MSI-X init failed\n");
1846                 goto err_msix_init;
1847         }
1848
1849         mlxsw_pci->bus_info.device_kind = driver_name;
1850         mlxsw_pci->bus_info.device_name = pci_name(mlxsw_pci->pdev);
1851         mlxsw_pci->bus_info.dev = &pdev->dev;
1852
1853         mlxsw_pci->dbg_dir = debugfs_create_dir(mlxsw_pci->bus_info.device_name,
1854                                                 mlxsw_pci_dbg_root);
1855         if (!mlxsw_pci->dbg_dir) {
1856                 dev_err(&pdev->dev, "Failed to create debugfs dir\n");
1857                 err = -ENOMEM;
1858                 goto err_dbg_create_dir;
1859         }
1860
1861         err = mlxsw_core_bus_device_register(&mlxsw_pci->bus_info,
1862                                              &mlxsw_pci_bus, mlxsw_pci);
1863         if (err) {
1864                 dev_err(&pdev->dev, "cannot register bus device\n");
1865                 goto err_bus_device_register;
1866         }
1867
1868         return 0;
1869
1870 err_bus_device_register:
1871         debugfs_remove_recursive(mlxsw_pci->dbg_dir);
1872 err_dbg_create_dir:
1873         pci_disable_msix(mlxsw_pci->pdev);
1874 err_msix_init:
1875 err_sw_reset:
1876         iounmap(mlxsw_pci->hw_addr);
1877 err_ioremap:
1878 err_pci_resource_len_check:
1879 err_pci_set_dma_mask:
1880         pci_release_regions(pdev);
1881 err_pci_request_regions:
1882         pci_disable_device(pdev);
1883 err_pci_enable_device:
1884         kfree(mlxsw_pci);
1885         return err;
1886 }
1887
1888 static void mlxsw_pci_remove(struct pci_dev *pdev)
1889 {
1890         struct mlxsw_pci *mlxsw_pci = pci_get_drvdata(pdev);
1891
1892         mlxsw_core_bus_device_unregister(mlxsw_pci->core);
1893         debugfs_remove_recursive(mlxsw_pci->dbg_dir);
1894         pci_disable_msix(mlxsw_pci->pdev);
1895         iounmap(mlxsw_pci->hw_addr);
1896         pci_release_regions(mlxsw_pci->pdev);
1897         pci_disable_device(mlxsw_pci->pdev);
1898         kfree(mlxsw_pci);
1899 }
1900
1901 int mlxsw_pci_driver_register(struct pci_driver *pci_driver)
1902 {
1903         pci_driver->probe = mlxsw_pci_probe;
1904         pci_driver->remove = mlxsw_pci_remove;
1905         return pci_register_driver(pci_driver);
1906 }
1907 EXPORT_SYMBOL(mlxsw_pci_driver_register);
1908
1909 void mlxsw_pci_driver_unregister(struct pci_driver *pci_driver)
1910 {
1911         pci_unregister_driver(pci_driver);
1912 }
1913 EXPORT_SYMBOL(mlxsw_pci_driver_unregister);
1914
1915 static int __init mlxsw_pci_module_init(void)
1916 {
1917         mlxsw_pci_dbg_root = debugfs_create_dir(mlxsw_pci_driver_name, NULL);
1918         if (!mlxsw_pci_dbg_root)
1919                 return -ENOMEM;
1920         return 0;
1921 }
1922
1923 static void __exit mlxsw_pci_module_exit(void)
1924 {
1925         debugfs_remove_recursive(mlxsw_pci_dbg_root);
1926 }
1927
1928 module_init(mlxsw_pci_module_init);
1929 module_exit(mlxsw_pci_module_exit);
1930
1931 MODULE_LICENSE("Dual BSD/GPL");
1932 MODULE_AUTHOR("Jiri Pirko <jiri@mellanox.com>");
1933 MODULE_DESCRIPTION("Mellanox switch PCI interface driver");