2 * drivers/net/ethernet/nxp/lpc_eth.c
4 * Author: Kevin Wells <kevin.wells@nxp.com>
6 * Copyright (C) 2010 NXP Semiconductors
7 * Copyright (C) 2012 Roland Stigge <stigge@antcom.de>
9 * This program is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License as published by
11 * the Free Software Foundation; either version 2 of the License, or
12 * (at your option) any later version.
14 * This program is distributed in the hope that it will be useful,
15 * but WITHOUT ANY WARRANTY; without even the implied warranty of
16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 * GNU General Public License for more details.
20 #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
22 #include <linux/module.h>
23 #include <linux/kernel.h>
24 #include <linux/sched.h>
25 #include <linux/slab.h>
26 #include <linux/delay.h>
27 #include <linux/interrupt.h>
28 #include <linux/errno.h>
29 #include <linux/ioport.h>
30 #include <linux/crc32.h>
31 #include <linux/platform_device.h>
32 #include <linux/spinlock.h>
33 #include <linux/ethtool.h>
34 #include <linux/mii.h>
35 #include <linux/clk.h>
36 #include <linux/workqueue.h>
37 #include <linux/netdevice.h>
38 #include <linux/etherdevice.h>
39 #include <linux/skbuff.h>
40 #include <linux/phy.h>
41 #include <linux/dma-mapping.h>
43 #include <linux/of_net.h>
44 #include <linux/types.h>
47 #include <mach/board.h>
48 #include <mach/platform.h>
49 #include <mach/hardware.h>
51 #define MODNAME "lpc-eth"
52 #define DRV_VERSION "1.00"
54 #define ENET_MAXF_SIZE 1536
55 #define ENET_RX_DESC 48
56 #define ENET_TX_DESC 16
58 #define NAPI_WEIGHT 16
61 * Ethernet MAC controller Register offsets
63 #define LPC_ENET_MAC1(x) (x + 0x000)
64 #define LPC_ENET_MAC2(x) (x + 0x004)
65 #define LPC_ENET_IPGT(x) (x + 0x008)
66 #define LPC_ENET_IPGR(x) (x + 0x00C)
67 #define LPC_ENET_CLRT(x) (x + 0x010)
68 #define LPC_ENET_MAXF(x) (x + 0x014)
69 #define LPC_ENET_SUPP(x) (x + 0x018)
70 #define LPC_ENET_TEST(x) (x + 0x01C)
71 #define LPC_ENET_MCFG(x) (x + 0x020)
72 #define LPC_ENET_MCMD(x) (x + 0x024)
73 #define LPC_ENET_MADR(x) (x + 0x028)
74 #define LPC_ENET_MWTD(x) (x + 0x02C)
75 #define LPC_ENET_MRDD(x) (x + 0x030)
76 #define LPC_ENET_MIND(x) (x + 0x034)
77 #define LPC_ENET_SA0(x) (x + 0x040)
78 #define LPC_ENET_SA1(x) (x + 0x044)
79 #define LPC_ENET_SA2(x) (x + 0x048)
80 #define LPC_ENET_COMMAND(x) (x + 0x100)
81 #define LPC_ENET_STATUS(x) (x + 0x104)
82 #define LPC_ENET_RXDESCRIPTOR(x) (x + 0x108)
83 #define LPC_ENET_RXSTATUS(x) (x + 0x10C)
84 #define LPC_ENET_RXDESCRIPTORNUMBER(x) (x + 0x110)
85 #define LPC_ENET_RXPRODUCEINDEX(x) (x + 0x114)
86 #define LPC_ENET_RXCONSUMEINDEX(x) (x + 0x118)
87 #define LPC_ENET_TXDESCRIPTOR(x) (x + 0x11C)
88 #define LPC_ENET_TXSTATUS(x) (x + 0x120)
89 #define LPC_ENET_TXDESCRIPTORNUMBER(x) (x + 0x124)
90 #define LPC_ENET_TXPRODUCEINDEX(x) (x + 0x128)
91 #define LPC_ENET_TXCONSUMEINDEX(x) (x + 0x12C)
92 #define LPC_ENET_TSV0(x) (x + 0x158)
93 #define LPC_ENET_TSV1(x) (x + 0x15C)
94 #define LPC_ENET_RSV(x) (x + 0x160)
95 #define LPC_ENET_FLOWCONTROLCOUNTER(x) (x + 0x170)
96 #define LPC_ENET_FLOWCONTROLSTATUS(x) (x + 0x174)
97 #define LPC_ENET_RXFILTER_CTRL(x) (x + 0x200)
98 #define LPC_ENET_RXFILTERWOLSTATUS(x) (x + 0x204)
99 #define LPC_ENET_RXFILTERWOLCLEAR(x) (x + 0x208)
100 #define LPC_ENET_HASHFILTERL(x) (x + 0x210)
101 #define LPC_ENET_HASHFILTERH(x) (x + 0x214)
102 #define LPC_ENET_INTSTATUS(x) (x + 0xFE0)
103 #define LPC_ENET_INTENABLE(x) (x + 0xFE4)
104 #define LPC_ENET_INTCLEAR(x) (x + 0xFE8)
105 #define LPC_ENET_INTSET(x) (x + 0xFEC)
106 #define LPC_ENET_POWERDOWN(x) (x + 0xFF4)
109 * mac1 register definitions
111 #define LPC_MAC1_RECV_ENABLE (1 << 0)
112 #define LPC_MAC1_PASS_ALL_RX_FRAMES (1 << 1)
113 #define LPC_MAC1_RX_FLOW_CONTROL (1 << 2)
114 #define LPC_MAC1_TX_FLOW_CONTROL (1 << 3)
115 #define LPC_MAC1_LOOPBACK (1 << 4)
116 #define LPC_MAC1_RESET_TX (1 << 8)
117 #define LPC_MAC1_RESET_MCS_TX (1 << 9)
118 #define LPC_MAC1_RESET_RX (1 << 10)
119 #define LPC_MAC1_RESET_MCS_RX (1 << 11)
120 #define LPC_MAC1_SIMULATION_RESET (1 << 14)
121 #define LPC_MAC1_SOFT_RESET (1 << 15)
124 * mac2 register definitions
126 #define LPC_MAC2_FULL_DUPLEX (1 << 0)
127 #define LPC_MAC2_FRAME_LENGTH_CHECKING (1 << 1)
128 #define LPC_MAC2_HUGH_LENGTH_CHECKING (1 << 2)
129 #define LPC_MAC2_DELAYED_CRC (1 << 3)
130 #define LPC_MAC2_CRC_ENABLE (1 << 4)
131 #define LPC_MAC2_PAD_CRC_ENABLE (1 << 5)
132 #define LPC_MAC2_VLAN_PAD_ENABLE (1 << 6)
133 #define LPC_MAC2_AUTO_DETECT_PAD_ENABLE (1 << 7)
134 #define LPC_MAC2_PURE_PREAMBLE_ENFORCEMENT (1 << 8)
135 #define LPC_MAC2_LONG_PREAMBLE_ENFORCEMENT (1 << 9)
136 #define LPC_MAC2_NO_BACKOFF (1 << 12)
137 #define LPC_MAC2_BACK_PRESSURE (1 << 13)
138 #define LPC_MAC2_EXCESS_DEFER (1 << 14)
141 * ipgt register definitions
143 #define LPC_IPGT_LOAD(n) ((n) & 0x7F)
146 * ipgr register definitions
148 #define LPC_IPGR_LOAD_PART2(n) ((n) & 0x7F)
149 #define LPC_IPGR_LOAD_PART1(n) (((n) & 0x7F) << 8)
152 * clrt register definitions
154 #define LPC_CLRT_LOAD_RETRY_MAX(n) ((n) & 0xF)
155 #define LPC_CLRT_LOAD_COLLISION_WINDOW(n) (((n) & 0x3F) << 8)
158 * maxf register definitions
160 #define LPC_MAXF_LOAD_MAX_FRAME_LEN(n) ((n) & 0xFFFF)
163 * supp register definitions
165 #define LPC_SUPP_SPEED (1 << 8)
166 #define LPC_SUPP_RESET_RMII (1 << 11)
169 * test register definitions
171 #define LPC_TEST_SHORTCUT_PAUSE_QUANTA (1 << 0)
172 #define LPC_TEST_PAUSE (1 << 1)
173 #define LPC_TEST_BACKPRESSURE (1 << 2)
176 * mcfg register definitions
178 #define LPC_MCFG_SCAN_INCREMENT (1 << 0)
179 #define LPC_MCFG_SUPPRESS_PREAMBLE (1 << 1)
180 #define LPC_MCFG_CLOCK_SELECT(n) (((n) & 0x7) << 2)
181 #define LPC_MCFG_CLOCK_HOST_DIV_4 0
182 #define LPC_MCFG_CLOCK_HOST_DIV_6 2
183 #define LPC_MCFG_CLOCK_HOST_DIV_8 3
184 #define LPC_MCFG_CLOCK_HOST_DIV_10 4
185 #define LPC_MCFG_CLOCK_HOST_DIV_14 5
186 #define LPC_MCFG_CLOCK_HOST_DIV_20 6
187 #define LPC_MCFG_CLOCK_HOST_DIV_28 7
188 #define LPC_MCFG_RESET_MII_MGMT (1 << 15)
191 * mcmd register definitions
193 #define LPC_MCMD_READ (1 << 0)
194 #define LPC_MCMD_SCAN (1 << 1)
197 * madr register definitions
199 #define LPC_MADR_REGISTER_ADDRESS(n) ((n) & 0x1F)
200 #define LPC_MADR_PHY_0ADDRESS(n) (((n) & 0x1F) << 8)
203 * mwtd register definitions
205 #define LPC_MWDT_WRITE(n) ((n) & 0xFFFF)
208 * mrdd register definitions
210 #define LPC_MRDD_READ_MASK 0xFFFF
213 * mind register definitions
215 #define LPC_MIND_BUSY (1 << 0)
216 #define LPC_MIND_SCANNING (1 << 1)
217 #define LPC_MIND_NOT_VALID (1 << 2)
218 #define LPC_MIND_MII_LINK_FAIL (1 << 3)
221 * command register definitions
223 #define LPC_COMMAND_RXENABLE (1 << 0)
224 #define LPC_COMMAND_TXENABLE (1 << 1)
225 #define LPC_COMMAND_REG_RESET (1 << 3)
226 #define LPC_COMMAND_TXRESET (1 << 4)
227 #define LPC_COMMAND_RXRESET (1 << 5)
228 #define LPC_COMMAND_PASSRUNTFRAME (1 << 6)
229 #define LPC_COMMAND_PASSRXFILTER (1 << 7)
230 #define LPC_COMMAND_TXFLOWCONTROL (1 << 8)
231 #define LPC_COMMAND_RMII (1 << 9)
232 #define LPC_COMMAND_FULLDUPLEX (1 << 10)
235 * status register definitions
237 #define LPC_STATUS_RXACTIVE (1 << 0)
238 #define LPC_STATUS_TXACTIVE (1 << 1)
241 * tsv0 register definitions
243 #define LPC_TSV0_CRC_ERROR (1 << 0)
244 #define LPC_TSV0_LENGTH_CHECK_ERROR (1 << 1)
245 #define LPC_TSV0_LENGTH_OUT_OF_RANGE (1 << 2)
246 #define LPC_TSV0_DONE (1 << 3)
247 #define LPC_TSV0_MULTICAST (1 << 4)
248 #define LPC_TSV0_BROADCAST (1 << 5)
249 #define LPC_TSV0_PACKET_DEFER (1 << 6)
250 #define LPC_TSV0_ESCESSIVE_DEFER (1 << 7)
251 #define LPC_TSV0_ESCESSIVE_COLLISION (1 << 8)
252 #define LPC_TSV0_LATE_COLLISION (1 << 9)
253 #define LPC_TSV0_GIANT (1 << 10)
254 #define LPC_TSV0_UNDERRUN (1 << 11)
255 #define LPC_TSV0_TOTAL_BYTES(n) (((n) >> 12) & 0xFFFF)
256 #define LPC_TSV0_CONTROL_FRAME (1 << 28)
257 #define LPC_TSV0_PAUSE (1 << 29)
258 #define LPC_TSV0_BACKPRESSURE (1 << 30)
259 #define LPC_TSV0_VLAN (1 << 31)
262 * tsv1 register definitions
264 #define LPC_TSV1_TRANSMIT_BYTE_COUNT(n) ((n) & 0xFFFF)
265 #define LPC_TSV1_COLLISION_COUNT(n) (((n) >> 16) & 0xF)
268 * rsv register definitions
270 #define LPC_RSV_RECEIVED_BYTE_COUNT(n) ((n) & 0xFFFF)
271 #define LPC_RSV_RXDV_EVENT_IGNORED (1 << 16)
272 #define LPC_RSV_RXDV_EVENT_PREVIOUSLY_SEEN (1 << 17)
273 #define LPC_RSV_CARRIER_EVNT_PREVIOUS_SEEN (1 << 18)
274 #define LPC_RSV_RECEIVE_CODE_VIOLATION (1 << 19)
275 #define LPC_RSV_CRC_ERROR (1 << 20)
276 #define LPC_RSV_LENGTH_CHECK_ERROR (1 << 21)
277 #define LPC_RSV_LENGTH_OUT_OF_RANGE (1 << 22)
278 #define LPC_RSV_RECEIVE_OK (1 << 23)
279 #define LPC_RSV_MULTICAST (1 << 24)
280 #define LPC_RSV_BROADCAST (1 << 25)
281 #define LPC_RSV_DRIBBLE_NIBBLE (1 << 26)
282 #define LPC_RSV_CONTROL_FRAME (1 << 27)
283 #define LPC_RSV_PAUSE (1 << 28)
284 #define LPC_RSV_UNSUPPORTED_OPCODE (1 << 29)
285 #define LPC_RSV_VLAN (1 << 30)
288 * flowcontrolcounter register definitions
290 #define LPC_FCCR_MIRRORCOUNTER(n) ((n) & 0xFFFF)
291 #define LPC_FCCR_PAUSETIMER(n) (((n) >> 16) & 0xFFFF)
294 * flowcontrolstatus register definitions
296 #define LPC_FCCR_MIRRORCOUNTERCURRENT(n) ((n) & 0xFFFF)
299 * rxfliterctrl, rxfilterwolstatus, and rxfilterwolclear shared
300 * register definitions
302 #define LPC_RXFLTRW_ACCEPTUNICAST (1 << 0)
303 #define LPC_RXFLTRW_ACCEPTUBROADCAST (1 << 1)
304 #define LPC_RXFLTRW_ACCEPTUMULTICAST (1 << 2)
305 #define LPC_RXFLTRW_ACCEPTUNICASTHASH (1 << 3)
306 #define LPC_RXFLTRW_ACCEPTUMULTICASTHASH (1 << 4)
307 #define LPC_RXFLTRW_ACCEPTPERFECT (1 << 5)
310 * rxfliterctrl register definitions
312 #define LPC_RXFLTRWSTS_MAGICPACKETENWOL (1 << 12)
313 #define LPC_RXFLTRWSTS_RXFILTERENWOL (1 << 13)
316 * rxfilterwolstatus/rxfilterwolclear register definitions
318 #define LPC_RXFLTRWSTS_RXFILTERWOL (1 << 7)
319 #define LPC_RXFLTRWSTS_MAGICPACKETWOL (1 << 8)
322 * intstatus, intenable, intclear, and Intset shared register
325 #define LPC_MACINT_RXOVERRUNINTEN (1 << 0)
326 #define LPC_MACINT_RXERRORONINT (1 << 1)
327 #define LPC_MACINT_RXFINISHEDINTEN (1 << 2)
328 #define LPC_MACINT_RXDONEINTEN (1 << 3)
329 #define LPC_MACINT_TXUNDERRUNINTEN (1 << 4)
330 #define LPC_MACINT_TXERRORINTEN (1 << 5)
331 #define LPC_MACINT_TXFINISHEDINTEN (1 << 6)
332 #define LPC_MACINT_TXDONEINTEN (1 << 7)
333 #define LPC_MACINT_SOFTINTEN (1 << 12)
334 #define LPC_MACINT_WAKEUPINTEN (1 << 13)
337 * powerdown register definitions
339 #define LPC_POWERDOWN_MACAHB (1 << 31)
341 static phy_interface_t lpc_phy_interface_mode(struct device *dev)
343 if (dev && dev->of_node) {
344 const char *mode = of_get_property(dev->of_node,
346 if (mode && !strcmp(mode, "mii"))
347 return PHY_INTERFACE_MODE_MII;
349 return PHY_INTERFACE_MODE_RMII;
352 static bool use_iram_for_net(struct device *dev)
354 if (dev && dev->of_node)
355 return of_property_read_bool(dev->of_node, "use-iram");
359 /* Receive Status information word */
360 #define RXSTATUS_SIZE 0x000007FF
361 #define RXSTATUS_CONTROL (1 << 18)
362 #define RXSTATUS_VLAN (1 << 19)
363 #define RXSTATUS_FILTER (1 << 20)
364 #define RXSTATUS_MULTICAST (1 << 21)
365 #define RXSTATUS_BROADCAST (1 << 22)
366 #define RXSTATUS_CRC (1 << 23)
367 #define RXSTATUS_SYMBOL (1 << 24)
368 #define RXSTATUS_LENGTH (1 << 25)
369 #define RXSTATUS_RANGE (1 << 26)
370 #define RXSTATUS_ALIGN (1 << 27)
371 #define RXSTATUS_OVERRUN (1 << 28)
372 #define RXSTATUS_NODESC (1 << 29)
373 #define RXSTATUS_LAST (1 << 30)
374 #define RXSTATUS_ERROR (1 << 31)
376 #define RXSTATUS_STATUS_ERROR \
377 (RXSTATUS_NODESC | RXSTATUS_OVERRUN | RXSTATUS_ALIGN | \
378 RXSTATUS_RANGE | RXSTATUS_LENGTH | RXSTATUS_SYMBOL | RXSTATUS_CRC)
380 /* Receive Descriptor control word */
381 #define RXDESC_CONTROL_SIZE 0x000007FF
382 #define RXDESC_CONTROL_INT (1 << 31)
384 /* Transmit Status information word */
385 #define TXSTATUS_COLLISIONS_GET(x) (((x) >> 21) & 0xF)
386 #define TXSTATUS_DEFER (1 << 25)
387 #define TXSTATUS_EXCESSDEFER (1 << 26)
388 #define TXSTATUS_EXCESSCOLL (1 << 27)
389 #define TXSTATUS_LATECOLL (1 << 28)
390 #define TXSTATUS_UNDERRUN (1 << 29)
391 #define TXSTATUS_NODESC (1 << 30)
392 #define TXSTATUS_ERROR (1 << 31)
394 /* Transmit Descriptor control word */
395 #define TXDESC_CONTROL_SIZE 0x000007FF
396 #define TXDESC_CONTROL_OVERRIDE (1 << 26)
397 #define TXDESC_CONTROL_HUGE (1 << 27)
398 #define TXDESC_CONTROL_PAD (1 << 28)
399 #define TXDESC_CONTROL_CRC (1 << 29)
400 #define TXDESC_CONTROL_LAST (1 << 30)
401 #define TXDESC_CONTROL_INT (1 << 31)
404 * Structure of a TX/RX descriptors and RX status
412 __le32 statushashcrc;
416 * Device driver data structure
418 struct netdata_local {
419 struct platform_device *pdev;
420 struct net_device *ndev;
422 void __iomem *net_base;
424 unsigned int skblen[ENET_TX_DESC];
425 unsigned int last_tx_idx;
426 unsigned int num_used_tx_buffs;
427 struct mii_bus *mii_bus;
428 struct phy_device *phy_dev;
430 dma_addr_t dma_buff_base_p;
431 void *dma_buff_base_v;
432 size_t dma_buff_size;
433 struct txrx_desc_t *tx_desc_v;
436 struct txrx_desc_t *rx_desc_v;
437 struct rx_status_t *rx_stat_v;
442 struct napi_struct napi;
446 * MAC support functions
448 static void __lpc_set_mac(struct netdata_local *pldat, u8 *mac)
452 /* Set station address */
453 tmp = mac[0] | ((u32)mac[1] << 8);
454 writel(tmp, LPC_ENET_SA2(pldat->net_base));
455 tmp = mac[2] | ((u32)mac[3] << 8);
456 writel(tmp, LPC_ENET_SA1(pldat->net_base));
457 tmp = mac[4] | ((u32)mac[5] << 8);
458 writel(tmp, LPC_ENET_SA0(pldat->net_base));
460 netdev_dbg(pldat->ndev, "Ethernet MAC address %pM\n", mac);
463 static void __lpc_get_mac(struct netdata_local *pldat, u8 *mac)
467 /* Get station address */
468 tmp = readl(LPC_ENET_SA2(pldat->net_base));
471 tmp = readl(LPC_ENET_SA1(pldat->net_base));
474 tmp = readl(LPC_ENET_SA0(pldat->net_base));
479 static void __lpc_eth_clock_enable(struct netdata_local *pldat, bool enable)
482 clk_prepare_enable(pldat->clk);
484 clk_disable_unprepare(pldat->clk);
487 static void __lpc_params_setup(struct netdata_local *pldat)
491 if (pldat->duplex == DUPLEX_FULL) {
492 tmp = readl(LPC_ENET_MAC2(pldat->net_base));
493 tmp |= LPC_MAC2_FULL_DUPLEX;
494 writel(tmp, LPC_ENET_MAC2(pldat->net_base));
495 tmp = readl(LPC_ENET_COMMAND(pldat->net_base));
496 tmp |= LPC_COMMAND_FULLDUPLEX;
497 writel(tmp, LPC_ENET_COMMAND(pldat->net_base));
498 writel(LPC_IPGT_LOAD(0x15), LPC_ENET_IPGT(pldat->net_base));
500 tmp = readl(LPC_ENET_MAC2(pldat->net_base));
501 tmp &= ~LPC_MAC2_FULL_DUPLEX;
502 writel(tmp, LPC_ENET_MAC2(pldat->net_base));
503 tmp = readl(LPC_ENET_COMMAND(pldat->net_base));
504 tmp &= ~LPC_COMMAND_FULLDUPLEX;
505 writel(tmp, LPC_ENET_COMMAND(pldat->net_base));
506 writel(LPC_IPGT_LOAD(0x12), LPC_ENET_IPGT(pldat->net_base));
509 if (pldat->speed == SPEED_100)
510 writel(LPC_SUPP_SPEED, LPC_ENET_SUPP(pldat->net_base));
512 writel(0, LPC_ENET_SUPP(pldat->net_base));
515 static void __lpc_eth_reset(struct netdata_local *pldat)
517 /* Reset all MAC logic */
518 writel((LPC_MAC1_RESET_TX | LPC_MAC1_RESET_MCS_TX | LPC_MAC1_RESET_RX |
519 LPC_MAC1_RESET_MCS_RX | LPC_MAC1_SIMULATION_RESET |
520 LPC_MAC1_SOFT_RESET), LPC_ENET_MAC1(pldat->net_base));
521 writel((LPC_COMMAND_REG_RESET | LPC_COMMAND_TXRESET |
522 LPC_COMMAND_RXRESET), LPC_ENET_COMMAND(pldat->net_base));
525 static int __lpc_mii_mngt_reset(struct netdata_local *pldat)
527 /* Reset MII management hardware */
528 writel(LPC_MCFG_RESET_MII_MGMT, LPC_ENET_MCFG(pldat->net_base));
530 /* Setup MII clock to slowest rate with a /28 divider */
531 writel(LPC_MCFG_CLOCK_SELECT(LPC_MCFG_CLOCK_HOST_DIV_28),
532 LPC_ENET_MCFG(pldat->net_base));
537 static inline phys_addr_t __va_to_pa(void *addr, struct netdata_local *pldat)
541 phaddr = addr - pldat->dma_buff_base_v;
542 phaddr += pldat->dma_buff_base_p;
547 static void lpc_eth_enable_int(void __iomem *regbase)
549 writel((LPC_MACINT_RXDONEINTEN | LPC_MACINT_TXDONEINTEN),
550 LPC_ENET_INTENABLE(regbase));
553 static void lpc_eth_disable_int(void __iomem *regbase)
555 writel(0, LPC_ENET_INTENABLE(regbase));
558 /* Setup TX/RX descriptors */
559 static void __lpc_txrx_desc_setup(struct netdata_local *pldat)
564 struct txrx_desc_t *ptxrxdesc;
565 struct rx_status_t *prxstat;
567 tbuff = PTR_ALIGN(pldat->dma_buff_base_v, 16);
569 /* Setup TX descriptors, status, and buffers */
570 pldat->tx_desc_v = tbuff;
571 tbuff += sizeof(struct txrx_desc_t) * ENET_TX_DESC;
573 pldat->tx_stat_v = tbuff;
574 tbuff += sizeof(u32) * ENET_TX_DESC;
576 tbuff = PTR_ALIGN(tbuff, 16);
577 pldat->tx_buff_v = tbuff;
578 tbuff += ENET_MAXF_SIZE * ENET_TX_DESC;
580 /* Setup RX descriptors, status, and buffers */
581 pldat->rx_desc_v = tbuff;
582 tbuff += sizeof(struct txrx_desc_t) * ENET_RX_DESC;
584 tbuff = PTR_ALIGN(tbuff, 16);
585 pldat->rx_stat_v = tbuff;
586 tbuff += sizeof(struct rx_status_t) * ENET_RX_DESC;
588 tbuff = PTR_ALIGN(tbuff, 16);
589 pldat->rx_buff_v = tbuff;
590 tbuff += ENET_MAXF_SIZE * ENET_RX_DESC;
592 /* Map the TX descriptors to the TX buffers in hardware */
593 for (i = 0; i < ENET_TX_DESC; i++) {
594 ptxstat = &pldat->tx_stat_v[i];
595 ptxrxdesc = &pldat->tx_desc_v[i];
597 ptxrxdesc->packet = __va_to_pa(
598 pldat->tx_buff_v + i * ENET_MAXF_SIZE, pldat);
599 ptxrxdesc->control = 0;
603 /* Map the RX descriptors to the RX buffers in hardware */
604 for (i = 0; i < ENET_RX_DESC; i++) {
605 prxstat = &pldat->rx_stat_v[i];
606 ptxrxdesc = &pldat->rx_desc_v[i];
608 ptxrxdesc->packet = __va_to_pa(
609 pldat->rx_buff_v + i * ENET_MAXF_SIZE, pldat);
610 ptxrxdesc->control = RXDESC_CONTROL_INT | (ENET_MAXF_SIZE - 1);
611 prxstat->statusinfo = 0;
612 prxstat->statushashcrc = 0;
615 /* Setup base addresses in hardware to point to buffers and
618 writel((ENET_TX_DESC - 1),
619 LPC_ENET_TXDESCRIPTORNUMBER(pldat->net_base));
620 writel(__va_to_pa(pldat->tx_desc_v, pldat),
621 LPC_ENET_TXDESCRIPTOR(pldat->net_base));
622 writel(__va_to_pa(pldat->tx_stat_v, pldat),
623 LPC_ENET_TXSTATUS(pldat->net_base));
624 writel((ENET_RX_DESC - 1),
625 LPC_ENET_RXDESCRIPTORNUMBER(pldat->net_base));
626 writel(__va_to_pa(pldat->rx_desc_v, pldat),
627 LPC_ENET_RXDESCRIPTOR(pldat->net_base));
628 writel(__va_to_pa(pldat->rx_stat_v, pldat),
629 LPC_ENET_RXSTATUS(pldat->net_base));
632 static void __lpc_eth_init(struct netdata_local *pldat)
636 /* Disable controller and reset */
637 tmp = readl(LPC_ENET_COMMAND(pldat->net_base));
638 tmp &= ~LPC_COMMAND_RXENABLE | LPC_COMMAND_TXENABLE;
639 writel(tmp, LPC_ENET_COMMAND(pldat->net_base));
640 tmp = readl(LPC_ENET_MAC1(pldat->net_base));
641 tmp &= ~LPC_MAC1_RECV_ENABLE;
642 writel(tmp, LPC_ENET_MAC1(pldat->net_base));
644 /* Initial MAC setup */
645 writel(LPC_MAC1_PASS_ALL_RX_FRAMES, LPC_ENET_MAC1(pldat->net_base));
646 writel((LPC_MAC2_PAD_CRC_ENABLE | LPC_MAC2_CRC_ENABLE),
647 LPC_ENET_MAC2(pldat->net_base));
648 writel(ENET_MAXF_SIZE, LPC_ENET_MAXF(pldat->net_base));
650 /* Collision window, gap */
651 writel((LPC_CLRT_LOAD_RETRY_MAX(0xF) |
652 LPC_CLRT_LOAD_COLLISION_WINDOW(0x37)),
653 LPC_ENET_CLRT(pldat->net_base));
654 writel(LPC_IPGR_LOAD_PART2(0x12), LPC_ENET_IPGR(pldat->net_base));
656 if (lpc_phy_interface_mode(&pldat->pdev->dev) == PHY_INTERFACE_MODE_MII)
657 writel(LPC_COMMAND_PASSRUNTFRAME,
658 LPC_ENET_COMMAND(pldat->net_base));
660 writel((LPC_COMMAND_PASSRUNTFRAME | LPC_COMMAND_RMII),
661 LPC_ENET_COMMAND(pldat->net_base));
662 writel(LPC_SUPP_RESET_RMII, LPC_ENET_SUPP(pldat->net_base));
665 __lpc_params_setup(pldat);
667 /* Setup TX and RX descriptors */
668 __lpc_txrx_desc_setup(pldat);
670 /* Setup packet filtering */
671 writel((LPC_RXFLTRW_ACCEPTUBROADCAST | LPC_RXFLTRW_ACCEPTPERFECT),
672 LPC_ENET_RXFILTER_CTRL(pldat->net_base));
674 /* Get the next TX buffer output index */
675 pldat->num_used_tx_buffs = 0;
677 readl(LPC_ENET_TXCONSUMEINDEX(pldat->net_base));
679 /* Clear and enable interrupts */
680 writel(0xFFFF, LPC_ENET_INTCLEAR(pldat->net_base));
682 lpc_eth_enable_int(pldat->net_base);
684 /* Enable controller */
685 tmp = readl(LPC_ENET_COMMAND(pldat->net_base));
686 tmp |= LPC_COMMAND_RXENABLE | LPC_COMMAND_TXENABLE;
687 writel(tmp, LPC_ENET_COMMAND(pldat->net_base));
688 tmp = readl(LPC_ENET_MAC1(pldat->net_base));
689 tmp |= LPC_MAC1_RECV_ENABLE;
690 writel(tmp, LPC_ENET_MAC1(pldat->net_base));
693 static void __lpc_eth_shutdown(struct netdata_local *pldat)
695 /* Reset ethernet and power down PHY */
696 __lpc_eth_reset(pldat);
697 writel(0, LPC_ENET_MAC1(pldat->net_base));
698 writel(0, LPC_ENET_MAC2(pldat->net_base));
702 * MAC<--->PHY support functions
704 static int lpc_mdio_read(struct mii_bus *bus, int phy_id, int phyreg)
706 struct netdata_local *pldat = bus->priv;
707 unsigned long timeout = jiffies + msecs_to_jiffies(100);
710 writel(((phy_id << 8) | phyreg), LPC_ENET_MADR(pldat->net_base));
711 writel(LPC_MCMD_READ, LPC_ENET_MCMD(pldat->net_base));
713 /* Wait for unbusy status */
714 while (readl(LPC_ENET_MIND(pldat->net_base)) & LPC_MIND_BUSY) {
715 if (time_after(jiffies, timeout))
720 lps = readl(LPC_ENET_MRDD(pldat->net_base));
721 writel(0, LPC_ENET_MCMD(pldat->net_base));
726 static int lpc_mdio_write(struct mii_bus *bus, int phy_id, int phyreg,
729 struct netdata_local *pldat = bus->priv;
730 unsigned long timeout = jiffies + msecs_to_jiffies(100);
732 writel(((phy_id << 8) | phyreg), LPC_ENET_MADR(pldat->net_base));
733 writel(phydata, LPC_ENET_MWTD(pldat->net_base));
735 /* Wait for completion */
736 while (readl(LPC_ENET_MIND(pldat->net_base)) & LPC_MIND_BUSY) {
737 if (time_after(jiffies, timeout))
745 static int lpc_mdio_reset(struct mii_bus *bus)
747 return __lpc_mii_mngt_reset((struct netdata_local *)bus->priv);
750 static void lpc_handle_link_change(struct net_device *ndev)
752 struct netdata_local *pldat = netdev_priv(ndev);
753 struct phy_device *phydev = pldat->phy_dev;
756 bool status_change = false;
758 spin_lock_irqsave(&pldat->lock, flags);
761 if ((pldat->speed != phydev->speed) ||
762 (pldat->duplex != phydev->duplex)) {
763 pldat->speed = phydev->speed;
764 pldat->duplex = phydev->duplex;
765 status_change = true;
769 if (phydev->link != pldat->link) {
774 pldat->link = phydev->link;
776 status_change = true;
779 spin_unlock_irqrestore(&pldat->lock, flags);
782 __lpc_params_setup(pldat);
785 static int lpc_mii_probe(struct net_device *ndev)
787 struct netdata_local *pldat = netdev_priv(ndev);
788 struct phy_device *phydev = phy_find_first(pldat->mii_bus);
791 netdev_err(ndev, "no PHY found\n");
795 /* Attach to the PHY */
796 if (lpc_phy_interface_mode(&pldat->pdev->dev) == PHY_INTERFACE_MODE_MII)
797 netdev_info(ndev, "using MII interface\n");
799 netdev_info(ndev, "using RMII interface\n");
800 phydev = phy_connect(ndev, dev_name(&phydev->dev),
801 &lpc_handle_link_change,
802 lpc_phy_interface_mode(&pldat->pdev->dev));
804 if (IS_ERR(phydev)) {
805 netdev_err(ndev, "Could not attach to PHY\n");
806 return PTR_ERR(phydev);
809 /* mask with MAC supported features */
810 phydev->supported &= PHY_BASIC_FEATURES;
812 phydev->advertising = phydev->supported;
817 pldat->phy_dev = phydev;
820 "attached PHY driver [%s] (mii_bus:phy_addr=%s, irq=%d)\n",
821 phydev->drv->name, dev_name(&phydev->dev), phydev->irq);
825 static int lpc_mii_init(struct netdata_local *pldat)
829 pldat->mii_bus = mdiobus_alloc();
830 if (!pldat->mii_bus) {
836 if (lpc_phy_interface_mode(&pldat->pdev->dev) == PHY_INTERFACE_MODE_MII)
837 writel(LPC_COMMAND_PASSRUNTFRAME,
838 LPC_ENET_COMMAND(pldat->net_base));
840 writel((LPC_COMMAND_PASSRUNTFRAME | LPC_COMMAND_RMII),
841 LPC_ENET_COMMAND(pldat->net_base));
842 writel(LPC_SUPP_RESET_RMII, LPC_ENET_SUPP(pldat->net_base));
845 pldat->mii_bus->name = "lpc_mii_bus";
846 pldat->mii_bus->read = &lpc_mdio_read;
847 pldat->mii_bus->write = &lpc_mdio_write;
848 pldat->mii_bus->reset = &lpc_mdio_reset;
849 snprintf(pldat->mii_bus->id, MII_BUS_ID_SIZE, "%s-%x",
850 pldat->pdev->name, pldat->pdev->id);
851 pldat->mii_bus->priv = pldat;
852 pldat->mii_bus->parent = &pldat->pdev->dev;
854 pldat->mii_bus->irq = kmalloc(sizeof(int) * PHY_MAX_ADDR, GFP_KERNEL);
855 if (!pldat->mii_bus->irq) {
860 for (i = 0; i < PHY_MAX_ADDR; i++)
861 pldat->mii_bus->irq[i] = PHY_POLL;
863 platform_set_drvdata(pldat->pdev, pldat->mii_bus);
865 if (mdiobus_register(pldat->mii_bus))
866 goto err_out_free_mdio_irq;
868 if (lpc_mii_probe(pldat->ndev) != 0)
869 goto err_out_unregister_bus;
873 err_out_unregister_bus:
874 mdiobus_unregister(pldat->mii_bus);
875 err_out_free_mdio_irq:
876 kfree(pldat->mii_bus->irq);
878 mdiobus_free(pldat->mii_bus);
883 static void __lpc_handle_xmit(struct net_device *ndev)
885 struct netdata_local *pldat = netdev_priv(ndev);
886 u32 txcidx, *ptxstat, txstat;
888 txcidx = readl(LPC_ENET_TXCONSUMEINDEX(pldat->net_base));
889 while (pldat->last_tx_idx != txcidx) {
890 unsigned int skblen = pldat->skblen[pldat->last_tx_idx];
892 /* A buffer is available, get buffer status */
893 ptxstat = &pldat->tx_stat_v[pldat->last_tx_idx];
896 /* Next buffer and decrement used buffer counter */
897 pldat->num_used_tx_buffs--;
898 pldat->last_tx_idx++;
899 if (pldat->last_tx_idx >= ENET_TX_DESC)
900 pldat->last_tx_idx = 0;
902 /* Update collision counter */
903 ndev->stats.collisions += TXSTATUS_COLLISIONS_GET(txstat);
905 /* Any errors occurred? */
906 if (txstat & TXSTATUS_ERROR) {
907 if (txstat & TXSTATUS_UNDERRUN) {
909 ndev->stats.tx_fifo_errors++;
911 if (txstat & TXSTATUS_LATECOLL) {
913 ndev->stats.tx_aborted_errors++;
915 if (txstat & TXSTATUS_EXCESSCOLL) {
916 /* Excessive collision */
917 ndev->stats.tx_aborted_errors++;
919 if (txstat & TXSTATUS_EXCESSDEFER) {
921 ndev->stats.tx_aborted_errors++;
923 ndev->stats.tx_errors++;
926 ndev->stats.tx_packets++;
927 ndev->stats.tx_bytes += skblen;
930 txcidx = readl(LPC_ENET_TXCONSUMEINDEX(pldat->net_base));
933 if (pldat->num_used_tx_buffs <= ENET_TX_DESC/2) {
934 if (netif_queue_stopped(ndev))
935 netif_wake_queue(ndev);
939 static int __lpc_handle_recv(struct net_device *ndev, int budget)
941 struct netdata_local *pldat = netdev_priv(ndev);
943 u32 rxconsidx, len, ethst;
944 struct rx_status_t *prxstat;
948 /* Get the current RX buffer indexes */
949 rxconsidx = readl(LPC_ENET_RXCONSUMEINDEX(pldat->net_base));
950 while (rx_done < budget && rxconsidx !=
951 readl(LPC_ENET_RXPRODUCEINDEX(pldat->net_base))) {
952 /* Get pointer to receive status */
953 prxstat = &pldat->rx_stat_v[rxconsidx];
954 len = (prxstat->statusinfo & RXSTATUS_SIZE) + 1;
957 ethst = prxstat->statusinfo;
958 if ((ethst & (RXSTATUS_ERROR | RXSTATUS_STATUS_ERROR)) ==
959 (RXSTATUS_ERROR | RXSTATUS_RANGE))
960 ethst &= ~RXSTATUS_ERROR;
962 if (ethst & RXSTATUS_ERROR) {
963 int si = prxstat->statusinfo;
965 if (si & RXSTATUS_OVERRUN) {
967 ndev->stats.rx_fifo_errors++;
968 } else if (si & RXSTATUS_CRC) {
970 ndev->stats.rx_crc_errors++;
971 } else if (si & RXSTATUS_LENGTH) {
973 ndev->stats.rx_length_errors++;
974 } else if (si & RXSTATUS_ERROR) {
976 ndev->stats.rx_length_errors++;
978 ndev->stats.rx_errors++;
981 skb = dev_alloc_skb(len);
983 ndev->stats.rx_dropped++;
985 prdbuf = skb_put(skb, len);
987 /* Copy packet from buffer */
988 memcpy(prdbuf, pldat->rx_buff_v +
989 rxconsidx * ENET_MAXF_SIZE, len);
991 /* Pass to upper layer */
992 skb->protocol = eth_type_trans(skb, ndev);
993 netif_receive_skb(skb);
994 ndev->stats.rx_packets++;
995 ndev->stats.rx_bytes += len;
999 /* Increment consume index */
1000 rxconsidx = rxconsidx + 1;
1001 if (rxconsidx >= ENET_RX_DESC)
1004 LPC_ENET_RXCONSUMEINDEX(pldat->net_base));
1011 static int lpc_eth_poll(struct napi_struct *napi, int budget)
1013 struct netdata_local *pldat = container_of(napi,
1014 struct netdata_local, napi);
1015 struct net_device *ndev = pldat->ndev;
1017 struct netdev_queue *txq = netdev_get_tx_queue(ndev, 0);
1019 __netif_tx_lock(txq, smp_processor_id());
1020 __lpc_handle_xmit(ndev);
1021 __netif_tx_unlock(txq);
1022 rx_done = __lpc_handle_recv(ndev, budget);
1024 if (rx_done < budget) {
1025 napi_complete(napi);
1026 lpc_eth_enable_int(pldat->net_base);
1032 static irqreturn_t __lpc_eth_interrupt(int irq, void *dev_id)
1034 struct net_device *ndev = dev_id;
1035 struct netdata_local *pldat = netdev_priv(ndev);
1038 spin_lock(&pldat->lock);
1040 tmp = readl(LPC_ENET_INTSTATUS(pldat->net_base));
1041 /* Clear interrupts */
1042 writel(tmp, LPC_ENET_INTCLEAR(pldat->net_base));
1044 lpc_eth_disable_int(pldat->net_base);
1045 if (likely(napi_schedule_prep(&pldat->napi)))
1046 __napi_schedule(&pldat->napi);
1048 spin_unlock(&pldat->lock);
1053 static int lpc_eth_close(struct net_device *ndev)
1055 unsigned long flags;
1056 struct netdata_local *pldat = netdev_priv(ndev);
1058 if (netif_msg_ifdown(pldat))
1059 dev_dbg(&pldat->pdev->dev, "shutting down %s\n", ndev->name);
1061 napi_disable(&pldat->napi);
1062 netif_stop_queue(ndev);
1065 phy_stop(pldat->phy_dev);
1067 spin_lock_irqsave(&pldat->lock, flags);
1068 __lpc_eth_reset(pldat);
1069 netif_carrier_off(ndev);
1070 writel(0, LPC_ENET_MAC1(pldat->net_base));
1071 writel(0, LPC_ENET_MAC2(pldat->net_base));
1072 spin_unlock_irqrestore(&pldat->lock, flags);
1074 __lpc_eth_clock_enable(pldat, false);
1079 static int lpc_eth_hard_start_xmit(struct sk_buff *skb, struct net_device *ndev)
1081 struct netdata_local *pldat = netdev_priv(ndev);
1084 struct txrx_desc_t *ptxrxdesc;
1088 spin_lock_irq(&pldat->lock);
1090 if (pldat->num_used_tx_buffs >= (ENET_TX_DESC - 1)) {
1091 /* This function should never be called when there are no
1093 netif_stop_queue(ndev);
1094 spin_unlock_irq(&pldat->lock);
1095 WARN(1, "BUG! TX request when no free TX buffers!\n");
1096 return NETDEV_TX_BUSY;
1099 /* Get the next TX descriptor index */
1100 txidx = readl(LPC_ENET_TXPRODUCEINDEX(pldat->net_base));
1102 /* Setup control for the transfer */
1103 ptxstat = &pldat->tx_stat_v[txidx];
1105 ptxrxdesc = &pldat->tx_desc_v[txidx];
1106 ptxrxdesc->control =
1107 (len - 1) | TXDESC_CONTROL_LAST | TXDESC_CONTROL_INT;
1109 /* Copy data to the DMA buffer */
1110 memcpy(pldat->tx_buff_v + txidx * ENET_MAXF_SIZE, skb->data, len);
1112 /* Save the buffer and increment the buffer counter */
1113 pldat->skblen[txidx] = len;
1114 pldat->num_used_tx_buffs++;
1116 /* Start transmit */
1118 if (txidx >= ENET_TX_DESC)
1120 writel(txidx, LPC_ENET_TXPRODUCEINDEX(pldat->net_base));
1122 /* Stop queue if no more TX buffers */
1123 if (pldat->num_used_tx_buffs >= (ENET_TX_DESC - 1))
1124 netif_stop_queue(ndev);
1126 spin_unlock_irq(&pldat->lock);
1129 return NETDEV_TX_OK;
1132 static int lpc_set_mac_address(struct net_device *ndev, void *p)
1134 struct sockaddr *addr = p;
1135 struct netdata_local *pldat = netdev_priv(ndev);
1136 unsigned long flags;
1138 if (!is_valid_ether_addr(addr->sa_data))
1139 return -EADDRNOTAVAIL;
1140 memcpy(ndev->dev_addr, addr->sa_data, ETH_ALEN);
1142 spin_lock_irqsave(&pldat->lock, flags);
1144 /* Set station address */
1145 __lpc_set_mac(pldat, ndev->dev_addr);
1147 spin_unlock_irqrestore(&pldat->lock, flags);
1152 static void lpc_eth_set_multicast_list(struct net_device *ndev)
1154 struct netdata_local *pldat = netdev_priv(ndev);
1155 struct netdev_hw_addr_list *mcptr = &ndev->mc;
1156 struct netdev_hw_addr *ha;
1157 u32 tmp32, hash_val, hashlo, hashhi;
1158 unsigned long flags;
1160 spin_lock_irqsave(&pldat->lock, flags);
1162 /* Set station address */
1163 __lpc_set_mac(pldat, ndev->dev_addr);
1165 tmp32 = LPC_RXFLTRW_ACCEPTUBROADCAST | LPC_RXFLTRW_ACCEPTPERFECT;
1167 if (ndev->flags & IFF_PROMISC)
1168 tmp32 |= LPC_RXFLTRW_ACCEPTUNICAST |
1169 LPC_RXFLTRW_ACCEPTUMULTICAST;
1170 if (ndev->flags & IFF_ALLMULTI)
1171 tmp32 |= LPC_RXFLTRW_ACCEPTUMULTICAST;
1173 if (netdev_hw_addr_list_count(mcptr))
1174 tmp32 |= LPC_RXFLTRW_ACCEPTUMULTICASTHASH;
1176 writel(tmp32, LPC_ENET_RXFILTER_CTRL(pldat->net_base));
1179 /* Set initial hash table */
1183 /* 64 bits : multicast address in hash table */
1184 netdev_hw_addr_list_for_each(ha, mcptr) {
1185 hash_val = (ether_crc(6, ha->addr) >> 23) & 0x3F;
1188 hashhi |= 1 << (hash_val - 32);
1190 hashlo |= 1 << hash_val;
1193 writel(hashlo, LPC_ENET_HASHFILTERL(pldat->net_base));
1194 writel(hashhi, LPC_ENET_HASHFILTERH(pldat->net_base));
1196 spin_unlock_irqrestore(&pldat->lock, flags);
1199 static int lpc_eth_ioctl(struct net_device *ndev, struct ifreq *req, int cmd)
1201 struct netdata_local *pldat = netdev_priv(ndev);
1202 struct phy_device *phydev = pldat->phy_dev;
1204 if (!netif_running(ndev))
1210 return phy_mii_ioctl(phydev, req, cmd);
1213 static int lpc_eth_open(struct net_device *ndev)
1215 struct netdata_local *pldat = netdev_priv(ndev);
1217 if (netif_msg_ifup(pldat))
1218 dev_dbg(&pldat->pdev->dev, "enabling %s\n", ndev->name);
1220 __lpc_eth_clock_enable(pldat, true);
1222 /* Suspended PHY makes LPC ethernet core block, so resume now */
1223 phy_resume(pldat->phy_dev);
1225 /* Reset and initialize */
1226 __lpc_eth_reset(pldat);
1227 __lpc_eth_init(pldat);
1229 /* schedule a link state check */
1230 phy_start(pldat->phy_dev);
1231 netif_start_queue(ndev);
1232 napi_enable(&pldat->napi);
1240 static void lpc_eth_ethtool_getdrvinfo(struct net_device *ndev,
1241 struct ethtool_drvinfo *info)
1243 strlcpy(info->driver, MODNAME, sizeof(info->driver));
1244 strlcpy(info->version, DRV_VERSION, sizeof(info->version));
1245 strlcpy(info->bus_info, dev_name(ndev->dev.parent),
1246 sizeof(info->bus_info));
1249 static u32 lpc_eth_ethtool_getmsglevel(struct net_device *ndev)
1251 struct netdata_local *pldat = netdev_priv(ndev);
1253 return pldat->msg_enable;
1256 static void lpc_eth_ethtool_setmsglevel(struct net_device *ndev, u32 level)
1258 struct netdata_local *pldat = netdev_priv(ndev);
1260 pldat->msg_enable = level;
1263 static int lpc_eth_ethtool_getsettings(struct net_device *ndev,
1264 struct ethtool_cmd *cmd)
1266 struct netdata_local *pldat = netdev_priv(ndev);
1267 struct phy_device *phydev = pldat->phy_dev;
1272 return phy_ethtool_gset(phydev, cmd);
1275 static int lpc_eth_ethtool_setsettings(struct net_device *ndev,
1276 struct ethtool_cmd *cmd)
1278 struct netdata_local *pldat = netdev_priv(ndev);
1279 struct phy_device *phydev = pldat->phy_dev;
1284 return phy_ethtool_sset(phydev, cmd);
1287 static const struct ethtool_ops lpc_eth_ethtool_ops = {
1288 .get_drvinfo = lpc_eth_ethtool_getdrvinfo,
1289 .get_settings = lpc_eth_ethtool_getsettings,
1290 .set_settings = lpc_eth_ethtool_setsettings,
1291 .get_msglevel = lpc_eth_ethtool_getmsglevel,
1292 .set_msglevel = lpc_eth_ethtool_setmsglevel,
1293 .get_link = ethtool_op_get_link,
1296 static const struct net_device_ops lpc_netdev_ops = {
1297 .ndo_open = lpc_eth_open,
1298 .ndo_stop = lpc_eth_close,
1299 .ndo_start_xmit = lpc_eth_hard_start_xmit,
1300 .ndo_set_rx_mode = lpc_eth_set_multicast_list,
1301 .ndo_do_ioctl = lpc_eth_ioctl,
1302 .ndo_set_mac_address = lpc_set_mac_address,
1303 .ndo_validate_addr = eth_validate_addr,
1304 .ndo_change_mtu = eth_change_mtu,
1307 static int lpc_eth_drv_probe(struct platform_device *pdev)
1309 struct resource *res;
1310 struct net_device *ndev;
1311 struct netdata_local *pldat;
1312 struct phy_device *phydev;
1313 dma_addr_t dma_handle;
1317 /* Setup network interface for RMII or MII mode */
1318 tmp = __raw_readl(LPC32XX_CLKPWR_MACCLK_CTRL);
1319 tmp &= ~LPC32XX_CLKPWR_MACCTRL_PINS_MSK;
1320 if (lpc_phy_interface_mode(&pdev->dev) == PHY_INTERFACE_MODE_MII)
1321 tmp |= LPC32XX_CLKPWR_MACCTRL_USE_MII_PINS;
1323 tmp |= LPC32XX_CLKPWR_MACCTRL_USE_RMII_PINS;
1324 __raw_writel(tmp, LPC32XX_CLKPWR_MACCLK_CTRL);
1326 /* Get platform resources */
1327 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1328 irq = platform_get_irq(pdev, 0);
1329 if ((!res) || (irq < 0) || (irq >= NR_IRQS)) {
1330 dev_err(&pdev->dev, "error getting resources.\n");
1335 /* Allocate net driver data structure */
1336 ndev = alloc_etherdev(sizeof(struct netdata_local));
1338 dev_err(&pdev->dev, "could not allocate device.\n");
1343 SET_NETDEV_DEV(ndev, &pdev->dev);
1345 pldat = netdev_priv(ndev);
1349 spin_lock_init(&pldat->lock);
1351 /* Save resources */
1354 /* Get clock for the device */
1355 pldat->clk = clk_get(&pdev->dev, NULL);
1356 if (IS_ERR(pldat->clk)) {
1357 dev_err(&pdev->dev, "error getting clock.\n");
1358 ret = PTR_ERR(pldat->clk);
1359 goto err_out_free_dev;
1362 /* Enable network clock */
1363 __lpc_eth_clock_enable(pldat, true);
1366 pldat->net_base = ioremap(res->start, resource_size(res));
1367 if (!pldat->net_base) {
1368 dev_err(&pdev->dev, "failed to map registers\n");
1370 goto err_out_disable_clocks;
1372 ret = request_irq(ndev->irq, __lpc_eth_interrupt, 0,
1375 dev_err(&pdev->dev, "error requesting interrupt.\n");
1376 goto err_out_iounmap;
1379 /* Setup driver functions */
1380 ndev->netdev_ops = &lpc_netdev_ops;
1381 ndev->ethtool_ops = &lpc_eth_ethtool_ops;
1382 ndev->watchdog_timeo = msecs_to_jiffies(2500);
1384 /* Get size of DMA buffers/descriptors region */
1385 pldat->dma_buff_size = (ENET_TX_DESC + ENET_RX_DESC) * (ENET_MAXF_SIZE +
1386 sizeof(struct txrx_desc_t) + sizeof(struct rx_status_t));
1387 pldat->dma_buff_base_v = 0;
1389 if (use_iram_for_net(&pldat->pdev->dev)) {
1390 dma_handle = LPC32XX_IRAM_BASE;
1391 if (pldat->dma_buff_size <= lpc32xx_return_iram_size())
1392 pldat->dma_buff_base_v =
1393 io_p2v(LPC32XX_IRAM_BASE);
1396 "IRAM not big enough for net buffers, using SDRAM instead.\n");
1399 if (pldat->dma_buff_base_v == 0) {
1400 ret = dma_coerce_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(32));
1402 goto err_out_free_irq;
1404 pldat->dma_buff_size = PAGE_ALIGN(pldat->dma_buff_size);
1406 /* Allocate a chunk of memory for the DMA ethernet buffers
1408 pldat->dma_buff_base_v =
1409 dma_alloc_coherent(&pldat->pdev->dev,
1410 pldat->dma_buff_size, &dma_handle,
1412 if (pldat->dma_buff_base_v == NULL) {
1414 goto err_out_free_irq;
1417 pldat->dma_buff_base_p = dma_handle;
1419 netdev_dbg(ndev, "IO address space :%pR\n", res);
1420 netdev_dbg(ndev, "IO address size :%d\n", resource_size(res));
1421 netdev_dbg(ndev, "IO address (mapped) :0x%p\n",
1423 netdev_dbg(ndev, "IRQ number :%d\n", ndev->irq);
1424 netdev_dbg(ndev, "DMA buffer size :%d\n", pldat->dma_buff_size);
1425 netdev_dbg(ndev, "DMA buffer P address :0x%08x\n",
1426 pldat->dma_buff_base_p);
1427 netdev_dbg(ndev, "DMA buffer V address :0x%p\n",
1428 pldat->dma_buff_base_v);
1430 /* Get MAC address from current HW setting (POR state is all zeros) */
1431 __lpc_get_mac(pldat, ndev->dev_addr);
1433 if (!is_valid_ether_addr(ndev->dev_addr)) {
1434 const char *macaddr = of_get_mac_address(pdev->dev.of_node);
1436 memcpy(ndev->dev_addr, macaddr, ETH_ALEN);
1438 if (!is_valid_ether_addr(ndev->dev_addr))
1439 eth_hw_addr_random(ndev);
1441 /* Reset the ethernet controller */
1442 __lpc_eth_reset(pldat);
1444 /* then shut everything down to save power */
1445 __lpc_eth_shutdown(pldat);
1447 /* Set default parameters */
1448 pldat->msg_enable = NETIF_MSG_LINK;
1450 /* Force an MII interface reset and clock setup */
1451 __lpc_mii_mngt_reset(pldat);
1453 /* Force default PHY interface setup in chip, this will probably be
1454 changed by the PHY driver */
1457 pldat->duplex = DUPLEX_FULL;
1458 __lpc_params_setup(pldat);
1460 netif_napi_add(ndev, &pldat->napi, lpc_eth_poll, NAPI_WEIGHT);
1462 ret = register_netdev(ndev);
1464 dev_err(&pdev->dev, "Cannot register net device, aborting.\n");
1465 goto err_out_dma_unmap;
1467 platform_set_drvdata(pdev, ndev);
1469 ret = lpc_mii_init(pldat);
1471 goto err_out_unregister_netdev;
1473 netdev_info(ndev, "LPC mac at 0x%08x irq %d\n",
1474 res->start, ndev->irq);
1476 phydev = pldat->phy_dev;
1478 device_init_wakeup(&pdev->dev, 1);
1479 device_set_wakeup_enable(&pdev->dev, 0);
1483 err_out_unregister_netdev:
1484 unregister_netdev(ndev);
1486 if (!use_iram_for_net(&pldat->pdev->dev) ||
1487 pldat->dma_buff_size > lpc32xx_return_iram_size())
1488 dma_free_coherent(&pldat->pdev->dev, pldat->dma_buff_size,
1489 pldat->dma_buff_base_v,
1490 pldat->dma_buff_base_p);
1492 free_irq(ndev->irq, ndev);
1494 iounmap(pldat->net_base);
1495 err_out_disable_clocks:
1496 clk_disable_unprepare(pldat->clk);
1497 clk_put(pldat->clk);
1501 pr_err("%s: not found (%d).\n", MODNAME, ret);
1505 static int lpc_eth_drv_remove(struct platform_device *pdev)
1507 struct net_device *ndev = platform_get_drvdata(pdev);
1508 struct netdata_local *pldat = netdev_priv(ndev);
1510 unregister_netdev(ndev);
1512 if (!use_iram_for_net(&pldat->pdev->dev) ||
1513 pldat->dma_buff_size > lpc32xx_return_iram_size())
1514 dma_free_coherent(&pldat->pdev->dev, pldat->dma_buff_size,
1515 pldat->dma_buff_base_v,
1516 pldat->dma_buff_base_p);
1517 free_irq(ndev->irq, ndev);
1518 iounmap(pldat->net_base);
1519 mdiobus_unregister(pldat->mii_bus);
1520 mdiobus_free(pldat->mii_bus);
1521 clk_disable_unprepare(pldat->clk);
1522 clk_put(pldat->clk);
1529 static int lpc_eth_drv_suspend(struct platform_device *pdev,
1532 struct net_device *ndev = platform_get_drvdata(pdev);
1533 struct netdata_local *pldat = netdev_priv(ndev);
1535 if (device_may_wakeup(&pdev->dev))
1536 enable_irq_wake(ndev->irq);
1539 if (netif_running(ndev)) {
1540 netif_device_detach(ndev);
1541 __lpc_eth_shutdown(pldat);
1542 clk_disable_unprepare(pldat->clk);
1545 * Reset again now clock is disable to be sure
1548 __lpc_eth_reset(pldat);
1555 static int lpc_eth_drv_resume(struct platform_device *pdev)
1557 struct net_device *ndev = platform_get_drvdata(pdev);
1558 struct netdata_local *pldat;
1560 if (device_may_wakeup(&pdev->dev))
1561 disable_irq_wake(ndev->irq);
1564 if (netif_running(ndev)) {
1565 pldat = netdev_priv(ndev);
1567 /* Enable interface clock */
1568 clk_enable(pldat->clk);
1570 /* Reset and initialize */
1571 __lpc_eth_reset(pldat);
1572 __lpc_eth_init(pldat);
1574 netif_device_attach(ndev);
1583 static const struct of_device_id lpc_eth_match[] = {
1584 { .compatible = "nxp,lpc-eth" },
1587 MODULE_DEVICE_TABLE(of, lpc_eth_match);
1590 static struct platform_driver lpc_eth_driver = {
1591 .probe = lpc_eth_drv_probe,
1592 .remove = lpc_eth_drv_remove,
1594 .suspend = lpc_eth_drv_suspend,
1595 .resume = lpc_eth_drv_resume,
1599 .of_match_table = of_match_ptr(lpc_eth_match),
1603 module_platform_driver(lpc_eth_driver);
1605 MODULE_AUTHOR("Kevin Wells <kevin.wells@nxp.com>");
1606 MODULE_AUTHOR("Roland Stigge <stigge@antcom.de>");
1607 MODULE_DESCRIPTION("LPC Ethernet Driver");
1608 MODULE_LICENSE("GPL");